1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybc 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Re< 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660. 8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h 9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h> <<
12 #include <dt-bindings/interconnect/qcom,sdm660 11 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/soc/qcom,apr.h> 15 #include <dt-bindings/soc/qcom,apr.h>
18 16
19 / { 17 / {
20 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
21 19
22 #address-cells = <2>; 20 #address-cells = <2>;
23 #size-cells = <2>; 21 #size-cells = <2>;
24 22
25 aliases { 23 aliases {
26 mmc1 = &sdhc_1; 24 mmc1 = &sdhc_1;
27 mmc2 = &sdhc_2; 25 mmc2 = &sdhc_2;
28 }; 26 };
29 27
30 chosen { }; 28 chosen { };
31 29
32 clocks { 30 clocks {
33 xo_board: xo-board { 31 xo_board: xo-board {
34 compatible = "fixed-cl 32 compatible = "fixed-clock";
35 #clock-cells = <0>; 33 #clock-cells = <0>;
36 clock-frequency = <192 34 clock-frequency = <19200000>;
37 clock-output-names = " 35 clock-output-names = "xo_board";
38 }; 36 };
39 37
40 sleep_clk: sleep-clk { 38 sleep_clk: sleep-clk {
41 compatible = "fixed-cl 39 compatible = "fixed-clock";
42 #clock-cells = <0>; 40 #clock-cells = <0>;
43 clock-frequency = <327 41 clock-frequency = <32764>;
44 clock-output-names = " 42 clock-output-names = "sleep_clk";
45 }; 43 };
46 }; 44 };
47 45
48 cpus { 46 cpus {
49 #address-cells = <2>; 47 #address-cells = <2>;
50 #size-cells = <0>; 48 #size-cells = <0>;
51 49
52 CPU0: cpu@100 { 50 CPU0: cpu@100 {
53 device_type = "cpu"; 51 device_type = "cpu";
54 compatible = "arm,cort 52 compatible = "arm,cortex-a53";
55 reg = <0x0 0x100>; 53 reg = <0x0 0x100>;
56 enable-method = "psci" 54 enable-method = "psci";
57 cpu-idle-states = <&PE 55 cpu-idle-states = <&PERF_CPU_SLEEP_0
58 56 &PERF_CPU_SLEEP_1
59 57 &PERF_CLUSTER_SLEEP_0
60 58 &PERF_CLUSTER_SLEEP_1
61 59 &PERF_CLUSTER_SLEEP_2>;
62 capacity-dmips-mhz = < 60 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>; 61 #cooling-cells = <2>;
64 next-level-cache = <&L 62 next-level-cache = <&L2_1>;
65 L2_1: l2-cache { 63 L2_1: l2-cache {
66 compatible = " 64 compatible = "cache";
67 cache-level = 65 cache-level = <2>;
68 cache-unified; 66 cache-unified;
69 }; 67 };
70 }; 68 };
71 69
72 CPU1: cpu@101 { 70 CPU1: cpu@101 {
73 device_type = "cpu"; 71 device_type = "cpu";
74 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
75 reg = <0x0 0x101>; 73 reg = <0x0 0x101>;
76 enable-method = "psci" 74 enable-method = "psci";
77 cpu-idle-states = <&PE 75 cpu-idle-states = <&PERF_CPU_SLEEP_0
78 76 &PERF_CPU_SLEEP_1
79 77 &PERF_CLUSTER_SLEEP_0
80 78 &PERF_CLUSTER_SLEEP_1
81 79 &PERF_CLUSTER_SLEEP_2>;
82 capacity-dmips-mhz = < 80 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>; 81 #cooling-cells = <2>;
84 next-level-cache = <&L 82 next-level-cache = <&L2_1>;
85 }; 83 };
86 84
87 CPU2: cpu@102 { 85 CPU2: cpu@102 {
88 device_type = "cpu"; 86 device_type = "cpu";
89 compatible = "arm,cort 87 compatible = "arm,cortex-a53";
90 reg = <0x0 0x102>; 88 reg = <0x0 0x102>;
91 enable-method = "psci" 89 enable-method = "psci";
92 cpu-idle-states = <&PE 90 cpu-idle-states = <&PERF_CPU_SLEEP_0
93 91 &PERF_CPU_SLEEP_1
94 92 &PERF_CLUSTER_SLEEP_0
95 93 &PERF_CLUSTER_SLEEP_1
96 94 &PERF_CLUSTER_SLEEP_2>;
97 capacity-dmips-mhz = < 95 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>; 96 #cooling-cells = <2>;
99 next-level-cache = <&L 97 next-level-cache = <&L2_1>;
100 }; 98 };
101 99
102 CPU3: cpu@103 { 100 CPU3: cpu@103 {
103 device_type = "cpu"; 101 device_type = "cpu";
104 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
105 reg = <0x0 0x103>; 103 reg = <0x0 0x103>;
106 enable-method = "psci" 104 enable-method = "psci";
107 cpu-idle-states = <&PE 105 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 106 &PERF_CPU_SLEEP_1
109 107 &PERF_CLUSTER_SLEEP_0
110 108 &PERF_CLUSTER_SLEEP_1
111 109 &PERF_CLUSTER_SLEEP_2>;
112 capacity-dmips-mhz = < 110 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>; 111 #cooling-cells = <2>;
114 next-level-cache = <&L 112 next-level-cache = <&L2_1>;
115 }; 113 };
116 114
117 CPU4: cpu@0 { 115 CPU4: cpu@0 {
118 device_type = "cpu"; 116 device_type = "cpu";
119 compatible = "arm,cort 117 compatible = "arm,cortex-a53";
120 reg = <0x0 0x0>; 118 reg = <0x0 0x0>;
121 enable-method = "psci" 119 enable-method = "psci";
122 cpu-idle-states = <&PW 120 cpu-idle-states = <&PWR_CPU_SLEEP_0
123 121 &PWR_CPU_SLEEP_1
124 122 &PWR_CLUSTER_SLEEP_0
125 123 &PWR_CLUSTER_SLEEP_1
126 124 &PWR_CLUSTER_SLEEP_2>;
127 capacity-dmips-mhz = < 125 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>; 126 #cooling-cells = <2>;
129 next-level-cache = <&L 127 next-level-cache = <&L2_0>;
130 L2_0: l2-cache { 128 L2_0: l2-cache {
131 compatible = " 129 compatible = "cache";
132 cache-level = 130 cache-level = <2>;
133 cache-unified; 131 cache-unified;
134 }; 132 };
135 }; 133 };
136 134
137 CPU5: cpu@1 { 135 CPU5: cpu@1 {
138 device_type = "cpu"; 136 device_type = "cpu";
139 compatible = "arm,cort 137 compatible = "arm,cortex-a53";
140 reg = <0x0 0x1>; 138 reg = <0x0 0x1>;
141 enable-method = "psci" 139 enable-method = "psci";
142 cpu-idle-states = <&PW 140 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 141 &PWR_CPU_SLEEP_1
144 142 &PWR_CLUSTER_SLEEP_0
145 143 &PWR_CLUSTER_SLEEP_1
146 144 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = < 145 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>; 146 #cooling-cells = <2>;
149 next-level-cache = <&L 147 next-level-cache = <&L2_0>;
150 }; 148 };
151 149
152 CPU6: cpu@2 { 150 CPU6: cpu@2 {
153 device_type = "cpu"; 151 device_type = "cpu";
154 compatible = "arm,cort 152 compatible = "arm,cortex-a53";
155 reg = <0x0 0x2>; 153 reg = <0x0 0x2>;
156 enable-method = "psci" 154 enable-method = "psci";
157 cpu-idle-states = <&PW 155 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 156 &PWR_CPU_SLEEP_1
159 157 &PWR_CLUSTER_SLEEP_0
160 158 &PWR_CLUSTER_SLEEP_1
161 159 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>; 161 #cooling-cells = <2>;
164 next-level-cache = <&L 162 next-level-cache = <&L2_0>;
165 }; 163 };
166 164
167 CPU7: cpu@3 { 165 CPU7: cpu@3 {
168 device_type = "cpu"; 166 device_type = "cpu";
169 compatible = "arm,cort 167 compatible = "arm,cortex-a53";
170 reg = <0x0 0x3>; 168 reg = <0x0 0x3>;
171 enable-method = "psci" 169 enable-method = "psci";
172 cpu-idle-states = <&PW 170 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 171 &PWR_CPU_SLEEP_1
174 172 &PWR_CLUSTER_SLEEP_0
175 173 &PWR_CLUSTER_SLEEP_1
176 174 &PWR_CLUSTER_SLEEP_2>;
177 capacity-dmips-mhz = < 175 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>; 176 #cooling-cells = <2>;
179 next-level-cache = <&L 177 next-level-cache = <&L2_0>;
180 }; 178 };
181 179
182 cpu-map { 180 cpu-map {
183 cluster0 { 181 cluster0 {
184 core0 { 182 core0 {
185 cpu = 183 cpu = <&CPU4>;
186 }; 184 };
187 185
188 core1 { 186 core1 {
189 cpu = 187 cpu = <&CPU5>;
190 }; 188 };
191 189
192 core2 { 190 core2 {
193 cpu = 191 cpu = <&CPU6>;
194 }; 192 };
195 193
196 core3 { 194 core3 {
197 cpu = 195 cpu = <&CPU7>;
198 }; 196 };
199 }; 197 };
200 198
201 cluster1 { 199 cluster1 {
202 core0 { 200 core0 {
203 cpu = 201 cpu = <&CPU0>;
204 }; 202 };
205 203
206 core1 { 204 core1 {
207 cpu = 205 cpu = <&CPU1>;
208 }; 206 };
209 207
210 core2 { 208 core2 {
211 cpu = 209 cpu = <&CPU2>;
212 }; 210 };
213 211
214 core3 { 212 core3 {
215 cpu = 213 cpu = <&CPU3>;
216 }; 214 };
217 }; 215 };
218 }; 216 };
219 217
220 idle-states { 218 idle-states {
221 entry-method = "psci"; 219 entry-method = "psci";
222 220
223 PWR_CPU_SLEEP_0: cpu-s 221 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = " 222 compatible = "arm,idle-state";
225 idle-state-nam 223 idle-state-name = "pwr-retention";
226 arm,psci-suspe 224 arm,psci-suspend-param = <0x40000002>;
227 entry-latency- 225 entry-latency-us = <338>;
228 exit-latency-u 226 exit-latency-us = <423>;
229 min-residency- 227 min-residency-us = <200>;
230 }; 228 };
231 229
232 PWR_CPU_SLEEP_1: cpu-s 230 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = " 231 compatible = "arm,idle-state";
234 idle-state-nam 232 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspe 233 arm,psci-suspend-param = <0x40000003>;
236 entry-latency- 234 entry-latency-us = <515>;
237 exit-latency-u 235 exit-latency-us = <1821>;
238 min-residency- 236 min-residency-us = <1000>;
239 local-timer-st 237 local-timer-stop;
240 }; 238 };
241 239
242 PERF_CPU_SLEEP_0: cpu- 240 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = " 241 compatible = "arm,idle-state";
244 idle-state-nam 242 idle-state-name = "perf-retention";
245 arm,psci-suspe 243 arm,psci-suspend-param = <0x40000002>;
246 entry-latency- 244 entry-latency-us = <154>;
247 exit-latency-u 245 exit-latency-us = <87>;
248 min-residency- 246 min-residency-us = <200>;
249 }; 247 };
250 248
251 PERF_CPU_SLEEP_1: cpu- 249 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = " 250 compatible = "arm,idle-state";
253 idle-state-nam 251 idle-state-name = "perf-power-collapse";
254 arm,psci-suspe 252 arm,psci-suspend-param = <0x40000003>;
255 entry-latency- 253 entry-latency-us = <262>;
256 exit-latency-u 254 exit-latency-us = <301>;
257 min-residency- 255 min-residency-us = <1000>;
258 local-timer-st 256 local-timer-stop;
259 }; 257 };
260 258
261 PWR_CLUSTER_SLEEP_0: c 259 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = " 260 compatible = "arm,idle-state";
263 idle-state-nam 261 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspe 262 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency- 263 entry-latency-us = <284>;
266 exit-latency-u 264 exit-latency-us = <384>;
267 min-residency- 265 min-residency-us = <9987>;
268 local-timer-st 266 local-timer-stop;
269 }; 267 };
270 268
271 PWR_CLUSTER_SLEEP_1: c 269 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = " 270 compatible = "arm,idle-state";
273 idle-state-nam 271 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspe 272 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency- 273 entry-latency-us = <338>;
276 exit-latency-u 274 exit-latency-us = <423>;
277 min-residency- 275 min-residency-us = <9987>;
278 local-timer-st 276 local-timer-stop;
279 }; 277 };
280 278
281 PWR_CLUSTER_SLEEP_2: c 279 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = " 280 compatible = "arm,idle-state";
283 idle-state-nam 281 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspe 282 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency- 283 entry-latency-us = <515>;
286 exit-latency-u 284 exit-latency-us = <1821>;
287 min-residency- 285 min-residency-us = <9987>;
288 local-timer-st 286 local-timer-stop;
289 }; 287 };
290 288
291 PERF_CLUSTER_SLEEP_0: 289 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = " 290 compatible = "arm,idle-state";
293 idle-state-nam 291 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspe 292 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency- 293 entry-latency-us = <272>;
296 exit-latency-u 294 exit-latency-us = <329>;
297 min-residency- 295 min-residency-us = <9987>;
298 local-timer-st 296 local-timer-stop;
299 }; 297 };
300 298
301 PERF_CLUSTER_SLEEP_1: 299 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = " 300 compatible = "arm,idle-state";
303 idle-state-nam 301 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspe 302 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency- 303 entry-latency-us = <332>;
306 exit-latency-u 304 exit-latency-us = <368>;
307 min-residency- 305 min-residency-us = <9987>;
308 local-timer-st 306 local-timer-stop;
309 }; 307 };
310 308
311 PERF_CLUSTER_SLEEP_2: 309 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = " 310 compatible = "arm,idle-state";
313 idle-state-nam 311 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspe 312 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency- 313 entry-latency-us = <545>;
316 exit-latency-u 314 exit-latency-us = <1609>;
317 min-residency- 315 min-residency-us = <9987>;
318 local-timer-st 316 local-timer-stop;
319 }; 317 };
320 }; 318 };
321 }; 319 };
322 320
323 firmware { 321 firmware {
324 scm { 322 scm {
325 compatible = "qcom,scm 323 compatible = "qcom,scm-msm8998", "qcom,scm";
326 }; 324 };
327 }; 325 };
328 326
329 memory@80000000 { 327 memory@80000000 {
330 device_type = "memory"; 328 device_type = "memory";
331 /* We expect the bootloader to 329 /* We expect the bootloader to fill in the reg */
332 reg = <0x0 0x80000000 0x0 0x0> 330 reg = <0x0 0x80000000 0x0 0x0>;
333 }; 331 };
334 332
335 dsi_opp_table: opp-table-dsi { 333 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points 334 compatible = "operating-points-v2";
337 335
338 opp-131250000 { 336 opp-131250000 {
339 opp-hz = /bits/ 64 <13 337 opp-hz = /bits/ 64 <131250000>;
340 required-opps = <&rpmp 338 required-opps = <&rpmpd_opp_svs>;
341 }; 339 };
342 340
343 opp-210000000 { 341 opp-210000000 {
344 opp-hz = /bits/ 64 <21 342 opp-hz = /bits/ 64 <210000000>;
345 required-opps = <&rpmp 343 required-opps = <&rpmpd_opp_svs_plus>;
346 }; 344 };
347 345
348 opp-262500000 { 346 opp-262500000 {
349 opp-hz = /bits/ 64 <26 347 opp-hz = /bits/ 64 <262500000>;
350 required-opps = <&rpmp 348 required-opps = <&rpmpd_opp_nom>;
351 }; 349 };
352 }; 350 };
353 351
354 pmu { 352 pmu {
355 compatible = "arm,armv8-pmuv3" 353 compatible = "arm,armv8-pmuv3";
356 interrupts = <GIC_PPI 6 IRQ_TY 354 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
357 }; 355 };
358 356
359 psci { 357 psci {
360 compatible = "arm,psci-1.0"; 358 compatible = "arm,psci-1.0";
361 method = "smc"; 359 method = "smc";
362 }; 360 };
363 361
364 rpm: remoteproc { <<
365 compatible = "qcom,sdm660-rpm- <<
366 <<
367 glink-edge { <<
368 compatible = "qcom,gli <<
369 <<
370 interrupts = <GIC_SPI <<
371 qcom,rpm-msg-ram = <&r <<
372 mboxes = <&apcs_glb 0> <<
373 <<
374 rpm_requests: rpm-requ <<
375 compatible = " <<
376 qcom,glink-cha <<
377 <<
378 rpmcc: clock-c <<
379 compat <<
380 #clock <<
381 }; <<
382 <<
383 rpmpd: power-c <<
384 compat <<
385 #power <<
386 operat <<
387 <<
388 rpmpd_ <<
389 <<
390 <<
391 <<
392 <<
393 <<
394 <<
395 <<
396 <<
397 <<
398 <<
399 <<
400 <<
401 <<
402 <<
403 <<
404 <<
405 <<
406 <<
407 <<
408 <<
409 <<
410 <<
411 <<
412 <<
413 <<
414 <<
415 <<
416 <<
417 <<
418 <<
419 <<
420 <<
421 <<
422 <<
423 <<
424 <<
425 <<
426 }; <<
427 }; <<
428 }; <<
429 }; <<
430 }; <<
431 <<
432 reserved-memory { 362 reserved-memory {
433 #address-cells = <2>; 363 #address-cells = <2>;
434 #size-cells = <2>; 364 #size-cells = <2>;
435 ranges; 365 ranges;
436 366
437 wlan_msa_guard: wlan-msa-guard 367 wlan_msa_guard: wlan-msa-guard@85600000 {
438 reg = <0x0 0x85600000 368 reg = <0x0 0x85600000 0x0 0x100000>;
439 no-map; 369 no-map;
440 }; 370 };
441 371
442 wlan_msa_mem: wlan-msa-mem@857 372 wlan_msa_mem: wlan-msa-mem@85700000 {
443 reg = <0x0 0x85700000 373 reg = <0x0 0x85700000 0x0 0x100000>;
444 no-map; 374 no-map;
445 }; 375 };
446 376
447 qhee_code: qhee-code@85800000 377 qhee_code: qhee-code@85800000 {
448 reg = <0x0 0x85800000 378 reg = <0x0 0x85800000 0x0 0x600000>;
449 no-map; 379 no-map;
450 }; 380 };
451 381
452 rmtfs_mem: memory@85e00000 { 382 rmtfs_mem: memory@85e00000 {
453 compatible = "qcom,rmt 383 compatible = "qcom,rmtfs-mem";
454 reg = <0x0 0x85e00000 384 reg = <0x0 0x85e00000 0x0 0x200000>;
455 no-map; 385 no-map;
456 386
457 qcom,client-id = <1>; 387 qcom,client-id = <1>;
458 qcom,vmid = <QCOM_SCM_ !! 388 qcom,vmid = <15>;
459 }; 389 };
460 390
461 smem_region: smem-mem@86000000 391 smem_region: smem-mem@86000000 {
462 reg = <0 0x86000000 0 392 reg = <0 0x86000000 0 0x200000>;
463 no-map; 393 no-map;
464 }; 394 };
465 395
466 tz_mem: memory@86200000 { 396 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000 397 reg = <0x0 0x86200000 0x0 0x3300000>;
468 no-map; 398 no-map;
469 }; 399 };
470 400
471 mpss_region: mpss@8ac00000 { 401 mpss_region: mpss@8ac00000 {
472 reg = <0x0 0x8ac00000 402 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
473 no-map; 403 no-map;
474 }; 404 };
475 405
476 adsp_region: adsp@92a00000 { 406 adsp_region: adsp@92a00000 {
477 reg = <0x0 0x92a00000 407 reg = <0x0 0x92a00000 0x0 0x1e00000>;
478 no-map; 408 no-map;
479 }; 409 };
480 410
481 mba_region: mba@94800000 { 411 mba_region: mba@94800000 {
482 reg = <0x0 0x94800000 412 reg = <0x0 0x94800000 0x0 0x200000>;
483 no-map; 413 no-map;
484 }; 414 };
485 415
486 buffer_mem: tzbuffer@94a00000 416 buffer_mem: tzbuffer@94a00000 {
487 reg = <0x0 0x94a00000 417 reg = <0x0 0x94a00000 0x0 0x100000>;
488 no-map; 418 no-map;
489 }; 419 };
490 420
491 venus_region: venus@9f800000 { 421 venus_region: venus@9f800000 {
492 reg = <0x0 0x9f800000 422 reg = <0x0 0x9f800000 0x0 0x800000>;
493 no-map; 423 no-map;
494 }; 424 };
495 425
496 adsp_mem: adsp-region@f6000000 426 adsp_mem: adsp-region@f6000000 {
497 reg = <0x0 0xf6000000 427 reg = <0x0 0xf6000000 0x0 0x800000>;
498 no-map; 428 no-map;
499 }; 429 };
500 430
501 qseecom_mem: qseecom-region@f6 431 qseecom_mem: qseecom-region@f6800000 {
502 reg = <0x0 0xf6800000 432 reg = <0x0 0xf6800000 0x0 0x1400000>;
503 no-map; 433 no-map;
504 }; 434 };
505 435
506 zap_shader_region: gpu@fed0000 436 zap_shader_region: gpu@fed00000 {
507 compatible = "shared-d 437 compatible = "shared-dma-pool";
508 reg = <0x0 0xfed00000 438 reg = <0x0 0xfed00000 0x0 0xa00000>;
509 no-map; 439 no-map;
510 }; 440 };
511 }; 441 };
512 442
>> 443 rpm-glink {
>> 444 compatible = "qcom,glink-rpm";
>> 445
>> 446 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
>> 447 qcom,rpm-msg-ram = <&rpm_msg_ram>;
>> 448 mboxes = <&apcs_glb 0>;
>> 449
>> 450 rpm_requests: rpm-requests {
>> 451 compatible = "qcom,rpm-sdm660";
>> 452 qcom,glink-channels = "rpm_requests";
>> 453
>> 454 rpmcc: clock-controller {
>> 455 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
>> 456 #clock-cells = <1>;
>> 457 };
>> 458
>> 459 rpmpd: power-controller {
>> 460 compatible = "qcom,sdm660-rpmpd";
>> 461 #power-domain-cells = <1>;
>> 462 operating-points-v2 = <&rpmpd_opp_table>;
>> 463
>> 464 rpmpd_opp_table: opp-table {
>> 465 compatible = "operating-points-v2";
>> 466
>> 467 rpmpd_opp_ret: opp1 {
>> 468 opp-level = <RPM_SMD_LEVEL_RETENTION>;
>> 469 };
>> 470
>> 471 rpmpd_opp_ret_plus: opp2 {
>> 472 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
>> 473 };
>> 474
>> 475 rpmpd_opp_min_svs: opp3 {
>> 476 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
>> 477 };
>> 478
>> 479 rpmpd_opp_low_svs: opp4 {
>> 480 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
>> 481 };
>> 482
>> 483 rpmpd_opp_svs: opp5 {
>> 484 opp-level = <RPM_SMD_LEVEL_SVS>;
>> 485 };
>> 486
>> 487 rpmpd_opp_svs_plus: opp6 {
>> 488 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
>> 489 };
>> 490
>> 491 rpmpd_opp_nom: opp7 {
>> 492 opp-level = <RPM_SMD_LEVEL_NOM>;
>> 493 };
>> 494
>> 495 rpmpd_opp_nom_plus: opp8 {
>> 496 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
>> 497 };
>> 498
>> 499 rpmpd_opp_turbo: opp9 {
>> 500 opp-level = <RPM_SMD_LEVEL_TURBO>;
>> 501 };
>> 502 };
>> 503 };
>> 504 };
>> 505 };
>> 506
513 smem: smem { 507 smem: smem {
514 compatible = "qcom,smem"; 508 compatible = "qcom,smem";
515 memory-region = <&smem_region> 509 memory-region = <&smem_region>;
516 hwlocks = <&tcsr_mutex 3>; 510 hwlocks = <&tcsr_mutex 3>;
517 }; 511 };
518 512
519 smp2p-adsp { 513 smp2p-adsp {
520 compatible = "qcom,smp2p"; 514 compatible = "qcom,smp2p";
521 qcom,smem = <443>, <429>; 515 qcom,smem = <443>, <429>;
522 interrupts = <GIC_SPI 158 IRQ_ 516 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
523 mboxes = <&apcs_glb 10>; 517 mboxes = <&apcs_glb 10>;
524 qcom,local-pid = <0>; 518 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>; 519 qcom,remote-pid = <2>;
526 520
527 adsp_smp2p_out: master-kernel 521 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "mas 522 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells 523 #qcom,smem-state-cells = <1>;
530 }; 524 };
531 525
532 adsp_smp2p_in: slave-kernel { 526 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "sla 527 qcom,entry-name = "slave-kernel";
534 interrupt-controller; 528 interrupt-controller;
535 #interrupt-cells = <2> 529 #interrupt-cells = <2>;
536 }; 530 };
537 }; 531 };
538 532
539 smp2p-mpss { 533 smp2p-mpss {
540 compatible = "qcom,smp2p"; 534 compatible = "qcom,smp2p";
541 qcom,smem = <435>, <428>; 535 qcom,smem = <435>, <428>;
542 interrupts = <GIC_SPI 451 IRQ_ 536 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
543 mboxes = <&apcs_glb 14>; 537 mboxes = <&apcs_glb 14>;
544 qcom,local-pid = <0>; 538 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>; 539 qcom,remote-pid = <1>;
546 540
547 modem_smp2p_out: master-kernel 541 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "mas 542 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells 543 #qcom,smem-state-cells = <1>;
550 }; 544 };
551 545
552 modem_smp2p_in: slave-kernel { 546 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "sla 547 qcom,entry-name = "slave-kernel";
554 interrupt-controller; 548 interrupt-controller;
555 #interrupt-cells = <2> 549 #interrupt-cells = <2>;
556 }; 550 };
557 }; 551 };
558 552
559 soc@0 { !! 553 soc {
560 #address-cells = <1>; 554 #address-cells = <1>;
561 #size-cells = <1>; 555 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>; 556 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus"; 557 compatible = "simple-bus";
564 558
565 gcc: clock-controller@100000 { 559 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc 560 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>; 561 #clock-cells = <1>;
568 #reset-cells = <1>; 562 #reset-cells = <1>;
569 #power-domain-cells = 563 #power-domain-cells = <1>;
570 reg = <0x00100000 0x94 564 reg = <0x00100000 0x94000>;
571 565
572 clock-names = "xo", "s 566 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>, 567 clocks = <&xo_board>,
574 <&slee 568 <&sleep_clk>;
575 }; 569 };
576 570
577 rpm_msg_ram: sram@778000 { 571 rpm_msg_ram: sram@778000 {
578 compatible = "qcom,rpm 572 compatible = "qcom,rpm-msg-ram";
579 reg = <0x00778000 0x70 573 reg = <0x00778000 0x7000>;
580 }; 574 };
581 575
582 qfprom: qfprom@780000 { 576 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm 577 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
584 reg = <0x00780000 0x62 578 reg = <0x00780000 0x621c>;
585 #address-cells = <1>; 579 #address-cells = <1>;
586 #size-cells = <1>; 580 #size-cells = <1>;
587 581
588 qusb2_hstx_trim: hstx- 582 qusb2_hstx_trim: hstx-trim@240 {
589 reg = <0x243 0 583 reg = <0x243 0x1>;
590 bits = <1 3>; 584 bits = <1 3>;
591 }; 585 };
592 586
593 gpu_speed_bin: gpu-spe 587 gpu_speed_bin: gpu-speed-bin@41a0 {
594 reg = <0x41a2 588 reg = <0x41a2 0x1>;
595 bits = <5 7>; 589 bits = <5 7>;
596 }; 590 };
597 }; 591 };
598 592
599 rng: rng@793000 { 593 rng: rng@793000 {
600 compatible = "qcom,prn 594 compatible = "qcom,prng-ee";
601 reg = <0x00793000 0x10 595 reg = <0x00793000 0x1000>;
602 clocks = <&gcc GCC_PRN 596 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core"; 597 clock-names = "core";
604 }; 598 };
605 599
606 bimc: interconnect@1008000 { 600 bimc: interconnect@1008000 {
607 compatible = "qcom,sdm 601 compatible = "qcom,sdm660-bimc";
608 reg = <0x01008000 0x78 602 reg = <0x01008000 0x78000>;
609 #interconnect-cells = 603 #interconnect-cells = <1>;
>> 604 clock-names = "bus", "bus_a";
>> 605 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 606 <&rpmcc RPM_SMD_BIMC_A_CLK>;
610 }; 607 };
611 608
612 restart@10ac000 { 609 restart@10ac000 {
613 compatible = "qcom,psh 610 compatible = "qcom,pshold";
614 reg = <0x010ac000 0x4> 611 reg = <0x010ac000 0x4>;
615 }; 612 };
616 613
617 cnoc: interconnect@1500000 { 614 cnoc: interconnect@1500000 {
618 compatible = "qcom,sdm 615 compatible = "qcom,sdm660-cnoc";
619 reg = <0x01500000 0x10 616 reg = <0x01500000 0x10000>;
620 #interconnect-cells = 617 #interconnect-cells = <1>;
>> 618 clock-names = "bus", "bus_a";
>> 619 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 620 <&rpmcc RPM_SMD_CNOC_A_CLK>;
621 }; 621 };
622 622
623 snoc: interconnect@1626000 { 623 snoc: interconnect@1626000 {
624 compatible = "qcom,sdm 624 compatible = "qcom,sdm660-snoc";
625 reg = <0x01626000 0x70 625 reg = <0x01626000 0x7090>;
626 #interconnect-cells = 626 #interconnect-cells = <1>;
>> 627 clock-names = "bus", "bus_a";
>> 628 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 629 <&rpmcc RPM_SMD_SNOC_A_CLK>;
627 }; 630 };
628 631
629 anoc2_smmu: iommu@16c0000 { 632 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm 633 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 reg = <0x016c0000 0x40 634 reg = <0x016c0000 0x40000>;
>> 635
>> 636 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 637 assigned-clock-rates = <1000>;
>> 638 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 639 clock-names = "bus";
632 #global-interrupts = < 640 #global-interrupts = <2>;
633 #iommu-cells = <1>; 641 #iommu-cells = <1>;
634 642
635 interrupts = 643 interrupts =
636 <GIC_SPI 229 I 644 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 231 I 645 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
638 646
639 <GIC_SPI 373 I 647 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 374 I 648 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
641 <GIC_SPI 375 I 649 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
642 <GIC_SPI 376 I 650 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
643 <GIC_SPI 377 I 651 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
644 <GIC_SPI 378 I 652 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
645 <GIC_SPI 462 I 653 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 463 I 654 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 464 I 655 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 465 I 656 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 466 I 657 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 467 I 658 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 353 I 659 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 354 I 660 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 355 I 661 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 356 I 662 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 357 I 663 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 358 I 664 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 359 I 665 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 360 I 666 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 442 I 667 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 443 I 668 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 444 I 669 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 447 I 670 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 468 I 671 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 469 I 672 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 472 I 673 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 473 I 674 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 474 I 675 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
668 676
669 status = "disabled"; 677 status = "disabled";
670 }; 678 };
671 679
672 a2noc: interconnect@1704000 { 680 a2noc: interconnect@1704000 {
673 compatible = "qcom,sdm 681 compatible = "qcom,sdm660-a2noc";
674 reg = <0x01704000 0xc1 682 reg = <0x01704000 0xc100>;
675 #interconnect-cells = 683 #interconnect-cells = <1>;
676 clock-names = "ipa", !! 684 clock-names = "bus",
>> 685 "bus_a",
>> 686 "ipa",
677 "ufs_axi 687 "ufs_axi",
678 "aggre2_ 688 "aggre2_ufs_axi",
679 "aggre2_ 689 "aggre2_usb3_axi",
680 "cfg_noc 690 "cfg_noc_usb2_axi";
681 clocks = <&rpmcc RPM_S !! 691 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 692 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 693 <&rpmcc RPM_SMD_IPA_CLK>,
682 <&gcc GCC_UFS 694 <&gcc GCC_UFS_AXI_CLK>,
683 <&gcc GCC_AGG 695 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
684 <&gcc GCC_AGG 696 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
685 <&gcc GCC_CFG 697 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
686 }; 698 };
687 699
688 mnoc: interconnect@1745000 { 700 mnoc: interconnect@1745000 {
689 compatible = "qcom,sdm 701 compatible = "qcom,sdm660-mnoc";
690 reg = <0x01745000 0xa0 702 reg = <0x01745000 0xa010>;
691 #interconnect-cells = 703 #interconnect-cells = <1>;
692 clock-names = "iface"; !! 704 clock-names = "bus", "bus_a", "iface";
693 clocks = <&mmcc AHB_CL !! 705 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
>> 706 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
>> 707 <&mmcc AHB_CLK_SRC>;
694 }; 708 };
695 709
696 tsens: thermal-sensor@10ae000 710 tsens: thermal-sensor@10ae000 {
697 compatible = "qcom,sdm 711 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
698 reg = <0x010ae000 0x10 712 reg = <0x010ae000 0x1000>, /* TM */
699 <0x010ad000 713 <0x010ad000 0x1000>; /* SROT */
700 #qcom,sensors = <12>; 714 #qcom,sensors = <12>;
701 interrupts = <GIC_SPI 715 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_ 716 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "upl 717 interrupt-names = "uplow", "critical";
704 #thermal-sensor-cells 718 #thermal-sensor-cells = <1>;
705 }; 719 };
706 720
707 tcsr_mutex: hwlock@1f40000 { 721 tcsr_mutex: hwlock@1f40000 {
708 compatible = "qcom,tcs 722 compatible = "qcom,tcsr-mutex";
709 reg = <0x01f40000 0x20 723 reg = <0x01f40000 0x20000>;
710 #hwlock-cells = <1>; 724 #hwlock-cells = <1>;
711 }; 725 };
712 726
713 tcsr_regs_1: syscon@1f60000 { 727 tcsr_regs_1: syscon@1f60000 {
714 compatible = "qcom,sdm 728 compatible = "qcom,sdm630-tcsr", "syscon";
715 reg = <0x01f60000 0x20 729 reg = <0x01f60000 0x20000>;
716 }; 730 };
717 731
718 tlmm: pinctrl@3100000 { 732 tlmm: pinctrl@3100000 {
719 compatible = "qcom,sdm 733 compatible = "qcom,sdm630-pinctrl";
720 reg = <0x03100000 0x40 734 reg = <0x03100000 0x400000>,
721 <0x03500000 735 <0x03500000 0x400000>,
722 <0x03900000 736 <0x03900000 0x400000>;
723 reg-names = "south", " 737 reg-names = "south", "center", "north";
724 interrupts = <GIC_SPI 738 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-controller; 739 gpio-controller;
726 gpio-ranges = <&tlmm 0 740 gpio-ranges = <&tlmm 0 0 114>;
727 #gpio-cells = <2>; 741 #gpio-cells = <2>;
728 interrupt-controller; 742 interrupt-controller;
729 #interrupt-cells = <2> 743 #interrupt-cells = <2>;
730 744
731 blsp1_uart1_default: b 745 blsp1_uart1_default: blsp1-uart1-default-state {
732 pins = "gpio0" 746 pins = "gpio0", "gpio1", "gpio2", "gpio3";
733 function = "bl 747 function = "blsp_uart1";
734 drive-strength 748 drive-strength = <2>;
735 bias-disable; 749 bias-disable;
736 }; 750 };
737 751
738 blsp1_uart1_sleep: bls 752 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
739 pins = "gpio0" 753 pins = "gpio0", "gpio1", "gpio2", "gpio3";
740 function = "gp 754 function = "gpio";
741 drive-strength 755 drive-strength = <2>;
742 bias-disable; 756 bias-disable;
743 }; 757 };
744 758
745 blsp1_uart2_default: b 759 blsp1_uart2_default: blsp1-uart2-default-state {
746 pins = "gpio4" 760 pins = "gpio4", "gpio5";
747 function = "bl 761 function = "blsp_uart2";
748 drive-strength 762 drive-strength = <2>;
749 bias-disable; 763 bias-disable;
750 }; 764 };
751 765
752 blsp2_uart1_default: b 766 blsp2_uart1_default: blsp2-uart1-active-state {
753 tx-rts-pins { 767 tx-rts-pins {
754 pins = 768 pins = "gpio16", "gpio19";
755 functi 769 function = "blsp_uart5";
756 drive- 770 drive-strength = <2>;
757 bias-d 771 bias-disable;
758 }; 772 };
759 773
760 rx-pins { 774 rx-pins {
761 /* 775 /*
762 * Avo 776 * Avoid garbage data while BT module
763 * is 777 * is powered off or not driving signal
764 */ 778 */
765 pins = 779 pins = "gpio17";
766 functi 780 function = "blsp_uart5";
767 drive- 781 drive-strength = <2>;
768 bias-p 782 bias-pull-up;
769 }; 783 };
770 784
771 cts-pins { 785 cts-pins {
772 /* Mat 786 /* Match the pull of the BT module */
773 pins = 787 pins = "gpio18";
774 functi 788 function = "blsp_uart5";
775 drive- 789 drive-strength = <2>;
776 bias-p 790 bias-pull-down;
777 }; 791 };
778 }; 792 };
779 793
780 blsp2_uart1_sleep: bls 794 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
781 tx-pins { 795 tx-pins {
782 pins = 796 pins = "gpio16";
783 functi 797 function = "gpio";
784 drive- 798 drive-strength = <2>;
785 bias-p 799 bias-pull-up;
786 }; 800 };
787 801
788 rx-cts-rts-pin 802 rx-cts-rts-pins {
789 pins = 803 pins = "gpio17", "gpio18", "gpio19";
790 functi 804 function = "gpio";
791 drive- 805 drive-strength = <2>;
792 bias-d 806 bias-disable;
793 }; 807 };
794 }; 808 };
795 809
796 i2c1_default: i2c1-def 810 i2c1_default: i2c1-default-state {
797 pins = "gpio2" 811 pins = "gpio2", "gpio3";
798 function = "bl 812 function = "blsp_i2c1";
799 drive-strength 813 drive-strength = <2>;
800 bias-disable; 814 bias-disable;
801 }; 815 };
802 816
803 i2c1_sleep: i2c1-sleep 817 i2c1_sleep: i2c1-sleep-state {
804 pins = "gpio2" 818 pins = "gpio2", "gpio3";
805 function = "bl 819 function = "blsp_i2c1";
806 drive-strength 820 drive-strength = <2>;
807 bias-pull-up; 821 bias-pull-up;
808 }; 822 };
809 823
810 i2c2_default: i2c2-def 824 i2c2_default: i2c2-default-state {
811 pins = "gpio6" 825 pins = "gpio6", "gpio7";
812 function = "bl 826 function = "blsp_i2c2";
813 drive-strength 827 drive-strength = <2>;
814 bias-disable; 828 bias-disable;
815 }; 829 };
816 830
817 i2c2_sleep: i2c2-sleep 831 i2c2_sleep: i2c2-sleep-state {
818 pins = "gpio6" 832 pins = "gpio6", "gpio7";
819 function = "bl 833 function = "blsp_i2c2";
820 drive-strength 834 drive-strength = <2>;
821 bias-pull-up; 835 bias-pull-up;
822 }; 836 };
823 837
824 i2c3_default: i2c3-def 838 i2c3_default: i2c3-default-state {
825 pins = "gpio10 839 pins = "gpio10", "gpio11";
826 function = "bl 840 function = "blsp_i2c3";
827 drive-strength 841 drive-strength = <2>;
828 bias-disable; 842 bias-disable;
829 }; 843 };
830 844
831 i2c3_sleep: i2c3-sleep 845 i2c3_sleep: i2c3-sleep-state {
832 pins = "gpio10 846 pins = "gpio10", "gpio11";
833 function = "bl 847 function = "blsp_i2c3";
834 drive-strength 848 drive-strength = <2>;
835 bias-pull-up; 849 bias-pull-up;
836 }; 850 };
837 851
838 i2c4_default: i2c4-def 852 i2c4_default: i2c4-default-state {
839 pins = "gpio14 853 pins = "gpio14", "gpio15";
840 function = "bl 854 function = "blsp_i2c4";
841 drive-strength 855 drive-strength = <2>;
842 bias-disable; 856 bias-disable;
843 }; 857 };
844 858
845 i2c4_sleep: i2c4-sleep 859 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio14 860 pins = "gpio14", "gpio15";
847 function = "bl 861 function = "blsp_i2c4";
848 drive-strength 862 drive-strength = <2>;
849 bias-pull-up; 863 bias-pull-up;
850 }; 864 };
851 865
852 i2c5_default: i2c5-def 866 i2c5_default: i2c5-default-state {
853 pins = "gpio18 867 pins = "gpio18", "gpio19";
854 function = "bl 868 function = "blsp_i2c5";
855 drive-strength 869 drive-strength = <2>;
856 bias-disable; 870 bias-disable;
857 }; 871 };
858 872
859 i2c5_sleep: i2c5-sleep 873 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio18 874 pins = "gpio18", "gpio19";
861 function = "bl 875 function = "blsp_i2c5";
862 drive-strength 876 drive-strength = <2>;
863 bias-pull-up; 877 bias-pull-up;
864 }; 878 };
865 879
866 i2c6_default: i2c6-def 880 i2c6_default: i2c6-default-state {
867 pins = "gpio22 881 pins = "gpio22", "gpio23";
868 function = "bl 882 function = "blsp_i2c6";
869 drive-strength 883 drive-strength = <2>;
870 bias-disable; 884 bias-disable;
871 }; 885 };
872 886
873 i2c6_sleep: i2c6-sleep 887 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio22 888 pins = "gpio22", "gpio23";
875 function = "bl 889 function = "blsp_i2c6";
876 drive-strength 890 drive-strength = <2>;
877 bias-pull-up; 891 bias-pull-up;
878 }; 892 };
879 893
880 i2c7_default: i2c7-def 894 i2c7_default: i2c7-default-state {
881 pins = "gpio26 895 pins = "gpio26", "gpio27";
882 function = "bl 896 function = "blsp_i2c7";
883 drive-strength 897 drive-strength = <2>;
884 bias-disable; 898 bias-disable;
885 }; 899 };
886 900
887 i2c7_sleep: i2c7-sleep 901 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio26 902 pins = "gpio26", "gpio27";
889 function = "bl 903 function = "blsp_i2c7";
890 drive-strength 904 drive-strength = <2>;
891 bias-pull-up; 905 bias-pull-up;
892 }; 906 };
893 907
894 i2c8_default: i2c8-def 908 i2c8_default: i2c8-default-state {
895 pins = "gpio30 909 pins = "gpio30", "gpio31";
896 function = "bl 910 function = "blsp_i2c8_a";
897 drive-strength 911 drive-strength = <2>;
898 bias-disable; 912 bias-disable;
899 }; 913 };
900 914
901 i2c8_sleep: i2c8-sleep 915 i2c8_sleep: i2c8-sleep-state {
902 pins = "gpio30 916 pins = "gpio30", "gpio31";
903 function = "bl 917 function = "blsp_i2c8_a";
904 drive-strength 918 drive-strength = <2>;
905 bias-pull-up; 919 bias-pull-up;
906 }; 920 };
907 921
908 cci0_default: cci0-def 922 cci0_default: cci0-default-state {
909 pins = "gpio36 923 pins = "gpio36","gpio37";
910 function = "cc 924 function = "cci_i2c";
911 bias-pull-up; 925 bias-pull-up;
912 drive-strength 926 drive-strength = <2>;
913 }; 927 };
914 928
915 cci1_default: cci1-def 929 cci1_default: cci1-default-state {
916 pins = "gpio38 930 pins = "gpio38","gpio39";
917 function = "cc 931 function = "cci_i2c";
918 bias-pull-up; 932 bias-pull-up;
919 drive-strength 933 drive-strength = <2>;
920 }; 934 };
921 935
922 sdc1_state_on: sdc1-on 936 sdc1_state_on: sdc1-on-state {
923 clk-pins { 937 clk-pins {
924 pins = 938 pins = "sdc1_clk";
925 bias-d 939 bias-disable;
926 drive- 940 drive-strength = <16>;
927 }; 941 };
928 942
929 cmd-pins { 943 cmd-pins {
930 pins = 944 pins = "sdc1_cmd";
931 bias-p 945 bias-pull-up;
932 drive- 946 drive-strength = <10>;
933 }; 947 };
934 948
935 data-pins { 949 data-pins {
936 pins = 950 pins = "sdc1_data";
937 bias-p 951 bias-pull-up;
938 drive- 952 drive-strength = <10>;
939 }; 953 };
940 954
941 rclk-pins { 955 rclk-pins {
942 pins = 956 pins = "sdc1_rclk";
943 bias-p 957 bias-pull-down;
944 }; 958 };
945 }; 959 };
946 960
947 sdc1_state_off: sdc1-o 961 sdc1_state_off: sdc1-off-state {
948 clk-pins { 962 clk-pins {
949 pins = 963 pins = "sdc1_clk";
950 bias-d 964 bias-disable;
951 drive- 965 drive-strength = <2>;
952 }; 966 };
953 967
954 cmd-pins { 968 cmd-pins {
955 pins = 969 pins = "sdc1_cmd";
956 bias-p 970 bias-pull-up;
957 drive- 971 drive-strength = <2>;
958 }; 972 };
959 973
960 data-pins { 974 data-pins {
961 pins = 975 pins = "sdc1_data";
962 bias-p 976 bias-pull-up;
963 drive- 977 drive-strength = <2>;
964 }; 978 };
965 979
966 rclk-pins { 980 rclk-pins {
967 pins = 981 pins = "sdc1_rclk";
968 bias-p 982 bias-pull-down;
969 }; 983 };
970 }; 984 };
971 985
972 sdc2_state_on: sdc2-on 986 sdc2_state_on: sdc2-on-state {
973 clk-pins { 987 clk-pins {
974 pins = 988 pins = "sdc2_clk";
975 bias-d 989 bias-disable;
976 drive- 990 drive-strength = <16>;
977 }; 991 };
978 992
979 cmd-pins { 993 cmd-pins {
980 pins = 994 pins = "sdc2_cmd";
981 bias-p 995 bias-pull-up;
982 drive- 996 drive-strength = <10>;
983 }; 997 };
984 998
985 data-pins { 999 data-pins {
986 pins = 1000 pins = "sdc2_data";
987 bias-p 1001 bias-pull-up;
988 drive- 1002 drive-strength = <10>;
989 }; 1003 };
990 }; 1004 };
991 1005
992 sdc2_state_off: sdc2-o 1006 sdc2_state_off: sdc2-off-state {
993 clk-pins { 1007 clk-pins {
994 pins = 1008 pins = "sdc2_clk";
995 bias-d 1009 bias-disable;
996 drive- 1010 drive-strength = <2>;
997 }; 1011 };
998 1012
999 cmd-pins { 1013 cmd-pins {
1000 pins 1014 pins = "sdc2_cmd";
1001 bias- 1015 bias-pull-up;
1002 drive 1016 drive-strength = <2>;
1003 }; 1017 };
1004 1018
1005 data-pins { 1019 data-pins {
1006 pins 1020 pins = "sdc2_data";
1007 bias- 1021 bias-pull-up;
1008 drive 1022 drive-strength = <2>;
1009 }; 1023 };
1010 }; 1024 };
1011 }; 1025 };
1012 1026
1013 remoteproc_mss: remoteproc@40 <<
1014 compatible = "qcom,sd <<
1015 reg = <0x04080000 0x1 <<
1016 reg-names = "qdsp6", <<
1017 <<
1018 interrupts-extended = <<
1019 <<
1020 <<
1021 <<
1022 <<
1023 <<
1024 interrupt-names = "wd <<
1025 "fa <<
1026 "re <<
1027 "ha <<
1028 "st <<
1029 "sh <<
1030 <<
1031 clocks = <&gcc GCC_MS <<
1032 <&gcc GCC_BI <<
1033 <&gcc GCC_BO <<
1034 <&gcc GPLL0_ <<
1035 <&gcc GCC_MS <<
1036 <&gcc GCC_MS <<
1037 <&rpmcc RPM_ <<
1038 <&rpmcc RPM_ <<
1039 clock-names = "iface" <<
1040 "bus", <<
1041 "mem", <<
1042 "gpll0_ <<
1043 "snoc_a <<
1044 "mnoc_a <<
1045 "qdss", <<
1046 "xo"; <<
1047 <<
1048 qcom,smem-states = <& <<
1049 qcom,smem-state-names <<
1050 <<
1051 resets = <&gcc GCC_MS <<
1052 reset-names = "mss_re <<
1053 <<
1054 qcom,halt-regs = <&tc <<
1055 <<
1056 power-domains = <&rpm <<
1057 <&rpm <<
1058 power-domain-names = <<
1059 <<
1060 memory-region = <&mba <<
1061 <<
1062 status = "disabled"; <<
1063 <<
1064 glink-edge { <<
1065 interrupts = <<
1066 label = "mode <<
1067 qcom,remote-p <<
1068 mboxes = <&ap <<
1069 }; <<
1070 }; <<
1071 <<
1072 adreno_gpu: gpu@5000000 { 1027 adreno_gpu: gpu@5000000 {
1073 compatible = "qcom,ad 1028 compatible = "qcom,adreno-508.0", "qcom,adreno";
1074 1029
1075 reg = <0x05000000 0x4 1030 reg = <0x05000000 0x40000>;
1076 reg-names = "kgsl_3d0 1031 reg-names = "kgsl_3d0_reg_memory";
1077 1032
1078 interrupts = <GIC_SPI !! 1033 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
1079 1034
1080 clocks = <&gcc GCC_GP 1035 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1081 <&gpucc GPUCC 1036 <&gpucc GPUCC_RBBMTIMER_CLK>,
1082 <&gcc GCC_BIM 1037 <&gcc GCC_BIMC_GFX_CLK>,
1083 <&gcc GCC_GPU 1038 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1084 <&gpucc GPUCC 1039 <&gpucc GPUCC_RBCPR_CLK>,
1085 <&gpucc GPUCC 1040 <&gpucc GPUCC_GFX3D_CLK>;
1086 1041
1087 clock-names = "iface" 1042 clock-names = "iface",
1088 "rbbmtimer", 1043 "rbbmtimer",
1089 "mem", 1044 "mem",
1090 "mem_iface", 1045 "mem_iface",
1091 "rbcpr", 1046 "rbcpr",
1092 "core"; 1047 "core";
1093 1048
1094 power-domains = <&rpm 1049 power-domains = <&rpmpd SDM660_VDDMX>;
1095 iommus = <&kgsl_smmu 1050 iommus = <&kgsl_smmu 0>;
1096 1051
1097 nvmem-cells = <&gpu_s 1052 nvmem-cells = <&gpu_speed_bin>;
1098 nvmem-cell-names = "s 1053 nvmem-cell-names = "speed_bin";
1099 1054
1100 interconnects = <&bim 1055 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1101 interconnect-names = 1056 interconnect-names = "gfx-mem";
1102 1057
1103 operating-points-v2 = 1058 operating-points-v2 = <&gpu_sdm630_opp_table>;
1104 #cooling-cells = <2>; <<
1105 1059
1106 status = "disabled"; 1060 status = "disabled";
1107 1061
1108 gpu_sdm630_opp_table: 1062 gpu_sdm630_opp_table: opp-table {
1109 compatible = 1063 compatible = "operating-points-v2";
1110 opp-775000000 1064 opp-775000000 {
1111 opp-h 1065 opp-hz = /bits/ 64 <775000000>;
1112 opp-l 1066 opp-level = <RPM_SMD_LEVEL_TURBO>;
1113 opp-p 1067 opp-peak-kBps = <5412000>;
1114 opp-s 1068 opp-supported-hw = <0xa2>;
1115 }; 1069 };
1116 opp-647000000 1070 opp-647000000 {
1117 opp-h 1071 opp-hz = /bits/ 64 <647000000>;
1118 opp-l 1072 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1119 opp-p 1073 opp-peak-kBps = <4068000>;
1120 opp-s 1074 opp-supported-hw = <0xff>;
1121 }; 1075 };
1122 opp-588000000 1076 opp-588000000 {
1123 opp-h 1077 opp-hz = /bits/ 64 <588000000>;
1124 opp-l 1078 opp-level = <RPM_SMD_LEVEL_NOM>;
1125 opp-p 1079 opp-peak-kBps = <3072000>;
1126 opp-s 1080 opp-supported-hw = <0xff>;
1127 }; 1081 };
1128 opp-465000000 1082 opp-465000000 {
1129 opp-h 1083 opp-hz = /bits/ 64 <465000000>;
1130 opp-l 1084 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1131 opp-p 1085 opp-peak-kBps = <2724000>;
1132 opp-s 1086 opp-supported-hw = <0xff>;
1133 }; 1087 };
1134 opp-370000000 1088 opp-370000000 {
1135 opp-h 1089 opp-hz = /bits/ 64 <370000000>;
1136 opp-l 1090 opp-level = <RPM_SMD_LEVEL_SVS>;
1137 opp-p 1091 opp-peak-kBps = <2188000>;
1138 opp-s 1092 opp-supported-hw = <0xff>;
1139 }; 1093 };
1140 opp-240000000 1094 opp-240000000 {
1141 opp-h 1095 opp-hz = /bits/ 64 <240000000>;
1142 opp-l 1096 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1143 opp-p 1097 opp-peak-kBps = <1648000>;
1144 opp-s 1098 opp-supported-hw = <0xff>;
1145 }; 1099 };
1146 opp-160000000 1100 opp-160000000 {
1147 opp-h 1101 opp-hz = /bits/ 64 <160000000>;
1148 opp-l 1102 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1149 opp-p 1103 opp-peak-kBps = <1200000>;
1150 opp-s 1104 opp-supported-hw = <0xff>;
1151 }; 1105 };
1152 }; 1106 };
1153 }; 1107 };
1154 1108
1155 kgsl_smmu: iommu@5040000 { 1109 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sd 1110 compatible = "qcom,sdm630-smmu-v2",
1157 "qcom,ad 1111 "qcom,adreno-smmu", "qcom,smmu-v2";
1158 reg = <0x05040000 0x1 1112 reg = <0x05040000 0x10000>;
1159 1113
1160 /* 1114 /*
1161 * GX GDSC parent is 1115 * GX GDSC parent is CX. We need to bring up CX for SMMU
1162 * but we need both u 1116 * but we need both up for Adreno. On the other hand, we
1163 * need to manage the 1117 * need to manage the GX rpmpd domain in the adreno driver.
1164 * Enable CX/GX GDSCs 1118 * Enable CX/GX GDSCs here so that we can manage just the GX
1165 * RPM Power Domain i 1119 * RPM Power Domain in the Adreno driver.
1166 */ 1120 */
1167 power-domains = <&gpu 1121 power-domains = <&gpucc GPU_GX_GDSC>;
1168 clocks = <&gcc GCC_GP 1122 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1169 <&gcc GCC_BI 1123 <&gcc GCC_BIMC_GFX_CLK>,
1170 <&gcc GCC_GP 1124 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1171 clock-names = "iface" !! 1125 clock-names = "iface", "mem", "mem_iface";
1172 "mem", <<
1173 "mem_if <<
1174 #global-interrupts = 1126 #global-interrupts = <2>;
1175 #iommu-cells = <1>; 1127 #iommu-cells = <1>;
1176 1128
1177 interrupts = 1129 interrupts =
1178 <GIC_SPI 229 1130 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 231 1131 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1180 1132
1181 <GIC_SPI 329 1133 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 330 1134 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 331 1135 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 332 1136 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 116 1137 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 117 1138 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 349 1139 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 350 1140 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1189 1141
1190 status = "disabled"; 1142 status = "disabled";
1191 }; 1143 };
1192 1144
1193 gpucc: clock-controller@50650 1145 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gp 1146 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>; 1147 #clock-cells = <1>;
1196 #reset-cells = <1>; 1148 #reset-cells = <1>;
1197 #power-domain-cells = 1149 #power-domain-cells = <1>;
1198 reg = <0x05065000 0x9 1150 reg = <0x05065000 0x9038>;
1199 1151
1200 clocks = <&xo_board>, 1152 clocks = <&xo_board>,
1201 <&gcc GCC_GP 1153 <&gcc GCC_GPU_GPLL0_CLK>,
1202 <&gcc GCC_GP 1154 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1203 clock-names = "xo", 1155 clock-names = "xo",
1204 "gcc_gp 1156 "gcc_gpu_gpll0_clk",
1205 "gcc_gp 1157 "gcc_gpu_gpll0_div_clk";
1206 status = "disabled"; 1158 status = "disabled";
1207 }; 1159 };
1208 1160
1209 lpass_smmu: iommu@5100000 { 1161 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sd 1162 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 reg = <0x05100000 0x4 1163 reg = <0x05100000 0x40000>;
1212 #iommu-cells = <1>; 1164 #iommu-cells = <1>;
1213 1165
1214 #global-interrupts = 1166 #global-interrupts = <2>;
1215 interrupts = 1167 interrupts =
1216 <GIC_SPI 229 1168 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 231 1169 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1218 1170
1219 <GIC_SPI 226 1171 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 393 1172 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 394 1173 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 395 1174 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 396 1175 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 397 1176 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 398 1177 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 399 1178 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 400 1179 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 401 1180 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 402 1181 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 403 1182 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 137 1183 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 224 1184 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 225 1185 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 310 1186 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 404 1187 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1236 1188
1237 status = "disabled"; 1189 status = "disabled";
1238 }; 1190 };
1239 1191
1240 sram@290000 { 1192 sram@290000 {
1241 compatible = "qcom,rp 1193 compatible = "qcom,rpm-stats";
1242 reg = <0x00290000 0x1 1194 reg = <0x00290000 0x10000>;
1243 }; 1195 };
1244 1196
1245 spmi_bus: spmi@800f000 { 1197 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,sp 1198 compatible = "qcom,spmi-pmic-arb";
1247 reg = <0x0800f000 0x1 !! 1199 reg = <0x0800f000 0x1000>,
1248 <0x08400000 0x1 !! 1200 <0x08400000 0x1000000>,
1249 <0x09400000 0x1 !! 1201 <0x09400000 0x1000000>,
1250 <0x0a400000 0x2 !! 1202 <0x0a400000 0x220000>,
1251 <0x0800a000 0x3 !! 1203 <0x0800a000 0x3000>;
1252 reg-names = "core", " 1204 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "pe 1205 interrupt-names = "periph_irq";
1254 interrupts = <GIC_SPI 1206 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1255 qcom,ee = <0>; 1207 qcom,ee = <0>;
1256 qcom,channel = <0>; 1208 qcom,channel = <0>;
1257 #address-cells = <2>; 1209 #address-cells = <2>;
1258 #size-cells = <0>; 1210 #size-cells = <0>;
1259 interrupt-controller; 1211 interrupt-controller;
1260 #interrupt-cells = <4 1212 #interrupt-cells = <4>;
1261 }; 1213 };
1262 1214
1263 usb3: usb@a8f8800 { 1215 usb3: usb@a8f8800 {
1264 compatible = "qcom,sd 1216 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1265 reg = <0x0a8f8800 0x4 1217 reg = <0x0a8f8800 0x400>;
1266 status = "disabled"; 1218 status = "disabled";
1267 #address-cells = <1>; 1219 #address-cells = <1>;
1268 #size-cells = <1>; 1220 #size-cells = <1>;
1269 ranges; 1221 ranges;
1270 1222
1271 clocks = <&gcc GCC_CF 1223 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1272 <&gcc GCC_US 1224 <&gcc GCC_USB30_MASTER_CLK>,
1273 <&gcc GCC_AG 1225 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1274 <&gcc GCC_US 1226 <&gcc GCC_USB30_SLEEP_CLK>,
1275 <&gcc GCC_US !! 1227 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
>> 1228 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1276 clock-names = "cfg_no 1229 clock-names = "cfg_noc",
1277 "core", 1230 "core",
1278 "iface" 1231 "iface",
1279 "sleep" 1232 "sleep",
1280 "mock_u !! 1233 "mock_utmi",
>> 1234 "bus";
1281 1235
1282 assigned-clocks = <&g 1236 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1283 <&g !! 1237 <&gcc GCC_USB30_MASTER_CLK>,
1284 assigned-clock-rates !! 1238 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1239 assigned-clock-rates = <19200000>, <120000000>,
>> 1240 <19200000>;
1285 1241
1286 interrupts = <GIC_SPI !! 1242 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI <<
1288 <GIC_SPI <<
1289 <GIC_SPI 1243 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1290 interrupt-names = "pw !! 1244 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1291 "qu <<
1292 "hs <<
1293 "ss <<
1294 1245
1295 power-domains = <&gcc 1246 power-domains = <&gcc USB_30_GDSC>;
>> 1247 qcom,select-utmi-as-pipe-clk;
1296 1248
1297 resets = <&gcc GCC_US 1249 resets = <&gcc GCC_USB_30_BCR>;
1298 1250
1299 usb3_dwc3: usb@a80000 1251 usb3_dwc3: usb@a800000 {
1300 compatible = 1252 compatible = "snps,dwc3";
1301 reg = <0x0a80 1253 reg = <0x0a800000 0xc8d0>;
1302 interrupts = 1254 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1303 snps,dis_u2_s 1255 snps,dis_u2_susphy_quirk;
1304 snps,dis_enbl 1256 snps,dis_enblslpm_quirk;
1305 snps,parkmode <<
1306 1257
1307 phys = <&qusb !! 1258 /*
1308 phy-names = " !! 1259 * SDM630 technically supports USB3 but I
>> 1260 * haven't seen any devices making use of it.
>> 1261 */
>> 1262 maximum-speed = "high-speed";
>> 1263 phys = <&qusb2phy0>;
>> 1264 phy-names = "usb2-phy";
1309 snps,hird-thr 1265 snps,hird-threshold = /bits/ 8 <0>;
1310 }; 1266 };
1311 }; 1267 };
1312 1268
1313 usb3_qmpphy: phy@c010000 { <<
1314 compatible = "qcom,sd <<
1315 reg = <0x0c010000 0x1 <<
1316 <<
1317 clocks = <&gcc GCC_US <<
1318 <&gcc GCC_US <<
1319 <&gcc GCC_US <<
1320 <&gcc GCC_US <<
1321 clock-names = "aux", <<
1322 "ref", <<
1323 "cfg_ah <<
1324 "pipe"; <<
1325 clock-output-names = <<
1326 #clock-cells = <0>; <<
1327 #phy-cells = <0>; <<
1328 <<
1329 resets = <&gcc GCC_US <<
1330 <&gcc GCC_US <<
1331 reset-names = "phy", <<
1332 "phy_ph <<
1333 <<
1334 qcom,tcsr-reg = <&tcs <<
1335 <<
1336 status = "disabled"; <<
1337 }; <<
1338 <<
1339 qusb2phy0: phy@c012000 { 1269 qusb2phy0: phy@c012000 {
1340 compatible = "qcom,sd 1270 compatible = "qcom,sdm660-qusb2-phy";
1341 reg = <0x0c012000 0x1 1271 reg = <0x0c012000 0x180>;
1342 #phy-cells = <0>; 1272 #phy-cells = <0>;
1343 1273
1344 clocks = <&gcc GCC_US 1274 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1345 <&gcc GCC_RX 1275 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1346 clock-names = "cfg_ah 1276 clock-names = "cfg_ahb", "ref";
1347 1277
1348 resets = <&gcc GCC_QU 1278 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1349 nvmem-cells = <&qusb2 1279 nvmem-cells = <&qusb2_hstx_trim>;
1350 status = "disabled"; 1280 status = "disabled";
1351 }; 1281 };
1352 1282
1353 qusb2phy1: phy@c014000 { 1283 qusb2phy1: phy@c014000 {
1354 compatible = "qcom,sd 1284 compatible = "qcom,sdm660-qusb2-phy";
1355 reg = <0x0c014000 0x1 1285 reg = <0x0c014000 0x180>;
1356 #phy-cells = <0>; 1286 #phy-cells = <0>;
1357 1287
1358 clocks = <&gcc GCC_US 1288 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1359 <&gcc GCC_RX 1289 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1360 clock-names = "cfg_ah 1290 clock-names = "cfg_ahb", "ref";
1361 1291
1362 resets = <&gcc GCC_QU 1292 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1363 nvmem-cells = <&qusb2 1293 nvmem-cells = <&qusb2_hstx_trim>;
1364 status = "disabled"; 1294 status = "disabled";
1365 }; 1295 };
1366 1296
1367 sdhc_2: mmc@c084000 { 1297 sdhc_2: mmc@c084000 {
1368 compatible = "qcom,sd 1298 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1369 reg = <0x0c084000 0x1 1299 reg = <0x0c084000 0x1000>;
1370 reg-names = "hc"; 1300 reg-names = "hc";
1371 1301
1372 interrupts = <GIC_SPI 1302 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_ 1303 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1374 interrupt-names = "hc 1304 interrupt-names = "hc_irq", "pwr_irq";
1375 1305
1376 bus-width = <4>; 1306 bus-width = <4>;
1377 1307
1378 clocks = <&gcc GCC_SD 1308 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1379 <&gcc 1309 <&gcc GCC_SDCC2_APPS_CLK>,
1380 <&xo_ 1310 <&xo_board>;
1381 clock-names = "iface" 1311 clock-names = "iface", "core", "xo";
1382 1312
1383 1313
1384 interconnects = <&a2n 1314 interconnects = <&a2noc 3 &a2noc 10>,
1385 <&gno 1315 <&gnoc 0 &cnoc 28>;
1386 interconnect-names = 1316 interconnect-names = "sdhc-ddr","cpu-sdhc";
1387 operating-points-v2 = 1317 operating-points-v2 = <&sdhc2_opp_table>;
1388 1318
1389 pinctrl-names = "defa 1319 pinctrl-names = "default", "sleep";
1390 pinctrl-0 = <&sdc2_st 1320 pinctrl-0 = <&sdc2_state_on>;
1391 pinctrl-1 = <&sdc2_st 1321 pinctrl-1 = <&sdc2_state_off>;
1392 power-domains = <&rpm 1322 power-domains = <&rpmpd SDM660_VDDCX>;
1393 1323
1394 status = "disabled"; 1324 status = "disabled";
1395 1325
1396 sdhc2_opp_table: opp- 1326 sdhc2_opp_table: opp-table {
1397 compatible = 1327 compatible = "operating-points-v2";
1398 1328
1399 opp-50000000 1329 opp-50000000 {
1400 opp-h 1330 opp-hz = /bits/ 64 <50000000>;
1401 requi 1331 required-opps = <&rpmpd_opp_low_svs>;
1402 opp-p 1332 opp-peak-kBps = <200000 140000>;
1403 opp-a 1333 opp-avg-kBps = <130718 133320>;
1404 }; 1334 };
1405 opp-10000000 1335 opp-100000000 {
1406 opp-h 1336 opp-hz = /bits/ 64 <100000000>;
1407 requi 1337 required-opps = <&rpmpd_opp_svs>;
1408 opp-p 1338 opp-peak-kBps = <250000 160000>;
1409 opp-a 1339 opp-avg-kBps = <196078 150000>;
1410 }; 1340 };
1411 opp-20000000 1341 opp-200000000 {
1412 opp-h 1342 opp-hz = /bits/ 64 <200000000>;
1413 requi 1343 required-opps = <&rpmpd_opp_nom>;
1414 opp-p 1344 opp-peak-kBps = <4096000 4096000>;
1415 opp-a 1345 opp-avg-kBps = <1338562 1338562>;
1416 }; 1346 };
1417 }; 1347 };
1418 }; 1348 };
1419 1349
1420 sdhc_1: mmc@c0c4000 { 1350 sdhc_1: mmc@c0c4000 {
1421 compatible = "qcom,sd 1351 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg = <0x0c0c4000 0x1 1352 reg = <0x0c0c4000 0x1000>,
1423 <0x0c0c5000 0x1 1353 <0x0c0c5000 0x1000>,
1424 <0x0c0c8000 0x8 1354 <0x0c0c8000 0x8000>;
1425 reg-names = "hc", "cq 1355 reg-names = "hc", "cqhci", "ice";
1426 1356
1427 interrupts = <GIC_SPI 1357 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_ 1358 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc 1359 interrupt-names = "hc_irq", "pwr_irq";
1430 1360
1431 clocks = <&gcc GCC_SD 1361 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1432 <&gcc GCC_SD 1362 <&gcc GCC_SDCC1_APPS_CLK>,
1433 <&xo_board>, 1363 <&xo_board>,
1434 <&gcc GCC_SD 1364 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1435 clock-names = "iface" 1365 clock-names = "iface", "core", "xo", "ice";
1436 1366
1437 interconnects = <&a2n 1367 interconnects = <&a2noc 2 &a2noc 10>,
1438 <&gno 1368 <&gnoc 0 &cnoc 27>;
1439 interconnect-names = 1369 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1440 operating-points-v2 = 1370 operating-points-v2 = <&sdhc1_opp_table>;
1441 pinctrl-names = "defa 1371 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_st 1372 pinctrl-0 = <&sdc1_state_on>;
1443 pinctrl-1 = <&sdc1_st 1373 pinctrl-1 = <&sdc1_state_off>;
1444 power-domains = <&rpm 1374 power-domains = <&rpmpd SDM660_VDDCX>;
1445 1375
1446 bus-width = <8>; 1376 bus-width = <8>;
1447 non-removable; 1377 non-removable;
1448 1378
1449 status = "disabled"; 1379 status = "disabled";
1450 1380
1451 sdhc1_opp_table: opp- 1381 sdhc1_opp_table: opp-table {
1452 compatible = 1382 compatible = "operating-points-v2";
1453 1383
1454 opp-50000000 1384 opp-50000000 {
1455 opp-h 1385 opp-hz = /bits/ 64 <50000000>;
1456 requi 1386 required-opps = <&rpmpd_opp_low_svs>;
1457 opp-p 1387 opp-peak-kBps = <200000 140000>;
1458 opp-a 1388 opp-avg-kBps = <130718 133320>;
1459 }; 1389 };
1460 opp-100000000 1390 opp-100000000 {
1461 opp-h 1391 opp-hz = /bits/ 64 <100000000>;
1462 requi 1392 required-opps = <&rpmpd_opp_svs>;
1463 opp-p 1393 opp-peak-kBps = <250000 160000>;
1464 opp-a 1394 opp-avg-kBps = <196078 150000>;
1465 }; 1395 };
1466 opp-384000000 1396 opp-384000000 {
1467 opp-h 1397 opp-hz = /bits/ 64 <384000000>;
1468 requi 1398 required-opps = <&rpmpd_opp_nom>;
1469 opp-p 1399 opp-peak-kBps = <4096000 4096000>;
1470 opp-a 1400 opp-avg-kBps = <1338562 1338562>;
1471 }; 1401 };
1472 }; 1402 };
1473 }; 1403 };
1474 1404
1475 usb2: usb@c2f8800 { 1405 usb2: usb@c2f8800 {
1476 compatible = "qcom,sd 1406 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1477 reg = <0x0c2f8800 0x4 1407 reg = <0x0c2f8800 0x400>;
1478 status = "disabled"; 1408 status = "disabled";
1479 #address-cells = <1>; 1409 #address-cells = <1>;
1480 #size-cells = <1>; 1410 #size-cells = <1>;
1481 ranges; 1411 ranges;
1482 1412
1483 clocks = <&gcc GCC_CF 1413 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1484 <&gcc GCC_US 1414 <&gcc GCC_USB20_MASTER_CLK>,
1485 <&gcc GCC_US !! 1415 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1486 <&gcc GCC_US !! 1416 <&gcc GCC_USB20_SLEEP_CLK>;
1487 clock-names = "cfg_no 1417 clock-names = "cfg_noc", "core",
1488 "sleep" !! 1418 "mock_utmi", "sleep";
1489 1419
1490 assigned-clocks = <&g 1420 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1491 <&g 1421 <&gcc GCC_USB20_MASTER_CLK>;
1492 assigned-clock-rates 1422 assigned-clock-rates = <19200000>, <60000000>;
1493 1423
1494 interrupts = <GIC_SPI !! 1424 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1495 <GIC_SPI !! 1425 interrupt-names = "hs_phy_irq";
1496 <GIC_SPI <<
1497 interrupt-names = "pw <<
1498 "qu <<
1499 "hs <<
1500 1426
1501 qcom,select-utmi-as-p 1427 qcom,select-utmi-as-pipe-clk;
1502 1428
1503 resets = <&gcc GCC_US 1429 resets = <&gcc GCC_USB_20_BCR>;
1504 1430
1505 usb2_dwc3: usb@c20000 1431 usb2_dwc3: usb@c200000 {
1506 compatible = 1432 compatible = "snps,dwc3";
1507 reg = <0x0c20 1433 reg = <0x0c200000 0xc8d0>;
1508 interrupts = 1434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1509 snps,dis_u2_s 1435 snps,dis_u2_susphy_quirk;
1510 snps,dis_enbl 1436 snps,dis_enblslpm_quirk;
1511 1437
1512 /* This is th 1438 /* This is the HS-only host */
1513 maximum-speed 1439 maximum-speed = "high-speed";
1514 phys = <&qusb 1440 phys = <&qusb2phy1>;
1515 phy-names = " 1441 phy-names = "usb2-phy";
1516 snps,hird-thr 1442 snps,hird-threshold = /bits/ 8 <0>;
1517 }; 1443 };
1518 }; 1444 };
1519 1445
1520 mmcc: clock-controller@c8c000 1446 mmcc: clock-controller@c8c0000 {
1521 compatible = "qcom,mm 1447 compatible = "qcom,mmcc-sdm630";
1522 reg = <0x0c8c0000 0x4 1448 reg = <0x0c8c0000 0x40000>;
1523 #clock-cells = <1>; 1449 #clock-cells = <1>;
1524 #reset-cells = <1>; 1450 #reset-cells = <1>;
1525 #power-domain-cells = 1451 #power-domain-cells = <1>;
1526 clock-names = "xo", 1452 clock-names = "xo",
1527 "slee 1453 "sleep_clk",
1528 "gpll 1454 "gpll0",
1529 "gpll 1455 "gpll0_div",
1530 "dsi0 1456 "dsi0pll",
1531 "dsi0 1457 "dsi0pllbyte",
1532 "dsi1 1458 "dsi1pll",
1533 "dsi1 1459 "dsi1pllbyte",
1534 "dp_l 1460 "dp_link_2x_clk_divsel_five",
1535 "dp_v 1461 "dp_vco_divided_clk_src_mux";
1536 clocks = <&rpmcc RPM_ 1462 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1537 <&sle 1463 <&sleep_clk>,
1538 <&gcc 1464 <&gcc GCC_MMSS_GPLL0_CLK>,
1539 <&gcc 1465 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1540 <&mds !! 1466 <&dsi0_phy 1>,
1541 <&mds !! 1467 <&dsi0_phy 0>,
1542 <0>, 1468 <0>,
1543 <0>, 1469 <0>,
1544 <0>, 1470 <0>,
1545 <0>; 1471 <0>;
1546 }; 1472 };
1547 1473
1548 mdss: display-subsystem@c9000 1474 mdss: display-subsystem@c900000 {
1549 compatible = "qcom,md 1475 compatible = "qcom,mdss";
1550 reg = <0x0c900000 0x1 1476 reg = <0x0c900000 0x1000>,
1551 <0x0c9b0000 0x1 1477 <0x0c9b0000 0x1040>;
1552 reg-names = "mdss_phy 1478 reg-names = "mdss_phys", "vbif_phys";
1553 1479
1554 power-domains = <&mmc 1480 power-domains = <&mmcc MDSS_GDSC>;
1555 1481
1556 clocks = <&mmcc MDSS_ 1482 clocks = <&mmcc MDSS_AHB_CLK>,
1557 <&mmcc MDSS_ 1483 <&mmcc MDSS_AXI_CLK>,
1558 <&mmcc MDSS_ 1484 <&mmcc MDSS_VSYNC_CLK>,
1559 <&mmcc MDSS_ 1485 <&mmcc MDSS_MDP_CLK>;
1560 clock-names = "iface" 1486 clock-names = "iface",
1561 "bus", 1487 "bus",
1562 "vsync" 1488 "vsync",
1563 "core"; 1489 "core";
1564 1490
1565 interrupts = <GIC_SPI 1491 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1566 1492
1567 interrupt-controller; 1493 interrupt-controller;
1568 #interrupt-cells = <1 1494 #interrupt-cells = <1>;
1569 1495
1570 #address-cells = <1>; 1496 #address-cells = <1>;
1571 #size-cells = <1>; 1497 #size-cells = <1>;
1572 ranges; 1498 ranges;
1573 status = "disabled"; 1499 status = "disabled";
1574 1500
1575 mdp: display-controll 1501 mdp: display-controller@c901000 {
1576 compatible = 1502 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1577 reg = <0x0c90 1503 reg = <0x0c901000 0x89000>;
1578 reg-names = " 1504 reg-names = "mdp_phys";
1579 1505
1580 interrupt-par 1506 interrupt-parent = <&mdss>;
1581 interrupts = 1507 interrupts = <0>;
1582 1508
1583 assigned-cloc 1509 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1584 1510 <&mmcc MDSS_VSYNC_CLK>;
1585 assigned-cloc 1511 assigned-clock-rates = <300000000>,
1586 1512 <19200000>;
1587 clocks = <&mm 1513 clocks = <&mmcc MDSS_AHB_CLK>,
1588 <&mm 1514 <&mmcc MDSS_AXI_CLK>,
1589 <&mm 1515 <&mmcc MDSS_MDP_CLK>,
1590 <&mm 1516 <&mmcc MDSS_VSYNC_CLK>;
1591 clock-names = 1517 clock-names = "iface",
1592 1518 "bus",
1593 1519 "core",
1594 1520 "vsync";
1595 1521
1596 interconnects 1522 interconnects = <&mnoc 2 &bimc 5>,
1597 1523 <&mnoc 3 &bimc 5>,
1598 1524 <&gnoc 0 &mnoc 17>;
1599 interconnect- 1525 interconnect-names = "mdp0-mem",
1600 1526 "mdp1-mem",
1601 1527 "rotator-mem";
1602 iommus = <&mm 1528 iommus = <&mmss_smmu 0>;
1603 operating-poi 1529 operating-points-v2 = <&mdp_opp_table>;
1604 power-domains 1530 power-domains = <&rpmpd SDM660_VDDCX>;
1605 1531
1606 ports { 1532 ports {
1607 #addr 1533 #address-cells = <1>;
1608 #size 1534 #size-cells = <0>;
1609 1535
1610 port@ 1536 port@0 {
1611 1537 reg = <0>;
1612 1538 mdp5_intf1_out: endpoint {
1613 !! 1539 remote-endpoint = <&dsi0_in>;
1614 1540 };
1615 }; 1541 };
1616 }; 1542 };
1617 1543
1618 mdp_opp_table 1544 mdp_opp_table: opp-table {
1619 compa 1545 compatible = "operating-points-v2";
1620 1546
1621 opp-1 1547 opp-150000000 {
1622 1548 opp-hz = /bits/ 64 <150000000>;
1623 1549 opp-peak-kBps = <320000 320000 76800>;
1624 1550 required-opps = <&rpmpd_opp_low_svs>;
1625 }; 1551 };
1626 opp-2 1552 opp-275000000 {
1627 1553 opp-hz = /bits/ 64 <275000000>;
1628 1554 opp-peak-kBps = <6400000 6400000 160000>;
1629 1555 required-opps = <&rpmpd_opp_svs>;
1630 }; 1556 };
1631 opp-3 1557 opp-300000000 {
1632 1558 opp-hz = /bits/ 64 <300000000>;
1633 1559 opp-peak-kBps = <6400000 6400000 190000>;
1634 1560 required-opps = <&rpmpd_opp_svs_plus>;
1635 }; 1561 };
1636 opp-3 1562 opp-330000000 {
1637 1563 opp-hz = /bits/ 64 <330000000>;
1638 1564 opp-peak-kBps = <6400000 6400000 240000>;
1639 1565 required-opps = <&rpmpd_opp_nom>;
1640 }; 1566 };
1641 opp-4 1567 opp-412500000 {
1642 1568 opp-hz = /bits/ 64 <412500000>;
1643 1569 opp-peak-kBps = <6400000 6400000 320000>;
1644 1570 required-opps = <&rpmpd_opp_turbo>;
1645 }; 1571 };
1646 }; 1572 };
1647 }; 1573 };
1648 1574
1649 mdss_dsi0: dsi@c99400 !! 1575 dsi0: dsi@c994000 {
1650 compatible = 1576 compatible = "qcom,sdm660-dsi-ctrl",
1651 1577 "qcom,mdss-dsi-ctrl";
1652 reg = <0x0c99 1578 reg = <0x0c994000 0x400>;
1653 reg-names = " 1579 reg-names = "dsi_ctrl";
1654 1580
1655 operating-poi 1581 operating-points-v2 = <&dsi_opp_table>;
1656 power-domains 1582 power-domains = <&rpmpd SDM660_VDDCX>;
1657 1583
1658 interrupt-par 1584 interrupt-parent = <&mdss>;
1659 interrupts = 1585 interrupts = <4>;
1660 1586
1661 assigned-cloc 1587 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1662 1588 <&mmcc PCLK0_CLK_SRC>;
1663 assigned-cloc !! 1589 assigned-clock-parents = <&dsi0_phy 0>,
1664 !! 1590 <&dsi0_phy 1>;
1665 1591
1666 clocks = <&mm 1592 clocks = <&mmcc MDSS_MDP_CLK>,
1667 <&mm 1593 <&mmcc MDSS_BYTE0_CLK>,
1668 <&mm 1594 <&mmcc MDSS_BYTE0_INTF_CLK>,
1669 <&mm 1595 <&mmcc MNOC_AHB_CLK>,
1670 <&mm 1596 <&mmcc MDSS_AHB_CLK>,
1671 <&mm 1597 <&mmcc MDSS_AXI_CLK>,
1672 <&mm 1598 <&mmcc MISC_AHB_CLK>,
1673 <&mm 1599 <&mmcc MDSS_PCLK0_CLK>,
1674 <&mm 1600 <&mmcc MDSS_ESC0_CLK>;
1675 clock-names = 1601 clock-names = "mdp_core",
1676 1602 "byte",
1677 1603 "byte_intf",
1678 1604 "mnoc",
1679 1605 "iface",
1680 1606 "bus",
1681 1607 "core_mmss",
1682 1608 "pixel",
1683 1609 "core";
1684 1610
1685 phys = <&mdss !! 1611 phys = <&dsi0_phy>;
1686 1612
1687 status = "dis 1613 status = "disabled";
1688 1614
1689 ports { 1615 ports {
1690 #addr 1616 #address-cells = <1>;
1691 #size 1617 #size-cells = <0>;
1692 1618
1693 port@ 1619 port@0 {
1694 1620 reg = <0>;
1695 !! 1621 dsi0_in: endpoint {
1696 1622 remote-endpoint = <&mdp5_intf1_out>;
1697 1623 };
1698 }; 1624 };
1699 1625
1700 port@ 1626 port@1 {
1701 1627 reg = <1>;
1702 !! 1628 dsi0_out: endpoint {
1703 1629 };
1704 }; 1630 };
1705 }; 1631 };
1706 }; 1632 };
1707 1633
1708 mdss_dsi0_phy: phy@c9 !! 1634 dsi0_phy: phy@c994400 {
1709 compatible = 1635 compatible = "qcom,dsi-phy-14nm-660";
1710 reg = <0x0c99 1636 reg = <0x0c994400 0x100>,
1711 <0x0c99 1637 <0x0c994500 0x300>,
1712 <0x0c99 1638 <0x0c994800 0x188>;
1713 reg-names = " 1639 reg-names = "dsi_phy",
1714 " 1640 "dsi_phy_lane",
1715 " 1641 "dsi_pll";
1716 1642
1717 #clock-cells 1643 #clock-cells = <1>;
1718 #phy-cells = 1644 #phy-cells = <0>;
1719 1645
1720 clocks = <&mm 1646 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1721 clock-names = 1647 clock-names = "iface", "ref";
1722 status = "dis 1648 status = "disabled";
1723 }; 1649 };
1724 }; 1650 };
1725 1651
1726 blsp1_dma: dma-controller@c14 1652 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,ba 1653 compatible = "qcom,bam-v1.7.0";
1728 reg = <0x0c144000 0x1 1654 reg = <0x0c144000 0x1f000>;
1729 interrupts = <GIC_SPI 1655 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1730 clocks = <&gcc GCC_BL 1656 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_cl 1657 clock-names = "bam_clk";
1732 #dma-cells = <1>; 1658 #dma-cells = <1>;
1733 qcom,ee = <0>; 1659 qcom,ee = <0>;
1734 qcom,controlled-remot 1660 qcom,controlled-remotely;
1735 num-channels = <18>; 1661 num-channels = <18>;
1736 qcom,num-ees = <4>; 1662 qcom,num-ees = <4>;
1737 }; 1663 };
1738 1664
1739 blsp1_uart1: serial@c16f000 { 1665 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,ms 1666 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1741 reg = <0x0c16f000 0x2 1667 reg = <0x0c16f000 0x200>;
1742 interrupts = <GIC_SPI 1668 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&gcc GCC_BL 1669 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1744 <&gcc GCC_BL 1670 <&gcc GCC_BLSP1_AHB_CLK>;
1745 clock-names = "core", 1671 clock-names = "core", "iface";
1746 dmas = <&blsp1_dma 0> 1672 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1747 dma-names = "tx", "rx 1673 dma-names = "tx", "rx";
1748 pinctrl-names = "defa 1674 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_u 1675 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_u 1676 pinctrl-1 = <&blsp1_uart1_sleep>;
1751 status = "disabled"; 1677 status = "disabled";
1752 }; 1678 };
1753 1679
1754 blsp1_uart2: serial@c170000 { 1680 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,ms 1681 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 reg = <0x0c170000 0x1 1682 reg = <0x0c170000 0x1000>;
1757 interrupts = <GIC_SPI 1683 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&gcc GCC_BL 1684 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1759 <&gcc GCC_BL 1685 <&gcc GCC_BLSP1_AHB_CLK>;
1760 clock-names = "core", 1686 clock-names = "core", "iface";
1761 dmas = <&blsp1_dma 2> 1687 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1762 dma-names = "tx", "rx 1688 dma-names = "tx", "rx";
1763 pinctrl-names = "defa 1689 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_u 1690 pinctrl-0 = <&blsp1_uart2_default>;
1765 status = "disabled"; 1691 status = "disabled";
1766 }; 1692 };
1767 1693
1768 blsp_i2c1: i2c@c175000 { 1694 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2 1695 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c175000 0x6 1696 reg = <0x0c175000 0x600>;
1771 interrupts = <GIC_SPI 1697 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1772 1698
1773 clocks = <&gcc GCC_BL 1699 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1774 <&gcc 1700 <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1701 clock-names = "core", "iface";
1776 clock-frequency = <40 1702 clock-frequency = <400000>;
1777 dmas = <&blsp1_dma 4> 1703 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1778 dma-names = "tx", "rx 1704 dma-names = "tx", "rx";
1779 1705
1780 pinctrl-names = "defa 1706 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_de 1707 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sl 1708 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>; 1709 #address-cells = <1>;
1784 #size-cells = <0>; 1710 #size-cells = <0>;
1785 status = "disabled"; 1711 status = "disabled";
1786 }; 1712 };
1787 1713
1788 blsp_i2c2: i2c@c176000 { 1714 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2 1715 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c176000 0x6 1716 reg = <0x0c176000 0x600>;
1791 interrupts = <GIC_SPI 1717 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1792 1718
1793 clocks = <&gcc GCC_BL 1719 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1794 <&gcc GCC_BL 1720 <&gcc GCC_BLSP1_AHB_CLK>;
1795 clock-names = "core", 1721 clock-names = "core", "iface";
1796 clock-frequency = <40 1722 clock-frequency = <400000>;
1797 dmas = <&blsp1_dma 6> 1723 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1798 dma-names = "tx", "rx 1724 dma-names = "tx", "rx";
1799 1725
1800 pinctrl-names = "defa 1726 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_de 1727 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sl 1728 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>; 1729 #address-cells = <1>;
1804 #size-cells = <0>; 1730 #size-cells = <0>;
1805 status = "disabled"; 1731 status = "disabled";
1806 }; 1732 };
1807 1733
1808 blsp_i2c3: i2c@c177000 { 1734 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2 1735 compatible = "qcom,i2c-qup-v2.2.1";
1810 reg = <0x0c177000 0x6 1736 reg = <0x0c177000 0x600>;
1811 interrupts = <GIC_SPI 1737 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1812 1738
1813 clocks = <&gcc GCC_BL 1739 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1814 <&gcc GCC_BL 1740 <&gcc GCC_BLSP1_AHB_CLK>;
1815 clock-names = "core", 1741 clock-names = "core", "iface";
1816 clock-frequency = <40 1742 clock-frequency = <400000>;
1817 dmas = <&blsp1_dma 8> 1743 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1818 dma-names = "tx", "rx 1744 dma-names = "tx", "rx";
1819 1745
1820 pinctrl-names = "defa 1746 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_de 1747 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sl 1748 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>; 1749 #address-cells = <1>;
1824 #size-cells = <0>; 1750 #size-cells = <0>;
1825 status = "disabled"; 1751 status = "disabled";
1826 }; 1752 };
1827 1753
1828 blsp_i2c4: i2c@c178000 { 1754 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2 1755 compatible = "qcom,i2c-qup-v2.2.1";
1830 reg = <0x0c178000 0x6 1756 reg = <0x0c178000 0x600>;
1831 interrupts = <GIC_SPI 1757 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1832 1758
1833 clocks = <&gcc GCC_BL 1759 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1834 <&gcc GCC_BL 1760 <&gcc GCC_BLSP1_AHB_CLK>;
1835 clock-names = "core", 1761 clock-names = "core", "iface";
1836 clock-frequency = <40 1762 clock-frequency = <400000>;
1837 dmas = <&blsp1_dma 10 1763 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1838 dma-names = "tx", "rx 1764 dma-names = "tx", "rx";
1839 1765
1840 pinctrl-names = "defa 1766 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_de 1767 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sl 1768 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>; 1769 #address-cells = <1>;
1844 #size-cells = <0>; 1770 #size-cells = <0>;
1845 status = "disabled"; 1771 status = "disabled";
1846 }; 1772 };
1847 1773
1848 blsp2_dma: dma-controller@c18 1774 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,ba 1775 compatible = "qcom,bam-v1.7.0";
1850 reg = <0x0c184000 0x1 1776 reg = <0x0c184000 0x1f000>;
1851 interrupts = <GIC_SPI 1777 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&gcc GCC_BL 1778 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_cl 1779 clock-names = "bam_clk";
1854 #dma-cells = <1>; 1780 #dma-cells = <1>;
1855 qcom,ee = <0>; 1781 qcom,ee = <0>;
1856 qcom,controlled-remot 1782 qcom,controlled-remotely;
1857 num-channels = <18>; 1783 num-channels = <18>;
1858 qcom,num-ees = <4>; 1784 qcom,num-ees = <4>;
1859 }; 1785 };
1860 1786
1861 blsp2_uart1: serial@c1af000 { 1787 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,ms 1788 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x0c1af000 0x2 1789 reg = <0x0c1af000 0x200>;
1864 interrupts = <GIC_SPI 1790 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BL 1791 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1866 <&gcc GCC_BL 1792 <&gcc GCC_BLSP2_AHB_CLK>;
1867 clock-names = "core", 1793 clock-names = "core", "iface";
1868 dmas = <&blsp2_dma 0> 1794 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1869 dma-names = "tx", "rx 1795 dma-names = "tx", "rx";
1870 pinctrl-names = "defa 1796 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_u 1797 pinctrl-0 = <&blsp2_uart1_default>;
1872 pinctrl-1 = <&blsp2_u 1798 pinctrl-1 = <&blsp2_uart1_sleep>;
1873 status = "disabled"; 1799 status = "disabled";
1874 }; 1800 };
1875 1801
1876 blsp_i2c5: i2c@c1b5000 { 1802 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2 1803 compatible = "qcom,i2c-qup-v2.2.1";
1878 reg = <0x0c1b5000 0x6 1804 reg = <0x0c1b5000 0x600>;
1879 interrupts = <GIC_SPI 1805 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1880 1806
1881 clocks = <&gcc GCC_BL 1807 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1882 <&gcc GCC_BL 1808 <&gcc GCC_BLSP2_AHB_CLK>;
1883 clock-names = "core", 1809 clock-names = "core", "iface";
1884 clock-frequency = <40 1810 clock-frequency = <400000>;
1885 dmas = <&blsp2_dma 4> 1811 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1886 dma-names = "tx", "rx 1812 dma-names = "tx", "rx";
1887 1813
1888 pinctrl-names = "defa 1814 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_de 1815 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sl 1816 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>; 1817 #address-cells = <1>;
1892 #size-cells = <0>; 1818 #size-cells = <0>;
1893 status = "disabled"; 1819 status = "disabled";
1894 }; 1820 };
1895 1821
1896 blsp_i2c6: i2c@c1b6000 { 1822 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2 1823 compatible = "qcom,i2c-qup-v2.2.1";
1898 reg = <0x0c1b6000 0x6 1824 reg = <0x0c1b6000 0x600>;
1899 interrupts = <GIC_SPI 1825 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1900 1826
1901 clocks = <&gcc GCC_BL 1827 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1902 <&gcc GCC_BL 1828 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", 1829 clock-names = "core", "iface";
1904 clock-frequency = <40 1830 clock-frequency = <400000>;
1905 dmas = <&blsp2_dma 6> 1831 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1906 dma-names = "tx", "rx 1832 dma-names = "tx", "rx";
1907 1833
1908 pinctrl-names = "defa 1834 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_de 1835 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sl 1836 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>; 1837 #address-cells = <1>;
1912 #size-cells = <0>; 1838 #size-cells = <0>;
1913 status = "disabled"; 1839 status = "disabled";
1914 }; 1840 };
1915 1841
1916 blsp_i2c7: i2c@c1b7000 { 1842 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2 1843 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x0c1b7000 0x6 1844 reg = <0x0c1b7000 0x600>;
1919 interrupts = <GIC_SPI 1845 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1920 1846
1921 clocks = <&gcc GCC_BL 1847 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1922 <&gcc GCC_BL 1848 <&gcc GCC_BLSP2_AHB_CLK>;
1923 clock-names = "core", 1849 clock-names = "core", "iface";
1924 clock-frequency = <40 1850 clock-frequency = <400000>;
1925 dmas = <&blsp2_dma 8> 1851 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1926 dma-names = "tx", "rx 1852 dma-names = "tx", "rx";
1927 1853
1928 pinctrl-names = "defa 1854 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_de 1855 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sl 1856 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>; 1857 #address-cells = <1>;
1932 #size-cells = <0>; 1858 #size-cells = <0>;
1933 status = "disabled"; 1859 status = "disabled";
1934 }; 1860 };
1935 1861
1936 blsp_i2c8: i2c@c1b8000 { 1862 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2 1863 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x0c1b8000 0x6 1864 reg = <0x0c1b8000 0x600>;
1939 interrupts = <GIC_SPI 1865 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1940 1866
1941 clocks = <&gcc GCC_BL 1867 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1942 <&gcc GCC_BL 1868 <&gcc GCC_BLSP2_AHB_CLK>;
1943 clock-names = "core", 1869 clock-names = "core", "iface";
1944 clock-frequency = <40 1870 clock-frequency = <400000>;
1945 dmas = <&blsp2_dma 10 1871 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1946 dma-names = "tx", "rx 1872 dma-names = "tx", "rx";
1947 1873
1948 pinctrl-names = "defa 1874 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_de 1875 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sl 1876 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>; 1877 #address-cells = <1>;
1952 #size-cells = <0>; 1878 #size-cells = <0>;
1953 status = "disabled"; 1879 status = "disabled";
1954 }; 1880 };
1955 1881
1956 sram@146bf000 { 1882 sram@146bf000 {
1957 compatible = "qcom,sd 1883 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1958 reg = <0x146bf000 0x1 1884 reg = <0x146bf000 0x1000>;
1959 1885
1960 #address-cells = <1>; 1886 #address-cells = <1>;
1961 #size-cells = <1>; 1887 #size-cells = <1>;
1962 1888
1963 ranges = <0 0x146bf00 1889 ranges = <0 0x146bf000 0x1000>;
1964 1890
1965 pil-reloc@94c { 1891 pil-reloc@94c {
1966 compatible = 1892 compatible = "qcom,pil-reloc-info";
1967 reg = <0x94c 1893 reg = <0x94c 0xc8>;
1968 }; 1894 };
1969 }; 1895 };
1970 1896
1971 camss: camss@ca00020 { 1897 camss: camss@ca00020 {
1972 compatible = "qcom,sd 1898 compatible = "qcom,sdm660-camss";
1973 reg = <0x0ca00020 0x1 1899 reg = <0x0ca00020 0x10>,
1974 <0x0ca30000 0x1 1900 <0x0ca30000 0x100>,
1975 <0x0ca30400 0x1 1901 <0x0ca30400 0x100>,
1976 <0x0ca30800 0x1 1902 <0x0ca30800 0x100>,
1977 <0x0ca30c00 0x1 1903 <0x0ca30c00 0x100>,
1978 <0x0c824000 0x1 1904 <0x0c824000 0x1000>,
1979 <0x0ca00120 0x4 1905 <0x0ca00120 0x4>,
1980 <0x0c825000 0x1 1906 <0x0c825000 0x1000>,
1981 <0x0ca00124 0x4 1907 <0x0ca00124 0x4>,
1982 <0x0c826000 0x1 1908 <0x0c826000 0x1000>,
1983 <0x0ca00128 0x4 1909 <0x0ca00128 0x4>,
1984 <0x0ca31000 0x5 1910 <0x0ca31000 0x500>,
1985 <0x0ca10000 0x1 1911 <0x0ca10000 0x1000>,
1986 <0x0ca14000 0x1 1912 <0x0ca14000 0x1000>;
1987 reg-names = "csi_clk_ 1913 reg-names = "csi_clk_mux",
1988 "csid0", 1914 "csid0",
1989 "csid1", 1915 "csid1",
1990 "csid2", 1916 "csid2",
1991 "csid3", 1917 "csid3",
1992 "csiphy0" 1918 "csiphy0",
1993 "csiphy0_ 1919 "csiphy0_clk_mux",
1994 "csiphy1" 1920 "csiphy1",
1995 "csiphy1_ 1921 "csiphy1_clk_mux",
1996 "csiphy2" 1922 "csiphy2",
1997 "csiphy2_ 1923 "csiphy2_clk_mux",
1998 "ispif", 1924 "ispif",
1999 "vfe0", 1925 "vfe0",
2000 "vfe1"; 1926 "vfe1";
2001 interrupts = <GIC_SPI 1927 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2002 <GIC_SPI 1928 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2003 <GIC_SPI 1929 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2004 <GIC_SPI 1930 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2005 <GIC_SPI 1931 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2006 <GIC_SPI 1932 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2007 <GIC_SPI 1933 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2008 <GIC_SPI 1934 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2009 <GIC_SPI 1935 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2010 <GIC_SPI 1936 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2011 interrupt-names = "cs 1937 interrupt-names = "csid0",
2012 "cs 1938 "csid1",
2013 "cs 1939 "csid2",
2014 "cs 1940 "csid3",
2015 "cs 1941 "csiphy0",
2016 "cs 1942 "csiphy1",
2017 "cs 1943 "csiphy2",
2018 "is 1944 "ispif",
2019 "vf 1945 "vfe0",
2020 "vf 1946 "vfe1";
2021 clocks = <&mmcc CAMSS 1947 clocks = <&mmcc CAMSS_AHB_CLK>,
2022 <&mmcc CAMSS 1948 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2023 <&mmcc CAMSS 1949 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2024 <&mmcc CAMSS 1950 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2025 <&mmcc CAMSS 1951 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2026 <&mmcc CAMSS 1952 <&mmcc CAMSS_CSI0_AHB_CLK>,
2027 <&mmcc CAMSS 1953 <&mmcc CAMSS_CSI0_CLK>,
2028 <&mmcc CAMSS 1954 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2029 <&mmcc CAMSS 1955 <&mmcc CAMSS_CSI0PIX_CLK>,
2030 <&mmcc CAMSS 1956 <&mmcc CAMSS_CSI0RDI_CLK>,
2031 <&mmcc CAMSS 1957 <&mmcc CAMSS_CSI1_AHB_CLK>,
2032 <&mmcc CAMSS 1958 <&mmcc CAMSS_CSI1_CLK>,
2033 <&mmcc CAMSS 1959 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2034 <&mmcc CAMSS 1960 <&mmcc CAMSS_CSI1PIX_CLK>,
2035 <&mmcc CAMSS 1961 <&mmcc CAMSS_CSI1RDI_CLK>,
2036 <&mmcc CAMSS 1962 <&mmcc CAMSS_CSI2_AHB_CLK>,
2037 <&mmcc CAMSS 1963 <&mmcc CAMSS_CSI2_CLK>,
2038 <&mmcc CAMSS 1964 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2039 <&mmcc CAMSS 1965 <&mmcc CAMSS_CSI2PIX_CLK>,
2040 <&mmcc CAMSS 1966 <&mmcc CAMSS_CSI2RDI_CLK>,
2041 <&mmcc CAMSS 1967 <&mmcc CAMSS_CSI3_AHB_CLK>,
2042 <&mmcc CAMSS 1968 <&mmcc CAMSS_CSI3_CLK>,
2043 <&mmcc CAMSS 1969 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2044 <&mmcc CAMSS 1970 <&mmcc CAMSS_CSI3PIX_CLK>,
2045 <&mmcc CAMSS 1971 <&mmcc CAMSS_CSI3RDI_CLK>,
2046 <&mmcc CAMSS 1972 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2047 <&mmcc CAMSS 1973 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2048 <&mmcc CAMSS 1974 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2049 <&mmcc CSIPH 1975 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2050 <&mmcc CAMSS 1976 <&mmcc CAMSS_CSI_VFE0_CLK>,
2051 <&mmcc CAMSS 1977 <&mmcc CAMSS_CSI_VFE1_CLK>,
2052 <&mmcc CAMSS 1978 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2053 <&mmcc THROT 1979 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2054 <&mmcc CAMSS 1980 <&mmcc CAMSS_TOP_AHB_CLK>,
2055 <&mmcc CAMSS 1981 <&mmcc CAMSS_VFE0_AHB_CLK>,
2056 <&mmcc CAMSS 1982 <&mmcc CAMSS_VFE0_CLK>,
2057 <&mmcc CAMSS 1983 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2058 <&mmcc CAMSS 1984 <&mmcc CAMSS_VFE1_AHB_CLK>,
2059 <&mmcc CAMSS 1985 <&mmcc CAMSS_VFE1_CLK>,
2060 <&mmcc CAMSS 1986 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2061 <&mmcc CAMSS 1987 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2062 <&mmcc CAMSS 1988 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2063 clock-names = "ahb", 1989 clock-names = "ahb",
2064 "cphy_c 1990 "cphy_csid0",
2065 "cphy_c 1991 "cphy_csid1",
2066 "cphy_c 1992 "cphy_csid2",
2067 "cphy_c 1993 "cphy_csid3",
2068 "csi0_a 1994 "csi0_ahb",
2069 "csi0", 1995 "csi0",
2070 "csi0_p 1996 "csi0_phy",
2071 "csi0_p 1997 "csi0_pix",
2072 "csi0_r 1998 "csi0_rdi",
2073 "csi1_a 1999 "csi1_ahb",
2074 "csi1", 2000 "csi1",
2075 "csi1_p 2001 "csi1_phy",
2076 "csi1_p 2002 "csi1_pix",
2077 "csi1_r 2003 "csi1_rdi",
2078 "csi2_a 2004 "csi2_ahb",
2079 "csi2", 2005 "csi2",
2080 "csi2_p 2006 "csi2_phy",
2081 "csi2_p 2007 "csi2_pix",
2082 "csi2_r 2008 "csi2_rdi",
2083 "csi3_a 2009 "csi3_ahb",
2084 "csi3", 2010 "csi3",
2085 "csi3_p 2011 "csi3_phy",
2086 "csi3_p 2012 "csi3_pix",
2087 "csi3_r 2013 "csi3_rdi",
2088 "csiphy 2014 "csiphy0_timer",
2089 "csiphy 2015 "csiphy1_timer",
2090 "csiphy 2016 "csiphy2_timer",
2091 "csiphy 2017 "csiphy_ahb2crif",
2092 "csi_vf 2018 "csi_vfe0",
2093 "csi_vf 2019 "csi_vfe1",
2094 "ispif_ 2020 "ispif_ahb",
2095 "thrott 2021 "throttle_axi",
2096 "top_ah 2022 "top_ahb",
2097 "vfe0_a 2023 "vfe0_ahb",
2098 "vfe0", 2024 "vfe0",
2099 "vfe0_s 2025 "vfe0_stream",
2100 "vfe1_a 2026 "vfe1_ahb",
2101 "vfe1", 2027 "vfe1",
2102 "vfe1_s 2028 "vfe1_stream",
2103 "vfe_ah 2029 "vfe_ahb",
2104 "vfe_ax 2030 "vfe_axi";
2105 interconnects = <&mno 2031 interconnects = <&mnoc 5 &bimc 5>;
2106 interconnect-names = 2032 interconnect-names = "vfe-mem";
2107 iommus = <&mmss_smmu 2033 iommus = <&mmss_smmu 0xc00>,
2108 <&mmss_smmu 2034 <&mmss_smmu 0xc01>,
2109 <&mmss_smmu 2035 <&mmss_smmu 0xc02>,
2110 <&mmss_smmu 2036 <&mmss_smmu 0xc03>;
2111 power-domains = <&mmc 2037 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2112 <&mmc 2038 <&mmcc CAMSS_VFE1_GDSC>;
2113 status = "disabled"; 2039 status = "disabled";
2114 2040
2115 ports { 2041 ports {
2116 #address-cell 2042 #address-cells = <1>;
2117 #size-cells = 2043 #size-cells = <0>;
2118 }; 2044 };
2119 }; 2045 };
2120 2046
2121 cci: cci@ca0c000 { 2047 cci: cci@ca0c000 {
2122 compatible = "qcom,ms 2048 compatible = "qcom,msm8996-cci";
2123 #address-cells = <1>; 2049 #address-cells = <1>;
2124 #size-cells = <0>; 2050 #size-cells = <0>;
2125 reg = <0x0ca0c000 0x1 2051 reg = <0x0ca0c000 0x1000>;
2126 interrupts = <GIC_SPI 2052 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2127 2053
2128 assigned-clocks = <&m 2054 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2129 <&m 2055 <&mmcc CAMSS_CCI_CLK>;
2130 assigned-clock-rates 2056 assigned-clock-rates = <80800000>, <37500000>;
2131 clocks = <&mmcc CAMSS 2057 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2132 <&mmcc CAMSS 2058 <&mmcc CAMSS_CCI_AHB_CLK>,
2133 <&mmcc CAMSS 2059 <&mmcc CAMSS_CCI_CLK>,
2134 <&mmcc CAMSS 2060 <&mmcc CAMSS_AHB_CLK>;
2135 clock-names = "camss_ 2061 clock-names = "camss_top_ahb",
2136 "cci_ah 2062 "cci_ahb",
2137 "cci", 2063 "cci",
2138 "camss_ 2064 "camss_ahb";
2139 2065
2140 pinctrl-names = "defa 2066 pinctrl-names = "default";
2141 pinctrl-0 = <&cci0_de 2067 pinctrl-0 = <&cci0_default &cci1_default>;
2142 power-domains = <&mmc 2068 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2143 status = "disabled"; 2069 status = "disabled";
2144 2070
2145 cci_i2c0: i2c-bus@0 { 2071 cci_i2c0: i2c-bus@0 {
2146 reg = <0>; 2072 reg = <0>;
2147 clock-frequen 2073 clock-frequency = <400000>;
2148 #address-cell 2074 #address-cells = <1>;
2149 #size-cells = 2075 #size-cells = <0>;
2150 }; 2076 };
2151 2077
2152 cci_i2c1: i2c-bus@1 { 2078 cci_i2c1: i2c-bus@1 {
2153 reg = <1>; 2079 reg = <1>;
2154 clock-frequen 2080 clock-frequency = <400000>;
2155 #address-cell 2081 #address-cells = <1>;
2156 #size-cells = 2082 #size-cells = <0>;
2157 }; 2083 };
2158 }; 2084 };
2159 2085
2160 venus: video-codec@cc00000 { 2086 venus: video-codec@cc00000 {
2161 compatible = "qcom,sd 2087 compatible = "qcom,sdm660-venus";
2162 reg = <0x0cc00000 0xf 2088 reg = <0x0cc00000 0xff000>;
2163 clocks = <&mmcc VIDEO 2089 clocks = <&mmcc VIDEO_CORE_CLK>,
2164 <&mmcc VIDEO 2090 <&mmcc VIDEO_AHB_CLK>,
2165 <&mmcc VIDEO 2091 <&mmcc VIDEO_AXI_CLK>,
2166 <&mmcc THROT 2092 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2167 clock-names = "core", 2093 clock-names = "core", "iface", "bus", "bus_throttle";
2168 interconnects = <&gno 2094 interconnects = <&gnoc 0 &mnoc 13>,
2169 <&mno 2095 <&mnoc 4 &bimc 5>;
2170 interconnect-names = 2096 interconnect-names = "cpu-cfg", "video-mem";
2171 interrupts = <GIC_SPI 2097 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&mmss_smmu 2098 iommus = <&mmss_smmu 0x400>,
2173 <&mmss_smmu 2099 <&mmss_smmu 0x401>,
2174 <&mmss_smmu 2100 <&mmss_smmu 0x40a>,
2175 <&mmss_smmu 2101 <&mmss_smmu 0x407>,
2176 <&mmss_smmu 2102 <&mmss_smmu 0x40e>,
2177 <&mmss_smmu 2103 <&mmss_smmu 0x40f>,
2178 <&mmss_smmu 2104 <&mmss_smmu 0x408>,
2179 <&mmss_smmu 2105 <&mmss_smmu 0x409>,
2180 <&mmss_smmu 2106 <&mmss_smmu 0x40b>,
2181 <&mmss_smmu 2107 <&mmss_smmu 0x40c>,
2182 <&mmss_smmu 2108 <&mmss_smmu 0x40d>,
2183 <&mmss_smmu 2109 <&mmss_smmu 0x410>,
2184 <&mmss_smmu 2110 <&mmss_smmu 0x421>,
2185 <&mmss_smmu 2111 <&mmss_smmu 0x428>,
2186 <&mmss_smmu 2112 <&mmss_smmu 0x429>,
2187 <&mmss_smmu 2113 <&mmss_smmu 0x42b>,
2188 <&mmss_smmu 2114 <&mmss_smmu 0x42c>,
2189 <&mmss_smmu 2115 <&mmss_smmu 0x42d>,
2190 <&mmss_smmu 2116 <&mmss_smmu 0x411>,
2191 <&mmss_smmu 2117 <&mmss_smmu 0x431>;
2192 memory-region = <&ven 2118 memory-region = <&venus_region>;
2193 power-domains = <&mmc 2119 power-domains = <&mmcc VENUS_GDSC>;
2194 status = "disabled"; 2120 status = "disabled";
2195 2121
2196 video-decoder { 2122 video-decoder {
2197 compatible = 2123 compatible = "venus-decoder";
2198 clocks = <&mm 2124 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2199 clock-names = 2125 clock-names = "vcodec0_core";
2200 power-domains 2126 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2201 }; 2127 };
2202 2128
2203 video-encoder { 2129 video-encoder {
2204 compatible = 2130 compatible = "venus-encoder";
2205 clocks = <&mm 2131 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2206 clock-names = 2132 clock-names = "vcodec0_core";
2207 power-domains 2133 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2208 }; 2134 };
2209 }; 2135 };
2210 2136
2211 mmss_smmu: iommu@cd00000 { 2137 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sd 2138 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2213 reg = <0x0cd00000 0x4 2139 reg = <0x0cd00000 0x40000>;
2214 2140
2215 clocks = <&mmcc MNOC_ 2141 clocks = <&mmcc MNOC_AHB_CLK>,
2216 <&mmcc BIMC_ 2142 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2143 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2217 <&mmcc BIMC_ 2144 <&mmcc BIMC_SMMU_AXI_CLK>;
2218 clock-names = "iface- 2145 clock-names = "iface-mm", "iface-smmu",
2219 "bus-sm !! 2146 "bus-mm", "bus-smmu";
2220 #global-interrupts = 2147 #global-interrupts = <2>;
2221 #iommu-cells = <1>; 2148 #iommu-cells = <1>;
2222 2149
2223 interrupts = 2150 interrupts =
2224 <GIC_SPI 229 2151 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 231 2152 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2226 2153
2227 <GIC_SPI 263 2154 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 266 2155 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 267 2156 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 268 2157 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 244 2158 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 245 2159 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 247 2160 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 248 2161 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 249 2162 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 250 2163 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 251 2164 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 252 2165 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 253 2166 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 254 2167 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 255 2168 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 256 2169 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 260 2170 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 261 2171 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 262 2172 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 272 2173 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 273 2174 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 274 2175 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 275 2176 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 276 2177 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2251 2178
2252 status = "disabled"; 2179 status = "disabled";
2253 }; 2180 };
2254 2181
2255 adsp_pil: remoteproc@15700000 2182 adsp_pil: remoteproc@15700000 {
2256 compatible = "qcom,sd 2183 compatible = "qcom,sdm660-adsp-pas";
2257 reg = <0x15700000 0x4 2184 reg = <0x15700000 0x4040>;
2258 2185
2259 interrupts-extended = 2186 interrupts-extended =
2260 <&intc GIC_SP 2187 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2261 <&adsp_smp2p_ 2188 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2262 <&adsp_smp2p_ 2189 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2263 <&adsp_smp2p_ 2190 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2264 <&adsp_smp2p_ 2191 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2265 interrupt-names = "wd 2192 interrupt-names = "wdog", "fatal", "ready",
2266 "ha 2193 "handover", "stop-ack";
2267 2194
2268 clocks = <&rpmcc RPM_ 2195 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2269 clock-names = "xo"; 2196 clock-names = "xo";
2270 2197
2271 memory-region = <&ads 2198 memory-region = <&adsp_region>;
2272 power-domains = <&rpm 2199 power-domains = <&rpmpd SDM660_VDDCX>;
2273 power-domain-names = 2200 power-domain-names = "cx";
2274 2201
2275 qcom,smem-states = <& 2202 qcom,smem-states = <&adsp_smp2p_out 0>;
2276 qcom,smem-state-names 2203 qcom,smem-state-names = "stop";
2277 2204
2278 glink-edge { 2205 glink-edge {
2279 interrupts = 2206 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2280 2207
2281 label = "lpas 2208 label = "lpass";
2282 mboxes = <&ap 2209 mboxes = <&apcs_glb 9>;
2283 qcom,remote-p 2210 qcom,remote-pid = <2>;
2284 2211
2285 apr { 2212 apr {
2286 compa 2213 compatible = "qcom,apr-v2";
2287 qcom, 2214 qcom,glink-channels = "apr_audio_svc";
2288 qcom, 2215 qcom,domain = <APR_DOMAIN_ADSP>;
2289 #addr 2216 #address-cells = <1>;
2290 #size 2217 #size-cells = <0>;
2291 2218
2292 servi 2219 service@3 {
2293 2220 reg = <APR_SVC_ADSP_CORE>;
2294 2221 compatible = "qcom,q6core";
2295 }; 2222 };
2296 2223
2297 q6afe 2224 q6afe: service@4 {
2298 2225 compatible = "qcom,q6afe";
2299 2226 reg = <APR_SVC_AFE>;
2300 2227 q6afedai: dais {
2301 2228 compatible = "qcom,q6afe-dais";
2302 2229 #address-cells = <1>;
2303 2230 #size-cells = <0>;
2304 2231 #sound-dai-cells = <1>;
2305 2232 };
2306 }; 2233 };
2307 2234
2308 q6asm 2235 q6asm: service@7 {
2309 2236 compatible = "qcom,q6asm";
2310 2237 reg = <APR_SVC_ASM>;
2311 2238 q6asmdai: dais {
2312 2239 compatible = "qcom,q6asm-dais";
2313 2240 #address-cells = <1>;
2314 2241 #size-cells = <0>;
2315 2242 #sound-dai-cells = <1>;
2316 2243 iommus = <&lpass_smmu 1>;
2317 2244 };
2318 }; 2245 };
2319 2246
2320 q6adm 2247 q6adm: service@8 {
2321 2248 compatible = "qcom,q6adm";
2322 2249 reg = <APR_SVC_ADM>;
2323 2250 q6routing: routing {
2324 2251 compatible = "qcom,q6adm-routing";
2325 2252 #sound-dai-cells = <0>;
2326 2253 };
2327 }; 2254 };
2328 }; 2255 };
2329 }; 2256 };
2330 }; 2257 };
2331 2258
2332 gnoc: interconnect@17900000 { 2259 gnoc: interconnect@17900000 {
2333 compatible = "qcom,sd 2260 compatible = "qcom,sdm660-gnoc";
2334 reg = <0x17900000 0xe 2261 reg = <0x17900000 0xe000>;
2335 #interconnect-cells = 2262 #interconnect-cells = <1>;
>> 2263 /*
>> 2264 * This one apparently features no clocks,
>> 2265 * so let's not mess with the driver needlessly
>> 2266 */
>> 2267 clock-names = "bus", "bus_a";
>> 2268 clocks = <&xo_board>, <&xo_board>;
2336 }; 2269 };
2337 2270
2338 apcs_glb: mailbox@17911000 { 2271 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sd 2272 compatible = "qcom,sdm660-apcs-hmss-global",
2340 "qcom,ms 2273 "qcom,msm8994-apcs-kpss-global";
2341 reg = <0x17911000 0x1 2274 reg = <0x17911000 0x1000>;
2342 2275
2343 #mbox-cells = <1>; 2276 #mbox-cells = <1>;
2344 }; 2277 };
2345 2278
2346 timer@17920000 { 2279 timer@17920000 {
2347 #address-cells = <1>; 2280 #address-cells = <1>;
2348 #size-cells = <1>; 2281 #size-cells = <1>;
2349 ranges; 2282 ranges;
2350 compatible = "arm,arm 2283 compatible = "arm,armv7-timer-mem";
2351 reg = <0x17920000 0x1 2284 reg = <0x17920000 0x1000>;
2352 clock-frequency = <19 2285 clock-frequency = <19200000>;
2353 2286
2354 frame@17921000 { 2287 frame@17921000 {
2355 frame-number 2288 frame-number = <0>;
2356 interrupts = !! 2289 interrupts = <0 8 0x4>,
2357 !! 2290 <0 7 0x4>;
2358 reg = <0x1792 2291 reg = <0x17921000 0x1000>,
2359 <0x17 2292 <0x17922000 0x1000>;
2360 }; 2293 };
2361 2294
2362 frame@17923000 { 2295 frame@17923000 {
2363 frame-number 2296 frame-number = <1>;
2364 interrupts = !! 2297 interrupts = <0 9 0x4>;
2365 reg = <0x1792 2298 reg = <0x17923000 0x1000>;
2366 status = "dis 2299 status = "disabled";
2367 }; 2300 };
2368 2301
2369 frame@17924000 { 2302 frame@17924000 {
2370 frame-number 2303 frame-number = <2>;
2371 interrupts = !! 2304 interrupts = <0 10 0x4>;
2372 reg = <0x1792 2305 reg = <0x17924000 0x1000>;
2373 status = "dis 2306 status = "disabled";
2374 }; 2307 };
2375 2308
2376 frame@17925000 { 2309 frame@17925000 {
2377 frame-number 2310 frame-number = <3>;
2378 interrupts = !! 2311 interrupts = <0 11 0x4>;
2379 reg = <0x1792 2312 reg = <0x17925000 0x1000>;
2380 status = "dis 2313 status = "disabled";
2381 }; 2314 };
2382 2315
2383 frame@17926000 { 2316 frame@17926000 {
2384 frame-number 2317 frame-number = <4>;
2385 interrupts = !! 2318 interrupts = <0 12 0x4>;
2386 reg = <0x1792 2319 reg = <0x17926000 0x1000>;
2387 status = "dis 2320 status = "disabled";
2388 }; 2321 };
2389 2322
2390 frame@17927000 { 2323 frame@17927000 {
2391 frame-number 2324 frame-number = <5>;
2392 interrupts = !! 2325 interrupts = <0 13 0x4>;
2393 reg = <0x1792 2326 reg = <0x17927000 0x1000>;
2394 status = "dis 2327 status = "disabled";
2395 }; 2328 };
2396 2329
2397 frame@17928000 { 2330 frame@17928000 {
2398 frame-number 2331 frame-number = <6>;
2399 interrupts = !! 2332 interrupts = <0 14 0x4>;
2400 reg = <0x1792 2333 reg = <0x17928000 0x1000>;
2401 status = "dis 2334 status = "disabled";
2402 }; 2335 };
2403 }; 2336 };
2404 2337
2405 intc: interrupt-controller@17 2338 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic 2339 compatible = "arm,gic-v3";
2407 reg = <0x17a00000 0x1 2340 reg = <0x17a00000 0x10000>, /* GICD */
2408 <0x17b00000 2341 <0x17b00000 0x100000>; /* GICR * 8 */
2409 #interrupt-cells = <3 2342 #interrupt-cells = <3>;
2410 #address-cells = <1>; 2343 #address-cells = <1>;
2411 #size-cells = <1>; 2344 #size-cells = <1>;
2412 ranges; 2345 ranges;
2413 interrupt-controller; 2346 interrupt-controller;
2414 #redistributor-region 2347 #redistributor-regions = <1>;
2415 redistributor-stride 2348 redistributor-stride = <0x0 0x20000>;
2416 interrupts = <GIC_PPI 2349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2417 }; 2350 };
2418 }; 2351 };
2419 2352
2420 sound: sound { 2353 sound: sound {
2421 }; 2354 };
2422 2355
2423 thermal-zones { 2356 thermal-zones {
2424 aoss-thermal { 2357 aoss-thermal {
2425 polling-delay-passive 2358 polling-delay-passive = <250>;
>> 2359 polling-delay = <1000>;
2426 2360
2427 thermal-sensors = <&t 2361 thermal-sensors = <&tsens 0>;
2428 2362
2429 trips { 2363 trips {
2430 aoss_alert0: 2364 aoss_alert0: trip-point0 {
2431 tempe 2365 temperature = <105000>;
2432 hyste 2366 hysteresis = <1000>;
2433 type 2367 type = "hot";
2434 }; 2368 };
2435 }; 2369 };
2436 }; 2370 };
2437 2371
2438 cpuss0-thermal { 2372 cpuss0-thermal {
2439 polling-delay-passive 2373 polling-delay-passive = <250>;
>> 2374 polling-delay = <1000>;
2440 2375
2441 thermal-sensors = <&t 2376 thermal-sensors = <&tsens 1>;
2442 2377
2443 trips { 2378 trips {
2444 cpuss0_alert0 2379 cpuss0_alert0: trip-point0 {
2445 tempe 2380 temperature = <125000>;
2446 hyste 2381 hysteresis = <1000>;
2447 type 2382 type = "hot";
2448 }; 2383 };
2449 }; 2384 };
2450 }; 2385 };
2451 2386
2452 cpuss1-thermal { 2387 cpuss1-thermal {
2453 polling-delay-passive 2388 polling-delay-passive = <250>;
>> 2389 polling-delay = <1000>;
2454 2390
2455 thermal-sensors = <&t 2391 thermal-sensors = <&tsens 2>;
2456 2392
2457 trips { 2393 trips {
2458 cpuss1_alert0 2394 cpuss1_alert0: trip-point0 {
2459 tempe 2395 temperature = <125000>;
2460 hyste 2396 hysteresis = <1000>;
2461 type 2397 type = "hot";
2462 }; 2398 };
2463 }; 2399 };
2464 }; 2400 };
2465 2401
2466 cpu0-thermal { 2402 cpu0-thermal {
2467 polling-delay-passive 2403 polling-delay-passive = <250>;
>> 2404 polling-delay = <1000>;
2468 2405
2469 thermal-sensors = <&t 2406 thermal-sensors = <&tsens 3>;
2470 2407
2471 trips { 2408 trips {
2472 cpu0_alert0: 2409 cpu0_alert0: trip-point0 {
2473 tempe 2410 temperature = <70000>;
2474 hyste 2411 hysteresis = <1000>;
2475 type 2412 type = "passive";
2476 }; 2413 };
2477 2414
2478 cpu0_crit: cp 2415 cpu0_crit: cpu-crit {
2479 tempe 2416 temperature = <110000>;
2480 hyste 2417 hysteresis = <1000>;
2481 type 2418 type = "critical";
2482 }; 2419 };
2483 }; 2420 };
2484 }; 2421 };
2485 2422
2486 cpu1-thermal { 2423 cpu1-thermal {
2487 polling-delay-passive 2424 polling-delay-passive = <250>;
>> 2425 polling-delay = <1000>;
2488 2426
2489 thermal-sensors = <&t 2427 thermal-sensors = <&tsens 4>;
2490 2428
2491 trips { 2429 trips {
2492 cpu1_alert0: 2430 cpu1_alert0: trip-point0 {
2493 tempe 2431 temperature = <70000>;
2494 hyste 2432 hysteresis = <1000>;
2495 type 2433 type = "passive";
2496 }; 2434 };
2497 2435
2498 cpu1_crit: cp 2436 cpu1_crit: cpu-crit {
2499 tempe 2437 temperature = <110000>;
2500 hyste 2438 hysteresis = <1000>;
2501 type 2439 type = "critical";
2502 }; 2440 };
2503 }; 2441 };
2504 }; 2442 };
2505 2443
2506 cpu2-thermal { 2444 cpu2-thermal {
2507 polling-delay-passive 2445 polling-delay-passive = <250>;
>> 2446 polling-delay = <1000>;
2508 2447
2509 thermal-sensors = <&t 2448 thermal-sensors = <&tsens 5>;
2510 2449
2511 trips { 2450 trips {
2512 cpu2_alert0: 2451 cpu2_alert0: trip-point0 {
2513 tempe 2452 temperature = <70000>;
2514 hyste 2453 hysteresis = <1000>;
2515 type 2454 type = "passive";
2516 }; 2455 };
2517 2456
2518 cpu2_crit: cp 2457 cpu2_crit: cpu-crit {
2519 tempe 2458 temperature = <110000>;
2520 hyste 2459 hysteresis = <1000>;
2521 type 2460 type = "critical";
2522 }; 2461 };
2523 }; 2462 };
2524 }; 2463 };
2525 2464
2526 cpu3-thermal { 2465 cpu3-thermal {
2527 polling-delay-passive 2466 polling-delay-passive = <250>;
>> 2467 polling-delay = <1000>;
2528 2468
2529 thermal-sensors = <&t 2469 thermal-sensors = <&tsens 6>;
2530 2470
2531 trips { 2471 trips {
2532 cpu3_alert0: 2472 cpu3_alert0: trip-point0 {
2533 tempe 2473 temperature = <70000>;
2534 hyste 2474 hysteresis = <1000>;
2535 type 2475 type = "passive";
2536 }; 2476 };
2537 2477
2538 cpu3_crit: cp 2478 cpu3_crit: cpu-crit {
2539 tempe 2479 temperature = <110000>;
2540 hyste 2480 hysteresis = <1000>;
2541 type 2481 type = "critical";
2542 }; 2482 };
2543 }; 2483 };
2544 }; 2484 };
2545 2485
2546 /* 2486 /*
2547 * According to what downstre 2487 * According to what downstream DTS says,
2548 * the entire power efficient 2488 * the entire power efficient cluster has
2549 * only a single thermal sens 2489 * only a single thermal sensor.
2550 */ 2490 */
2551 2491
2552 pwr-cluster-thermal { 2492 pwr-cluster-thermal {
2553 polling-delay-passive 2493 polling-delay-passive = <250>;
>> 2494 polling-delay = <1000>;
2554 2495
2555 thermal-sensors = <&t 2496 thermal-sensors = <&tsens 7>;
2556 2497
2557 trips { 2498 trips {
2558 pwr_cluster_a 2499 pwr_cluster_alert0: trip-point0 {
2559 tempe 2500 temperature = <70000>;
2560 hyste 2501 hysteresis = <1000>;
2561 type 2502 type = "passive";
2562 }; 2503 };
2563 2504
2564 pwr_cluster_c 2505 pwr_cluster_crit: cpu-crit {
2565 tempe 2506 temperature = <110000>;
2566 hyste 2507 hysteresis = <1000>;
2567 type 2508 type = "critical";
2568 }; 2509 };
2569 }; 2510 };
2570 }; 2511 };
2571 2512
2572 gpu-thermal { 2513 gpu-thermal {
2573 polling-delay-passive 2514 polling-delay-passive = <250>;
>> 2515 polling-delay = <1000>;
2574 2516
2575 thermal-sensors = <&t 2517 thermal-sensors = <&tsens 8>;
2576 2518
2577 cooling-maps { <<
2578 map0 { <<
2579 trip <<
2580 cooli <<
2581 }; <<
2582 }; <<
2583 <<
2584 trips { 2519 trips {
2585 gpu_alert0: t 2520 gpu_alert0: trip-point0 {
2586 tempe <<
2587 hyste <<
2588 type <<
2589 }; <<
2590 <<
2591 trip-point1 { <<
2592 tempe 2521 temperature = <90000>;
2593 hyste 2522 hysteresis = <1000>;
2594 type 2523 type = "hot";
2595 }; 2524 };
2596 <<
2597 trip-point2 { <<
2598 tempe <<
2599 hyste <<
2600 type <<
2601 }; <<
2602 }; 2525 };
2603 }; 2526 };
2604 }; 2527 };
2605 2528
2606 timer { 2529 timer {
2607 compatible = "arm,armv8-timer 2530 compatible = "arm,armv8-timer";
2608 interrupts = <GIC_PPI 1 (GIC_ !! 2531 interrupts = <GIC_PPI 1 0xf08>,
2609 <GIC_PPI 2 (GIC_ !! 2532 <GIC_PPI 2 0xf08>,
2610 <GIC_PPI 3 (GIC_ !! 2533 <GIC_PPI 3 0xf08>,
2611 <GIC_PPI 0 (GIC_ !! 2534 <GIC_PPI 0 0xf08>;
2612 }; 2535 };
2613 }; 2536 };
2614 2537
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