1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybc 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Re< 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660. 8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h 9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h> <<
12 #include <dt-bindings/interconnect/qcom,sdm660 11 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 12 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h> 13 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/soc/qcom,apr.h> 15 #include <dt-bindings/soc/qcom,apr.h>
18 16
19 / { 17 / {
20 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
21 19
22 #address-cells = <2>; 20 #address-cells = <2>;
23 #size-cells = <2>; 21 #size-cells = <2>;
24 22
25 aliases { 23 aliases {
26 mmc1 = &sdhc_1; 24 mmc1 = &sdhc_1;
27 mmc2 = &sdhc_2; 25 mmc2 = &sdhc_2;
28 }; 26 };
29 27
30 chosen { }; 28 chosen { };
31 29
32 clocks { 30 clocks {
33 xo_board: xo-board { 31 xo_board: xo-board {
34 compatible = "fixed-cl 32 compatible = "fixed-clock";
35 #clock-cells = <0>; 33 #clock-cells = <0>;
36 clock-frequency = <192 34 clock-frequency = <19200000>;
37 clock-output-names = " 35 clock-output-names = "xo_board";
38 }; 36 };
39 37
40 sleep_clk: sleep-clk { 38 sleep_clk: sleep-clk {
41 compatible = "fixed-cl 39 compatible = "fixed-clock";
42 #clock-cells = <0>; 40 #clock-cells = <0>;
43 clock-frequency = <327 41 clock-frequency = <32764>;
44 clock-output-names = " 42 clock-output-names = "sleep_clk";
45 }; 43 };
46 }; 44 };
47 45
48 cpus { 46 cpus {
49 #address-cells = <2>; 47 #address-cells = <2>;
50 #size-cells = <0>; 48 #size-cells = <0>;
51 49
52 CPU0: cpu@100 { 50 CPU0: cpu@100 {
53 device_type = "cpu"; 51 device_type = "cpu";
54 compatible = "arm,cort 52 compatible = "arm,cortex-a53";
55 reg = <0x0 0x100>; 53 reg = <0x0 0x100>;
56 enable-method = "psci" 54 enable-method = "psci";
57 cpu-idle-states = <&PE 55 cpu-idle-states = <&PERF_CPU_SLEEP_0
58 56 &PERF_CPU_SLEEP_1
59 57 &PERF_CLUSTER_SLEEP_0
60 58 &PERF_CLUSTER_SLEEP_1
61 59 &PERF_CLUSTER_SLEEP_2>;
62 capacity-dmips-mhz = < 60 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>; 61 #cooling-cells = <2>;
64 next-level-cache = <&L 62 next-level-cache = <&L2_1>;
65 L2_1: l2-cache { 63 L2_1: l2-cache {
66 compatible = " 64 compatible = "cache";
67 cache-level = 65 cache-level = <2>;
68 cache-unified; 66 cache-unified;
69 }; 67 };
70 }; 68 };
71 69
72 CPU1: cpu@101 { 70 CPU1: cpu@101 {
73 device_type = "cpu"; 71 device_type = "cpu";
74 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
75 reg = <0x0 0x101>; 73 reg = <0x0 0x101>;
76 enable-method = "psci" 74 enable-method = "psci";
77 cpu-idle-states = <&PE 75 cpu-idle-states = <&PERF_CPU_SLEEP_0
78 76 &PERF_CPU_SLEEP_1
79 77 &PERF_CLUSTER_SLEEP_0
80 78 &PERF_CLUSTER_SLEEP_1
81 79 &PERF_CLUSTER_SLEEP_2>;
82 capacity-dmips-mhz = < 80 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>; 81 #cooling-cells = <2>;
84 next-level-cache = <&L 82 next-level-cache = <&L2_1>;
85 }; 83 };
86 84
87 CPU2: cpu@102 { 85 CPU2: cpu@102 {
88 device_type = "cpu"; 86 device_type = "cpu";
89 compatible = "arm,cort 87 compatible = "arm,cortex-a53";
90 reg = <0x0 0x102>; 88 reg = <0x0 0x102>;
91 enable-method = "psci" 89 enable-method = "psci";
92 cpu-idle-states = <&PE 90 cpu-idle-states = <&PERF_CPU_SLEEP_0
93 91 &PERF_CPU_SLEEP_1
94 92 &PERF_CLUSTER_SLEEP_0
95 93 &PERF_CLUSTER_SLEEP_1
96 94 &PERF_CLUSTER_SLEEP_2>;
97 capacity-dmips-mhz = < 95 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>; 96 #cooling-cells = <2>;
99 next-level-cache = <&L 97 next-level-cache = <&L2_1>;
100 }; 98 };
101 99
102 CPU3: cpu@103 { 100 CPU3: cpu@103 {
103 device_type = "cpu"; 101 device_type = "cpu";
104 compatible = "arm,cort 102 compatible = "arm,cortex-a53";
105 reg = <0x0 0x103>; 103 reg = <0x0 0x103>;
106 enable-method = "psci" 104 enable-method = "psci";
107 cpu-idle-states = <&PE 105 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 106 &PERF_CPU_SLEEP_1
109 107 &PERF_CLUSTER_SLEEP_0
110 108 &PERF_CLUSTER_SLEEP_1
111 109 &PERF_CLUSTER_SLEEP_2>;
112 capacity-dmips-mhz = < 110 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>; 111 #cooling-cells = <2>;
114 next-level-cache = <&L 112 next-level-cache = <&L2_1>;
115 }; 113 };
116 114
117 CPU4: cpu@0 { 115 CPU4: cpu@0 {
118 device_type = "cpu"; 116 device_type = "cpu";
119 compatible = "arm,cort 117 compatible = "arm,cortex-a53";
120 reg = <0x0 0x0>; 118 reg = <0x0 0x0>;
121 enable-method = "psci" 119 enable-method = "psci";
122 cpu-idle-states = <&PW 120 cpu-idle-states = <&PWR_CPU_SLEEP_0
123 121 &PWR_CPU_SLEEP_1
124 122 &PWR_CLUSTER_SLEEP_0
125 123 &PWR_CLUSTER_SLEEP_1
126 124 &PWR_CLUSTER_SLEEP_2>;
127 capacity-dmips-mhz = < 125 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>; 126 #cooling-cells = <2>;
129 next-level-cache = <&L 127 next-level-cache = <&L2_0>;
130 L2_0: l2-cache { 128 L2_0: l2-cache {
131 compatible = " 129 compatible = "cache";
132 cache-level = 130 cache-level = <2>;
133 cache-unified; 131 cache-unified;
134 }; 132 };
135 }; 133 };
136 134
137 CPU5: cpu@1 { 135 CPU5: cpu@1 {
138 device_type = "cpu"; 136 device_type = "cpu";
139 compatible = "arm,cort 137 compatible = "arm,cortex-a53";
140 reg = <0x0 0x1>; 138 reg = <0x0 0x1>;
141 enable-method = "psci" 139 enable-method = "psci";
142 cpu-idle-states = <&PW 140 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 141 &PWR_CPU_SLEEP_1
144 142 &PWR_CLUSTER_SLEEP_0
145 143 &PWR_CLUSTER_SLEEP_1
146 144 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = < 145 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>; 146 #cooling-cells = <2>;
149 next-level-cache = <&L 147 next-level-cache = <&L2_0>;
150 }; 148 };
151 149
152 CPU6: cpu@2 { 150 CPU6: cpu@2 {
153 device_type = "cpu"; 151 device_type = "cpu";
154 compatible = "arm,cort 152 compatible = "arm,cortex-a53";
155 reg = <0x0 0x2>; 153 reg = <0x0 0x2>;
156 enable-method = "psci" 154 enable-method = "psci";
157 cpu-idle-states = <&PW 155 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 156 &PWR_CPU_SLEEP_1
159 157 &PWR_CLUSTER_SLEEP_0
160 158 &PWR_CLUSTER_SLEEP_1
161 159 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>; 161 #cooling-cells = <2>;
164 next-level-cache = <&L 162 next-level-cache = <&L2_0>;
165 }; 163 };
166 164
167 CPU7: cpu@3 { 165 CPU7: cpu@3 {
168 device_type = "cpu"; 166 device_type = "cpu";
169 compatible = "arm,cort 167 compatible = "arm,cortex-a53";
170 reg = <0x0 0x3>; 168 reg = <0x0 0x3>;
171 enable-method = "psci" 169 enable-method = "psci";
172 cpu-idle-states = <&PW 170 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 171 &PWR_CPU_SLEEP_1
174 172 &PWR_CLUSTER_SLEEP_0
175 173 &PWR_CLUSTER_SLEEP_1
176 174 &PWR_CLUSTER_SLEEP_2>;
177 capacity-dmips-mhz = < 175 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>; 176 #cooling-cells = <2>;
179 next-level-cache = <&L 177 next-level-cache = <&L2_0>;
180 }; 178 };
181 179
182 cpu-map { 180 cpu-map {
183 cluster0 { 181 cluster0 {
184 core0 { 182 core0 {
185 cpu = 183 cpu = <&CPU4>;
186 }; 184 };
187 185
188 core1 { 186 core1 {
189 cpu = 187 cpu = <&CPU5>;
190 }; 188 };
191 189
192 core2 { 190 core2 {
193 cpu = 191 cpu = <&CPU6>;
194 }; 192 };
195 193
196 core3 { 194 core3 {
197 cpu = 195 cpu = <&CPU7>;
198 }; 196 };
199 }; 197 };
200 198
201 cluster1 { 199 cluster1 {
202 core0 { 200 core0 {
203 cpu = 201 cpu = <&CPU0>;
204 }; 202 };
205 203
206 core1 { 204 core1 {
207 cpu = 205 cpu = <&CPU1>;
208 }; 206 };
209 207
210 core2 { 208 core2 {
211 cpu = 209 cpu = <&CPU2>;
212 }; 210 };
213 211
214 core3 { 212 core3 {
215 cpu = 213 cpu = <&CPU3>;
216 }; 214 };
217 }; 215 };
218 }; 216 };
219 217
220 idle-states { 218 idle-states {
221 entry-method = "psci"; 219 entry-method = "psci";
222 220
223 PWR_CPU_SLEEP_0: cpu-s 221 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = " 222 compatible = "arm,idle-state";
225 idle-state-nam 223 idle-state-name = "pwr-retention";
226 arm,psci-suspe 224 arm,psci-suspend-param = <0x40000002>;
227 entry-latency- 225 entry-latency-us = <338>;
228 exit-latency-u 226 exit-latency-us = <423>;
229 min-residency- 227 min-residency-us = <200>;
230 }; 228 };
231 229
232 PWR_CPU_SLEEP_1: cpu-s 230 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = " 231 compatible = "arm,idle-state";
234 idle-state-nam 232 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspe 233 arm,psci-suspend-param = <0x40000003>;
236 entry-latency- 234 entry-latency-us = <515>;
237 exit-latency-u 235 exit-latency-us = <1821>;
238 min-residency- 236 min-residency-us = <1000>;
239 local-timer-st 237 local-timer-stop;
240 }; 238 };
241 239
242 PERF_CPU_SLEEP_0: cpu- 240 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = " 241 compatible = "arm,idle-state";
244 idle-state-nam 242 idle-state-name = "perf-retention";
245 arm,psci-suspe 243 arm,psci-suspend-param = <0x40000002>;
246 entry-latency- 244 entry-latency-us = <154>;
247 exit-latency-u 245 exit-latency-us = <87>;
248 min-residency- 246 min-residency-us = <200>;
249 }; 247 };
250 248
251 PERF_CPU_SLEEP_1: cpu- 249 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = " 250 compatible = "arm,idle-state";
253 idle-state-nam 251 idle-state-name = "perf-power-collapse";
254 arm,psci-suspe 252 arm,psci-suspend-param = <0x40000003>;
255 entry-latency- 253 entry-latency-us = <262>;
256 exit-latency-u 254 exit-latency-us = <301>;
257 min-residency- 255 min-residency-us = <1000>;
258 local-timer-st 256 local-timer-stop;
259 }; 257 };
260 258
261 PWR_CLUSTER_SLEEP_0: c 259 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = " 260 compatible = "arm,idle-state";
263 idle-state-nam 261 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspe 262 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency- 263 entry-latency-us = <284>;
266 exit-latency-u 264 exit-latency-us = <384>;
267 min-residency- 265 min-residency-us = <9987>;
268 local-timer-st 266 local-timer-stop;
269 }; 267 };
270 268
271 PWR_CLUSTER_SLEEP_1: c 269 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = " 270 compatible = "arm,idle-state";
273 idle-state-nam 271 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspe 272 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency- 273 entry-latency-us = <338>;
276 exit-latency-u 274 exit-latency-us = <423>;
277 min-residency- 275 min-residency-us = <9987>;
278 local-timer-st 276 local-timer-stop;
279 }; 277 };
280 278
281 PWR_CLUSTER_SLEEP_2: c 279 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = " 280 compatible = "arm,idle-state";
283 idle-state-nam 281 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspe 282 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency- 283 entry-latency-us = <515>;
286 exit-latency-u 284 exit-latency-us = <1821>;
287 min-residency- 285 min-residency-us = <9987>;
288 local-timer-st 286 local-timer-stop;
289 }; 287 };
290 288
291 PERF_CLUSTER_SLEEP_0: 289 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = " 290 compatible = "arm,idle-state";
293 idle-state-nam 291 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspe 292 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency- 293 entry-latency-us = <272>;
296 exit-latency-u 294 exit-latency-us = <329>;
297 min-residency- 295 min-residency-us = <9987>;
298 local-timer-st 296 local-timer-stop;
299 }; 297 };
300 298
301 PERF_CLUSTER_SLEEP_1: 299 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = " 300 compatible = "arm,idle-state";
303 idle-state-nam 301 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspe 302 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency- 303 entry-latency-us = <332>;
306 exit-latency-u 304 exit-latency-us = <368>;
307 min-residency- 305 min-residency-us = <9987>;
308 local-timer-st 306 local-timer-stop;
309 }; 307 };
310 308
311 PERF_CLUSTER_SLEEP_2: 309 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = " 310 compatible = "arm,idle-state";
313 idle-state-nam 311 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspe 312 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency- 313 entry-latency-us = <545>;
316 exit-latency-u 314 exit-latency-us = <1609>;
317 min-residency- 315 min-residency-us = <9987>;
318 local-timer-st 316 local-timer-stop;
319 }; 317 };
320 }; 318 };
321 }; 319 };
322 320
323 firmware { 321 firmware {
324 scm { 322 scm {
325 compatible = "qcom,scm 323 compatible = "qcom,scm-msm8998", "qcom,scm";
326 }; 324 };
327 }; 325 };
328 326
329 memory@80000000 { 327 memory@80000000 {
330 device_type = "memory"; 328 device_type = "memory";
331 /* We expect the bootloader to 329 /* We expect the bootloader to fill in the reg */
332 reg = <0x0 0x80000000 0x0 0x0> 330 reg = <0x0 0x80000000 0x0 0x0>;
333 }; 331 };
334 332
335 dsi_opp_table: opp-table-dsi { 333 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points 334 compatible = "operating-points-v2";
337 335
338 opp-131250000 { 336 opp-131250000 {
339 opp-hz = /bits/ 64 <13 337 opp-hz = /bits/ 64 <131250000>;
340 required-opps = <&rpmp 338 required-opps = <&rpmpd_opp_svs>;
341 }; 339 };
342 340
343 opp-210000000 { 341 opp-210000000 {
344 opp-hz = /bits/ 64 <21 342 opp-hz = /bits/ 64 <210000000>;
345 required-opps = <&rpmp 343 required-opps = <&rpmpd_opp_svs_plus>;
346 }; 344 };
347 345
348 opp-262500000 { 346 opp-262500000 {
349 opp-hz = /bits/ 64 <26 347 opp-hz = /bits/ 64 <262500000>;
350 required-opps = <&rpmp 348 required-opps = <&rpmpd_opp_nom>;
351 }; 349 };
352 }; 350 };
353 351
354 pmu { 352 pmu {
355 compatible = "arm,armv8-pmuv3" 353 compatible = "arm,armv8-pmuv3";
356 interrupts = <GIC_PPI 6 IRQ_TY 354 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
357 }; 355 };
358 356
359 psci { 357 psci {
360 compatible = "arm,psci-1.0"; 358 compatible = "arm,psci-1.0";
361 method = "smc"; 359 method = "smc";
362 }; 360 };
363 361
364 rpm: remoteproc { 362 rpm: remoteproc {
365 compatible = "qcom,sdm660-rpm- 363 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
366 364
367 glink-edge { 365 glink-edge {
368 compatible = "qcom,gli 366 compatible = "qcom,glink-rpm";
369 367
370 interrupts = <GIC_SPI 368 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
371 qcom,rpm-msg-ram = <&r 369 qcom,rpm-msg-ram = <&rpm_msg_ram>;
372 mboxes = <&apcs_glb 0> 370 mboxes = <&apcs_glb 0>;
373 371
374 rpm_requests: rpm-requ 372 rpm_requests: rpm-requests {
375 compatible = " !! 373 compatible = "qcom,rpm-sdm660";
376 qcom,glink-cha 374 qcom,glink-channels = "rpm_requests";
377 375
378 rpmcc: clock-c 376 rpmcc: clock-controller {
379 compat 377 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
380 #clock 378 #clock-cells = <1>;
381 }; 379 };
382 380
383 rpmpd: power-c 381 rpmpd: power-controller {
384 compat 382 compatible = "qcom,sdm660-rpmpd";
385 #power 383 #power-domain-cells = <1>;
386 operat 384 operating-points-v2 = <&rpmpd_opp_table>;
387 385
388 rpmpd_ 386 rpmpd_opp_table: opp-table {
389 387 compatible = "operating-points-v2";
390 388
391 389 rpmpd_opp_ret: opp1 {
392 390 opp-level = <RPM_SMD_LEVEL_RETENTION>;
393 391 };
394 392
395 393 rpmpd_opp_ret_plus: opp2 {
396 394 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
397 395 };
398 396
399 397 rpmpd_opp_min_svs: opp3 {
400 398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
401 399 };
402 400
403 401 rpmpd_opp_low_svs: opp4 {
404 402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
405 403 };
406 404
407 405 rpmpd_opp_svs: opp5 {
408 406 opp-level = <RPM_SMD_LEVEL_SVS>;
409 407 };
410 408
411 409 rpmpd_opp_svs_plus: opp6 {
412 410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
413 411 };
414 412
415 413 rpmpd_opp_nom: opp7 {
416 414 opp-level = <RPM_SMD_LEVEL_NOM>;
417 415 };
418 416
419 417 rpmpd_opp_nom_plus: opp8 {
420 418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
421 419 };
422 420
423 421 rpmpd_opp_turbo: opp9 {
424 422 opp-level = <RPM_SMD_LEVEL_TURBO>;
425 423 };
426 }; 424 };
427 }; 425 };
428 }; 426 };
429 }; 427 };
430 }; 428 };
431 429
432 reserved-memory { 430 reserved-memory {
433 #address-cells = <2>; 431 #address-cells = <2>;
434 #size-cells = <2>; 432 #size-cells = <2>;
435 ranges; 433 ranges;
436 434
437 wlan_msa_guard: wlan-msa-guard 435 wlan_msa_guard: wlan-msa-guard@85600000 {
438 reg = <0x0 0x85600000 436 reg = <0x0 0x85600000 0x0 0x100000>;
439 no-map; 437 no-map;
440 }; 438 };
441 439
442 wlan_msa_mem: wlan-msa-mem@857 440 wlan_msa_mem: wlan-msa-mem@85700000 {
443 reg = <0x0 0x85700000 441 reg = <0x0 0x85700000 0x0 0x100000>;
444 no-map; 442 no-map;
445 }; 443 };
446 444
447 qhee_code: qhee-code@85800000 445 qhee_code: qhee-code@85800000 {
448 reg = <0x0 0x85800000 446 reg = <0x0 0x85800000 0x0 0x600000>;
449 no-map; 447 no-map;
450 }; 448 };
451 449
452 rmtfs_mem: memory@85e00000 { 450 rmtfs_mem: memory@85e00000 {
453 compatible = "qcom,rmt 451 compatible = "qcom,rmtfs-mem";
454 reg = <0x0 0x85e00000 452 reg = <0x0 0x85e00000 0x0 0x200000>;
455 no-map; 453 no-map;
456 454
457 qcom,client-id = <1>; 455 qcom,client-id = <1>;
458 qcom,vmid = <QCOM_SCM_ !! 456 qcom,vmid = <15>;
459 }; 457 };
460 458
461 smem_region: smem-mem@86000000 459 smem_region: smem-mem@86000000 {
462 reg = <0 0x86000000 0 460 reg = <0 0x86000000 0 0x200000>;
463 no-map; 461 no-map;
464 }; 462 };
465 463
466 tz_mem: memory@86200000 { 464 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000 465 reg = <0x0 0x86200000 0x0 0x3300000>;
468 no-map; 466 no-map;
469 }; 467 };
470 468
471 mpss_region: mpss@8ac00000 { 469 mpss_region: mpss@8ac00000 {
472 reg = <0x0 0x8ac00000 470 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
473 no-map; 471 no-map;
474 }; 472 };
475 473
476 adsp_region: adsp@92a00000 { 474 adsp_region: adsp@92a00000 {
477 reg = <0x0 0x92a00000 475 reg = <0x0 0x92a00000 0x0 0x1e00000>;
478 no-map; 476 no-map;
479 }; 477 };
480 478
481 mba_region: mba@94800000 { 479 mba_region: mba@94800000 {
482 reg = <0x0 0x94800000 480 reg = <0x0 0x94800000 0x0 0x200000>;
483 no-map; 481 no-map;
484 }; 482 };
485 483
486 buffer_mem: tzbuffer@94a00000 484 buffer_mem: tzbuffer@94a00000 {
487 reg = <0x0 0x94a00000 485 reg = <0x0 0x94a00000 0x0 0x100000>;
488 no-map; 486 no-map;
489 }; 487 };
490 488
491 venus_region: venus@9f800000 { 489 venus_region: venus@9f800000 {
492 reg = <0x0 0x9f800000 490 reg = <0x0 0x9f800000 0x0 0x800000>;
493 no-map; 491 no-map;
494 }; 492 };
495 493
496 adsp_mem: adsp-region@f6000000 494 adsp_mem: adsp-region@f6000000 {
497 reg = <0x0 0xf6000000 495 reg = <0x0 0xf6000000 0x0 0x800000>;
498 no-map; 496 no-map;
499 }; 497 };
500 498
501 qseecom_mem: qseecom-region@f6 499 qseecom_mem: qseecom-region@f6800000 {
502 reg = <0x0 0xf6800000 500 reg = <0x0 0xf6800000 0x0 0x1400000>;
503 no-map; 501 no-map;
504 }; 502 };
505 503
506 zap_shader_region: gpu@fed0000 504 zap_shader_region: gpu@fed00000 {
507 compatible = "shared-d 505 compatible = "shared-dma-pool";
508 reg = <0x0 0xfed00000 506 reg = <0x0 0xfed00000 0x0 0xa00000>;
509 no-map; 507 no-map;
510 }; 508 };
511 }; 509 };
512 510
513 smem: smem { 511 smem: smem {
514 compatible = "qcom,smem"; 512 compatible = "qcom,smem";
515 memory-region = <&smem_region> 513 memory-region = <&smem_region>;
516 hwlocks = <&tcsr_mutex 3>; 514 hwlocks = <&tcsr_mutex 3>;
517 }; 515 };
518 516
519 smp2p-adsp { 517 smp2p-adsp {
520 compatible = "qcom,smp2p"; 518 compatible = "qcom,smp2p";
521 qcom,smem = <443>, <429>; 519 qcom,smem = <443>, <429>;
522 interrupts = <GIC_SPI 158 IRQ_ 520 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
523 mboxes = <&apcs_glb 10>; 521 mboxes = <&apcs_glb 10>;
524 qcom,local-pid = <0>; 522 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>; 523 qcom,remote-pid = <2>;
526 524
527 adsp_smp2p_out: master-kernel 525 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "mas 526 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells 527 #qcom,smem-state-cells = <1>;
530 }; 528 };
531 529
532 adsp_smp2p_in: slave-kernel { 530 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "sla 531 qcom,entry-name = "slave-kernel";
534 interrupt-controller; 532 interrupt-controller;
535 #interrupt-cells = <2> 533 #interrupt-cells = <2>;
536 }; 534 };
537 }; 535 };
538 536
539 smp2p-mpss { 537 smp2p-mpss {
540 compatible = "qcom,smp2p"; 538 compatible = "qcom,smp2p";
541 qcom,smem = <435>, <428>; 539 qcom,smem = <435>, <428>;
542 interrupts = <GIC_SPI 451 IRQ_ 540 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
543 mboxes = <&apcs_glb 14>; 541 mboxes = <&apcs_glb 14>;
544 qcom,local-pid = <0>; 542 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>; 543 qcom,remote-pid = <1>;
546 544
547 modem_smp2p_out: master-kernel 545 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "mas 546 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells 547 #qcom,smem-state-cells = <1>;
550 }; 548 };
551 549
552 modem_smp2p_in: slave-kernel { 550 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "sla 551 qcom,entry-name = "slave-kernel";
554 interrupt-controller; 552 interrupt-controller;
555 #interrupt-cells = <2> 553 #interrupt-cells = <2>;
556 }; 554 };
557 }; 555 };
558 556
559 soc@0 { 557 soc@0 {
560 #address-cells = <1>; 558 #address-cells = <1>;
561 #size-cells = <1>; 559 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>; 560 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus"; 561 compatible = "simple-bus";
564 562
565 gcc: clock-controller@100000 { 563 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc 564 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>; 565 #clock-cells = <1>;
568 #reset-cells = <1>; 566 #reset-cells = <1>;
569 #power-domain-cells = 567 #power-domain-cells = <1>;
570 reg = <0x00100000 0x94 568 reg = <0x00100000 0x94000>;
571 569
572 clock-names = "xo", "s 570 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>, 571 clocks = <&xo_board>,
574 <&slee 572 <&sleep_clk>;
575 }; 573 };
576 574
577 rpm_msg_ram: sram@778000 { 575 rpm_msg_ram: sram@778000 {
578 compatible = "qcom,rpm 576 compatible = "qcom,rpm-msg-ram";
579 reg = <0x00778000 0x70 577 reg = <0x00778000 0x7000>;
580 }; 578 };
581 579
582 qfprom: qfprom@780000 { 580 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm 581 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
584 reg = <0x00780000 0x62 582 reg = <0x00780000 0x621c>;
585 #address-cells = <1>; 583 #address-cells = <1>;
586 #size-cells = <1>; 584 #size-cells = <1>;
587 585
588 qusb2_hstx_trim: hstx- 586 qusb2_hstx_trim: hstx-trim@240 {
589 reg = <0x243 0 587 reg = <0x243 0x1>;
590 bits = <1 3>; 588 bits = <1 3>;
591 }; 589 };
592 590
593 gpu_speed_bin: gpu-spe 591 gpu_speed_bin: gpu-speed-bin@41a0 {
594 reg = <0x41a2 592 reg = <0x41a2 0x1>;
595 bits = <5 7>; 593 bits = <5 7>;
596 }; 594 };
597 }; 595 };
598 596
599 rng: rng@793000 { 597 rng: rng@793000 {
600 compatible = "qcom,prn 598 compatible = "qcom,prng-ee";
601 reg = <0x00793000 0x10 599 reg = <0x00793000 0x1000>;
602 clocks = <&gcc GCC_PRN 600 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core"; 601 clock-names = "core";
604 }; 602 };
605 603
606 bimc: interconnect@1008000 { 604 bimc: interconnect@1008000 {
607 compatible = "qcom,sdm 605 compatible = "qcom,sdm660-bimc";
608 reg = <0x01008000 0x78 606 reg = <0x01008000 0x78000>;
609 #interconnect-cells = 607 #interconnect-cells = <1>;
>> 608 clock-names = "bus", "bus_a";
>> 609 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 610 <&rpmcc RPM_SMD_BIMC_A_CLK>;
610 }; 611 };
611 612
612 restart@10ac000 { 613 restart@10ac000 {
613 compatible = "qcom,psh 614 compatible = "qcom,pshold";
614 reg = <0x010ac000 0x4> 615 reg = <0x010ac000 0x4>;
615 }; 616 };
616 617
617 cnoc: interconnect@1500000 { 618 cnoc: interconnect@1500000 {
618 compatible = "qcom,sdm 619 compatible = "qcom,sdm660-cnoc";
619 reg = <0x01500000 0x10 620 reg = <0x01500000 0x10000>;
620 #interconnect-cells = 621 #interconnect-cells = <1>;
>> 622 clock-names = "bus", "bus_a";
>> 623 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 624 <&rpmcc RPM_SMD_CNOC_A_CLK>;
621 }; 625 };
622 626
623 snoc: interconnect@1626000 { 627 snoc: interconnect@1626000 {
624 compatible = "qcom,sdm 628 compatible = "qcom,sdm660-snoc";
625 reg = <0x01626000 0x70 629 reg = <0x01626000 0x7090>;
626 #interconnect-cells = 630 #interconnect-cells = <1>;
>> 631 clock-names = "bus", "bus_a";
>> 632 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 633 <&rpmcc RPM_SMD_SNOC_A_CLK>;
627 }; 634 };
628 635
629 anoc2_smmu: iommu@16c0000 { 636 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm 637 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 reg = <0x016c0000 0x40 638 reg = <0x016c0000 0x40000>;
>> 639
>> 640 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 641 assigned-clock-rates = <1000>;
>> 642 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 643 clock-names = "bus";
632 #global-interrupts = < 644 #global-interrupts = <2>;
633 #iommu-cells = <1>; 645 #iommu-cells = <1>;
634 646
635 interrupts = 647 interrupts =
636 <GIC_SPI 229 I 648 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 231 I 649 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
638 650
639 <GIC_SPI 373 I 651 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 374 I 652 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
641 <GIC_SPI 375 I 653 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
642 <GIC_SPI 376 I 654 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
643 <GIC_SPI 377 I 655 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
644 <GIC_SPI 378 I 656 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
645 <GIC_SPI 462 I 657 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 463 I 658 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 464 I 659 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 465 I 660 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 466 I 661 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 467 I 662 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 353 I 663 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 354 I 664 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 355 I 665 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 356 I 666 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 357 I 667 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 358 I 668 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 359 I 669 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 360 I 670 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 442 I 671 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 443 I 672 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 444 I 673 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 447 I 674 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 468 I 675 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 469 I 676 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 472 I 677 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 473 I 678 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 474 I 679 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
668 680
669 status = "disabled"; 681 status = "disabled";
670 }; 682 };
671 683
672 a2noc: interconnect@1704000 { 684 a2noc: interconnect@1704000 {
673 compatible = "qcom,sdm 685 compatible = "qcom,sdm660-a2noc";
674 reg = <0x01704000 0xc1 686 reg = <0x01704000 0xc100>;
675 #interconnect-cells = 687 #interconnect-cells = <1>;
676 clock-names = "ipa", !! 688 clock-names = "bus",
>> 689 "bus_a",
>> 690 "ipa",
677 "ufs_axi 691 "ufs_axi",
678 "aggre2_ 692 "aggre2_ufs_axi",
679 "aggre2_ 693 "aggre2_usb3_axi",
680 "cfg_noc 694 "cfg_noc_usb2_axi";
681 clocks = <&rpmcc RPM_S !! 695 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 696 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 697 <&rpmcc RPM_SMD_IPA_CLK>,
682 <&gcc GCC_UFS 698 <&gcc GCC_UFS_AXI_CLK>,
683 <&gcc GCC_AGG 699 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
684 <&gcc GCC_AGG 700 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
685 <&gcc GCC_CFG 701 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
686 }; 702 };
687 703
688 mnoc: interconnect@1745000 { 704 mnoc: interconnect@1745000 {
689 compatible = "qcom,sdm 705 compatible = "qcom,sdm660-mnoc";
690 reg = <0x01745000 0xa0 706 reg = <0x01745000 0xa010>;
691 #interconnect-cells = 707 #interconnect-cells = <1>;
692 clock-names = "iface"; !! 708 clock-names = "bus", "bus_a", "iface";
693 clocks = <&mmcc AHB_CL !! 709 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
>> 710 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
>> 711 <&mmcc AHB_CLK_SRC>;
694 }; 712 };
695 713
696 tsens: thermal-sensor@10ae000 714 tsens: thermal-sensor@10ae000 {
697 compatible = "qcom,sdm 715 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
698 reg = <0x010ae000 0x10 716 reg = <0x010ae000 0x1000>, /* TM */
699 <0x010ad000 717 <0x010ad000 0x1000>; /* SROT */
700 #qcom,sensors = <12>; 718 #qcom,sensors = <12>;
701 interrupts = <GIC_SPI 719 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_ 720 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "upl 721 interrupt-names = "uplow", "critical";
704 #thermal-sensor-cells 722 #thermal-sensor-cells = <1>;
705 }; 723 };
706 724
707 tcsr_mutex: hwlock@1f40000 { 725 tcsr_mutex: hwlock@1f40000 {
708 compatible = "qcom,tcs 726 compatible = "qcom,tcsr-mutex";
709 reg = <0x01f40000 0x20 727 reg = <0x01f40000 0x20000>;
710 #hwlock-cells = <1>; 728 #hwlock-cells = <1>;
711 }; 729 };
712 730
713 tcsr_regs_1: syscon@1f60000 { 731 tcsr_regs_1: syscon@1f60000 {
714 compatible = "qcom,sdm 732 compatible = "qcom,sdm630-tcsr", "syscon";
715 reg = <0x01f60000 0x20 733 reg = <0x01f60000 0x20000>;
716 }; 734 };
717 735
718 tlmm: pinctrl@3100000 { 736 tlmm: pinctrl@3100000 {
719 compatible = "qcom,sdm 737 compatible = "qcom,sdm630-pinctrl";
720 reg = <0x03100000 0x40 738 reg = <0x03100000 0x400000>,
721 <0x03500000 739 <0x03500000 0x400000>,
722 <0x03900000 740 <0x03900000 0x400000>;
723 reg-names = "south", " 741 reg-names = "south", "center", "north";
724 interrupts = <GIC_SPI 742 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-controller; 743 gpio-controller;
726 gpio-ranges = <&tlmm 0 744 gpio-ranges = <&tlmm 0 0 114>;
727 #gpio-cells = <2>; 745 #gpio-cells = <2>;
728 interrupt-controller; 746 interrupt-controller;
729 #interrupt-cells = <2> 747 #interrupt-cells = <2>;
730 748
731 blsp1_uart1_default: b 749 blsp1_uart1_default: blsp1-uart1-default-state {
732 pins = "gpio0" 750 pins = "gpio0", "gpio1", "gpio2", "gpio3";
733 function = "bl 751 function = "blsp_uart1";
734 drive-strength 752 drive-strength = <2>;
735 bias-disable; 753 bias-disable;
736 }; 754 };
737 755
738 blsp1_uart1_sleep: bls 756 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
739 pins = "gpio0" 757 pins = "gpio0", "gpio1", "gpio2", "gpio3";
740 function = "gp 758 function = "gpio";
741 drive-strength 759 drive-strength = <2>;
742 bias-disable; 760 bias-disable;
743 }; 761 };
744 762
745 blsp1_uart2_default: b 763 blsp1_uart2_default: blsp1-uart2-default-state {
746 pins = "gpio4" 764 pins = "gpio4", "gpio5";
747 function = "bl 765 function = "blsp_uart2";
748 drive-strength 766 drive-strength = <2>;
749 bias-disable; 767 bias-disable;
750 }; 768 };
751 769
752 blsp2_uart1_default: b 770 blsp2_uart1_default: blsp2-uart1-active-state {
753 tx-rts-pins { 771 tx-rts-pins {
754 pins = 772 pins = "gpio16", "gpio19";
755 functi 773 function = "blsp_uart5";
756 drive- 774 drive-strength = <2>;
757 bias-d 775 bias-disable;
758 }; 776 };
759 777
760 rx-pins { 778 rx-pins {
761 /* 779 /*
762 * Avo 780 * Avoid garbage data while BT module
763 * is 781 * is powered off or not driving signal
764 */ 782 */
765 pins = 783 pins = "gpio17";
766 functi 784 function = "blsp_uart5";
767 drive- 785 drive-strength = <2>;
768 bias-p 786 bias-pull-up;
769 }; 787 };
770 788
771 cts-pins { 789 cts-pins {
772 /* Mat 790 /* Match the pull of the BT module */
773 pins = 791 pins = "gpio18";
774 functi 792 function = "blsp_uart5";
775 drive- 793 drive-strength = <2>;
776 bias-p 794 bias-pull-down;
777 }; 795 };
778 }; 796 };
779 797
780 blsp2_uart1_sleep: bls 798 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
781 tx-pins { 799 tx-pins {
782 pins = 800 pins = "gpio16";
783 functi 801 function = "gpio";
784 drive- 802 drive-strength = <2>;
785 bias-p 803 bias-pull-up;
786 }; 804 };
787 805
788 rx-cts-rts-pin 806 rx-cts-rts-pins {
789 pins = 807 pins = "gpio17", "gpio18", "gpio19";
790 functi 808 function = "gpio";
791 drive- 809 drive-strength = <2>;
792 bias-d 810 bias-disable;
793 }; 811 };
794 }; 812 };
795 813
796 i2c1_default: i2c1-def 814 i2c1_default: i2c1-default-state {
797 pins = "gpio2" 815 pins = "gpio2", "gpio3";
798 function = "bl 816 function = "blsp_i2c1";
799 drive-strength 817 drive-strength = <2>;
800 bias-disable; 818 bias-disable;
801 }; 819 };
802 820
803 i2c1_sleep: i2c1-sleep 821 i2c1_sleep: i2c1-sleep-state {
804 pins = "gpio2" 822 pins = "gpio2", "gpio3";
805 function = "bl 823 function = "blsp_i2c1";
806 drive-strength 824 drive-strength = <2>;
807 bias-pull-up; 825 bias-pull-up;
808 }; 826 };
809 827
810 i2c2_default: i2c2-def 828 i2c2_default: i2c2-default-state {
811 pins = "gpio6" 829 pins = "gpio6", "gpio7";
812 function = "bl 830 function = "blsp_i2c2";
813 drive-strength 831 drive-strength = <2>;
814 bias-disable; 832 bias-disable;
815 }; 833 };
816 834
817 i2c2_sleep: i2c2-sleep 835 i2c2_sleep: i2c2-sleep-state {
818 pins = "gpio6" 836 pins = "gpio6", "gpio7";
819 function = "bl 837 function = "blsp_i2c2";
820 drive-strength 838 drive-strength = <2>;
821 bias-pull-up; 839 bias-pull-up;
822 }; 840 };
823 841
824 i2c3_default: i2c3-def 842 i2c3_default: i2c3-default-state {
825 pins = "gpio10 843 pins = "gpio10", "gpio11";
826 function = "bl 844 function = "blsp_i2c3";
827 drive-strength 845 drive-strength = <2>;
828 bias-disable; 846 bias-disable;
829 }; 847 };
830 848
831 i2c3_sleep: i2c3-sleep 849 i2c3_sleep: i2c3-sleep-state {
832 pins = "gpio10 850 pins = "gpio10", "gpio11";
833 function = "bl 851 function = "blsp_i2c3";
834 drive-strength 852 drive-strength = <2>;
835 bias-pull-up; 853 bias-pull-up;
836 }; 854 };
837 855
838 i2c4_default: i2c4-def 856 i2c4_default: i2c4-default-state {
839 pins = "gpio14 857 pins = "gpio14", "gpio15";
840 function = "bl 858 function = "blsp_i2c4";
841 drive-strength 859 drive-strength = <2>;
842 bias-disable; 860 bias-disable;
843 }; 861 };
844 862
845 i2c4_sleep: i2c4-sleep 863 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio14 864 pins = "gpio14", "gpio15";
847 function = "bl 865 function = "blsp_i2c4";
848 drive-strength 866 drive-strength = <2>;
849 bias-pull-up; 867 bias-pull-up;
850 }; 868 };
851 869
852 i2c5_default: i2c5-def 870 i2c5_default: i2c5-default-state {
853 pins = "gpio18 871 pins = "gpio18", "gpio19";
854 function = "bl 872 function = "blsp_i2c5";
855 drive-strength 873 drive-strength = <2>;
856 bias-disable; 874 bias-disable;
857 }; 875 };
858 876
859 i2c5_sleep: i2c5-sleep 877 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio18 878 pins = "gpio18", "gpio19";
861 function = "bl 879 function = "blsp_i2c5";
862 drive-strength 880 drive-strength = <2>;
863 bias-pull-up; 881 bias-pull-up;
864 }; 882 };
865 883
866 i2c6_default: i2c6-def 884 i2c6_default: i2c6-default-state {
867 pins = "gpio22 885 pins = "gpio22", "gpio23";
868 function = "bl 886 function = "blsp_i2c6";
869 drive-strength 887 drive-strength = <2>;
870 bias-disable; 888 bias-disable;
871 }; 889 };
872 890
873 i2c6_sleep: i2c6-sleep 891 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio22 892 pins = "gpio22", "gpio23";
875 function = "bl 893 function = "blsp_i2c6";
876 drive-strength 894 drive-strength = <2>;
877 bias-pull-up; 895 bias-pull-up;
878 }; 896 };
879 897
880 i2c7_default: i2c7-def 898 i2c7_default: i2c7-default-state {
881 pins = "gpio26 899 pins = "gpio26", "gpio27";
882 function = "bl 900 function = "blsp_i2c7";
883 drive-strength 901 drive-strength = <2>;
884 bias-disable; 902 bias-disable;
885 }; 903 };
886 904
887 i2c7_sleep: i2c7-sleep 905 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio26 906 pins = "gpio26", "gpio27";
889 function = "bl 907 function = "blsp_i2c7";
890 drive-strength 908 drive-strength = <2>;
891 bias-pull-up; 909 bias-pull-up;
892 }; 910 };
893 911
894 i2c8_default: i2c8-def 912 i2c8_default: i2c8-default-state {
895 pins = "gpio30 913 pins = "gpio30", "gpio31";
896 function = "bl 914 function = "blsp_i2c8_a";
897 drive-strength 915 drive-strength = <2>;
898 bias-disable; 916 bias-disable;
899 }; 917 };
900 918
901 i2c8_sleep: i2c8-sleep 919 i2c8_sleep: i2c8-sleep-state {
902 pins = "gpio30 920 pins = "gpio30", "gpio31";
903 function = "bl 921 function = "blsp_i2c8_a";
904 drive-strength 922 drive-strength = <2>;
905 bias-pull-up; 923 bias-pull-up;
906 }; 924 };
907 925
908 cci0_default: cci0-def 926 cci0_default: cci0-default-state {
909 pins = "gpio36 927 pins = "gpio36","gpio37";
910 function = "cc 928 function = "cci_i2c";
911 bias-pull-up; 929 bias-pull-up;
912 drive-strength 930 drive-strength = <2>;
913 }; 931 };
914 932
915 cci1_default: cci1-def 933 cci1_default: cci1-default-state {
916 pins = "gpio38 934 pins = "gpio38","gpio39";
917 function = "cc 935 function = "cci_i2c";
918 bias-pull-up; 936 bias-pull-up;
919 drive-strength 937 drive-strength = <2>;
920 }; 938 };
921 939
922 sdc1_state_on: sdc1-on 940 sdc1_state_on: sdc1-on-state {
923 clk-pins { 941 clk-pins {
924 pins = 942 pins = "sdc1_clk";
925 bias-d 943 bias-disable;
926 drive- 944 drive-strength = <16>;
927 }; 945 };
928 946
929 cmd-pins { 947 cmd-pins {
930 pins = 948 pins = "sdc1_cmd";
931 bias-p 949 bias-pull-up;
932 drive- 950 drive-strength = <10>;
933 }; 951 };
934 952
935 data-pins { 953 data-pins {
936 pins = 954 pins = "sdc1_data";
937 bias-p 955 bias-pull-up;
938 drive- 956 drive-strength = <10>;
939 }; 957 };
940 958
941 rclk-pins { 959 rclk-pins {
942 pins = 960 pins = "sdc1_rclk";
943 bias-p 961 bias-pull-down;
944 }; 962 };
945 }; 963 };
946 964
947 sdc1_state_off: sdc1-o 965 sdc1_state_off: sdc1-off-state {
948 clk-pins { 966 clk-pins {
949 pins = 967 pins = "sdc1_clk";
950 bias-d 968 bias-disable;
951 drive- 969 drive-strength = <2>;
952 }; 970 };
953 971
954 cmd-pins { 972 cmd-pins {
955 pins = 973 pins = "sdc1_cmd";
956 bias-p 974 bias-pull-up;
957 drive- 975 drive-strength = <2>;
958 }; 976 };
959 977
960 data-pins { 978 data-pins {
961 pins = 979 pins = "sdc1_data";
962 bias-p 980 bias-pull-up;
963 drive- 981 drive-strength = <2>;
964 }; 982 };
965 983
966 rclk-pins { 984 rclk-pins {
967 pins = 985 pins = "sdc1_rclk";
968 bias-p 986 bias-pull-down;
969 }; 987 };
970 }; 988 };
971 989
972 sdc2_state_on: sdc2-on 990 sdc2_state_on: sdc2-on-state {
973 clk-pins { 991 clk-pins {
974 pins = 992 pins = "sdc2_clk";
975 bias-d 993 bias-disable;
976 drive- 994 drive-strength = <16>;
977 }; 995 };
978 996
979 cmd-pins { 997 cmd-pins {
980 pins = 998 pins = "sdc2_cmd";
981 bias-p 999 bias-pull-up;
982 drive- 1000 drive-strength = <10>;
983 }; 1001 };
984 1002
985 data-pins { 1003 data-pins {
986 pins = 1004 pins = "sdc2_data";
987 bias-p 1005 bias-pull-up;
988 drive- 1006 drive-strength = <10>;
989 }; 1007 };
990 }; 1008 };
991 1009
992 sdc2_state_off: sdc2-o 1010 sdc2_state_off: sdc2-off-state {
993 clk-pins { 1011 clk-pins {
994 pins = 1012 pins = "sdc2_clk";
995 bias-d 1013 bias-disable;
996 drive- 1014 drive-strength = <2>;
997 }; 1015 };
998 1016
999 cmd-pins { 1017 cmd-pins {
1000 pins 1018 pins = "sdc2_cmd";
1001 bias- 1019 bias-pull-up;
1002 drive 1020 drive-strength = <2>;
1003 }; 1021 };
1004 1022
1005 data-pins { 1023 data-pins {
1006 pins 1024 pins = "sdc2_data";
1007 bias- 1025 bias-pull-up;
1008 drive 1026 drive-strength = <2>;
1009 }; 1027 };
1010 }; 1028 };
1011 }; 1029 };
1012 1030
1013 remoteproc_mss: remoteproc@40 <<
1014 compatible = "qcom,sd <<
1015 reg = <0x04080000 0x1 <<
1016 reg-names = "qdsp6", <<
1017 <<
1018 interrupts-extended = <<
1019 <<
1020 <<
1021 <<
1022 <<
1023 <<
1024 interrupt-names = "wd <<
1025 "fa <<
1026 "re <<
1027 "ha <<
1028 "st <<
1029 "sh <<
1030 <<
1031 clocks = <&gcc GCC_MS <<
1032 <&gcc GCC_BI <<
1033 <&gcc GCC_BO <<
1034 <&gcc GPLL0_ <<
1035 <&gcc GCC_MS <<
1036 <&gcc GCC_MS <<
1037 <&rpmcc RPM_ <<
1038 <&rpmcc RPM_ <<
1039 clock-names = "iface" <<
1040 "bus", <<
1041 "mem", <<
1042 "gpll0_ <<
1043 "snoc_a <<
1044 "mnoc_a <<
1045 "qdss", <<
1046 "xo"; <<
1047 <<
1048 qcom,smem-states = <& <<
1049 qcom,smem-state-names <<
1050 <<
1051 resets = <&gcc GCC_MS <<
1052 reset-names = "mss_re <<
1053 <<
1054 qcom,halt-regs = <&tc <<
1055 <<
1056 power-domains = <&rpm <<
1057 <&rpm <<
1058 power-domain-names = <<
1059 <<
1060 memory-region = <&mba <<
1061 <<
1062 status = "disabled"; <<
1063 <<
1064 glink-edge { <<
1065 interrupts = <<
1066 label = "mode <<
1067 qcom,remote-p <<
1068 mboxes = <&ap <<
1069 }; <<
1070 }; <<
1071 <<
1072 adreno_gpu: gpu@5000000 { 1031 adreno_gpu: gpu@5000000 {
1073 compatible = "qcom,ad 1032 compatible = "qcom,adreno-508.0", "qcom,adreno";
1074 1033
1075 reg = <0x05000000 0x4 1034 reg = <0x05000000 0x40000>;
1076 reg-names = "kgsl_3d0 1035 reg-names = "kgsl_3d0_reg_memory";
1077 1036
1078 interrupts = <GIC_SPI 1037 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1079 1038
1080 clocks = <&gcc GCC_GP 1039 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1081 <&gpucc GPUCC 1040 <&gpucc GPUCC_RBBMTIMER_CLK>,
1082 <&gcc GCC_BIM 1041 <&gcc GCC_BIMC_GFX_CLK>,
1083 <&gcc GCC_GPU 1042 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1084 <&gpucc GPUCC 1043 <&gpucc GPUCC_RBCPR_CLK>,
1085 <&gpucc GPUCC 1044 <&gpucc GPUCC_GFX3D_CLK>;
1086 1045
1087 clock-names = "iface" 1046 clock-names = "iface",
1088 "rbbmtimer", 1047 "rbbmtimer",
1089 "mem", 1048 "mem",
1090 "mem_iface", 1049 "mem_iface",
1091 "rbcpr", 1050 "rbcpr",
1092 "core"; 1051 "core";
1093 1052
1094 power-domains = <&rpm 1053 power-domains = <&rpmpd SDM660_VDDMX>;
1095 iommus = <&kgsl_smmu 1054 iommus = <&kgsl_smmu 0>;
1096 1055
1097 nvmem-cells = <&gpu_s 1056 nvmem-cells = <&gpu_speed_bin>;
1098 nvmem-cell-names = "s 1057 nvmem-cell-names = "speed_bin";
1099 1058
1100 interconnects = <&bim 1059 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1101 interconnect-names = 1060 interconnect-names = "gfx-mem";
1102 1061
1103 operating-points-v2 = 1062 operating-points-v2 = <&gpu_sdm630_opp_table>;
1104 #cooling-cells = <2>; <<
1105 1063
1106 status = "disabled"; 1064 status = "disabled";
1107 1065
1108 gpu_sdm630_opp_table: 1066 gpu_sdm630_opp_table: opp-table {
1109 compatible = 1067 compatible = "operating-points-v2";
1110 opp-775000000 1068 opp-775000000 {
1111 opp-h 1069 opp-hz = /bits/ 64 <775000000>;
1112 opp-l 1070 opp-level = <RPM_SMD_LEVEL_TURBO>;
1113 opp-p 1071 opp-peak-kBps = <5412000>;
1114 opp-s 1072 opp-supported-hw = <0xa2>;
1115 }; 1073 };
1116 opp-647000000 1074 opp-647000000 {
1117 opp-h 1075 opp-hz = /bits/ 64 <647000000>;
1118 opp-l 1076 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1119 opp-p 1077 opp-peak-kBps = <4068000>;
1120 opp-s 1078 opp-supported-hw = <0xff>;
1121 }; 1079 };
1122 opp-588000000 1080 opp-588000000 {
1123 opp-h 1081 opp-hz = /bits/ 64 <588000000>;
1124 opp-l 1082 opp-level = <RPM_SMD_LEVEL_NOM>;
1125 opp-p 1083 opp-peak-kBps = <3072000>;
1126 opp-s 1084 opp-supported-hw = <0xff>;
1127 }; 1085 };
1128 opp-465000000 1086 opp-465000000 {
1129 opp-h 1087 opp-hz = /bits/ 64 <465000000>;
1130 opp-l 1088 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1131 opp-p 1089 opp-peak-kBps = <2724000>;
1132 opp-s 1090 opp-supported-hw = <0xff>;
1133 }; 1091 };
1134 opp-370000000 1092 opp-370000000 {
1135 opp-h 1093 opp-hz = /bits/ 64 <370000000>;
1136 opp-l 1094 opp-level = <RPM_SMD_LEVEL_SVS>;
1137 opp-p 1095 opp-peak-kBps = <2188000>;
1138 opp-s 1096 opp-supported-hw = <0xff>;
1139 }; 1097 };
1140 opp-240000000 1098 opp-240000000 {
1141 opp-h 1099 opp-hz = /bits/ 64 <240000000>;
1142 opp-l 1100 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1143 opp-p 1101 opp-peak-kBps = <1648000>;
1144 opp-s 1102 opp-supported-hw = <0xff>;
1145 }; 1103 };
1146 opp-160000000 1104 opp-160000000 {
1147 opp-h 1105 opp-hz = /bits/ 64 <160000000>;
1148 opp-l 1106 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1149 opp-p 1107 opp-peak-kBps = <1200000>;
1150 opp-s 1108 opp-supported-hw = <0xff>;
1151 }; 1109 };
1152 }; 1110 };
1153 }; 1111 };
1154 1112
1155 kgsl_smmu: iommu@5040000 { 1113 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sd 1114 compatible = "qcom,sdm630-smmu-v2",
1157 "qcom,ad 1115 "qcom,adreno-smmu", "qcom,smmu-v2";
1158 reg = <0x05040000 0x1 1116 reg = <0x05040000 0x10000>;
1159 1117
1160 /* 1118 /*
1161 * GX GDSC parent is 1119 * GX GDSC parent is CX. We need to bring up CX for SMMU
1162 * but we need both u 1120 * but we need both up for Adreno. On the other hand, we
1163 * need to manage the 1121 * need to manage the GX rpmpd domain in the adreno driver.
1164 * Enable CX/GX GDSCs 1122 * Enable CX/GX GDSCs here so that we can manage just the GX
1165 * RPM Power Domain i 1123 * RPM Power Domain in the Adreno driver.
1166 */ 1124 */
1167 power-domains = <&gpu 1125 power-domains = <&gpucc GPU_GX_GDSC>;
1168 clocks = <&gcc GCC_GP 1126 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1169 <&gcc GCC_BI 1127 <&gcc GCC_BIMC_GFX_CLK>,
1170 <&gcc GCC_GP 1128 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1171 clock-names = "iface" !! 1129 clock-names = "iface", "mem", "mem_iface";
1172 "mem", <<
1173 "mem_if <<
1174 #global-interrupts = 1130 #global-interrupts = <2>;
1175 #iommu-cells = <1>; 1131 #iommu-cells = <1>;
1176 1132
1177 interrupts = 1133 interrupts =
1178 <GIC_SPI 229 1134 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 231 1135 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1180 1136
1181 <GIC_SPI 329 1137 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 330 1138 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 331 1139 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 332 1140 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 116 1141 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 117 1142 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 349 1143 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 350 1144 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1189 1145
1190 status = "disabled"; 1146 status = "disabled";
1191 }; 1147 };
1192 1148
1193 gpucc: clock-controller@50650 1149 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gp 1150 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>; 1151 #clock-cells = <1>;
1196 #reset-cells = <1>; 1152 #reset-cells = <1>;
1197 #power-domain-cells = 1153 #power-domain-cells = <1>;
1198 reg = <0x05065000 0x9 1154 reg = <0x05065000 0x9038>;
1199 1155
1200 clocks = <&xo_board>, 1156 clocks = <&xo_board>,
1201 <&gcc GCC_GP 1157 <&gcc GCC_GPU_GPLL0_CLK>,
1202 <&gcc GCC_GP 1158 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1203 clock-names = "xo", 1159 clock-names = "xo",
1204 "gcc_gp 1160 "gcc_gpu_gpll0_clk",
1205 "gcc_gp 1161 "gcc_gpu_gpll0_div_clk";
1206 status = "disabled"; 1162 status = "disabled";
1207 }; 1163 };
1208 1164
1209 lpass_smmu: iommu@5100000 { 1165 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sd 1166 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 reg = <0x05100000 0x4 1167 reg = <0x05100000 0x40000>;
1212 #iommu-cells = <1>; 1168 #iommu-cells = <1>;
1213 1169
1214 #global-interrupts = 1170 #global-interrupts = <2>;
1215 interrupts = 1171 interrupts =
1216 <GIC_SPI 229 1172 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 231 1173 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1218 1174
1219 <GIC_SPI 226 1175 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 393 1176 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 394 1177 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 395 1178 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 396 1179 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 397 1180 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 398 1181 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 399 1182 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 400 1183 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 401 1184 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 402 1185 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 403 1186 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 137 1187 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 224 1188 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 225 1189 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 310 1190 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 404 1191 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1236 1192
1237 status = "disabled"; 1193 status = "disabled";
1238 }; 1194 };
1239 1195
1240 sram@290000 { 1196 sram@290000 {
1241 compatible = "qcom,rp 1197 compatible = "qcom,rpm-stats";
1242 reg = <0x00290000 0x1 1198 reg = <0x00290000 0x10000>;
1243 }; 1199 };
1244 1200
1245 spmi_bus: spmi@800f000 { 1201 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,sp 1202 compatible = "qcom,spmi-pmic-arb";
1247 reg = <0x0800f000 0x1 1203 reg = <0x0800f000 0x1000>,
1248 <0x08400000 0x1 1204 <0x08400000 0x1000000>,
1249 <0x09400000 0x1 1205 <0x09400000 0x1000000>,
1250 <0x0a400000 0x2 1206 <0x0a400000 0x220000>,
1251 <0x0800a000 0x3 1207 <0x0800a000 0x3000>;
1252 reg-names = "core", " 1208 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "pe 1209 interrupt-names = "periph_irq";
1254 interrupts = <GIC_SPI 1210 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1255 qcom,ee = <0>; 1211 qcom,ee = <0>;
1256 qcom,channel = <0>; 1212 qcom,channel = <0>;
1257 #address-cells = <2>; 1213 #address-cells = <2>;
1258 #size-cells = <0>; 1214 #size-cells = <0>;
1259 interrupt-controller; 1215 interrupt-controller;
1260 #interrupt-cells = <4 1216 #interrupt-cells = <4>;
1261 }; 1217 };
1262 1218
1263 usb3: usb@a8f8800 { 1219 usb3: usb@a8f8800 {
1264 compatible = "qcom,sd 1220 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1265 reg = <0x0a8f8800 0x4 1221 reg = <0x0a8f8800 0x400>;
1266 status = "disabled"; 1222 status = "disabled";
1267 #address-cells = <1>; 1223 #address-cells = <1>;
1268 #size-cells = <1>; 1224 #size-cells = <1>;
1269 ranges; 1225 ranges;
1270 1226
1271 clocks = <&gcc GCC_CF 1227 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1272 <&gcc GCC_US 1228 <&gcc GCC_USB30_MASTER_CLK>,
1273 <&gcc GCC_AG 1229 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1274 <&gcc GCC_US 1230 <&gcc GCC_USB30_SLEEP_CLK>,
1275 <&gcc GCC_US !! 1231 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
>> 1232 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1276 clock-names = "cfg_no 1233 clock-names = "cfg_noc",
1277 "core", 1234 "core",
1278 "iface" 1235 "iface",
1279 "sleep" 1236 "sleep",
1280 "mock_u !! 1237 "mock_utmi",
>> 1238 "bus";
1281 1239
1282 assigned-clocks = <&g 1240 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1283 <&g !! 1241 <&gcc GCC_USB30_MASTER_CLK>,
1284 assigned-clock-rates !! 1242 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1243 assigned-clock-rates = <19200000>, <120000000>,
>> 1244 <19200000>;
1285 1245
1286 interrupts = <GIC_SPI !! 1246 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI <<
1288 <GIC_SPI <<
1289 <GIC_SPI 1247 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1290 interrupt-names = "pw !! 1248 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1291 "qu <<
1292 "hs <<
1293 "ss <<
1294 1249
1295 power-domains = <&gcc 1250 power-domains = <&gcc USB_30_GDSC>;
>> 1251 qcom,select-utmi-as-pipe-clk;
1296 1252
1297 resets = <&gcc GCC_US 1253 resets = <&gcc GCC_USB_30_BCR>;
1298 1254
1299 usb3_dwc3: usb@a80000 1255 usb3_dwc3: usb@a800000 {
1300 compatible = 1256 compatible = "snps,dwc3";
1301 reg = <0x0a80 1257 reg = <0x0a800000 0xc8d0>;
1302 interrupts = 1258 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1303 snps,dis_u2_s 1259 snps,dis_u2_susphy_quirk;
1304 snps,dis_enbl 1260 snps,dis_enblslpm_quirk;
1305 snps,parkmode 1261 snps,parkmode-disable-ss-quirk;
1306 1262
1307 phys = <&qusb !! 1263 /*
1308 phy-names = " !! 1264 * SDM630 technically supports USB3 but I
>> 1265 * haven't seen any devices making use of it.
>> 1266 */
>> 1267 maximum-speed = "high-speed";
>> 1268 phys = <&qusb2phy0>;
>> 1269 phy-names = "usb2-phy";
1309 snps,hird-thr 1270 snps,hird-threshold = /bits/ 8 <0>;
1310 }; 1271 };
1311 }; 1272 };
1312 1273
1313 usb3_qmpphy: phy@c010000 { <<
1314 compatible = "qcom,sd <<
1315 reg = <0x0c010000 0x1 <<
1316 <<
1317 clocks = <&gcc GCC_US <<
1318 <&gcc GCC_US <<
1319 <&gcc GCC_US <<
1320 <&gcc GCC_US <<
1321 clock-names = "aux", <<
1322 "ref", <<
1323 "cfg_ah <<
1324 "pipe"; <<
1325 clock-output-names = <<
1326 #clock-cells = <0>; <<
1327 #phy-cells = <0>; <<
1328 <<
1329 resets = <&gcc GCC_US <<
1330 <&gcc GCC_US <<
1331 reset-names = "phy", <<
1332 "phy_ph <<
1333 <<
1334 qcom,tcsr-reg = <&tcs <<
1335 <<
1336 status = "disabled"; <<
1337 }; <<
1338 <<
1339 qusb2phy0: phy@c012000 { 1274 qusb2phy0: phy@c012000 {
1340 compatible = "qcom,sd 1275 compatible = "qcom,sdm660-qusb2-phy";
1341 reg = <0x0c012000 0x1 1276 reg = <0x0c012000 0x180>;
1342 #phy-cells = <0>; 1277 #phy-cells = <0>;
1343 1278
1344 clocks = <&gcc GCC_US 1279 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1345 <&gcc GCC_RX 1280 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1346 clock-names = "cfg_ah 1281 clock-names = "cfg_ahb", "ref";
1347 1282
1348 resets = <&gcc GCC_QU 1283 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1349 nvmem-cells = <&qusb2 1284 nvmem-cells = <&qusb2_hstx_trim>;
1350 status = "disabled"; 1285 status = "disabled";
1351 }; 1286 };
1352 1287
1353 qusb2phy1: phy@c014000 { 1288 qusb2phy1: phy@c014000 {
1354 compatible = "qcom,sd 1289 compatible = "qcom,sdm660-qusb2-phy";
1355 reg = <0x0c014000 0x1 1290 reg = <0x0c014000 0x180>;
1356 #phy-cells = <0>; 1291 #phy-cells = <0>;
1357 1292
1358 clocks = <&gcc GCC_US 1293 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1359 <&gcc GCC_RX 1294 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1360 clock-names = "cfg_ah 1295 clock-names = "cfg_ahb", "ref";
1361 1296
1362 resets = <&gcc GCC_QU 1297 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1363 nvmem-cells = <&qusb2 1298 nvmem-cells = <&qusb2_hstx_trim>;
1364 status = "disabled"; 1299 status = "disabled";
1365 }; 1300 };
1366 1301
1367 sdhc_2: mmc@c084000 { 1302 sdhc_2: mmc@c084000 {
1368 compatible = "qcom,sd 1303 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1369 reg = <0x0c084000 0x1 1304 reg = <0x0c084000 0x1000>;
1370 reg-names = "hc"; 1305 reg-names = "hc";
1371 1306
1372 interrupts = <GIC_SPI 1307 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_ 1308 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1374 interrupt-names = "hc 1309 interrupt-names = "hc_irq", "pwr_irq";
1375 1310
1376 bus-width = <4>; 1311 bus-width = <4>;
1377 1312
1378 clocks = <&gcc GCC_SD 1313 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1379 <&gcc 1314 <&gcc GCC_SDCC2_APPS_CLK>,
1380 <&xo_ 1315 <&xo_board>;
1381 clock-names = "iface" 1316 clock-names = "iface", "core", "xo";
1382 1317
1383 1318
1384 interconnects = <&a2n 1319 interconnects = <&a2noc 3 &a2noc 10>,
1385 <&gno 1320 <&gnoc 0 &cnoc 28>;
1386 interconnect-names = 1321 interconnect-names = "sdhc-ddr","cpu-sdhc";
1387 operating-points-v2 = 1322 operating-points-v2 = <&sdhc2_opp_table>;
1388 1323
1389 pinctrl-names = "defa 1324 pinctrl-names = "default", "sleep";
1390 pinctrl-0 = <&sdc2_st 1325 pinctrl-0 = <&sdc2_state_on>;
1391 pinctrl-1 = <&sdc2_st 1326 pinctrl-1 = <&sdc2_state_off>;
1392 power-domains = <&rpm 1327 power-domains = <&rpmpd SDM660_VDDCX>;
1393 1328
1394 status = "disabled"; 1329 status = "disabled";
1395 1330
1396 sdhc2_opp_table: opp- 1331 sdhc2_opp_table: opp-table {
1397 compatible = 1332 compatible = "operating-points-v2";
1398 1333
1399 opp-50000000 1334 opp-50000000 {
1400 opp-h 1335 opp-hz = /bits/ 64 <50000000>;
1401 requi 1336 required-opps = <&rpmpd_opp_low_svs>;
1402 opp-p 1337 opp-peak-kBps = <200000 140000>;
1403 opp-a 1338 opp-avg-kBps = <130718 133320>;
1404 }; 1339 };
1405 opp-10000000 1340 opp-100000000 {
1406 opp-h 1341 opp-hz = /bits/ 64 <100000000>;
1407 requi 1342 required-opps = <&rpmpd_opp_svs>;
1408 opp-p 1343 opp-peak-kBps = <250000 160000>;
1409 opp-a 1344 opp-avg-kBps = <196078 150000>;
1410 }; 1345 };
1411 opp-20000000 1346 opp-200000000 {
1412 opp-h 1347 opp-hz = /bits/ 64 <200000000>;
1413 requi 1348 required-opps = <&rpmpd_opp_nom>;
1414 opp-p 1349 opp-peak-kBps = <4096000 4096000>;
1415 opp-a 1350 opp-avg-kBps = <1338562 1338562>;
1416 }; 1351 };
1417 }; 1352 };
1418 }; 1353 };
1419 1354
1420 sdhc_1: mmc@c0c4000 { 1355 sdhc_1: mmc@c0c4000 {
1421 compatible = "qcom,sd 1356 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg = <0x0c0c4000 0x1 1357 reg = <0x0c0c4000 0x1000>,
1423 <0x0c0c5000 0x1 1358 <0x0c0c5000 0x1000>,
1424 <0x0c0c8000 0x8 1359 <0x0c0c8000 0x8000>;
1425 reg-names = "hc", "cq 1360 reg-names = "hc", "cqhci", "ice";
1426 1361
1427 interrupts = <GIC_SPI 1362 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_ 1363 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc 1364 interrupt-names = "hc_irq", "pwr_irq";
1430 1365
1431 clocks = <&gcc GCC_SD 1366 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1432 <&gcc GCC_SD 1367 <&gcc GCC_SDCC1_APPS_CLK>,
1433 <&xo_board>, 1368 <&xo_board>,
1434 <&gcc GCC_SD 1369 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1435 clock-names = "iface" 1370 clock-names = "iface", "core", "xo", "ice";
1436 1371
1437 interconnects = <&a2n 1372 interconnects = <&a2noc 2 &a2noc 10>,
1438 <&gno 1373 <&gnoc 0 &cnoc 27>;
1439 interconnect-names = 1374 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1440 operating-points-v2 = 1375 operating-points-v2 = <&sdhc1_opp_table>;
1441 pinctrl-names = "defa 1376 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_st 1377 pinctrl-0 = <&sdc1_state_on>;
1443 pinctrl-1 = <&sdc1_st 1378 pinctrl-1 = <&sdc1_state_off>;
1444 power-domains = <&rpm 1379 power-domains = <&rpmpd SDM660_VDDCX>;
1445 1380
1446 bus-width = <8>; 1381 bus-width = <8>;
1447 non-removable; 1382 non-removable;
1448 1383
1449 status = "disabled"; 1384 status = "disabled";
1450 1385
1451 sdhc1_opp_table: opp- 1386 sdhc1_opp_table: opp-table {
1452 compatible = 1387 compatible = "operating-points-v2";
1453 1388
1454 opp-50000000 1389 opp-50000000 {
1455 opp-h 1390 opp-hz = /bits/ 64 <50000000>;
1456 requi 1391 required-opps = <&rpmpd_opp_low_svs>;
1457 opp-p 1392 opp-peak-kBps = <200000 140000>;
1458 opp-a 1393 opp-avg-kBps = <130718 133320>;
1459 }; 1394 };
1460 opp-100000000 1395 opp-100000000 {
1461 opp-h 1396 opp-hz = /bits/ 64 <100000000>;
1462 requi 1397 required-opps = <&rpmpd_opp_svs>;
1463 opp-p 1398 opp-peak-kBps = <250000 160000>;
1464 opp-a 1399 opp-avg-kBps = <196078 150000>;
1465 }; 1400 };
1466 opp-384000000 1401 opp-384000000 {
1467 opp-h 1402 opp-hz = /bits/ 64 <384000000>;
1468 requi 1403 required-opps = <&rpmpd_opp_nom>;
1469 opp-p 1404 opp-peak-kBps = <4096000 4096000>;
1470 opp-a 1405 opp-avg-kBps = <1338562 1338562>;
1471 }; 1406 };
1472 }; 1407 };
1473 }; 1408 };
1474 1409
1475 usb2: usb@c2f8800 { 1410 usb2: usb@c2f8800 {
1476 compatible = "qcom,sd 1411 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1477 reg = <0x0c2f8800 0x4 1412 reg = <0x0c2f8800 0x400>;
1478 status = "disabled"; 1413 status = "disabled";
1479 #address-cells = <1>; 1414 #address-cells = <1>;
1480 #size-cells = <1>; 1415 #size-cells = <1>;
1481 ranges; 1416 ranges;
1482 1417
1483 clocks = <&gcc GCC_CF 1418 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1484 <&gcc GCC_US 1419 <&gcc GCC_USB20_MASTER_CLK>,
1485 <&gcc GCC_US !! 1420 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1486 <&gcc GCC_US !! 1421 <&gcc GCC_USB20_SLEEP_CLK>;
1487 clock-names = "cfg_no 1422 clock-names = "cfg_noc", "core",
1488 "sleep" !! 1423 "mock_utmi", "sleep";
1489 1424
1490 assigned-clocks = <&g 1425 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1491 <&g 1426 <&gcc GCC_USB20_MASTER_CLK>;
1492 assigned-clock-rates 1427 assigned-clock-rates = <19200000>, <60000000>;
1493 1428
1494 interrupts = <GIC_SPI !! 1429 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1495 <GIC_SPI !! 1430 interrupt-names = "hs_phy_irq";
1496 <GIC_SPI <<
1497 interrupt-names = "pw <<
1498 "qu <<
1499 "hs <<
1500 1431
1501 qcom,select-utmi-as-p 1432 qcom,select-utmi-as-pipe-clk;
1502 1433
1503 resets = <&gcc GCC_US 1434 resets = <&gcc GCC_USB_20_BCR>;
1504 1435
1505 usb2_dwc3: usb@c20000 1436 usb2_dwc3: usb@c200000 {
1506 compatible = 1437 compatible = "snps,dwc3";
1507 reg = <0x0c20 1438 reg = <0x0c200000 0xc8d0>;
1508 interrupts = 1439 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1509 snps,dis_u2_s 1440 snps,dis_u2_susphy_quirk;
1510 snps,dis_enbl 1441 snps,dis_enblslpm_quirk;
1511 1442
1512 /* This is th 1443 /* This is the HS-only host */
1513 maximum-speed 1444 maximum-speed = "high-speed";
1514 phys = <&qusb 1445 phys = <&qusb2phy1>;
1515 phy-names = " 1446 phy-names = "usb2-phy";
1516 snps,hird-thr 1447 snps,hird-threshold = /bits/ 8 <0>;
1517 }; 1448 };
1518 }; 1449 };
1519 1450
1520 mmcc: clock-controller@c8c000 1451 mmcc: clock-controller@c8c0000 {
1521 compatible = "qcom,mm 1452 compatible = "qcom,mmcc-sdm630";
1522 reg = <0x0c8c0000 0x4 1453 reg = <0x0c8c0000 0x40000>;
1523 #clock-cells = <1>; 1454 #clock-cells = <1>;
1524 #reset-cells = <1>; 1455 #reset-cells = <1>;
1525 #power-domain-cells = 1456 #power-domain-cells = <1>;
1526 clock-names = "xo", 1457 clock-names = "xo",
1527 "slee 1458 "sleep_clk",
1528 "gpll 1459 "gpll0",
1529 "gpll 1460 "gpll0_div",
1530 "dsi0 1461 "dsi0pll",
1531 "dsi0 1462 "dsi0pllbyte",
1532 "dsi1 1463 "dsi1pll",
1533 "dsi1 1464 "dsi1pllbyte",
1534 "dp_l 1465 "dp_link_2x_clk_divsel_five",
1535 "dp_v 1466 "dp_vco_divided_clk_src_mux";
1536 clocks = <&rpmcc RPM_ 1467 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1537 <&sle 1468 <&sleep_clk>,
1538 <&gcc 1469 <&gcc GCC_MMSS_GPLL0_CLK>,
1539 <&gcc 1470 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1540 <&mds 1471 <&mdss_dsi0_phy 1>,
1541 <&mds 1472 <&mdss_dsi0_phy 0>,
1542 <0>, 1473 <0>,
1543 <0>, 1474 <0>,
1544 <0>, 1475 <0>,
1545 <0>; 1476 <0>;
1546 }; 1477 };
1547 1478
1548 mdss: display-subsystem@c9000 1479 mdss: display-subsystem@c900000 {
1549 compatible = "qcom,md 1480 compatible = "qcom,mdss";
1550 reg = <0x0c900000 0x1 1481 reg = <0x0c900000 0x1000>,
1551 <0x0c9b0000 0x1 1482 <0x0c9b0000 0x1040>;
1552 reg-names = "mdss_phy 1483 reg-names = "mdss_phys", "vbif_phys";
1553 1484
1554 power-domains = <&mmc 1485 power-domains = <&mmcc MDSS_GDSC>;
1555 1486
1556 clocks = <&mmcc MDSS_ 1487 clocks = <&mmcc MDSS_AHB_CLK>,
1557 <&mmcc MDSS_ 1488 <&mmcc MDSS_AXI_CLK>,
1558 <&mmcc MDSS_ 1489 <&mmcc MDSS_VSYNC_CLK>,
1559 <&mmcc MDSS_ 1490 <&mmcc MDSS_MDP_CLK>;
1560 clock-names = "iface" 1491 clock-names = "iface",
1561 "bus", 1492 "bus",
1562 "vsync" 1493 "vsync",
1563 "core"; 1494 "core";
1564 1495
1565 interrupts = <GIC_SPI 1496 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1566 1497
1567 interrupt-controller; 1498 interrupt-controller;
1568 #interrupt-cells = <1 1499 #interrupt-cells = <1>;
1569 1500
1570 #address-cells = <1>; 1501 #address-cells = <1>;
1571 #size-cells = <1>; 1502 #size-cells = <1>;
1572 ranges; 1503 ranges;
1573 status = "disabled"; 1504 status = "disabled";
1574 1505
1575 mdp: display-controll 1506 mdp: display-controller@c901000 {
1576 compatible = 1507 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1577 reg = <0x0c90 1508 reg = <0x0c901000 0x89000>;
1578 reg-names = " 1509 reg-names = "mdp_phys";
1579 1510
1580 interrupt-par 1511 interrupt-parent = <&mdss>;
1581 interrupts = 1512 interrupts = <0>;
1582 1513
1583 assigned-cloc 1514 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1584 1515 <&mmcc MDSS_VSYNC_CLK>;
1585 assigned-cloc 1516 assigned-clock-rates = <300000000>,
1586 1517 <19200000>;
1587 clocks = <&mm 1518 clocks = <&mmcc MDSS_AHB_CLK>,
1588 <&mm 1519 <&mmcc MDSS_AXI_CLK>,
1589 <&mm 1520 <&mmcc MDSS_MDP_CLK>,
1590 <&mm 1521 <&mmcc MDSS_VSYNC_CLK>;
1591 clock-names = 1522 clock-names = "iface",
1592 1523 "bus",
1593 1524 "core",
1594 1525 "vsync";
1595 1526
1596 interconnects 1527 interconnects = <&mnoc 2 &bimc 5>,
1597 1528 <&mnoc 3 &bimc 5>,
1598 1529 <&gnoc 0 &mnoc 17>;
1599 interconnect- 1530 interconnect-names = "mdp0-mem",
1600 1531 "mdp1-mem",
1601 1532 "rotator-mem";
1602 iommus = <&mm 1533 iommus = <&mmss_smmu 0>;
1603 operating-poi 1534 operating-points-v2 = <&mdp_opp_table>;
1604 power-domains 1535 power-domains = <&rpmpd SDM660_VDDCX>;
1605 1536
1606 ports { 1537 ports {
1607 #addr 1538 #address-cells = <1>;
1608 #size 1539 #size-cells = <0>;
1609 1540
1610 port@ 1541 port@0 {
1611 1542 reg = <0>;
1612 1543 mdp5_intf1_out: endpoint {
1613 1544 remote-endpoint = <&mdss_dsi0_in>;
1614 1545 };
1615 }; 1546 };
1616 }; 1547 };
1617 1548
1618 mdp_opp_table 1549 mdp_opp_table: opp-table {
1619 compa 1550 compatible = "operating-points-v2";
1620 1551
1621 opp-1 1552 opp-150000000 {
1622 1553 opp-hz = /bits/ 64 <150000000>;
1623 1554 opp-peak-kBps = <320000 320000 76800>;
1624 1555 required-opps = <&rpmpd_opp_low_svs>;
1625 }; 1556 };
1626 opp-2 1557 opp-275000000 {
1627 1558 opp-hz = /bits/ 64 <275000000>;
1628 1559 opp-peak-kBps = <6400000 6400000 160000>;
1629 1560 required-opps = <&rpmpd_opp_svs>;
1630 }; 1561 };
1631 opp-3 1562 opp-300000000 {
1632 1563 opp-hz = /bits/ 64 <300000000>;
1633 1564 opp-peak-kBps = <6400000 6400000 190000>;
1634 1565 required-opps = <&rpmpd_opp_svs_plus>;
1635 }; 1566 };
1636 opp-3 1567 opp-330000000 {
1637 1568 opp-hz = /bits/ 64 <330000000>;
1638 1569 opp-peak-kBps = <6400000 6400000 240000>;
1639 1570 required-opps = <&rpmpd_opp_nom>;
1640 }; 1571 };
1641 opp-4 1572 opp-412500000 {
1642 1573 opp-hz = /bits/ 64 <412500000>;
1643 1574 opp-peak-kBps = <6400000 6400000 320000>;
1644 1575 required-opps = <&rpmpd_opp_turbo>;
1645 }; 1576 };
1646 }; 1577 };
1647 }; 1578 };
1648 1579
1649 mdss_dsi0: dsi@c99400 1580 mdss_dsi0: dsi@c994000 {
1650 compatible = 1581 compatible = "qcom,sdm660-dsi-ctrl",
1651 1582 "qcom,mdss-dsi-ctrl";
1652 reg = <0x0c99 1583 reg = <0x0c994000 0x400>;
1653 reg-names = " 1584 reg-names = "dsi_ctrl";
1654 1585
1655 operating-poi 1586 operating-points-v2 = <&dsi_opp_table>;
1656 power-domains 1587 power-domains = <&rpmpd SDM660_VDDCX>;
1657 1588
1658 interrupt-par 1589 interrupt-parent = <&mdss>;
1659 interrupts = 1590 interrupts = <4>;
1660 1591
1661 assigned-cloc 1592 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1662 1593 <&mmcc PCLK0_CLK_SRC>;
1663 assigned-cloc 1594 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1664 1595 <&mdss_dsi0_phy 1>;
1665 1596
1666 clocks = <&mm 1597 clocks = <&mmcc MDSS_MDP_CLK>,
1667 <&mm 1598 <&mmcc MDSS_BYTE0_CLK>,
1668 <&mm 1599 <&mmcc MDSS_BYTE0_INTF_CLK>,
1669 <&mm 1600 <&mmcc MNOC_AHB_CLK>,
1670 <&mm 1601 <&mmcc MDSS_AHB_CLK>,
1671 <&mm 1602 <&mmcc MDSS_AXI_CLK>,
1672 <&mm 1603 <&mmcc MISC_AHB_CLK>,
1673 <&mm 1604 <&mmcc MDSS_PCLK0_CLK>,
1674 <&mm 1605 <&mmcc MDSS_ESC0_CLK>;
1675 clock-names = 1606 clock-names = "mdp_core",
1676 1607 "byte",
1677 1608 "byte_intf",
1678 1609 "mnoc",
1679 1610 "iface",
1680 1611 "bus",
1681 1612 "core_mmss",
1682 1613 "pixel",
1683 1614 "core";
1684 1615
1685 phys = <&mdss 1616 phys = <&mdss_dsi0_phy>;
1686 1617
1687 status = "dis 1618 status = "disabled";
1688 1619
1689 ports { 1620 ports {
1690 #addr 1621 #address-cells = <1>;
1691 #size 1622 #size-cells = <0>;
1692 1623
1693 port@ 1624 port@0 {
1694 1625 reg = <0>;
1695 1626 mdss_dsi0_in: endpoint {
1696 1627 remote-endpoint = <&mdp5_intf1_out>;
1697 1628 };
1698 }; 1629 };
1699 1630
1700 port@ 1631 port@1 {
1701 1632 reg = <1>;
1702 1633 mdss_dsi0_out: endpoint {
1703 1634 };
1704 }; 1635 };
1705 }; 1636 };
1706 }; 1637 };
1707 1638
1708 mdss_dsi0_phy: phy@c9 1639 mdss_dsi0_phy: phy@c994400 {
1709 compatible = 1640 compatible = "qcom,dsi-phy-14nm-660";
1710 reg = <0x0c99 1641 reg = <0x0c994400 0x100>,
1711 <0x0c99 1642 <0x0c994500 0x300>,
1712 <0x0c99 1643 <0x0c994800 0x188>;
1713 reg-names = " 1644 reg-names = "dsi_phy",
1714 " 1645 "dsi_phy_lane",
1715 " 1646 "dsi_pll";
1716 1647
1717 #clock-cells 1648 #clock-cells = <1>;
1718 #phy-cells = 1649 #phy-cells = <0>;
1719 1650
1720 clocks = <&mm 1651 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1721 clock-names = 1652 clock-names = "iface", "ref";
1722 status = "dis 1653 status = "disabled";
1723 }; 1654 };
1724 }; 1655 };
1725 1656
1726 blsp1_dma: dma-controller@c14 1657 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,ba 1658 compatible = "qcom,bam-v1.7.0";
1728 reg = <0x0c144000 0x1 1659 reg = <0x0c144000 0x1f000>;
1729 interrupts = <GIC_SPI 1660 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1730 clocks = <&gcc GCC_BL 1661 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_cl 1662 clock-names = "bam_clk";
1732 #dma-cells = <1>; 1663 #dma-cells = <1>;
1733 qcom,ee = <0>; 1664 qcom,ee = <0>;
1734 qcom,controlled-remot 1665 qcom,controlled-remotely;
1735 num-channels = <18>; 1666 num-channels = <18>;
1736 qcom,num-ees = <4>; 1667 qcom,num-ees = <4>;
1737 }; 1668 };
1738 1669
1739 blsp1_uart1: serial@c16f000 { 1670 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,ms 1671 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1741 reg = <0x0c16f000 0x2 1672 reg = <0x0c16f000 0x200>;
1742 interrupts = <GIC_SPI 1673 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&gcc GCC_BL 1674 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1744 <&gcc GCC_BL 1675 <&gcc GCC_BLSP1_AHB_CLK>;
1745 clock-names = "core", 1676 clock-names = "core", "iface";
1746 dmas = <&blsp1_dma 0> 1677 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1747 dma-names = "tx", "rx 1678 dma-names = "tx", "rx";
1748 pinctrl-names = "defa 1679 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_u 1680 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_u 1681 pinctrl-1 = <&blsp1_uart1_sleep>;
1751 status = "disabled"; 1682 status = "disabled";
1752 }; 1683 };
1753 1684
1754 blsp1_uart2: serial@c170000 { 1685 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,ms 1686 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 reg = <0x0c170000 0x1 1687 reg = <0x0c170000 0x1000>;
1757 interrupts = <GIC_SPI 1688 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&gcc GCC_BL 1689 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1759 <&gcc GCC_BL 1690 <&gcc GCC_BLSP1_AHB_CLK>;
1760 clock-names = "core", 1691 clock-names = "core", "iface";
1761 dmas = <&blsp1_dma 2> 1692 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1762 dma-names = "tx", "rx 1693 dma-names = "tx", "rx";
1763 pinctrl-names = "defa 1694 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_u 1695 pinctrl-0 = <&blsp1_uart2_default>;
1765 status = "disabled"; 1696 status = "disabled";
1766 }; 1697 };
1767 1698
1768 blsp_i2c1: i2c@c175000 { 1699 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2 1700 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c175000 0x6 1701 reg = <0x0c175000 0x600>;
1771 interrupts = <GIC_SPI 1702 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1772 1703
1773 clocks = <&gcc GCC_BL 1704 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1774 <&gcc 1705 <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1706 clock-names = "core", "iface";
1776 clock-frequency = <40 1707 clock-frequency = <400000>;
1777 dmas = <&blsp1_dma 4> 1708 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1778 dma-names = "tx", "rx 1709 dma-names = "tx", "rx";
1779 1710
1780 pinctrl-names = "defa 1711 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_de 1712 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sl 1713 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>; 1714 #address-cells = <1>;
1784 #size-cells = <0>; 1715 #size-cells = <0>;
1785 status = "disabled"; 1716 status = "disabled";
1786 }; 1717 };
1787 1718
1788 blsp_i2c2: i2c@c176000 { 1719 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2 1720 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c176000 0x6 1721 reg = <0x0c176000 0x600>;
1791 interrupts = <GIC_SPI 1722 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1792 1723
1793 clocks = <&gcc GCC_BL 1724 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1794 <&gcc GCC_BL 1725 <&gcc GCC_BLSP1_AHB_CLK>;
1795 clock-names = "core", 1726 clock-names = "core", "iface";
1796 clock-frequency = <40 1727 clock-frequency = <400000>;
1797 dmas = <&blsp1_dma 6> 1728 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1798 dma-names = "tx", "rx 1729 dma-names = "tx", "rx";
1799 1730
1800 pinctrl-names = "defa 1731 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_de 1732 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sl 1733 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>; 1734 #address-cells = <1>;
1804 #size-cells = <0>; 1735 #size-cells = <0>;
1805 status = "disabled"; 1736 status = "disabled";
1806 }; 1737 };
1807 1738
1808 blsp_i2c3: i2c@c177000 { 1739 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2 1740 compatible = "qcom,i2c-qup-v2.2.1";
1810 reg = <0x0c177000 0x6 1741 reg = <0x0c177000 0x600>;
1811 interrupts = <GIC_SPI 1742 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1812 1743
1813 clocks = <&gcc GCC_BL 1744 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1814 <&gcc GCC_BL 1745 <&gcc GCC_BLSP1_AHB_CLK>;
1815 clock-names = "core", 1746 clock-names = "core", "iface";
1816 clock-frequency = <40 1747 clock-frequency = <400000>;
1817 dmas = <&blsp1_dma 8> 1748 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1818 dma-names = "tx", "rx 1749 dma-names = "tx", "rx";
1819 1750
1820 pinctrl-names = "defa 1751 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_de 1752 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sl 1753 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>; 1754 #address-cells = <1>;
1824 #size-cells = <0>; 1755 #size-cells = <0>;
1825 status = "disabled"; 1756 status = "disabled";
1826 }; 1757 };
1827 1758
1828 blsp_i2c4: i2c@c178000 { 1759 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2 1760 compatible = "qcom,i2c-qup-v2.2.1";
1830 reg = <0x0c178000 0x6 1761 reg = <0x0c178000 0x600>;
1831 interrupts = <GIC_SPI 1762 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1832 1763
1833 clocks = <&gcc GCC_BL 1764 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1834 <&gcc GCC_BL 1765 <&gcc GCC_BLSP1_AHB_CLK>;
1835 clock-names = "core", 1766 clock-names = "core", "iface";
1836 clock-frequency = <40 1767 clock-frequency = <400000>;
1837 dmas = <&blsp1_dma 10 1768 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1838 dma-names = "tx", "rx 1769 dma-names = "tx", "rx";
1839 1770
1840 pinctrl-names = "defa 1771 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_de 1772 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sl 1773 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>; 1774 #address-cells = <1>;
1844 #size-cells = <0>; 1775 #size-cells = <0>;
1845 status = "disabled"; 1776 status = "disabled";
1846 }; 1777 };
1847 1778
1848 blsp2_dma: dma-controller@c18 1779 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,ba 1780 compatible = "qcom,bam-v1.7.0";
1850 reg = <0x0c184000 0x1 1781 reg = <0x0c184000 0x1f000>;
1851 interrupts = <GIC_SPI 1782 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&gcc GCC_BL 1783 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_cl 1784 clock-names = "bam_clk";
1854 #dma-cells = <1>; 1785 #dma-cells = <1>;
1855 qcom,ee = <0>; 1786 qcom,ee = <0>;
1856 qcom,controlled-remot 1787 qcom,controlled-remotely;
1857 num-channels = <18>; 1788 num-channels = <18>;
1858 qcom,num-ees = <4>; 1789 qcom,num-ees = <4>;
1859 }; 1790 };
1860 1791
1861 blsp2_uart1: serial@c1af000 { 1792 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,ms 1793 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x0c1af000 0x2 1794 reg = <0x0c1af000 0x200>;
1864 interrupts = <GIC_SPI 1795 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BL 1796 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1866 <&gcc GCC_BL 1797 <&gcc GCC_BLSP2_AHB_CLK>;
1867 clock-names = "core", 1798 clock-names = "core", "iface";
1868 dmas = <&blsp2_dma 0> 1799 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1869 dma-names = "tx", "rx 1800 dma-names = "tx", "rx";
1870 pinctrl-names = "defa 1801 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_u 1802 pinctrl-0 = <&blsp2_uart1_default>;
1872 pinctrl-1 = <&blsp2_u 1803 pinctrl-1 = <&blsp2_uart1_sleep>;
1873 status = "disabled"; 1804 status = "disabled";
1874 }; 1805 };
1875 1806
1876 blsp_i2c5: i2c@c1b5000 { 1807 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2 1808 compatible = "qcom,i2c-qup-v2.2.1";
1878 reg = <0x0c1b5000 0x6 1809 reg = <0x0c1b5000 0x600>;
1879 interrupts = <GIC_SPI 1810 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1880 1811
1881 clocks = <&gcc GCC_BL 1812 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1882 <&gcc GCC_BL 1813 <&gcc GCC_BLSP2_AHB_CLK>;
1883 clock-names = "core", 1814 clock-names = "core", "iface";
1884 clock-frequency = <40 1815 clock-frequency = <400000>;
1885 dmas = <&blsp2_dma 4> 1816 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1886 dma-names = "tx", "rx 1817 dma-names = "tx", "rx";
1887 1818
1888 pinctrl-names = "defa 1819 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_de 1820 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sl 1821 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>; 1822 #address-cells = <1>;
1892 #size-cells = <0>; 1823 #size-cells = <0>;
1893 status = "disabled"; 1824 status = "disabled";
1894 }; 1825 };
1895 1826
1896 blsp_i2c6: i2c@c1b6000 { 1827 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2 1828 compatible = "qcom,i2c-qup-v2.2.1";
1898 reg = <0x0c1b6000 0x6 1829 reg = <0x0c1b6000 0x600>;
1899 interrupts = <GIC_SPI 1830 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1900 1831
1901 clocks = <&gcc GCC_BL 1832 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1902 <&gcc GCC_BL 1833 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", 1834 clock-names = "core", "iface";
1904 clock-frequency = <40 1835 clock-frequency = <400000>;
1905 dmas = <&blsp2_dma 6> 1836 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1906 dma-names = "tx", "rx 1837 dma-names = "tx", "rx";
1907 1838
1908 pinctrl-names = "defa 1839 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_de 1840 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sl 1841 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>; 1842 #address-cells = <1>;
1912 #size-cells = <0>; 1843 #size-cells = <0>;
1913 status = "disabled"; 1844 status = "disabled";
1914 }; 1845 };
1915 1846
1916 blsp_i2c7: i2c@c1b7000 { 1847 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2 1848 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x0c1b7000 0x6 1849 reg = <0x0c1b7000 0x600>;
1919 interrupts = <GIC_SPI 1850 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1920 1851
1921 clocks = <&gcc GCC_BL 1852 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1922 <&gcc GCC_BL 1853 <&gcc GCC_BLSP2_AHB_CLK>;
1923 clock-names = "core", 1854 clock-names = "core", "iface";
1924 clock-frequency = <40 1855 clock-frequency = <400000>;
1925 dmas = <&blsp2_dma 8> 1856 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1926 dma-names = "tx", "rx 1857 dma-names = "tx", "rx";
1927 1858
1928 pinctrl-names = "defa 1859 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_de 1860 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sl 1861 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>; 1862 #address-cells = <1>;
1932 #size-cells = <0>; 1863 #size-cells = <0>;
1933 status = "disabled"; 1864 status = "disabled";
1934 }; 1865 };
1935 1866
1936 blsp_i2c8: i2c@c1b8000 { 1867 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2 1868 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x0c1b8000 0x6 1869 reg = <0x0c1b8000 0x600>;
1939 interrupts = <GIC_SPI 1870 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1940 1871
1941 clocks = <&gcc GCC_BL 1872 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1942 <&gcc GCC_BL 1873 <&gcc GCC_BLSP2_AHB_CLK>;
1943 clock-names = "core", 1874 clock-names = "core", "iface";
1944 clock-frequency = <40 1875 clock-frequency = <400000>;
1945 dmas = <&blsp2_dma 10 1876 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1946 dma-names = "tx", "rx 1877 dma-names = "tx", "rx";
1947 1878
1948 pinctrl-names = "defa 1879 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_de 1880 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sl 1881 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>; 1882 #address-cells = <1>;
1952 #size-cells = <0>; 1883 #size-cells = <0>;
1953 status = "disabled"; 1884 status = "disabled";
1954 }; 1885 };
1955 1886
1956 sram@146bf000 { 1887 sram@146bf000 {
1957 compatible = "qcom,sd 1888 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1958 reg = <0x146bf000 0x1 1889 reg = <0x146bf000 0x1000>;
1959 1890
1960 #address-cells = <1>; 1891 #address-cells = <1>;
1961 #size-cells = <1>; 1892 #size-cells = <1>;
1962 1893
1963 ranges = <0 0x146bf00 1894 ranges = <0 0x146bf000 0x1000>;
1964 1895
1965 pil-reloc@94c { 1896 pil-reloc@94c {
1966 compatible = 1897 compatible = "qcom,pil-reloc-info";
1967 reg = <0x94c 1898 reg = <0x94c 0xc8>;
1968 }; 1899 };
1969 }; 1900 };
1970 1901
1971 camss: camss@ca00020 { 1902 camss: camss@ca00020 {
1972 compatible = "qcom,sd 1903 compatible = "qcom,sdm660-camss";
1973 reg = <0x0ca00020 0x1 1904 reg = <0x0ca00020 0x10>,
1974 <0x0ca30000 0x1 1905 <0x0ca30000 0x100>,
1975 <0x0ca30400 0x1 1906 <0x0ca30400 0x100>,
1976 <0x0ca30800 0x1 1907 <0x0ca30800 0x100>,
1977 <0x0ca30c00 0x1 1908 <0x0ca30c00 0x100>,
1978 <0x0c824000 0x1 1909 <0x0c824000 0x1000>,
1979 <0x0ca00120 0x4 1910 <0x0ca00120 0x4>,
1980 <0x0c825000 0x1 1911 <0x0c825000 0x1000>,
1981 <0x0ca00124 0x4 1912 <0x0ca00124 0x4>,
1982 <0x0c826000 0x1 1913 <0x0c826000 0x1000>,
1983 <0x0ca00128 0x4 1914 <0x0ca00128 0x4>,
1984 <0x0ca31000 0x5 1915 <0x0ca31000 0x500>,
1985 <0x0ca10000 0x1 1916 <0x0ca10000 0x1000>,
1986 <0x0ca14000 0x1 1917 <0x0ca14000 0x1000>;
1987 reg-names = "csi_clk_ 1918 reg-names = "csi_clk_mux",
1988 "csid0", 1919 "csid0",
1989 "csid1", 1920 "csid1",
1990 "csid2", 1921 "csid2",
1991 "csid3", 1922 "csid3",
1992 "csiphy0" 1923 "csiphy0",
1993 "csiphy0_ 1924 "csiphy0_clk_mux",
1994 "csiphy1" 1925 "csiphy1",
1995 "csiphy1_ 1926 "csiphy1_clk_mux",
1996 "csiphy2" 1927 "csiphy2",
1997 "csiphy2_ 1928 "csiphy2_clk_mux",
1998 "ispif", 1929 "ispif",
1999 "vfe0", 1930 "vfe0",
2000 "vfe1"; 1931 "vfe1";
2001 interrupts = <GIC_SPI 1932 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2002 <GIC_SPI 1933 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2003 <GIC_SPI 1934 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2004 <GIC_SPI 1935 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2005 <GIC_SPI 1936 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2006 <GIC_SPI 1937 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2007 <GIC_SPI 1938 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2008 <GIC_SPI 1939 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2009 <GIC_SPI 1940 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2010 <GIC_SPI 1941 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2011 interrupt-names = "cs 1942 interrupt-names = "csid0",
2012 "cs 1943 "csid1",
2013 "cs 1944 "csid2",
2014 "cs 1945 "csid3",
2015 "cs 1946 "csiphy0",
2016 "cs 1947 "csiphy1",
2017 "cs 1948 "csiphy2",
2018 "is 1949 "ispif",
2019 "vf 1950 "vfe0",
2020 "vf 1951 "vfe1";
2021 clocks = <&mmcc CAMSS 1952 clocks = <&mmcc CAMSS_AHB_CLK>,
2022 <&mmcc CAMSS 1953 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2023 <&mmcc CAMSS 1954 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2024 <&mmcc CAMSS 1955 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2025 <&mmcc CAMSS 1956 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2026 <&mmcc CAMSS 1957 <&mmcc CAMSS_CSI0_AHB_CLK>,
2027 <&mmcc CAMSS 1958 <&mmcc CAMSS_CSI0_CLK>,
2028 <&mmcc CAMSS 1959 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2029 <&mmcc CAMSS 1960 <&mmcc CAMSS_CSI0PIX_CLK>,
2030 <&mmcc CAMSS 1961 <&mmcc CAMSS_CSI0RDI_CLK>,
2031 <&mmcc CAMSS 1962 <&mmcc CAMSS_CSI1_AHB_CLK>,
2032 <&mmcc CAMSS 1963 <&mmcc CAMSS_CSI1_CLK>,
2033 <&mmcc CAMSS 1964 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2034 <&mmcc CAMSS 1965 <&mmcc CAMSS_CSI1PIX_CLK>,
2035 <&mmcc CAMSS 1966 <&mmcc CAMSS_CSI1RDI_CLK>,
2036 <&mmcc CAMSS 1967 <&mmcc CAMSS_CSI2_AHB_CLK>,
2037 <&mmcc CAMSS 1968 <&mmcc CAMSS_CSI2_CLK>,
2038 <&mmcc CAMSS 1969 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2039 <&mmcc CAMSS 1970 <&mmcc CAMSS_CSI2PIX_CLK>,
2040 <&mmcc CAMSS 1971 <&mmcc CAMSS_CSI2RDI_CLK>,
2041 <&mmcc CAMSS 1972 <&mmcc CAMSS_CSI3_AHB_CLK>,
2042 <&mmcc CAMSS 1973 <&mmcc CAMSS_CSI3_CLK>,
2043 <&mmcc CAMSS 1974 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2044 <&mmcc CAMSS 1975 <&mmcc CAMSS_CSI3PIX_CLK>,
2045 <&mmcc CAMSS 1976 <&mmcc CAMSS_CSI3RDI_CLK>,
2046 <&mmcc CAMSS 1977 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2047 <&mmcc CAMSS 1978 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2048 <&mmcc CAMSS 1979 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2049 <&mmcc CSIPH 1980 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2050 <&mmcc CAMSS 1981 <&mmcc CAMSS_CSI_VFE0_CLK>,
2051 <&mmcc CAMSS 1982 <&mmcc CAMSS_CSI_VFE1_CLK>,
2052 <&mmcc CAMSS 1983 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2053 <&mmcc THROT 1984 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2054 <&mmcc CAMSS 1985 <&mmcc CAMSS_TOP_AHB_CLK>,
2055 <&mmcc CAMSS 1986 <&mmcc CAMSS_VFE0_AHB_CLK>,
2056 <&mmcc CAMSS 1987 <&mmcc CAMSS_VFE0_CLK>,
2057 <&mmcc CAMSS 1988 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2058 <&mmcc CAMSS 1989 <&mmcc CAMSS_VFE1_AHB_CLK>,
2059 <&mmcc CAMSS 1990 <&mmcc CAMSS_VFE1_CLK>,
2060 <&mmcc CAMSS 1991 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2061 <&mmcc CAMSS 1992 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2062 <&mmcc CAMSS 1993 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2063 clock-names = "ahb", 1994 clock-names = "ahb",
2064 "cphy_c 1995 "cphy_csid0",
2065 "cphy_c 1996 "cphy_csid1",
2066 "cphy_c 1997 "cphy_csid2",
2067 "cphy_c 1998 "cphy_csid3",
2068 "csi0_a 1999 "csi0_ahb",
2069 "csi0", 2000 "csi0",
2070 "csi0_p 2001 "csi0_phy",
2071 "csi0_p 2002 "csi0_pix",
2072 "csi0_r 2003 "csi0_rdi",
2073 "csi1_a 2004 "csi1_ahb",
2074 "csi1", 2005 "csi1",
2075 "csi1_p 2006 "csi1_phy",
2076 "csi1_p 2007 "csi1_pix",
2077 "csi1_r 2008 "csi1_rdi",
2078 "csi2_a 2009 "csi2_ahb",
2079 "csi2", 2010 "csi2",
2080 "csi2_p 2011 "csi2_phy",
2081 "csi2_p 2012 "csi2_pix",
2082 "csi2_r 2013 "csi2_rdi",
2083 "csi3_a 2014 "csi3_ahb",
2084 "csi3", 2015 "csi3",
2085 "csi3_p 2016 "csi3_phy",
2086 "csi3_p 2017 "csi3_pix",
2087 "csi3_r 2018 "csi3_rdi",
2088 "csiphy 2019 "csiphy0_timer",
2089 "csiphy 2020 "csiphy1_timer",
2090 "csiphy 2021 "csiphy2_timer",
2091 "csiphy 2022 "csiphy_ahb2crif",
2092 "csi_vf 2023 "csi_vfe0",
2093 "csi_vf 2024 "csi_vfe1",
2094 "ispif_ 2025 "ispif_ahb",
2095 "thrott 2026 "throttle_axi",
2096 "top_ah 2027 "top_ahb",
2097 "vfe0_a 2028 "vfe0_ahb",
2098 "vfe0", 2029 "vfe0",
2099 "vfe0_s 2030 "vfe0_stream",
2100 "vfe1_a 2031 "vfe1_ahb",
2101 "vfe1", 2032 "vfe1",
2102 "vfe1_s 2033 "vfe1_stream",
2103 "vfe_ah 2034 "vfe_ahb",
2104 "vfe_ax 2035 "vfe_axi";
2105 interconnects = <&mno 2036 interconnects = <&mnoc 5 &bimc 5>;
2106 interconnect-names = 2037 interconnect-names = "vfe-mem";
2107 iommus = <&mmss_smmu 2038 iommus = <&mmss_smmu 0xc00>,
2108 <&mmss_smmu 2039 <&mmss_smmu 0xc01>,
2109 <&mmss_smmu 2040 <&mmss_smmu 0xc02>,
2110 <&mmss_smmu 2041 <&mmss_smmu 0xc03>;
2111 power-domains = <&mmc 2042 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2112 <&mmc 2043 <&mmcc CAMSS_VFE1_GDSC>;
2113 status = "disabled"; 2044 status = "disabled";
2114 2045
2115 ports { 2046 ports {
2116 #address-cell 2047 #address-cells = <1>;
2117 #size-cells = 2048 #size-cells = <0>;
2118 }; 2049 };
2119 }; 2050 };
2120 2051
2121 cci: cci@ca0c000 { 2052 cci: cci@ca0c000 {
2122 compatible = "qcom,ms 2053 compatible = "qcom,msm8996-cci";
2123 #address-cells = <1>; 2054 #address-cells = <1>;
2124 #size-cells = <0>; 2055 #size-cells = <0>;
2125 reg = <0x0ca0c000 0x1 2056 reg = <0x0ca0c000 0x1000>;
2126 interrupts = <GIC_SPI 2057 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2127 2058
2128 assigned-clocks = <&m 2059 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2129 <&m 2060 <&mmcc CAMSS_CCI_CLK>;
2130 assigned-clock-rates 2061 assigned-clock-rates = <80800000>, <37500000>;
2131 clocks = <&mmcc CAMSS 2062 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2132 <&mmcc CAMSS 2063 <&mmcc CAMSS_CCI_AHB_CLK>,
2133 <&mmcc CAMSS 2064 <&mmcc CAMSS_CCI_CLK>,
2134 <&mmcc CAMSS 2065 <&mmcc CAMSS_AHB_CLK>;
2135 clock-names = "camss_ 2066 clock-names = "camss_top_ahb",
2136 "cci_ah 2067 "cci_ahb",
2137 "cci", 2068 "cci",
2138 "camss_ 2069 "camss_ahb";
2139 2070
2140 pinctrl-names = "defa 2071 pinctrl-names = "default";
2141 pinctrl-0 = <&cci0_de 2072 pinctrl-0 = <&cci0_default &cci1_default>;
2142 power-domains = <&mmc 2073 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2143 status = "disabled"; 2074 status = "disabled";
2144 2075
2145 cci_i2c0: i2c-bus@0 { 2076 cci_i2c0: i2c-bus@0 {
2146 reg = <0>; 2077 reg = <0>;
2147 clock-frequen 2078 clock-frequency = <400000>;
2148 #address-cell 2079 #address-cells = <1>;
2149 #size-cells = 2080 #size-cells = <0>;
2150 }; 2081 };
2151 2082
2152 cci_i2c1: i2c-bus@1 { 2083 cci_i2c1: i2c-bus@1 {
2153 reg = <1>; 2084 reg = <1>;
2154 clock-frequen 2085 clock-frequency = <400000>;
2155 #address-cell 2086 #address-cells = <1>;
2156 #size-cells = 2087 #size-cells = <0>;
2157 }; 2088 };
2158 }; 2089 };
2159 2090
2160 venus: video-codec@cc00000 { 2091 venus: video-codec@cc00000 {
2161 compatible = "qcom,sd 2092 compatible = "qcom,sdm660-venus";
2162 reg = <0x0cc00000 0xf 2093 reg = <0x0cc00000 0xff000>;
2163 clocks = <&mmcc VIDEO 2094 clocks = <&mmcc VIDEO_CORE_CLK>,
2164 <&mmcc VIDEO 2095 <&mmcc VIDEO_AHB_CLK>,
2165 <&mmcc VIDEO 2096 <&mmcc VIDEO_AXI_CLK>,
2166 <&mmcc THROT 2097 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2167 clock-names = "core", 2098 clock-names = "core", "iface", "bus", "bus_throttle";
2168 interconnects = <&gno 2099 interconnects = <&gnoc 0 &mnoc 13>,
2169 <&mno 2100 <&mnoc 4 &bimc 5>;
2170 interconnect-names = 2101 interconnect-names = "cpu-cfg", "video-mem";
2171 interrupts = <GIC_SPI 2102 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&mmss_smmu 2103 iommus = <&mmss_smmu 0x400>,
2173 <&mmss_smmu 2104 <&mmss_smmu 0x401>,
2174 <&mmss_smmu 2105 <&mmss_smmu 0x40a>,
2175 <&mmss_smmu 2106 <&mmss_smmu 0x407>,
2176 <&mmss_smmu 2107 <&mmss_smmu 0x40e>,
2177 <&mmss_smmu 2108 <&mmss_smmu 0x40f>,
2178 <&mmss_smmu 2109 <&mmss_smmu 0x408>,
2179 <&mmss_smmu 2110 <&mmss_smmu 0x409>,
2180 <&mmss_smmu 2111 <&mmss_smmu 0x40b>,
2181 <&mmss_smmu 2112 <&mmss_smmu 0x40c>,
2182 <&mmss_smmu 2113 <&mmss_smmu 0x40d>,
2183 <&mmss_smmu 2114 <&mmss_smmu 0x410>,
2184 <&mmss_smmu 2115 <&mmss_smmu 0x421>,
2185 <&mmss_smmu 2116 <&mmss_smmu 0x428>,
2186 <&mmss_smmu 2117 <&mmss_smmu 0x429>,
2187 <&mmss_smmu 2118 <&mmss_smmu 0x42b>,
2188 <&mmss_smmu 2119 <&mmss_smmu 0x42c>,
2189 <&mmss_smmu 2120 <&mmss_smmu 0x42d>,
2190 <&mmss_smmu 2121 <&mmss_smmu 0x411>,
2191 <&mmss_smmu 2122 <&mmss_smmu 0x431>;
2192 memory-region = <&ven 2123 memory-region = <&venus_region>;
2193 power-domains = <&mmc 2124 power-domains = <&mmcc VENUS_GDSC>;
2194 status = "disabled"; 2125 status = "disabled";
2195 2126
2196 video-decoder { 2127 video-decoder {
2197 compatible = 2128 compatible = "venus-decoder";
2198 clocks = <&mm 2129 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2199 clock-names = 2130 clock-names = "vcodec0_core";
2200 power-domains 2131 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2201 }; 2132 };
2202 2133
2203 video-encoder { 2134 video-encoder {
2204 compatible = 2135 compatible = "venus-encoder";
2205 clocks = <&mm 2136 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2206 clock-names = 2137 clock-names = "vcodec0_core";
2207 power-domains 2138 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2208 }; 2139 };
2209 }; 2140 };
2210 2141
2211 mmss_smmu: iommu@cd00000 { 2142 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sd 2143 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2213 reg = <0x0cd00000 0x4 2144 reg = <0x0cd00000 0x40000>;
2214 2145
2215 clocks = <&mmcc MNOC_ 2146 clocks = <&mmcc MNOC_AHB_CLK>,
2216 <&mmcc BIMC_ 2147 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2148 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2217 <&mmcc BIMC_ 2149 <&mmcc BIMC_SMMU_AXI_CLK>;
2218 clock-names = "iface- 2150 clock-names = "iface-mm", "iface-smmu",
2219 "bus-sm !! 2151 "bus-mm", "bus-smmu";
2220 #global-interrupts = 2152 #global-interrupts = <2>;
2221 #iommu-cells = <1>; 2153 #iommu-cells = <1>;
2222 2154
2223 interrupts = 2155 interrupts =
2224 <GIC_SPI 229 2156 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 231 2157 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2226 2158
2227 <GIC_SPI 263 2159 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 266 2160 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 267 2161 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 268 2162 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 244 2163 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 245 2164 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 247 2165 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 248 2166 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 249 2167 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 250 2168 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 251 2169 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 252 2170 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 253 2171 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 254 2172 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 255 2173 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 256 2174 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 260 2175 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 261 2176 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 262 2177 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 272 2178 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 273 2179 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 274 2180 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 275 2181 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 276 2182 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2251 2183
2252 status = "disabled"; 2184 status = "disabled";
2253 }; 2185 };
2254 2186
2255 adsp_pil: remoteproc@15700000 2187 adsp_pil: remoteproc@15700000 {
2256 compatible = "qcom,sd 2188 compatible = "qcom,sdm660-adsp-pas";
2257 reg = <0x15700000 0x4 2189 reg = <0x15700000 0x4040>;
2258 2190
2259 interrupts-extended = 2191 interrupts-extended =
2260 <&intc GIC_SP 2192 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2261 <&adsp_smp2p_ 2193 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2262 <&adsp_smp2p_ 2194 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2263 <&adsp_smp2p_ 2195 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2264 <&adsp_smp2p_ 2196 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2265 interrupt-names = "wd 2197 interrupt-names = "wdog", "fatal", "ready",
2266 "ha 2198 "handover", "stop-ack";
2267 2199
2268 clocks = <&rpmcc RPM_ 2200 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2269 clock-names = "xo"; 2201 clock-names = "xo";
2270 2202
2271 memory-region = <&ads 2203 memory-region = <&adsp_region>;
2272 power-domains = <&rpm 2204 power-domains = <&rpmpd SDM660_VDDCX>;
2273 power-domain-names = 2205 power-domain-names = "cx";
2274 2206
2275 qcom,smem-states = <& 2207 qcom,smem-states = <&adsp_smp2p_out 0>;
2276 qcom,smem-state-names 2208 qcom,smem-state-names = "stop";
2277 2209
2278 glink-edge { 2210 glink-edge {
2279 interrupts = 2211 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2280 2212
2281 label = "lpas 2213 label = "lpass";
2282 mboxes = <&ap 2214 mboxes = <&apcs_glb 9>;
2283 qcom,remote-p 2215 qcom,remote-pid = <2>;
2284 2216
2285 apr { 2217 apr {
2286 compa 2218 compatible = "qcom,apr-v2";
2287 qcom, 2219 qcom,glink-channels = "apr_audio_svc";
2288 qcom, 2220 qcom,domain = <APR_DOMAIN_ADSP>;
2289 #addr 2221 #address-cells = <1>;
2290 #size 2222 #size-cells = <0>;
2291 2223
2292 servi 2224 service@3 {
2293 2225 reg = <APR_SVC_ADSP_CORE>;
2294 2226 compatible = "qcom,q6core";
2295 }; 2227 };
2296 2228
2297 q6afe 2229 q6afe: service@4 {
2298 2230 compatible = "qcom,q6afe";
2299 2231 reg = <APR_SVC_AFE>;
2300 2232 q6afedai: dais {
2301 2233 compatible = "qcom,q6afe-dais";
2302 2234 #address-cells = <1>;
2303 2235 #size-cells = <0>;
2304 2236 #sound-dai-cells = <1>;
2305 2237 };
2306 }; 2238 };
2307 2239
2308 q6asm 2240 q6asm: service@7 {
2309 2241 compatible = "qcom,q6asm";
2310 2242 reg = <APR_SVC_ASM>;
2311 2243 q6asmdai: dais {
2312 2244 compatible = "qcom,q6asm-dais";
2313 2245 #address-cells = <1>;
2314 2246 #size-cells = <0>;
2315 2247 #sound-dai-cells = <1>;
2316 2248 iommus = <&lpass_smmu 1>;
2317 2249 };
2318 }; 2250 };
2319 2251
2320 q6adm 2252 q6adm: service@8 {
2321 2253 compatible = "qcom,q6adm";
2322 2254 reg = <APR_SVC_ADM>;
2323 2255 q6routing: routing {
2324 2256 compatible = "qcom,q6adm-routing";
2325 2257 #sound-dai-cells = <0>;
2326 2258 };
2327 }; 2259 };
2328 }; 2260 };
2329 }; 2261 };
2330 }; 2262 };
2331 2263
2332 gnoc: interconnect@17900000 { 2264 gnoc: interconnect@17900000 {
2333 compatible = "qcom,sd 2265 compatible = "qcom,sdm660-gnoc";
2334 reg = <0x17900000 0xe 2266 reg = <0x17900000 0xe000>;
2335 #interconnect-cells = 2267 #interconnect-cells = <1>;
>> 2268 /*
>> 2269 * This one apparently features no clocks,
>> 2270 * so let's not mess with the driver needlessly
>> 2271 */
>> 2272 clock-names = "bus", "bus_a";
>> 2273 clocks = <&xo_board>, <&xo_board>;
2336 }; 2274 };
2337 2275
2338 apcs_glb: mailbox@17911000 { 2276 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sd 2277 compatible = "qcom,sdm660-apcs-hmss-global",
2340 "qcom,ms 2278 "qcom,msm8994-apcs-kpss-global";
2341 reg = <0x17911000 0x1 2279 reg = <0x17911000 0x1000>;
2342 2280
2343 #mbox-cells = <1>; 2281 #mbox-cells = <1>;
2344 }; 2282 };
2345 2283
2346 timer@17920000 { 2284 timer@17920000 {
2347 #address-cells = <1>; 2285 #address-cells = <1>;
2348 #size-cells = <1>; 2286 #size-cells = <1>;
2349 ranges; 2287 ranges;
2350 compatible = "arm,arm 2288 compatible = "arm,armv7-timer-mem";
2351 reg = <0x17920000 0x1 2289 reg = <0x17920000 0x1000>;
2352 clock-frequency = <19 2290 clock-frequency = <19200000>;
2353 2291
2354 frame@17921000 { 2292 frame@17921000 {
2355 frame-number 2293 frame-number = <0>;
2356 interrupts = 2294 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2357 2295 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2358 reg = <0x1792 2296 reg = <0x17921000 0x1000>,
2359 <0x17 2297 <0x17922000 0x1000>;
2360 }; 2298 };
2361 2299
2362 frame@17923000 { 2300 frame@17923000 {
2363 frame-number 2301 frame-number = <1>;
2364 interrupts = 2302 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2365 reg = <0x1792 2303 reg = <0x17923000 0x1000>;
2366 status = "dis 2304 status = "disabled";
2367 }; 2305 };
2368 2306
2369 frame@17924000 { 2307 frame@17924000 {
2370 frame-number 2308 frame-number = <2>;
2371 interrupts = 2309 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2372 reg = <0x1792 2310 reg = <0x17924000 0x1000>;
2373 status = "dis 2311 status = "disabled";
2374 }; 2312 };
2375 2313
2376 frame@17925000 { 2314 frame@17925000 {
2377 frame-number 2315 frame-number = <3>;
2378 interrupts = 2316 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2379 reg = <0x1792 2317 reg = <0x17925000 0x1000>;
2380 status = "dis 2318 status = "disabled";
2381 }; 2319 };
2382 2320
2383 frame@17926000 { 2321 frame@17926000 {
2384 frame-number 2322 frame-number = <4>;
2385 interrupts = 2323 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2386 reg = <0x1792 2324 reg = <0x17926000 0x1000>;
2387 status = "dis 2325 status = "disabled";
2388 }; 2326 };
2389 2327
2390 frame@17927000 { 2328 frame@17927000 {
2391 frame-number 2329 frame-number = <5>;
2392 interrupts = 2330 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2393 reg = <0x1792 2331 reg = <0x17927000 0x1000>;
2394 status = "dis 2332 status = "disabled";
2395 }; 2333 };
2396 2334
2397 frame@17928000 { 2335 frame@17928000 {
2398 frame-number 2336 frame-number = <6>;
2399 interrupts = 2337 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2400 reg = <0x1792 2338 reg = <0x17928000 0x1000>;
2401 status = "dis 2339 status = "disabled";
2402 }; 2340 };
2403 }; 2341 };
2404 2342
2405 intc: interrupt-controller@17 2343 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic 2344 compatible = "arm,gic-v3";
2407 reg = <0x17a00000 0x1 2345 reg = <0x17a00000 0x10000>, /* GICD */
2408 <0x17b00000 2346 <0x17b00000 0x100000>; /* GICR * 8 */
2409 #interrupt-cells = <3 2347 #interrupt-cells = <3>;
2410 #address-cells = <1>; 2348 #address-cells = <1>;
2411 #size-cells = <1>; 2349 #size-cells = <1>;
2412 ranges; 2350 ranges;
2413 interrupt-controller; 2351 interrupt-controller;
2414 #redistributor-region 2352 #redistributor-regions = <1>;
2415 redistributor-stride 2353 redistributor-stride = <0x0 0x20000>;
2416 interrupts = <GIC_PPI 2354 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2417 }; 2355 };
2418 }; 2356 };
2419 2357
2420 sound: sound { 2358 sound: sound {
2421 }; 2359 };
2422 2360
2423 thermal-zones { 2361 thermal-zones {
2424 aoss-thermal { 2362 aoss-thermal {
2425 polling-delay-passive 2363 polling-delay-passive = <250>;
>> 2364 polling-delay = <1000>;
2426 2365
2427 thermal-sensors = <&t 2366 thermal-sensors = <&tsens 0>;
2428 2367
2429 trips { 2368 trips {
2430 aoss_alert0: 2369 aoss_alert0: trip-point0 {
2431 tempe 2370 temperature = <105000>;
2432 hyste 2371 hysteresis = <1000>;
2433 type 2372 type = "hot";
2434 }; 2373 };
2435 }; 2374 };
2436 }; 2375 };
2437 2376
2438 cpuss0-thermal { 2377 cpuss0-thermal {
2439 polling-delay-passive 2378 polling-delay-passive = <250>;
>> 2379 polling-delay = <1000>;
2440 2380
2441 thermal-sensors = <&t 2381 thermal-sensors = <&tsens 1>;
2442 2382
2443 trips { 2383 trips {
2444 cpuss0_alert0 2384 cpuss0_alert0: trip-point0 {
2445 tempe 2385 temperature = <125000>;
2446 hyste 2386 hysteresis = <1000>;
2447 type 2387 type = "hot";
2448 }; 2388 };
2449 }; 2389 };
2450 }; 2390 };
2451 2391
2452 cpuss1-thermal { 2392 cpuss1-thermal {
2453 polling-delay-passive 2393 polling-delay-passive = <250>;
>> 2394 polling-delay = <1000>;
2454 2395
2455 thermal-sensors = <&t 2396 thermal-sensors = <&tsens 2>;
2456 2397
2457 trips { 2398 trips {
2458 cpuss1_alert0 2399 cpuss1_alert0: trip-point0 {
2459 tempe 2400 temperature = <125000>;
2460 hyste 2401 hysteresis = <1000>;
2461 type 2402 type = "hot";
2462 }; 2403 };
2463 }; 2404 };
2464 }; 2405 };
2465 2406
2466 cpu0-thermal { 2407 cpu0-thermal {
2467 polling-delay-passive 2408 polling-delay-passive = <250>;
>> 2409 polling-delay = <1000>;
2468 2410
2469 thermal-sensors = <&t 2411 thermal-sensors = <&tsens 3>;
2470 2412
2471 trips { 2413 trips {
2472 cpu0_alert0: 2414 cpu0_alert0: trip-point0 {
2473 tempe 2415 temperature = <70000>;
2474 hyste 2416 hysteresis = <1000>;
2475 type 2417 type = "passive";
2476 }; 2418 };
2477 2419
2478 cpu0_crit: cp 2420 cpu0_crit: cpu-crit {
2479 tempe 2421 temperature = <110000>;
2480 hyste 2422 hysteresis = <1000>;
2481 type 2423 type = "critical";
2482 }; 2424 };
2483 }; 2425 };
2484 }; 2426 };
2485 2427
2486 cpu1-thermal { 2428 cpu1-thermal {
2487 polling-delay-passive 2429 polling-delay-passive = <250>;
>> 2430 polling-delay = <1000>;
2488 2431
2489 thermal-sensors = <&t 2432 thermal-sensors = <&tsens 4>;
2490 2433
2491 trips { 2434 trips {
2492 cpu1_alert0: 2435 cpu1_alert0: trip-point0 {
2493 tempe 2436 temperature = <70000>;
2494 hyste 2437 hysteresis = <1000>;
2495 type 2438 type = "passive";
2496 }; 2439 };
2497 2440
2498 cpu1_crit: cp 2441 cpu1_crit: cpu-crit {
2499 tempe 2442 temperature = <110000>;
2500 hyste 2443 hysteresis = <1000>;
2501 type 2444 type = "critical";
2502 }; 2445 };
2503 }; 2446 };
2504 }; 2447 };
2505 2448
2506 cpu2-thermal { 2449 cpu2-thermal {
2507 polling-delay-passive 2450 polling-delay-passive = <250>;
>> 2451 polling-delay = <1000>;
2508 2452
2509 thermal-sensors = <&t 2453 thermal-sensors = <&tsens 5>;
2510 2454
2511 trips { 2455 trips {
2512 cpu2_alert0: 2456 cpu2_alert0: trip-point0 {
2513 tempe 2457 temperature = <70000>;
2514 hyste 2458 hysteresis = <1000>;
2515 type 2459 type = "passive";
2516 }; 2460 };
2517 2461
2518 cpu2_crit: cp 2462 cpu2_crit: cpu-crit {
2519 tempe 2463 temperature = <110000>;
2520 hyste 2464 hysteresis = <1000>;
2521 type 2465 type = "critical";
2522 }; 2466 };
2523 }; 2467 };
2524 }; 2468 };
2525 2469
2526 cpu3-thermal { 2470 cpu3-thermal {
2527 polling-delay-passive 2471 polling-delay-passive = <250>;
>> 2472 polling-delay = <1000>;
2528 2473
2529 thermal-sensors = <&t 2474 thermal-sensors = <&tsens 6>;
2530 2475
2531 trips { 2476 trips {
2532 cpu3_alert0: 2477 cpu3_alert0: trip-point0 {
2533 tempe 2478 temperature = <70000>;
2534 hyste 2479 hysteresis = <1000>;
2535 type 2480 type = "passive";
2536 }; 2481 };
2537 2482
2538 cpu3_crit: cp 2483 cpu3_crit: cpu-crit {
2539 tempe 2484 temperature = <110000>;
2540 hyste 2485 hysteresis = <1000>;
2541 type 2486 type = "critical";
2542 }; 2487 };
2543 }; 2488 };
2544 }; 2489 };
2545 2490
2546 /* 2491 /*
2547 * According to what downstre 2492 * According to what downstream DTS says,
2548 * the entire power efficient 2493 * the entire power efficient cluster has
2549 * only a single thermal sens 2494 * only a single thermal sensor.
2550 */ 2495 */
2551 2496
2552 pwr-cluster-thermal { 2497 pwr-cluster-thermal {
2553 polling-delay-passive 2498 polling-delay-passive = <250>;
>> 2499 polling-delay = <1000>;
2554 2500
2555 thermal-sensors = <&t 2501 thermal-sensors = <&tsens 7>;
2556 2502
2557 trips { 2503 trips {
2558 pwr_cluster_a 2504 pwr_cluster_alert0: trip-point0 {
2559 tempe 2505 temperature = <70000>;
2560 hyste 2506 hysteresis = <1000>;
2561 type 2507 type = "passive";
2562 }; 2508 };
2563 2509
2564 pwr_cluster_c 2510 pwr_cluster_crit: cpu-crit {
2565 tempe 2511 temperature = <110000>;
2566 hyste 2512 hysteresis = <1000>;
2567 type 2513 type = "critical";
2568 }; 2514 };
2569 }; 2515 };
2570 }; 2516 };
2571 2517
2572 gpu-thermal { 2518 gpu-thermal {
2573 polling-delay-passive 2519 polling-delay-passive = <250>;
>> 2520 polling-delay = <1000>;
2574 2521
2575 thermal-sensors = <&t 2522 thermal-sensors = <&tsens 8>;
2576 2523
2577 cooling-maps { <<
2578 map0 { <<
2579 trip <<
2580 cooli <<
2581 }; <<
2582 }; <<
2583 <<
2584 trips { 2524 trips {
2585 gpu_alert0: t 2525 gpu_alert0: trip-point0 {
2586 tempe <<
2587 hyste <<
2588 type <<
2589 }; <<
2590 <<
2591 trip-point1 { <<
2592 tempe 2526 temperature = <90000>;
2593 hyste 2527 hysteresis = <1000>;
2594 type 2528 type = "hot";
2595 }; 2529 };
2596 <<
2597 trip-point2 { <<
2598 tempe <<
2599 hyste <<
2600 type <<
2601 }; <<
2602 }; 2530 };
2603 }; 2531 };
2604 }; 2532 };
2605 2533
2606 timer { 2534 timer {
2607 compatible = "arm,armv8-timer 2535 compatible = "arm,armv8-timer";
2608 interrupts = <GIC_PPI 1 (GIC_ !! 2536 interrupts = <GIC_PPI 1 0xf08>,
2609 <GIC_PPI 2 (GIC_ !! 2537 <GIC_PPI 2 0xf08>,
2610 <GIC_PPI 3 (GIC_ !! 2538 <GIC_PPI 3 0xf08>,
2611 <GIC_PPI 0 (GIC_ !! 2539 <GIC_PPI 0 0xf08>;
2612 }; 2540 };
2613 }; 2541 };
2614 2542
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