1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, Konrad Dybcio <konradybc 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
4 * Copyright (c) 2020, AngeloGioacchino Del Re< 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/qcom,gcc-sdm660.h> 7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
8 #include <dt-bindings/clock/qcom,gpucc-sdm660. 8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h 9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/firmware/qcom,scm.h> 11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/interconnect/qcom,sdm660 12 #include <dt-bindings/interconnect/qcom,sdm660.h>
13 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/thermal/thermal.h> <<
17 #include <dt-bindings/soc/qcom,apr.h> 16 #include <dt-bindings/soc/qcom,apr.h>
18 17
19 / { 18 / {
20 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
21 20
22 #address-cells = <2>; 21 #address-cells = <2>;
23 #size-cells = <2>; 22 #size-cells = <2>;
24 23
25 aliases { 24 aliases {
26 mmc1 = &sdhc_1; 25 mmc1 = &sdhc_1;
27 mmc2 = &sdhc_2; 26 mmc2 = &sdhc_2;
28 }; 27 };
29 28
30 chosen { }; 29 chosen { };
31 30
32 clocks { 31 clocks {
33 xo_board: xo-board { 32 xo_board: xo-board {
34 compatible = "fixed-cl 33 compatible = "fixed-clock";
35 #clock-cells = <0>; 34 #clock-cells = <0>;
36 clock-frequency = <192 35 clock-frequency = <19200000>;
37 clock-output-names = " 36 clock-output-names = "xo_board";
38 }; 37 };
39 38
40 sleep_clk: sleep-clk { 39 sleep_clk: sleep-clk {
41 compatible = "fixed-cl 40 compatible = "fixed-clock";
42 #clock-cells = <0>; 41 #clock-cells = <0>;
43 clock-frequency = <327 42 clock-frequency = <32764>;
44 clock-output-names = " 43 clock-output-names = "sleep_clk";
45 }; 44 };
46 }; 45 };
47 46
48 cpus { 47 cpus {
49 #address-cells = <2>; 48 #address-cells = <2>;
50 #size-cells = <0>; 49 #size-cells = <0>;
51 50
52 CPU0: cpu@100 { 51 CPU0: cpu@100 {
53 device_type = "cpu"; 52 device_type = "cpu";
54 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
55 reg = <0x0 0x100>; 54 reg = <0x0 0x100>;
56 enable-method = "psci" 55 enable-method = "psci";
57 cpu-idle-states = <&PE 56 cpu-idle-states = <&PERF_CPU_SLEEP_0
58 57 &PERF_CPU_SLEEP_1
59 58 &PERF_CLUSTER_SLEEP_0
60 59 &PERF_CLUSTER_SLEEP_1
61 60 &PERF_CLUSTER_SLEEP_2>;
62 capacity-dmips-mhz = < 61 capacity-dmips-mhz = <1126>;
63 #cooling-cells = <2>; 62 #cooling-cells = <2>;
64 next-level-cache = <&L 63 next-level-cache = <&L2_1>;
65 L2_1: l2-cache { 64 L2_1: l2-cache {
66 compatible = " 65 compatible = "cache";
67 cache-level = 66 cache-level = <2>;
68 cache-unified; 67 cache-unified;
69 }; 68 };
70 }; 69 };
71 70
72 CPU1: cpu@101 { 71 CPU1: cpu@101 {
73 device_type = "cpu"; 72 device_type = "cpu";
74 compatible = "arm,cort 73 compatible = "arm,cortex-a53";
75 reg = <0x0 0x101>; 74 reg = <0x0 0x101>;
76 enable-method = "psci" 75 enable-method = "psci";
77 cpu-idle-states = <&PE 76 cpu-idle-states = <&PERF_CPU_SLEEP_0
78 77 &PERF_CPU_SLEEP_1
79 78 &PERF_CLUSTER_SLEEP_0
80 79 &PERF_CLUSTER_SLEEP_1
81 80 &PERF_CLUSTER_SLEEP_2>;
82 capacity-dmips-mhz = < 81 capacity-dmips-mhz = <1126>;
83 #cooling-cells = <2>; 82 #cooling-cells = <2>;
84 next-level-cache = <&L 83 next-level-cache = <&L2_1>;
85 }; 84 };
86 85
87 CPU2: cpu@102 { 86 CPU2: cpu@102 {
88 device_type = "cpu"; 87 device_type = "cpu";
89 compatible = "arm,cort 88 compatible = "arm,cortex-a53";
90 reg = <0x0 0x102>; 89 reg = <0x0 0x102>;
91 enable-method = "psci" 90 enable-method = "psci";
92 cpu-idle-states = <&PE 91 cpu-idle-states = <&PERF_CPU_SLEEP_0
93 92 &PERF_CPU_SLEEP_1
94 93 &PERF_CLUSTER_SLEEP_0
95 94 &PERF_CLUSTER_SLEEP_1
96 95 &PERF_CLUSTER_SLEEP_2>;
97 capacity-dmips-mhz = < 96 capacity-dmips-mhz = <1126>;
98 #cooling-cells = <2>; 97 #cooling-cells = <2>;
99 next-level-cache = <&L 98 next-level-cache = <&L2_1>;
100 }; 99 };
101 100
102 CPU3: cpu@103 { 101 CPU3: cpu@103 {
103 device_type = "cpu"; 102 device_type = "cpu";
104 compatible = "arm,cort 103 compatible = "arm,cortex-a53";
105 reg = <0x0 0x103>; 104 reg = <0x0 0x103>;
106 enable-method = "psci" 105 enable-method = "psci";
107 cpu-idle-states = <&PE 106 cpu-idle-states = <&PERF_CPU_SLEEP_0
108 107 &PERF_CPU_SLEEP_1
109 108 &PERF_CLUSTER_SLEEP_0
110 109 &PERF_CLUSTER_SLEEP_1
111 110 &PERF_CLUSTER_SLEEP_2>;
112 capacity-dmips-mhz = < 111 capacity-dmips-mhz = <1126>;
113 #cooling-cells = <2>; 112 #cooling-cells = <2>;
114 next-level-cache = <&L 113 next-level-cache = <&L2_1>;
115 }; 114 };
116 115
117 CPU4: cpu@0 { 116 CPU4: cpu@0 {
118 device_type = "cpu"; 117 device_type = "cpu";
119 compatible = "arm,cort 118 compatible = "arm,cortex-a53";
120 reg = <0x0 0x0>; 119 reg = <0x0 0x0>;
121 enable-method = "psci" 120 enable-method = "psci";
122 cpu-idle-states = <&PW 121 cpu-idle-states = <&PWR_CPU_SLEEP_0
123 122 &PWR_CPU_SLEEP_1
124 123 &PWR_CLUSTER_SLEEP_0
125 124 &PWR_CLUSTER_SLEEP_1
126 125 &PWR_CLUSTER_SLEEP_2>;
127 capacity-dmips-mhz = < 126 capacity-dmips-mhz = <1024>;
128 #cooling-cells = <2>; 127 #cooling-cells = <2>;
129 next-level-cache = <&L 128 next-level-cache = <&L2_0>;
130 L2_0: l2-cache { 129 L2_0: l2-cache {
131 compatible = " 130 compatible = "cache";
132 cache-level = 131 cache-level = <2>;
133 cache-unified; 132 cache-unified;
134 }; 133 };
135 }; 134 };
136 135
137 CPU5: cpu@1 { 136 CPU5: cpu@1 {
138 device_type = "cpu"; 137 device_type = "cpu";
139 compatible = "arm,cort 138 compatible = "arm,cortex-a53";
140 reg = <0x0 0x1>; 139 reg = <0x0 0x1>;
141 enable-method = "psci" 140 enable-method = "psci";
142 cpu-idle-states = <&PW 141 cpu-idle-states = <&PWR_CPU_SLEEP_0
143 142 &PWR_CPU_SLEEP_1
144 143 &PWR_CLUSTER_SLEEP_0
145 144 &PWR_CLUSTER_SLEEP_1
146 145 &PWR_CLUSTER_SLEEP_2>;
147 capacity-dmips-mhz = < 146 capacity-dmips-mhz = <1024>;
148 #cooling-cells = <2>; 147 #cooling-cells = <2>;
149 next-level-cache = <&L 148 next-level-cache = <&L2_0>;
150 }; 149 };
151 150
152 CPU6: cpu@2 { 151 CPU6: cpu@2 {
153 device_type = "cpu"; 152 device_type = "cpu";
154 compatible = "arm,cort 153 compatible = "arm,cortex-a53";
155 reg = <0x0 0x2>; 154 reg = <0x0 0x2>;
156 enable-method = "psci" 155 enable-method = "psci";
157 cpu-idle-states = <&PW 156 cpu-idle-states = <&PWR_CPU_SLEEP_0
158 157 &PWR_CPU_SLEEP_1
159 158 &PWR_CLUSTER_SLEEP_0
160 159 &PWR_CLUSTER_SLEEP_1
161 160 &PWR_CLUSTER_SLEEP_2>;
162 capacity-dmips-mhz = < 161 capacity-dmips-mhz = <1024>;
163 #cooling-cells = <2>; 162 #cooling-cells = <2>;
164 next-level-cache = <&L 163 next-level-cache = <&L2_0>;
165 }; 164 };
166 165
167 CPU7: cpu@3 { 166 CPU7: cpu@3 {
168 device_type = "cpu"; 167 device_type = "cpu";
169 compatible = "arm,cort 168 compatible = "arm,cortex-a53";
170 reg = <0x0 0x3>; 169 reg = <0x0 0x3>;
171 enable-method = "psci" 170 enable-method = "psci";
172 cpu-idle-states = <&PW 171 cpu-idle-states = <&PWR_CPU_SLEEP_0
173 172 &PWR_CPU_SLEEP_1
174 173 &PWR_CLUSTER_SLEEP_0
175 174 &PWR_CLUSTER_SLEEP_1
176 175 &PWR_CLUSTER_SLEEP_2>;
177 capacity-dmips-mhz = < 176 capacity-dmips-mhz = <1024>;
178 #cooling-cells = <2>; 177 #cooling-cells = <2>;
179 next-level-cache = <&L 178 next-level-cache = <&L2_0>;
180 }; 179 };
181 180
182 cpu-map { 181 cpu-map {
183 cluster0 { 182 cluster0 {
184 core0 { 183 core0 {
185 cpu = 184 cpu = <&CPU4>;
186 }; 185 };
187 186
188 core1 { 187 core1 {
189 cpu = 188 cpu = <&CPU5>;
190 }; 189 };
191 190
192 core2 { 191 core2 {
193 cpu = 192 cpu = <&CPU6>;
194 }; 193 };
195 194
196 core3 { 195 core3 {
197 cpu = 196 cpu = <&CPU7>;
198 }; 197 };
199 }; 198 };
200 199
201 cluster1 { 200 cluster1 {
202 core0 { 201 core0 {
203 cpu = 202 cpu = <&CPU0>;
204 }; 203 };
205 204
206 core1 { 205 core1 {
207 cpu = 206 cpu = <&CPU1>;
208 }; 207 };
209 208
210 core2 { 209 core2 {
211 cpu = 210 cpu = <&CPU2>;
212 }; 211 };
213 212
214 core3 { 213 core3 {
215 cpu = 214 cpu = <&CPU3>;
216 }; 215 };
217 }; 216 };
218 }; 217 };
219 218
220 idle-states { 219 idle-states {
221 entry-method = "psci"; 220 entry-method = "psci";
222 221
223 PWR_CPU_SLEEP_0: cpu-s 222 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 compatible = " 223 compatible = "arm,idle-state";
225 idle-state-nam 224 idle-state-name = "pwr-retention";
226 arm,psci-suspe 225 arm,psci-suspend-param = <0x40000002>;
227 entry-latency- 226 entry-latency-us = <338>;
228 exit-latency-u 227 exit-latency-us = <423>;
229 min-residency- 228 min-residency-us = <200>;
230 }; 229 };
231 230
232 PWR_CPU_SLEEP_1: cpu-s 231 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 compatible = " 232 compatible = "arm,idle-state";
234 idle-state-nam 233 idle-state-name = "pwr-power-collapse";
235 arm,psci-suspe 234 arm,psci-suspend-param = <0x40000003>;
236 entry-latency- 235 entry-latency-us = <515>;
237 exit-latency-u 236 exit-latency-us = <1821>;
238 min-residency- 237 min-residency-us = <1000>;
239 local-timer-st 238 local-timer-stop;
240 }; 239 };
241 240
242 PERF_CPU_SLEEP_0: cpu- 241 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 compatible = " 242 compatible = "arm,idle-state";
244 idle-state-nam 243 idle-state-name = "perf-retention";
245 arm,psci-suspe 244 arm,psci-suspend-param = <0x40000002>;
246 entry-latency- 245 entry-latency-us = <154>;
247 exit-latency-u 246 exit-latency-us = <87>;
248 min-residency- 247 min-residency-us = <200>;
249 }; 248 };
250 249
251 PERF_CPU_SLEEP_1: cpu- 250 PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
252 compatible = " 251 compatible = "arm,idle-state";
253 idle-state-nam 252 idle-state-name = "perf-power-collapse";
254 arm,psci-suspe 253 arm,psci-suspend-param = <0x40000003>;
255 entry-latency- 254 entry-latency-us = <262>;
256 exit-latency-u 255 exit-latency-us = <301>;
257 min-residency- 256 min-residency-us = <1000>;
258 local-timer-st 257 local-timer-stop;
259 }; 258 };
260 259
261 PWR_CLUSTER_SLEEP_0: c 260 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 compatible = " 261 compatible = "arm,idle-state";
263 idle-state-nam 262 idle-state-name = "pwr-cluster-dynamic-retention";
264 arm,psci-suspe 263 arm,psci-suspend-param = <0x400000F2>;
265 entry-latency- 264 entry-latency-us = <284>;
266 exit-latency-u 265 exit-latency-us = <384>;
267 min-residency- 266 min-residency-us = <9987>;
268 local-timer-st 267 local-timer-stop;
269 }; 268 };
270 269
271 PWR_CLUSTER_SLEEP_1: c 270 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 compatible = " 271 compatible = "arm,idle-state";
273 idle-state-nam 272 idle-state-name = "pwr-cluster-retention";
274 arm,psci-suspe 273 arm,psci-suspend-param = <0x400000F3>;
275 entry-latency- 274 entry-latency-us = <338>;
276 exit-latency-u 275 exit-latency-us = <423>;
277 min-residency- 276 min-residency-us = <9987>;
278 local-timer-st 277 local-timer-stop;
279 }; 278 };
280 279
281 PWR_CLUSTER_SLEEP_2: c 280 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 compatible = " 281 compatible = "arm,idle-state";
283 idle-state-nam 282 idle-state-name = "pwr-cluster-retention";
284 arm,psci-suspe 283 arm,psci-suspend-param = <0x400000F4>;
285 entry-latency- 284 entry-latency-us = <515>;
286 exit-latency-u 285 exit-latency-us = <1821>;
287 min-residency- 286 min-residency-us = <9987>;
288 local-timer-st 287 local-timer-stop;
289 }; 288 };
290 289
291 PERF_CLUSTER_SLEEP_0: 290 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 compatible = " 291 compatible = "arm,idle-state";
293 idle-state-nam 292 idle-state-name = "perf-cluster-dynamic-retention";
294 arm,psci-suspe 293 arm,psci-suspend-param = <0x400000F2>;
295 entry-latency- 294 entry-latency-us = <272>;
296 exit-latency-u 295 exit-latency-us = <329>;
297 min-residency- 296 min-residency-us = <9987>;
298 local-timer-st 297 local-timer-stop;
299 }; 298 };
300 299
301 PERF_CLUSTER_SLEEP_1: 300 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
302 compatible = " 301 compatible = "arm,idle-state";
303 idle-state-nam 302 idle-state-name = "perf-cluster-retention";
304 arm,psci-suspe 303 arm,psci-suspend-param = <0x400000F3>;
305 entry-latency- 304 entry-latency-us = <332>;
306 exit-latency-u 305 exit-latency-us = <368>;
307 min-residency- 306 min-residency-us = <9987>;
308 local-timer-st 307 local-timer-stop;
309 }; 308 };
310 309
311 PERF_CLUSTER_SLEEP_2: 310 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
312 compatible = " 311 compatible = "arm,idle-state";
313 idle-state-nam 312 idle-state-name = "perf-cluster-retention";
314 arm,psci-suspe 313 arm,psci-suspend-param = <0x400000F4>;
315 entry-latency- 314 entry-latency-us = <545>;
316 exit-latency-u 315 exit-latency-us = <1609>;
317 min-residency- 316 min-residency-us = <9987>;
318 local-timer-st 317 local-timer-stop;
319 }; 318 };
320 }; 319 };
321 }; 320 };
322 321
323 firmware { 322 firmware {
324 scm { 323 scm {
325 compatible = "qcom,scm 324 compatible = "qcom,scm-msm8998", "qcom,scm";
326 }; 325 };
327 }; 326 };
328 327
329 memory@80000000 { 328 memory@80000000 {
330 device_type = "memory"; 329 device_type = "memory";
331 /* We expect the bootloader to 330 /* We expect the bootloader to fill in the reg */
332 reg = <0x0 0x80000000 0x0 0x0> 331 reg = <0x0 0x80000000 0x0 0x0>;
333 }; 332 };
334 333
335 dsi_opp_table: opp-table-dsi { 334 dsi_opp_table: opp-table-dsi {
336 compatible = "operating-points 335 compatible = "operating-points-v2";
337 336
338 opp-131250000 { 337 opp-131250000 {
339 opp-hz = /bits/ 64 <13 338 opp-hz = /bits/ 64 <131250000>;
340 required-opps = <&rpmp 339 required-opps = <&rpmpd_opp_svs>;
341 }; 340 };
342 341
343 opp-210000000 { 342 opp-210000000 {
344 opp-hz = /bits/ 64 <21 343 opp-hz = /bits/ 64 <210000000>;
345 required-opps = <&rpmp 344 required-opps = <&rpmpd_opp_svs_plus>;
346 }; 345 };
347 346
348 opp-262500000 { 347 opp-262500000 {
349 opp-hz = /bits/ 64 <26 348 opp-hz = /bits/ 64 <262500000>;
350 required-opps = <&rpmp 349 required-opps = <&rpmpd_opp_nom>;
351 }; 350 };
352 }; 351 };
353 352
354 pmu { 353 pmu {
355 compatible = "arm,armv8-pmuv3" 354 compatible = "arm,armv8-pmuv3";
356 interrupts = <GIC_PPI 6 IRQ_TY 355 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
357 }; 356 };
358 357
359 psci { 358 psci {
360 compatible = "arm,psci-1.0"; 359 compatible = "arm,psci-1.0";
361 method = "smc"; 360 method = "smc";
362 }; 361 };
363 362
364 rpm: remoteproc { 363 rpm: remoteproc {
365 compatible = "qcom,sdm660-rpm- 364 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
366 365
367 glink-edge { 366 glink-edge {
368 compatible = "qcom,gli 367 compatible = "qcom,glink-rpm";
369 368
370 interrupts = <GIC_SPI 369 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
371 qcom,rpm-msg-ram = <&r 370 qcom,rpm-msg-ram = <&rpm_msg_ram>;
372 mboxes = <&apcs_glb 0> 371 mboxes = <&apcs_glb 0>;
373 372
374 rpm_requests: rpm-requ 373 rpm_requests: rpm-requests {
375 compatible = " !! 374 compatible = "qcom,rpm-sdm660";
376 qcom,glink-cha 375 qcom,glink-channels = "rpm_requests";
377 376
378 rpmcc: clock-c 377 rpmcc: clock-controller {
379 compat 378 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
380 #clock 379 #clock-cells = <1>;
381 }; 380 };
382 381
383 rpmpd: power-c 382 rpmpd: power-controller {
384 compat 383 compatible = "qcom,sdm660-rpmpd";
385 #power 384 #power-domain-cells = <1>;
386 operat 385 operating-points-v2 = <&rpmpd_opp_table>;
387 386
388 rpmpd_ 387 rpmpd_opp_table: opp-table {
389 388 compatible = "operating-points-v2";
390 389
391 390 rpmpd_opp_ret: opp1 {
392 391 opp-level = <RPM_SMD_LEVEL_RETENTION>;
393 392 };
394 393
395 394 rpmpd_opp_ret_plus: opp2 {
396 395 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
397 396 };
398 397
399 398 rpmpd_opp_min_svs: opp3 {
400 399 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
401 400 };
402 401
403 402 rpmpd_opp_low_svs: opp4 {
404 403 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
405 404 };
406 405
407 406 rpmpd_opp_svs: opp5 {
408 407 opp-level = <RPM_SMD_LEVEL_SVS>;
409 408 };
410 409
411 410 rpmpd_opp_svs_plus: opp6 {
412 411 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
413 412 };
414 413
415 414 rpmpd_opp_nom: opp7 {
416 415 opp-level = <RPM_SMD_LEVEL_NOM>;
417 416 };
418 417
419 418 rpmpd_opp_nom_plus: opp8 {
420 419 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
421 420 };
422 421
423 422 rpmpd_opp_turbo: opp9 {
424 423 opp-level = <RPM_SMD_LEVEL_TURBO>;
425 424 };
426 }; 425 };
427 }; 426 };
428 }; 427 };
429 }; 428 };
430 }; 429 };
431 430
432 reserved-memory { 431 reserved-memory {
433 #address-cells = <2>; 432 #address-cells = <2>;
434 #size-cells = <2>; 433 #size-cells = <2>;
435 ranges; 434 ranges;
436 435
437 wlan_msa_guard: wlan-msa-guard 436 wlan_msa_guard: wlan-msa-guard@85600000 {
438 reg = <0x0 0x85600000 437 reg = <0x0 0x85600000 0x0 0x100000>;
439 no-map; 438 no-map;
440 }; 439 };
441 440
442 wlan_msa_mem: wlan-msa-mem@857 441 wlan_msa_mem: wlan-msa-mem@85700000 {
443 reg = <0x0 0x85700000 442 reg = <0x0 0x85700000 0x0 0x100000>;
444 no-map; 443 no-map;
445 }; 444 };
446 445
447 qhee_code: qhee-code@85800000 446 qhee_code: qhee-code@85800000 {
448 reg = <0x0 0x85800000 447 reg = <0x0 0x85800000 0x0 0x600000>;
449 no-map; 448 no-map;
450 }; 449 };
451 450
452 rmtfs_mem: memory@85e00000 { 451 rmtfs_mem: memory@85e00000 {
453 compatible = "qcom,rmt 452 compatible = "qcom,rmtfs-mem";
454 reg = <0x0 0x85e00000 453 reg = <0x0 0x85e00000 0x0 0x200000>;
455 no-map; 454 no-map;
456 455
457 qcom,client-id = <1>; 456 qcom,client-id = <1>;
458 qcom,vmid = <QCOM_SCM_ 457 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
459 }; 458 };
460 459
461 smem_region: smem-mem@86000000 460 smem_region: smem-mem@86000000 {
462 reg = <0 0x86000000 0 461 reg = <0 0x86000000 0 0x200000>;
463 no-map; 462 no-map;
464 }; 463 };
465 464
466 tz_mem: memory@86200000 { 465 tz_mem: memory@86200000 {
467 reg = <0x0 0x86200000 466 reg = <0x0 0x86200000 0x0 0x3300000>;
468 no-map; 467 no-map;
469 }; 468 };
470 469
471 mpss_region: mpss@8ac00000 { 470 mpss_region: mpss@8ac00000 {
472 reg = <0x0 0x8ac00000 471 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
473 no-map; 472 no-map;
474 }; 473 };
475 474
476 adsp_region: adsp@92a00000 { 475 adsp_region: adsp@92a00000 {
477 reg = <0x0 0x92a00000 476 reg = <0x0 0x92a00000 0x0 0x1e00000>;
478 no-map; 477 no-map;
479 }; 478 };
480 479
481 mba_region: mba@94800000 { 480 mba_region: mba@94800000 {
482 reg = <0x0 0x94800000 481 reg = <0x0 0x94800000 0x0 0x200000>;
483 no-map; 482 no-map;
484 }; 483 };
485 484
486 buffer_mem: tzbuffer@94a00000 485 buffer_mem: tzbuffer@94a00000 {
487 reg = <0x0 0x94a00000 486 reg = <0x0 0x94a00000 0x0 0x100000>;
488 no-map; 487 no-map;
489 }; 488 };
490 489
491 venus_region: venus@9f800000 { 490 venus_region: venus@9f800000 {
492 reg = <0x0 0x9f800000 491 reg = <0x0 0x9f800000 0x0 0x800000>;
493 no-map; 492 no-map;
494 }; 493 };
495 494
496 adsp_mem: adsp-region@f6000000 495 adsp_mem: adsp-region@f6000000 {
497 reg = <0x0 0xf6000000 496 reg = <0x0 0xf6000000 0x0 0x800000>;
498 no-map; 497 no-map;
499 }; 498 };
500 499
501 qseecom_mem: qseecom-region@f6 500 qseecom_mem: qseecom-region@f6800000 {
502 reg = <0x0 0xf6800000 501 reg = <0x0 0xf6800000 0x0 0x1400000>;
503 no-map; 502 no-map;
504 }; 503 };
505 504
506 zap_shader_region: gpu@fed0000 505 zap_shader_region: gpu@fed00000 {
507 compatible = "shared-d 506 compatible = "shared-dma-pool";
508 reg = <0x0 0xfed00000 507 reg = <0x0 0xfed00000 0x0 0xa00000>;
509 no-map; 508 no-map;
510 }; 509 };
511 }; 510 };
512 511
513 smem: smem { 512 smem: smem {
514 compatible = "qcom,smem"; 513 compatible = "qcom,smem";
515 memory-region = <&smem_region> 514 memory-region = <&smem_region>;
516 hwlocks = <&tcsr_mutex 3>; 515 hwlocks = <&tcsr_mutex 3>;
517 }; 516 };
518 517
519 smp2p-adsp { 518 smp2p-adsp {
520 compatible = "qcom,smp2p"; 519 compatible = "qcom,smp2p";
521 qcom,smem = <443>, <429>; 520 qcom,smem = <443>, <429>;
522 interrupts = <GIC_SPI 158 IRQ_ 521 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
523 mboxes = <&apcs_glb 10>; 522 mboxes = <&apcs_glb 10>;
524 qcom,local-pid = <0>; 523 qcom,local-pid = <0>;
525 qcom,remote-pid = <2>; 524 qcom,remote-pid = <2>;
526 525
527 adsp_smp2p_out: master-kernel 526 adsp_smp2p_out: master-kernel {
528 qcom,entry-name = "mas 527 qcom,entry-name = "master-kernel";
529 #qcom,smem-state-cells 528 #qcom,smem-state-cells = <1>;
530 }; 529 };
531 530
532 adsp_smp2p_in: slave-kernel { 531 adsp_smp2p_in: slave-kernel {
533 qcom,entry-name = "sla 532 qcom,entry-name = "slave-kernel";
534 interrupt-controller; 533 interrupt-controller;
535 #interrupt-cells = <2> 534 #interrupt-cells = <2>;
536 }; 535 };
537 }; 536 };
538 537
539 smp2p-mpss { 538 smp2p-mpss {
540 compatible = "qcom,smp2p"; 539 compatible = "qcom,smp2p";
541 qcom,smem = <435>, <428>; 540 qcom,smem = <435>, <428>;
542 interrupts = <GIC_SPI 451 IRQ_ 541 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
543 mboxes = <&apcs_glb 14>; 542 mboxes = <&apcs_glb 14>;
544 qcom,local-pid = <0>; 543 qcom,local-pid = <0>;
545 qcom,remote-pid = <1>; 544 qcom,remote-pid = <1>;
546 545
547 modem_smp2p_out: master-kernel 546 modem_smp2p_out: master-kernel {
548 qcom,entry-name = "mas 547 qcom,entry-name = "master-kernel";
549 #qcom,smem-state-cells 548 #qcom,smem-state-cells = <1>;
550 }; 549 };
551 550
552 modem_smp2p_in: slave-kernel { 551 modem_smp2p_in: slave-kernel {
553 qcom,entry-name = "sla 552 qcom,entry-name = "slave-kernel";
554 interrupt-controller; 553 interrupt-controller;
555 #interrupt-cells = <2> 554 #interrupt-cells = <2>;
556 }; 555 };
557 }; 556 };
558 557
559 soc@0 { 558 soc@0 {
560 #address-cells = <1>; 559 #address-cells = <1>;
561 #size-cells = <1>; 560 #size-cells = <1>;
562 ranges = <0 0 0 0xffffffff>; 561 ranges = <0 0 0 0xffffffff>;
563 compatible = "simple-bus"; 562 compatible = "simple-bus";
564 563
565 gcc: clock-controller@100000 { 564 gcc: clock-controller@100000 {
566 compatible = "qcom,gcc 565 compatible = "qcom,gcc-sdm630";
567 #clock-cells = <1>; 566 #clock-cells = <1>;
568 #reset-cells = <1>; 567 #reset-cells = <1>;
569 #power-domain-cells = 568 #power-domain-cells = <1>;
570 reg = <0x00100000 0x94 569 reg = <0x00100000 0x94000>;
571 570
572 clock-names = "xo", "s 571 clock-names = "xo", "sleep_clk";
573 clocks = <&xo_board>, 572 clocks = <&xo_board>,
574 <&slee 573 <&sleep_clk>;
575 }; 574 };
576 575
577 rpm_msg_ram: sram@778000 { 576 rpm_msg_ram: sram@778000 {
578 compatible = "qcom,rpm 577 compatible = "qcom,rpm-msg-ram";
579 reg = <0x00778000 0x70 578 reg = <0x00778000 0x7000>;
580 }; 579 };
581 580
582 qfprom: qfprom@780000 { 581 qfprom: qfprom@780000 {
583 compatible = "qcom,sdm 582 compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
584 reg = <0x00780000 0x62 583 reg = <0x00780000 0x621c>;
585 #address-cells = <1>; 584 #address-cells = <1>;
586 #size-cells = <1>; 585 #size-cells = <1>;
587 586
588 qusb2_hstx_trim: hstx- 587 qusb2_hstx_trim: hstx-trim@240 {
589 reg = <0x243 0 588 reg = <0x243 0x1>;
590 bits = <1 3>; 589 bits = <1 3>;
591 }; 590 };
592 591
593 gpu_speed_bin: gpu-spe 592 gpu_speed_bin: gpu-speed-bin@41a0 {
594 reg = <0x41a2 593 reg = <0x41a2 0x1>;
595 bits = <5 7>; 594 bits = <5 7>;
596 }; 595 };
597 }; 596 };
598 597
599 rng: rng@793000 { 598 rng: rng@793000 {
600 compatible = "qcom,prn 599 compatible = "qcom,prng-ee";
601 reg = <0x00793000 0x10 600 reg = <0x00793000 0x1000>;
602 clocks = <&gcc GCC_PRN 601 clocks = <&gcc GCC_PRNG_AHB_CLK>;
603 clock-names = "core"; 602 clock-names = "core";
604 }; 603 };
605 604
606 bimc: interconnect@1008000 { 605 bimc: interconnect@1008000 {
607 compatible = "qcom,sdm 606 compatible = "qcom,sdm660-bimc";
608 reg = <0x01008000 0x78 607 reg = <0x01008000 0x78000>;
609 #interconnect-cells = 608 #interconnect-cells = <1>;
>> 609 clock-names = "bus", "bus_a";
>> 610 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
>> 611 <&rpmcc RPM_SMD_BIMC_A_CLK>;
610 }; 612 };
611 613
612 restart@10ac000 { 614 restart@10ac000 {
613 compatible = "qcom,psh 615 compatible = "qcom,pshold";
614 reg = <0x010ac000 0x4> 616 reg = <0x010ac000 0x4>;
615 }; 617 };
616 618
617 cnoc: interconnect@1500000 { 619 cnoc: interconnect@1500000 {
618 compatible = "qcom,sdm 620 compatible = "qcom,sdm660-cnoc";
619 reg = <0x01500000 0x10 621 reg = <0x01500000 0x10000>;
620 #interconnect-cells = 622 #interconnect-cells = <1>;
>> 623 clock-names = "bus", "bus_a";
>> 624 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
>> 625 <&rpmcc RPM_SMD_CNOC_A_CLK>;
621 }; 626 };
622 627
623 snoc: interconnect@1626000 { 628 snoc: interconnect@1626000 {
624 compatible = "qcom,sdm 629 compatible = "qcom,sdm660-snoc";
625 reg = <0x01626000 0x70 630 reg = <0x01626000 0x7090>;
626 #interconnect-cells = 631 #interconnect-cells = <1>;
>> 632 clock-names = "bus", "bus_a";
>> 633 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
>> 634 <&rpmcc RPM_SMD_SNOC_A_CLK>;
627 }; 635 };
628 636
629 anoc2_smmu: iommu@16c0000 { 637 anoc2_smmu: iommu@16c0000 {
630 compatible = "qcom,sdm 638 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
631 reg = <0x016c0000 0x40 639 reg = <0x016c0000 0x40000>;
>> 640
>> 641 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 642 assigned-clock-rates = <1000>;
>> 643 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 644 clock-names = "bus";
632 #global-interrupts = < 645 #global-interrupts = <2>;
633 #iommu-cells = <1>; 646 #iommu-cells = <1>;
634 647
635 interrupts = 648 interrupts =
636 <GIC_SPI 229 I 649 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 231 I 650 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
638 651
639 <GIC_SPI 373 I 652 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 374 I 653 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
641 <GIC_SPI 375 I 654 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
642 <GIC_SPI 376 I 655 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
643 <GIC_SPI 377 I 656 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
644 <GIC_SPI 378 I 657 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
645 <GIC_SPI 462 I 658 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 463 I 659 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 464 I 660 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 465 I 661 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 466 I 662 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 467 I 663 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 353 I 664 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 354 I 665 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 355 I 666 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 356 I 667 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 357 I 668 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 358 I 669 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 359 I 670 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 360 I 671 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 442 I 672 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 443 I 673 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 444 I 674 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 447 I 675 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 468 I 676 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 469 I 677 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 472 I 678 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 473 I 679 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 474 I 680 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
668 681
669 status = "disabled"; 682 status = "disabled";
670 }; 683 };
671 684
672 a2noc: interconnect@1704000 { 685 a2noc: interconnect@1704000 {
673 compatible = "qcom,sdm 686 compatible = "qcom,sdm660-a2noc";
674 reg = <0x01704000 0xc1 687 reg = <0x01704000 0xc100>;
675 #interconnect-cells = 688 #interconnect-cells = <1>;
676 clock-names = "ipa", !! 689 clock-names = "bus",
>> 690 "bus_a",
>> 691 "ipa",
677 "ufs_axi 692 "ufs_axi",
678 "aggre2_ 693 "aggre2_ufs_axi",
679 "aggre2_ 694 "aggre2_usb3_axi",
680 "cfg_noc 695 "cfg_noc_usb2_axi";
681 clocks = <&rpmcc RPM_S !! 696 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
>> 697 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
>> 698 <&rpmcc RPM_SMD_IPA_CLK>,
682 <&gcc GCC_UFS 699 <&gcc GCC_UFS_AXI_CLK>,
683 <&gcc GCC_AGG 700 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
684 <&gcc GCC_AGG 701 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
685 <&gcc GCC_CFG 702 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
686 }; 703 };
687 704
688 mnoc: interconnect@1745000 { 705 mnoc: interconnect@1745000 {
689 compatible = "qcom,sdm 706 compatible = "qcom,sdm660-mnoc";
690 reg = <0x01745000 0xa0 707 reg = <0x01745000 0xa010>;
691 #interconnect-cells = 708 #interconnect-cells = <1>;
692 clock-names = "iface"; !! 709 clock-names = "bus", "bus_a", "iface";
693 clocks = <&mmcc AHB_CL !! 710 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
>> 711 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
>> 712 <&mmcc AHB_CLK_SRC>;
694 }; 713 };
695 714
696 tsens: thermal-sensor@10ae000 715 tsens: thermal-sensor@10ae000 {
697 compatible = "qcom,sdm 716 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
698 reg = <0x010ae000 0x10 717 reg = <0x010ae000 0x1000>, /* TM */
699 <0x010ad000 718 <0x010ad000 0x1000>; /* SROT */
700 #qcom,sensors = <12>; 719 #qcom,sensors = <12>;
701 interrupts = <GIC_SPI 720 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_ 721 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "upl 722 interrupt-names = "uplow", "critical";
704 #thermal-sensor-cells 723 #thermal-sensor-cells = <1>;
705 }; 724 };
706 725
707 tcsr_mutex: hwlock@1f40000 { 726 tcsr_mutex: hwlock@1f40000 {
708 compatible = "qcom,tcs 727 compatible = "qcom,tcsr-mutex";
709 reg = <0x01f40000 0x20 728 reg = <0x01f40000 0x20000>;
710 #hwlock-cells = <1>; 729 #hwlock-cells = <1>;
711 }; 730 };
712 731
713 tcsr_regs_1: syscon@1f60000 { 732 tcsr_regs_1: syscon@1f60000 {
714 compatible = "qcom,sdm 733 compatible = "qcom,sdm630-tcsr", "syscon";
715 reg = <0x01f60000 0x20 734 reg = <0x01f60000 0x20000>;
716 }; 735 };
717 736
718 tlmm: pinctrl@3100000 { 737 tlmm: pinctrl@3100000 {
719 compatible = "qcom,sdm 738 compatible = "qcom,sdm630-pinctrl";
720 reg = <0x03100000 0x40 739 reg = <0x03100000 0x400000>,
721 <0x03500000 740 <0x03500000 0x400000>,
722 <0x03900000 741 <0x03900000 0x400000>;
723 reg-names = "south", " 742 reg-names = "south", "center", "north";
724 interrupts = <GIC_SPI 743 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-controller; 744 gpio-controller;
726 gpio-ranges = <&tlmm 0 745 gpio-ranges = <&tlmm 0 0 114>;
727 #gpio-cells = <2>; 746 #gpio-cells = <2>;
728 interrupt-controller; 747 interrupt-controller;
729 #interrupt-cells = <2> 748 #interrupt-cells = <2>;
730 749
731 blsp1_uart1_default: b 750 blsp1_uart1_default: blsp1-uart1-default-state {
732 pins = "gpio0" 751 pins = "gpio0", "gpio1", "gpio2", "gpio3";
733 function = "bl 752 function = "blsp_uart1";
734 drive-strength 753 drive-strength = <2>;
735 bias-disable; 754 bias-disable;
736 }; 755 };
737 756
738 blsp1_uart1_sleep: bls 757 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
739 pins = "gpio0" 758 pins = "gpio0", "gpio1", "gpio2", "gpio3";
740 function = "gp 759 function = "gpio";
741 drive-strength 760 drive-strength = <2>;
742 bias-disable; 761 bias-disable;
743 }; 762 };
744 763
745 blsp1_uart2_default: b 764 blsp1_uart2_default: blsp1-uart2-default-state {
746 pins = "gpio4" 765 pins = "gpio4", "gpio5";
747 function = "bl 766 function = "blsp_uart2";
748 drive-strength 767 drive-strength = <2>;
749 bias-disable; 768 bias-disable;
750 }; 769 };
751 770
752 blsp2_uart1_default: b 771 blsp2_uart1_default: blsp2-uart1-active-state {
753 tx-rts-pins { 772 tx-rts-pins {
754 pins = 773 pins = "gpio16", "gpio19";
755 functi 774 function = "blsp_uart5";
756 drive- 775 drive-strength = <2>;
757 bias-d 776 bias-disable;
758 }; 777 };
759 778
760 rx-pins { 779 rx-pins {
761 /* 780 /*
762 * Avo 781 * Avoid garbage data while BT module
763 * is 782 * is powered off or not driving signal
764 */ 783 */
765 pins = 784 pins = "gpio17";
766 functi 785 function = "blsp_uart5";
767 drive- 786 drive-strength = <2>;
768 bias-p 787 bias-pull-up;
769 }; 788 };
770 789
771 cts-pins { 790 cts-pins {
772 /* Mat 791 /* Match the pull of the BT module */
773 pins = 792 pins = "gpio18";
774 functi 793 function = "blsp_uart5";
775 drive- 794 drive-strength = <2>;
776 bias-p 795 bias-pull-down;
777 }; 796 };
778 }; 797 };
779 798
780 blsp2_uart1_sleep: bls 799 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
781 tx-pins { 800 tx-pins {
782 pins = 801 pins = "gpio16";
783 functi 802 function = "gpio";
784 drive- 803 drive-strength = <2>;
785 bias-p 804 bias-pull-up;
786 }; 805 };
787 806
788 rx-cts-rts-pin 807 rx-cts-rts-pins {
789 pins = 808 pins = "gpio17", "gpio18", "gpio19";
790 functi 809 function = "gpio";
791 drive- 810 drive-strength = <2>;
792 bias-d 811 bias-disable;
793 }; 812 };
794 }; 813 };
795 814
796 i2c1_default: i2c1-def 815 i2c1_default: i2c1-default-state {
797 pins = "gpio2" 816 pins = "gpio2", "gpio3";
798 function = "bl 817 function = "blsp_i2c1";
799 drive-strength 818 drive-strength = <2>;
800 bias-disable; 819 bias-disable;
801 }; 820 };
802 821
803 i2c1_sleep: i2c1-sleep 822 i2c1_sleep: i2c1-sleep-state {
804 pins = "gpio2" 823 pins = "gpio2", "gpio3";
805 function = "bl 824 function = "blsp_i2c1";
806 drive-strength 825 drive-strength = <2>;
807 bias-pull-up; 826 bias-pull-up;
808 }; 827 };
809 828
810 i2c2_default: i2c2-def 829 i2c2_default: i2c2-default-state {
811 pins = "gpio6" 830 pins = "gpio6", "gpio7";
812 function = "bl 831 function = "blsp_i2c2";
813 drive-strength 832 drive-strength = <2>;
814 bias-disable; 833 bias-disable;
815 }; 834 };
816 835
817 i2c2_sleep: i2c2-sleep 836 i2c2_sleep: i2c2-sleep-state {
818 pins = "gpio6" 837 pins = "gpio6", "gpio7";
819 function = "bl 838 function = "blsp_i2c2";
820 drive-strength 839 drive-strength = <2>;
821 bias-pull-up; 840 bias-pull-up;
822 }; 841 };
823 842
824 i2c3_default: i2c3-def 843 i2c3_default: i2c3-default-state {
825 pins = "gpio10 844 pins = "gpio10", "gpio11";
826 function = "bl 845 function = "blsp_i2c3";
827 drive-strength 846 drive-strength = <2>;
828 bias-disable; 847 bias-disable;
829 }; 848 };
830 849
831 i2c3_sleep: i2c3-sleep 850 i2c3_sleep: i2c3-sleep-state {
832 pins = "gpio10 851 pins = "gpio10", "gpio11";
833 function = "bl 852 function = "blsp_i2c3";
834 drive-strength 853 drive-strength = <2>;
835 bias-pull-up; 854 bias-pull-up;
836 }; 855 };
837 856
838 i2c4_default: i2c4-def 857 i2c4_default: i2c4-default-state {
839 pins = "gpio14 858 pins = "gpio14", "gpio15";
840 function = "bl 859 function = "blsp_i2c4";
841 drive-strength 860 drive-strength = <2>;
842 bias-disable; 861 bias-disable;
843 }; 862 };
844 863
845 i2c4_sleep: i2c4-sleep 864 i2c4_sleep: i2c4-sleep-state {
846 pins = "gpio14 865 pins = "gpio14", "gpio15";
847 function = "bl 866 function = "blsp_i2c4";
848 drive-strength 867 drive-strength = <2>;
849 bias-pull-up; 868 bias-pull-up;
850 }; 869 };
851 870
852 i2c5_default: i2c5-def 871 i2c5_default: i2c5-default-state {
853 pins = "gpio18 872 pins = "gpio18", "gpio19";
854 function = "bl 873 function = "blsp_i2c5";
855 drive-strength 874 drive-strength = <2>;
856 bias-disable; 875 bias-disable;
857 }; 876 };
858 877
859 i2c5_sleep: i2c5-sleep 878 i2c5_sleep: i2c5-sleep-state {
860 pins = "gpio18 879 pins = "gpio18", "gpio19";
861 function = "bl 880 function = "blsp_i2c5";
862 drive-strength 881 drive-strength = <2>;
863 bias-pull-up; 882 bias-pull-up;
864 }; 883 };
865 884
866 i2c6_default: i2c6-def 885 i2c6_default: i2c6-default-state {
867 pins = "gpio22 886 pins = "gpio22", "gpio23";
868 function = "bl 887 function = "blsp_i2c6";
869 drive-strength 888 drive-strength = <2>;
870 bias-disable; 889 bias-disable;
871 }; 890 };
872 891
873 i2c6_sleep: i2c6-sleep 892 i2c6_sleep: i2c6-sleep-state {
874 pins = "gpio22 893 pins = "gpio22", "gpio23";
875 function = "bl 894 function = "blsp_i2c6";
876 drive-strength 895 drive-strength = <2>;
877 bias-pull-up; 896 bias-pull-up;
878 }; 897 };
879 898
880 i2c7_default: i2c7-def 899 i2c7_default: i2c7-default-state {
881 pins = "gpio26 900 pins = "gpio26", "gpio27";
882 function = "bl 901 function = "blsp_i2c7";
883 drive-strength 902 drive-strength = <2>;
884 bias-disable; 903 bias-disable;
885 }; 904 };
886 905
887 i2c7_sleep: i2c7-sleep 906 i2c7_sleep: i2c7-sleep-state {
888 pins = "gpio26 907 pins = "gpio26", "gpio27";
889 function = "bl 908 function = "blsp_i2c7";
890 drive-strength 909 drive-strength = <2>;
891 bias-pull-up; 910 bias-pull-up;
892 }; 911 };
893 912
894 i2c8_default: i2c8-def 913 i2c8_default: i2c8-default-state {
895 pins = "gpio30 914 pins = "gpio30", "gpio31";
896 function = "bl 915 function = "blsp_i2c8_a";
897 drive-strength 916 drive-strength = <2>;
898 bias-disable; 917 bias-disable;
899 }; 918 };
900 919
901 i2c8_sleep: i2c8-sleep 920 i2c8_sleep: i2c8-sleep-state {
902 pins = "gpio30 921 pins = "gpio30", "gpio31";
903 function = "bl 922 function = "blsp_i2c8_a";
904 drive-strength 923 drive-strength = <2>;
905 bias-pull-up; 924 bias-pull-up;
906 }; 925 };
907 926
908 cci0_default: cci0-def 927 cci0_default: cci0-default-state {
909 pins = "gpio36 928 pins = "gpio36","gpio37";
910 function = "cc 929 function = "cci_i2c";
911 bias-pull-up; 930 bias-pull-up;
912 drive-strength 931 drive-strength = <2>;
913 }; 932 };
914 933
915 cci1_default: cci1-def 934 cci1_default: cci1-default-state {
916 pins = "gpio38 935 pins = "gpio38","gpio39";
917 function = "cc 936 function = "cci_i2c";
918 bias-pull-up; 937 bias-pull-up;
919 drive-strength 938 drive-strength = <2>;
920 }; 939 };
921 940
922 sdc1_state_on: sdc1-on 941 sdc1_state_on: sdc1-on-state {
923 clk-pins { 942 clk-pins {
924 pins = 943 pins = "sdc1_clk";
925 bias-d 944 bias-disable;
926 drive- 945 drive-strength = <16>;
927 }; 946 };
928 947
929 cmd-pins { 948 cmd-pins {
930 pins = 949 pins = "sdc1_cmd";
931 bias-p 950 bias-pull-up;
932 drive- 951 drive-strength = <10>;
933 }; 952 };
934 953
935 data-pins { 954 data-pins {
936 pins = 955 pins = "sdc1_data";
937 bias-p 956 bias-pull-up;
938 drive- 957 drive-strength = <10>;
939 }; 958 };
940 959
941 rclk-pins { 960 rclk-pins {
942 pins = 961 pins = "sdc1_rclk";
943 bias-p 962 bias-pull-down;
944 }; 963 };
945 }; 964 };
946 965
947 sdc1_state_off: sdc1-o 966 sdc1_state_off: sdc1-off-state {
948 clk-pins { 967 clk-pins {
949 pins = 968 pins = "sdc1_clk";
950 bias-d 969 bias-disable;
951 drive- 970 drive-strength = <2>;
952 }; 971 };
953 972
954 cmd-pins { 973 cmd-pins {
955 pins = 974 pins = "sdc1_cmd";
956 bias-p 975 bias-pull-up;
957 drive- 976 drive-strength = <2>;
958 }; 977 };
959 978
960 data-pins { 979 data-pins {
961 pins = 980 pins = "sdc1_data";
962 bias-p 981 bias-pull-up;
963 drive- 982 drive-strength = <2>;
964 }; 983 };
965 984
966 rclk-pins { 985 rclk-pins {
967 pins = 986 pins = "sdc1_rclk";
968 bias-p 987 bias-pull-down;
969 }; 988 };
970 }; 989 };
971 990
972 sdc2_state_on: sdc2-on 991 sdc2_state_on: sdc2-on-state {
973 clk-pins { 992 clk-pins {
974 pins = 993 pins = "sdc2_clk";
975 bias-d 994 bias-disable;
976 drive- 995 drive-strength = <16>;
977 }; 996 };
978 997
979 cmd-pins { 998 cmd-pins {
980 pins = 999 pins = "sdc2_cmd";
981 bias-p 1000 bias-pull-up;
982 drive- 1001 drive-strength = <10>;
983 }; 1002 };
984 1003
985 data-pins { 1004 data-pins {
986 pins = 1005 pins = "sdc2_data";
987 bias-p 1006 bias-pull-up;
988 drive- 1007 drive-strength = <10>;
989 }; 1008 };
990 }; 1009 };
991 1010
992 sdc2_state_off: sdc2-o 1011 sdc2_state_off: sdc2-off-state {
993 clk-pins { 1012 clk-pins {
994 pins = 1013 pins = "sdc2_clk";
995 bias-d 1014 bias-disable;
996 drive- 1015 drive-strength = <2>;
997 }; 1016 };
998 1017
999 cmd-pins { 1018 cmd-pins {
1000 pins 1019 pins = "sdc2_cmd";
1001 bias- 1020 bias-pull-up;
1002 drive 1021 drive-strength = <2>;
1003 }; 1022 };
1004 1023
1005 data-pins { 1024 data-pins {
1006 pins 1025 pins = "sdc2_data";
1007 bias- 1026 bias-pull-up;
1008 drive 1027 drive-strength = <2>;
1009 }; 1028 };
1010 }; 1029 };
1011 }; 1030 };
1012 1031
1013 remoteproc_mss: remoteproc@40 1032 remoteproc_mss: remoteproc@4080000 {
1014 compatible = "qcom,sd 1033 compatible = "qcom,sdm660-mss-pil";
1015 reg = <0x04080000 0x1 1034 reg = <0x04080000 0x100>, <0x04180000 0x40>;
1016 reg-names = "qdsp6", 1035 reg-names = "qdsp6", "rmb";
1017 1036
1018 interrupts-extended = 1037 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1019 1038 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1020 1039 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1021 1040 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1022 1041 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1023 1042 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1024 interrupt-names = "wd 1043 interrupt-names = "wdog",
1025 "fa 1044 "fatal",
1026 "re 1045 "ready",
1027 "ha 1046 "handover",
1028 "st 1047 "stop-ack",
1029 "sh 1048 "shutdown-ack";
1030 1049
1031 clocks = <&gcc GCC_MS 1050 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1032 <&gcc GCC_BI 1051 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1033 <&gcc GCC_BO 1052 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1034 <&gcc GPLL0_ 1053 <&gcc GPLL0_OUT_MSSCC>,
1035 <&gcc GCC_MS 1054 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1036 <&gcc GCC_MS 1055 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1037 <&rpmcc RPM_ 1056 <&rpmcc RPM_SMD_QDSS_CLK>,
1038 <&rpmcc RPM_ 1057 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1039 clock-names = "iface" 1058 clock-names = "iface",
1040 "bus", 1059 "bus",
1041 "mem", 1060 "mem",
1042 "gpll0_ 1061 "gpll0_mss",
1043 "snoc_a 1062 "snoc_axi",
1044 "mnoc_a 1063 "mnoc_axi",
1045 "qdss", 1064 "qdss",
1046 "xo"; 1065 "xo";
1047 1066
1048 qcom,smem-states = <& 1067 qcom,smem-states = <&modem_smp2p_out 0>;
1049 qcom,smem-state-names 1068 qcom,smem-state-names = "stop";
1050 1069
1051 resets = <&gcc GCC_MS 1070 resets = <&gcc GCC_MSS_RESTART>;
1052 reset-names = "mss_re 1071 reset-names = "mss_restart";
1053 1072
1054 qcom,halt-regs = <&tc 1073 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1055 1074
1056 power-domains = <&rpm 1075 power-domains = <&rpmpd SDM660_VDDCX>,
1057 <&rpm 1076 <&rpmpd SDM660_VDDMX>;
1058 power-domain-names = 1077 power-domain-names = "cx", "mx";
1059 1078
1060 memory-region = <&mba 1079 memory-region = <&mba_region>, <&mpss_region>;
1061 1080
1062 status = "disabled"; 1081 status = "disabled";
1063 1082
1064 glink-edge { 1083 glink-edge {
1065 interrupts = 1084 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1066 label = "mode 1085 label = "modem";
1067 qcom,remote-p 1086 qcom,remote-pid = <1>;
1068 mboxes = <&ap 1087 mboxes = <&apcs_glb 15>;
1069 }; 1088 };
1070 }; 1089 };
1071 1090
1072 adreno_gpu: gpu@5000000 { 1091 adreno_gpu: gpu@5000000 {
1073 compatible = "qcom,ad 1092 compatible = "qcom,adreno-508.0", "qcom,adreno";
1074 1093
1075 reg = <0x05000000 0x4 1094 reg = <0x05000000 0x40000>;
1076 reg-names = "kgsl_3d0 1095 reg-names = "kgsl_3d0_reg_memory";
1077 1096
1078 interrupts = <GIC_SPI 1097 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1079 1098
1080 clocks = <&gcc GCC_GP 1099 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1081 <&gpucc GPUCC 1100 <&gpucc GPUCC_RBBMTIMER_CLK>,
1082 <&gcc GCC_BIM 1101 <&gcc GCC_BIMC_GFX_CLK>,
1083 <&gcc GCC_GPU 1102 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1084 <&gpucc GPUCC 1103 <&gpucc GPUCC_RBCPR_CLK>,
1085 <&gpucc GPUCC 1104 <&gpucc GPUCC_GFX3D_CLK>;
1086 1105
1087 clock-names = "iface" 1106 clock-names = "iface",
1088 "rbbmtimer", 1107 "rbbmtimer",
1089 "mem", 1108 "mem",
1090 "mem_iface", 1109 "mem_iface",
1091 "rbcpr", 1110 "rbcpr",
1092 "core"; 1111 "core";
1093 1112
1094 power-domains = <&rpm 1113 power-domains = <&rpmpd SDM660_VDDMX>;
1095 iommus = <&kgsl_smmu 1114 iommus = <&kgsl_smmu 0>;
1096 1115
1097 nvmem-cells = <&gpu_s 1116 nvmem-cells = <&gpu_speed_bin>;
1098 nvmem-cell-names = "s 1117 nvmem-cell-names = "speed_bin";
1099 1118
1100 interconnects = <&bim 1119 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1101 interconnect-names = 1120 interconnect-names = "gfx-mem";
1102 1121
1103 operating-points-v2 = 1122 operating-points-v2 = <&gpu_sdm630_opp_table>;
1104 #cooling-cells = <2>; <<
1105 1123
1106 status = "disabled"; 1124 status = "disabled";
1107 1125
1108 gpu_sdm630_opp_table: 1126 gpu_sdm630_opp_table: opp-table {
1109 compatible = 1127 compatible = "operating-points-v2";
1110 opp-775000000 1128 opp-775000000 {
1111 opp-h 1129 opp-hz = /bits/ 64 <775000000>;
1112 opp-l 1130 opp-level = <RPM_SMD_LEVEL_TURBO>;
1113 opp-p 1131 opp-peak-kBps = <5412000>;
1114 opp-s 1132 opp-supported-hw = <0xa2>;
1115 }; 1133 };
1116 opp-647000000 1134 opp-647000000 {
1117 opp-h 1135 opp-hz = /bits/ 64 <647000000>;
1118 opp-l 1136 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1119 opp-p 1137 opp-peak-kBps = <4068000>;
1120 opp-s 1138 opp-supported-hw = <0xff>;
1121 }; 1139 };
1122 opp-588000000 1140 opp-588000000 {
1123 opp-h 1141 opp-hz = /bits/ 64 <588000000>;
1124 opp-l 1142 opp-level = <RPM_SMD_LEVEL_NOM>;
1125 opp-p 1143 opp-peak-kBps = <3072000>;
1126 opp-s 1144 opp-supported-hw = <0xff>;
1127 }; 1145 };
1128 opp-465000000 1146 opp-465000000 {
1129 opp-h 1147 opp-hz = /bits/ 64 <465000000>;
1130 opp-l 1148 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1131 opp-p 1149 opp-peak-kBps = <2724000>;
1132 opp-s 1150 opp-supported-hw = <0xff>;
1133 }; 1151 };
1134 opp-370000000 1152 opp-370000000 {
1135 opp-h 1153 opp-hz = /bits/ 64 <370000000>;
1136 opp-l 1154 opp-level = <RPM_SMD_LEVEL_SVS>;
1137 opp-p 1155 opp-peak-kBps = <2188000>;
1138 opp-s 1156 opp-supported-hw = <0xff>;
1139 }; 1157 };
1140 opp-240000000 1158 opp-240000000 {
1141 opp-h 1159 opp-hz = /bits/ 64 <240000000>;
1142 opp-l 1160 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1143 opp-p 1161 opp-peak-kBps = <1648000>;
1144 opp-s 1162 opp-supported-hw = <0xff>;
1145 }; 1163 };
1146 opp-160000000 1164 opp-160000000 {
1147 opp-h 1165 opp-hz = /bits/ 64 <160000000>;
1148 opp-l 1166 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1149 opp-p 1167 opp-peak-kBps = <1200000>;
1150 opp-s 1168 opp-supported-hw = <0xff>;
1151 }; 1169 };
1152 }; 1170 };
1153 }; 1171 };
1154 1172
1155 kgsl_smmu: iommu@5040000 { 1173 kgsl_smmu: iommu@5040000 {
1156 compatible = "qcom,sd 1174 compatible = "qcom,sdm630-smmu-v2",
1157 "qcom,ad 1175 "qcom,adreno-smmu", "qcom,smmu-v2";
1158 reg = <0x05040000 0x1 1176 reg = <0x05040000 0x10000>;
1159 1177
1160 /* 1178 /*
1161 * GX GDSC parent is 1179 * GX GDSC parent is CX. We need to bring up CX for SMMU
1162 * but we need both u 1180 * but we need both up for Adreno. On the other hand, we
1163 * need to manage the 1181 * need to manage the GX rpmpd domain in the adreno driver.
1164 * Enable CX/GX GDSCs 1182 * Enable CX/GX GDSCs here so that we can manage just the GX
1165 * RPM Power Domain i 1183 * RPM Power Domain in the Adreno driver.
1166 */ 1184 */
1167 power-domains = <&gpu 1185 power-domains = <&gpucc GPU_GX_GDSC>;
1168 clocks = <&gcc GCC_GP 1186 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1169 <&gcc GCC_BI 1187 <&gcc GCC_BIMC_GFX_CLK>,
1170 <&gcc GCC_GP 1188 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1171 clock-names = "iface" !! 1189 clock-names = "iface", "mem", "mem_iface";
1172 "mem", <<
1173 "mem_if <<
1174 #global-interrupts = 1190 #global-interrupts = <2>;
1175 #iommu-cells = <1>; 1191 #iommu-cells = <1>;
1176 1192
1177 interrupts = 1193 interrupts =
1178 <GIC_SPI 229 1194 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 231 1195 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1180 1196
1181 <GIC_SPI 329 1197 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 330 1198 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 331 1199 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 332 1200 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 116 1201 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 117 1202 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 349 1203 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 350 1204 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1189 1205
1190 status = "disabled"; 1206 status = "disabled";
1191 }; 1207 };
1192 1208
1193 gpucc: clock-controller@50650 1209 gpucc: clock-controller@5065000 {
1194 compatible = "qcom,gp 1210 compatible = "qcom,gpucc-sdm630";
1195 #clock-cells = <1>; 1211 #clock-cells = <1>;
1196 #reset-cells = <1>; 1212 #reset-cells = <1>;
1197 #power-domain-cells = 1213 #power-domain-cells = <1>;
1198 reg = <0x05065000 0x9 1214 reg = <0x05065000 0x9038>;
1199 1215
1200 clocks = <&xo_board>, 1216 clocks = <&xo_board>,
1201 <&gcc GCC_GP 1217 <&gcc GCC_GPU_GPLL0_CLK>,
1202 <&gcc GCC_GP 1218 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1203 clock-names = "xo", 1219 clock-names = "xo",
1204 "gcc_gp 1220 "gcc_gpu_gpll0_clk",
1205 "gcc_gp 1221 "gcc_gpu_gpll0_div_clk";
1206 status = "disabled"; 1222 status = "disabled";
1207 }; 1223 };
1208 1224
1209 lpass_smmu: iommu@5100000 { 1225 lpass_smmu: iommu@5100000 {
1210 compatible = "qcom,sd 1226 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1211 reg = <0x05100000 0x4 1227 reg = <0x05100000 0x40000>;
1212 #iommu-cells = <1>; 1228 #iommu-cells = <1>;
1213 1229
1214 #global-interrupts = 1230 #global-interrupts = <2>;
1215 interrupts = 1231 interrupts =
1216 <GIC_SPI 229 1232 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 231 1233 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1218 1234
1219 <GIC_SPI 226 1235 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 393 1236 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 394 1237 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 395 1238 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 396 1239 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 397 1240 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 398 1241 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 399 1242 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 400 1243 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 401 1244 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 402 1245 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 403 1246 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 137 1247 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 224 1248 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 225 1249 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 310 1250 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 404 1251 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1236 1252
1237 status = "disabled"; 1253 status = "disabled";
1238 }; 1254 };
1239 1255
1240 sram@290000 { 1256 sram@290000 {
1241 compatible = "qcom,rp 1257 compatible = "qcom,rpm-stats";
1242 reg = <0x00290000 0x1 1258 reg = <0x00290000 0x10000>;
1243 }; 1259 };
1244 1260
1245 spmi_bus: spmi@800f000 { 1261 spmi_bus: spmi@800f000 {
1246 compatible = "qcom,sp 1262 compatible = "qcom,spmi-pmic-arb";
1247 reg = <0x0800f000 0x1 1263 reg = <0x0800f000 0x1000>,
1248 <0x08400000 0x1 1264 <0x08400000 0x1000000>,
1249 <0x09400000 0x1 1265 <0x09400000 0x1000000>,
1250 <0x0a400000 0x2 1266 <0x0a400000 0x220000>,
1251 <0x0800a000 0x3 1267 <0x0800a000 0x3000>;
1252 reg-names = "core", " 1268 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1253 interrupt-names = "pe 1269 interrupt-names = "periph_irq";
1254 interrupts = <GIC_SPI 1270 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1255 qcom,ee = <0>; 1271 qcom,ee = <0>;
1256 qcom,channel = <0>; 1272 qcom,channel = <0>;
1257 #address-cells = <2>; 1273 #address-cells = <2>;
1258 #size-cells = <0>; 1274 #size-cells = <0>;
1259 interrupt-controller; 1275 interrupt-controller;
1260 #interrupt-cells = <4 1276 #interrupt-cells = <4>;
1261 }; 1277 };
1262 1278
1263 usb3: usb@a8f8800 { 1279 usb3: usb@a8f8800 {
1264 compatible = "qcom,sd 1280 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1265 reg = <0x0a8f8800 0x4 1281 reg = <0x0a8f8800 0x400>;
1266 status = "disabled"; 1282 status = "disabled";
1267 #address-cells = <1>; 1283 #address-cells = <1>;
1268 #size-cells = <1>; 1284 #size-cells = <1>;
1269 ranges; 1285 ranges;
1270 1286
1271 clocks = <&gcc GCC_CF 1287 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1272 <&gcc GCC_US 1288 <&gcc GCC_USB30_MASTER_CLK>,
1273 <&gcc GCC_AG 1289 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1274 <&gcc GCC_US 1290 <&gcc GCC_USB30_SLEEP_CLK>,
1275 <&gcc GCC_US !! 1291 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
>> 1292 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1276 clock-names = "cfg_no 1293 clock-names = "cfg_noc",
1277 "core", 1294 "core",
1278 "iface" 1295 "iface",
1279 "sleep" 1296 "sleep",
1280 "mock_u !! 1297 "mock_utmi",
>> 1298 "bus";
1281 1299
1282 assigned-clocks = <&g 1300 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1283 <&g !! 1301 <&gcc GCC_USB30_MASTER_CLK>,
1284 assigned-clock-rates !! 1302 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
>> 1303 assigned-clock-rates = <19200000>, <120000000>,
>> 1304 <19200000>;
1285 1305
1286 interrupts = <GIC_SPI !! 1306 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI <<
1288 <GIC_SPI <<
1289 <GIC_SPI 1307 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1290 interrupt-names = "pw !! 1308 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1291 "qu <<
1292 "hs <<
1293 "ss <<
1294 1309
1295 power-domains = <&gcc 1310 power-domains = <&gcc USB_30_GDSC>;
>> 1311 qcom,select-utmi-as-pipe-clk;
1296 1312
1297 resets = <&gcc GCC_US 1313 resets = <&gcc GCC_USB_30_BCR>;
1298 1314
1299 usb3_dwc3: usb@a80000 1315 usb3_dwc3: usb@a800000 {
1300 compatible = 1316 compatible = "snps,dwc3";
1301 reg = <0x0a80 1317 reg = <0x0a800000 0xc8d0>;
1302 interrupts = 1318 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1303 snps,dis_u2_s 1319 snps,dis_u2_susphy_quirk;
1304 snps,dis_enbl 1320 snps,dis_enblslpm_quirk;
1305 snps,parkmode <<
1306 1321
1307 phys = <&qusb !! 1322 /*
1308 phy-names = " !! 1323 * SDM630 technically supports USB3 but I
>> 1324 * haven't seen any devices making use of it.
>> 1325 */
>> 1326 maximum-speed = "high-speed";
>> 1327 phys = <&qusb2phy0>;
>> 1328 phy-names = "usb2-phy";
1309 snps,hird-thr 1329 snps,hird-threshold = /bits/ 8 <0>;
1310 }; 1330 };
1311 }; 1331 };
1312 1332
1313 usb3_qmpphy: phy@c010000 { <<
1314 compatible = "qcom,sd <<
1315 reg = <0x0c010000 0x1 <<
1316 <<
1317 clocks = <&gcc GCC_US <<
1318 <&gcc GCC_US <<
1319 <&gcc GCC_US <<
1320 <&gcc GCC_US <<
1321 clock-names = "aux", <<
1322 "ref", <<
1323 "cfg_ah <<
1324 "pipe"; <<
1325 clock-output-names = <<
1326 #clock-cells = <0>; <<
1327 #phy-cells = <0>; <<
1328 <<
1329 resets = <&gcc GCC_US <<
1330 <&gcc GCC_US <<
1331 reset-names = "phy", <<
1332 "phy_ph <<
1333 <<
1334 qcom,tcsr-reg = <&tcs <<
1335 <<
1336 status = "disabled"; <<
1337 }; <<
1338 <<
1339 qusb2phy0: phy@c012000 { 1333 qusb2phy0: phy@c012000 {
1340 compatible = "qcom,sd 1334 compatible = "qcom,sdm660-qusb2-phy";
1341 reg = <0x0c012000 0x1 1335 reg = <0x0c012000 0x180>;
1342 #phy-cells = <0>; 1336 #phy-cells = <0>;
1343 1337
1344 clocks = <&gcc GCC_US 1338 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1345 <&gcc GCC_RX 1339 <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1346 clock-names = "cfg_ah 1340 clock-names = "cfg_ahb", "ref";
1347 1341
1348 resets = <&gcc GCC_QU 1342 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1349 nvmem-cells = <&qusb2 1343 nvmem-cells = <&qusb2_hstx_trim>;
1350 status = "disabled"; 1344 status = "disabled";
1351 }; 1345 };
1352 1346
1353 qusb2phy1: phy@c014000 { 1347 qusb2phy1: phy@c014000 {
1354 compatible = "qcom,sd 1348 compatible = "qcom,sdm660-qusb2-phy";
1355 reg = <0x0c014000 0x1 1349 reg = <0x0c014000 0x180>;
1356 #phy-cells = <0>; 1350 #phy-cells = <0>;
1357 1351
1358 clocks = <&gcc GCC_US 1352 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1359 <&gcc GCC_RX 1353 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1360 clock-names = "cfg_ah 1354 clock-names = "cfg_ahb", "ref";
1361 1355
1362 resets = <&gcc GCC_QU 1356 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1363 nvmem-cells = <&qusb2 1357 nvmem-cells = <&qusb2_hstx_trim>;
1364 status = "disabled"; 1358 status = "disabled";
1365 }; 1359 };
1366 1360
1367 sdhc_2: mmc@c084000 { 1361 sdhc_2: mmc@c084000 {
1368 compatible = "qcom,sd 1362 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1369 reg = <0x0c084000 0x1 1363 reg = <0x0c084000 0x1000>;
1370 reg-names = "hc"; 1364 reg-names = "hc";
1371 1365
1372 interrupts = <GIC_SPI 1366 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_ 1367 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1374 interrupt-names = "hc 1368 interrupt-names = "hc_irq", "pwr_irq";
1375 1369
1376 bus-width = <4>; 1370 bus-width = <4>;
1377 1371
1378 clocks = <&gcc GCC_SD 1372 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1379 <&gcc 1373 <&gcc GCC_SDCC2_APPS_CLK>,
1380 <&xo_ 1374 <&xo_board>;
1381 clock-names = "iface" 1375 clock-names = "iface", "core", "xo";
1382 1376
1383 1377
1384 interconnects = <&a2n 1378 interconnects = <&a2noc 3 &a2noc 10>,
1385 <&gno 1379 <&gnoc 0 &cnoc 28>;
1386 interconnect-names = 1380 interconnect-names = "sdhc-ddr","cpu-sdhc";
1387 operating-points-v2 = 1381 operating-points-v2 = <&sdhc2_opp_table>;
1388 1382
1389 pinctrl-names = "defa 1383 pinctrl-names = "default", "sleep";
1390 pinctrl-0 = <&sdc2_st 1384 pinctrl-0 = <&sdc2_state_on>;
1391 pinctrl-1 = <&sdc2_st 1385 pinctrl-1 = <&sdc2_state_off>;
1392 power-domains = <&rpm 1386 power-domains = <&rpmpd SDM660_VDDCX>;
1393 1387
1394 status = "disabled"; 1388 status = "disabled";
1395 1389
1396 sdhc2_opp_table: opp- 1390 sdhc2_opp_table: opp-table {
1397 compatible = 1391 compatible = "operating-points-v2";
1398 1392
1399 opp-50000000 1393 opp-50000000 {
1400 opp-h 1394 opp-hz = /bits/ 64 <50000000>;
1401 requi 1395 required-opps = <&rpmpd_opp_low_svs>;
1402 opp-p 1396 opp-peak-kBps = <200000 140000>;
1403 opp-a 1397 opp-avg-kBps = <130718 133320>;
1404 }; 1398 };
1405 opp-10000000 1399 opp-100000000 {
1406 opp-h 1400 opp-hz = /bits/ 64 <100000000>;
1407 requi 1401 required-opps = <&rpmpd_opp_svs>;
1408 opp-p 1402 opp-peak-kBps = <250000 160000>;
1409 opp-a 1403 opp-avg-kBps = <196078 150000>;
1410 }; 1404 };
1411 opp-20000000 1405 opp-200000000 {
1412 opp-h 1406 opp-hz = /bits/ 64 <200000000>;
1413 requi 1407 required-opps = <&rpmpd_opp_nom>;
1414 opp-p 1408 opp-peak-kBps = <4096000 4096000>;
1415 opp-a 1409 opp-avg-kBps = <1338562 1338562>;
1416 }; 1410 };
1417 }; 1411 };
1418 }; 1412 };
1419 1413
1420 sdhc_1: mmc@c0c4000 { 1414 sdhc_1: mmc@c0c4000 {
1421 compatible = "qcom,sd 1415 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1422 reg = <0x0c0c4000 0x1 1416 reg = <0x0c0c4000 0x1000>,
1423 <0x0c0c5000 0x1 1417 <0x0c0c5000 0x1000>,
1424 <0x0c0c8000 0x8 1418 <0x0c0c8000 0x8000>;
1425 reg-names = "hc", "cq 1419 reg-names = "hc", "cqhci", "ice";
1426 1420
1427 interrupts = <GIC_SPI 1421 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_ 1422 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1429 interrupt-names = "hc 1423 interrupt-names = "hc_irq", "pwr_irq";
1430 1424
1431 clocks = <&gcc GCC_SD 1425 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1432 <&gcc GCC_SD 1426 <&gcc GCC_SDCC1_APPS_CLK>,
1433 <&xo_board>, 1427 <&xo_board>,
1434 <&gcc GCC_SD 1428 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1435 clock-names = "iface" 1429 clock-names = "iface", "core", "xo", "ice";
1436 1430
1437 interconnects = <&a2n 1431 interconnects = <&a2noc 2 &a2noc 10>,
1438 <&gno 1432 <&gnoc 0 &cnoc 27>;
1439 interconnect-names = 1433 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1440 operating-points-v2 = 1434 operating-points-v2 = <&sdhc1_opp_table>;
1441 pinctrl-names = "defa 1435 pinctrl-names = "default", "sleep";
1442 pinctrl-0 = <&sdc1_st 1436 pinctrl-0 = <&sdc1_state_on>;
1443 pinctrl-1 = <&sdc1_st 1437 pinctrl-1 = <&sdc1_state_off>;
1444 power-domains = <&rpm 1438 power-domains = <&rpmpd SDM660_VDDCX>;
1445 1439
1446 bus-width = <8>; 1440 bus-width = <8>;
1447 non-removable; 1441 non-removable;
1448 1442
1449 status = "disabled"; 1443 status = "disabled";
1450 1444
1451 sdhc1_opp_table: opp- 1445 sdhc1_opp_table: opp-table {
1452 compatible = 1446 compatible = "operating-points-v2";
1453 1447
1454 opp-50000000 1448 opp-50000000 {
1455 opp-h 1449 opp-hz = /bits/ 64 <50000000>;
1456 requi 1450 required-opps = <&rpmpd_opp_low_svs>;
1457 opp-p 1451 opp-peak-kBps = <200000 140000>;
1458 opp-a 1452 opp-avg-kBps = <130718 133320>;
1459 }; 1453 };
1460 opp-100000000 1454 opp-100000000 {
1461 opp-h 1455 opp-hz = /bits/ 64 <100000000>;
1462 requi 1456 required-opps = <&rpmpd_opp_svs>;
1463 opp-p 1457 opp-peak-kBps = <250000 160000>;
1464 opp-a 1458 opp-avg-kBps = <196078 150000>;
1465 }; 1459 };
1466 opp-384000000 1460 opp-384000000 {
1467 opp-h 1461 opp-hz = /bits/ 64 <384000000>;
1468 requi 1462 required-opps = <&rpmpd_opp_nom>;
1469 opp-p 1463 opp-peak-kBps = <4096000 4096000>;
1470 opp-a 1464 opp-avg-kBps = <1338562 1338562>;
1471 }; 1465 };
1472 }; 1466 };
1473 }; 1467 };
1474 1468
1475 usb2: usb@c2f8800 { 1469 usb2: usb@c2f8800 {
1476 compatible = "qcom,sd 1470 compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1477 reg = <0x0c2f8800 0x4 1471 reg = <0x0c2f8800 0x400>;
1478 status = "disabled"; 1472 status = "disabled";
1479 #address-cells = <1>; 1473 #address-cells = <1>;
1480 #size-cells = <1>; 1474 #size-cells = <1>;
1481 ranges; 1475 ranges;
1482 1476
1483 clocks = <&gcc GCC_CF 1477 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1484 <&gcc GCC_US 1478 <&gcc GCC_USB20_MASTER_CLK>,
1485 <&gcc GCC_US 1479 <&gcc GCC_USB20_SLEEP_CLK>,
1486 <&gcc GCC_US 1480 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1487 clock-names = "cfg_no 1481 clock-names = "cfg_noc", "core",
1488 "sleep" 1482 "sleep", "mock_utmi";
1489 1483
1490 assigned-clocks = <&g 1484 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1491 <&g 1485 <&gcc GCC_USB20_MASTER_CLK>;
1492 assigned-clock-rates 1486 assigned-clock-rates = <19200000>, <60000000>;
1493 1487
1494 interrupts = <GIC_SPI !! 1488 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1495 <GIC_SPI !! 1489 interrupt-names = "hs_phy_irq";
1496 <GIC_SPI <<
1497 interrupt-names = "pw <<
1498 "qu <<
1499 "hs <<
1500 1490
1501 qcom,select-utmi-as-p 1491 qcom,select-utmi-as-pipe-clk;
1502 1492
1503 resets = <&gcc GCC_US 1493 resets = <&gcc GCC_USB_20_BCR>;
1504 1494
1505 usb2_dwc3: usb@c20000 1495 usb2_dwc3: usb@c200000 {
1506 compatible = 1496 compatible = "snps,dwc3";
1507 reg = <0x0c20 1497 reg = <0x0c200000 0xc8d0>;
1508 interrupts = 1498 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1509 snps,dis_u2_s 1499 snps,dis_u2_susphy_quirk;
1510 snps,dis_enbl 1500 snps,dis_enblslpm_quirk;
1511 1501
1512 /* This is th 1502 /* This is the HS-only host */
1513 maximum-speed 1503 maximum-speed = "high-speed";
1514 phys = <&qusb 1504 phys = <&qusb2phy1>;
1515 phy-names = " 1505 phy-names = "usb2-phy";
1516 snps,hird-thr 1506 snps,hird-threshold = /bits/ 8 <0>;
1517 }; 1507 };
1518 }; 1508 };
1519 1509
1520 mmcc: clock-controller@c8c000 1510 mmcc: clock-controller@c8c0000 {
1521 compatible = "qcom,mm 1511 compatible = "qcom,mmcc-sdm630";
1522 reg = <0x0c8c0000 0x4 1512 reg = <0x0c8c0000 0x40000>;
1523 #clock-cells = <1>; 1513 #clock-cells = <1>;
1524 #reset-cells = <1>; 1514 #reset-cells = <1>;
1525 #power-domain-cells = 1515 #power-domain-cells = <1>;
1526 clock-names = "xo", 1516 clock-names = "xo",
1527 "slee 1517 "sleep_clk",
1528 "gpll 1518 "gpll0",
1529 "gpll 1519 "gpll0_div",
1530 "dsi0 1520 "dsi0pll",
1531 "dsi0 1521 "dsi0pllbyte",
1532 "dsi1 1522 "dsi1pll",
1533 "dsi1 1523 "dsi1pllbyte",
1534 "dp_l 1524 "dp_link_2x_clk_divsel_five",
1535 "dp_v 1525 "dp_vco_divided_clk_src_mux";
1536 clocks = <&rpmcc RPM_ 1526 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1537 <&sle 1527 <&sleep_clk>,
1538 <&gcc 1528 <&gcc GCC_MMSS_GPLL0_CLK>,
1539 <&gcc 1529 <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1540 <&mds 1530 <&mdss_dsi0_phy 1>,
1541 <&mds 1531 <&mdss_dsi0_phy 0>,
1542 <0>, 1532 <0>,
1543 <0>, 1533 <0>,
1544 <0>, 1534 <0>,
1545 <0>; 1535 <0>;
1546 }; 1536 };
1547 1537
1548 mdss: display-subsystem@c9000 1538 mdss: display-subsystem@c900000 {
1549 compatible = "qcom,md 1539 compatible = "qcom,mdss";
1550 reg = <0x0c900000 0x1 1540 reg = <0x0c900000 0x1000>,
1551 <0x0c9b0000 0x1 1541 <0x0c9b0000 0x1040>;
1552 reg-names = "mdss_phy 1542 reg-names = "mdss_phys", "vbif_phys";
1553 1543
1554 power-domains = <&mmc 1544 power-domains = <&mmcc MDSS_GDSC>;
1555 1545
1556 clocks = <&mmcc MDSS_ 1546 clocks = <&mmcc MDSS_AHB_CLK>,
1557 <&mmcc MDSS_ 1547 <&mmcc MDSS_AXI_CLK>,
1558 <&mmcc MDSS_ 1548 <&mmcc MDSS_VSYNC_CLK>,
1559 <&mmcc MDSS_ 1549 <&mmcc MDSS_MDP_CLK>;
1560 clock-names = "iface" 1550 clock-names = "iface",
1561 "bus", 1551 "bus",
1562 "vsync" 1552 "vsync",
1563 "core"; 1553 "core";
1564 1554
1565 interrupts = <GIC_SPI 1555 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1566 1556
1567 interrupt-controller; 1557 interrupt-controller;
1568 #interrupt-cells = <1 1558 #interrupt-cells = <1>;
1569 1559
1570 #address-cells = <1>; 1560 #address-cells = <1>;
1571 #size-cells = <1>; 1561 #size-cells = <1>;
1572 ranges; 1562 ranges;
1573 status = "disabled"; 1563 status = "disabled";
1574 1564
1575 mdp: display-controll 1565 mdp: display-controller@c901000 {
1576 compatible = 1566 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1577 reg = <0x0c90 1567 reg = <0x0c901000 0x89000>;
1578 reg-names = " 1568 reg-names = "mdp_phys";
1579 1569
1580 interrupt-par 1570 interrupt-parent = <&mdss>;
1581 interrupts = 1571 interrupts = <0>;
1582 1572
1583 assigned-cloc 1573 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1584 1574 <&mmcc MDSS_VSYNC_CLK>;
1585 assigned-cloc 1575 assigned-clock-rates = <300000000>,
1586 1576 <19200000>;
1587 clocks = <&mm 1577 clocks = <&mmcc MDSS_AHB_CLK>,
1588 <&mm 1578 <&mmcc MDSS_AXI_CLK>,
1589 <&mm 1579 <&mmcc MDSS_MDP_CLK>,
1590 <&mm 1580 <&mmcc MDSS_VSYNC_CLK>;
1591 clock-names = 1581 clock-names = "iface",
1592 1582 "bus",
1593 1583 "core",
1594 1584 "vsync";
1595 1585
1596 interconnects 1586 interconnects = <&mnoc 2 &bimc 5>,
1597 1587 <&mnoc 3 &bimc 5>,
1598 1588 <&gnoc 0 &mnoc 17>;
1599 interconnect- 1589 interconnect-names = "mdp0-mem",
1600 1590 "mdp1-mem",
1601 1591 "rotator-mem";
1602 iommus = <&mm 1592 iommus = <&mmss_smmu 0>;
1603 operating-poi 1593 operating-points-v2 = <&mdp_opp_table>;
1604 power-domains 1594 power-domains = <&rpmpd SDM660_VDDCX>;
1605 1595
1606 ports { 1596 ports {
1607 #addr 1597 #address-cells = <1>;
1608 #size 1598 #size-cells = <0>;
1609 1599
1610 port@ 1600 port@0 {
1611 1601 reg = <0>;
1612 1602 mdp5_intf1_out: endpoint {
1613 1603 remote-endpoint = <&mdss_dsi0_in>;
1614 1604 };
1615 }; 1605 };
1616 }; 1606 };
1617 1607
1618 mdp_opp_table 1608 mdp_opp_table: opp-table {
1619 compa 1609 compatible = "operating-points-v2";
1620 1610
1621 opp-1 1611 opp-150000000 {
1622 1612 opp-hz = /bits/ 64 <150000000>;
1623 1613 opp-peak-kBps = <320000 320000 76800>;
1624 1614 required-opps = <&rpmpd_opp_low_svs>;
1625 }; 1615 };
1626 opp-2 1616 opp-275000000 {
1627 1617 opp-hz = /bits/ 64 <275000000>;
1628 1618 opp-peak-kBps = <6400000 6400000 160000>;
1629 1619 required-opps = <&rpmpd_opp_svs>;
1630 }; 1620 };
1631 opp-3 1621 opp-300000000 {
1632 1622 opp-hz = /bits/ 64 <300000000>;
1633 1623 opp-peak-kBps = <6400000 6400000 190000>;
1634 1624 required-opps = <&rpmpd_opp_svs_plus>;
1635 }; 1625 };
1636 opp-3 1626 opp-330000000 {
1637 1627 opp-hz = /bits/ 64 <330000000>;
1638 1628 opp-peak-kBps = <6400000 6400000 240000>;
1639 1629 required-opps = <&rpmpd_opp_nom>;
1640 }; 1630 };
1641 opp-4 1631 opp-412500000 {
1642 1632 opp-hz = /bits/ 64 <412500000>;
1643 1633 opp-peak-kBps = <6400000 6400000 320000>;
1644 1634 required-opps = <&rpmpd_opp_turbo>;
1645 }; 1635 };
1646 }; 1636 };
1647 }; 1637 };
1648 1638
1649 mdss_dsi0: dsi@c99400 1639 mdss_dsi0: dsi@c994000 {
1650 compatible = 1640 compatible = "qcom,sdm660-dsi-ctrl",
1651 1641 "qcom,mdss-dsi-ctrl";
1652 reg = <0x0c99 1642 reg = <0x0c994000 0x400>;
1653 reg-names = " 1643 reg-names = "dsi_ctrl";
1654 1644
1655 operating-poi 1645 operating-points-v2 = <&dsi_opp_table>;
1656 power-domains 1646 power-domains = <&rpmpd SDM660_VDDCX>;
1657 1647
1658 interrupt-par 1648 interrupt-parent = <&mdss>;
1659 interrupts = 1649 interrupts = <4>;
1660 1650
1661 assigned-cloc 1651 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1662 1652 <&mmcc PCLK0_CLK_SRC>;
1663 assigned-cloc 1653 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1664 1654 <&mdss_dsi0_phy 1>;
1665 1655
1666 clocks = <&mm 1656 clocks = <&mmcc MDSS_MDP_CLK>,
1667 <&mm 1657 <&mmcc MDSS_BYTE0_CLK>,
1668 <&mm 1658 <&mmcc MDSS_BYTE0_INTF_CLK>,
1669 <&mm 1659 <&mmcc MNOC_AHB_CLK>,
1670 <&mm 1660 <&mmcc MDSS_AHB_CLK>,
1671 <&mm 1661 <&mmcc MDSS_AXI_CLK>,
1672 <&mm 1662 <&mmcc MISC_AHB_CLK>,
1673 <&mm 1663 <&mmcc MDSS_PCLK0_CLK>,
1674 <&mm 1664 <&mmcc MDSS_ESC0_CLK>;
1675 clock-names = 1665 clock-names = "mdp_core",
1676 1666 "byte",
1677 1667 "byte_intf",
1678 1668 "mnoc",
1679 1669 "iface",
1680 1670 "bus",
1681 1671 "core_mmss",
1682 1672 "pixel",
1683 1673 "core";
1684 1674
1685 phys = <&mdss 1675 phys = <&mdss_dsi0_phy>;
1686 1676
1687 status = "dis 1677 status = "disabled";
1688 1678
1689 ports { 1679 ports {
1690 #addr 1680 #address-cells = <1>;
1691 #size 1681 #size-cells = <0>;
1692 1682
1693 port@ 1683 port@0 {
1694 1684 reg = <0>;
1695 1685 mdss_dsi0_in: endpoint {
1696 1686 remote-endpoint = <&mdp5_intf1_out>;
1697 1687 };
1698 }; 1688 };
1699 1689
1700 port@ 1690 port@1 {
1701 1691 reg = <1>;
1702 1692 mdss_dsi0_out: endpoint {
1703 1693 };
1704 }; 1694 };
1705 }; 1695 };
1706 }; 1696 };
1707 1697
1708 mdss_dsi0_phy: phy@c9 1698 mdss_dsi0_phy: phy@c994400 {
1709 compatible = 1699 compatible = "qcom,dsi-phy-14nm-660";
1710 reg = <0x0c99 1700 reg = <0x0c994400 0x100>,
1711 <0x0c99 1701 <0x0c994500 0x300>,
1712 <0x0c99 1702 <0x0c994800 0x188>;
1713 reg-names = " 1703 reg-names = "dsi_phy",
1714 " 1704 "dsi_phy_lane",
1715 " 1705 "dsi_pll";
1716 1706
1717 #clock-cells 1707 #clock-cells = <1>;
1718 #phy-cells = 1708 #phy-cells = <0>;
1719 1709
1720 clocks = <&mm 1710 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1721 clock-names = 1711 clock-names = "iface", "ref";
1722 status = "dis 1712 status = "disabled";
1723 }; 1713 };
1724 }; 1714 };
1725 1715
1726 blsp1_dma: dma-controller@c14 1716 blsp1_dma: dma-controller@c144000 {
1727 compatible = "qcom,ba 1717 compatible = "qcom,bam-v1.7.0";
1728 reg = <0x0c144000 0x1 1718 reg = <0x0c144000 0x1f000>;
1729 interrupts = <GIC_SPI 1719 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1730 clocks = <&gcc GCC_BL 1720 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1731 clock-names = "bam_cl 1721 clock-names = "bam_clk";
1732 #dma-cells = <1>; 1722 #dma-cells = <1>;
1733 qcom,ee = <0>; 1723 qcom,ee = <0>;
1734 qcom,controlled-remot 1724 qcom,controlled-remotely;
1735 num-channels = <18>; 1725 num-channels = <18>;
1736 qcom,num-ees = <4>; 1726 qcom,num-ees = <4>;
1737 }; 1727 };
1738 1728
1739 blsp1_uart1: serial@c16f000 { 1729 blsp1_uart1: serial@c16f000 {
1740 compatible = "qcom,ms 1730 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1741 reg = <0x0c16f000 0x2 1731 reg = <0x0c16f000 0x200>;
1742 interrupts = <GIC_SPI 1732 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1743 clocks = <&gcc GCC_BL 1733 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1744 <&gcc GCC_BL 1734 <&gcc GCC_BLSP1_AHB_CLK>;
1745 clock-names = "core", 1735 clock-names = "core", "iface";
1746 dmas = <&blsp1_dma 0> 1736 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1747 dma-names = "tx", "rx 1737 dma-names = "tx", "rx";
1748 pinctrl-names = "defa 1738 pinctrl-names = "default", "sleep";
1749 pinctrl-0 = <&blsp1_u 1739 pinctrl-0 = <&blsp1_uart1_default>;
1750 pinctrl-1 = <&blsp1_u 1740 pinctrl-1 = <&blsp1_uart1_sleep>;
1751 status = "disabled"; 1741 status = "disabled";
1752 }; 1742 };
1753 1743
1754 blsp1_uart2: serial@c170000 { 1744 blsp1_uart2: serial@c170000 {
1755 compatible = "qcom,ms 1745 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1756 reg = <0x0c170000 0x1 1746 reg = <0x0c170000 0x1000>;
1757 interrupts = <GIC_SPI 1747 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1758 clocks = <&gcc GCC_BL 1748 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1759 <&gcc GCC_BL 1749 <&gcc GCC_BLSP1_AHB_CLK>;
1760 clock-names = "core", 1750 clock-names = "core", "iface";
1761 dmas = <&blsp1_dma 2> 1751 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1762 dma-names = "tx", "rx 1752 dma-names = "tx", "rx";
1763 pinctrl-names = "defa 1753 pinctrl-names = "default";
1764 pinctrl-0 = <&blsp1_u 1754 pinctrl-0 = <&blsp1_uart2_default>;
1765 status = "disabled"; 1755 status = "disabled";
1766 }; 1756 };
1767 1757
1768 blsp_i2c1: i2c@c175000 { 1758 blsp_i2c1: i2c@c175000 {
1769 compatible = "qcom,i2 1759 compatible = "qcom,i2c-qup-v2.2.1";
1770 reg = <0x0c175000 0x6 1760 reg = <0x0c175000 0x600>;
1771 interrupts = <GIC_SPI 1761 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1772 1762
1773 clocks = <&gcc GCC_BL 1763 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1774 <&gcc 1764 <&gcc GCC_BLSP1_AHB_CLK>;
1775 clock-names = "core", 1765 clock-names = "core", "iface";
1776 clock-frequency = <40 1766 clock-frequency = <400000>;
1777 dmas = <&blsp1_dma 4> 1767 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1778 dma-names = "tx", "rx 1768 dma-names = "tx", "rx";
1779 1769
1780 pinctrl-names = "defa 1770 pinctrl-names = "default", "sleep";
1781 pinctrl-0 = <&i2c1_de 1771 pinctrl-0 = <&i2c1_default>;
1782 pinctrl-1 = <&i2c1_sl 1772 pinctrl-1 = <&i2c1_sleep>;
1783 #address-cells = <1>; 1773 #address-cells = <1>;
1784 #size-cells = <0>; 1774 #size-cells = <0>;
1785 status = "disabled"; 1775 status = "disabled";
1786 }; 1776 };
1787 1777
1788 blsp_i2c2: i2c@c176000 { 1778 blsp_i2c2: i2c@c176000 {
1789 compatible = "qcom,i2 1779 compatible = "qcom,i2c-qup-v2.2.1";
1790 reg = <0x0c176000 0x6 1780 reg = <0x0c176000 0x600>;
1791 interrupts = <GIC_SPI 1781 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1792 1782
1793 clocks = <&gcc GCC_BL 1783 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1794 <&gcc GCC_BL 1784 <&gcc GCC_BLSP1_AHB_CLK>;
1795 clock-names = "core", 1785 clock-names = "core", "iface";
1796 clock-frequency = <40 1786 clock-frequency = <400000>;
1797 dmas = <&blsp1_dma 6> 1787 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1798 dma-names = "tx", "rx 1788 dma-names = "tx", "rx";
1799 1789
1800 pinctrl-names = "defa 1790 pinctrl-names = "default", "sleep";
1801 pinctrl-0 = <&i2c2_de 1791 pinctrl-0 = <&i2c2_default>;
1802 pinctrl-1 = <&i2c2_sl 1792 pinctrl-1 = <&i2c2_sleep>;
1803 #address-cells = <1>; 1793 #address-cells = <1>;
1804 #size-cells = <0>; 1794 #size-cells = <0>;
1805 status = "disabled"; 1795 status = "disabled";
1806 }; 1796 };
1807 1797
1808 blsp_i2c3: i2c@c177000 { 1798 blsp_i2c3: i2c@c177000 {
1809 compatible = "qcom,i2 1799 compatible = "qcom,i2c-qup-v2.2.1";
1810 reg = <0x0c177000 0x6 1800 reg = <0x0c177000 0x600>;
1811 interrupts = <GIC_SPI 1801 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1812 1802
1813 clocks = <&gcc GCC_BL 1803 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1814 <&gcc GCC_BL 1804 <&gcc GCC_BLSP1_AHB_CLK>;
1815 clock-names = "core", 1805 clock-names = "core", "iface";
1816 clock-frequency = <40 1806 clock-frequency = <400000>;
1817 dmas = <&blsp1_dma 8> 1807 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1818 dma-names = "tx", "rx 1808 dma-names = "tx", "rx";
1819 1809
1820 pinctrl-names = "defa 1810 pinctrl-names = "default", "sleep";
1821 pinctrl-0 = <&i2c3_de 1811 pinctrl-0 = <&i2c3_default>;
1822 pinctrl-1 = <&i2c3_sl 1812 pinctrl-1 = <&i2c3_sleep>;
1823 #address-cells = <1>; 1813 #address-cells = <1>;
1824 #size-cells = <0>; 1814 #size-cells = <0>;
1825 status = "disabled"; 1815 status = "disabled";
1826 }; 1816 };
1827 1817
1828 blsp_i2c4: i2c@c178000 { 1818 blsp_i2c4: i2c@c178000 {
1829 compatible = "qcom,i2 1819 compatible = "qcom,i2c-qup-v2.2.1";
1830 reg = <0x0c178000 0x6 1820 reg = <0x0c178000 0x600>;
1831 interrupts = <GIC_SPI 1821 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1832 1822
1833 clocks = <&gcc GCC_BL 1823 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1834 <&gcc GCC_BL 1824 <&gcc GCC_BLSP1_AHB_CLK>;
1835 clock-names = "core", 1825 clock-names = "core", "iface";
1836 clock-frequency = <40 1826 clock-frequency = <400000>;
1837 dmas = <&blsp1_dma 10 1827 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1838 dma-names = "tx", "rx 1828 dma-names = "tx", "rx";
1839 1829
1840 pinctrl-names = "defa 1830 pinctrl-names = "default", "sleep";
1841 pinctrl-0 = <&i2c4_de 1831 pinctrl-0 = <&i2c4_default>;
1842 pinctrl-1 = <&i2c4_sl 1832 pinctrl-1 = <&i2c4_sleep>;
1843 #address-cells = <1>; 1833 #address-cells = <1>;
1844 #size-cells = <0>; 1834 #size-cells = <0>;
1845 status = "disabled"; 1835 status = "disabled";
1846 }; 1836 };
1847 1837
1848 blsp2_dma: dma-controller@c18 1838 blsp2_dma: dma-controller@c184000 {
1849 compatible = "qcom,ba 1839 compatible = "qcom,bam-v1.7.0";
1850 reg = <0x0c184000 0x1 1840 reg = <0x0c184000 0x1f000>;
1851 interrupts = <GIC_SPI 1841 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1852 clocks = <&gcc GCC_BL 1842 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1853 clock-names = "bam_cl 1843 clock-names = "bam_clk";
1854 #dma-cells = <1>; 1844 #dma-cells = <1>;
1855 qcom,ee = <0>; 1845 qcom,ee = <0>;
1856 qcom,controlled-remot 1846 qcom,controlled-remotely;
1857 num-channels = <18>; 1847 num-channels = <18>;
1858 qcom,num-ees = <4>; 1848 qcom,num-ees = <4>;
1859 }; 1849 };
1860 1850
1861 blsp2_uart1: serial@c1af000 { 1851 blsp2_uart1: serial@c1af000 {
1862 compatible = "qcom,ms 1852 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1863 reg = <0x0c1af000 0x2 1853 reg = <0x0c1af000 0x200>;
1864 interrupts = <GIC_SPI 1854 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1865 clocks = <&gcc GCC_BL 1855 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1866 <&gcc GCC_BL 1856 <&gcc GCC_BLSP2_AHB_CLK>;
1867 clock-names = "core", 1857 clock-names = "core", "iface";
1868 dmas = <&blsp2_dma 0> 1858 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1869 dma-names = "tx", "rx 1859 dma-names = "tx", "rx";
1870 pinctrl-names = "defa 1860 pinctrl-names = "default", "sleep";
1871 pinctrl-0 = <&blsp2_u 1861 pinctrl-0 = <&blsp2_uart1_default>;
1872 pinctrl-1 = <&blsp2_u 1862 pinctrl-1 = <&blsp2_uart1_sleep>;
1873 status = "disabled"; 1863 status = "disabled";
1874 }; 1864 };
1875 1865
1876 blsp_i2c5: i2c@c1b5000 { 1866 blsp_i2c5: i2c@c1b5000 {
1877 compatible = "qcom,i2 1867 compatible = "qcom,i2c-qup-v2.2.1";
1878 reg = <0x0c1b5000 0x6 1868 reg = <0x0c1b5000 0x600>;
1879 interrupts = <GIC_SPI 1869 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1880 1870
1881 clocks = <&gcc GCC_BL 1871 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1882 <&gcc GCC_BL 1872 <&gcc GCC_BLSP2_AHB_CLK>;
1883 clock-names = "core", 1873 clock-names = "core", "iface";
1884 clock-frequency = <40 1874 clock-frequency = <400000>;
1885 dmas = <&blsp2_dma 4> 1875 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1886 dma-names = "tx", "rx 1876 dma-names = "tx", "rx";
1887 1877
1888 pinctrl-names = "defa 1878 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&i2c5_de 1879 pinctrl-0 = <&i2c5_default>;
1890 pinctrl-1 = <&i2c5_sl 1880 pinctrl-1 = <&i2c5_sleep>;
1891 #address-cells = <1>; 1881 #address-cells = <1>;
1892 #size-cells = <0>; 1882 #size-cells = <0>;
1893 status = "disabled"; 1883 status = "disabled";
1894 }; 1884 };
1895 1885
1896 blsp_i2c6: i2c@c1b6000 { 1886 blsp_i2c6: i2c@c1b6000 {
1897 compatible = "qcom,i2 1887 compatible = "qcom,i2c-qup-v2.2.1";
1898 reg = <0x0c1b6000 0x6 1888 reg = <0x0c1b6000 0x600>;
1899 interrupts = <GIC_SPI 1889 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1900 1890
1901 clocks = <&gcc GCC_BL 1891 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1902 <&gcc GCC_BL 1892 <&gcc GCC_BLSP2_AHB_CLK>;
1903 clock-names = "core", 1893 clock-names = "core", "iface";
1904 clock-frequency = <40 1894 clock-frequency = <400000>;
1905 dmas = <&blsp2_dma 6> 1895 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1906 dma-names = "tx", "rx 1896 dma-names = "tx", "rx";
1907 1897
1908 pinctrl-names = "defa 1898 pinctrl-names = "default", "sleep";
1909 pinctrl-0 = <&i2c6_de 1899 pinctrl-0 = <&i2c6_default>;
1910 pinctrl-1 = <&i2c6_sl 1900 pinctrl-1 = <&i2c6_sleep>;
1911 #address-cells = <1>; 1901 #address-cells = <1>;
1912 #size-cells = <0>; 1902 #size-cells = <0>;
1913 status = "disabled"; 1903 status = "disabled";
1914 }; 1904 };
1915 1905
1916 blsp_i2c7: i2c@c1b7000 { 1906 blsp_i2c7: i2c@c1b7000 {
1917 compatible = "qcom,i2 1907 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x0c1b7000 0x6 1908 reg = <0x0c1b7000 0x600>;
1919 interrupts = <GIC_SPI 1909 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1920 1910
1921 clocks = <&gcc GCC_BL 1911 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1922 <&gcc GCC_BL 1912 <&gcc GCC_BLSP2_AHB_CLK>;
1923 clock-names = "core", 1913 clock-names = "core", "iface";
1924 clock-frequency = <40 1914 clock-frequency = <400000>;
1925 dmas = <&blsp2_dma 8> 1915 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1926 dma-names = "tx", "rx 1916 dma-names = "tx", "rx";
1927 1917
1928 pinctrl-names = "defa 1918 pinctrl-names = "default", "sleep";
1929 pinctrl-0 = <&i2c7_de 1919 pinctrl-0 = <&i2c7_default>;
1930 pinctrl-1 = <&i2c7_sl 1920 pinctrl-1 = <&i2c7_sleep>;
1931 #address-cells = <1>; 1921 #address-cells = <1>;
1932 #size-cells = <0>; 1922 #size-cells = <0>;
1933 status = "disabled"; 1923 status = "disabled";
1934 }; 1924 };
1935 1925
1936 blsp_i2c8: i2c@c1b8000 { 1926 blsp_i2c8: i2c@c1b8000 {
1937 compatible = "qcom,i2 1927 compatible = "qcom,i2c-qup-v2.2.1";
1938 reg = <0x0c1b8000 0x6 1928 reg = <0x0c1b8000 0x600>;
1939 interrupts = <GIC_SPI 1929 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1940 1930
1941 clocks = <&gcc GCC_BL 1931 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1942 <&gcc GCC_BL 1932 <&gcc GCC_BLSP2_AHB_CLK>;
1943 clock-names = "core", 1933 clock-names = "core", "iface";
1944 clock-frequency = <40 1934 clock-frequency = <400000>;
1945 dmas = <&blsp2_dma 10 1935 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1946 dma-names = "tx", "rx 1936 dma-names = "tx", "rx";
1947 1937
1948 pinctrl-names = "defa 1938 pinctrl-names = "default", "sleep";
1949 pinctrl-0 = <&i2c8_de 1939 pinctrl-0 = <&i2c8_default>;
1950 pinctrl-1 = <&i2c8_sl 1940 pinctrl-1 = <&i2c8_sleep>;
1951 #address-cells = <1>; 1941 #address-cells = <1>;
1952 #size-cells = <0>; 1942 #size-cells = <0>;
1953 status = "disabled"; 1943 status = "disabled";
1954 }; 1944 };
1955 1945
1956 sram@146bf000 { 1946 sram@146bf000 {
1957 compatible = "qcom,sd 1947 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1958 reg = <0x146bf000 0x1 1948 reg = <0x146bf000 0x1000>;
1959 1949
1960 #address-cells = <1>; 1950 #address-cells = <1>;
1961 #size-cells = <1>; 1951 #size-cells = <1>;
1962 1952
1963 ranges = <0 0x146bf00 1953 ranges = <0 0x146bf000 0x1000>;
1964 1954
1965 pil-reloc@94c { 1955 pil-reloc@94c {
1966 compatible = 1956 compatible = "qcom,pil-reloc-info";
1967 reg = <0x94c 1957 reg = <0x94c 0xc8>;
1968 }; 1958 };
1969 }; 1959 };
1970 1960
1971 camss: camss@ca00020 { 1961 camss: camss@ca00020 {
1972 compatible = "qcom,sd 1962 compatible = "qcom,sdm660-camss";
1973 reg = <0x0ca00020 0x1 1963 reg = <0x0ca00020 0x10>,
1974 <0x0ca30000 0x1 1964 <0x0ca30000 0x100>,
1975 <0x0ca30400 0x1 1965 <0x0ca30400 0x100>,
1976 <0x0ca30800 0x1 1966 <0x0ca30800 0x100>,
1977 <0x0ca30c00 0x1 1967 <0x0ca30c00 0x100>,
1978 <0x0c824000 0x1 1968 <0x0c824000 0x1000>,
1979 <0x0ca00120 0x4 1969 <0x0ca00120 0x4>,
1980 <0x0c825000 0x1 1970 <0x0c825000 0x1000>,
1981 <0x0ca00124 0x4 1971 <0x0ca00124 0x4>,
1982 <0x0c826000 0x1 1972 <0x0c826000 0x1000>,
1983 <0x0ca00128 0x4 1973 <0x0ca00128 0x4>,
1984 <0x0ca31000 0x5 1974 <0x0ca31000 0x500>,
1985 <0x0ca10000 0x1 1975 <0x0ca10000 0x1000>,
1986 <0x0ca14000 0x1 1976 <0x0ca14000 0x1000>;
1987 reg-names = "csi_clk_ 1977 reg-names = "csi_clk_mux",
1988 "csid0", 1978 "csid0",
1989 "csid1", 1979 "csid1",
1990 "csid2", 1980 "csid2",
1991 "csid3", 1981 "csid3",
1992 "csiphy0" 1982 "csiphy0",
1993 "csiphy0_ 1983 "csiphy0_clk_mux",
1994 "csiphy1" 1984 "csiphy1",
1995 "csiphy1_ 1985 "csiphy1_clk_mux",
1996 "csiphy2" 1986 "csiphy2",
1997 "csiphy2_ 1987 "csiphy2_clk_mux",
1998 "ispif", 1988 "ispif",
1999 "vfe0", 1989 "vfe0",
2000 "vfe1"; 1990 "vfe1";
2001 interrupts = <GIC_SPI 1991 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
2002 <GIC_SPI 1992 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
2003 <GIC_SPI 1993 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
2004 <GIC_SPI 1994 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
2005 <GIC_SPI 1995 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
2006 <GIC_SPI 1996 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
2007 <GIC_SPI 1997 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
2008 <GIC_SPI 1998 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
2009 <GIC_SPI 1999 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2010 <GIC_SPI 2000 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2011 interrupt-names = "cs 2001 interrupt-names = "csid0",
2012 "cs 2002 "csid1",
2013 "cs 2003 "csid2",
2014 "cs 2004 "csid3",
2015 "cs 2005 "csiphy0",
2016 "cs 2006 "csiphy1",
2017 "cs 2007 "csiphy2",
2018 "is 2008 "ispif",
2019 "vf 2009 "vfe0",
2020 "vf 2010 "vfe1";
2021 clocks = <&mmcc CAMSS 2011 clocks = <&mmcc CAMSS_AHB_CLK>,
2022 <&mmcc CAMSS 2012 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2023 <&mmcc CAMSS 2013 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2024 <&mmcc CAMSS 2014 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2025 <&mmcc CAMSS 2015 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2026 <&mmcc CAMSS 2016 <&mmcc CAMSS_CSI0_AHB_CLK>,
2027 <&mmcc CAMSS 2017 <&mmcc CAMSS_CSI0_CLK>,
2028 <&mmcc CAMSS 2018 <&mmcc CAMSS_CPHY_CSID0_CLK>,
2029 <&mmcc CAMSS 2019 <&mmcc CAMSS_CSI0PIX_CLK>,
2030 <&mmcc CAMSS 2020 <&mmcc CAMSS_CSI0RDI_CLK>,
2031 <&mmcc CAMSS 2021 <&mmcc CAMSS_CSI1_AHB_CLK>,
2032 <&mmcc CAMSS 2022 <&mmcc CAMSS_CSI1_CLK>,
2033 <&mmcc CAMSS 2023 <&mmcc CAMSS_CPHY_CSID1_CLK>,
2034 <&mmcc CAMSS 2024 <&mmcc CAMSS_CSI1PIX_CLK>,
2035 <&mmcc CAMSS 2025 <&mmcc CAMSS_CSI1RDI_CLK>,
2036 <&mmcc CAMSS 2026 <&mmcc CAMSS_CSI2_AHB_CLK>,
2037 <&mmcc CAMSS 2027 <&mmcc CAMSS_CSI2_CLK>,
2038 <&mmcc CAMSS 2028 <&mmcc CAMSS_CPHY_CSID2_CLK>,
2039 <&mmcc CAMSS 2029 <&mmcc CAMSS_CSI2PIX_CLK>,
2040 <&mmcc CAMSS 2030 <&mmcc CAMSS_CSI2RDI_CLK>,
2041 <&mmcc CAMSS 2031 <&mmcc CAMSS_CSI3_AHB_CLK>,
2042 <&mmcc CAMSS 2032 <&mmcc CAMSS_CSI3_CLK>,
2043 <&mmcc CAMSS 2033 <&mmcc CAMSS_CPHY_CSID3_CLK>,
2044 <&mmcc CAMSS 2034 <&mmcc CAMSS_CSI3PIX_CLK>,
2045 <&mmcc CAMSS 2035 <&mmcc CAMSS_CSI3RDI_CLK>,
2046 <&mmcc CAMSS 2036 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2047 <&mmcc CAMSS 2037 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2048 <&mmcc CAMSS 2038 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2049 <&mmcc CSIPH 2039 <&mmcc CSIPHY_AHB2CRIF_CLK>,
2050 <&mmcc CAMSS 2040 <&mmcc CAMSS_CSI_VFE0_CLK>,
2051 <&mmcc CAMSS 2041 <&mmcc CAMSS_CSI_VFE1_CLK>,
2052 <&mmcc CAMSS 2042 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2053 <&mmcc THROT 2043 <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2054 <&mmcc CAMSS 2044 <&mmcc CAMSS_TOP_AHB_CLK>,
2055 <&mmcc CAMSS 2045 <&mmcc CAMSS_VFE0_AHB_CLK>,
2056 <&mmcc CAMSS 2046 <&mmcc CAMSS_VFE0_CLK>,
2057 <&mmcc CAMSS 2047 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2058 <&mmcc CAMSS 2048 <&mmcc CAMSS_VFE1_AHB_CLK>,
2059 <&mmcc CAMSS 2049 <&mmcc CAMSS_VFE1_CLK>,
2060 <&mmcc CAMSS 2050 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2061 <&mmcc CAMSS 2051 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2062 <&mmcc CAMSS 2052 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2063 clock-names = "ahb", 2053 clock-names = "ahb",
2064 "cphy_c 2054 "cphy_csid0",
2065 "cphy_c 2055 "cphy_csid1",
2066 "cphy_c 2056 "cphy_csid2",
2067 "cphy_c 2057 "cphy_csid3",
2068 "csi0_a 2058 "csi0_ahb",
2069 "csi0", 2059 "csi0",
2070 "csi0_p 2060 "csi0_phy",
2071 "csi0_p 2061 "csi0_pix",
2072 "csi0_r 2062 "csi0_rdi",
2073 "csi1_a 2063 "csi1_ahb",
2074 "csi1", 2064 "csi1",
2075 "csi1_p 2065 "csi1_phy",
2076 "csi1_p 2066 "csi1_pix",
2077 "csi1_r 2067 "csi1_rdi",
2078 "csi2_a 2068 "csi2_ahb",
2079 "csi2", 2069 "csi2",
2080 "csi2_p 2070 "csi2_phy",
2081 "csi2_p 2071 "csi2_pix",
2082 "csi2_r 2072 "csi2_rdi",
2083 "csi3_a 2073 "csi3_ahb",
2084 "csi3", 2074 "csi3",
2085 "csi3_p 2075 "csi3_phy",
2086 "csi3_p 2076 "csi3_pix",
2087 "csi3_r 2077 "csi3_rdi",
2088 "csiphy 2078 "csiphy0_timer",
2089 "csiphy 2079 "csiphy1_timer",
2090 "csiphy 2080 "csiphy2_timer",
2091 "csiphy 2081 "csiphy_ahb2crif",
2092 "csi_vf 2082 "csi_vfe0",
2093 "csi_vf 2083 "csi_vfe1",
2094 "ispif_ 2084 "ispif_ahb",
2095 "thrott 2085 "throttle_axi",
2096 "top_ah 2086 "top_ahb",
2097 "vfe0_a 2087 "vfe0_ahb",
2098 "vfe0", 2088 "vfe0",
2099 "vfe0_s 2089 "vfe0_stream",
2100 "vfe1_a 2090 "vfe1_ahb",
2101 "vfe1", 2091 "vfe1",
2102 "vfe1_s 2092 "vfe1_stream",
2103 "vfe_ah 2093 "vfe_ahb",
2104 "vfe_ax 2094 "vfe_axi";
2105 interconnects = <&mno 2095 interconnects = <&mnoc 5 &bimc 5>;
2106 interconnect-names = 2096 interconnect-names = "vfe-mem";
2107 iommus = <&mmss_smmu 2097 iommus = <&mmss_smmu 0xc00>,
2108 <&mmss_smmu 2098 <&mmss_smmu 0xc01>,
2109 <&mmss_smmu 2099 <&mmss_smmu 0xc02>,
2110 <&mmss_smmu 2100 <&mmss_smmu 0xc03>;
2111 power-domains = <&mmc 2101 power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2112 <&mmc 2102 <&mmcc CAMSS_VFE1_GDSC>;
2113 status = "disabled"; 2103 status = "disabled";
2114 2104
2115 ports { 2105 ports {
2116 #address-cell 2106 #address-cells = <1>;
2117 #size-cells = 2107 #size-cells = <0>;
2118 }; 2108 };
2119 }; 2109 };
2120 2110
2121 cci: cci@ca0c000 { 2111 cci: cci@ca0c000 {
2122 compatible = "qcom,ms 2112 compatible = "qcom,msm8996-cci";
2123 #address-cells = <1>; 2113 #address-cells = <1>;
2124 #size-cells = <0>; 2114 #size-cells = <0>;
2125 reg = <0x0ca0c000 0x1 2115 reg = <0x0ca0c000 0x1000>;
2126 interrupts = <GIC_SPI 2116 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2127 2117
2128 assigned-clocks = <&m 2118 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2129 <&m 2119 <&mmcc CAMSS_CCI_CLK>;
2130 assigned-clock-rates 2120 assigned-clock-rates = <80800000>, <37500000>;
2131 clocks = <&mmcc CAMSS 2121 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2132 <&mmcc CAMSS 2122 <&mmcc CAMSS_CCI_AHB_CLK>,
2133 <&mmcc CAMSS 2123 <&mmcc CAMSS_CCI_CLK>,
2134 <&mmcc CAMSS 2124 <&mmcc CAMSS_AHB_CLK>;
2135 clock-names = "camss_ 2125 clock-names = "camss_top_ahb",
2136 "cci_ah 2126 "cci_ahb",
2137 "cci", 2127 "cci",
2138 "camss_ 2128 "camss_ahb";
2139 2129
2140 pinctrl-names = "defa 2130 pinctrl-names = "default";
2141 pinctrl-0 = <&cci0_de 2131 pinctrl-0 = <&cci0_default &cci1_default>;
2142 power-domains = <&mmc 2132 power-domains = <&mmcc CAMSS_TOP_GDSC>;
2143 status = "disabled"; 2133 status = "disabled";
2144 2134
2145 cci_i2c0: i2c-bus@0 { 2135 cci_i2c0: i2c-bus@0 {
2146 reg = <0>; 2136 reg = <0>;
2147 clock-frequen 2137 clock-frequency = <400000>;
2148 #address-cell 2138 #address-cells = <1>;
2149 #size-cells = 2139 #size-cells = <0>;
2150 }; 2140 };
2151 2141
2152 cci_i2c1: i2c-bus@1 { 2142 cci_i2c1: i2c-bus@1 {
2153 reg = <1>; 2143 reg = <1>;
2154 clock-frequen 2144 clock-frequency = <400000>;
2155 #address-cell 2145 #address-cells = <1>;
2156 #size-cells = 2146 #size-cells = <0>;
2157 }; 2147 };
2158 }; 2148 };
2159 2149
2160 venus: video-codec@cc00000 { 2150 venus: video-codec@cc00000 {
2161 compatible = "qcom,sd 2151 compatible = "qcom,sdm660-venus";
2162 reg = <0x0cc00000 0xf 2152 reg = <0x0cc00000 0xff000>;
2163 clocks = <&mmcc VIDEO 2153 clocks = <&mmcc VIDEO_CORE_CLK>,
2164 <&mmcc VIDEO 2154 <&mmcc VIDEO_AHB_CLK>,
2165 <&mmcc VIDEO 2155 <&mmcc VIDEO_AXI_CLK>,
2166 <&mmcc THROT 2156 <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2167 clock-names = "core", 2157 clock-names = "core", "iface", "bus", "bus_throttle";
2168 interconnects = <&gno 2158 interconnects = <&gnoc 0 &mnoc 13>,
2169 <&mno 2159 <&mnoc 4 &bimc 5>;
2170 interconnect-names = 2160 interconnect-names = "cpu-cfg", "video-mem";
2171 interrupts = <GIC_SPI 2161 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2172 iommus = <&mmss_smmu 2162 iommus = <&mmss_smmu 0x400>,
2173 <&mmss_smmu 2163 <&mmss_smmu 0x401>,
2174 <&mmss_smmu 2164 <&mmss_smmu 0x40a>,
2175 <&mmss_smmu 2165 <&mmss_smmu 0x407>,
2176 <&mmss_smmu 2166 <&mmss_smmu 0x40e>,
2177 <&mmss_smmu 2167 <&mmss_smmu 0x40f>,
2178 <&mmss_smmu 2168 <&mmss_smmu 0x408>,
2179 <&mmss_smmu 2169 <&mmss_smmu 0x409>,
2180 <&mmss_smmu 2170 <&mmss_smmu 0x40b>,
2181 <&mmss_smmu 2171 <&mmss_smmu 0x40c>,
2182 <&mmss_smmu 2172 <&mmss_smmu 0x40d>,
2183 <&mmss_smmu 2173 <&mmss_smmu 0x410>,
2184 <&mmss_smmu 2174 <&mmss_smmu 0x421>,
2185 <&mmss_smmu 2175 <&mmss_smmu 0x428>,
2186 <&mmss_smmu 2176 <&mmss_smmu 0x429>,
2187 <&mmss_smmu 2177 <&mmss_smmu 0x42b>,
2188 <&mmss_smmu 2178 <&mmss_smmu 0x42c>,
2189 <&mmss_smmu 2179 <&mmss_smmu 0x42d>,
2190 <&mmss_smmu 2180 <&mmss_smmu 0x411>,
2191 <&mmss_smmu 2181 <&mmss_smmu 0x431>;
2192 memory-region = <&ven 2182 memory-region = <&venus_region>;
2193 power-domains = <&mmc 2183 power-domains = <&mmcc VENUS_GDSC>;
2194 status = "disabled"; 2184 status = "disabled";
2195 2185
2196 video-decoder { 2186 video-decoder {
2197 compatible = 2187 compatible = "venus-decoder";
2198 clocks = <&mm 2188 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2199 clock-names = 2189 clock-names = "vcodec0_core";
2200 power-domains 2190 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2201 }; 2191 };
2202 2192
2203 video-encoder { 2193 video-encoder {
2204 compatible = 2194 compatible = "venus-encoder";
2205 clocks = <&mm 2195 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2206 clock-names = 2196 clock-names = "vcodec0_core";
2207 power-domains 2197 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2208 }; 2198 };
2209 }; 2199 };
2210 2200
2211 mmss_smmu: iommu@cd00000 { 2201 mmss_smmu: iommu@cd00000 {
2212 compatible = "qcom,sd 2202 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2213 reg = <0x0cd00000 0x4 2203 reg = <0x0cd00000 0x40000>;
2214 2204
2215 clocks = <&mmcc MNOC_ 2205 clocks = <&mmcc MNOC_AHB_CLK>,
2216 <&mmcc BIMC_ 2206 <&mmcc BIMC_SMMU_AHB_CLK>,
>> 2207 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2217 <&mmcc BIMC_ 2208 <&mmcc BIMC_SMMU_AXI_CLK>;
2218 clock-names = "iface- 2209 clock-names = "iface-mm", "iface-smmu",
2219 "bus-sm !! 2210 "bus-mm", "bus-smmu";
2220 #global-interrupts = 2211 #global-interrupts = <2>;
2221 #iommu-cells = <1>; 2212 #iommu-cells = <1>;
2222 2213
2223 interrupts = 2214 interrupts =
2224 <GIC_SPI 229 2215 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 231 2216 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2226 2217
2227 <GIC_SPI 263 2218 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2228 <GIC_SPI 266 2219 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2229 <GIC_SPI 267 2220 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2230 <GIC_SPI 268 2221 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2231 <GIC_SPI 244 2222 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2232 <GIC_SPI 245 2223 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2233 <GIC_SPI 247 2224 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2234 <GIC_SPI 248 2225 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2235 <GIC_SPI 249 2226 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2236 <GIC_SPI 250 2227 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2237 <GIC_SPI 251 2228 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2238 <GIC_SPI 252 2229 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2239 <GIC_SPI 253 2230 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2240 <GIC_SPI 254 2231 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2241 <GIC_SPI 255 2232 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2242 <GIC_SPI 256 2233 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2243 <GIC_SPI 260 2234 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2244 <GIC_SPI 261 2235 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2245 <GIC_SPI 262 2236 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2246 <GIC_SPI 272 2237 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2247 <GIC_SPI 273 2238 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2248 <GIC_SPI 274 2239 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2249 <GIC_SPI 275 2240 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2250 <GIC_SPI 276 2241 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2251 2242
2252 status = "disabled"; 2243 status = "disabled";
2253 }; 2244 };
2254 2245
2255 adsp_pil: remoteproc@15700000 2246 adsp_pil: remoteproc@15700000 {
2256 compatible = "qcom,sd 2247 compatible = "qcom,sdm660-adsp-pas";
2257 reg = <0x15700000 0x4 2248 reg = <0x15700000 0x4040>;
2258 2249
2259 interrupts-extended = 2250 interrupts-extended =
2260 <&intc GIC_SP 2251 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2261 <&adsp_smp2p_ 2252 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2262 <&adsp_smp2p_ 2253 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2263 <&adsp_smp2p_ 2254 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2264 <&adsp_smp2p_ 2255 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2265 interrupt-names = "wd 2256 interrupt-names = "wdog", "fatal", "ready",
2266 "ha 2257 "handover", "stop-ack";
2267 2258
2268 clocks = <&rpmcc RPM_ 2259 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2269 clock-names = "xo"; 2260 clock-names = "xo";
2270 2261
2271 memory-region = <&ads 2262 memory-region = <&adsp_region>;
2272 power-domains = <&rpm 2263 power-domains = <&rpmpd SDM660_VDDCX>;
2273 power-domain-names = 2264 power-domain-names = "cx";
2274 2265
2275 qcom,smem-states = <& 2266 qcom,smem-states = <&adsp_smp2p_out 0>;
2276 qcom,smem-state-names 2267 qcom,smem-state-names = "stop";
2277 2268
2278 glink-edge { 2269 glink-edge {
2279 interrupts = 2270 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2280 2271
2281 label = "lpas 2272 label = "lpass";
2282 mboxes = <&ap 2273 mboxes = <&apcs_glb 9>;
2283 qcom,remote-p 2274 qcom,remote-pid = <2>;
2284 2275
2285 apr { 2276 apr {
2286 compa 2277 compatible = "qcom,apr-v2";
2287 qcom, 2278 qcom,glink-channels = "apr_audio_svc";
2288 qcom, 2279 qcom,domain = <APR_DOMAIN_ADSP>;
2289 #addr 2280 #address-cells = <1>;
2290 #size 2281 #size-cells = <0>;
2291 2282
2292 servi 2283 service@3 {
2293 2284 reg = <APR_SVC_ADSP_CORE>;
2294 2285 compatible = "qcom,q6core";
2295 }; 2286 };
2296 2287
2297 q6afe 2288 q6afe: service@4 {
2298 2289 compatible = "qcom,q6afe";
2299 2290 reg = <APR_SVC_AFE>;
2300 2291 q6afedai: dais {
2301 2292 compatible = "qcom,q6afe-dais";
2302 2293 #address-cells = <1>;
2303 2294 #size-cells = <0>;
2304 2295 #sound-dai-cells = <1>;
2305 2296 };
2306 }; 2297 };
2307 2298
2308 q6asm 2299 q6asm: service@7 {
2309 2300 compatible = "qcom,q6asm";
2310 2301 reg = <APR_SVC_ASM>;
2311 2302 q6asmdai: dais {
2312 2303 compatible = "qcom,q6asm-dais";
2313 2304 #address-cells = <1>;
2314 2305 #size-cells = <0>;
2315 2306 #sound-dai-cells = <1>;
2316 2307 iommus = <&lpass_smmu 1>;
2317 2308 };
2318 }; 2309 };
2319 2310
2320 q6adm 2311 q6adm: service@8 {
2321 2312 compatible = "qcom,q6adm";
2322 2313 reg = <APR_SVC_ADM>;
2323 2314 q6routing: routing {
2324 2315 compatible = "qcom,q6adm-routing";
2325 2316 #sound-dai-cells = <0>;
2326 2317 };
2327 }; 2318 };
2328 }; 2319 };
2329 }; 2320 };
2330 }; 2321 };
2331 2322
2332 gnoc: interconnect@17900000 { 2323 gnoc: interconnect@17900000 {
2333 compatible = "qcom,sd 2324 compatible = "qcom,sdm660-gnoc";
2334 reg = <0x17900000 0xe 2325 reg = <0x17900000 0xe000>;
2335 #interconnect-cells = 2326 #interconnect-cells = <1>;
>> 2327 /*
>> 2328 * This one apparently features no clocks,
>> 2329 * so let's not mess with the driver needlessly
>> 2330 */
>> 2331 clock-names = "bus", "bus_a";
>> 2332 clocks = <&xo_board>, <&xo_board>;
2336 }; 2333 };
2337 2334
2338 apcs_glb: mailbox@17911000 { 2335 apcs_glb: mailbox@17911000 {
2339 compatible = "qcom,sd 2336 compatible = "qcom,sdm660-apcs-hmss-global",
2340 "qcom,ms 2337 "qcom,msm8994-apcs-kpss-global";
2341 reg = <0x17911000 0x1 2338 reg = <0x17911000 0x1000>;
2342 2339
2343 #mbox-cells = <1>; 2340 #mbox-cells = <1>;
2344 }; 2341 };
2345 2342
2346 timer@17920000 { 2343 timer@17920000 {
2347 #address-cells = <1>; 2344 #address-cells = <1>;
2348 #size-cells = <1>; 2345 #size-cells = <1>;
2349 ranges; 2346 ranges;
2350 compatible = "arm,arm 2347 compatible = "arm,armv7-timer-mem";
2351 reg = <0x17920000 0x1 2348 reg = <0x17920000 0x1000>;
2352 clock-frequency = <19 2349 clock-frequency = <19200000>;
2353 2350
2354 frame@17921000 { 2351 frame@17921000 {
2355 frame-number 2352 frame-number = <0>;
2356 interrupts = 2353 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2357 2354 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2358 reg = <0x1792 2355 reg = <0x17921000 0x1000>,
2359 <0x17 2356 <0x17922000 0x1000>;
2360 }; 2357 };
2361 2358
2362 frame@17923000 { 2359 frame@17923000 {
2363 frame-number 2360 frame-number = <1>;
2364 interrupts = 2361 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2365 reg = <0x1792 2362 reg = <0x17923000 0x1000>;
2366 status = "dis 2363 status = "disabled";
2367 }; 2364 };
2368 2365
2369 frame@17924000 { 2366 frame@17924000 {
2370 frame-number 2367 frame-number = <2>;
2371 interrupts = 2368 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2372 reg = <0x1792 2369 reg = <0x17924000 0x1000>;
2373 status = "dis 2370 status = "disabled";
2374 }; 2371 };
2375 2372
2376 frame@17925000 { 2373 frame@17925000 {
2377 frame-number 2374 frame-number = <3>;
2378 interrupts = 2375 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2379 reg = <0x1792 2376 reg = <0x17925000 0x1000>;
2380 status = "dis 2377 status = "disabled";
2381 }; 2378 };
2382 2379
2383 frame@17926000 { 2380 frame@17926000 {
2384 frame-number 2381 frame-number = <4>;
2385 interrupts = 2382 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2386 reg = <0x1792 2383 reg = <0x17926000 0x1000>;
2387 status = "dis 2384 status = "disabled";
2388 }; 2385 };
2389 2386
2390 frame@17927000 { 2387 frame@17927000 {
2391 frame-number 2388 frame-number = <5>;
2392 interrupts = 2389 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2393 reg = <0x1792 2390 reg = <0x17927000 0x1000>;
2394 status = "dis 2391 status = "disabled";
2395 }; 2392 };
2396 2393
2397 frame@17928000 { 2394 frame@17928000 {
2398 frame-number 2395 frame-number = <6>;
2399 interrupts = 2396 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2400 reg = <0x1792 2397 reg = <0x17928000 0x1000>;
2401 status = "dis 2398 status = "disabled";
2402 }; 2399 };
2403 }; 2400 };
2404 2401
2405 intc: interrupt-controller@17 2402 intc: interrupt-controller@17a00000 {
2406 compatible = "arm,gic 2403 compatible = "arm,gic-v3";
2407 reg = <0x17a00000 0x1 2404 reg = <0x17a00000 0x10000>, /* GICD */
2408 <0x17b00000 2405 <0x17b00000 0x100000>; /* GICR * 8 */
2409 #interrupt-cells = <3 2406 #interrupt-cells = <3>;
2410 #address-cells = <1>; 2407 #address-cells = <1>;
2411 #size-cells = <1>; 2408 #size-cells = <1>;
2412 ranges; 2409 ranges;
2413 interrupt-controller; 2410 interrupt-controller;
2414 #redistributor-region 2411 #redistributor-regions = <1>;
2415 redistributor-stride 2412 redistributor-stride = <0x0 0x20000>;
2416 interrupts = <GIC_PPI 2413 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2417 }; 2414 };
2418 }; 2415 };
2419 2416
2420 sound: sound { 2417 sound: sound {
2421 }; 2418 };
2422 2419
2423 thermal-zones { 2420 thermal-zones {
2424 aoss-thermal { 2421 aoss-thermal {
2425 polling-delay-passive 2422 polling-delay-passive = <250>;
>> 2423 polling-delay = <1000>;
2426 2424
2427 thermal-sensors = <&t 2425 thermal-sensors = <&tsens 0>;
2428 2426
2429 trips { 2427 trips {
2430 aoss_alert0: 2428 aoss_alert0: trip-point0 {
2431 tempe 2429 temperature = <105000>;
2432 hyste 2430 hysteresis = <1000>;
2433 type 2431 type = "hot";
2434 }; 2432 };
2435 }; 2433 };
2436 }; 2434 };
2437 2435
2438 cpuss0-thermal { 2436 cpuss0-thermal {
2439 polling-delay-passive 2437 polling-delay-passive = <250>;
>> 2438 polling-delay = <1000>;
2440 2439
2441 thermal-sensors = <&t 2440 thermal-sensors = <&tsens 1>;
2442 2441
2443 trips { 2442 trips {
2444 cpuss0_alert0 2443 cpuss0_alert0: trip-point0 {
2445 tempe 2444 temperature = <125000>;
2446 hyste 2445 hysteresis = <1000>;
2447 type 2446 type = "hot";
2448 }; 2447 };
2449 }; 2448 };
2450 }; 2449 };
2451 2450
2452 cpuss1-thermal { 2451 cpuss1-thermal {
2453 polling-delay-passive 2452 polling-delay-passive = <250>;
>> 2453 polling-delay = <1000>;
2454 2454
2455 thermal-sensors = <&t 2455 thermal-sensors = <&tsens 2>;
2456 2456
2457 trips { 2457 trips {
2458 cpuss1_alert0 2458 cpuss1_alert0: trip-point0 {
2459 tempe 2459 temperature = <125000>;
2460 hyste 2460 hysteresis = <1000>;
2461 type 2461 type = "hot";
2462 }; 2462 };
2463 }; 2463 };
2464 }; 2464 };
2465 2465
2466 cpu0-thermal { 2466 cpu0-thermal {
2467 polling-delay-passive 2467 polling-delay-passive = <250>;
>> 2468 polling-delay = <1000>;
2468 2469
2469 thermal-sensors = <&t 2470 thermal-sensors = <&tsens 3>;
2470 2471
2471 trips { 2472 trips {
2472 cpu0_alert0: 2473 cpu0_alert0: trip-point0 {
2473 tempe 2474 temperature = <70000>;
2474 hyste 2475 hysteresis = <1000>;
2475 type 2476 type = "passive";
2476 }; 2477 };
2477 2478
2478 cpu0_crit: cp 2479 cpu0_crit: cpu-crit {
2479 tempe 2480 temperature = <110000>;
2480 hyste 2481 hysteresis = <1000>;
2481 type 2482 type = "critical";
2482 }; 2483 };
2483 }; 2484 };
2484 }; 2485 };
2485 2486
2486 cpu1-thermal { 2487 cpu1-thermal {
2487 polling-delay-passive 2488 polling-delay-passive = <250>;
>> 2489 polling-delay = <1000>;
2488 2490
2489 thermal-sensors = <&t 2491 thermal-sensors = <&tsens 4>;
2490 2492
2491 trips { 2493 trips {
2492 cpu1_alert0: 2494 cpu1_alert0: trip-point0 {
2493 tempe 2495 temperature = <70000>;
2494 hyste 2496 hysteresis = <1000>;
2495 type 2497 type = "passive";
2496 }; 2498 };
2497 2499
2498 cpu1_crit: cp 2500 cpu1_crit: cpu-crit {
2499 tempe 2501 temperature = <110000>;
2500 hyste 2502 hysteresis = <1000>;
2501 type 2503 type = "critical";
2502 }; 2504 };
2503 }; 2505 };
2504 }; 2506 };
2505 2507
2506 cpu2-thermal { 2508 cpu2-thermal {
2507 polling-delay-passive 2509 polling-delay-passive = <250>;
>> 2510 polling-delay = <1000>;
2508 2511
2509 thermal-sensors = <&t 2512 thermal-sensors = <&tsens 5>;
2510 2513
2511 trips { 2514 trips {
2512 cpu2_alert0: 2515 cpu2_alert0: trip-point0 {
2513 tempe 2516 temperature = <70000>;
2514 hyste 2517 hysteresis = <1000>;
2515 type 2518 type = "passive";
2516 }; 2519 };
2517 2520
2518 cpu2_crit: cp 2521 cpu2_crit: cpu-crit {
2519 tempe 2522 temperature = <110000>;
2520 hyste 2523 hysteresis = <1000>;
2521 type 2524 type = "critical";
2522 }; 2525 };
2523 }; 2526 };
2524 }; 2527 };
2525 2528
2526 cpu3-thermal { 2529 cpu3-thermal {
2527 polling-delay-passive 2530 polling-delay-passive = <250>;
>> 2531 polling-delay = <1000>;
2528 2532
2529 thermal-sensors = <&t 2533 thermal-sensors = <&tsens 6>;
2530 2534
2531 trips { 2535 trips {
2532 cpu3_alert0: 2536 cpu3_alert0: trip-point0 {
2533 tempe 2537 temperature = <70000>;
2534 hyste 2538 hysteresis = <1000>;
2535 type 2539 type = "passive";
2536 }; 2540 };
2537 2541
2538 cpu3_crit: cp 2542 cpu3_crit: cpu-crit {
2539 tempe 2543 temperature = <110000>;
2540 hyste 2544 hysteresis = <1000>;
2541 type 2545 type = "critical";
2542 }; 2546 };
2543 }; 2547 };
2544 }; 2548 };
2545 2549
2546 /* 2550 /*
2547 * According to what downstre 2551 * According to what downstream DTS says,
2548 * the entire power efficient 2552 * the entire power efficient cluster has
2549 * only a single thermal sens 2553 * only a single thermal sensor.
2550 */ 2554 */
2551 2555
2552 pwr-cluster-thermal { 2556 pwr-cluster-thermal {
2553 polling-delay-passive 2557 polling-delay-passive = <250>;
>> 2558 polling-delay = <1000>;
2554 2559
2555 thermal-sensors = <&t 2560 thermal-sensors = <&tsens 7>;
2556 2561
2557 trips { 2562 trips {
2558 pwr_cluster_a 2563 pwr_cluster_alert0: trip-point0 {
2559 tempe 2564 temperature = <70000>;
2560 hyste 2565 hysteresis = <1000>;
2561 type 2566 type = "passive";
2562 }; 2567 };
2563 2568
2564 pwr_cluster_c 2569 pwr_cluster_crit: cpu-crit {
2565 tempe 2570 temperature = <110000>;
2566 hyste 2571 hysteresis = <1000>;
2567 type 2572 type = "critical";
2568 }; 2573 };
2569 }; 2574 };
2570 }; 2575 };
2571 2576
2572 gpu-thermal { 2577 gpu-thermal {
2573 polling-delay-passive 2578 polling-delay-passive = <250>;
>> 2579 polling-delay = <1000>;
2574 2580
2575 thermal-sensors = <&t 2581 thermal-sensors = <&tsens 8>;
2576 2582
2577 cooling-maps { <<
2578 map0 { <<
2579 trip <<
2580 cooli <<
2581 }; <<
2582 }; <<
2583 <<
2584 trips { 2583 trips {
2585 gpu_alert0: t 2584 gpu_alert0: trip-point0 {
2586 tempe <<
2587 hyste <<
2588 type <<
2589 }; <<
2590 <<
2591 trip-point1 { <<
2592 tempe 2585 temperature = <90000>;
2593 hyste 2586 hysteresis = <1000>;
2594 type 2587 type = "hot";
2595 }; 2588 };
2596 <<
2597 trip-point2 { <<
2598 tempe <<
2599 hyste <<
2600 type <<
2601 }; <<
2602 }; 2589 };
2603 }; 2590 };
2604 }; 2591 };
2605 2592
2606 timer { 2593 timer {
2607 compatible = "arm,armv8-timer 2594 compatible = "arm,armv8-timer";
2608 interrupts = <GIC_PPI 1 (GIC_ !! 2595 interrupts = <GIC_PPI 1 0xf08>,
2609 <GIC_PPI 2 (GIC_ !! 2596 <GIC_PPI 2 0xf08>,
2610 <GIC_PPI 3 (GIC_ !! 2597 <GIC_PPI 3 0xf08>,
2611 <GIC_PPI 0 (GIC_ !! 2598 <GIC_PPI 0 0xf08>;
2612 }; 2599 };
2613 }; 2600 };
2614 2601
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