Linux/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0 2 /* 2 /* 3 * SDM845 MTP board device tree source 3 * SDM845 MTP board device tree source 4 * 4 * 5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 6 */ 7 7 8 /dts-v1/; 8 /dts-v1/; 9 9 10 #include <dt-bindings/regulator/qcom,rpmh-regu << 11 #include "sdm845.dtsi" 10 #include "sdm845.dtsi" 12 #include "pm8998.dtsi" << 13 #include "pmi8998.dtsi" << 14 11 15 / { 12 / { 16 model = "Qualcomm Technologies, Inc. S 13 model = "Qualcomm Technologies, Inc. SDM845 MTP"; 17 compatible = "qcom,sdm845-mtp", "qcom, !! 14 compatible = "qcom,sdm845-mtp"; 18 chassis-type = "handset"; << 19 << 20 aliases { << 21 serial0 = &uart9; << 22 }; << 23 << 24 chosen { << 25 stdout-path = "serial0:115200n << 26 }; << 27 << 28 vph_pwr: vph-pwr-regulator { << 29 compatible = "regulator-fixed" << 30 regulator-name = "vph_pwr"; << 31 regulator-min-microvolt = <370 << 32 regulator-max-microvolt = <370 << 33 }; << 34 << 35 /* << 36 * Apparently RPMh does not provide su << 37 * is always-on; model it as a fixed r << 38 */ << 39 vreg_s4a_1p8: pm8998-smps4 { << 40 compatible = "regulator-fixed" << 41 regulator-name = "vreg_s4a_1p8 << 42 << 43 regulator-min-microvolt = <180 << 44 regulator-max-microvolt = <180 << 45 << 46 regulator-always-on; << 47 regulator-boot-on; << 48 << 49 vin-supply = <&vph_pwr>; << 50 }; << 51 << 52 thermal-zones { << 53 xo_thermal: xo-thermal { << 54 thermal-sensors = <&pm << 55 << 56 trips { << 57 trip-point { << 58 temper << 59 hyster << 60 type = << 61 }; << 62 }; << 63 }; << 64 << 65 msm_thermal: msm-thermal { << 66 thermal-sensors = <&pm << 67 << 68 trips { << 69 trip-point { << 70 temper << 71 hyster << 72 type = << 73 }; << 74 }; << 75 }; << 76 << 77 pa_thermal: pa-thermal { << 78 thermal-sensors = <&pm << 79 << 80 trips { << 81 trip-point { << 82 temper << 83 hyster << 84 type = << 85 }; << 86 }; << 87 }; << 88 << 89 quiet_thermal: quiet-thermal { << 90 thermal-sensors = <&pm << 91 << 92 trips { << 93 trip-point { << 94 temper << 95 hyster << 96 type = << 97 }; << 98 }; << 99 }; << 100 }; << 101 }; << 102 << 103 &adsp_pas { << 104 status = "okay"; << 105 firmware-name = "qcom/sdm845/adsp.mbn" << 106 }; << 107 << 108 &apps_rsc { << 109 regulators-0 { << 110 compatible = "qcom,pm8998-rpmh << 111 qcom,pmic-id = "a"; << 112 << 113 vdd-s1-supply = <&vph_pwr>; << 114 vdd-s2-supply = <&vph_pwr>; << 115 vdd-s3-supply = <&vph_pwr>; << 116 vdd-s4-supply = <&vph_pwr>; << 117 vdd-s5-supply = <&vph_pwr>; << 118 vdd-s6-supply = <&vph_pwr>; << 119 vdd-s7-supply = <&vph_pwr>; << 120 vdd-s8-supply = <&vph_pwr>; << 121 vdd-s9-supply = <&vph_pwr>; << 122 vdd-s10-supply = <&vph_pwr>; << 123 vdd-s11-supply = <&vph_pwr>; << 124 vdd-s12-supply = <&vph_pwr>; << 125 vdd-s13-supply = <&vph_pwr>; << 126 vdd-l1-l27-supply = <&vreg_s7a << 127 vdd-l2-l8-l17-supply = <&vreg_ << 128 vdd-l3-l11-supply = <&vreg_s7a << 129 vdd-l4-l5-supply = <&vreg_s7a_ << 130 vdd-l6-supply = <&vph_pwr>; << 131 vdd-l7-l12-l14-l15-supply = <& << 132 vdd-l9-supply = <&vreg_bob>; << 133 vdd-l10-l23-l25-supply = <&vre << 134 vdd-l13-l19-l21-supply = <&vre << 135 vdd-l16-l28-supply = <&vreg_bo << 136 vdd-l18-l22-supply = <&vreg_bo << 137 vdd-l20-l24-supply = <&vreg_bo << 138 vdd-l26-supply = <&vreg_s3a_1p << 139 vin-lvs-1-2-supply = <&vreg_s4 << 140 << 141 vreg_s2a_1p125: smps2 { << 142 regulator-min-microvol << 143 regulator-max-microvol << 144 }; << 145 << 146 vreg_s3a_1p35: smps3 { << 147 regulator-min-microvol << 148 regulator-max-microvol << 149 }; << 150 << 151 vreg_s5a_2p04: smps5 { << 152 regulator-min-microvol << 153 regulator-max-microvol << 154 }; << 155 << 156 vreg_s7a_1p025: smps7 { << 157 regulator-min-microvol << 158 regulator-max-microvol << 159 }; << 160 << 161 vdd_qusb_hs0: << 162 vdda_hp_pcie_core: << 163 vdda_mipi_csi0_0p9: << 164 vdda_mipi_csi1_0p9: << 165 vdda_mipi_csi2_0p9: << 166 vdda_mipi_dsi0_pll: << 167 vdda_mipi_dsi1_pll: << 168 vdda_qlink_lv: << 169 vdda_qlink_lv_ck: << 170 vdda_qrefs_0p875: << 171 vdda_pcie_core: << 172 vdda_pll_cc_ebi01: << 173 vdda_pll_cc_ebi23: << 174 vdda_sp_sensor: << 175 vdda_ufs1_core: << 176 vdda_ufs2_core: << 177 vdda_usb1_ss_core: << 178 vdda_usb2_ss_core: << 179 vreg_l1a_0p875: ldo1 { << 180 regulator-min-microvol << 181 regulator-max-microvol << 182 regulator-initial-mode << 183 }; << 184 << 185 vddpx_10: << 186 vreg_l2a_1p2: ldo2 { << 187 regulator-min-microvol << 188 regulator-max-microvol << 189 regulator-initial-mode << 190 regulator-always-on; << 191 }; << 192 << 193 vreg_l3a_1p0: ldo3 { << 194 regulator-min-microvol << 195 regulator-max-microvol << 196 regulator-initial-mode << 197 }; << 198 << 199 vdd_wcss_cx: << 200 vdd_wcss_mx: << 201 vdda_wcss_pll: << 202 vreg_l5a_0p8: ldo5 { << 203 regulator-min-microvol << 204 regulator-max-microvol << 205 regulator-initial-mode << 206 }; << 207 << 208 vddpx_13: << 209 vreg_l6a_1p8: ldo6 { << 210 regulator-min-microvol << 211 regulator-max-microvol << 212 regulator-initial-mode << 213 }; << 214 << 215 vreg_l7a_1p8: ldo7 { << 216 regulator-min-microvol << 217 regulator-max-microvol << 218 regulator-initial-mode << 219 }; << 220 << 221 vreg_l8a_1p2: ldo8 { << 222 regulator-min-microvol << 223 regulator-max-microvol << 224 regulator-initial-mode << 225 }; << 226 << 227 vreg_l9a_1p8: ldo9 { << 228 regulator-min-microvol << 229 regulator-max-microvol << 230 regulator-initial-mode << 231 }; << 232 << 233 vreg_l10a_1p8: ldo10 { << 234 regulator-min-microvol << 235 regulator-max-microvol << 236 regulator-initial-mode << 237 }; << 238 << 239 vreg_l11a_1p0: ldo11 { << 240 regulator-min-microvol << 241 regulator-max-microvol << 242 regulator-initial-mode << 243 }; << 244 << 245 vdd_qfprom: << 246 vdd_qfprom_sp: << 247 vdda_apc1_cs_1p8: << 248 vdda_gfx_cs_1p8: << 249 vdda_qrefs_1p8: << 250 vdda_qusb_hs0_1p8: << 251 vddpx_11: << 252 vreg_l12a_1p8: ldo12 { << 253 regulator-min-microvol << 254 regulator-max-microvol << 255 regulator-initial-mode << 256 }; << 257 << 258 vddpx_2: << 259 vreg_l13a_2p95: ldo13 { << 260 regulator-min-microvol << 261 regulator-max-microvol << 262 regulator-initial-mode << 263 }; << 264 << 265 vreg_l14a_1p88: ldo14 { << 266 regulator-min-microvol << 267 regulator-max-microvol << 268 regulator-initial-mode << 269 }; << 270 << 271 vreg_l15a_1p8: ldo15 { << 272 regulator-min-microvol << 273 regulator-max-microvol << 274 regulator-initial-mode << 275 }; << 276 << 277 vreg_l16a_2p7: ldo16 { << 278 regulator-min-microvol << 279 regulator-max-microvol << 280 regulator-initial-mode << 281 }; << 282 << 283 vreg_l17a_1p3: ldo17 { << 284 regulator-min-microvol << 285 regulator-max-microvol << 286 regulator-initial-mode << 287 }; << 288 << 289 vreg_l18a_2p7: ldo18 { << 290 regulator-min-microvol << 291 regulator-max-microvol << 292 regulator-initial-mode << 293 }; << 294 << 295 vreg_l19a_3p0: ldo19 { << 296 regulator-min-microvol << 297 regulator-max-microvol << 298 regulator-initial-mode << 299 }; << 300 << 301 vreg_l20a_2p95: ldo20 { << 302 regulator-min-microvol << 303 regulator-max-microvol << 304 regulator-initial-mode << 305 }; << 306 << 307 vreg_l21a_2p95: ldo21 { << 308 regulator-min-microvol << 309 regulator-max-microvol << 310 regulator-initial-mode << 311 }; << 312 << 313 vreg_l22a_2p85: ldo22 { << 314 regulator-min-microvol << 315 regulator-max-microvol << 316 regulator-initial-mode << 317 }; << 318 << 319 vreg_l23a_3p3: ldo23 { << 320 regulator-min-microvol << 321 regulator-max-microvol << 322 regulator-initial-mode << 323 }; << 324 << 325 vdda_qusb_hs0_3p1: << 326 vreg_l24a_3p075: ldo24 { << 327 regulator-min-microvol << 328 regulator-max-microvol << 329 regulator-initial-mode << 330 }; << 331 << 332 vreg_l25a_3p3: ldo25 { << 333 regulator-min-microvol << 334 regulator-max-microvol << 335 regulator-initial-mode << 336 }; << 337 << 338 vdda_hp_pcie_1p2: << 339 vdda_hv_ebi0: << 340 vdda_hv_ebi1: << 341 vdda_hv_ebi2: << 342 vdda_hv_ebi3: << 343 vdda_mipi_csi_1p25: << 344 vdda_mipi_dsi0_1p2: << 345 vdda_mipi_dsi1_1p2: << 346 vdda_pcie_1p2: << 347 vdda_ufs1_1p2: << 348 vdda_ufs2_1p2: << 349 vdda_usb1_ss_1p2: << 350 vdda_usb2_ss_1p2: << 351 vreg_l26a_1p2: ldo26 { << 352 regulator-min-microvol << 353 regulator-max-microvol << 354 regulator-initial-mode << 355 }; << 356 << 357 vreg_l28a_3p0: ldo28 { << 358 regulator-min-microvol << 359 regulator-max-microvol << 360 regulator-initial-mode << 361 }; << 362 << 363 vreg_lvs1a_1p8: lvs1 { << 364 regulator-min-microvol << 365 regulator-max-microvol << 366 }; << 367 << 368 vreg_lvs2a_1p8: lvs2 { << 369 regulator-min-microvol << 370 regulator-max-microvol << 371 }; << 372 }; << 373 << 374 regulators-1 { << 375 compatible = "qcom,pmi8998-rpm << 376 qcom,pmic-id = "b"; << 377 << 378 vdd-bob-supply = <&vph_pwr>; << 379 << 380 vreg_bob: bob { << 381 regulator-min-microvol << 382 regulator-max-microvol << 383 regulator-initial-mode << 384 regulator-allow-bypass << 385 }; << 386 }; << 387 << 388 regulators-2 { << 389 compatible = "qcom,pm8005-rpmh << 390 qcom,pmic-id = "c"; << 391 << 392 vdd-s1-supply = <&vph_pwr>; << 393 vdd-s2-supply = <&vph_pwr>; << 394 vdd-s3-supply = <&vph_pwr>; << 395 vdd-s4-supply = <&vph_pwr>; << 396 << 397 vreg_s3c_0p6: smps3 { << 398 regulator-min-microvol << 399 regulator-max-microvol << 400 }; << 401 }; << 402 }; << 403 << 404 &cdsp_pas { << 405 status = "okay"; << 406 firmware-name = "qcom/sdm845/cdsp.mbn" << 407 }; << 408 << 409 &gcc { << 410 protected-clocks = <GCC_QSPI_CORE_CLK> << 411 <GCC_QSPI_CORE_CLK_ << 412 <GCC_QSPI_CNOC_PERI << 413 <GCC_LPASS_Q6_AXI_C << 414 <GCC_LPASS_SWAY_CLK << 415 }; << 416 << 417 &gmu { << 418 status = "okay"; << 419 }; << 420 << 421 &gpu { << 422 status = "okay"; << 423 << 424 zap-shader { << 425 memory-region = <&gpu_mem>; << 426 firmware-name = "qcom/sdm845/a << 427 }; << 428 }; << 429 << 430 &i2c10 { << 431 status = "okay"; << 432 clock-frequency = <400000>; << 433 }; << 434 << 435 &ipa { << 436 qcom,gsi-loader = "self"; << 437 memory-region = <&ipa_fw_mem>; << 438 status = "okay"; << 439 }; << 440 << 441 &mdss { << 442 status = "okay"; << 443 }; << 444 << 445 &mdss_dsi0 { << 446 status = "okay"; << 447 vdda-supply = <&vdda_mipi_dsi0_1p2>; << 448 << 449 qcom,dual-dsi-mode; << 450 qcom,master-dsi; << 451 << 452 ports { << 453 port@1 { << 454 endpoint { << 455 remote-endpoin << 456 data-lanes = < << 457 }; << 458 }; << 459 }; << 460 << 461 panel@0 { << 462 compatible = "truly,nt35597-2K << 463 reg = <0>; << 464 vdda-supply = <&vreg_l14a_1p88 << 465 << 466 reset-gpios = <&tlmm 6 GPIO_AC << 467 mode-gpios = <&tlmm 52 GPIO_AC << 468 << 469 ports { << 470 #address-cells = <1>; << 471 #size-cells = <0>; << 472 << 473 port@0 { << 474 reg = <0>; << 475 truly_in_0: en << 476 remote << 477 }; << 478 }; << 479 << 480 port@1 { << 481 reg = <1>; << 482 truly_in_1: en << 483 remote << 484 }; << 485 }; << 486 }; << 487 }; << 488 }; << 489 << 490 &mdss_dsi0_phy { << 491 status = "okay"; << 492 vdds-supply = <&vdda_mipi_dsi0_pll>; << 493 }; << 494 << 495 &mdss_dsi1 { << 496 status = "okay"; << 497 vdda-supply = <&vdda_mipi_dsi1_1p2>; << 498 << 499 qcom,dual-dsi-mode; << 500 << 501 /* DSI1 is slave, so use DSI0 clocks * << 502 assigned-clock-parents = <&mdss_dsi0_p << 503 << 504 ports { << 505 port@1 { << 506 endpoint { << 507 remote-endpoin << 508 data-lanes = < << 509 }; << 510 }; << 511 }; << 512 }; << 513 << 514 &mdss_dsi1_phy { << 515 status = "okay"; << 516 vdds-supply = <&vdda_mipi_dsi1_pll>; << 517 }; << 518 << 519 &mss_pil { << 520 status = "okay"; << 521 firmware-name = "qcom/sdm845/mba.mbn", << 522 }; << 523 << 524 &pcie0 { << 525 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LO << 526 << 527 pinctrl-0 = <&pcie0_default_state>; << 528 pinctrl-names = "default"; << 529 << 530 status = "okay"; << 531 }; << 532 << 533 &pcie0_phy { << 534 vdda-phy-supply = <&vreg_l1a_0p875>; << 535 vdda-pll-supply = <&vreg_l26a_1p2>; << 536 << 537 status = "okay"; << 538 }; << 539 << 540 &pcie1 { << 541 perst-gpios = <&tlmm 102 GPIO_ACTIVE_L << 542 << 543 pinctrl-names = "default"; << 544 pinctrl-0 = <&pcie1_default_state>; << 545 << 546 status = "okay"; << 547 }; << 548 << 549 &pcie1_phy { << 550 status = "okay"; << 551 << 552 vdda-phy-supply = <&vreg_l1a_0p875>; << 553 vdda-pll-supply = <&vreg_l26a_1p2>; << 554 }; << 555 << 556 &pm8998_adc { << 557 channel@4c { << 558 reg = <ADC5_XO_THERM_100K_PU>; << 559 label = "xo_therm"; << 560 qcom,ratiometric; << 561 qcom,hw-settle-time = <200>; << 562 }; << 563 << 564 channel@4d { << 565 reg = <ADC5_AMUX_THM1_100K_PU> << 566 label = "msm_therm"; << 567 qcom,ratiometric; << 568 qcom,hw-settle-time = <200>; << 569 }; << 570 << 571 channel@4f { << 572 reg = <ADC5_AMUX_THM3_100K_PU> << 573 label = "pa_therm1"; << 574 qcom,ratiometric; << 575 qcom,hw-settle-time = <200>; << 576 }; << 577 << 578 channel@51 { << 579 reg = <ADC5_AMUX_THM5_100K_PU> << 580 label = "quiet_therm"; << 581 qcom,ratiometric; << 582 qcom,hw-settle-time = <200>; << 583 }; << 584 << 585 channel@83 { << 586 reg = <ADC5_VPH_PWR>; << 587 label = "vph_pwr"; << 588 qcom,ratiometric; << 589 qcom,hw-settle-time = <200>; << 590 }; << 591 << 592 channel@85 { << 593 reg = <ADC5_VCOIN>; << 594 label = "vcoin"; << 595 qcom,ratiometric; << 596 qcom,hw-settle-time = <200>; << 597 }; << 598 }; << 599 << 600 &pm8998_adc_tm { << 601 status = "okay"; << 602 << 603 xo-thermistor@1 { << 604 reg = <1>; << 605 io-channels = <&pm8998_adc ADC << 606 qcom,ratiometric; << 607 qcom,hw-settle-time-us = <200> << 608 }; << 609 << 610 msm-thermistor@2 { << 611 reg = <2>; << 612 io-channels = <&pm8998_adc ADC << 613 qcom,ratiometric; << 614 qcom,hw-settle-time-us = <200> << 615 }; << 616 << 617 pa-thermistor@3 { << 618 reg = <3>; << 619 io-channels = <&pm8998_adc ADC << 620 qcom,ratiometric; << 621 qcom,hw-settle-time-us = <200> << 622 }; << 623 << 624 quiet-thermistor@4 { << 625 reg = <4>; << 626 io-channels = <&pm8998_adc ADC << 627 qcom,ratiometric; << 628 qcom,hw-settle-time-us = <200> << 629 }; << 630 }; << 631 << 632 &pm8998_resin { << 633 linux,code = <KEY_VOLUMEDOWN>; << 634 status = "okay"; << 635 }; << 636 << 637 &qupv3_id_1 { << 638 status = "okay"; << 639 }; << 640 << 641 &sdhc_2 { << 642 status = "okay"; << 643 << 644 pinctrl-names = "default"; << 645 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2 << 646 << 647 vmmc-supply = <&vreg_l21a_2p95>; << 648 vqmmc-supply = <&vddpx_2>; << 649 << 650 cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW> << 651 }; << 652 << 653 &tlmm { << 654 pcie0_default_state: pcie0-default-sta << 655 clkreq-pins { << 656 pins = "gpio36"; << 657 function = "pci_e0"; << 658 bias-pull-up; << 659 }; << 660 << 661 perst-n-pins { << 662 pins = "gpio35"; << 663 function = "gpio"; << 664 drive-strength = <2>; << 665 bias-pull-down; << 666 }; << 667 << 668 wake-n-pins { << 669 pins = "gpio37"; << 670 function = "gpio"; << 671 drive-strength = <2>; << 672 bias-pull-up; << 673 }; << 674 }; << 675 << 676 pcie1_default_state: pcie1-default-sta << 677 clkreq-pins { << 678 pins = "gpio103"; << 679 function = "pci_e1"; << 680 bias-pull-up; << 681 }; << 682 << 683 perst-n-pins { << 684 pins = "gpio102"; << 685 function = "gpio"; << 686 drive-strength = <16>; << 687 bias-pull-down; << 688 }; << 689 << 690 wake-n-pins { << 691 pins = "gpio104"; << 692 function = "gpio"; << 693 drive-strength = <2>; << 694 bias-pull-up; << 695 }; << 696 }; << 697 }; << 698 << 699 &uart9 { << 700 status = "okay"; << 701 }; << 702 << 703 &ufs_mem_hc { << 704 status = "okay"; << 705 << 706 reset-gpios = <&tlmm 150 GPIO_ACTIVE_L << 707 << 708 vcc-supply = <&vreg_l20a_2p95>; << 709 vcc-max-microamp = <600000>; << 710 }; << 711 << 712 &ufs_mem_phy { << 713 status = "okay"; << 714 << 715 vdda-phy-supply = <&vdda_ufs1_core>; << 716 vdda-pll-supply = <&vdda_ufs1_1p2>; << 717 }; << 718 << 719 &usb_1 { << 720 status = "okay"; << 721 }; << 722 << 723 &usb_1_dwc3 { << 724 /* Until we have Type C hooked up we'l << 725 dr_mode = "peripheral"; << 726 }; << 727 << 728 &usb_1_hsphy { << 729 status = "okay"; << 730 << 731 vdd-supply = <&vdda_usb1_ss_core>; << 732 vdda-pll-supply = <&vdda_qusb_hs0_1p8> << 733 vdda-phy-dpdm-supply = <&vdda_qusb_hs0 << 734 << 735 qcom,imp-res-offset-value = <8>; << 736 qcom,hstx-trim-value = <QUSB2_V2_HSTX_ << 737 qcom,preemphasis-level = <QUSB2_V2_PRE << 738 qcom,preemphasis-width = <QUSB2_V2_PRE << 739 }; << 740 << 741 &usb_1_qmpphy { << 742 status = "okay"; << 743 << 744 vdda-phy-supply = <&vdda_usb1_ss_1p2>; << 745 vdda-pll-supply = <&vdda_usb1_ss_core> << 746 }; << 747 << 748 &usb_2 { << 749 status = "okay"; << 750 }; << 751 << 752 &usb_2_dwc3 { << 753 /* << 754 * Though the USB block on SDM845 can << 755 * signal for this port on MTP. Thus << 756 * hub that works without vbus) the on << 757 * peripheral mode. << 758 */ << 759 dr_mode = "peripheral"; << 760 }; << 761 << 762 &usb_2_hsphy { << 763 status = "okay"; << 764 << 765 vdd-supply = <&vdda_usb2_ss_core>; << 766 vdda-pll-supply = <&vdda_qusb_hs0_1p8> << 767 vdda-phy-dpdm-supply = <&vdda_qusb_hs0 << 768 << 769 qcom,imp-res-offset-value = <8>; << 770 qcom,hstx-trim-value = <QUSB2_V2_HSTX_ << 771 }; << 772 << 773 &usb_2_qmpphy { << 774 status = "okay"; << 775 << 776 vdda-phy-supply = <&vdda_usb2_ss_1p2>; << 777 vdda-pll-supply = <&vdda_usb2_ss_core> << 778 }; << 779 << 780 &venus { << 781 status = "okay"; << 782 }; << 783 << 784 &wifi { << 785 status = "okay"; << 786 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8> << 787 vdd-1.8-xo-supply = <&vreg_l7a_1p8>; << 788 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; << 789 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; << 790 << 791 qcom,snoc-host-cap-8bit-quirk; << 792 qcom,ath10k-calibration-variant = "Qua << 793 }; << 794 << 795 /* PINCTRL - additions to nodes defined in sdm << 796 << 797 &qup_i2c10_default { << 798 drive-strength = <2>; << 799 bias-disable; << 800 }; << 801 << 802 &qup_uart9_rx { << 803 drive-strength = <2>; << 804 bias-pull-up; << 805 }; << 806 << 807 &qup_uart9_tx { << 808 drive-strength = <2>; << 809 bias-disable; << 810 }; << 811 << 812 &tlmm { << 813 gpio-reserved-ranges = <0 4>, <81 4>; << 814 << 815 sdc2_clk: sdc2-clk-state { << 816 pins = "sdc2_clk"; << 817 bias-disable; << 818 << 819 /* << 820 * It seems that mmc_test repo << 821 * strength is not 16 on clk, << 822 */ << 823 drive-strength = <16>; << 824 }; << 825 << 826 sdc2_cmd: sdc2-cmd-state { << 827 pins = "sdc2_cmd"; << 828 bias-pull-up; << 829 drive-strength = <16>; << 830 }; << 831 << 832 sdc2_data: sdc2-data-state { << 833 pins = "sdc2_data"; << 834 bias-pull-up; << 835 drive-strength = <16>; << 836 }; << 837 << 838 sd_card_det_n: sd-card-det-n-state { << 839 pins = "gpio126"; << 840 function = "gpio"; << 841 bias-pull-up; << 842 }; << 843 }; 15 };

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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts

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Differences between /scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts (Version linux-4.18.20)

TOMOYO Linux Cross Reference Linux/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts

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Differences between /scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts (Version linux-4.18.20)

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/qcom/sdm845-mtp.dts