1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 MTP board device tree source 3 * SDM845 MTP board device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
>> 10 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regu 11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include "sdm845.dtsi" 12 #include "sdm845.dtsi"
12 #include "pm8998.dtsi" <<
13 #include "pmi8998.dtsi" <<
14 13
15 / { 14 / {
16 model = "Qualcomm Technologies, Inc. S 15 model = "Qualcomm Technologies, Inc. SDM845 MTP";
17 compatible = "qcom,sdm845-mtp", "qcom, 16 compatible = "qcom,sdm845-mtp", "qcom,sdm845";
18 chassis-type = "handset"; <<
19 17
20 aliases { 18 aliases {
21 serial0 = &uart9; 19 serial0 = &uart9;
22 }; 20 };
23 21
24 chosen { 22 chosen {
25 stdout-path = "serial0:115200n 23 stdout-path = "serial0:115200n8";
26 }; 24 };
27 25
28 vph_pwr: vph-pwr-regulator { 26 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed" 27 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr"; 28 regulator-name = "vph_pwr";
31 regulator-min-microvolt = <370 29 regulator-min-microvolt = <3700000>;
32 regulator-max-microvolt = <370 30 regulator-max-microvolt = <3700000>;
33 }; 31 };
34 32
35 /* 33 /*
36 * Apparently RPMh does not provide su 34 * Apparently RPMh does not provide support for PM8998 S4 because it
37 * is always-on; model it as a fixed r 35 * is always-on; model it as a fixed regulator.
38 */ 36 */
39 vreg_s4a_1p8: pm8998-smps4 { 37 vreg_s4a_1p8: pm8998-smps4 {
40 compatible = "regulator-fixed" 38 compatible = "regulator-fixed";
41 regulator-name = "vreg_s4a_1p8 39 regulator-name = "vreg_s4a_1p8";
42 40
43 regulator-min-microvolt = <180 41 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <180 42 regulator-max-microvolt = <1800000>;
45 43
46 regulator-always-on; 44 regulator-always-on;
47 regulator-boot-on; 45 regulator-boot-on;
48 46
49 vin-supply = <&vph_pwr>; 47 vin-supply = <&vph_pwr>;
50 }; 48 };
51 <<
52 thermal-zones { <<
53 xo_thermal: xo-thermal { <<
54 thermal-sensors = <&pm <<
55 <<
56 trips { <<
57 trip-point { <<
58 temper <<
59 hyster <<
60 type = <<
61 }; <<
62 }; <<
63 }; <<
64 <<
65 msm_thermal: msm-thermal { <<
66 thermal-sensors = <&pm <<
67 <<
68 trips { <<
69 trip-point { <<
70 temper <<
71 hyster <<
72 type = <<
73 }; <<
74 }; <<
75 }; <<
76 <<
77 pa_thermal: pa-thermal { <<
78 thermal-sensors = <&pm <<
79 <<
80 trips { <<
81 trip-point { <<
82 temper <<
83 hyster <<
84 type = <<
85 }; <<
86 }; <<
87 }; <<
88 <<
89 quiet_thermal: quiet-thermal { <<
90 thermal-sensors = <&pm <<
91 <<
92 trips { <<
93 trip-point { <<
94 temper <<
95 hyster <<
96 type = <<
97 }; <<
98 }; <<
99 }; <<
100 }; <<
101 }; 49 };
102 50
103 &adsp_pas { 51 &adsp_pas {
104 status = "okay"; 52 status = "okay";
105 firmware-name = "qcom/sdm845/adsp.mbn" !! 53 firmware-name = "qcom/sdm845/adsp.mdt";
106 }; 54 };
107 55
108 &apps_rsc { 56 &apps_rsc {
109 regulators-0 { !! 57 pm8998-rpmh-regulators {
110 compatible = "qcom,pm8998-rpmh 58 compatible = "qcom,pm8998-rpmh-regulators";
111 qcom,pmic-id = "a"; 59 qcom,pmic-id = "a";
112 60
113 vdd-s1-supply = <&vph_pwr>; 61 vdd-s1-supply = <&vph_pwr>;
114 vdd-s2-supply = <&vph_pwr>; 62 vdd-s2-supply = <&vph_pwr>;
115 vdd-s3-supply = <&vph_pwr>; 63 vdd-s3-supply = <&vph_pwr>;
116 vdd-s4-supply = <&vph_pwr>; 64 vdd-s4-supply = <&vph_pwr>;
117 vdd-s5-supply = <&vph_pwr>; 65 vdd-s5-supply = <&vph_pwr>;
118 vdd-s6-supply = <&vph_pwr>; 66 vdd-s6-supply = <&vph_pwr>;
119 vdd-s7-supply = <&vph_pwr>; 67 vdd-s7-supply = <&vph_pwr>;
120 vdd-s8-supply = <&vph_pwr>; 68 vdd-s8-supply = <&vph_pwr>;
121 vdd-s9-supply = <&vph_pwr>; 69 vdd-s9-supply = <&vph_pwr>;
122 vdd-s10-supply = <&vph_pwr>; 70 vdd-s10-supply = <&vph_pwr>;
123 vdd-s11-supply = <&vph_pwr>; 71 vdd-s11-supply = <&vph_pwr>;
124 vdd-s12-supply = <&vph_pwr>; 72 vdd-s12-supply = <&vph_pwr>;
125 vdd-s13-supply = <&vph_pwr>; 73 vdd-s13-supply = <&vph_pwr>;
126 vdd-l1-l27-supply = <&vreg_s7a 74 vdd-l1-l27-supply = <&vreg_s7a_1p025>;
127 vdd-l2-l8-l17-supply = <&vreg_ 75 vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
128 vdd-l3-l11-supply = <&vreg_s7a 76 vdd-l3-l11-supply = <&vreg_s7a_1p025>;
129 vdd-l4-l5-supply = <&vreg_s7a_ 77 vdd-l4-l5-supply = <&vreg_s7a_1p025>;
130 vdd-l6-supply = <&vph_pwr>; 78 vdd-l6-supply = <&vph_pwr>;
131 vdd-l7-l12-l14-l15-supply = <& 79 vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
132 vdd-l9-supply = <&vreg_bob>; 80 vdd-l9-supply = <&vreg_bob>;
133 vdd-l10-l23-l25-supply = <&vre 81 vdd-l10-l23-l25-supply = <&vreg_bob>;
134 vdd-l13-l19-l21-supply = <&vre 82 vdd-l13-l19-l21-supply = <&vreg_bob>;
135 vdd-l16-l28-supply = <&vreg_bo 83 vdd-l16-l28-supply = <&vreg_bob>;
136 vdd-l18-l22-supply = <&vreg_bo 84 vdd-l18-l22-supply = <&vreg_bob>;
137 vdd-l20-l24-supply = <&vreg_bo 85 vdd-l20-l24-supply = <&vreg_bob>;
138 vdd-l26-supply = <&vreg_s3a_1p 86 vdd-l26-supply = <&vreg_s3a_1p35>;
139 vin-lvs-1-2-supply = <&vreg_s4 87 vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
140 88
141 vreg_s2a_1p125: smps2 { 89 vreg_s2a_1p125: smps2 {
142 regulator-min-microvol 90 regulator-min-microvolt = <1100000>;
143 regulator-max-microvol 91 regulator-max-microvolt = <1100000>;
144 }; 92 };
145 93
146 vreg_s3a_1p35: smps3 { 94 vreg_s3a_1p35: smps3 {
147 regulator-min-microvol 95 regulator-min-microvolt = <1352000>;
148 regulator-max-microvol 96 regulator-max-microvolt = <1352000>;
149 }; 97 };
150 98
151 vreg_s5a_2p04: smps5 { 99 vreg_s5a_2p04: smps5 {
152 regulator-min-microvol 100 regulator-min-microvolt = <1904000>;
153 regulator-max-microvol 101 regulator-max-microvolt = <2040000>;
154 }; 102 };
155 103
156 vreg_s7a_1p025: smps7 { 104 vreg_s7a_1p025: smps7 {
157 regulator-min-microvol 105 regulator-min-microvolt = <900000>;
158 regulator-max-microvol 106 regulator-max-microvolt = <1028000>;
159 }; 107 };
160 108
161 vdd_qusb_hs0: 109 vdd_qusb_hs0:
162 vdda_hp_pcie_core: 110 vdda_hp_pcie_core:
163 vdda_mipi_csi0_0p9: 111 vdda_mipi_csi0_0p9:
164 vdda_mipi_csi1_0p9: 112 vdda_mipi_csi1_0p9:
165 vdda_mipi_csi2_0p9: 113 vdda_mipi_csi2_0p9:
166 vdda_mipi_dsi0_pll: 114 vdda_mipi_dsi0_pll:
167 vdda_mipi_dsi1_pll: 115 vdda_mipi_dsi1_pll:
168 vdda_qlink_lv: 116 vdda_qlink_lv:
169 vdda_qlink_lv_ck: 117 vdda_qlink_lv_ck:
170 vdda_qrefs_0p875: 118 vdda_qrefs_0p875:
171 vdda_pcie_core: 119 vdda_pcie_core:
172 vdda_pll_cc_ebi01: 120 vdda_pll_cc_ebi01:
173 vdda_pll_cc_ebi23: 121 vdda_pll_cc_ebi23:
174 vdda_sp_sensor: 122 vdda_sp_sensor:
175 vdda_ufs1_core: 123 vdda_ufs1_core:
176 vdda_ufs2_core: 124 vdda_ufs2_core:
177 vdda_usb1_ss_core: 125 vdda_usb1_ss_core:
178 vdda_usb2_ss_core: 126 vdda_usb2_ss_core:
179 vreg_l1a_0p875: ldo1 { 127 vreg_l1a_0p875: ldo1 {
180 regulator-min-microvol 128 regulator-min-microvolt = <880000>;
181 regulator-max-microvol 129 regulator-max-microvolt = <880000>;
182 regulator-initial-mode 130 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
183 }; 131 };
184 132
185 vddpx_10: 133 vddpx_10:
186 vreg_l2a_1p2: ldo2 { 134 vreg_l2a_1p2: ldo2 {
187 regulator-min-microvol 135 regulator-min-microvolt = <1200000>;
188 regulator-max-microvol 136 regulator-max-microvolt = <1200000>;
189 regulator-initial-mode 137 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
190 regulator-always-on; 138 regulator-always-on;
191 }; 139 };
192 140
193 vreg_l3a_1p0: ldo3 { 141 vreg_l3a_1p0: ldo3 {
194 regulator-min-microvol 142 regulator-min-microvolt = <1000000>;
195 regulator-max-microvol 143 regulator-max-microvolt = <1000000>;
196 regulator-initial-mode 144 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
197 }; 145 };
198 146
199 vdd_wcss_cx: 147 vdd_wcss_cx:
200 vdd_wcss_mx: 148 vdd_wcss_mx:
201 vdda_wcss_pll: 149 vdda_wcss_pll:
202 vreg_l5a_0p8: ldo5 { 150 vreg_l5a_0p8: ldo5 {
203 regulator-min-microvol 151 regulator-min-microvolt = <800000>;
204 regulator-max-microvol 152 regulator-max-microvolt = <800000>;
205 regulator-initial-mode 153 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
206 }; 154 };
207 155
208 vddpx_13: 156 vddpx_13:
209 vreg_l6a_1p8: ldo6 { 157 vreg_l6a_1p8: ldo6 {
210 regulator-min-microvol 158 regulator-min-microvolt = <1856000>;
211 regulator-max-microvol 159 regulator-max-microvolt = <1856000>;
212 regulator-initial-mode 160 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
213 }; 161 };
214 162
215 vreg_l7a_1p8: ldo7 { 163 vreg_l7a_1p8: ldo7 {
216 regulator-min-microvol 164 regulator-min-microvolt = <1800000>;
217 regulator-max-microvol 165 regulator-max-microvolt = <1800000>;
218 regulator-initial-mode 166 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
219 }; 167 };
220 168
221 vreg_l8a_1p2: ldo8 { 169 vreg_l8a_1p2: ldo8 {
222 regulator-min-microvol 170 regulator-min-microvolt = <1200000>;
223 regulator-max-microvol 171 regulator-max-microvolt = <1248000>;
224 regulator-initial-mode 172 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
225 }; 173 };
226 174
227 vreg_l9a_1p8: ldo9 { 175 vreg_l9a_1p8: ldo9 {
228 regulator-min-microvol 176 regulator-min-microvolt = <1704000>;
229 regulator-max-microvol 177 regulator-max-microvolt = <2928000>;
230 regulator-initial-mode 178 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
231 }; 179 };
232 180
233 vreg_l10a_1p8: ldo10 { 181 vreg_l10a_1p8: ldo10 {
234 regulator-min-microvol 182 regulator-min-microvolt = <1704000>;
235 regulator-max-microvol 183 regulator-max-microvolt = <2928000>;
236 regulator-initial-mode 184 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
237 }; 185 };
238 186
239 vreg_l11a_1p0: ldo11 { 187 vreg_l11a_1p0: ldo11 {
240 regulator-min-microvol 188 regulator-min-microvolt = <1000000>;
241 regulator-max-microvol 189 regulator-max-microvolt = <1048000>;
242 regulator-initial-mode 190 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
243 }; 191 };
244 192
245 vdd_qfprom: 193 vdd_qfprom:
246 vdd_qfprom_sp: 194 vdd_qfprom_sp:
247 vdda_apc1_cs_1p8: 195 vdda_apc1_cs_1p8:
248 vdda_gfx_cs_1p8: 196 vdda_gfx_cs_1p8:
249 vdda_qrefs_1p8: 197 vdda_qrefs_1p8:
250 vdda_qusb_hs0_1p8: 198 vdda_qusb_hs0_1p8:
251 vddpx_11: 199 vddpx_11:
252 vreg_l12a_1p8: ldo12 { 200 vreg_l12a_1p8: ldo12 {
253 regulator-min-microvol 201 regulator-min-microvolt = <1800000>;
254 regulator-max-microvol 202 regulator-max-microvolt = <1800000>;
255 regulator-initial-mode 203 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
256 }; 204 };
257 205
258 vddpx_2: 206 vddpx_2:
259 vreg_l13a_2p95: ldo13 { 207 vreg_l13a_2p95: ldo13 {
260 regulator-min-microvol 208 regulator-min-microvolt = <1800000>;
261 regulator-max-microvol 209 regulator-max-microvolt = <2960000>;
262 regulator-initial-mode 210 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
263 }; 211 };
264 212
265 vreg_l14a_1p88: ldo14 { 213 vreg_l14a_1p88: ldo14 {
266 regulator-min-microvol 214 regulator-min-microvolt = <1800000>;
267 regulator-max-microvol 215 regulator-max-microvolt = <1800000>;
268 regulator-initial-mode 216 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
269 }; 217 };
270 218
271 vreg_l15a_1p8: ldo15 { 219 vreg_l15a_1p8: ldo15 {
272 regulator-min-microvol 220 regulator-min-microvolt = <1800000>;
273 regulator-max-microvol 221 regulator-max-microvolt = <1800000>;
274 regulator-initial-mode 222 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
275 }; 223 };
276 224
277 vreg_l16a_2p7: ldo16 { 225 vreg_l16a_2p7: ldo16 {
278 regulator-min-microvol 226 regulator-min-microvolt = <2704000>;
279 regulator-max-microvol 227 regulator-max-microvolt = <2704000>;
280 regulator-initial-mode 228 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
281 }; 229 };
282 230
283 vreg_l17a_1p3: ldo17 { 231 vreg_l17a_1p3: ldo17 {
284 regulator-min-microvol 232 regulator-min-microvolt = <1304000>;
285 regulator-max-microvol 233 regulator-max-microvolt = <1304000>;
286 regulator-initial-mode 234 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
287 }; 235 };
288 236
289 vreg_l18a_2p7: ldo18 { 237 vreg_l18a_2p7: ldo18 {
290 regulator-min-microvol 238 regulator-min-microvolt = <2704000>;
291 regulator-max-microvol 239 regulator-max-microvolt = <2960000>;
292 regulator-initial-mode 240 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
293 }; 241 };
294 242
295 vreg_l19a_3p0: ldo19 { 243 vreg_l19a_3p0: ldo19 {
296 regulator-min-microvol 244 regulator-min-microvolt = <2856000>;
297 regulator-max-microvol 245 regulator-max-microvolt = <3104000>;
298 regulator-initial-mode 246 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
299 }; 247 };
300 248
301 vreg_l20a_2p95: ldo20 { 249 vreg_l20a_2p95: ldo20 {
302 regulator-min-microvol 250 regulator-min-microvolt = <2704000>;
303 regulator-max-microvol 251 regulator-max-microvolt = <2960000>;
304 regulator-initial-mode 252 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
305 }; 253 };
306 254
307 vreg_l21a_2p95: ldo21 { 255 vreg_l21a_2p95: ldo21 {
308 regulator-min-microvol 256 regulator-min-microvolt = <2704000>;
309 regulator-max-microvol 257 regulator-max-microvolt = <2960000>;
310 regulator-initial-mode 258 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
311 }; 259 };
312 260
313 vreg_l22a_2p85: ldo22 { 261 vreg_l22a_2p85: ldo22 {
314 regulator-min-microvol 262 regulator-min-microvolt = <2864000>;
315 regulator-max-microvol 263 regulator-max-microvolt = <3312000>;
316 regulator-initial-mode 264 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
317 }; 265 };
318 266
319 vreg_l23a_3p3: ldo23 { 267 vreg_l23a_3p3: ldo23 {
320 regulator-min-microvol 268 regulator-min-microvolt = <3000000>;
321 regulator-max-microvol 269 regulator-max-microvolt = <3312000>;
322 regulator-initial-mode 270 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
323 }; 271 };
324 272
325 vdda_qusb_hs0_3p1: 273 vdda_qusb_hs0_3p1:
326 vreg_l24a_3p075: ldo24 { 274 vreg_l24a_3p075: ldo24 {
327 regulator-min-microvol 275 regulator-min-microvolt = <3088000>;
328 regulator-max-microvol 276 regulator-max-microvolt = <3088000>;
329 regulator-initial-mode 277 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
330 }; 278 };
331 279
332 vreg_l25a_3p3: ldo25 { 280 vreg_l25a_3p3: ldo25 {
333 regulator-min-microvol 281 regulator-min-microvolt = <3300000>;
334 regulator-max-microvol 282 regulator-max-microvolt = <3312000>;
335 regulator-initial-mode 283 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
336 }; 284 };
337 285
338 vdda_hp_pcie_1p2: 286 vdda_hp_pcie_1p2:
339 vdda_hv_ebi0: 287 vdda_hv_ebi0:
340 vdda_hv_ebi1: 288 vdda_hv_ebi1:
341 vdda_hv_ebi2: 289 vdda_hv_ebi2:
342 vdda_hv_ebi3: 290 vdda_hv_ebi3:
343 vdda_mipi_csi_1p25: 291 vdda_mipi_csi_1p25:
344 vdda_mipi_dsi0_1p2: 292 vdda_mipi_dsi0_1p2:
345 vdda_mipi_dsi1_1p2: 293 vdda_mipi_dsi1_1p2:
346 vdda_pcie_1p2: 294 vdda_pcie_1p2:
347 vdda_ufs1_1p2: 295 vdda_ufs1_1p2:
348 vdda_ufs2_1p2: 296 vdda_ufs2_1p2:
349 vdda_usb1_ss_1p2: 297 vdda_usb1_ss_1p2:
350 vdda_usb2_ss_1p2: 298 vdda_usb2_ss_1p2:
351 vreg_l26a_1p2: ldo26 { 299 vreg_l26a_1p2: ldo26 {
352 regulator-min-microvol 300 regulator-min-microvolt = <1200000>;
353 regulator-max-microvol 301 regulator-max-microvolt = <1200000>;
354 regulator-initial-mode 302 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
355 }; 303 };
356 304
357 vreg_l28a_3p0: ldo28 { 305 vreg_l28a_3p0: ldo28 {
358 regulator-min-microvol 306 regulator-min-microvolt = <2856000>;
359 regulator-max-microvol 307 regulator-max-microvolt = <3008000>;
360 regulator-initial-mode 308 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
361 }; 309 };
362 310
363 vreg_lvs1a_1p8: lvs1 { 311 vreg_lvs1a_1p8: lvs1 {
364 regulator-min-microvol 312 regulator-min-microvolt = <1800000>;
365 regulator-max-microvol 313 regulator-max-microvolt = <1800000>;
366 }; 314 };
367 315
368 vreg_lvs2a_1p8: lvs2 { 316 vreg_lvs2a_1p8: lvs2 {
369 regulator-min-microvol 317 regulator-min-microvolt = <1800000>;
370 regulator-max-microvol 318 regulator-max-microvolt = <1800000>;
371 }; 319 };
372 }; 320 };
373 321
374 regulators-1 { !! 322 pmi8998-rpmh-regulators {
375 compatible = "qcom,pmi8998-rpm 323 compatible = "qcom,pmi8998-rpmh-regulators";
376 qcom,pmic-id = "b"; 324 qcom,pmic-id = "b";
377 325
378 vdd-bob-supply = <&vph_pwr>; 326 vdd-bob-supply = <&vph_pwr>;
379 327
380 vreg_bob: bob { 328 vreg_bob: bob {
381 regulator-min-microvol 329 regulator-min-microvolt = <3312000>;
382 regulator-max-microvol 330 regulator-max-microvolt = <3600000>;
383 regulator-initial-mode 331 regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
384 regulator-allow-bypass 332 regulator-allow-bypass;
385 }; 333 };
386 }; 334 };
387 335
388 regulators-2 { !! 336 pm8005-rpmh-regulators {
389 compatible = "qcom,pm8005-rpmh 337 compatible = "qcom,pm8005-rpmh-regulators";
390 qcom,pmic-id = "c"; 338 qcom,pmic-id = "c";
391 339
392 vdd-s1-supply = <&vph_pwr>; 340 vdd-s1-supply = <&vph_pwr>;
393 vdd-s2-supply = <&vph_pwr>; 341 vdd-s2-supply = <&vph_pwr>;
394 vdd-s3-supply = <&vph_pwr>; 342 vdd-s3-supply = <&vph_pwr>;
395 vdd-s4-supply = <&vph_pwr>; 343 vdd-s4-supply = <&vph_pwr>;
396 344
397 vreg_s3c_0p6: smps3 { 345 vreg_s3c_0p6: smps3 {
398 regulator-min-microvol 346 regulator-min-microvolt = <600000>;
399 regulator-max-microvol 347 regulator-max-microvolt = <600000>;
400 }; 348 };
401 }; 349 };
402 }; 350 };
403 351
404 &cdsp_pas { 352 &cdsp_pas {
405 status = "okay"; 353 status = "okay";
406 firmware-name = "qcom/sdm845/cdsp.mbn" !! 354 firmware-name = "qcom/sdm845/cdsp.mdt";
407 }; <<
408 <<
409 &gcc { <<
410 protected-clocks = <GCC_QSPI_CORE_CLK> <<
411 <GCC_QSPI_CORE_CLK_ <<
412 <GCC_QSPI_CNOC_PERI <<
413 <GCC_LPASS_Q6_AXI_C <<
414 <GCC_LPASS_SWAY_CLK <<
415 }; <<
416 <<
417 &gmu { <<
418 status = "okay"; <<
419 }; <<
420 <<
421 &gpu { <<
422 status = "okay"; <<
423 <<
424 zap-shader { <<
425 memory-region = <&gpu_mem>; <<
426 firmware-name = "qcom/sdm845/a <<
427 }; <<
428 }; <<
429 <<
430 &i2c10 { <<
431 status = "okay"; <<
432 clock-frequency = <400000>; <<
433 }; <<
434 <<
435 &ipa { <<
436 qcom,gsi-loader = "self"; <<
437 memory-region = <&ipa_fw_mem>; <<
438 status = "okay"; <<
439 }; 355 };
440 356
441 &mdss { !! 357 &dsi0 {
442 status = "okay"; <<
443 }; <<
444 <<
445 &mdss_dsi0 { <<
446 status = "okay"; 358 status = "okay";
447 vdda-supply = <&vdda_mipi_dsi0_1p2>; 359 vdda-supply = <&vdda_mipi_dsi0_1p2>;
448 360
449 qcom,dual-dsi-mode; 361 qcom,dual-dsi-mode;
450 qcom,master-dsi; 362 qcom,master-dsi;
451 363
>> 364 #address-cells = <1>;
>> 365 #size-cells = <0>;
>> 366
452 ports { 367 ports {
453 port@1 { 368 port@1 {
454 endpoint { 369 endpoint {
455 remote-endpoin 370 remote-endpoint = <&truly_in_0>;
456 data-lanes = < 371 data-lanes = <0 1 2 3>;
457 }; 372 };
458 }; 373 };
459 }; 374 };
460 375
461 panel@0 { 376 panel@0 {
462 compatible = "truly,nt35597-2K 377 compatible = "truly,nt35597-2K-display";
463 reg = <0>; 378 reg = <0>;
464 vdda-supply = <&vreg_l14a_1p88 379 vdda-supply = <&vreg_l14a_1p88>;
465 380
466 reset-gpios = <&tlmm 6 GPIO_AC 381 reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
467 mode-gpios = <&tlmm 52 GPIO_AC 382 mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
468 383
469 ports { 384 ports {
470 #address-cells = <1>; 385 #address-cells = <1>;
471 #size-cells = <0>; 386 #size-cells = <0>;
472 387
473 port@0 { 388 port@0 {
474 reg = <0>; 389 reg = <0>;
475 truly_in_0: en 390 truly_in_0: endpoint {
476 remote !! 391 remote-endpoint = <&dsi0_out>;
477 }; 392 };
478 }; 393 };
479 394
480 port@1 { 395 port@1 {
481 reg = <1>; 396 reg = <1>;
482 truly_in_1: en 397 truly_in_1: endpoint {
483 remote !! 398 remote-endpoint = <&dsi1_out>;
484 }; 399 };
485 }; 400 };
486 }; 401 };
487 }; 402 };
488 }; 403 };
489 404
490 &mdss_dsi0_phy { !! 405 &dsi0_phy {
491 status = "okay"; 406 status = "okay";
492 vdds-supply = <&vdda_mipi_dsi0_pll>; 407 vdds-supply = <&vdda_mipi_dsi0_pll>;
493 }; 408 };
494 409
495 &mdss_dsi1 { !! 410 &dsi1 {
496 status = "okay"; 411 status = "okay";
497 vdda-supply = <&vdda_mipi_dsi1_1p2>; 412 vdda-supply = <&vdda_mipi_dsi1_1p2>;
498 413
499 qcom,dual-dsi-mode; 414 qcom,dual-dsi-mode;
500 415
501 /* DSI1 is slave, so use DSI0 clocks * 416 /* DSI1 is slave, so use DSI0 clocks */
502 assigned-clock-parents = <&mdss_dsi0_p !! 417 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
503 418
504 ports { 419 ports {
505 port@1 { 420 port@1 {
506 endpoint { 421 endpoint {
507 remote-endpoin 422 remote-endpoint = <&truly_in_1>;
508 data-lanes = < 423 data-lanes = <0 1 2 3>;
509 }; 424 };
510 }; 425 };
511 }; 426 };
512 }; 427 };
513 428
514 &mdss_dsi1_phy { !! 429 &dsi1_phy {
515 status = "okay"; 430 status = "okay";
516 vdds-supply = <&vdda_mipi_dsi1_pll>; 431 vdds-supply = <&vdda_mipi_dsi1_pll>;
517 }; 432 };
518 433
519 &mss_pil { !! 434 &gcc {
520 status = "okay"; !! 435 protected-clocks = <GCC_QSPI_CORE_CLK>,
521 firmware-name = "qcom/sdm845/mba.mbn", !! 436 <GCC_QSPI_CORE_CLK_SRC>,
>> 437 <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>> 438 <GCC_LPASS_Q6_AXI_CLK>,
>> 439 <GCC_LPASS_SWAY_CLK>;
522 }; 440 };
523 441
524 &pcie0 { !! 442 &gpu {
525 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LO !! 443 zap-shader {
526 !! 444 memory-region = <&gpu_mem>;
527 pinctrl-0 = <&pcie0_default_state>; !! 445 firmware-name = "qcom/sdm845/a630_zap.mbn";
528 pinctrl-names = "default"; !! 446 };
529 <<
530 status = "okay"; <<
531 }; 447 };
532 448
533 &pcie0_phy { !! 449 &i2c10 {
534 vdda-phy-supply = <&vreg_l1a_0p875>; <<
535 vdda-pll-supply = <&vreg_l26a_1p2>; <<
536 <<
537 status = "okay"; 450 status = "okay";
>> 451 clock-frequency = <400000>;
538 }; 452 };
539 453
540 &pcie1 { !! 454 &ipa {
541 perst-gpios = <&tlmm 102 GPIO_ACTIVE_L <<
542 <<
543 pinctrl-names = "default"; <<
544 pinctrl-0 = <&pcie1_default_state>; <<
545 <<
546 status = "okay"; 455 status = "okay";
>> 456 memory-region = <&ipa_fw_mem>;
547 }; 457 };
548 458
549 &pcie1_phy { !! 459 &mdss {
550 status = "okay"; 460 status = "okay";
551 <<
552 vdda-phy-supply = <&vreg_l1a_0p875>; <<
553 vdda-pll-supply = <&vreg_l26a_1p2>; <<
554 }; <<
555 <<
556 &pm8998_adc { <<
557 channel@4c { <<
558 reg = <ADC5_XO_THERM_100K_PU>; <<
559 label = "xo_therm"; <<
560 qcom,ratiometric; <<
561 qcom,hw-settle-time = <200>; <<
562 }; <<
563 <<
564 channel@4d { <<
565 reg = <ADC5_AMUX_THM1_100K_PU> <<
566 label = "msm_therm"; <<
567 qcom,ratiometric; <<
568 qcom,hw-settle-time = <200>; <<
569 }; <<
570 <<
571 channel@4f { <<
572 reg = <ADC5_AMUX_THM3_100K_PU> <<
573 label = "pa_therm1"; <<
574 qcom,ratiometric; <<
575 qcom,hw-settle-time = <200>; <<
576 }; <<
577 <<
578 channel@51 { <<
579 reg = <ADC5_AMUX_THM5_100K_PU> <<
580 label = "quiet_therm"; <<
581 qcom,ratiometric; <<
582 qcom,hw-settle-time = <200>; <<
583 }; <<
584 <<
585 channel@83 { <<
586 reg = <ADC5_VPH_PWR>; <<
587 label = "vph_pwr"; <<
588 qcom,ratiometric; <<
589 qcom,hw-settle-time = <200>; <<
590 }; <<
591 <<
592 channel@85 { <<
593 reg = <ADC5_VCOIN>; <<
594 label = "vcoin"; <<
595 qcom,ratiometric; <<
596 qcom,hw-settle-time = <200>; <<
597 }; <<
598 }; 461 };
599 462
600 &pm8998_adc_tm { !! 463 &mdss_mdp {
601 status = "okay"; 464 status = "okay";
602 <<
603 xo-thermistor@1 { <<
604 reg = <1>; <<
605 io-channels = <&pm8998_adc ADC <<
606 qcom,ratiometric; <<
607 qcom,hw-settle-time-us = <200> <<
608 }; <<
609 <<
610 msm-thermistor@2 { <<
611 reg = <2>; <<
612 io-channels = <&pm8998_adc ADC <<
613 qcom,ratiometric; <<
614 qcom,hw-settle-time-us = <200> <<
615 }; <<
616 <<
617 pa-thermistor@3 { <<
618 reg = <3>; <<
619 io-channels = <&pm8998_adc ADC <<
620 qcom,ratiometric; <<
621 qcom,hw-settle-time-us = <200> <<
622 }; <<
623 <<
624 quiet-thermistor@4 { <<
625 reg = <4>; <<
626 io-channels = <&pm8998_adc ADC <<
627 qcom,ratiometric; <<
628 qcom,hw-settle-time-us = <200> <<
629 }; <<
630 }; 465 };
631 466
632 &pm8998_resin { !! 467 &mss_pil {
633 linux,code = <KEY_VOLUMEDOWN>; <<
634 status = "okay"; 468 status = "okay";
>> 469 firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
635 }; 470 };
636 471
637 &qupv3_id_1 { 472 &qupv3_id_1 {
638 status = "okay"; 473 status = "okay";
639 }; 474 };
640 475
641 &sdhc_2 { 476 &sdhc_2 {
642 status = "okay"; 477 status = "okay";
643 478
644 pinctrl-names = "default"; 479 pinctrl-names = "default";
645 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2 480 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;
646 481
647 vmmc-supply = <&vreg_l21a_2p95>; 482 vmmc-supply = <&vreg_l21a_2p95>;
648 vqmmc-supply = <&vddpx_2>; 483 vqmmc-supply = <&vddpx_2>;
649 484
650 cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW> 485 cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
651 }; 486 };
652 487
653 &tlmm { <<
654 pcie0_default_state: pcie0-default-sta <<
655 clkreq-pins { <<
656 pins = "gpio36"; <<
657 function = "pci_e0"; <<
658 bias-pull-up; <<
659 }; <<
660 <<
661 perst-n-pins { <<
662 pins = "gpio35"; <<
663 function = "gpio"; <<
664 drive-strength = <2>; <<
665 bias-pull-down; <<
666 }; <<
667 <<
668 wake-n-pins { <<
669 pins = "gpio37"; <<
670 function = "gpio"; <<
671 drive-strength = <2>; <<
672 bias-pull-up; <<
673 }; <<
674 }; <<
675 <<
676 pcie1_default_state: pcie1-default-sta <<
677 clkreq-pins { <<
678 pins = "gpio103"; <<
679 function = "pci_e1"; <<
680 bias-pull-up; <<
681 }; <<
682 <<
683 perst-n-pins { <<
684 pins = "gpio102"; <<
685 function = "gpio"; <<
686 drive-strength = <16>; <<
687 bias-pull-down; <<
688 }; <<
689 <<
690 wake-n-pins { <<
691 pins = "gpio104"; <<
692 function = "gpio"; <<
693 drive-strength = <2>; <<
694 bias-pull-up; <<
695 }; <<
696 }; <<
697 }; <<
698 <<
699 &uart9 { 488 &uart9 {
700 status = "okay"; 489 status = "okay";
701 }; 490 };
702 491
703 &ufs_mem_hc { 492 &ufs_mem_hc {
704 status = "okay"; 493 status = "okay";
705 494
706 reset-gpios = <&tlmm 150 GPIO_ACTIVE_L 495 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
707 496
708 vcc-supply = <&vreg_l20a_2p95>; 497 vcc-supply = <&vreg_l20a_2p95>;
709 vcc-max-microamp = <600000>; 498 vcc-max-microamp = <600000>;
710 }; 499 };
711 500
712 &ufs_mem_phy { 501 &ufs_mem_phy {
713 status = "okay"; 502 status = "okay";
714 503
715 vdda-phy-supply = <&vdda_ufs1_core>; 504 vdda-phy-supply = <&vdda_ufs1_core>;
716 vdda-pll-supply = <&vdda_ufs1_1p2>; 505 vdda-pll-supply = <&vdda_ufs1_1p2>;
717 }; 506 };
718 507
719 &usb_1 { 508 &usb_1 {
720 status = "okay"; 509 status = "okay";
721 }; 510 };
722 511
723 &usb_1_dwc3 { 512 &usb_1_dwc3 {
724 /* Until we have Type C hooked up we'l 513 /* Until we have Type C hooked up we'll force this as peripheral. */
725 dr_mode = "peripheral"; 514 dr_mode = "peripheral";
726 }; 515 };
727 516
728 &usb_1_hsphy { 517 &usb_1_hsphy {
729 status = "okay"; 518 status = "okay";
730 519
731 vdd-supply = <&vdda_usb1_ss_core>; 520 vdd-supply = <&vdda_usb1_ss_core>;
732 vdda-pll-supply = <&vdda_qusb_hs0_1p8> 521 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
733 vdda-phy-dpdm-supply = <&vdda_qusb_hs0 522 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
734 523
735 qcom,imp-res-offset-value = <8>; 524 qcom,imp-res-offset-value = <8>;
736 qcom,hstx-trim-value = <QUSB2_V2_HSTX_ 525 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
737 qcom,preemphasis-level = <QUSB2_V2_PRE 526 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
738 qcom,preemphasis-width = <QUSB2_V2_PRE 527 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
739 }; 528 };
740 529
741 &usb_1_qmpphy { 530 &usb_1_qmpphy {
742 status = "okay"; 531 status = "okay";
743 532
744 vdda-phy-supply = <&vdda_usb1_ss_1p2>; 533 vdda-phy-supply = <&vdda_usb1_ss_1p2>;
745 vdda-pll-supply = <&vdda_usb1_ss_core> 534 vdda-pll-supply = <&vdda_usb1_ss_core>;
746 }; 535 };
747 536
748 &usb_2 { 537 &usb_2 {
749 status = "okay"; 538 status = "okay";
750 }; 539 };
751 540
752 &usb_2_dwc3 { 541 &usb_2_dwc3 {
753 /* 542 /*
754 * Though the USB block on SDM845 can 543 * Though the USB block on SDM845 can support host, there's no vbus
755 * signal for this port on MTP. Thus 544 * signal for this port on MTP. Thus (unless you have a non-compliant
756 * hub that works without vbus) the on 545 * hub that works without vbus) the only sensible thing is to force
757 * peripheral mode. 546 * peripheral mode.
758 */ 547 */
759 dr_mode = "peripheral"; 548 dr_mode = "peripheral";
760 }; 549 };
761 550
762 &usb_2_hsphy { 551 &usb_2_hsphy {
763 status = "okay"; 552 status = "okay";
764 553
765 vdd-supply = <&vdda_usb2_ss_core>; 554 vdd-supply = <&vdda_usb2_ss_core>;
766 vdda-pll-supply = <&vdda_qusb_hs0_1p8> 555 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
767 vdda-phy-dpdm-supply = <&vdda_qusb_hs0 556 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
768 557
769 qcom,imp-res-offset-value = <8>; 558 qcom,imp-res-offset-value = <8>;
770 qcom,hstx-trim-value = <QUSB2_V2_HSTX_ 559 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
771 }; 560 };
772 561
773 &usb_2_qmpphy { 562 &usb_2_qmpphy {
774 status = "okay"; 563 status = "okay";
775 564
776 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 565 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
777 vdda-pll-supply = <&vdda_usb2_ss_core> 566 vdda-pll-supply = <&vdda_usb2_ss_core>;
778 }; 567 };
779 568
780 &venus { <<
781 status = "okay"; <<
782 }; <<
783 <<
784 &wifi { 569 &wifi {
785 status = "okay"; 570 status = "okay";
786 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8> 571 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
787 vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 572 vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
788 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 573 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
789 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 574 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
790 575
791 qcom,snoc-host-cap-8bit-quirk; 576 qcom,snoc-host-cap-8bit-quirk;
792 qcom,ath10k-calibration-variant = "Qua <<
793 }; 577 };
794 578
795 /* PINCTRL - additions to nodes defined in sdm 579 /* PINCTRL - additions to nodes defined in sdm845.dtsi */
796 580
797 &qup_i2c10_default { 581 &qup_i2c10_default {
798 drive-strength = <2>; !! 582 pinconf {
799 bias-disable; !! 583 pins = "gpio55", "gpio56";
>> 584 drive-strength = <2>;
>> 585 bias-disable;
>> 586 };
800 }; 587 };
801 588
802 &qup_uart9_rx { !! 589 &qup_uart9_default {
803 drive-strength = <2>; !! 590 pinconf-tx {
804 bias-pull-up; !! 591 pins = "gpio4";
805 }; !! 592 drive-strength = <2>;
>> 593 bias-disable;
>> 594 };
806 595
807 &qup_uart9_tx { !! 596 pinconf-rx {
808 drive-strength = <2>; !! 597 pins = "gpio5";
809 bias-disable; !! 598 drive-strength = <2>;
>> 599 bias-pull-up;
>> 600 };
810 }; 601 };
811 602
812 &tlmm { 603 &tlmm {
813 gpio-reserved-ranges = <0 4>, <81 4>; 604 gpio-reserved-ranges = <0 4>, <81 4>;
814 605
815 sdc2_clk: sdc2-clk-state { !! 606 sdc2_clk: sdc2-clk {
816 pins = "sdc2_clk"; !! 607 pinconf {
817 bias-disable; !! 608 pins = "sdc2_clk";
818 !! 609 bias-disable;
819 /* !! 610
820 * It seems that mmc_test repo !! 611 /*
821 * strength is not 16 on clk, !! 612 * It seems that mmc_test reports errors if drive
822 */ !! 613 * strength is not 16 on clk, cmd, and data pins.
823 drive-strength = <16>; !! 614 */
>> 615 drive-strength = <16>;
>> 616 };
824 }; 617 };
825 618
826 sdc2_cmd: sdc2-cmd-state { !! 619 sdc2_cmd: sdc2-cmd {
827 pins = "sdc2_cmd"; !! 620 pinconf {
828 bias-pull-up; !! 621 pins = "sdc2_cmd";
829 drive-strength = <16>; !! 622 bias-pull-up;
>> 623 drive-strength = <16>;
>> 624 };
830 }; 625 };
831 626
832 sdc2_data: sdc2-data-state { !! 627 sdc2_data: sdc2-data {
833 pins = "sdc2_data"; !! 628 pinconf {
834 bias-pull-up; !! 629 pins = "sdc2_data";
835 drive-strength = <16>; !! 630 bias-pull-up;
>> 631 drive-strength = <16>;
>> 632 };
836 }; 633 };
837 634
838 sd_card_det_n: sd-card-det-n-state { !! 635 sd_card_det_n: sd-card-det-n {
839 pins = "gpio126"; !! 636 pinmux {
840 function = "gpio"; !! 637 pins = "gpio126";
841 bias-pull-up; !! 638 function = "gpio";
>> 639 };
>> 640
>> 641 pinconf {
>> 642 pins = "gpio126";
>> 643 bias-pull-up;
>> 644 };
842 }; 645 };
843 }; 646 };
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