1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 MTP board device tree source 3 * SDM845 MTP board device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include <dt-bindings/regulator/qcom,rpmh-regu 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include "sdm845.dtsi" 11 #include "sdm845.dtsi"
12 #include "pm8998.dtsi" <<
13 #include "pmi8998.dtsi" <<
14 12
15 / { 13 / {
16 model = "Qualcomm Technologies, Inc. S 14 model = "Qualcomm Technologies, Inc. SDM845 MTP";
17 compatible = "qcom,sdm845-mtp", "qcom, 15 compatible = "qcom,sdm845-mtp", "qcom,sdm845";
18 chassis-type = "handset"; <<
19 16
20 aliases { 17 aliases {
21 serial0 = &uart9; 18 serial0 = &uart9;
22 }; 19 };
23 20
24 chosen { 21 chosen {
25 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
26 }; 23 };
27 24
28 vph_pwr: vph-pwr-regulator { 25 vph_pwr: vph-pwr-regulator {
29 compatible = "regulator-fixed" 26 compatible = "regulator-fixed";
30 regulator-name = "vph_pwr"; 27 regulator-name = "vph_pwr";
31 regulator-min-microvolt = <370 28 regulator-min-microvolt = <3700000>;
32 regulator-max-microvolt = <370 29 regulator-max-microvolt = <3700000>;
33 }; 30 };
34 31
35 /* 32 /*
36 * Apparently RPMh does not provide su 33 * Apparently RPMh does not provide support for PM8998 S4 because it
37 * is always-on; model it as a fixed r 34 * is always-on; model it as a fixed regulator.
38 */ 35 */
39 vreg_s4a_1p8: pm8998-smps4 { 36 vreg_s4a_1p8: pm8998-smps4 {
40 compatible = "regulator-fixed" 37 compatible = "regulator-fixed";
41 regulator-name = "vreg_s4a_1p8 38 regulator-name = "vreg_s4a_1p8";
42 39
43 regulator-min-microvolt = <180 40 regulator-min-microvolt = <1800000>;
44 regulator-max-microvolt = <180 41 regulator-max-microvolt = <1800000>;
45 42
46 regulator-always-on; 43 regulator-always-on;
47 regulator-boot-on; 44 regulator-boot-on;
48 45
49 vin-supply = <&vph_pwr>; 46 vin-supply = <&vph_pwr>;
50 }; 47 };
51 <<
52 thermal-zones { <<
53 xo_thermal: xo-thermal { <<
54 thermal-sensors = <&pm <<
55 <<
56 trips { <<
57 trip-point { <<
58 temper <<
59 hyster <<
60 type = <<
61 }; <<
62 }; <<
63 }; <<
64 <<
65 msm_thermal: msm-thermal { <<
66 thermal-sensors = <&pm <<
67 <<
68 trips { <<
69 trip-point { <<
70 temper <<
71 hyster <<
72 type = <<
73 }; <<
74 }; <<
75 }; <<
76 <<
77 pa_thermal: pa-thermal { <<
78 thermal-sensors = <&pm <<
79 <<
80 trips { <<
81 trip-point { <<
82 temper <<
83 hyster <<
84 type = <<
85 }; <<
86 }; <<
87 }; <<
88 <<
89 quiet_thermal: quiet-thermal { <<
90 thermal-sensors = <&pm <<
91 <<
92 trips { <<
93 trip-point { <<
94 temper <<
95 hyster <<
96 type = <<
97 }; <<
98 }; <<
99 }; <<
100 }; <<
101 }; 48 };
102 49
103 &adsp_pas { 50 &adsp_pas {
104 status = "okay"; 51 status = "okay";
105 firmware-name = "qcom/sdm845/adsp.mbn" !! 52 firmware-name = "qcom/sdm845/adsp.mdt";
106 }; 53 };
107 54
108 &apps_rsc { 55 &apps_rsc {
109 regulators-0 { !! 56 pm8998-rpmh-regulators {
110 compatible = "qcom,pm8998-rpmh 57 compatible = "qcom,pm8998-rpmh-regulators";
111 qcom,pmic-id = "a"; 58 qcom,pmic-id = "a";
112 59
113 vdd-s1-supply = <&vph_pwr>; 60 vdd-s1-supply = <&vph_pwr>;
114 vdd-s2-supply = <&vph_pwr>; 61 vdd-s2-supply = <&vph_pwr>;
115 vdd-s3-supply = <&vph_pwr>; 62 vdd-s3-supply = <&vph_pwr>;
116 vdd-s4-supply = <&vph_pwr>; 63 vdd-s4-supply = <&vph_pwr>;
117 vdd-s5-supply = <&vph_pwr>; 64 vdd-s5-supply = <&vph_pwr>;
118 vdd-s6-supply = <&vph_pwr>; 65 vdd-s6-supply = <&vph_pwr>;
119 vdd-s7-supply = <&vph_pwr>; 66 vdd-s7-supply = <&vph_pwr>;
120 vdd-s8-supply = <&vph_pwr>; 67 vdd-s8-supply = <&vph_pwr>;
121 vdd-s9-supply = <&vph_pwr>; 68 vdd-s9-supply = <&vph_pwr>;
122 vdd-s10-supply = <&vph_pwr>; 69 vdd-s10-supply = <&vph_pwr>;
123 vdd-s11-supply = <&vph_pwr>; 70 vdd-s11-supply = <&vph_pwr>;
124 vdd-s12-supply = <&vph_pwr>; 71 vdd-s12-supply = <&vph_pwr>;
125 vdd-s13-supply = <&vph_pwr>; 72 vdd-s13-supply = <&vph_pwr>;
126 vdd-l1-l27-supply = <&vreg_s7a 73 vdd-l1-l27-supply = <&vreg_s7a_1p025>;
127 vdd-l2-l8-l17-supply = <&vreg_ 74 vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
128 vdd-l3-l11-supply = <&vreg_s7a 75 vdd-l3-l11-supply = <&vreg_s7a_1p025>;
129 vdd-l4-l5-supply = <&vreg_s7a_ 76 vdd-l4-l5-supply = <&vreg_s7a_1p025>;
130 vdd-l6-supply = <&vph_pwr>; 77 vdd-l6-supply = <&vph_pwr>;
131 vdd-l7-l12-l14-l15-supply = <& 78 vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
132 vdd-l9-supply = <&vreg_bob>; 79 vdd-l9-supply = <&vreg_bob>;
133 vdd-l10-l23-l25-supply = <&vre 80 vdd-l10-l23-l25-supply = <&vreg_bob>;
134 vdd-l13-l19-l21-supply = <&vre 81 vdd-l13-l19-l21-supply = <&vreg_bob>;
135 vdd-l16-l28-supply = <&vreg_bo 82 vdd-l16-l28-supply = <&vreg_bob>;
136 vdd-l18-l22-supply = <&vreg_bo 83 vdd-l18-l22-supply = <&vreg_bob>;
137 vdd-l20-l24-supply = <&vreg_bo 84 vdd-l20-l24-supply = <&vreg_bob>;
138 vdd-l26-supply = <&vreg_s3a_1p 85 vdd-l26-supply = <&vreg_s3a_1p35>;
139 vin-lvs-1-2-supply = <&vreg_s4 86 vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
140 87
141 vreg_s2a_1p125: smps2 { 88 vreg_s2a_1p125: smps2 {
142 regulator-min-microvol 89 regulator-min-microvolt = <1100000>;
143 regulator-max-microvol 90 regulator-max-microvolt = <1100000>;
144 }; 91 };
145 92
146 vreg_s3a_1p35: smps3 { 93 vreg_s3a_1p35: smps3 {
147 regulator-min-microvol 94 regulator-min-microvolt = <1352000>;
148 regulator-max-microvol 95 regulator-max-microvolt = <1352000>;
149 }; 96 };
150 97
151 vreg_s5a_2p04: smps5 { 98 vreg_s5a_2p04: smps5 {
152 regulator-min-microvol 99 regulator-min-microvolt = <1904000>;
153 regulator-max-microvol 100 regulator-max-microvolt = <2040000>;
154 }; 101 };
155 102
156 vreg_s7a_1p025: smps7 { 103 vreg_s7a_1p025: smps7 {
157 regulator-min-microvol 104 regulator-min-microvolt = <900000>;
158 regulator-max-microvol 105 regulator-max-microvolt = <1028000>;
159 }; 106 };
160 107
161 vdd_qusb_hs0: 108 vdd_qusb_hs0:
162 vdda_hp_pcie_core: 109 vdda_hp_pcie_core:
163 vdda_mipi_csi0_0p9: 110 vdda_mipi_csi0_0p9:
164 vdda_mipi_csi1_0p9: 111 vdda_mipi_csi1_0p9:
165 vdda_mipi_csi2_0p9: 112 vdda_mipi_csi2_0p9:
166 vdda_mipi_dsi0_pll: 113 vdda_mipi_dsi0_pll:
167 vdda_mipi_dsi1_pll: 114 vdda_mipi_dsi1_pll:
168 vdda_qlink_lv: 115 vdda_qlink_lv:
169 vdda_qlink_lv_ck: 116 vdda_qlink_lv_ck:
170 vdda_qrefs_0p875: 117 vdda_qrefs_0p875:
171 vdda_pcie_core: 118 vdda_pcie_core:
172 vdda_pll_cc_ebi01: 119 vdda_pll_cc_ebi01:
173 vdda_pll_cc_ebi23: 120 vdda_pll_cc_ebi23:
174 vdda_sp_sensor: 121 vdda_sp_sensor:
175 vdda_ufs1_core: 122 vdda_ufs1_core:
176 vdda_ufs2_core: 123 vdda_ufs2_core:
177 vdda_usb1_ss_core: 124 vdda_usb1_ss_core:
178 vdda_usb2_ss_core: 125 vdda_usb2_ss_core:
179 vreg_l1a_0p875: ldo1 { 126 vreg_l1a_0p875: ldo1 {
180 regulator-min-microvol 127 regulator-min-microvolt = <880000>;
181 regulator-max-microvol 128 regulator-max-microvolt = <880000>;
182 regulator-initial-mode 129 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
183 }; 130 };
184 131
185 vddpx_10: 132 vddpx_10:
186 vreg_l2a_1p2: ldo2 { 133 vreg_l2a_1p2: ldo2 {
187 regulator-min-microvol 134 regulator-min-microvolt = <1200000>;
188 regulator-max-microvol 135 regulator-max-microvolt = <1200000>;
189 regulator-initial-mode 136 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
190 regulator-always-on; 137 regulator-always-on;
191 }; 138 };
192 139
193 vreg_l3a_1p0: ldo3 { 140 vreg_l3a_1p0: ldo3 {
194 regulator-min-microvol 141 regulator-min-microvolt = <1000000>;
195 regulator-max-microvol 142 regulator-max-microvolt = <1000000>;
196 regulator-initial-mode 143 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
197 }; 144 };
198 145
199 vdd_wcss_cx: 146 vdd_wcss_cx:
200 vdd_wcss_mx: 147 vdd_wcss_mx:
201 vdda_wcss_pll: 148 vdda_wcss_pll:
202 vreg_l5a_0p8: ldo5 { 149 vreg_l5a_0p8: ldo5 {
203 regulator-min-microvol 150 regulator-min-microvolt = <800000>;
204 regulator-max-microvol 151 regulator-max-microvolt = <800000>;
205 regulator-initial-mode 152 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
206 }; 153 };
207 154
208 vddpx_13: 155 vddpx_13:
209 vreg_l6a_1p8: ldo6 { 156 vreg_l6a_1p8: ldo6 {
210 regulator-min-microvol 157 regulator-min-microvolt = <1856000>;
211 regulator-max-microvol 158 regulator-max-microvolt = <1856000>;
212 regulator-initial-mode 159 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
213 }; 160 };
214 161
215 vreg_l7a_1p8: ldo7 { 162 vreg_l7a_1p8: ldo7 {
216 regulator-min-microvol 163 regulator-min-microvolt = <1800000>;
217 regulator-max-microvol 164 regulator-max-microvolt = <1800000>;
218 regulator-initial-mode 165 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
219 }; 166 };
220 167
221 vreg_l8a_1p2: ldo8 { 168 vreg_l8a_1p2: ldo8 {
222 regulator-min-microvol 169 regulator-min-microvolt = <1200000>;
223 regulator-max-microvol 170 regulator-max-microvolt = <1248000>;
224 regulator-initial-mode 171 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
225 }; 172 };
226 173
227 vreg_l9a_1p8: ldo9 { 174 vreg_l9a_1p8: ldo9 {
228 regulator-min-microvol 175 regulator-min-microvolt = <1704000>;
229 regulator-max-microvol 176 regulator-max-microvolt = <2928000>;
230 regulator-initial-mode 177 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
231 }; 178 };
232 179
233 vreg_l10a_1p8: ldo10 { 180 vreg_l10a_1p8: ldo10 {
234 regulator-min-microvol 181 regulator-min-microvolt = <1704000>;
235 regulator-max-microvol 182 regulator-max-microvolt = <2928000>;
236 regulator-initial-mode 183 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
237 }; 184 };
238 185
239 vreg_l11a_1p0: ldo11 { 186 vreg_l11a_1p0: ldo11 {
240 regulator-min-microvol 187 regulator-min-microvolt = <1000000>;
241 regulator-max-microvol 188 regulator-max-microvolt = <1048000>;
242 regulator-initial-mode 189 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
243 }; 190 };
244 191
245 vdd_qfprom: 192 vdd_qfprom:
246 vdd_qfprom_sp: 193 vdd_qfprom_sp:
247 vdda_apc1_cs_1p8: 194 vdda_apc1_cs_1p8:
248 vdda_gfx_cs_1p8: 195 vdda_gfx_cs_1p8:
249 vdda_qrefs_1p8: 196 vdda_qrefs_1p8:
250 vdda_qusb_hs0_1p8: 197 vdda_qusb_hs0_1p8:
251 vddpx_11: 198 vddpx_11:
252 vreg_l12a_1p8: ldo12 { 199 vreg_l12a_1p8: ldo12 {
253 regulator-min-microvol 200 regulator-min-microvolt = <1800000>;
254 regulator-max-microvol 201 regulator-max-microvolt = <1800000>;
255 regulator-initial-mode 202 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
256 }; 203 };
257 204
258 vddpx_2: 205 vddpx_2:
259 vreg_l13a_2p95: ldo13 { 206 vreg_l13a_2p95: ldo13 {
260 regulator-min-microvol 207 regulator-min-microvolt = <1800000>;
261 regulator-max-microvol 208 regulator-max-microvolt = <2960000>;
262 regulator-initial-mode 209 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
263 }; 210 };
264 211
265 vreg_l14a_1p88: ldo14 { 212 vreg_l14a_1p88: ldo14 {
266 regulator-min-microvol 213 regulator-min-microvolt = <1800000>;
267 regulator-max-microvol 214 regulator-max-microvolt = <1800000>;
268 regulator-initial-mode 215 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
269 }; 216 };
270 217
271 vreg_l15a_1p8: ldo15 { 218 vreg_l15a_1p8: ldo15 {
272 regulator-min-microvol 219 regulator-min-microvolt = <1800000>;
273 regulator-max-microvol 220 regulator-max-microvolt = <1800000>;
274 regulator-initial-mode 221 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
275 }; 222 };
276 223
277 vreg_l16a_2p7: ldo16 { 224 vreg_l16a_2p7: ldo16 {
278 regulator-min-microvol 225 regulator-min-microvolt = <2704000>;
279 regulator-max-microvol 226 regulator-max-microvolt = <2704000>;
280 regulator-initial-mode 227 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
281 }; 228 };
282 229
283 vreg_l17a_1p3: ldo17 { 230 vreg_l17a_1p3: ldo17 {
284 regulator-min-microvol 231 regulator-min-microvolt = <1304000>;
285 regulator-max-microvol 232 regulator-max-microvolt = <1304000>;
286 regulator-initial-mode 233 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
287 }; 234 };
288 235
289 vreg_l18a_2p7: ldo18 { 236 vreg_l18a_2p7: ldo18 {
290 regulator-min-microvol 237 regulator-min-microvolt = <2704000>;
291 regulator-max-microvol 238 regulator-max-microvolt = <2960000>;
292 regulator-initial-mode 239 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
293 }; 240 };
294 241
295 vreg_l19a_3p0: ldo19 { 242 vreg_l19a_3p0: ldo19 {
296 regulator-min-microvol 243 regulator-min-microvolt = <2856000>;
297 regulator-max-microvol 244 regulator-max-microvolt = <3104000>;
298 regulator-initial-mode 245 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
299 }; 246 };
300 247
301 vreg_l20a_2p95: ldo20 { 248 vreg_l20a_2p95: ldo20 {
302 regulator-min-microvol 249 regulator-min-microvolt = <2704000>;
303 regulator-max-microvol 250 regulator-max-microvolt = <2960000>;
304 regulator-initial-mode 251 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
305 }; 252 };
306 253
307 vreg_l21a_2p95: ldo21 { 254 vreg_l21a_2p95: ldo21 {
308 regulator-min-microvol 255 regulator-min-microvolt = <2704000>;
309 regulator-max-microvol 256 regulator-max-microvolt = <2960000>;
310 regulator-initial-mode 257 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
311 }; 258 };
312 259
313 vreg_l22a_2p85: ldo22 { 260 vreg_l22a_2p85: ldo22 {
314 regulator-min-microvol 261 regulator-min-microvolt = <2864000>;
315 regulator-max-microvol 262 regulator-max-microvolt = <3312000>;
316 regulator-initial-mode 263 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
317 }; 264 };
318 265
319 vreg_l23a_3p3: ldo23 { 266 vreg_l23a_3p3: ldo23 {
320 regulator-min-microvol 267 regulator-min-microvolt = <3000000>;
321 regulator-max-microvol 268 regulator-max-microvolt = <3312000>;
322 regulator-initial-mode 269 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
323 }; 270 };
324 271
325 vdda_qusb_hs0_3p1: 272 vdda_qusb_hs0_3p1:
326 vreg_l24a_3p075: ldo24 { 273 vreg_l24a_3p075: ldo24 {
327 regulator-min-microvol 274 regulator-min-microvolt = <3088000>;
328 regulator-max-microvol 275 regulator-max-microvolt = <3088000>;
329 regulator-initial-mode 276 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
330 }; 277 };
331 278
332 vreg_l25a_3p3: ldo25 { 279 vreg_l25a_3p3: ldo25 {
333 regulator-min-microvol 280 regulator-min-microvolt = <3300000>;
334 regulator-max-microvol 281 regulator-max-microvolt = <3312000>;
335 regulator-initial-mode 282 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
336 }; 283 };
337 284
338 vdda_hp_pcie_1p2: 285 vdda_hp_pcie_1p2:
339 vdda_hv_ebi0: 286 vdda_hv_ebi0:
340 vdda_hv_ebi1: 287 vdda_hv_ebi1:
341 vdda_hv_ebi2: 288 vdda_hv_ebi2:
342 vdda_hv_ebi3: 289 vdda_hv_ebi3:
343 vdda_mipi_csi_1p25: 290 vdda_mipi_csi_1p25:
344 vdda_mipi_dsi0_1p2: 291 vdda_mipi_dsi0_1p2:
345 vdda_mipi_dsi1_1p2: 292 vdda_mipi_dsi1_1p2:
346 vdda_pcie_1p2: 293 vdda_pcie_1p2:
347 vdda_ufs1_1p2: 294 vdda_ufs1_1p2:
348 vdda_ufs2_1p2: 295 vdda_ufs2_1p2:
349 vdda_usb1_ss_1p2: 296 vdda_usb1_ss_1p2:
350 vdda_usb2_ss_1p2: 297 vdda_usb2_ss_1p2:
351 vreg_l26a_1p2: ldo26 { 298 vreg_l26a_1p2: ldo26 {
352 regulator-min-microvol 299 regulator-min-microvolt = <1200000>;
353 regulator-max-microvol 300 regulator-max-microvolt = <1200000>;
354 regulator-initial-mode 301 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
355 }; 302 };
356 303
357 vreg_l28a_3p0: ldo28 { 304 vreg_l28a_3p0: ldo28 {
358 regulator-min-microvol 305 regulator-min-microvolt = <2856000>;
359 regulator-max-microvol 306 regulator-max-microvolt = <3008000>;
360 regulator-initial-mode 307 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
361 }; 308 };
362 309
363 vreg_lvs1a_1p8: lvs1 { 310 vreg_lvs1a_1p8: lvs1 {
364 regulator-min-microvol 311 regulator-min-microvolt = <1800000>;
365 regulator-max-microvol 312 regulator-max-microvolt = <1800000>;
366 }; 313 };
367 314
368 vreg_lvs2a_1p8: lvs2 { 315 vreg_lvs2a_1p8: lvs2 {
369 regulator-min-microvol 316 regulator-min-microvolt = <1800000>;
370 regulator-max-microvol 317 regulator-max-microvolt = <1800000>;
371 }; 318 };
372 }; 319 };
373 320
374 regulators-1 { !! 321 pmi8998-rpmh-regulators {
375 compatible = "qcom,pmi8998-rpm 322 compatible = "qcom,pmi8998-rpmh-regulators";
376 qcom,pmic-id = "b"; 323 qcom,pmic-id = "b";
377 324
378 vdd-bob-supply = <&vph_pwr>; 325 vdd-bob-supply = <&vph_pwr>;
379 326
380 vreg_bob: bob { 327 vreg_bob: bob {
381 regulator-min-microvol 328 regulator-min-microvolt = <3312000>;
382 regulator-max-microvol 329 regulator-max-microvolt = <3600000>;
383 regulator-initial-mode 330 regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
384 regulator-allow-bypass 331 regulator-allow-bypass;
385 }; 332 };
386 }; 333 };
387 334
388 regulators-2 { !! 335 pm8005-rpmh-regulators {
389 compatible = "qcom,pm8005-rpmh 336 compatible = "qcom,pm8005-rpmh-regulators";
390 qcom,pmic-id = "c"; 337 qcom,pmic-id = "c";
391 338
392 vdd-s1-supply = <&vph_pwr>; 339 vdd-s1-supply = <&vph_pwr>;
393 vdd-s2-supply = <&vph_pwr>; 340 vdd-s2-supply = <&vph_pwr>;
394 vdd-s3-supply = <&vph_pwr>; 341 vdd-s3-supply = <&vph_pwr>;
395 vdd-s4-supply = <&vph_pwr>; 342 vdd-s4-supply = <&vph_pwr>;
396 343
397 vreg_s3c_0p6: smps3 { 344 vreg_s3c_0p6: smps3 {
398 regulator-min-microvol 345 regulator-min-microvolt = <600000>;
399 regulator-max-microvol 346 regulator-max-microvolt = <600000>;
400 }; 347 };
401 }; 348 };
402 }; 349 };
403 350
404 &cdsp_pas { 351 &cdsp_pas {
405 status = "okay"; 352 status = "okay";
406 firmware-name = "qcom/sdm845/cdsp.mbn" !! 353 firmware-name = "qcom/sdm845/cdsp.mdt";
407 }; 354 };
408 355
409 &gcc { !! 356 &dsi0 {
410 protected-clocks = <GCC_QSPI_CORE_CLK> <<
411 <GCC_QSPI_CORE_CLK_ <<
412 <GCC_QSPI_CNOC_PERI <<
413 <GCC_LPASS_Q6_AXI_C <<
414 <GCC_LPASS_SWAY_CLK <<
415 }; <<
416 <<
417 &gmu { <<
418 status = "okay"; <<
419 }; <<
420 <<
421 &gpu { <<
422 status = "okay"; <<
423 <<
424 zap-shader { <<
425 memory-region = <&gpu_mem>; <<
426 firmware-name = "qcom/sdm845/a <<
427 }; <<
428 }; <<
429 <<
430 &i2c10 { <<
431 status = "okay"; <<
432 clock-frequency = <400000>; <<
433 }; <<
434 <<
435 &ipa { <<
436 qcom,gsi-loader = "self"; <<
437 memory-region = <&ipa_fw_mem>; <<
438 status = "okay"; <<
439 }; <<
440 <<
441 &mdss { <<
442 status = "okay"; <<
443 }; <<
444 <<
445 &mdss_dsi0 { <<
446 status = "okay"; 357 status = "okay";
447 vdda-supply = <&vdda_mipi_dsi0_1p2>; 358 vdda-supply = <&vdda_mipi_dsi0_1p2>;
448 359
449 qcom,dual-dsi-mode; 360 qcom,dual-dsi-mode;
450 qcom,master-dsi; 361 qcom,master-dsi;
451 362
452 ports { 363 ports {
453 port@1 { 364 port@1 {
454 endpoint { 365 endpoint {
455 remote-endpoin 366 remote-endpoint = <&truly_in_0>;
456 data-lanes = < 367 data-lanes = <0 1 2 3>;
457 }; 368 };
458 }; 369 };
459 }; 370 };
460 371
461 panel@0 { 372 panel@0 {
462 compatible = "truly,nt35597-2K 373 compatible = "truly,nt35597-2K-display";
463 reg = <0>; 374 reg = <0>;
464 vdda-supply = <&vreg_l14a_1p88 375 vdda-supply = <&vreg_l14a_1p88>;
465 376
466 reset-gpios = <&tlmm 6 GPIO_AC 377 reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
467 mode-gpios = <&tlmm 52 GPIO_AC 378 mode-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
468 379
469 ports { 380 ports {
470 #address-cells = <1>; 381 #address-cells = <1>;
471 #size-cells = <0>; 382 #size-cells = <0>;
472 383
473 port@0 { 384 port@0 {
474 reg = <0>; 385 reg = <0>;
475 truly_in_0: en 386 truly_in_0: endpoint {
476 remote !! 387 remote-endpoint = <&dsi0_out>;
477 }; 388 };
478 }; 389 };
479 390
480 port@1 { 391 port@1 {
481 reg = <1>; 392 reg = <1>;
482 truly_in_1: en 393 truly_in_1: endpoint {
483 remote !! 394 remote-endpoint = <&dsi1_out>;
484 }; 395 };
485 }; 396 };
486 }; 397 };
487 }; 398 };
488 }; 399 };
489 400
490 &mdss_dsi0_phy { !! 401 &dsi0_phy {
491 status = "okay"; 402 status = "okay";
492 vdds-supply = <&vdda_mipi_dsi0_pll>; 403 vdds-supply = <&vdda_mipi_dsi0_pll>;
493 }; 404 };
494 405
495 &mdss_dsi1 { !! 406 &dsi1 {
496 status = "okay"; 407 status = "okay";
497 vdda-supply = <&vdda_mipi_dsi1_1p2>; 408 vdda-supply = <&vdda_mipi_dsi1_1p2>;
498 409
499 qcom,dual-dsi-mode; 410 qcom,dual-dsi-mode;
500 411
501 /* DSI1 is slave, so use DSI0 clocks * 412 /* DSI1 is slave, so use DSI0 clocks */
502 assigned-clock-parents = <&mdss_dsi0_p !! 413 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
503 414
504 ports { 415 ports {
505 port@1 { 416 port@1 {
506 endpoint { 417 endpoint {
507 remote-endpoin 418 remote-endpoint = <&truly_in_1>;
508 data-lanes = < 419 data-lanes = <0 1 2 3>;
509 }; 420 };
510 }; 421 };
511 }; 422 };
512 }; 423 };
513 424
514 &mdss_dsi1_phy { !! 425 &dsi1_phy {
515 status = "okay"; 426 status = "okay";
516 vdds-supply = <&vdda_mipi_dsi1_pll>; 427 vdds-supply = <&vdda_mipi_dsi1_pll>;
517 }; 428 };
518 429
519 &mss_pil { !! 430 &gcc {
520 status = "okay"; !! 431 protected-clocks = <GCC_QSPI_CORE_CLK>,
521 firmware-name = "qcom/sdm845/mba.mbn", !! 432 <GCC_QSPI_CORE_CLK_SRC>,
>> 433 <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>> 434 <GCC_LPASS_Q6_AXI_CLK>,
>> 435 <GCC_LPASS_SWAY_CLK>;
522 }; 436 };
523 437
524 &pcie0 { !! 438 &gmu {
525 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LO <<
526 <<
527 pinctrl-0 = <&pcie0_default_state>; <<
528 pinctrl-names = "default"; <<
529 <<
530 status = "okay"; 439 status = "okay";
531 }; 440 };
532 441
533 &pcie0_phy { !! 442 &gpu {
534 vdda-phy-supply = <&vreg_l1a_0p875>; <<
535 vdda-pll-supply = <&vreg_l26a_1p2>; <<
536 <<
537 status = "okay"; 443 status = "okay";
538 }; <<
539 <<
540 &pcie1 { <<
541 perst-gpios = <&tlmm 102 GPIO_ACTIVE_L <<
542 444
543 pinctrl-names = "default"; !! 445 zap-shader {
544 pinctrl-0 = <&pcie1_default_state>; !! 446 memory-region = <&gpu_mem>;
545 !! 447 firmware-name = "qcom/sdm845/a630_zap.mbn";
546 status = "okay"; !! 448 };
547 }; 449 };
548 450
549 &pcie1_phy { !! 451 &i2c10 {
550 status = "okay"; 452 status = "okay";
551 !! 453 clock-frequency = <400000>;
552 vdda-phy-supply = <&vreg_l1a_0p875>; <<
553 vdda-pll-supply = <&vreg_l26a_1p2>; <<
554 }; 454 };
555 455
556 &pm8998_adc { !! 456 &ipa {
557 channel@4c { !! 457 status = "okay";
558 reg = <ADC5_XO_THERM_100K_PU>; !! 458 memory-region = <&ipa_fw_mem>;
559 label = "xo_therm"; <<
560 qcom,ratiometric; <<
561 qcom,hw-settle-time = <200>; <<
562 }; <<
563 <<
564 channel@4d { <<
565 reg = <ADC5_AMUX_THM1_100K_PU> <<
566 label = "msm_therm"; <<
567 qcom,ratiometric; <<
568 qcom,hw-settle-time = <200>; <<
569 }; <<
570 <<
571 channel@4f { <<
572 reg = <ADC5_AMUX_THM3_100K_PU> <<
573 label = "pa_therm1"; <<
574 qcom,ratiometric; <<
575 qcom,hw-settle-time = <200>; <<
576 }; <<
577 <<
578 channel@51 { <<
579 reg = <ADC5_AMUX_THM5_100K_PU> <<
580 label = "quiet_therm"; <<
581 qcom,ratiometric; <<
582 qcom,hw-settle-time = <200>; <<
583 }; <<
584 <<
585 channel@83 { <<
586 reg = <ADC5_VPH_PWR>; <<
587 label = "vph_pwr"; <<
588 qcom,ratiometric; <<
589 qcom,hw-settle-time = <200>; <<
590 }; <<
591 <<
592 channel@85 { <<
593 reg = <ADC5_VCOIN>; <<
594 label = "vcoin"; <<
595 qcom,ratiometric; <<
596 qcom,hw-settle-time = <200>; <<
597 }; <<
598 }; 459 };
599 460
600 &pm8998_adc_tm { !! 461 &mdss {
601 status = "okay"; 462 status = "okay";
602 <<
603 xo-thermistor@1 { <<
604 reg = <1>; <<
605 io-channels = <&pm8998_adc ADC <<
606 qcom,ratiometric; <<
607 qcom,hw-settle-time-us = <200> <<
608 }; <<
609 <<
610 msm-thermistor@2 { <<
611 reg = <2>; <<
612 io-channels = <&pm8998_adc ADC <<
613 qcom,ratiometric; <<
614 qcom,hw-settle-time-us = <200> <<
615 }; <<
616 <<
617 pa-thermistor@3 { <<
618 reg = <3>; <<
619 io-channels = <&pm8998_adc ADC <<
620 qcom,ratiometric; <<
621 qcom,hw-settle-time-us = <200> <<
622 }; <<
623 <<
624 quiet-thermistor@4 { <<
625 reg = <4>; <<
626 io-channels = <&pm8998_adc ADC <<
627 qcom,ratiometric; <<
628 qcom,hw-settle-time-us = <200> <<
629 }; <<
630 }; 463 };
631 464
632 &pm8998_resin { !! 465 &mss_pil {
633 linux,code = <KEY_VOLUMEDOWN>; <<
634 status = "okay"; 466 status = "okay";
>> 467 firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
635 }; 468 };
636 469
637 &qupv3_id_1 { 470 &qupv3_id_1 {
638 status = "okay"; 471 status = "okay";
639 }; 472 };
640 473
641 &sdhc_2 { 474 &sdhc_2 {
642 status = "okay"; 475 status = "okay";
643 476
644 pinctrl-names = "default"; 477 pinctrl-names = "default";
645 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2 478 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_card_det_n>;
646 479
647 vmmc-supply = <&vreg_l21a_2p95>; 480 vmmc-supply = <&vreg_l21a_2p95>;
648 vqmmc-supply = <&vddpx_2>; 481 vqmmc-supply = <&vddpx_2>;
649 482
650 cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW> 483 cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
651 }; 484 };
652 485
653 &tlmm { <<
654 pcie0_default_state: pcie0-default-sta <<
655 clkreq-pins { <<
656 pins = "gpio36"; <<
657 function = "pci_e0"; <<
658 bias-pull-up; <<
659 }; <<
660 <<
661 perst-n-pins { <<
662 pins = "gpio35"; <<
663 function = "gpio"; <<
664 drive-strength = <2>; <<
665 bias-pull-down; <<
666 }; <<
667 <<
668 wake-n-pins { <<
669 pins = "gpio37"; <<
670 function = "gpio"; <<
671 drive-strength = <2>; <<
672 bias-pull-up; <<
673 }; <<
674 }; <<
675 <<
676 pcie1_default_state: pcie1-default-sta <<
677 clkreq-pins { <<
678 pins = "gpio103"; <<
679 function = "pci_e1"; <<
680 bias-pull-up; <<
681 }; <<
682 <<
683 perst-n-pins { <<
684 pins = "gpio102"; <<
685 function = "gpio"; <<
686 drive-strength = <16>; <<
687 bias-pull-down; <<
688 }; <<
689 <<
690 wake-n-pins { <<
691 pins = "gpio104"; <<
692 function = "gpio"; <<
693 drive-strength = <2>; <<
694 bias-pull-up; <<
695 }; <<
696 }; <<
697 }; <<
698 <<
699 &uart9 { 486 &uart9 {
700 status = "okay"; 487 status = "okay";
701 }; 488 };
702 489
703 &ufs_mem_hc { 490 &ufs_mem_hc {
704 status = "okay"; 491 status = "okay";
705 492
706 reset-gpios = <&tlmm 150 GPIO_ACTIVE_L 493 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
707 494
708 vcc-supply = <&vreg_l20a_2p95>; 495 vcc-supply = <&vreg_l20a_2p95>;
709 vcc-max-microamp = <600000>; 496 vcc-max-microamp = <600000>;
710 }; 497 };
711 498
712 &ufs_mem_phy { 499 &ufs_mem_phy {
713 status = "okay"; 500 status = "okay";
714 501
715 vdda-phy-supply = <&vdda_ufs1_core>; 502 vdda-phy-supply = <&vdda_ufs1_core>;
716 vdda-pll-supply = <&vdda_ufs1_1p2>; 503 vdda-pll-supply = <&vdda_ufs1_1p2>;
717 }; 504 };
718 505
719 &usb_1 { 506 &usb_1 {
720 status = "okay"; 507 status = "okay";
721 }; 508 };
722 509
723 &usb_1_dwc3 { 510 &usb_1_dwc3 {
724 /* Until we have Type C hooked up we'l 511 /* Until we have Type C hooked up we'll force this as peripheral. */
725 dr_mode = "peripheral"; 512 dr_mode = "peripheral";
726 }; 513 };
727 514
728 &usb_1_hsphy { 515 &usb_1_hsphy {
729 status = "okay"; 516 status = "okay";
730 517
731 vdd-supply = <&vdda_usb1_ss_core>; 518 vdd-supply = <&vdda_usb1_ss_core>;
732 vdda-pll-supply = <&vdda_qusb_hs0_1p8> 519 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
733 vdda-phy-dpdm-supply = <&vdda_qusb_hs0 520 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
734 521
735 qcom,imp-res-offset-value = <8>; 522 qcom,imp-res-offset-value = <8>;
736 qcom,hstx-trim-value = <QUSB2_V2_HSTX_ 523 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
737 qcom,preemphasis-level = <QUSB2_V2_PRE 524 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
738 qcom,preemphasis-width = <QUSB2_V2_PRE 525 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
739 }; 526 };
740 527
741 &usb_1_qmpphy { 528 &usb_1_qmpphy {
742 status = "okay"; 529 status = "okay";
743 530
744 vdda-phy-supply = <&vdda_usb1_ss_1p2>; 531 vdda-phy-supply = <&vdda_usb1_ss_1p2>;
745 vdda-pll-supply = <&vdda_usb1_ss_core> 532 vdda-pll-supply = <&vdda_usb1_ss_core>;
746 }; 533 };
747 534
748 &usb_2 { 535 &usb_2 {
749 status = "okay"; 536 status = "okay";
750 }; 537 };
751 538
752 &usb_2_dwc3 { 539 &usb_2_dwc3 {
753 /* 540 /*
754 * Though the USB block on SDM845 can 541 * Though the USB block on SDM845 can support host, there's no vbus
755 * signal for this port on MTP. Thus 542 * signal for this port on MTP. Thus (unless you have a non-compliant
756 * hub that works without vbus) the on 543 * hub that works without vbus) the only sensible thing is to force
757 * peripheral mode. 544 * peripheral mode.
758 */ 545 */
759 dr_mode = "peripheral"; 546 dr_mode = "peripheral";
760 }; 547 };
761 548
762 &usb_2_hsphy { 549 &usb_2_hsphy {
763 status = "okay"; 550 status = "okay";
764 551
765 vdd-supply = <&vdda_usb2_ss_core>; 552 vdd-supply = <&vdda_usb2_ss_core>;
766 vdda-pll-supply = <&vdda_qusb_hs0_1p8> 553 vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
767 vdda-phy-dpdm-supply = <&vdda_qusb_hs0 554 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
768 555
769 qcom,imp-res-offset-value = <8>; 556 qcom,imp-res-offset-value = <8>;
770 qcom,hstx-trim-value = <QUSB2_V2_HSTX_ 557 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
771 }; 558 };
772 559
773 &usb_2_qmpphy { 560 &usb_2_qmpphy {
774 status = "okay"; 561 status = "okay";
775 562
776 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 563 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
777 vdda-pll-supply = <&vdda_usb2_ss_core> 564 vdda-pll-supply = <&vdda_usb2_ss_core>;
778 }; 565 };
779 566
780 &venus { 567 &venus {
781 status = "okay"; 568 status = "okay";
782 }; 569 };
783 570
784 &wifi { 571 &wifi {
785 status = "okay"; 572 status = "okay";
786 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8> 573 vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
787 vdd-1.8-xo-supply = <&vreg_l7a_1p8>; 574 vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
788 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; 575 vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
789 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; 576 vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
790 <<
791 qcom,snoc-host-cap-8bit-quirk; <<
792 qcom,ath10k-calibration-variant = "Qua <<
793 }; 577 };
794 578
795 /* PINCTRL - additions to nodes defined in sdm 579 /* PINCTRL - additions to nodes defined in sdm845.dtsi */
796 580
797 &qup_i2c10_default { 581 &qup_i2c10_default {
798 drive-strength = <2>; !! 582 pinconf {
799 bias-disable; !! 583 pins = "gpio55", "gpio56";
>> 584 drive-strength = <2>;
>> 585 bias-disable;
>> 586 };
800 }; 587 };
801 588
802 &qup_uart9_rx { !! 589 &qup_uart9_default {
803 drive-strength = <2>; !! 590 pinconf-tx {
804 bias-pull-up; !! 591 pins = "gpio4";
805 }; !! 592 drive-strength = <2>;
>> 593 bias-disable;
>> 594 };
806 595
807 &qup_uart9_tx { !! 596 pinconf-rx {
808 drive-strength = <2>; !! 597 pins = "gpio5";
809 bias-disable; !! 598 drive-strength = <2>;
>> 599 bias-pull-up;
>> 600 };
810 }; 601 };
811 602
812 &tlmm { 603 &tlmm {
813 gpio-reserved-ranges = <0 4>, <81 4>; 604 gpio-reserved-ranges = <0 4>, <81 4>;
814 605
815 sdc2_clk: sdc2-clk-state { !! 606 sdc2_clk: sdc2-clk {
816 pins = "sdc2_clk"; !! 607 pinconf {
817 bias-disable; !! 608 pins = "sdc2_clk";
818 !! 609 bias-disable;
819 /* !! 610
820 * It seems that mmc_test repo !! 611 /*
821 * strength is not 16 on clk, !! 612 * It seems that mmc_test reports errors if drive
822 */ !! 613 * strength is not 16 on clk, cmd, and data pins.
823 drive-strength = <16>; !! 614 */
>> 615 drive-strength = <16>;
>> 616 };
824 }; 617 };
825 618
826 sdc2_cmd: sdc2-cmd-state { !! 619 sdc2_cmd: sdc2-cmd {
827 pins = "sdc2_cmd"; !! 620 pinconf {
828 bias-pull-up; !! 621 pins = "sdc2_cmd";
829 drive-strength = <16>; !! 622 bias-pull-up;
>> 623 drive-strength = <16>;
>> 624 };
830 }; 625 };
831 626
832 sdc2_data: sdc2-data-state { !! 627 sdc2_data: sdc2-data {
833 pins = "sdc2_data"; !! 628 pinconf {
834 bias-pull-up; !! 629 pins = "sdc2_data";
835 drive-strength = <16>; !! 630 bias-pull-up;
>> 631 drive-strength = <16>;
>> 632 };
836 }; 633 };
837 634
838 sd_card_det_n: sd-card-det-n-state { !! 635 sd_card_det_n: sd-card-det-n {
839 pins = "gpio126"; !! 636 pinmux {
840 function = "gpio"; !! 637 pins = "gpio126";
841 bias-pull-up; !! 638 function = "gpio";
>> 639 };
>> 640
>> 641 pinconf {
>> 642 pins = "gpio126";
>> 643 bias-pull-up;
>> 644 };
842 }; 645 };
843 }; 646 };
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