1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> 15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h> 16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h> 18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,osm-l3 19 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 20 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> 22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 24 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 25 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 27 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 29 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 30 #include <dt-bindings/thermal/thermal.h>
31 31
32 / { 32 / {
33 interrupt-parent = <&intc>; 33 interrupt-parent = <&intc>;
34 34
35 #address-cells = <2>; 35 #address-cells = <2>;
36 #size-cells = <2>; 36 #size-cells = <2>;
37 37
38 aliases { 38 aliases {
39 i2c0 = &i2c0; 39 i2c0 = &i2c0;
40 i2c1 = &i2c1; 40 i2c1 = &i2c1;
41 i2c2 = &i2c2; 41 i2c2 = &i2c2;
42 i2c3 = &i2c3; 42 i2c3 = &i2c3;
43 i2c4 = &i2c4; 43 i2c4 = &i2c4;
44 i2c5 = &i2c5; 44 i2c5 = &i2c5;
45 i2c6 = &i2c6; 45 i2c6 = &i2c6;
46 i2c7 = &i2c7; 46 i2c7 = &i2c7;
47 i2c8 = &i2c8; 47 i2c8 = &i2c8;
48 i2c9 = &i2c9; 48 i2c9 = &i2c9;
49 i2c10 = &i2c10; 49 i2c10 = &i2c10;
50 i2c11 = &i2c11; 50 i2c11 = &i2c11;
51 i2c12 = &i2c12; 51 i2c12 = &i2c12;
52 i2c13 = &i2c13; 52 i2c13 = &i2c13;
53 i2c14 = &i2c14; 53 i2c14 = &i2c14;
54 i2c15 = &i2c15; 54 i2c15 = &i2c15;
55 spi0 = &spi0; 55 spi0 = &spi0;
56 spi1 = &spi1; 56 spi1 = &spi1;
57 spi2 = &spi2; 57 spi2 = &spi2;
58 spi3 = &spi3; 58 spi3 = &spi3;
59 spi4 = &spi4; 59 spi4 = &spi4;
60 spi5 = &spi5; 60 spi5 = &spi5;
61 spi6 = &spi6; 61 spi6 = &spi6;
62 spi7 = &spi7; 62 spi7 = &spi7;
63 spi8 = &spi8; 63 spi8 = &spi8;
64 spi9 = &spi9; 64 spi9 = &spi9;
65 spi10 = &spi10; 65 spi10 = &spi10;
66 spi11 = &spi11; 66 spi11 = &spi11;
67 spi12 = &spi12; 67 spi12 = &spi12;
68 spi13 = &spi13; 68 spi13 = &spi13;
69 spi14 = &spi14; 69 spi14 = &spi14;
70 spi15 = &spi15; 70 spi15 = &spi15;
71 }; 71 };
72 72
73 chosen { }; 73 chosen { };
74 74
75 clocks { 75 clocks {
76 xo_board: xo-board { 76 xo_board: xo-board {
77 compatible = "fixed-cl 77 compatible = "fixed-clock";
78 #clock-cells = <0>; 78 #clock-cells = <0>;
79 clock-frequency = <384 79 clock-frequency = <38400000>;
80 clock-output-names = " 80 clock-output-names = "xo_board";
81 }; 81 };
82 82
83 sleep_clk: sleep-clk { 83 sleep_clk: sleep-clk {
84 compatible = "fixed-cl 84 compatible = "fixed-clock";
85 #clock-cells = <0>; 85 #clock-cells = <0>;
86 clock-frequency = <327 86 clock-frequency = <32764>;
87 }; 87 };
88 }; 88 };
89 89
90 cpus: cpus { 90 cpus: cpus {
91 #address-cells = <2>; 91 #address-cells = <2>;
92 #size-cells = <0>; 92 #size-cells = <0>;
93 93
94 CPU0: cpu@0 { 94 CPU0: cpu@0 {
95 device_type = "cpu"; 95 device_type = "cpu";
96 compatible = "qcom,kry 96 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 98 clocks = <&cpufreq_hw 0>;
99 enable-method = "psci" 99 enable-method = "psci";
100 capacity-dmips-mhz = < 100 capacity-dmips-mhz = <611>;
101 dynamic-power-coeffici 101 dynamic-power-coefficient = <154>;
102 qcom,freq-domain = <&c 102 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 103 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 104 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 105 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ 106 power-domains = <&CPU_PD0>;
107 power-domain-names = " 107 power-domain-names = "psci";
108 #cooling-cells = <2>; 108 #cooling-cells = <2>;
109 next-level-cache = <&L 109 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 110 L2_0: l2-cache {
111 compatible = " 111 compatible = "cache";
112 cache-level = 112 cache-level = <2>;
113 cache-unified; 113 cache-unified;
114 next-level-cac 114 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 115 L3_0: l3-cache {
116 compat 116 compatible = "cache";
117 cache- 117 cache-level = <3>;
118 cache- 118 cache-unified;
119 }; 119 };
120 }; 120 };
121 }; 121 };
122 122
123 CPU1: cpu@100 { 123 CPU1: cpu@100 {
124 device_type = "cpu"; 124 device_type = "cpu";
125 compatible = "qcom,kry 125 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 127 clocks = <&cpufreq_hw 0>;
128 enable-method = "psci" 128 enable-method = "psci";
129 capacity-dmips-mhz = < 129 capacity-dmips-mhz = <611>;
130 dynamic-power-coeffici 130 dynamic-power-coefficient = <154>;
131 qcom,freq-domain = <&c 131 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 132 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 133 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 134 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ 135 power-domains = <&CPU_PD1>;
136 power-domain-names = " 136 power-domain-names = "psci";
137 #cooling-cells = <2>; 137 #cooling-cells = <2>;
138 next-level-cache = <&L 138 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 139 L2_100: l2-cache {
140 compatible = " 140 compatible = "cache";
141 cache-level = 141 cache-level = <2>;
142 cache-unified; 142 cache-unified;
143 next-level-cac 143 next-level-cache = <&L3_0>;
144 }; 144 };
145 }; 145 };
146 146
147 CPU2: cpu@200 { 147 CPU2: cpu@200 {
148 device_type = "cpu"; 148 device_type = "cpu";
149 compatible = "qcom,kry 149 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 150 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw 151 clocks = <&cpufreq_hw 0>;
152 enable-method = "psci" 152 enable-method = "psci";
153 capacity-dmips-mhz = < 153 capacity-dmips-mhz = <611>;
154 dynamic-power-coeffici 154 dynamic-power-coefficient = <154>;
155 qcom,freq-domain = <&c 155 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 156 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 157 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 158 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ 159 power-domains = <&CPU_PD2>;
160 power-domain-names = " 160 power-domain-names = "psci";
161 #cooling-cells = <2>; 161 #cooling-cells = <2>;
162 next-level-cache = <&L 162 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 163 L2_200: l2-cache {
164 compatible = " 164 compatible = "cache";
165 cache-level = 165 cache-level = <2>;
166 cache-unified; 166 cache-unified;
167 next-level-cac 167 next-level-cache = <&L3_0>;
168 }; 168 };
169 }; 169 };
170 170
171 CPU3: cpu@300 { 171 CPU3: cpu@300 {
172 device_type = "cpu"; 172 device_type = "cpu";
173 compatible = "qcom,kry 173 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 174 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw 175 clocks = <&cpufreq_hw 0>;
176 enable-method = "psci" 176 enable-method = "psci";
177 capacity-dmips-mhz = < 177 capacity-dmips-mhz = <611>;
178 dynamic-power-coeffici 178 dynamic-power-coefficient = <154>;
179 qcom,freq-domain = <&c 179 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 180 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 181 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 182 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 183 #cooling-cells = <2>;
184 power-domains = <&CPU_ 184 power-domains = <&CPU_PD3>;
185 power-domain-names = " 185 power-domain-names = "psci";
186 next-level-cache = <&L 186 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 187 L2_300: l2-cache {
188 compatible = " 188 compatible = "cache";
189 cache-level = 189 cache-level = <2>;
190 cache-unified; 190 cache-unified;
191 next-level-cac 191 next-level-cache = <&L3_0>;
192 }; 192 };
193 }; 193 };
194 194
195 CPU4: cpu@400 { 195 CPU4: cpu@400 {
196 device_type = "cpu"; 196 device_type = "cpu";
197 compatible = "qcom,kry 197 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 198 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw 199 clocks = <&cpufreq_hw 1>;
200 enable-method = "psci" 200 enable-method = "psci";
201 capacity-dmips-mhz = < 201 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici 202 dynamic-power-coefficient = <442>;
203 qcom,freq-domain = <&c 203 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 204 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 205 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 206 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ 207 power-domains = <&CPU_PD4>;
208 power-domain-names = " 208 power-domain-names = "psci";
209 #cooling-cells = <2>; 209 #cooling-cells = <2>;
210 next-level-cache = <&L 210 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 211 L2_400: l2-cache {
212 compatible = " 212 compatible = "cache";
213 cache-level = 213 cache-level = <2>;
214 cache-unified; 214 cache-unified;
215 next-level-cac 215 next-level-cache = <&L3_0>;
216 }; 216 };
217 }; 217 };
218 218
219 CPU5: cpu@500 { 219 CPU5: cpu@500 {
220 device_type = "cpu"; 220 device_type = "cpu";
221 compatible = "qcom,kry 221 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 222 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw 223 clocks = <&cpufreq_hw 1>;
224 enable-method = "psci" 224 enable-method = "psci";
225 capacity-dmips-mhz = < 225 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici 226 dynamic-power-coefficient = <442>;
227 qcom,freq-domain = <&c 227 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 228 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 229 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 230 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ 231 power-domains = <&CPU_PD5>;
232 power-domain-names = " 232 power-domain-names = "psci";
233 #cooling-cells = <2>; 233 #cooling-cells = <2>;
234 next-level-cache = <&L 234 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 235 L2_500: l2-cache {
236 compatible = " 236 compatible = "cache";
237 cache-level = 237 cache-level = <2>;
238 cache-unified; 238 cache-unified;
239 next-level-cac 239 next-level-cache = <&L3_0>;
240 }; 240 };
241 }; 241 };
242 242
243 CPU6: cpu@600 { 243 CPU6: cpu@600 {
244 device_type = "cpu"; 244 device_type = "cpu";
245 compatible = "qcom,kry 245 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 246 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw 247 clocks = <&cpufreq_hw 1>;
248 enable-method = "psci" 248 enable-method = "psci";
249 capacity-dmips-mhz = < 249 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici 250 dynamic-power-coefficient = <442>;
251 qcom,freq-domain = <&c 251 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 252 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 253 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 254 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ 255 power-domains = <&CPU_PD6>;
256 power-domain-names = " 256 power-domain-names = "psci";
257 #cooling-cells = <2>; 257 #cooling-cells = <2>;
258 next-level-cache = <&L 258 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 259 L2_600: l2-cache {
260 compatible = " 260 compatible = "cache";
261 cache-level = 261 cache-level = <2>;
262 cache-unified; 262 cache-unified;
263 next-level-cac 263 next-level-cache = <&L3_0>;
264 }; 264 };
265 }; 265 };
266 266
267 CPU7: cpu@700 { 267 CPU7: cpu@700 {
268 device_type = "cpu"; 268 device_type = "cpu";
269 compatible = "qcom,kry 269 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 270 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw 271 clocks = <&cpufreq_hw 1>;
272 enable-method = "psci" 272 enable-method = "psci";
273 capacity-dmips-mhz = < 273 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici 274 dynamic-power-coefficient = <442>;
275 qcom,freq-domain = <&c 275 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 276 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 277 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 278 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ 279 power-domains = <&CPU_PD7>;
280 power-domain-names = " 280 power-domain-names = "psci";
281 #cooling-cells = <2>; 281 #cooling-cells = <2>;
282 next-level-cache = <&L 282 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 283 L2_700: l2-cache {
284 compatible = " 284 compatible = "cache";
285 cache-level = 285 cache-level = <2>;
286 cache-unified; 286 cache-unified;
287 next-level-cac 287 next-level-cache = <&L3_0>;
288 }; 288 };
289 }; 289 };
290 290
291 cpu-map { 291 cpu-map {
292 cluster0 { 292 cluster0 {
293 core0 { 293 core0 {
294 cpu = 294 cpu = <&CPU0>;
295 }; 295 };
296 296
297 core1 { 297 core1 {
298 cpu = 298 cpu = <&CPU1>;
299 }; 299 };
300 300
301 core2 { 301 core2 {
302 cpu = 302 cpu = <&CPU2>;
303 }; 303 };
304 304
305 core3 { 305 core3 {
306 cpu = 306 cpu = <&CPU3>;
307 }; 307 };
308 308
309 core4 { 309 core4 {
310 cpu = 310 cpu = <&CPU4>;
311 }; 311 };
312 312
313 core5 { 313 core5 {
314 cpu = 314 cpu = <&CPU5>;
315 }; 315 };
316 316
317 core6 { 317 core6 {
318 cpu = 318 cpu = <&CPU6>;
319 }; 319 };
320 320
321 core7 { 321 core7 {
322 cpu = 322 cpu = <&CPU7>;
323 }; 323 };
324 }; 324 };
325 }; 325 };
326 326
327 cpu_idle_states: idle-states { 327 cpu_idle_states: idle-states {
328 entry-method = "psci"; 328 entry-method = "psci";
329 329
330 LITTLE_CPU_SLEEP_0: cp 330 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 331 compatible = "arm,idle-state";
332 idle-state-nam 332 idle-state-name = "little-rail-power-collapse";
333 arm,psci-suspe 333 arm,psci-suspend-param = <0x40000004>;
334 entry-latency- 334 entry-latency-us = <350>;
335 exit-latency-u 335 exit-latency-us = <461>;
336 min-residency- 336 min-residency-us = <1890>;
337 local-timer-st 337 local-timer-stop;
338 }; 338 };
339 339
340 BIG_CPU_SLEEP_0: cpu-s 340 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 compatible = " 341 compatible = "arm,idle-state";
342 idle-state-nam 342 idle-state-name = "big-rail-power-collapse";
343 arm,psci-suspe 343 arm,psci-suspend-param = <0x40000004>;
344 entry-latency- 344 entry-latency-us = <264>;
345 exit-latency-u 345 exit-latency-us = <621>;
346 min-residency- 346 min-residency-us = <952>;
347 local-timer-st 347 local-timer-stop;
348 }; 348 };
349 }; 349 };
350 350
351 domain-idle-states { 351 domain-idle-states {
352 CLUSTER_SLEEP_0: clust 352 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " 353 compatible = "domain-idle-state";
354 arm,psci-suspe 354 arm,psci-suspend-param = <0x4100c244>;
355 entry-latency- 355 entry-latency-us = <3263>;
356 exit-latency-u 356 exit-latency-us = <6562>;
357 min-residency- 357 min-residency-us = <9987>;
358 }; 358 };
359 }; 359 };
360 }; 360 };
361 361
362 firmware { 362 firmware {
363 scm { 363 scm {
364 compatible = "qcom,scm 364 compatible = "qcom,scm-sdm845", "qcom,scm";
365 }; 365 };
366 }; 366 };
367 367
368 memory@80000000 { 368 memory@80000000 {
369 device_type = "memory"; 369 device_type = "memory";
370 /* We expect the bootloader to 370 /* We expect the bootloader to fill in the size */
371 reg = <0 0x80000000 0 0>; 371 reg = <0 0x80000000 0 0>;
372 }; 372 };
373 373
374 cpu0_opp_table: opp-table-cpu0 { 374 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points 375 compatible = "operating-points-v2";
376 opp-shared; 376 opp-shared;
377 377
378 cpu0_opp1: opp-300000000 { 378 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 379 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 380 opp-peak-kBps = <800000 4800000>;
381 }; 381 };
382 382
383 cpu0_opp2: opp-403200000 { 383 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 384 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 385 opp-peak-kBps = <800000 4800000>;
386 }; 386 };
387 387
388 cpu0_opp3: opp-480000000 { 388 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 389 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 390 opp-peak-kBps = <800000 6451200>;
391 }; 391 };
392 392
393 cpu0_opp4: opp-576000000 { 393 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 394 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 395 opp-peak-kBps = <800000 6451200>;
396 }; 396 };
397 397
398 cpu0_opp5: opp-652800000 { 398 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 399 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 400 opp-peak-kBps = <800000 7680000>;
401 }; 401 };
402 402
403 cpu0_opp6: opp-748800000 { 403 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 404 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 405 opp-peak-kBps = <1804000 9216000>;
406 }; 406 };
407 407
408 cpu0_opp7: opp-825600000 { 408 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 409 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 410 opp-peak-kBps = <1804000 9216000>;
411 }; 411 };
412 412
413 cpu0_opp8: opp-902400000 { 413 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 414 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 415 opp-peak-kBps = <1804000 10444800>;
416 }; 416 };
417 417
418 cpu0_opp9: opp-979200000 { 418 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 419 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 420 opp-peak-kBps = <1804000 11980800>;
421 }; 421 };
422 422
423 cpu0_opp10: opp-1056000000 { 423 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 424 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 425 opp-peak-kBps = <1804000 11980800>;
426 }; 426 };
427 427
428 cpu0_opp11: opp-1132800000 { 428 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 429 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 430 opp-peak-kBps = <2188000 13516800>;
431 }; 431 };
432 432
433 cpu0_opp12: opp-1228800000 { 433 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 434 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 435 opp-peak-kBps = <2188000 15052800>;
436 }; 436 };
437 437
438 cpu0_opp13: opp-1324800000 { 438 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 439 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 440 opp-peak-kBps = <2188000 16588800>;
441 }; 441 };
442 442
443 cpu0_opp14: opp-1420800000 { 443 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 444 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 445 opp-peak-kBps = <3072000 18124800>;
446 }; 446 };
447 447
448 cpu0_opp15: opp-1516800000 { 448 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 449 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 450 opp-peak-kBps = <3072000 19353600>;
451 }; 451 };
452 452
453 cpu0_opp16: opp-1612800000 { 453 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 454 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 455 opp-peak-kBps = <4068000 19353600>;
456 }; 456 };
457 457
458 cpu0_opp17: opp-1689600000 { 458 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 459 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 460 opp-peak-kBps = <4068000 20889600>;
461 }; 461 };
462 462
463 cpu0_opp18: opp-1766400000 { 463 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 464 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 465 opp-peak-kBps = <4068000 22425600>;
466 }; 466 };
467 }; 467 };
468 468
469 cpu4_opp_table: opp-table-cpu4 { 469 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 470 compatible = "operating-points-v2";
471 opp-shared; 471 opp-shared;
472 472
473 cpu4_opp1: opp-300000000 { 473 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 474 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 475 opp-peak-kBps = <800000 4800000>;
476 }; 476 };
477 477
478 cpu4_opp2: opp-403200000 { 478 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 479 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 480 opp-peak-kBps = <800000 4800000>;
481 }; 481 };
482 482
483 cpu4_opp3: opp-480000000 { 483 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 484 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 485 opp-peak-kBps = <1804000 4800000>;
486 }; 486 };
487 487
488 cpu4_opp4: opp-576000000 { 488 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 489 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 490 opp-peak-kBps = <1804000 4800000>;
491 }; 491 };
492 492
493 cpu4_opp5: opp-652800000 { 493 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 494 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 495 opp-peak-kBps = <1804000 4800000>;
496 }; 496 };
497 497
498 cpu4_opp6: opp-748800000 { 498 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 499 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 500 opp-peak-kBps = <1804000 4800000>;
501 }; 501 };
502 502
503 cpu4_opp7: opp-825600000 { 503 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 504 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 505 opp-peak-kBps = <2188000 9216000>;
506 }; 506 };
507 507
508 cpu4_opp8: opp-902400000 { 508 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 509 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 510 opp-peak-kBps = <2188000 9216000>;
511 }; 511 };
512 512
513 cpu4_opp9: opp-979200000 { 513 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 514 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 515 opp-peak-kBps = <2188000 9216000>;
516 }; 516 };
517 517
518 cpu4_opp10: opp-1056000000 { 518 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 519 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 520 opp-peak-kBps = <3072000 9216000>;
521 }; 521 };
522 522
523 cpu4_opp11: opp-1132800000 { 523 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 524 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 525 opp-peak-kBps = <3072000 11980800>;
526 }; 526 };
527 527
528 cpu4_opp12: opp-1209600000 { 528 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 529 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 530 opp-peak-kBps = <4068000 11980800>;
531 }; 531 };
532 532
533 cpu4_opp13: opp-1286400000 { 533 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 534 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 535 opp-peak-kBps = <4068000 11980800>;
536 }; 536 };
537 537
538 cpu4_opp14: opp-1363200000 { 538 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 539 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 540 opp-peak-kBps = <4068000 15052800>;
541 }; 541 };
542 542
543 cpu4_opp15: opp-1459200000 { 543 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 544 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 545 opp-peak-kBps = <4068000 15052800>;
546 }; 546 };
547 547
548 cpu4_opp16: opp-1536000000 { 548 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 549 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 550 opp-peak-kBps = <5412000 15052800>;
551 }; 551 };
552 552
553 cpu4_opp17: opp-1612800000 { 553 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 554 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 555 opp-peak-kBps = <5412000 15052800>;
556 }; 556 };
557 557
558 cpu4_opp18: opp-1689600000 { 558 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 559 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 560 opp-peak-kBps = <5412000 19353600>;
561 }; 561 };
562 562
563 cpu4_opp19: opp-1766400000 { 563 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 564 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 565 opp-peak-kBps = <6220000 19353600>;
566 }; 566 };
567 567
568 cpu4_opp20: opp-1843200000 { 568 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 569 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 570 opp-peak-kBps = <6220000 19353600>;
571 }; 571 };
572 572
573 cpu4_opp21: opp-1920000000 { 573 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 574 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 575 opp-peak-kBps = <7216000 19353600>;
576 }; 576 };
577 577
578 cpu4_opp22: opp-1996800000 { 578 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 579 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 580 opp-peak-kBps = <7216000 20889600>;
581 }; 581 };
582 582
583 cpu4_opp23: opp-2092800000 { 583 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 584 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 585 opp-peak-kBps = <7216000 20889600>;
586 }; 586 };
587 587
588 cpu4_opp24: opp-2169600000 { 588 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 589 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 590 opp-peak-kBps = <7216000 20889600>;
591 }; 591 };
592 592
593 cpu4_opp25: opp-2246400000 { 593 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 594 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 595 opp-peak-kBps = <7216000 20889600>;
596 }; 596 };
597 597
598 cpu4_opp26: opp-2323200000 { 598 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 599 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 600 opp-peak-kBps = <7216000 20889600>;
601 }; 601 };
602 602
603 cpu4_opp27: opp-2400000000 { 603 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 604 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 605 opp-peak-kBps = <7216000 22425600>;
606 }; 606 };
607 607
608 cpu4_opp28: opp-2476800000 { 608 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 609 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 610 opp-peak-kBps = <7216000 22425600>;
611 }; 611 };
612 612
613 cpu4_opp29: opp-2553600000 { 613 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 614 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 615 opp-peak-kBps = <7216000 22425600>;
616 }; 616 };
617 617
618 cpu4_opp30: opp-2649600000 { 618 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 619 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 620 opp-peak-kBps = <7216000 22425600>;
621 }; 621 };
622 622
623 cpu4_opp31: opp-2745600000 { 623 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 624 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 625 opp-peak-kBps = <7216000 25497600>;
626 }; 626 };
627 627
628 cpu4_opp32: opp-2803200000 { 628 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 629 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 630 opp-peak-kBps = <7216000 25497600>;
631 }; 631 };
632 }; 632 };
633 633
634 dsi_opp_table: opp-table-dsi { 634 dsi_opp_table: opp-table-dsi {
635 compatible = "operating-points 635 compatible = "operating-points-v2";
636 636
637 opp-19200000 { 637 opp-19200000 {
638 opp-hz = /bits/ 64 <19 638 opp-hz = /bits/ 64 <19200000>;
639 required-opps = <&rpmh 639 required-opps = <&rpmhpd_opp_min_svs>;
640 }; 640 };
641 641
642 opp-180000000 { 642 opp-180000000 {
643 opp-hz = /bits/ 64 <18 643 opp-hz = /bits/ 64 <180000000>;
644 required-opps = <&rpmh 644 required-opps = <&rpmhpd_opp_low_svs>;
645 }; 645 };
646 646
647 opp-275000000 { 647 opp-275000000 {
648 opp-hz = /bits/ 64 <27 648 opp-hz = /bits/ 64 <275000000>;
649 required-opps = <&rpmh 649 required-opps = <&rpmhpd_opp_svs>;
650 }; 650 };
651 651
652 opp-328580000 { 652 opp-328580000 {
653 opp-hz = /bits/ 64 <32 653 opp-hz = /bits/ 64 <328580000>;
654 required-opps = <&rpmh 654 required-opps = <&rpmhpd_opp_svs_l1>;
655 }; 655 };
656 656
657 opp-358000000 { 657 opp-358000000 {
658 opp-hz = /bits/ 64 <35 658 opp-hz = /bits/ 64 <358000000>;
659 required-opps = <&rpmh 659 required-opps = <&rpmhpd_opp_nom>;
660 }; 660 };
661 }; 661 };
662 662
663 qspi_opp_table: opp-table-qspi { 663 qspi_opp_table: opp-table-qspi {
664 compatible = "operating-points 664 compatible = "operating-points-v2";
665 665
666 opp-19200000 { 666 opp-19200000 {
667 opp-hz = /bits/ 64 <19 667 opp-hz = /bits/ 64 <19200000>;
668 required-opps = <&rpmh 668 required-opps = <&rpmhpd_opp_min_svs>;
669 }; 669 };
670 670
671 opp-100000000 { 671 opp-100000000 {
672 opp-hz = /bits/ 64 <10 672 opp-hz = /bits/ 64 <100000000>;
673 required-opps = <&rpmh 673 required-opps = <&rpmhpd_opp_low_svs>;
674 }; 674 };
675 675
676 opp-150000000 { 676 opp-150000000 {
677 opp-hz = /bits/ 64 <15 677 opp-hz = /bits/ 64 <150000000>;
678 required-opps = <&rpmh 678 required-opps = <&rpmhpd_opp_svs>;
679 }; 679 };
680 680
681 opp-300000000 { 681 opp-300000000 {
682 opp-hz = /bits/ 64 <30 682 opp-hz = /bits/ 64 <300000000>;
683 required-opps = <&rpmh 683 required-opps = <&rpmhpd_opp_nom>;
684 }; 684 };
685 }; 685 };
686 686
687 qup_opp_table: opp-table-qup { 687 qup_opp_table: opp-table-qup {
688 compatible = "operating-points 688 compatible = "operating-points-v2";
689 689
690 opp-50000000 { 690 opp-50000000 {
691 opp-hz = /bits/ 64 <50 691 opp-hz = /bits/ 64 <50000000>;
692 required-opps = <&rpmh 692 required-opps = <&rpmhpd_opp_min_svs>;
693 }; 693 };
694 694
695 opp-75000000 { 695 opp-75000000 {
696 opp-hz = /bits/ 64 <75 696 opp-hz = /bits/ 64 <75000000>;
697 required-opps = <&rpmh 697 required-opps = <&rpmhpd_opp_low_svs>;
698 }; 698 };
699 699
700 opp-100000000 { 700 opp-100000000 {
701 opp-hz = /bits/ 64 <10 701 opp-hz = /bits/ 64 <100000000>;
702 required-opps = <&rpmh 702 required-opps = <&rpmhpd_opp_svs>;
703 }; 703 };
704 704
705 opp-128000000 { 705 opp-128000000 {
706 opp-hz = /bits/ 64 <12 706 opp-hz = /bits/ 64 <128000000>;
707 required-opps = <&rpmh 707 required-opps = <&rpmhpd_opp_nom>;
708 }; 708 };
709 }; 709 };
710 710
711 pmu { 711 pmu {
712 compatible = "arm,armv8-pmuv3" 712 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 713 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 714 };
715 715
716 psci: psci { 716 psci: psci {
717 compatible = "arm,psci-1.0"; 717 compatible = "arm,psci-1.0";
718 method = "smc"; 718 method = "smc";
719 719
720 CPU_PD0: power-domain-cpu0 { 720 CPU_PD0: power-domain-cpu0 {
721 #power-domain-cells = 721 #power-domain-cells = <0>;
722 power-domains = <&CLUS 722 power-domains = <&CLUSTER_PD>;
723 domain-idle-states = < 723 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
724 }; 724 };
725 725
726 CPU_PD1: power-domain-cpu1 { 726 CPU_PD1: power-domain-cpu1 {
727 #power-domain-cells = 727 #power-domain-cells = <0>;
728 power-domains = <&CLUS 728 power-domains = <&CLUSTER_PD>;
729 domain-idle-states = < 729 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
730 }; 730 };
731 731
732 CPU_PD2: power-domain-cpu2 { 732 CPU_PD2: power-domain-cpu2 {
733 #power-domain-cells = 733 #power-domain-cells = <0>;
734 power-domains = <&CLUS 734 power-domains = <&CLUSTER_PD>;
735 domain-idle-states = < 735 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
736 }; 736 };
737 737
738 CPU_PD3: power-domain-cpu3 { 738 CPU_PD3: power-domain-cpu3 {
739 #power-domain-cells = 739 #power-domain-cells = <0>;
740 power-domains = <&CLUS 740 power-domains = <&CLUSTER_PD>;
741 domain-idle-states = < 741 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
742 }; 742 };
743 743
744 CPU_PD4: power-domain-cpu4 { 744 CPU_PD4: power-domain-cpu4 {
745 #power-domain-cells = 745 #power-domain-cells = <0>;
746 power-domains = <&CLUS 746 power-domains = <&CLUSTER_PD>;
747 domain-idle-states = < 747 domain-idle-states = <&BIG_CPU_SLEEP_0>;
748 }; 748 };
749 749
750 CPU_PD5: power-domain-cpu5 { 750 CPU_PD5: power-domain-cpu5 {
751 #power-domain-cells = 751 #power-domain-cells = <0>;
752 power-domains = <&CLUS 752 power-domains = <&CLUSTER_PD>;
753 domain-idle-states = < 753 domain-idle-states = <&BIG_CPU_SLEEP_0>;
754 }; 754 };
755 755
756 CPU_PD6: power-domain-cpu6 { 756 CPU_PD6: power-domain-cpu6 {
757 #power-domain-cells = 757 #power-domain-cells = <0>;
758 power-domains = <&CLUS 758 power-domains = <&CLUSTER_PD>;
759 domain-idle-states = < 759 domain-idle-states = <&BIG_CPU_SLEEP_0>;
760 }; 760 };
761 761
762 CPU_PD7: power-domain-cpu7 { 762 CPU_PD7: power-domain-cpu7 {
763 #power-domain-cells = 763 #power-domain-cells = <0>;
764 power-domains = <&CLUS 764 power-domains = <&CLUSTER_PD>;
765 domain-idle-states = < 765 domain-idle-states = <&BIG_CPU_SLEEP_0>;
766 }; 766 };
767 767
768 CLUSTER_PD: power-domain-clust 768 CLUSTER_PD: power-domain-cluster {
769 #power-domain-cells = 769 #power-domain-cells = <0>;
770 domain-idle-states = < 770 domain-idle-states = <&CLUSTER_SLEEP_0>;
771 }; 771 };
772 }; 772 };
773 773
774 reserved-memory { 774 reserved-memory {
775 #address-cells = <2>; 775 #address-cells = <2>;
776 #size-cells = <2>; 776 #size-cells = <2>;
777 ranges; 777 ranges;
778 778
779 hyp_mem: hyp-mem@85700000 { 779 hyp_mem: hyp-mem@85700000 {
780 reg = <0 0x85700000 0 780 reg = <0 0x85700000 0 0x600000>;
781 no-map; 781 no-map;
782 }; 782 };
783 783
784 xbl_mem: xbl-mem@85e00000 { 784 xbl_mem: xbl-mem@85e00000 {
785 reg = <0 0x85e00000 0 785 reg = <0 0x85e00000 0 0x100000>;
786 no-map; 786 no-map;
787 }; 787 };
788 788
789 aop_mem: aop-mem@85fc0000 { 789 aop_mem: aop-mem@85fc0000 {
790 reg = <0 0x85fc0000 0 790 reg = <0 0x85fc0000 0 0x20000>;
791 no-map; 791 no-map;
792 }; 792 };
793 793
794 aop_cmd_db_mem: aop-cmd-db-mem 794 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
795 compatible = "qcom,cmd 795 compatible = "qcom,cmd-db";
796 reg = <0x0 0x85fe0000 796 reg = <0x0 0x85fe0000 0 0x20000>;
797 no-map; 797 no-map;
798 }; 798 };
799 799
800 smem@86000000 { 800 smem@86000000 {
801 compatible = "qcom,sme 801 compatible = "qcom,smem";
802 reg = <0x0 0x86000000 802 reg = <0x0 0x86000000 0 0x200000>;
803 no-map; 803 no-map;
804 hwlocks = <&tcsr_mutex 804 hwlocks = <&tcsr_mutex 3>;
805 }; 805 };
806 806
807 tz_mem: tz@86200000 { 807 tz_mem: tz@86200000 {
808 reg = <0 0x86200000 0 808 reg = <0 0x86200000 0 0x2d00000>;
809 no-map; 809 no-map;
810 }; 810 };
811 811
812 rmtfs_mem: rmtfs@88f00000 { 812 rmtfs_mem: rmtfs@88f00000 {
813 compatible = "qcom,rmt 813 compatible = "qcom,rmtfs-mem";
814 reg = <0 0x88f00000 0 814 reg = <0 0x88f00000 0 0x200000>;
815 no-map; 815 no-map;
816 816
817 qcom,client-id = <1>; 817 qcom,client-id = <1>;
818 qcom,vmid = <QCOM_SCM_ 818 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
819 }; 819 };
820 820
821 qseecom_mem: qseecom@8ab00000 821 qseecom_mem: qseecom@8ab00000 {
822 reg = <0 0x8ab00000 0 822 reg = <0 0x8ab00000 0 0x1400000>;
823 no-map; 823 no-map;
824 }; 824 };
825 825
826 camera_mem: camera-mem@8bf0000 826 camera_mem: camera-mem@8bf00000 {
827 reg = <0 0x8bf00000 0 827 reg = <0 0x8bf00000 0 0x500000>;
828 no-map; 828 no-map;
829 }; 829 };
830 830
831 ipa_fw_mem: ipa-fw@8c400000 { 831 ipa_fw_mem: ipa-fw@8c400000 {
832 reg = <0 0x8c400000 0 832 reg = <0 0x8c400000 0 0x10000>;
833 no-map; 833 no-map;
834 }; 834 };
835 835
836 ipa_gsi_mem: ipa-gsi@8c410000 836 ipa_gsi_mem: ipa-gsi@8c410000 {
837 reg = <0 0x8c410000 0 837 reg = <0 0x8c410000 0 0x5000>;
838 no-map; 838 no-map;
839 }; 839 };
840 840
841 gpu_mem: gpu@8c415000 { 841 gpu_mem: gpu@8c415000 {
842 reg = <0 0x8c415000 0 842 reg = <0 0x8c415000 0 0x2000>;
843 no-map; 843 no-map;
844 }; 844 };
845 845
846 adsp_mem: adsp@8c500000 { 846 adsp_mem: adsp@8c500000 {
847 reg = <0 0x8c500000 0 847 reg = <0 0x8c500000 0 0x1a00000>;
848 no-map; 848 no-map;
849 }; 849 };
850 850
851 wlan_msa_mem: wlan-msa@8df0000 851 wlan_msa_mem: wlan-msa@8df00000 {
852 reg = <0 0x8df00000 0 852 reg = <0 0x8df00000 0 0x100000>;
853 no-map; 853 no-map;
854 }; 854 };
855 855
856 mpss_region: mpss@8e000000 { 856 mpss_region: mpss@8e000000 {
857 reg = <0 0x8e000000 0 857 reg = <0 0x8e000000 0 0x7800000>;
858 no-map; 858 no-map;
859 }; 859 };
860 860
861 venus_mem: venus@95800000 { 861 venus_mem: venus@95800000 {
862 reg = <0 0x95800000 0 862 reg = <0 0x95800000 0 0x500000>;
863 no-map; 863 no-map;
864 }; 864 };
865 865
866 cdsp_mem: cdsp@95d00000 { 866 cdsp_mem: cdsp@95d00000 {
867 reg = <0 0x95d00000 0 867 reg = <0 0x95d00000 0 0x800000>;
868 no-map; 868 no-map;
869 }; 869 };
870 870
871 mba_region: mba@96500000 { 871 mba_region: mba@96500000 {
872 reg = <0 0x96500000 0 872 reg = <0 0x96500000 0 0x200000>;
873 no-map; 873 no-map;
874 }; 874 };
875 875
876 slpi_mem: slpi@96700000 { 876 slpi_mem: slpi@96700000 {
877 reg = <0 0x96700000 0 877 reg = <0 0x96700000 0 0x1400000>;
878 no-map; 878 no-map;
879 }; 879 };
880 880
881 spss_mem: spss@97b00000 { 881 spss_mem: spss@97b00000 {
882 reg = <0 0x97b00000 0 882 reg = <0 0x97b00000 0 0x100000>;
883 no-map; 883 no-map;
884 }; 884 };
885 885
886 mdata_mem: mpss-metadata { 886 mdata_mem: mpss-metadata {
887 alloc-ranges = <0 0xa0 887 alloc-ranges = <0 0xa0000000 0 0x20000000>;
888 size = <0 0x4000>; 888 size = <0 0x4000>;
889 no-map; 889 no-map;
890 }; 890 };
891 891
892 fastrpc_mem: fastrpc { 892 fastrpc_mem: fastrpc {
893 compatible = "shared-d 893 compatible = "shared-dma-pool";
894 alloc-ranges = <0x0 0x 894 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
895 alignment = <0x0 0x400 895 alignment = <0x0 0x400000>;
896 size = <0x0 0x1000000> 896 size = <0x0 0x1000000>;
897 reusable; 897 reusable;
898 }; 898 };
899 }; 899 };
900 900
901 adsp_pas: remoteproc-adsp { 901 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 902 compatible = "qcom,sdm845-adsp-pas";
903 903
904 interrupts-extended = <&intc G 904 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 905 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 906 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 907 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 908 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 909 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 910 "handover", "stop-ack";
911 911
912 clocks = <&rpmhcc RPMH_CXO_CLK 912 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 913 clock-names = "xo";
914 914
915 memory-region = <&adsp_mem>; 915 memory-region = <&adsp_mem>;
916 916
917 qcom,qmp = <&aoss_qmp>; 917 qcom,qmp = <&aoss_qmp>;
918 918
919 qcom,smem-states = <&adsp_smp2 919 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 920 qcom,smem-state-names = "stop";
921 921
922 status = "disabled"; 922 status = "disabled";
923 923
924 glink-edge { 924 glink-edge {
925 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 926 label = "lpass";
927 qcom,remote-pid = <2>; 927 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 928 mboxes = <&apss_shared 8>;
929 929
930 apr { 930 apr {
931 compatible = " 931 compatible = "qcom,apr-v2";
932 qcom,glink-cha 932 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = 933 qcom,domain = <APR_DOMAIN_ADSP>;
934 #address-cells 934 #address-cells = <1>;
935 #size-cells = 935 #size-cells = <0>;
936 qcom,intents = 936 qcom,intents = <512 20>;
937 937
938 service@3 { 938 service@3 {
939 reg = 939 reg = <APR_SVC_ADSP_CORE>;
940 compat 940 compatible = "qcom,q6core";
941 qcom,p 941 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 942 };
943 943
944 q6afe: service 944 q6afe: service@4 {
945 compat 945 compatible = "qcom,q6afe";
946 reg = 946 reg = <APR_SVC_AFE>;
947 qcom,p 947 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 948 q6afedai: dais {
949 949 compatible = "qcom,q6afe-dais";
950 950 #address-cells = <1>;
951 951 #size-cells = <0>;
952 952 #sound-dai-cells = <1>;
953 }; 953 };
954 }; 954 };
955 955
956 q6asm: service 956 q6asm: service@7 {
957 compat 957 compatible = "qcom,q6asm";
958 reg = 958 reg = <APR_SVC_ASM>;
959 qcom,p 959 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 960 q6asmdai: dais {
961 961 compatible = "qcom,q6asm-dais";
962 962 #address-cells = <1>;
963 963 #size-cells = <0>;
964 964 #sound-dai-cells = <1>;
965 965 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 966 };
967 }; 967 };
968 968
969 q6adm: service 969 q6adm: service@8 {
970 compat 970 compatible = "qcom,q6adm";
971 reg = 971 reg = <APR_SVC_ADM>;
972 qcom,p 972 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 973 q6routing: routing {
974 974 compatible = "qcom,q6adm-routing";
975 975 #sound-dai-cells = <0>;
976 }; 976 };
977 }; 977 };
978 }; 978 };
979 979
980 fastrpc { 980 fastrpc {
981 compatible = " 981 compatible = "qcom,fastrpc";
982 qcom,glink-cha 982 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 983 label = "adsp";
984 qcom,non-secur 984 qcom,non-secure-domain;
985 #address-cells 985 #address-cells = <1>;
986 #size-cells = 986 #size-cells = <0>;
987 987
988 compute-cb@3 { 988 compute-cb@3 {
989 compat 989 compatible = "qcom,fastrpc-compute-cb";
990 reg = 990 reg = <3>;
991 iommus 991 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 992 };
993 993
994 compute-cb@4 { 994 compute-cb@4 {
995 compat 995 compatible = "qcom,fastrpc-compute-cb";
996 reg = 996 reg = <4>;
997 iommus 997 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 998 };
999 }; 999 };
1000 }; 1000 };
1001 }; 1001 };
1002 1002
1003 cdsp_pas: remoteproc-cdsp { 1003 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 1004 compatible = "qcom,sdm845-cdsp-pas";
1005 1005
1006 interrupts-extended = <&intc 1006 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 1007 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 1008 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 1009 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 1010 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 1011 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 1012 "handover", "stop-ack";
1013 1013
1014 clocks = <&rpmhcc RPMH_CXO_CL 1014 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 1015 clock-names = "xo";
1016 1016
1017 memory-region = <&cdsp_mem>; 1017 memory-region = <&cdsp_mem>;
1018 1018
1019 qcom,qmp = <&aoss_qmp>; 1019 qcom,qmp = <&aoss_qmp>;
1020 1020
1021 qcom,smem-states = <&cdsp_smp 1021 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 1022 qcom,smem-state-names = "stop";
1023 1023
1024 status = "disabled"; 1024 status = "disabled";
1025 1025
1026 glink-edge { 1026 glink-edge {
1027 interrupts = <GIC_SPI 1027 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 1028 label = "turing";
1029 qcom,remote-pid = <5> 1029 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 1030 mboxes = <&apss_shared 4>;
1031 fastrpc { 1031 fastrpc {
1032 compatible = 1032 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 1033 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 1034 label = "cdsp";
1035 qcom,non-secu 1035 qcom,non-secure-domain;
1036 #address-cell 1036 #address-cells = <1>;
1037 #size-cells = 1037 #size-cells = <0>;
1038 1038
1039 compute-cb@1 1039 compute-cb@1 {
1040 compa 1040 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 1041 reg = <1>;
1042 iommu 1042 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 1043 };
1044 1044
1045 compute-cb@2 1045 compute-cb@2 {
1046 compa 1046 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 1047 reg = <2>;
1048 iommu 1048 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 1049 };
1050 1050
1051 compute-cb@3 1051 compute-cb@3 {
1052 compa 1052 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 1053 reg = <3>;
1054 iommu 1054 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 1055 };
1056 1056
1057 compute-cb@4 1057 compute-cb@4 {
1058 compa 1058 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 1059 reg = <4>;
1060 iommu 1060 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 1061 };
1062 1062
1063 compute-cb@5 1063 compute-cb@5 {
1064 compa 1064 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 1065 reg = <5>;
1066 iommu 1066 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 1067 };
1068 1068
1069 compute-cb@6 1069 compute-cb@6 {
1070 compa 1070 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 1071 reg = <6>;
1072 iommu 1072 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 1073 };
1074 1074
1075 compute-cb@7 1075 compute-cb@7 {
1076 compa 1076 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 1077 reg = <7>;
1078 iommu 1078 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 1079 };
1080 1080
1081 compute-cb@8 1081 compute-cb@8 {
1082 compa 1082 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 1083 reg = <8>;
1084 iommu 1084 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 1085 };
1086 }; 1086 };
1087 }; 1087 };
1088 }; 1088 };
1089 1089
1090 smp2p-cdsp { 1090 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 1091 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 1092 qcom,smem = <94>, <432>;
1093 1093
1094 interrupts = <GIC_SPI 576 IRQ 1094 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 1095
1096 mboxes = <&apss_shared 6>; 1096 mboxes = <&apss_shared 6>;
1097 1097
1098 qcom,local-pid = <0>; 1098 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 1099 qcom,remote-pid = <5>;
1100 1100
1101 cdsp_smp2p_out: master-kernel 1101 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 1102 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 1103 #qcom,smem-state-cells = <1>;
1104 }; 1104 };
1105 1105
1106 cdsp_smp2p_in: slave-kernel { 1106 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 1107 qcom,entry-name = "slave-kernel";
1108 1108
1109 interrupt-controller; 1109 interrupt-controller;
1110 #interrupt-cells = <2 1110 #interrupt-cells = <2>;
1111 }; 1111 };
1112 }; 1112 };
1113 1113
1114 smp2p-lpass { 1114 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 1115 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 1116 qcom,smem = <443>, <429>;
1117 1117
1118 interrupts = <GIC_SPI 158 IRQ 1118 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 1119
1120 mboxes = <&apss_shared 10>; 1120 mboxes = <&apss_shared 10>;
1121 1121
1122 qcom,local-pid = <0>; 1122 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 1123 qcom,remote-pid = <2>;
1124 1124
1125 adsp_smp2p_out: master-kernel 1125 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 1126 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 1127 #qcom,smem-state-cells = <1>;
1128 }; 1128 };
1129 1129
1130 adsp_smp2p_in: slave-kernel { 1130 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 1131 qcom,entry-name = "slave-kernel";
1132 1132
1133 interrupt-controller; 1133 interrupt-controller;
1134 #interrupt-cells = <2 1134 #interrupt-cells = <2>;
1135 }; 1135 };
1136 }; 1136 };
1137 1137
1138 smp2p-mpss { 1138 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 1139 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 1140 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 1141 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 1142 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 1143 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 1144 qcom,remote-pid = <1>;
1145 1145
1146 modem_smp2p_out: master-kerne 1146 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 1147 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 1148 #qcom,smem-state-cells = <1>;
1149 }; 1149 };
1150 1150
1151 modem_smp2p_in: slave-kernel 1151 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 1152 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 1153 interrupt-controller;
1154 #interrupt-cells = <2 1154 #interrupt-cells = <2>;
1155 }; 1155 };
1156 1156
1157 ipa_smp2p_out: ipa-ap-to-mode 1157 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 1158 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 1159 #qcom,smem-state-cells = <1>;
1160 }; 1160 };
1161 1161
1162 ipa_smp2p_in: ipa-modem-to-ap 1162 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1163 qcom,entry-name = "ipa";
1164 interrupt-controller; 1164 interrupt-controller;
1165 #interrupt-cells = <2 1165 #interrupt-cells = <2>;
1166 }; 1166 };
1167 }; 1167 };
1168 1168
1169 smp2p-slpi { 1169 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1170 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1171 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1172 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1173 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1174 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1175 qcom,remote-pid = <3>;
1176 1176
1177 slpi_smp2p_out: master-kernel 1177 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1178 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1179 #qcom,smem-state-cells = <1>;
1180 }; 1180 };
1181 1181
1182 slpi_smp2p_in: slave-kernel { 1182 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1183 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1184 interrupt-controller;
1185 #interrupt-cells = <2 1185 #interrupt-cells = <2>;
1186 }; 1186 };
1187 }; 1187 };
1188 1188
1189 soc: soc@0 { 1189 soc: soc@0 {
1190 #address-cells = <2>; 1190 #address-cells = <2>;
1191 #size-cells = <2>; 1191 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1192 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1193 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1194 compatible = "simple-bus";
1195 1195
1196 gcc: clock-controller@100000 1196 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1197 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1198 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1199 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1200 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1201 <&sleep_clk>,
1202 <&pcie0_phy> 1202 <&pcie0_phy>,
1203 <&pcie1_phy> 1203 <&pcie1_phy>;
1204 clock-names = "bi_tcx 1204 clock-names = "bi_tcxo",
1205 "bi_tcx 1205 "bi_tcxo_ao",
1206 "sleep_ 1206 "sleep_clk",
1207 "pcie_0 1207 "pcie_0_pipe_clk",
1208 "pcie_1 1208 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1209 #clock-cells = <1>;
1210 #reset-cells = <1>; 1210 #reset-cells = <1>;
1211 #power-domain-cells = 1211 #power-domain-cells = <1>;
1212 power-domains = <&rpm 1212 power-domains = <&rpmhpd SDM845_CX>;
1213 }; 1213 };
1214 1214
1215 qfprom@784000 { 1215 qfprom@784000 {
1216 compatible = "qcom,sd 1216 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 reg = <0 0x00784000 0 1217 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1218 #address-cells = <1>;
1219 #size-cells = <1>; 1219 #size-cells = <1>;
1220 1220
1221 qusb2p_hstx_trim: hst 1221 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1222 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1223 bits = <1 4>;
1224 }; 1224 };
1225 1225
1226 qusb2s_hstx_trim: hst 1226 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1227 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1228 bits = <6 4>;
1229 }; 1229 };
1230 }; 1230 };
1231 1231
1232 rng: rng@793000 { 1232 rng: rng@793000 {
1233 compatible = "qcom,pr 1233 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1234 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1235 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1236 clock-names = "core";
1237 }; 1237 };
1238 1238
1239 gpi_dma0: dma-controller@8000 1239 gpi_dma0: dma-controller@800000 {
1240 #dma-cells = <3>; 1240 #dma-cells = <3>;
1241 compatible = "qcom,sd 1241 compatible = "qcom,sdm845-gpi-dma";
1242 reg = <0 0x00800000 0 1242 reg = <0 0x00800000 0 0x60000>;
1243 interrupts = <GIC_SPI 1243 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 1244 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 1245 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 1246 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 1247 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 1248 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 1249 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 1250 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 1251 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 1252 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 1253 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 1254 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 1255 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256 dma-channels = <13>; 1256 dma-channels = <13>;
1257 dma-channel-mask = <0 1257 dma-channel-mask = <0xfa>;
1258 iommus = <&apps_smmu 1258 iommus = <&apps_smmu 0x0016 0x0>;
1259 status = "disabled"; 1259 status = "disabled";
1260 }; 1260 };
1261 1261
1262 qupv3_id_0: geniqup@8c0000 { 1262 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1263 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1264 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1265 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1266 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1267 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1268 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1269 #address-cells = <2>;
1270 #size-cells = <2>; 1270 #size-cells = <2>;
1271 ranges; 1271 ranges;
1272 interconnects = <&agg 1272 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1273 interconnect-names = "qup-core";
1274 status = "disabled"; 1274 status = "disabled";
1275 1275
1276 i2c0: i2c@880000 { 1276 i2c0: i2c@880000 {
1277 compatible = 1277 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1278 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1279 clock-names = "se";
1280 clocks = <&gc 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1281 pinctrl-names = "default";
1282 pinctrl-0 = < 1282 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1283 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1284 #address-cells = <1>;
1285 #size-cells = 1285 #size-cells = <0>;
1286 power-domains 1286 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1287 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1288 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1289 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1290 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1291 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ 1292 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293 <&gpi_ 1293 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1294 dma-names = " 1294 dma-names = "tx", "rx";
1295 status = "dis 1295 status = "disabled";
1296 }; 1296 };
1297 1297
1298 spi0: spi@880000 { 1298 spi0: spi@880000 {
1299 compatible = 1299 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1300 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1301 clock-names = "se";
1302 clocks = <&gc 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1303 pinctrl-names = "default";
1304 pinctrl-0 = < 1304 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1305 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1306 #address-cells = <1>;
1307 #size-cells = 1307 #size-cells = <0>;
1308 interconnects 1308 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1309 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1310 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ 1311 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_ 1312 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313 dma-names = " 1313 dma-names = "tx", "rx";
1314 status = "dis 1314 status = "disabled";
1315 }; 1315 };
1316 1316
1317 uart0: serial@880000 1317 uart0: serial@880000 {
1318 compatible = 1318 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1319 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1320 clock-names = "se";
1321 clocks = <&gc 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1322 pinctrl-names = "default";
1323 pinctrl-0 = < 1323 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1324 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1325 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1326 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1327 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1328 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1329 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1330 status = "disabled";
1331 }; 1331 };
1332 1332
1333 i2c1: i2c@884000 { 1333 i2c1: i2c@884000 {
1334 compatible = 1334 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1335 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1336 clock-names = "se";
1337 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1338 pinctrl-names = "default";
1339 pinctrl-0 = < 1339 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1340 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1341 #address-cells = <1>;
1342 #size-cells = 1342 #size-cells = <0>;
1343 power-domains 1343 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1344 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1345 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1346 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1347 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1348 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ 1349 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1350 <&gpi_ 1350 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1351 dma-names = " 1351 dma-names = "tx", "rx";
1352 status = "dis 1352 status = "disabled";
1353 }; 1353 };
1354 1354
1355 spi1: spi@884000 { 1355 spi1: spi@884000 {
1356 compatible = 1356 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1357 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1358 clock-names = "se";
1359 clocks = <&gc 1359 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1360 pinctrl-names = "default";
1361 pinctrl-0 = < 1361 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1362 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1363 #address-cells = <1>;
1364 #size-cells = 1364 #size-cells = <0>;
1365 interconnects 1365 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1366 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1367 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ 1368 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1369 <&gpi_ 1369 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1370 dma-names = " 1370 dma-names = "tx", "rx";
1371 status = "dis 1371 status = "disabled";
1372 }; 1372 };
1373 1373
1374 uart1: serial@884000 1374 uart1: serial@884000 {
1375 compatible = 1375 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1376 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1377 clock-names = "se";
1378 clocks = <&gc 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1379 pinctrl-names = "default";
1380 pinctrl-0 = < 1380 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1381 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1382 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1383 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1384 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1385 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1386 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1387 status = "disabled";
1388 }; 1388 };
1389 1389
1390 i2c2: i2c@888000 { 1390 i2c2: i2c@888000 {
1391 compatible = 1391 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1392 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1393 clock-names = "se";
1394 clocks = <&gc 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1395 pinctrl-names = "default";
1396 pinctrl-0 = < 1396 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1397 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1398 #address-cells = <1>;
1399 #size-cells = 1399 #size-cells = <0>;
1400 power-domains 1400 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1401 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1402 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1403 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1404 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1405 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ 1406 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1407 <&gpi_ 1407 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1408 dma-names = " 1408 dma-names = "tx", "rx";
1409 status = "dis 1409 status = "disabled";
1410 }; 1410 };
1411 1411
1412 spi2: spi@888000 { 1412 spi2: spi@888000 {
1413 compatible = 1413 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1414 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1415 clock-names = "se";
1416 clocks = <&gc 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1417 pinctrl-names = "default";
1418 pinctrl-0 = < 1418 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1419 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1420 #address-cells = <1>;
1421 #size-cells = 1421 #size-cells = <0>;
1422 interconnects 1422 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1423 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1424 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ 1425 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1426 <&gpi_ 1426 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1427 dma-names = " 1427 dma-names = "tx", "rx";
1428 status = "dis 1428 status = "disabled";
1429 }; 1429 };
1430 1430
1431 uart2: serial@888000 1431 uart2: serial@888000 {
1432 compatible = 1432 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1433 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1434 clock-names = "se";
1435 clocks = <&gc 1435 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1436 pinctrl-names = "default";
1437 pinctrl-0 = < 1437 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1438 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1439 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1440 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1441 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1442 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1443 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1444 status = "disabled";
1445 }; 1445 };
1446 1446
1447 i2c3: i2c@88c000 { 1447 i2c3: i2c@88c000 {
1448 compatible = 1448 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1449 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1450 clock-names = "se";
1451 clocks = <&gc 1451 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1452 pinctrl-names = "default";
1453 pinctrl-0 = < 1453 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1454 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1455 #address-cells = <1>;
1456 #size-cells = 1456 #size-cells = <0>;
1457 power-domains 1457 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1458 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1459 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1460 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1461 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1462 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ 1463 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1464 <&gpi_ 1464 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1465 dma-names = " 1465 dma-names = "tx", "rx";
1466 status = "dis 1466 status = "disabled";
1467 }; 1467 };
1468 1468
1469 spi3: spi@88c000 { 1469 spi3: spi@88c000 {
1470 compatible = 1470 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1471 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1472 clock-names = "se";
1473 clocks = <&gc 1473 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1474 pinctrl-names = "default";
1475 pinctrl-0 = < 1475 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1476 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1477 #address-cells = <1>;
1478 #size-cells = 1478 #size-cells = <0>;
1479 interconnects 1479 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1480 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1481 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ 1482 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1483 <&gpi_ 1483 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1484 dma-names = " 1484 dma-names = "tx", "rx";
1485 status = "dis 1485 status = "disabled";
1486 }; 1486 };
1487 1487
1488 uart3: serial@88c000 1488 uart3: serial@88c000 {
1489 compatible = 1489 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1490 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1491 clock-names = "se";
1492 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1493 pinctrl-names = "default";
1494 pinctrl-0 = < 1494 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1495 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1496 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1497 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1498 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1499 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1500 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1501 status = "disabled";
1502 }; 1502 };
1503 1503
1504 i2c4: i2c@890000 { 1504 i2c4: i2c@890000 {
1505 compatible = 1505 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1506 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1507 clock-names = "se";
1508 clocks = <&gc 1508 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1509 pinctrl-names = "default";
1510 pinctrl-0 = < 1510 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1511 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1512 #address-cells = <1>;
1513 #size-cells = 1513 #size-cells = <0>;
1514 power-domains 1514 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1515 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1516 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1517 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1518 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1519 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ 1520 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521 <&gpi_ 1521 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522 dma-names = " 1522 dma-names = "tx", "rx";
1523 status = "dis 1523 status = "disabled";
1524 }; 1524 };
1525 1525
1526 spi4: spi@890000 { 1526 spi4: spi@890000 {
1527 compatible = 1527 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1528 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1529 clock-names = "se";
1530 clocks = <&gc 1530 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1531 pinctrl-names = "default";
1532 pinctrl-0 = < 1532 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1533 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1534 #address-cells = <1>;
1535 #size-cells = 1535 #size-cells = <0>;
1536 interconnects 1536 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1537 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1538 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ 1539 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1540 <&gpi_ 1540 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1541 dma-names = " 1541 dma-names = "tx", "rx";
1542 status = "dis 1542 status = "disabled";
1543 }; 1543 };
1544 1544
1545 uart4: serial@890000 1545 uart4: serial@890000 {
1546 compatible = 1546 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1547 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1548 clock-names = "se";
1549 clocks = <&gc 1549 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1550 pinctrl-names = "default";
1551 pinctrl-0 = < 1551 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1552 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1553 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1554 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1555 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1556 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1557 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1558 status = "disabled";
1559 }; 1559 };
1560 1560
1561 i2c5: i2c@894000 { 1561 i2c5: i2c@894000 {
1562 compatible = 1562 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1563 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1564 clock-names = "se";
1565 clocks = <&gc 1565 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1566 pinctrl-names = "default";
1567 pinctrl-0 = < 1567 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1568 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1569 #address-cells = <1>;
1570 #size-cells = 1570 #size-cells = <0>;
1571 power-domains 1571 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1572 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1573 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1574 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1575 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ 1577 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1578 <&gpi_ 1578 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1579 dma-names = " 1579 dma-names = "tx", "rx";
1580 status = "dis 1580 status = "disabled";
1581 }; 1581 };
1582 1582
1583 spi5: spi@894000 { 1583 spi5: spi@894000 {
1584 compatible = 1584 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1585 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1586 clock-names = "se";
1587 clocks = <&gc 1587 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1588 pinctrl-names = "default";
1589 pinctrl-0 = < 1589 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1590 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1591 #address-cells = <1>;
1592 #size-cells = 1592 #size-cells = <0>;
1593 interconnects 1593 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1594 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1595 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ 1596 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1597 <&gpi_ 1597 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1598 dma-names = " 1598 dma-names = "tx", "rx";
1599 status = "dis 1599 status = "disabled";
1600 }; 1600 };
1601 1601
1602 uart5: serial@894000 1602 uart5: serial@894000 {
1603 compatible = 1603 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1604 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1605 clock-names = "se";
1606 clocks = <&gc 1606 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1607 pinctrl-names = "default";
1608 pinctrl-0 = < 1608 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1609 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1610 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1611 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1612 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1613 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1614 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1615 status = "disabled";
1616 }; 1616 };
1617 1617
1618 i2c6: i2c@898000 { 1618 i2c6: i2c@898000 {
1619 compatible = 1619 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1620 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1621 clock-names = "se";
1622 clocks = <&gc 1622 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1623 pinctrl-names = "default";
1624 pinctrl-0 = < 1624 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1625 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1626 #address-cells = <1>;
1627 #size-cells = 1627 #size-cells = <0>;
1628 power-domains 1628 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1629 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1630 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1631 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1632 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1633 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ 1634 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1635 <&gpi_ 1635 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1636 dma-names = " 1636 dma-names = "tx", "rx";
1637 status = "dis 1637 status = "disabled";
1638 }; 1638 };
1639 1639
1640 spi6: spi@898000 { 1640 spi6: spi@898000 {
1641 compatible = 1641 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1642 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1643 clock-names = "se";
1644 clocks = <&gc 1644 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1645 pinctrl-names = "default";
1646 pinctrl-0 = < 1646 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1647 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1648 #address-cells = <1>;
1649 #size-cells = 1649 #size-cells = <0>;
1650 interconnects 1650 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1651 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1652 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ 1653 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1654 <&gpi_ 1654 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1655 dma-names = " 1655 dma-names = "tx", "rx";
1656 status = "dis 1656 status = "disabled";
1657 }; 1657 };
1658 1658
1659 uart6: serial@898000 1659 uart6: serial@898000 {
1660 compatible = 1660 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1661 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1662 clock-names = "se";
1663 clocks = <&gc 1663 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1664 pinctrl-names = "default";
1665 pinctrl-0 = < 1665 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1666 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1667 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1668 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1669 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1670 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1671 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1672 status = "disabled";
1673 }; 1673 };
1674 1674
1675 i2c7: i2c@89c000 { 1675 i2c7: i2c@89c000 {
1676 compatible = 1676 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1677 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1678 clock-names = "se";
1679 clocks = <&gc 1679 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1680 pinctrl-names = "default";
1681 pinctrl-0 = < 1681 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1682 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1683 #address-cells = <1>;
1684 #size-cells = 1684 #size-cells = <0>;
1685 power-domains 1685 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1686 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1687 status = "disabled";
1688 }; 1688 };
1689 1689
1690 spi7: spi@89c000 { 1690 spi7: spi@89c000 {
1691 compatible = 1691 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1692 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1693 clock-names = "se";
1694 clocks = <&gc 1694 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1695 pinctrl-names = "default";
1696 pinctrl-0 = < 1696 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1697 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1698 #address-cells = <1>;
1699 #size-cells = 1699 #size-cells = <0>;
1700 interconnects 1700 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1701 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1702 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ 1703 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1704 <&gpi_ 1704 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1705 dma-names = " 1705 dma-names = "tx", "rx";
1706 status = "dis 1706 status = "disabled";
1707 }; 1707 };
1708 1708
1709 uart7: serial@89c000 1709 uart7: serial@89c000 {
1710 compatible = 1710 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1711 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1712 clock-names = "se";
1713 clocks = <&gc 1713 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1714 pinctrl-names = "default";
1715 pinctrl-0 = < 1715 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1716 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1717 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1718 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1719 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1720 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1721 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1722 status = "disabled";
1723 }; 1723 };
1724 }; 1724 };
1725 1725
1726 gpi_dma1: dma-controller@a000 1726 gpi_dma1: dma-controller@a00000 {
1727 #dma-cells = <3>; 1727 #dma-cells = <3>;
1728 compatible = "qcom,sd 1728 compatible = "qcom,sdm845-gpi-dma";
1729 reg = <0 0x00a00000 0 1729 reg = <0 0x00a00000 0 0x60000>;
1730 interrupts = <GIC_SPI 1730 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1731 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 1732 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 1733 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 1734 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 1735 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 1736 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1737 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1738 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1739 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1740 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1741 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1742 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743 dma-channels = <13>; 1743 dma-channels = <13>;
1744 dma-channel-mask = <0 1744 dma-channel-mask = <0xfa>;
1745 iommus = <&apps_smmu 1745 iommus = <&apps_smmu 0x06d6 0x0>;
1746 status = "disabled"; 1746 status = "disabled";
1747 }; 1747 };
1748 1748
1749 qupv3_id_1: geniqup@ac0000 { 1749 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1750 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1751 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1752 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1753 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1754 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1755 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1756 #address-cells = <2>;
1757 #size-cells = <2>; 1757 #size-cells = <2>;
1758 ranges; 1758 ranges;
1759 interconnects = <&agg 1759 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1760 interconnect-names = "qup-core";
1761 status = "disabled"; 1761 status = "disabled";
1762 1762
1763 i2c8: i2c@a80000 { 1763 i2c8: i2c@a80000 {
1764 compatible = 1764 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1765 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1766 clock-names = "se";
1767 clocks = <&gc 1767 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1768 pinctrl-names = "default";
1769 pinctrl-0 = < 1769 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1770 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1771 #address-cells = <1>;
1772 #size-cells = 1772 #size-cells = <0>;
1773 power-domains 1773 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1774 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1775 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1776 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1777 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1778 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ 1779 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780 <&gpi_ 1780 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1781 dma-names = " 1781 dma-names = "tx", "rx";
1782 status = "dis 1782 status = "disabled";
1783 }; 1783 };
1784 1784
1785 spi8: spi@a80000 { 1785 spi8: spi@a80000 {
1786 compatible = 1786 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1787 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1788 clock-names = "se";
1789 clocks = <&gc 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1790 pinctrl-names = "default";
1791 pinctrl-0 = < 1791 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1792 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1793 #address-cells = <1>;
1794 #size-cells = 1794 #size-cells = <0>;
1795 interconnects 1795 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1796 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1797 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ 1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799 <&gpi_ 1799 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1800 dma-names = " 1800 dma-names = "tx", "rx";
1801 status = "dis 1801 status = "disabled";
1802 }; 1802 };
1803 1803
1804 uart8: serial@a80000 1804 uart8: serial@a80000 {
1805 compatible = 1805 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1806 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1807 clock-names = "se";
1808 clocks = <&gc 1808 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1809 pinctrl-names = "default";
1810 pinctrl-0 = < 1810 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1811 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1812 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1813 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1814 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1815 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1816 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1817 status = "disabled";
1818 }; 1818 };
1819 1819
1820 i2c9: i2c@a84000 { 1820 i2c9: i2c@a84000 {
1821 compatible = 1821 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1822 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1823 clock-names = "se";
1824 clocks = <&gc 1824 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1825 pinctrl-names = "default";
1826 pinctrl-0 = < 1826 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1827 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1828 #address-cells = <1>;
1829 #size-cells = 1829 #size-cells = <0>;
1830 power-domains 1830 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1831 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1832 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1833 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1834 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1835 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ 1836 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1837 <&gpi_ 1837 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1838 dma-names = " 1838 dma-names = "tx", "rx";
1839 status = "dis 1839 status = "disabled";
1840 }; 1840 };
1841 1841
1842 spi9: spi@a84000 { 1842 spi9: spi@a84000 {
1843 compatible = 1843 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1844 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1845 clock-names = "se";
1846 clocks = <&gc 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1847 pinctrl-names = "default";
1848 pinctrl-0 = < 1848 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1849 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1850 #address-cells = <1>;
1851 #size-cells = 1851 #size-cells = <0>;
1852 interconnects 1852 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1853 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1854 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ 1855 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1856 <&gpi_ 1856 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1857 dma-names = " 1857 dma-names = "tx", "rx";
1858 status = "dis 1858 status = "disabled";
1859 }; 1859 };
1860 1860
1861 uart9: serial@a84000 1861 uart9: serial@a84000 {
1862 compatible = 1862 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1863 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1864 clock-names = "se";
1865 clocks = <&gc 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1866 pinctrl-names = "default";
1867 pinctrl-0 = < 1867 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1868 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1869 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1870 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1871 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1872 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1873 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1874 status = "disabled";
1875 }; 1875 };
1876 1876
1877 i2c10: i2c@a88000 { 1877 i2c10: i2c@a88000 {
1878 compatible = 1878 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1879 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1880 clock-names = "se";
1881 clocks = <&gc 1881 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1882 pinctrl-names = "default";
1883 pinctrl-0 = < 1883 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1884 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1885 #address-cells = <1>;
1886 #size-cells = 1886 #size-cells = <0>;
1887 power-domains 1887 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1888 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1889 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1890 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1891 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1892 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ 1893 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1894 <&gpi_ 1894 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1895 dma-names = " 1895 dma-names = "tx", "rx";
1896 status = "dis 1896 status = "disabled";
1897 }; 1897 };
1898 1898
1899 spi10: spi@a88000 { 1899 spi10: spi@a88000 {
1900 compatible = 1900 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1901 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1902 clock-names = "se";
1903 clocks = <&gc 1903 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1904 pinctrl-names = "default";
1905 pinctrl-0 = < 1905 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1906 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1907 #address-cells = <1>;
1908 #size-cells = 1908 #size-cells = <0>;
1909 interconnects 1909 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1910 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1911 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ 1912 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913 <&gpi_ 1913 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1914 dma-names = " 1914 dma-names = "tx", "rx";
1915 status = "dis 1915 status = "disabled";
1916 }; 1916 };
1917 1917
1918 uart10: serial@a88000 1918 uart10: serial@a88000 {
1919 compatible = 1919 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1920 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1921 clock-names = "se";
1922 clocks = <&gc 1922 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1923 pinctrl-names = "default";
1924 pinctrl-0 = < 1924 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1925 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1926 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1927 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1928 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1929 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1930 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1931 status = "disabled";
1932 }; 1932 };
1933 1933
1934 i2c11: i2c@a8c000 { 1934 i2c11: i2c@a8c000 {
1935 compatible = 1935 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1936 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1937 clock-names = "se";
1938 clocks = <&gc 1938 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1939 pinctrl-names = "default";
1940 pinctrl-0 = < 1940 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1941 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1942 #address-cells = <1>;
1943 #size-cells = 1943 #size-cells = <0>;
1944 power-domains 1944 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1945 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1946 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1947 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1948 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1949 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ 1950 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1951 <&gpi_ 1951 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1952 dma-names = " 1952 dma-names = "tx", "rx";
1953 status = "dis 1953 status = "disabled";
1954 }; 1954 };
1955 1955
1956 spi11: spi@a8c000 { 1956 spi11: spi@a8c000 {
1957 compatible = 1957 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1958 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1959 clock-names = "se";
1960 clocks = <&gc 1960 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1961 pinctrl-names = "default";
1962 pinctrl-0 = < 1962 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1963 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1964 #address-cells = <1>;
1965 #size-cells = 1965 #size-cells = <0>;
1966 interconnects 1966 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1967 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1968 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ 1969 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1970 <&gpi_ 1970 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1971 dma-names = " 1971 dma-names = "tx", "rx";
1972 status = "dis 1972 status = "disabled";
1973 }; 1973 };
1974 1974
1975 uart11: serial@a8c000 1975 uart11: serial@a8c000 {
1976 compatible = 1976 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1977 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1978 clock-names = "se";
1979 clocks = <&gc 1979 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1980 pinctrl-names = "default";
1981 pinctrl-0 = < 1981 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1982 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1983 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1984 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1985 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1986 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1987 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1988 status = "disabled";
1989 }; 1989 };
1990 1990
1991 i2c12: i2c@a90000 { 1991 i2c12: i2c@a90000 {
1992 compatible = 1992 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1993 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1994 clock-names = "se";
1995 clocks = <&gc 1995 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1996 pinctrl-names = "default";
1997 pinctrl-0 = < 1997 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1998 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1999 #address-cells = <1>;
2000 #size-cells = 2000 #size-cells = <0>;
2001 power-domains 2001 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 2002 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 2003 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 2004 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 2005 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 2006 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ 2007 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2008 <&gpi_ 2008 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2009 dma-names = " 2009 dma-names = "tx", "rx";
2010 status = "dis 2010 status = "disabled";
2011 }; 2011 };
2012 2012
2013 spi12: spi@a90000 { 2013 spi12: spi@a90000 {
2014 compatible = 2014 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 2015 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 2016 clock-names = "se";
2017 clocks = <&gc 2017 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 2018 pinctrl-names = "default";
2019 pinctrl-0 = < 2019 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 2020 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 2021 #address-cells = <1>;
2022 #size-cells = 2022 #size-cells = <0>;
2023 interconnects 2023 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 2024 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 2025 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ 2026 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2027 <&gpi_ 2027 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2028 dma-names = " 2028 dma-names = "tx", "rx";
2029 status = "dis 2029 status = "disabled";
2030 }; 2030 };
2031 2031
2032 uart12: serial@a90000 2032 uart12: serial@a90000 {
2033 compatible = 2033 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 2034 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 2035 clock-names = "se";
2036 clocks = <&gc 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 2037 pinctrl-names = "default";
2038 pinctrl-0 = < 2038 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 2039 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 2040 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 2041 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 2042 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 2043 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 2044 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 2045 status = "disabled";
2046 }; 2046 };
2047 2047
2048 i2c13: i2c@a94000 { 2048 i2c13: i2c@a94000 {
2049 compatible = 2049 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 2050 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 2051 clock-names = "se";
2052 clocks = <&gc 2052 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 2053 pinctrl-names = "default";
2054 pinctrl-0 = < 2054 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 2055 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 2056 #address-cells = <1>;
2057 #size-cells = 2057 #size-cells = <0>;
2058 power-domains 2058 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 2059 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 2060 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 2061 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 2062 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 2063 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ 2064 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2065 <&gpi_ 2065 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2066 dma-names = " 2066 dma-names = "tx", "rx";
2067 status = "dis 2067 status = "disabled";
2068 }; 2068 };
2069 2069
2070 spi13: spi@a94000 { 2070 spi13: spi@a94000 {
2071 compatible = 2071 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 2072 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 2073 clock-names = "se";
2074 clocks = <&gc 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 2075 pinctrl-names = "default";
2076 pinctrl-0 = < 2076 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 2077 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 2078 #address-cells = <1>;
2079 #size-cells = 2079 #size-cells = <0>;
2080 interconnects 2080 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 2081 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 2082 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ 2083 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2084 <&gpi_ 2084 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2085 dma-names = " 2085 dma-names = "tx", "rx";
2086 status = "dis 2086 status = "disabled";
2087 }; 2087 };
2088 2088
2089 uart13: serial@a94000 2089 uart13: serial@a94000 {
2090 compatible = 2090 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 2091 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 2092 clock-names = "se";
2093 clocks = <&gc 2093 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 2094 pinctrl-names = "default";
2095 pinctrl-0 = < 2095 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 2096 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 2097 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 2098 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 2099 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 2100 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 2101 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 2102 status = "disabled";
2103 }; 2103 };
2104 2104
2105 i2c14: i2c@a98000 { 2105 i2c14: i2c@a98000 {
2106 compatible = 2106 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 2107 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 2108 clock-names = "se";
2109 clocks = <&gc 2109 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 2110 pinctrl-names = "default";
2111 pinctrl-0 = < 2111 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 2112 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 2113 #address-cells = <1>;
2114 #size-cells = 2114 #size-cells = <0>;
2115 power-domains 2115 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 2116 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 2117 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 2118 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 2119 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 2120 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ 2121 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2122 <&gpi_ 2122 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2123 dma-names = " 2123 dma-names = "tx", "rx";
2124 status = "dis 2124 status = "disabled";
2125 }; 2125 };
2126 2126
2127 spi14: spi@a98000 { 2127 spi14: spi@a98000 {
2128 compatible = 2128 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 2129 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 2130 clock-names = "se";
2131 clocks = <&gc 2131 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 2132 pinctrl-names = "default";
2133 pinctrl-0 = < 2133 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 2134 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 2135 #address-cells = <1>;
2136 #size-cells = 2136 #size-cells = <0>;
2137 interconnects 2137 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 2138 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 2139 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ 2140 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2141 <&gpi_ 2141 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2142 dma-names = " 2142 dma-names = "tx", "rx";
2143 status = "dis 2143 status = "disabled";
2144 }; 2144 };
2145 2145
2146 uart14: serial@a98000 2146 uart14: serial@a98000 {
2147 compatible = 2147 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 2148 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 2149 clock-names = "se";
2150 clocks = <&gc 2150 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 2151 pinctrl-names = "default";
2152 pinctrl-0 = < 2152 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 2153 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 2154 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 2155 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 2156 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 2157 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 2158 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 2159 status = "disabled";
2160 }; 2160 };
2161 2161
2162 i2c15: i2c@a9c000 { 2162 i2c15: i2c@a9c000 {
2163 compatible = 2163 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 2164 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 2165 clock-names = "se";
2166 clocks = <&gc 2166 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 2167 pinctrl-names = "default";
2168 pinctrl-0 = < 2168 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 2169 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 2170 #address-cells = <1>;
2171 #size-cells = 2171 #size-cells = <0>;
2172 power-domains 2172 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 2173 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 2174 status = "disabled";
2175 interconnects 2175 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 2176 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 2177 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 2178 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ 2179 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2180 <&gpi_ 2180 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2181 dma-names = " 2181 dma-names = "tx", "rx";
2182 }; 2182 };
2183 2183
2184 spi15: spi@a9c000 { 2184 spi15: spi@a9c000 {
2185 compatible = 2185 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 2186 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 2187 clock-names = "se";
2188 clocks = <&gc 2188 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 2189 pinctrl-names = "default";
2190 pinctrl-0 = < 2190 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 2191 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 2192 #address-cells = <1>;
2193 #size-cells = 2193 #size-cells = <0>;
2194 interconnects 2194 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 2195 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 2196 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ 2197 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2198 <&gpi_ 2198 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2199 dma-names = " 2199 dma-names = "tx", "rx";
2200 status = "dis 2200 status = "disabled";
2201 }; 2201 };
2202 2202
2203 uart15: serial@a9c000 2203 uart15: serial@a9c000 {
2204 compatible = 2204 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 2205 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 2206 clock-names = "se";
2207 clocks = <&gc 2207 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 2208 pinctrl-names = "default";
2209 pinctrl-0 = < 2209 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 2210 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 2211 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 2212 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 2213 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 2214 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 2215 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 2216 status = "disabled";
2217 }; 2217 };
2218 }; 2218 };
2219 2219
2220 llcc: system-cache-controller 2220 llcc: system-cache-controller@1100000 {
2221 compatible = "qcom,sd 2221 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 2222 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2223 <0 0x01200000 0 2223 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2224 <0 0x01300000 0 2224 <0 0x01300000 0 0x50000>;
2225 reg-names = "llcc0_ba 2225 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2226 "llcc3_ba 2226 "llcc3_base", "llcc_broadcast_base";
2227 interrupts = <GIC_SPI 2227 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 2228 };
2229 2229
2230 dma@10a2000 { 2230 dma@10a2000 {
2231 compatible = "qcom,sd 2231 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2232 reg = <0x0 0x010a2000 2232 reg = <0x0 0x010a2000 0x0 0x1000>,
2233 <0x0 0x010ae000 2233 <0x0 0x010ae000 0x0 0x2000>;
2234 }; 2234 };
2235 2235
2236 pmu@114a000 { 2236 pmu@114a000 {
2237 compatible = "qcom,sd 2237 compatible = "qcom,sdm845-llcc-bwmon";
2238 reg = <0 0x0114a000 0 2238 reg = <0 0x0114a000 0 0x1000>;
2239 interrupts = <GIC_SPI 2239 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2240 interconnects = <&mem 2240 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2241 2241
2242 operating-points-v2 = 2242 operating-points-v2 = <&llcc_bwmon_opp_table>;
2243 2243
2244 llcc_bwmon_opp_table: 2244 llcc_bwmon_opp_table: opp-table {
2245 compatible = 2245 compatible = "operating-points-v2";
2246 2246
2247 /* 2247 /*
2248 * The interc 2248 * The interconnect path bandwidth taken from
2249 * cpu4_opp_t 2249 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2250 * interconne 2250 * interconnect. This also matches the
2251 * bandwidth 2251 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2252 * bus width: 2252 * bus width: 4 bytes) from msm-4.9 downstream
2253 * kernel. 2253 * kernel.
2254 */ 2254 */
2255 opp-0 { 2255 opp-0 {
2256 opp-p 2256 opp-peak-kBps = <800000>;
2257 }; 2257 };
2258 opp-1 { 2258 opp-1 {
2259 opp-p 2259 opp-peak-kBps = <1804000>;
2260 }; 2260 };
2261 opp-2 { 2261 opp-2 {
2262 opp-p 2262 opp-peak-kBps = <3072000>;
2263 }; 2263 };
2264 opp-3 { 2264 opp-3 {
2265 opp-p 2265 opp-peak-kBps = <5412000>;
2266 }; 2266 };
2267 opp-4 { 2267 opp-4 {
2268 opp-p 2268 opp-peak-kBps = <7216000>;
2269 }; 2269 };
2270 }; 2270 };
2271 }; 2271 };
2272 2272
2273 pmu@1436400 { 2273 pmu@1436400 {
2274 compatible = "qcom,sd 2274 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2275 reg = <0 0x01436400 0 2275 reg = <0 0x01436400 0 0x600>;
2276 interrupts = <GIC_SPI 2276 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2277 interconnects = <&gla 2277 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278 2278
2279 operating-points-v2 = 2279 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 2280
2281 cpu_bwmon_opp_table: 2281 cpu_bwmon_opp_table: opp-table {
2282 compatible = 2282 compatible = "operating-points-v2";
2283 2283
2284 /* 2284 /*
2285 * The interc 2285 * The interconnect path bandwidth taken from
2286 * cpu4_opp_t 2286 * cpu4_opp_table bandwidth for OSM L3
2287 * interconne 2287 * interconnect. This also matches the OSM L3
2288 * from bandw 2288 * from bandwidth table of qcom,cpu4-l3lat-mon
2289 * (qcom,core 2289 * (qcom,core-dev-table, bus width: 16 bytes)
2290 * from msm-4 2290 * from msm-4.9 downstream kernel.
2291 */ 2291 */
2292 opp-0 { 2292 opp-0 {
2293 opp-p 2293 opp-peak-kBps = <4800000>;
2294 }; 2294 };
2295 opp-1 { 2295 opp-1 {
2296 opp-p 2296 opp-peak-kBps = <9216000>;
2297 }; 2297 };
2298 opp-2 { 2298 opp-2 {
2299 opp-p 2299 opp-peak-kBps = <15052800>;
2300 }; 2300 };
2301 opp-3 { 2301 opp-3 {
2302 opp-p 2302 opp-peak-kBps = <20889600>;
2303 }; 2303 };
2304 opp-4 { 2304 opp-4 {
2305 opp-p 2305 opp-peak-kBps = <25497600>;
2306 }; 2306 };
2307 }; 2307 };
2308 }; 2308 };
2309 2309
2310 pcie0: pcie@1c00000 { 2310 pcie0: pcie@1c00000 {
2311 compatible = "qcom,pc 2311 compatible = "qcom,pcie-sdm845";
2312 reg = <0 0x01c00000 0 2312 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 2313 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 2314 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 2315 <0 0x60100000 0 0x100000>,
2316 <0 0x01c07000 0 2316 <0 0x01c07000 0 0x1000>;
2317 reg-names = "parf", " 2317 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2318 device_type = "pci"; 2318 device_type = "pci";
2319 linux,pci-domain = <0 2319 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 2320 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 2321 num-lanes = <1>;
2322 2322
2323 #address-cells = <3>; 2323 #address-cells = <3>;
2324 #size-cells = <2>; 2324 #size-cells = <2>;
2325 2325
2326 ranges = <0x01000000 2326 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2327 <0x02000000 2327 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2328 2328
2329 interrupts = <GIC_SPI 2329 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 2330 interrupt-names = "msi";
2331 #interrupt-cells = <1 2331 #interrupt-cells = <1>;
2332 interrupt-map-mask = 2332 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 2333 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 2334 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 2335 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 2336 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2337
2338 clocks = <&gcc GCC_PC 2338 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2339 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2340 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2341 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2342 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2343 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2344 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2345 clock-names = "pipe",
2346 "aux", 2346 "aux",
2347 "cfg", 2347 "cfg",
2348 "bus_ma 2348 "bus_master",
2349 "bus_sl 2349 "bus_slave",
2350 "slave_ 2350 "slave_q2a",
2351 "tbu"; 2351 "tbu";
2352 2352
2353 iommu-map = <0x0 &a 2353 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2354 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2355 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2356 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2357 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2358 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2359 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2360 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2361 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2362 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2363 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2364 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2365 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2366 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2367 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2368 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2369
2370 resets = <&gcc GCC_PC 2370 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2371 reset-names = "pci";
2372 2372
2373 power-domains = <&gcc 2373 power-domains = <&gcc PCIE_0_GDSC>;
2374 2374
2375 phys = <&pcie0_phy>; 2375 phys = <&pcie0_phy>;
2376 phy-names = "pciephy" 2376 phy-names = "pciephy";
2377 2377
2378 status = "disabled"; 2378 status = "disabled";
2379 2379
2380 pcie@0 { 2380 pcie@0 {
2381 device_type = 2381 device_type = "pci";
2382 reg = <0x0 0x 2382 reg = <0x0 0x0 0x0 0x0 0x0>;
2383 bus-range = < 2383 bus-range = <0x01 0xff>;
2384 2384
2385 #address-cell 2385 #address-cells = <3>;
2386 #size-cells = 2386 #size-cells = <2>;
2387 ranges; 2387 ranges;
2388 }; 2388 };
2389 }; 2389 };
2390 2390
2391 pcie0_phy: phy@1c06000 { 2391 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2392 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 2393 reg = <0 0x01c06000 0 0x1000>;
2394 clocks = <&gcc GCC_PC 2394 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2395 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2396 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC 2397 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2398 <&gcc GCC_PC 2398 <&gcc GCC_PCIE_0_PIPE_CLK>;
2399 clock-names = "aux", 2399 clock-names = "aux",
2400 "cfg_ah 2400 "cfg_ahb",
2401 "ref", 2401 "ref",
2402 "refgen 2402 "refgen",
2403 "pipe"; 2403 "pipe";
2404 2404
2405 clock-output-names = 2405 clock-output-names = "pcie_0_pipe_clk";
2406 #clock-cells = <0>; 2406 #clock-cells = <0>;
2407 2407
2408 #phy-cells = <0>; 2408 #phy-cells = <0>;
2409 2409
2410 resets = <&gcc GCC_PC 2410 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2411 reset-names = "phy";
2412 2412
2413 assigned-clocks = <&g 2413 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2414 assigned-clock-rates = <100000000>;
2415 2415
2416 status = "disabled"; 2416 status = "disabled";
2417 }; 2417 };
2418 2418
2419 pcie1: pcie@1c08000 { 2419 pcie1: pcie@1c08000 {
2420 compatible = "qcom,pc 2420 compatible = "qcom,pcie-sdm845";
2421 reg = <0 0x01c08000 0 2421 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2422 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2423 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 2424 <0 0x40100000 0 0x100000>,
2425 <0 0x01c0c000 0 2425 <0 0x01c0c000 0 0x1000>;
2426 reg-names = "parf", " 2426 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2427 device_type = "pci"; 2427 device_type = "pci";
2428 linux,pci-domain = <1 2428 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2429 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2430 num-lanes = <1>;
2431 2431
2432 #address-cells = <3>; 2432 #address-cells = <3>;
2433 #size-cells = <2>; 2433 #size-cells = <2>;
2434 2434
2435 ranges = <0x01000000 2435 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2436 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2437
2438 interrupts = <GIC_SPI 2438 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2439 interrupt-names = "msi";
2440 #interrupt-cells = <1 2440 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2441 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 2442 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 2443 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 2444 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 2445 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2446
2447 clocks = <&gcc GCC_PC 2447 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2448 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2449 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2450 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2451 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2452 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2453 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2454 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2455 clock-names = "pipe",
2456 "aux", 2456 "aux",
2457 "cfg", 2457 "cfg",
2458 "bus_ma 2458 "bus_master",
2459 "bus_sl 2459 "bus_slave",
2460 "slave_ 2460 "slave_q2a",
2461 "ref", 2461 "ref",
2462 "tbu"; 2462 "tbu";
2463 2463
2464 assigned-clocks = <&g 2464 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2465 assigned-clock-rates = <19200000>;
2466 2466
2467 iommu-map = <0x0 &a 2467 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2468 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2469 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2470 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2471 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2472 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2473 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2474 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2475 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2476 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2477 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2478 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2479 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2480 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2481 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2482 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2483
2484 resets = <&gcc GCC_PC 2484 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2485 reset-names = "pci";
2486 2486
2487 power-domains = <&gcc 2487 power-domains = <&gcc PCIE_1_GDSC>;
2488 2488
2489 phys = <&pcie1_phy>; 2489 phys = <&pcie1_phy>;
2490 phy-names = "pciephy" 2490 phy-names = "pciephy";
2491 2491
2492 status = "disabled"; 2492 status = "disabled";
2493 2493
2494 pcie@0 { 2494 pcie@0 {
2495 device_type = 2495 device_type = "pci";
2496 reg = <0x0 0x 2496 reg = <0x0 0x0 0x0 0x0 0x0>;
2497 bus-range = < 2497 bus-range = <0x01 0xff>;
2498 2498
2499 #address-cell 2499 #address-cells = <3>;
2500 #size-cells = 2500 #size-cells = <2>;
2501 ranges; 2501 ranges;
2502 }; 2502 };
2503 }; 2503 };
2504 2504
2505 pcie1_phy: phy@1c0a000 { 2505 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2506 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 2507 reg = <0 0x01c0a000 0 0x2000>;
2508 clocks = <&gcc GCC_PC 2508 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2509 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2510 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC 2511 <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2512 <&gcc GCC_PC 2512 <&gcc GCC_PCIE_1_PIPE_CLK>;
2513 clock-names = "aux", 2513 clock-names = "aux",
2514 "cfg_ah 2514 "cfg_ahb",
2515 "ref", 2515 "ref",
2516 "refgen 2516 "refgen",
2517 "pipe"; 2517 "pipe";
2518 2518
2519 clock-output-names = 2519 clock-output-names = "pcie_1_pipe_clk";
2520 #clock-cells = <0>; 2520 #clock-cells = <0>;
2521 2521
2522 #phy-cells = <0>; 2522 #phy-cells = <0>;
2523 2523
2524 resets = <&gcc GCC_PC 2524 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2525 reset-names = "phy";
2526 2526
2527 assigned-clocks = <&g 2527 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2528 assigned-clock-rates = <100000000>;
2529 2529
2530 status = "disabled"; 2530 status = "disabled";
2531 }; 2531 };
2532 2532
2533 mem_noc: interconnect@1380000 2533 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2534 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2535 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2536 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2537 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2538 };
2539 2539
2540 dc_noc: interconnect@14e0000 2540 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2541 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2542 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2543 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2544 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2545 };
2546 2546
2547 config_noc: interconnect@1500 2547 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2548 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2549 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2550 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2551 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2552 };
2553 2553
2554 system_noc: interconnect@1620 2554 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2555 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2556 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2557 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2558 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2559 };
2560 2560
2561 aggre1_noc: interconnect@16e0 2561 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2562 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2563 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2564 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2565 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2566 };
2567 2567
2568 aggre2_noc: interconnect@1700 2568 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2569 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2570 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2571 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2572 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2573 };
2574 2574
2575 mmss_noc: interconnect@174000 2575 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2576 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2577 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2578 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2579 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2580 };
2581 2581
2582 ufs_mem_hc: ufshc@1d84000 { 2582 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2583 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2584 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2585 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2586 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2587 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2588 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> 2589 phys = <&ufs_mem_phy>;
2590 phy-names = "ufsphy"; 2590 phy-names = "ufsphy";
2591 lanes-per-direction = 2591 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2592 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2593 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2594 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2595 reset-names = "rst";
2596 2596
2597 iommus = <&apps_smmu 2597 iommus = <&apps_smmu 0x100 0xf>;
2598 2598
2599 clock-names = 2599 clock-names =
2600 "core_clk", 2600 "core_clk",
2601 "bus_aggr_clk 2601 "bus_aggr_clk",
2602 "iface_clk", 2602 "iface_clk",
2603 "core_clk_uni 2603 "core_clk_unipro",
2604 "ref_clk", 2604 "ref_clk",
2605 "tx_lane0_syn 2605 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2606 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2607 "rx_lane1_sync_clk",
2608 "ice_core_clk 2608 "ice_core_clk";
2609 clocks = 2609 clocks =
2610 <&gcc GCC_UFS 2610 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2611 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2612 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2613 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2614 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2615 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2616 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2617 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2618 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 2619
2620 operating-points-v2 = 2620 operating-points-v2 = <&ufs_opp_table>;
2621 2621
2622 interconnects = <&agg 2622 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2623 <&gla 2623 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2624 interconnect-names = 2624 interconnect-names = "ufs-ddr", "cpu-ufs";
2625 2625
2626 status = "disabled"; 2626 status = "disabled";
2627 2627
2628 ufs_opp_table: opp-ta 2628 ufs_opp_table: opp-table {
2629 compatible = 2629 compatible = "operating-points-v2";
2630 2630
2631 opp-50000000 2631 opp-50000000 {
2632 opp-h 2632 opp-hz = /bits/ 64 <50000000>,
2633 2633 /bits/ 64 <0>,
2634 2634 /bits/ 64 <0>,
2635 2635 /bits/ 64 <37500000>,
2636 2636 /bits/ 64 <0>,
2637 2637 /bits/ 64 <0>,
2638 2638 /bits/ 64 <0>,
2639 2639 /bits/ 64 <0>,
2640 2640 /bits/ 64 <75000000>;
2641 requi 2641 required-opps = <&rpmhpd_opp_low_svs>;
2642 }; 2642 };
2643 2643
2644 opp-200000000 2644 opp-200000000 {
2645 opp-h 2645 opp-hz = /bits/ 64 <200000000>,
2646 2646 /bits/ 64 <0>,
2647 2647 /bits/ 64 <0>,
2648 2648 /bits/ 64 <150000000>,
2649 2649 /bits/ 64 <0>,
2650 2650 /bits/ 64 <0>,
2651 2651 /bits/ 64 <0>,
2652 2652 /bits/ 64 <0>,
2653 2653 /bits/ 64 <300000000>;
2654 requi 2654 required-opps = <&rpmhpd_opp_nom>;
2655 }; 2655 };
2656 }; 2656 };
2657 }; 2657 };
2658 2658
2659 ufs_mem_phy: phy@1d87000 { 2659 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2660 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 2661 reg = <0 0x01d87000 0 0x1000>;
2662 2662
2663 clocks = <&rpmhcc RPM 2663 clocks = <&rpmhcc RPMH_CXO_CLK>,
2664 <&gcc GCC_UF 2664 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2665 <&gcc GCC_UF 2665 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
2666 clock-names = "ref", 2666 clock-names = "ref",
2667 "ref_au 2667 "ref_aux",
2668 "qref"; 2668 "qref";
2669 2669
2670 power-domains = <&gcc 2670 power-domains = <&gcc UFS_PHY_GDSC>;
2671 2671
2672 resets = <&ufs_mem_hc 2672 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2673 reset-names = "ufsphy";
2674 2674
2675 #phy-cells = <0>; 2675 #phy-cells = <0>;
2676 status = "disabled"; 2676 status = "disabled";
2677 }; 2677 };
2678 2678
2679 cryptobam: dma-controller@1dc 2679 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,ba 2680 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2681 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2682 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2683 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2684 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2685 #dma-cells = <1>;
2686 qcom,ee = <0>; 2686 qcom,ee = <0>;
2687 qcom,controlled-remot 2687 qcom,controlled-remotely;
2688 iommus = <&apps_smmu 2688 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2689 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2690 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2691 <&apps_smmu 0x716 0x1>;
2692 }; 2692 };
2693 2693
2694 crypto: crypto@1dfa000 { 2694 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2695 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2696 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2697 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2698 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2699 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2700 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2701 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2702 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2703 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2704 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2705 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2706 <&apps_smmu 0x716 0x1>;
2707 }; 2707 };
2708 2708
2709 ipa: ipa@1e40000 { 2709 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2710 compatible = "qcom,sdm845-ipa";
2711 2711
2712 iommus = <&apps_smmu 2712 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2713 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 2714 reg = <0 0x01e40000 0 0x7000>,
2715 <0 0x01e47000 0 2715 <0 0x01e47000 0 0x2000>,
2716 <0 0x01e04000 0 2716 <0 0x01e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2717 reg-names = "ipa-reg",
2718 "ipa-shar 2718 "ipa-shared",
2719 "gsi"; 2719 "gsi";
2720 2720
2721 interrupts-extended = 2721 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2722 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2723 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2724 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2725 interrupt-names = "ipa",
2726 "gs 2726 "gsi",
2727 "ip 2727 "ipa-clock-query",
2728 "ip 2728 "ipa-setup-ready";
2729 2729
2730 clocks = <&rpmhcc RPM 2730 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2731 clock-names = "core";
2732 2732
2733 interconnects = <&agg 2733 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2734 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2735 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2736 interconnect-names = "memory",
2737 2737 "imem",
2738 2738 "config";
2739 2739
2740 qcom,smem-states = <& 2740 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2741 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2742 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2743 "ipa-clock-enabled";
2744 2744
2745 status = "disabled"; 2745 status = "disabled";
2746 }; 2746 };
2747 2747
2748 tcsr_mutex: hwlock@1f40000 { 2748 tcsr_mutex: hwlock@1f40000 {
2749 compatible = "qcom,tc 2749 compatible = "qcom,tcsr-mutex";
2750 reg = <0 0x01f40000 0 2750 reg = <0 0x01f40000 0 0x20000>;
2751 #hwlock-cells = <1>; 2751 #hwlock-cells = <1>;
2752 }; 2752 };
2753 2753
2754 tcsr_regs_1: syscon@1f60000 { 2754 tcsr_regs_1: syscon@1f60000 {
2755 compatible = "qcom,sd 2755 compatible = "qcom,sdm845-tcsr", "syscon";
2756 reg = <0 0x01f60000 0 2756 reg = <0 0x01f60000 0 0x20000>;
2757 }; 2757 };
2758 2758
2759 tlmm: pinctrl@3400000 { 2759 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2760 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2761 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2762 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2763 gpio-controller;
2764 #gpio-cells = <2>; 2764 #gpio-cells = <2>;
2765 interrupt-controller; 2765 interrupt-controller;
2766 #interrupt-cells = <2 2766 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2767 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2768 wakeup-parent = <&pdc_intc>;
2769 2769
2770 cci0_default: cci0-de 2770 cci0_default: cci0-default-state {
2771 /* SDA, SCL * 2771 /* SDA, SCL */
2772 pins = "gpio1 2772 pins = "gpio17", "gpio18";
2773 function = "c 2773 function = "cci_i2c";
2774 2774
2775 bias-pull-up; 2775 bias-pull-up;
2776 drive-strengt 2776 drive-strength = <2>; /* 2 mA */
2777 }; 2777 };
2778 2778
2779 cci0_sleep: cci0-slee 2779 cci0_sleep: cci0-sleep-state {
2780 /* SDA, SCL * 2780 /* SDA, SCL */
2781 pins = "gpio1 2781 pins = "gpio17", "gpio18";
2782 function = "c 2782 function = "cci_i2c";
2783 2783
2784 drive-strengt 2784 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2785 bias-pull-down;
2786 }; 2786 };
2787 2787
2788 cci1_default: cci1-de 2788 cci1_default: cci1-default-state {
2789 /* SDA, SCL * 2789 /* SDA, SCL */
2790 pins = "gpio1 2790 pins = "gpio19", "gpio20";
2791 function = "c 2791 function = "cci_i2c";
2792 2792
2793 bias-pull-up; 2793 bias-pull-up;
2794 drive-strengt 2794 drive-strength = <2>; /* 2 mA */
2795 }; 2795 };
2796 2796
2797 cci1_sleep: cci1-slee 2797 cci1_sleep: cci1-sleep-state {
2798 /* SDA, SCL * 2798 /* SDA, SCL */
2799 pins = "gpio1 2799 pins = "gpio19", "gpio20";
2800 function = "c 2800 function = "cci_i2c";
2801 2801
2802 drive-strengt 2802 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2803 bias-pull-down;
2804 }; 2804 };
2805 2805
2806 qspi_clk: qspi-clk-st 2806 qspi_clk: qspi-clk-state {
2807 pins = "gpio9 2807 pins = "gpio95";
2808 function = "q 2808 function = "qspi_clk";
2809 }; 2809 };
2810 2810
2811 qspi_cs0: qspi-cs0-st 2811 qspi_cs0: qspi-cs0-state {
2812 pins = "gpio9 2812 pins = "gpio90";
2813 function = "q 2813 function = "qspi_cs";
2814 }; 2814 };
2815 2815
2816 qspi_cs1: qspi-cs1-st 2816 qspi_cs1: qspi-cs1-state {
2817 pins = "gpio8 2817 pins = "gpio89";
2818 function = "q 2818 function = "qspi_cs";
2819 }; 2819 };
2820 2820
2821 qspi_data0: qspi-data 2821 qspi_data0: qspi-data0-state {
2822 pins = "gpio9 2822 pins = "gpio91";
2823 function = "q 2823 function = "qspi_data";
2824 }; 2824 };
2825 2825
2826 qspi_data1: qspi-data 2826 qspi_data1: qspi-data1-state {
2827 pins = "gpio9 2827 pins = "gpio92";
2828 function = "q 2828 function = "qspi_data";
2829 }; 2829 };
2830 2830
2831 qspi_data23: qspi-dat 2831 qspi_data23: qspi-data23-state {
2832 pins = "gpio9 2832 pins = "gpio93", "gpio94";
2833 function = "q 2833 function = "qspi_data";
2834 }; 2834 };
2835 2835
2836 qup_i2c0_default: qup 2836 qup_i2c0_default: qup-i2c0-default-state {
2837 pins = "gpio0 2837 pins = "gpio0", "gpio1";
2838 function = "q 2838 function = "qup0";
2839 }; 2839 };
2840 2840
2841 qup_i2c1_default: qup 2841 qup_i2c1_default: qup-i2c1-default-state {
2842 pins = "gpio1 2842 pins = "gpio17", "gpio18";
2843 function = "q 2843 function = "qup1";
2844 }; 2844 };
2845 2845
2846 qup_i2c2_default: qup 2846 qup_i2c2_default: qup-i2c2-default-state {
2847 pins = "gpio2 2847 pins = "gpio27", "gpio28";
2848 function = "q 2848 function = "qup2";
2849 }; 2849 };
2850 2850
2851 qup_i2c3_default: qup 2851 qup_i2c3_default: qup-i2c3-default-state {
2852 pins = "gpio4 2852 pins = "gpio41", "gpio42";
2853 function = "q 2853 function = "qup3";
2854 }; 2854 };
2855 2855
2856 qup_i2c4_default: qup 2856 qup_i2c4_default: qup-i2c4-default-state {
2857 pins = "gpio8 2857 pins = "gpio89", "gpio90";
2858 function = "q 2858 function = "qup4";
2859 }; 2859 };
2860 2860
2861 qup_i2c5_default: qup 2861 qup_i2c5_default: qup-i2c5-default-state {
2862 pins = "gpio8 2862 pins = "gpio85", "gpio86";
2863 function = "q 2863 function = "qup5";
2864 }; 2864 };
2865 2865
2866 qup_i2c6_default: qup 2866 qup_i2c6_default: qup-i2c6-default-state {
2867 pins = "gpio4 2867 pins = "gpio45", "gpio46";
2868 function = "q 2868 function = "qup6";
2869 }; 2869 };
2870 2870
2871 qup_i2c7_default: qup 2871 qup_i2c7_default: qup-i2c7-default-state {
2872 pins = "gpio9 2872 pins = "gpio93", "gpio94";
2873 function = "q 2873 function = "qup7";
2874 }; 2874 };
2875 2875
2876 qup_i2c8_default: qup 2876 qup_i2c8_default: qup-i2c8-default-state {
2877 pins = "gpio6 2877 pins = "gpio65", "gpio66";
2878 function = "q 2878 function = "qup8";
2879 }; 2879 };
2880 2880
2881 qup_i2c9_default: qup 2881 qup_i2c9_default: qup-i2c9-default-state {
2882 pins = "gpio6 2882 pins = "gpio6", "gpio7";
2883 function = "q 2883 function = "qup9";
2884 }; 2884 };
2885 2885
2886 qup_i2c10_default: qu 2886 qup_i2c10_default: qup-i2c10-default-state {
2887 pins = "gpio5 2887 pins = "gpio55", "gpio56";
2888 function = "q 2888 function = "qup10";
2889 }; 2889 };
2890 2890
2891 qup_i2c11_default: qu 2891 qup_i2c11_default: qup-i2c11-default-state {
2892 pins = "gpio3 2892 pins = "gpio31", "gpio32";
2893 function = "q 2893 function = "qup11";
2894 }; 2894 };
2895 2895
2896 qup_i2c12_default: qu 2896 qup_i2c12_default: qup-i2c12-default-state {
2897 pins = "gpio4 2897 pins = "gpio49", "gpio50";
2898 function = "q 2898 function = "qup12";
2899 }; 2899 };
2900 2900
2901 qup_i2c13_default: qu 2901 qup_i2c13_default: qup-i2c13-default-state {
2902 pins = "gpio1 2902 pins = "gpio105", "gpio106";
2903 function = "q 2903 function = "qup13";
2904 }; 2904 };
2905 2905
2906 qup_i2c14_default: qu 2906 qup_i2c14_default: qup-i2c14-default-state {
2907 pins = "gpio3 2907 pins = "gpio33", "gpio34";
2908 function = "q 2908 function = "qup14";
2909 }; 2909 };
2910 2910
2911 qup_i2c15_default: qu 2911 qup_i2c15_default: qup-i2c15-default-state {
2912 pins = "gpio8 2912 pins = "gpio81", "gpio82";
2913 function = "q 2913 function = "qup15";
2914 }; 2914 };
2915 2915
2916 qup_spi0_default: qup 2916 qup_spi0_default: qup-spi0-default-state {
2917 pins = "gpio0 2917 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2918 function = "q 2918 function = "qup0";
2919 }; 2919 };
2920 2920
2921 qup_spi1_default: qup 2921 qup_spi1_default: qup-spi1-default-state {
2922 pins = "gpio1 2922 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2923 function = "q 2923 function = "qup1";
2924 }; 2924 };
2925 2925
2926 qup_spi2_default: qup 2926 qup_spi2_default: qup-spi2-default-state {
2927 pins = "gpio2 2927 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2928 function = "q 2928 function = "qup2";
2929 }; 2929 };
2930 2930
2931 qup_spi3_default: qup 2931 qup_spi3_default: qup-spi3-default-state {
2932 pins = "gpio4 2932 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2933 function = "q 2933 function = "qup3";
2934 }; 2934 };
2935 2935
2936 qup_spi4_default: qup 2936 qup_spi4_default: qup-spi4-default-state {
2937 pins = "gpio8 2937 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2938 function = "q 2938 function = "qup4";
2939 }; 2939 };
2940 2940
2941 qup_spi5_default: qup 2941 qup_spi5_default: qup-spi5-default-state {
2942 pins = "gpio8 2942 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2943 function = "q 2943 function = "qup5";
2944 }; 2944 };
2945 2945
2946 qup_spi6_default: qup 2946 qup_spi6_default: qup-spi6-default-state {
2947 pins = "gpio4 2947 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2948 function = "q 2948 function = "qup6";
2949 }; 2949 };
2950 2950
2951 qup_spi7_default: qup 2951 qup_spi7_default: qup-spi7-default-state {
2952 pins = "gpio9 2952 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2953 function = "q 2953 function = "qup7";
2954 }; 2954 };
2955 2955
2956 qup_spi8_default: qup 2956 qup_spi8_default: qup-spi8-default-state {
2957 pins = "gpio6 2957 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2958 function = "q 2958 function = "qup8";
2959 }; 2959 };
2960 2960
2961 qup_spi9_default: qup 2961 qup_spi9_default: qup-spi9-default-state {
2962 pins = "gpio6 2962 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2963 function = "q 2963 function = "qup9";
2964 }; 2964 };
2965 2965
2966 qup_spi10_default: qu 2966 qup_spi10_default: qup-spi10-default-state {
2967 pins = "gpio5 2967 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2968 function = "q 2968 function = "qup10";
2969 }; 2969 };
2970 2970
2971 qup_spi11_default: qu 2971 qup_spi11_default: qup-spi11-default-state {
2972 pins = "gpio3 2972 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2973 function = "q 2973 function = "qup11";
2974 }; 2974 };
2975 2975
2976 qup_spi12_default: qu 2976 qup_spi12_default: qup-spi12-default-state {
2977 pins = "gpio4 2977 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2978 function = "q 2978 function = "qup12";
2979 }; 2979 };
2980 2980
2981 qup_spi13_default: qu 2981 qup_spi13_default: qup-spi13-default-state {
2982 pins = "gpio1 2982 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2983 function = "q 2983 function = "qup13";
2984 }; 2984 };
2985 2985
2986 qup_spi14_default: qu 2986 qup_spi14_default: qup-spi14-default-state {
2987 pins = "gpio3 2987 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2988 function = "q 2988 function = "qup14";
2989 }; 2989 };
2990 2990
2991 qup_spi15_default: qu 2991 qup_spi15_default: qup-spi15-default-state {
2992 pins = "gpio8 2992 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2993 function = "q 2993 function = "qup15";
2994 }; 2994 };
2995 2995
2996 qup_uart0_default: qu 2996 qup_uart0_default: qup-uart0-default-state {
2997 qup_uart0_tx: 2997 qup_uart0_tx: tx-pins {
2998 pins 2998 pins = "gpio2";
2999 funct 2999 function = "qup0";
3000 }; 3000 };
3001 3001
3002 qup_uart0_rx: 3002 qup_uart0_rx: rx-pins {
3003 pins 3003 pins = "gpio3";
3004 funct 3004 function = "qup0";
3005 }; 3005 };
3006 }; 3006 };
3007 3007
3008 qup_uart1_default: qu 3008 qup_uart1_default: qup-uart1-default-state {
3009 qup_uart1_tx: 3009 qup_uart1_tx: tx-pins {
3010 pins 3010 pins = "gpio19";
3011 funct 3011 function = "qup1";
3012 }; 3012 };
3013 3013
3014 qup_uart1_rx: 3014 qup_uart1_rx: rx-pins {
3015 pins 3015 pins = "gpio20";
3016 funct 3016 function = "qup1";
3017 }; 3017 };
3018 }; 3018 };
3019 3019
3020 qup_uart2_default: qu 3020 qup_uart2_default: qup-uart2-default-state {
3021 qup_uart2_tx: 3021 qup_uart2_tx: tx-pins {
3022 pins 3022 pins = "gpio29";
3023 funct 3023 function = "qup2";
3024 }; 3024 };
3025 3025
3026 qup_uart2_rx: 3026 qup_uart2_rx: rx-pins {
3027 pins 3027 pins = "gpio30";
3028 funct 3028 function = "qup2";
3029 }; 3029 };
3030 }; 3030 };
3031 3031
3032 qup_uart3_default: qu 3032 qup_uart3_default: qup-uart3-default-state {
3033 qup_uart3_tx: 3033 qup_uart3_tx: tx-pins {
3034 pins 3034 pins = "gpio43";
3035 funct 3035 function = "qup3";
3036 }; 3036 };
3037 3037
3038 qup_uart3_rx: 3038 qup_uart3_rx: rx-pins {
3039 pins 3039 pins = "gpio44";
3040 funct 3040 function = "qup3";
3041 }; 3041 };
3042 }; 3042 };
3043 3043
3044 qup_uart3_4pin: qup-u 3044 qup_uart3_4pin: qup-uart3-4pin-state {
3045 qup_uart3_4pi 3045 qup_uart3_4pin_cts: cts-pins {
3046 pins 3046 pins = "gpio41";
3047 funct 3047 function = "qup3";
3048 }; 3048 };
3049 3049
3050 qup_uart3_4pi 3050 qup_uart3_4pin_rts_tx: rts-tx-pins {
3051 pins 3051 pins = "gpio42", "gpio43";
3052 funct 3052 function = "qup3";
3053 }; 3053 };
3054 3054
3055 qup_uart3_4pi 3055 qup_uart3_4pin_rx: rx-pins {
3056 pins 3056 pins = "gpio44";
3057 funct 3057 function = "qup3";
3058 }; 3058 };
3059 }; 3059 };
3060 3060
3061 qup_uart4_default: qu 3061 qup_uart4_default: qup-uart4-default-state {
3062 qup_uart4_tx: 3062 qup_uart4_tx: tx-pins {
3063 pins 3063 pins = "gpio91";
3064 funct 3064 function = "qup4";
3065 }; 3065 };
3066 3066
3067 qup_uart4_rx: 3067 qup_uart4_rx: rx-pins {
3068 pins 3068 pins = "gpio92";
3069 funct 3069 function = "qup4";
3070 }; 3070 };
3071 }; 3071 };
3072 3072
3073 qup_uart5_default: qu 3073 qup_uart5_default: qup-uart5-default-state {
3074 qup_uart5_tx: 3074 qup_uart5_tx: tx-pins {
3075 pins 3075 pins = "gpio87";
3076 funct 3076 function = "qup5";
3077 }; 3077 };
3078 3078
3079 qup_uart5_rx: 3079 qup_uart5_rx: rx-pins {
3080 pins 3080 pins = "gpio88";
3081 funct 3081 function = "qup5";
3082 }; 3082 };
3083 }; 3083 };
3084 3084
3085 qup_uart6_default: qu 3085 qup_uart6_default: qup-uart6-default-state {
3086 qup_uart6_tx: 3086 qup_uart6_tx: tx-pins {
3087 pins 3087 pins = "gpio47";
3088 funct 3088 function = "qup6";
3089 }; 3089 };
3090 3090
3091 qup_uart6_rx: 3091 qup_uart6_rx: rx-pins {
3092 pins 3092 pins = "gpio48";
3093 funct 3093 function = "qup6";
3094 }; 3094 };
3095 }; 3095 };
3096 3096
3097 qup_uart6_4pin: qup-u 3097 qup_uart6_4pin: qup-uart6-4pin-state {
3098 qup_uart6_4pi 3098 qup_uart6_4pin_cts: cts-pins {
3099 pins 3099 pins = "gpio45";
3100 funct 3100 function = "qup6";
3101 bias- 3101 bias-pull-down;
3102 }; 3102 };
3103 3103
3104 qup_uart6_4pi 3104 qup_uart6_4pin_rts_tx: rts-tx-pins {
3105 pins 3105 pins = "gpio46", "gpio47";
3106 funct 3106 function = "qup6";
3107 drive 3107 drive-strength = <2>;
3108 bias- 3108 bias-disable;
3109 }; 3109 };
3110 3110
3111 qup_uart6_4pi 3111 qup_uart6_4pin_rx: rx-pins {
3112 pins 3112 pins = "gpio48";
3113 funct 3113 function = "qup6";
3114 bias- 3114 bias-pull-up;
3115 }; 3115 };
3116 }; 3116 };
3117 3117
3118 qup_uart7_default: qu 3118 qup_uart7_default: qup-uart7-default-state {
3119 qup_uart7_tx: 3119 qup_uart7_tx: tx-pins {
3120 pins 3120 pins = "gpio95";
3121 funct 3121 function = "qup7";
3122 }; 3122 };
3123 3123
3124 qup_uart7_rx: 3124 qup_uart7_rx: rx-pins {
3125 pins 3125 pins = "gpio96";
3126 funct 3126 function = "qup7";
3127 }; 3127 };
3128 }; 3128 };
3129 3129
3130 qup_uart8_default: qu 3130 qup_uart8_default: qup-uart8-default-state {
3131 qup_uart8_tx: 3131 qup_uart8_tx: tx-pins {
3132 pins 3132 pins = "gpio67";
3133 funct 3133 function = "qup8";
3134 }; 3134 };
3135 3135
3136 qup_uart8_rx: 3136 qup_uart8_rx: rx-pins {
3137 pins 3137 pins = "gpio68";
3138 funct 3138 function = "qup8";
3139 }; 3139 };
3140 }; 3140 };
3141 3141
3142 qup_uart9_default: qu 3142 qup_uart9_default: qup-uart9-default-state {
3143 qup_uart9_tx: 3143 qup_uart9_tx: tx-pins {
3144 pins 3144 pins = "gpio4";
3145 funct 3145 function = "qup9";
3146 }; 3146 };
3147 3147
3148 qup_uart9_rx: 3148 qup_uart9_rx: rx-pins {
3149 pins 3149 pins = "gpio5";
3150 funct 3150 function = "qup9";
3151 }; 3151 };
3152 }; 3152 };
3153 3153
3154 qup_uart10_default: q 3154 qup_uart10_default: qup-uart10-default-state {
3155 qup_uart10_tx 3155 qup_uart10_tx: tx-pins {
3156 pins 3156 pins = "gpio53";
3157 funct 3157 function = "qup10";
3158 }; 3158 };
3159 3159
3160 qup_uart10_rx 3160 qup_uart10_rx: rx-pins {
3161 pins 3161 pins = "gpio54";
3162 funct 3162 function = "qup10";
3163 }; 3163 };
3164 }; 3164 };
3165 3165
3166 qup_uart11_default: q 3166 qup_uart11_default: qup-uart11-default-state {
3167 qup_uart11_tx 3167 qup_uart11_tx: tx-pins {
3168 pins 3168 pins = "gpio33";
3169 funct 3169 function = "qup11";
3170 }; 3170 };
3171 3171
3172 qup_uart11_rx 3172 qup_uart11_rx: rx-pins {
3173 pins 3173 pins = "gpio34";
3174 funct 3174 function = "qup11";
3175 }; 3175 };
3176 }; 3176 };
3177 3177
3178 qup_uart12_default: q 3178 qup_uart12_default: qup-uart12-default-state {
3179 qup_uart12_tx 3179 qup_uart12_tx: tx-pins {
3180 pins 3180 pins = "gpio51";
3181 funct 3181 function = "qup0";
3182 }; 3182 };
3183 3183
3184 qup_uart12_rx 3184 qup_uart12_rx: rx-pins {
3185 pins 3185 pins = "gpio52";
3186 funct 3186 function = "qup0";
3187 }; 3187 };
3188 }; 3188 };
3189 3189
3190 qup_uart13_default: q 3190 qup_uart13_default: qup-uart13-default-state {
3191 qup_uart13_tx 3191 qup_uart13_tx: tx-pins {
3192 pins 3192 pins = "gpio107";
3193 funct 3193 function = "qup13";
3194 }; 3194 };
3195 3195
3196 qup_uart13_rx 3196 qup_uart13_rx: rx-pins {
3197 pins 3197 pins = "gpio108";
3198 funct 3198 function = "qup13";
3199 }; 3199 };
3200 }; 3200 };
3201 3201
3202 qup_uart14_default: q 3202 qup_uart14_default: qup-uart14-default-state {
3203 qup_uart14_tx 3203 qup_uart14_tx: tx-pins {
3204 pins 3204 pins = "gpio31";
3205 funct 3205 function = "qup14";
3206 }; 3206 };
3207 3207
3208 qup_uart14_rx 3208 qup_uart14_rx: rx-pins {
3209 pins 3209 pins = "gpio32";
3210 funct 3210 function = "qup14";
3211 }; 3211 };
3212 }; 3212 };
3213 3213
3214 qup_uart15_default: q 3214 qup_uart15_default: qup-uart15-default-state {
3215 qup_uart15_tx 3215 qup_uart15_tx: tx-pins {
3216 pins 3216 pins = "gpio83";
3217 funct 3217 function = "qup15";
3218 }; 3218 };
3219 3219
3220 qup_uart15_rx 3220 qup_uart15_rx: rx-pins {
3221 pins 3221 pins = "gpio84";
3222 funct 3222 function = "qup15";
3223 }; 3223 };
3224 }; 3224 };
3225 3225
3226 quat_mi2s_sleep: quat 3226 quat_mi2s_sleep: quat-mi2s-sleep-state {
3227 pins = "gpio5 3227 pins = "gpio58", "gpio59";
3228 function = "g 3228 function = "gpio";
3229 drive-strengt 3229 drive-strength = <2>;
3230 bias-pull-dow 3230 bias-pull-down;
3231 }; 3231 };
3232 3232
3233 quat_mi2s_active: qua 3233 quat_mi2s_active: quat-mi2s-active-state {
3234 pins = "gpio5 3234 pins = "gpio58", "gpio59";
3235 function = "q 3235 function = "qua_mi2s";
3236 drive-strengt 3236 drive-strength = <8>;
3237 bias-disable; 3237 bias-disable;
3238 output-high; 3238 output-high;
3239 }; 3239 };
3240 3240
3241 quat_mi2s_sd0_sleep: 3241 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3242 pins = "gpio6 3242 pins = "gpio60";
3243 function = "g 3243 function = "gpio";
3244 drive-strengt 3244 drive-strength = <2>;
3245 bias-pull-dow 3245 bias-pull-down;
3246 }; 3246 };
3247 3247
3248 quat_mi2s_sd0_active: 3248 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3249 pins = "gpio6 3249 pins = "gpio60";
3250 function = "q 3250 function = "qua_mi2s";
3251 drive-strengt 3251 drive-strength = <8>;
3252 bias-disable; 3252 bias-disable;
3253 }; 3253 };
3254 3254
3255 quat_mi2s_sd1_sleep: 3255 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3256 pins = "gpio6 3256 pins = "gpio61";
3257 function = "g 3257 function = "gpio";
3258 drive-strengt 3258 drive-strength = <2>;
3259 bias-pull-dow 3259 bias-pull-down;
3260 }; 3260 };
3261 3261
3262 quat_mi2s_sd1_active: 3262 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3263 pins = "gpio6 3263 pins = "gpio61";
3264 function = "q 3264 function = "qua_mi2s";
3265 drive-strengt 3265 drive-strength = <8>;
3266 bias-disable; 3266 bias-disable;
3267 }; 3267 };
3268 3268
3269 quat_mi2s_sd2_sleep: 3269 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3270 pins = "gpio6 3270 pins = "gpio62";
3271 function = "g 3271 function = "gpio";
3272 drive-strengt 3272 drive-strength = <2>;
3273 bias-pull-dow 3273 bias-pull-down;
3274 }; 3274 };
3275 3275
3276 quat_mi2s_sd2_active: 3276 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3277 pins = "gpio6 3277 pins = "gpio62";
3278 function = "q 3278 function = "qua_mi2s";
3279 drive-strengt 3279 drive-strength = <8>;
3280 bias-disable; 3280 bias-disable;
3281 }; 3281 };
3282 3282
3283 quat_mi2s_sd3_sleep: 3283 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3284 pins = "gpio6 3284 pins = "gpio63";
3285 function = "g 3285 function = "gpio";
3286 drive-strengt 3286 drive-strength = <2>;
3287 bias-pull-dow 3287 bias-pull-down;
3288 }; 3288 };
3289 3289
3290 quat_mi2s_sd3_active: 3290 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3291 pins = "gpio6 3291 pins = "gpio63";
3292 function = "q 3292 function = "qua_mi2s";
3293 drive-strengt 3293 drive-strength = <8>;
3294 bias-disable; 3294 bias-disable;
3295 }; 3295 };
3296 }; 3296 };
3297 3297
3298 mss_pil: remoteproc@4080000 { 3298 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 3299 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 3300 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 3301 reg-names = "qdsp6", "rmb";
3302 3302
3303 interrupts-extended = 3303 interrupts-extended =
3304 <&intc GIC_SP 3304 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 3305 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 3306 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 3307 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 3308 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 3309 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 3310 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 3311 "handover", "stop-ack",
3312 "sh 3312 "shutdown-ack";
3313 3313
3314 clocks = <&gcc GCC_MS 3314 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 3315 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 3316 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 3317 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 3318 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 3319 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 3320 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 3321 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 3322 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 3323 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 3324
3325 qcom,qmp = <&aoss_qmp 3325 qcom,qmp = <&aoss_qmp>;
3326 3326
3327 qcom,smem-states = <& 3327 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 3328 qcom,smem-state-names = "stop";
3329 3329
3330 resets = <&aoss_reset 3330 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 3331 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 3332 reset-names = "mss_restart", "pdc_reset";
3333 3333
3334 qcom,halt-regs = <&tc 3334 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3335 3335
3336 power-domains = <&rpm 3336 power-domains = <&rpmhpd SDM845_CX>,
3337 <&rpm 3337 <&rpmhpd SDM845_MX>,
3338 <&rpm 3338 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = 3339 power-domain-names = "cx", "mx", "mss";
3340 3340
3341 status = "disabled"; 3341 status = "disabled";
3342 3342
3343 mba { 3343 mba {
3344 memory-region 3344 memory-region = <&mba_region>;
3345 }; 3345 };
3346 3346
3347 mpss { 3347 mpss {
3348 memory-region 3348 memory-region = <&mpss_region>;
3349 }; 3349 };
3350 3350
3351 metadata { 3351 metadata {
3352 memory-region 3352 memory-region = <&mdata_mem>;
3353 }; 3353 };
3354 3354
3355 glink-edge { 3355 glink-edge {
3356 interrupts = 3356 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3357 label = "modem";
3358 qcom,remote-p 3358 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3359 mboxes = <&apss_shared 12>;
3360 }; 3360 };
3361 }; 3361 };
3362 3362
3363 gpucc: clock-controller@50900 3363 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3364 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3365 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3366 #clock-cells = <1>;
3367 #reset-cells = <1>; 3367 #reset-cells = <1>;
3368 #power-domain-cells = 3368 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3369 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3370 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3371 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3372 clock-names = "bi_tcxo",
3373 "gcc_gp 3373 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3374 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3375 };
3376 3376
3377 slpi_pas: remoteproc@5c00000 3377 slpi_pas: remoteproc@5c00000 {
3378 compatible = "qcom,sd 3378 compatible = "qcom,sdm845-slpi-pas";
3379 reg = <0 0x5c00000 0 3379 reg = <0 0x5c00000 0 0x4000>;
3380 3380
3381 interrupts-extended = 3381 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3382 3382 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3383 3383 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3384 3384 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3385 3385 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3386 interrupt-names = "wd 3386 interrupt-names = "wdog", "fatal", "ready",
3387 3387 "handover", "stop-ack";
3388 3388
3389 clocks = <&rpmhcc RPM 3389 clocks = <&rpmhcc RPMH_CXO_CLK>;
3390 clock-names = "xo"; 3390 clock-names = "xo";
3391 3391
3392 qcom,qmp = <&aoss_qmp 3392 qcom,qmp = <&aoss_qmp>;
3393 3393
3394 power-domains = <&rpm 3394 power-domains = <&rpmhpd SDM845_LCX>,
3395 <&rpm 3395 <&rpmhpd SDM845_LMX>;
3396 power-domain-names = 3396 power-domain-names = "lcx", "lmx";
3397 3397
3398 memory-region = <&slp 3398 memory-region = <&slpi_mem>;
3399 3399
3400 qcom,smem-states = <& 3400 qcom,smem-states = <&slpi_smp2p_out 0>;
3401 qcom,smem-state-names 3401 qcom,smem-state-names = "stop";
3402 3402
3403 status = "disabled"; 3403 status = "disabled";
3404 3404
3405 glink-edge { 3405 glink-edge {
3406 interrupts = 3406 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3407 label = "dsps 3407 label = "dsps";
3408 qcom,remote-p 3408 qcom,remote-pid = <3>;
3409 mboxes = <&ap 3409 mboxes = <&apss_shared 24>;
3410 3410
3411 fastrpc { 3411 fastrpc {
3412 compa 3412 compatible = "qcom,fastrpc";
3413 qcom, 3413 qcom,glink-channels = "fastrpcglink-apps-dsp";
3414 label 3414 label = "sdsp";
3415 qcom, 3415 qcom,non-secure-domain;
3416 qcom, 3416 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3417 3417 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3418 memor 3418 memory-region = <&fastrpc_mem>;
3419 #addr 3419 #address-cells = <1>;
3420 #size 3420 #size-cells = <0>;
3421 3421
3422 compu 3422 compute-cb@0 {
3423 3423 compatible = "qcom,fastrpc-compute-cb";
3424 3424 reg = <0>;
3425 }; 3425 };
3426 }; 3426 };
3427 }; 3427 };
3428 }; 3428 };
3429 3429
3430 stm@6002000 { 3430 stm@6002000 {
3431 compatible = "arm,cor 3431 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3432 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3433 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3434 reg-names = "stm-base", "stm-stimulus-base";
3435 3435
3436 clocks = <&aoss_qmp>; 3436 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3437 clock-names = "apb_pclk";
3438 3438
3439 out-ports { 3439 out-ports {
3440 port { 3440 port {
3441 stm_o 3441 stm_out: endpoint {
3442 3442 remote-endpoint =
3443 3443 <&funnel0_in7>;
3444 }; 3444 };
3445 }; 3445 };
3446 }; 3446 };
3447 }; 3447 };
3448 3448
3449 funnel@6041000 { 3449 funnel@6041000 {
3450 compatible = "arm,cor 3450 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3451 reg = <0 0x06041000 0 0x1000>;
3452 3452
3453 clocks = <&aoss_qmp>; 3453 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3454 clock-names = "apb_pclk";
3455 3455
3456 out-ports { 3456 out-ports {
3457 port { 3457 port {
3458 funne 3458 funnel0_out: endpoint {
3459 3459 remote-endpoint =
3460 3460 <&merge_funnel_in0>;
3461 }; 3461 };
3462 }; 3462 };
3463 }; 3463 };
3464 3464
3465 in-ports { 3465 in-ports {
3466 #address-cell 3466 #address-cells = <1>;
3467 #size-cells = 3467 #size-cells = <0>;
3468 3468
3469 port@7 { 3469 port@7 {
3470 reg = 3470 reg = <7>;
3471 funne 3471 funnel0_in7: endpoint {
3472 3472 remote-endpoint = <&stm_out>;
3473 }; 3473 };
3474 }; 3474 };
3475 }; 3475 };
3476 }; 3476 };
3477 3477
3478 funnel@6043000 { 3478 funnel@6043000 {
3479 compatible = "arm,cor 3479 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3480 reg = <0 0x06043000 0 0x1000>;
3481 3481
3482 clocks = <&aoss_qmp>; 3482 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3483 clock-names = "apb_pclk";
3484 3484
3485 out-ports { 3485 out-ports {
3486 port { 3486 port {
3487 funne 3487 funnel2_out: endpoint {
3488 3488 remote-endpoint =
3489 3489 <&merge_funnel_in2>;
3490 }; 3490 };
3491 }; 3491 };
3492 }; 3492 };
3493 3493
3494 in-ports { 3494 in-ports {
3495 #address-cell 3495 #address-cells = <1>;
3496 #size-cells = 3496 #size-cells = <0>;
3497 3497
3498 port@5 { 3498 port@5 {
3499 reg = 3499 reg = <5>;
3500 funne 3500 funnel2_in5: endpoint {
3501 3501 remote-endpoint =
3502 3502 <&apss_merge_funnel_out>;
3503 }; 3503 };
3504 }; 3504 };
3505 }; 3505 };
3506 }; 3506 };
3507 3507
3508 funnel@6045000 { 3508 funnel@6045000 {
3509 compatible = "arm,cor 3509 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3510 reg = <0 0x06045000 0 0x1000>;
3511 3511
3512 clocks = <&aoss_qmp>; 3512 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3513 clock-names = "apb_pclk";
3514 3514
3515 out-ports { 3515 out-ports {
3516 port { 3516 port {
3517 merge 3517 merge_funnel_out: endpoint {
3518 3518 remote-endpoint = <&etf_in>;
3519 }; 3519 };
3520 }; 3520 };
3521 }; 3521 };
3522 3522
3523 in-ports { 3523 in-ports {
3524 #address-cell 3524 #address-cells = <1>;
3525 #size-cells = 3525 #size-cells = <0>;
3526 3526
3527 port@0 { 3527 port@0 {
3528 reg = 3528 reg = <0>;
3529 merge 3529 merge_funnel_in0: endpoint {
3530 3530 remote-endpoint =
3531 3531 <&funnel0_out>;
3532 }; 3532 };
3533 }; 3533 };
3534 3534
3535 port@2 { 3535 port@2 {
3536 reg = 3536 reg = <2>;
3537 merge 3537 merge_funnel_in2: endpoint {
3538 3538 remote-endpoint =
3539 3539 <&funnel2_out>;
3540 }; 3540 };
3541 }; 3541 };
3542 }; 3542 };
3543 }; 3543 };
3544 3544
3545 replicator@6046000 { 3545 replicator@6046000 {
3546 compatible = "arm,cor 3546 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3547 reg = <0 0x06046000 0 0x1000>;
3548 3548
3549 clocks = <&aoss_qmp>; 3549 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3550 clock-names = "apb_pclk";
3551 3551
3552 out-ports { 3552 out-ports {
3553 port { 3553 port {
3554 repli 3554 replicator_out: endpoint {
3555 3555 remote-endpoint = <&etr_in>;
3556 }; 3556 };
3557 }; 3557 };
3558 }; 3558 };
3559 3559
3560 in-ports { 3560 in-ports {
3561 port { 3561 port {
3562 repli 3562 replicator_in: endpoint {
3563 3563 remote-endpoint = <&etf_out>;
3564 }; 3564 };
3565 }; 3565 };
3566 }; 3566 };
3567 }; 3567 };
3568 3568
3569 etf@6047000 { 3569 etf@6047000 {
3570 compatible = "arm,cor 3570 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3571 reg = <0 0x06047000 0 0x1000>;
3572 3572
3573 clocks = <&aoss_qmp>; 3573 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3574 clock-names = "apb_pclk";
3575 3575
3576 out-ports { 3576 out-ports {
3577 port { 3577 port {
3578 etf_o 3578 etf_out: endpoint {
3579 3579 remote-endpoint =
3580 3580 <&replicator_in>;
3581 }; 3581 };
3582 }; 3582 };
3583 }; 3583 };
3584 3584
3585 in-ports { 3585 in-ports {
3586 3586
3587 port { 3587 port {
3588 etf_i 3588 etf_in: endpoint {
3589 3589 remote-endpoint =
3590 3590 <&merge_funnel_out>;
3591 }; 3591 };
3592 }; 3592 };
3593 }; 3593 };
3594 }; 3594 };
3595 3595
3596 etr@6048000 { 3596 etr@6048000 {
3597 compatible = "arm,cor 3597 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3598 reg = <0 0x06048000 0 0x1000>;
3599 3599
3600 clocks = <&aoss_qmp>; 3600 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3601 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3602 arm,scatter-gather;
3603 3603
3604 in-ports { 3604 in-ports {
3605 port { 3605 port {
3606 etr_i 3606 etr_in: endpoint {
3607 3607 remote-endpoint =
3608 3608 <&replicator_out>;
3609 }; 3609 };
3610 }; 3610 };
3611 }; 3611 };
3612 }; 3612 };
3613 3613
3614 etm@7040000 { 3614 etm@7040000 {
3615 compatible = "arm,cor 3615 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3616 reg = <0 0x07040000 0 0x1000>;
3617 3617
3618 cpu = <&CPU0>; 3618 cpu = <&CPU0>;
3619 3619
3620 clocks = <&aoss_qmp>; 3620 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3621 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3622 arm,coresight-loses-context-with-cpu;
3623 3623
3624 out-ports { 3624 out-ports {
3625 port { 3625 port {
3626 etm0_ 3626 etm0_out: endpoint {
3627 3627 remote-endpoint =
3628 3628 <&apss_funnel_in0>;
3629 }; 3629 };
3630 }; 3630 };
3631 }; 3631 };
3632 }; 3632 };
3633 3633
3634 etm@7140000 { 3634 etm@7140000 {
3635 compatible = "arm,cor 3635 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3636 reg = <0 0x07140000 0 0x1000>;
3637 3637
3638 cpu = <&CPU1>; 3638 cpu = <&CPU1>;
3639 3639
3640 clocks = <&aoss_qmp>; 3640 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3641 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3642 arm,coresight-loses-context-with-cpu;
3643 3643
3644 out-ports { 3644 out-ports {
3645 port { 3645 port {
3646 etm1_ 3646 etm1_out: endpoint {
3647 3647 remote-endpoint =
3648 3648 <&apss_funnel_in1>;
3649 }; 3649 };
3650 }; 3650 };
3651 }; 3651 };
3652 }; 3652 };
3653 3653
3654 etm@7240000 { 3654 etm@7240000 {
3655 compatible = "arm,cor 3655 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3656 reg = <0 0x07240000 0 0x1000>;
3657 3657
3658 cpu = <&CPU2>; 3658 cpu = <&CPU2>;
3659 3659
3660 clocks = <&aoss_qmp>; 3660 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3661 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3662 arm,coresight-loses-context-with-cpu;
3663 3663
3664 out-ports { 3664 out-ports {
3665 port { 3665 port {
3666 etm2_ 3666 etm2_out: endpoint {
3667 3667 remote-endpoint =
3668 3668 <&apss_funnel_in2>;
3669 }; 3669 };
3670 }; 3670 };
3671 }; 3671 };
3672 }; 3672 };
3673 3673
3674 etm@7340000 { 3674 etm@7340000 {
3675 compatible = "arm,cor 3675 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3676 reg = <0 0x07340000 0 0x1000>;
3677 3677
3678 cpu = <&CPU3>; 3678 cpu = <&CPU3>;
3679 3679
3680 clocks = <&aoss_qmp>; 3680 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3681 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3682 arm,coresight-loses-context-with-cpu;
3683 3683
3684 out-ports { 3684 out-ports {
3685 port { 3685 port {
3686 etm3_ 3686 etm3_out: endpoint {
3687 3687 remote-endpoint =
3688 3688 <&apss_funnel_in3>;
3689 }; 3689 };
3690 }; 3690 };
3691 }; 3691 };
3692 }; 3692 };
3693 3693
3694 etm@7440000 { 3694 etm@7440000 {
3695 compatible = "arm,cor 3695 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3696 reg = <0 0x07440000 0 0x1000>;
3697 3697
3698 cpu = <&CPU4>; 3698 cpu = <&CPU4>;
3699 3699
3700 clocks = <&aoss_qmp>; 3700 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3701 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3702 arm,coresight-loses-context-with-cpu;
3703 3703
3704 out-ports { 3704 out-ports {
3705 port { 3705 port {
3706 etm4_ 3706 etm4_out: endpoint {
3707 3707 remote-endpoint =
3708 3708 <&apss_funnel_in4>;
3709 }; 3709 };
3710 }; 3710 };
3711 }; 3711 };
3712 }; 3712 };
3713 3713
3714 etm@7540000 { 3714 etm@7540000 {
3715 compatible = "arm,cor 3715 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3716 reg = <0 0x07540000 0 0x1000>;
3717 3717
3718 cpu = <&CPU5>; 3718 cpu = <&CPU5>;
3719 3719
3720 clocks = <&aoss_qmp>; 3720 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3721 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3722 arm,coresight-loses-context-with-cpu;
3723 3723
3724 out-ports { 3724 out-ports {
3725 port { 3725 port {
3726 etm5_ 3726 etm5_out: endpoint {
3727 3727 remote-endpoint =
3728 3728 <&apss_funnel_in5>;
3729 }; 3729 };
3730 }; 3730 };
3731 }; 3731 };
3732 }; 3732 };
3733 3733
3734 etm@7640000 { 3734 etm@7640000 {
3735 compatible = "arm,cor 3735 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3736 reg = <0 0x07640000 0 0x1000>;
3737 3737
3738 cpu = <&CPU6>; 3738 cpu = <&CPU6>;
3739 3739
3740 clocks = <&aoss_qmp>; 3740 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3741 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3742 arm,coresight-loses-context-with-cpu;
3743 3743
3744 out-ports { 3744 out-ports {
3745 port { 3745 port {
3746 etm6_ 3746 etm6_out: endpoint {
3747 3747 remote-endpoint =
3748 3748 <&apss_funnel_in6>;
3749 }; 3749 };
3750 }; 3750 };
3751 }; 3751 };
3752 }; 3752 };
3753 3753
3754 etm@7740000 { 3754 etm@7740000 {
3755 compatible = "arm,cor 3755 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3756 reg = <0 0x07740000 0 0x1000>;
3757 3757
3758 cpu = <&CPU7>; 3758 cpu = <&CPU7>;
3759 3759
3760 clocks = <&aoss_qmp>; 3760 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3761 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3762 arm,coresight-loses-context-with-cpu;
3763 3763
3764 out-ports { 3764 out-ports {
3765 port { 3765 port {
3766 etm7_ 3766 etm7_out: endpoint {
3767 3767 remote-endpoint =
3768 3768 <&apss_funnel_in7>;
3769 }; 3769 };
3770 }; 3770 };
3771 }; 3771 };
3772 }; 3772 };
3773 3773
3774 funnel@7800000 { /* APSS Funn 3774 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3776 reg = <0 0x07800000 0 0x1000>;
3777 3777
3778 clocks = <&aoss_qmp>; 3778 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3779 clock-names = "apb_pclk";
3780 3780
3781 out-ports { 3781 out-ports {
3782 port { 3782 port {
3783 apss_ 3783 apss_funnel_out: endpoint {
3784 3784 remote-endpoint =
3785 3785 <&apss_merge_funnel_in>;
3786 }; 3786 };
3787 }; 3787 };
3788 }; 3788 };
3789 3789
3790 in-ports { 3790 in-ports {
3791 #address-cell 3791 #address-cells = <1>;
3792 #size-cells = 3792 #size-cells = <0>;
3793 3793
3794 port@0 { 3794 port@0 {
3795 reg = 3795 reg = <0>;
3796 apss_ 3796 apss_funnel_in0: endpoint {
3797 3797 remote-endpoint =
3798 3798 <&etm0_out>;
3799 }; 3799 };
3800 }; 3800 };
3801 3801
3802 port@1 { 3802 port@1 {
3803 reg = 3803 reg = <1>;
3804 apss_ 3804 apss_funnel_in1: endpoint {
3805 3805 remote-endpoint =
3806 3806 <&etm1_out>;
3807 }; 3807 };
3808 }; 3808 };
3809 3809
3810 port@2 { 3810 port@2 {
3811 reg = 3811 reg = <2>;
3812 apss_ 3812 apss_funnel_in2: endpoint {
3813 3813 remote-endpoint =
3814 3814 <&etm2_out>;
3815 }; 3815 };
3816 }; 3816 };
3817 3817
3818 port@3 { 3818 port@3 {
3819 reg = 3819 reg = <3>;
3820 apss_ 3820 apss_funnel_in3: endpoint {
3821 3821 remote-endpoint =
3822 3822 <&etm3_out>;
3823 }; 3823 };
3824 }; 3824 };
3825 3825
3826 port@4 { 3826 port@4 {
3827 reg = 3827 reg = <4>;
3828 apss_ 3828 apss_funnel_in4: endpoint {
3829 3829 remote-endpoint =
3830 3830 <&etm4_out>;
3831 }; 3831 };
3832 }; 3832 };
3833 3833
3834 port@5 { 3834 port@5 {
3835 reg = 3835 reg = <5>;
3836 apss_ 3836 apss_funnel_in5: endpoint {
3837 3837 remote-endpoint =
3838 3838 <&etm5_out>;
3839 }; 3839 };
3840 }; 3840 };
3841 3841
3842 port@6 { 3842 port@6 {
3843 reg = 3843 reg = <6>;
3844 apss_ 3844 apss_funnel_in6: endpoint {
3845 3845 remote-endpoint =
3846 3846 <&etm6_out>;
3847 }; 3847 };
3848 }; 3848 };
3849 3849
3850 port@7 { 3850 port@7 {
3851 reg = 3851 reg = <7>;
3852 apss_ 3852 apss_funnel_in7: endpoint {
3853 3853 remote-endpoint =
3854 3854 <&etm7_out>;
3855 }; 3855 };
3856 }; 3856 };
3857 }; 3857 };
3858 }; 3858 };
3859 3859
3860 funnel@7810000 { 3860 funnel@7810000 {
3861 compatible = "arm,cor 3861 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3862 reg = <0 0x07810000 0 0x1000>;
3863 3863
3864 clocks = <&aoss_qmp>; 3864 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3865 clock-names = "apb_pclk";
3866 3866
3867 out-ports { 3867 out-ports {
3868 port { 3868 port {
3869 apss_ 3869 apss_merge_funnel_out: endpoint {
3870 3870 remote-endpoint =
3871 3871 <&funnel2_in5>;
3872 }; 3872 };
3873 }; 3873 };
3874 }; 3874 };
3875 3875
3876 in-ports { 3876 in-ports {
3877 port { 3877 port {
3878 apss_ 3878 apss_merge_funnel_in: endpoint {
3879 3879 remote-endpoint =
3880 3880 <&apss_funnel_out>;
3881 }; 3881 };
3882 }; 3882 };
3883 }; 3883 };
3884 }; 3884 };
3885 3885
3886 sdhc_2: mmc@8804000 { 3886 sdhc_2: mmc@8804000 {
3887 compatible = "qcom,sd 3887 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3888 reg = <0 0x08804000 0 0x1000>;
3889 3889
3890 interrupts = <GIC_SPI 3890 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3891 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3892 interrupt-names = "hc_irq", "pwr_irq";
3893 3893
3894 clocks = <&gcc GCC_SD 3894 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD 3895 <&gcc GCC_SDCC2_APPS_CLK>,
3896 <&rpmhcc RPM 3896 <&rpmhcc RPMH_CXO_CLK>;
3897 clock-names = "iface" 3897 clock-names = "iface", "core", "xo";
3898 iommus = <&apps_smmu 3898 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3899 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3900 operating-points-v2 = <&sdhc2_opp_table>;
3901 3901
3902 status = "disabled"; 3902 status = "disabled";
3903 3903
3904 sdhc2_opp_table: opp- 3904 sdhc2_opp_table: opp-table {
3905 compatible = 3905 compatible = "operating-points-v2";
3906 3906
3907 opp-9600000 { 3907 opp-9600000 {
3908 opp-h 3908 opp-hz = /bits/ 64 <9600000>;
3909 requi 3909 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3910 };
3911 3911
3912 opp-19200000 3912 opp-19200000 {
3913 opp-h 3913 opp-hz = /bits/ 64 <19200000>;
3914 requi 3914 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3915 };
3916 3916
3917 opp-100000000 3917 opp-100000000 {
3918 opp-h 3918 opp-hz = /bits/ 64 <100000000>;
3919 requi 3919 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3920 };
3921 3921
3922 opp-201500000 3922 opp-201500000 {
3923 opp-h 3923 opp-hz = /bits/ 64 <201500000>;
3924 requi 3924 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3925 };
3926 }; 3926 };
3927 }; 3927 };
3928 3928
3929 qspi: spi@88df000 { 3929 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3930 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3931 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu 3932 iommus = <&apps_smmu 0x160 0x0>;
3933 #address-cells = <1>; 3933 #address-cells = <1>;
3934 #size-cells = <0>; 3934 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3935 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3936 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3937 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3938 clock-names = "iface", "core";
3939 power-domains = <&rpm 3939 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3940 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3941 status = "disabled";
3942 }; 3942 };
3943 3943
3944 slim: slim-ngd@171c0000 { 3944 slim: slim-ngd@171c0000 {
3945 compatible = "qcom,sl 3945 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3946 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3947 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3948
3949 dmas = <&slimbam 3>, 3949 dmas = <&slimbam 3>, <&slimbam 4>;
3950 dma-names = "rx", "tx 3950 dma-names = "rx", "tx";
3951 3951
3952 iommus = <&apps_smmu 3952 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3953 #address-cells = <1>;
3954 #size-cells = <0>; 3954 #size-cells = <0>;
3955 status = "disabled"; 3955 status = "disabled";
3956 }; 3956 };
3957 3957
3958 lmh_cluster1: lmh@17d70800 { 3958 lmh_cluster1: lmh@17d70800 {
3959 compatible = "qcom,sd 3959 compatible = "qcom,sdm845-lmh";
3960 reg = <0 0x17d70800 0 3960 reg = <0 0x17d70800 0 0x400>;
3961 interrupts = <GIC_SPI 3961 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962 cpus = <&CPU4>; 3962 cpus = <&CPU4>;
3963 qcom,lmh-temp-arm-mil 3963 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-mil 3964 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-mi 3965 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller; 3966 interrupt-controller;
3967 #interrupt-cells = <1 3967 #interrupt-cells = <1>;
3968 }; 3968 };
3969 3969
3970 lmh_cluster0: lmh@17d78800 { 3970 lmh_cluster0: lmh@17d78800 {
3971 compatible = "qcom,sd 3971 compatible = "qcom,sdm845-lmh";
3972 reg = <0 0x17d78800 0 3972 reg = <0 0x17d78800 0 0x400>;
3973 interrupts = <GIC_SPI 3973 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974 cpus = <&CPU0>; 3974 cpus = <&CPU0>;
3975 qcom,lmh-temp-arm-mil 3975 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-mil 3976 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-mi 3977 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller; 3978 interrupt-controller;
3979 #interrupt-cells = <1 3979 #interrupt-cells = <1>;
3980 }; 3980 };
3981 3981
3982 usb_1_hsphy: phy@88e2000 { 3982 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3983 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3984 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3985 status = "disabled";
3986 #phy-cells = <0>; 3986 #phy-cells = <0>;
3987 3987
3988 clocks = <&gcc GCC_US 3988 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3989 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3990 clock-names = "cfg_ahb", "ref";
3991 3991
3992 resets = <&gcc GCC_QU 3992 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3993
3994 nvmem-cells = <&qusb2 3994 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3995 };
3996 3996
3997 usb_2_hsphy: phy@88e3000 { 3997 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3998 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3999 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 4000 status = "disabled";
4001 #phy-cells = <0>; 4001 #phy-cells = <0>;
4002 4002
4003 clocks = <&gcc GCC_US 4003 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 4004 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 4005 clock-names = "cfg_ahb", "ref";
4006 4006
4007 resets = <&gcc GCC_QU 4007 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 4008
4009 nvmem-cells = <&qusb2 4009 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 4010 };
4011 4011
4012 usb_1_qmpphy: phy@88e8000 { 4012 usb_1_qmpphy: phy@88e8000 {
4013 compatible = "qcom,sd 4013 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4014 reg = <0 0x088e8000 0 4014 reg = <0 0x088e8000 0 0x3000>;
4015 status = "disabled"; 4015 status = "disabled";
4016 4016
4017 clocks = <&gcc GCC_US 4017 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
4018 <&gcc GCC_US 4018 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US 4019 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
4020 <&gcc GCC_US 4020 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
4021 <&gcc GCC_US 4021 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
4022 clock-names = "aux", 4022 clock-names = "aux",
4023 "ref", 4023 "ref",
4024 "com_au 4024 "com_aux",
4025 "usb3_p 4025 "usb3_pipe",
4026 "cfg_ah 4026 "cfg_ahb";
4027 4027
4028 resets = <&gcc GCC_US 4028 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4029 <&gcc GCC_US 4029 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4030 reset-names = "phy", 4030 reset-names = "phy", "common";
4031 4031
4032 #clock-cells = <1>; 4032 #clock-cells = <1>;
4033 #phy-cells = <1>; 4033 #phy-cells = <1>;
4034 orientation-switch; 4034 orientation-switch;
4035 4035
4036 ports { 4036 ports {
4037 #address-cell 4037 #address-cells = <1>;
4038 #size-cells = 4038 #size-cells = <0>;
4039 4039
4040 port@0 { 4040 port@0 {
4041 reg = 4041 reg = <0>;
4042 4042
4043 usb_1 4043 usb_1_qmpphy_out: endpoint {
4044 }; 4044 };
4045 }; 4045 };
4046 4046
4047 port@1 { 4047 port@1 {
4048 reg = 4048 reg = <1>;
4049 4049
4050 usb_1 4050 usb_1_qmpphy_usb_ss_in: endpoint {
4051 4051 remote-endpoint = <&usb_1_dwc3_ss>;
4052 }; 4052 };
4053 }; 4053 };
4054 4054
4055 port@2 { 4055 port@2 {
4056 reg = 4056 reg = <2>;
4057 4057
4058 usb_1 4058 usb_1_qmpphy_dp_in: endpoint {
4059 4059 remote-endpoint = <&dp_out>;
4060 }; 4060 };
4061 }; 4061 };
4062 }; 4062 };
4063 }; 4063 };
4064 4064
4065 usb_2_qmpphy: phy@88eb000 { 4065 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 4066 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 4067 reg = <0 0x088eb000 0 0x1000>;
4068 4068
4069 clocks = <&gcc GCC_US 4069 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 4070 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 4071 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US 4072 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
4073 <&gcc GCC_US 4073 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4074 clock-names = "aux", 4074 clock-names = "aux",
4075 "cfg_ah 4075 "cfg_ahb",
4076 "ref", 4076 "ref",
4077 "com_au 4077 "com_aux",
4078 "pipe"; 4078 "pipe";
4079 clock-output-names = 4079 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4080 #clock-cells = <0>; 4080 #clock-cells = <0>;
4081 #phy-cells = <0>; 4081 #phy-cells = <0>;
4082 4082
4083 resets = <&gcc GCC_US 4083 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
4084 <&gcc GCC_US 4084 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
4085 reset-names = "phy", 4085 reset-names = "phy",
4086 "phy_ph 4086 "phy_phy";
4087 4087
4088 status = "disabled"; 4088 status = "disabled";
4089 }; 4089 };
4090 4090
4091 usb_1: usb@a6f8800 { 4091 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 4092 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 4093 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 4094 status = "disabled";
4095 #address-cells = <2>; 4095 #address-cells = <2>;
4096 #size-cells = <2>; 4096 #size-cells = <2>;
4097 ranges; 4097 ranges;
4098 dma-ranges; 4098 dma-ranges;
4099 4099
4100 clocks = <&gcc GCC_CF 4100 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 4101 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 4102 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US 4103 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4104 <&gcc GCC_US 4104 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4105 clock-names = "cfg_no 4105 clock-names = "cfg_noc",
4106 "core", 4106 "core",
4107 "iface" 4107 "iface",
4108 "sleep" 4108 "sleep",
4109 "mock_u 4109 "mock_utmi";
4110 4110
4111 assigned-clocks = <&g 4111 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 4112 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 4113 assigned-clock-rates = <19200000>, <150000000>;
4114 4114
4115 interrupts-extended = 4115 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4116 4116 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4117 4117 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>,
4118 4118 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
4119 4119 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>;
4120 interrupt-names = "pw 4120 interrupt-names = "pwr_event",
4121 "hs 4121 "hs_phy_irq",
4122 "dp 4122 "dp_hs_phy_irq",
4123 "dm 4123 "dm_hs_phy_irq",
4124 "ss 4124 "ss_phy_irq";
4125 4125
4126 power-domains = <&gcc 4126 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 4127
4128 resets = <&gcc GCC_US 4128 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 4129
4130 interconnects = <&agg 4130 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 4131 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 4132 interconnect-names = "usb-ddr", "apps-usb";
4133 4133
4134 usb_1_dwc3: usb@a6000 4134 usb_1_dwc3: usb@a600000 {
4135 compatible = 4135 compatible = "snps,dwc3";
4136 reg = <0 0x0a 4136 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 4137 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 4138 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 4139 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 4140 snps,dis_enblslpm_quirk;
4141 snps,parkmode 4141 snps,parkmode-disable-ss-quirk;
4142 phys = <&usb_ 4142 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4143 phy-names = " 4143 phy-names = "usb2-phy", "usb3-phy";
4144 4144
4145 ports { 4145 ports {
4146 #addr 4146 #address-cells = <1>;
4147 #size 4147 #size-cells = <0>;
4148 4148
4149 port@ 4149 port@0 {
4150 4150 reg = <0>;
4151 4151
4152 4152 usb_1_dwc3_hs: endpoint {
4153 4153 };
4154 }; 4154 };
4155 4155
4156 port@ 4156 port@1 {
4157 4157 reg = <1>;
4158 4158
4159 4159 usb_1_dwc3_ss: endpoint {
4160 4160 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
4161 4161 };
4162 }; 4162 };
4163 }; 4163 };
4164 }; 4164 };
4165 }; 4165 };
4166 4166
4167 usb_2: usb@a8f8800 { 4167 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 4168 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 4169 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 4170 status = "disabled";
4171 #address-cells = <2>; 4171 #address-cells = <2>;
4172 #size-cells = <2>; 4172 #size-cells = <2>;
4173 ranges; 4173 ranges;
4174 dma-ranges; 4174 dma-ranges;
4175 4175
4176 clocks = <&gcc GCC_CF 4176 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 4177 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 4178 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US 4179 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4180 <&gcc GCC_US 4180 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4181 clock-names = "cfg_no 4181 clock-names = "cfg_noc",
4182 "core", 4182 "core",
4183 "iface" 4183 "iface",
4184 "sleep" 4184 "sleep",
4185 "mock_u 4185 "mock_utmi";
4186 4186
4187 assigned-clocks = <&g 4187 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 4188 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 4189 assigned-clock-rates = <19200000>, <150000000>;
4190 4190
4191 interrupts-extended = 4191 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4192 4192 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4193 4193 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>,
4194 4194 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
4195 4195 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>;
4196 interrupt-names = "pw 4196 interrupt-names = "pwr_event",
4197 "hs 4197 "hs_phy_irq",
4198 "dp 4198 "dp_hs_phy_irq",
4199 "dm 4199 "dm_hs_phy_irq",
4200 "ss 4200 "ss_phy_irq";
4201 4201
4202 power-domains = <&gcc 4202 power-domains = <&gcc USB30_SEC_GDSC>;
4203 4203
4204 resets = <&gcc GCC_US 4204 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 4205
4206 interconnects = <&agg 4206 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 4207 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 4208 interconnect-names = "usb-ddr", "apps-usb";
4209 4209
4210 usb_2_dwc3: usb@a8000 4210 usb_2_dwc3: usb@a800000 {
4211 compatible = 4211 compatible = "snps,dwc3";
4212 reg = <0 0x0a 4212 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 4213 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 4214 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 4215 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 4216 snps,dis_enblslpm_quirk;
4217 snps,parkmode 4217 snps,parkmode-disable-ss-quirk;
4218 phys = <&usb_ 4218 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
4219 phy-names = " 4219 phy-names = "usb2-phy", "usb3-phy";
4220 }; 4220 };
4221 }; 4221 };
4222 4222
4223 venus: video-codec@aa00000 { 4223 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 4224 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 4225 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 4226 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 4227 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 4228 <&videocc VCODEC0_GDSC>,
4229 <&vid 4229 <&videocc VCODEC1_GDSC>,
4230 <&rpm 4230 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 4231 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 4232 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 4233 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 4234 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 4235 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 4236 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 4237 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 4238 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 4239 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 4240 clock-names = "core", "iface", "bus",
4241 "vcodec 4241 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 4242 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 4243 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 4244 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 4245 memory-region = <&venus_mem>;
4246 interconnects = <&mms 4246 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 4247 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 4248 interconnect-names = "video-mem", "cpu-cfg";
4249 4249
4250 status = "disabled"; 4250 status = "disabled";
4251 4251
4252 video-core0 { 4252 video-core0 {
4253 compatible = 4253 compatible = "venus-decoder";
4254 }; 4254 };
4255 4255
4256 video-core1 { 4256 video-core1 {
4257 compatible = 4257 compatible = "venus-encoder";
4258 }; 4258 };
4259 4259
4260 venus_opp_table: opp- 4260 venus_opp_table: opp-table {
4261 compatible = 4261 compatible = "operating-points-v2";
4262 4262
4263 opp-100000000 4263 opp-100000000 {
4264 opp-h 4264 opp-hz = /bits/ 64 <100000000>;
4265 requi 4265 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 4266 };
4267 4267
4268 opp-200000000 4268 opp-200000000 {
4269 opp-h 4269 opp-hz = /bits/ 64 <200000000>;
4270 requi 4270 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 4271 };
4272 4272
4273 opp-320000000 4273 opp-320000000 {
4274 opp-h 4274 opp-hz = /bits/ 64 <320000000>;
4275 requi 4275 required-opps = <&rpmhpd_opp_svs>;
4276 }; 4276 };
4277 4277
4278 opp-380000000 4278 opp-380000000 {
4279 opp-h 4279 opp-hz = /bits/ 64 <380000000>;
4280 requi 4280 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 4281 };
4282 4282
4283 opp-444000000 4283 opp-444000000 {
4284 opp-h 4284 opp-hz = /bits/ 64 <444000000>;
4285 requi 4285 required-opps = <&rpmhpd_opp_nom>;
4286 }; 4286 };
4287 4287
4288 opp-533000097 4288 opp-533000097 {
4289 opp-h 4289 opp-hz = /bits/ 64 <533000097>;
4290 requi 4290 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 4291 };
4292 }; 4292 };
4293 }; 4293 };
4294 4294
4295 videocc: clock-controller@ab0 4295 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 4296 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 4297 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 4298 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 4299 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 4300 #clock-cells = <1>;
4301 #power-domain-cells = 4301 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 4302 #reset-cells = <1>;
4303 }; 4303 };
4304 4304
4305 camss: camss@acb3000 { 4305 camss: camss@acb3000 {
4306 compatible = "qcom,sd 4306 compatible = "qcom,sdm845-camss";
4307 4307
4308 reg = <0 0x0acb3000 0 4308 reg = <0 0x0acb3000 0 0x1000>,
4309 <0 0x0acba000 4309 <0 0x0acba000 0 0x1000>,
4310 <0 0x0acc8000 4310 <0 0x0acc8000 0 0x1000>,
4311 <0 0x0ac65000 4311 <0 0x0ac65000 0 0x1000>,
4312 <0 0x0ac66000 4312 <0 0x0ac66000 0 0x1000>,
4313 <0 0x0ac67000 4313 <0 0x0ac67000 0 0x1000>,
4314 <0 0x0ac68000 4314 <0 0x0ac68000 0 0x1000>,
4315 <0 0x0acaf000 4315 <0 0x0acaf000 0 0x4000>,
4316 <0 0x0acb6000 4316 <0 0x0acb6000 0 0x4000>,
4317 <0 0x0acc4000 4317 <0 0x0acc4000 0 0x4000>;
4318 reg-names = "csid0", 4318 reg-names = "csid0",
4319 "csid1", 4319 "csid1",
4320 "csid2", 4320 "csid2",
4321 "csiphy0", 4321 "csiphy0",
4322 "csiphy1", 4322 "csiphy1",
4323 "csiphy2", 4323 "csiphy2",
4324 "csiphy3", 4324 "csiphy3",
4325 "vfe0", 4325 "vfe0",
4326 "vfe1", 4326 "vfe1",
4327 "vfe_lite"; 4327 "vfe_lite";
4328 4328
4329 interrupts = <GIC_SPI 4329 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 4330 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 4331 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 4332 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 4333 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 4334 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 4335 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 4336 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 4337 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 4338 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 4339 interrupt-names = "csid0",
4340 "csid1", 4340 "csid1",
4341 "csid2", 4341 "csid2",
4342 "csiphy0", 4342 "csiphy0",
4343 "csiphy1", 4343 "csiphy1",
4344 "csiphy2", 4344 "csiphy2",
4345 "csiphy3", 4345 "csiphy3",
4346 "vfe0", 4346 "vfe0",
4347 "vfe1", 4347 "vfe1",
4348 "vfe_lite"; 4348 "vfe_lite";
4349 4349
4350 power-domains = <&clo 4350 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 4351 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 4352 <&clock_camcc TITAN_TOP_GDSC>;
4353 4353
4354 clocks = <&clock_camc 4354 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 4355 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 4356 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 4357 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 4358 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 4359 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 4360 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 4361 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 4362 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 4363 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 4364 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 4365 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 4366 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 4367 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 4368 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 4369 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 4370 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 4371 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 4372 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 4373 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 4374 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 4375 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 4376 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 4377 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 4378 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 4379 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 4380 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4381 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4382 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4383 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4384 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4385 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4386 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4387 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4388 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4389 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4390 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4391 "cpas_ahb",
4392 "cphy_rx_src" 4392 "cphy_rx_src",
4393 "csi0", 4393 "csi0",
4394 "csi0_src", 4394 "csi0_src",
4395 "csi1", 4395 "csi1",
4396 "csi1_src", 4396 "csi1_src",
4397 "csi2", 4397 "csi2",
4398 "csi2_src", 4398 "csi2_src",
4399 "csiphy0", 4399 "csiphy0",
4400 "csiphy0_time 4400 "csiphy0_timer",
4401 "csiphy0_time 4401 "csiphy0_timer_src",
4402 "csiphy1", 4402 "csiphy1",
4403 "csiphy1_time 4403 "csiphy1_timer",
4404 "csiphy1_time 4404 "csiphy1_timer_src",
4405 "csiphy2", 4405 "csiphy2",
4406 "csiphy2_time 4406 "csiphy2_timer",
4407 "csiphy2_time 4407 "csiphy2_timer_src",
4408 "csiphy3", 4408 "csiphy3",
4409 "csiphy3_time 4409 "csiphy3_timer",
4410 "csiphy3_time 4410 "csiphy3_timer_src",
4411 "gcc_camera_a 4411 "gcc_camera_ahb",
4412 "gcc_camera_a 4412 "gcc_camera_axi",
4413 "slow_ahb_src 4413 "slow_ahb_src",
4414 "soc_ahb", 4414 "soc_ahb",
4415 "vfe0_axi", 4415 "vfe0_axi",
4416 "vfe0", 4416 "vfe0",
4417 "vfe0_cphy_rx 4417 "vfe0_cphy_rx",
4418 "vfe0_src", 4418 "vfe0_src",
4419 "vfe1_axi", 4419 "vfe1_axi",
4420 "vfe1", 4420 "vfe1",
4421 "vfe1_cphy_rx 4421 "vfe1_cphy_rx",
4422 "vfe1_src", 4422 "vfe1_src",
4423 "vfe_lite", 4423 "vfe_lite",
4424 "vfe_lite_cph 4424 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4425 "vfe_lite_src";
4426 4426
4427 iommus = <&apps_smmu 4427 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4428 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4429 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4430 <&apps_smmu 0x0c10 0x8>;
4431 4431
4432 status = "disabled"; 4432 status = "disabled";
4433 4433
4434 ports { 4434 ports {
4435 #address-cell 4435 #address-cells = <1>;
4436 #size-cells = 4436 #size-cells = <0>;
4437 4437
4438 port@0 { 4438 port@0 {
4439 reg = 4439 reg = <0>;
4440 }; 4440 };
4441 4441
4442 port@1 { 4442 port@1 {
4443 reg = 4443 reg = <1>;
4444 }; 4444 };
4445 4445
4446 port@2 { 4446 port@2 {
4447 reg = 4447 reg = <2>;
4448 }; 4448 };
4449 4449
4450 port@3 { 4450 port@3 {
4451 reg = 4451 reg = <3>;
4452 }; 4452 };
4453 }; 4453 };
4454 }; 4454 };
4455 4455
4456 cci: cci@ac4a000 { 4456 cci: cci@ac4a000 {
4457 compatible = "qcom,sd 4457 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4458 #address-cells = <1>; 4458 #address-cells = <1>;
4459 #size-cells = <0>; 4459 #size-cells = <0>;
4460 4460
4461 reg = <0 0x0ac4a000 0 4461 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4462 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4463 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4464
4465 clocks = <&clock_camc 4465 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4466 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4467 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4468 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4469 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4470 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4471 clock-names = "camnoc_axi",
4472 "soc_ahb", 4472 "soc_ahb",
4473 "slow_ahb_src 4473 "slow_ahb_src",
4474 "cpas_ahb", 4474 "cpas_ahb",
4475 "cci", 4475 "cci",
4476 "cci_src"; 4476 "cci_src";
4477 4477
4478 assigned-clocks = <&c 4478 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4479 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4480 assigned-clock-rates = <80000000>, <37500000>;
4481 4481
4482 pinctrl-names = "defa 4482 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4483 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4484 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4485
4486 status = "disabled"; 4486 status = "disabled";
4487 4487
4488 cci_i2c0: i2c-bus@0 { 4488 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4489 reg = <0>;
4490 clock-frequen 4490 clock-frequency = <1000000>;
4491 #address-cell 4491 #address-cells = <1>;
4492 #size-cells = 4492 #size-cells = <0>;
4493 }; 4493 };
4494 4494
4495 cci_i2c1: i2c-bus@1 { 4495 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4496 reg = <1>;
4497 clock-frequen 4497 clock-frequency = <1000000>;
4498 #address-cell 4498 #address-cells = <1>;
4499 #size-cells = 4499 #size-cells = <0>;
4500 }; 4500 };
4501 }; 4501 };
4502 4502
4503 clock_camcc: clock-controller 4503 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4504 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4505 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4506 #clock-cells = <1>;
4507 #reset-cells = <1>; 4507 #reset-cells = <1>;
4508 #power-domain-cells = 4508 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM 4509 clocks = <&rpmhcc RPMH_CXO_CLK>;
4510 clock-names = "bi_tcx 4510 clock-names = "bi_tcxo";
4511 }; 4511 };
4512 4512
4513 mdss: display-subsystem@ae000 4513 mdss: display-subsystem@ae00000 {
4514 compatible = "qcom,sd 4514 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4515 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4516 reg-names = "mdss";
4517 4517
4518 power-domains = <&dis 4518 power-domains = <&dispcc MDSS_GDSC>;
4519 4519
4520 clocks = <&dispcc DIS 4520 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521 <&dispcc DIS 4521 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" 4522 clock-names = "iface", "core";
4523 4523
4524 interrupts = <GIC_SPI 4524 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4525 interrupt-controller;
4526 #interrupt-cells = <1 4526 #interrupt-cells = <1>;
4527 4527
4528 interconnects = <&mms 4528 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4529 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4530 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4531
4532 iommus = <&apps_smmu 4532 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4533 <&apps_smmu 0xc80 0x8>;
4534 4534
4535 status = "disabled"; 4535 status = "disabled";
4536 4536
4537 #address-cells = <2>; 4537 #address-cells = <2>;
4538 #size-cells = <2>; 4538 #size-cells = <2>;
4539 ranges; 4539 ranges;
4540 4540
4541 mdss_mdp: display-con 4541 mdss_mdp: display-controller@ae01000 {
4542 compatible = 4542 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4543 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4544 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4545 reg-names = "mdp", "vbif";
4546 4546
4547 clocks = <&gc 4547 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548 <&di 4548 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549 <&di 4549 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4550 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4551 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = 4552 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553 4553
4554 assigned-cloc 4554 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555 assigned-cloc 4555 assigned-clock-rates = <19200000>;
4556 operating-poi 4556 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4557 power-domains = <&rpmhpd SDM845_CX>;
4558 4558
4559 interrupt-par 4559 interrupt-parent = <&mdss>;
4560 interrupts = 4560 interrupts = <0>;
4561 4561
4562 ports { 4562 ports {
4563 #addr 4563 #address-cells = <1>;
4564 #size 4564 #size-cells = <0>;
4565 4565
4566 port@ 4566 port@0 {
4567 4567 reg = <0>;
4568 4568 dpu_intf0_out: endpoint {
4569 4569 remote-endpoint = <&dp_in>;
4570 4570 };
4571 }; 4571 };
4572 4572
4573 port@ 4573 port@1 {
4574 4574 reg = <1>;
4575 4575 dpu_intf1_out: endpoint {
4576 4576 remote-endpoint = <&mdss_dsi0_in>;
4577 4577 };
4578 }; 4578 };
4579 4579
4580 port@ 4580 port@2 {
4581 4581 reg = <2>;
4582 4582 dpu_intf2_out: endpoint {
4583 4583 remote-endpoint = <&mdss_dsi1_in>;
4584 4584 };
4585 }; 4585 };
4586 }; 4586 };
4587 4587
4588 mdp_opp_table 4588 mdp_opp_table: opp-table {
4589 compa 4589 compatible = "operating-points-v2";
4590 4590
4591 opp-1 4591 opp-19200000 {
4592 4592 opp-hz = /bits/ 64 <19200000>;
4593 4593 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4594 };
4595 4595
4596 opp-1 4596 opp-171428571 {
4597 4597 opp-hz = /bits/ 64 <171428571>;
4598 4598 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4599 };
4600 4600
4601 opp-3 4601 opp-344000000 {
4602 4602 opp-hz = /bits/ 64 <344000000>;
4603 4603 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4604 };
4605 4605
4606 opp-4 4606 opp-430000000 {
4607 4607 opp-hz = /bits/ 64 <430000000>;
4608 4608 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4609 };
4610 }; 4610 };
4611 }; 4611 };
4612 4612
4613 mdss_dp: displayport- 4613 mdss_dp: displayport-controller@ae90000 {
4614 status = "dis 4614 status = "disabled";
4615 compatible = 4615 compatible = "qcom,sdm845-dp";
4616 4616
4617 reg = <0 0x0a 4617 reg = <0 0x0ae90000 0 0x200>,
4618 <0 0x0a 4618 <0 0x0ae90200 0 0x200>,
4619 <0 0x0a 4619 <0 0x0ae90400 0 0x600>,
4620 <0 0x0a 4620 <0 0x0ae90a00 0 0x600>,
4621 <0 0x0a 4621 <0 0x0ae91000 0 0x600>;
4622 4622
4623 interrupt-par 4623 interrupt-parent = <&mdss>;
4624 interrupts = 4624 interrupts = <12>;
4625 4625
4626 clocks = <&di 4626 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4627 <&di 4627 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4628 <&di 4628 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4629 <&di 4629 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4630 <&di 4630 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4631 clock-names = 4631 clock-names = "core_iface", "core_aux", "ctrl_link",
4632 4632 "ctrl_link_iface", "stream_pixel";
4633 assigned-cloc 4633 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4634 4634 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4635 assigned-cloc 4635 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4636 4636 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4637 phys = <&usb_ 4637 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4638 phy-names = " 4638 phy-names = "dp";
4639 4639
4640 operating-poi 4640 operating-points-v2 = <&dp_opp_table>;
4641 power-domains 4641 power-domains = <&rpmhpd SDM845_CX>;
4642 4642
4643 ports { 4643 ports {
4644 #addr 4644 #address-cells = <1>;
4645 #size 4645 #size-cells = <0>;
4646 port@ 4646 port@0 {
4647 4647 reg = <0>;
4648 4648 dp_in: endpoint {
4649 4649 remote-endpoint = <&dpu_intf0_out>;
4650 4650 };
4651 }; 4651 };
4652 4652
4653 port@ 4653 port@1 {
4654 4654 reg = <1>;
4655 4655 dp_out: endpoint {
4656 4656 remote-endpoint = <&usb_1_qmpphy_dp_in>;
4657 4657 };
4658 }; 4658 };
4659 }; 4659 };
4660 4660
4661 dp_opp_table: 4661 dp_opp_table: opp-table {
4662 compa 4662 compatible = "operating-points-v2";
4663 4663
4664 opp-1 4664 opp-162000000 {
4665 4665 opp-hz = /bits/ 64 <162000000>;
4666 4666 required-opps = <&rpmhpd_opp_low_svs>;
4667 }; 4667 };
4668 4668
4669 opp-2 4669 opp-270000000 {
4670 4670 opp-hz = /bits/ 64 <270000000>;
4671 4671 required-opps = <&rpmhpd_opp_svs>;
4672 }; 4672 };
4673 4673
4674 opp-5 4674 opp-540000000 {
4675 4675 opp-hz = /bits/ 64 <540000000>;
4676 4676 required-opps = <&rpmhpd_opp_svs_l1>;
4677 }; 4677 };
4678 4678
4679 opp-8 4679 opp-810000000 {
4680 4680 opp-hz = /bits/ 64 <810000000>;
4681 4681 required-opps = <&rpmhpd_opp_nom>;
4682 }; 4682 };
4683 }; 4683 };
4684 }; 4684 };
4685 4685
4686 mdss_dsi0: dsi@ae9400 4686 mdss_dsi0: dsi@ae94000 {
4687 compatible = 4687 compatible = "qcom,sdm845-dsi-ctrl",
4688 4688 "qcom,mdss-dsi-ctrl";
4689 reg = <0 0x0a 4689 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4690 reg-names = "dsi_ctrl";
4691 4691
4692 interrupt-par 4692 interrupt-parent = <&mdss>;
4693 interrupts = 4693 interrupts = <4>;
4694 4694
4695 clocks = <&di 4695 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4696 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4697 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4698 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4699 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4700 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4701 clock-names = "byte",
4702 4702 "byte_intf",
4703 4703 "pixel",
4704 4704 "core",
4705 4705 "iface",
4706 4706 "bus";
4707 assigned-cloc 4707 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-cloc 4708 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4709 4709
4710 operating-poi 4710 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4711 power-domains = <&rpmhpd SDM845_CX>;
4712 4712
4713 phys = <&mdss 4713 phys = <&mdss_dsi0_phy>;
4714 4714
4715 status = "dis 4715 status = "disabled";
4716 4716
4717 #address-cell 4717 #address-cells = <1>;
4718 #size-cells = 4718 #size-cells = <0>;
4719 4719
4720 ports { 4720 ports {
4721 #addr 4721 #address-cells = <1>;
4722 #size 4722 #size-cells = <0>;
4723 4723
4724 port@ 4724 port@0 {
4725 4725 reg = <0>;
4726 4726 mdss_dsi0_in: endpoint {
4727 4727 remote-endpoint = <&dpu_intf1_out>;
4728 4728 };
4729 }; 4729 };
4730 4730
4731 port@ 4731 port@1 {
4732 4732 reg = <1>;
4733 4733 mdss_dsi0_out: endpoint {
4734 4734 };
4735 }; 4735 };
4736 }; 4736 };
4737 }; 4737 };
4738 4738
4739 mdss_dsi0_phy: phy@ae 4739 mdss_dsi0_phy: phy@ae94400 {
4740 compatible = 4740 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4741 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4742 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4743 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4744 reg-names = "dsi_phy",
4745 " 4745 "dsi_phy_lane",
4746 " 4746 "dsi_pll";
4747 4747
4748 #clock-cells 4748 #clock-cells = <1>;
4749 #phy-cells = 4749 #phy-cells = <0>;
4750 4750
4751 clocks = <&di 4751 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4752 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4753 clock-names = "iface", "ref";
4754 4754
4755 status = "dis 4755 status = "disabled";
4756 }; 4756 };
4757 4757
4758 mdss_dsi1: dsi@ae9600 4758 mdss_dsi1: dsi@ae96000 {
4759 compatible = 4759 compatible = "qcom,sdm845-dsi-ctrl",
4760 4760 "qcom,mdss-dsi-ctrl";
4761 reg = <0 0x0a 4761 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4762 reg-names = "dsi_ctrl";
4763 4763
4764 interrupt-par 4764 interrupt-parent = <&mdss>;
4765 interrupts = 4765 interrupts = <5>;
4766 4766
4767 clocks = <&di 4767 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4768 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4769 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4770 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4771 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4772 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4773 clock-names = "byte",
4774 4774 "byte_intf",
4775 4775 "pixel",
4776 4776 "core",
4777 4777 "iface",
4778 4778 "bus";
4779 assigned-cloc 4779 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-cloc 4780 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4781 4781
4782 operating-poi 4782 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4783 power-domains = <&rpmhpd SDM845_CX>;
4784 4784
4785 phys = <&mdss 4785 phys = <&mdss_dsi1_phy>;
4786 4786
4787 status = "dis 4787 status = "disabled";
4788 4788
4789 #address-cell 4789 #address-cells = <1>;
4790 #size-cells = 4790 #size-cells = <0>;
4791 4791
4792 ports { 4792 ports {
4793 #addr 4793 #address-cells = <1>;
4794 #size 4794 #size-cells = <0>;
4795 4795
4796 port@ 4796 port@0 {
4797 4797 reg = <0>;
4798 4798 mdss_dsi1_in: endpoint {
4799 4799 remote-endpoint = <&dpu_intf2_out>;
4800 4800 };
4801 }; 4801 };
4802 4802
4803 port@ 4803 port@1 {
4804 4804 reg = <1>;
4805 4805 mdss_dsi1_out: endpoint {
4806 4806 };
4807 }; 4807 };
4808 }; 4808 };
4809 }; 4809 };
4810 4810
4811 mdss_dsi1_phy: phy@ae 4811 mdss_dsi1_phy: phy@ae96400 {
4812 compatible = 4812 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4813 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4814 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4815 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4816 reg-names = "dsi_phy",
4817 " 4817 "dsi_phy_lane",
4818 " 4818 "dsi_pll";
4819 4819
4820 #clock-cells 4820 #clock-cells = <1>;
4821 #phy-cells = 4821 #phy-cells = <0>;
4822 4822
4823 clocks = <&di 4823 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4824 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4825 clock-names = "iface", "ref";
4826 4826
4827 status = "dis 4827 status = "disabled";
4828 }; 4828 };
4829 }; 4829 };
4830 4830
4831 gpu: gpu@5000000 { 4831 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4832 compatible = "qcom,adreno-630.2", "qcom,adreno";
4833 4833
4834 reg = <0 0x05000000 0 4834 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4835 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4836
4837 /* 4837 /*
4838 * Look ma, no clocks 4838 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4839 * controlled entirely by the GMU
4840 */ 4840 */
4841 4841
4842 interrupts = <GIC_SPI 4842 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4843
4844 iommus = <&adreno_smm 4844 iommus = <&adreno_smmu 0>;
4845 4845
4846 operating-points-v2 = 4846 operating-points-v2 = <&gpu_opp_table>;
4847 4847
4848 qcom,gmu = <&gmu>; 4848 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; 4849 #cooling-cells = <2>;
4850 4850
4851 interconnects = <&mem 4851 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4852 interconnect-names = "gfx-mem";
4853 4853
4854 status = "disabled"; 4854 status = "disabled";
4855 4855
4856 gpu_opp_table: opp-ta 4856 gpu_opp_table: opp-table {
4857 compatible = 4857 compatible = "operating-points-v2";
4858 4858
4859 opp-710000000 4859 opp-710000000 {
4860 opp-h 4860 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4861 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4862 opp-peak-kBps = <7216000>;
4863 }; 4863 };
4864 4864
4865 opp-675000000 4865 opp-675000000 {
4866 opp-h 4866 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4867 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4868 opp-peak-kBps = <7216000>;
4869 }; 4869 };
4870 4870
4871 opp-596000000 4871 opp-596000000 {
4872 opp-h 4872 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4873 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4874 opp-peak-kBps = <6220000>;
4875 }; 4875 };
4876 4876
4877 opp-520000000 4877 opp-520000000 {
4878 opp-h 4878 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4879 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4880 opp-peak-kBps = <6220000>;
4881 }; 4881 };
4882 4882
4883 opp-414000000 4883 opp-414000000 {
4884 opp-h 4884 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4885 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4886 opp-peak-kBps = <4068000>;
4887 }; 4887 };
4888 4888
4889 opp-342000000 4889 opp-342000000 {
4890 opp-h 4890 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4891 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4892 opp-peak-kBps = <2724000>;
4893 }; 4893 };
4894 4894
4895 opp-257000000 4895 opp-257000000 {
4896 opp-h 4896 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4897 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4898 opp-peak-kBps = <1648000>;
4899 }; 4899 };
4900 }; 4900 };
4901 }; 4901 };
4902 4902
4903 adreno_smmu: iommu@5040000 { 4903 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4904 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 4905 reg = <0 0x05040000 0 0x10000>;
4906 #iommu-cells = <1>; 4906 #iommu-cells = <1>;
4907 #global-interrupts = 4907 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4908 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4909 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4910 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4911 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4912 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4913 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4914 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4915 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4916 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4917 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4918 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4919 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4920 clock-names = "bus", "iface";
4921 4921
4922 power-domains = <&gpu 4922 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4923 };
4924 4924
4925 gmu: gmu@506a000 { 4925 gmu: gmu@506a000 {
4926 compatible = "qcom,ad 4926 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4927
4928 reg = <0 0x0506a000 0 4928 reg = <0 0x0506a000 0 0x30000>,
4929 <0 0x0b280000 0 4929 <0 0x0b280000 0 0x10000>,
4930 <0 0x0b480000 0 4930 <0 0x0b480000 0 0x10000>;
4931 reg-names = "gmu", "g 4931 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4932
4933 interrupts = <GIC_SPI 4933 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4934 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4935 interrupt-names = "hfi", "gmu";
4936 4936
4937 clocks = <&gpucc GPU_ 4937 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4938 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4939 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4940 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4941 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4942
4943 power-domains = <&gpu 4943 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4944 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4945 power-domain-names = "cx", "gx";
4946 4946
4947 iommus = <&adreno_smm 4947 iommus = <&adreno_smmu 5>;
4948 4948
4949 operating-points-v2 = 4949 operating-points-v2 = <&gmu_opp_table>;
4950 4950
4951 status = "disabled"; 4951 status = "disabled";
4952 4952
4953 gmu_opp_table: opp-ta 4953 gmu_opp_table: opp-table {
4954 compatible = 4954 compatible = "operating-points-v2";
4955 4955
4956 opp-400000000 4956 opp-400000000 {
4957 opp-h 4957 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4958 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4959 };
4960 4960
4961 opp-200000000 4961 opp-200000000 {
4962 opp-h 4962 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4963 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4964 };
4965 }; 4965 };
4966 }; 4966 };
4967 4967
4968 dispcc: clock-controller@af00 4968 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4969 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4970 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4971 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4972 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4973 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ 4974 <&mdss_dsi0_phy 0>,
4975 <&mdss_dsi0_ 4975 <&mdss_dsi0_phy 1>,
4976 <&mdss_dsi1_ 4976 <&mdss_dsi1_phy 0>,
4977 <&mdss_dsi1_ 4977 <&mdss_dsi1_phy 1>,
4978 <&usb_1_qmpp 4978 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4979 <&usb_1_qmpp 4979 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4980 clock-names = "bi_tcx 4980 clock-names = "bi_tcxo",
4981 "gcc_di 4981 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4982 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4983 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4984 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4985 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4986 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4987 "dp_link_clk_divsel_ten",
4988 "dp_vco 4988 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4989 #clock-cells = <1>;
4990 #reset-cells = <1>; 4990 #reset-cells = <1>;
4991 #power-domain-cells = 4991 #power-domain-cells = <1>;
4992 }; 4992 };
4993 4993
4994 pdc_intc: interrupt-controlle 4994 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4995 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4996 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4997 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4998 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4999 interrupt-parent = <&intc>;
5000 interrupt-controller; 5000 interrupt-controller;
5001 }; 5001 };
5002 5002
5003 pdc_reset: reset-controller@b 5003 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 5004 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 5005 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 5006 #reset-cells = <1>;
5007 }; 5007 };
5008 5008
5009 tsens0: thermal-sensor@c26300 5009 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 5010 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 5011 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 5012 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 5013 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 5014 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 5015 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 5016 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 5017 #thermal-sensor-cells = <1>;
5018 }; 5018 };
5019 5019
5020 tsens1: thermal-sensor@c26500 5020 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 5021 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 5022 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 5023 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 5024 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 5025 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 5026 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 5027 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 5028 #thermal-sensor-cells = <1>;
5029 }; 5029 };
5030 5030
5031 aoss_reset: reset-controller@ 5031 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 5032 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 5033 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 5034 #reset-cells = <1>;
5035 }; 5035 };
5036 5036
5037 aoss_qmp: power-management@c3 5037 aoss_qmp: power-management@c300000 {
5038 compatible = "qcom,sd 5038 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039 reg = <0 0x0c300000 0 5039 reg = <0 0x0c300000 0 0x400>;
5040 interrupts = <GIC_SPI 5040 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 5041 mboxes = <&apss_shared 0>;
5042 5042
5043 #clock-cells = <0>; 5043 #clock-cells = <0>;
5044 5044
5045 cx_cdev: cx { 5045 cx_cdev: cx {
5046 #cooling-cell 5046 #cooling-cells = <2>;
5047 }; 5047 };
5048 5048
5049 ebi_cdev: ebi { 5049 ebi_cdev: ebi {
5050 #cooling-cell 5050 #cooling-cells = <2>;
5051 }; 5051 };
5052 }; 5052 };
5053 5053
5054 sram@c3f0000 { 5054 sram@c3f0000 {
5055 compatible = "qcom,sd 5055 compatible = "qcom,sdm845-rpmh-stats";
5056 reg = <0 0x0c3f0000 0 5056 reg = <0 0x0c3f0000 0 0x400>;
5057 }; 5057 };
5058 5058
5059 spmi_bus: spmi@c440000 { 5059 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 5060 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 5061 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 5062 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 5063 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 5064 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 5065 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 5066 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 5067 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 5068 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 5069 qcom,ee = <0>;
5070 qcom,channel = <0>; 5070 qcom,channel = <0>;
5071 #address-cells = <2>; 5071 #address-cells = <2>;
5072 #size-cells = <0>; 5072 #size-cells = <0>;
5073 interrupt-controller; 5073 interrupt-controller;
5074 #interrupt-cells = <4 5074 #interrupt-cells = <4>;
5075 }; 5075 };
5076 5076
5077 sram@146bf000 { 5077 sram@146bf000 {
5078 compatible = "qcom,sd 5078 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5079 reg = <0 0x146bf000 0 5079 reg = <0 0x146bf000 0 0x1000>;
5080 5080
5081 #address-cells = <1>; 5081 #address-cells = <1>;
5082 #size-cells = <1>; 5082 #size-cells = <1>;
5083 5083
5084 ranges = <0 0 0x146bf 5084 ranges = <0 0 0x146bf000 0x1000>;
5085 5085
5086 pil-reloc@94c { 5086 pil-reloc@94c {
5087 compatible = 5087 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 5088 reg = <0x94c 0xc8>;
5089 }; 5089 };
5090 }; 5090 };
5091 5091
5092 apps_smmu: iommu@15000000 { 5092 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 5093 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 5094 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 5095 #iommu-cells = <2>;
5096 #global-interrupts = 5096 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 5097 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 5098 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 5099 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 5100 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 5101 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 5102 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 5103 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 5104 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 5105 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 5106 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 5107 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 5108 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 5109 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 5110 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 5111 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 5112 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 5113 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 5114 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 5115 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 5116 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 5117 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 5118 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 5119 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 5120 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 5121 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 5122 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 5123 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 5124 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 5125 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 5126 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 5127 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 5128 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 5129 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 5130 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 5131 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 5132 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 5133 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 5134 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 5135 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 5136 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 5137 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 5138 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 5139 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 5140 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 5141 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 5142 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 5143 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 5144 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 5145 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 5146 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 5147 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 5148 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 5149 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 5150 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 5151 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 5152 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 5153 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 5154 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 5155 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 5156 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 5157 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 5158 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 5159 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 5160 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 5161 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 5162 };
5163 5163
5164 anoc_1_tbu: tbu@150c5000 { 5164 anoc_1_tbu: tbu@150c5000 {
5165 compatible = "qcom,sd 5165 compatible = "qcom,sdm845-tbu";
5166 reg = <0x0 0x150c5000 5166 reg = <0x0 0x150c5000 0x0 0x1000>;
5167 interconnects = <&sys 5167 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
5168 &con 5168 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
5169 power-domains = <&gcc 5169 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
5170 qcom,stream-id-range 5170 qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
5171 }; 5171 };
5172 5172
5173 anoc_2_tbu: tbu@150c9000 { 5173 anoc_2_tbu: tbu@150c9000 {
5174 compatible = "qcom,sd 5174 compatible = "qcom,sdm845-tbu";
5175 reg = <0x0 0x150c9000 5175 reg = <0x0 0x150c9000 0x0 0x1000>;
5176 interconnects = <&sys 5176 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
5177 &con 5177 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
5178 power-domains = <&gcc 5178 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
5179 qcom,stream-id-range 5179 qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
5180 }; 5180 };
5181 5181
5182 mnoc_hf_0_tbu: tbu@150cd000 { 5182 mnoc_hf_0_tbu: tbu@150cd000 {
5183 compatible = "qcom,sd 5183 compatible = "qcom,sdm845-tbu";
5184 reg = <0x0 0x150cd000 5184 reg = <0x0 0x150cd000 0x0 0x1000>;
5185 interconnects = <&mms 5185 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
5186 &mms 5186 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
5187 power-domains = <&gcc 5187 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
5188 qcom,stream-id-range 5188 qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
5189 }; 5189 };
5190 5190
5191 mnoc_hf_1_tbu: tbu@150d1000 { 5191 mnoc_hf_1_tbu: tbu@150d1000 {
5192 compatible = "qcom,sd 5192 compatible = "qcom,sdm845-tbu";
5193 reg = <0x0 0x150d1000 5193 reg = <0x0 0x150d1000 0x0 0x1000>;
5194 interconnects = <&mms 5194 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
5195 &mms 5195 &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
5196 power-domains = <&gcc 5196 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
5197 qcom,stream-id-range 5197 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
5198 }; 5198 };
5199 5199
5200 mnoc_sf_0_tbu: tbu@150d5000 { 5200 mnoc_sf_0_tbu: tbu@150d5000 {
5201 compatible = "qcom,sd 5201 compatible = "qcom,sdm845-tbu";
5202 reg = <0x0 0x150d5000 5202 reg = <0x0 0x150d5000 0x0 0x1000>;
5203 interconnects = <&mms 5203 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
5204 &mms 5204 &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
5205 power-domains = <&gcc 5205 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>;
5206 qcom,stream-id-range 5206 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
5207 }; 5207 };
5208 5208
5209 compute_dsp_tbu: tbu@150d9000 5209 compute_dsp_tbu: tbu@150d9000 {
5210 compatible = "qcom,sd 5210 compatible = "qcom,sdm845-tbu";
5211 reg = <0x0 0x150d9000 5211 reg = <0x0 0x150d9000 0x0 0x1000>;
5212 interconnects = <&sys 5212 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
5213 &con 5213 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
5214 qcom,stream-id-range 5214 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
5215 }; 5215 };
5216 5216
5217 adsp_tbu: tbu@150dd000 { 5217 adsp_tbu: tbu@150dd000 {
5218 compatible = "qcom,sd 5218 compatible = "qcom,sdm845-tbu";
5219 reg = <0x0 0x150dd000 5219 reg = <0x0 0x150dd000 0x0 0x1000>;
5220 interconnects = <&sys 5220 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
5221 &con 5221 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
5222 power-domains = <&gcc 5222 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
5223 qcom,stream-id-range 5223 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
5224 }; 5224 };
5225 5225
5226 anoc_1_pcie_tbu: tbu@150e1000 5226 anoc_1_pcie_tbu: tbu@150e1000 {
5227 compatible = "qcom,sd 5227 compatible = "qcom,sdm845-tbu";
5228 reg = <0x0 0x150e1000 5228 reg = <0x0 0x150e1000 0x0 0x1000>;
5229 clocks = <&gcc GCC_AG 5229 clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
5230 interconnects = <&sys 5230 interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
5231 &con 5231 &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
5232 power-domains = <&gcc 5232 power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
5233 qcom,stream-id-range 5233 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
5234 }; 5234 };
5235 5235
5236 lpasscc: clock-controller@170 5236 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 5237 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 5238 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 5239 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 5240 #clock-cells = <1>;
5241 status = "disabled"; 5241 status = "disabled";
5242 }; 5242 };
5243 5243
5244 gladiator_noc: interconnect@1 5244 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 5245 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 5246 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 5247 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 5248 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 5249 };
5250 5250
5251 watchdog@17980000 { 5251 watchdog@17980000 {
5252 compatible = "qcom,ap 5252 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 5253 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 5254 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI 5255 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5256 }; 5256 };
5257 5257
5258 apss_shared: mailbox@17990000 5258 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 5259 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 5260 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 5261 #mbox-cells = <1>;
5262 }; 5262 };
5263 5263
5264 apps_rsc: rsc@179c0000 { 5264 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 5265 label = "apps_rsc";
5266 compatible = "qcom,rp 5266 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 5267 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 5268 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 5269 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 5270 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 5271 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 5272 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 5273 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 5274 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 5275 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 5276 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 5277 <SLEEP_TCS 3>,
5278 <WA 5278 <WAKE_TCS 3>,
5279 <CO 5279 <CONTROL_TCS 1>;
5280 power-domains = <&CLU 5280 power-domains = <&CLUSTER_PD>;
5281 5281
5282 apps_bcm_voter: bcm-v 5282 apps_bcm_voter: bcm-voter {
5283 compatible = 5283 compatible = "qcom,bcm-voter";
5284 }; 5284 };
5285 5285
5286 rpmhcc: clock-control 5286 rpmhcc: clock-controller {
5287 compatible = 5287 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 5288 #clock-cells = <1>;
5289 clock-names = 5289 clock-names = "xo";
5290 clocks = <&xo 5290 clocks = <&xo_board>;
5291 }; 5291 };
5292 5292
5293 rpmhpd: power-control 5293 rpmhpd: power-controller {
5294 compatible = 5294 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 5295 #power-domain-cells = <1>;
5296 operating-poi 5296 operating-points-v2 = <&rpmhpd_opp_table>;
5297 5297
5298 rpmhpd_opp_ta 5298 rpmhpd_opp_table: opp-table {
5299 compa 5299 compatible = "operating-points-v2";
5300 5300
5301 rpmhp 5301 rpmhpd_opp_ret: opp1 {
5302 5302 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 5303 };
5304 5304
5305 rpmhp 5305 rpmhpd_opp_min_svs: opp2 {
5306 5306 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 5307 };
5308 5308
5309 rpmhp 5309 rpmhpd_opp_low_svs: opp3 {
5310 5310 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 5311 };
5312 5312
5313 rpmhp 5313 rpmhpd_opp_svs: opp4 {
5314 5314 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 5315 };
5316 5316
5317 rpmhp 5317 rpmhpd_opp_svs_l1: opp5 {
5318 5318 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 5319 };
5320 5320
5321 rpmhp 5321 rpmhpd_opp_nom: opp6 {
5322 5322 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 5323 };
5324 5324
5325 rpmhp 5325 rpmhpd_opp_nom_l1: opp7 {
5326 5326 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 5327 };
5328 5328
5329 rpmhp 5329 rpmhpd_opp_nom_l2: opp8 {
5330 5330 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 5331 };
5332 5332
5333 rpmhp 5333 rpmhpd_opp_turbo: opp9 {
5334 5334 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 5335 };
5336 5336
5337 rpmhp 5337 rpmhpd_opp_turbo_l1: opp10 {
5338 5338 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 5339 };
5340 }; 5340 };
5341 }; 5341 };
5342 }; 5342 };
5343 5343
5344 intc: interrupt-controller@17 5344 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 5345 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 5346 #address-cells = <2>;
5347 #size-cells = <2>; 5347 #size-cells = <2>;
5348 ranges; 5348 ranges;
5349 #interrupt-cells = <3 5349 #interrupt-cells = <3>;
5350 interrupt-controller; 5350 interrupt-controller;
5351 reg = <0 0x17a00000 0 5351 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 5352 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 5353 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 5354
5355 msi-controller@17a400 5355 msi-controller@17a40000 {
5356 compatible = 5356 compatible = "arm,gic-v3-its";
5357 msi-controlle 5357 msi-controller;
5358 #msi-cells = 5358 #msi-cells = <1>;
5359 reg = <0 0x17 5359 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 5360 status = "disabled";
5361 }; 5361 };
5362 }; 5362 };
5363 5363
5364 slimbam: dma-controller@17184 5364 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba 5365 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 5366 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 5367 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; 5368 num-channels = <31>;
5369 interrupts = <GIC_SPI 5369 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 5370 #dma-cells = <1>;
5371 qcom,ee = <1>; 5371 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 5372 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 5373 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 5374 };
5375 5375
5376 timer@17c90000 { 5376 timer@17c90000 {
5377 #address-cells = <1>; 5377 #address-cells = <1>;
5378 #size-cells = <1>; 5378 #size-cells = <1>;
5379 ranges = <0 0 0 0x200 5379 ranges = <0 0 0 0x20000000>;
5380 compatible = "arm,arm 5380 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 5381 reg = <0 0x17c90000 0 0x1000>;
5382 5382
5383 frame@17ca0000 { 5383 frame@17ca0000 {
5384 frame-number 5384 frame-number = <0>;
5385 interrupts = 5385 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 5386 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca 5387 reg = <0x17ca0000 0x1000>,
5388 <0x17cb 5388 <0x17cb0000 0x1000>;
5389 }; 5389 };
5390 5390
5391 frame@17cc0000 { 5391 frame@17cc0000 {
5392 frame-number 5392 frame-number = <1>;
5393 interrupts = 5393 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc 5394 reg = <0x17cc0000 0x1000>;
5395 status = "dis 5395 status = "disabled";
5396 }; 5396 };
5397 5397
5398 frame@17cd0000 { 5398 frame@17cd0000 {
5399 frame-number 5399 frame-number = <2>;
5400 interrupts = 5400 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd 5401 reg = <0x17cd0000 0x1000>;
5402 status = "dis 5402 status = "disabled";
5403 }; 5403 };
5404 5404
5405 frame@17ce0000 { 5405 frame@17ce0000 {
5406 frame-number 5406 frame-number = <3>;
5407 interrupts = 5407 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce 5408 reg = <0x17ce0000 0x1000>;
5409 status = "dis 5409 status = "disabled";
5410 }; 5410 };
5411 5411
5412 frame@17cf0000 { 5412 frame@17cf0000 {
5413 frame-number 5413 frame-number = <4>;
5414 interrupts = 5414 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf 5415 reg = <0x17cf0000 0x1000>;
5416 status = "dis 5416 status = "disabled";
5417 }; 5417 };
5418 5418
5419 frame@17d00000 { 5419 frame@17d00000 {
5420 frame-number 5420 frame-number = <5>;
5421 interrupts = 5421 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 5422 reg = <0x17d00000 0x1000>;
5423 status = "dis 5423 status = "disabled";
5424 }; 5424 };
5425 5425
5426 frame@17d10000 { 5426 frame@17d10000 {
5427 frame-number 5427 frame-number = <6>;
5428 interrupts = 5428 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 5429 reg = <0x17d10000 0x1000>;
5430 status = "dis 5430 status = "disabled";
5431 }; 5431 };
5432 }; 5432 };
5433 5433
5434 osm_l3: interconnect@17d41000 5434 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd 5435 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5436 reg = <0 0x17d41000 0 5436 reg = <0 0x17d41000 0 0x1400>;
5437 5437
5438 clocks = <&rpmhcc RPM 5438 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 5439 clock-names = "xo", "alternate";
5440 5440
5441 #interconnect-cells = 5441 #interconnect-cells = <1>;
5442 }; 5442 };
5443 5443
5444 cpufreq_hw: cpufreq@17d43000 5444 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd 5445 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 5446 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 5447 reg-names = "freq-domain0", "freq-domain1";
5448 5448
5449 interrupts-extended = 5449 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450 5450
5451 clocks = <&rpmhcc RPM 5451 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 5452 clock-names = "xo", "alternate";
5453 5453
5454 #freq-domain-cells = 5454 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; 5455 #clock-cells = <1>;
5456 }; 5456 };
5457 5457
5458 wifi: wifi@18800000 { 5458 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 5459 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 5460 status = "disabled";
5461 reg = <0 0x18800000 0 5461 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 5462 reg-names = "membase";
5463 memory-region = <&wla 5463 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 5464 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 5465 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 5466 interrupts =
5467 <GIC_SPI 414 5467 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 5468 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 5469 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 5470 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 5471 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 5472 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 5473 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 5474 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 5475 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 5476 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 5477 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 5478 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 5479 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 5480 };
5481 }; 5481 };
5482 5482
5483 sound: sound { 5483 sound: sound {
5484 }; 5484 };
5485 5485
5486 thermal-zones { 5486 thermal-zones {
5487 cpu0-thermal { 5487 cpu0-thermal {
5488 polling-delay-passive 5488 polling-delay-passive = <250>;
5489 5489
5490 thermal-sensors = <&t 5490 thermal-sensors = <&tsens0 1>;
5491 5491
5492 trips { 5492 trips {
5493 cpu0_alert0: 5493 cpu0_alert0: trip-point0 {
5494 tempe 5494 temperature = <90000>;
5495 hyste 5495 hysteresis = <2000>;
5496 type 5496 type = "passive";
5497 }; 5497 };
5498 5498
5499 cpu0_alert1: 5499 cpu0_alert1: trip-point1 {
5500 tempe 5500 temperature = <95000>;
5501 hyste 5501 hysteresis = <2000>;
5502 type 5502 type = "passive";
5503 }; 5503 };
5504 5504
5505 cpu0_crit: cp 5505 cpu0_crit: cpu-crit {
5506 tempe 5506 temperature = <110000>;
5507 hyste 5507 hysteresis = <1000>;
5508 type 5508 type = "critical";
5509 }; 5509 };
5510 }; 5510 };
5511 }; 5511 };
5512 5512
5513 cpu1-thermal { 5513 cpu1-thermal {
5514 polling-delay-passive 5514 polling-delay-passive = <250>;
5515 5515
5516 thermal-sensors = <&t 5516 thermal-sensors = <&tsens0 2>;
5517 5517
5518 trips { 5518 trips {
5519 cpu1_alert0: 5519 cpu1_alert0: trip-point0 {
5520 tempe 5520 temperature = <90000>;
5521 hyste 5521 hysteresis = <2000>;
5522 type 5522 type = "passive";
5523 }; 5523 };
5524 5524
5525 cpu1_alert1: 5525 cpu1_alert1: trip-point1 {
5526 tempe 5526 temperature = <95000>;
5527 hyste 5527 hysteresis = <2000>;
5528 type 5528 type = "passive";
5529 }; 5529 };
5530 5530
5531 cpu1_crit: cp 5531 cpu1_crit: cpu-crit {
5532 tempe 5532 temperature = <110000>;
5533 hyste 5533 hysteresis = <1000>;
5534 type 5534 type = "critical";
5535 }; 5535 };
5536 }; 5536 };
5537 }; 5537 };
5538 5538
5539 cpu2-thermal { 5539 cpu2-thermal {
5540 polling-delay-passive 5540 polling-delay-passive = <250>;
5541 5541
5542 thermal-sensors = <&t 5542 thermal-sensors = <&tsens0 3>;
5543 5543
5544 trips { 5544 trips {
5545 cpu2_alert0: 5545 cpu2_alert0: trip-point0 {
5546 tempe 5546 temperature = <90000>;
5547 hyste 5547 hysteresis = <2000>;
5548 type 5548 type = "passive";
5549 }; 5549 };
5550 5550
5551 cpu2_alert1: 5551 cpu2_alert1: trip-point1 {
5552 tempe 5552 temperature = <95000>;
5553 hyste 5553 hysteresis = <2000>;
5554 type 5554 type = "passive";
5555 }; 5555 };
5556 5556
5557 cpu2_crit: cp 5557 cpu2_crit: cpu-crit {
5558 tempe 5558 temperature = <110000>;
5559 hyste 5559 hysteresis = <1000>;
5560 type 5560 type = "critical";
5561 }; 5561 };
5562 }; 5562 };
5563 }; 5563 };
5564 5564
5565 cpu3-thermal { 5565 cpu3-thermal {
5566 polling-delay-passive 5566 polling-delay-passive = <250>;
5567 5567
5568 thermal-sensors = <&t 5568 thermal-sensors = <&tsens0 4>;
5569 5569
5570 trips { 5570 trips {
5571 cpu3_alert0: 5571 cpu3_alert0: trip-point0 {
5572 tempe 5572 temperature = <90000>;
5573 hyste 5573 hysteresis = <2000>;
5574 type 5574 type = "passive";
5575 }; 5575 };
5576 5576
5577 cpu3_alert1: 5577 cpu3_alert1: trip-point1 {
5578 tempe 5578 temperature = <95000>;
5579 hyste 5579 hysteresis = <2000>;
5580 type 5580 type = "passive";
5581 }; 5581 };
5582 5582
5583 cpu3_crit: cp 5583 cpu3_crit: cpu-crit {
5584 tempe 5584 temperature = <110000>;
5585 hyste 5585 hysteresis = <1000>;
5586 type 5586 type = "critical";
5587 }; 5587 };
5588 }; 5588 };
5589 }; 5589 };
5590 5590
5591 cpu4-thermal { 5591 cpu4-thermal {
5592 polling-delay-passive 5592 polling-delay-passive = <250>;
5593 5593
5594 thermal-sensors = <&t 5594 thermal-sensors = <&tsens0 7>;
5595 5595
5596 trips { 5596 trips {
5597 cpu4_alert0: 5597 cpu4_alert0: trip-point0 {
5598 tempe 5598 temperature = <90000>;
5599 hyste 5599 hysteresis = <2000>;
5600 type 5600 type = "passive";
5601 }; 5601 };
5602 5602
5603 cpu4_alert1: 5603 cpu4_alert1: trip-point1 {
5604 tempe 5604 temperature = <95000>;
5605 hyste 5605 hysteresis = <2000>;
5606 type 5606 type = "passive";
5607 }; 5607 };
5608 5608
5609 cpu4_crit: cp 5609 cpu4_crit: cpu-crit {
5610 tempe 5610 temperature = <110000>;
5611 hyste 5611 hysteresis = <1000>;
5612 type 5612 type = "critical";
5613 }; 5613 };
5614 }; 5614 };
5615 }; 5615 };
5616 5616
5617 cpu5-thermal { 5617 cpu5-thermal {
5618 polling-delay-passive 5618 polling-delay-passive = <250>;
5619 5619
5620 thermal-sensors = <&t 5620 thermal-sensors = <&tsens0 8>;
5621 5621
5622 trips { 5622 trips {
5623 cpu5_alert0: 5623 cpu5_alert0: trip-point0 {
5624 tempe 5624 temperature = <90000>;
5625 hyste 5625 hysteresis = <2000>;
5626 type 5626 type = "passive";
5627 }; 5627 };
5628 5628
5629 cpu5_alert1: 5629 cpu5_alert1: trip-point1 {
5630 tempe 5630 temperature = <95000>;
5631 hyste 5631 hysteresis = <2000>;
5632 type 5632 type = "passive";
5633 }; 5633 };
5634 5634
5635 cpu5_crit: cp 5635 cpu5_crit: cpu-crit {
5636 tempe 5636 temperature = <110000>;
5637 hyste 5637 hysteresis = <1000>;
5638 type 5638 type = "critical";
5639 }; 5639 };
5640 }; 5640 };
5641 }; 5641 };
5642 5642
5643 cpu6-thermal { 5643 cpu6-thermal {
5644 polling-delay-passive 5644 polling-delay-passive = <250>;
5645 5645
5646 thermal-sensors = <&t 5646 thermal-sensors = <&tsens0 9>;
5647 5647
5648 trips { 5648 trips {
5649 cpu6_alert0: 5649 cpu6_alert0: trip-point0 {
5650 tempe 5650 temperature = <90000>;
5651 hyste 5651 hysteresis = <2000>;
5652 type 5652 type = "passive";
5653 }; 5653 };
5654 5654
5655 cpu6_alert1: 5655 cpu6_alert1: trip-point1 {
5656 tempe 5656 temperature = <95000>;
5657 hyste 5657 hysteresis = <2000>;
5658 type 5658 type = "passive";
5659 }; 5659 };
5660 5660
5661 cpu6_crit: cp 5661 cpu6_crit: cpu-crit {
5662 tempe 5662 temperature = <110000>;
5663 hyste 5663 hysteresis = <1000>;
5664 type 5664 type = "critical";
5665 }; 5665 };
5666 }; 5666 };
5667 }; 5667 };
5668 5668
5669 cpu7-thermal { 5669 cpu7-thermal {
5670 polling-delay-passive 5670 polling-delay-passive = <250>;
5671 5671
5672 thermal-sensors = <&t 5672 thermal-sensors = <&tsens0 10>;
5673 5673
5674 trips { 5674 trips {
5675 cpu7_alert0: 5675 cpu7_alert0: trip-point0 {
5676 tempe 5676 temperature = <90000>;
5677 hyste 5677 hysteresis = <2000>;
5678 type 5678 type = "passive";
5679 }; 5679 };
5680 5680
5681 cpu7_alert1: 5681 cpu7_alert1: trip-point1 {
5682 tempe 5682 temperature = <95000>;
5683 hyste 5683 hysteresis = <2000>;
5684 type 5684 type = "passive";
5685 }; 5685 };
5686 5686
5687 cpu7_crit: cp 5687 cpu7_crit: cpu-crit {
5688 tempe 5688 temperature = <110000>;
5689 hyste 5689 hysteresis = <1000>;
5690 type 5690 type = "critical";
5691 }; 5691 };
5692 }; 5692 };
5693 }; 5693 };
5694 5694
5695 aoss0-thermal { 5695 aoss0-thermal {
5696 polling-delay-passive 5696 polling-delay-passive = <250>;
5697 5697
5698 thermal-sensors = <&t 5698 thermal-sensors = <&tsens0 0>;
5699 5699
5700 trips { 5700 trips {
5701 aoss0_alert0: 5701 aoss0_alert0: trip-point0 {
5702 tempe 5702 temperature = <90000>;
5703 hyste 5703 hysteresis = <2000>;
5704 type 5704 type = "hot";
5705 }; 5705 };
5706 }; 5706 };
5707 }; 5707 };
5708 5708
5709 cluster0-thermal { 5709 cluster0-thermal {
5710 polling-delay-passive 5710 polling-delay-passive = <250>;
5711 5711
5712 thermal-sensors = <&t 5712 thermal-sensors = <&tsens0 5>;
5713 5713
5714 trips { 5714 trips {
5715 cluster0_aler 5715 cluster0_alert0: trip-point0 {
5716 tempe 5716 temperature = <90000>;
5717 hyste 5717 hysteresis = <2000>;
5718 type 5718 type = "hot";
5719 }; 5719 };
5720 cluster0_crit 5720 cluster0_crit: cluster0-crit {
5721 tempe 5721 temperature = <110000>;
5722 hyste 5722 hysteresis = <2000>;
5723 type 5723 type = "critical";
5724 }; 5724 };
5725 }; 5725 };
5726 }; 5726 };
5727 5727
5728 cluster1-thermal { 5728 cluster1-thermal {
5729 polling-delay-passive 5729 polling-delay-passive = <250>;
5730 5730
5731 thermal-sensors = <&t 5731 thermal-sensors = <&tsens0 6>;
5732 5732
5733 trips { 5733 trips {
5734 cluster1_aler 5734 cluster1_alert0: trip-point0 {
5735 tempe 5735 temperature = <90000>;
5736 hyste 5736 hysteresis = <2000>;
5737 type 5737 type = "hot";
5738 }; 5738 };
5739 cluster1_crit 5739 cluster1_crit: cluster1-crit {
5740 tempe 5740 temperature = <110000>;
5741 hyste 5741 hysteresis = <2000>;
5742 type 5742 type = "critical";
5743 }; 5743 };
5744 }; 5744 };
5745 }; 5745 };
5746 5746
5747 gpu-top-thermal { 5747 gpu-top-thermal {
5748 polling-delay-passive 5748 polling-delay-passive = <250>;
5749 5749
5750 thermal-sensors = <&t 5750 thermal-sensors = <&tsens0 11>;
5751 5751
5752 cooling-maps { 5752 cooling-maps {
5753 map0 { 5753 map0 {
5754 trip 5754 trip = <&gpu_top_alert0>;
5755 cooli 5755 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5756 }; 5756 };
5757 }; 5757 };
5758 5758
5759 trips { 5759 trips {
5760 gpu_top_alert 5760 gpu_top_alert0: trip-point0 {
5761 tempe 5761 temperature = <85000>;
5762 hyste 5762 hysteresis = <1000>;
5763 type 5763 type = "passive";
5764 }; 5764 };
5765 5765
5766 trip-point1 { 5766 trip-point1 {
5767 tempe 5767 temperature = <90000>;
5768 hyste 5768 hysteresis = <1000>;
5769 type 5769 type = "hot";
5770 }; 5770 };
5771 5771
5772 trip-point2 { 5772 trip-point2 {
5773 tempe 5773 temperature = <110000>;
5774 hyste 5774 hysteresis = <1000>;
5775 type 5775 type = "critical";
5776 }; 5776 };
5777 }; 5777 };
5778 }; 5778 };
5779 5779
5780 gpu-bottom-thermal { 5780 gpu-bottom-thermal {
5781 polling-delay-passive 5781 polling-delay-passive = <250>;
5782 5782
5783 thermal-sensors = <&t 5783 thermal-sensors = <&tsens0 12>;
5784 5784
5785 cooling-maps { 5785 cooling-maps {
5786 map0 { 5786 map0 {
5787 trip 5787 trip = <&gpu_bottom_alert0>;
5788 cooli 5788 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5789 }; 5789 };
5790 }; 5790 };
5791 5791
5792 trips { 5792 trips {
5793 gpu_bottom_al 5793 gpu_bottom_alert0: trip-point0 {
5794 tempe 5794 temperature = <85000>;
5795 hyste 5795 hysteresis = <1000>;
5796 type 5796 type = "passive";
5797 }; 5797 };
5798 5798
5799 trip-point1 { 5799 trip-point1 {
5800 tempe 5800 temperature = <90000>;
5801 hyste 5801 hysteresis = <1000>;
5802 type 5802 type = "hot";
5803 }; 5803 };
5804 5804
5805 trip-point2 { 5805 trip-point2 {
5806 tempe 5806 temperature = <110000>;
5807 hyste 5807 hysteresis = <1000>;
5808 type 5808 type = "critical";
5809 }; 5809 };
5810 }; 5810 };
5811 }; 5811 };
5812 5812
5813 aoss1-thermal { 5813 aoss1-thermal {
5814 polling-delay-passive 5814 polling-delay-passive = <250>;
5815 5815
5816 thermal-sensors = <&t 5816 thermal-sensors = <&tsens1 0>;
5817 5817
5818 trips { 5818 trips {
5819 aoss1_alert0: 5819 aoss1_alert0: trip-point0 {
5820 tempe 5820 temperature = <90000>;
5821 hyste 5821 hysteresis = <2000>;
5822 type 5822 type = "hot";
5823 }; 5823 };
5824 }; 5824 };
5825 }; 5825 };
5826 5826
5827 q6-modem-thermal { 5827 q6-modem-thermal {
5828 polling-delay-passive 5828 polling-delay-passive = <250>;
5829 5829
5830 thermal-sensors = <&t 5830 thermal-sensors = <&tsens1 1>;
5831 5831
5832 trips { 5832 trips {
5833 q6_modem_aler 5833 q6_modem_alert0: trip-point0 {
5834 tempe 5834 temperature = <90000>;
5835 hyste 5835 hysteresis = <2000>;
5836 type 5836 type = "hot";
5837 }; 5837 };
5838 }; 5838 };
5839 }; 5839 };
5840 5840
5841 mem-thermal { 5841 mem-thermal {
5842 polling-delay-passive 5842 polling-delay-passive = <250>;
5843 5843
5844 thermal-sensors = <&t 5844 thermal-sensors = <&tsens1 2>;
5845 5845
5846 trips { 5846 trips {
5847 mem_alert0: t 5847 mem_alert0: trip-point0 {
5848 tempe 5848 temperature = <90000>;
5849 hyste 5849 hysteresis = <2000>;
5850 type 5850 type = "hot";
5851 }; 5851 };
5852 }; 5852 };
5853 }; 5853 };
5854 5854
5855 wlan-thermal { 5855 wlan-thermal {
5856 polling-delay-passive 5856 polling-delay-passive = <250>;
5857 5857
5858 thermal-sensors = <&t 5858 thermal-sensors = <&tsens1 3>;
5859 5859
5860 trips { 5860 trips {
5861 wlan_alert0: 5861 wlan_alert0: trip-point0 {
5862 tempe 5862 temperature = <90000>;
5863 hyste 5863 hysteresis = <2000>;
5864 type 5864 type = "hot";
5865 }; 5865 };
5866 }; 5866 };
5867 }; 5867 };
5868 5868
5869 q6-hvx-thermal { 5869 q6-hvx-thermal {
5870 polling-delay-passive 5870 polling-delay-passive = <250>;
5871 5871
5872 thermal-sensors = <&t 5872 thermal-sensors = <&tsens1 4>;
5873 5873
5874 trips { 5874 trips {
5875 q6_hvx_alert0 5875 q6_hvx_alert0: trip-point0 {
5876 tempe 5876 temperature = <90000>;
5877 hyste 5877 hysteresis = <2000>;
5878 type 5878 type = "hot";
5879 }; 5879 };
5880 }; 5880 };
5881 }; 5881 };
5882 5882
5883 camera-thermal { 5883 camera-thermal {
5884 polling-delay-passive 5884 polling-delay-passive = <250>;
5885 5885
5886 thermal-sensors = <&t 5886 thermal-sensors = <&tsens1 5>;
5887 5887
5888 trips { 5888 trips {
5889 camera_alert0 5889 camera_alert0: trip-point0 {
5890 tempe 5890 temperature = <90000>;
5891 hyste 5891 hysteresis = <2000>;
5892 type 5892 type = "hot";
5893 }; 5893 };
5894 }; 5894 };
5895 }; 5895 };
5896 5896
5897 video-thermal { 5897 video-thermal {
5898 polling-delay-passive 5898 polling-delay-passive = <250>;
5899 5899
5900 thermal-sensors = <&t 5900 thermal-sensors = <&tsens1 6>;
5901 5901
5902 trips { 5902 trips {
5903 video_alert0: 5903 video_alert0: trip-point0 {
5904 tempe 5904 temperature = <90000>;
5905 hyste 5905 hysteresis = <2000>;
5906 type 5906 type = "hot";
5907 }; 5907 };
5908 }; 5908 };
5909 }; 5909 };
5910 5910
5911 modem-thermal { 5911 modem-thermal {
5912 polling-delay-passive 5912 polling-delay-passive = <250>;
5913 5913
5914 thermal-sensors = <&t 5914 thermal-sensors = <&tsens1 7>;
5915 5915
5916 trips { 5916 trips {
5917 modem_alert0: 5917 modem_alert0: trip-point0 {
5918 tempe 5918 temperature = <90000>;
5919 hyste 5919 hysteresis = <2000>;
5920 type 5920 type = "hot";
5921 }; 5921 };
5922 }; 5922 };
5923 }; 5923 };
5924 }; 5924 };
5925 5925
5926 timer { 5926 timer {
5927 compatible = "arm,armv8-timer 5927 compatible = "arm,armv8-timer";
5928 interrupts = <GIC_PPI 1 IRQ_T 5928 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5929 <GIC_PPI 2 IRQ_T 5929 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5930 <GIC_PPI 3 IRQ_T 5930 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5931 <GIC_PPI 0 IRQ_T 5931 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5932 }; 5932 };
5933 }; 5933 };
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