1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> <<
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 16 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 17 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 22 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 25 #include <dt-bindings/thermal/thermal.h>
31 26
32 / { 27 / {
33 interrupt-parent = <&intc>; 28 interrupt-parent = <&intc>;
34 29
35 #address-cells = <2>; 30 #address-cells = <2>;
36 #size-cells = <2>; 31 #size-cells = <2>;
37 32
38 aliases { 33 aliases {
39 i2c0 = &i2c0; 34 i2c0 = &i2c0;
40 i2c1 = &i2c1; 35 i2c1 = &i2c1;
41 i2c2 = &i2c2; 36 i2c2 = &i2c2;
42 i2c3 = &i2c3; 37 i2c3 = &i2c3;
43 i2c4 = &i2c4; 38 i2c4 = &i2c4;
44 i2c5 = &i2c5; 39 i2c5 = &i2c5;
45 i2c6 = &i2c6; 40 i2c6 = &i2c6;
46 i2c7 = &i2c7; 41 i2c7 = &i2c7;
47 i2c8 = &i2c8; 42 i2c8 = &i2c8;
48 i2c9 = &i2c9; 43 i2c9 = &i2c9;
49 i2c10 = &i2c10; 44 i2c10 = &i2c10;
50 i2c11 = &i2c11; 45 i2c11 = &i2c11;
51 i2c12 = &i2c12; 46 i2c12 = &i2c12;
52 i2c13 = &i2c13; 47 i2c13 = &i2c13;
53 i2c14 = &i2c14; 48 i2c14 = &i2c14;
54 i2c15 = &i2c15; 49 i2c15 = &i2c15;
55 spi0 = &spi0; 50 spi0 = &spi0;
56 spi1 = &spi1; 51 spi1 = &spi1;
57 spi2 = &spi2; 52 spi2 = &spi2;
58 spi3 = &spi3; 53 spi3 = &spi3;
59 spi4 = &spi4; 54 spi4 = &spi4;
60 spi5 = &spi5; 55 spi5 = &spi5;
61 spi6 = &spi6; 56 spi6 = &spi6;
62 spi7 = &spi7; 57 spi7 = &spi7;
63 spi8 = &spi8; 58 spi8 = &spi8;
64 spi9 = &spi9; 59 spi9 = &spi9;
65 spi10 = &spi10; 60 spi10 = &spi10;
66 spi11 = &spi11; 61 spi11 = &spi11;
67 spi12 = &spi12; 62 spi12 = &spi12;
68 spi13 = &spi13; 63 spi13 = &spi13;
69 spi14 = &spi14; 64 spi14 = &spi14;
70 spi15 = &spi15; 65 spi15 = &spi15;
71 }; 66 };
72 67
73 chosen { }; 68 chosen { };
74 69
75 clocks { !! 70 memory@80000000 {
76 xo_board: xo-board { !! 71 device_type = "memory";
77 compatible = "fixed-cl !! 72 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 73 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 74 };
80 clock-output-names = " !! 75
>> 76 reserved-memory {
>> 77 #address-cells = <2>;
>> 78 #size-cells = <2>;
>> 79 ranges;
>> 80
>> 81 hyp_mem: memory@85700000 {
>> 82 reg = <0 0x85700000 0 0x600000>;
>> 83 no-map;
81 }; 84 };
82 85
83 sleep_clk: sleep-clk { !! 86 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 87 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 88 no-map;
86 clock-frequency = <327 !! 89 };
>> 90
>> 91 aop_mem: memory@85fc0000 {
>> 92 reg = <0 0x85fc0000 0 0x20000>;
>> 93 no-map;
>> 94 };
>> 95
>> 96 aop_cmd_db_mem: memory@85fe0000 {
>> 97 compatible = "qcom,cmd-db";
>> 98 reg = <0x0 0x85fe0000 0 0x20000>;
>> 99 no-map;
>> 100 };
>> 101
>> 102 smem_mem: memory@86000000 {
>> 103 reg = <0x0 0x86000000 0 0x200000>;
>> 104 no-map;
>> 105 };
>> 106
>> 107 tz_mem: memory@86200000 {
>> 108 reg = <0 0x86200000 0 0x2d00000>;
>> 109 no-map;
>> 110 };
>> 111
>> 112 rmtfs_mem: memory@88f00000 {
>> 113 compatible = "qcom,rmtfs-mem";
>> 114 reg = <0 0x88f00000 0 0x200000>;
>> 115 no-map;
>> 116
>> 117 qcom,client-id = <1>;
>> 118 qcom,vmid = <15>;
>> 119 };
>> 120
>> 121 qseecom_mem: memory@8ab00000 {
>> 122 reg = <0 0x8ab00000 0 0x1400000>;
>> 123 no-map;
>> 124 };
>> 125
>> 126 camera_mem: memory@8bf00000 {
>> 127 reg = <0 0x8bf00000 0 0x500000>;
>> 128 no-map;
>> 129 };
>> 130
>> 131 ipa_fw_mem: memory@8c400000 {
>> 132 reg = <0 0x8c400000 0 0x10000>;
>> 133 no-map;
>> 134 };
>> 135
>> 136 ipa_gsi_mem: memory@8c410000 {
>> 137 reg = <0 0x8c410000 0 0x5000>;
>> 138 no-map;
>> 139 };
>> 140
>> 141 gpu_mem: memory@8c415000 {
>> 142 reg = <0 0x8c415000 0 0x2000>;
>> 143 no-map;
>> 144 };
>> 145
>> 146 adsp_mem: memory@8c500000 {
>> 147 reg = <0 0x8c500000 0 0x1a00000>;
>> 148 no-map;
>> 149 };
>> 150
>> 151 wlan_msa_mem: memory@8df00000 {
>> 152 reg = <0 0x8df00000 0 0x100000>;
>> 153 no-map;
>> 154 };
>> 155
>> 156 mpss_region: memory@8e000000 {
>> 157 reg = <0 0x8e000000 0 0x7800000>;
>> 158 no-map;
>> 159 };
>> 160
>> 161 venus_mem: memory@95800000 {
>> 162 reg = <0 0x95800000 0 0x500000>;
>> 163 no-map;
>> 164 };
>> 165
>> 166 cdsp_mem: memory@95d00000 {
>> 167 reg = <0 0x95d00000 0 0x800000>;
>> 168 no-map;
>> 169 };
>> 170
>> 171 mba_region: memory@96500000 {
>> 172 reg = <0 0x96500000 0 0x200000>;
>> 173 no-map;
>> 174 };
>> 175
>> 176 slpi_mem: memory@96700000 {
>> 177 reg = <0 0x96700000 0 0x1400000>;
>> 178 no-map;
>> 179 };
>> 180
>> 181 spss_mem: memory@97b00000 {
>> 182 reg = <0 0x97b00000 0 0x100000>;
>> 183 no-map;
87 }; 184 };
88 }; 185 };
89 186
90 cpus: cpus { !! 187 cpus {
91 #address-cells = <2>; 188 #address-cells = <2>;
92 #size-cells = <0>; 189 #size-cells = <0>;
93 190
94 CPU0: cpu@0 { 191 CPU0: cpu@0 {
95 device_type = "cpu"; 192 device_type = "cpu";
96 compatible = "qcom,kry 193 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 194 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 195 enable-method = "psci";
100 capacity-dmips-mhz = < !! 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101 dynamic-power-coeffici !! 197 &LITTLE_CPU_SLEEP_1
>> 198 &CLUSTER_SLEEP_0>;
>> 199 capacity-dmips-mhz = <607>;
>> 200 dynamic-power-coefficient = <100>;
102 qcom,freq-domain = <&c 201 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 202 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 205 #cooling-cells = <2>;
109 next-level-cache = <&L 206 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 207 L2_0: l2-cache {
111 compatible = " 208 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 209 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 210 L3_0: l3-cache {
116 compat !! 211 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 212 };
120 }; 213 };
121 }; 214 };
122 215
123 CPU1: cpu@100 { 216 CPU1: cpu@100 {
124 device_type = "cpu"; 217 device_type = "cpu";
125 compatible = "qcom,kry 218 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 219 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 220 enable-method = "psci";
129 capacity-dmips-mhz = < !! 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130 dynamic-power-coeffici !! 222 &LITTLE_CPU_SLEEP_1
>> 223 &CLUSTER_SLEEP_0>;
>> 224 capacity-dmips-mhz = <607>;
>> 225 dynamic-power-coefficient = <100>;
131 qcom,freq-domain = <&c 226 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 227 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 230 #cooling-cells = <2>;
138 next-level-cache = <&L 231 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 232 L2_100: l2-cache {
140 compatible = " 233 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 234 next-level-cache = <&L3_0>;
144 }; 235 };
145 }; 236 };
146 237
147 CPU2: cpu@200 { 238 CPU2: cpu@200 {
148 device_type = "cpu"; 239 device_type = "cpu";
149 compatible = "qcom,kry 240 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 241 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 242 enable-method = "psci";
153 capacity-dmips-mhz = < !! 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154 dynamic-power-coeffici !! 244 &LITTLE_CPU_SLEEP_1
>> 245 &CLUSTER_SLEEP_0>;
>> 246 capacity-dmips-mhz = <607>;
>> 247 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&c 248 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 249 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 252 #cooling-cells = <2>;
162 next-level-cache = <&L 253 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 254 L2_200: l2-cache {
164 compatible = " 255 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 256 next-level-cache = <&L3_0>;
168 }; 257 };
169 }; 258 };
170 259
171 CPU3: cpu@300 { 260 CPU3: cpu@300 {
172 device_type = "cpu"; 261 device_type = "cpu";
173 compatible = "qcom,kry 262 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 263 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 264 enable-method = "psci";
177 capacity-dmips-mhz = < !! 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178 dynamic-power-coeffici !! 266 &LITTLE_CPU_SLEEP_1
>> 267 &CLUSTER_SLEEP_0>;
>> 268 capacity-dmips-mhz = <607>;
>> 269 dynamic-power-coefficient = <100>;
179 qcom,freq-domain = <&c 270 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 271 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 274 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 275 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 276 L2_300: l2-cache {
188 compatible = " 277 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 278 next-level-cache = <&L3_0>;
192 }; 279 };
193 }; 280 };
194 281
195 CPU4: cpu@400 { 282 CPU4: cpu@400 {
196 device_type = "cpu"; 283 device_type = "cpu";
197 compatible = "qcom,kry 284 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 285 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 286 enable-method = "psci";
201 capacity-dmips-mhz = < 287 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici !! 288 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 289 &BIG_CPU_SLEEP_1
>> 290 &CLUSTER_SLEEP_0>;
>> 291 dynamic-power-coefficient = <396>;
203 qcom,freq-domain = <&c 292 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 293 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 296 #cooling-cells = <2>;
210 next-level-cache = <&L 297 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 298 L2_400: l2-cache {
212 compatible = " 299 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 300 next-level-cache = <&L3_0>;
216 }; 301 };
217 }; 302 };
218 303
219 CPU5: cpu@500 { 304 CPU5: cpu@500 {
220 device_type = "cpu"; 305 device_type = "cpu";
221 compatible = "qcom,kry 306 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 307 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 308 enable-method = "psci";
225 capacity-dmips-mhz = < 309 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici !! 310 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 311 &BIG_CPU_SLEEP_1
>> 312 &CLUSTER_SLEEP_0>;
>> 313 dynamic-power-coefficient = <396>;
227 qcom,freq-domain = <&c 314 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 315 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 318 #cooling-cells = <2>;
234 next-level-cache = <&L 319 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 320 L2_500: l2-cache {
236 compatible = " 321 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 322 next-level-cache = <&L3_0>;
240 }; 323 };
241 }; 324 };
242 325
243 CPU6: cpu@600 { 326 CPU6: cpu@600 {
244 device_type = "cpu"; 327 device_type = "cpu";
245 compatible = "qcom,kry 328 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 329 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 330 enable-method = "psci";
249 capacity-dmips-mhz = < 331 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici !! 332 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 333 &BIG_CPU_SLEEP_1
>> 334 &CLUSTER_SLEEP_0>;
>> 335 dynamic-power-coefficient = <396>;
251 qcom,freq-domain = <&c 336 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 337 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 340 #cooling-cells = <2>;
258 next-level-cache = <&L 341 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 342 L2_600: l2-cache {
260 compatible = " 343 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 344 next-level-cache = <&L3_0>;
264 }; 345 };
265 }; 346 };
266 347
267 CPU7: cpu@700 { 348 CPU7: cpu@700 {
268 device_type = "cpu"; 349 device_type = "cpu";
269 compatible = "qcom,kry 350 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 351 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 352 enable-method = "psci";
273 capacity-dmips-mhz = < 353 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici !! 354 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 355 &BIG_CPU_SLEEP_1
>> 356 &CLUSTER_SLEEP_0>;
>> 357 dynamic-power-coefficient = <396>;
275 qcom,freq-domain = <&c 358 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 359 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 362 #cooling-cells = <2>;
282 next-level-cache = <&L 363 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 364 L2_700: l2-cache {
284 compatible = " 365 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 366 next-level-cache = <&L3_0>;
288 }; 367 };
289 }; 368 };
290 369
291 cpu-map { 370 cpu-map {
292 cluster0 { 371 cluster0 {
293 core0 { 372 core0 {
294 cpu = 373 cpu = <&CPU0>;
295 }; 374 };
296 375
297 core1 { 376 core1 {
298 cpu = 377 cpu = <&CPU1>;
299 }; 378 };
300 379
301 core2 { 380 core2 {
302 cpu = 381 cpu = <&CPU2>;
303 }; 382 };
304 383
305 core3 { 384 core3 {
306 cpu = 385 cpu = <&CPU3>;
307 }; 386 };
308 387
309 core4 { 388 core4 {
310 cpu = 389 cpu = <&CPU4>;
311 }; 390 };
312 391
313 core5 { 392 core5 {
314 cpu = 393 cpu = <&CPU5>;
315 }; 394 };
316 395
317 core6 { 396 core6 {
318 cpu = 397 cpu = <&CPU6>;
319 }; 398 };
320 399
321 core7 { 400 core7 {
322 cpu = 401 cpu = <&CPU7>;
323 }; 402 };
324 }; 403 };
325 }; 404 };
326 405
327 cpu_idle_states: idle-states { !! 406 idle-states {
328 entry-method = "psci"; 407 entry-method = "psci";
329 408
330 LITTLE_CPU_SLEEP_0: cp 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 410 compatible = "arm,idle-state";
332 idle-state-nam !! 411 idle-state-name = "little-power-down";
333 arm,psci-suspe !! 412 arm,psci-suspend-param = <0x40000003>;
334 entry-latency- 413 entry-latency-us = <350>;
335 exit-latency-u 414 exit-latency-us = <461>;
336 min-residency- 415 min-residency-us = <1890>;
337 local-timer-st 416 local-timer-stop;
338 }; 417 };
339 418
340 BIG_CPU_SLEEP_0: cpu-s !! 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341 compatible = " 420 compatible = "arm,idle-state";
342 idle-state-nam !! 421 idle-state-name = "little-rail-power-down";
343 arm,psci-suspe 422 arm,psci-suspend-param = <0x40000004>;
>> 423 entry-latency-us = <360>;
>> 424 exit-latency-us = <531>;
>> 425 min-residency-us = <3934>;
>> 426 local-timer-stop;
>> 427 };
>> 428
>> 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> 430 compatible = "arm,idle-state";
>> 431 idle-state-name = "big-power-down";
>> 432 arm,psci-suspend-param = <0x40000003>;
344 entry-latency- 433 entry-latency-us = <264>;
345 exit-latency-u 434 exit-latency-us = <621>;
346 min-residency- 435 min-residency-us = <952>;
347 local-timer-st 436 local-timer-stop;
348 }; 437 };
349 }; <<
350 438
351 domain-idle-states { !! 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
>> 440 compatible = "arm,idle-state";
>> 441 idle-state-name = "big-rail-power-down";
>> 442 arm,psci-suspend-param = <0x40000004>;
>> 443 entry-latency-us = <702>;
>> 444 exit-latency-us = <1061>;
>> 445 min-residency-us = <4488>;
>> 446 local-timer-stop;
>> 447 };
>> 448
352 CLUSTER_SLEEP_0: clust 449 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " !! 450 compatible = "arm,idle-state";
354 arm,psci-suspe !! 451 idle-state-name = "cluster-power-down";
>> 452 arm,psci-suspend-param = <0x400000F4>;
355 entry-latency- 453 entry-latency-us = <3263>;
356 exit-latency-u 454 exit-latency-us = <6562>;
357 min-residency- 455 min-residency-us = <9987>;
>> 456 local-timer-stop;
358 }; 457 };
359 }; 458 };
360 }; 459 };
361 460
362 firmware { !! 461 cpu0_opp_table: cpu0_opp_table {
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points 462 compatible = "operating-points-v2";
376 opp-shared; 463 opp-shared;
377 464
378 cpu0_opp1: opp-300000000 { 465 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 466 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 467 opp-peak-kBps = <800000 4800000>;
381 }; 468 };
382 469
383 cpu0_opp2: opp-403200000 { 470 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 471 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 472 opp-peak-kBps = <800000 4800000>;
386 }; 473 };
387 474
388 cpu0_opp3: opp-480000000 { 475 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 476 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 477 opp-peak-kBps = <800000 6451200>;
391 }; 478 };
392 479
393 cpu0_opp4: opp-576000000 { 480 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 481 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 482 opp-peak-kBps = <800000 6451200>;
396 }; 483 };
397 484
398 cpu0_opp5: opp-652800000 { 485 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 486 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 487 opp-peak-kBps = <800000 7680000>;
401 }; 488 };
402 489
403 cpu0_opp6: opp-748800000 { 490 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 491 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 492 opp-peak-kBps = <1804000 9216000>;
406 }; 493 };
407 494
408 cpu0_opp7: opp-825600000 { 495 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 496 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 497 opp-peak-kBps = <1804000 9216000>;
411 }; 498 };
412 499
413 cpu0_opp8: opp-902400000 { 500 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 501 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 502 opp-peak-kBps = <1804000 10444800>;
416 }; 503 };
417 504
418 cpu0_opp9: opp-979200000 { 505 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 506 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 507 opp-peak-kBps = <1804000 11980800>;
421 }; 508 };
422 509
423 cpu0_opp10: opp-1056000000 { 510 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 511 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 512 opp-peak-kBps = <1804000 11980800>;
426 }; 513 };
427 514
428 cpu0_opp11: opp-1132800000 { 515 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 516 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 517 opp-peak-kBps = <2188000 13516800>;
431 }; 518 };
432 519
433 cpu0_opp12: opp-1228800000 { 520 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 521 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 522 opp-peak-kBps = <2188000 15052800>;
436 }; 523 };
437 524
438 cpu0_opp13: opp-1324800000 { 525 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 526 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 527 opp-peak-kBps = <2188000 16588800>;
441 }; 528 };
442 529
443 cpu0_opp14: opp-1420800000 { 530 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 531 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 532 opp-peak-kBps = <3072000 18124800>;
446 }; 533 };
447 534
448 cpu0_opp15: opp-1516800000 { 535 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 536 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 537 opp-peak-kBps = <3072000 19353600>;
451 }; 538 };
452 539
453 cpu0_opp16: opp-1612800000 { 540 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 541 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 542 opp-peak-kBps = <4068000 19353600>;
456 }; 543 };
457 544
458 cpu0_opp17: opp-1689600000 { 545 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 546 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 547 opp-peak-kBps = <4068000 20889600>;
461 }; 548 };
462 549
463 cpu0_opp18: opp-1766400000 { 550 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 551 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 552 opp-peak-kBps = <4068000 22425600>;
466 }; 553 };
467 }; 554 };
468 555
469 cpu4_opp_table: opp-table-cpu4 { !! 556 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 557 compatible = "operating-points-v2";
471 opp-shared; 558 opp-shared;
472 559
473 cpu4_opp1: opp-300000000 { 560 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 561 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 562 opp-peak-kBps = <800000 4800000>;
476 }; 563 };
477 564
478 cpu4_opp2: opp-403200000 { 565 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 566 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 567 opp-peak-kBps = <800000 4800000>;
481 }; 568 };
482 569
483 cpu4_opp3: opp-480000000 { 570 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 571 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 572 opp-peak-kBps = <1804000 4800000>;
486 }; 573 };
487 574
488 cpu4_opp4: opp-576000000 { 575 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 576 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 577 opp-peak-kBps = <1804000 4800000>;
491 }; 578 };
492 579
493 cpu4_opp5: opp-652800000 { 580 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 581 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 582 opp-peak-kBps = <1804000 4800000>;
496 }; 583 };
497 584
498 cpu4_opp6: opp-748800000 { 585 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 586 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 587 opp-peak-kBps = <1804000 4800000>;
501 }; 588 };
502 589
503 cpu4_opp7: opp-825600000 { 590 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 591 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 592 opp-peak-kBps = <2188000 9216000>;
506 }; 593 };
507 594
508 cpu4_opp8: opp-902400000 { 595 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 596 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 597 opp-peak-kBps = <2188000 9216000>;
511 }; 598 };
512 599
513 cpu4_opp9: opp-979200000 { 600 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 601 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 602 opp-peak-kBps = <2188000 9216000>;
516 }; 603 };
517 604
518 cpu4_opp10: opp-1056000000 { 605 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 606 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 607 opp-peak-kBps = <3072000 9216000>;
521 }; 608 };
522 609
523 cpu4_opp11: opp-1132800000 { 610 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 611 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 612 opp-peak-kBps = <3072000 11980800>;
526 }; 613 };
527 614
528 cpu4_opp12: opp-1209600000 { 615 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 616 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 617 opp-peak-kBps = <4068000 11980800>;
531 }; 618 };
532 619
533 cpu4_opp13: opp-1286400000 { 620 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 621 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 622 opp-peak-kBps = <4068000 11980800>;
536 }; 623 };
537 624
538 cpu4_opp14: opp-1363200000 { 625 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 626 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 627 opp-peak-kBps = <4068000 15052800>;
541 }; 628 };
542 629
543 cpu4_opp15: opp-1459200000 { 630 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 631 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 632 opp-peak-kBps = <4068000 15052800>;
546 }; 633 };
547 634
548 cpu4_opp16: opp-1536000000 { 635 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 636 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 637 opp-peak-kBps = <5412000 15052800>;
551 }; 638 };
552 639
553 cpu4_opp17: opp-1612800000 { 640 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 641 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 642 opp-peak-kBps = <5412000 15052800>;
556 }; 643 };
557 644
558 cpu4_opp18: opp-1689600000 { 645 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 646 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 647 opp-peak-kBps = <5412000 19353600>;
561 }; 648 };
562 649
563 cpu4_opp19: opp-1766400000 { 650 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 651 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 652 opp-peak-kBps = <6220000 19353600>;
566 }; 653 };
567 654
568 cpu4_opp20: opp-1843200000 { 655 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 656 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 657 opp-peak-kBps = <6220000 19353600>;
571 }; 658 };
572 659
573 cpu4_opp21: opp-1920000000 { 660 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 661 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 662 opp-peak-kBps = <7216000 19353600>;
576 }; 663 };
577 664
578 cpu4_opp22: opp-1996800000 { 665 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 666 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 667 opp-peak-kBps = <7216000 20889600>;
581 }; 668 };
582 669
583 cpu4_opp23: opp-2092800000 { 670 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 671 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 672 opp-peak-kBps = <7216000 20889600>;
586 }; 673 };
587 674
588 cpu4_opp24: opp-2169600000 { 675 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 676 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 677 opp-peak-kBps = <7216000 20889600>;
591 }; 678 };
592 679
593 cpu4_opp25: opp-2246400000 { 680 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 681 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 682 opp-peak-kBps = <7216000 20889600>;
596 }; 683 };
597 684
598 cpu4_opp26: opp-2323200000 { 685 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 686 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 687 opp-peak-kBps = <7216000 20889600>;
601 }; 688 };
602 689
603 cpu4_opp27: opp-2400000000 { 690 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 691 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 692 opp-peak-kBps = <7216000 22425600>;
606 }; 693 };
607 694
608 cpu4_opp28: opp-2476800000 { 695 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 696 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 697 opp-peak-kBps = <7216000 22425600>;
611 }; 698 };
612 699
613 cpu4_opp29: opp-2553600000 { 700 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 701 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 702 opp-peak-kBps = <7216000 22425600>;
616 }; 703 };
617 704
618 cpu4_opp30: opp-2649600000 { 705 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 706 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 707 opp-peak-kBps = <7216000 22425600>;
621 }; 708 };
622 709
623 cpu4_opp31: opp-2745600000 { 710 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 711 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 712 opp-peak-kBps = <7216000 25497600>;
626 }; 713 };
627 714
628 cpu4_opp32: opp-2803200000 { 715 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 716 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 717 opp-peak-kBps = <7216000 25497600>;
631 }; 718 };
632 }; 719 };
633 720
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 721 pmu {
712 compatible = "arm,armv8-pmuv3" 722 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 724 };
715 725
716 psci: psci { !! 726 timer {
717 compatible = "arm,psci-1.0"; !! 727 compatible = "arm,armv8-timer";
718 method = "smc"; !! 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 732 };
773 733
774 reserved-memory { !! 734 clocks {
775 #address-cells = <2>; !! 735 xo_board: xo-board {
776 #size-cells = <2>; !! 736 compatible = "fixed-clock";
777 ranges; !! 737 #clock-cells = <0>;
778 !! 738 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 739 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 740 };
885 741
886 mdata_mem: mpss-metadata { !! 742 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 743 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 744 #clock-cells = <0>;
889 no-map; !! 745 clock-frequency = <32764>;
890 }; 746 };
>> 747 };
891 748
892 fastrpc_mem: fastrpc { !! 749 firmware {
893 compatible = "shared-d !! 750 scm {
894 alloc-ranges = <0x0 0x !! 751 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 752 };
899 }; 753 };
900 754
901 adsp_pas: remoteproc-adsp { 755 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 756 compatible = "qcom,sdm845-adsp-pas";
903 757
904 interrupts-extended = <&intc G 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 763 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 764 "handover", "stop-ack";
911 765
912 clocks = <&rpmhcc RPMH_CXO_CLK 766 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 767 clock-names = "xo";
914 768
915 memory-region = <&adsp_mem>; 769 memory-region = <&adsp_mem>;
916 770
917 qcom,qmp = <&aoss_qmp>; <<
918 <<
919 qcom,smem-states = <&adsp_smp2 771 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 772 qcom,smem-state-names = "stop";
921 773
922 status = "disabled"; 774 status = "disabled";
923 775
924 glink-edge { 776 glink-edge {
925 interrupts = <GIC_SPI 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 778 label = "lpass";
927 qcom,remote-pid = <2>; 779 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 780 mboxes = <&apss_shared 8>;
929 781
930 apr { 782 apr {
931 compatible = " 783 compatible = "qcom,apr-v2";
932 qcom,glink-cha 784 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = !! 785 qcom,apr-domain = <APR_DOMAIN_ADSP>;
934 #address-cells 786 #address-cells = <1>;
935 #size-cells = 787 #size-cells = <0>;
936 qcom,intents = 788 qcom,intents = <512 20>;
937 789
938 service@3 { !! 790 apr-service@3 {
939 reg = 791 reg = <APR_SVC_ADSP_CORE>;
940 compat 792 compatible = "qcom,q6core";
941 qcom,p 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 794 };
943 795
944 q6afe: service !! 796 q6afe: apr-service@4 {
945 compat 797 compatible = "qcom,q6afe";
946 reg = 798 reg = <APR_SVC_AFE>;
947 qcom,p 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 800 q6afedai: dais {
949 801 compatible = "qcom,q6afe-dais";
950 802 #address-cells = <1>;
951 803 #size-cells = <0>;
952 804 #sound-dai-cells = <1>;
953 }; 805 };
954 }; 806 };
955 807
956 q6asm: service !! 808 q6asm: apr-service@7 {
957 compat 809 compatible = "qcom,q6asm";
958 reg = 810 reg = <APR_SVC_ASM>;
959 qcom,p 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 812 q6asmdai: dais {
961 813 compatible = "qcom,q6asm-dais";
962 814 #address-cells = <1>;
963 815 #size-cells = <0>;
964 816 #sound-dai-cells = <1>;
965 817 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 818 };
967 }; 819 };
968 820
969 q6adm: service !! 821 q6adm: apr-service@8 {
970 compat 822 compatible = "qcom,q6adm";
971 reg = 823 reg = <APR_SVC_ADM>;
972 qcom,p 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 825 q6routing: routing {
974 826 compatible = "qcom,q6adm-routing";
975 827 #sound-dai-cells = <0>;
976 }; 828 };
977 }; 829 };
978 }; 830 };
979 831
980 fastrpc { 832 fastrpc {
981 compatible = " 833 compatible = "qcom,fastrpc";
982 qcom,glink-cha 834 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 835 label = "adsp";
984 qcom,non-secur <<
985 #address-cells 836 #address-cells = <1>;
986 #size-cells = 837 #size-cells = <0>;
987 838
988 compute-cb@3 { 839 compute-cb@3 {
989 compat 840 compatible = "qcom,fastrpc-compute-cb";
990 reg = 841 reg = <3>;
991 iommus 842 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 843 };
993 844
994 compute-cb@4 { 845 compute-cb@4 {
995 compat 846 compatible = "qcom,fastrpc-compute-cb";
996 reg = 847 reg = <4>;
997 iommus 848 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 849 };
999 }; 850 };
1000 }; 851 };
1001 }; 852 };
1002 853
1003 cdsp_pas: remoteproc-cdsp { 854 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 855 compatible = "qcom,sdm845-cdsp-pas";
1005 856
1006 interrupts-extended = <&intc 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 862 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 863 "handover", "stop-ack";
1013 864
1014 clocks = <&rpmhcc RPMH_CXO_CL 865 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 866 clock-names = "xo";
1016 867
1017 memory-region = <&cdsp_mem>; 868 memory-region = <&cdsp_mem>;
1018 869
1019 qcom,qmp = <&aoss_qmp>; <<
1020 <<
1021 qcom,smem-states = <&cdsp_smp 870 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 871 qcom,smem-state-names = "stop";
1023 872
1024 status = "disabled"; 873 status = "disabled";
1025 874
1026 glink-edge { 875 glink-edge {
1027 interrupts = <GIC_SPI 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 877 label = "turing";
1029 qcom,remote-pid = <5> 878 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 879 mboxes = <&apss_shared 4>;
1031 fastrpc { 880 fastrpc {
1032 compatible = 881 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 882 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 883 label = "cdsp";
1035 qcom,non-secu <<
1036 #address-cell 884 #address-cells = <1>;
1037 #size-cells = 885 #size-cells = <0>;
1038 886
1039 compute-cb@1 887 compute-cb@1 {
1040 compa 888 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 889 reg = <1>;
1042 iommu 890 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 891 };
1044 892
1045 compute-cb@2 893 compute-cb@2 {
1046 compa 894 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 895 reg = <2>;
1048 iommu 896 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 897 };
1050 898
1051 compute-cb@3 899 compute-cb@3 {
1052 compa 900 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 901 reg = <3>;
1054 iommu 902 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 903 };
1056 904
1057 compute-cb@4 905 compute-cb@4 {
1058 compa 906 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 907 reg = <4>;
1060 iommu 908 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 909 };
1062 910
1063 compute-cb@5 911 compute-cb@5 {
1064 compa 912 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 913 reg = <5>;
1066 iommu 914 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 915 };
1068 916
1069 compute-cb@6 917 compute-cb@6 {
1070 compa 918 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 919 reg = <6>;
1072 iommu 920 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 921 };
1074 922
1075 compute-cb@7 923 compute-cb@7 {
1076 compa 924 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 925 reg = <7>;
1078 iommu 926 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 927 };
1080 928
1081 compute-cb@8 929 compute-cb@8 {
1082 compa 930 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 931 reg = <8>;
1084 iommu 932 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 933 };
1086 }; 934 };
1087 }; 935 };
1088 }; 936 };
1089 937
>> 938 tcsr_mutex: hwlock {
>> 939 compatible = "qcom,tcsr-mutex";
>> 940 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 941 #hwlock-cells = <1>;
>> 942 };
>> 943
>> 944 smem {
>> 945 compatible = "qcom,smem";
>> 946 memory-region = <&smem_mem>;
>> 947 hwlocks = <&tcsr_mutex 3>;
>> 948 };
>> 949
1090 smp2p-cdsp { 950 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 951 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 952 qcom,smem = <94>, <432>;
1093 953
1094 interrupts = <GIC_SPI 576 IRQ 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 955
1096 mboxes = <&apss_shared 6>; 956 mboxes = <&apss_shared 6>;
1097 957
1098 qcom,local-pid = <0>; 958 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 959 qcom,remote-pid = <5>;
1100 960
1101 cdsp_smp2p_out: master-kernel 961 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 962 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 963 #qcom,smem-state-cells = <1>;
1104 }; 964 };
1105 965
1106 cdsp_smp2p_in: slave-kernel { 966 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 967 qcom,entry-name = "slave-kernel";
1108 968
1109 interrupt-controller; 969 interrupt-controller;
1110 #interrupt-cells = <2 970 #interrupt-cells = <2>;
1111 }; 971 };
1112 }; 972 };
1113 973
1114 smp2p-lpass { 974 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 975 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 976 qcom,smem = <443>, <429>;
1117 977
1118 interrupts = <GIC_SPI 158 IRQ 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 979
1120 mboxes = <&apss_shared 10>; 980 mboxes = <&apss_shared 10>;
1121 981
1122 qcom,local-pid = <0>; 982 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 983 qcom,remote-pid = <2>;
1124 984
1125 adsp_smp2p_out: master-kernel 985 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 986 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 987 #qcom,smem-state-cells = <1>;
1128 }; 988 };
1129 989
1130 adsp_smp2p_in: slave-kernel { 990 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 991 qcom,entry-name = "slave-kernel";
1132 992
1133 interrupt-controller; 993 interrupt-controller;
1134 #interrupt-cells = <2 994 #interrupt-cells = <2>;
1135 }; 995 };
1136 }; 996 };
1137 997
1138 smp2p-mpss { 998 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 999 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 1000 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 1002 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 1003 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 1004 qcom,remote-pid = <1>;
1145 1005
1146 modem_smp2p_out: master-kerne 1006 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 1007 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 1008 #qcom,smem-state-cells = <1>;
1149 }; 1009 };
1150 1010
1151 modem_smp2p_in: slave-kernel 1011 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 1012 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 1013 interrupt-controller;
1154 #interrupt-cells = <2 1014 #interrupt-cells = <2>;
1155 }; 1015 };
1156 1016
1157 ipa_smp2p_out: ipa-ap-to-mode 1017 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 1018 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 1019 #qcom,smem-state-cells = <1>;
1160 }; 1020 };
1161 1021
1162 ipa_smp2p_in: ipa-modem-to-ap 1022 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1023 qcom,entry-name = "ipa";
1164 interrupt-controller; 1024 interrupt-controller;
1165 #interrupt-cells = <2 1025 #interrupt-cells = <2>;
1166 }; 1026 };
1167 }; 1027 };
1168 1028
1169 smp2p-slpi { 1029 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1030 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1031 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1033 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1034 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1035 qcom,remote-pid = <3>;
1176 1036
1177 slpi_smp2p_out: master-kernel 1037 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1038 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1039 #qcom,smem-state-cells = <1>;
1180 }; 1040 };
1181 1041
1182 slpi_smp2p_in: slave-kernel { 1042 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1043 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1044 interrupt-controller;
1185 #interrupt-cells = <2 1045 #interrupt-cells = <2>;
1186 }; 1046 };
1187 }; 1047 };
1188 1048
>> 1049 psci {
>> 1050 compatible = "arm,psci-1.0";
>> 1051 method = "smc";
>> 1052 };
>> 1053
1189 soc: soc@0 { 1054 soc: soc@0 {
1190 #address-cells = <2>; 1055 #address-cells = <2>;
1191 #size-cells = <2>; 1056 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1057 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1058 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1059 compatible = "simple-bus";
1195 1060
1196 gcc: clock-controller@100000 1061 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1062 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1063 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM <<
1200 <&rpmhcc RPM <<
1201 <&sleep_clk> <<
1202 <&pcie0_phy> <<
1203 <&pcie1_phy> <<
1204 clock-names = "bi_tcx <<
1205 "bi_tcx <<
1206 "sleep_ <<
1207 "pcie_0 <<
1208 "pcie_1 <<
1209 #clock-cells = <1>; 1064 #clock-cells = <1>;
1210 #reset-cells = <1>; 1065 #reset-cells = <1>;
1211 #power-domain-cells = 1066 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 1067 };
1214 1068
1215 qfprom@784000 { 1069 qfprom@784000 {
1216 compatible = "qcom,sd !! 1070 compatible = "qcom,qfprom";
1217 reg = <0 0x00784000 0 1071 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1072 #address-cells = <1>;
1219 #size-cells = <1>; 1073 #size-cells = <1>;
1220 1074
1221 qusb2p_hstx_trim: hst 1075 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1076 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1077 bits = <1 4>;
1224 }; 1078 };
1225 1079
1226 qusb2s_hstx_trim: hst 1080 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1081 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1082 bits = <6 4>;
1229 }; 1083 };
1230 }; 1084 };
1231 1085
1232 rng: rng@793000 { 1086 rng: rng@793000 {
1233 compatible = "qcom,pr 1087 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1088 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1089 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1090 clock-names = "core";
1237 }; 1091 };
1238 1092
1239 gpi_dma0: dma-controller@8000 !! 1093 qup_opp_table: qup-opp-table {
1240 #dma-cells = <3>; !! 1094 compatible = "operating-points-v2";
1241 compatible = "qcom,sd !! 1095
1242 reg = <0 0x00800000 0 !! 1096 opp-50000000 {
1243 interrupts = <GIC_SPI !! 1097 opp-hz = /bits/ 64 <50000000>;
1244 <GIC_SPI !! 1098 required-opps = <&rpmhpd_opp_min_svs>;
1245 <GIC_SPI !! 1099 };
1246 <GIC_SPI !! 1100
1247 <GIC_SPI !! 1101 opp-75000000 {
1248 <GIC_SPI !! 1102 opp-hz = /bits/ 64 <75000000>;
1249 <GIC_SPI !! 1103 required-opps = <&rpmhpd_opp_low_svs>;
1250 <GIC_SPI !! 1104 };
1251 <GIC_SPI !! 1105
1252 <GIC_SPI !! 1106 opp-100000000 {
1253 <GIC_SPI !! 1107 opp-hz = /bits/ 64 <100000000>;
1254 <GIC_SPI !! 1108 required-opps = <&rpmhpd_opp_svs>;
1255 <GIC_SPI !! 1109 };
1256 dma-channels = <13>; !! 1110
1257 dma-channel-mask = <0 !! 1111 opp-128000000 {
1258 iommus = <&apps_smmu !! 1112 opp-hz = /bits/ 64 <128000000>;
1259 status = "disabled"; !! 1113 required-opps = <&rpmhpd_opp_nom>;
>> 1114 };
1260 }; 1115 };
1261 1116
1262 qupv3_id_0: geniqup@8c0000 { 1117 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1118 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1119 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1120 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1121 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1122 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1123 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1124 #address-cells = <2>;
1270 #size-cells = <2>; 1125 #size-cells = <2>;
1271 ranges; 1126 ranges;
1272 interconnects = <&agg 1127 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1128 interconnect-names = "qup-core";
1274 status = "disabled"; 1129 status = "disabled";
1275 1130
1276 i2c0: i2c@880000 { 1131 i2c0: i2c@880000 {
1277 compatible = 1132 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1133 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1134 clock-names = "se";
1280 clocks = <&gc 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1136 pinctrl-names = "default";
1282 pinctrl-0 = < 1137 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1138 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1139 #address-cells = <1>;
1285 #size-cells = 1140 #size-cells = <0>;
1286 power-domains 1141 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1142 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1143 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1144 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1145 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1146 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 1147 status = "disabled";
1296 }; 1148 };
1297 1149
1298 spi0: spi@880000 { 1150 spi0: spi@880000 {
1299 compatible = 1151 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1152 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1153 clock-names = "se";
1302 clocks = <&gc 1154 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1155 pinctrl-names = "default";
1304 pinctrl-0 = < 1156 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1157 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1158 #address-cells = <1>;
1307 #size-cells = 1159 #size-cells = <0>;
1308 interconnects 1160 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1161 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1162 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 1163 status = "disabled";
1315 }; 1164 };
1316 1165
1317 uart0: serial@880000 1166 uart0: serial@880000 {
1318 compatible = 1167 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1168 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1169 clock-names = "se";
1321 clocks = <&gc 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1171 pinctrl-names = "default";
1323 pinctrl-0 = < 1172 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1173 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1174 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1175 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1176 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1177 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1178 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1179 status = "disabled";
1331 }; 1180 };
1332 1181
1333 i2c1: i2c@884000 { 1182 i2c1: i2c@884000 {
1334 compatible = 1183 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1184 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1185 clock-names = "se";
1337 clocks = <&gc 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1187 pinctrl-names = "default";
1339 pinctrl-0 = < 1188 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1189 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1190 #address-cells = <1>;
1342 #size-cells = 1191 #size-cells = <0>;
1343 power-domains 1192 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1193 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1194 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1195 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1196 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1197 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 1198 status = "disabled";
1353 }; 1199 };
1354 1200
1355 spi1: spi@884000 { 1201 spi1: spi@884000 {
1356 compatible = 1202 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1203 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1204 clock-names = "se";
1359 clocks = <&gc 1205 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1206 pinctrl-names = "default";
1361 pinctrl-0 = < 1207 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1208 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1209 #address-cells = <1>;
1364 #size-cells = 1210 #size-cells = <0>;
1365 interconnects 1211 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1212 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1213 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 1214 status = "disabled";
1372 }; 1215 };
1373 1216
1374 uart1: serial@884000 1217 uart1: serial@884000 {
1375 compatible = 1218 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1219 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1220 clock-names = "se";
1378 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1222 pinctrl-names = "default";
1380 pinctrl-0 = < 1223 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1224 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1225 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1226 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1227 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1228 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1229 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1230 status = "disabled";
1388 }; 1231 };
1389 1232
1390 i2c2: i2c@888000 { 1233 i2c2: i2c@888000 {
1391 compatible = 1234 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1235 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1236 clock-names = "se";
1394 clocks = <&gc 1237 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1238 pinctrl-names = "default";
1396 pinctrl-0 = < 1239 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1240 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1241 #address-cells = <1>;
1399 #size-cells = 1242 #size-cells = <0>;
1400 power-domains 1243 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1244 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1245 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1246 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1247 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1248 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 1249 status = "disabled";
1410 }; 1250 };
1411 1251
1412 spi2: spi@888000 { 1252 spi2: spi@888000 {
1413 compatible = 1253 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1254 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1255 clock-names = "se";
1416 clocks = <&gc 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1257 pinctrl-names = "default";
1418 pinctrl-0 = < 1258 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1259 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1260 #address-cells = <1>;
1421 #size-cells = 1261 #size-cells = <0>;
1422 interconnects 1262 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1263 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1264 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 1265 status = "disabled";
1429 }; 1266 };
1430 1267
1431 uart2: serial@888000 1268 uart2: serial@888000 {
1432 compatible = 1269 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1270 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1271 clock-names = "se";
1435 clocks = <&gc 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1273 pinctrl-names = "default";
1437 pinctrl-0 = < 1274 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1275 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1276 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1277 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1278 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1279 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1280 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1281 status = "disabled";
1445 }; 1282 };
1446 1283
1447 i2c3: i2c@88c000 { 1284 i2c3: i2c@88c000 {
1448 compatible = 1285 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1286 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1287 clock-names = "se";
1451 clocks = <&gc 1288 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1289 pinctrl-names = "default";
1453 pinctrl-0 = < 1290 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1291 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1292 #address-cells = <1>;
1456 #size-cells = 1293 #size-cells = <0>;
1457 power-domains 1294 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1295 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1296 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1297 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1298 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1299 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 1300 status = "disabled";
1467 }; 1301 };
1468 1302
1469 spi3: spi@88c000 { 1303 spi3: spi@88c000 {
1470 compatible = 1304 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1305 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1306 clock-names = "se";
1473 clocks = <&gc 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1308 pinctrl-names = "default";
1475 pinctrl-0 = < 1309 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1310 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1311 #address-cells = <1>;
1478 #size-cells = 1312 #size-cells = <0>;
1479 interconnects 1313 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1314 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1315 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 1316 status = "disabled";
1486 }; 1317 };
1487 1318
1488 uart3: serial@88c000 1319 uart3: serial@88c000 {
1489 compatible = 1320 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1321 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1322 clock-names = "se";
1492 clocks = <&gc 1323 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1324 pinctrl-names = "default";
1494 pinctrl-0 = < 1325 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1326 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1327 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1328 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1329 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1330 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1331 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1332 status = "disabled";
1502 }; 1333 };
1503 1334
1504 i2c4: i2c@890000 { 1335 i2c4: i2c@890000 {
1505 compatible = 1336 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1337 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1338 clock-names = "se";
1508 clocks = <&gc 1339 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1340 pinctrl-names = "default";
1510 pinctrl-0 = < 1341 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1342 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1343 #address-cells = <1>;
1513 #size-cells = 1344 #size-cells = <0>;
1514 power-domains 1345 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1346 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1347 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1348 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1349 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1350 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 1351 status = "disabled";
1524 }; 1352 };
1525 1353
1526 spi4: spi@890000 { 1354 spi4: spi@890000 {
1527 compatible = 1355 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1356 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1357 clock-names = "se";
1530 clocks = <&gc 1358 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1359 pinctrl-names = "default";
1532 pinctrl-0 = < 1360 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1361 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1362 #address-cells = <1>;
1535 #size-cells = 1363 #size-cells = <0>;
1536 interconnects 1364 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1365 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1366 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 1367 status = "disabled";
1543 }; 1368 };
1544 1369
1545 uart4: serial@890000 1370 uart4: serial@890000 {
1546 compatible = 1371 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1372 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1373 clock-names = "se";
1549 clocks = <&gc 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1375 pinctrl-names = "default";
1551 pinctrl-0 = < 1376 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1377 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1378 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1379 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1380 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1381 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1382 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1383 status = "disabled";
1559 }; 1384 };
1560 1385
1561 i2c5: i2c@894000 { 1386 i2c5: i2c@894000 {
1562 compatible = 1387 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1388 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1389 clock-names = "se";
1565 clocks = <&gc 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1391 pinctrl-names = "default";
1567 pinctrl-0 = < 1392 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1393 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1394 #address-cells = <1>;
1570 #size-cells = 1395 #size-cells = <0>;
1571 power-domains 1396 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1397 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1398 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1399 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1400 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1401 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 1402 status = "disabled";
1581 }; 1403 };
1582 1404
1583 spi5: spi@894000 { 1405 spi5: spi@894000 {
1584 compatible = 1406 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1407 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1408 clock-names = "se";
1587 clocks = <&gc 1409 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1410 pinctrl-names = "default";
1589 pinctrl-0 = < 1411 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1412 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1413 #address-cells = <1>;
1592 #size-cells = 1414 #size-cells = <0>;
1593 interconnects 1415 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1416 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1417 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 1418 status = "disabled";
1600 }; 1419 };
1601 1420
1602 uart5: serial@894000 1421 uart5: serial@894000 {
1603 compatible = 1422 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1423 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1424 clock-names = "se";
1606 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1426 pinctrl-names = "default";
1608 pinctrl-0 = < 1427 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1428 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1429 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1430 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1431 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1432 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1433 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1434 status = "disabled";
1616 }; 1435 };
1617 1436
1618 i2c6: i2c@898000 { 1437 i2c6: i2c@898000 {
1619 compatible = 1438 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1439 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1440 clock-names = "se";
1622 clocks = <&gc 1441 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1442 pinctrl-names = "default";
1624 pinctrl-0 = < 1443 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1444 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1445 #address-cells = <1>;
1627 #size-cells = 1446 #size-cells = <0>;
1628 power-domains 1447 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1448 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1449 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1450 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1451 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1452 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 1453 status = "disabled";
1638 }; 1454 };
1639 1455
1640 spi6: spi@898000 { 1456 spi6: spi@898000 {
1641 compatible = 1457 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1458 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1459 clock-names = "se";
1644 clocks = <&gc 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1461 pinctrl-names = "default";
1646 pinctrl-0 = < 1462 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1463 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1464 #address-cells = <1>;
1649 #size-cells = 1465 #size-cells = <0>;
1650 interconnects 1466 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1467 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1468 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 1469 status = "disabled";
1657 }; 1470 };
1658 1471
1659 uart6: serial@898000 1472 uart6: serial@898000 {
1660 compatible = 1473 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1474 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1475 clock-names = "se";
1663 clocks = <&gc 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1477 pinctrl-names = "default";
1665 pinctrl-0 = < 1478 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1479 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1480 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1481 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1482 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1483 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1484 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1485 status = "disabled";
1673 }; 1486 };
1674 1487
1675 i2c7: i2c@89c000 { 1488 i2c7: i2c@89c000 {
1676 compatible = 1489 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1490 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1491 clock-names = "se";
1679 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1493 pinctrl-names = "default";
1681 pinctrl-0 = < 1494 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1495 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1496 #address-cells = <1>;
1684 #size-cells = 1497 #size-cells = <0>;
1685 power-domains 1498 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1499 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1500 status = "disabled";
1688 }; 1501 };
1689 1502
1690 spi7: spi@89c000 { 1503 spi7: spi@89c000 {
1691 compatible = 1504 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1505 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1506 clock-names = "se";
1694 clocks = <&gc 1507 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1508 pinctrl-names = "default";
1696 pinctrl-0 = < 1509 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1510 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1511 #address-cells = <1>;
1699 #size-cells = 1512 #size-cells = <0>;
1700 interconnects 1513 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1514 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1515 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 1516 status = "disabled";
1707 }; 1517 };
1708 1518
1709 uart7: serial@89c000 1519 uart7: serial@89c000 {
1710 compatible = 1520 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1521 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1522 clock-names = "se";
1713 clocks = <&gc 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1524 pinctrl-names = "default";
1715 pinctrl-0 = < 1525 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1526 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1527 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1528 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1529 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1530 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1531 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1532 status = "disabled";
1723 }; 1533 };
1724 }; 1534 };
1725 1535
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 1536 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1537 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1538 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1539 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1540 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1541 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1542 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1543 #address-cells = <2>;
1757 #size-cells = <2>; 1544 #size-cells = <2>;
1758 ranges; 1545 ranges;
1759 interconnects = <&agg 1546 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1547 interconnect-names = "qup-core";
1761 status = "disabled"; 1548 status = "disabled";
1762 1549
1763 i2c8: i2c@a80000 { 1550 i2c8: i2c@a80000 {
1764 compatible = 1551 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1552 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1553 clock-names = "se";
1767 clocks = <&gc 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1555 pinctrl-names = "default";
1769 pinctrl-0 = < 1556 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1557 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1558 #address-cells = <1>;
1772 #size-cells = 1559 #size-cells = <0>;
1773 power-domains 1560 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1561 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1562 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1563 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1564 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1565 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 1566 status = "disabled";
1783 }; 1567 };
1784 1568
1785 spi8: spi@a80000 { 1569 spi8: spi@a80000 {
1786 compatible = 1570 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1571 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1572 clock-names = "se";
1789 clocks = <&gc 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1574 pinctrl-names = "default";
1791 pinctrl-0 = < 1575 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1576 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1577 #address-cells = <1>;
1794 #size-cells = 1578 #size-cells = <0>;
1795 interconnects 1579 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1580 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1581 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 1582 status = "disabled";
1802 }; 1583 };
1803 1584
1804 uart8: serial@a80000 1585 uart8: serial@a80000 {
1805 compatible = 1586 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1587 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1588 clock-names = "se";
1808 clocks = <&gc 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1590 pinctrl-names = "default";
1810 pinctrl-0 = < 1591 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1592 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1593 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1594 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1595 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1596 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1597 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1598 status = "disabled";
1818 }; 1599 };
1819 1600
1820 i2c9: i2c@a84000 { 1601 i2c9: i2c@a84000 {
1821 compatible = 1602 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1603 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1604 clock-names = "se";
1824 clocks = <&gc 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1606 pinctrl-names = "default";
1826 pinctrl-0 = < 1607 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1609 #address-cells = <1>;
1829 #size-cells = 1610 #size-cells = <0>;
1830 power-domains 1611 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1612 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1613 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1615 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1616 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 1617 status = "disabled";
1840 }; 1618 };
1841 1619
1842 spi9: spi@a84000 { 1620 spi9: spi@a84000 {
1843 compatible = 1621 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1622 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1623 clock-names = "se";
1846 clocks = <&gc 1624 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1625 pinctrl-names = "default";
1848 pinctrl-0 = < 1626 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1627 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1628 #address-cells = <1>;
1851 #size-cells = 1629 #size-cells = <0>;
1852 interconnects 1630 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1631 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1632 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 1633 status = "disabled";
1859 }; 1634 };
1860 1635
1861 uart9: serial@a84000 1636 uart9: serial@a84000 {
1862 compatible = 1637 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1638 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1639 clock-names = "se";
1865 clocks = <&gc 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1641 pinctrl-names = "default";
1867 pinctrl-0 = < 1642 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1643 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1644 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1645 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1646 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1647 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1648 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1649 status = "disabled";
1875 }; 1650 };
1876 1651
1877 i2c10: i2c@a88000 { 1652 i2c10: i2c@a88000 {
1878 compatible = 1653 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1654 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1655 clock-names = "se";
1881 clocks = <&gc 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1657 pinctrl-names = "default";
1883 pinctrl-0 = < 1658 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1659 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1660 #address-cells = <1>;
1886 #size-cells = 1661 #size-cells = <0>;
1887 power-domains 1662 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1663 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1664 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1665 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1666 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1667 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 1668 status = "disabled";
1897 }; 1669 };
1898 1670
1899 spi10: spi@a88000 { 1671 spi10: spi@a88000 {
1900 compatible = 1672 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1673 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1674 clock-names = "se";
1903 clocks = <&gc 1675 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1676 pinctrl-names = "default";
1905 pinctrl-0 = < 1677 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1678 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1679 #address-cells = <1>;
1908 #size-cells = 1680 #size-cells = <0>;
1909 interconnects 1681 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1682 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1683 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1684 status = "disabled";
1916 }; 1685 };
1917 1686
1918 uart10: serial@a88000 1687 uart10: serial@a88000 {
1919 compatible = 1688 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1689 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1690 clock-names = "se";
1922 clocks = <&gc 1691 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1692 pinctrl-names = "default";
1924 pinctrl-0 = < 1693 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1694 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1695 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1696 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1697 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1698 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1699 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1700 status = "disabled";
1932 }; 1701 };
1933 1702
1934 i2c11: i2c@a8c000 { 1703 i2c11: i2c@a8c000 {
1935 compatible = 1704 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1705 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1706 clock-names = "se";
1938 clocks = <&gc 1707 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1708 pinctrl-names = "default";
1940 pinctrl-0 = < 1709 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1710 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1711 #address-cells = <1>;
1943 #size-cells = 1712 #size-cells = <0>;
1944 power-domains 1713 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1714 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1715 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1716 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1717 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1718 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1719 status = "disabled";
1954 }; 1720 };
1955 1721
1956 spi11: spi@a8c000 { 1722 spi11: spi@a8c000 {
1957 compatible = 1723 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1724 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1725 clock-names = "se";
1960 clocks = <&gc 1726 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1727 pinctrl-names = "default";
1962 pinctrl-0 = < 1728 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1729 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1730 #address-cells = <1>;
1965 #size-cells = 1731 #size-cells = <0>;
1966 interconnects 1732 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1733 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1734 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1735 status = "disabled";
1973 }; 1736 };
1974 1737
1975 uart11: serial@a8c000 1738 uart11: serial@a8c000 {
1976 compatible = 1739 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1740 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1741 clock-names = "se";
1979 clocks = <&gc 1742 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1743 pinctrl-names = "default";
1981 pinctrl-0 = < 1744 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1745 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1746 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1747 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1748 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1749 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1750 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1751 status = "disabled";
1989 }; 1752 };
1990 1753
1991 i2c12: i2c@a90000 { 1754 i2c12: i2c@a90000 {
1992 compatible = 1755 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1756 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1757 clock-names = "se";
1995 clocks = <&gc 1758 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1759 pinctrl-names = "default";
1997 pinctrl-0 = < 1760 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1761 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1762 #address-cells = <1>;
2000 #size-cells = 1763 #size-cells = <0>;
2001 power-domains 1764 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1765 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 1766 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 1767 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 1768 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 1769 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1770 status = "disabled";
2011 }; 1771 };
2012 1772
2013 spi12: spi@a90000 { 1773 spi12: spi@a90000 {
2014 compatible = 1774 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1775 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1776 clock-names = "se";
2017 clocks = <&gc 1777 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1778 pinctrl-names = "default";
2019 pinctrl-0 = < 1779 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1780 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1781 #address-cells = <1>;
2022 #size-cells = 1782 #size-cells = <0>;
2023 interconnects 1783 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 1784 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 1785 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1786 status = "disabled";
2030 }; 1787 };
2031 1788
2032 uart12: serial@a90000 1789 uart12: serial@a90000 {
2033 compatible = 1790 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1791 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1792 clock-names = "se";
2036 clocks = <&gc 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1794 pinctrl-names = "default";
2038 pinctrl-0 = < 1795 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1796 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1797 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1798 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 1799 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 1800 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 1801 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 1802 status = "disabled";
2046 }; 1803 };
2047 1804
2048 i2c13: i2c@a94000 { 1805 i2c13: i2c@a94000 {
2049 compatible = 1806 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1807 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1808 clock-names = "se";
2052 clocks = <&gc 1809 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1810 pinctrl-names = "default";
2054 pinctrl-0 = < 1811 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1812 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1813 #address-cells = <1>;
2057 #size-cells = 1814 #size-cells = <0>;
2058 power-domains 1815 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1816 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 1817 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 1818 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 1819 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 1820 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1821 status = "disabled";
2068 }; 1822 };
2069 1823
2070 spi13: spi@a94000 { 1824 spi13: spi@a94000 {
2071 compatible = 1825 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1826 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1827 clock-names = "se";
2074 clocks = <&gc 1828 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1829 pinctrl-names = "default";
2076 pinctrl-0 = < 1830 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1831 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1832 #address-cells = <1>;
2079 #size-cells = 1833 #size-cells = <0>;
2080 interconnects 1834 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 1835 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 1836 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1837 status = "disabled";
2087 }; 1838 };
2088 1839
2089 uart13: serial@a94000 1840 uart13: serial@a94000 {
2090 compatible = 1841 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1842 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1843 clock-names = "se";
2093 clocks = <&gc 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1845 pinctrl-names = "default";
2095 pinctrl-0 = < 1846 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1847 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 1848 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 1849 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 1850 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 1851 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 1852 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 1853 status = "disabled";
2103 }; 1854 };
2104 1855
2105 i2c14: i2c@a98000 { 1856 i2c14: i2c@a98000 {
2106 compatible = 1857 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1858 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1859 clock-names = "se";
2109 clocks = <&gc 1860 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1861 pinctrl-names = "default";
2111 pinctrl-0 = < 1862 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1863 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1864 #address-cells = <1>;
2114 #size-cells = 1865 #size-cells = <0>;
2115 power-domains 1866 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 1867 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 1868 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 1869 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 1870 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 1871 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1872 status = "disabled";
2125 }; 1873 };
2126 1874
2127 spi14: spi@a98000 { 1875 spi14: spi@a98000 {
2128 compatible = 1876 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1877 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1878 clock-names = "se";
2131 clocks = <&gc 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1880 pinctrl-names = "default";
2133 pinctrl-0 = < 1881 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1882 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1883 #address-cells = <1>;
2136 #size-cells = 1884 #size-cells = <0>;
2137 interconnects 1885 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 1886 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 1887 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1888 status = "disabled";
2144 }; 1889 };
2145 1890
2146 uart14: serial@a98000 1891 uart14: serial@a98000 {
2147 compatible = 1892 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1893 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1894 clock-names = "se";
2150 clocks = <&gc 1895 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1896 pinctrl-names = "default";
2152 pinctrl-0 = < 1897 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1898 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 1899 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 1900 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 1901 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 1902 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 1903 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 1904 status = "disabled";
2160 }; 1905 };
2161 1906
2162 i2c15: i2c@a9c000 { 1907 i2c15: i2c@a9c000 {
2163 compatible = 1908 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1909 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1910 clock-names = "se";
2166 clocks = <&gc 1911 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1912 pinctrl-names = "default";
2168 pinctrl-0 = < 1913 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1914 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1915 #address-cells = <1>;
2171 #size-cells = 1916 #size-cells = <0>;
2172 power-domains 1917 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 1918 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 1919 status = "disabled";
2175 interconnects 1920 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 1921 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 1922 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 1923 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1924 };
2183 1925
2184 spi15: spi@a9c000 { 1926 spi15: spi@a9c000 {
2185 compatible = 1927 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1928 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1929 clock-names = "se";
2188 clocks = <&gc 1930 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1931 pinctrl-names = "default";
2190 pinctrl-0 = < 1932 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1933 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1934 #address-cells = <1>;
2193 #size-cells = 1935 #size-cells = <0>;
2194 interconnects 1936 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 1937 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 1938 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1939 status = "disabled";
2201 }; 1940 };
2202 1941
2203 uart15: serial@a9c000 1942 uart15: serial@a9c000 {
2204 compatible = 1943 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1944 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1945 clock-names = "se";
2207 clocks = <&gc 1946 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1947 pinctrl-names = "default";
2209 pinctrl-0 = < 1948 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1949 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 1950 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 1951 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 1952 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 1953 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 1954 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 1955 status = "disabled";
2217 }; 1956 };
2218 }; 1957 };
2219 1958
2220 llcc: system-cache-controller !! 1959 system-cache-controller@1100000 {
2221 compatible = "qcom,sd 1960 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 1961 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 1962 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 1963 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 1964 };
2229 1965
2230 dma@10a2000 { !! 1966 pcie0: pci@1c00000 {
2231 compatible = "qcom,sd !! 1967 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 1968 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 1969 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 1970 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 1971 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 1972 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 1973 device_type = "pci";
2319 linux,pci-domain = <0 1974 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 1975 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 1976 num-lanes = <1>;
2322 1977
2323 #address-cells = <3>; 1978 #address-cells = <3>;
2324 #size-cells = <2>; 1979 #size-cells = <2>;
2325 1980
2326 ranges = <0x01000000 !! 1981 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327 <0x02000000 !! 1982 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328 1983
2329 interrupts = <GIC_SPI 1984 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 1985 interrupt-names = "msi";
2331 #interrupt-cells = <1 1986 #interrupt-cells = <1>;
2332 interrupt-map-mask = 1987 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 !! 1988 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 !! 1989 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 !! 1990 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 !! 1991 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 1992
2338 clocks = <&gcc GCC_PC 1993 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 1994 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 1995 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 1996 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 1997 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 1998 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 1999 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2000 clock-names = "pipe",
2346 "aux", 2001 "aux",
2347 "cfg", 2002 "cfg",
2348 "bus_ma 2003 "bus_master",
2349 "bus_sl 2004 "bus_slave",
2350 "slave_ 2005 "slave_q2a",
2351 "tbu"; 2006 "tbu";
2352 2007
>> 2008 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 2009 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2010 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2011 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2012 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2013 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2014 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2015 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2016 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2017 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2018 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2019 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2020 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2021 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2022 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2023 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2024 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2025
2370 resets = <&gcc GCC_PC 2026 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2027 reset-names = "pci";
2372 2028
2373 power-domains = <&gcc 2029 power-domains = <&gcc PCIE_0_GDSC>;
2374 2030
2375 phys = <&pcie0_phy>; !! 2031 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2032 phy-names = "pciephy";
2377 2033
2378 status = "disabled"; 2034 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2035 };
2390 2036
2391 pcie0_phy: phy@1c06000 { 2037 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2038 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2039 reg = <0 0x01c06000 0 0x18c>;
>> 2040 #address-cells = <2>;
>> 2041 #size-cells = <2>;
>> 2042 ranges;
2394 clocks = <&gcc GCC_PC 2043 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2044 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2045 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2046 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2047 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2048
2410 resets = <&gcc GCC_PC 2049 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2050 reset-names = "phy";
2412 2051
2413 assigned-clocks = <&g 2052 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2053 assigned-clock-rates = <100000000>;
2415 2054
2416 status = "disabled"; 2055 status = "disabled";
>> 2056
>> 2057 pcie0_lane: lanes@1c06200 {
>> 2058 reg = <0 0x01c06200 0 0x128>,
>> 2059 <0 0x01c06400 0 0x1fc>,
>> 2060 <0 0x01c06800 0 0x218>,
>> 2061 <0 0x01c06600 0 0x70>;
>> 2062 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2063 clock-names = "pipe0";
>> 2064
>> 2065 #phy-cells = <0>;
>> 2066 clock-output-names = "pcie_0_pipe_clk";
>> 2067 };
2417 }; 2068 };
2418 2069
2419 pcie1: pcie@1c08000 { !! 2070 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc !! 2071 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2421 reg = <0 0x01c08000 0 2072 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2073 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2074 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 2075 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 2076 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 2077 device_type = "pci";
2428 linux,pci-domain = <1 2078 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2079 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2080 num-lanes = <1>;
2431 2081
2432 #address-cells = <3>; 2082 #address-cells = <3>;
2433 #size-cells = <2>; 2083 #size-cells = <2>;
2434 2084
2435 ranges = <0x01000000 !! 2085 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2086 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2087
2438 interrupts = <GIC_SPI 2088 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2089 interrupt-names = "msi";
2440 #interrupt-cells = <1 2090 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2091 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 !! 2092 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 !! 2093 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 !! 2094 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 !! 2095 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2096
2447 clocks = <&gcc GCC_PC 2097 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2098 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2099 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2100 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2101 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2102 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2103 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2104 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2105 clock-names = "pipe",
2456 "aux", 2106 "aux",
2457 "cfg", 2107 "cfg",
2458 "bus_ma 2108 "bus_master",
2459 "bus_sl 2109 "bus_slave",
2460 "slave_ 2110 "slave_q2a",
2461 "ref", 2111 "ref",
2462 "tbu"; 2112 "tbu";
2463 2113
2464 assigned-clocks = <&g 2114 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2115 assigned-clock-rates = <19200000>;
2466 2116
>> 2117 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 2118 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2119 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2120 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2121 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2122 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2123 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2124 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2125 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2126 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2127 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2128 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2129 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2130 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2131 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2132 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2133 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2134
2484 resets = <&gcc GCC_PC 2135 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2136 reset-names = "pci";
2486 2137
2487 power-domains = <&gcc 2138 power-domains = <&gcc PCIE_1_GDSC>;
2488 2139
2489 phys = <&pcie1_phy>; !! 2140 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2141 phy-names = "pciephy";
2491 2142
2492 status = "disabled"; 2143 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2144 };
2504 2145
2505 pcie1_phy: phy@1c0a000 { 2146 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2147 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2148 reg = <0 0x01c0a000 0 0x800>;
>> 2149 #address-cells = <2>;
>> 2150 #size-cells = <2>;
>> 2151 ranges;
2508 clocks = <&gcc GCC_PC 2152 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2153 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2154 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2155 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2156 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2157
2524 resets = <&gcc GCC_PC 2158 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2159 reset-names = "phy";
2526 2160
2527 assigned-clocks = <&g 2161 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2162 assigned-clock-rates = <100000000>;
2529 2163
2530 status = "disabled"; 2164 status = "disabled";
>> 2165
>> 2166 pcie1_lane: lanes@1c06200 {
>> 2167 reg = <0 0x01c0a800 0 0x800>,
>> 2168 <0 0x01c0a800 0 0x800>,
>> 2169 <0 0x01c0b800 0 0x400>;
>> 2170 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2171 clock-names = "pipe0";
>> 2172
>> 2173 #phy-cells = <0>;
>> 2174 clock-output-names = "pcie_1_pipe_clk";
>> 2175 };
2531 }; 2176 };
2532 2177
2533 mem_noc: interconnect@1380000 2178 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2179 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2180 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2181 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2182 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2183 };
2539 2184
2540 dc_noc: interconnect@14e0000 2185 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2186 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2187 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2188 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2189 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2190 };
2546 2191
2547 config_noc: interconnect@1500 2192 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2193 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2194 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2195 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2196 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2197 };
2553 2198
2554 system_noc: interconnect@1620 2199 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2200 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2201 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2202 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2203 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2204 };
2560 2205
2561 aggre1_noc: interconnect@16e0 2206 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2207 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2208 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2209 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2210 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2211 };
2567 2212
2568 aggre2_noc: interconnect@1700 2213 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2214 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2215 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2216 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2217 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2218 };
2574 2219
2575 mmss_noc: interconnect@174000 2220 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2221 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2222 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2223 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2224 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2225 };
2581 2226
2582 ufs_mem_hc: ufshc@1d84000 { 2227 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2228 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2229 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2230 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2231 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2232 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2233 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2234 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2235 phy-names = "ufsphy";
2591 lanes-per-direction = 2236 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2237 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2238 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2239 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2240 reset-names = "rst";
2596 2241
2597 iommus = <&apps_smmu 2242 iommus = <&apps_smmu 0x100 0xf>;
2598 2243
2599 clock-names = 2244 clock-names =
2600 "core_clk", 2245 "core_clk",
2601 "bus_aggr_clk 2246 "bus_aggr_clk",
2602 "iface_clk", 2247 "iface_clk",
2603 "core_clk_uni 2248 "core_clk_unipro",
2604 "ref_clk", 2249 "ref_clk",
2605 "tx_lane0_syn 2250 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2251 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2252 "rx_lane1_sync_clk",
2608 "ice_core_clk 2253 "ice_core_clk";
2609 clocks = 2254 clocks =
2610 <&gcc GCC_UFS 2255 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2256 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2257 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2258 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2259 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2260 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2261 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2262 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2263 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2264 freq-table-hz =
2620 operating-points-v2 = !! 2265 <50000000 200000000>,
2621 !! 2266 <0 0>,
2622 interconnects = <&agg !! 2267 <0 0>,
2623 <&gla !! 2268 <37500000 150000000>,
2624 interconnect-names = !! 2269 <0 0>,
>> 2270 <0 0>,
>> 2271 <0 0>,
>> 2272 <0 0>,
>> 2273 <0 300000000>;
2625 2274
2626 status = "disabled"; 2275 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2276 };
2658 2277
2659 ufs_mem_phy: phy@1d87000 { 2278 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2279 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2280 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2281 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2282 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2283 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2284 clock-names = "ref",
2667 "ref_au !! 2285 "ref_aux";
2668 "qref"; !! 2286 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2287 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2288
2672 resets = <&ufs_mem_hc 2289 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2290 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2291 status = "disabled";
>> 2292
>> 2293 ufs_mem_phy_lanes: lanes@1d87400 {
>> 2294 reg = <0 0x01d87400 0 0x108>,
>> 2295 <0 0x01d87600 0 0x1e0>,
>> 2296 <0 0x01d87c00 0 0x1dc>,
>> 2297 <0 0x01d87800 0 0x108>,
>> 2298 <0 0x01d87a00 0 0x1e0>;
>> 2299 #phy-cells = <0>;
>> 2300 };
2677 }; 2301 };
2678 2302
2679 cryptobam: dma-controller@1dc !! 2303 cryptobam: dma@1dc4000 {
2680 compatible = "qcom,ba !! 2304 compatible = "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2305 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2306 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM !! 2307 clocks = <&rpmhcc 15>;
2684 clock-names = "bam_cl 2308 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2309 #dma-cells = <1>;
2686 qcom,ee = <0>; 2310 qcom,ee = <0>;
2687 qcom,controlled-remot !! 2311 qcom,controlled-remotely = <1>;
2688 iommus = <&apps_smmu 2312 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2313 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2314 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2315 <&apps_smmu 0x716 0x1>;
2692 }; 2316 };
2693 2317
2694 crypto: crypto@1dfa000 { 2318 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2319 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2320 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2321 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE !! 2322 <&gcc GCC_CE1_AHB_CLK>,
2699 <&rpmhcc RPM !! 2323 <&rpmhcc 15>;
2700 clock-names = "iface" 2324 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2325 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2326 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2327 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2328 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2329 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2330 <&apps_smmu 0x716 0x1>;
2707 }; 2331 };
2708 2332
2709 ipa: ipa@1e40000 { 2333 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2334 compatible = "qcom,sdm845-ipa";
2711 2335
2712 iommus = <&apps_smmu 2336 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2337 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 !! 2338 reg = <0 0x1e40000 0 0x7000>,
2715 <0 0x01e47000 0 !! 2339 <0 0x1e47000 0 0x2000>,
2716 <0 0x01e04000 0 !! 2340 <0 0x1e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2341 reg-names = "ipa-reg",
2718 "ipa-shar 2342 "ipa-shared",
2719 "gsi"; 2343 "gsi";
2720 2344
2721 interrupts-extended = 2345 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2346 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2347 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2348 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2349 interrupt-names = "ipa",
2726 "gs 2350 "gsi",
2727 "ip 2351 "ipa-clock-query",
2728 "ip 2352 "ipa-setup-ready";
2729 2353
2730 clocks = <&rpmhcc RPM 2354 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2355 clock-names = "core";
2732 2356
2733 interconnects = <&agg 2357 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2358 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2359 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2360 interconnect-names = "memory",
2737 2361 "imem",
2738 2362 "config";
2739 2363
2740 qcom,smem-states = <& 2364 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2365 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2366 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2367 "ipa-clock-enabled";
2744 2368
2745 status = "disabled"; 2369 status = "disabled";
2746 }; 2370 };
2747 2371
2748 tcsr_mutex: hwlock@1f40000 { !! 2372 tcsr_mutex_regs: syscon@1f40000 {
2749 compatible = "qcom,tc !! 2373 compatible = "syscon";
2750 reg = <0 0x01f40000 0 !! 2374 reg = <0 0x01f40000 0 0x40000>;
2751 #hwlock-cells = <1>; <<
2752 }; <<
2753 <<
2754 tcsr_regs_1: syscon@1f60000 { <<
2755 compatible = "qcom,sd <<
2756 reg = <0 0x01f60000 0 <<
2757 }; 2375 };
2758 2376
2759 tlmm: pinctrl@3400000 { 2377 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2378 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2379 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2380 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2381 gpio-controller;
2764 #gpio-cells = <2>; 2382 #gpio-cells = <2>;
2765 interrupt-controller; 2383 interrupt-controller;
2766 #interrupt-cells = <2 2384 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2385 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2386 wakeup-parent = <&pdc_intc>;
2769 2387
2770 cci0_default: cci0-de !! 2388 cci0_default: cci0-default {
2771 /* SDA, SCL * 2389 /* SDA, SCL */
2772 pins = "gpio1 2390 pins = "gpio17", "gpio18";
2773 function = "c 2391 function = "cci_i2c";
2774 2392
2775 bias-pull-up; 2393 bias-pull-up;
2776 drive-strengt 2394 drive-strength = <2>; /* 2 mA */
2777 }; 2395 };
2778 2396
2779 cci0_sleep: cci0-slee !! 2397 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2398 /* SDA, SCL */
2781 pins = "gpio1 2399 pins = "gpio17", "gpio18";
2782 function = "c 2400 function = "cci_i2c";
2783 2401
2784 drive-strengt 2402 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2403 bias-pull-down;
2786 }; 2404 };
2787 2405
2788 cci1_default: cci1-de !! 2406 cci1_default: cci1-default {
2789 /* SDA, SCL * 2407 /* SDA, SCL */
2790 pins = "gpio1 2408 pins = "gpio19", "gpio20";
2791 function = "c 2409 function = "cci_i2c";
2792 2410
2793 bias-pull-up; 2411 bias-pull-up;
2794 drive-strengt 2412 drive-strength = <2>; /* 2 mA */
2795 }; 2413 };
2796 2414
2797 cci1_sleep: cci1-slee !! 2415 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2416 /* SDA, SCL */
2799 pins = "gpio1 2417 pins = "gpio19", "gpio20";
2800 function = "c 2418 function = "cci_i2c";
2801 2419
2802 drive-strengt 2420 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2421 bias-pull-down;
2804 }; 2422 };
2805 2423
2806 qspi_clk: qspi-clk-st !! 2424 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2425 pinmux {
2808 function = "q !! 2426 pins = "gpio95";
2809 }; !! 2427 function = "qspi_clk";
2810 !! 2428 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; 2429 };
2820 2430
2821 qspi_data0: qspi-data !! 2431 qspi_cs0: qspi-cs0 {
2822 pins = "gpio9 !! 2432 pinmux {
2823 function = "q !! 2433 pins = "gpio90";
>> 2434 function = "qspi_cs";
>> 2435 };
2824 }; 2436 };
2825 2437
2826 qspi_data1: qspi-data !! 2438 qspi_cs1: qspi-cs1 {
2827 pins = "gpio9 !! 2439 pinmux {
2828 function = "q !! 2440 pins = "gpio89";
>> 2441 function = "qspi_cs";
>> 2442 };
2829 }; 2443 };
2830 2444
2831 qspi_data23: qspi-dat !! 2445 qspi_data01: qspi-data01 {
2832 pins = "gpio9 !! 2446 pinmux-data {
2833 function = "q !! 2447 pins = "gpio91", "gpio92";
>> 2448 function = "qspi_data";
>> 2449 };
2834 }; 2450 };
2835 2451
2836 qup_i2c0_default: qup !! 2452 qspi_data12: qspi-data12 {
2837 pins = "gpio0 !! 2453 pinmux-data {
2838 function = "q !! 2454 pins = "gpio93", "gpio94";
>> 2455 function = "qspi_data";
>> 2456 };
2839 }; 2457 };
2840 2458
2841 qup_i2c1_default: qup !! 2459 qup_i2c0_default: qup-i2c0-default {
2842 pins = "gpio1 !! 2460 pinmux {
2843 function = "q !! 2461 pins = "gpio0", "gpio1";
>> 2462 function = "qup0";
>> 2463 };
2844 }; 2464 };
2845 2465
2846 qup_i2c2_default: qup !! 2466 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio2 !! 2467 pinmux {
2848 function = "q !! 2468 pins = "gpio17", "gpio18";
>> 2469 function = "qup1";
>> 2470 };
2849 }; 2471 };
2850 2472
2851 qup_i2c3_default: qup !! 2473 qup_i2c2_default: qup-i2c2-default {
2852 pins = "gpio4 !! 2474 pinmux {
2853 function = "q !! 2475 pins = "gpio27", "gpio28";
>> 2476 function = "qup2";
>> 2477 };
2854 }; 2478 };
2855 2479
2856 qup_i2c4_default: qup !! 2480 qup_i2c3_default: qup-i2c3-default {
2857 pins = "gpio8 !! 2481 pinmux {
2858 function = "q !! 2482 pins = "gpio41", "gpio42";
>> 2483 function = "qup3";
>> 2484 };
2859 }; 2485 };
2860 2486
2861 qup_i2c5_default: qup !! 2487 qup_i2c4_default: qup-i2c4-default {
2862 pins = "gpio8 !! 2488 pinmux {
2863 function = "q !! 2489 pins = "gpio89", "gpio90";
>> 2490 function = "qup4";
>> 2491 };
2864 }; 2492 };
2865 2493
2866 qup_i2c6_default: qup !! 2494 qup_i2c5_default: qup-i2c5-default {
2867 pins = "gpio4 !! 2495 pinmux {
2868 function = "q !! 2496 pins = "gpio85", "gpio86";
>> 2497 function = "qup5";
>> 2498 };
2869 }; 2499 };
2870 2500
2871 qup_i2c7_default: qup !! 2501 qup_i2c6_default: qup-i2c6-default {
2872 pins = "gpio9 !! 2502 pinmux {
2873 function = "q !! 2503 pins = "gpio45", "gpio46";
>> 2504 function = "qup6";
>> 2505 };
2874 }; 2506 };
2875 2507
2876 qup_i2c8_default: qup !! 2508 qup_i2c7_default: qup-i2c7-default {
2877 pins = "gpio6 !! 2509 pinmux {
2878 function = "q !! 2510 pins = "gpio93", "gpio94";
>> 2511 function = "qup7";
>> 2512 };
2879 }; 2513 };
2880 2514
2881 qup_i2c9_default: qup !! 2515 qup_i2c8_default: qup-i2c8-default {
2882 pins = "gpio6 !! 2516 pinmux {
2883 function = "q !! 2517 pins = "gpio65", "gpio66";
>> 2518 function = "qup8";
>> 2519 };
2884 }; 2520 };
2885 2521
2886 qup_i2c10_default: qu !! 2522 qup_i2c9_default: qup-i2c9-default {
2887 pins = "gpio5 !! 2523 pinmux {
2888 function = "q !! 2524 pins = "gpio6", "gpio7";
>> 2525 function = "qup9";
>> 2526 };
2889 }; 2527 };
2890 2528
2891 qup_i2c11_default: qu !! 2529 qup_i2c10_default: qup-i2c10-default {
2892 pins = "gpio3 !! 2530 pinmux {
2893 function = "q !! 2531 pins = "gpio55", "gpio56";
>> 2532 function = "qup10";
>> 2533 };
2894 }; 2534 };
2895 2535
2896 qup_i2c12_default: qu !! 2536 qup_i2c11_default: qup-i2c11-default {
2897 pins = "gpio4 !! 2537 pinmux {
2898 function = "q !! 2538 pins = "gpio31", "gpio32";
>> 2539 function = "qup11";
>> 2540 };
2899 }; 2541 };
2900 2542
2901 qup_i2c13_default: qu !! 2543 qup_i2c12_default: qup-i2c12-default {
2902 pins = "gpio1 !! 2544 pinmux {
2903 function = "q !! 2545 pins = "gpio49", "gpio50";
>> 2546 function = "qup12";
>> 2547 };
2904 }; 2548 };
2905 2549
2906 qup_i2c14_default: qu !! 2550 qup_i2c13_default: qup-i2c13-default {
2907 pins = "gpio3 !! 2551 pinmux {
2908 function = "q !! 2552 pins = "gpio105", "gpio106";
>> 2553 function = "qup13";
>> 2554 };
2909 }; 2555 };
2910 2556
2911 qup_i2c15_default: qu !! 2557 qup_i2c14_default: qup-i2c14-default {
2912 pins = "gpio8 !! 2558 pinmux {
2913 function = "q !! 2559 pins = "gpio33", "gpio34";
>> 2560 function = "qup14";
>> 2561 };
2914 }; 2562 };
2915 2563
2916 qup_spi0_default: qup !! 2564 qup_i2c15_default: qup-i2c15-default {
2917 pins = "gpio0 !! 2565 pinmux {
2918 function = "q !! 2566 pins = "gpio81", "gpio82";
>> 2567 function = "qup15";
>> 2568 };
2919 }; 2569 };
2920 2570
2921 qup_spi1_default: qup !! 2571 qup_spi0_default: qup-spi0-default {
2922 pins = "gpio1 !! 2572 pinmux {
2923 function = "q !! 2573 pins = "gpio0", "gpio1",
>> 2574 "gpio2", "gpio3";
>> 2575 function = "qup0";
>> 2576 };
2924 }; 2577 };
2925 2578
2926 qup_spi2_default: qup !! 2579 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2580 pinmux {
2928 function = "q !! 2581 pins = "gpio17", "gpio18",
>> 2582 "gpio19", "gpio20";
>> 2583 function = "qup1";
>> 2584 };
2929 }; 2585 };
2930 2586
2931 qup_spi3_default: qup !! 2587 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2588 pinmux {
2933 function = "q !! 2589 pins = "gpio27", "gpio28",
>> 2590 "gpio29", "gpio30";
>> 2591 function = "qup2";
>> 2592 };
2934 }; 2593 };
2935 2594
2936 qup_spi4_default: qup !! 2595 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2596 pinmux {
2938 function = "q !! 2597 pins = "gpio41", "gpio42",
>> 2598 "gpio43", "gpio44";
>> 2599 function = "qup3";
>> 2600 };
2939 }; 2601 };
2940 2602
2941 qup_spi5_default: qup !! 2603 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2604 pinmux {
2943 function = "q !! 2605 pins = "gpio89", "gpio90",
>> 2606 "gpio91", "gpio92";
>> 2607 function = "qup4";
>> 2608 };
2944 }; 2609 };
2945 2610
2946 qup_spi6_default: qup !! 2611 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2612 pinmux {
2948 function = "q !! 2613 pins = "gpio85", "gpio86",
>> 2614 "gpio87", "gpio88";
>> 2615 function = "qup5";
>> 2616 };
2949 }; 2617 };
2950 2618
2951 qup_spi7_default: qup !! 2619 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2620 pinmux {
2953 function = "q !! 2621 pins = "gpio45", "gpio46",
>> 2622 "gpio47", "gpio48";
>> 2623 function = "qup6";
>> 2624 };
2954 }; 2625 };
2955 2626
2956 qup_spi8_default: qup !! 2627 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2628 pinmux {
2958 function = "q !! 2629 pins = "gpio93", "gpio94",
>> 2630 "gpio95", "gpio96";
>> 2631 function = "qup7";
>> 2632 };
2959 }; 2633 };
2960 2634
2961 qup_spi9_default: qup !! 2635 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2636 pinmux {
2963 function = "q !! 2637 pins = "gpio65", "gpio66",
>> 2638 "gpio67", "gpio68";
>> 2639 function = "qup8";
>> 2640 };
2964 }; 2641 };
2965 2642
2966 qup_spi10_default: qu !! 2643 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2644 pinmux {
2968 function = "q !! 2645 pins = "gpio6", "gpio7",
>> 2646 "gpio4", "gpio5";
>> 2647 function = "qup9";
>> 2648 };
2969 }; 2649 };
2970 2650
2971 qup_spi11_default: qu !! 2651 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2652 pinmux {
2973 function = "q !! 2653 pins = "gpio55", "gpio56",
>> 2654 "gpio53", "gpio54";
>> 2655 function = "qup10";
>> 2656 };
2974 }; 2657 };
2975 2658
2976 qup_spi12_default: qu !! 2659 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2660 pinmux {
2978 function = "q !! 2661 pins = "gpio31", "gpio32",
>> 2662 "gpio33", "gpio34";
>> 2663 function = "qup11";
>> 2664 };
2979 }; 2665 };
2980 2666
2981 qup_spi13_default: qu !! 2667 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2668 pinmux {
2983 function = "q !! 2669 pins = "gpio49", "gpio50",
>> 2670 "gpio51", "gpio52";
>> 2671 function = "qup12";
>> 2672 };
2984 }; 2673 };
2985 2674
2986 qup_spi14_default: qu !! 2675 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2676 pinmux {
2988 function = "q !! 2677 pins = "gpio105", "gpio106",
>> 2678 "gpio107", "gpio108";
>> 2679 function = "qup13";
>> 2680 };
2989 }; 2681 };
2990 2682
2991 qup_spi15_default: qu !! 2683 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2684 pinmux {
2993 function = "q !! 2685 pins = "gpio33", "gpio34",
>> 2686 "gpio31", "gpio32";
>> 2687 function = "qup14";
>> 2688 };
2994 }; 2689 };
2995 2690
2996 qup_uart0_default: qu !! 2691 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2692 pinmux {
2998 pins !! 2693 pins = "gpio81", "gpio82",
2999 funct !! 2694 "gpio83", "gpio84";
>> 2695 function = "qup15";
3000 }; 2696 };
>> 2697 };
3001 2698
3002 qup_uart0_rx: !! 2699 qup_uart0_default: qup-uart0-default {
3003 pins !! 2700 pinmux {
>> 2701 pins = "gpio2", "gpio3";
3004 funct 2702 function = "qup0";
3005 }; 2703 };
3006 }; 2704 };
3007 2705
3008 qup_uart1_default: qu !! 2706 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2707 pinmux {
3010 pins !! 2708 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2709 function = "qup1";
3017 }; 2710 };
3018 }; 2711 };
3019 2712
3020 qup_uart2_default: qu !! 2713 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2714 pinmux {
3022 pins !! 2715 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2716 function = "qup2";
3029 }; 2717 };
3030 }; 2718 };
3031 2719
3032 qup_uart3_default: qu !! 2720 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2721 pinmux {
3034 pins !! 2722 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2723 function = "qup3";
3041 }; 2724 };
3042 }; 2725 };
3043 2726
3044 qup_uart3_4pin: qup-u !! 2727 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2728 pinmux {
3046 pins !! 2729 pins = "gpio91", "gpio92";
3047 funct !! 2730 function = "qup4";
3048 }; 2731 };
>> 2732 };
3049 2733
3050 qup_uart3_4pi !! 2734 qup_uart5_default: qup-uart5-default {
3051 pins !! 2735 pinmux {
3052 funct !! 2736 pins = "gpio87", "gpio88";
>> 2737 function = "qup5";
3053 }; 2738 };
>> 2739 };
3054 2740
3055 qup_uart3_4pi !! 2741 qup_uart6_default: qup-uart6-default {
3056 pins !! 2742 pinmux {
3057 funct !! 2743 pins = "gpio47", "gpio48";
>> 2744 function = "qup6";
3058 }; 2745 };
3059 }; 2746 };
3060 2747
3061 qup_uart4_default: qu !! 2748 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 2749 pinmux {
3063 pins !! 2750 pins = "gpio95", "gpio96";
3064 funct !! 2751 function = "qup7";
3065 }; 2752 };
>> 2753 };
3066 2754
3067 qup_uart4_rx: !! 2755 qup_uart8_default: qup-uart8-default {
3068 pins !! 2756 pinmux {
3069 funct !! 2757 pins = "gpio67", "gpio68";
>> 2758 function = "qup8";
3070 }; 2759 };
3071 }; 2760 };
3072 2761
3073 qup_uart5_default: qu !! 2762 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 2763 pinmux {
3075 pins !! 2764 pins = "gpio4", "gpio5";
3076 funct !! 2765 function = "qup9";
3077 }; 2766 };
>> 2767 };
3078 2768
3079 qup_uart5_rx: !! 2769 qup_uart10_default: qup-uart10-default {
3080 pins !! 2770 pinmux {
3081 funct !! 2771 pins = "gpio53", "gpio54";
>> 2772 function = "qup10";
3082 }; 2773 };
3083 }; 2774 };
3084 2775
3085 qup_uart6_default: qu !! 2776 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 2777 pinmux {
3087 pins !! 2778 pins = "gpio33", "gpio34";
3088 funct !! 2779 function = "qup11";
3089 }; 2780 };
>> 2781 };
3090 2782
3091 qup_uart6_rx: !! 2783 qup_uart12_default: qup-uart12-default {
3092 pins !! 2784 pinmux {
3093 funct !! 2785 pins = "gpio51", "gpio52";
>> 2786 function = "qup12";
3094 }; 2787 };
3095 }; 2788 };
3096 2789
3097 qup_uart6_4pin: qup-u !! 2790 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 2791 pinmux {
3099 pins !! 2792 pins = "gpio107", "gpio108";
3100 funct !! 2793 function = "qup13";
3101 bias- <<
3102 }; 2794 };
>> 2795 };
3103 2796
3104 qup_uart6_4pi !! 2797 qup_uart14_default: qup-uart14-default {
3105 pins !! 2798 pinmux {
3106 funct !! 2799 pins = "gpio31", "gpio32";
3107 drive !! 2800 function = "qup14";
3108 bias- <<
3109 }; 2801 };
>> 2802 };
3110 2803
3111 qup_uart6_4pi !! 2804 qup_uart15_default: qup-uart15-default {
3112 pins !! 2805 pinmux {
3113 funct !! 2806 pins = "gpio83", "gpio84";
3114 bias- !! 2807 function = "qup15";
3115 }; 2808 };
3116 }; 2809 };
3117 2810
3118 qup_uart7_default: qu !! 2811 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 2812 mux {
3120 pins !! 2813 pins = "gpio58", "gpio59";
3121 funct !! 2814 function = "gpio";
3122 }; 2815 };
3123 2816
3124 qup_uart7_rx: !! 2817 config {
3125 pins !! 2818 pins = "gpio58", "gpio59";
3126 funct !! 2819 drive-strength = <2>;
>> 2820 bias-pull-down;
>> 2821 input-enable;
3127 }; 2822 };
3128 }; 2823 };
3129 2824
3130 qup_uart8_default: qu !! 2825 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 2826 mux {
3132 pins !! 2827 pins = "gpio58", "gpio59";
3133 funct !! 2828 function = "qua_mi2s";
3134 }; 2829 };
3135 2830
3136 qup_uart8_rx: !! 2831 config {
3137 pins !! 2832 pins = "gpio58", "gpio59";
3138 funct !! 2833 drive-strength = <8>;
>> 2834 bias-disable;
>> 2835 output-high;
3139 }; 2836 };
3140 }; 2837 };
3141 2838
3142 qup_uart9_default: qu !! 2839 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 2840 mux {
3144 pins !! 2841 pins = "gpio60";
3145 funct !! 2842 function = "gpio";
3146 }; 2843 };
3147 2844
3148 qup_uart9_rx: !! 2845 config {
3149 pins !! 2846 pins = "gpio60";
3150 funct !! 2847 drive-strength = <2>;
>> 2848 bias-pull-down;
>> 2849 input-enable;
3151 }; 2850 };
3152 }; 2851 };
3153 2852
3154 qup_uart10_default: q !! 2853 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 2854 mux {
3156 pins !! 2855 pins = "gpio60";
3157 funct !! 2856 function = "qua_mi2s";
3158 }; 2857 };
3159 2858
3160 qup_uart10_rx !! 2859 config {
3161 pins !! 2860 pins = "gpio60";
3162 funct !! 2861 drive-strength = <8>;
>> 2862 bias-disable;
3163 }; 2863 };
3164 }; 2864 };
3165 2865
3166 qup_uart11_default: q !! 2866 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 2867 mux {
3168 pins !! 2868 pins = "gpio61";
3169 funct !! 2869 function = "gpio";
3170 }; 2870 };
3171 2871
3172 qup_uart11_rx !! 2872 config {
3173 pins !! 2873 pins = "gpio61";
3174 funct !! 2874 drive-strength = <2>;
>> 2875 bias-pull-down;
>> 2876 input-enable;
3175 }; 2877 };
3176 }; 2878 };
3177 2879
3178 qup_uart12_default: q !! 2880 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 2881 mux {
3180 pins !! 2882 pins = "gpio61";
3181 funct !! 2883 function = "qua_mi2s";
3182 }; 2884 };
3183 2885
3184 qup_uart12_rx !! 2886 config {
3185 pins !! 2887 pins = "gpio61";
3186 funct !! 2888 drive-strength = <8>;
>> 2889 bias-disable;
3187 }; 2890 };
3188 }; 2891 };
3189 2892
3190 qup_uart13_default: q !! 2893 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 2894 mux {
3192 pins !! 2895 pins = "gpio62";
3193 funct !! 2896 function = "gpio";
3194 }; 2897 };
3195 2898
3196 qup_uart13_rx !! 2899 config {
3197 pins !! 2900 pins = "gpio62";
3198 funct !! 2901 drive-strength = <2>;
>> 2902 bias-pull-down;
>> 2903 input-enable;
3199 }; 2904 };
3200 }; 2905 };
3201 2906
3202 qup_uart14_default: q !! 2907 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 2908 mux {
3204 pins !! 2909 pins = "gpio62";
3205 funct !! 2910 function = "qua_mi2s";
3206 }; 2911 };
3207 2912
3208 qup_uart14_rx !! 2913 config {
3209 pins !! 2914 pins = "gpio62";
3210 funct !! 2915 drive-strength = <8>;
>> 2916 bias-disable;
3211 }; 2917 };
3212 }; 2918 };
3213 2919
3214 qup_uart15_default: q !! 2920 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 2921 mux {
3216 pins !! 2922 pins = "gpio63";
3217 funct !! 2923 function = "gpio";
3218 }; 2924 };
3219 2925
3220 qup_uart15_rx !! 2926 config {
3221 pins !! 2927 pins = "gpio63";
3222 funct !! 2928 drive-strength = <2>;
>> 2929 bias-pull-down;
>> 2930 input-enable;
3223 }; 2931 };
3224 }; 2932 };
3225 2933
3226 quat_mi2s_sleep: quat !! 2934 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 2935 mux {
3228 function = "g !! 2936 pins = "gpio63";
3229 drive-strengt !! 2937 function = "qua_mi2s";
3230 bias-pull-dow !! 2938 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 2939
3290 quat_mi2s_sd3_active: !! 2940 config {
3291 pins = "gpio6 !! 2941 pins = "gpio63";
3292 function = "q !! 2942 drive-strength = <8>;
3293 drive-strengt !! 2943 bias-disable;
3294 bias-disable; !! 2944 };
3295 }; 2945 };
3296 }; 2946 };
3297 2947
3298 mss_pil: remoteproc@4080000 { 2948 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 2949 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 2950 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 2951 reg-names = "qdsp6", "rmb";
3302 2952
3303 interrupts-extended = 2953 interrupts-extended =
3304 <&intc GIC_SP 2954 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 2955 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 2956 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 2957 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 2958 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 2959 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 2960 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 2961 "handover", "stop-ack",
3312 "sh 2962 "shutdown-ack";
3313 2963
3314 clocks = <&gcc GCC_MS 2964 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 2965 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 2966 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 2967 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 2968 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 2969 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 2970 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 2971 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 2972 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 2973 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 2974
3325 qcom,qmp = <&aoss_qmp <<
3326 <<
3327 qcom,smem-states = <& 2975 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 2976 qcom,smem-state-names = "stop";
3329 2977
3330 resets = <&aoss_reset 2978 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 2979 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 2980 reset-names = "mss_restart", "pdc_reset";
3333 2981
3334 qcom,halt-regs = <&tc !! 2982 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 2983
3336 power-domains = <&rpm !! 2984 power-domains = <&aoss_qmp 2>,
>> 2985 <&rpmhpd SDM845_CX>,
3337 <&rpm 2986 <&rpmhpd SDM845_MX>,
3338 <&rpm 2987 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = !! 2988 power-domain-names = "load_state", "cx", "mx", "mss";
3340 <<
3341 status = "disabled"; <<
3342 2989
3343 mba { 2990 mba {
3344 memory-region 2991 memory-region = <&mba_region>;
3345 }; 2992 };
3346 2993
3347 mpss { 2994 mpss {
3348 memory-region 2995 memory-region = <&mpss_region>;
3349 }; 2996 };
3350 2997
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 2998 glink-edge {
3356 interrupts = 2999 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3000 label = "modem";
3358 qcom,remote-p 3001 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3002 mboxes = <&apss_shared 12>;
3360 }; 3003 };
3361 }; 3004 };
3362 3005
3363 gpucc: clock-controller@50900 3006 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3007 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3008 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3009 #clock-cells = <1>;
3367 #reset-cells = <1>; 3010 #reset-cells = <1>;
3368 #power-domain-cells = 3011 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3012 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3013 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3014 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3015 clock-names = "bi_tcxo",
3373 "gcc_gp 3016 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3017 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3018 };
3376 3019
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 3020 stm@6002000 {
3431 compatible = "arm,cor 3021 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3022 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3023 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3024 reg-names = "stm-base", "stm-stimulus-base";
3435 3025
3436 clocks = <&aoss_qmp>; 3026 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3027 clock-names = "apb_pclk";
3438 3028
3439 out-ports { 3029 out-ports {
3440 port { 3030 port {
3441 stm_o 3031 stm_out: endpoint {
3442 3032 remote-endpoint =
3443 3033 <&funnel0_in7>;
3444 }; 3034 };
3445 }; 3035 };
3446 }; 3036 };
3447 }; 3037 };
3448 3038
3449 funnel@6041000 { 3039 funnel@6041000 {
3450 compatible = "arm,cor 3040 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3041 reg = <0 0x06041000 0 0x1000>;
3452 3042
3453 clocks = <&aoss_qmp>; 3043 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3044 clock-names = "apb_pclk";
3455 3045
3456 out-ports { 3046 out-ports {
3457 port { 3047 port {
3458 funne 3048 funnel0_out: endpoint {
3459 3049 remote-endpoint =
3460 3050 <&merge_funnel_in0>;
3461 }; 3051 };
3462 }; 3052 };
3463 }; 3053 };
3464 3054
3465 in-ports { 3055 in-ports {
3466 #address-cell 3056 #address-cells = <1>;
3467 #size-cells = 3057 #size-cells = <0>;
3468 3058
3469 port@7 { 3059 port@7 {
3470 reg = 3060 reg = <7>;
3471 funne 3061 funnel0_in7: endpoint {
3472 3062 remote-endpoint = <&stm_out>;
3473 }; 3063 };
3474 }; 3064 };
3475 }; 3065 };
3476 }; 3066 };
3477 3067
3478 funnel@6043000 { 3068 funnel@6043000 {
3479 compatible = "arm,cor 3069 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3070 reg = <0 0x06043000 0 0x1000>;
3481 3071
3482 clocks = <&aoss_qmp>; 3072 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3073 clock-names = "apb_pclk";
3484 3074
3485 out-ports { 3075 out-ports {
3486 port { 3076 port {
3487 funne 3077 funnel2_out: endpoint {
3488 3078 remote-endpoint =
3489 3079 <&merge_funnel_in2>;
3490 }; 3080 };
3491 }; 3081 };
3492 }; 3082 };
3493 3083
3494 in-ports { 3084 in-ports {
3495 #address-cell 3085 #address-cells = <1>;
3496 #size-cells = 3086 #size-cells = <0>;
3497 3087
3498 port@5 { 3088 port@5 {
3499 reg = 3089 reg = <5>;
3500 funne 3090 funnel2_in5: endpoint {
3501 3091 remote-endpoint =
3502 3092 <&apss_merge_funnel_out>;
3503 }; 3093 };
3504 }; 3094 };
3505 }; 3095 };
3506 }; 3096 };
3507 3097
3508 funnel@6045000 { 3098 funnel@6045000 {
3509 compatible = "arm,cor 3099 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3100 reg = <0 0x06045000 0 0x1000>;
3511 3101
3512 clocks = <&aoss_qmp>; 3102 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3103 clock-names = "apb_pclk";
3514 3104
3515 out-ports { 3105 out-ports {
3516 port { 3106 port {
3517 merge 3107 merge_funnel_out: endpoint {
3518 3108 remote-endpoint = <&etf_in>;
3519 }; 3109 };
3520 }; 3110 };
3521 }; 3111 };
3522 3112
3523 in-ports { 3113 in-ports {
3524 #address-cell 3114 #address-cells = <1>;
3525 #size-cells = 3115 #size-cells = <0>;
3526 3116
3527 port@0 { 3117 port@0 {
3528 reg = 3118 reg = <0>;
3529 merge 3119 merge_funnel_in0: endpoint {
3530 3120 remote-endpoint =
3531 3121 <&funnel0_out>;
3532 }; 3122 };
3533 }; 3123 };
3534 3124
3535 port@2 { 3125 port@2 {
3536 reg = 3126 reg = <2>;
3537 merge 3127 merge_funnel_in2: endpoint {
3538 3128 remote-endpoint =
3539 3129 <&funnel2_out>;
3540 }; 3130 };
3541 }; 3131 };
3542 }; 3132 };
3543 }; 3133 };
3544 3134
3545 replicator@6046000 { 3135 replicator@6046000 {
3546 compatible = "arm,cor 3136 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3137 reg = <0 0x06046000 0 0x1000>;
3548 3138
3549 clocks = <&aoss_qmp>; 3139 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3140 clock-names = "apb_pclk";
3551 3141
3552 out-ports { 3142 out-ports {
3553 port { 3143 port {
3554 repli 3144 replicator_out: endpoint {
3555 3145 remote-endpoint = <&etr_in>;
3556 }; 3146 };
3557 }; 3147 };
3558 }; 3148 };
3559 3149
3560 in-ports { 3150 in-ports {
3561 port { 3151 port {
3562 repli 3152 replicator_in: endpoint {
3563 3153 remote-endpoint = <&etf_out>;
3564 }; 3154 };
3565 }; 3155 };
3566 }; 3156 };
3567 }; 3157 };
3568 3158
3569 etf@6047000 { 3159 etf@6047000 {
3570 compatible = "arm,cor 3160 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3161 reg = <0 0x06047000 0 0x1000>;
3572 3162
3573 clocks = <&aoss_qmp>; 3163 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3164 clock-names = "apb_pclk";
3575 3165
3576 out-ports { 3166 out-ports {
3577 port { 3167 port {
3578 etf_o 3168 etf_out: endpoint {
3579 3169 remote-endpoint =
3580 3170 <&replicator_in>;
3581 }; 3171 };
3582 }; 3172 };
3583 }; 3173 };
3584 3174
3585 in-ports { 3175 in-ports {
>> 3176 #address-cells = <1>;
>> 3177 #size-cells = <0>;
3586 3178
3587 port { !! 3179 port@1 {
>> 3180 reg = <1>;
3588 etf_i 3181 etf_in: endpoint {
3589 3182 remote-endpoint =
3590 3183 <&merge_funnel_out>;
3591 }; 3184 };
3592 }; 3185 };
3593 }; 3186 };
3594 }; 3187 };
3595 3188
3596 etr@6048000 { 3189 etr@6048000 {
3597 compatible = "arm,cor 3190 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3191 reg = <0 0x06048000 0 0x1000>;
3599 3192
3600 clocks = <&aoss_qmp>; 3193 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3194 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3195 arm,scatter-gather;
3603 3196
3604 in-ports { 3197 in-ports {
3605 port { 3198 port {
3606 etr_i 3199 etr_in: endpoint {
3607 3200 remote-endpoint =
3608 3201 <&replicator_out>;
3609 }; 3202 };
3610 }; 3203 };
3611 }; 3204 };
3612 }; 3205 };
3613 3206
3614 etm@7040000 { 3207 etm@7040000 {
3615 compatible = "arm,cor 3208 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3209 reg = <0 0x07040000 0 0x1000>;
3617 3210
3618 cpu = <&CPU0>; 3211 cpu = <&CPU0>;
3619 3212
3620 clocks = <&aoss_qmp>; 3213 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3214 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3215 arm,coresight-loses-context-with-cpu;
3623 3216
3624 out-ports { 3217 out-ports {
3625 port { 3218 port {
3626 etm0_ 3219 etm0_out: endpoint {
3627 3220 remote-endpoint =
3628 3221 <&apss_funnel_in0>;
3629 }; 3222 };
3630 }; 3223 };
3631 }; 3224 };
3632 }; 3225 };
3633 3226
3634 etm@7140000 { 3227 etm@7140000 {
3635 compatible = "arm,cor 3228 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3229 reg = <0 0x07140000 0 0x1000>;
3637 3230
3638 cpu = <&CPU1>; 3231 cpu = <&CPU1>;
3639 3232
3640 clocks = <&aoss_qmp>; 3233 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3234 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3235 arm,coresight-loses-context-with-cpu;
3643 3236
3644 out-ports { 3237 out-ports {
3645 port { 3238 port {
3646 etm1_ 3239 etm1_out: endpoint {
3647 3240 remote-endpoint =
3648 3241 <&apss_funnel_in1>;
3649 }; 3242 };
3650 }; 3243 };
3651 }; 3244 };
3652 }; 3245 };
3653 3246
3654 etm@7240000 { 3247 etm@7240000 {
3655 compatible = "arm,cor 3248 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3249 reg = <0 0x07240000 0 0x1000>;
3657 3250
3658 cpu = <&CPU2>; 3251 cpu = <&CPU2>;
3659 3252
3660 clocks = <&aoss_qmp>; 3253 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3254 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3255 arm,coresight-loses-context-with-cpu;
3663 3256
3664 out-ports { 3257 out-ports {
3665 port { 3258 port {
3666 etm2_ 3259 etm2_out: endpoint {
3667 3260 remote-endpoint =
3668 3261 <&apss_funnel_in2>;
3669 }; 3262 };
3670 }; 3263 };
3671 }; 3264 };
3672 }; 3265 };
3673 3266
3674 etm@7340000 { 3267 etm@7340000 {
3675 compatible = "arm,cor 3268 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3269 reg = <0 0x07340000 0 0x1000>;
3677 3270
3678 cpu = <&CPU3>; 3271 cpu = <&CPU3>;
3679 3272
3680 clocks = <&aoss_qmp>; 3273 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3274 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3275 arm,coresight-loses-context-with-cpu;
3683 3276
3684 out-ports { 3277 out-ports {
3685 port { 3278 port {
3686 etm3_ 3279 etm3_out: endpoint {
3687 3280 remote-endpoint =
3688 3281 <&apss_funnel_in3>;
3689 }; 3282 };
3690 }; 3283 };
3691 }; 3284 };
3692 }; 3285 };
3693 3286
3694 etm@7440000 { 3287 etm@7440000 {
3695 compatible = "arm,cor 3288 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3289 reg = <0 0x07440000 0 0x1000>;
3697 3290
3698 cpu = <&CPU4>; 3291 cpu = <&CPU4>;
3699 3292
3700 clocks = <&aoss_qmp>; 3293 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3294 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3295 arm,coresight-loses-context-with-cpu;
3703 3296
3704 out-ports { 3297 out-ports {
3705 port { 3298 port {
3706 etm4_ 3299 etm4_out: endpoint {
3707 3300 remote-endpoint =
3708 3301 <&apss_funnel_in4>;
3709 }; 3302 };
3710 }; 3303 };
3711 }; 3304 };
3712 }; 3305 };
3713 3306
3714 etm@7540000 { 3307 etm@7540000 {
3715 compatible = "arm,cor 3308 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3309 reg = <0 0x07540000 0 0x1000>;
3717 3310
3718 cpu = <&CPU5>; 3311 cpu = <&CPU5>;
3719 3312
3720 clocks = <&aoss_qmp>; 3313 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3314 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3315 arm,coresight-loses-context-with-cpu;
3723 3316
3724 out-ports { 3317 out-ports {
3725 port { 3318 port {
3726 etm5_ 3319 etm5_out: endpoint {
3727 3320 remote-endpoint =
3728 3321 <&apss_funnel_in5>;
3729 }; 3322 };
3730 }; 3323 };
3731 }; 3324 };
3732 }; 3325 };
3733 3326
3734 etm@7640000 { 3327 etm@7640000 {
3735 compatible = "arm,cor 3328 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3329 reg = <0 0x07640000 0 0x1000>;
3737 3330
3738 cpu = <&CPU6>; 3331 cpu = <&CPU6>;
3739 3332
3740 clocks = <&aoss_qmp>; 3333 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3334 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3335 arm,coresight-loses-context-with-cpu;
3743 3336
3744 out-ports { 3337 out-ports {
3745 port { 3338 port {
3746 etm6_ 3339 etm6_out: endpoint {
3747 3340 remote-endpoint =
3748 3341 <&apss_funnel_in6>;
3749 }; 3342 };
3750 }; 3343 };
3751 }; 3344 };
3752 }; 3345 };
3753 3346
3754 etm@7740000 { 3347 etm@7740000 {
3755 compatible = "arm,cor 3348 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3349 reg = <0 0x07740000 0 0x1000>;
3757 3350
3758 cpu = <&CPU7>; 3351 cpu = <&CPU7>;
3759 3352
3760 clocks = <&aoss_qmp>; 3353 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3354 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3355 arm,coresight-loses-context-with-cpu;
3763 3356
3764 out-ports { 3357 out-ports {
3765 port { 3358 port {
3766 etm7_ 3359 etm7_out: endpoint {
3767 3360 remote-endpoint =
3768 3361 <&apss_funnel_in7>;
3769 }; 3362 };
3770 }; 3363 };
3771 }; 3364 };
3772 }; 3365 };
3773 3366
3774 funnel@7800000 { /* APSS Funn 3367 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3368 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3369 reg = <0 0x07800000 0 0x1000>;
3777 3370
3778 clocks = <&aoss_qmp>; 3371 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3372 clock-names = "apb_pclk";
3780 3373
3781 out-ports { 3374 out-ports {
3782 port { 3375 port {
3783 apss_ 3376 apss_funnel_out: endpoint {
3784 3377 remote-endpoint =
3785 3378 <&apss_merge_funnel_in>;
3786 }; 3379 };
3787 }; 3380 };
3788 }; 3381 };
3789 3382
3790 in-ports { 3383 in-ports {
3791 #address-cell 3384 #address-cells = <1>;
3792 #size-cells = 3385 #size-cells = <0>;
3793 3386
3794 port@0 { 3387 port@0 {
3795 reg = 3388 reg = <0>;
3796 apss_ 3389 apss_funnel_in0: endpoint {
3797 3390 remote-endpoint =
3798 3391 <&etm0_out>;
3799 }; 3392 };
3800 }; 3393 };
3801 3394
3802 port@1 { 3395 port@1 {
3803 reg = 3396 reg = <1>;
3804 apss_ 3397 apss_funnel_in1: endpoint {
3805 3398 remote-endpoint =
3806 3399 <&etm1_out>;
3807 }; 3400 };
3808 }; 3401 };
3809 3402
3810 port@2 { 3403 port@2 {
3811 reg = 3404 reg = <2>;
3812 apss_ 3405 apss_funnel_in2: endpoint {
3813 3406 remote-endpoint =
3814 3407 <&etm2_out>;
3815 }; 3408 };
3816 }; 3409 };
3817 3410
3818 port@3 { 3411 port@3 {
3819 reg = 3412 reg = <3>;
3820 apss_ 3413 apss_funnel_in3: endpoint {
3821 3414 remote-endpoint =
3822 3415 <&etm3_out>;
3823 }; 3416 };
3824 }; 3417 };
3825 3418
3826 port@4 { 3419 port@4 {
3827 reg = 3420 reg = <4>;
3828 apss_ 3421 apss_funnel_in4: endpoint {
3829 3422 remote-endpoint =
3830 3423 <&etm4_out>;
3831 }; 3424 };
3832 }; 3425 };
3833 3426
3834 port@5 { 3427 port@5 {
3835 reg = 3428 reg = <5>;
3836 apss_ 3429 apss_funnel_in5: endpoint {
3837 3430 remote-endpoint =
3838 3431 <&etm5_out>;
3839 }; 3432 };
3840 }; 3433 };
3841 3434
3842 port@6 { 3435 port@6 {
3843 reg = 3436 reg = <6>;
3844 apss_ 3437 apss_funnel_in6: endpoint {
3845 3438 remote-endpoint =
3846 3439 <&etm6_out>;
3847 }; 3440 };
3848 }; 3441 };
3849 3442
3850 port@7 { 3443 port@7 {
3851 reg = 3444 reg = <7>;
3852 apss_ 3445 apss_funnel_in7: endpoint {
3853 3446 remote-endpoint =
3854 3447 <&etm7_out>;
3855 }; 3448 };
3856 }; 3449 };
3857 }; 3450 };
3858 }; 3451 };
3859 3452
3860 funnel@7810000 { 3453 funnel@7810000 {
3861 compatible = "arm,cor 3454 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3455 reg = <0 0x07810000 0 0x1000>;
3863 3456
3864 clocks = <&aoss_qmp>; 3457 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3458 clock-names = "apb_pclk";
3866 3459
3867 out-ports { 3460 out-ports {
3868 port { 3461 port {
3869 apss_ 3462 apss_merge_funnel_out: endpoint {
3870 3463 remote-endpoint =
3871 3464 <&funnel2_in5>;
3872 }; 3465 };
3873 }; 3466 };
3874 }; 3467 };
3875 3468
3876 in-ports { 3469 in-ports {
3877 port { 3470 port {
3878 apss_ 3471 apss_merge_funnel_in: endpoint {
3879 3472 remote-endpoint =
3880 3473 <&apss_funnel_out>;
3881 }; 3474 };
3882 }; 3475 };
3883 }; 3476 };
3884 }; 3477 };
3885 3478
3886 sdhc_2: mmc@8804000 { !! 3479 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 3480 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3481 reg = <0 0x08804000 0 0x1000>;
3889 3482
3890 interrupts = <GIC_SPI 3483 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3484 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3485 interrupt-names = "hc_irq", "pwr_irq";
3893 3486
3894 clocks = <&gcc GCC_SD 3487 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD !! 3488 <&gcc GCC_SDCC2_APPS_CLK>;
3896 <&rpmhcc RPM !! 3489 clock-names = "iface", "core";
3897 clock-names = "iface" <<
3898 iommus = <&apps_smmu 3490 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3491 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3492 operating-points-v2 = <&sdhc2_opp_table>;
3901 3493
3902 status = "disabled"; 3494 status = "disabled";
3903 3495
3904 sdhc2_opp_table: opp- !! 3496 sdhc2_opp_table: sdhc2-opp-table {
3905 compatible = 3497 compatible = "operating-points-v2";
3906 3498
3907 opp-9600000 { 3499 opp-9600000 {
3908 opp-h 3500 opp-hz = /bits/ 64 <9600000>;
3909 requi 3501 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3502 };
3911 3503
3912 opp-19200000 3504 opp-19200000 {
3913 opp-h 3505 opp-hz = /bits/ 64 <19200000>;
3914 requi 3506 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3507 };
3916 3508
3917 opp-100000000 3509 opp-100000000 {
3918 opp-h 3510 opp-hz = /bits/ 64 <100000000>;
3919 requi 3511 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3512 };
3921 3513
3922 opp-201500000 3514 opp-201500000 {
3923 opp-h 3515 opp-hz = /bits/ 64 <201500000>;
3924 requi 3516 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3517 };
3926 }; 3518 };
3927 }; 3519 };
3928 3520
>> 3521 qspi_opp_table: qspi-opp-table {
>> 3522 compatible = "operating-points-v2";
>> 3523
>> 3524 opp-19200000 {
>> 3525 opp-hz = /bits/ 64 <19200000>;
>> 3526 required-opps = <&rpmhpd_opp_min_svs>;
>> 3527 };
>> 3528
>> 3529 opp-100000000 {
>> 3530 opp-hz = /bits/ 64 <100000000>;
>> 3531 required-opps = <&rpmhpd_opp_low_svs>;
>> 3532 };
>> 3533
>> 3534 opp-150000000 {
>> 3535 opp-hz = /bits/ 64 <150000000>;
>> 3536 required-opps = <&rpmhpd_opp_svs>;
>> 3537 };
>> 3538
>> 3539 opp-300000000 {
>> 3540 opp-hz = /bits/ 64 <300000000>;
>> 3541 required-opps = <&rpmhpd_opp_nom>;
>> 3542 };
>> 3543 };
>> 3544
3929 qspi: spi@88df000 { 3545 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3546 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3547 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3548 #address-cells = <1>;
3934 #size-cells = <0>; 3549 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3550 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3551 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3552 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3553 clock-names = "iface", "core";
3939 power-domains = <&rpm 3554 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3555 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3556 status = "disabled";
3942 }; 3557 };
3943 3558
3944 slim: slim-ngd@171c0000 { !! 3559 slim: slim@171c0000 {
3945 compatible = "qcom,sl 3560 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3561 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3562 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3563
3949 dmas = <&slimbam 3>, !! 3564 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 3565 qcom,ea-pc = <0x270>;
>> 3566 status = "okay";
>> 3567 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3568 <&slimbam 5>, <&slimbam 6>;
>> 3569 dma-names = "rx", "tx", "tx2", "rx2";
3951 3570
3952 iommus = <&apps_smmu 3571 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3572 #address-cells = <1>;
3954 #size-cells = <0>; 3573 #size-cells = <0>;
3955 status = "disabled"; <<
3956 }; <<
3957 3574
3958 lmh_cluster1: lmh@17d70800 { !! 3575 ngd@1 {
3959 compatible = "qcom,sd !! 3576 reg = <1>;
3960 reg = <0 0x17d70800 0 !! 3577 #address-cells = <2>;
3961 interrupts = <GIC_SPI !! 3578 #size-cells = <0>;
3962 cpus = <&CPU4>; !! 3579
3963 qcom,lmh-temp-arm-mil !! 3580 wcd9340_ifd: ifd@0{
3964 qcom,lmh-temp-low-mil !! 3581 compatible = "slim217,250";
3965 qcom,lmh-temp-high-mi !! 3582 reg = <0 0>;
3966 interrupt-controller; !! 3583 };
3967 #interrupt-cells = <1 !! 3584
>> 3585 wcd9340: codec@1{
>> 3586 compatible = "slim217,250";
>> 3587 reg = <1 0>;
>> 3588 slim-ifc-dev = <&wcd9340_ifd>;
>> 3589
>> 3590 #sound-dai-cells = <1>;
>> 3591
>> 3592 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3593 interrupt-controller;
>> 3594 #interrupt-cells = <1>;
>> 3595
>> 3596 #clock-cells = <0>;
>> 3597 clock-frequency = <9600000>;
>> 3598 clock-output-names = "mclk";
>> 3599 qcom,micbias1-millivolt = <1800>;
>> 3600 qcom,micbias2-millivolt = <1800>;
>> 3601 qcom,micbias3-millivolt = <1800>;
>> 3602 qcom,micbias4-millivolt = <1800>;
>> 3603
>> 3604 #address-cells = <1>;
>> 3605 #size-cells = <1>;
>> 3606
>> 3607 wcdgpio: gpio-controller@42 {
>> 3608 compatible = "qcom,wcd9340-gpio";
>> 3609 gpio-controller;
>> 3610 #gpio-cells = <2>;
>> 3611 reg = <0x42 0x2>;
>> 3612 };
>> 3613
>> 3614 swm: swm@c85 {
>> 3615 compatible = "qcom,soundwire-v1.3.0";
>> 3616 reg = <0xc85 0x40>;
>> 3617 interrupts-extended = <&wcd9340 20>;
>> 3618
>> 3619 qcom,dout-ports = <6>;
>> 3620 qcom,din-ports = <2>;
>> 3621 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3622 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3623 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3624
>> 3625 #sound-dai-cells = <1>;
>> 3626 clocks = <&wcd9340>;
>> 3627 clock-names = "iface";
>> 3628 #address-cells = <2>;
>> 3629 #size-cells = <0>;
>> 3630
>> 3631
>> 3632 };
>> 3633 };
>> 3634 };
3968 }; 3635 };
3969 3636
3970 lmh_cluster0: lmh@17d78800 { !! 3637 sound: sound {
3971 compatible = "qcom,sd <<
3972 reg = <0 0x17d78800 0 <<
3973 interrupts = <GIC_SPI <<
3974 cpus = <&CPU0>; <<
3975 qcom,lmh-temp-arm-mil <<
3976 qcom,lmh-temp-low-mil <<
3977 qcom,lmh-temp-high-mi <<
3978 interrupt-controller; <<
3979 #interrupt-cells = <1 <<
3980 }; 3638 };
3981 3639
3982 usb_1_hsphy: phy@88e2000 { 3640 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3641 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3642 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3643 status = "disabled";
3986 #phy-cells = <0>; 3644 #phy-cells = <0>;
3987 3645
3988 clocks = <&gcc GCC_US 3646 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3647 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3648 clock-names = "cfg_ahb", "ref";
3991 3649
3992 resets = <&gcc GCC_QU 3650 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3651
3994 nvmem-cells = <&qusb2 3652 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3653 };
3996 3654
3997 usb_2_hsphy: phy@88e3000 { 3655 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3656 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3657 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3658 status = "disabled";
4001 #phy-cells = <0>; 3659 #phy-cells = <0>;
4002 3660
4003 clocks = <&gcc GCC_US 3661 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3662 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3663 clock-names = "cfg_ahb", "ref";
4006 3664
4007 resets = <&gcc GCC_QU 3665 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3666
4009 nvmem-cells = <&qusb2 3667 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3668 };
4011 3669
4012 usb_1_qmpphy: phy@88e8000 { !! 3670 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3671 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3672 reg = <0 0x088e9000 0 0x18c>,
>> 3673 <0 0x088e8000 0 0x10>;
>> 3674 reg-names = "reg-base", "dp_com";
4015 status = "disabled"; 3675 status = "disabled";
>> 3676 #clock-cells = <1>;
>> 3677 #address-cells = <2>;
>> 3678 #size-cells = <2>;
>> 3679 ranges;
4016 3680
4017 clocks = <&gcc GCC_US 3681 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3682 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3683 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3684 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3685 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3686
4028 resets = <&gcc GCC_US !! 3687 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3688 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3689 reset-names = "phy", "common";
4031 3690
4032 #clock-cells = <1>; !! 3691 usb_1_ssphy: lanes@88e9200 {
4033 #phy-cells = <1>; !! 3692 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3693 <0 0x088e9400 0 0x200>,
4035 !! 3694 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3695 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3696 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3697 <0 0x088e9a00 0 0x100>;
4039 !! 3698 #phy-cells = <0>;
4040 port@0 { !! 3699 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4041 reg = !! 3700 clock-names = "pipe0";
4042 !! 3701 clock-output-names = "usb3_phy_pipe_clk_src";
4043 usb_1 <<
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3702 };
4063 }; 3703 };
4064 3704
4065 usb_2_qmpphy: phy@88eb000 { 3705 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3706 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 3707 reg = <0 0x088eb000 0 0x18c>;
>> 3708 status = "disabled";
>> 3709 #clock-cells = <1>;
>> 3710 #address-cells = <2>;
>> 3711 #size-cells = <2>;
>> 3712 ranges;
4068 3713
4069 clocks = <&gcc GCC_US 3714 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 3715 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 3716 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 3717 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 3718 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 3719
4083 resets = <&gcc GCC_US !! 3720 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 3721 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 3722 reset-names = "phy", "common";
4086 "phy_ph <<
4087 3723
4088 status = "disabled"; !! 3724 usb_2_ssphy: lane@88eb200 {
>> 3725 reg = <0 0x088eb200 0 0x128>,
>> 3726 <0 0x088eb400 0 0x1fc>,
>> 3727 <0 0x088eb800 0 0x218>,
>> 3728 <0 0x088eb600 0 0x70>;
>> 3729 #phy-cells = <0>;
>> 3730 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3731 clock-names = "pipe0";
>> 3732 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3733 };
4089 }; 3734 };
4090 3735
4091 usb_1: usb@a6f8800 { 3736 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 3737 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 3738 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 3739 status = "disabled";
4095 #address-cells = <2>; 3740 #address-cells = <2>;
4096 #size-cells = <2>; 3741 #size-cells = <2>;
4097 ranges; 3742 ranges;
4098 dma-ranges; 3743 dma-ranges;
4099 3744
4100 clocks = <&gcc GCC_CF 3745 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 3746 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 3747 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 3748 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 3749 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 3750 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 3751 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 3752
4111 assigned-clocks = <&g 3753 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 3754 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 3755 assigned-clock-rates = <19200000>, <150000000>;
4114 3756
4115 interrupts-extended = !! 3757 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 3758 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 3759 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 3760 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 3761 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 3762 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 3763
4126 power-domains = <&gcc 3764 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 3765
4128 resets = <&gcc GCC_US 3766 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 3767
4130 interconnects = <&agg 3768 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 3769 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 3770 interconnect-names = "usb-ddr", "apps-usb";
4133 3771
4134 usb_1_dwc3: usb@a6000 !! 3772 usb_1_dwc3: dwc3@a600000 {
4135 compatible = 3773 compatible = "snps,dwc3";
4136 reg = <0 0x0a 3774 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 3775 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 3776 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 3777 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 3778 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 3779 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 3780 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 3781 };
4165 }; 3782 };
4166 3783
4167 usb_2: usb@a8f8800 { 3784 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 3785 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 3786 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 3787 status = "disabled";
4171 #address-cells = <2>; 3788 #address-cells = <2>;
4172 #size-cells = <2>; 3789 #size-cells = <2>;
4173 ranges; 3790 ranges;
4174 dma-ranges; 3791 dma-ranges;
4175 3792
4176 clocks = <&gcc GCC_CF 3793 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 3794 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 3795 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 3796 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 3797 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 3798 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 3799 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 3800
4187 assigned-clocks = <&g 3801 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 3802 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 3803 assigned-clock-rates = <19200000>, <150000000>;
4190 3804
4191 interrupts-extended = !! 3805 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 3806 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 3807 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 3808 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 3809 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 3810 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 3811
4202 power-domains = <&gcc 3812 power-domains = <&gcc USB30_SEC_GDSC>;
4203 3813
4204 resets = <&gcc GCC_US 3814 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 3815
4206 interconnects = <&agg 3816 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 3817 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 3818 interconnect-names = "usb-ddr", "apps-usb";
4209 3819
4210 usb_2_dwc3: usb@a8000 !! 3820 usb_2_dwc3: dwc3@a800000 {
4211 compatible = 3821 compatible = "snps,dwc3";
4212 reg = <0 0x0a 3822 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 3823 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 3824 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 3825 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 3826 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 3827 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 3828 phy-names = "usb2-phy", "usb3-phy";
4220 }; 3829 };
4221 }; 3830 };
4222 3831
4223 venus: video-codec@aa00000 { 3832 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 3833 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 3834 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 3835 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 3836 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 3837 <&videocc VCODEC0_GDSC>,
4229 <&vid 3838 <&videocc VCODEC1_GDSC>,
4230 <&rpm 3839 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 3840 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 3841 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 3842 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 3843 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 3844 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 3845 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 3846 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 3847 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 3848 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 3849 clock-names = "core", "iface", "bus",
4241 "vcodec 3850 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 3851 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 3852 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 3853 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 3854 memory-region = <&venus_mem>;
4246 interconnects = <&mms 3855 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 3856 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 3857 interconnect-names = "video-mem", "cpu-cfg";
4249 3858
4250 status = "disabled"; <<
4251 <<
4252 video-core0 { 3859 video-core0 {
4253 compatible = 3860 compatible = "venus-decoder";
4254 }; 3861 };
4255 3862
4256 video-core1 { 3863 video-core1 {
4257 compatible = 3864 compatible = "venus-encoder";
4258 }; 3865 };
4259 3866
4260 venus_opp_table: opp- !! 3867 venus_opp_table: venus-opp-table {
4261 compatible = 3868 compatible = "operating-points-v2";
4262 3869
4263 opp-100000000 3870 opp-100000000 {
4264 opp-h 3871 opp-hz = /bits/ 64 <100000000>;
4265 requi 3872 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 3873 };
4267 3874
4268 opp-200000000 3875 opp-200000000 {
4269 opp-h 3876 opp-hz = /bits/ 64 <200000000>;
4270 requi 3877 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 3878 };
4272 3879
4273 opp-320000000 3880 opp-320000000 {
4274 opp-h 3881 opp-hz = /bits/ 64 <320000000>;
4275 requi 3882 required-opps = <&rpmhpd_opp_svs>;
4276 }; 3883 };
4277 3884
4278 opp-380000000 3885 opp-380000000 {
4279 opp-h 3886 opp-hz = /bits/ 64 <380000000>;
4280 requi 3887 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 3888 };
4282 3889
4283 opp-444000000 3890 opp-444000000 {
4284 opp-h 3891 opp-hz = /bits/ 64 <444000000>;
4285 requi 3892 required-opps = <&rpmhpd_opp_nom>;
4286 }; 3893 };
4287 3894
4288 opp-533000097 3895 opp-533000097 {
4289 opp-h 3896 opp-hz = /bits/ 64 <533000097>;
4290 requi 3897 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 3898 };
4292 }; 3899 };
4293 }; 3900 };
4294 3901
4295 videocc: clock-controller@ab0 3902 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 3903 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 3904 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 3905 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 3906 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 3907 #clock-cells = <1>;
4301 #power-domain-cells = 3908 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 3909 #reset-cells = <1>;
4303 }; 3910 };
4304 3911
4305 camss: camss@acb3000 { <<
4306 compatible = "qcom,sd <<
4307 <<
4308 reg = <0 0x0acb3000 0 <<
4309 <0 0x0acba000 <<
4310 <0 0x0acc8000 <<
4311 <0 0x0ac65000 <<
4312 <0 0x0ac66000 <<
4313 <0 0x0ac67000 <<
4314 <0 0x0ac68000 <<
4315 <0 0x0acaf000 <<
4316 <0 0x0acb6000 <<
4317 <0 0x0acc4000 <<
4318 reg-names = "csid0", <<
4319 "csid1", <<
4320 "csid2", <<
4321 "csiphy0", <<
4322 "csiphy1", <<
4323 "csiphy2", <<
4324 "csiphy3", <<
4325 "vfe0", <<
4326 "vfe1", <<
4327 "vfe_lite"; <<
4328 <<
4329 interrupts = <GIC_SPI <<
4330 <GIC_SPI 466 <<
4331 <GIC_SPI 468 <<
4332 <GIC_SPI 477 <<
4333 <GIC_SPI 478 <<
4334 <GIC_SPI 479 <<
4335 <GIC_SPI 448 <<
4336 <GIC_SPI 465 <<
4337 <GIC_SPI 467 <<
4338 <GIC_SPI 469 <<
4339 interrupt-names = "cs <<
4340 "csid1", <<
4341 "csid2", <<
4342 "csiphy0", <<
4343 "csiphy1", <<
4344 "csiphy2", <<
4345 "csiphy3", <<
4346 "vfe0", <<
4347 "vfe1", <<
4348 "vfe_lite"; <<
4349 <<
4350 power-domains = <&clo <<
4351 <&clock_camcc <<
4352 <&clock_camcc <<
4353 <<
4354 clocks = <&clock_camc <<
4355 <&clock_camcc <<
4356 <&clock_camcc <<
4357 <&clock_camcc <<
4358 <&clock_camcc <<
4359 <&clock_camcc <<
4360 <&clock_camcc <<
4361 <&clock_camcc <<
4362 <&clock_camcc <<
4363 <&clock_camcc <<
4364 <&clock_camcc <<
4365 <&clock_camcc <<
4366 <&clock_camcc <<
4367 <&clock_camcc <<
4368 <&clock_camcc <<
4369 <&clock_camcc <<
4370 <&clock_camcc <<
4371 <&clock_camcc <<
4372 <&clock_camcc <<
4373 <&clock_camcc <<
4374 <&clock_camcc <<
4375 <&gcc GCC_CAM <<
4376 <&gcc GCC_CAM <<
4377 <&clock_camcc <<
4378 <&clock_camcc <<
4379 <&clock_camcc <<
4380 <&clock_camcc <<
4381 <&clock_camcc <<
4382 <&clock_camcc <<
4383 <&clock_camcc <<
4384 <&clock_camcc <<
4385 <&clock_camcc <<
4386 <&clock_camcc <<
4387 <&clock_camcc <<
4388 <&clock_camcc <<
4389 <&clock_camcc <<
4390 clock-names = "camnoc <<
4391 "cpas_ahb", <<
4392 "cphy_rx_src" <<
4393 "csi0", <<
4394 "csi0_src", <<
4395 "csi1", <<
4396 "csi1_src", <<
4397 "csi2", <<
4398 "csi2_src", <<
4399 "csiphy0", <<
4400 "csiphy0_time <<
4401 "csiphy0_time <<
4402 "csiphy1", <<
4403 "csiphy1_time <<
4404 "csiphy1_time <<
4405 "csiphy2", <<
4406 "csiphy2_time <<
4407 "csiphy2_time <<
4408 "csiphy3", <<
4409 "csiphy3_time <<
4410 "csiphy3_time <<
4411 "gcc_camera_a <<
4412 "gcc_camera_a <<
4413 "slow_ahb_src <<
4414 "soc_ahb", <<
4415 "vfe0_axi", <<
4416 "vfe0", <<
4417 "vfe0_cphy_rx <<
4418 "vfe0_src", <<
4419 "vfe1_axi", <<
4420 "vfe1", <<
4421 "vfe1_cphy_rx <<
4422 "vfe1_src", <<
4423 "vfe_lite", <<
4424 "vfe_lite_cph <<
4425 "vfe_lite_src <<
4426 <<
4427 iommus = <&apps_smmu <<
4428 <&apps_smmu <<
4429 <&apps_smmu <<
4430 <&apps_smmu <<
4431 <<
4432 status = "disabled"; <<
4433 <<
4434 ports { <<
4435 #address-cell <<
4436 #size-cells = <<
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; <<
4454 }; <<
4455 <<
4456 cci: cci@ac4a000 { 3912 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 3913 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 3914 #address-cells = <1>;
4459 #size-cells = <0>; 3915 #size-cells = <0>;
4460 3916
4461 reg = <0 0x0ac4a000 0 3917 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 3918 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 3919 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 3920
4465 clocks = <&clock_camc 3921 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 3922 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 3923 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 3924 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 3925 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 3926 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 3927 clock-names = "camnoc_axi",
4472 "soc_ahb", 3928 "soc_ahb",
4473 "slow_ahb_src 3929 "slow_ahb_src",
4474 "cpas_ahb", 3930 "cpas_ahb",
4475 "cci", 3931 "cci",
4476 "cci_src"; 3932 "cci_src";
4477 3933
4478 assigned-clocks = <&c 3934 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 3935 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 3936 assigned-clock-rates = <80000000>, <37500000>;
4481 3937
4482 pinctrl-names = "defa 3938 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 3939 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 3940 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 3941
4486 status = "disabled"; 3942 status = "disabled";
4487 3943
4488 cci_i2c0: i2c-bus@0 { 3944 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 3945 reg = <0>;
4490 clock-frequen 3946 clock-frequency = <1000000>;
4491 #address-cell 3947 #address-cells = <1>;
4492 #size-cells = 3948 #size-cells = <0>;
4493 }; 3949 };
4494 3950
4495 cci_i2c1: i2c-bus@1 { 3951 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 3952 reg = <1>;
4497 clock-frequen 3953 clock-frequency = <1000000>;
4498 #address-cell 3954 #address-cells = <1>;
4499 #size-cells = 3955 #size-cells = <0>;
4500 }; 3956 };
4501 }; 3957 };
4502 3958
4503 clock_camcc: clock-controller 3959 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 3960 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 3961 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 3962 #clock-cells = <1>;
4507 #reset-cells = <1>; 3963 #reset-cells = <1>;
4508 #power-domain-cells = 3964 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; 3965 };
4512 3966
4513 mdss: display-subsystem@ae000 !! 3967 dsi_opp_table: dsi-opp-table {
>> 3968 compatible = "operating-points-v2";
>> 3969
>> 3970 opp-19200000 {
>> 3971 opp-hz = /bits/ 64 <19200000>;
>> 3972 required-opps = <&rpmhpd_opp_min_svs>;
>> 3973 };
>> 3974
>> 3975 opp-180000000 {
>> 3976 opp-hz = /bits/ 64 <180000000>;
>> 3977 required-opps = <&rpmhpd_opp_low_svs>;
>> 3978 };
>> 3979
>> 3980 opp-275000000 {
>> 3981 opp-hz = /bits/ 64 <275000000>;
>> 3982 required-opps = <&rpmhpd_opp_svs>;
>> 3983 };
>> 3984
>> 3985 opp-328580000 {
>> 3986 opp-hz = /bits/ 64 <328580000>;
>> 3987 required-opps = <&rpmhpd_opp_svs_l1>;
>> 3988 };
>> 3989
>> 3990 opp-358000000 {
>> 3991 opp-hz = /bits/ 64 <358000000>;
>> 3992 required-opps = <&rpmhpd_opp_nom>;
>> 3993 };
>> 3994 };
>> 3995
>> 3996 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 3997 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 3998 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 3999 reg-names = "mdss";
4517 4000
4518 power-domains = <&dis 4001 power-domains = <&dispcc MDSS_GDSC>;
4519 4002
4520 clocks = <&dispcc DIS !! 4003 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 4004 <&gcc GCC_DISP_AXI_CLK>,
4521 <&dispcc DIS 4005 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" !! 4006 clock-names = "iface", "bus", "core";
>> 4007
>> 4008 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 4009 assigned-clock-rates = <300000000>;
4523 4010
4524 interrupts = <GIC_SPI 4011 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4012 interrupt-controller;
4526 #interrupt-cells = <1 4013 #interrupt-cells = <1>;
4527 4014
4528 interconnects = <&mms 4015 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4016 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4017 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4018
4532 iommus = <&apps_smmu 4019 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4020 <&apps_smmu 0xc80 0x8>;
4534 4021
4535 status = "disabled"; 4022 status = "disabled";
4536 4023
4537 #address-cells = <2>; 4024 #address-cells = <2>;
4538 #size-cells = <2>; 4025 #size-cells = <2>;
4539 ranges; 4026 ranges;
4540 4027
4541 mdss_mdp: display-con !! 4028 mdss_mdp: mdp@ae01000 {
4542 compatible = 4029 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4030 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4031 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4032 reg-names = "mdp", "vbif";
4546 4033
4547 clocks = <&gc !! 4034 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4548 <&di <<
4549 <&di 4035 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4036 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4037 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = !! 4038 clock-names = "iface", "bus", "core", "vsync";
4553 4039
4554 assigned-cloc !! 4040 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 4041 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 4042 assigned-clock-rates = <300000000>,
>> 4043 <19200000>;
4556 operating-poi 4044 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4045 power-domains = <&rpmhpd SDM845_CX>;
4558 4046
4559 interrupt-par 4047 interrupt-parent = <&mdss>;
4560 interrupts = !! 4048 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> 4049
>> 4050 status = "disabled";
4561 4051
4562 ports { 4052 ports {
4563 #addr 4053 #address-cells = <1>;
4564 #size 4054 #size-cells = <0>;
4565 4055
4566 port@ 4056 port@0 {
4567 4057 reg = <0>;
4568 !! 4058 dpu_intf1_out: endpoint {
4569 !! 4059 remote-endpoint = <&dsi0_in>;
4570 4060 };
4571 }; 4061 };
4572 4062
4573 port@ 4063 port@1 {
4574 4064 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 4065 dpu_intf2_out: endpoint {
4583 !! 4066 remote-endpoint = <&dsi1_in>;
4584 4067 };
4585 }; 4068 };
4586 }; 4069 };
4587 4070
4588 mdp_opp_table !! 4071 mdp_opp_table: mdp-opp-table {
4589 compa 4072 compatible = "operating-points-v2";
4590 4073
4591 opp-1 4074 opp-19200000 {
4592 4075 opp-hz = /bits/ 64 <19200000>;
4593 4076 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4077 };
4595 4078
4596 opp-1 4079 opp-171428571 {
4597 4080 opp-hz = /bits/ 64 <171428571>;
4598 4081 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4082 };
4600 4083
4601 opp-3 4084 opp-344000000 {
4602 4085 opp-hz = /bits/ 64 <344000000>;
4603 4086 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4087 };
4605 4088
4606 opp-4 4089 opp-430000000 {
4607 4090 opp-hz = /bits/ 64 <430000000>;
4608 4091 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4092 };
4610 }; 4093 };
4611 }; 4094 };
4612 4095
4613 mdss_dp: displayport- !! 4096 dsi0: dsi@ae94000 {
4614 status = "dis !! 4097 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 4098 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4099 reg-names = "dsi_ctrl";
4691 4100
4692 interrupt-par 4101 interrupt-parent = <&mdss>;
4693 interrupts = !! 4102 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 4103
4695 clocks = <&di 4104 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4105 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4106 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4107 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4108 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4109 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4110 clock-names = "byte",
4702 4111 "byte_intf",
4703 4112 "pixel",
4704 4113 "core",
4705 4114 "iface",
4706 4115 "bus";
4707 assigned-cloc <<
4708 assigned-cloc <<
4709 <<
4710 operating-poi 4116 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4117 power-domains = <&rpmhpd SDM845_CX>;
4712 4118
4713 phys = <&mdss !! 4119 phys = <&dsi0_phy>;
>> 4120 phy-names = "dsi";
4714 4121
4715 status = "dis 4122 status = "disabled";
4716 4123
4717 #address-cell <<
4718 #size-cells = <<
4719 <<
4720 ports { 4124 ports {
4721 #addr 4125 #address-cells = <1>;
4722 #size 4126 #size-cells = <0>;
4723 4127
4724 port@ 4128 port@0 {
4725 4129 reg = <0>;
4726 !! 4130 dsi0_in: endpoint {
4727 4131 remote-endpoint = <&dpu_intf1_out>;
4728 4132 };
4729 }; 4133 };
4730 4134
4731 port@ 4135 port@1 {
4732 4136 reg = <1>;
4733 !! 4137 dsi0_out: endpoint {
4734 4138 };
4735 }; 4139 };
4736 }; 4140 };
4737 }; 4141 };
4738 4142
4739 mdss_dsi0_phy: phy@ae !! 4143 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 4144 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4145 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4146 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4147 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4148 reg-names = "dsi_phy",
4745 " 4149 "dsi_phy_lane",
4746 " 4150 "dsi_pll";
4747 4151
4748 #clock-cells 4152 #clock-cells = <1>;
4749 #phy-cells = 4153 #phy-cells = <0>;
4750 4154
4751 clocks = <&di 4155 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4156 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4157 clock-names = "iface", "ref";
4754 4158
4755 status = "dis 4159 status = "disabled";
4756 }; 4160 };
4757 4161
4758 mdss_dsi1: dsi@ae9600 !! 4162 dsi1: dsi@ae96000 {
4759 compatible = !! 4163 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 4164 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4165 reg-names = "dsi_ctrl";
4763 4166
4764 interrupt-par 4167 interrupt-parent = <&mdss>;
4765 interrupts = !! 4168 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 4169
4767 clocks = <&di 4170 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4171 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4172 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4173 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4174 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4175 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4176 clock-names = "byte",
4774 4177 "byte_intf",
4775 4178 "pixel",
4776 4179 "core",
4777 4180 "iface",
4778 4181 "bus";
4779 assigned-cloc <<
4780 assigned-cloc <<
4781 <<
4782 operating-poi 4182 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4183 power-domains = <&rpmhpd SDM845_CX>;
4784 4184
4785 phys = <&mdss !! 4185 phys = <&dsi1_phy>;
>> 4186 phy-names = "dsi";
4786 4187
4787 status = "dis 4188 status = "disabled";
4788 4189
4789 #address-cell <<
4790 #size-cells = <<
4791 <<
4792 ports { 4190 ports {
4793 #addr 4191 #address-cells = <1>;
4794 #size 4192 #size-cells = <0>;
4795 4193
4796 port@ 4194 port@0 {
4797 4195 reg = <0>;
4798 !! 4196 dsi1_in: endpoint {
4799 4197 remote-endpoint = <&dpu_intf2_out>;
4800 4198 };
4801 }; 4199 };
4802 4200
4803 port@ 4201 port@1 {
4804 4202 reg = <1>;
4805 !! 4203 dsi1_out: endpoint {
4806 4204 };
4807 }; 4205 };
4808 }; 4206 };
4809 }; 4207 };
4810 4208
4811 mdss_dsi1_phy: phy@ae !! 4209 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 4210 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4211 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4212 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4213 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4214 reg-names = "dsi_phy",
4817 " 4215 "dsi_phy_lane",
4818 " 4216 "dsi_pll";
4819 4217
4820 #clock-cells 4218 #clock-cells = <1>;
4821 #phy-cells = 4219 #phy-cells = <0>;
4822 4220
4823 clocks = <&di 4221 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4222 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4223 clock-names = "iface", "ref";
4826 4224
4827 status = "dis 4225 status = "disabled";
4828 }; 4226 };
4829 }; 4227 };
4830 4228
4831 gpu: gpu@5000000 { 4229 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4230 compatible = "qcom,adreno-630.2", "qcom,adreno";
>> 4231 #stream-id-cells = <16>;
4833 4232
4834 reg = <0 0x05000000 0 !! 4233 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4234 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4235
4837 /* 4236 /*
4838 * Look ma, no clocks 4237 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4238 * controlled entirely by the GMU
4840 */ 4239 */
4841 4240
4842 interrupts = <GIC_SPI 4241 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4242
4844 iommus = <&adreno_smm 4243 iommus = <&adreno_smmu 0>;
4845 4244
4846 operating-points-v2 = 4245 operating-points-v2 = <&gpu_opp_table>;
4847 4246
4848 qcom,gmu = <&gmu>; 4247 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4248
4851 interconnects = <&mem 4249 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4250 interconnect-names = "gfx-mem";
4853 4251
4854 status = "disabled"; <<
4855 <<
4856 gpu_opp_table: opp-ta 4252 gpu_opp_table: opp-table {
4857 compatible = 4253 compatible = "operating-points-v2";
4858 4254
4859 opp-710000000 4255 opp-710000000 {
4860 opp-h 4256 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4257 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4258 opp-peak-kBps = <7216000>;
4863 }; 4259 };
4864 4260
4865 opp-675000000 4261 opp-675000000 {
4866 opp-h 4262 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4263 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4264 opp-peak-kBps = <7216000>;
4869 }; 4265 };
4870 4266
4871 opp-596000000 4267 opp-596000000 {
4872 opp-h 4268 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4269 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4270 opp-peak-kBps = <6220000>;
4875 }; 4271 };
4876 4272
4877 opp-520000000 4273 opp-520000000 {
4878 opp-h 4274 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4275 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4276 opp-peak-kBps = <6220000>;
4881 }; 4277 };
4882 4278
4883 opp-414000000 4279 opp-414000000 {
4884 opp-h 4280 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4281 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4282 opp-peak-kBps = <4068000>;
4887 }; 4283 };
4888 4284
4889 opp-342000000 4285 opp-342000000 {
4890 opp-h 4286 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4287 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4288 opp-peak-kBps = <2724000>;
4893 }; 4289 };
4894 4290
4895 opp-257000000 4291 opp-257000000 {
4896 opp-h 4292 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4293 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4294 opp-peak-kBps = <1648000>;
4899 }; 4295 };
4900 }; 4296 };
4901 }; 4297 };
4902 4298
4903 adreno_smmu: iommu@5040000 { 4299 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4300 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4301 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4302 #iommu-cells = <1>;
4907 #global-interrupts = 4303 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4304 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4305 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4306 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4307 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4308 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4309 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4310 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4311 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4312 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4313 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4314 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4315 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4316 clock-names = "bus", "iface";
4921 4317
4922 power-domains = <&gpu 4318 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4319 };
4924 4320
4925 gmu: gmu@506a000 { 4321 gmu: gmu@506a000 {
4926 compatible = "qcom,ad !! 4322 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4323
4928 reg = <0 0x0506a000 0 !! 4324 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4325 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4326 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4327 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4328
4933 interrupts = <GIC_SPI 4329 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4330 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4331 interrupt-names = "hfi", "gmu";
4936 4332
4937 clocks = <&gpucc GPU_ 4333 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4334 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4335 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4336 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4337 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4338
4943 power-domains = <&gpu 4339 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4340 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4341 power-domain-names = "cx", "gx";
4946 4342
4947 iommus = <&adreno_smm 4343 iommus = <&adreno_smmu 5>;
4948 4344
4949 operating-points-v2 = 4345 operating-points-v2 = <&gmu_opp_table>;
4950 4346
4951 status = "disabled"; <<
4952 <<
4953 gmu_opp_table: opp-ta 4347 gmu_opp_table: opp-table {
4954 compatible = 4348 compatible = "operating-points-v2";
4955 4349
4956 opp-400000000 4350 opp-400000000 {
4957 opp-h 4351 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4352 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4353 };
4960 4354
4961 opp-200000000 4355 opp-200000000 {
4962 opp-h 4356 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4357 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4358 };
4965 }; 4359 };
4966 }; 4360 };
4967 4361
4968 dispcc: clock-controller@af00 4362 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4363 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4364 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4365 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4366 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4367 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4368 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4369 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4370 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4371 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4372 <0>,
4979 <&usb_1_qmpp !! 4373 <0>;
4980 clock-names = "bi_tcx 4374 clock-names = "bi_tcxo",
4981 "gcc_di 4375 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4376 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4377 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4378 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4379 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4380 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4381 "dp_link_clk_divsel_ten",
4988 "dp_vco 4382 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4383 #clock-cells = <1>;
4990 #reset-cells = <1>; 4384 #reset-cells = <1>;
4991 #power-domain-cells = 4385 #power-domain-cells = <1>;
4992 }; 4386 };
4993 4387
4994 pdc_intc: interrupt-controlle 4388 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4389 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4390 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4391 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4392 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4393 interrupt-parent = <&intc>;
5000 interrupt-controller; 4394 interrupt-controller;
5001 }; 4395 };
5002 4396
5003 pdc_reset: reset-controller@b 4397 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4398 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4399 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4400 #reset-cells = <1>;
5007 }; 4401 };
5008 4402
5009 tsens0: thermal-sensor@c26300 4403 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4404 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4405 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4406 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4407 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4408 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4409 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4410 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4411 #thermal-sensor-cells = <1>;
5018 }; 4412 };
5019 4413
5020 tsens1: thermal-sensor@c26500 4414 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4415 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4416 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4417 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4418 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4419 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4420 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4421 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4422 #thermal-sensor-cells = <1>;
5029 }; 4423 };
5030 4424
5031 aoss_reset: reset-controller@ 4425 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4426 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4427 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4428 #reset-cells = <1>;
5035 }; 4429 };
5036 4430
5037 aoss_qmp: power-management@c3 !! 4431 aoss_qmp: qmp@c300000 {
5038 compatible = "qcom,sd !! 4432 compatible = "qcom,sdm845-aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 4433 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 4434 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4435 mboxes = <&apss_shared 0>;
5042 4436
5043 #clock-cells = <0>; 4437 #clock-cells = <0>;
>> 4438 #power-domain-cells = <1>;
5044 4439
5045 cx_cdev: cx { 4440 cx_cdev: cx {
5046 #cooling-cell 4441 #cooling-cells = <2>;
5047 }; 4442 };
5048 4443
5049 ebi_cdev: ebi { 4444 ebi_cdev: ebi {
5050 #cooling-cell 4445 #cooling-cells = <2>;
5051 }; 4446 };
5052 }; 4447 };
5053 4448
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 4449 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4450 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4451 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4452 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4453 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4454 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4455 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 4456 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 4457 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 4458 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 4459 qcom,ee = <0>;
5070 qcom,channel = <0>; 4460 qcom,channel = <0>;
5071 #address-cells = <2>; 4461 #address-cells = <2>;
5072 #size-cells = <0>; 4462 #size-cells = <0>;
5073 interrupt-controller; 4463 interrupt-controller;
5074 #interrupt-cells = <4 4464 #interrupt-cells = <4>;
>> 4465 cell-index = <0>;
5075 }; 4466 };
5076 4467
5077 sram@146bf000 { !! 4468 imem@146bf000 {
5078 compatible = "qcom,sd !! 4469 compatible = "simple-mfd";
5079 reg = <0 0x146bf000 0 4470 reg = <0 0x146bf000 0 0x1000>;
5080 4471
5081 #address-cells = <1>; 4472 #address-cells = <1>;
5082 #size-cells = <1>; 4473 #size-cells = <1>;
5083 4474
5084 ranges = <0 0 0x146bf 4475 ranges = <0 0 0x146bf000 0x1000>;
5085 4476
5086 pil-reloc@94c { 4477 pil-reloc@94c {
5087 compatible = 4478 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 4479 reg = <0x94c 0xc8>;
5089 }; 4480 };
5090 }; 4481 };
5091 4482
5092 apps_smmu: iommu@15000000 { 4483 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 4484 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 4485 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 4486 #iommu-cells = <2>;
5096 #global-interrupts = 4487 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 4488 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 4489 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 4490 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 4491 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 4492 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 4493 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 4494 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 4495 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 4496 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 4497 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4498 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4499 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 4500 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 4501 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 4502 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 4503 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 4504 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 4505 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 4506 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 4507 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 4508 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 4509 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 4510 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 4511 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 4512 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 4513 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 4514 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 4515 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 4516 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 4517 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 4518 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 4519 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 4520 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 4521 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 4522 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4523 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 4524 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 4525 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 4526 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 4527 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 4528 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4529 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 4530 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 4531 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 4532 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 4533 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 4534 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4535 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 4536 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 4537 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 4538 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 4539 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 4540 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 4541 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 4542 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 4543 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 4544 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 4545 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 4546 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 4547 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 4548 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 4549 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 4550 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 4551 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 4552 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 4553 };
5163 4554
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 4555 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 4556 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 4557 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 4558 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 4559 #clock-cells = <1>;
5241 status = "disabled"; 4560 status = "disabled";
5242 }; 4561 };
5243 4562
5244 gladiator_noc: interconnect@1 4563 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 4564 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 4565 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 4566 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 4567 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 4568 };
5250 4569
5251 watchdog@17980000 { 4570 watchdog@17980000 {
5252 compatible = "qcom,ap 4571 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 4572 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 4573 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI !! 4574 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256 }; 4575 };
5257 4576
5258 apss_shared: mailbox@17990000 4577 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 4578 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 4579 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 4580 #mbox-cells = <1>;
5262 }; 4581 };
5263 4582
5264 apps_rsc: rsc@179c0000 { 4583 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 4584 label = "apps_rsc";
5266 compatible = "qcom,rp 4585 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 4586 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 4587 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 4588 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 4589 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 4590 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 4591 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 4592 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 4593 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 4594 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 4595 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 4596 <SLEEP_TCS 3>,
5278 <WA 4597 <WAKE_TCS 3>,
5279 <CO 4598 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 4599
5282 apps_bcm_voter: bcm-v 4600 apps_bcm_voter: bcm-voter {
5283 compatible = 4601 compatible = "qcom,bcm-voter";
5284 }; 4602 };
5285 4603
5286 rpmhcc: clock-control 4604 rpmhcc: clock-controller {
5287 compatible = 4605 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 4606 #clock-cells = <1>;
5289 clock-names = 4607 clock-names = "xo";
5290 clocks = <&xo 4608 clocks = <&xo_board>;
5291 }; 4609 };
5292 4610
5293 rpmhpd: power-control 4611 rpmhpd: power-controller {
5294 compatible = 4612 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 4613 #power-domain-cells = <1>;
5296 operating-poi 4614 operating-points-v2 = <&rpmhpd_opp_table>;
5297 4615
5298 rpmhpd_opp_ta 4616 rpmhpd_opp_table: opp-table {
5299 compa 4617 compatible = "operating-points-v2";
5300 4618
5301 rpmhp 4619 rpmhpd_opp_ret: opp1 {
5302 4620 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 4621 };
5304 4622
5305 rpmhp 4623 rpmhpd_opp_min_svs: opp2 {
5306 4624 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 4625 };
5308 4626
5309 rpmhp 4627 rpmhpd_opp_low_svs: opp3 {
5310 4628 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 4629 };
5312 4630
5313 rpmhp 4631 rpmhpd_opp_svs: opp4 {
5314 4632 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 4633 };
5316 4634
5317 rpmhp 4635 rpmhpd_opp_svs_l1: opp5 {
5318 4636 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 4637 };
5320 4638
5321 rpmhp 4639 rpmhpd_opp_nom: opp6 {
5322 4640 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 4641 };
5324 4642
5325 rpmhp 4643 rpmhpd_opp_nom_l1: opp7 {
5326 4644 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 4645 };
5328 4646
5329 rpmhp 4647 rpmhpd_opp_nom_l2: opp8 {
5330 4648 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 4649 };
5332 4650
5333 rpmhp 4651 rpmhpd_opp_turbo: opp9 {
5334 4652 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 4653 };
5336 4654
5337 rpmhp 4655 rpmhpd_opp_turbo_l1: opp10 {
5338 4656 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 4657 };
5340 }; 4658 };
5341 }; 4659 };
5342 }; 4660 };
5343 4661
5344 intc: interrupt-controller@17 4662 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 4663 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 4664 #address-cells = <2>;
5347 #size-cells = <2>; 4665 #size-cells = <2>;
5348 ranges; 4666 ranges;
5349 #interrupt-cells = <3 4667 #interrupt-cells = <3>;
5350 interrupt-controller; 4668 interrupt-controller;
5351 reg = <0 0x17a00000 0 4669 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 4670 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 4671 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 4672
5355 msi-controller@17a400 4673 msi-controller@17a40000 {
5356 compatible = 4674 compatible = "arm,gic-v3-its";
5357 msi-controlle 4675 msi-controller;
5358 #msi-cells = 4676 #msi-cells = <1>;
5359 reg = <0 0x17 4677 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 4678 status = "disabled";
5361 }; 4679 };
5362 }; 4680 };
5363 4681
5364 slimbam: dma-controller@17184 4682 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba !! 4683 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 4684 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 4685 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; !! 4686 num-channels = <31>;
5369 interrupts = <GIC_SPI 4687 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 4688 #dma-cells = <1>;
5371 qcom,ee = <1>; 4689 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 4690 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 4691 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 4692 };
5375 4693
5376 timer@17c90000 { 4694 timer@17c90000 {
5377 #address-cells = <1>; !! 4695 #address-cells = <2>;
5378 #size-cells = <1>; !! 4696 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 4697 ranges;
5380 compatible = "arm,arm 4698 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 4699 reg = <0 0x17c90000 0 0x1000>;
5382 4700
5383 frame@17ca0000 { 4701 frame@17ca0000 {
5384 frame-number 4702 frame-number = <0>;
5385 interrupts = 4703 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 4704 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 4705 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 4706 <0 0x17cb0000 0 0x1000>;
5389 }; 4707 };
5390 4708
5391 frame@17cc0000 { 4709 frame@17cc0000 {
5392 frame-number 4710 frame-number = <1>;
5393 interrupts = 4711 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 4712 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 4713 status = "disabled";
5396 }; 4714 };
5397 4715
5398 frame@17cd0000 { 4716 frame@17cd0000 {
5399 frame-number 4717 frame-number = <2>;
5400 interrupts = 4718 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 4719 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 4720 status = "disabled";
5403 }; 4721 };
5404 4722
5405 frame@17ce0000 { 4723 frame@17ce0000 {
5406 frame-number 4724 frame-number = <3>;
5407 interrupts = 4725 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 4726 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 4727 status = "disabled";
5410 }; 4728 };
5411 4729
5412 frame@17cf0000 { 4730 frame@17cf0000 {
5413 frame-number 4731 frame-number = <4>;
5414 interrupts = 4732 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 4733 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 4734 status = "disabled";
5417 }; 4735 };
5418 4736
5419 frame@17d00000 { 4737 frame@17d00000 {
5420 frame-number 4738 frame-number = <5>;
5421 interrupts = 4739 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 4740 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 4741 status = "disabled";
5424 }; 4742 };
5425 4743
5426 frame@17d10000 { 4744 frame@17d10000 {
5427 frame-number 4745 frame-number = <6>;
5428 interrupts = 4746 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 4747 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 4748 status = "disabled";
5431 }; 4749 };
5432 }; 4750 };
5433 4751
5434 osm_l3: interconnect@17d41000 4752 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 4753 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 4754 reg = <0 0x17d41000 0 0x1400>;
5437 4755
5438 clocks = <&rpmhcc RPM 4756 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 4757 clock-names = "xo", "alternate";
5440 4758
5441 #interconnect-cells = 4759 #interconnect-cells = <1>;
5442 }; 4760 };
5443 4761
5444 cpufreq_hw: cpufreq@17d43000 4762 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 4763 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 4764 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 4765 reg-names = "freq-domain0", "freq-domain1";
5448 4766
5449 interrupts-extended = <<
5450 <<
5451 clocks = <&rpmhcc RPM 4767 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 4768 clock-names = "xo", "alternate";
5453 4769
5454 #freq-domain-cells = 4770 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 4771 };
5457 4772
5458 wifi: wifi@18800000 { 4773 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 4774 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 4775 status = "disabled";
5461 reg = <0 0x18800000 0 4776 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 4777 reg-names = "membase";
5463 memory-region = <&wla 4778 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 4779 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 4780 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 4781 interrupts =
5467 <GIC_SPI 414 4782 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 4783 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 4784 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 4785 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 4786 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 4787 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 4788 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 4789 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 4790 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 4791 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 4792 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 4793 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 4794 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 4795 };
5481 }; 4796 };
5482 4797
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 4798 thermal-zones {
5487 cpu0-thermal { 4799 cpu0-thermal {
5488 polling-delay-passive 4800 polling-delay-passive = <250>;
>> 4801 polling-delay = <1000>;
5489 4802
5490 thermal-sensors = <&t 4803 thermal-sensors = <&tsens0 1>;
5491 4804
5492 trips { 4805 trips {
5493 cpu0_alert0: 4806 cpu0_alert0: trip-point0 {
5494 tempe 4807 temperature = <90000>;
5495 hyste 4808 hysteresis = <2000>;
5496 type 4809 type = "passive";
5497 }; 4810 };
5498 4811
5499 cpu0_alert1: 4812 cpu0_alert1: trip-point1 {
5500 tempe 4813 temperature = <95000>;
5501 hyste 4814 hysteresis = <2000>;
5502 type 4815 type = "passive";
5503 }; 4816 };
5504 4817
5505 cpu0_crit: cp !! 4818 cpu0_crit: cpu_crit {
5506 tempe 4819 temperature = <110000>;
5507 hyste 4820 hysteresis = <1000>;
5508 type 4821 type = "critical";
5509 }; 4822 };
5510 }; 4823 };
>> 4824
>> 4825 cooling-maps {
>> 4826 map0 {
>> 4827 trip = <&cpu0_alert0>;
>> 4828 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4829 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4830 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4831 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4832 };
>> 4833 map1 {
>> 4834 trip = <&cpu0_alert1>;
>> 4835 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4836 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4837 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4838 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4839 };
>> 4840 };
5511 }; 4841 };
5512 4842
5513 cpu1-thermal { 4843 cpu1-thermal {
5514 polling-delay-passive 4844 polling-delay-passive = <250>;
>> 4845 polling-delay = <1000>;
5515 4846
5516 thermal-sensors = <&t 4847 thermal-sensors = <&tsens0 2>;
5517 4848
5518 trips { 4849 trips {
5519 cpu1_alert0: 4850 cpu1_alert0: trip-point0 {
5520 tempe 4851 temperature = <90000>;
5521 hyste 4852 hysteresis = <2000>;
5522 type 4853 type = "passive";
5523 }; 4854 };
5524 4855
5525 cpu1_alert1: 4856 cpu1_alert1: trip-point1 {
5526 tempe 4857 temperature = <95000>;
5527 hyste 4858 hysteresis = <2000>;
5528 type 4859 type = "passive";
5529 }; 4860 };
5530 4861
5531 cpu1_crit: cp !! 4862 cpu1_crit: cpu_crit {
5532 tempe 4863 temperature = <110000>;
5533 hyste 4864 hysteresis = <1000>;
5534 type 4865 type = "critical";
5535 }; 4866 };
5536 }; 4867 };
>> 4868
>> 4869 cooling-maps {
>> 4870 map0 {
>> 4871 trip = <&cpu1_alert0>;
>> 4872 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4873 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4874 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4875 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4876 };
>> 4877 map1 {
>> 4878 trip = <&cpu1_alert1>;
>> 4879 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4880 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4881 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4882 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4883 };
>> 4884 };
5537 }; 4885 };
5538 4886
5539 cpu2-thermal { 4887 cpu2-thermal {
5540 polling-delay-passive 4888 polling-delay-passive = <250>;
>> 4889 polling-delay = <1000>;
5541 4890
5542 thermal-sensors = <&t 4891 thermal-sensors = <&tsens0 3>;
5543 4892
5544 trips { 4893 trips {
5545 cpu2_alert0: 4894 cpu2_alert0: trip-point0 {
5546 tempe 4895 temperature = <90000>;
5547 hyste 4896 hysteresis = <2000>;
5548 type 4897 type = "passive";
5549 }; 4898 };
5550 4899
5551 cpu2_alert1: 4900 cpu2_alert1: trip-point1 {
5552 tempe 4901 temperature = <95000>;
5553 hyste 4902 hysteresis = <2000>;
5554 type 4903 type = "passive";
5555 }; 4904 };
5556 4905
5557 cpu2_crit: cp !! 4906 cpu2_crit: cpu_crit {
5558 tempe 4907 temperature = <110000>;
5559 hyste 4908 hysteresis = <1000>;
5560 type 4909 type = "critical";
5561 }; 4910 };
5562 }; 4911 };
>> 4912
>> 4913 cooling-maps {
>> 4914 map0 {
>> 4915 trip = <&cpu2_alert0>;
>> 4916 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4917 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4918 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4919 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4920 };
>> 4921 map1 {
>> 4922 trip = <&cpu2_alert1>;
>> 4923 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4924 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4925 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4926 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4927 };
>> 4928 };
5563 }; 4929 };
5564 4930
5565 cpu3-thermal { 4931 cpu3-thermal {
5566 polling-delay-passive 4932 polling-delay-passive = <250>;
>> 4933 polling-delay = <1000>;
5567 4934
5568 thermal-sensors = <&t 4935 thermal-sensors = <&tsens0 4>;
5569 4936
5570 trips { 4937 trips {
5571 cpu3_alert0: 4938 cpu3_alert0: trip-point0 {
5572 tempe 4939 temperature = <90000>;
5573 hyste 4940 hysteresis = <2000>;
5574 type 4941 type = "passive";
5575 }; 4942 };
5576 4943
5577 cpu3_alert1: 4944 cpu3_alert1: trip-point1 {
5578 tempe 4945 temperature = <95000>;
5579 hyste 4946 hysteresis = <2000>;
5580 type 4947 type = "passive";
5581 }; 4948 };
5582 4949
5583 cpu3_crit: cp !! 4950 cpu3_crit: cpu_crit {
5584 tempe 4951 temperature = <110000>;
5585 hyste 4952 hysteresis = <1000>;
5586 type 4953 type = "critical";
5587 }; 4954 };
5588 }; 4955 };
>> 4956
>> 4957 cooling-maps {
>> 4958 map0 {
>> 4959 trip = <&cpu3_alert0>;
>> 4960 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4961 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4962 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4963 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4964 };
>> 4965 map1 {
>> 4966 trip = <&cpu3_alert1>;
>> 4967 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4968 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4969 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4970 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4971 };
>> 4972 };
5589 }; 4973 };
5590 4974
5591 cpu4-thermal { 4975 cpu4-thermal {
5592 polling-delay-passive 4976 polling-delay-passive = <250>;
>> 4977 polling-delay = <1000>;
5593 4978
5594 thermal-sensors = <&t 4979 thermal-sensors = <&tsens0 7>;
5595 4980
5596 trips { 4981 trips {
5597 cpu4_alert0: 4982 cpu4_alert0: trip-point0 {
5598 tempe 4983 temperature = <90000>;
5599 hyste 4984 hysteresis = <2000>;
5600 type 4985 type = "passive";
5601 }; 4986 };
5602 4987
5603 cpu4_alert1: 4988 cpu4_alert1: trip-point1 {
5604 tempe 4989 temperature = <95000>;
5605 hyste 4990 hysteresis = <2000>;
5606 type 4991 type = "passive";
5607 }; 4992 };
5608 4993
5609 cpu4_crit: cp !! 4994 cpu4_crit: cpu_crit {
5610 tempe 4995 temperature = <110000>;
5611 hyste 4996 hysteresis = <1000>;
5612 type 4997 type = "critical";
5613 }; 4998 };
5614 }; 4999 };
>> 5000
>> 5001 cooling-maps {
>> 5002 map0 {
>> 5003 trip = <&cpu4_alert0>;
>> 5004 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5005 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5006 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5007 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5008 };
>> 5009 map1 {
>> 5010 trip = <&cpu4_alert1>;
>> 5011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5015 };
>> 5016 };
5615 }; 5017 };
5616 5018
5617 cpu5-thermal { 5019 cpu5-thermal {
5618 polling-delay-passive 5020 polling-delay-passive = <250>;
>> 5021 polling-delay = <1000>;
5619 5022
5620 thermal-sensors = <&t 5023 thermal-sensors = <&tsens0 8>;
5621 5024
5622 trips { 5025 trips {
5623 cpu5_alert0: 5026 cpu5_alert0: trip-point0 {
5624 tempe 5027 temperature = <90000>;
5625 hyste 5028 hysteresis = <2000>;
5626 type 5029 type = "passive";
5627 }; 5030 };
5628 5031
5629 cpu5_alert1: 5032 cpu5_alert1: trip-point1 {
5630 tempe 5033 temperature = <95000>;
5631 hyste 5034 hysteresis = <2000>;
5632 type 5035 type = "passive";
5633 }; 5036 };
5634 5037
5635 cpu5_crit: cp !! 5038 cpu5_crit: cpu_crit {
5636 tempe 5039 temperature = <110000>;
5637 hyste 5040 hysteresis = <1000>;
5638 type 5041 type = "critical";
5639 }; 5042 };
5640 }; 5043 };
>> 5044
>> 5045 cooling-maps {
>> 5046 map0 {
>> 5047 trip = <&cpu5_alert0>;
>> 5048 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5049 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5050 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5051 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5052 };
>> 5053 map1 {
>> 5054 trip = <&cpu5_alert1>;
>> 5055 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5057 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5058 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5059 };
>> 5060 };
5641 }; 5061 };
5642 5062
5643 cpu6-thermal { 5063 cpu6-thermal {
5644 polling-delay-passive 5064 polling-delay-passive = <250>;
>> 5065 polling-delay = <1000>;
5645 5066
5646 thermal-sensors = <&t 5067 thermal-sensors = <&tsens0 9>;
5647 5068
5648 trips { 5069 trips {
5649 cpu6_alert0: 5070 cpu6_alert0: trip-point0 {
5650 tempe 5071 temperature = <90000>;
5651 hyste 5072 hysteresis = <2000>;
5652 type 5073 type = "passive";
5653 }; 5074 };
5654 5075
5655 cpu6_alert1: 5076 cpu6_alert1: trip-point1 {
5656 tempe 5077 temperature = <95000>;
5657 hyste 5078 hysteresis = <2000>;
5658 type 5079 type = "passive";
5659 }; 5080 };
5660 5081
5661 cpu6_crit: cp !! 5082 cpu6_crit: cpu_crit {
5662 tempe 5083 temperature = <110000>;
5663 hyste 5084 hysteresis = <1000>;
5664 type 5085 type = "critical";
5665 }; 5086 };
5666 }; 5087 };
>> 5088
>> 5089 cooling-maps {
>> 5090 map0 {
>> 5091 trip = <&cpu6_alert0>;
>> 5092 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5093 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5094 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5095 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5096 };
>> 5097 map1 {
>> 5098 trip = <&cpu6_alert1>;
>> 5099 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5100 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5101 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5102 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5103 };
>> 5104 };
5667 }; 5105 };
5668 5106
5669 cpu7-thermal { 5107 cpu7-thermal {
5670 polling-delay-passive 5108 polling-delay-passive = <250>;
>> 5109 polling-delay = <1000>;
5671 5110
5672 thermal-sensors = <&t 5111 thermal-sensors = <&tsens0 10>;
5673 5112
5674 trips { 5113 trips {
5675 cpu7_alert0: 5114 cpu7_alert0: trip-point0 {
5676 tempe 5115 temperature = <90000>;
5677 hyste 5116 hysteresis = <2000>;
5678 type 5117 type = "passive";
5679 }; 5118 };
5680 5119
5681 cpu7_alert1: 5120 cpu7_alert1: trip-point1 {
5682 tempe 5121 temperature = <95000>;
5683 hyste 5122 hysteresis = <2000>;
5684 type 5123 type = "passive";
5685 }; 5124 };
5686 5125
5687 cpu7_crit: cp !! 5126 cpu7_crit: cpu_crit {
5688 tempe 5127 temperature = <110000>;
5689 hyste 5128 hysteresis = <1000>;
5690 type 5129 type = "critical";
5691 }; 5130 };
5692 }; 5131 };
>> 5132
>> 5133 cooling-maps {
>> 5134 map0 {
>> 5135 trip = <&cpu7_alert0>;
>> 5136 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5137 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5138 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5139 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5140 };
>> 5141 map1 {
>> 5142 trip = <&cpu7_alert1>;
>> 5143 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5144 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5145 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5146 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5147 };
>> 5148 };
5693 }; 5149 };
5694 5150
5695 aoss0-thermal { 5151 aoss0-thermal {
5696 polling-delay-passive 5152 polling-delay-passive = <250>;
>> 5153 polling-delay = <1000>;
5697 5154
5698 thermal-sensors = <&t 5155 thermal-sensors = <&tsens0 0>;
5699 5156
5700 trips { 5157 trips {
5701 aoss0_alert0: 5158 aoss0_alert0: trip-point0 {
5702 tempe 5159 temperature = <90000>;
5703 hyste 5160 hysteresis = <2000>;
5704 type 5161 type = "hot";
5705 }; 5162 };
5706 }; 5163 };
5707 }; 5164 };
5708 5165
5709 cluster0-thermal { 5166 cluster0-thermal {
5710 polling-delay-passive 5167 polling-delay-passive = <250>;
>> 5168 polling-delay = <1000>;
5711 5169
5712 thermal-sensors = <&t 5170 thermal-sensors = <&tsens0 5>;
5713 5171
5714 trips { 5172 trips {
5715 cluster0_aler 5173 cluster0_alert0: trip-point0 {
5716 tempe 5174 temperature = <90000>;
5717 hyste 5175 hysteresis = <2000>;
5718 type 5176 type = "hot";
5719 }; 5177 };
5720 cluster0_crit !! 5178 cluster0_crit: cluster0_crit {
5721 tempe 5179 temperature = <110000>;
5722 hyste 5180 hysteresis = <2000>;
5723 type 5181 type = "critical";
5724 }; 5182 };
5725 }; 5183 };
5726 }; 5184 };
5727 5185
5728 cluster1-thermal { 5186 cluster1-thermal {
5729 polling-delay-passive 5187 polling-delay-passive = <250>;
>> 5188 polling-delay = <1000>;
5730 5189
5731 thermal-sensors = <&t 5190 thermal-sensors = <&tsens0 6>;
5732 5191
5733 trips { 5192 trips {
5734 cluster1_aler 5193 cluster1_alert0: trip-point0 {
5735 tempe 5194 temperature = <90000>;
5736 hyste 5195 hysteresis = <2000>;
5737 type 5196 type = "hot";
5738 }; 5197 };
5739 cluster1_crit !! 5198 cluster1_crit: cluster1_crit {
5740 tempe 5199 temperature = <110000>;
5741 hyste 5200 hysteresis = <2000>;
5742 type 5201 type = "critical";
5743 }; 5202 };
5744 }; 5203 };
5745 }; 5204 };
5746 5205
5747 gpu-top-thermal { !! 5206 gpu-thermal-top {
5748 polling-delay-passive 5207 polling-delay-passive = <250>;
>> 5208 polling-delay = <1000>;
5749 5209
5750 thermal-sensors = <&t 5210 thermal-sensors = <&tsens0 11>;
5751 5211
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5212 trips {
5760 gpu_top_alert !! 5213 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5214 temperature = <90000>;
5768 hyste !! 5215 hysteresis = <2000>;
5769 type 5216 type = "hot";
5770 }; 5217 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5218 };
5778 }; 5219 };
5779 5220
5780 gpu-bottom-thermal { !! 5221 gpu-thermal-bottom {
5781 polling-delay-passive 5222 polling-delay-passive = <250>;
>> 5223 polling-delay = <1000>;
5782 5224
5783 thermal-sensors = <&t 5225 thermal-sensors = <&tsens0 12>;
5784 5226
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5227 trips {
5793 gpu_bottom_al !! 5228 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5229 temperature = <90000>;
5801 hyste !! 5230 hysteresis = <2000>;
5802 type 5231 type = "hot";
5803 }; 5232 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5233 };
5811 }; 5234 };
5812 5235
5813 aoss1-thermal { 5236 aoss1-thermal {
5814 polling-delay-passive 5237 polling-delay-passive = <250>;
>> 5238 polling-delay = <1000>;
5815 5239
5816 thermal-sensors = <&t 5240 thermal-sensors = <&tsens1 0>;
5817 5241
5818 trips { 5242 trips {
5819 aoss1_alert0: 5243 aoss1_alert0: trip-point0 {
5820 tempe 5244 temperature = <90000>;
5821 hyste 5245 hysteresis = <2000>;
5822 type 5246 type = "hot";
5823 }; 5247 };
5824 }; 5248 };
5825 }; 5249 };
5826 5250
5827 q6-modem-thermal { 5251 q6-modem-thermal {
5828 polling-delay-passive 5252 polling-delay-passive = <250>;
>> 5253 polling-delay = <1000>;
5829 5254
5830 thermal-sensors = <&t 5255 thermal-sensors = <&tsens1 1>;
5831 5256
5832 trips { 5257 trips {
5833 q6_modem_aler 5258 q6_modem_alert0: trip-point0 {
5834 tempe 5259 temperature = <90000>;
5835 hyste 5260 hysteresis = <2000>;
5836 type 5261 type = "hot";
5837 }; 5262 };
5838 }; 5263 };
5839 }; 5264 };
5840 5265
5841 mem-thermal { 5266 mem-thermal {
5842 polling-delay-passive 5267 polling-delay-passive = <250>;
>> 5268 polling-delay = <1000>;
5843 5269
5844 thermal-sensors = <&t 5270 thermal-sensors = <&tsens1 2>;
5845 5271
5846 trips { 5272 trips {
5847 mem_alert0: t 5273 mem_alert0: trip-point0 {
5848 tempe 5274 temperature = <90000>;
5849 hyste 5275 hysteresis = <2000>;
5850 type 5276 type = "hot";
5851 }; 5277 };
5852 }; 5278 };
5853 }; 5279 };
5854 5280
5855 wlan-thermal { 5281 wlan-thermal {
5856 polling-delay-passive 5282 polling-delay-passive = <250>;
>> 5283 polling-delay = <1000>;
5857 5284
5858 thermal-sensors = <&t 5285 thermal-sensors = <&tsens1 3>;
5859 5286
5860 trips { 5287 trips {
5861 wlan_alert0: 5288 wlan_alert0: trip-point0 {
5862 tempe 5289 temperature = <90000>;
5863 hyste 5290 hysteresis = <2000>;
5864 type 5291 type = "hot";
5865 }; 5292 };
5866 }; 5293 };
5867 }; 5294 };
5868 5295
5869 q6-hvx-thermal { 5296 q6-hvx-thermal {
5870 polling-delay-passive 5297 polling-delay-passive = <250>;
>> 5298 polling-delay = <1000>;
5871 5299
5872 thermal-sensors = <&t 5300 thermal-sensors = <&tsens1 4>;
5873 5301
5874 trips { 5302 trips {
5875 q6_hvx_alert0 5303 q6_hvx_alert0: trip-point0 {
5876 tempe 5304 temperature = <90000>;
5877 hyste 5305 hysteresis = <2000>;
5878 type 5306 type = "hot";
5879 }; 5307 };
5880 }; 5308 };
5881 }; 5309 };
5882 5310
5883 camera-thermal { 5311 camera-thermal {
5884 polling-delay-passive 5312 polling-delay-passive = <250>;
>> 5313 polling-delay = <1000>;
5885 5314
5886 thermal-sensors = <&t 5315 thermal-sensors = <&tsens1 5>;
5887 5316
5888 trips { 5317 trips {
5889 camera_alert0 5318 camera_alert0: trip-point0 {
5890 tempe 5319 temperature = <90000>;
5891 hyste 5320 hysteresis = <2000>;
5892 type 5321 type = "hot";
5893 }; 5322 };
5894 }; 5323 };
5895 }; 5324 };
5896 5325
5897 video-thermal { 5326 video-thermal {
5898 polling-delay-passive 5327 polling-delay-passive = <250>;
>> 5328 polling-delay = <1000>;
5899 5329
5900 thermal-sensors = <&t 5330 thermal-sensors = <&tsens1 6>;
5901 5331
5902 trips { 5332 trips {
5903 video_alert0: 5333 video_alert0: trip-point0 {
5904 tempe 5334 temperature = <90000>;
5905 hyste 5335 hysteresis = <2000>;
5906 type 5336 type = "hot";
5907 }; 5337 };
5908 }; 5338 };
5909 }; 5339 };
5910 5340
5911 modem-thermal { 5341 modem-thermal {
5912 polling-delay-passive 5342 polling-delay-passive = <250>;
>> 5343 polling-delay = <1000>;
5913 5344
5914 thermal-sensors = <&t 5345 thermal-sensors = <&tsens1 7>;
5915 5346
5916 trips { 5347 trips {
5917 modem_alert0: 5348 modem_alert0: trip-point0 {
5918 tempe 5349 temperature = <90000>;
5919 hyste 5350 hysteresis = <2000>;
5920 type 5351 type = "hot";
5921 }; 5352 };
5922 }; 5353 };
5923 }; 5354 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5355 };
5933 }; 5356 };
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