1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> <<
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 16 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 17 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 22 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 25 #include <dt-bindings/thermal/thermal.h>
31 26
32 / { 27 / {
33 interrupt-parent = <&intc>; 28 interrupt-parent = <&intc>;
34 29
35 #address-cells = <2>; 30 #address-cells = <2>;
36 #size-cells = <2>; 31 #size-cells = <2>;
37 32
38 aliases { 33 aliases {
39 i2c0 = &i2c0; 34 i2c0 = &i2c0;
40 i2c1 = &i2c1; 35 i2c1 = &i2c1;
41 i2c2 = &i2c2; 36 i2c2 = &i2c2;
42 i2c3 = &i2c3; 37 i2c3 = &i2c3;
43 i2c4 = &i2c4; 38 i2c4 = &i2c4;
44 i2c5 = &i2c5; 39 i2c5 = &i2c5;
45 i2c6 = &i2c6; 40 i2c6 = &i2c6;
46 i2c7 = &i2c7; 41 i2c7 = &i2c7;
47 i2c8 = &i2c8; 42 i2c8 = &i2c8;
48 i2c9 = &i2c9; 43 i2c9 = &i2c9;
49 i2c10 = &i2c10; 44 i2c10 = &i2c10;
50 i2c11 = &i2c11; 45 i2c11 = &i2c11;
51 i2c12 = &i2c12; 46 i2c12 = &i2c12;
52 i2c13 = &i2c13; 47 i2c13 = &i2c13;
53 i2c14 = &i2c14; 48 i2c14 = &i2c14;
54 i2c15 = &i2c15; 49 i2c15 = &i2c15;
55 spi0 = &spi0; 50 spi0 = &spi0;
56 spi1 = &spi1; 51 spi1 = &spi1;
57 spi2 = &spi2; 52 spi2 = &spi2;
58 spi3 = &spi3; 53 spi3 = &spi3;
59 spi4 = &spi4; 54 spi4 = &spi4;
60 spi5 = &spi5; 55 spi5 = &spi5;
61 spi6 = &spi6; 56 spi6 = &spi6;
62 spi7 = &spi7; 57 spi7 = &spi7;
63 spi8 = &spi8; 58 spi8 = &spi8;
64 spi9 = &spi9; 59 spi9 = &spi9;
65 spi10 = &spi10; 60 spi10 = &spi10;
66 spi11 = &spi11; 61 spi11 = &spi11;
67 spi12 = &spi12; 62 spi12 = &spi12;
68 spi13 = &spi13; 63 spi13 = &spi13;
69 spi14 = &spi14; 64 spi14 = &spi14;
70 spi15 = &spi15; 65 spi15 = &spi15;
71 }; 66 };
72 67
73 chosen { }; 68 chosen { };
74 69
75 clocks { !! 70 memory@80000000 {
76 xo_board: xo-board { !! 71 device_type = "memory";
77 compatible = "fixed-cl !! 72 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 73 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 74 };
80 clock-output-names = " !! 75
>> 76 reserved-memory {
>> 77 #address-cells = <2>;
>> 78 #size-cells = <2>;
>> 79 ranges;
>> 80
>> 81 hyp_mem: memory@85700000 {
>> 82 reg = <0 0x85700000 0 0x600000>;
>> 83 no-map;
81 }; 84 };
82 85
83 sleep_clk: sleep-clk { !! 86 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 87 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 88 no-map;
86 clock-frequency = <327 !! 89 };
>> 90
>> 91 aop_mem: memory@85fc0000 {
>> 92 reg = <0 0x85fc0000 0 0x20000>;
>> 93 no-map;
>> 94 };
>> 95
>> 96 aop_cmd_db_mem: memory@85fe0000 {
>> 97 compatible = "qcom,cmd-db";
>> 98 reg = <0x0 0x85fe0000 0 0x20000>;
>> 99 no-map;
>> 100 };
>> 101
>> 102 smem_mem: memory@86000000 {
>> 103 reg = <0x0 0x86000000 0 0x200000>;
>> 104 no-map;
>> 105 };
>> 106
>> 107 tz_mem: memory@86200000 {
>> 108 reg = <0 0x86200000 0 0x2d00000>;
>> 109 no-map;
>> 110 };
>> 111
>> 112 rmtfs_mem: memory@88f00000 {
>> 113 compatible = "qcom,rmtfs-mem";
>> 114 reg = <0 0x88f00000 0 0x200000>;
>> 115 no-map;
>> 116
>> 117 qcom,client-id = <1>;
>> 118 qcom,vmid = <15>;
>> 119 };
>> 120
>> 121 qseecom_mem: memory@8ab00000 {
>> 122 reg = <0 0x8ab00000 0 0x1400000>;
>> 123 no-map;
>> 124 };
>> 125
>> 126 camera_mem: memory@8bf00000 {
>> 127 reg = <0 0x8bf00000 0 0x500000>;
>> 128 no-map;
>> 129 };
>> 130
>> 131 ipa_fw_mem: memory@8c400000 {
>> 132 reg = <0 0x8c400000 0 0x10000>;
>> 133 no-map;
>> 134 };
>> 135
>> 136 ipa_gsi_mem: memory@8c410000 {
>> 137 reg = <0 0x8c410000 0 0x5000>;
>> 138 no-map;
>> 139 };
>> 140
>> 141 gpu_mem: memory@8c415000 {
>> 142 reg = <0 0x8c415000 0 0x2000>;
>> 143 no-map;
>> 144 };
>> 145
>> 146 adsp_mem: memory@8c500000 {
>> 147 reg = <0 0x8c500000 0 0x1a00000>;
>> 148 no-map;
>> 149 };
>> 150
>> 151 wlan_msa_mem: memory@8df00000 {
>> 152 reg = <0 0x8df00000 0 0x100000>;
>> 153 no-map;
>> 154 };
>> 155
>> 156 mpss_region: memory@8e000000 {
>> 157 reg = <0 0x8e000000 0 0x7800000>;
>> 158 no-map;
>> 159 };
>> 160
>> 161 venus_mem: memory@95800000 {
>> 162 reg = <0 0x95800000 0 0x500000>;
>> 163 no-map;
>> 164 };
>> 165
>> 166 cdsp_mem: memory@95d00000 {
>> 167 reg = <0 0x95d00000 0 0x800000>;
>> 168 no-map;
>> 169 };
>> 170
>> 171 mba_region: memory@96500000 {
>> 172 reg = <0 0x96500000 0 0x200000>;
>> 173 no-map;
>> 174 };
>> 175
>> 176 slpi_mem: memory@96700000 {
>> 177 reg = <0 0x96700000 0 0x1400000>;
>> 178 no-map;
>> 179 };
>> 180
>> 181 spss_mem: memory@97b00000 {
>> 182 reg = <0 0x97b00000 0 0x100000>;
>> 183 no-map;
87 }; 184 };
88 }; 185 };
89 186
90 cpus: cpus { !! 187 cpus {
91 #address-cells = <2>; 188 #address-cells = <2>;
92 #size-cells = <0>; 189 #size-cells = <0>;
93 190
94 CPU0: cpu@0 { 191 CPU0: cpu@0 {
95 device_type = "cpu"; 192 device_type = "cpu";
96 compatible = "qcom,kry 193 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 194 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 195 enable-method = "psci";
100 capacity-dmips-mhz = < !! 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101 dynamic-power-coeffici !! 197 &LITTLE_CPU_SLEEP_1
>> 198 &CLUSTER_SLEEP_0>;
>> 199 capacity-dmips-mhz = <607>;
>> 200 dynamic-power-coefficient = <100>;
102 qcom,freq-domain = <&c 201 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 202 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 205 #cooling-cells = <2>;
109 next-level-cache = <&L 206 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 207 L2_0: l2-cache {
111 compatible = " 208 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 209 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 210 L3_0: l3-cache {
116 compat !! 211 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 212 };
120 }; 213 };
121 }; 214 };
122 215
123 CPU1: cpu@100 { 216 CPU1: cpu@100 {
124 device_type = "cpu"; 217 device_type = "cpu";
125 compatible = "qcom,kry 218 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 219 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 220 enable-method = "psci";
129 capacity-dmips-mhz = < !! 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130 dynamic-power-coeffici !! 222 &LITTLE_CPU_SLEEP_1
>> 223 &CLUSTER_SLEEP_0>;
>> 224 capacity-dmips-mhz = <607>;
>> 225 dynamic-power-coefficient = <100>;
131 qcom,freq-domain = <&c 226 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 227 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 230 #cooling-cells = <2>;
138 next-level-cache = <&L 231 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 232 L2_100: l2-cache {
140 compatible = " 233 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 234 next-level-cache = <&L3_0>;
144 }; 235 };
145 }; 236 };
146 237
147 CPU2: cpu@200 { 238 CPU2: cpu@200 {
148 device_type = "cpu"; 239 device_type = "cpu";
149 compatible = "qcom,kry 240 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 241 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 242 enable-method = "psci";
153 capacity-dmips-mhz = < !! 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154 dynamic-power-coeffici !! 244 &LITTLE_CPU_SLEEP_1
>> 245 &CLUSTER_SLEEP_0>;
>> 246 capacity-dmips-mhz = <607>;
>> 247 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&c 248 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 249 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 252 #cooling-cells = <2>;
162 next-level-cache = <&L 253 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 254 L2_200: l2-cache {
164 compatible = " 255 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 256 next-level-cache = <&L3_0>;
168 }; 257 };
169 }; 258 };
170 259
171 CPU3: cpu@300 { 260 CPU3: cpu@300 {
172 device_type = "cpu"; 261 device_type = "cpu";
173 compatible = "qcom,kry 262 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 263 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 264 enable-method = "psci";
177 capacity-dmips-mhz = < !! 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178 dynamic-power-coeffici !! 266 &LITTLE_CPU_SLEEP_1
>> 267 &CLUSTER_SLEEP_0>;
>> 268 capacity-dmips-mhz = <607>;
>> 269 dynamic-power-coefficient = <100>;
179 qcom,freq-domain = <&c 270 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 271 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 274 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 275 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 276 L2_300: l2-cache {
188 compatible = " 277 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 278 next-level-cache = <&L3_0>;
192 }; 279 };
193 }; 280 };
194 281
195 CPU4: cpu@400 { 282 CPU4: cpu@400 {
196 device_type = "cpu"; 283 device_type = "cpu";
197 compatible = "qcom,kry 284 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 285 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 286 enable-method = "psci";
201 capacity-dmips-mhz = < 287 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici !! 288 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 289 &BIG_CPU_SLEEP_1
>> 290 &CLUSTER_SLEEP_0>;
>> 291 dynamic-power-coefficient = <396>;
203 qcom,freq-domain = <&c 292 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 293 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 296 #cooling-cells = <2>;
210 next-level-cache = <&L 297 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 298 L2_400: l2-cache {
212 compatible = " 299 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 300 next-level-cache = <&L3_0>;
216 }; 301 };
217 }; 302 };
218 303
219 CPU5: cpu@500 { 304 CPU5: cpu@500 {
220 device_type = "cpu"; 305 device_type = "cpu";
221 compatible = "qcom,kry 306 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 307 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 308 enable-method = "psci";
225 capacity-dmips-mhz = < 309 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici !! 310 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 311 &BIG_CPU_SLEEP_1
>> 312 &CLUSTER_SLEEP_0>;
>> 313 dynamic-power-coefficient = <396>;
227 qcom,freq-domain = <&c 314 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 315 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 318 #cooling-cells = <2>;
234 next-level-cache = <&L 319 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 320 L2_500: l2-cache {
236 compatible = " 321 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 322 next-level-cache = <&L3_0>;
240 }; 323 };
241 }; 324 };
242 325
243 CPU6: cpu@600 { 326 CPU6: cpu@600 {
244 device_type = "cpu"; 327 device_type = "cpu";
245 compatible = "qcom,kry 328 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 329 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 330 enable-method = "psci";
249 capacity-dmips-mhz = < 331 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici !! 332 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 333 &BIG_CPU_SLEEP_1
>> 334 &CLUSTER_SLEEP_0>;
>> 335 dynamic-power-coefficient = <396>;
251 qcom,freq-domain = <&c 336 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 337 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 340 #cooling-cells = <2>;
258 next-level-cache = <&L 341 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 342 L2_600: l2-cache {
260 compatible = " 343 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 344 next-level-cache = <&L3_0>;
264 }; 345 };
265 }; 346 };
266 347
267 CPU7: cpu@700 { 348 CPU7: cpu@700 {
268 device_type = "cpu"; 349 device_type = "cpu";
269 compatible = "qcom,kry 350 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 351 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 352 enable-method = "psci";
273 capacity-dmips-mhz = < 353 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici !! 354 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 355 &BIG_CPU_SLEEP_1
>> 356 &CLUSTER_SLEEP_0>;
>> 357 dynamic-power-coefficient = <396>;
275 qcom,freq-domain = <&c 358 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 359 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 362 #cooling-cells = <2>;
282 next-level-cache = <&L 363 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 364 L2_700: l2-cache {
284 compatible = " 365 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 366 next-level-cache = <&L3_0>;
288 }; 367 };
289 }; 368 };
290 369
291 cpu-map { 370 cpu-map {
292 cluster0 { 371 cluster0 {
293 core0 { 372 core0 {
294 cpu = 373 cpu = <&CPU0>;
295 }; 374 };
296 375
297 core1 { 376 core1 {
298 cpu = 377 cpu = <&CPU1>;
299 }; 378 };
300 379
301 core2 { 380 core2 {
302 cpu = 381 cpu = <&CPU2>;
303 }; 382 };
304 383
305 core3 { 384 core3 {
306 cpu = 385 cpu = <&CPU3>;
307 }; 386 };
308 387
309 core4 { 388 core4 {
310 cpu = 389 cpu = <&CPU4>;
311 }; 390 };
312 391
313 core5 { 392 core5 {
314 cpu = 393 cpu = <&CPU5>;
315 }; 394 };
316 395
317 core6 { 396 core6 {
318 cpu = 397 cpu = <&CPU6>;
319 }; 398 };
320 399
321 core7 { 400 core7 {
322 cpu = 401 cpu = <&CPU7>;
323 }; 402 };
324 }; 403 };
325 }; 404 };
326 405
327 cpu_idle_states: idle-states { !! 406 idle-states {
328 entry-method = "psci"; 407 entry-method = "psci";
329 408
330 LITTLE_CPU_SLEEP_0: cp 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 410 compatible = "arm,idle-state";
332 idle-state-nam !! 411 idle-state-name = "little-power-down";
333 arm,psci-suspe !! 412 arm,psci-suspend-param = <0x40000003>;
334 entry-latency- 413 entry-latency-us = <350>;
335 exit-latency-u 414 exit-latency-us = <461>;
336 min-residency- 415 min-residency-us = <1890>;
337 local-timer-st 416 local-timer-stop;
338 }; 417 };
339 418
340 BIG_CPU_SLEEP_0: cpu-s !! 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341 compatible = " 420 compatible = "arm,idle-state";
342 idle-state-nam !! 421 idle-state-name = "little-rail-power-down";
343 arm,psci-suspe 422 arm,psci-suspend-param = <0x40000004>;
>> 423 entry-latency-us = <360>;
>> 424 exit-latency-us = <531>;
>> 425 min-residency-us = <3934>;
>> 426 local-timer-stop;
>> 427 };
>> 428
>> 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> 430 compatible = "arm,idle-state";
>> 431 idle-state-name = "big-power-down";
>> 432 arm,psci-suspend-param = <0x40000003>;
344 entry-latency- 433 entry-latency-us = <264>;
345 exit-latency-u 434 exit-latency-us = <621>;
346 min-residency- 435 min-residency-us = <952>;
347 local-timer-st 436 local-timer-stop;
348 }; 437 };
349 }; <<
350 438
351 domain-idle-states { !! 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
>> 440 compatible = "arm,idle-state";
>> 441 idle-state-name = "big-rail-power-down";
>> 442 arm,psci-suspend-param = <0x40000004>;
>> 443 entry-latency-us = <702>;
>> 444 exit-latency-us = <1061>;
>> 445 min-residency-us = <4488>;
>> 446 local-timer-stop;
>> 447 };
>> 448
352 CLUSTER_SLEEP_0: clust 449 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " !! 450 compatible = "arm,idle-state";
354 arm,psci-suspe !! 451 idle-state-name = "cluster-power-down";
>> 452 arm,psci-suspend-param = <0x400000F4>;
355 entry-latency- 453 entry-latency-us = <3263>;
356 exit-latency-u 454 exit-latency-us = <6562>;
357 min-residency- 455 min-residency-us = <9987>;
>> 456 local-timer-stop;
358 }; 457 };
359 }; 458 };
360 }; 459 };
361 460
362 firmware { !! 461 cpu0_opp_table: cpu0_opp_table {
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points 462 compatible = "operating-points-v2";
376 opp-shared; 463 opp-shared;
377 464
378 cpu0_opp1: opp-300000000 { 465 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 466 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 467 opp-peak-kBps = <800000 4800000>;
381 }; 468 };
382 469
383 cpu0_opp2: opp-403200000 { 470 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 471 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 472 opp-peak-kBps = <800000 4800000>;
386 }; 473 };
387 474
388 cpu0_opp3: opp-480000000 { 475 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 476 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 477 opp-peak-kBps = <800000 6451200>;
391 }; 478 };
392 479
393 cpu0_opp4: opp-576000000 { 480 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 481 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 482 opp-peak-kBps = <800000 6451200>;
396 }; 483 };
397 484
398 cpu0_opp5: opp-652800000 { 485 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 486 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 487 opp-peak-kBps = <800000 7680000>;
401 }; 488 };
402 489
403 cpu0_opp6: opp-748800000 { 490 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 491 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 492 opp-peak-kBps = <1804000 9216000>;
406 }; 493 };
407 494
408 cpu0_opp7: opp-825600000 { 495 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 496 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 497 opp-peak-kBps = <1804000 9216000>;
411 }; 498 };
412 499
413 cpu0_opp8: opp-902400000 { 500 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 501 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 502 opp-peak-kBps = <1804000 10444800>;
416 }; 503 };
417 504
418 cpu0_opp9: opp-979200000 { 505 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 506 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 507 opp-peak-kBps = <1804000 11980800>;
421 }; 508 };
422 509
423 cpu0_opp10: opp-1056000000 { 510 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 511 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 512 opp-peak-kBps = <1804000 11980800>;
426 }; 513 };
427 514
428 cpu0_opp11: opp-1132800000 { 515 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 516 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 517 opp-peak-kBps = <2188000 13516800>;
431 }; 518 };
432 519
433 cpu0_opp12: opp-1228800000 { 520 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 521 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 522 opp-peak-kBps = <2188000 15052800>;
436 }; 523 };
437 524
438 cpu0_opp13: opp-1324800000 { 525 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 526 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 527 opp-peak-kBps = <2188000 16588800>;
441 }; 528 };
442 529
443 cpu0_opp14: opp-1420800000 { 530 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 531 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 532 opp-peak-kBps = <3072000 18124800>;
446 }; 533 };
447 534
448 cpu0_opp15: opp-1516800000 { 535 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 536 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 537 opp-peak-kBps = <3072000 19353600>;
451 }; 538 };
452 539
453 cpu0_opp16: opp-1612800000 { 540 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 541 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 542 opp-peak-kBps = <4068000 19353600>;
456 }; 543 };
457 544
458 cpu0_opp17: opp-1689600000 { 545 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 546 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 547 opp-peak-kBps = <4068000 20889600>;
461 }; 548 };
462 549
463 cpu0_opp18: opp-1766400000 { 550 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 551 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 552 opp-peak-kBps = <4068000 22425600>;
466 }; 553 };
467 }; 554 };
468 555
469 cpu4_opp_table: opp-table-cpu4 { !! 556 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 557 compatible = "operating-points-v2";
471 opp-shared; 558 opp-shared;
472 559
473 cpu4_opp1: opp-300000000 { 560 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 561 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 562 opp-peak-kBps = <800000 4800000>;
476 }; 563 };
477 564
478 cpu4_opp2: opp-403200000 { 565 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 566 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 567 opp-peak-kBps = <800000 4800000>;
481 }; 568 };
482 569
483 cpu4_opp3: opp-480000000 { 570 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 571 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 572 opp-peak-kBps = <1804000 4800000>;
486 }; 573 };
487 574
488 cpu4_opp4: opp-576000000 { 575 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 576 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 577 opp-peak-kBps = <1804000 4800000>;
491 }; 578 };
492 579
493 cpu4_opp5: opp-652800000 { 580 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 581 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 582 opp-peak-kBps = <1804000 4800000>;
496 }; 583 };
497 584
498 cpu4_opp6: opp-748800000 { 585 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 586 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 587 opp-peak-kBps = <1804000 4800000>;
501 }; 588 };
502 589
503 cpu4_opp7: opp-825600000 { 590 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 591 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 592 opp-peak-kBps = <2188000 9216000>;
506 }; 593 };
507 594
508 cpu4_opp8: opp-902400000 { 595 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 596 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 597 opp-peak-kBps = <2188000 9216000>;
511 }; 598 };
512 599
513 cpu4_opp9: opp-979200000 { 600 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 601 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 602 opp-peak-kBps = <2188000 9216000>;
516 }; 603 };
517 604
518 cpu4_opp10: opp-1056000000 { 605 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 606 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 607 opp-peak-kBps = <3072000 9216000>;
521 }; 608 };
522 609
523 cpu4_opp11: opp-1132800000 { 610 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 611 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 612 opp-peak-kBps = <3072000 11980800>;
526 }; 613 };
527 614
528 cpu4_opp12: opp-1209600000 { 615 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 616 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 617 opp-peak-kBps = <4068000 11980800>;
531 }; 618 };
532 619
533 cpu4_opp13: opp-1286400000 { 620 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 621 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 622 opp-peak-kBps = <4068000 11980800>;
536 }; 623 };
537 624
538 cpu4_opp14: opp-1363200000 { 625 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 626 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 627 opp-peak-kBps = <4068000 15052800>;
541 }; 628 };
542 629
543 cpu4_opp15: opp-1459200000 { 630 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 631 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 632 opp-peak-kBps = <4068000 15052800>;
546 }; 633 };
547 634
548 cpu4_opp16: opp-1536000000 { 635 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 636 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 637 opp-peak-kBps = <5412000 15052800>;
551 }; 638 };
552 639
553 cpu4_opp17: opp-1612800000 { 640 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 641 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 642 opp-peak-kBps = <5412000 15052800>;
556 }; 643 };
557 644
558 cpu4_opp18: opp-1689600000 { 645 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 646 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 647 opp-peak-kBps = <5412000 19353600>;
561 }; 648 };
562 649
563 cpu4_opp19: opp-1766400000 { 650 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 651 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 652 opp-peak-kBps = <6220000 19353600>;
566 }; 653 };
567 654
568 cpu4_opp20: opp-1843200000 { 655 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 656 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 657 opp-peak-kBps = <6220000 19353600>;
571 }; 658 };
572 659
573 cpu4_opp21: opp-1920000000 { 660 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 661 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 662 opp-peak-kBps = <7216000 19353600>;
576 }; 663 };
577 664
578 cpu4_opp22: opp-1996800000 { 665 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 666 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 667 opp-peak-kBps = <7216000 20889600>;
581 }; 668 };
582 669
583 cpu4_opp23: opp-2092800000 { 670 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 671 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 672 opp-peak-kBps = <7216000 20889600>;
586 }; 673 };
587 674
588 cpu4_opp24: opp-2169600000 { 675 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 676 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 677 opp-peak-kBps = <7216000 20889600>;
591 }; 678 };
592 679
593 cpu4_opp25: opp-2246400000 { 680 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 681 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 682 opp-peak-kBps = <7216000 20889600>;
596 }; 683 };
597 684
598 cpu4_opp26: opp-2323200000 { 685 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 686 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 687 opp-peak-kBps = <7216000 20889600>;
601 }; 688 };
602 689
603 cpu4_opp27: opp-2400000000 { 690 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 691 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 692 opp-peak-kBps = <7216000 22425600>;
606 }; 693 };
607 694
608 cpu4_opp28: opp-2476800000 { 695 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 696 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 697 opp-peak-kBps = <7216000 22425600>;
611 }; 698 };
612 699
613 cpu4_opp29: opp-2553600000 { 700 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 701 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 702 opp-peak-kBps = <7216000 22425600>;
616 }; 703 };
617 704
618 cpu4_opp30: opp-2649600000 { 705 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 706 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 707 opp-peak-kBps = <7216000 22425600>;
621 }; 708 };
622 709
623 cpu4_opp31: opp-2745600000 { 710 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 711 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 712 opp-peak-kBps = <7216000 25497600>;
626 }; 713 };
627 714
628 cpu4_opp32: opp-2803200000 { 715 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 716 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 717 opp-peak-kBps = <7216000 25497600>;
631 }; 718 };
632 }; 719 };
633 720
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 721 pmu {
712 compatible = "arm,armv8-pmuv3" 722 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 724 };
715 725
716 psci: psci { !! 726 timer {
717 compatible = "arm,psci-1.0"; !! 727 compatible = "arm,armv8-timer";
718 method = "smc"; !! 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 732 };
773 733
774 reserved-memory { !! 734 clocks {
775 #address-cells = <2>; !! 735 xo_board: xo-board {
776 #size-cells = <2>; !! 736 compatible = "fixed-clock";
777 ranges; !! 737 #clock-cells = <0>;
778 !! 738 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 739 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 740 };
885 741
886 mdata_mem: mpss-metadata { !! 742 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 743 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 744 #clock-cells = <0>;
889 no-map; !! 745 clock-frequency = <32764>;
890 }; 746 };
>> 747 };
891 748
892 fastrpc_mem: fastrpc { !! 749 firmware {
893 compatible = "shared-d !! 750 scm {
894 alloc-ranges = <0x0 0x !! 751 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 752 };
899 }; 753 };
900 754
901 adsp_pas: remoteproc-adsp { 755 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 756 compatible = "qcom,sdm845-adsp-pas";
903 757
904 interrupts-extended = <&intc G 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 763 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 764 "handover", "stop-ack";
911 765
912 clocks = <&rpmhcc RPMH_CXO_CLK 766 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 767 clock-names = "xo";
914 768
915 memory-region = <&adsp_mem>; 769 memory-region = <&adsp_mem>;
916 770
917 qcom,qmp = <&aoss_qmp>; <<
918 <<
919 qcom,smem-states = <&adsp_smp2 771 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 772 qcom,smem-state-names = "stop";
921 773
922 status = "disabled"; 774 status = "disabled";
923 775
924 glink-edge { 776 glink-edge {
925 interrupts = <GIC_SPI 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 778 label = "lpass";
927 qcom,remote-pid = <2>; 779 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 780 mboxes = <&apss_shared 8>;
929 781
930 apr { 782 apr {
931 compatible = " 783 compatible = "qcom,apr-v2";
932 qcom,glink-cha 784 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = !! 785 qcom,apr-domain = <APR_DOMAIN_ADSP>;
934 #address-cells 786 #address-cells = <1>;
935 #size-cells = 787 #size-cells = <0>;
936 qcom,intents = 788 qcom,intents = <512 20>;
937 789
938 service@3 { !! 790 apr-service@3 {
939 reg = 791 reg = <APR_SVC_ADSP_CORE>;
940 compat 792 compatible = "qcom,q6core";
941 qcom,p 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 794 };
943 795
944 q6afe: service !! 796 q6afe: apr-service@4 {
945 compat 797 compatible = "qcom,q6afe";
946 reg = 798 reg = <APR_SVC_AFE>;
947 qcom,p 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 800 q6afedai: dais {
949 801 compatible = "qcom,q6afe-dais";
950 802 #address-cells = <1>;
951 803 #size-cells = <0>;
952 804 #sound-dai-cells = <1>;
953 }; 805 };
954 }; 806 };
955 807
956 q6asm: service !! 808 q6asm: apr-service@7 {
957 compat 809 compatible = "qcom,q6asm";
958 reg = 810 reg = <APR_SVC_ASM>;
959 qcom,p 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 812 q6asmdai: dais {
961 813 compatible = "qcom,q6asm-dais";
962 814 #address-cells = <1>;
963 815 #size-cells = <0>;
964 816 #sound-dai-cells = <1>;
965 817 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 818 };
967 }; 819 };
968 820
969 q6adm: service !! 821 q6adm: apr-service@8 {
970 compat 822 compatible = "qcom,q6adm";
971 reg = 823 reg = <APR_SVC_ADM>;
972 qcom,p 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 825 q6routing: routing {
974 826 compatible = "qcom,q6adm-routing";
975 827 #sound-dai-cells = <0>;
976 }; 828 };
977 }; 829 };
978 }; 830 };
979 831
980 fastrpc { 832 fastrpc {
981 compatible = " 833 compatible = "qcom,fastrpc";
982 qcom,glink-cha 834 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 835 label = "adsp";
984 qcom,non-secur <<
985 #address-cells 836 #address-cells = <1>;
986 #size-cells = 837 #size-cells = <0>;
987 838
988 compute-cb@3 { 839 compute-cb@3 {
989 compat 840 compatible = "qcom,fastrpc-compute-cb";
990 reg = 841 reg = <3>;
991 iommus 842 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 843 };
993 844
994 compute-cb@4 { 845 compute-cb@4 {
995 compat 846 compatible = "qcom,fastrpc-compute-cb";
996 reg = 847 reg = <4>;
997 iommus 848 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 849 };
999 }; 850 };
1000 }; 851 };
1001 }; 852 };
1002 853
1003 cdsp_pas: remoteproc-cdsp { 854 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 855 compatible = "qcom,sdm845-cdsp-pas";
1005 856
1006 interrupts-extended = <&intc 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 862 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 863 "handover", "stop-ack";
1013 864
1014 clocks = <&rpmhcc RPMH_CXO_CL 865 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 866 clock-names = "xo";
1016 867
1017 memory-region = <&cdsp_mem>; 868 memory-region = <&cdsp_mem>;
1018 869
1019 qcom,qmp = <&aoss_qmp>; <<
1020 <<
1021 qcom,smem-states = <&cdsp_smp 870 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 871 qcom,smem-state-names = "stop";
1023 872
1024 status = "disabled"; 873 status = "disabled";
1025 874
1026 glink-edge { 875 glink-edge {
1027 interrupts = <GIC_SPI 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 877 label = "turing";
1029 qcom,remote-pid = <5> 878 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 879 mboxes = <&apss_shared 4>;
1031 fastrpc { 880 fastrpc {
1032 compatible = 881 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 882 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 883 label = "cdsp";
1035 qcom,non-secu <<
1036 #address-cell 884 #address-cells = <1>;
1037 #size-cells = 885 #size-cells = <0>;
1038 886
1039 compute-cb@1 887 compute-cb@1 {
1040 compa 888 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 889 reg = <1>;
1042 iommu 890 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 891 };
1044 892
1045 compute-cb@2 893 compute-cb@2 {
1046 compa 894 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 895 reg = <2>;
1048 iommu 896 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 897 };
1050 898
1051 compute-cb@3 899 compute-cb@3 {
1052 compa 900 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 901 reg = <3>;
1054 iommu 902 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 903 };
1056 904
1057 compute-cb@4 905 compute-cb@4 {
1058 compa 906 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 907 reg = <4>;
1060 iommu 908 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 909 };
1062 910
1063 compute-cb@5 911 compute-cb@5 {
1064 compa 912 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 913 reg = <5>;
1066 iommu 914 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 915 };
1068 916
1069 compute-cb@6 917 compute-cb@6 {
1070 compa 918 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 919 reg = <6>;
1072 iommu 920 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 921 };
1074 922
1075 compute-cb@7 923 compute-cb@7 {
1076 compa 924 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 925 reg = <7>;
1078 iommu 926 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 927 };
1080 928
1081 compute-cb@8 929 compute-cb@8 {
1082 compa 930 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 931 reg = <8>;
1084 iommu 932 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 933 };
1086 }; 934 };
1087 }; 935 };
1088 }; 936 };
1089 937
>> 938 tcsr_mutex: hwlock {
>> 939 compatible = "qcom,tcsr-mutex";
>> 940 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 941 #hwlock-cells = <1>;
>> 942 };
>> 943
>> 944 smem {
>> 945 compatible = "qcom,smem";
>> 946 memory-region = <&smem_mem>;
>> 947 hwlocks = <&tcsr_mutex 3>;
>> 948 };
>> 949
1090 smp2p-cdsp { 950 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 951 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 952 qcom,smem = <94>, <432>;
1093 953
1094 interrupts = <GIC_SPI 576 IRQ 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 955
1096 mboxes = <&apss_shared 6>; 956 mboxes = <&apss_shared 6>;
1097 957
1098 qcom,local-pid = <0>; 958 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 959 qcom,remote-pid = <5>;
1100 960
1101 cdsp_smp2p_out: master-kernel 961 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 962 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 963 #qcom,smem-state-cells = <1>;
1104 }; 964 };
1105 965
1106 cdsp_smp2p_in: slave-kernel { 966 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 967 qcom,entry-name = "slave-kernel";
1108 968
1109 interrupt-controller; 969 interrupt-controller;
1110 #interrupt-cells = <2 970 #interrupt-cells = <2>;
1111 }; 971 };
1112 }; 972 };
1113 973
1114 smp2p-lpass { 974 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 975 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 976 qcom,smem = <443>, <429>;
1117 977
1118 interrupts = <GIC_SPI 158 IRQ 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 979
1120 mboxes = <&apss_shared 10>; 980 mboxes = <&apss_shared 10>;
1121 981
1122 qcom,local-pid = <0>; 982 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 983 qcom,remote-pid = <2>;
1124 984
1125 adsp_smp2p_out: master-kernel 985 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 986 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 987 #qcom,smem-state-cells = <1>;
1128 }; 988 };
1129 989
1130 adsp_smp2p_in: slave-kernel { 990 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 991 qcom,entry-name = "slave-kernel";
1132 992
1133 interrupt-controller; 993 interrupt-controller;
1134 #interrupt-cells = <2 994 #interrupt-cells = <2>;
1135 }; 995 };
1136 }; 996 };
1137 997
1138 smp2p-mpss { 998 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 999 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 1000 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 1002 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 1003 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 1004 qcom,remote-pid = <1>;
1145 1005
1146 modem_smp2p_out: master-kerne 1006 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 1007 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 1008 #qcom,smem-state-cells = <1>;
1149 }; 1009 };
1150 1010
1151 modem_smp2p_in: slave-kernel 1011 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 1012 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 1013 interrupt-controller;
1154 #interrupt-cells = <2 1014 #interrupt-cells = <2>;
1155 }; 1015 };
1156 1016
1157 ipa_smp2p_out: ipa-ap-to-mode 1017 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 1018 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 1019 #qcom,smem-state-cells = <1>;
1160 }; 1020 };
1161 1021
1162 ipa_smp2p_in: ipa-modem-to-ap 1022 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1023 qcom,entry-name = "ipa";
1164 interrupt-controller; 1024 interrupt-controller;
1165 #interrupt-cells = <2 1025 #interrupt-cells = <2>;
1166 }; 1026 };
1167 }; 1027 };
1168 1028
1169 smp2p-slpi { 1029 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1030 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1031 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1033 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1034 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1035 qcom,remote-pid = <3>;
1176 1036
1177 slpi_smp2p_out: master-kernel 1037 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1038 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1039 #qcom,smem-state-cells = <1>;
1180 }; 1040 };
1181 1041
1182 slpi_smp2p_in: slave-kernel { 1042 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1043 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1044 interrupt-controller;
1185 #interrupt-cells = <2 1045 #interrupt-cells = <2>;
1186 }; 1046 };
1187 }; 1047 };
1188 1048
>> 1049 psci {
>> 1050 compatible = "arm,psci-1.0";
>> 1051 method = "smc";
>> 1052 };
>> 1053
1189 soc: soc@0 { 1054 soc: soc@0 {
1190 #address-cells = <2>; 1055 #address-cells = <2>;
1191 #size-cells = <2>; 1056 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1057 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1058 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1059 compatible = "simple-bus";
1195 1060
1196 gcc: clock-controller@100000 1061 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1062 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1063 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1064 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1065 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1066 <&sleep_clk>,
1202 <&pcie0_phy> !! 1067 <&pcie0_lane>,
1203 <&pcie1_phy> !! 1068 <&pcie1_lane>;
1204 clock-names = "bi_tcx 1069 clock-names = "bi_tcxo",
1205 "bi_tcx 1070 "bi_tcxo_ao",
1206 "sleep_ 1071 "sleep_clk",
1207 "pcie_0 1072 "pcie_0_pipe_clk",
1208 "pcie_1 1073 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1074 #clock-cells = <1>;
1210 #reset-cells = <1>; 1075 #reset-cells = <1>;
1211 #power-domain-cells = 1076 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 1077 };
1214 1078
1215 qfprom@784000 { 1079 qfprom@784000 {
1216 compatible = "qcom,sd !! 1080 compatible = "qcom,qfprom";
1217 reg = <0 0x00784000 0 1081 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1082 #address-cells = <1>;
1219 #size-cells = <1>; 1083 #size-cells = <1>;
1220 1084
1221 qusb2p_hstx_trim: hst 1085 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1086 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1087 bits = <1 4>;
1224 }; 1088 };
1225 1089
1226 qusb2s_hstx_trim: hst 1090 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1091 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1092 bits = <6 4>;
1229 }; 1093 };
1230 }; 1094 };
1231 1095
1232 rng: rng@793000 { 1096 rng: rng@793000 {
1233 compatible = "qcom,pr 1097 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1098 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1099 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1100 clock-names = "core";
1237 }; 1101 };
1238 1102
1239 gpi_dma0: dma-controller@8000 !! 1103 qup_opp_table: qup-opp-table {
1240 #dma-cells = <3>; !! 1104 compatible = "operating-points-v2";
1241 compatible = "qcom,sd !! 1105
1242 reg = <0 0x00800000 0 !! 1106 opp-50000000 {
1243 interrupts = <GIC_SPI !! 1107 opp-hz = /bits/ 64 <50000000>;
1244 <GIC_SPI !! 1108 required-opps = <&rpmhpd_opp_min_svs>;
1245 <GIC_SPI !! 1109 };
1246 <GIC_SPI !! 1110
1247 <GIC_SPI !! 1111 opp-75000000 {
1248 <GIC_SPI !! 1112 opp-hz = /bits/ 64 <75000000>;
1249 <GIC_SPI !! 1113 required-opps = <&rpmhpd_opp_low_svs>;
1250 <GIC_SPI !! 1114 };
1251 <GIC_SPI !! 1115
1252 <GIC_SPI !! 1116 opp-100000000 {
1253 <GIC_SPI !! 1117 opp-hz = /bits/ 64 <100000000>;
1254 <GIC_SPI !! 1118 required-opps = <&rpmhpd_opp_svs>;
1255 <GIC_SPI !! 1119 };
1256 dma-channels = <13>; !! 1120
1257 dma-channel-mask = <0 !! 1121 opp-128000000 {
1258 iommus = <&apps_smmu !! 1122 opp-hz = /bits/ 64 <128000000>;
1259 status = "disabled"; !! 1123 required-opps = <&rpmhpd_opp_nom>;
>> 1124 };
1260 }; 1125 };
1261 1126
1262 qupv3_id_0: geniqup@8c0000 { 1127 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1128 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1129 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1130 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1131 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1132 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1133 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1134 #address-cells = <2>;
1270 #size-cells = <2>; 1135 #size-cells = <2>;
1271 ranges; 1136 ranges;
1272 interconnects = <&agg 1137 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1138 interconnect-names = "qup-core";
1274 status = "disabled"; 1139 status = "disabled";
1275 1140
1276 i2c0: i2c@880000 { 1141 i2c0: i2c@880000 {
1277 compatible = 1142 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1143 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1144 clock-names = "se";
1280 clocks = <&gc 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1146 pinctrl-names = "default";
1282 pinctrl-0 = < 1147 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1148 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1149 #address-cells = <1>;
1285 #size-cells = 1150 #size-cells = <0>;
1286 power-domains 1151 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1152 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1153 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1154 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1155 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1156 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 1157 status = "disabled";
1296 }; 1158 };
1297 1159
1298 spi0: spi@880000 { 1160 spi0: spi@880000 {
1299 compatible = 1161 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1162 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1163 clock-names = "se";
1302 clocks = <&gc 1164 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1165 pinctrl-names = "default";
1304 pinctrl-0 = < 1166 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1167 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1168 #address-cells = <1>;
1307 #size-cells = 1169 #size-cells = <0>;
1308 interconnects 1170 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1171 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1172 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 1173 status = "disabled";
1315 }; 1174 };
1316 1175
1317 uart0: serial@880000 1176 uart0: serial@880000 {
1318 compatible = 1177 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1178 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1179 clock-names = "se";
1321 clocks = <&gc 1180 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1181 pinctrl-names = "default";
1323 pinctrl-0 = < 1182 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1183 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1184 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1185 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1186 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1187 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1188 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1189 status = "disabled";
1331 }; 1190 };
1332 1191
1333 i2c1: i2c@884000 { 1192 i2c1: i2c@884000 {
1334 compatible = 1193 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1194 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1195 clock-names = "se";
1337 clocks = <&gc 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1197 pinctrl-names = "default";
1339 pinctrl-0 = < 1198 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1199 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1200 #address-cells = <1>;
1342 #size-cells = 1201 #size-cells = <0>;
1343 power-domains 1202 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1203 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1204 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1205 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1206 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 1208 status = "disabled";
1353 }; 1209 };
1354 1210
1355 spi1: spi@884000 { 1211 spi1: spi@884000 {
1356 compatible = 1212 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1213 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1214 clock-names = "se";
1359 clocks = <&gc 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1216 pinctrl-names = "default";
1361 pinctrl-0 = < 1217 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1218 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1219 #address-cells = <1>;
1364 #size-cells = 1220 #size-cells = <0>;
1365 interconnects 1221 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1222 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1223 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 1224 status = "disabled";
1372 }; 1225 };
1373 1226
1374 uart1: serial@884000 1227 uart1: serial@884000 {
1375 compatible = 1228 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1229 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1230 clock-names = "se";
1378 clocks = <&gc 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1232 pinctrl-names = "default";
1380 pinctrl-0 = < 1233 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1234 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1235 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1236 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1237 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1238 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1239 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1240 status = "disabled";
1388 }; 1241 };
1389 1242
1390 i2c2: i2c@888000 { 1243 i2c2: i2c@888000 {
1391 compatible = 1244 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1245 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1246 clock-names = "se";
1394 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1248 pinctrl-names = "default";
1396 pinctrl-0 = < 1249 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1251 #address-cells = <1>;
1399 #size-cells = 1252 #size-cells = <0>;
1400 power-domains 1253 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1254 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1255 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1256 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1257 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1258 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 1259 status = "disabled";
1410 }; 1260 };
1411 1261
1412 spi2: spi@888000 { 1262 spi2: spi@888000 {
1413 compatible = 1263 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1264 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1265 clock-names = "se";
1416 clocks = <&gc 1266 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1267 pinctrl-names = "default";
1418 pinctrl-0 = < 1268 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1269 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1270 #address-cells = <1>;
1421 #size-cells = 1271 #size-cells = <0>;
1422 interconnects 1272 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1273 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1274 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 1275 status = "disabled";
1429 }; 1276 };
1430 1277
1431 uart2: serial@888000 1278 uart2: serial@888000 {
1432 compatible = 1279 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1280 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1281 clock-names = "se";
1435 clocks = <&gc 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1283 pinctrl-names = "default";
1437 pinctrl-0 = < 1284 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1285 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1286 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1287 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1288 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1289 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1290 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1291 status = "disabled";
1445 }; 1292 };
1446 1293
1447 i2c3: i2c@88c000 { 1294 i2c3: i2c@88c000 {
1448 compatible = 1295 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1296 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1297 clock-names = "se";
1451 clocks = <&gc 1298 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1299 pinctrl-names = "default";
1453 pinctrl-0 = < 1300 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1301 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1302 #address-cells = <1>;
1456 #size-cells = 1303 #size-cells = <0>;
1457 power-domains 1304 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1305 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1308 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1309 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 1310 status = "disabled";
1467 }; 1311 };
1468 1312
1469 spi3: spi@88c000 { 1313 spi3: spi@88c000 {
1470 compatible = 1314 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1315 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1316 clock-names = "se";
1473 clocks = <&gc 1317 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1318 pinctrl-names = "default";
1475 pinctrl-0 = < 1319 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1320 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1321 #address-cells = <1>;
1478 #size-cells = 1322 #size-cells = <0>;
1479 interconnects 1323 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1324 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1325 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 1326 status = "disabled";
1486 }; 1327 };
1487 1328
1488 uart3: serial@88c000 1329 uart3: serial@88c000 {
1489 compatible = 1330 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1331 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1332 clock-names = "se";
1492 clocks = <&gc 1333 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1334 pinctrl-names = "default";
1494 pinctrl-0 = < 1335 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1336 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1337 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1338 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1339 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1340 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1341 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1342 status = "disabled";
1502 }; 1343 };
1503 1344
1504 i2c4: i2c@890000 { 1345 i2c4: i2c@890000 {
1505 compatible = 1346 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1347 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1348 clock-names = "se";
1508 clocks = <&gc 1349 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1350 pinctrl-names = "default";
1510 pinctrl-0 = < 1351 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1352 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1353 #address-cells = <1>;
1513 #size-cells = 1354 #size-cells = <0>;
1514 power-domains 1355 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1356 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1357 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1358 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1359 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1360 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 1361 status = "disabled";
1524 }; 1362 };
1525 1363
1526 spi4: spi@890000 { 1364 spi4: spi@890000 {
1527 compatible = 1365 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1366 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1367 clock-names = "se";
1530 clocks = <&gc 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1369 pinctrl-names = "default";
1532 pinctrl-0 = < 1370 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1371 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1372 #address-cells = <1>;
1535 #size-cells = 1373 #size-cells = <0>;
1536 interconnects 1374 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1375 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1376 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 1377 status = "disabled";
1543 }; 1378 };
1544 1379
1545 uart4: serial@890000 1380 uart4: serial@890000 {
1546 compatible = 1381 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1382 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1383 clock-names = "se";
1549 clocks = <&gc 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1385 pinctrl-names = "default";
1551 pinctrl-0 = < 1386 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1387 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1388 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1389 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1390 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1391 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1392 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1393 status = "disabled";
1559 }; 1394 };
1560 1395
1561 i2c5: i2c@894000 { 1396 i2c5: i2c@894000 {
1562 compatible = 1397 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1398 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1399 clock-names = "se";
1565 clocks = <&gc 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1401 pinctrl-names = "default";
1567 pinctrl-0 = < 1402 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1403 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1404 #address-cells = <1>;
1570 #size-cells = 1405 #size-cells = <0>;
1571 power-domains 1406 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1407 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1408 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1409 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1410 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1411 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 1412 status = "disabled";
1581 }; 1413 };
1582 1414
1583 spi5: spi@894000 { 1415 spi5: spi@894000 {
1584 compatible = 1416 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1417 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1418 clock-names = "se";
1587 clocks = <&gc 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1420 pinctrl-names = "default";
1589 pinctrl-0 = < 1421 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1422 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1423 #address-cells = <1>;
1592 #size-cells = 1424 #size-cells = <0>;
1593 interconnects 1425 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1426 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1427 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 1428 status = "disabled";
1600 }; 1429 };
1601 1430
1602 uart5: serial@894000 1431 uart5: serial@894000 {
1603 compatible = 1432 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1433 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1434 clock-names = "se";
1606 clocks = <&gc 1435 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1436 pinctrl-names = "default";
1608 pinctrl-0 = < 1437 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1438 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1439 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1440 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1441 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1442 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1443 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1444 status = "disabled";
1616 }; 1445 };
1617 1446
1618 i2c6: i2c@898000 { 1447 i2c6: i2c@898000 {
1619 compatible = 1448 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1449 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1450 clock-names = "se";
1622 clocks = <&gc 1451 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1452 pinctrl-names = "default";
1624 pinctrl-0 = < 1453 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1454 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1455 #address-cells = <1>;
1627 #size-cells = 1456 #size-cells = <0>;
1628 power-domains 1457 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1458 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1459 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1460 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1461 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1462 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 1463 status = "disabled";
1638 }; 1464 };
1639 1465
1640 spi6: spi@898000 { 1466 spi6: spi@898000 {
1641 compatible = 1467 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1468 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1469 clock-names = "se";
1644 clocks = <&gc 1470 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1471 pinctrl-names = "default";
1646 pinctrl-0 = < 1472 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1473 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1474 #address-cells = <1>;
1649 #size-cells = 1475 #size-cells = <0>;
1650 interconnects 1476 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1477 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1478 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 1479 status = "disabled";
1657 }; 1480 };
1658 1481
1659 uart6: serial@898000 1482 uart6: serial@898000 {
1660 compatible = 1483 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1484 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1485 clock-names = "se";
1663 clocks = <&gc 1486 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1487 pinctrl-names = "default";
1665 pinctrl-0 = < 1488 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1489 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1490 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1491 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1492 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1493 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1494 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1495 status = "disabled";
1673 }; 1496 };
1674 1497
1675 i2c7: i2c@89c000 { 1498 i2c7: i2c@89c000 {
1676 compatible = 1499 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1500 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1501 clock-names = "se";
1679 clocks = <&gc 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1503 pinctrl-names = "default";
1681 pinctrl-0 = < 1504 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1505 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1506 #address-cells = <1>;
1684 #size-cells = 1507 #size-cells = <0>;
1685 power-domains 1508 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1509 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1510 status = "disabled";
1688 }; 1511 };
1689 1512
1690 spi7: spi@89c000 { 1513 spi7: spi@89c000 {
1691 compatible = 1514 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1515 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1516 clock-names = "se";
1694 clocks = <&gc 1517 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1518 pinctrl-names = "default";
1696 pinctrl-0 = < 1519 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1520 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1521 #address-cells = <1>;
1699 #size-cells = 1522 #size-cells = <0>;
1700 interconnects 1523 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1524 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1525 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 1526 status = "disabled";
1707 }; 1527 };
1708 1528
1709 uart7: serial@89c000 1529 uart7: serial@89c000 {
1710 compatible = 1530 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1531 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1532 clock-names = "se";
1713 clocks = <&gc 1533 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1534 pinctrl-names = "default";
1715 pinctrl-0 = < 1535 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1536 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1537 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1538 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1539 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1540 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1541 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1542 status = "disabled";
1723 }; 1543 };
1724 }; 1544 };
1725 1545
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 1546 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1547 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1548 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1549 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1550 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1551 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1552 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1553 #address-cells = <2>;
1757 #size-cells = <2>; 1554 #size-cells = <2>;
1758 ranges; 1555 ranges;
1759 interconnects = <&agg 1556 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1557 interconnect-names = "qup-core";
1761 status = "disabled"; 1558 status = "disabled";
1762 1559
1763 i2c8: i2c@a80000 { 1560 i2c8: i2c@a80000 {
1764 compatible = 1561 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1562 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1563 clock-names = "se";
1767 clocks = <&gc 1564 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1565 pinctrl-names = "default";
1769 pinctrl-0 = < 1566 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1567 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1568 #address-cells = <1>;
1772 #size-cells = 1569 #size-cells = <0>;
1773 power-domains 1570 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1571 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1572 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1573 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1574 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1575 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 1576 status = "disabled";
1783 }; 1577 };
1784 1578
1785 spi8: spi@a80000 { 1579 spi8: spi@a80000 {
1786 compatible = 1580 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1581 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1582 clock-names = "se";
1789 clocks = <&gc 1583 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1584 pinctrl-names = "default";
1791 pinctrl-0 = < 1585 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1586 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1587 #address-cells = <1>;
1794 #size-cells = 1588 #size-cells = <0>;
1795 interconnects 1589 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1590 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1591 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 1592 status = "disabled";
1802 }; 1593 };
1803 1594
1804 uart8: serial@a80000 1595 uart8: serial@a80000 {
1805 compatible = 1596 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1597 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1598 clock-names = "se";
1808 clocks = <&gc 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1600 pinctrl-names = "default";
1810 pinctrl-0 = < 1601 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1602 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1603 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1604 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1605 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1606 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1607 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1608 status = "disabled";
1818 }; 1609 };
1819 1610
1820 i2c9: i2c@a84000 { 1611 i2c9: i2c@a84000 {
1821 compatible = 1612 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1613 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1614 clock-names = "se";
1824 clocks = <&gc 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1616 pinctrl-names = "default";
1826 pinctrl-0 = < 1617 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1618 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1619 #address-cells = <1>;
1829 #size-cells = 1620 #size-cells = <0>;
1830 power-domains 1621 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1622 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1623 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1624 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1625 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1626 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 1627 status = "disabled";
1840 }; 1628 };
1841 1629
1842 spi9: spi@a84000 { 1630 spi9: spi@a84000 {
1843 compatible = 1631 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1632 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1633 clock-names = "se";
1846 clocks = <&gc 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1635 pinctrl-names = "default";
1848 pinctrl-0 = < 1636 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1637 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1638 #address-cells = <1>;
1851 #size-cells = 1639 #size-cells = <0>;
1852 interconnects 1640 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1641 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1642 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 1643 status = "disabled";
1859 }; 1644 };
1860 1645
1861 uart9: serial@a84000 1646 uart9: serial@a84000 {
1862 compatible = 1647 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1648 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1649 clock-names = "se";
1865 clocks = <&gc 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1651 pinctrl-names = "default";
1867 pinctrl-0 = < 1652 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1653 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1654 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1655 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1656 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1657 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1658 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1659 status = "disabled";
1875 }; 1660 };
1876 1661
1877 i2c10: i2c@a88000 { 1662 i2c10: i2c@a88000 {
1878 compatible = 1663 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1664 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1665 clock-names = "se";
1881 clocks = <&gc 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1667 pinctrl-names = "default";
1883 pinctrl-0 = < 1668 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1669 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1670 #address-cells = <1>;
1886 #size-cells = 1671 #size-cells = <0>;
1887 power-domains 1672 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1673 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1674 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1675 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1676 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1677 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 1678 status = "disabled";
1897 }; 1679 };
1898 1680
1899 spi10: spi@a88000 { 1681 spi10: spi@a88000 {
1900 compatible = 1682 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1683 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1684 clock-names = "se";
1903 clocks = <&gc 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1686 pinctrl-names = "default";
1905 pinctrl-0 = < 1687 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1688 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1689 #address-cells = <1>;
1908 #size-cells = 1690 #size-cells = <0>;
1909 interconnects 1691 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1692 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1693 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1694 status = "disabled";
1916 }; 1695 };
1917 1696
1918 uart10: serial@a88000 1697 uart10: serial@a88000 {
1919 compatible = 1698 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1699 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1700 clock-names = "se";
1922 clocks = <&gc 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1702 pinctrl-names = "default";
1924 pinctrl-0 = < 1703 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1704 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1705 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1706 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1707 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1708 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1709 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1710 status = "disabled";
1932 }; 1711 };
1933 1712
1934 i2c11: i2c@a8c000 { 1713 i2c11: i2c@a8c000 {
1935 compatible = 1714 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1715 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1716 clock-names = "se";
1938 clocks = <&gc 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1718 pinctrl-names = "default";
1940 pinctrl-0 = < 1719 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1720 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1721 #address-cells = <1>;
1943 #size-cells = 1722 #size-cells = <0>;
1944 power-domains 1723 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1724 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1725 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1726 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1727 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1728 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1729 status = "disabled";
1954 }; 1730 };
1955 1731
1956 spi11: spi@a8c000 { 1732 spi11: spi@a8c000 {
1957 compatible = 1733 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1734 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1735 clock-names = "se";
1960 clocks = <&gc 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1737 pinctrl-names = "default";
1962 pinctrl-0 = < 1738 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1739 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1740 #address-cells = <1>;
1965 #size-cells = 1741 #size-cells = <0>;
1966 interconnects 1742 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1743 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1744 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1745 status = "disabled";
1973 }; 1746 };
1974 1747
1975 uart11: serial@a8c000 1748 uart11: serial@a8c000 {
1976 compatible = 1749 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1750 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1751 clock-names = "se";
1979 clocks = <&gc 1752 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1753 pinctrl-names = "default";
1981 pinctrl-0 = < 1754 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1755 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1756 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1757 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1758 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1759 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1760 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1761 status = "disabled";
1989 }; 1762 };
1990 1763
1991 i2c12: i2c@a90000 { 1764 i2c12: i2c@a90000 {
1992 compatible = 1765 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1766 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1767 clock-names = "se";
1995 clocks = <&gc 1768 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1769 pinctrl-names = "default";
1997 pinctrl-0 = < 1770 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1771 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1772 #address-cells = <1>;
2000 #size-cells = 1773 #size-cells = <0>;
2001 power-domains 1774 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1775 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 1776 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 1777 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 1778 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 1779 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1780 status = "disabled";
2011 }; 1781 };
2012 1782
2013 spi12: spi@a90000 { 1783 spi12: spi@a90000 {
2014 compatible = 1784 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1785 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1786 clock-names = "se";
2017 clocks = <&gc 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1788 pinctrl-names = "default";
2019 pinctrl-0 = < 1789 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1790 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1791 #address-cells = <1>;
2022 #size-cells = 1792 #size-cells = <0>;
2023 interconnects 1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 1795 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1796 status = "disabled";
2030 }; 1797 };
2031 1798
2032 uart12: serial@a90000 1799 uart12: serial@a90000 {
2033 compatible = 1800 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1801 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1802 clock-names = "se";
2036 clocks = <&gc 1803 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1804 pinctrl-names = "default";
2038 pinctrl-0 = < 1805 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1806 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1807 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1808 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 1809 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 1810 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 1811 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 1812 status = "disabled";
2046 }; 1813 };
2047 1814
2048 i2c13: i2c@a94000 { 1815 i2c13: i2c@a94000 {
2049 compatible = 1816 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1817 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1818 clock-names = "se";
2052 clocks = <&gc 1819 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1820 pinctrl-names = "default";
2054 pinctrl-0 = < 1821 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1822 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1823 #address-cells = <1>;
2057 #size-cells = 1824 #size-cells = <0>;
2058 power-domains 1825 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1826 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 1827 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 1828 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 1829 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 1830 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1831 status = "disabled";
2068 }; 1832 };
2069 1833
2070 spi13: spi@a94000 { 1834 spi13: spi@a94000 {
2071 compatible = 1835 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1836 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1837 clock-names = "se";
2074 clocks = <&gc 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1839 pinctrl-names = "default";
2076 pinctrl-0 = < 1840 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1841 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1842 #address-cells = <1>;
2079 #size-cells = 1843 #size-cells = <0>;
2080 interconnects 1844 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 1845 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 1846 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1847 status = "disabled";
2087 }; 1848 };
2088 1849
2089 uart13: serial@a94000 1850 uart13: serial@a94000 {
2090 compatible = 1851 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1852 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1853 clock-names = "se";
2093 clocks = <&gc 1854 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1855 pinctrl-names = "default";
2095 pinctrl-0 = < 1856 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1857 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 1858 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 1859 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 1860 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 1861 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 1862 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 1863 status = "disabled";
2103 }; 1864 };
2104 1865
2105 i2c14: i2c@a98000 { 1866 i2c14: i2c@a98000 {
2106 compatible = 1867 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1868 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1869 clock-names = "se";
2109 clocks = <&gc 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1871 pinctrl-names = "default";
2111 pinctrl-0 = < 1872 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1873 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1874 #address-cells = <1>;
2114 #size-cells = 1875 #size-cells = <0>;
2115 power-domains 1876 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 1877 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 1878 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 1879 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 1880 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 1881 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1882 status = "disabled";
2125 }; 1883 };
2126 1884
2127 spi14: spi@a98000 { 1885 spi14: spi@a98000 {
2128 compatible = 1886 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1887 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1888 clock-names = "se";
2131 clocks = <&gc 1889 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1890 pinctrl-names = "default";
2133 pinctrl-0 = < 1891 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1892 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1893 #address-cells = <1>;
2136 #size-cells = 1894 #size-cells = <0>;
2137 interconnects 1895 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 1896 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 1897 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1898 status = "disabled";
2144 }; 1899 };
2145 1900
2146 uart14: serial@a98000 1901 uart14: serial@a98000 {
2147 compatible = 1902 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1903 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1904 clock-names = "se";
2150 clocks = <&gc 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1906 pinctrl-names = "default";
2152 pinctrl-0 = < 1907 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1908 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 1909 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 1910 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 1911 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 1912 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 1913 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 1914 status = "disabled";
2160 }; 1915 };
2161 1916
2162 i2c15: i2c@a9c000 { 1917 i2c15: i2c@a9c000 {
2163 compatible = 1918 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1919 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1920 clock-names = "se";
2166 clocks = <&gc 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1922 pinctrl-names = "default";
2168 pinctrl-0 = < 1923 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1924 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1925 #address-cells = <1>;
2171 #size-cells = 1926 #size-cells = <0>;
2172 power-domains 1927 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 1928 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 1929 status = "disabled";
2175 interconnects 1930 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 1931 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 1932 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 1933 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1934 };
2183 1935
2184 spi15: spi@a9c000 { 1936 spi15: spi@a9c000 {
2185 compatible = 1937 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1938 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1939 clock-names = "se";
2188 clocks = <&gc 1940 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1941 pinctrl-names = "default";
2190 pinctrl-0 = < 1942 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1943 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1944 #address-cells = <1>;
2193 #size-cells = 1945 #size-cells = <0>;
2194 interconnects 1946 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 1947 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 1948 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1949 status = "disabled";
2201 }; 1950 };
2202 1951
2203 uart15: serial@a9c000 1952 uart15: serial@a9c000 {
2204 compatible = 1953 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1954 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1955 clock-names = "se";
2207 clocks = <&gc 1956 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1957 pinctrl-names = "default";
2209 pinctrl-0 = < 1958 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1959 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 1960 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 1961 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 1962 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 1963 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 1964 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 1965 status = "disabled";
2217 }; 1966 };
2218 }; 1967 };
2219 1968
2220 llcc: system-cache-controller !! 1969 system-cache-controller@1100000 {
2221 compatible = "qcom,sd 1970 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 1971 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 1972 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 1973 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 1974 };
2229 1975
2230 dma@10a2000 { !! 1976 pcie0: pci@1c00000 {
2231 compatible = "qcom,sd !! 1977 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 1978 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 1979 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 1980 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 1981 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 1982 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 1983 device_type = "pci";
2319 linux,pci-domain = <0 1984 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 1985 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 1986 num-lanes = <1>;
2322 1987
2323 #address-cells = <3>; 1988 #address-cells = <3>;
2324 #size-cells = <2>; 1989 #size-cells = <2>;
2325 1990
2326 ranges = <0x01000000 !! 1991 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327 <0x02000000 !! 1992 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328 1993
2329 interrupts = <GIC_SPI 1994 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 1995 interrupt-names = "msi";
2331 #interrupt-cells = <1 1996 #interrupt-cells = <1>;
2332 interrupt-map-mask = 1997 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 !! 1998 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 !! 1999 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 !! 2000 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 !! 2001 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2002
2338 clocks = <&gcc GCC_PC 2003 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2004 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2005 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2006 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2007 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2008 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2009 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2010 clock-names = "pipe",
2346 "aux", 2011 "aux",
2347 "cfg", 2012 "cfg",
2348 "bus_ma 2013 "bus_master",
2349 "bus_sl 2014 "bus_slave",
2350 "slave_ 2015 "slave_q2a",
2351 "tbu"; 2016 "tbu";
2352 2017
>> 2018 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 2019 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2020 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2021 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2022 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2023 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2024 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2025 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2026 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2027 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2028 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2029 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2030 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2031 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2032 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2033 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2034 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2035
2370 resets = <&gcc GCC_PC 2036 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2037 reset-names = "pci";
2372 2038
2373 power-domains = <&gcc 2039 power-domains = <&gcc PCIE_0_GDSC>;
2374 2040
2375 phys = <&pcie0_phy>; !! 2041 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2042 phy-names = "pciephy";
2377 2043
2378 status = "disabled"; 2044 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2045 };
2390 2046
2391 pcie0_phy: phy@1c06000 { 2047 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2048 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2049 reg = <0 0x01c06000 0 0x18c>;
>> 2050 #address-cells = <2>;
>> 2051 #size-cells = <2>;
>> 2052 ranges;
2394 clocks = <&gcc GCC_PC 2053 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2054 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2055 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2056 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2057 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2058
2410 resets = <&gcc GCC_PC 2059 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2060 reset-names = "phy";
2412 2061
2413 assigned-clocks = <&g 2062 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2063 assigned-clock-rates = <100000000>;
2415 2064
2416 status = "disabled"; 2065 status = "disabled";
>> 2066
>> 2067 pcie0_lane: lanes@1c06200 {
>> 2068 reg = <0 0x01c06200 0 0x128>,
>> 2069 <0 0x01c06400 0 0x1fc>,
>> 2070 <0 0x01c06800 0 0x218>,
>> 2071 <0 0x01c06600 0 0x70>;
>> 2072 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2073 clock-names = "pipe0";
>> 2074
>> 2075 #clock-cells = <0>;
>> 2076 #phy-cells = <0>;
>> 2077 clock-output-names = "pcie_0_pipe_clk";
>> 2078 };
2417 }; 2079 };
2418 2080
2419 pcie1: pcie@1c08000 { !! 2081 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc !! 2082 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2421 reg = <0 0x01c08000 0 2083 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2084 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2085 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 2086 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 2087 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 2088 device_type = "pci";
2428 linux,pci-domain = <1 2089 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2090 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2091 num-lanes = <1>;
2431 2092
2432 #address-cells = <3>; 2093 #address-cells = <3>;
2433 #size-cells = <2>; 2094 #size-cells = <2>;
2434 2095
2435 ranges = <0x01000000 !! 2096 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2097 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2098
2438 interrupts = <GIC_SPI 2099 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2100 interrupt-names = "msi";
2440 #interrupt-cells = <1 2101 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2102 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 !! 2103 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 !! 2104 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 !! 2105 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 !! 2106 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2107
2447 clocks = <&gcc GCC_PC 2108 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2109 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2110 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2111 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2112 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2113 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2114 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2115 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2116 clock-names = "pipe",
2456 "aux", 2117 "aux",
2457 "cfg", 2118 "cfg",
2458 "bus_ma 2119 "bus_master",
2459 "bus_sl 2120 "bus_slave",
2460 "slave_ 2121 "slave_q2a",
2461 "ref", 2122 "ref",
2462 "tbu"; 2123 "tbu";
2463 2124
2464 assigned-clocks = <&g 2125 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2126 assigned-clock-rates = <19200000>;
2466 2127
>> 2128 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 2129 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2130 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2131 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2132 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2133 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2134 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2135 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2136 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2137 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2138 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2139 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2140 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2141 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2142 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2143 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2144 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2145
2484 resets = <&gcc GCC_PC 2146 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2147 reset-names = "pci";
2486 2148
2487 power-domains = <&gcc 2149 power-domains = <&gcc PCIE_1_GDSC>;
2488 2150
2489 phys = <&pcie1_phy>; !! 2151 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2152 phy-names = "pciephy";
2491 2153
2492 status = "disabled"; 2154 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2155 };
2504 2156
2505 pcie1_phy: phy@1c0a000 { 2157 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2158 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2159 reg = <0 0x01c0a000 0 0x800>;
>> 2160 #address-cells = <2>;
>> 2161 #size-cells = <2>;
>> 2162 ranges;
2508 clocks = <&gcc GCC_PC 2163 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2164 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2165 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2166 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2167 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2168
2524 resets = <&gcc GCC_PC 2169 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2170 reset-names = "phy";
2526 2171
2527 assigned-clocks = <&g 2172 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2173 assigned-clock-rates = <100000000>;
2529 2174
2530 status = "disabled"; 2175 status = "disabled";
>> 2176
>> 2177 pcie1_lane: lanes@1c06200 {
>> 2178 reg = <0 0x01c0a800 0 0x800>,
>> 2179 <0 0x01c0a800 0 0x800>,
>> 2180 <0 0x01c0b800 0 0x400>;
>> 2181 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2182 clock-names = "pipe0";
>> 2183
>> 2184 #clock-cells = <0>;
>> 2185 #phy-cells = <0>;
>> 2186 clock-output-names = "pcie_1_pipe_clk";
>> 2187 };
2531 }; 2188 };
2532 2189
2533 mem_noc: interconnect@1380000 2190 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2191 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2192 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2193 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2194 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2195 };
2539 2196
2540 dc_noc: interconnect@14e0000 2197 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2198 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2199 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2200 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2201 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2202 };
2546 2203
2547 config_noc: interconnect@1500 2204 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2205 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2206 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2207 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2208 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2209 };
2553 2210
2554 system_noc: interconnect@1620 2211 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2212 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2213 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2214 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2215 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2216 };
2560 2217
2561 aggre1_noc: interconnect@16e0 2218 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2219 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2220 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2221 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2222 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2223 };
2567 2224
2568 aggre2_noc: interconnect@1700 2225 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2226 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2227 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2228 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2229 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2230 };
2574 2231
2575 mmss_noc: interconnect@174000 2232 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2233 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2234 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2235 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2236 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2237 };
2581 2238
2582 ufs_mem_hc: ufshc@1d84000 { 2239 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2240 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2241 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2242 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2243 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2244 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2245 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2246 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2247 phy-names = "ufsphy";
2591 lanes-per-direction = 2248 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2249 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2250 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2251 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2252 reset-names = "rst";
2596 2253
2597 iommus = <&apps_smmu 2254 iommus = <&apps_smmu 0x100 0xf>;
2598 2255
2599 clock-names = 2256 clock-names =
2600 "core_clk", 2257 "core_clk",
2601 "bus_aggr_clk 2258 "bus_aggr_clk",
2602 "iface_clk", 2259 "iface_clk",
2603 "core_clk_uni 2260 "core_clk_unipro",
2604 "ref_clk", 2261 "ref_clk",
2605 "tx_lane0_syn 2262 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2263 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2264 "rx_lane1_sync_clk",
2608 "ice_core_clk 2265 "ice_core_clk";
2609 clocks = 2266 clocks =
2610 <&gcc GCC_UFS 2267 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2268 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2269 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2270 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2271 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2272 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2273 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2274 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2275 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2276 freq-table-hz =
2620 operating-points-v2 = !! 2277 <50000000 200000000>,
2621 !! 2278 <0 0>,
2622 interconnects = <&agg !! 2279 <0 0>,
2623 <&gla !! 2280 <37500000 150000000>,
2624 interconnect-names = !! 2281 <0 0>,
>> 2282 <0 0>,
>> 2283 <0 0>,
>> 2284 <0 0>,
>> 2285 <0 300000000>;
2625 2286
2626 status = "disabled"; 2287 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2288 };
2658 2289
2659 ufs_mem_phy: phy@1d87000 { 2290 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2291 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2292 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2293 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2294 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2295 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2296 clock-names = "ref",
2667 "ref_au !! 2297 "ref_aux";
2668 "qref"; !! 2298 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2299 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2300
2672 resets = <&ufs_mem_hc 2301 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2302 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2303 status = "disabled";
>> 2304
>> 2305 ufs_mem_phy_lanes: lanes@1d87400 {
>> 2306 reg = <0 0x01d87400 0 0x108>,
>> 2307 <0 0x01d87600 0 0x1e0>,
>> 2308 <0 0x01d87c00 0 0x1dc>,
>> 2309 <0 0x01d87800 0 0x108>,
>> 2310 <0 0x01d87a00 0 0x1e0>;
>> 2311 #phy-cells = <0>;
>> 2312 };
2677 }; 2313 };
2678 2314
2679 cryptobam: dma-controller@1dc !! 2315 cryptobam: dma@1dc4000 {
2680 compatible = "qcom,ba !! 2316 compatible = "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2317 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2318 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2319 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2320 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2321 #dma-cells = <1>;
2686 qcom,ee = <0>; 2322 qcom,ee = <0>;
2687 qcom,controlled-remot !! 2323 qcom,controlled-remotely = <1>;
2688 iommus = <&apps_smmu 2324 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2325 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2326 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2327 <&apps_smmu 0x716 0x1>;
2692 }; 2328 };
2693 2329
2694 crypto: crypto@1dfa000 { 2330 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2331 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2332 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2333 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2334 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2335 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2336 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2337 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2338 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2339 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2340 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2341 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2342 <&apps_smmu 0x716 0x1>;
2707 }; 2343 };
2708 2344
2709 ipa: ipa@1e40000 { 2345 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2346 compatible = "qcom,sdm845-ipa";
2711 2347
2712 iommus = <&apps_smmu 2348 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2349 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 !! 2350 reg = <0 0x1e40000 0 0x7000>,
2715 <0 0x01e47000 0 !! 2351 <0 0x1e47000 0 0x2000>,
2716 <0 0x01e04000 0 !! 2352 <0 0x1e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2353 reg-names = "ipa-reg",
2718 "ipa-shar 2354 "ipa-shared",
2719 "gsi"; 2355 "gsi";
2720 2356
2721 interrupts-extended = 2357 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2358 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2359 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2360 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2361 interrupt-names = "ipa",
2726 "gs 2362 "gsi",
2727 "ip 2363 "ipa-clock-query",
2728 "ip 2364 "ipa-setup-ready";
2729 2365
2730 clocks = <&rpmhcc RPM 2366 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2367 clock-names = "core";
2732 2368
2733 interconnects = <&agg 2369 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2370 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2371 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2372 interconnect-names = "memory",
2737 2373 "imem",
2738 2374 "config";
2739 2375
2740 qcom,smem-states = <& 2376 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2377 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2378 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2379 "ipa-clock-enabled";
2744 2380
2745 status = "disabled"; 2381 status = "disabled";
2746 }; 2382 };
2747 2383
2748 tcsr_mutex: hwlock@1f40000 { !! 2384 tcsr_mutex_regs: syscon@1f40000 {
2749 compatible = "qcom,tc !! 2385 compatible = "syscon";
2750 reg = <0 0x01f40000 0 !! 2386 reg = <0 0x01f40000 0 0x40000>;
2751 #hwlock-cells = <1>; <<
2752 }; <<
2753 <<
2754 tcsr_regs_1: syscon@1f60000 { <<
2755 compatible = "qcom,sd <<
2756 reg = <0 0x01f60000 0 <<
2757 }; 2387 };
2758 2388
2759 tlmm: pinctrl@3400000 { 2389 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2390 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2391 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2392 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2393 gpio-controller;
2764 #gpio-cells = <2>; 2394 #gpio-cells = <2>;
2765 interrupt-controller; 2395 interrupt-controller;
2766 #interrupt-cells = <2 2396 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2397 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2398 wakeup-parent = <&pdc_intc>;
2769 2399
2770 cci0_default: cci0-de !! 2400 cci0_default: cci0-default {
2771 /* SDA, SCL * 2401 /* SDA, SCL */
2772 pins = "gpio1 2402 pins = "gpio17", "gpio18";
2773 function = "c 2403 function = "cci_i2c";
2774 2404
2775 bias-pull-up; 2405 bias-pull-up;
2776 drive-strengt 2406 drive-strength = <2>; /* 2 mA */
2777 }; 2407 };
2778 2408
2779 cci0_sleep: cci0-slee !! 2409 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2410 /* SDA, SCL */
2781 pins = "gpio1 2411 pins = "gpio17", "gpio18";
2782 function = "c 2412 function = "cci_i2c";
2783 2413
2784 drive-strengt 2414 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2415 bias-pull-down;
2786 }; 2416 };
2787 2417
2788 cci1_default: cci1-de !! 2418 cci1_default: cci1-default {
2789 /* SDA, SCL * 2419 /* SDA, SCL */
2790 pins = "gpio1 2420 pins = "gpio19", "gpio20";
2791 function = "c 2421 function = "cci_i2c";
2792 2422
2793 bias-pull-up; 2423 bias-pull-up;
2794 drive-strengt 2424 drive-strength = <2>; /* 2 mA */
2795 }; 2425 };
2796 2426
2797 cci1_sleep: cci1-slee !! 2427 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2428 /* SDA, SCL */
2799 pins = "gpio1 2429 pins = "gpio19", "gpio20";
2800 function = "c 2430 function = "cci_i2c";
2801 2431
2802 drive-strengt 2432 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2433 bias-pull-down;
2804 }; 2434 };
2805 2435
2806 qspi_clk: qspi-clk-st !! 2436 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2437 pinmux {
2808 function = "q !! 2438 pins = "gpio95";
2809 }; !! 2439 function = "qspi_clk";
2810 !! 2440 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; 2441 };
2820 2442
2821 qspi_data0: qspi-data !! 2443 qspi_cs0: qspi-cs0 {
2822 pins = "gpio9 !! 2444 pinmux {
2823 function = "q !! 2445 pins = "gpio90";
>> 2446 function = "qspi_cs";
>> 2447 };
2824 }; 2448 };
2825 2449
2826 qspi_data1: qspi-data !! 2450 qspi_cs1: qspi-cs1 {
2827 pins = "gpio9 !! 2451 pinmux {
2828 function = "q !! 2452 pins = "gpio89";
>> 2453 function = "qspi_cs";
>> 2454 };
2829 }; 2455 };
2830 2456
2831 qspi_data23: qspi-dat !! 2457 qspi_data01: qspi-data01 {
2832 pins = "gpio9 !! 2458 pinmux-data {
2833 function = "q !! 2459 pins = "gpio91", "gpio92";
>> 2460 function = "qspi_data";
>> 2461 };
2834 }; 2462 };
2835 2463
2836 qup_i2c0_default: qup !! 2464 qspi_data12: qspi-data12 {
2837 pins = "gpio0 !! 2465 pinmux-data {
2838 function = "q !! 2466 pins = "gpio93", "gpio94";
>> 2467 function = "qspi_data";
>> 2468 };
2839 }; 2469 };
2840 2470
2841 qup_i2c1_default: qup !! 2471 qup_i2c0_default: qup-i2c0-default {
2842 pins = "gpio1 !! 2472 pinmux {
2843 function = "q !! 2473 pins = "gpio0", "gpio1";
>> 2474 function = "qup0";
>> 2475 };
2844 }; 2476 };
2845 2477
2846 qup_i2c2_default: qup !! 2478 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio2 !! 2479 pinmux {
2848 function = "q !! 2480 pins = "gpio17", "gpio18";
>> 2481 function = "qup1";
>> 2482 };
2849 }; 2483 };
2850 2484
2851 qup_i2c3_default: qup !! 2485 qup_i2c2_default: qup-i2c2-default {
2852 pins = "gpio4 !! 2486 pinmux {
2853 function = "q !! 2487 pins = "gpio27", "gpio28";
>> 2488 function = "qup2";
>> 2489 };
2854 }; 2490 };
2855 2491
2856 qup_i2c4_default: qup !! 2492 qup_i2c3_default: qup-i2c3-default {
2857 pins = "gpio8 !! 2493 pinmux {
2858 function = "q !! 2494 pins = "gpio41", "gpio42";
>> 2495 function = "qup3";
>> 2496 };
2859 }; 2497 };
2860 2498
2861 qup_i2c5_default: qup !! 2499 qup_i2c4_default: qup-i2c4-default {
2862 pins = "gpio8 !! 2500 pinmux {
2863 function = "q !! 2501 pins = "gpio89", "gpio90";
>> 2502 function = "qup4";
>> 2503 };
2864 }; 2504 };
2865 2505
2866 qup_i2c6_default: qup !! 2506 qup_i2c5_default: qup-i2c5-default {
2867 pins = "gpio4 !! 2507 pinmux {
2868 function = "q !! 2508 pins = "gpio85", "gpio86";
>> 2509 function = "qup5";
>> 2510 };
2869 }; 2511 };
2870 2512
2871 qup_i2c7_default: qup !! 2513 qup_i2c6_default: qup-i2c6-default {
2872 pins = "gpio9 !! 2514 pinmux {
2873 function = "q !! 2515 pins = "gpio45", "gpio46";
>> 2516 function = "qup6";
>> 2517 };
2874 }; 2518 };
2875 2519
2876 qup_i2c8_default: qup !! 2520 qup_i2c7_default: qup-i2c7-default {
2877 pins = "gpio6 !! 2521 pinmux {
2878 function = "q !! 2522 pins = "gpio93", "gpio94";
>> 2523 function = "qup7";
>> 2524 };
2879 }; 2525 };
2880 2526
2881 qup_i2c9_default: qup !! 2527 qup_i2c8_default: qup-i2c8-default {
2882 pins = "gpio6 !! 2528 pinmux {
2883 function = "q !! 2529 pins = "gpio65", "gpio66";
>> 2530 function = "qup8";
>> 2531 };
2884 }; 2532 };
2885 2533
2886 qup_i2c10_default: qu !! 2534 qup_i2c9_default: qup-i2c9-default {
2887 pins = "gpio5 !! 2535 pinmux {
2888 function = "q !! 2536 pins = "gpio6", "gpio7";
>> 2537 function = "qup9";
>> 2538 };
2889 }; 2539 };
2890 2540
2891 qup_i2c11_default: qu !! 2541 qup_i2c10_default: qup-i2c10-default {
2892 pins = "gpio3 !! 2542 pinmux {
2893 function = "q !! 2543 pins = "gpio55", "gpio56";
>> 2544 function = "qup10";
>> 2545 };
2894 }; 2546 };
2895 2547
2896 qup_i2c12_default: qu !! 2548 qup_i2c11_default: qup-i2c11-default {
2897 pins = "gpio4 !! 2549 pinmux {
2898 function = "q !! 2550 pins = "gpio31", "gpio32";
>> 2551 function = "qup11";
>> 2552 };
2899 }; 2553 };
2900 2554
2901 qup_i2c13_default: qu !! 2555 qup_i2c12_default: qup-i2c12-default {
2902 pins = "gpio1 !! 2556 pinmux {
2903 function = "q !! 2557 pins = "gpio49", "gpio50";
>> 2558 function = "qup12";
>> 2559 };
2904 }; 2560 };
2905 2561
2906 qup_i2c14_default: qu !! 2562 qup_i2c13_default: qup-i2c13-default {
2907 pins = "gpio3 !! 2563 pinmux {
2908 function = "q !! 2564 pins = "gpio105", "gpio106";
>> 2565 function = "qup13";
>> 2566 };
2909 }; 2567 };
2910 2568
2911 qup_i2c15_default: qu !! 2569 qup_i2c14_default: qup-i2c14-default {
2912 pins = "gpio8 !! 2570 pinmux {
2913 function = "q !! 2571 pins = "gpio33", "gpio34";
>> 2572 function = "qup14";
>> 2573 };
2914 }; 2574 };
2915 2575
2916 qup_spi0_default: qup !! 2576 qup_i2c15_default: qup-i2c15-default {
2917 pins = "gpio0 !! 2577 pinmux {
2918 function = "q !! 2578 pins = "gpio81", "gpio82";
>> 2579 function = "qup15";
>> 2580 };
2919 }; 2581 };
2920 2582
2921 qup_spi1_default: qup !! 2583 qup_spi0_default: qup-spi0-default {
2922 pins = "gpio1 !! 2584 pinmux {
2923 function = "q !! 2585 pins = "gpio0", "gpio1",
>> 2586 "gpio2", "gpio3";
>> 2587 function = "qup0";
>> 2588 };
2924 }; 2589 };
2925 2590
2926 qup_spi2_default: qup !! 2591 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2592 pinmux {
2928 function = "q !! 2593 pins = "gpio17", "gpio18",
>> 2594 "gpio19", "gpio20";
>> 2595 function = "qup1";
>> 2596 };
2929 }; 2597 };
2930 2598
2931 qup_spi3_default: qup !! 2599 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2600 pinmux {
2933 function = "q !! 2601 pins = "gpio27", "gpio28",
>> 2602 "gpio29", "gpio30";
>> 2603 function = "qup2";
>> 2604 };
2934 }; 2605 };
2935 2606
2936 qup_spi4_default: qup !! 2607 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2608 pinmux {
2938 function = "q !! 2609 pins = "gpio41", "gpio42",
>> 2610 "gpio43", "gpio44";
>> 2611 function = "qup3";
>> 2612 };
2939 }; 2613 };
2940 2614
2941 qup_spi5_default: qup !! 2615 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2616 pinmux {
2943 function = "q !! 2617 pins = "gpio89", "gpio90",
>> 2618 "gpio91", "gpio92";
>> 2619 function = "qup4";
>> 2620 };
2944 }; 2621 };
2945 2622
2946 qup_spi6_default: qup !! 2623 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2624 pinmux {
2948 function = "q !! 2625 pins = "gpio85", "gpio86",
>> 2626 "gpio87", "gpio88";
>> 2627 function = "qup5";
>> 2628 };
2949 }; 2629 };
2950 2630
2951 qup_spi7_default: qup !! 2631 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2632 pinmux {
2953 function = "q !! 2633 pins = "gpio45", "gpio46",
>> 2634 "gpio47", "gpio48";
>> 2635 function = "qup6";
>> 2636 };
2954 }; 2637 };
2955 2638
2956 qup_spi8_default: qup !! 2639 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2640 pinmux {
2958 function = "q !! 2641 pins = "gpio93", "gpio94",
>> 2642 "gpio95", "gpio96";
>> 2643 function = "qup7";
>> 2644 };
2959 }; 2645 };
2960 2646
2961 qup_spi9_default: qup !! 2647 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2648 pinmux {
2963 function = "q !! 2649 pins = "gpio65", "gpio66",
>> 2650 "gpio67", "gpio68";
>> 2651 function = "qup8";
>> 2652 };
2964 }; 2653 };
2965 2654
2966 qup_spi10_default: qu !! 2655 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2656 pinmux {
2968 function = "q !! 2657 pins = "gpio6", "gpio7",
>> 2658 "gpio4", "gpio5";
>> 2659 function = "qup9";
>> 2660 };
2969 }; 2661 };
2970 2662
2971 qup_spi11_default: qu !! 2663 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2664 pinmux {
2973 function = "q !! 2665 pins = "gpio55", "gpio56",
>> 2666 "gpio53", "gpio54";
>> 2667 function = "qup10";
>> 2668 };
2974 }; 2669 };
2975 2670
2976 qup_spi12_default: qu !! 2671 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2672 pinmux {
2978 function = "q !! 2673 pins = "gpio31", "gpio32",
>> 2674 "gpio33", "gpio34";
>> 2675 function = "qup11";
>> 2676 };
2979 }; 2677 };
2980 2678
2981 qup_spi13_default: qu !! 2679 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2680 pinmux {
2983 function = "q !! 2681 pins = "gpio49", "gpio50",
>> 2682 "gpio51", "gpio52";
>> 2683 function = "qup12";
>> 2684 };
2984 }; 2685 };
2985 2686
2986 qup_spi14_default: qu !! 2687 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2688 pinmux {
2988 function = "q !! 2689 pins = "gpio105", "gpio106",
>> 2690 "gpio107", "gpio108";
>> 2691 function = "qup13";
>> 2692 };
2989 }; 2693 };
2990 2694
2991 qup_spi15_default: qu !! 2695 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2696 pinmux {
2993 function = "q !! 2697 pins = "gpio33", "gpio34",
>> 2698 "gpio31", "gpio32";
>> 2699 function = "qup14";
>> 2700 };
2994 }; 2701 };
2995 2702
2996 qup_uart0_default: qu !! 2703 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2704 pinmux {
2998 pins !! 2705 pins = "gpio81", "gpio82",
2999 funct !! 2706 "gpio83", "gpio84";
>> 2707 function = "qup15";
3000 }; 2708 };
>> 2709 };
3001 2710
3002 qup_uart0_rx: !! 2711 qup_uart0_default: qup-uart0-default {
3003 pins !! 2712 pinmux {
>> 2713 pins = "gpio2", "gpio3";
3004 funct 2714 function = "qup0";
3005 }; 2715 };
3006 }; 2716 };
3007 2717
3008 qup_uart1_default: qu !! 2718 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2719 pinmux {
3010 pins !! 2720 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2721 function = "qup1";
3017 }; 2722 };
3018 }; 2723 };
3019 2724
3020 qup_uart2_default: qu !! 2725 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2726 pinmux {
3022 pins !! 2727 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2728 function = "qup2";
3029 }; 2729 };
3030 }; 2730 };
3031 2731
3032 qup_uart3_default: qu !! 2732 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2733 pinmux {
3034 pins !! 2734 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2735 function = "qup3";
3041 }; 2736 };
3042 }; 2737 };
3043 2738
3044 qup_uart3_4pin: qup-u !! 2739 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2740 pinmux {
3046 pins !! 2741 pins = "gpio91", "gpio92";
3047 funct !! 2742 function = "qup4";
3048 }; 2743 };
>> 2744 };
3049 2745
3050 qup_uart3_4pi !! 2746 qup_uart5_default: qup-uart5-default {
3051 pins !! 2747 pinmux {
3052 funct !! 2748 pins = "gpio87", "gpio88";
>> 2749 function = "qup5";
3053 }; 2750 };
>> 2751 };
3054 2752
3055 qup_uart3_4pi !! 2753 qup_uart6_default: qup-uart6-default {
3056 pins !! 2754 pinmux {
3057 funct !! 2755 pins = "gpio47", "gpio48";
>> 2756 function = "qup6";
3058 }; 2757 };
3059 }; 2758 };
3060 2759
3061 qup_uart4_default: qu !! 2760 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 2761 pinmux {
3063 pins !! 2762 pins = "gpio95", "gpio96";
3064 funct !! 2763 function = "qup7";
3065 }; 2764 };
>> 2765 };
3066 2766
3067 qup_uart4_rx: !! 2767 qup_uart8_default: qup-uart8-default {
3068 pins !! 2768 pinmux {
3069 funct !! 2769 pins = "gpio67", "gpio68";
>> 2770 function = "qup8";
3070 }; 2771 };
3071 }; 2772 };
3072 2773
3073 qup_uart5_default: qu !! 2774 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 2775 pinmux {
3075 pins !! 2776 pins = "gpio4", "gpio5";
3076 funct !! 2777 function = "qup9";
3077 }; 2778 };
>> 2779 };
3078 2780
3079 qup_uart5_rx: !! 2781 qup_uart10_default: qup-uart10-default {
3080 pins !! 2782 pinmux {
3081 funct !! 2783 pins = "gpio53", "gpio54";
>> 2784 function = "qup10";
3082 }; 2785 };
3083 }; 2786 };
3084 2787
3085 qup_uart6_default: qu !! 2788 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 2789 pinmux {
3087 pins !! 2790 pins = "gpio33", "gpio34";
3088 funct !! 2791 function = "qup11";
3089 }; 2792 };
>> 2793 };
3090 2794
3091 qup_uart6_rx: !! 2795 qup_uart12_default: qup-uart12-default {
3092 pins !! 2796 pinmux {
3093 funct !! 2797 pins = "gpio51", "gpio52";
>> 2798 function = "qup12";
3094 }; 2799 };
3095 }; 2800 };
3096 2801
3097 qup_uart6_4pin: qup-u !! 2802 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 2803 pinmux {
3099 pins !! 2804 pins = "gpio107", "gpio108";
3100 funct !! 2805 function = "qup13";
3101 bias- <<
3102 }; 2806 };
>> 2807 };
3103 2808
3104 qup_uart6_4pi !! 2809 qup_uart14_default: qup-uart14-default {
3105 pins !! 2810 pinmux {
3106 funct !! 2811 pins = "gpio31", "gpio32";
3107 drive !! 2812 function = "qup14";
3108 bias- <<
3109 }; 2813 };
>> 2814 };
3110 2815
3111 qup_uart6_4pi !! 2816 qup_uart15_default: qup-uart15-default {
3112 pins !! 2817 pinmux {
3113 funct !! 2818 pins = "gpio83", "gpio84";
3114 bias- !! 2819 function = "qup15";
3115 }; 2820 };
3116 }; 2821 };
3117 2822
3118 qup_uart7_default: qu !! 2823 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 2824 mux {
3120 pins !! 2825 pins = "gpio58", "gpio59";
3121 funct !! 2826 function = "gpio";
3122 }; 2827 };
3123 2828
3124 qup_uart7_rx: !! 2829 config {
3125 pins !! 2830 pins = "gpio58", "gpio59";
3126 funct !! 2831 drive-strength = <2>;
>> 2832 bias-pull-down;
>> 2833 input-enable;
3127 }; 2834 };
3128 }; 2835 };
3129 2836
3130 qup_uart8_default: qu !! 2837 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 2838 mux {
3132 pins !! 2839 pins = "gpio58", "gpio59";
3133 funct !! 2840 function = "qua_mi2s";
3134 }; 2841 };
3135 2842
3136 qup_uart8_rx: !! 2843 config {
3137 pins !! 2844 pins = "gpio58", "gpio59";
3138 funct !! 2845 drive-strength = <8>;
>> 2846 bias-disable;
>> 2847 output-high;
3139 }; 2848 };
3140 }; 2849 };
3141 2850
3142 qup_uart9_default: qu !! 2851 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 2852 mux {
3144 pins !! 2853 pins = "gpio60";
3145 funct !! 2854 function = "gpio";
3146 }; 2855 };
3147 2856
3148 qup_uart9_rx: !! 2857 config {
3149 pins !! 2858 pins = "gpio60";
3150 funct !! 2859 drive-strength = <2>;
>> 2860 bias-pull-down;
>> 2861 input-enable;
3151 }; 2862 };
3152 }; 2863 };
3153 2864
3154 qup_uart10_default: q !! 2865 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 2866 mux {
3156 pins !! 2867 pins = "gpio60";
3157 funct !! 2868 function = "qua_mi2s";
3158 }; 2869 };
3159 2870
3160 qup_uart10_rx !! 2871 config {
3161 pins !! 2872 pins = "gpio60";
3162 funct !! 2873 drive-strength = <8>;
>> 2874 bias-disable;
3163 }; 2875 };
3164 }; 2876 };
3165 2877
3166 qup_uart11_default: q !! 2878 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 2879 mux {
3168 pins !! 2880 pins = "gpio61";
3169 funct !! 2881 function = "gpio";
3170 }; 2882 };
3171 2883
3172 qup_uart11_rx !! 2884 config {
3173 pins !! 2885 pins = "gpio61";
3174 funct !! 2886 drive-strength = <2>;
>> 2887 bias-pull-down;
>> 2888 input-enable;
3175 }; 2889 };
3176 }; 2890 };
3177 2891
3178 qup_uart12_default: q !! 2892 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 2893 mux {
3180 pins !! 2894 pins = "gpio61";
3181 funct !! 2895 function = "qua_mi2s";
3182 }; 2896 };
3183 2897
3184 qup_uart12_rx !! 2898 config {
3185 pins !! 2899 pins = "gpio61";
3186 funct !! 2900 drive-strength = <8>;
>> 2901 bias-disable;
3187 }; 2902 };
3188 }; 2903 };
3189 2904
3190 qup_uart13_default: q !! 2905 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 2906 mux {
3192 pins !! 2907 pins = "gpio62";
3193 funct !! 2908 function = "gpio";
3194 }; 2909 };
3195 2910
3196 qup_uart13_rx !! 2911 config {
3197 pins !! 2912 pins = "gpio62";
3198 funct !! 2913 drive-strength = <2>;
>> 2914 bias-pull-down;
>> 2915 input-enable;
3199 }; 2916 };
3200 }; 2917 };
3201 2918
3202 qup_uart14_default: q !! 2919 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 2920 mux {
3204 pins !! 2921 pins = "gpio62";
3205 funct !! 2922 function = "qua_mi2s";
3206 }; 2923 };
3207 2924
3208 qup_uart14_rx !! 2925 config {
3209 pins !! 2926 pins = "gpio62";
3210 funct !! 2927 drive-strength = <8>;
>> 2928 bias-disable;
3211 }; 2929 };
3212 }; 2930 };
3213 2931
3214 qup_uart15_default: q !! 2932 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 2933 mux {
3216 pins !! 2934 pins = "gpio63";
3217 funct !! 2935 function = "gpio";
3218 }; 2936 };
3219 2937
3220 qup_uart15_rx !! 2938 config {
3221 pins !! 2939 pins = "gpio63";
3222 funct !! 2940 drive-strength = <2>;
>> 2941 bias-pull-down;
>> 2942 input-enable;
3223 }; 2943 };
3224 }; 2944 };
3225 2945
3226 quat_mi2s_sleep: quat !! 2946 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 2947 mux {
3228 function = "g !! 2948 pins = "gpio63";
3229 drive-strengt !! 2949 function = "qua_mi2s";
3230 bias-pull-dow !! 2950 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 2951
3290 quat_mi2s_sd3_active: !! 2952 config {
3291 pins = "gpio6 !! 2953 pins = "gpio63";
3292 function = "q !! 2954 drive-strength = <8>;
3293 drive-strengt !! 2955 bias-disable;
3294 bias-disable; !! 2956 };
3295 }; 2957 };
3296 }; 2958 };
3297 2959
3298 mss_pil: remoteproc@4080000 { 2960 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 2961 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 2962 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 2963 reg-names = "qdsp6", "rmb";
3302 2964
3303 interrupts-extended = 2965 interrupts-extended =
3304 <&intc GIC_SP 2966 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 2967 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 2968 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 2969 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 2970 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 2971 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 2972 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 2973 "handover", "stop-ack",
3312 "sh 2974 "shutdown-ack";
3313 2975
3314 clocks = <&gcc GCC_MS 2976 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 2977 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 2978 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 2979 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 2980 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 2981 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 2982 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 2983 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 2984 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 2985 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 2986
3325 qcom,qmp = <&aoss_qmp <<
3326 <<
3327 qcom,smem-states = <& 2987 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 2988 qcom,smem-state-names = "stop";
3329 2989
3330 resets = <&aoss_reset 2990 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 2991 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 2992 reset-names = "mss_restart", "pdc_reset";
3333 2993
3334 qcom,halt-regs = <&tc !! 2994 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 2995
3336 power-domains = <&rpm !! 2996 power-domains = <&aoss_qmp 2>,
>> 2997 <&rpmhpd SDM845_CX>,
3337 <&rpm 2998 <&rpmhpd SDM845_MX>,
3338 <&rpm 2999 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = !! 3000 power-domain-names = "load_state", "cx", "mx", "mss";
3340 <<
3341 status = "disabled"; <<
3342 3001
3343 mba { 3002 mba {
3344 memory-region 3003 memory-region = <&mba_region>;
3345 }; 3004 };
3346 3005
3347 mpss { 3006 mpss {
3348 memory-region 3007 memory-region = <&mpss_region>;
3349 }; 3008 };
3350 3009
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 3010 glink-edge {
3356 interrupts = 3011 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3012 label = "modem";
3358 qcom,remote-p 3013 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3014 mboxes = <&apss_shared 12>;
3360 }; 3015 };
3361 }; 3016 };
3362 3017
3363 gpucc: clock-controller@50900 3018 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3019 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3020 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3021 #clock-cells = <1>;
3367 #reset-cells = <1>; 3022 #reset-cells = <1>;
3368 #power-domain-cells = 3023 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3024 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3025 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3026 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3027 clock-names = "bi_tcxo",
3373 "gcc_gp 3028 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3029 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3030 };
3376 3031
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 3032 stm@6002000 {
3431 compatible = "arm,cor 3033 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3034 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3035 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3036 reg-names = "stm-base", "stm-stimulus-base";
3435 3037
3436 clocks = <&aoss_qmp>; 3038 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3039 clock-names = "apb_pclk";
3438 3040
3439 out-ports { 3041 out-ports {
3440 port { 3042 port {
3441 stm_o 3043 stm_out: endpoint {
3442 3044 remote-endpoint =
3443 3045 <&funnel0_in7>;
3444 }; 3046 };
3445 }; 3047 };
3446 }; 3048 };
3447 }; 3049 };
3448 3050
3449 funnel@6041000 { 3051 funnel@6041000 {
3450 compatible = "arm,cor 3052 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3053 reg = <0 0x06041000 0 0x1000>;
3452 3054
3453 clocks = <&aoss_qmp>; 3055 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3056 clock-names = "apb_pclk";
3455 3057
3456 out-ports { 3058 out-ports {
3457 port { 3059 port {
3458 funne 3060 funnel0_out: endpoint {
3459 3061 remote-endpoint =
3460 3062 <&merge_funnel_in0>;
3461 }; 3063 };
3462 }; 3064 };
3463 }; 3065 };
3464 3066
3465 in-ports { 3067 in-ports {
3466 #address-cell 3068 #address-cells = <1>;
3467 #size-cells = 3069 #size-cells = <0>;
3468 3070
3469 port@7 { 3071 port@7 {
3470 reg = 3072 reg = <7>;
3471 funne 3073 funnel0_in7: endpoint {
3472 3074 remote-endpoint = <&stm_out>;
3473 }; 3075 };
3474 }; 3076 };
3475 }; 3077 };
3476 }; 3078 };
3477 3079
3478 funnel@6043000 { 3080 funnel@6043000 {
3479 compatible = "arm,cor 3081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3082 reg = <0 0x06043000 0 0x1000>;
3481 3083
3482 clocks = <&aoss_qmp>; 3084 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3085 clock-names = "apb_pclk";
3484 3086
3485 out-ports { 3087 out-ports {
3486 port { 3088 port {
3487 funne 3089 funnel2_out: endpoint {
3488 3090 remote-endpoint =
3489 3091 <&merge_funnel_in2>;
3490 }; 3092 };
3491 }; 3093 };
3492 }; 3094 };
3493 3095
3494 in-ports { 3096 in-ports {
3495 #address-cell 3097 #address-cells = <1>;
3496 #size-cells = 3098 #size-cells = <0>;
3497 3099
3498 port@5 { 3100 port@5 {
3499 reg = 3101 reg = <5>;
3500 funne 3102 funnel2_in5: endpoint {
3501 3103 remote-endpoint =
3502 3104 <&apss_merge_funnel_out>;
3503 }; 3105 };
3504 }; 3106 };
3505 }; 3107 };
3506 }; 3108 };
3507 3109
3508 funnel@6045000 { 3110 funnel@6045000 {
3509 compatible = "arm,cor 3111 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3112 reg = <0 0x06045000 0 0x1000>;
3511 3113
3512 clocks = <&aoss_qmp>; 3114 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3115 clock-names = "apb_pclk";
3514 3116
3515 out-ports { 3117 out-ports {
3516 port { 3118 port {
3517 merge 3119 merge_funnel_out: endpoint {
3518 3120 remote-endpoint = <&etf_in>;
3519 }; 3121 };
3520 }; 3122 };
3521 }; 3123 };
3522 3124
3523 in-ports { 3125 in-ports {
3524 #address-cell 3126 #address-cells = <1>;
3525 #size-cells = 3127 #size-cells = <0>;
3526 3128
3527 port@0 { 3129 port@0 {
3528 reg = 3130 reg = <0>;
3529 merge 3131 merge_funnel_in0: endpoint {
3530 3132 remote-endpoint =
3531 3133 <&funnel0_out>;
3532 }; 3134 };
3533 }; 3135 };
3534 3136
3535 port@2 { 3137 port@2 {
3536 reg = 3138 reg = <2>;
3537 merge 3139 merge_funnel_in2: endpoint {
3538 3140 remote-endpoint =
3539 3141 <&funnel2_out>;
3540 }; 3142 };
3541 }; 3143 };
3542 }; 3144 };
3543 }; 3145 };
3544 3146
3545 replicator@6046000 { 3147 replicator@6046000 {
3546 compatible = "arm,cor 3148 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3149 reg = <0 0x06046000 0 0x1000>;
3548 3150
3549 clocks = <&aoss_qmp>; 3151 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3152 clock-names = "apb_pclk";
3551 3153
3552 out-ports { 3154 out-ports {
3553 port { 3155 port {
3554 repli 3156 replicator_out: endpoint {
3555 3157 remote-endpoint = <&etr_in>;
3556 }; 3158 };
3557 }; 3159 };
3558 }; 3160 };
3559 3161
3560 in-ports { 3162 in-ports {
3561 port { 3163 port {
3562 repli 3164 replicator_in: endpoint {
3563 3165 remote-endpoint = <&etf_out>;
3564 }; 3166 };
3565 }; 3167 };
3566 }; 3168 };
3567 }; 3169 };
3568 3170
3569 etf@6047000 { 3171 etf@6047000 {
3570 compatible = "arm,cor 3172 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3173 reg = <0 0x06047000 0 0x1000>;
3572 3174
3573 clocks = <&aoss_qmp>; 3175 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3176 clock-names = "apb_pclk";
3575 3177
3576 out-ports { 3178 out-ports {
3577 port { 3179 port {
3578 etf_o 3180 etf_out: endpoint {
3579 3181 remote-endpoint =
3580 3182 <&replicator_in>;
3581 }; 3183 };
3582 }; 3184 };
3583 }; 3185 };
3584 3186
3585 in-ports { 3187 in-ports {
>> 3188 #address-cells = <1>;
>> 3189 #size-cells = <0>;
3586 3190
3587 port { !! 3191 port@1 {
>> 3192 reg = <1>;
3588 etf_i 3193 etf_in: endpoint {
3589 3194 remote-endpoint =
3590 3195 <&merge_funnel_out>;
3591 }; 3196 };
3592 }; 3197 };
3593 }; 3198 };
3594 }; 3199 };
3595 3200
3596 etr@6048000 { 3201 etr@6048000 {
3597 compatible = "arm,cor 3202 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3203 reg = <0 0x06048000 0 0x1000>;
3599 3204
3600 clocks = <&aoss_qmp>; 3205 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3206 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3207 arm,scatter-gather;
3603 3208
3604 in-ports { 3209 in-ports {
3605 port { 3210 port {
3606 etr_i 3211 etr_in: endpoint {
3607 3212 remote-endpoint =
3608 3213 <&replicator_out>;
3609 }; 3214 };
3610 }; 3215 };
3611 }; 3216 };
3612 }; 3217 };
3613 3218
3614 etm@7040000 { 3219 etm@7040000 {
3615 compatible = "arm,cor 3220 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3221 reg = <0 0x07040000 0 0x1000>;
3617 3222
3618 cpu = <&CPU0>; 3223 cpu = <&CPU0>;
3619 3224
3620 clocks = <&aoss_qmp>; 3225 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3226 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3227 arm,coresight-loses-context-with-cpu;
3623 3228
3624 out-ports { 3229 out-ports {
3625 port { 3230 port {
3626 etm0_ 3231 etm0_out: endpoint {
3627 3232 remote-endpoint =
3628 3233 <&apss_funnel_in0>;
3629 }; 3234 };
3630 }; 3235 };
3631 }; 3236 };
3632 }; 3237 };
3633 3238
3634 etm@7140000 { 3239 etm@7140000 {
3635 compatible = "arm,cor 3240 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3241 reg = <0 0x07140000 0 0x1000>;
3637 3242
3638 cpu = <&CPU1>; 3243 cpu = <&CPU1>;
3639 3244
3640 clocks = <&aoss_qmp>; 3245 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3246 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3247 arm,coresight-loses-context-with-cpu;
3643 3248
3644 out-ports { 3249 out-ports {
3645 port { 3250 port {
3646 etm1_ 3251 etm1_out: endpoint {
3647 3252 remote-endpoint =
3648 3253 <&apss_funnel_in1>;
3649 }; 3254 };
3650 }; 3255 };
3651 }; 3256 };
3652 }; 3257 };
3653 3258
3654 etm@7240000 { 3259 etm@7240000 {
3655 compatible = "arm,cor 3260 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3261 reg = <0 0x07240000 0 0x1000>;
3657 3262
3658 cpu = <&CPU2>; 3263 cpu = <&CPU2>;
3659 3264
3660 clocks = <&aoss_qmp>; 3265 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3266 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3267 arm,coresight-loses-context-with-cpu;
3663 3268
3664 out-ports { 3269 out-ports {
3665 port { 3270 port {
3666 etm2_ 3271 etm2_out: endpoint {
3667 3272 remote-endpoint =
3668 3273 <&apss_funnel_in2>;
3669 }; 3274 };
3670 }; 3275 };
3671 }; 3276 };
3672 }; 3277 };
3673 3278
3674 etm@7340000 { 3279 etm@7340000 {
3675 compatible = "arm,cor 3280 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3281 reg = <0 0x07340000 0 0x1000>;
3677 3282
3678 cpu = <&CPU3>; 3283 cpu = <&CPU3>;
3679 3284
3680 clocks = <&aoss_qmp>; 3285 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3286 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3287 arm,coresight-loses-context-with-cpu;
3683 3288
3684 out-ports { 3289 out-ports {
3685 port { 3290 port {
3686 etm3_ 3291 etm3_out: endpoint {
3687 3292 remote-endpoint =
3688 3293 <&apss_funnel_in3>;
3689 }; 3294 };
3690 }; 3295 };
3691 }; 3296 };
3692 }; 3297 };
3693 3298
3694 etm@7440000 { 3299 etm@7440000 {
3695 compatible = "arm,cor 3300 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3301 reg = <0 0x07440000 0 0x1000>;
3697 3302
3698 cpu = <&CPU4>; 3303 cpu = <&CPU4>;
3699 3304
3700 clocks = <&aoss_qmp>; 3305 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3306 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3307 arm,coresight-loses-context-with-cpu;
3703 3308
3704 out-ports { 3309 out-ports {
3705 port { 3310 port {
3706 etm4_ 3311 etm4_out: endpoint {
3707 3312 remote-endpoint =
3708 3313 <&apss_funnel_in4>;
3709 }; 3314 };
3710 }; 3315 };
3711 }; 3316 };
3712 }; 3317 };
3713 3318
3714 etm@7540000 { 3319 etm@7540000 {
3715 compatible = "arm,cor 3320 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3321 reg = <0 0x07540000 0 0x1000>;
3717 3322
3718 cpu = <&CPU5>; 3323 cpu = <&CPU5>;
3719 3324
3720 clocks = <&aoss_qmp>; 3325 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3326 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3327 arm,coresight-loses-context-with-cpu;
3723 3328
3724 out-ports { 3329 out-ports {
3725 port { 3330 port {
3726 etm5_ 3331 etm5_out: endpoint {
3727 3332 remote-endpoint =
3728 3333 <&apss_funnel_in5>;
3729 }; 3334 };
3730 }; 3335 };
3731 }; 3336 };
3732 }; 3337 };
3733 3338
3734 etm@7640000 { 3339 etm@7640000 {
3735 compatible = "arm,cor 3340 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3341 reg = <0 0x07640000 0 0x1000>;
3737 3342
3738 cpu = <&CPU6>; 3343 cpu = <&CPU6>;
3739 3344
3740 clocks = <&aoss_qmp>; 3345 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3346 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3347 arm,coresight-loses-context-with-cpu;
3743 3348
3744 out-ports { 3349 out-ports {
3745 port { 3350 port {
3746 etm6_ 3351 etm6_out: endpoint {
3747 3352 remote-endpoint =
3748 3353 <&apss_funnel_in6>;
3749 }; 3354 };
3750 }; 3355 };
3751 }; 3356 };
3752 }; 3357 };
3753 3358
3754 etm@7740000 { 3359 etm@7740000 {
3755 compatible = "arm,cor 3360 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3361 reg = <0 0x07740000 0 0x1000>;
3757 3362
3758 cpu = <&CPU7>; 3363 cpu = <&CPU7>;
3759 3364
3760 clocks = <&aoss_qmp>; 3365 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3366 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3367 arm,coresight-loses-context-with-cpu;
3763 3368
3764 out-ports { 3369 out-ports {
3765 port { 3370 port {
3766 etm7_ 3371 etm7_out: endpoint {
3767 3372 remote-endpoint =
3768 3373 <&apss_funnel_in7>;
3769 }; 3374 };
3770 }; 3375 };
3771 }; 3376 };
3772 }; 3377 };
3773 3378
3774 funnel@7800000 { /* APSS Funn 3379 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3381 reg = <0 0x07800000 0 0x1000>;
3777 3382
3778 clocks = <&aoss_qmp>; 3383 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3384 clock-names = "apb_pclk";
3780 3385
3781 out-ports { 3386 out-ports {
3782 port { 3387 port {
3783 apss_ 3388 apss_funnel_out: endpoint {
3784 3389 remote-endpoint =
3785 3390 <&apss_merge_funnel_in>;
3786 }; 3391 };
3787 }; 3392 };
3788 }; 3393 };
3789 3394
3790 in-ports { 3395 in-ports {
3791 #address-cell 3396 #address-cells = <1>;
3792 #size-cells = 3397 #size-cells = <0>;
3793 3398
3794 port@0 { 3399 port@0 {
3795 reg = 3400 reg = <0>;
3796 apss_ 3401 apss_funnel_in0: endpoint {
3797 3402 remote-endpoint =
3798 3403 <&etm0_out>;
3799 }; 3404 };
3800 }; 3405 };
3801 3406
3802 port@1 { 3407 port@1 {
3803 reg = 3408 reg = <1>;
3804 apss_ 3409 apss_funnel_in1: endpoint {
3805 3410 remote-endpoint =
3806 3411 <&etm1_out>;
3807 }; 3412 };
3808 }; 3413 };
3809 3414
3810 port@2 { 3415 port@2 {
3811 reg = 3416 reg = <2>;
3812 apss_ 3417 apss_funnel_in2: endpoint {
3813 3418 remote-endpoint =
3814 3419 <&etm2_out>;
3815 }; 3420 };
3816 }; 3421 };
3817 3422
3818 port@3 { 3423 port@3 {
3819 reg = 3424 reg = <3>;
3820 apss_ 3425 apss_funnel_in3: endpoint {
3821 3426 remote-endpoint =
3822 3427 <&etm3_out>;
3823 }; 3428 };
3824 }; 3429 };
3825 3430
3826 port@4 { 3431 port@4 {
3827 reg = 3432 reg = <4>;
3828 apss_ 3433 apss_funnel_in4: endpoint {
3829 3434 remote-endpoint =
3830 3435 <&etm4_out>;
3831 }; 3436 };
3832 }; 3437 };
3833 3438
3834 port@5 { 3439 port@5 {
3835 reg = 3440 reg = <5>;
3836 apss_ 3441 apss_funnel_in5: endpoint {
3837 3442 remote-endpoint =
3838 3443 <&etm5_out>;
3839 }; 3444 };
3840 }; 3445 };
3841 3446
3842 port@6 { 3447 port@6 {
3843 reg = 3448 reg = <6>;
3844 apss_ 3449 apss_funnel_in6: endpoint {
3845 3450 remote-endpoint =
3846 3451 <&etm6_out>;
3847 }; 3452 };
3848 }; 3453 };
3849 3454
3850 port@7 { 3455 port@7 {
3851 reg = 3456 reg = <7>;
3852 apss_ 3457 apss_funnel_in7: endpoint {
3853 3458 remote-endpoint =
3854 3459 <&etm7_out>;
3855 }; 3460 };
3856 }; 3461 };
3857 }; 3462 };
3858 }; 3463 };
3859 3464
3860 funnel@7810000 { 3465 funnel@7810000 {
3861 compatible = "arm,cor 3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3467 reg = <0 0x07810000 0 0x1000>;
3863 3468
3864 clocks = <&aoss_qmp>; 3469 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3470 clock-names = "apb_pclk";
3866 3471
3867 out-ports { 3472 out-ports {
3868 port { 3473 port {
3869 apss_ 3474 apss_merge_funnel_out: endpoint {
3870 3475 remote-endpoint =
3871 3476 <&funnel2_in5>;
3872 }; 3477 };
3873 }; 3478 };
3874 }; 3479 };
3875 3480
3876 in-ports { 3481 in-ports {
3877 port { 3482 port {
3878 apss_ 3483 apss_merge_funnel_in: endpoint {
3879 3484 remote-endpoint =
3880 3485 <&apss_funnel_out>;
3881 }; 3486 };
3882 }; 3487 };
3883 }; 3488 };
3884 }; 3489 };
3885 3490
3886 sdhc_2: mmc@8804000 { !! 3491 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 3492 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3493 reg = <0 0x08804000 0 0x1000>;
3889 3494
3890 interrupts = <GIC_SPI 3495 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3496 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3497 interrupt-names = "hc_irq", "pwr_irq";
3893 3498
3894 clocks = <&gcc GCC_SD 3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD !! 3500 <&gcc GCC_SDCC2_APPS_CLK>;
3896 <&rpmhcc RPM !! 3501 clock-names = "iface", "core";
3897 clock-names = "iface" <<
3898 iommus = <&apps_smmu 3502 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3503 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3504 operating-points-v2 = <&sdhc2_opp_table>;
3901 3505
3902 status = "disabled"; 3506 status = "disabled";
3903 3507
3904 sdhc2_opp_table: opp- !! 3508 sdhc2_opp_table: sdhc2-opp-table {
3905 compatible = 3509 compatible = "operating-points-v2";
3906 3510
3907 opp-9600000 { 3511 opp-9600000 {
3908 opp-h 3512 opp-hz = /bits/ 64 <9600000>;
3909 requi 3513 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3514 };
3911 3515
3912 opp-19200000 3516 opp-19200000 {
3913 opp-h 3517 opp-hz = /bits/ 64 <19200000>;
3914 requi 3518 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3519 };
3916 3520
3917 opp-100000000 3521 opp-100000000 {
3918 opp-h 3522 opp-hz = /bits/ 64 <100000000>;
3919 requi 3523 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3524 };
3921 3525
3922 opp-201500000 3526 opp-201500000 {
3923 opp-h 3527 opp-hz = /bits/ 64 <201500000>;
3924 requi 3528 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3529 };
3926 }; 3530 };
3927 }; 3531 };
3928 3532
>> 3533 qspi_opp_table: qspi-opp-table {
>> 3534 compatible = "operating-points-v2";
>> 3535
>> 3536 opp-19200000 {
>> 3537 opp-hz = /bits/ 64 <19200000>;
>> 3538 required-opps = <&rpmhpd_opp_min_svs>;
>> 3539 };
>> 3540
>> 3541 opp-100000000 {
>> 3542 opp-hz = /bits/ 64 <100000000>;
>> 3543 required-opps = <&rpmhpd_opp_low_svs>;
>> 3544 };
>> 3545
>> 3546 opp-150000000 {
>> 3547 opp-hz = /bits/ 64 <150000000>;
>> 3548 required-opps = <&rpmhpd_opp_svs>;
>> 3549 };
>> 3550
>> 3551 opp-300000000 {
>> 3552 opp-hz = /bits/ 64 <300000000>;
>> 3553 required-opps = <&rpmhpd_opp_nom>;
>> 3554 };
>> 3555 };
>> 3556
3929 qspi: spi@88df000 { 3557 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3558 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3559 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3560 #address-cells = <1>;
3934 #size-cells = <0>; 3561 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3562 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3563 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3564 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3565 clock-names = "iface", "core";
3939 power-domains = <&rpm 3566 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3567 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3568 status = "disabled";
3942 }; 3569 };
3943 3570
3944 slim: slim-ngd@171c0000 { !! 3571 slim: slim@171c0000 {
3945 compatible = "qcom,sl 3572 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3573 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3574 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3575
3949 dmas = <&slimbam 3>, !! 3576 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 3577 qcom,ea-pc = <0x270>;
>> 3578 status = "okay";
>> 3579 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3580 <&slimbam 5>, <&slimbam 6>;
>> 3581 dma-names = "rx", "tx", "tx2", "rx2";
3951 3582
3952 iommus = <&apps_smmu 3583 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3584 #address-cells = <1>;
3954 #size-cells = <0>; 3585 #size-cells = <0>;
3955 status = "disabled"; <<
3956 }; <<
3957 3586
3958 lmh_cluster1: lmh@17d70800 { !! 3587 ngd@1 {
3959 compatible = "qcom,sd !! 3588 reg = <1>;
3960 reg = <0 0x17d70800 0 !! 3589 #address-cells = <2>;
3961 interrupts = <GIC_SPI !! 3590 #size-cells = <0>;
3962 cpus = <&CPU4>; !! 3591
3963 qcom,lmh-temp-arm-mil !! 3592 wcd9340_ifd: ifd@0{
3964 qcom,lmh-temp-low-mil !! 3593 compatible = "slim217,250";
3965 qcom,lmh-temp-high-mi !! 3594 reg = <0 0>;
3966 interrupt-controller; !! 3595 };
3967 #interrupt-cells = <1 !! 3596
>> 3597 wcd9340: codec@1{
>> 3598 compatible = "slim217,250";
>> 3599 reg = <1 0>;
>> 3600 slim-ifc-dev = <&wcd9340_ifd>;
>> 3601
>> 3602 #sound-dai-cells = <1>;
>> 3603
>> 3604 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3605 interrupt-controller;
>> 3606 #interrupt-cells = <1>;
>> 3607
>> 3608 #clock-cells = <0>;
>> 3609 clock-frequency = <9600000>;
>> 3610 clock-output-names = "mclk";
>> 3611 qcom,micbias1-millivolt = <1800>;
>> 3612 qcom,micbias2-millivolt = <1800>;
>> 3613 qcom,micbias3-millivolt = <1800>;
>> 3614 qcom,micbias4-millivolt = <1800>;
>> 3615
>> 3616 #address-cells = <1>;
>> 3617 #size-cells = <1>;
>> 3618
>> 3619 wcdgpio: gpio-controller@42 {
>> 3620 compatible = "qcom,wcd9340-gpio";
>> 3621 gpio-controller;
>> 3622 #gpio-cells = <2>;
>> 3623 reg = <0x42 0x2>;
>> 3624 };
>> 3625
>> 3626 swm: swm@c85 {
>> 3627 compatible = "qcom,soundwire-v1.3.0";
>> 3628 reg = <0xc85 0x40>;
>> 3629 interrupts-extended = <&wcd9340 20>;
>> 3630
>> 3631 qcom,dout-ports = <6>;
>> 3632 qcom,din-ports = <2>;
>> 3633 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3634 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3635 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3636
>> 3637 #sound-dai-cells = <1>;
>> 3638 clocks = <&wcd9340>;
>> 3639 clock-names = "iface";
>> 3640 #address-cells = <2>;
>> 3641 #size-cells = <0>;
>> 3642
>> 3643
>> 3644 };
>> 3645 };
>> 3646 };
3968 }; 3647 };
3969 3648
3970 lmh_cluster0: lmh@17d78800 { !! 3649 sound: sound {
3971 compatible = "qcom,sd <<
3972 reg = <0 0x17d78800 0 <<
3973 interrupts = <GIC_SPI <<
3974 cpus = <&CPU0>; <<
3975 qcom,lmh-temp-arm-mil <<
3976 qcom,lmh-temp-low-mil <<
3977 qcom,lmh-temp-high-mi <<
3978 interrupt-controller; <<
3979 #interrupt-cells = <1 <<
3980 }; 3650 };
3981 3651
3982 usb_1_hsphy: phy@88e2000 { 3652 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3653 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3654 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3655 status = "disabled";
3986 #phy-cells = <0>; 3656 #phy-cells = <0>;
3987 3657
3988 clocks = <&gcc GCC_US 3658 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3659 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3660 clock-names = "cfg_ahb", "ref";
3991 3661
3992 resets = <&gcc GCC_QU 3662 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3663
3994 nvmem-cells = <&qusb2 3664 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3665 };
3996 3666
3997 usb_2_hsphy: phy@88e3000 { 3667 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3668 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3669 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3670 status = "disabled";
4001 #phy-cells = <0>; 3671 #phy-cells = <0>;
4002 3672
4003 clocks = <&gcc GCC_US 3673 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3674 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3675 clock-names = "cfg_ahb", "ref";
4006 3676
4007 resets = <&gcc GCC_QU 3677 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3678
4009 nvmem-cells = <&qusb2 3679 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3680 };
4011 3681
4012 usb_1_qmpphy: phy@88e8000 { !! 3682 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3683 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3684 reg = <0 0x088e9000 0 0x18c>,
>> 3685 <0 0x088e8000 0 0x10>;
>> 3686 reg-names = "reg-base", "dp_com";
4015 status = "disabled"; 3687 status = "disabled";
>> 3688 #address-cells = <2>;
>> 3689 #size-cells = <2>;
>> 3690 ranges;
4016 3691
4017 clocks = <&gcc GCC_US 3692 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3693 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3694 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3695 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3696 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3697
4028 resets = <&gcc GCC_US !! 3698 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3699 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3700 reset-names = "phy", "common";
4031 3701
4032 #clock-cells = <1>; !! 3702 usb_1_ssphy: lanes@88e9200 {
4033 #phy-cells = <1>; !! 3703 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3704 <0 0x088e9400 0 0x200>,
4035 !! 3705 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3706 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3707 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3708 <0 0x088e9a00 0 0x100>;
4039 !! 3709 #clock-cells = <0>;
4040 port@0 { !! 3710 #phy-cells = <0>;
4041 reg = !! 3711 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042 !! 3712 clock-names = "pipe0";
4043 usb_1 !! 3713 clock-output-names = "usb3_phy_pipe_clk_src";
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3714 };
4063 }; 3715 };
4064 3716
4065 usb_2_qmpphy: phy@88eb000 { 3717 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3718 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 3719 reg = <0 0x088eb000 0 0x18c>;
>> 3720 status = "disabled";
>> 3721 #address-cells = <2>;
>> 3722 #size-cells = <2>;
>> 3723 ranges;
4068 3724
4069 clocks = <&gcc GCC_US 3725 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 3726 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 3727 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 3728 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 3729 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 3730
4083 resets = <&gcc GCC_US !! 3731 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 3732 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 3733 reset-names = "phy", "common";
4086 "phy_ph <<
4087 3734
4088 status = "disabled"; !! 3735 usb_2_ssphy: lane@88eb200 {
>> 3736 reg = <0 0x088eb200 0 0x128>,
>> 3737 <0 0x088eb400 0 0x1fc>,
>> 3738 <0 0x088eb800 0 0x218>,
>> 3739 <0 0x088eb600 0 0x70>;
>> 3740 #clock-cells = <0>;
>> 3741 #phy-cells = <0>;
>> 3742 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3743 clock-names = "pipe0";
>> 3744 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3745 };
4089 }; 3746 };
4090 3747
4091 usb_1: usb@a6f8800 { 3748 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 3749 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 3750 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 3751 status = "disabled";
4095 #address-cells = <2>; 3752 #address-cells = <2>;
4096 #size-cells = <2>; 3753 #size-cells = <2>;
4097 ranges; 3754 ranges;
4098 dma-ranges; 3755 dma-ranges;
4099 3756
4100 clocks = <&gcc GCC_CF 3757 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 3758 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 3759 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 3760 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 3761 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 3762 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 3763 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 3764
4111 assigned-clocks = <&g 3765 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 3766 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 3767 assigned-clock-rates = <19200000>, <150000000>;
4114 3768
4115 interrupts-extended = !! 3769 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 3770 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 3771 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 3772 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 3773 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 3774 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 3775
4126 power-domains = <&gcc 3776 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 3777
4128 resets = <&gcc GCC_US 3778 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 3779
4130 interconnects = <&agg 3780 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 3781 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 3782 interconnect-names = "usb-ddr", "apps-usb";
4133 3783
4134 usb_1_dwc3: usb@a6000 !! 3784 usb_1_dwc3: dwc3@a600000 {
4135 compatible = 3785 compatible = "snps,dwc3";
4136 reg = <0 0x0a 3786 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 3787 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 3788 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 3789 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 3790 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 3791 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 3792 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 3793 };
4165 }; 3794 };
4166 3795
4167 usb_2: usb@a8f8800 { 3796 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 3797 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 3798 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 3799 status = "disabled";
4171 #address-cells = <2>; 3800 #address-cells = <2>;
4172 #size-cells = <2>; 3801 #size-cells = <2>;
4173 ranges; 3802 ranges;
4174 dma-ranges; 3803 dma-ranges;
4175 3804
4176 clocks = <&gcc GCC_CF 3805 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 3806 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 3807 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 3808 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 3809 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 3810 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 3811 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 3812
4187 assigned-clocks = <&g 3813 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 3814 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 3815 assigned-clock-rates = <19200000>, <150000000>;
4190 3816
4191 interrupts-extended = !! 3817 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 3818 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 3819 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 3820 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 3821 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 3822 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 3823
4202 power-domains = <&gcc 3824 power-domains = <&gcc USB30_SEC_GDSC>;
4203 3825
4204 resets = <&gcc GCC_US 3826 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 3827
4206 interconnects = <&agg 3828 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 3829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 3830 interconnect-names = "usb-ddr", "apps-usb";
4209 3831
4210 usb_2_dwc3: usb@a8000 !! 3832 usb_2_dwc3: dwc3@a800000 {
4211 compatible = 3833 compatible = "snps,dwc3";
4212 reg = <0 0x0a 3834 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 3835 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 3836 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 3837 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 3838 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 3839 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 3840 phy-names = "usb2-phy", "usb3-phy";
4220 }; 3841 };
4221 }; 3842 };
4222 3843
4223 venus: video-codec@aa00000 { 3844 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 3845 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 3846 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 3847 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 3848 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 3849 <&videocc VCODEC0_GDSC>,
4229 <&vid 3850 <&videocc VCODEC1_GDSC>,
4230 <&rpm 3851 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 3852 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 3853 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 3854 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 3855 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 3856 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 3857 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 3858 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 3859 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 3860 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 3861 clock-names = "core", "iface", "bus",
4241 "vcodec 3862 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 3863 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 3864 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 3865 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 3866 memory-region = <&venus_mem>;
4246 interconnects = <&mms 3867 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 3868 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 3869 interconnect-names = "video-mem", "cpu-cfg";
4249 3870
4250 status = "disabled"; <<
4251 <<
4252 video-core0 { 3871 video-core0 {
4253 compatible = 3872 compatible = "venus-decoder";
4254 }; 3873 };
4255 3874
4256 video-core1 { 3875 video-core1 {
4257 compatible = 3876 compatible = "venus-encoder";
4258 }; 3877 };
4259 3878
4260 venus_opp_table: opp- !! 3879 venus_opp_table: venus-opp-table {
4261 compatible = 3880 compatible = "operating-points-v2";
4262 3881
4263 opp-100000000 3882 opp-100000000 {
4264 opp-h 3883 opp-hz = /bits/ 64 <100000000>;
4265 requi 3884 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 3885 };
4267 3886
4268 opp-200000000 3887 opp-200000000 {
4269 opp-h 3888 opp-hz = /bits/ 64 <200000000>;
4270 requi 3889 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 3890 };
4272 3891
4273 opp-320000000 3892 opp-320000000 {
4274 opp-h 3893 opp-hz = /bits/ 64 <320000000>;
4275 requi 3894 required-opps = <&rpmhpd_opp_svs>;
4276 }; 3895 };
4277 3896
4278 opp-380000000 3897 opp-380000000 {
4279 opp-h 3898 opp-hz = /bits/ 64 <380000000>;
4280 requi 3899 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 3900 };
4282 3901
4283 opp-444000000 3902 opp-444000000 {
4284 opp-h 3903 opp-hz = /bits/ 64 <444000000>;
4285 requi 3904 required-opps = <&rpmhpd_opp_nom>;
4286 }; 3905 };
4287 3906
4288 opp-533000097 3907 opp-533000097 {
4289 opp-h 3908 opp-hz = /bits/ 64 <533000097>;
4290 requi 3909 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 3910 };
4292 }; 3911 };
4293 }; 3912 };
4294 3913
4295 videocc: clock-controller@ab0 3914 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 3915 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 3916 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 3917 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 3918 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 3919 #clock-cells = <1>;
4301 #power-domain-cells = 3920 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 3921 #reset-cells = <1>;
4303 }; 3922 };
4304 3923
4305 camss: camss@acb3000 { !! 3924 camss: camss@a00000 {
4306 compatible = "qcom,sd 3925 compatible = "qcom,sdm845-camss";
4307 3926
4308 reg = <0 0x0acb3000 0 !! 3927 reg = <0 0xacb3000 0 0x1000>,
4309 <0 0x0acba000 !! 3928 <0 0xacba000 0 0x1000>,
4310 <0 0x0acc8000 !! 3929 <0 0xacc8000 0 0x1000>,
4311 <0 0x0ac65000 !! 3930 <0 0xac65000 0 0x1000>,
4312 <0 0x0ac66000 !! 3931 <0 0xac66000 0 0x1000>,
4313 <0 0x0ac67000 !! 3932 <0 0xac67000 0 0x1000>,
4314 <0 0x0ac68000 !! 3933 <0 0xac68000 0 0x1000>,
4315 <0 0x0acaf000 !! 3934 <0 0xacaf000 0 0x4000>,
4316 <0 0x0acb6000 !! 3935 <0 0xacb6000 0 0x4000>,
4317 <0 0x0acc4000 !! 3936 <0 0xacc4000 0 0x4000>;
4318 reg-names = "csid0", 3937 reg-names = "csid0",
4319 "csid1", 3938 "csid1",
4320 "csid2", 3939 "csid2",
4321 "csiphy0", 3940 "csiphy0",
4322 "csiphy1", 3941 "csiphy1",
4323 "csiphy2", 3942 "csiphy2",
4324 "csiphy3", 3943 "csiphy3",
4325 "vfe0", 3944 "vfe0",
4326 "vfe1", 3945 "vfe1",
4327 "vfe_lite"; 3946 "vfe_lite";
4328 3947
4329 interrupts = <GIC_SPI 3948 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 3949 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 3950 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 3951 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 3952 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 3953 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 3954 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 3955 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 3956 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 3957 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 3958 interrupt-names = "csid0",
4340 "csid1", 3959 "csid1",
4341 "csid2", 3960 "csid2",
4342 "csiphy0", 3961 "csiphy0",
4343 "csiphy1", 3962 "csiphy1",
4344 "csiphy2", 3963 "csiphy2",
4345 "csiphy3", 3964 "csiphy3",
4346 "vfe0", 3965 "vfe0",
4347 "vfe1", 3966 "vfe1",
4348 "vfe_lite"; 3967 "vfe_lite";
4349 3968
4350 power-domains = <&clo 3969 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 3970 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 3971 <&clock_camcc TITAN_TOP_GDSC>;
4353 3972
4354 clocks = <&clock_camc 3973 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 3974 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 3975 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 3976 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 3977 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 3978 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 3979 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 3980 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 3981 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 3982 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 3983 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 3984 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 3985 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 3986 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 3987 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 3988 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 3989 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 3990 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 3991 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 3992 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 3993 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 3994 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 3995 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 3996 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 3997 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 3998 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 3999 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4000 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4001 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4002 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4003 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4004 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4005 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4006 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4007 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4008 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4009 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4010 "cpas_ahb",
4392 "cphy_rx_src" 4011 "cphy_rx_src",
4393 "csi0", 4012 "csi0",
4394 "csi0_src", 4013 "csi0_src",
4395 "csi1", 4014 "csi1",
4396 "csi1_src", 4015 "csi1_src",
4397 "csi2", 4016 "csi2",
4398 "csi2_src", 4017 "csi2_src",
4399 "csiphy0", 4018 "csiphy0",
4400 "csiphy0_time 4019 "csiphy0_timer",
4401 "csiphy0_time 4020 "csiphy0_timer_src",
4402 "csiphy1", 4021 "csiphy1",
4403 "csiphy1_time 4022 "csiphy1_timer",
4404 "csiphy1_time 4023 "csiphy1_timer_src",
4405 "csiphy2", 4024 "csiphy2",
4406 "csiphy2_time 4025 "csiphy2_timer",
4407 "csiphy2_time 4026 "csiphy2_timer_src",
4408 "csiphy3", 4027 "csiphy3",
4409 "csiphy3_time 4028 "csiphy3_timer",
4410 "csiphy3_time 4029 "csiphy3_timer_src",
4411 "gcc_camera_a 4030 "gcc_camera_ahb",
4412 "gcc_camera_a 4031 "gcc_camera_axi",
4413 "slow_ahb_src 4032 "slow_ahb_src",
4414 "soc_ahb", 4033 "soc_ahb",
4415 "vfe0_axi", 4034 "vfe0_axi",
4416 "vfe0", 4035 "vfe0",
4417 "vfe0_cphy_rx 4036 "vfe0_cphy_rx",
4418 "vfe0_src", 4037 "vfe0_src",
4419 "vfe1_axi", 4038 "vfe1_axi",
4420 "vfe1", 4039 "vfe1",
4421 "vfe1_cphy_rx 4040 "vfe1_cphy_rx",
4422 "vfe1_src", 4041 "vfe1_src",
4423 "vfe_lite", 4042 "vfe_lite",
4424 "vfe_lite_cph 4043 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4044 "vfe_lite_src";
4426 4045
4427 iommus = <&apps_smmu 4046 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4047 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4048 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4049 <&apps_smmu 0x0c10 0x8>;
4431 4050
4432 status = "disabled"; 4051 status = "disabled";
4433 4052
4434 ports { 4053 ports {
4435 #address-cell 4054 #address-cells = <1>;
4436 #size-cells = 4055 #size-cells = <0>;
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; 4056 };
4454 }; 4057 };
4455 4058
4456 cci: cci@ac4a000 { 4059 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 4060 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 4061 #address-cells = <1>;
4459 #size-cells = <0>; 4062 #size-cells = <0>;
4460 4063
4461 reg = <0 0x0ac4a000 0 4064 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4065 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4066 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4067
4465 clocks = <&clock_camc 4068 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4069 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4070 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4071 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4072 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4073 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4074 clock-names = "camnoc_axi",
4472 "soc_ahb", 4075 "soc_ahb",
4473 "slow_ahb_src 4076 "slow_ahb_src",
4474 "cpas_ahb", 4077 "cpas_ahb",
4475 "cci", 4078 "cci",
4476 "cci_src"; 4079 "cci_src";
4477 4080
4478 assigned-clocks = <&c 4081 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4082 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4083 assigned-clock-rates = <80000000>, <37500000>;
4481 4084
4482 pinctrl-names = "defa 4085 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4086 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4087 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4088
4486 status = "disabled"; 4089 status = "disabled";
4487 4090
4488 cci_i2c0: i2c-bus@0 { 4091 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4092 reg = <0>;
4490 clock-frequen 4093 clock-frequency = <1000000>;
4491 #address-cell 4094 #address-cells = <1>;
4492 #size-cells = 4095 #size-cells = <0>;
4493 }; 4096 };
4494 4097
4495 cci_i2c1: i2c-bus@1 { 4098 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4099 reg = <1>;
4497 clock-frequen 4100 clock-frequency = <1000000>;
4498 #address-cell 4101 #address-cells = <1>;
4499 #size-cells = 4102 #size-cells = <0>;
4500 }; 4103 };
4501 }; 4104 };
4502 4105
4503 clock_camcc: clock-controller 4106 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4107 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4108 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4109 #clock-cells = <1>;
4507 #reset-cells = <1>; 4110 #reset-cells = <1>;
4508 #power-domain-cells = 4111 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; 4112 };
4512 4113
4513 mdss: display-subsystem@ae000 !! 4114 dsi_opp_table: dsi-opp-table {
>> 4115 compatible = "operating-points-v2";
>> 4116
>> 4117 opp-19200000 {
>> 4118 opp-hz = /bits/ 64 <19200000>;
>> 4119 required-opps = <&rpmhpd_opp_min_svs>;
>> 4120 };
>> 4121
>> 4122 opp-180000000 {
>> 4123 opp-hz = /bits/ 64 <180000000>;
>> 4124 required-opps = <&rpmhpd_opp_low_svs>;
>> 4125 };
>> 4126
>> 4127 opp-275000000 {
>> 4128 opp-hz = /bits/ 64 <275000000>;
>> 4129 required-opps = <&rpmhpd_opp_svs>;
>> 4130 };
>> 4131
>> 4132 opp-328580000 {
>> 4133 opp-hz = /bits/ 64 <328580000>;
>> 4134 required-opps = <&rpmhpd_opp_svs_l1>;
>> 4135 };
>> 4136
>> 4137 opp-358000000 {
>> 4138 opp-hz = /bits/ 64 <358000000>;
>> 4139 required-opps = <&rpmhpd_opp_nom>;
>> 4140 };
>> 4141 };
>> 4142
>> 4143 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 4144 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4145 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4146 reg-names = "mdss";
4517 4147
4518 power-domains = <&dis 4148 power-domains = <&dispcc MDSS_GDSC>;
4519 4149
4520 clocks = <&dispcc DIS !! 4150 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 4151 <&gcc GCC_DISP_AXI_CLK>,
4521 <&dispcc DIS 4152 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" !! 4153 clock-names = "iface", "bus", "core";
>> 4154
>> 4155 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 4156 assigned-clock-rates = <300000000>;
4523 4157
4524 interrupts = <GIC_SPI 4158 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4159 interrupt-controller;
4526 #interrupt-cells = <1 4160 #interrupt-cells = <1>;
4527 4161
4528 interconnects = <&mms 4162 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4163 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4164 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4165
4532 iommus = <&apps_smmu 4166 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4167 <&apps_smmu 0xc80 0x8>;
4534 4168
4535 status = "disabled"; 4169 status = "disabled";
4536 4170
4537 #address-cells = <2>; 4171 #address-cells = <2>;
4538 #size-cells = <2>; 4172 #size-cells = <2>;
4539 ranges; 4173 ranges;
4540 4174
4541 mdss_mdp: display-con !! 4175 mdss_mdp: mdp@ae01000 {
4542 compatible = 4176 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4177 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4178 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4179 reg-names = "mdp", "vbif";
4546 4180
4547 clocks = <&gc !! 4181 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4548 <&di <<
4549 <&di 4182 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4183 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4184 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = !! 4185 clock-names = "iface", "bus", "core", "vsync";
4553 4186
4554 assigned-cloc !! 4187 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 4188 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 4189 assigned-clock-rates = <300000000>,
>> 4190 <19200000>;
4556 operating-poi 4191 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4192 power-domains = <&rpmhpd SDM845_CX>;
4558 4193
4559 interrupt-par 4194 interrupt-parent = <&mdss>;
4560 interrupts = !! 4195 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> 4196
>> 4197 status = "disabled";
4561 4198
4562 ports { 4199 ports {
4563 #addr 4200 #address-cells = <1>;
4564 #size 4201 #size-cells = <0>;
4565 4202
4566 port@ 4203 port@0 {
4567 4204 reg = <0>;
4568 !! 4205 dpu_intf1_out: endpoint {
4569 !! 4206 remote-endpoint = <&dsi0_in>;
4570 4207 };
4571 }; 4208 };
4572 4209
4573 port@ 4210 port@1 {
4574 4211 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 4212 dpu_intf2_out: endpoint {
4583 !! 4213 remote-endpoint = <&dsi1_in>;
4584 4214 };
4585 }; 4215 };
4586 }; 4216 };
4587 4217
4588 mdp_opp_table !! 4218 mdp_opp_table: mdp-opp-table {
4589 compa 4219 compatible = "operating-points-v2";
4590 4220
4591 opp-1 4221 opp-19200000 {
4592 4222 opp-hz = /bits/ 64 <19200000>;
4593 4223 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4224 };
4595 4225
4596 opp-1 4226 opp-171428571 {
4597 4227 opp-hz = /bits/ 64 <171428571>;
4598 4228 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4229 };
4600 4230
4601 opp-3 4231 opp-344000000 {
4602 4232 opp-hz = /bits/ 64 <344000000>;
4603 4233 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4234 };
4605 4235
4606 opp-4 4236 opp-430000000 {
4607 4237 opp-hz = /bits/ 64 <430000000>;
4608 4238 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4239 };
4610 }; 4240 };
4611 }; 4241 };
4612 4242
4613 mdss_dp: displayport- !! 4243 dsi0: dsi@ae94000 {
4614 status = "dis !! 4244 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 4245 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4246 reg-names = "dsi_ctrl";
4691 4247
4692 interrupt-par 4248 interrupt-parent = <&mdss>;
4693 interrupts = !! 4249 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 4250
4695 clocks = <&di 4251 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4252 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4253 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4254 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4255 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4256 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4257 clock-names = "byte",
4702 4258 "byte_intf",
4703 4259 "pixel",
4704 4260 "core",
4705 4261 "iface",
4706 4262 "bus";
4707 assigned-cloc <<
4708 assigned-cloc <<
4709 <<
4710 operating-poi 4263 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4264 power-domains = <&rpmhpd SDM845_CX>;
4712 4265
4713 phys = <&mdss !! 4266 phys = <&dsi0_phy>;
>> 4267 phy-names = "dsi";
4714 4268
4715 status = "dis 4269 status = "disabled";
4716 4270
4717 #address-cell <<
4718 #size-cells = <<
4719 <<
4720 ports { 4271 ports {
4721 #addr 4272 #address-cells = <1>;
4722 #size 4273 #size-cells = <0>;
4723 4274
4724 port@ 4275 port@0 {
4725 4276 reg = <0>;
4726 !! 4277 dsi0_in: endpoint {
4727 4278 remote-endpoint = <&dpu_intf1_out>;
4728 4279 };
4729 }; 4280 };
4730 4281
4731 port@ 4282 port@1 {
4732 4283 reg = <1>;
4733 !! 4284 dsi0_out: endpoint {
4734 4285 };
4735 }; 4286 };
4736 }; 4287 };
4737 }; 4288 };
4738 4289
4739 mdss_dsi0_phy: phy@ae !! 4290 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 4291 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4292 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4293 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4294 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4295 reg-names = "dsi_phy",
4745 " 4296 "dsi_phy_lane",
4746 " 4297 "dsi_pll";
4747 4298
4748 #clock-cells 4299 #clock-cells = <1>;
4749 #phy-cells = 4300 #phy-cells = <0>;
4750 4301
4751 clocks = <&di 4302 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4303 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4304 clock-names = "iface", "ref";
4754 4305
4755 status = "dis 4306 status = "disabled";
4756 }; 4307 };
4757 4308
4758 mdss_dsi1: dsi@ae9600 !! 4309 dsi1: dsi@ae96000 {
4759 compatible = !! 4310 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 4311 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4312 reg-names = "dsi_ctrl";
4763 4313
4764 interrupt-par 4314 interrupt-parent = <&mdss>;
4765 interrupts = !! 4315 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 4316
4767 clocks = <&di 4317 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4318 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4319 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4320 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4321 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4322 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4323 clock-names = "byte",
4774 4324 "byte_intf",
4775 4325 "pixel",
4776 4326 "core",
4777 4327 "iface",
4778 4328 "bus";
4779 assigned-cloc <<
4780 assigned-cloc <<
4781 <<
4782 operating-poi 4329 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4330 power-domains = <&rpmhpd SDM845_CX>;
4784 4331
4785 phys = <&mdss !! 4332 phys = <&dsi1_phy>;
>> 4333 phy-names = "dsi";
4786 4334
4787 status = "dis 4335 status = "disabled";
4788 4336
4789 #address-cell <<
4790 #size-cells = <<
4791 <<
4792 ports { 4337 ports {
4793 #addr 4338 #address-cells = <1>;
4794 #size 4339 #size-cells = <0>;
4795 4340
4796 port@ 4341 port@0 {
4797 4342 reg = <0>;
4798 !! 4343 dsi1_in: endpoint {
4799 4344 remote-endpoint = <&dpu_intf2_out>;
4800 4345 };
4801 }; 4346 };
4802 4347
4803 port@ 4348 port@1 {
4804 4349 reg = <1>;
4805 !! 4350 dsi1_out: endpoint {
4806 4351 };
4807 }; 4352 };
4808 }; 4353 };
4809 }; 4354 };
4810 4355
4811 mdss_dsi1_phy: phy@ae !! 4356 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 4357 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4358 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4359 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4360 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4361 reg-names = "dsi_phy",
4817 " 4362 "dsi_phy_lane",
4818 " 4363 "dsi_pll";
4819 4364
4820 #clock-cells 4365 #clock-cells = <1>;
4821 #phy-cells = 4366 #phy-cells = <0>;
4822 4367
4823 clocks = <&di 4368 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4369 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4370 clock-names = "iface", "ref";
4826 4371
4827 status = "dis 4372 status = "disabled";
4828 }; 4373 };
4829 }; 4374 };
4830 4375
4831 gpu: gpu@5000000 { 4376 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4377 compatible = "qcom,adreno-630.2", "qcom,adreno";
>> 4378 #stream-id-cells = <16>;
4833 4379
4834 reg = <0 0x05000000 0 !! 4380 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4381 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4382
4837 /* 4383 /*
4838 * Look ma, no clocks 4384 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4385 * controlled entirely by the GMU
4840 */ 4386 */
4841 4387
4842 interrupts = <GIC_SPI 4388 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4389
4844 iommus = <&adreno_smm 4390 iommus = <&adreno_smmu 0>;
4845 4391
4846 operating-points-v2 = 4392 operating-points-v2 = <&gpu_opp_table>;
4847 4393
4848 qcom,gmu = <&gmu>; 4394 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4395
4851 interconnects = <&mem 4396 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4397 interconnect-names = "gfx-mem";
4853 4398
4854 status = "disabled"; <<
4855 <<
4856 gpu_opp_table: opp-ta 4399 gpu_opp_table: opp-table {
4857 compatible = 4400 compatible = "operating-points-v2";
4858 4401
4859 opp-710000000 4402 opp-710000000 {
4860 opp-h 4403 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4404 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4405 opp-peak-kBps = <7216000>;
4863 }; 4406 };
4864 4407
4865 opp-675000000 4408 opp-675000000 {
4866 opp-h 4409 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4411 opp-peak-kBps = <7216000>;
4869 }; 4412 };
4870 4413
4871 opp-596000000 4414 opp-596000000 {
4872 opp-h 4415 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4416 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4417 opp-peak-kBps = <6220000>;
4875 }; 4418 };
4876 4419
4877 opp-520000000 4420 opp-520000000 {
4878 opp-h 4421 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4422 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4423 opp-peak-kBps = <6220000>;
4881 }; 4424 };
4882 4425
4883 opp-414000000 4426 opp-414000000 {
4884 opp-h 4427 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4428 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4429 opp-peak-kBps = <4068000>;
4887 }; 4430 };
4888 4431
4889 opp-342000000 4432 opp-342000000 {
4890 opp-h 4433 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4434 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4435 opp-peak-kBps = <2724000>;
4893 }; 4436 };
4894 4437
4895 opp-257000000 4438 opp-257000000 {
4896 opp-h 4439 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4441 opp-peak-kBps = <1648000>;
4899 }; 4442 };
4900 }; 4443 };
4901 }; 4444 };
4902 4445
4903 adreno_smmu: iommu@5040000 { 4446 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4447 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4448 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4449 #iommu-cells = <1>;
4907 #global-interrupts = 4450 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4451 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4452 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4453 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4454 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4455 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4456 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4457 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4458 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4459 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4460 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4461 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4462 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4463 clock-names = "bus", "iface";
4921 4464
4922 power-domains = <&gpu 4465 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4466 };
4924 4467
4925 gmu: gmu@506a000 { 4468 gmu: gmu@506a000 {
4926 compatible = "qcom,ad !! 4469 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4470
4928 reg = <0 0x0506a000 0 !! 4471 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4472 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4473 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4474 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4475
4933 interrupts = <GIC_SPI 4476 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4477 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4478 interrupt-names = "hfi", "gmu";
4936 4479
4937 clocks = <&gpucc GPU_ 4480 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4481 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4482 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4483 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4484 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4485
4943 power-domains = <&gpu 4486 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4487 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4488 power-domain-names = "cx", "gx";
4946 4489
4947 iommus = <&adreno_smm 4490 iommus = <&adreno_smmu 5>;
4948 4491
4949 operating-points-v2 = 4492 operating-points-v2 = <&gmu_opp_table>;
4950 4493
4951 status = "disabled"; <<
4952 <<
4953 gmu_opp_table: opp-ta 4494 gmu_opp_table: opp-table {
4954 compatible = 4495 compatible = "operating-points-v2";
4955 4496
4956 opp-400000000 4497 opp-400000000 {
4957 opp-h 4498 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4499 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4500 };
4960 4501
4961 opp-200000000 4502 opp-200000000 {
4962 opp-h 4503 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4504 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4505 };
4965 }; 4506 };
4966 }; 4507 };
4967 4508
4968 dispcc: clock-controller@af00 4509 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4510 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4511 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4512 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4513 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4514 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4515 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4516 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4517 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4518 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4519 <0>,
4979 <&usb_1_qmpp !! 4520 <0>;
4980 clock-names = "bi_tcx 4521 clock-names = "bi_tcxo",
4981 "gcc_di 4522 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4523 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4524 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4525 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4526 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4527 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4528 "dp_link_clk_divsel_ten",
4988 "dp_vco 4529 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4530 #clock-cells = <1>;
4990 #reset-cells = <1>; 4531 #reset-cells = <1>;
4991 #power-domain-cells = 4532 #power-domain-cells = <1>;
4992 }; 4533 };
4993 4534
4994 pdc_intc: interrupt-controlle 4535 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4536 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4537 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4538 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4539 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4540 interrupt-parent = <&intc>;
5000 interrupt-controller; 4541 interrupt-controller;
5001 }; 4542 };
5002 4543
5003 pdc_reset: reset-controller@b 4544 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4545 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4546 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4547 #reset-cells = <1>;
5007 }; 4548 };
5008 4549
5009 tsens0: thermal-sensor@c26300 4550 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4551 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4552 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4553 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4554 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4555 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4556 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4557 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4558 #thermal-sensor-cells = <1>;
5018 }; 4559 };
5019 4560
5020 tsens1: thermal-sensor@c26500 4561 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4562 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4563 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4564 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4565 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4566 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4567 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4568 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4569 #thermal-sensor-cells = <1>;
5029 }; 4570 };
5030 4571
5031 aoss_reset: reset-controller@ 4572 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4573 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4574 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4575 #reset-cells = <1>;
5035 }; 4576 };
5036 4577
5037 aoss_qmp: power-management@c3 !! 4578 aoss_qmp: power-controller@c300000 {
5038 compatible = "qcom,sd !! 4579 compatible = "qcom,sdm845-aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 4580 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 4581 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4582 mboxes = <&apss_shared 0>;
5042 4583
5043 #clock-cells = <0>; 4584 #clock-cells = <0>;
>> 4585 #power-domain-cells = <1>;
5044 4586
5045 cx_cdev: cx { 4587 cx_cdev: cx {
5046 #cooling-cell 4588 #cooling-cells = <2>;
5047 }; 4589 };
5048 4590
5049 ebi_cdev: ebi { 4591 ebi_cdev: ebi {
5050 #cooling-cell 4592 #cooling-cells = <2>;
5051 }; 4593 };
5052 }; 4594 };
5053 4595
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 4596 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4597 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4598 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4599 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4600 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4601 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4602 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 4603 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 4604 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 4605 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 4606 qcom,ee = <0>;
5070 qcom,channel = <0>; 4607 qcom,channel = <0>;
5071 #address-cells = <2>; 4608 #address-cells = <2>;
5072 #size-cells = <0>; 4609 #size-cells = <0>;
5073 interrupt-controller; 4610 interrupt-controller;
5074 #interrupt-cells = <4 4611 #interrupt-cells = <4>;
>> 4612 cell-index = <0>;
5075 }; 4613 };
5076 4614
5077 sram@146bf000 { !! 4615 imem@146bf000 {
5078 compatible = "qcom,sd !! 4616 compatible = "simple-mfd";
5079 reg = <0 0x146bf000 0 4617 reg = <0 0x146bf000 0 0x1000>;
5080 4618
5081 #address-cells = <1>; 4619 #address-cells = <1>;
5082 #size-cells = <1>; 4620 #size-cells = <1>;
5083 4621
5084 ranges = <0 0 0x146bf 4622 ranges = <0 0 0x146bf000 0x1000>;
5085 4623
5086 pil-reloc@94c { 4624 pil-reloc@94c {
5087 compatible = 4625 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 4626 reg = <0x94c 0xc8>;
5089 }; 4627 };
5090 }; 4628 };
5091 4629
5092 apps_smmu: iommu@15000000 { 4630 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 4631 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 4632 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 4633 #iommu-cells = <2>;
5096 #global-interrupts = 4634 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 4635 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 4636 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 4637 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 4638 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 4639 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 4640 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 4641 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 4642 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 4643 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 4644 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4645 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4646 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 4647 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 4648 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 4649 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 4650 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 4651 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 4652 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 4653 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 4654 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 4655 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 4656 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 4657 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 4658 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 4659 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 4660 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 4661 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 4662 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 4663 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 4664 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 4665 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 4666 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 4667 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 4668 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 4669 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4670 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 4671 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 4672 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 4673 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 4674 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 4675 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4676 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 4677 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 4678 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 4679 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 4680 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 4681 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4682 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 4683 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 4684 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 4685 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 4686 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 4687 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 4688 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 4689 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 4690 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 4691 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 4692 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 4693 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 4694 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 4695 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 4696 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 4697 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 4698 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 4699 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 4700 };
5163 4701
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 4702 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 4703 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 4704 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 4705 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 4706 #clock-cells = <1>;
5241 status = "disabled"; 4707 status = "disabled";
5242 }; 4708 };
5243 4709
5244 gladiator_noc: interconnect@1 4710 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 4711 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 4712 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 4713 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 4714 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 4715 };
5250 4716
5251 watchdog@17980000 { 4717 watchdog@17980000 {
5252 compatible = "qcom,ap 4718 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 4719 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 4720 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI !! 4721 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256 }; 4722 };
5257 4723
5258 apss_shared: mailbox@17990000 4724 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 4725 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 4726 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 4727 #mbox-cells = <1>;
5262 }; 4728 };
5263 4729
5264 apps_rsc: rsc@179c0000 { 4730 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 4731 label = "apps_rsc";
5266 compatible = "qcom,rp 4732 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 4733 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 4734 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 4735 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 4736 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 4737 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 4738 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 4739 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 4740 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 4741 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 4742 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 4743 <SLEEP_TCS 3>,
5278 <WA 4744 <WAKE_TCS 3>,
5279 <CO 4745 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 4746
5282 apps_bcm_voter: bcm-v 4747 apps_bcm_voter: bcm-voter {
5283 compatible = 4748 compatible = "qcom,bcm-voter";
5284 }; 4749 };
5285 4750
5286 rpmhcc: clock-control 4751 rpmhcc: clock-controller {
5287 compatible = 4752 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 4753 #clock-cells = <1>;
5289 clock-names = 4754 clock-names = "xo";
5290 clocks = <&xo 4755 clocks = <&xo_board>;
5291 }; 4756 };
5292 4757
5293 rpmhpd: power-control 4758 rpmhpd: power-controller {
5294 compatible = 4759 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 4760 #power-domain-cells = <1>;
5296 operating-poi 4761 operating-points-v2 = <&rpmhpd_opp_table>;
5297 4762
5298 rpmhpd_opp_ta 4763 rpmhpd_opp_table: opp-table {
5299 compa 4764 compatible = "operating-points-v2";
5300 4765
5301 rpmhp 4766 rpmhpd_opp_ret: opp1 {
5302 4767 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 4768 };
5304 4769
5305 rpmhp 4770 rpmhpd_opp_min_svs: opp2 {
5306 4771 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 4772 };
5308 4773
5309 rpmhp 4774 rpmhpd_opp_low_svs: opp3 {
5310 4775 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 4776 };
5312 4777
5313 rpmhp 4778 rpmhpd_opp_svs: opp4 {
5314 4779 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 4780 };
5316 4781
5317 rpmhp 4782 rpmhpd_opp_svs_l1: opp5 {
5318 4783 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 4784 };
5320 4785
5321 rpmhp 4786 rpmhpd_opp_nom: opp6 {
5322 4787 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 4788 };
5324 4789
5325 rpmhp 4790 rpmhpd_opp_nom_l1: opp7 {
5326 4791 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 4792 };
5328 4793
5329 rpmhp 4794 rpmhpd_opp_nom_l2: opp8 {
5330 4795 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 4796 };
5332 4797
5333 rpmhp 4798 rpmhpd_opp_turbo: opp9 {
5334 4799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 4800 };
5336 4801
5337 rpmhp 4802 rpmhpd_opp_turbo_l1: opp10 {
5338 4803 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 4804 };
5340 }; 4805 };
5341 }; 4806 };
5342 }; 4807 };
5343 4808
5344 intc: interrupt-controller@17 4809 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 4810 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 4811 #address-cells = <2>;
5347 #size-cells = <2>; 4812 #size-cells = <2>;
5348 ranges; 4813 ranges;
5349 #interrupt-cells = <3 4814 #interrupt-cells = <3>;
5350 interrupt-controller; 4815 interrupt-controller;
5351 reg = <0 0x17a00000 0 4816 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 4817 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 4818 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 4819
5355 msi-controller@17a400 4820 msi-controller@17a40000 {
5356 compatible = 4821 compatible = "arm,gic-v3-its";
5357 msi-controlle 4822 msi-controller;
5358 #msi-cells = 4823 #msi-cells = <1>;
5359 reg = <0 0x17 4824 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 4825 status = "disabled";
5361 }; 4826 };
5362 }; 4827 };
5363 4828
5364 slimbam: dma-controller@17184 4829 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba !! 4830 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 4831 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 4832 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; !! 4833 num-channels = <31>;
5369 interrupts = <GIC_SPI 4834 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 4835 #dma-cells = <1>;
5371 qcom,ee = <1>; 4836 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 4837 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 4838 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 4839 };
5375 4840
5376 timer@17c90000 { 4841 timer@17c90000 {
5377 #address-cells = <1>; !! 4842 #address-cells = <2>;
5378 #size-cells = <1>; !! 4843 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 4844 ranges;
5380 compatible = "arm,arm 4845 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 4846 reg = <0 0x17c90000 0 0x1000>;
5382 4847
5383 frame@17ca0000 { 4848 frame@17ca0000 {
5384 frame-number 4849 frame-number = <0>;
5385 interrupts = 4850 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 4851 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 4852 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 4853 <0 0x17cb0000 0 0x1000>;
5389 }; 4854 };
5390 4855
5391 frame@17cc0000 { 4856 frame@17cc0000 {
5392 frame-number 4857 frame-number = <1>;
5393 interrupts = 4858 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 4859 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 4860 status = "disabled";
5396 }; 4861 };
5397 4862
5398 frame@17cd0000 { 4863 frame@17cd0000 {
5399 frame-number 4864 frame-number = <2>;
5400 interrupts = 4865 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 4866 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 4867 status = "disabled";
5403 }; 4868 };
5404 4869
5405 frame@17ce0000 { 4870 frame@17ce0000 {
5406 frame-number 4871 frame-number = <3>;
5407 interrupts = 4872 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 4873 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 4874 status = "disabled";
5410 }; 4875 };
5411 4876
5412 frame@17cf0000 { 4877 frame@17cf0000 {
5413 frame-number 4878 frame-number = <4>;
5414 interrupts = 4879 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 4880 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 4881 status = "disabled";
5417 }; 4882 };
5418 4883
5419 frame@17d00000 { 4884 frame@17d00000 {
5420 frame-number 4885 frame-number = <5>;
5421 interrupts = 4886 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 4887 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 4888 status = "disabled";
5424 }; 4889 };
5425 4890
5426 frame@17d10000 { 4891 frame@17d10000 {
5427 frame-number 4892 frame-number = <6>;
5428 interrupts = 4893 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 4894 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 4895 status = "disabled";
5431 }; 4896 };
5432 }; 4897 };
5433 4898
5434 osm_l3: interconnect@17d41000 4899 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 4900 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 4901 reg = <0 0x17d41000 0 0x1400>;
5437 4902
5438 clocks = <&rpmhcc RPM 4903 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 4904 clock-names = "xo", "alternate";
5440 4905
5441 #interconnect-cells = 4906 #interconnect-cells = <1>;
5442 }; 4907 };
5443 4908
5444 cpufreq_hw: cpufreq@17d43000 4909 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 4910 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 4911 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 4912 reg-names = "freq-domain0", "freq-domain1";
5448 4913
5449 interrupts-extended = <<
5450 <<
5451 clocks = <&rpmhcc RPM 4914 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 4915 clock-names = "xo", "alternate";
5453 4916
5454 #freq-domain-cells = 4917 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 4918 };
5457 4919
5458 wifi: wifi@18800000 { 4920 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 4921 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 4922 status = "disabled";
5461 reg = <0 0x18800000 0 4923 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 4924 reg-names = "membase";
5463 memory-region = <&wla 4925 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 4926 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 4927 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 4928 interrupts =
5467 <GIC_SPI 414 4929 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 4930 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 4931 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 4932 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 4933 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 4934 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 4935 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 4936 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 4937 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 4938 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 4939 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 4940 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 4941 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 4942 };
5481 }; 4943 };
5482 4944
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 4945 thermal-zones {
5487 cpu0-thermal { 4946 cpu0-thermal {
5488 polling-delay-passive 4947 polling-delay-passive = <250>;
>> 4948 polling-delay = <1000>;
5489 4949
5490 thermal-sensors = <&t 4950 thermal-sensors = <&tsens0 1>;
5491 4951
5492 trips { 4952 trips {
5493 cpu0_alert0: 4953 cpu0_alert0: trip-point0 {
5494 tempe 4954 temperature = <90000>;
5495 hyste 4955 hysteresis = <2000>;
5496 type 4956 type = "passive";
5497 }; 4957 };
5498 4958
5499 cpu0_alert1: 4959 cpu0_alert1: trip-point1 {
5500 tempe 4960 temperature = <95000>;
5501 hyste 4961 hysteresis = <2000>;
5502 type 4962 type = "passive";
5503 }; 4963 };
5504 4964
5505 cpu0_crit: cp !! 4965 cpu0_crit: cpu_crit {
5506 tempe 4966 temperature = <110000>;
5507 hyste 4967 hysteresis = <1000>;
5508 type 4968 type = "critical";
5509 }; 4969 };
5510 }; 4970 };
>> 4971
>> 4972 cooling-maps {
>> 4973 map0 {
>> 4974 trip = <&cpu0_alert0>;
>> 4975 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4976 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4977 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4978 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4979 };
>> 4980 map1 {
>> 4981 trip = <&cpu0_alert1>;
>> 4982 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4983 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4984 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4985 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4986 };
>> 4987 };
5511 }; 4988 };
5512 4989
5513 cpu1-thermal { 4990 cpu1-thermal {
5514 polling-delay-passive 4991 polling-delay-passive = <250>;
>> 4992 polling-delay = <1000>;
5515 4993
5516 thermal-sensors = <&t 4994 thermal-sensors = <&tsens0 2>;
5517 4995
5518 trips { 4996 trips {
5519 cpu1_alert0: 4997 cpu1_alert0: trip-point0 {
5520 tempe 4998 temperature = <90000>;
5521 hyste 4999 hysteresis = <2000>;
5522 type 5000 type = "passive";
5523 }; 5001 };
5524 5002
5525 cpu1_alert1: 5003 cpu1_alert1: trip-point1 {
5526 tempe 5004 temperature = <95000>;
5527 hyste 5005 hysteresis = <2000>;
5528 type 5006 type = "passive";
5529 }; 5007 };
5530 5008
5531 cpu1_crit: cp !! 5009 cpu1_crit: cpu_crit {
5532 tempe 5010 temperature = <110000>;
5533 hyste 5011 hysteresis = <1000>;
5534 type 5012 type = "critical";
5535 }; 5013 };
5536 }; 5014 };
>> 5015
>> 5016 cooling-maps {
>> 5017 map0 {
>> 5018 trip = <&cpu1_alert0>;
>> 5019 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5020 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5021 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5022 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5023 };
>> 5024 map1 {
>> 5025 trip = <&cpu1_alert1>;
>> 5026 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5027 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5028 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5029 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5030 };
>> 5031 };
5537 }; 5032 };
5538 5033
5539 cpu2-thermal { 5034 cpu2-thermal {
5540 polling-delay-passive 5035 polling-delay-passive = <250>;
>> 5036 polling-delay = <1000>;
5541 5037
5542 thermal-sensors = <&t 5038 thermal-sensors = <&tsens0 3>;
5543 5039
5544 trips { 5040 trips {
5545 cpu2_alert0: 5041 cpu2_alert0: trip-point0 {
5546 tempe 5042 temperature = <90000>;
5547 hyste 5043 hysteresis = <2000>;
5548 type 5044 type = "passive";
5549 }; 5045 };
5550 5046
5551 cpu2_alert1: 5047 cpu2_alert1: trip-point1 {
5552 tempe 5048 temperature = <95000>;
5553 hyste 5049 hysteresis = <2000>;
5554 type 5050 type = "passive";
5555 }; 5051 };
5556 5052
5557 cpu2_crit: cp !! 5053 cpu2_crit: cpu_crit {
5558 tempe 5054 temperature = <110000>;
5559 hyste 5055 hysteresis = <1000>;
5560 type 5056 type = "critical";
5561 }; 5057 };
5562 }; 5058 };
>> 5059
>> 5060 cooling-maps {
>> 5061 map0 {
>> 5062 trip = <&cpu2_alert0>;
>> 5063 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5064 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5065 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5066 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5067 };
>> 5068 map1 {
>> 5069 trip = <&cpu2_alert1>;
>> 5070 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5071 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5072 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5073 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5074 };
>> 5075 };
5563 }; 5076 };
5564 5077
5565 cpu3-thermal { 5078 cpu3-thermal {
5566 polling-delay-passive 5079 polling-delay-passive = <250>;
>> 5080 polling-delay = <1000>;
5567 5081
5568 thermal-sensors = <&t 5082 thermal-sensors = <&tsens0 4>;
5569 5083
5570 trips { 5084 trips {
5571 cpu3_alert0: 5085 cpu3_alert0: trip-point0 {
5572 tempe 5086 temperature = <90000>;
5573 hyste 5087 hysteresis = <2000>;
5574 type 5088 type = "passive";
5575 }; 5089 };
5576 5090
5577 cpu3_alert1: 5091 cpu3_alert1: trip-point1 {
5578 tempe 5092 temperature = <95000>;
5579 hyste 5093 hysteresis = <2000>;
5580 type 5094 type = "passive";
5581 }; 5095 };
5582 5096
5583 cpu3_crit: cp !! 5097 cpu3_crit: cpu_crit {
5584 tempe 5098 temperature = <110000>;
5585 hyste 5099 hysteresis = <1000>;
5586 type 5100 type = "critical";
5587 }; 5101 };
5588 }; 5102 };
>> 5103
>> 5104 cooling-maps {
>> 5105 map0 {
>> 5106 trip = <&cpu3_alert0>;
>> 5107 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5108 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5109 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5110 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5111 };
>> 5112 map1 {
>> 5113 trip = <&cpu3_alert1>;
>> 5114 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5115 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5116 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5117 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5118 };
>> 5119 };
5589 }; 5120 };
5590 5121
5591 cpu4-thermal { 5122 cpu4-thermal {
5592 polling-delay-passive 5123 polling-delay-passive = <250>;
>> 5124 polling-delay = <1000>;
5593 5125
5594 thermal-sensors = <&t 5126 thermal-sensors = <&tsens0 7>;
5595 5127
5596 trips { 5128 trips {
5597 cpu4_alert0: 5129 cpu4_alert0: trip-point0 {
5598 tempe 5130 temperature = <90000>;
5599 hyste 5131 hysteresis = <2000>;
5600 type 5132 type = "passive";
5601 }; 5133 };
5602 5134
5603 cpu4_alert1: 5135 cpu4_alert1: trip-point1 {
5604 tempe 5136 temperature = <95000>;
5605 hyste 5137 hysteresis = <2000>;
5606 type 5138 type = "passive";
5607 }; 5139 };
5608 5140
5609 cpu4_crit: cp !! 5141 cpu4_crit: cpu_crit {
5610 tempe 5142 temperature = <110000>;
5611 hyste 5143 hysteresis = <1000>;
5612 type 5144 type = "critical";
5613 }; 5145 };
5614 }; 5146 };
>> 5147
>> 5148 cooling-maps {
>> 5149 map0 {
>> 5150 trip = <&cpu4_alert0>;
>> 5151 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5152 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5153 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5154 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5155 };
>> 5156 map1 {
>> 5157 trip = <&cpu4_alert1>;
>> 5158 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5159 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5160 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5161 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5162 };
>> 5163 };
5615 }; 5164 };
5616 5165
5617 cpu5-thermal { 5166 cpu5-thermal {
5618 polling-delay-passive 5167 polling-delay-passive = <250>;
>> 5168 polling-delay = <1000>;
5619 5169
5620 thermal-sensors = <&t 5170 thermal-sensors = <&tsens0 8>;
5621 5171
5622 trips { 5172 trips {
5623 cpu5_alert0: 5173 cpu5_alert0: trip-point0 {
5624 tempe 5174 temperature = <90000>;
5625 hyste 5175 hysteresis = <2000>;
5626 type 5176 type = "passive";
5627 }; 5177 };
5628 5178
5629 cpu5_alert1: 5179 cpu5_alert1: trip-point1 {
5630 tempe 5180 temperature = <95000>;
5631 hyste 5181 hysteresis = <2000>;
5632 type 5182 type = "passive";
5633 }; 5183 };
5634 5184
5635 cpu5_crit: cp !! 5185 cpu5_crit: cpu_crit {
5636 tempe 5186 temperature = <110000>;
5637 hyste 5187 hysteresis = <1000>;
5638 type 5188 type = "critical";
5639 }; 5189 };
5640 }; 5190 };
>> 5191
>> 5192 cooling-maps {
>> 5193 map0 {
>> 5194 trip = <&cpu5_alert0>;
>> 5195 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5196 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5197 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5198 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5199 };
>> 5200 map1 {
>> 5201 trip = <&cpu5_alert1>;
>> 5202 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5203 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5204 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5205 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5206 };
>> 5207 };
5641 }; 5208 };
5642 5209
5643 cpu6-thermal { 5210 cpu6-thermal {
5644 polling-delay-passive 5211 polling-delay-passive = <250>;
>> 5212 polling-delay = <1000>;
5645 5213
5646 thermal-sensors = <&t 5214 thermal-sensors = <&tsens0 9>;
5647 5215
5648 trips { 5216 trips {
5649 cpu6_alert0: 5217 cpu6_alert0: trip-point0 {
5650 tempe 5218 temperature = <90000>;
5651 hyste 5219 hysteresis = <2000>;
5652 type 5220 type = "passive";
5653 }; 5221 };
5654 5222
5655 cpu6_alert1: 5223 cpu6_alert1: trip-point1 {
5656 tempe 5224 temperature = <95000>;
5657 hyste 5225 hysteresis = <2000>;
5658 type 5226 type = "passive";
5659 }; 5227 };
5660 5228
5661 cpu6_crit: cp !! 5229 cpu6_crit: cpu_crit {
5662 tempe 5230 temperature = <110000>;
5663 hyste 5231 hysteresis = <1000>;
5664 type 5232 type = "critical";
5665 }; 5233 };
5666 }; 5234 };
>> 5235
>> 5236 cooling-maps {
>> 5237 map0 {
>> 5238 trip = <&cpu6_alert0>;
>> 5239 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5240 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5241 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5242 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5243 };
>> 5244 map1 {
>> 5245 trip = <&cpu6_alert1>;
>> 5246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5250 };
>> 5251 };
5667 }; 5252 };
5668 5253
5669 cpu7-thermal { 5254 cpu7-thermal {
5670 polling-delay-passive 5255 polling-delay-passive = <250>;
>> 5256 polling-delay = <1000>;
5671 5257
5672 thermal-sensors = <&t 5258 thermal-sensors = <&tsens0 10>;
5673 5259
5674 trips { 5260 trips {
5675 cpu7_alert0: 5261 cpu7_alert0: trip-point0 {
5676 tempe 5262 temperature = <90000>;
5677 hyste 5263 hysteresis = <2000>;
5678 type 5264 type = "passive";
5679 }; 5265 };
5680 5266
5681 cpu7_alert1: 5267 cpu7_alert1: trip-point1 {
5682 tempe 5268 temperature = <95000>;
5683 hyste 5269 hysteresis = <2000>;
5684 type 5270 type = "passive";
5685 }; 5271 };
5686 5272
5687 cpu7_crit: cp !! 5273 cpu7_crit: cpu_crit {
5688 tempe 5274 temperature = <110000>;
5689 hyste 5275 hysteresis = <1000>;
5690 type 5276 type = "critical";
5691 }; 5277 };
5692 }; 5278 };
>> 5279
>> 5280 cooling-maps {
>> 5281 map0 {
>> 5282 trip = <&cpu7_alert0>;
>> 5283 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5284 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5285 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5286 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5287 };
>> 5288 map1 {
>> 5289 trip = <&cpu7_alert1>;
>> 5290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 5293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 5294 };
>> 5295 };
5693 }; 5296 };
5694 5297
5695 aoss0-thermal { 5298 aoss0-thermal {
5696 polling-delay-passive 5299 polling-delay-passive = <250>;
>> 5300 polling-delay = <1000>;
5697 5301
5698 thermal-sensors = <&t 5302 thermal-sensors = <&tsens0 0>;
5699 5303
5700 trips { 5304 trips {
5701 aoss0_alert0: 5305 aoss0_alert0: trip-point0 {
5702 tempe 5306 temperature = <90000>;
5703 hyste 5307 hysteresis = <2000>;
5704 type 5308 type = "hot";
5705 }; 5309 };
5706 }; 5310 };
5707 }; 5311 };
5708 5312
5709 cluster0-thermal { 5313 cluster0-thermal {
5710 polling-delay-passive 5314 polling-delay-passive = <250>;
>> 5315 polling-delay = <1000>;
5711 5316
5712 thermal-sensors = <&t 5317 thermal-sensors = <&tsens0 5>;
5713 5318
5714 trips { 5319 trips {
5715 cluster0_aler 5320 cluster0_alert0: trip-point0 {
5716 tempe 5321 temperature = <90000>;
5717 hyste 5322 hysteresis = <2000>;
5718 type 5323 type = "hot";
5719 }; 5324 };
5720 cluster0_crit !! 5325 cluster0_crit: cluster0_crit {
5721 tempe 5326 temperature = <110000>;
5722 hyste 5327 hysteresis = <2000>;
5723 type 5328 type = "critical";
5724 }; 5329 };
5725 }; 5330 };
5726 }; 5331 };
5727 5332
5728 cluster1-thermal { 5333 cluster1-thermal {
5729 polling-delay-passive 5334 polling-delay-passive = <250>;
>> 5335 polling-delay = <1000>;
5730 5336
5731 thermal-sensors = <&t 5337 thermal-sensors = <&tsens0 6>;
5732 5338
5733 trips { 5339 trips {
5734 cluster1_aler 5340 cluster1_alert0: trip-point0 {
5735 tempe 5341 temperature = <90000>;
5736 hyste 5342 hysteresis = <2000>;
5737 type 5343 type = "hot";
5738 }; 5344 };
5739 cluster1_crit !! 5345 cluster1_crit: cluster1_crit {
5740 tempe 5346 temperature = <110000>;
5741 hyste 5347 hysteresis = <2000>;
5742 type 5348 type = "critical";
5743 }; 5349 };
5744 }; 5350 };
5745 }; 5351 };
5746 5352
5747 gpu-top-thermal { !! 5353 gpu-thermal-top {
5748 polling-delay-passive 5354 polling-delay-passive = <250>;
>> 5355 polling-delay = <1000>;
5749 5356
5750 thermal-sensors = <&t 5357 thermal-sensors = <&tsens0 11>;
5751 5358
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5359 trips {
5760 gpu_top_alert !! 5360 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5361 temperature = <90000>;
5768 hyste !! 5362 hysteresis = <2000>;
5769 type 5363 type = "hot";
5770 }; 5364 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5365 };
5778 }; 5366 };
5779 5367
5780 gpu-bottom-thermal { !! 5368 gpu-thermal-bottom {
5781 polling-delay-passive 5369 polling-delay-passive = <250>;
>> 5370 polling-delay = <1000>;
5782 5371
5783 thermal-sensors = <&t 5372 thermal-sensors = <&tsens0 12>;
5784 5373
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5374 trips {
5793 gpu_bottom_al !! 5375 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5376 temperature = <90000>;
5801 hyste !! 5377 hysteresis = <2000>;
5802 type 5378 type = "hot";
5803 }; 5379 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5380 };
5811 }; 5381 };
5812 5382
5813 aoss1-thermal { 5383 aoss1-thermal {
5814 polling-delay-passive 5384 polling-delay-passive = <250>;
>> 5385 polling-delay = <1000>;
5815 5386
5816 thermal-sensors = <&t 5387 thermal-sensors = <&tsens1 0>;
5817 5388
5818 trips { 5389 trips {
5819 aoss1_alert0: 5390 aoss1_alert0: trip-point0 {
5820 tempe 5391 temperature = <90000>;
5821 hyste 5392 hysteresis = <2000>;
5822 type 5393 type = "hot";
5823 }; 5394 };
5824 }; 5395 };
5825 }; 5396 };
5826 5397
5827 q6-modem-thermal { 5398 q6-modem-thermal {
5828 polling-delay-passive 5399 polling-delay-passive = <250>;
>> 5400 polling-delay = <1000>;
5829 5401
5830 thermal-sensors = <&t 5402 thermal-sensors = <&tsens1 1>;
5831 5403
5832 trips { 5404 trips {
5833 q6_modem_aler 5405 q6_modem_alert0: trip-point0 {
5834 tempe 5406 temperature = <90000>;
5835 hyste 5407 hysteresis = <2000>;
5836 type 5408 type = "hot";
5837 }; 5409 };
5838 }; 5410 };
5839 }; 5411 };
5840 5412
5841 mem-thermal { 5413 mem-thermal {
5842 polling-delay-passive 5414 polling-delay-passive = <250>;
>> 5415 polling-delay = <1000>;
5843 5416
5844 thermal-sensors = <&t 5417 thermal-sensors = <&tsens1 2>;
5845 5418
5846 trips { 5419 trips {
5847 mem_alert0: t 5420 mem_alert0: trip-point0 {
5848 tempe 5421 temperature = <90000>;
5849 hyste 5422 hysteresis = <2000>;
5850 type 5423 type = "hot";
5851 }; 5424 };
5852 }; 5425 };
5853 }; 5426 };
5854 5427
5855 wlan-thermal { 5428 wlan-thermal {
5856 polling-delay-passive 5429 polling-delay-passive = <250>;
>> 5430 polling-delay = <1000>;
5857 5431
5858 thermal-sensors = <&t 5432 thermal-sensors = <&tsens1 3>;
5859 5433
5860 trips { 5434 trips {
5861 wlan_alert0: 5435 wlan_alert0: trip-point0 {
5862 tempe 5436 temperature = <90000>;
5863 hyste 5437 hysteresis = <2000>;
5864 type 5438 type = "hot";
5865 }; 5439 };
5866 }; 5440 };
5867 }; 5441 };
5868 5442
5869 q6-hvx-thermal { 5443 q6-hvx-thermal {
5870 polling-delay-passive 5444 polling-delay-passive = <250>;
>> 5445 polling-delay = <1000>;
5871 5446
5872 thermal-sensors = <&t 5447 thermal-sensors = <&tsens1 4>;
5873 5448
5874 trips { 5449 trips {
5875 q6_hvx_alert0 5450 q6_hvx_alert0: trip-point0 {
5876 tempe 5451 temperature = <90000>;
5877 hyste 5452 hysteresis = <2000>;
5878 type 5453 type = "hot";
5879 }; 5454 };
5880 }; 5455 };
5881 }; 5456 };
5882 5457
5883 camera-thermal { 5458 camera-thermal {
5884 polling-delay-passive 5459 polling-delay-passive = <250>;
>> 5460 polling-delay = <1000>;
5885 5461
5886 thermal-sensors = <&t 5462 thermal-sensors = <&tsens1 5>;
5887 5463
5888 trips { 5464 trips {
5889 camera_alert0 5465 camera_alert0: trip-point0 {
5890 tempe 5466 temperature = <90000>;
5891 hyste 5467 hysteresis = <2000>;
5892 type 5468 type = "hot";
5893 }; 5469 };
5894 }; 5470 };
5895 }; 5471 };
5896 5472
5897 video-thermal { 5473 video-thermal {
5898 polling-delay-passive 5474 polling-delay-passive = <250>;
>> 5475 polling-delay = <1000>;
5899 5476
5900 thermal-sensors = <&t 5477 thermal-sensors = <&tsens1 6>;
5901 5478
5902 trips { 5479 trips {
5903 video_alert0: 5480 video_alert0: trip-point0 {
5904 tempe 5481 temperature = <90000>;
5905 hyste 5482 hysteresis = <2000>;
5906 type 5483 type = "hot";
5907 }; 5484 };
5908 }; 5485 };
5909 }; 5486 };
5910 5487
5911 modem-thermal { 5488 modem-thermal {
5912 polling-delay-passive 5489 polling-delay-passive = <250>;
>> 5490 polling-delay = <1000>;
5913 5491
5914 thermal-sensors = <&t 5492 thermal-sensors = <&tsens1 7>;
5915 5493
5916 trips { 5494 trips {
5917 modem_alert0: 5495 modem_alert0: trip-point0 {
5918 tempe 5496 temperature = <90000>;
5919 hyste 5497 hysteresis = <2000>;
5920 type 5498 type = "hot";
5921 }; 5499 };
5922 }; 5500 };
5923 }; 5501 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5502 };
5933 }; 5503 };
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