1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 16 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 17 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 18 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 19 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 20 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 21 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 22 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 23 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 25 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 26 #include <dt-bindings/thermal/thermal.h>
31 27
32 / { 28 / {
33 interrupt-parent = <&intc>; 29 interrupt-parent = <&intc>;
34 30
35 #address-cells = <2>; 31 #address-cells = <2>;
36 #size-cells = <2>; 32 #size-cells = <2>;
37 33
38 aliases { 34 aliases {
39 i2c0 = &i2c0; 35 i2c0 = &i2c0;
40 i2c1 = &i2c1; 36 i2c1 = &i2c1;
41 i2c2 = &i2c2; 37 i2c2 = &i2c2;
42 i2c3 = &i2c3; 38 i2c3 = &i2c3;
43 i2c4 = &i2c4; 39 i2c4 = &i2c4;
44 i2c5 = &i2c5; 40 i2c5 = &i2c5;
45 i2c6 = &i2c6; 41 i2c6 = &i2c6;
46 i2c7 = &i2c7; 42 i2c7 = &i2c7;
47 i2c8 = &i2c8; 43 i2c8 = &i2c8;
48 i2c9 = &i2c9; 44 i2c9 = &i2c9;
49 i2c10 = &i2c10; 45 i2c10 = &i2c10;
50 i2c11 = &i2c11; 46 i2c11 = &i2c11;
51 i2c12 = &i2c12; 47 i2c12 = &i2c12;
52 i2c13 = &i2c13; 48 i2c13 = &i2c13;
53 i2c14 = &i2c14; 49 i2c14 = &i2c14;
54 i2c15 = &i2c15; 50 i2c15 = &i2c15;
55 spi0 = &spi0; 51 spi0 = &spi0;
56 spi1 = &spi1; 52 spi1 = &spi1;
57 spi2 = &spi2; 53 spi2 = &spi2;
58 spi3 = &spi3; 54 spi3 = &spi3;
59 spi4 = &spi4; 55 spi4 = &spi4;
60 spi5 = &spi5; 56 spi5 = &spi5;
61 spi6 = &spi6; 57 spi6 = &spi6;
62 spi7 = &spi7; 58 spi7 = &spi7;
63 spi8 = &spi8; 59 spi8 = &spi8;
64 spi9 = &spi9; 60 spi9 = &spi9;
65 spi10 = &spi10; 61 spi10 = &spi10;
66 spi11 = &spi11; 62 spi11 = &spi11;
67 spi12 = &spi12; 63 spi12 = &spi12;
68 spi13 = &spi13; 64 spi13 = &spi13;
69 spi14 = &spi14; 65 spi14 = &spi14;
70 spi15 = &spi15; 66 spi15 = &spi15;
71 }; 67 };
72 68
73 chosen { }; 69 chosen { };
74 70
75 clocks { !! 71 memory@80000000 {
76 xo_board: xo-board { !! 72 device_type = "memory";
77 compatible = "fixed-cl !! 73 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 74 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 75 };
80 clock-output-names = " !! 76
>> 77 reserved-memory {
>> 78 #address-cells = <2>;
>> 79 #size-cells = <2>;
>> 80 ranges;
>> 81
>> 82 hyp_mem: memory@85700000 {
>> 83 reg = <0 0x85700000 0 0x600000>;
>> 84 no-map;
81 }; 85 };
82 86
83 sleep_clk: sleep-clk { !! 87 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 88 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 89 no-map;
86 clock-frequency = <327 !! 90 };
>> 91
>> 92 aop_mem: memory@85fc0000 {
>> 93 reg = <0 0x85fc0000 0 0x20000>;
>> 94 no-map;
>> 95 };
>> 96
>> 97 aop_cmd_db_mem: memory@85fe0000 {
>> 98 compatible = "qcom,cmd-db";
>> 99 reg = <0x0 0x85fe0000 0 0x20000>;
>> 100 no-map;
>> 101 };
>> 102
>> 103 smem@86000000 {
>> 104 compatible = "qcom,smem";
>> 105 reg = <0x0 0x86000000 0 0x200000>;
>> 106 no-map;
>> 107 hwlocks = <&tcsr_mutex 3>;
>> 108 };
>> 109
>> 110 tz_mem: memory@86200000 {
>> 111 reg = <0 0x86200000 0 0x2d00000>;
>> 112 no-map;
>> 113 };
>> 114
>> 115 rmtfs_mem: memory@88f00000 {
>> 116 compatible = "qcom,rmtfs-mem";
>> 117 reg = <0 0x88f00000 0 0x200000>;
>> 118 no-map;
>> 119
>> 120 qcom,client-id = <1>;
>> 121 qcom,vmid = <15>;
>> 122 };
>> 123
>> 124 qseecom_mem: memory@8ab00000 {
>> 125 reg = <0 0x8ab00000 0 0x1400000>;
>> 126 no-map;
>> 127 };
>> 128
>> 129 camera_mem: memory@8bf00000 {
>> 130 reg = <0 0x8bf00000 0 0x500000>;
>> 131 no-map;
>> 132 };
>> 133
>> 134 ipa_fw_mem: memory@8c400000 {
>> 135 reg = <0 0x8c400000 0 0x10000>;
>> 136 no-map;
>> 137 };
>> 138
>> 139 ipa_gsi_mem: memory@8c410000 {
>> 140 reg = <0 0x8c410000 0 0x5000>;
>> 141 no-map;
>> 142 };
>> 143
>> 144 gpu_mem: memory@8c415000 {
>> 145 reg = <0 0x8c415000 0 0x2000>;
>> 146 no-map;
>> 147 };
>> 148
>> 149 adsp_mem: memory@8c500000 {
>> 150 reg = <0 0x8c500000 0 0x1a00000>;
>> 151 no-map;
>> 152 };
>> 153
>> 154 wlan_msa_mem: memory@8df00000 {
>> 155 reg = <0 0x8df00000 0 0x100000>;
>> 156 no-map;
>> 157 };
>> 158
>> 159 mpss_region: memory@8e000000 {
>> 160 reg = <0 0x8e000000 0 0x7800000>;
>> 161 no-map;
>> 162 };
>> 163
>> 164 venus_mem: memory@95800000 {
>> 165 reg = <0 0x95800000 0 0x500000>;
>> 166 no-map;
>> 167 };
>> 168
>> 169 cdsp_mem: memory@95d00000 {
>> 170 reg = <0 0x95d00000 0 0x800000>;
>> 171 no-map;
>> 172 };
>> 173
>> 174 mba_region: memory@96500000 {
>> 175 reg = <0 0x96500000 0 0x200000>;
>> 176 no-map;
>> 177 };
>> 178
>> 179 slpi_mem: memory@96700000 {
>> 180 reg = <0 0x96700000 0 0x1400000>;
>> 181 no-map;
>> 182 };
>> 183
>> 184 spss_mem: memory@97b00000 {
>> 185 reg = <0 0x97b00000 0 0x100000>;
>> 186 no-map;
87 }; 187 };
88 }; 188 };
89 189
90 cpus: cpus { !! 190 cpus {
91 #address-cells = <2>; 191 #address-cells = <2>;
92 #size-cells = <0>; 192 #size-cells = <0>;
93 193
94 CPU0: cpu@0 { 194 CPU0: cpu@0 {
95 device_type = "cpu"; 195 device_type = "cpu";
96 compatible = "qcom,kry 196 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 197 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 198 enable-method = "psci";
100 capacity-dmips-mhz = < !! 199 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101 dynamic-power-coeffici !! 200 &LITTLE_CPU_SLEEP_1
>> 201 &CLUSTER_SLEEP_0>;
>> 202 capacity-dmips-mhz = <607>;
>> 203 dynamic-power-coefficient = <100>;
102 qcom,freq-domain = <&c 204 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 205 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 206 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 207 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 208 #cooling-cells = <2>;
109 next-level-cache = <&L 209 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 210 L2_0: l2-cache {
111 compatible = " 211 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 212 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 213 L3_0: l3-cache {
116 compat !! 214 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 215 };
120 }; 216 };
121 }; 217 };
122 218
123 CPU1: cpu@100 { 219 CPU1: cpu@100 {
124 device_type = "cpu"; 220 device_type = "cpu";
125 compatible = "qcom,kry 221 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 222 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 223 enable-method = "psci";
129 capacity-dmips-mhz = < !! 224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130 dynamic-power-coeffici !! 225 &LITTLE_CPU_SLEEP_1
>> 226 &CLUSTER_SLEEP_0>;
>> 227 capacity-dmips-mhz = <607>;
>> 228 dynamic-power-coefficient = <100>;
131 qcom,freq-domain = <&c 229 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 230 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 231 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 233 #cooling-cells = <2>;
138 next-level-cache = <&L 234 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 235 L2_100: l2-cache {
140 compatible = " 236 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 237 next-level-cache = <&L3_0>;
144 }; 238 };
145 }; 239 };
146 240
147 CPU2: cpu@200 { 241 CPU2: cpu@200 {
148 device_type = "cpu"; 242 device_type = "cpu";
149 compatible = "qcom,kry 243 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 244 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 245 enable-method = "psci";
153 capacity-dmips-mhz = < !! 246 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154 dynamic-power-coeffici !! 247 &LITTLE_CPU_SLEEP_1
>> 248 &CLUSTER_SLEEP_0>;
>> 249 capacity-dmips-mhz = <607>;
>> 250 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&c 251 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 252 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 253 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 254 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 255 #cooling-cells = <2>;
162 next-level-cache = <&L 256 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 257 L2_200: l2-cache {
164 compatible = " 258 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 259 next-level-cache = <&L3_0>;
168 }; 260 };
169 }; 261 };
170 262
171 CPU3: cpu@300 { 263 CPU3: cpu@300 {
172 device_type = "cpu"; 264 device_type = "cpu";
173 compatible = "qcom,kry 265 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 266 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 267 enable-method = "psci";
177 capacity-dmips-mhz = < !! 268 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178 dynamic-power-coeffici !! 269 &LITTLE_CPU_SLEEP_1
>> 270 &CLUSTER_SLEEP_0>;
>> 271 capacity-dmips-mhz = <607>;
>> 272 dynamic-power-coefficient = <100>;
179 qcom,freq-domain = <&c 273 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 274 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 277 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 278 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 279 L2_300: l2-cache {
188 compatible = " 280 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 281 next-level-cache = <&L3_0>;
192 }; 282 };
193 }; 283 };
194 284
195 CPU4: cpu@400 { 285 CPU4: cpu@400 {
196 device_type = "cpu"; 286 device_type = "cpu";
197 compatible = "qcom,kry 287 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 288 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 289 enable-method = "psci";
201 capacity-dmips-mhz = < 290 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici !! 291 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 292 &BIG_CPU_SLEEP_1
>> 293 &CLUSTER_SLEEP_0>;
>> 294 dynamic-power-coefficient = <396>;
203 qcom,freq-domain = <&c 295 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 296 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 297 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 298 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 299 #cooling-cells = <2>;
210 next-level-cache = <&L 300 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 301 L2_400: l2-cache {
212 compatible = " 302 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 303 next-level-cache = <&L3_0>;
216 }; 304 };
217 }; 305 };
218 306
219 CPU5: cpu@500 { 307 CPU5: cpu@500 {
220 device_type = "cpu"; 308 device_type = "cpu";
221 compatible = "qcom,kry 309 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 310 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 311 enable-method = "psci";
225 capacity-dmips-mhz = < 312 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici !! 313 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 314 &BIG_CPU_SLEEP_1
>> 315 &CLUSTER_SLEEP_0>;
>> 316 dynamic-power-coefficient = <396>;
227 qcom,freq-domain = <&c 317 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 318 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 319 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 320 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 321 #cooling-cells = <2>;
234 next-level-cache = <&L 322 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 323 L2_500: l2-cache {
236 compatible = " 324 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 325 next-level-cache = <&L3_0>;
240 }; 326 };
241 }; 327 };
242 328
243 CPU6: cpu@600 { 329 CPU6: cpu@600 {
244 device_type = "cpu"; 330 device_type = "cpu";
245 compatible = "qcom,kry 331 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 332 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 333 enable-method = "psci";
249 capacity-dmips-mhz = < 334 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici !! 335 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 336 &BIG_CPU_SLEEP_1
>> 337 &CLUSTER_SLEEP_0>;
>> 338 dynamic-power-coefficient = <396>;
251 qcom,freq-domain = <&c 339 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 340 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 341 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 342 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 343 #cooling-cells = <2>;
258 next-level-cache = <&L 344 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 345 L2_600: l2-cache {
260 compatible = " 346 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 347 next-level-cache = <&L3_0>;
264 }; 348 };
265 }; 349 };
266 350
267 CPU7: cpu@700 { 351 CPU7: cpu@700 {
268 device_type = "cpu"; 352 device_type = "cpu";
269 compatible = "qcom,kry 353 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 354 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 355 enable-method = "psci";
273 capacity-dmips-mhz = < 356 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici !! 357 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 358 &BIG_CPU_SLEEP_1
>> 359 &CLUSTER_SLEEP_0>;
>> 360 dynamic-power-coefficient = <396>;
275 qcom,freq-domain = <&c 361 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 362 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 363 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 364 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 365 #cooling-cells = <2>;
282 next-level-cache = <&L 366 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 367 L2_700: l2-cache {
284 compatible = " 368 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 369 next-level-cache = <&L3_0>;
288 }; 370 };
289 }; 371 };
290 372
291 cpu-map { 373 cpu-map {
292 cluster0 { 374 cluster0 {
293 core0 { 375 core0 {
294 cpu = 376 cpu = <&CPU0>;
295 }; 377 };
296 378
297 core1 { 379 core1 {
298 cpu = 380 cpu = <&CPU1>;
299 }; 381 };
300 382
301 core2 { 383 core2 {
302 cpu = 384 cpu = <&CPU2>;
303 }; 385 };
304 386
305 core3 { 387 core3 {
306 cpu = 388 cpu = <&CPU3>;
307 }; 389 };
308 390
309 core4 { 391 core4 {
310 cpu = 392 cpu = <&CPU4>;
311 }; 393 };
312 394
313 core5 { 395 core5 {
314 cpu = 396 cpu = <&CPU5>;
315 }; 397 };
316 398
317 core6 { 399 core6 {
318 cpu = 400 cpu = <&CPU6>;
319 }; 401 };
320 402
321 core7 { 403 core7 {
322 cpu = 404 cpu = <&CPU7>;
323 }; 405 };
324 }; 406 };
325 }; 407 };
326 408
327 cpu_idle_states: idle-states { !! 409 idle-states {
328 entry-method = "psci"; 410 entry-method = "psci";
329 411
330 LITTLE_CPU_SLEEP_0: cp 412 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 413 compatible = "arm,idle-state";
332 idle-state-nam !! 414 idle-state-name = "little-power-down";
333 arm,psci-suspe !! 415 arm,psci-suspend-param = <0x40000003>;
334 entry-latency- 416 entry-latency-us = <350>;
335 exit-latency-u 417 exit-latency-us = <461>;
336 min-residency- 418 min-residency-us = <1890>;
337 local-timer-st 419 local-timer-stop;
338 }; 420 };
339 421
340 BIG_CPU_SLEEP_0: cpu-s !! 422 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341 compatible = " 423 compatible = "arm,idle-state";
342 idle-state-nam !! 424 idle-state-name = "little-rail-power-down";
343 arm,psci-suspe 425 arm,psci-suspend-param = <0x40000004>;
>> 426 entry-latency-us = <360>;
>> 427 exit-latency-us = <531>;
>> 428 min-residency-us = <3934>;
>> 429 local-timer-stop;
>> 430 };
>> 431
>> 432 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> 433 compatible = "arm,idle-state";
>> 434 idle-state-name = "big-power-down";
>> 435 arm,psci-suspend-param = <0x40000003>;
344 entry-latency- 436 entry-latency-us = <264>;
345 exit-latency-u 437 exit-latency-us = <621>;
346 min-residency- 438 min-residency-us = <952>;
347 local-timer-st 439 local-timer-stop;
348 }; 440 };
349 }; <<
350 441
351 domain-idle-states { !! 442 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
>> 443 compatible = "arm,idle-state";
>> 444 idle-state-name = "big-rail-power-down";
>> 445 arm,psci-suspend-param = <0x40000004>;
>> 446 entry-latency-us = <702>;
>> 447 exit-latency-us = <1061>;
>> 448 min-residency-us = <4488>;
>> 449 local-timer-stop;
>> 450 };
>> 451
352 CLUSTER_SLEEP_0: clust 452 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " !! 453 compatible = "arm,idle-state";
354 arm,psci-suspe !! 454 idle-state-name = "cluster-power-down";
>> 455 arm,psci-suspend-param = <0x400000F4>;
355 entry-latency- 456 entry-latency-us = <3263>;
356 exit-latency-u 457 exit-latency-us = <6562>;
357 min-residency- 458 min-residency-us = <9987>;
>> 459 local-timer-stop;
358 }; 460 };
359 }; 461 };
360 }; 462 };
361 463
362 firmware { !! 464 cpu0_opp_table: cpu0_opp_table {
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points 465 compatible = "operating-points-v2";
376 opp-shared; 466 opp-shared;
377 467
378 cpu0_opp1: opp-300000000 { 468 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 469 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 470 opp-peak-kBps = <800000 4800000>;
381 }; 471 };
382 472
383 cpu0_opp2: opp-403200000 { 473 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 474 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 475 opp-peak-kBps = <800000 4800000>;
386 }; 476 };
387 477
388 cpu0_opp3: opp-480000000 { 478 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 479 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 480 opp-peak-kBps = <800000 6451200>;
391 }; 481 };
392 482
393 cpu0_opp4: opp-576000000 { 483 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 484 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 485 opp-peak-kBps = <800000 6451200>;
396 }; 486 };
397 487
398 cpu0_opp5: opp-652800000 { 488 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 489 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 490 opp-peak-kBps = <800000 7680000>;
401 }; 491 };
402 492
403 cpu0_opp6: opp-748800000 { 493 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 494 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 495 opp-peak-kBps = <1804000 9216000>;
406 }; 496 };
407 497
408 cpu0_opp7: opp-825600000 { 498 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 499 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 500 opp-peak-kBps = <1804000 9216000>;
411 }; 501 };
412 502
413 cpu0_opp8: opp-902400000 { 503 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 504 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 505 opp-peak-kBps = <1804000 10444800>;
416 }; 506 };
417 507
418 cpu0_opp9: opp-979200000 { 508 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 509 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 510 opp-peak-kBps = <1804000 11980800>;
421 }; 511 };
422 512
423 cpu0_opp10: opp-1056000000 { 513 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 514 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 515 opp-peak-kBps = <1804000 11980800>;
426 }; 516 };
427 517
428 cpu0_opp11: opp-1132800000 { 518 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 519 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 520 opp-peak-kBps = <2188000 13516800>;
431 }; 521 };
432 522
433 cpu0_opp12: opp-1228800000 { 523 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 524 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 525 opp-peak-kBps = <2188000 15052800>;
436 }; 526 };
437 527
438 cpu0_opp13: opp-1324800000 { 528 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 529 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 530 opp-peak-kBps = <2188000 16588800>;
441 }; 531 };
442 532
443 cpu0_opp14: opp-1420800000 { 533 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 534 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 535 opp-peak-kBps = <3072000 18124800>;
446 }; 536 };
447 537
448 cpu0_opp15: opp-1516800000 { 538 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 539 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 540 opp-peak-kBps = <3072000 19353600>;
451 }; 541 };
452 542
453 cpu0_opp16: opp-1612800000 { 543 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 544 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 545 opp-peak-kBps = <4068000 19353600>;
456 }; 546 };
457 547
458 cpu0_opp17: opp-1689600000 { 548 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 549 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 550 opp-peak-kBps = <4068000 20889600>;
461 }; 551 };
462 552
463 cpu0_opp18: opp-1766400000 { 553 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 554 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 555 opp-peak-kBps = <4068000 22425600>;
466 }; 556 };
467 }; 557 };
468 558
469 cpu4_opp_table: opp-table-cpu4 { !! 559 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 560 compatible = "operating-points-v2";
471 opp-shared; 561 opp-shared;
472 562
473 cpu4_opp1: opp-300000000 { 563 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 564 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 565 opp-peak-kBps = <800000 4800000>;
476 }; 566 };
477 567
478 cpu4_opp2: opp-403200000 { 568 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 569 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 570 opp-peak-kBps = <800000 4800000>;
481 }; 571 };
482 572
483 cpu4_opp3: opp-480000000 { 573 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 574 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 575 opp-peak-kBps = <1804000 4800000>;
486 }; 576 };
487 577
488 cpu4_opp4: opp-576000000 { 578 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 579 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 580 opp-peak-kBps = <1804000 4800000>;
491 }; 581 };
492 582
493 cpu4_opp5: opp-652800000 { 583 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 584 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 585 opp-peak-kBps = <1804000 4800000>;
496 }; 586 };
497 587
498 cpu4_opp6: opp-748800000 { 588 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 589 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 590 opp-peak-kBps = <1804000 4800000>;
501 }; 591 };
502 592
503 cpu4_opp7: opp-825600000 { 593 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 594 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 595 opp-peak-kBps = <2188000 9216000>;
506 }; 596 };
507 597
508 cpu4_opp8: opp-902400000 { 598 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 599 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 600 opp-peak-kBps = <2188000 9216000>;
511 }; 601 };
512 602
513 cpu4_opp9: opp-979200000 { 603 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 604 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 605 opp-peak-kBps = <2188000 9216000>;
516 }; 606 };
517 607
518 cpu4_opp10: opp-1056000000 { 608 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 609 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 610 opp-peak-kBps = <3072000 9216000>;
521 }; 611 };
522 612
523 cpu4_opp11: opp-1132800000 { 613 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 614 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 615 opp-peak-kBps = <3072000 11980800>;
526 }; 616 };
527 617
528 cpu4_opp12: opp-1209600000 { 618 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 619 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 620 opp-peak-kBps = <4068000 11980800>;
531 }; 621 };
532 622
533 cpu4_opp13: opp-1286400000 { 623 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 624 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 625 opp-peak-kBps = <4068000 11980800>;
536 }; 626 };
537 627
538 cpu4_opp14: opp-1363200000 { 628 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 629 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 630 opp-peak-kBps = <4068000 15052800>;
541 }; 631 };
542 632
543 cpu4_opp15: opp-1459200000 { 633 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 634 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 635 opp-peak-kBps = <4068000 15052800>;
546 }; 636 };
547 637
548 cpu4_opp16: opp-1536000000 { 638 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 639 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 640 opp-peak-kBps = <5412000 15052800>;
551 }; 641 };
552 642
553 cpu4_opp17: opp-1612800000 { 643 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 644 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 645 opp-peak-kBps = <5412000 15052800>;
556 }; 646 };
557 647
558 cpu4_opp18: opp-1689600000 { 648 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 649 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 650 opp-peak-kBps = <5412000 19353600>;
561 }; 651 };
562 652
563 cpu4_opp19: opp-1766400000 { 653 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 654 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 655 opp-peak-kBps = <6220000 19353600>;
566 }; 656 };
567 657
568 cpu4_opp20: opp-1843200000 { 658 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 659 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 660 opp-peak-kBps = <6220000 19353600>;
571 }; 661 };
572 662
573 cpu4_opp21: opp-1920000000 { 663 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 664 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 665 opp-peak-kBps = <7216000 19353600>;
576 }; 666 };
577 667
578 cpu4_opp22: opp-1996800000 { 668 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 669 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 670 opp-peak-kBps = <7216000 20889600>;
581 }; 671 };
582 672
583 cpu4_opp23: opp-2092800000 { 673 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 674 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 675 opp-peak-kBps = <7216000 20889600>;
586 }; 676 };
587 677
588 cpu4_opp24: opp-2169600000 { 678 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 679 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 680 opp-peak-kBps = <7216000 20889600>;
591 }; 681 };
592 682
593 cpu4_opp25: opp-2246400000 { 683 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 684 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 685 opp-peak-kBps = <7216000 20889600>;
596 }; 686 };
597 687
598 cpu4_opp26: opp-2323200000 { 688 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 689 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 690 opp-peak-kBps = <7216000 20889600>;
601 }; 691 };
602 692
603 cpu4_opp27: opp-2400000000 { 693 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 694 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 695 opp-peak-kBps = <7216000 22425600>;
606 }; 696 };
607 697
608 cpu4_opp28: opp-2476800000 { 698 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 699 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 700 opp-peak-kBps = <7216000 22425600>;
611 }; 701 };
612 702
613 cpu4_opp29: opp-2553600000 { 703 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 704 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 705 opp-peak-kBps = <7216000 22425600>;
616 }; 706 };
617 707
618 cpu4_opp30: opp-2649600000 { 708 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 709 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 710 opp-peak-kBps = <7216000 22425600>;
621 }; 711 };
622 712
623 cpu4_opp31: opp-2745600000 { 713 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 714 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 715 opp-peak-kBps = <7216000 25497600>;
626 }; 716 };
627 717
628 cpu4_opp32: opp-2803200000 { 718 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 719 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 720 opp-peak-kBps = <7216000 25497600>;
631 }; 721 };
632 }; 722 };
633 723
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 724 pmu {
712 compatible = "arm,armv8-pmuv3" 725 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 726 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 727 };
715 728
716 psci: psci { !! 729 timer {
717 compatible = "arm,psci-1.0"; !! 730 compatible = "arm,armv8-timer";
718 method = "smc"; !! 731 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 732 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 733 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 734 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 735 };
773 736
774 reserved-memory { !! 737 clocks {
775 #address-cells = <2>; !! 738 xo_board: xo-board {
776 #size-cells = <2>; !! 739 compatible = "fixed-clock";
777 ranges; !! 740 #clock-cells = <0>;
778 !! 741 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 742 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 743 };
885 744
886 mdata_mem: mpss-metadata { !! 745 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 746 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 747 #clock-cells = <0>;
889 no-map; !! 748 clock-frequency = <32764>;
890 }; 749 };
>> 750 };
891 751
892 fastrpc_mem: fastrpc { !! 752 firmware {
893 compatible = "shared-d !! 753 scm {
894 alloc-ranges = <0x0 0x !! 754 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 755 };
899 }; 756 };
900 757
901 adsp_pas: remoteproc-adsp { 758 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 759 compatible = "qcom,sdm845-adsp-pas";
903 760
904 interrupts-extended = <&intc G 761 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 762 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 763 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 764 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 765 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 766 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 767 "handover", "stop-ack";
911 768
912 clocks = <&rpmhcc RPMH_CXO_CLK 769 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 770 clock-names = "xo";
914 771
915 memory-region = <&adsp_mem>; 772 memory-region = <&adsp_mem>;
916 773
917 qcom,qmp = <&aoss_qmp>; 774 qcom,qmp = <&aoss_qmp>;
918 775
919 qcom,smem-states = <&adsp_smp2 776 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 777 qcom,smem-state-names = "stop";
921 778
922 status = "disabled"; 779 status = "disabled";
923 780
924 glink-edge { 781 glink-edge {
925 interrupts = <GIC_SPI 782 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 783 label = "lpass";
927 qcom,remote-pid = <2>; 784 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 785 mboxes = <&apss_shared 8>;
929 786
930 apr { 787 apr {
931 compatible = " 788 compatible = "qcom,apr-v2";
932 qcom,glink-cha 789 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = !! 790 qcom,apr-domain = <APR_DOMAIN_ADSP>;
934 #address-cells 791 #address-cells = <1>;
935 #size-cells = 792 #size-cells = <0>;
936 qcom,intents = 793 qcom,intents = <512 20>;
937 794
938 service@3 { !! 795 apr-service@3 {
939 reg = 796 reg = <APR_SVC_ADSP_CORE>;
940 compat 797 compatible = "qcom,q6core";
941 qcom,p 798 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 799 };
943 800
944 q6afe: service !! 801 q6afe: apr-service@4 {
945 compat 802 compatible = "qcom,q6afe";
946 reg = 803 reg = <APR_SVC_AFE>;
947 qcom,p 804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 805 q6afedai: dais {
949 806 compatible = "qcom,q6afe-dais";
950 807 #address-cells = <1>;
951 808 #size-cells = <0>;
952 809 #sound-dai-cells = <1>;
953 }; 810 };
954 }; 811 };
955 812
956 q6asm: service !! 813 q6asm: apr-service@7 {
957 compat 814 compatible = "qcom,q6asm";
958 reg = 815 reg = <APR_SVC_ASM>;
959 qcom,p 816 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 817 q6asmdai: dais {
961 818 compatible = "qcom,q6asm-dais";
962 819 #address-cells = <1>;
963 820 #size-cells = <0>;
964 821 #sound-dai-cells = <1>;
965 822 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 823 };
967 }; 824 };
968 825
969 q6adm: service !! 826 q6adm: apr-service@8 {
970 compat 827 compatible = "qcom,q6adm";
971 reg = 828 reg = <APR_SVC_ADM>;
972 qcom,p 829 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 830 q6routing: routing {
974 831 compatible = "qcom,q6adm-routing";
975 832 #sound-dai-cells = <0>;
976 }; 833 };
977 }; 834 };
978 }; 835 };
979 836
980 fastrpc { 837 fastrpc {
981 compatible = " 838 compatible = "qcom,fastrpc";
982 qcom,glink-cha 839 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 840 label = "adsp";
984 qcom,non-secur <<
985 #address-cells 841 #address-cells = <1>;
986 #size-cells = 842 #size-cells = <0>;
987 843
988 compute-cb@3 { 844 compute-cb@3 {
989 compat 845 compatible = "qcom,fastrpc-compute-cb";
990 reg = 846 reg = <3>;
991 iommus 847 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 848 };
993 849
994 compute-cb@4 { 850 compute-cb@4 {
995 compat 851 compatible = "qcom,fastrpc-compute-cb";
996 reg = 852 reg = <4>;
997 iommus 853 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 854 };
999 }; 855 };
1000 }; 856 };
1001 }; 857 };
1002 858
1003 cdsp_pas: remoteproc-cdsp { 859 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 860 compatible = "qcom,sdm845-cdsp-pas";
1005 861
1006 interrupts-extended = <&intc 862 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 863 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 864 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 865 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 866 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 867 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 868 "handover", "stop-ack";
1013 869
1014 clocks = <&rpmhcc RPMH_CXO_CL 870 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 871 clock-names = "xo";
1016 872
1017 memory-region = <&cdsp_mem>; 873 memory-region = <&cdsp_mem>;
1018 874
1019 qcom,qmp = <&aoss_qmp>; 875 qcom,qmp = <&aoss_qmp>;
1020 876
1021 qcom,smem-states = <&cdsp_smp 877 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 878 qcom,smem-state-names = "stop";
1023 879
1024 status = "disabled"; 880 status = "disabled";
1025 881
1026 glink-edge { 882 glink-edge {
1027 interrupts = <GIC_SPI 883 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 884 label = "turing";
1029 qcom,remote-pid = <5> 885 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 886 mboxes = <&apss_shared 4>;
1031 fastrpc { 887 fastrpc {
1032 compatible = 888 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 889 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 890 label = "cdsp";
1035 qcom,non-secu <<
1036 #address-cell 891 #address-cells = <1>;
1037 #size-cells = 892 #size-cells = <0>;
1038 893
1039 compute-cb@1 894 compute-cb@1 {
1040 compa 895 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 896 reg = <1>;
1042 iommu 897 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 898 };
1044 899
1045 compute-cb@2 900 compute-cb@2 {
1046 compa 901 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 902 reg = <2>;
1048 iommu 903 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 904 };
1050 905
1051 compute-cb@3 906 compute-cb@3 {
1052 compa 907 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 908 reg = <3>;
1054 iommu 909 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 910 };
1056 911
1057 compute-cb@4 912 compute-cb@4 {
1058 compa 913 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 914 reg = <4>;
1060 iommu 915 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 916 };
1062 917
1063 compute-cb@5 918 compute-cb@5 {
1064 compa 919 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 920 reg = <5>;
1066 iommu 921 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 922 };
1068 923
1069 compute-cb@6 924 compute-cb@6 {
1070 compa 925 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 926 reg = <6>;
1072 iommu 927 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 928 };
1074 929
1075 compute-cb@7 930 compute-cb@7 {
1076 compa 931 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 932 reg = <7>;
1078 iommu 933 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 934 };
1080 935
1081 compute-cb@8 936 compute-cb@8 {
1082 compa 937 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 938 reg = <8>;
1084 iommu 939 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 940 };
1086 }; 941 };
1087 }; 942 };
1088 }; 943 };
1089 944
>> 945 tcsr_mutex: hwlock {
>> 946 compatible = "qcom,tcsr-mutex";
>> 947 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 948 #hwlock-cells = <1>;
>> 949 };
>> 950
1090 smp2p-cdsp { 951 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 952 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 953 qcom,smem = <94>, <432>;
1093 954
1094 interrupts = <GIC_SPI 576 IRQ 955 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 956
1096 mboxes = <&apss_shared 6>; 957 mboxes = <&apss_shared 6>;
1097 958
1098 qcom,local-pid = <0>; 959 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 960 qcom,remote-pid = <5>;
1100 961
1101 cdsp_smp2p_out: master-kernel 962 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 963 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 964 #qcom,smem-state-cells = <1>;
1104 }; 965 };
1105 966
1106 cdsp_smp2p_in: slave-kernel { 967 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 968 qcom,entry-name = "slave-kernel";
1108 969
1109 interrupt-controller; 970 interrupt-controller;
1110 #interrupt-cells = <2 971 #interrupt-cells = <2>;
1111 }; 972 };
1112 }; 973 };
1113 974
1114 smp2p-lpass { 975 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 976 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 977 qcom,smem = <443>, <429>;
1117 978
1118 interrupts = <GIC_SPI 158 IRQ 979 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 980
1120 mboxes = <&apss_shared 10>; 981 mboxes = <&apss_shared 10>;
1121 982
1122 qcom,local-pid = <0>; 983 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 984 qcom,remote-pid = <2>;
1124 985
1125 adsp_smp2p_out: master-kernel 986 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 987 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 988 #qcom,smem-state-cells = <1>;
1128 }; 989 };
1129 990
1130 adsp_smp2p_in: slave-kernel { 991 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 992 qcom,entry-name = "slave-kernel";
1132 993
1133 interrupt-controller; 994 interrupt-controller;
1134 #interrupt-cells = <2 995 #interrupt-cells = <2>;
1135 }; 996 };
1136 }; 997 };
1137 998
1138 smp2p-mpss { 999 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 1000 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 1001 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 1002 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 1003 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 1004 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 1005 qcom,remote-pid = <1>;
1145 1006
1146 modem_smp2p_out: master-kerne 1007 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 1008 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 1009 #qcom,smem-state-cells = <1>;
1149 }; 1010 };
1150 1011
1151 modem_smp2p_in: slave-kernel 1012 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 1013 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 1014 interrupt-controller;
1154 #interrupt-cells = <2 1015 #interrupt-cells = <2>;
1155 }; 1016 };
1156 1017
1157 ipa_smp2p_out: ipa-ap-to-mode 1018 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 1019 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 1020 #qcom,smem-state-cells = <1>;
1160 }; 1021 };
1161 1022
1162 ipa_smp2p_in: ipa-modem-to-ap 1023 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1024 qcom,entry-name = "ipa";
1164 interrupt-controller; 1025 interrupt-controller;
1165 #interrupt-cells = <2 1026 #interrupt-cells = <2>;
1166 }; 1027 };
1167 }; 1028 };
1168 1029
1169 smp2p-slpi { 1030 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1031 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1032 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1033 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1034 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1035 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1036 qcom,remote-pid = <3>;
1176 1037
1177 slpi_smp2p_out: master-kernel 1038 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1039 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1040 #qcom,smem-state-cells = <1>;
1180 }; 1041 };
1181 1042
1182 slpi_smp2p_in: slave-kernel { 1043 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1044 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1045 interrupt-controller;
1185 #interrupt-cells = <2 1046 #interrupt-cells = <2>;
1186 }; 1047 };
1187 }; 1048 };
1188 1049
>> 1050 psci {
>> 1051 compatible = "arm,psci-1.0";
>> 1052 method = "smc";
>> 1053 };
>> 1054
1189 soc: soc@0 { 1055 soc: soc@0 {
1190 #address-cells = <2>; 1056 #address-cells = <2>;
1191 #size-cells = <2>; 1057 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1058 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1059 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1060 compatible = "simple-bus";
1195 1061
1196 gcc: clock-controller@100000 1062 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1063 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1064 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1065 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1066 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1067 <&sleep_clk>,
1202 <&pcie0_phy> !! 1068 <&pcie0_lane>,
1203 <&pcie1_phy> !! 1069 <&pcie1_lane>;
1204 clock-names = "bi_tcx 1070 clock-names = "bi_tcxo",
1205 "bi_tcx 1071 "bi_tcxo_ao",
1206 "sleep_ 1072 "sleep_clk",
1207 "pcie_0 1073 "pcie_0_pipe_clk",
1208 "pcie_1 1074 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1075 #clock-cells = <1>;
1210 #reset-cells = <1>; 1076 #reset-cells = <1>;
1211 #power-domain-cells = 1077 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 1078 };
1214 1079
1215 qfprom@784000 { 1080 qfprom@784000 {
1216 compatible = "qcom,sd 1081 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 reg = <0 0x00784000 0 1082 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1083 #address-cells = <1>;
1219 #size-cells = <1>; 1084 #size-cells = <1>;
1220 1085
1221 qusb2p_hstx_trim: hst 1086 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1087 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1088 bits = <1 4>;
1224 }; 1089 };
1225 1090
1226 qusb2s_hstx_trim: hst 1091 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1092 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1093 bits = <6 4>;
1229 }; 1094 };
1230 }; 1095 };
1231 1096
1232 rng: rng@793000 { 1097 rng: rng@793000 {
1233 compatible = "qcom,pr 1098 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1099 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1100 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1101 clock-names = "core";
1237 }; 1102 };
1238 1103
1239 gpi_dma0: dma-controller@8000 !! 1104 qup_opp_table: qup-opp-table {
1240 #dma-cells = <3>; !! 1105 compatible = "operating-points-v2";
1241 compatible = "qcom,sd !! 1106
1242 reg = <0 0x00800000 0 !! 1107 opp-50000000 {
1243 interrupts = <GIC_SPI !! 1108 opp-hz = /bits/ 64 <50000000>;
1244 <GIC_SPI !! 1109 required-opps = <&rpmhpd_opp_min_svs>;
1245 <GIC_SPI !! 1110 };
1246 <GIC_SPI !! 1111
1247 <GIC_SPI !! 1112 opp-75000000 {
1248 <GIC_SPI !! 1113 opp-hz = /bits/ 64 <75000000>;
1249 <GIC_SPI !! 1114 required-opps = <&rpmhpd_opp_low_svs>;
1250 <GIC_SPI !! 1115 };
1251 <GIC_SPI !! 1116
1252 <GIC_SPI !! 1117 opp-100000000 {
1253 <GIC_SPI !! 1118 opp-hz = /bits/ 64 <100000000>;
1254 <GIC_SPI !! 1119 required-opps = <&rpmhpd_opp_svs>;
1255 <GIC_SPI !! 1120 };
1256 dma-channels = <13>; !! 1121
1257 dma-channel-mask = <0 !! 1122 opp-128000000 {
1258 iommus = <&apps_smmu !! 1123 opp-hz = /bits/ 64 <128000000>;
1259 status = "disabled"; !! 1124 required-opps = <&rpmhpd_opp_nom>;
>> 1125 };
1260 }; 1126 };
1261 1127
1262 qupv3_id_0: geniqup@8c0000 { 1128 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1129 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1130 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1131 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1132 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1133 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1134 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1135 #address-cells = <2>;
1270 #size-cells = <2>; 1136 #size-cells = <2>;
1271 ranges; 1137 ranges;
1272 interconnects = <&agg 1138 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1139 interconnect-names = "qup-core";
1274 status = "disabled"; 1140 status = "disabled";
1275 1141
1276 i2c0: i2c@880000 { 1142 i2c0: i2c@880000 {
1277 compatible = 1143 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1144 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1145 clock-names = "se";
1280 clocks = <&gc 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1147 pinctrl-names = "default";
1282 pinctrl-0 = < 1148 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1150 #address-cells = <1>;
1285 #size-cells = 1151 #size-cells = <0>;
1286 power-domains 1152 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1153 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1154 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1156 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1157 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 1158 status = "disabled";
1296 }; 1159 };
1297 1160
1298 spi0: spi@880000 { 1161 spi0: spi@880000 {
1299 compatible = 1162 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1163 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1164 clock-names = "se";
1302 clocks = <&gc 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1166 pinctrl-names = "default";
1304 pinctrl-0 = < 1167 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1168 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1169 #address-cells = <1>;
1307 #size-cells = 1170 #size-cells = <0>;
1308 interconnects 1171 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1172 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1173 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 1174 status = "disabled";
1315 }; 1175 };
1316 1176
1317 uart0: serial@880000 1177 uart0: serial@880000 {
1318 compatible = 1178 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1179 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1180 clock-names = "se";
1321 clocks = <&gc 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1182 pinctrl-names = "default";
1323 pinctrl-0 = < 1183 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1184 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1185 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1186 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1187 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1188 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1189 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1190 status = "disabled";
1331 }; 1191 };
1332 1192
1333 i2c1: i2c@884000 { 1193 i2c1: i2c@884000 {
1334 compatible = 1194 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1195 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1196 clock-names = "se";
1337 clocks = <&gc 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1198 pinctrl-names = "default";
1339 pinctrl-0 = < 1199 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1200 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1201 #address-cells = <1>;
1342 #size-cells = 1202 #size-cells = <0>;
1343 power-domains 1203 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1204 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1205 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1206 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1207 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1208 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 1209 status = "disabled";
1353 }; 1210 };
1354 1211
1355 spi1: spi@884000 { 1212 spi1: spi@884000 {
1356 compatible = 1213 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1214 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1215 clock-names = "se";
1359 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1217 pinctrl-names = "default";
1361 pinctrl-0 = < 1218 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1220 #address-cells = <1>;
1364 #size-cells = 1221 #size-cells = <0>;
1365 interconnects 1222 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1223 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1224 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 1225 status = "disabled";
1372 }; 1226 };
1373 1227
1374 uart1: serial@884000 1228 uart1: serial@884000 {
1375 compatible = 1229 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1230 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1231 clock-names = "se";
1378 clocks = <&gc 1232 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1233 pinctrl-names = "default";
1380 pinctrl-0 = < 1234 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1235 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1236 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1237 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1238 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1239 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1240 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1241 status = "disabled";
1388 }; 1242 };
1389 1243
1390 i2c2: i2c@888000 { 1244 i2c2: i2c@888000 {
1391 compatible = 1245 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1246 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1247 clock-names = "se";
1394 clocks = <&gc 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1249 pinctrl-names = "default";
1396 pinctrl-0 = < 1250 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1251 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1252 #address-cells = <1>;
1399 #size-cells = 1253 #size-cells = <0>;
1400 power-domains 1254 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1255 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1256 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1257 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1258 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1259 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 1260 status = "disabled";
1410 }; 1261 };
1411 1262
1412 spi2: spi@888000 { 1263 spi2: spi@888000 {
1413 compatible = 1264 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1265 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1266 clock-names = "se";
1416 clocks = <&gc 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1268 pinctrl-names = "default";
1418 pinctrl-0 = < 1269 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1270 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1271 #address-cells = <1>;
1421 #size-cells = 1272 #size-cells = <0>;
1422 interconnects 1273 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1274 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1275 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 1276 status = "disabled";
1429 }; 1277 };
1430 1278
1431 uart2: serial@888000 1279 uart2: serial@888000 {
1432 compatible = 1280 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1281 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1282 clock-names = "se";
1435 clocks = <&gc 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1284 pinctrl-names = "default";
1437 pinctrl-0 = < 1285 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1286 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1287 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1288 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1289 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1290 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1291 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1292 status = "disabled";
1445 }; 1293 };
1446 1294
1447 i2c3: i2c@88c000 { 1295 i2c3: i2c@88c000 {
1448 compatible = 1296 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1297 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1298 clock-names = "se";
1451 clocks = <&gc 1299 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1300 pinctrl-names = "default";
1453 pinctrl-0 = < 1301 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1302 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1303 #address-cells = <1>;
1456 #size-cells = 1304 #size-cells = <0>;
1457 power-domains 1305 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1306 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1307 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1308 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1309 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1310 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 1311 status = "disabled";
1467 }; 1312 };
1468 1313
1469 spi3: spi@88c000 { 1314 spi3: spi@88c000 {
1470 compatible = 1315 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1316 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1317 clock-names = "se";
1473 clocks = <&gc 1318 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1319 pinctrl-names = "default";
1475 pinctrl-0 = < 1320 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1321 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1322 #address-cells = <1>;
1478 #size-cells = 1323 #size-cells = <0>;
1479 interconnects 1324 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1325 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1326 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 1327 status = "disabled";
1486 }; 1328 };
1487 1329
1488 uart3: serial@88c000 1330 uart3: serial@88c000 {
1489 compatible = 1331 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1332 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1333 clock-names = "se";
1492 clocks = <&gc 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1335 pinctrl-names = "default";
1494 pinctrl-0 = < 1336 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1337 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1338 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1339 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1340 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1341 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1342 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1343 status = "disabled";
1502 }; 1344 };
1503 1345
1504 i2c4: i2c@890000 { 1346 i2c4: i2c@890000 {
1505 compatible = 1347 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1348 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1349 clock-names = "se";
1508 clocks = <&gc 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1351 pinctrl-names = "default";
1510 pinctrl-0 = < 1352 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1353 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1354 #address-cells = <1>;
1513 #size-cells = 1355 #size-cells = <0>;
1514 power-domains 1356 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1357 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1358 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1359 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1360 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1361 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 1362 status = "disabled";
1524 }; 1363 };
1525 1364
1526 spi4: spi@890000 { 1365 spi4: spi@890000 {
1527 compatible = 1366 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1367 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1368 clock-names = "se";
1530 clocks = <&gc 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1370 pinctrl-names = "default";
1532 pinctrl-0 = < 1371 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1372 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1373 #address-cells = <1>;
1535 #size-cells = 1374 #size-cells = <0>;
1536 interconnects 1375 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1376 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1377 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 1378 status = "disabled";
1543 }; 1379 };
1544 1380
1545 uart4: serial@890000 1381 uart4: serial@890000 {
1546 compatible = 1382 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1383 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1384 clock-names = "se";
1549 clocks = <&gc 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1386 pinctrl-names = "default";
1551 pinctrl-0 = < 1387 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1388 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1389 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1390 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1391 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1392 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1393 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1394 status = "disabled";
1559 }; 1395 };
1560 1396
1561 i2c5: i2c@894000 { 1397 i2c5: i2c@894000 {
1562 compatible = 1398 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1399 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1400 clock-names = "se";
1565 clocks = <&gc 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1402 pinctrl-names = "default";
1567 pinctrl-0 = < 1403 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1404 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1405 #address-cells = <1>;
1570 #size-cells = 1406 #size-cells = <0>;
1571 power-domains 1407 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1408 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1409 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1410 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1411 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1412 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 1413 status = "disabled";
1581 }; 1414 };
1582 1415
1583 spi5: spi@894000 { 1416 spi5: spi@894000 {
1584 compatible = 1417 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1418 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1419 clock-names = "se";
1587 clocks = <&gc 1420 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1421 pinctrl-names = "default";
1589 pinctrl-0 = < 1422 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1423 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1424 #address-cells = <1>;
1592 #size-cells = 1425 #size-cells = <0>;
1593 interconnects 1426 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1427 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1428 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 1429 status = "disabled";
1600 }; 1430 };
1601 1431
1602 uart5: serial@894000 1432 uart5: serial@894000 {
1603 compatible = 1433 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1434 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1435 clock-names = "se";
1606 clocks = <&gc 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1437 pinctrl-names = "default";
1608 pinctrl-0 = < 1438 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1439 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1440 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1441 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1442 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1443 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1444 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1445 status = "disabled";
1616 }; 1446 };
1617 1447
1618 i2c6: i2c@898000 { 1448 i2c6: i2c@898000 {
1619 compatible = 1449 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1450 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1451 clock-names = "se";
1622 clocks = <&gc 1452 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1453 pinctrl-names = "default";
1624 pinctrl-0 = < 1454 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1455 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1456 #address-cells = <1>;
1627 #size-cells = 1457 #size-cells = <0>;
1628 power-domains 1458 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1459 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1460 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1461 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1462 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1463 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 1464 status = "disabled";
1638 }; 1465 };
1639 1466
1640 spi6: spi@898000 { 1467 spi6: spi@898000 {
1641 compatible = 1468 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1469 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1470 clock-names = "se";
1644 clocks = <&gc 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1472 pinctrl-names = "default";
1646 pinctrl-0 = < 1473 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1474 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1475 #address-cells = <1>;
1649 #size-cells = 1476 #size-cells = <0>;
1650 interconnects 1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1479 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 1480 status = "disabled";
1657 }; 1481 };
1658 1482
1659 uart6: serial@898000 1483 uart6: serial@898000 {
1660 compatible = 1484 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1485 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1486 clock-names = "se";
1663 clocks = <&gc 1487 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1488 pinctrl-names = "default";
1665 pinctrl-0 = < 1489 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1490 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1491 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1492 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1493 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1494 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1495 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1496 status = "disabled";
1673 }; 1497 };
1674 1498
1675 i2c7: i2c@89c000 { 1499 i2c7: i2c@89c000 {
1676 compatible = 1500 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1501 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1502 clock-names = "se";
1679 clocks = <&gc 1503 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1504 pinctrl-names = "default";
1681 pinctrl-0 = < 1505 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1506 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1507 #address-cells = <1>;
1684 #size-cells = 1508 #size-cells = <0>;
1685 power-domains 1509 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1510 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1511 status = "disabled";
1688 }; 1512 };
1689 1513
1690 spi7: spi@89c000 { 1514 spi7: spi@89c000 {
1691 compatible = 1515 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1516 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1517 clock-names = "se";
1694 clocks = <&gc 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1519 pinctrl-names = "default";
1696 pinctrl-0 = < 1520 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1521 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1522 #address-cells = <1>;
1699 #size-cells = 1523 #size-cells = <0>;
1700 interconnects 1524 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1525 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1526 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 1527 status = "disabled";
1707 }; 1528 };
1708 1529
1709 uart7: serial@89c000 1530 uart7: serial@89c000 {
1710 compatible = 1531 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1532 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1533 clock-names = "se";
1713 clocks = <&gc 1534 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1535 pinctrl-names = "default";
1715 pinctrl-0 = < 1536 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1537 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1538 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1539 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1540 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1541 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1542 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1543 status = "disabled";
1723 }; 1544 };
1724 }; 1545 };
1725 1546
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 1547 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1548 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1549 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1550 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1551 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1552 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1553 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1554 #address-cells = <2>;
1757 #size-cells = <2>; 1555 #size-cells = <2>;
1758 ranges; 1556 ranges;
1759 interconnects = <&agg 1557 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1558 interconnect-names = "qup-core";
1761 status = "disabled"; 1559 status = "disabled";
1762 1560
1763 i2c8: i2c@a80000 { 1561 i2c8: i2c@a80000 {
1764 compatible = 1562 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1563 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1564 clock-names = "se";
1767 clocks = <&gc 1565 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1566 pinctrl-names = "default";
1769 pinctrl-0 = < 1567 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1568 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1569 #address-cells = <1>;
1772 #size-cells = 1570 #size-cells = <0>;
1773 power-domains 1571 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1572 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1573 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1574 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1575 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1576 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 1577 status = "disabled";
1783 }; 1578 };
1784 1579
1785 spi8: spi@a80000 { 1580 spi8: spi@a80000 {
1786 compatible = 1581 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1582 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1583 clock-names = "se";
1789 clocks = <&gc 1584 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1585 pinctrl-names = "default";
1791 pinctrl-0 = < 1586 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1587 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1588 #address-cells = <1>;
1794 #size-cells = 1589 #size-cells = <0>;
1795 interconnects 1590 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1591 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1592 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 1593 status = "disabled";
1802 }; 1594 };
1803 1595
1804 uart8: serial@a80000 1596 uart8: serial@a80000 {
1805 compatible = 1597 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1598 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1599 clock-names = "se";
1808 clocks = <&gc 1600 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1601 pinctrl-names = "default";
1810 pinctrl-0 = < 1602 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1603 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1604 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1605 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1606 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1607 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1608 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1609 status = "disabled";
1818 }; 1610 };
1819 1611
1820 i2c9: i2c@a84000 { 1612 i2c9: i2c@a84000 {
1821 compatible = 1613 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1614 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1615 clock-names = "se";
1824 clocks = <&gc 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1617 pinctrl-names = "default";
1826 pinctrl-0 = < 1618 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1620 #address-cells = <1>;
1829 #size-cells = 1621 #size-cells = <0>;
1830 power-domains 1622 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1623 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1624 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1625 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1626 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1627 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 1628 status = "disabled";
1840 }; 1629 };
1841 1630
1842 spi9: spi@a84000 { 1631 spi9: spi@a84000 {
1843 compatible = 1632 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1633 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1634 clock-names = "se";
1846 clocks = <&gc 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1636 pinctrl-names = "default";
1848 pinctrl-0 = < 1637 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1638 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1639 #address-cells = <1>;
1851 #size-cells = 1640 #size-cells = <0>;
1852 interconnects 1641 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1642 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1643 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 1644 status = "disabled";
1859 }; 1645 };
1860 1646
1861 uart9: serial@a84000 1647 uart9: serial@a84000 {
1862 compatible = 1648 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1649 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1650 clock-names = "se";
1865 clocks = <&gc 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1652 pinctrl-names = "default";
1867 pinctrl-0 = < 1653 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1654 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1655 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1656 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1657 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1658 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1659 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1660 status = "disabled";
1875 }; 1661 };
1876 1662
1877 i2c10: i2c@a88000 { 1663 i2c10: i2c@a88000 {
1878 compatible = 1664 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1665 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1666 clock-names = "se";
1881 clocks = <&gc 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1668 pinctrl-names = "default";
1883 pinctrl-0 = < 1669 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1670 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1671 #address-cells = <1>;
1886 #size-cells = 1672 #size-cells = <0>;
1887 power-domains 1673 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1674 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1675 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1676 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1677 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1678 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 1679 status = "disabled";
1897 }; 1680 };
1898 1681
1899 spi10: spi@a88000 { 1682 spi10: spi@a88000 {
1900 compatible = 1683 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1684 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1685 clock-names = "se";
1903 clocks = <&gc 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1687 pinctrl-names = "default";
1905 pinctrl-0 = < 1688 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1689 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1690 #address-cells = <1>;
1908 #size-cells = 1691 #size-cells = <0>;
1909 interconnects 1692 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1693 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1694 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1695 status = "disabled";
1916 }; 1696 };
1917 1697
1918 uart10: serial@a88000 1698 uart10: serial@a88000 {
1919 compatible = 1699 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1700 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1701 clock-names = "se";
1922 clocks = <&gc 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1703 pinctrl-names = "default";
1924 pinctrl-0 = < 1704 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1705 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1706 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1707 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1708 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1709 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1710 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1711 status = "disabled";
1932 }; 1712 };
1933 1713
1934 i2c11: i2c@a8c000 { 1714 i2c11: i2c@a8c000 {
1935 compatible = 1715 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1716 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1717 clock-names = "se";
1938 clocks = <&gc 1718 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1719 pinctrl-names = "default";
1940 pinctrl-0 = < 1720 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1721 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1722 #address-cells = <1>;
1943 #size-cells = 1723 #size-cells = <0>;
1944 power-domains 1724 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1725 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1726 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1727 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1728 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1729 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1730 status = "disabled";
1954 }; 1731 };
1955 1732
1956 spi11: spi@a8c000 { 1733 spi11: spi@a8c000 {
1957 compatible = 1734 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1735 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1736 clock-names = "se";
1960 clocks = <&gc 1737 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1738 pinctrl-names = "default";
1962 pinctrl-0 = < 1739 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1740 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1741 #address-cells = <1>;
1965 #size-cells = 1742 #size-cells = <0>;
1966 interconnects 1743 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1744 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1745 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1746 status = "disabled";
1973 }; 1747 };
1974 1748
1975 uart11: serial@a8c000 1749 uart11: serial@a8c000 {
1976 compatible = 1750 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1751 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1752 clock-names = "se";
1979 clocks = <&gc 1753 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1754 pinctrl-names = "default";
1981 pinctrl-0 = < 1755 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1756 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1757 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1758 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1759 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1760 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1761 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1762 status = "disabled";
1989 }; 1763 };
1990 1764
1991 i2c12: i2c@a90000 { 1765 i2c12: i2c@a90000 {
1992 compatible = 1766 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1767 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1768 clock-names = "se";
1995 clocks = <&gc 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1770 pinctrl-names = "default";
1997 pinctrl-0 = < 1771 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1773 #address-cells = <1>;
2000 #size-cells = 1774 #size-cells = <0>;
2001 power-domains 1775 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1776 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 1777 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 1778 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 1779 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 1780 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1781 status = "disabled";
2011 }; 1782 };
2012 1783
2013 spi12: spi@a90000 { 1784 spi12: spi@a90000 {
2014 compatible = 1785 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1786 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1787 clock-names = "se";
2017 clocks = <&gc 1788 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1789 pinctrl-names = "default";
2019 pinctrl-0 = < 1790 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1791 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1792 #address-cells = <1>;
2022 #size-cells = 1793 #size-cells = <0>;
2023 interconnects 1794 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 1795 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 1796 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1797 status = "disabled";
2030 }; 1798 };
2031 1799
2032 uart12: serial@a90000 1800 uart12: serial@a90000 {
2033 compatible = 1801 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1802 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1803 clock-names = "se";
2036 clocks = <&gc 1804 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1805 pinctrl-names = "default";
2038 pinctrl-0 = < 1806 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1807 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1808 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1809 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 1810 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 1811 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 1812 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 1813 status = "disabled";
2046 }; 1814 };
2047 1815
2048 i2c13: i2c@a94000 { 1816 i2c13: i2c@a94000 {
2049 compatible = 1817 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1818 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1819 clock-names = "se";
2052 clocks = <&gc 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1821 pinctrl-names = "default";
2054 pinctrl-0 = < 1822 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1823 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1824 #address-cells = <1>;
2057 #size-cells = 1825 #size-cells = <0>;
2058 power-domains 1826 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1827 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 1828 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 1829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 1830 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 1831 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1832 status = "disabled";
2068 }; 1833 };
2069 1834
2070 spi13: spi@a94000 { 1835 spi13: spi@a94000 {
2071 compatible = 1836 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1837 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1838 clock-names = "se";
2074 clocks = <&gc 1839 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1840 pinctrl-names = "default";
2076 pinctrl-0 = < 1841 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1842 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1843 #address-cells = <1>;
2079 #size-cells = 1844 #size-cells = <0>;
2080 interconnects 1845 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 1846 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 1847 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1848 status = "disabled";
2087 }; 1849 };
2088 1850
2089 uart13: serial@a94000 1851 uart13: serial@a94000 {
2090 compatible = 1852 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1853 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1854 clock-names = "se";
2093 clocks = <&gc 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1856 pinctrl-names = "default";
2095 pinctrl-0 = < 1857 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1858 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 1859 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 1860 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 1861 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 1862 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 1863 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 1864 status = "disabled";
2103 }; 1865 };
2104 1866
2105 i2c14: i2c@a98000 { 1867 i2c14: i2c@a98000 {
2106 compatible = 1868 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1869 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1870 clock-names = "se";
2109 clocks = <&gc 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1872 pinctrl-names = "default";
2111 pinctrl-0 = < 1873 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1874 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1875 #address-cells = <1>;
2114 #size-cells = 1876 #size-cells = <0>;
2115 power-domains 1877 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 1878 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 1879 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 1880 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 1881 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 1882 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1883 status = "disabled";
2125 }; 1884 };
2126 1885
2127 spi14: spi@a98000 { 1886 spi14: spi@a98000 {
2128 compatible = 1887 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1888 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1889 clock-names = "se";
2131 clocks = <&gc 1890 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1891 pinctrl-names = "default";
2133 pinctrl-0 = < 1892 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1893 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1894 #address-cells = <1>;
2136 #size-cells = 1895 #size-cells = <0>;
2137 interconnects 1896 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 1897 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 1898 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1899 status = "disabled";
2144 }; 1900 };
2145 1901
2146 uart14: serial@a98000 1902 uart14: serial@a98000 {
2147 compatible = 1903 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1904 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1905 clock-names = "se";
2150 clocks = <&gc 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1907 pinctrl-names = "default";
2152 pinctrl-0 = < 1908 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1909 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 1910 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 1911 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 1912 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 1913 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 1914 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 1915 status = "disabled";
2160 }; 1916 };
2161 1917
2162 i2c15: i2c@a9c000 { 1918 i2c15: i2c@a9c000 {
2163 compatible = 1919 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1920 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1921 clock-names = "se";
2166 clocks = <&gc 1922 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1923 pinctrl-names = "default";
2168 pinctrl-0 = < 1924 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1925 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1926 #address-cells = <1>;
2171 #size-cells = 1927 #size-cells = <0>;
2172 power-domains 1928 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 1929 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 1930 status = "disabled";
2175 interconnects 1931 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 1932 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 1933 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 1934 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1935 };
2183 1936
2184 spi15: spi@a9c000 { 1937 spi15: spi@a9c000 {
2185 compatible = 1938 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1939 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1940 clock-names = "se";
2188 clocks = <&gc 1941 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1942 pinctrl-names = "default";
2190 pinctrl-0 = < 1943 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1944 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1945 #address-cells = <1>;
2193 #size-cells = 1946 #size-cells = <0>;
2194 interconnects 1947 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 1948 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 1949 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1950 status = "disabled";
2201 }; 1951 };
2202 1952
2203 uart15: serial@a9c000 1953 uart15: serial@a9c000 {
2204 compatible = 1954 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1955 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1956 clock-names = "se";
2207 clocks = <&gc 1957 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1958 pinctrl-names = "default";
2209 pinctrl-0 = < 1959 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1960 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 1961 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 1962 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 1963 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 1964 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 1965 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 1966 status = "disabled";
2217 }; 1967 };
2218 }; 1968 };
2219 1969
2220 llcc: system-cache-controller !! 1970 system-cache-controller@1100000 {
2221 compatible = "qcom,sd 1971 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 1972 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 1973 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 1974 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 1975 };
2229 1976
2230 dma@10a2000 { !! 1977 pcie0: pci@1c00000 {
2231 compatible = "qcom,sd !! 1978 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 1979 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 1980 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 1981 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 1982 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 1983 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 1984 device_type = "pci";
2319 linux,pci-domain = <0 1985 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 1986 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 1987 num-lanes = <1>;
2322 1988
2323 #address-cells = <3>; 1989 #address-cells = <3>;
2324 #size-cells = <2>; 1990 #size-cells = <2>;
2325 1991
2326 ranges = <0x01000000 !! 1992 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327 <0x02000000 !! 1993 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328 1994
2329 interrupts = <GIC_SPI 1995 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 1996 interrupt-names = "msi";
2331 #interrupt-cells = <1 1997 #interrupt-cells = <1>;
2332 interrupt-map-mask = 1998 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 1999 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 2000 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 2001 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 2002 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2003
2338 clocks = <&gcc GCC_PC 2004 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2005 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2006 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2007 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2008 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2009 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2010 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2011 clock-names = "pipe",
2346 "aux", 2012 "aux",
2347 "cfg", 2013 "cfg",
2348 "bus_ma 2014 "bus_master",
2349 "bus_sl 2015 "bus_slave",
2350 "slave_ 2016 "slave_q2a",
2351 "tbu"; 2017 "tbu";
2352 2018
>> 2019 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 2020 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2021 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2022 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2023 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2024 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2025 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2026 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2027 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2028 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2029 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2030 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2031 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2032 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2033 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2034 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2035 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2036
2370 resets = <&gcc GCC_PC 2037 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2038 reset-names = "pci";
2372 2039
2373 power-domains = <&gcc 2040 power-domains = <&gcc PCIE_0_GDSC>;
2374 2041
2375 phys = <&pcie0_phy>; !! 2042 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2043 phy-names = "pciephy";
2377 2044
2378 status = "disabled"; 2045 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2046 };
2390 2047
2391 pcie0_phy: phy@1c06000 { 2048 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2049 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2050 reg = <0 0x01c06000 0 0x18c>;
>> 2051 #address-cells = <2>;
>> 2052 #size-cells = <2>;
>> 2053 ranges;
2394 clocks = <&gcc GCC_PC 2054 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2055 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2056 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2057 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2058 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2059
2410 resets = <&gcc GCC_PC 2060 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2061 reset-names = "phy";
2412 2062
2413 assigned-clocks = <&g 2063 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2064 assigned-clock-rates = <100000000>;
2415 2065
2416 status = "disabled"; 2066 status = "disabled";
>> 2067
>> 2068 pcie0_lane: phy@1c06200 {
>> 2069 reg = <0 0x01c06200 0 0x128>,
>> 2070 <0 0x01c06400 0 0x1fc>,
>> 2071 <0 0x01c06800 0 0x218>,
>> 2072 <0 0x01c06600 0 0x70>;
>> 2073 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2074 clock-names = "pipe0";
>> 2075
>> 2076 #clock-cells = <0>;
>> 2077 #phy-cells = <0>;
>> 2078 clock-output-names = "pcie_0_pipe_clk";
>> 2079 };
2417 }; 2080 };
2418 2081
2419 pcie1: pcie@1c08000 { !! 2082 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc !! 2083 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2421 reg = <0 0x01c08000 0 2084 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2085 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2086 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 2087 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 2088 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 2089 device_type = "pci";
2428 linux,pci-domain = <1 2090 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2091 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2092 num-lanes = <1>;
2431 2093
2432 #address-cells = <3>; 2094 #address-cells = <3>;
2433 #size-cells = <2>; 2095 #size-cells = <2>;
2434 2096
2435 ranges = <0x01000000 !! 2097 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2098 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2099
2438 interrupts = <GIC_SPI 2100 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2101 interrupt-names = "msi";
2440 #interrupt-cells = <1 2102 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2103 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 2104 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 2105 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 2106 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 2107 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2108
2447 clocks = <&gcc GCC_PC 2109 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2110 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2111 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2112 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2113 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2114 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2115 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2116 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2117 clock-names = "pipe",
2456 "aux", 2118 "aux",
2457 "cfg", 2119 "cfg",
2458 "bus_ma 2120 "bus_master",
2459 "bus_sl 2121 "bus_slave",
2460 "slave_ 2122 "slave_q2a",
2461 "ref", 2123 "ref",
2462 "tbu"; 2124 "tbu";
2463 2125
2464 assigned-clocks = <&g 2126 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2127 assigned-clock-rates = <19200000>;
2466 2128
>> 2129 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 2130 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2131 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2132 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2133 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2134 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2135 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2136 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2137 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2138 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2139 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2140 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2141 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2142 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2143 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2144 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2145 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2146
2484 resets = <&gcc GCC_PC 2147 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2148 reset-names = "pci";
2486 2149
2487 power-domains = <&gcc 2150 power-domains = <&gcc PCIE_1_GDSC>;
2488 2151
2489 phys = <&pcie1_phy>; !! 2152 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2153 phy-names = "pciephy";
2491 2154
2492 status = "disabled"; 2155 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2156 };
2504 2157
2505 pcie1_phy: phy@1c0a000 { 2158 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2159 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2160 reg = <0 0x01c0a000 0 0x800>;
>> 2161 #address-cells = <2>;
>> 2162 #size-cells = <2>;
>> 2163 ranges;
2508 clocks = <&gcc GCC_PC 2164 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2165 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2166 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2167 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2168 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2169
2524 resets = <&gcc GCC_PC 2170 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2171 reset-names = "phy";
2526 2172
2527 assigned-clocks = <&g 2173 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2174 assigned-clock-rates = <100000000>;
2529 2175
2530 status = "disabled"; 2176 status = "disabled";
>> 2177
>> 2178 pcie1_lane: phy@1c06200 {
>> 2179 reg = <0 0x01c0a800 0 0x800>,
>> 2180 <0 0x01c0a800 0 0x800>,
>> 2181 <0 0x01c0b800 0 0x400>;
>> 2182 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2183 clock-names = "pipe0";
>> 2184
>> 2185 #clock-cells = <0>;
>> 2186 #phy-cells = <0>;
>> 2187 clock-output-names = "pcie_1_pipe_clk";
>> 2188 };
2531 }; 2189 };
2532 2190
2533 mem_noc: interconnect@1380000 2191 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2192 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2193 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2194 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2195 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2196 };
2539 2197
2540 dc_noc: interconnect@14e0000 2198 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2199 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2200 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2201 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2202 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2203 };
2546 2204
2547 config_noc: interconnect@1500 2205 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2206 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2207 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2208 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2209 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2210 };
2553 2211
2554 system_noc: interconnect@1620 2212 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2213 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2214 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2215 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2216 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2217 };
2560 2218
2561 aggre1_noc: interconnect@16e0 2219 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2220 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2221 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2222 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2223 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2224 };
2567 2225
2568 aggre2_noc: interconnect@1700 2226 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2227 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2228 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2229 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2230 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2231 };
2574 2232
2575 mmss_noc: interconnect@174000 2233 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2234 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2235 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2236 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2237 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2238 };
2581 2239
2582 ufs_mem_hc: ufshc@1d84000 { 2240 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2241 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2242 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2243 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2244 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2245 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2246 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2247 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2248 phy-names = "ufsphy";
2591 lanes-per-direction = 2249 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2250 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2251 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2252 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2253 reset-names = "rst";
2596 2254
2597 iommus = <&apps_smmu 2255 iommus = <&apps_smmu 0x100 0xf>;
2598 2256
2599 clock-names = 2257 clock-names =
2600 "core_clk", 2258 "core_clk",
2601 "bus_aggr_clk 2259 "bus_aggr_clk",
2602 "iface_clk", 2260 "iface_clk",
2603 "core_clk_uni 2261 "core_clk_unipro",
2604 "ref_clk", 2262 "ref_clk",
2605 "tx_lane0_syn 2263 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2264 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2265 "rx_lane1_sync_clk",
2608 "ice_core_clk 2266 "ice_core_clk";
2609 clocks = 2267 clocks =
2610 <&gcc GCC_UFS 2268 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2269 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2270 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2271 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2272 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2273 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2274 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2275 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2276 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2277 freq-table-hz =
2620 operating-points-v2 = !! 2278 <50000000 200000000>,
2621 !! 2279 <0 0>,
2622 interconnects = <&agg !! 2280 <0 0>,
2623 <&gla !! 2281 <37500000 150000000>,
2624 interconnect-names = !! 2282 <0 0>,
>> 2283 <0 0>,
>> 2284 <0 0>,
>> 2285 <0 0>,
>> 2286 <0 300000000>;
2625 2287
2626 status = "disabled"; 2288 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2289 };
2658 2290
2659 ufs_mem_phy: phy@1d87000 { 2291 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2292 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2293 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2294 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2295 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2296 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2297 clock-names = "ref",
2667 "ref_au !! 2298 "ref_aux";
2668 "qref"; !! 2299 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2300 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2301
2672 resets = <&ufs_mem_hc 2302 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2303 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2304 status = "disabled";
>> 2305
>> 2306 ufs_mem_phy_lanes: phy@1d87400 {
>> 2307 reg = <0 0x01d87400 0 0x108>,
>> 2308 <0 0x01d87600 0 0x1e0>,
>> 2309 <0 0x01d87c00 0 0x1dc>,
>> 2310 <0 0x01d87800 0 0x108>,
>> 2311 <0 0x01d87a00 0 0x1e0>;
>> 2312 #phy-cells = <0>;
>> 2313 };
2677 }; 2314 };
2678 2315
2679 cryptobam: dma-controller@1dc 2316 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,ba !! 2317 compatible = "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2318 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2319 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2320 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2321 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2322 #dma-cells = <1>;
2686 qcom,ee = <0>; 2323 qcom,ee = <0>;
2687 qcom,controlled-remot 2324 qcom,controlled-remotely;
2688 iommus = <&apps_smmu 2325 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2326 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2327 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2328 <&apps_smmu 0x716 0x1>;
2692 }; 2329 };
2693 2330
2694 crypto: crypto@1dfa000 { 2331 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2332 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2333 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2334 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2335 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2336 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2337 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2338 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2339 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2340 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2341 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2342 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2343 <&apps_smmu 0x716 0x1>;
2707 }; 2344 };
2708 2345
2709 ipa: ipa@1e40000 { 2346 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2347 compatible = "qcom,sdm845-ipa";
2711 2348
2712 iommus = <&apps_smmu 2349 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2350 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 !! 2351 reg = <0 0x1e40000 0 0x7000>,
2715 <0 0x01e47000 0 !! 2352 <0 0x1e47000 0 0x2000>,
2716 <0 0x01e04000 0 !! 2353 <0 0x1e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2354 reg-names = "ipa-reg",
2718 "ipa-shar 2355 "ipa-shared",
2719 "gsi"; 2356 "gsi";
2720 2357
2721 interrupts-extended = 2358 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2359 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2360 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2361 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2362 interrupt-names = "ipa",
2726 "gs 2363 "gsi",
2727 "ip 2364 "ipa-clock-query",
2728 "ip 2365 "ipa-setup-ready";
2729 2366
2730 clocks = <&rpmhcc RPM 2367 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2368 clock-names = "core";
2732 2369
2733 interconnects = <&agg 2370 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2371 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2372 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2373 interconnect-names = "memory",
2737 2374 "imem",
2738 2375 "config";
2739 2376
2740 qcom,smem-states = <& 2377 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2378 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2379 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2380 "ipa-clock-enabled";
2744 2381
2745 status = "disabled"; 2382 status = "disabled";
2746 }; 2383 };
2747 2384
2748 tcsr_mutex: hwlock@1f40000 { !! 2385 tcsr_mutex_regs: syscon@1f40000 {
2749 compatible = "qcom,tc !! 2386 compatible = "syscon";
2750 reg = <0 0x01f40000 0 !! 2387 reg = <0 0x01f40000 0 0x40000>;
2751 #hwlock-cells = <1>; <<
2752 }; <<
2753 <<
2754 tcsr_regs_1: syscon@1f60000 { <<
2755 compatible = "qcom,sd <<
2756 reg = <0 0x01f60000 0 <<
2757 }; 2388 };
2758 2389
2759 tlmm: pinctrl@3400000 { 2390 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2391 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2392 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2393 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2394 gpio-controller;
2764 #gpio-cells = <2>; 2395 #gpio-cells = <2>;
2765 interrupt-controller; 2396 interrupt-controller;
2766 #interrupt-cells = <2 2397 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2398 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2399 wakeup-parent = <&pdc_intc>;
2769 2400
2770 cci0_default: cci0-de !! 2401 cci0_default: cci0-default {
2771 /* SDA, SCL * 2402 /* SDA, SCL */
2772 pins = "gpio1 2403 pins = "gpio17", "gpio18";
2773 function = "c 2404 function = "cci_i2c";
2774 2405
2775 bias-pull-up; 2406 bias-pull-up;
2776 drive-strengt 2407 drive-strength = <2>; /* 2 mA */
2777 }; 2408 };
2778 2409
2779 cci0_sleep: cci0-slee !! 2410 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2411 /* SDA, SCL */
2781 pins = "gpio1 2412 pins = "gpio17", "gpio18";
2782 function = "c 2413 function = "cci_i2c";
2783 2414
2784 drive-strengt 2415 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2416 bias-pull-down;
2786 }; 2417 };
2787 2418
2788 cci1_default: cci1-de !! 2419 cci1_default: cci1-default {
2789 /* SDA, SCL * 2420 /* SDA, SCL */
2790 pins = "gpio1 2421 pins = "gpio19", "gpio20";
2791 function = "c 2422 function = "cci_i2c";
2792 2423
2793 bias-pull-up; 2424 bias-pull-up;
2794 drive-strengt 2425 drive-strength = <2>; /* 2 mA */
2795 }; 2426 };
2796 2427
2797 cci1_sleep: cci1-slee !! 2428 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2429 /* SDA, SCL */
2799 pins = "gpio1 2430 pins = "gpio19", "gpio20";
2800 function = "c 2431 function = "cci_i2c";
2801 2432
2802 drive-strengt 2433 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2434 bias-pull-down;
2804 }; 2435 };
2805 2436
2806 qspi_clk: qspi-clk-st !! 2437 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2438 pinmux {
2808 function = "q !! 2439 pins = "gpio95";
2809 }; !! 2440 function = "qspi_clk";
2810 !! 2441 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; 2442 };
2820 2443
2821 qspi_data0: qspi-data !! 2444 qspi_cs0: qspi-cs0 {
2822 pins = "gpio9 !! 2445 pinmux {
2823 function = "q !! 2446 pins = "gpio90";
>> 2447 function = "qspi_cs";
>> 2448 };
2824 }; 2449 };
2825 2450
2826 qspi_data1: qspi-data !! 2451 qspi_cs1: qspi-cs1 {
2827 pins = "gpio9 !! 2452 pinmux {
2828 function = "q !! 2453 pins = "gpio89";
>> 2454 function = "qspi_cs";
>> 2455 };
2829 }; 2456 };
2830 2457
2831 qspi_data23: qspi-dat !! 2458 qspi_data01: qspi-data01 {
2832 pins = "gpio9 !! 2459 pinmux-data {
2833 function = "q !! 2460 pins = "gpio91", "gpio92";
>> 2461 function = "qspi_data";
>> 2462 };
2834 }; 2463 };
2835 2464
2836 qup_i2c0_default: qup !! 2465 qspi_data12: qspi-data12 {
2837 pins = "gpio0 !! 2466 pinmux-data {
2838 function = "q !! 2467 pins = "gpio93", "gpio94";
>> 2468 function = "qspi_data";
>> 2469 };
2839 }; 2470 };
2840 2471
2841 qup_i2c1_default: qup !! 2472 qup_i2c0_default: qup-i2c0-default {
2842 pins = "gpio1 !! 2473 pinmux {
2843 function = "q !! 2474 pins = "gpio0", "gpio1";
>> 2475 function = "qup0";
>> 2476 };
2844 }; 2477 };
2845 2478
2846 qup_i2c2_default: qup !! 2479 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio2 !! 2480 pinmux {
2848 function = "q !! 2481 pins = "gpio17", "gpio18";
>> 2482 function = "qup1";
>> 2483 };
2849 }; 2484 };
2850 2485
2851 qup_i2c3_default: qup !! 2486 qup_i2c2_default: qup-i2c2-default {
2852 pins = "gpio4 !! 2487 pinmux {
2853 function = "q !! 2488 pins = "gpio27", "gpio28";
>> 2489 function = "qup2";
>> 2490 };
2854 }; 2491 };
2855 2492
2856 qup_i2c4_default: qup !! 2493 qup_i2c3_default: qup-i2c3-default {
2857 pins = "gpio8 !! 2494 pinmux {
2858 function = "q !! 2495 pins = "gpio41", "gpio42";
>> 2496 function = "qup3";
>> 2497 };
2859 }; 2498 };
2860 2499
2861 qup_i2c5_default: qup !! 2500 qup_i2c4_default: qup-i2c4-default {
2862 pins = "gpio8 !! 2501 pinmux {
2863 function = "q !! 2502 pins = "gpio89", "gpio90";
>> 2503 function = "qup4";
>> 2504 };
2864 }; 2505 };
2865 2506
2866 qup_i2c6_default: qup !! 2507 qup_i2c5_default: qup-i2c5-default {
2867 pins = "gpio4 !! 2508 pinmux {
2868 function = "q !! 2509 pins = "gpio85", "gpio86";
>> 2510 function = "qup5";
>> 2511 };
2869 }; 2512 };
2870 2513
2871 qup_i2c7_default: qup !! 2514 qup_i2c6_default: qup-i2c6-default {
2872 pins = "gpio9 !! 2515 pinmux {
2873 function = "q !! 2516 pins = "gpio45", "gpio46";
>> 2517 function = "qup6";
>> 2518 };
2874 }; 2519 };
2875 2520
2876 qup_i2c8_default: qup !! 2521 qup_i2c7_default: qup-i2c7-default {
2877 pins = "gpio6 !! 2522 pinmux {
2878 function = "q !! 2523 pins = "gpio93", "gpio94";
>> 2524 function = "qup7";
>> 2525 };
2879 }; 2526 };
2880 2527
2881 qup_i2c9_default: qup !! 2528 qup_i2c8_default: qup-i2c8-default {
2882 pins = "gpio6 !! 2529 pinmux {
2883 function = "q !! 2530 pins = "gpio65", "gpio66";
>> 2531 function = "qup8";
>> 2532 };
2884 }; 2533 };
2885 2534
2886 qup_i2c10_default: qu !! 2535 qup_i2c9_default: qup-i2c9-default {
2887 pins = "gpio5 !! 2536 pinmux {
2888 function = "q !! 2537 pins = "gpio6", "gpio7";
>> 2538 function = "qup9";
>> 2539 };
2889 }; 2540 };
2890 2541
2891 qup_i2c11_default: qu !! 2542 qup_i2c10_default: qup-i2c10-default {
2892 pins = "gpio3 !! 2543 pinmux {
2893 function = "q !! 2544 pins = "gpio55", "gpio56";
>> 2545 function = "qup10";
>> 2546 };
2894 }; 2547 };
2895 2548
2896 qup_i2c12_default: qu !! 2549 qup_i2c11_default: qup-i2c11-default {
2897 pins = "gpio4 !! 2550 pinmux {
2898 function = "q !! 2551 pins = "gpio31", "gpio32";
>> 2552 function = "qup11";
>> 2553 };
2899 }; 2554 };
2900 2555
2901 qup_i2c13_default: qu !! 2556 qup_i2c12_default: qup-i2c12-default {
2902 pins = "gpio1 !! 2557 pinmux {
2903 function = "q !! 2558 pins = "gpio49", "gpio50";
>> 2559 function = "qup12";
>> 2560 };
2904 }; 2561 };
2905 2562
2906 qup_i2c14_default: qu !! 2563 qup_i2c13_default: qup-i2c13-default {
2907 pins = "gpio3 !! 2564 pinmux {
2908 function = "q !! 2565 pins = "gpio105", "gpio106";
>> 2566 function = "qup13";
>> 2567 };
2909 }; 2568 };
2910 2569
2911 qup_i2c15_default: qu !! 2570 qup_i2c14_default: qup-i2c14-default {
2912 pins = "gpio8 !! 2571 pinmux {
2913 function = "q !! 2572 pins = "gpio33", "gpio34";
>> 2573 function = "qup14";
>> 2574 };
2914 }; 2575 };
2915 2576
2916 qup_spi0_default: qup !! 2577 qup_i2c15_default: qup-i2c15-default {
2917 pins = "gpio0 !! 2578 pinmux {
2918 function = "q !! 2579 pins = "gpio81", "gpio82";
>> 2580 function = "qup15";
>> 2581 };
2919 }; 2582 };
2920 2583
2921 qup_spi1_default: qup !! 2584 qup_spi0_default: qup-spi0-default {
2922 pins = "gpio1 !! 2585 pinmux {
2923 function = "q !! 2586 pins = "gpio0", "gpio1",
>> 2587 "gpio2", "gpio3";
>> 2588 function = "qup0";
>> 2589 };
2924 }; 2590 };
2925 2591
2926 qup_spi2_default: qup !! 2592 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2593 pinmux {
2928 function = "q !! 2594 pins = "gpio17", "gpio18",
>> 2595 "gpio19", "gpio20";
>> 2596 function = "qup1";
>> 2597 };
2929 }; 2598 };
2930 2599
2931 qup_spi3_default: qup !! 2600 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2601 pinmux {
2933 function = "q !! 2602 pins = "gpio27", "gpio28",
>> 2603 "gpio29", "gpio30";
>> 2604 function = "qup2";
>> 2605 };
2934 }; 2606 };
2935 2607
2936 qup_spi4_default: qup !! 2608 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2609 pinmux {
2938 function = "q !! 2610 pins = "gpio41", "gpio42",
>> 2611 "gpio43", "gpio44";
>> 2612 function = "qup3";
>> 2613 };
2939 }; 2614 };
2940 2615
2941 qup_spi5_default: qup !! 2616 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2617 pinmux {
2943 function = "q !! 2618 pins = "gpio89", "gpio90",
>> 2619 "gpio91", "gpio92";
>> 2620 function = "qup4";
>> 2621 };
2944 }; 2622 };
2945 2623
2946 qup_spi6_default: qup !! 2624 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2625 pinmux {
2948 function = "q !! 2626 pins = "gpio85", "gpio86",
>> 2627 "gpio87", "gpio88";
>> 2628 function = "qup5";
>> 2629 };
2949 }; 2630 };
2950 2631
2951 qup_spi7_default: qup !! 2632 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2633 pinmux {
2953 function = "q !! 2634 pins = "gpio45", "gpio46",
>> 2635 "gpio47", "gpio48";
>> 2636 function = "qup6";
>> 2637 };
2954 }; 2638 };
2955 2639
2956 qup_spi8_default: qup !! 2640 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2641 pinmux {
2958 function = "q !! 2642 pins = "gpio93", "gpio94",
>> 2643 "gpio95", "gpio96";
>> 2644 function = "qup7";
>> 2645 };
2959 }; 2646 };
2960 2647
2961 qup_spi9_default: qup !! 2648 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2649 pinmux {
2963 function = "q !! 2650 pins = "gpio65", "gpio66",
>> 2651 "gpio67", "gpio68";
>> 2652 function = "qup8";
>> 2653 };
2964 }; 2654 };
2965 2655
2966 qup_spi10_default: qu !! 2656 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2657 pinmux {
2968 function = "q !! 2658 pins = "gpio6", "gpio7",
>> 2659 "gpio4", "gpio5";
>> 2660 function = "qup9";
>> 2661 };
2969 }; 2662 };
2970 2663
2971 qup_spi11_default: qu !! 2664 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2665 pinmux {
2973 function = "q !! 2666 pins = "gpio55", "gpio56",
>> 2667 "gpio53", "gpio54";
>> 2668 function = "qup10";
>> 2669 };
2974 }; 2670 };
2975 2671
2976 qup_spi12_default: qu !! 2672 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2673 pinmux {
2978 function = "q !! 2674 pins = "gpio31", "gpio32",
>> 2675 "gpio33", "gpio34";
>> 2676 function = "qup11";
>> 2677 };
2979 }; 2678 };
2980 2679
2981 qup_spi13_default: qu !! 2680 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2681 pinmux {
2983 function = "q !! 2682 pins = "gpio49", "gpio50",
>> 2683 "gpio51", "gpio52";
>> 2684 function = "qup12";
>> 2685 };
2984 }; 2686 };
2985 2687
2986 qup_spi14_default: qu !! 2688 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2689 pinmux {
2988 function = "q !! 2690 pins = "gpio105", "gpio106",
>> 2691 "gpio107", "gpio108";
>> 2692 function = "qup13";
>> 2693 };
2989 }; 2694 };
2990 2695
2991 qup_spi15_default: qu !! 2696 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2697 pinmux {
2993 function = "q !! 2698 pins = "gpio33", "gpio34",
>> 2699 "gpio31", "gpio32";
>> 2700 function = "qup14";
>> 2701 };
2994 }; 2702 };
2995 2703
2996 qup_uart0_default: qu !! 2704 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2705 pinmux {
2998 pins !! 2706 pins = "gpio81", "gpio82",
2999 funct !! 2707 "gpio83", "gpio84";
>> 2708 function = "qup15";
3000 }; 2709 };
>> 2710 };
3001 2711
3002 qup_uart0_rx: !! 2712 qup_uart0_default: qup-uart0-default {
3003 pins !! 2713 pinmux {
>> 2714 pins = "gpio2", "gpio3";
3004 funct 2715 function = "qup0";
3005 }; 2716 };
3006 }; 2717 };
3007 2718
3008 qup_uart1_default: qu !! 2719 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2720 pinmux {
3010 pins !! 2721 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2722 function = "qup1";
3017 }; 2723 };
3018 }; 2724 };
3019 2725
3020 qup_uart2_default: qu !! 2726 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2727 pinmux {
3022 pins !! 2728 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2729 function = "qup2";
3029 }; 2730 };
3030 }; 2731 };
3031 2732
3032 qup_uart3_default: qu !! 2733 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2734 pinmux {
3034 pins !! 2735 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2736 function = "qup3";
3041 }; 2737 };
3042 }; 2738 };
3043 2739
3044 qup_uart3_4pin: qup-u !! 2740 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2741 pinmux {
3046 pins !! 2742 pins = "gpio91", "gpio92";
3047 funct !! 2743 function = "qup4";
3048 }; 2744 };
>> 2745 };
3049 2746
3050 qup_uart3_4pi !! 2747 qup_uart5_default: qup-uart5-default {
3051 pins !! 2748 pinmux {
3052 funct !! 2749 pins = "gpio87", "gpio88";
>> 2750 function = "qup5";
3053 }; 2751 };
>> 2752 };
3054 2753
3055 qup_uart3_4pi !! 2754 qup_uart6_default: qup-uart6-default {
3056 pins !! 2755 pinmux {
3057 funct !! 2756 pins = "gpio47", "gpio48";
>> 2757 function = "qup6";
3058 }; 2758 };
3059 }; 2759 };
3060 2760
3061 qup_uart4_default: qu !! 2761 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 2762 pinmux {
3063 pins !! 2763 pins = "gpio95", "gpio96";
3064 funct !! 2764 function = "qup7";
3065 }; 2765 };
>> 2766 };
3066 2767
3067 qup_uart4_rx: !! 2768 qup_uart8_default: qup-uart8-default {
3068 pins !! 2769 pinmux {
3069 funct !! 2770 pins = "gpio67", "gpio68";
>> 2771 function = "qup8";
3070 }; 2772 };
3071 }; 2773 };
3072 2774
3073 qup_uart5_default: qu !! 2775 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 2776 pinmux {
3075 pins !! 2777 pins = "gpio4", "gpio5";
3076 funct !! 2778 function = "qup9";
3077 }; 2779 };
>> 2780 };
3078 2781
3079 qup_uart5_rx: !! 2782 qup_uart10_default: qup-uart10-default {
3080 pins !! 2783 pinmux {
3081 funct !! 2784 pins = "gpio53", "gpio54";
>> 2785 function = "qup10";
3082 }; 2786 };
3083 }; 2787 };
3084 2788
3085 qup_uart6_default: qu !! 2789 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 2790 pinmux {
3087 pins !! 2791 pins = "gpio33", "gpio34";
3088 funct !! 2792 function = "qup11";
3089 }; 2793 };
>> 2794 };
3090 2795
3091 qup_uart6_rx: !! 2796 qup_uart12_default: qup-uart12-default {
3092 pins !! 2797 pinmux {
3093 funct !! 2798 pins = "gpio51", "gpio52";
>> 2799 function = "qup12";
3094 }; 2800 };
3095 }; 2801 };
3096 2802
3097 qup_uart6_4pin: qup-u !! 2803 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 2804 pinmux {
3099 pins !! 2805 pins = "gpio107", "gpio108";
3100 funct !! 2806 function = "qup13";
3101 bias- <<
3102 }; 2807 };
>> 2808 };
3103 2809
3104 qup_uart6_4pi !! 2810 qup_uart14_default: qup-uart14-default {
3105 pins !! 2811 pinmux {
3106 funct !! 2812 pins = "gpio31", "gpio32";
3107 drive !! 2813 function = "qup14";
3108 bias- <<
3109 }; 2814 };
>> 2815 };
3110 2816
3111 qup_uart6_4pi !! 2817 qup_uart15_default: qup-uart15-default {
3112 pins !! 2818 pinmux {
3113 funct !! 2819 pins = "gpio83", "gpio84";
3114 bias- !! 2820 function = "qup15";
3115 }; 2821 };
3116 }; 2822 };
3117 2823
3118 qup_uart7_default: qu !! 2824 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 2825 mux {
3120 pins !! 2826 pins = "gpio58", "gpio59";
3121 funct !! 2827 function = "gpio";
3122 }; 2828 };
3123 2829
3124 qup_uart7_rx: !! 2830 config {
3125 pins !! 2831 pins = "gpio58", "gpio59";
3126 funct !! 2832 drive-strength = <2>;
>> 2833 bias-pull-down;
>> 2834 input-enable;
3127 }; 2835 };
3128 }; 2836 };
3129 2837
3130 qup_uart8_default: qu !! 2838 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 2839 mux {
3132 pins !! 2840 pins = "gpio58", "gpio59";
3133 funct !! 2841 function = "qua_mi2s";
3134 }; 2842 };
3135 2843
3136 qup_uart8_rx: !! 2844 config {
3137 pins !! 2845 pins = "gpio58", "gpio59";
3138 funct !! 2846 drive-strength = <8>;
>> 2847 bias-disable;
>> 2848 output-high;
3139 }; 2849 };
3140 }; 2850 };
3141 2851
3142 qup_uart9_default: qu !! 2852 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 2853 mux {
3144 pins !! 2854 pins = "gpio60";
3145 funct !! 2855 function = "gpio";
3146 }; 2856 };
3147 2857
3148 qup_uart9_rx: !! 2858 config {
3149 pins !! 2859 pins = "gpio60";
3150 funct !! 2860 drive-strength = <2>;
>> 2861 bias-pull-down;
>> 2862 input-enable;
3151 }; 2863 };
3152 }; 2864 };
3153 2865
3154 qup_uart10_default: q !! 2866 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 2867 mux {
3156 pins !! 2868 pins = "gpio60";
3157 funct !! 2869 function = "qua_mi2s";
3158 }; 2870 };
3159 2871
3160 qup_uart10_rx !! 2872 config {
3161 pins !! 2873 pins = "gpio60";
3162 funct !! 2874 drive-strength = <8>;
>> 2875 bias-disable;
3163 }; 2876 };
3164 }; 2877 };
3165 2878
3166 qup_uart11_default: q !! 2879 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 2880 mux {
3168 pins !! 2881 pins = "gpio61";
3169 funct !! 2882 function = "gpio";
3170 }; 2883 };
3171 2884
3172 qup_uart11_rx !! 2885 config {
3173 pins !! 2886 pins = "gpio61";
3174 funct !! 2887 drive-strength = <2>;
>> 2888 bias-pull-down;
>> 2889 input-enable;
3175 }; 2890 };
3176 }; 2891 };
3177 2892
3178 qup_uart12_default: q !! 2893 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 2894 mux {
3180 pins !! 2895 pins = "gpio61";
3181 funct !! 2896 function = "qua_mi2s";
3182 }; 2897 };
3183 2898
3184 qup_uart12_rx !! 2899 config {
3185 pins !! 2900 pins = "gpio61";
3186 funct !! 2901 drive-strength = <8>;
>> 2902 bias-disable;
3187 }; 2903 };
3188 }; 2904 };
3189 2905
3190 qup_uart13_default: q !! 2906 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 2907 mux {
3192 pins !! 2908 pins = "gpio62";
3193 funct !! 2909 function = "gpio";
3194 }; 2910 };
3195 2911
3196 qup_uart13_rx !! 2912 config {
3197 pins !! 2913 pins = "gpio62";
3198 funct !! 2914 drive-strength = <2>;
>> 2915 bias-pull-down;
>> 2916 input-enable;
3199 }; 2917 };
3200 }; 2918 };
3201 2919
3202 qup_uart14_default: q !! 2920 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 2921 mux {
3204 pins !! 2922 pins = "gpio62";
3205 funct !! 2923 function = "qua_mi2s";
3206 }; 2924 };
3207 2925
3208 qup_uart14_rx !! 2926 config {
3209 pins !! 2927 pins = "gpio62";
3210 funct !! 2928 drive-strength = <8>;
>> 2929 bias-disable;
3211 }; 2930 };
3212 }; 2931 };
3213 2932
3214 qup_uart15_default: q !! 2933 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 2934 mux {
3216 pins !! 2935 pins = "gpio63";
3217 funct !! 2936 function = "gpio";
3218 }; 2937 };
3219 2938
3220 qup_uart15_rx !! 2939 config {
3221 pins !! 2940 pins = "gpio63";
3222 funct !! 2941 drive-strength = <2>;
>> 2942 bias-pull-down;
>> 2943 input-enable;
3223 }; 2944 };
3224 }; 2945 };
3225 2946
3226 quat_mi2s_sleep: quat !! 2947 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 2948 mux {
3228 function = "g !! 2949 pins = "gpio63";
3229 drive-strengt !! 2950 function = "qua_mi2s";
3230 bias-pull-dow !! 2951 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 2952
3290 quat_mi2s_sd3_active: !! 2953 config {
3291 pins = "gpio6 !! 2954 pins = "gpio63";
3292 function = "q !! 2955 drive-strength = <8>;
3293 drive-strengt !! 2956 bias-disable;
3294 bias-disable; !! 2957 };
3295 }; 2958 };
3296 }; 2959 };
3297 2960
3298 mss_pil: remoteproc@4080000 { 2961 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 2962 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 2963 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 2964 reg-names = "qdsp6", "rmb";
3302 2965
3303 interrupts-extended = 2966 interrupts-extended =
3304 <&intc GIC_SP 2967 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 2968 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 2969 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 2970 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 2971 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 2972 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 2973 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 2974 "handover", "stop-ack",
3312 "sh 2975 "shutdown-ack";
3313 2976
3314 clocks = <&gcc GCC_MS 2977 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 2978 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 2979 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 2980 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 2981 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 2982 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 2983 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 2984 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 2985 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 2986 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 2987
3325 qcom,qmp = <&aoss_qmp 2988 qcom,qmp = <&aoss_qmp>;
3326 2989
3327 qcom,smem-states = <& 2990 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 2991 qcom,smem-state-names = "stop";
3329 2992
3330 resets = <&aoss_reset 2993 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 2994 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 2995 reset-names = "mss_restart", "pdc_reset";
3333 2996
3334 qcom,halt-regs = <&tc !! 2997 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 2998
3336 power-domains = <&rpm 2999 power-domains = <&rpmhpd SDM845_CX>,
3337 <&rpm 3000 <&rpmhpd SDM845_MX>,
3338 <&rpm 3001 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = 3002 power-domain-names = "cx", "mx", "mss";
3340 3003
3341 status = "disabled"; 3004 status = "disabled";
3342 3005
3343 mba { 3006 mba {
3344 memory-region 3007 memory-region = <&mba_region>;
3345 }; 3008 };
3346 3009
3347 mpss { 3010 mpss {
3348 memory-region 3011 memory-region = <&mpss_region>;
3349 }; 3012 };
3350 3013
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 3014 glink-edge {
3356 interrupts = 3015 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3016 label = "modem";
3358 qcom,remote-p 3017 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3018 mboxes = <&apss_shared 12>;
3360 }; 3019 };
3361 }; 3020 };
3362 3021
3363 gpucc: clock-controller@50900 3022 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3023 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3024 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3025 #clock-cells = <1>;
3367 #reset-cells = <1>; 3026 #reset-cells = <1>;
3368 #power-domain-cells = 3027 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3028 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3029 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3030 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3031 clock-names = "bi_tcxo",
3373 "gcc_gp 3032 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3033 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3034 };
3376 3035
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 3036 stm@6002000 {
3431 compatible = "arm,cor 3037 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3038 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3039 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3040 reg-names = "stm-base", "stm-stimulus-base";
3435 3041
3436 clocks = <&aoss_qmp>; 3042 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3043 clock-names = "apb_pclk";
3438 3044
3439 out-ports { 3045 out-ports {
3440 port { 3046 port {
3441 stm_o 3047 stm_out: endpoint {
3442 3048 remote-endpoint =
3443 3049 <&funnel0_in7>;
3444 }; 3050 };
3445 }; 3051 };
3446 }; 3052 };
3447 }; 3053 };
3448 3054
3449 funnel@6041000 { 3055 funnel@6041000 {
3450 compatible = "arm,cor 3056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3057 reg = <0 0x06041000 0 0x1000>;
3452 3058
3453 clocks = <&aoss_qmp>; 3059 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3060 clock-names = "apb_pclk";
3455 3061
3456 out-ports { 3062 out-ports {
3457 port { 3063 port {
3458 funne 3064 funnel0_out: endpoint {
3459 3065 remote-endpoint =
3460 3066 <&merge_funnel_in0>;
3461 }; 3067 };
3462 }; 3068 };
3463 }; 3069 };
3464 3070
3465 in-ports { 3071 in-ports {
3466 #address-cell 3072 #address-cells = <1>;
3467 #size-cells = 3073 #size-cells = <0>;
3468 3074
3469 port@7 { 3075 port@7 {
3470 reg = 3076 reg = <7>;
3471 funne 3077 funnel0_in7: endpoint {
3472 3078 remote-endpoint = <&stm_out>;
3473 }; 3079 };
3474 }; 3080 };
3475 }; 3081 };
3476 }; 3082 };
3477 3083
3478 funnel@6043000 { 3084 funnel@6043000 {
3479 compatible = "arm,cor 3085 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3086 reg = <0 0x06043000 0 0x1000>;
3481 3087
3482 clocks = <&aoss_qmp>; 3088 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3089 clock-names = "apb_pclk";
3484 3090
3485 out-ports { 3091 out-ports {
3486 port { 3092 port {
3487 funne 3093 funnel2_out: endpoint {
3488 3094 remote-endpoint =
3489 3095 <&merge_funnel_in2>;
3490 }; 3096 };
3491 }; 3097 };
3492 }; 3098 };
3493 3099
3494 in-ports { 3100 in-ports {
3495 #address-cell 3101 #address-cells = <1>;
3496 #size-cells = 3102 #size-cells = <0>;
3497 3103
3498 port@5 { 3104 port@5 {
3499 reg = 3105 reg = <5>;
3500 funne 3106 funnel2_in5: endpoint {
3501 3107 remote-endpoint =
3502 3108 <&apss_merge_funnel_out>;
3503 }; 3109 };
3504 }; 3110 };
3505 }; 3111 };
3506 }; 3112 };
3507 3113
3508 funnel@6045000 { 3114 funnel@6045000 {
3509 compatible = "arm,cor 3115 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3116 reg = <0 0x06045000 0 0x1000>;
3511 3117
3512 clocks = <&aoss_qmp>; 3118 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3119 clock-names = "apb_pclk";
3514 3120
3515 out-ports { 3121 out-ports {
3516 port { 3122 port {
3517 merge 3123 merge_funnel_out: endpoint {
3518 3124 remote-endpoint = <&etf_in>;
3519 }; 3125 };
3520 }; 3126 };
3521 }; 3127 };
3522 3128
3523 in-ports { 3129 in-ports {
3524 #address-cell 3130 #address-cells = <1>;
3525 #size-cells = 3131 #size-cells = <0>;
3526 3132
3527 port@0 { 3133 port@0 {
3528 reg = 3134 reg = <0>;
3529 merge 3135 merge_funnel_in0: endpoint {
3530 3136 remote-endpoint =
3531 3137 <&funnel0_out>;
3532 }; 3138 };
3533 }; 3139 };
3534 3140
3535 port@2 { 3141 port@2 {
3536 reg = 3142 reg = <2>;
3537 merge 3143 merge_funnel_in2: endpoint {
3538 3144 remote-endpoint =
3539 3145 <&funnel2_out>;
3540 }; 3146 };
3541 }; 3147 };
3542 }; 3148 };
3543 }; 3149 };
3544 3150
3545 replicator@6046000 { 3151 replicator@6046000 {
3546 compatible = "arm,cor 3152 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3153 reg = <0 0x06046000 0 0x1000>;
3548 3154
3549 clocks = <&aoss_qmp>; 3155 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3156 clock-names = "apb_pclk";
3551 3157
3552 out-ports { 3158 out-ports {
3553 port { 3159 port {
3554 repli 3160 replicator_out: endpoint {
3555 3161 remote-endpoint = <&etr_in>;
3556 }; 3162 };
3557 }; 3163 };
3558 }; 3164 };
3559 3165
3560 in-ports { 3166 in-ports {
3561 port { 3167 port {
3562 repli 3168 replicator_in: endpoint {
3563 3169 remote-endpoint = <&etf_out>;
3564 }; 3170 };
3565 }; 3171 };
3566 }; 3172 };
3567 }; 3173 };
3568 3174
3569 etf@6047000 { 3175 etf@6047000 {
3570 compatible = "arm,cor 3176 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3177 reg = <0 0x06047000 0 0x1000>;
3572 3178
3573 clocks = <&aoss_qmp>; 3179 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3180 clock-names = "apb_pclk";
3575 3181
3576 out-ports { 3182 out-ports {
3577 port { 3183 port {
3578 etf_o 3184 etf_out: endpoint {
3579 3185 remote-endpoint =
3580 3186 <&replicator_in>;
3581 }; 3187 };
3582 }; 3188 };
3583 }; 3189 };
3584 3190
3585 in-ports { 3191 in-ports {
>> 3192 #address-cells = <1>;
>> 3193 #size-cells = <0>;
3586 3194
3587 port { !! 3195 port@1 {
>> 3196 reg = <1>;
3588 etf_i 3197 etf_in: endpoint {
3589 3198 remote-endpoint =
3590 3199 <&merge_funnel_out>;
3591 }; 3200 };
3592 }; 3201 };
3593 }; 3202 };
3594 }; 3203 };
3595 3204
3596 etr@6048000 { 3205 etr@6048000 {
3597 compatible = "arm,cor 3206 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3207 reg = <0 0x06048000 0 0x1000>;
3599 3208
3600 clocks = <&aoss_qmp>; 3209 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3210 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3211 arm,scatter-gather;
3603 3212
3604 in-ports { 3213 in-ports {
3605 port { 3214 port {
3606 etr_i 3215 etr_in: endpoint {
3607 3216 remote-endpoint =
3608 3217 <&replicator_out>;
3609 }; 3218 };
3610 }; 3219 };
3611 }; 3220 };
3612 }; 3221 };
3613 3222
3614 etm@7040000 { 3223 etm@7040000 {
3615 compatible = "arm,cor 3224 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3225 reg = <0 0x07040000 0 0x1000>;
3617 3226
3618 cpu = <&CPU0>; 3227 cpu = <&CPU0>;
3619 3228
3620 clocks = <&aoss_qmp>; 3229 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3230 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3231 arm,coresight-loses-context-with-cpu;
3623 3232
3624 out-ports { 3233 out-ports {
3625 port { 3234 port {
3626 etm0_ 3235 etm0_out: endpoint {
3627 3236 remote-endpoint =
3628 3237 <&apss_funnel_in0>;
3629 }; 3238 };
3630 }; 3239 };
3631 }; 3240 };
3632 }; 3241 };
3633 3242
3634 etm@7140000 { 3243 etm@7140000 {
3635 compatible = "arm,cor 3244 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3245 reg = <0 0x07140000 0 0x1000>;
3637 3246
3638 cpu = <&CPU1>; 3247 cpu = <&CPU1>;
3639 3248
3640 clocks = <&aoss_qmp>; 3249 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3250 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3251 arm,coresight-loses-context-with-cpu;
3643 3252
3644 out-ports { 3253 out-ports {
3645 port { 3254 port {
3646 etm1_ 3255 etm1_out: endpoint {
3647 3256 remote-endpoint =
3648 3257 <&apss_funnel_in1>;
3649 }; 3258 };
3650 }; 3259 };
3651 }; 3260 };
3652 }; 3261 };
3653 3262
3654 etm@7240000 { 3263 etm@7240000 {
3655 compatible = "arm,cor 3264 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3265 reg = <0 0x07240000 0 0x1000>;
3657 3266
3658 cpu = <&CPU2>; 3267 cpu = <&CPU2>;
3659 3268
3660 clocks = <&aoss_qmp>; 3269 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3270 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3271 arm,coresight-loses-context-with-cpu;
3663 3272
3664 out-ports { 3273 out-ports {
3665 port { 3274 port {
3666 etm2_ 3275 etm2_out: endpoint {
3667 3276 remote-endpoint =
3668 3277 <&apss_funnel_in2>;
3669 }; 3278 };
3670 }; 3279 };
3671 }; 3280 };
3672 }; 3281 };
3673 3282
3674 etm@7340000 { 3283 etm@7340000 {
3675 compatible = "arm,cor 3284 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3285 reg = <0 0x07340000 0 0x1000>;
3677 3286
3678 cpu = <&CPU3>; 3287 cpu = <&CPU3>;
3679 3288
3680 clocks = <&aoss_qmp>; 3289 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3290 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3291 arm,coresight-loses-context-with-cpu;
3683 3292
3684 out-ports { 3293 out-ports {
3685 port { 3294 port {
3686 etm3_ 3295 etm3_out: endpoint {
3687 3296 remote-endpoint =
3688 3297 <&apss_funnel_in3>;
3689 }; 3298 };
3690 }; 3299 };
3691 }; 3300 };
3692 }; 3301 };
3693 3302
3694 etm@7440000 { 3303 etm@7440000 {
3695 compatible = "arm,cor 3304 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3305 reg = <0 0x07440000 0 0x1000>;
3697 3306
3698 cpu = <&CPU4>; 3307 cpu = <&CPU4>;
3699 3308
3700 clocks = <&aoss_qmp>; 3309 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3310 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3311 arm,coresight-loses-context-with-cpu;
3703 3312
3704 out-ports { 3313 out-ports {
3705 port { 3314 port {
3706 etm4_ 3315 etm4_out: endpoint {
3707 3316 remote-endpoint =
3708 3317 <&apss_funnel_in4>;
3709 }; 3318 };
3710 }; 3319 };
3711 }; 3320 };
3712 }; 3321 };
3713 3322
3714 etm@7540000 { 3323 etm@7540000 {
3715 compatible = "arm,cor 3324 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3325 reg = <0 0x07540000 0 0x1000>;
3717 3326
3718 cpu = <&CPU5>; 3327 cpu = <&CPU5>;
3719 3328
3720 clocks = <&aoss_qmp>; 3329 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3330 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3331 arm,coresight-loses-context-with-cpu;
3723 3332
3724 out-ports { 3333 out-ports {
3725 port { 3334 port {
3726 etm5_ 3335 etm5_out: endpoint {
3727 3336 remote-endpoint =
3728 3337 <&apss_funnel_in5>;
3729 }; 3338 };
3730 }; 3339 };
3731 }; 3340 };
3732 }; 3341 };
3733 3342
3734 etm@7640000 { 3343 etm@7640000 {
3735 compatible = "arm,cor 3344 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3345 reg = <0 0x07640000 0 0x1000>;
3737 3346
3738 cpu = <&CPU6>; 3347 cpu = <&CPU6>;
3739 3348
3740 clocks = <&aoss_qmp>; 3349 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3350 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3351 arm,coresight-loses-context-with-cpu;
3743 3352
3744 out-ports { 3353 out-ports {
3745 port { 3354 port {
3746 etm6_ 3355 etm6_out: endpoint {
3747 3356 remote-endpoint =
3748 3357 <&apss_funnel_in6>;
3749 }; 3358 };
3750 }; 3359 };
3751 }; 3360 };
3752 }; 3361 };
3753 3362
3754 etm@7740000 { 3363 etm@7740000 {
3755 compatible = "arm,cor 3364 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3365 reg = <0 0x07740000 0 0x1000>;
3757 3366
3758 cpu = <&CPU7>; 3367 cpu = <&CPU7>;
3759 3368
3760 clocks = <&aoss_qmp>; 3369 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3370 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3371 arm,coresight-loses-context-with-cpu;
3763 3372
3764 out-ports { 3373 out-ports {
3765 port { 3374 port {
3766 etm7_ 3375 etm7_out: endpoint {
3767 3376 remote-endpoint =
3768 3377 <&apss_funnel_in7>;
3769 }; 3378 };
3770 }; 3379 };
3771 }; 3380 };
3772 }; 3381 };
3773 3382
3774 funnel@7800000 { /* APSS Funn 3383 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3384 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3385 reg = <0 0x07800000 0 0x1000>;
3777 3386
3778 clocks = <&aoss_qmp>; 3387 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3388 clock-names = "apb_pclk";
3780 3389
3781 out-ports { 3390 out-ports {
3782 port { 3391 port {
3783 apss_ 3392 apss_funnel_out: endpoint {
3784 3393 remote-endpoint =
3785 3394 <&apss_merge_funnel_in>;
3786 }; 3395 };
3787 }; 3396 };
3788 }; 3397 };
3789 3398
3790 in-ports { 3399 in-ports {
3791 #address-cell 3400 #address-cells = <1>;
3792 #size-cells = 3401 #size-cells = <0>;
3793 3402
3794 port@0 { 3403 port@0 {
3795 reg = 3404 reg = <0>;
3796 apss_ 3405 apss_funnel_in0: endpoint {
3797 3406 remote-endpoint =
3798 3407 <&etm0_out>;
3799 }; 3408 };
3800 }; 3409 };
3801 3410
3802 port@1 { 3411 port@1 {
3803 reg = 3412 reg = <1>;
3804 apss_ 3413 apss_funnel_in1: endpoint {
3805 3414 remote-endpoint =
3806 3415 <&etm1_out>;
3807 }; 3416 };
3808 }; 3417 };
3809 3418
3810 port@2 { 3419 port@2 {
3811 reg = 3420 reg = <2>;
3812 apss_ 3421 apss_funnel_in2: endpoint {
3813 3422 remote-endpoint =
3814 3423 <&etm2_out>;
3815 }; 3424 };
3816 }; 3425 };
3817 3426
3818 port@3 { 3427 port@3 {
3819 reg = 3428 reg = <3>;
3820 apss_ 3429 apss_funnel_in3: endpoint {
3821 3430 remote-endpoint =
3822 3431 <&etm3_out>;
3823 }; 3432 };
3824 }; 3433 };
3825 3434
3826 port@4 { 3435 port@4 {
3827 reg = 3436 reg = <4>;
3828 apss_ 3437 apss_funnel_in4: endpoint {
3829 3438 remote-endpoint =
3830 3439 <&etm4_out>;
3831 }; 3440 };
3832 }; 3441 };
3833 3442
3834 port@5 { 3443 port@5 {
3835 reg = 3444 reg = <5>;
3836 apss_ 3445 apss_funnel_in5: endpoint {
3837 3446 remote-endpoint =
3838 3447 <&etm5_out>;
3839 }; 3448 };
3840 }; 3449 };
3841 3450
3842 port@6 { 3451 port@6 {
3843 reg = 3452 reg = <6>;
3844 apss_ 3453 apss_funnel_in6: endpoint {
3845 3454 remote-endpoint =
3846 3455 <&etm6_out>;
3847 }; 3456 };
3848 }; 3457 };
3849 3458
3850 port@7 { 3459 port@7 {
3851 reg = 3460 reg = <7>;
3852 apss_ 3461 apss_funnel_in7: endpoint {
3853 3462 remote-endpoint =
3854 3463 <&etm7_out>;
3855 }; 3464 };
3856 }; 3465 };
3857 }; 3466 };
3858 }; 3467 };
3859 3468
3860 funnel@7810000 { 3469 funnel@7810000 {
3861 compatible = "arm,cor 3470 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3471 reg = <0 0x07810000 0 0x1000>;
3863 3472
3864 clocks = <&aoss_qmp>; 3473 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3474 clock-names = "apb_pclk";
3866 3475
3867 out-ports { 3476 out-ports {
3868 port { 3477 port {
3869 apss_ 3478 apss_merge_funnel_out: endpoint {
3870 3479 remote-endpoint =
3871 3480 <&funnel2_in5>;
3872 }; 3481 };
3873 }; 3482 };
3874 }; 3483 };
3875 3484
3876 in-ports { 3485 in-ports {
3877 port { 3486 port {
3878 apss_ 3487 apss_merge_funnel_in: endpoint {
3879 3488 remote-endpoint =
3880 3489 <&apss_funnel_out>;
3881 }; 3490 };
3882 }; 3491 };
3883 }; 3492 };
3884 }; 3493 };
3885 3494
3886 sdhc_2: mmc@8804000 { !! 3495 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 3496 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3497 reg = <0 0x08804000 0 0x1000>;
3889 3498
3890 interrupts = <GIC_SPI 3499 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3500 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3501 interrupt-names = "hc_irq", "pwr_irq";
3893 3502
3894 clocks = <&gcc GCC_SD 3503 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD 3504 <&gcc GCC_SDCC2_APPS_CLK>,
3896 <&rpmhcc RPM 3505 <&rpmhcc RPMH_CXO_CLK>;
3897 clock-names = "iface" 3506 clock-names = "iface", "core", "xo";
3898 iommus = <&apps_smmu 3507 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3508 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3509 operating-points-v2 = <&sdhc2_opp_table>;
3901 3510
3902 status = "disabled"; 3511 status = "disabled";
3903 3512
3904 sdhc2_opp_table: opp- !! 3513 sdhc2_opp_table: sdhc2-opp-table {
3905 compatible = 3514 compatible = "operating-points-v2";
3906 3515
3907 opp-9600000 { 3516 opp-9600000 {
3908 opp-h 3517 opp-hz = /bits/ 64 <9600000>;
3909 requi 3518 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3519 };
3911 3520
3912 opp-19200000 3521 opp-19200000 {
3913 opp-h 3522 opp-hz = /bits/ 64 <19200000>;
3914 requi 3523 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3524 };
3916 3525
3917 opp-100000000 3526 opp-100000000 {
3918 opp-h 3527 opp-hz = /bits/ 64 <100000000>;
3919 requi 3528 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3529 };
3921 3530
3922 opp-201500000 3531 opp-201500000 {
3923 opp-h 3532 opp-hz = /bits/ 64 <201500000>;
3924 requi 3533 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3534 };
3926 }; 3535 };
3927 }; 3536 };
3928 3537
>> 3538 qspi_opp_table: qspi-opp-table {
>> 3539 compatible = "operating-points-v2";
>> 3540
>> 3541 opp-19200000 {
>> 3542 opp-hz = /bits/ 64 <19200000>;
>> 3543 required-opps = <&rpmhpd_opp_min_svs>;
>> 3544 };
>> 3545
>> 3546 opp-100000000 {
>> 3547 opp-hz = /bits/ 64 <100000000>;
>> 3548 required-opps = <&rpmhpd_opp_low_svs>;
>> 3549 };
>> 3550
>> 3551 opp-150000000 {
>> 3552 opp-hz = /bits/ 64 <150000000>;
>> 3553 required-opps = <&rpmhpd_opp_svs>;
>> 3554 };
>> 3555
>> 3556 opp-300000000 {
>> 3557 opp-hz = /bits/ 64 <300000000>;
>> 3558 required-opps = <&rpmhpd_opp_nom>;
>> 3559 };
>> 3560 };
>> 3561
3929 qspi: spi@88df000 { 3562 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3563 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3564 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3565 #address-cells = <1>;
3934 #size-cells = <0>; 3566 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3567 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3568 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3569 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3570 clock-names = "iface", "core";
3939 power-domains = <&rpm 3571 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3572 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3573 status = "disabled";
3942 }; 3574 };
3943 3575
3944 slim: slim-ngd@171c0000 { !! 3576 slim: slim@171c0000 {
3945 compatible = "qcom,sl 3577 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3578 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3579 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3580
3949 dmas = <&slimbam 3>, !! 3581 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 3582 qcom,ea-pc = <0x270>;
>> 3583 status = "okay";
>> 3584 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3585 <&slimbam 5>, <&slimbam 6>;
>> 3586 dma-names = "rx", "tx", "tx2", "rx2";
3951 3587
3952 iommus = <&apps_smmu 3588 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3589 #address-cells = <1>;
3954 #size-cells = <0>; 3590 #size-cells = <0>;
3955 status = "disabled"; !! 3591
>> 3592 ngd@1 {
>> 3593 reg = <1>;
>> 3594 #address-cells = <2>;
>> 3595 #size-cells = <0>;
>> 3596
>> 3597 wcd9340_ifd: ifd@0{
>> 3598 compatible = "slim217,250";
>> 3599 reg = <0 0>;
>> 3600 };
>> 3601
>> 3602 wcd9340: codec@1{
>> 3603 compatible = "slim217,250";
>> 3604 reg = <1 0>;
>> 3605 slim-ifc-dev = <&wcd9340_ifd>;
>> 3606
>> 3607 #sound-dai-cells = <1>;
>> 3608
>> 3609 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3610 interrupt-controller;
>> 3611 #interrupt-cells = <1>;
>> 3612
>> 3613 #clock-cells = <0>;
>> 3614 clock-frequency = <9600000>;
>> 3615 clock-output-names = "mclk";
>> 3616 qcom,micbias1-microvolt = <1800000>;
>> 3617 qcom,micbias2-microvolt = <1800000>;
>> 3618 qcom,micbias3-microvolt = <1800000>;
>> 3619 qcom,micbias4-microvolt = <1800000>;
>> 3620
>> 3621 #address-cells = <1>;
>> 3622 #size-cells = <1>;
>> 3623
>> 3624 wcdgpio: gpio-controller@42 {
>> 3625 compatible = "qcom,wcd9340-gpio";
>> 3626 gpio-controller;
>> 3627 #gpio-cells = <2>;
>> 3628 reg = <0x42 0x2>;
>> 3629 };
>> 3630
>> 3631 swm: swm@c85 {
>> 3632 compatible = "qcom,soundwire-v1.3.0";
>> 3633 reg = <0xc85 0x40>;
>> 3634 interrupts-extended = <&wcd9340 20>;
>> 3635
>> 3636 qcom,dout-ports = <6>;
>> 3637 qcom,din-ports = <2>;
>> 3638 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3639 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3640 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3641
>> 3642 #sound-dai-cells = <1>;
>> 3643 clocks = <&wcd9340>;
>> 3644 clock-names = "iface";
>> 3645 #address-cells = <2>;
>> 3646 #size-cells = <0>;
>> 3647
>> 3648
>> 3649 };
>> 3650 };
>> 3651 };
3956 }; 3652 };
3957 3653
3958 lmh_cluster1: lmh@17d70800 { 3654 lmh_cluster1: lmh@17d70800 {
3959 compatible = "qcom,sd 3655 compatible = "qcom,sdm845-lmh";
3960 reg = <0 0x17d70800 0 3656 reg = <0 0x17d70800 0 0x400>;
3961 interrupts = <GIC_SPI 3657 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962 cpus = <&CPU4>; 3658 cpus = <&CPU4>;
3963 qcom,lmh-temp-arm-mil 3659 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-mil 3660 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-mi 3661 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller; 3662 interrupt-controller;
3967 #interrupt-cells = <1 3663 #interrupt-cells = <1>;
3968 }; 3664 };
3969 3665
3970 lmh_cluster0: lmh@17d78800 { 3666 lmh_cluster0: lmh@17d78800 {
3971 compatible = "qcom,sd 3667 compatible = "qcom,sdm845-lmh";
3972 reg = <0 0x17d78800 0 3668 reg = <0 0x17d78800 0 0x400>;
3973 interrupts = <GIC_SPI 3669 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974 cpus = <&CPU0>; 3670 cpus = <&CPU0>;
3975 qcom,lmh-temp-arm-mil 3671 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-mil 3672 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-mi 3673 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller; 3674 interrupt-controller;
3979 #interrupt-cells = <1 3675 #interrupt-cells = <1>;
3980 }; 3676 };
3981 3677
>> 3678 sound: sound {
>> 3679 };
>> 3680
3982 usb_1_hsphy: phy@88e2000 { 3681 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3682 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3683 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3684 status = "disabled";
3986 #phy-cells = <0>; 3685 #phy-cells = <0>;
3987 3686
3988 clocks = <&gcc GCC_US 3687 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3688 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3689 clock-names = "cfg_ahb", "ref";
3991 3690
3992 resets = <&gcc GCC_QU 3691 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3692
3994 nvmem-cells = <&qusb2 3693 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3694 };
3996 3695
3997 usb_2_hsphy: phy@88e3000 { 3696 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3697 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3698 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3699 status = "disabled";
4001 #phy-cells = <0>; 3700 #phy-cells = <0>;
4002 3701
4003 clocks = <&gcc GCC_US 3702 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3703 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3704 clock-names = "cfg_ahb", "ref";
4006 3705
4007 resets = <&gcc GCC_QU 3706 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3707
4009 nvmem-cells = <&qusb2 3708 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3709 };
4011 3710
4012 usb_1_qmpphy: phy@88e8000 { !! 3711 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3712 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3713 reg = <0 0x088e9000 0 0x18c>,
>> 3714 <0 0x088e8000 0 0x10>;
4015 status = "disabled"; 3715 status = "disabled";
>> 3716 #address-cells = <2>;
>> 3717 #size-cells = <2>;
>> 3718 ranges;
4016 3719
4017 clocks = <&gcc GCC_US 3720 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3721 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3722 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3723 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3724 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3725
4028 resets = <&gcc GCC_US !! 3726 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3727 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3728 reset-names = "phy", "common";
4031 3729
4032 #clock-cells = <1>; !! 3730 usb_1_ssphy: phy@88e9200 {
4033 #phy-cells = <1>; !! 3731 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3732 <0 0x088e9400 0 0x200>,
4035 !! 3733 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3734 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3735 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3736 <0 0x088e9a00 0 0x100>;
4039 !! 3737 #clock-cells = <0>;
4040 port@0 { !! 3738 #phy-cells = <0>;
4041 reg = !! 3739 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042 !! 3740 clock-names = "pipe0";
4043 usb_1 !! 3741 clock-output-names = "usb3_phy_pipe_clk_src";
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3742 };
4063 }; 3743 };
4064 3744
4065 usb_2_qmpphy: phy@88eb000 { 3745 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3746 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 3747 reg = <0 0x088eb000 0 0x18c>;
>> 3748 status = "disabled";
>> 3749 #address-cells = <2>;
>> 3750 #size-cells = <2>;
>> 3751 ranges;
4068 3752
4069 clocks = <&gcc GCC_US 3753 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 3754 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 3755 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 3756 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 3757 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 3758
4083 resets = <&gcc GCC_US !! 3759 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 3760 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 3761 reset-names = "phy", "common";
4086 "phy_ph <<
4087 3762
4088 status = "disabled"; !! 3763 usb_2_ssphy: phy@88eb200 {
>> 3764 reg = <0 0x088eb200 0 0x128>,
>> 3765 <0 0x088eb400 0 0x1fc>,
>> 3766 <0 0x088eb800 0 0x218>,
>> 3767 <0 0x088eb600 0 0x70>;
>> 3768 #clock-cells = <0>;
>> 3769 #phy-cells = <0>;
>> 3770 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3771 clock-names = "pipe0";
>> 3772 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3773 };
4089 }; 3774 };
4090 3775
4091 usb_1: usb@a6f8800 { 3776 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 3777 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 3778 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 3779 status = "disabled";
4095 #address-cells = <2>; 3780 #address-cells = <2>;
4096 #size-cells = <2>; 3781 #size-cells = <2>;
4097 ranges; 3782 ranges;
4098 dma-ranges; 3783 dma-ranges;
4099 3784
4100 clocks = <&gcc GCC_CF 3785 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 3786 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 3787 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 3788 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 3789 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 3790 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 3791 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 3792
4111 assigned-clocks = <&g 3793 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 3794 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 3795 assigned-clock-rates = <19200000>, <150000000>;
4114 3796
4115 interrupts-extended = !! 3797 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 3798 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 3799 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 3800 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 3801 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 3802 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 3803
4126 power-domains = <&gcc 3804 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 3805
4128 resets = <&gcc GCC_US 3806 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 3807
4130 interconnects = <&agg 3808 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 3809 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 3810 interconnect-names = "usb-ddr", "apps-usb";
4133 3811
4134 usb_1_dwc3: usb@a6000 !! 3812 usb_1_dwc3: dwc3@a600000 {
4135 compatible = 3813 compatible = "snps,dwc3";
4136 reg = <0 0x0a 3814 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 3815 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 3816 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 3817 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 3818 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 3819 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 3820 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 3821 };
4165 }; 3822 };
4166 3823
4167 usb_2: usb@a8f8800 { 3824 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 3825 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 3826 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 3827 status = "disabled";
4171 #address-cells = <2>; 3828 #address-cells = <2>;
4172 #size-cells = <2>; 3829 #size-cells = <2>;
4173 ranges; 3830 ranges;
4174 dma-ranges; 3831 dma-ranges;
4175 3832
4176 clocks = <&gcc GCC_CF 3833 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 3834 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 3835 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 3836 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 3837 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 3838 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 3839 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 3840
4187 assigned-clocks = <&g 3841 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 3842 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 3843 assigned-clock-rates = <19200000>, <150000000>;
4190 3844
4191 interrupts-extended = !! 3845 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 3846 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 3847 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 3848 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 3849 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 3850 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 3851
4202 power-domains = <&gcc 3852 power-domains = <&gcc USB30_SEC_GDSC>;
4203 3853
4204 resets = <&gcc GCC_US 3854 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 3855
4206 interconnects = <&agg 3856 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 3857 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 3858 interconnect-names = "usb-ddr", "apps-usb";
4209 3859
4210 usb_2_dwc3: usb@a8000 !! 3860 usb_2_dwc3: dwc3@a800000 {
4211 compatible = 3861 compatible = "snps,dwc3";
4212 reg = <0 0x0a 3862 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 3863 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 3864 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 3865 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 3866 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 3867 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 3868 phy-names = "usb2-phy", "usb3-phy";
4220 }; 3869 };
4221 }; 3870 };
4222 3871
4223 venus: video-codec@aa00000 { 3872 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 3873 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 3874 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 3875 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 3876 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 3877 <&videocc VCODEC0_GDSC>,
4229 <&vid 3878 <&videocc VCODEC1_GDSC>,
4230 <&rpm 3879 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 3880 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 3881 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 3882 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 3883 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 3884 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 3885 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 3886 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 3887 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 3888 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 3889 clock-names = "core", "iface", "bus",
4241 "vcodec 3890 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 3891 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 3892 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 3893 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 3894 memory-region = <&venus_mem>;
4246 interconnects = <&mms 3895 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 3896 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 3897 interconnect-names = "video-mem", "cpu-cfg";
4249 3898
4250 status = "disabled"; 3899 status = "disabled";
4251 3900
4252 video-core0 { 3901 video-core0 {
4253 compatible = 3902 compatible = "venus-decoder";
4254 }; 3903 };
4255 3904
4256 video-core1 { 3905 video-core1 {
4257 compatible = 3906 compatible = "venus-encoder";
4258 }; 3907 };
4259 3908
4260 venus_opp_table: opp- !! 3909 venus_opp_table: venus-opp-table {
4261 compatible = 3910 compatible = "operating-points-v2";
4262 3911
4263 opp-100000000 3912 opp-100000000 {
4264 opp-h 3913 opp-hz = /bits/ 64 <100000000>;
4265 requi 3914 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 3915 };
4267 3916
4268 opp-200000000 3917 opp-200000000 {
4269 opp-h 3918 opp-hz = /bits/ 64 <200000000>;
4270 requi 3919 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 3920 };
4272 3921
4273 opp-320000000 3922 opp-320000000 {
4274 opp-h 3923 opp-hz = /bits/ 64 <320000000>;
4275 requi 3924 required-opps = <&rpmhpd_opp_svs>;
4276 }; 3925 };
4277 3926
4278 opp-380000000 3927 opp-380000000 {
4279 opp-h 3928 opp-hz = /bits/ 64 <380000000>;
4280 requi 3929 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 3930 };
4282 3931
4283 opp-444000000 3932 opp-444000000 {
4284 opp-h 3933 opp-hz = /bits/ 64 <444000000>;
4285 requi 3934 required-opps = <&rpmhpd_opp_nom>;
4286 }; 3935 };
4287 3936
4288 opp-533000097 3937 opp-533000097 {
4289 opp-h 3938 opp-hz = /bits/ 64 <533000097>;
4290 requi 3939 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 3940 };
4292 }; 3941 };
4293 }; 3942 };
4294 3943
4295 videocc: clock-controller@ab0 3944 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 3945 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 3946 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 3947 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 3948 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 3949 #clock-cells = <1>;
4301 #power-domain-cells = 3950 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 3951 #reset-cells = <1>;
4303 }; 3952 };
4304 3953
4305 camss: camss@acb3000 { !! 3954 camss: camss@a00000 {
4306 compatible = "qcom,sd 3955 compatible = "qcom,sdm845-camss";
4307 3956
4308 reg = <0 0x0acb3000 0 !! 3957 reg = <0 0xacb3000 0 0x1000>,
4309 <0 0x0acba000 !! 3958 <0 0xacba000 0 0x1000>,
4310 <0 0x0acc8000 !! 3959 <0 0xacc8000 0 0x1000>,
4311 <0 0x0ac65000 !! 3960 <0 0xac65000 0 0x1000>,
4312 <0 0x0ac66000 !! 3961 <0 0xac66000 0 0x1000>,
4313 <0 0x0ac67000 !! 3962 <0 0xac67000 0 0x1000>,
4314 <0 0x0ac68000 !! 3963 <0 0xac68000 0 0x1000>,
4315 <0 0x0acaf000 !! 3964 <0 0xacaf000 0 0x4000>,
4316 <0 0x0acb6000 !! 3965 <0 0xacb6000 0 0x4000>,
4317 <0 0x0acc4000 !! 3966 <0 0xacc4000 0 0x4000>;
4318 reg-names = "csid0", 3967 reg-names = "csid0",
4319 "csid1", 3968 "csid1",
4320 "csid2", 3969 "csid2",
4321 "csiphy0", 3970 "csiphy0",
4322 "csiphy1", 3971 "csiphy1",
4323 "csiphy2", 3972 "csiphy2",
4324 "csiphy3", 3973 "csiphy3",
4325 "vfe0", 3974 "vfe0",
4326 "vfe1", 3975 "vfe1",
4327 "vfe_lite"; 3976 "vfe_lite";
4328 3977
4329 interrupts = <GIC_SPI 3978 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 3979 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 3980 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 3981 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 3982 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 3983 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 3984 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 3985 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 3986 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 3987 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 3988 interrupt-names = "csid0",
4340 "csid1", 3989 "csid1",
4341 "csid2", 3990 "csid2",
4342 "csiphy0", 3991 "csiphy0",
4343 "csiphy1", 3992 "csiphy1",
4344 "csiphy2", 3993 "csiphy2",
4345 "csiphy3", 3994 "csiphy3",
4346 "vfe0", 3995 "vfe0",
4347 "vfe1", 3996 "vfe1",
4348 "vfe_lite"; 3997 "vfe_lite";
4349 3998
4350 power-domains = <&clo 3999 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 4000 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 4001 <&clock_camcc TITAN_TOP_GDSC>;
4353 4002
4354 clocks = <&clock_camc 4003 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 4004 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 4005 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 4006 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 4007 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 4008 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 4009 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 4010 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 4011 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 4012 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 4013 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 4014 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 4015 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 4016 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 4017 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 4018 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 4019 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 4020 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 4021 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 4022 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 4023 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 4024 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 4025 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 4026 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 4027 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 4028 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 4029 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4030 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4031 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4032 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4033 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4034 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4035 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4036 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4037 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4038 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4039 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4040 "cpas_ahb",
4392 "cphy_rx_src" 4041 "cphy_rx_src",
4393 "csi0", 4042 "csi0",
4394 "csi0_src", 4043 "csi0_src",
4395 "csi1", 4044 "csi1",
4396 "csi1_src", 4045 "csi1_src",
4397 "csi2", 4046 "csi2",
4398 "csi2_src", 4047 "csi2_src",
4399 "csiphy0", 4048 "csiphy0",
4400 "csiphy0_time 4049 "csiphy0_timer",
4401 "csiphy0_time 4050 "csiphy0_timer_src",
4402 "csiphy1", 4051 "csiphy1",
4403 "csiphy1_time 4052 "csiphy1_timer",
4404 "csiphy1_time 4053 "csiphy1_timer_src",
4405 "csiphy2", 4054 "csiphy2",
4406 "csiphy2_time 4055 "csiphy2_timer",
4407 "csiphy2_time 4056 "csiphy2_timer_src",
4408 "csiphy3", 4057 "csiphy3",
4409 "csiphy3_time 4058 "csiphy3_timer",
4410 "csiphy3_time 4059 "csiphy3_timer_src",
4411 "gcc_camera_a 4060 "gcc_camera_ahb",
4412 "gcc_camera_a 4061 "gcc_camera_axi",
4413 "slow_ahb_src 4062 "slow_ahb_src",
4414 "soc_ahb", 4063 "soc_ahb",
4415 "vfe0_axi", 4064 "vfe0_axi",
4416 "vfe0", 4065 "vfe0",
4417 "vfe0_cphy_rx 4066 "vfe0_cphy_rx",
4418 "vfe0_src", 4067 "vfe0_src",
4419 "vfe1_axi", 4068 "vfe1_axi",
4420 "vfe1", 4069 "vfe1",
4421 "vfe1_cphy_rx 4070 "vfe1_cphy_rx",
4422 "vfe1_src", 4071 "vfe1_src",
4423 "vfe_lite", 4072 "vfe_lite",
4424 "vfe_lite_cph 4073 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4074 "vfe_lite_src";
4426 4075
4427 iommus = <&apps_smmu 4076 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4077 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4078 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4079 <&apps_smmu 0x0c10 0x8>;
4431 4080
4432 status = "disabled"; 4081 status = "disabled";
4433 4082
4434 ports { 4083 ports {
4435 #address-cell 4084 #address-cells = <1>;
4436 #size-cells = 4085 #size-cells = <0>;
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; 4086 };
4454 }; 4087 };
4455 4088
4456 cci: cci@ac4a000 { 4089 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 4090 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 4091 #address-cells = <1>;
4459 #size-cells = <0>; 4092 #size-cells = <0>;
4460 4093
4461 reg = <0 0x0ac4a000 0 4094 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4095 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4096 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4097
4465 clocks = <&clock_camc 4098 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4099 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4100 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4101 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4102 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4103 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4104 clock-names = "camnoc_axi",
4472 "soc_ahb", 4105 "soc_ahb",
4473 "slow_ahb_src 4106 "slow_ahb_src",
4474 "cpas_ahb", 4107 "cpas_ahb",
4475 "cci", 4108 "cci",
4476 "cci_src"; 4109 "cci_src";
4477 4110
4478 assigned-clocks = <&c 4111 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4112 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4113 assigned-clock-rates = <80000000>, <37500000>;
4481 4114
4482 pinctrl-names = "defa 4115 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4116 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4117 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4118
4486 status = "disabled"; 4119 status = "disabled";
4487 4120
4488 cci_i2c0: i2c-bus@0 { 4121 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4122 reg = <0>;
4490 clock-frequen 4123 clock-frequency = <1000000>;
4491 #address-cell 4124 #address-cells = <1>;
4492 #size-cells = 4125 #size-cells = <0>;
4493 }; 4126 };
4494 4127
4495 cci_i2c1: i2c-bus@1 { 4128 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4129 reg = <1>;
4497 clock-frequen 4130 clock-frequency = <1000000>;
4498 #address-cell 4131 #address-cells = <1>;
4499 #size-cells = 4132 #size-cells = <0>;
4500 }; 4133 };
4501 }; 4134 };
4502 4135
4503 clock_camcc: clock-controller 4136 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4137 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4138 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4139 #clock-cells = <1>;
4507 #reset-cells = <1>; 4140 #reset-cells = <1>;
4508 #power-domain-cells = 4141 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; 4142 };
4512 4143
4513 mdss: display-subsystem@ae000 !! 4144 dsi_opp_table: dsi-opp-table {
>> 4145 compatible = "operating-points-v2";
>> 4146
>> 4147 opp-19200000 {
>> 4148 opp-hz = /bits/ 64 <19200000>;
>> 4149 required-opps = <&rpmhpd_opp_min_svs>;
>> 4150 };
>> 4151
>> 4152 opp-180000000 {
>> 4153 opp-hz = /bits/ 64 <180000000>;
>> 4154 required-opps = <&rpmhpd_opp_low_svs>;
>> 4155 };
>> 4156
>> 4157 opp-275000000 {
>> 4158 opp-hz = /bits/ 64 <275000000>;
>> 4159 required-opps = <&rpmhpd_opp_svs>;
>> 4160 };
>> 4161
>> 4162 opp-328580000 {
>> 4163 opp-hz = /bits/ 64 <328580000>;
>> 4164 required-opps = <&rpmhpd_opp_svs_l1>;
>> 4165 };
>> 4166
>> 4167 opp-358000000 {
>> 4168 opp-hz = /bits/ 64 <358000000>;
>> 4169 required-opps = <&rpmhpd_opp_nom>;
>> 4170 };
>> 4171 };
>> 4172
>> 4173 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 4174 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4175 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4176 reg-names = "mdss";
4517 4177
4518 power-domains = <&dis 4178 power-domains = <&dispcc MDSS_GDSC>;
4519 4179
4520 clocks = <&dispcc DIS !! 4180 clocks = <&gcc GCC_DISP_AHB_CLK>,
4521 <&dispcc DIS 4181 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" 4182 clock-names = "iface", "core";
4523 4183
>> 4184 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 4185 assigned-clock-rates = <300000000>;
>> 4186
4524 interrupts = <GIC_SPI 4187 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4188 interrupt-controller;
4526 #interrupt-cells = <1 4189 #interrupt-cells = <1>;
4527 4190
4528 interconnects = <&mms 4191 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4192 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4193 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4194
4532 iommus = <&apps_smmu 4195 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4196 <&apps_smmu 0xc80 0x8>;
4534 4197
4535 status = "disabled"; 4198 status = "disabled";
4536 4199
4537 #address-cells = <2>; 4200 #address-cells = <2>;
4538 #size-cells = <2>; 4201 #size-cells = <2>;
4539 ranges; 4202 ranges;
4540 4203
4541 mdss_mdp: display-con !! 4204 mdss_mdp: mdp@ae01000 {
4542 compatible = 4205 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4206 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4207 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4208 reg-names = "mdp", "vbif";
4546 4209
4547 clocks = <&gc 4210 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548 <&di 4211 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549 <&di 4212 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4213 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4214 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = 4215 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553 4216
4554 assigned-cloc !! 4217 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 4218 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 4219 assigned-clock-rates = <300000000>,
>> 4220 <19200000>;
4556 operating-poi 4221 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4222 power-domains = <&rpmhpd SDM845_CX>;
4558 4223
4559 interrupt-par 4224 interrupt-parent = <&mdss>;
4560 interrupts = !! 4225 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4561 4226
4562 ports { 4227 ports {
4563 #addr 4228 #address-cells = <1>;
4564 #size 4229 #size-cells = <0>;
4565 4230
4566 port@ 4231 port@0 {
4567 4232 reg = <0>;
4568 !! 4233 dpu_intf1_out: endpoint {
4569 !! 4234 remote-endpoint = <&dsi0_in>;
4570 4235 };
4571 }; 4236 };
4572 4237
4573 port@ 4238 port@1 {
4574 4239 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 4240 dpu_intf2_out: endpoint {
4583 !! 4241 remote-endpoint = <&dsi1_in>;
4584 4242 };
4585 }; 4243 };
4586 }; 4244 };
4587 4245
4588 mdp_opp_table !! 4246 mdp_opp_table: mdp-opp-table {
4589 compa 4247 compatible = "operating-points-v2";
4590 4248
4591 opp-1 4249 opp-19200000 {
4592 4250 opp-hz = /bits/ 64 <19200000>;
4593 4251 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4252 };
4595 4253
4596 opp-1 4254 opp-171428571 {
4597 4255 opp-hz = /bits/ 64 <171428571>;
4598 4256 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4257 };
4600 4258
4601 opp-3 4259 opp-344000000 {
4602 4260 opp-hz = /bits/ 64 <344000000>;
4603 4261 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4262 };
4605 4263
4606 opp-4 4264 opp-430000000 {
4607 4265 opp-hz = /bits/ 64 <430000000>;
4608 4266 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4267 };
4610 }; 4268 };
4611 }; 4269 };
4612 4270
4613 mdss_dp: displayport- !! 4271 dsi0: dsi@ae94000 {
4614 status = "dis !! 4272 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 4273 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4274 reg-names = "dsi_ctrl";
4691 4275
4692 interrupt-par 4276 interrupt-parent = <&mdss>;
4693 interrupts = !! 4277 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 4278
4695 clocks = <&di 4279 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4280 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4281 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4282 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4283 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4284 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4285 clock-names = "byte",
4702 4286 "byte_intf",
4703 4287 "pixel",
4704 4288 "core",
4705 4289 "iface",
4706 4290 "bus";
4707 assigned-cloc 4291 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-cloc !! 4292 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4709 4293
4710 operating-poi 4294 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4295 power-domains = <&rpmhpd SDM845_CX>;
4712 4296
4713 phys = <&mdss !! 4297 phys = <&dsi0_phy>;
>> 4298 phy-names = "dsi";
4714 4299
4715 status = "dis 4300 status = "disabled";
4716 4301
4717 #address-cell 4302 #address-cells = <1>;
4718 #size-cells = 4303 #size-cells = <0>;
4719 4304
4720 ports { 4305 ports {
4721 #addr 4306 #address-cells = <1>;
4722 #size 4307 #size-cells = <0>;
4723 4308
4724 port@ 4309 port@0 {
4725 4310 reg = <0>;
4726 !! 4311 dsi0_in: endpoint {
4727 4312 remote-endpoint = <&dpu_intf1_out>;
4728 4313 };
4729 }; 4314 };
4730 4315
4731 port@ 4316 port@1 {
4732 4317 reg = <1>;
4733 !! 4318 dsi0_out: endpoint {
4734 4319 };
4735 }; 4320 };
4736 }; 4321 };
4737 }; 4322 };
4738 4323
4739 mdss_dsi0_phy: phy@ae !! 4324 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 4325 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4326 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4327 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4328 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4329 reg-names = "dsi_phy",
4745 " 4330 "dsi_phy_lane",
4746 " 4331 "dsi_pll";
4747 4332
4748 #clock-cells 4333 #clock-cells = <1>;
4749 #phy-cells = 4334 #phy-cells = <0>;
4750 4335
4751 clocks = <&di 4336 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4337 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4338 clock-names = "iface", "ref";
4754 4339
4755 status = "dis 4340 status = "disabled";
4756 }; 4341 };
4757 4342
4758 mdss_dsi1: dsi@ae9600 !! 4343 dsi1: dsi@ae96000 {
4759 compatible = !! 4344 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 4345 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4346 reg-names = "dsi_ctrl";
4763 4347
4764 interrupt-par 4348 interrupt-parent = <&mdss>;
4765 interrupts = !! 4349 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 4350
4767 clocks = <&di 4351 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4352 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4353 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4354 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4355 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4356 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4357 clock-names = "byte",
4774 4358 "byte_intf",
4775 4359 "pixel",
4776 4360 "core",
4777 4361 "iface",
4778 4362 "bus";
4779 assigned-cloc 4363 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-cloc !! 4364 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4781 4365
4782 operating-poi 4366 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4367 power-domains = <&rpmhpd SDM845_CX>;
4784 4368
4785 phys = <&mdss !! 4369 phys = <&dsi1_phy>;
>> 4370 phy-names = "dsi";
4786 4371
4787 status = "dis 4372 status = "disabled";
4788 4373
4789 #address-cell 4374 #address-cells = <1>;
4790 #size-cells = 4375 #size-cells = <0>;
4791 4376
4792 ports { 4377 ports {
4793 #addr 4378 #address-cells = <1>;
4794 #size 4379 #size-cells = <0>;
4795 4380
4796 port@ 4381 port@0 {
4797 4382 reg = <0>;
4798 !! 4383 dsi1_in: endpoint {
4799 4384 remote-endpoint = <&dpu_intf2_out>;
4800 4385 };
4801 }; 4386 };
4802 4387
4803 port@ 4388 port@1 {
4804 4389 reg = <1>;
4805 !! 4390 dsi1_out: endpoint {
4806 4391 };
4807 }; 4392 };
4808 }; 4393 };
4809 }; 4394 };
4810 4395
4811 mdss_dsi1_phy: phy@ae !! 4396 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 4397 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4398 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4399 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4400 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4401 reg-names = "dsi_phy",
4817 " 4402 "dsi_phy_lane",
4818 " 4403 "dsi_pll";
4819 4404
4820 #clock-cells 4405 #clock-cells = <1>;
4821 #phy-cells = 4406 #phy-cells = <0>;
4822 4407
4823 clocks = <&di 4408 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4409 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4410 clock-names = "iface", "ref";
4826 4411
4827 status = "dis 4412 status = "disabled";
4828 }; 4413 };
4829 }; 4414 };
4830 4415
4831 gpu: gpu@5000000 { 4416 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4417 compatible = "qcom,adreno-630.2", "qcom,adreno";
4833 4418
4834 reg = <0 0x05000000 0 !! 4419 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4420 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4421
4837 /* 4422 /*
4838 * Look ma, no clocks 4423 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4424 * controlled entirely by the GMU
4840 */ 4425 */
4841 4426
4842 interrupts = <GIC_SPI 4427 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4428
4844 iommus = <&adreno_smm 4429 iommus = <&adreno_smmu 0>;
4845 4430
4846 operating-points-v2 = 4431 operating-points-v2 = <&gpu_opp_table>;
4847 4432
4848 qcom,gmu = <&gmu>; 4433 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4434
4851 interconnects = <&mem 4435 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4436 interconnect-names = "gfx-mem";
4853 4437
4854 status = "disabled"; 4438 status = "disabled";
4855 4439
4856 gpu_opp_table: opp-ta 4440 gpu_opp_table: opp-table {
4857 compatible = 4441 compatible = "operating-points-v2";
4858 4442
4859 opp-710000000 4443 opp-710000000 {
4860 opp-h 4444 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4445 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4446 opp-peak-kBps = <7216000>;
4863 }; 4447 };
4864 4448
4865 opp-675000000 4449 opp-675000000 {
4866 opp-h 4450 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4452 opp-peak-kBps = <7216000>;
4869 }; 4453 };
4870 4454
4871 opp-596000000 4455 opp-596000000 {
4872 opp-h 4456 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4457 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4458 opp-peak-kBps = <6220000>;
4875 }; 4459 };
4876 4460
4877 opp-520000000 4461 opp-520000000 {
4878 opp-h 4462 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4463 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4464 opp-peak-kBps = <6220000>;
4881 }; 4465 };
4882 4466
4883 opp-414000000 4467 opp-414000000 {
4884 opp-h 4468 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4470 opp-peak-kBps = <4068000>;
4887 }; 4471 };
4888 4472
4889 opp-342000000 4473 opp-342000000 {
4890 opp-h 4474 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4475 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4476 opp-peak-kBps = <2724000>;
4893 }; 4477 };
4894 4478
4895 opp-257000000 4479 opp-257000000 {
4896 opp-h 4480 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4482 opp-peak-kBps = <1648000>;
4899 }; 4483 };
4900 }; 4484 };
4901 }; 4485 };
4902 4486
4903 adreno_smmu: iommu@5040000 { 4487 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4488 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4489 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4490 #iommu-cells = <1>;
4907 #global-interrupts = 4491 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4493 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4494 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4495 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4496 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4497 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4498 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4499 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4500 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4501 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4502 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4503 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4504 clock-names = "bus", "iface";
4921 4505
4922 power-domains = <&gpu 4506 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4507 };
4924 4508
4925 gmu: gmu@506a000 { 4509 gmu: gmu@506a000 {
4926 compatible = "qcom,ad !! 4510 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4511
4928 reg = <0 0x0506a000 0 !! 4512 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4513 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4514 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4515 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4516
4933 interrupts = <GIC_SPI 4517 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4518 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4519 interrupt-names = "hfi", "gmu";
4936 4520
4937 clocks = <&gpucc GPU_ 4521 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4522 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4523 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4524 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4525 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4526
4943 power-domains = <&gpu 4527 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4528 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4529 power-domain-names = "cx", "gx";
4946 4530
4947 iommus = <&adreno_smm 4531 iommus = <&adreno_smmu 5>;
4948 4532
4949 operating-points-v2 = 4533 operating-points-v2 = <&gmu_opp_table>;
4950 4534
4951 status = "disabled"; 4535 status = "disabled";
4952 4536
4953 gmu_opp_table: opp-ta 4537 gmu_opp_table: opp-table {
4954 compatible = 4538 compatible = "operating-points-v2";
4955 4539
4956 opp-400000000 4540 opp-400000000 {
4957 opp-h 4541 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4542 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4543 };
4960 4544
4961 opp-200000000 4545 opp-200000000 {
4962 opp-h 4546 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4547 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4548 };
4965 }; 4549 };
4966 }; 4550 };
4967 4551
4968 dispcc: clock-controller@af00 4552 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4553 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4554 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4555 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4556 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4557 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4558 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4559 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4560 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4561 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4562 <0>,
4979 <&usb_1_qmpp !! 4563 <0>;
4980 clock-names = "bi_tcx 4564 clock-names = "bi_tcxo",
4981 "gcc_di 4565 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4566 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4567 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4568 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4569 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4570 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4571 "dp_link_clk_divsel_ten",
4988 "dp_vco 4572 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4573 #clock-cells = <1>;
4990 #reset-cells = <1>; 4574 #reset-cells = <1>;
4991 #power-domain-cells = 4575 #power-domain-cells = <1>;
4992 }; 4576 };
4993 4577
4994 pdc_intc: interrupt-controlle 4578 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4579 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4580 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4581 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4582 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4583 interrupt-parent = <&intc>;
5000 interrupt-controller; 4584 interrupt-controller;
5001 }; 4585 };
5002 4586
5003 pdc_reset: reset-controller@b 4587 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4588 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4589 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4590 #reset-cells = <1>;
5007 }; 4591 };
5008 4592
5009 tsens0: thermal-sensor@c26300 4593 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4594 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4595 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4596 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4597 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4598 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4599 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4600 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4601 #thermal-sensor-cells = <1>;
5018 }; 4602 };
5019 4603
5020 tsens1: thermal-sensor@c26500 4604 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4605 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4606 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4607 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4608 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4609 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4610 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4611 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4612 #thermal-sensor-cells = <1>;
5029 }; 4613 };
5030 4614
5031 aoss_reset: reset-controller@ 4615 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4616 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4617 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4618 #reset-cells = <1>;
5035 }; 4619 };
5036 4620
5037 aoss_qmp: power-management@c3 !! 4621 aoss_qmp: power-controller@c300000 {
5038 compatible = "qcom,sd !! 4622 compatible = "qcom,sdm845-aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 4623 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 4624 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4625 mboxes = <&apss_shared 0>;
5042 4626
5043 #clock-cells = <0>; 4627 #clock-cells = <0>;
5044 4628
5045 cx_cdev: cx { 4629 cx_cdev: cx {
5046 #cooling-cell 4630 #cooling-cells = <2>;
5047 }; 4631 };
5048 4632
5049 ebi_cdev: ebi { 4633 ebi_cdev: ebi {
5050 #cooling-cell 4634 #cooling-cells = <2>;
5051 }; 4635 };
5052 }; 4636 };
5053 4637
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 4638 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4639 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4640 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4641 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4642 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4643 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4644 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 4645 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 4646 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 4647 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 4648 qcom,ee = <0>;
5070 qcom,channel = <0>; 4649 qcom,channel = <0>;
5071 #address-cells = <2>; 4650 #address-cells = <2>;
5072 #size-cells = <0>; 4651 #size-cells = <0>;
5073 interrupt-controller; 4652 interrupt-controller;
5074 #interrupt-cells = <4 4653 #interrupt-cells = <4>;
>> 4654 cell-index = <0>;
5075 }; 4655 };
5076 4656
5077 sram@146bf000 { !! 4657 imem@146bf000 {
5078 compatible = "qcom,sd !! 4658 compatible = "simple-mfd";
5079 reg = <0 0x146bf000 0 4659 reg = <0 0x146bf000 0 0x1000>;
5080 4660
5081 #address-cells = <1>; 4661 #address-cells = <1>;
5082 #size-cells = <1>; 4662 #size-cells = <1>;
5083 4663
5084 ranges = <0 0 0x146bf 4664 ranges = <0 0 0x146bf000 0x1000>;
5085 4665
5086 pil-reloc@94c { 4666 pil-reloc@94c {
5087 compatible = 4667 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 4668 reg = <0x94c 0xc8>;
5089 }; 4669 };
5090 }; 4670 };
5091 4671
5092 apps_smmu: iommu@15000000 { 4672 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 4673 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 4674 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 4675 #iommu-cells = <2>;
5096 #global-interrupts = 4676 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 4677 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 4678 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 4679 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 4680 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 4681 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 4682 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 4683 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 4684 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 4685 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 4686 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4687 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4688 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 4689 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 4690 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 4691 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 4692 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 4693 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 4694 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 4695 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 4696 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 4697 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 4698 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 4699 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 4700 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 4701 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 4702 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 4703 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 4704 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 4705 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 4706 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 4707 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 4708 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 4709 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 4710 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 4711 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4712 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 4713 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 4714 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 4715 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 4716 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 4717 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4718 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 4719 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 4720 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 4721 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 4722 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 4723 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4724 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 4725 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 4726 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 4727 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 4728 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 4729 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 4730 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 4731 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 4732 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 4733 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 4734 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 4735 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 4736 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 4737 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 4738 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 4739 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 4740 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 4741 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 4742 };
5163 4743
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 4744 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 4745 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 4746 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 4747 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 4748 #clock-cells = <1>;
5241 status = "disabled"; 4749 status = "disabled";
5242 }; 4750 };
5243 4751
5244 gladiator_noc: interconnect@1 4752 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 4753 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 4754 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 4755 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 4756 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 4757 };
5250 4758
5251 watchdog@17980000 { 4759 watchdog@17980000 {
5252 compatible = "qcom,ap 4760 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 4761 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 4762 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI !! 4763 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256 }; 4764 };
5257 4765
5258 apss_shared: mailbox@17990000 4766 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 4767 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 4768 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 4769 #mbox-cells = <1>;
5262 }; 4770 };
5263 4771
5264 apps_rsc: rsc@179c0000 { 4772 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 4773 label = "apps_rsc";
5266 compatible = "qcom,rp 4774 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 4775 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 4776 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 4777 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 4778 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 4779 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 4780 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 4781 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 4782 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 4783 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 4784 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 4785 <SLEEP_TCS 3>,
5278 <WA 4786 <WAKE_TCS 3>,
5279 <CO 4787 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 4788
5282 apps_bcm_voter: bcm-v 4789 apps_bcm_voter: bcm-voter {
5283 compatible = 4790 compatible = "qcom,bcm-voter";
5284 }; 4791 };
5285 4792
5286 rpmhcc: clock-control 4793 rpmhcc: clock-controller {
5287 compatible = 4794 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 4795 #clock-cells = <1>;
5289 clock-names = 4796 clock-names = "xo";
5290 clocks = <&xo 4797 clocks = <&xo_board>;
5291 }; 4798 };
5292 4799
5293 rpmhpd: power-control 4800 rpmhpd: power-controller {
5294 compatible = 4801 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 4802 #power-domain-cells = <1>;
5296 operating-poi 4803 operating-points-v2 = <&rpmhpd_opp_table>;
5297 4804
5298 rpmhpd_opp_ta 4805 rpmhpd_opp_table: opp-table {
5299 compa 4806 compatible = "operating-points-v2";
5300 4807
5301 rpmhp 4808 rpmhpd_opp_ret: opp1 {
5302 4809 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 4810 };
5304 4811
5305 rpmhp 4812 rpmhpd_opp_min_svs: opp2 {
5306 4813 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 4814 };
5308 4815
5309 rpmhp 4816 rpmhpd_opp_low_svs: opp3 {
5310 4817 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 4818 };
5312 4819
5313 rpmhp 4820 rpmhpd_opp_svs: opp4 {
5314 4821 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 4822 };
5316 4823
5317 rpmhp 4824 rpmhpd_opp_svs_l1: opp5 {
5318 4825 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 4826 };
5320 4827
5321 rpmhp 4828 rpmhpd_opp_nom: opp6 {
5322 4829 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 4830 };
5324 4831
5325 rpmhp 4832 rpmhpd_opp_nom_l1: opp7 {
5326 4833 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 4834 };
5328 4835
5329 rpmhp 4836 rpmhpd_opp_nom_l2: opp8 {
5330 4837 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 4838 };
5332 4839
5333 rpmhp 4840 rpmhpd_opp_turbo: opp9 {
5334 4841 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 4842 };
5336 4843
5337 rpmhp 4844 rpmhpd_opp_turbo_l1: opp10 {
5338 4845 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 4846 };
5340 }; 4847 };
5341 }; 4848 };
5342 }; 4849 };
5343 4850
5344 intc: interrupt-controller@17 4851 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 4852 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 4853 #address-cells = <2>;
5347 #size-cells = <2>; 4854 #size-cells = <2>;
5348 ranges; 4855 ranges;
5349 #interrupt-cells = <3 4856 #interrupt-cells = <3>;
5350 interrupt-controller; 4857 interrupt-controller;
5351 reg = <0 0x17a00000 0 4858 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 4859 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 4860 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 4861
5355 msi-controller@17a400 4862 msi-controller@17a40000 {
5356 compatible = 4863 compatible = "arm,gic-v3-its";
5357 msi-controlle 4864 msi-controller;
5358 #msi-cells = 4865 #msi-cells = <1>;
5359 reg = <0 0x17 4866 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 4867 status = "disabled";
5361 }; 4868 };
5362 }; 4869 };
5363 4870
5364 slimbam: dma-controller@17184 4871 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba !! 4872 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 4873 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 4874 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; !! 4875 num-channels = <31>;
5369 interrupts = <GIC_SPI 4876 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 4877 #dma-cells = <1>;
5371 qcom,ee = <1>; 4878 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 4879 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 4880 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 4881 };
5375 4882
5376 timer@17c90000 { 4883 timer@17c90000 {
5377 #address-cells = <1>; !! 4884 #address-cells = <2>;
5378 #size-cells = <1>; !! 4885 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 4886 ranges;
5380 compatible = "arm,arm 4887 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 4888 reg = <0 0x17c90000 0 0x1000>;
5382 4889
5383 frame@17ca0000 { 4890 frame@17ca0000 {
5384 frame-number 4891 frame-number = <0>;
5385 interrupts = 4892 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 4893 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 4894 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 4895 <0 0x17cb0000 0 0x1000>;
5389 }; 4896 };
5390 4897
5391 frame@17cc0000 { 4898 frame@17cc0000 {
5392 frame-number 4899 frame-number = <1>;
5393 interrupts = 4900 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 4901 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 4902 status = "disabled";
5396 }; 4903 };
5397 4904
5398 frame@17cd0000 { 4905 frame@17cd0000 {
5399 frame-number 4906 frame-number = <2>;
5400 interrupts = 4907 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 4908 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 4909 status = "disabled";
5403 }; 4910 };
5404 4911
5405 frame@17ce0000 { 4912 frame@17ce0000 {
5406 frame-number 4913 frame-number = <3>;
5407 interrupts = 4914 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 4915 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 4916 status = "disabled";
5410 }; 4917 };
5411 4918
5412 frame@17cf0000 { 4919 frame@17cf0000 {
5413 frame-number 4920 frame-number = <4>;
5414 interrupts = 4921 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 4922 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 4923 status = "disabled";
5417 }; 4924 };
5418 4925
5419 frame@17d00000 { 4926 frame@17d00000 {
5420 frame-number 4927 frame-number = <5>;
5421 interrupts = 4928 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 4929 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 4930 status = "disabled";
5424 }; 4931 };
5425 4932
5426 frame@17d10000 { 4933 frame@17d10000 {
5427 frame-number 4934 frame-number = <6>;
5428 interrupts = 4935 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 4936 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 4937 status = "disabled";
5431 }; 4938 };
5432 }; 4939 };
5433 4940
5434 osm_l3: interconnect@17d41000 4941 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 4942 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 4943 reg = <0 0x17d41000 0 0x1400>;
5437 4944
5438 clocks = <&rpmhcc RPM 4945 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 4946 clock-names = "xo", "alternate";
5440 4947
5441 #interconnect-cells = 4948 #interconnect-cells = <1>;
5442 }; 4949 };
5443 4950
5444 cpufreq_hw: cpufreq@17d43000 4951 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 4952 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 4953 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 4954 reg-names = "freq-domain0", "freq-domain1";
5448 4955
5449 interrupts-extended = 4956 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450 4957
5451 clocks = <&rpmhcc RPM 4958 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 4959 clock-names = "xo", "alternate";
5453 4960
5454 #freq-domain-cells = 4961 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 4962 };
5457 4963
5458 wifi: wifi@18800000 { 4964 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 4965 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 4966 status = "disabled";
5461 reg = <0 0x18800000 0 4967 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 4968 reg-names = "membase";
5463 memory-region = <&wla 4969 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 4970 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 4971 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 4972 interrupts =
5467 <GIC_SPI 414 4973 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 4974 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 4975 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 4976 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 4977 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 4978 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 4979 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 4980 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 4981 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 4982 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 4983 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 4984 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 4985 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 4986 };
5481 }; 4987 };
5482 4988
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 4989 thermal-zones {
5487 cpu0-thermal { 4990 cpu0-thermal {
5488 polling-delay-passive 4991 polling-delay-passive = <250>;
>> 4992 polling-delay = <1000>;
5489 4993
5490 thermal-sensors = <&t 4994 thermal-sensors = <&tsens0 1>;
5491 4995
5492 trips { 4996 trips {
5493 cpu0_alert0: 4997 cpu0_alert0: trip-point0 {
5494 tempe 4998 temperature = <90000>;
5495 hyste 4999 hysteresis = <2000>;
5496 type 5000 type = "passive";
5497 }; 5001 };
5498 5002
5499 cpu0_alert1: 5003 cpu0_alert1: trip-point1 {
5500 tempe 5004 temperature = <95000>;
5501 hyste 5005 hysteresis = <2000>;
5502 type 5006 type = "passive";
5503 }; 5007 };
5504 5008
5505 cpu0_crit: cp !! 5009 cpu0_crit: cpu_crit {
5506 tempe 5010 temperature = <110000>;
5507 hyste 5011 hysteresis = <1000>;
5508 type 5012 type = "critical";
5509 }; 5013 };
5510 }; 5014 };
5511 }; 5015 };
5512 5016
5513 cpu1-thermal { 5017 cpu1-thermal {
5514 polling-delay-passive 5018 polling-delay-passive = <250>;
>> 5019 polling-delay = <1000>;
5515 5020
5516 thermal-sensors = <&t 5021 thermal-sensors = <&tsens0 2>;
5517 5022
5518 trips { 5023 trips {
5519 cpu1_alert0: 5024 cpu1_alert0: trip-point0 {
5520 tempe 5025 temperature = <90000>;
5521 hyste 5026 hysteresis = <2000>;
5522 type 5027 type = "passive";
5523 }; 5028 };
5524 5029
5525 cpu1_alert1: 5030 cpu1_alert1: trip-point1 {
5526 tempe 5031 temperature = <95000>;
5527 hyste 5032 hysteresis = <2000>;
5528 type 5033 type = "passive";
5529 }; 5034 };
5530 5035
5531 cpu1_crit: cp !! 5036 cpu1_crit: cpu_crit {
5532 tempe 5037 temperature = <110000>;
5533 hyste 5038 hysteresis = <1000>;
5534 type 5039 type = "critical";
5535 }; 5040 };
5536 }; 5041 };
5537 }; 5042 };
5538 5043
5539 cpu2-thermal { 5044 cpu2-thermal {
5540 polling-delay-passive 5045 polling-delay-passive = <250>;
>> 5046 polling-delay = <1000>;
5541 5047
5542 thermal-sensors = <&t 5048 thermal-sensors = <&tsens0 3>;
5543 5049
5544 trips { 5050 trips {
5545 cpu2_alert0: 5051 cpu2_alert0: trip-point0 {
5546 tempe 5052 temperature = <90000>;
5547 hyste 5053 hysteresis = <2000>;
5548 type 5054 type = "passive";
5549 }; 5055 };
5550 5056
5551 cpu2_alert1: 5057 cpu2_alert1: trip-point1 {
5552 tempe 5058 temperature = <95000>;
5553 hyste 5059 hysteresis = <2000>;
5554 type 5060 type = "passive";
5555 }; 5061 };
5556 5062
5557 cpu2_crit: cp !! 5063 cpu2_crit: cpu_crit {
5558 tempe 5064 temperature = <110000>;
5559 hyste 5065 hysteresis = <1000>;
5560 type 5066 type = "critical";
5561 }; 5067 };
5562 }; 5068 };
5563 }; 5069 };
5564 5070
5565 cpu3-thermal { 5071 cpu3-thermal {
5566 polling-delay-passive 5072 polling-delay-passive = <250>;
>> 5073 polling-delay = <1000>;
5567 5074
5568 thermal-sensors = <&t 5075 thermal-sensors = <&tsens0 4>;
5569 5076
5570 trips { 5077 trips {
5571 cpu3_alert0: 5078 cpu3_alert0: trip-point0 {
5572 tempe 5079 temperature = <90000>;
5573 hyste 5080 hysteresis = <2000>;
5574 type 5081 type = "passive";
5575 }; 5082 };
5576 5083
5577 cpu3_alert1: 5084 cpu3_alert1: trip-point1 {
5578 tempe 5085 temperature = <95000>;
5579 hyste 5086 hysteresis = <2000>;
5580 type 5087 type = "passive";
5581 }; 5088 };
5582 5089
5583 cpu3_crit: cp !! 5090 cpu3_crit: cpu_crit {
5584 tempe 5091 temperature = <110000>;
5585 hyste 5092 hysteresis = <1000>;
5586 type 5093 type = "critical";
5587 }; 5094 };
5588 }; 5095 };
5589 }; 5096 };
5590 5097
5591 cpu4-thermal { 5098 cpu4-thermal {
5592 polling-delay-passive 5099 polling-delay-passive = <250>;
>> 5100 polling-delay = <1000>;
5593 5101
5594 thermal-sensors = <&t 5102 thermal-sensors = <&tsens0 7>;
5595 5103
5596 trips { 5104 trips {
5597 cpu4_alert0: 5105 cpu4_alert0: trip-point0 {
5598 tempe 5106 temperature = <90000>;
5599 hyste 5107 hysteresis = <2000>;
5600 type 5108 type = "passive";
5601 }; 5109 };
5602 5110
5603 cpu4_alert1: 5111 cpu4_alert1: trip-point1 {
5604 tempe 5112 temperature = <95000>;
5605 hyste 5113 hysteresis = <2000>;
5606 type 5114 type = "passive";
5607 }; 5115 };
5608 5116
5609 cpu4_crit: cp !! 5117 cpu4_crit: cpu_crit {
5610 tempe 5118 temperature = <110000>;
5611 hyste 5119 hysteresis = <1000>;
5612 type 5120 type = "critical";
5613 }; 5121 };
5614 }; 5122 };
5615 }; 5123 };
5616 5124
5617 cpu5-thermal { 5125 cpu5-thermal {
5618 polling-delay-passive 5126 polling-delay-passive = <250>;
>> 5127 polling-delay = <1000>;
5619 5128
5620 thermal-sensors = <&t 5129 thermal-sensors = <&tsens0 8>;
5621 5130
5622 trips { 5131 trips {
5623 cpu5_alert0: 5132 cpu5_alert0: trip-point0 {
5624 tempe 5133 temperature = <90000>;
5625 hyste 5134 hysteresis = <2000>;
5626 type 5135 type = "passive";
5627 }; 5136 };
5628 5137
5629 cpu5_alert1: 5138 cpu5_alert1: trip-point1 {
5630 tempe 5139 temperature = <95000>;
5631 hyste 5140 hysteresis = <2000>;
5632 type 5141 type = "passive";
5633 }; 5142 };
5634 5143
5635 cpu5_crit: cp !! 5144 cpu5_crit: cpu_crit {
5636 tempe 5145 temperature = <110000>;
5637 hyste 5146 hysteresis = <1000>;
5638 type 5147 type = "critical";
5639 }; 5148 };
5640 }; 5149 };
5641 }; 5150 };
5642 5151
5643 cpu6-thermal { 5152 cpu6-thermal {
5644 polling-delay-passive 5153 polling-delay-passive = <250>;
>> 5154 polling-delay = <1000>;
5645 5155
5646 thermal-sensors = <&t 5156 thermal-sensors = <&tsens0 9>;
5647 5157
5648 trips { 5158 trips {
5649 cpu6_alert0: 5159 cpu6_alert0: trip-point0 {
5650 tempe 5160 temperature = <90000>;
5651 hyste 5161 hysteresis = <2000>;
5652 type 5162 type = "passive";
5653 }; 5163 };
5654 5164
5655 cpu6_alert1: 5165 cpu6_alert1: trip-point1 {
5656 tempe 5166 temperature = <95000>;
5657 hyste 5167 hysteresis = <2000>;
5658 type 5168 type = "passive";
5659 }; 5169 };
5660 5170
5661 cpu6_crit: cp !! 5171 cpu6_crit: cpu_crit {
5662 tempe 5172 temperature = <110000>;
5663 hyste 5173 hysteresis = <1000>;
5664 type 5174 type = "critical";
5665 }; 5175 };
5666 }; 5176 };
5667 }; 5177 };
5668 5178
5669 cpu7-thermal { 5179 cpu7-thermal {
5670 polling-delay-passive 5180 polling-delay-passive = <250>;
>> 5181 polling-delay = <1000>;
5671 5182
5672 thermal-sensors = <&t 5183 thermal-sensors = <&tsens0 10>;
5673 5184
5674 trips { 5185 trips {
5675 cpu7_alert0: 5186 cpu7_alert0: trip-point0 {
5676 tempe 5187 temperature = <90000>;
5677 hyste 5188 hysteresis = <2000>;
5678 type 5189 type = "passive";
5679 }; 5190 };
5680 5191
5681 cpu7_alert1: 5192 cpu7_alert1: trip-point1 {
5682 tempe 5193 temperature = <95000>;
5683 hyste 5194 hysteresis = <2000>;
5684 type 5195 type = "passive";
5685 }; 5196 };
5686 5197
5687 cpu7_crit: cp !! 5198 cpu7_crit: cpu_crit {
5688 tempe 5199 temperature = <110000>;
5689 hyste 5200 hysteresis = <1000>;
5690 type 5201 type = "critical";
5691 }; 5202 };
5692 }; 5203 };
5693 }; 5204 };
5694 5205
5695 aoss0-thermal { 5206 aoss0-thermal {
5696 polling-delay-passive 5207 polling-delay-passive = <250>;
>> 5208 polling-delay = <1000>;
5697 5209
5698 thermal-sensors = <&t 5210 thermal-sensors = <&tsens0 0>;
5699 5211
5700 trips { 5212 trips {
5701 aoss0_alert0: 5213 aoss0_alert0: trip-point0 {
5702 tempe 5214 temperature = <90000>;
5703 hyste 5215 hysteresis = <2000>;
5704 type 5216 type = "hot";
5705 }; 5217 };
5706 }; 5218 };
5707 }; 5219 };
5708 5220
5709 cluster0-thermal { 5221 cluster0-thermal {
5710 polling-delay-passive 5222 polling-delay-passive = <250>;
>> 5223 polling-delay = <1000>;
5711 5224
5712 thermal-sensors = <&t 5225 thermal-sensors = <&tsens0 5>;
5713 5226
5714 trips { 5227 trips {
5715 cluster0_aler 5228 cluster0_alert0: trip-point0 {
5716 tempe 5229 temperature = <90000>;
5717 hyste 5230 hysteresis = <2000>;
5718 type 5231 type = "hot";
5719 }; 5232 };
5720 cluster0_crit !! 5233 cluster0_crit: cluster0_crit {
5721 tempe 5234 temperature = <110000>;
5722 hyste 5235 hysteresis = <2000>;
5723 type 5236 type = "critical";
5724 }; 5237 };
5725 }; 5238 };
5726 }; 5239 };
5727 5240
5728 cluster1-thermal { 5241 cluster1-thermal {
5729 polling-delay-passive 5242 polling-delay-passive = <250>;
>> 5243 polling-delay = <1000>;
5730 5244
5731 thermal-sensors = <&t 5245 thermal-sensors = <&tsens0 6>;
5732 5246
5733 trips { 5247 trips {
5734 cluster1_aler 5248 cluster1_alert0: trip-point0 {
5735 tempe 5249 temperature = <90000>;
5736 hyste 5250 hysteresis = <2000>;
5737 type 5251 type = "hot";
5738 }; 5252 };
5739 cluster1_crit !! 5253 cluster1_crit: cluster1_crit {
5740 tempe 5254 temperature = <110000>;
5741 hyste 5255 hysteresis = <2000>;
5742 type 5256 type = "critical";
5743 }; 5257 };
5744 }; 5258 };
5745 }; 5259 };
5746 5260
5747 gpu-top-thermal { !! 5261 gpu-thermal-top {
5748 polling-delay-passive 5262 polling-delay-passive = <250>;
>> 5263 polling-delay = <1000>;
5749 5264
5750 thermal-sensors = <&t 5265 thermal-sensors = <&tsens0 11>;
5751 5266
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5267 trips {
5760 gpu_top_alert !! 5268 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5269 temperature = <90000>;
5768 hyste !! 5270 hysteresis = <2000>;
5769 type 5271 type = "hot";
5770 }; 5272 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5273 };
5778 }; 5274 };
5779 5275
5780 gpu-bottom-thermal { !! 5276 gpu-thermal-bottom {
5781 polling-delay-passive 5277 polling-delay-passive = <250>;
>> 5278 polling-delay = <1000>;
5782 5279
5783 thermal-sensors = <&t 5280 thermal-sensors = <&tsens0 12>;
5784 5281
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5282 trips {
5793 gpu_bottom_al !! 5283 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5284 temperature = <90000>;
5801 hyste !! 5285 hysteresis = <2000>;
5802 type 5286 type = "hot";
5803 }; 5287 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5288 };
5811 }; 5289 };
5812 5290
5813 aoss1-thermal { 5291 aoss1-thermal {
5814 polling-delay-passive 5292 polling-delay-passive = <250>;
>> 5293 polling-delay = <1000>;
5815 5294
5816 thermal-sensors = <&t 5295 thermal-sensors = <&tsens1 0>;
5817 5296
5818 trips { 5297 trips {
5819 aoss1_alert0: 5298 aoss1_alert0: trip-point0 {
5820 tempe 5299 temperature = <90000>;
5821 hyste 5300 hysteresis = <2000>;
5822 type 5301 type = "hot";
5823 }; 5302 };
5824 }; 5303 };
5825 }; 5304 };
5826 5305
5827 q6-modem-thermal { 5306 q6-modem-thermal {
5828 polling-delay-passive 5307 polling-delay-passive = <250>;
>> 5308 polling-delay = <1000>;
5829 5309
5830 thermal-sensors = <&t 5310 thermal-sensors = <&tsens1 1>;
5831 5311
5832 trips { 5312 trips {
5833 q6_modem_aler 5313 q6_modem_alert0: trip-point0 {
5834 tempe 5314 temperature = <90000>;
5835 hyste 5315 hysteresis = <2000>;
5836 type 5316 type = "hot";
5837 }; 5317 };
5838 }; 5318 };
5839 }; 5319 };
5840 5320
5841 mem-thermal { 5321 mem-thermal {
5842 polling-delay-passive 5322 polling-delay-passive = <250>;
>> 5323 polling-delay = <1000>;
5843 5324
5844 thermal-sensors = <&t 5325 thermal-sensors = <&tsens1 2>;
5845 5326
5846 trips { 5327 trips {
5847 mem_alert0: t 5328 mem_alert0: trip-point0 {
5848 tempe 5329 temperature = <90000>;
5849 hyste 5330 hysteresis = <2000>;
5850 type 5331 type = "hot";
5851 }; 5332 };
5852 }; 5333 };
5853 }; 5334 };
5854 5335
5855 wlan-thermal { 5336 wlan-thermal {
5856 polling-delay-passive 5337 polling-delay-passive = <250>;
>> 5338 polling-delay = <1000>;
5857 5339
5858 thermal-sensors = <&t 5340 thermal-sensors = <&tsens1 3>;
5859 5341
5860 trips { 5342 trips {
5861 wlan_alert0: 5343 wlan_alert0: trip-point0 {
5862 tempe 5344 temperature = <90000>;
5863 hyste 5345 hysteresis = <2000>;
5864 type 5346 type = "hot";
5865 }; 5347 };
5866 }; 5348 };
5867 }; 5349 };
5868 5350
5869 q6-hvx-thermal { 5351 q6-hvx-thermal {
5870 polling-delay-passive 5352 polling-delay-passive = <250>;
>> 5353 polling-delay = <1000>;
5871 5354
5872 thermal-sensors = <&t 5355 thermal-sensors = <&tsens1 4>;
5873 5356
5874 trips { 5357 trips {
5875 q6_hvx_alert0 5358 q6_hvx_alert0: trip-point0 {
5876 tempe 5359 temperature = <90000>;
5877 hyste 5360 hysteresis = <2000>;
5878 type 5361 type = "hot";
5879 }; 5362 };
5880 }; 5363 };
5881 }; 5364 };
5882 5365
5883 camera-thermal { 5366 camera-thermal {
5884 polling-delay-passive 5367 polling-delay-passive = <250>;
>> 5368 polling-delay = <1000>;
5885 5369
5886 thermal-sensors = <&t 5370 thermal-sensors = <&tsens1 5>;
5887 5371
5888 trips { 5372 trips {
5889 camera_alert0 5373 camera_alert0: trip-point0 {
5890 tempe 5374 temperature = <90000>;
5891 hyste 5375 hysteresis = <2000>;
5892 type 5376 type = "hot";
5893 }; 5377 };
5894 }; 5378 };
5895 }; 5379 };
5896 5380
5897 video-thermal { 5381 video-thermal {
5898 polling-delay-passive 5382 polling-delay-passive = <250>;
>> 5383 polling-delay = <1000>;
5899 5384
5900 thermal-sensors = <&t 5385 thermal-sensors = <&tsens1 6>;
5901 5386
5902 trips { 5387 trips {
5903 video_alert0: 5388 video_alert0: trip-point0 {
5904 tempe 5389 temperature = <90000>;
5905 hyste 5390 hysteresis = <2000>;
5906 type 5391 type = "hot";
5907 }; 5392 };
5908 }; 5393 };
5909 }; 5394 };
5910 5395
5911 modem-thermal { 5396 modem-thermal {
5912 polling-delay-passive 5397 polling-delay-passive = <250>;
>> 5398 polling-delay = <1000>;
5913 5399
5914 thermal-sensors = <&t 5400 thermal-sensors = <&tsens1 7>;
5915 5401
5916 trips { 5402 trips {
5917 modem_alert0: 5403 modem_alert0: trip-point0 {
5918 tempe 5404 temperature = <90000>;
5919 hyste 5405 hysteresis = <2000>;
5920 type 5406 type = "hot";
5921 }; 5407 };
5922 }; 5408 };
5923 }; 5409 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5410 };
5933 }; 5411 };
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