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Linux/scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi (Version linux-5.18.19)


  1 // SPDX-License-Identifier: GPL-2.0                 1 // SPDX-License-Identifier: GPL-2.0
  2 /*                                                  2 /*
  3  * SDM845 SoC device tree source                    3  * SDM845 SoC device tree source
  4  *                                                  4  *
  5  * Copyright (c) 2018, The Linux Foundation. A      5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  6  */                                                 6  */
  7                                                     7 
  8 #include <dt-bindings/clock/qcom,camcc-sdm845.      8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
  9 #include <dt-bindings/clock/qcom,dispcc-sdm845      9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>     10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.     11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 12 #include <dt-bindings/clock/qcom,lpass-sdm845.     12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
 13 #include <dt-bindings/clock/qcom,rpmh.h>           13 #include <dt-bindings/clock/qcom,rpmh.h>
 14 #include <dt-bindings/clock/qcom,videocc-sdm84     14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
 15 #include <dt-bindings/dma/qcom-gpi.h>              15 #include <dt-bindings/dma/qcom-gpi.h>
 16 #include <dt-bindings/firmware/qcom,scm.h>     << 
 17 #include <dt-bindings/gpio/gpio.h>                 16 #include <dt-bindings/gpio/gpio.h>
 18 #include <dt-bindings/interconnect/qcom,icc.h> << 
 19 #include <dt-bindings/interconnect/qcom,osm-l3     17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 20 #include <dt-bindings/interconnect/qcom,sdm845     18 #include <dt-bindings/interconnect/qcom,sdm845.h>
 21 #include <dt-bindings/interrupt-controller/arm     19 #include <dt-bindings/interrupt-controller/arm-gic.h>
 22 #include <dt-bindings/phy/phy-qcom-qmp.h>      << 
 23 #include <dt-bindings/phy/phy-qcom-qusb2.h>        20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
 24 #include <dt-bindings/power/qcom-rpmpd.h>          21 #include <dt-bindings/power/qcom-rpmpd.h>
 25 #include <dt-bindings/reset/qcom,sdm845-aoss.h     22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>     23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
 27 #include <dt-bindings/soc/qcom,apr.h>              24 #include <dt-bindings/soc/qcom,apr.h>
 28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>         25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 29 #include <dt-bindings/clock/qcom,gcc-sdm845.h>     26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 30 #include <dt-bindings/thermal/thermal.h>           27 #include <dt-bindings/thermal/thermal.h>
 31                                                    28 
 32 / {                                                29 / {
 33         interrupt-parent = <&intc>;                30         interrupt-parent = <&intc>;
 34                                                    31 
 35         #address-cells = <2>;                      32         #address-cells = <2>;
 36         #size-cells = <2>;                         33         #size-cells = <2>;
 37                                                    34 
 38         aliases {                                  35         aliases {
 39                 i2c0 = &i2c0;                      36                 i2c0 = &i2c0;
 40                 i2c1 = &i2c1;                      37                 i2c1 = &i2c1;
 41                 i2c2 = &i2c2;                      38                 i2c2 = &i2c2;
 42                 i2c3 = &i2c3;                      39                 i2c3 = &i2c3;
 43                 i2c4 = &i2c4;                      40                 i2c4 = &i2c4;
 44                 i2c5 = &i2c5;                      41                 i2c5 = &i2c5;
 45                 i2c6 = &i2c6;                      42                 i2c6 = &i2c6;
 46                 i2c7 = &i2c7;                      43                 i2c7 = &i2c7;
 47                 i2c8 = &i2c8;                      44                 i2c8 = &i2c8;
 48                 i2c9 = &i2c9;                      45                 i2c9 = &i2c9;
 49                 i2c10 = &i2c10;                    46                 i2c10 = &i2c10;
 50                 i2c11 = &i2c11;                    47                 i2c11 = &i2c11;
 51                 i2c12 = &i2c12;                    48                 i2c12 = &i2c12;
 52                 i2c13 = &i2c13;                    49                 i2c13 = &i2c13;
 53                 i2c14 = &i2c14;                    50                 i2c14 = &i2c14;
 54                 i2c15 = &i2c15;                    51                 i2c15 = &i2c15;
 55                 spi0 = &spi0;                      52                 spi0 = &spi0;
 56                 spi1 = &spi1;                      53                 spi1 = &spi1;
 57                 spi2 = &spi2;                      54                 spi2 = &spi2;
 58                 spi3 = &spi3;                      55                 spi3 = &spi3;
 59                 spi4 = &spi4;                      56                 spi4 = &spi4;
 60                 spi5 = &spi5;                      57                 spi5 = &spi5;
 61                 spi6 = &spi6;                      58                 spi6 = &spi6;
 62                 spi7 = &spi7;                      59                 spi7 = &spi7;
 63                 spi8 = &spi8;                      60                 spi8 = &spi8;
 64                 spi9 = &spi9;                      61                 spi9 = &spi9;
 65                 spi10 = &spi10;                    62                 spi10 = &spi10;
 66                 spi11 = &spi11;                    63                 spi11 = &spi11;
 67                 spi12 = &spi12;                    64                 spi12 = &spi12;
 68                 spi13 = &spi13;                    65                 spi13 = &spi13;
 69                 spi14 = &spi14;                    66                 spi14 = &spi14;
 70                 spi15 = &spi15;                    67                 spi15 = &spi15;
 71         };                                         68         };
 72                                                    69 
 73         chosen { };                                70         chosen { };
 74                                                    71 
 75         clocks {                               !!  72         memory@80000000 {
 76                 xo_board: xo-board {           !!  73                 device_type = "memory";
 77                         compatible = "fixed-cl !!  74                 /* We expect the bootloader to fill in the size */
 78                         #clock-cells = <0>;    !!  75                 reg = <0 0x80000000 0 0>;
 79                         clock-frequency = <384 !!  76         };
 80                         clock-output-names = " !!  77 
                                                   >>  78         reserved-memory {
                                                   >>  79                 #address-cells = <2>;
                                                   >>  80                 #size-cells = <2>;
                                                   >>  81                 ranges;
                                                   >>  82 
                                                   >>  83                 hyp_mem: hyp-mem@85700000 {
                                                   >>  84                         reg = <0 0x85700000 0 0x600000>;
                                                   >>  85                         no-map;
 81                 };                                 86                 };
 82                                                    87 
 83                 sleep_clk: sleep-clk {         !!  88                 xbl_mem: xbl-mem@85e00000 {
 84                         compatible = "fixed-cl !!  89                         reg = <0 0x85e00000 0 0x100000>;
 85                         #clock-cells = <0>;    !!  90                         no-map;
 86                         clock-frequency = <327 !!  91                 };
                                                   >>  92 
                                                   >>  93                 aop_mem: aop-mem@85fc0000 {
                                                   >>  94                         reg = <0 0x85fc0000 0 0x20000>;
                                                   >>  95                         no-map;
                                                   >>  96                 };
                                                   >>  97 
                                                   >>  98                 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
                                                   >>  99                         compatible = "qcom,cmd-db";
                                                   >> 100                         reg = <0x0 0x85fe0000 0 0x20000>;
                                                   >> 101                         no-map;
                                                   >> 102                 };
                                                   >> 103 
                                                   >> 104                 smem@86000000 {
                                                   >> 105                         compatible = "qcom,smem";
                                                   >> 106                         reg = <0x0 0x86000000 0 0x200000>;
                                                   >> 107                         no-map;
                                                   >> 108                         hwlocks = <&tcsr_mutex 3>;
                                                   >> 109                 };
                                                   >> 110 
                                                   >> 111                 tz_mem: tz@86200000 {
                                                   >> 112                         reg = <0 0x86200000 0 0x2d00000>;
                                                   >> 113                         no-map;
                                                   >> 114                 };
                                                   >> 115 
                                                   >> 116                 rmtfs_mem: rmtfs@88f00000 {
                                                   >> 117                         compatible = "qcom,rmtfs-mem";
                                                   >> 118                         reg = <0 0x88f00000 0 0x200000>;
                                                   >> 119                         no-map;
                                                   >> 120 
                                                   >> 121                         qcom,client-id = <1>;
                                                   >> 122                         qcom,vmid = <15>;
                                                   >> 123                 };
                                                   >> 124 
                                                   >> 125                 qseecom_mem: qseecom@8ab00000 {
                                                   >> 126                         reg = <0 0x8ab00000 0 0x1400000>;
                                                   >> 127                         no-map;
                                                   >> 128                 };
                                                   >> 129 
                                                   >> 130                 camera_mem: camera-mem@8bf00000 {
                                                   >> 131                         reg = <0 0x8bf00000 0 0x500000>;
                                                   >> 132                         no-map;
                                                   >> 133                 };
                                                   >> 134 
                                                   >> 135                 ipa_fw_mem: ipa-fw@8c400000 {
                                                   >> 136                         reg = <0 0x8c400000 0 0x10000>;
                                                   >> 137                         no-map;
                                                   >> 138                 };
                                                   >> 139 
                                                   >> 140                 ipa_gsi_mem: ipa-gsi@8c410000 {
                                                   >> 141                         reg = <0 0x8c410000 0 0x5000>;
                                                   >> 142                         no-map;
                                                   >> 143                 };
                                                   >> 144 
                                                   >> 145                 gpu_mem: gpu@8c415000 {
                                                   >> 146                         reg = <0 0x8c415000 0 0x2000>;
                                                   >> 147                         no-map;
                                                   >> 148                 };
                                                   >> 149 
                                                   >> 150                 adsp_mem: adsp@8c500000 {
                                                   >> 151                         reg = <0 0x8c500000 0 0x1a00000>;
                                                   >> 152                         no-map;
                                                   >> 153                 };
                                                   >> 154 
                                                   >> 155                 wlan_msa_mem: wlan-msa@8df00000 {
                                                   >> 156                         reg = <0 0x8df00000 0 0x100000>;
                                                   >> 157                         no-map;
                                                   >> 158                 };
                                                   >> 159 
                                                   >> 160                 mpss_region: mpss@8e000000 {
                                                   >> 161                         reg = <0 0x8e000000 0 0x7800000>;
                                                   >> 162                         no-map;
                                                   >> 163                 };
                                                   >> 164 
                                                   >> 165                 venus_mem: venus@95800000 {
                                                   >> 166                         reg = <0 0x95800000 0 0x500000>;
                                                   >> 167                         no-map;
                                                   >> 168                 };
                                                   >> 169 
                                                   >> 170                 cdsp_mem: cdsp@95d00000 {
                                                   >> 171                         reg = <0 0x95d00000 0 0x800000>;
                                                   >> 172                         no-map;
                                                   >> 173                 };
                                                   >> 174 
                                                   >> 175                 mba_region: mba@96500000 {
                                                   >> 176                         reg = <0 0x96500000 0 0x200000>;
                                                   >> 177                         no-map;
                                                   >> 178                 };
                                                   >> 179 
                                                   >> 180                 slpi_mem: slpi@96700000 {
                                                   >> 181                         reg = <0 0x96700000 0 0x1400000>;
                                                   >> 182                         no-map;
                                                   >> 183                 };
                                                   >> 184 
                                                   >> 185                 spss_mem: spss@97b00000 {
                                                   >> 186                         reg = <0 0x97b00000 0 0x100000>;
                                                   >> 187                         no-map;
 87                 };                                188                 };
 88         };                                        189         };
 89                                                   190 
 90         cpus: cpus {                           !! 191         cpus {
 91                 #address-cells = <2>;             192                 #address-cells = <2>;
 92                 #size-cells = <0>;                193                 #size-cells = <0>;
 93                                                   194 
 94                 CPU0: cpu@0 {                     195                 CPU0: cpu@0 {
 95                         device_type = "cpu";      196                         device_type = "cpu";
 96                         compatible = "qcom,kry    197                         compatible = "qcom,kryo385";
 97                         reg = <0x0 0x0>;          198                         reg = <0x0 0x0>;
 98                         clocks = <&cpufreq_hw  << 
 99                         enable-method = "psci"    199                         enable-method = "psci";
100                         capacity-dmips-mhz = < !! 200                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101                         dynamic-power-coeffici !! 201                                            &LITTLE_CPU_SLEEP_1
                                                   >> 202                                            &CLUSTER_SLEEP_0>;
                                                   >> 203                         capacity-dmips-mhz = <607>;
                                                   >> 204                         dynamic-power-coefficient = <100>;
102                         qcom,freq-domain = <&c    205                         qcom,freq-domain = <&cpufreq_hw 0>;
103                         operating-points-v2 =     206                         operating-points-v2 = <&cpu0_opp_table>;
104                         interconnects = <&glad    207                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105                                         <&osm_    208                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106                         power-domains = <&CPU_ << 
107                         power-domain-names = " << 
108                         #cooling-cells = <2>;     209                         #cooling-cells = <2>;
109                         next-level-cache = <&L    210                         next-level-cache = <&L2_0>;
110                         L2_0: l2-cache {          211                         L2_0: l2-cache {
111                                 compatible = "    212                                 compatible = "cache";
112                                 cache-level =  << 
113                                 cache-unified; << 
114                                 next-level-cac    213                                 next-level-cache = <&L3_0>;
115                                 L3_0: l3-cache    214                                 L3_0: l3-cache {
116                                         compat !! 215                                       compatible = "cache";
117                                         cache- << 
118                                         cache- << 
119                                 };                216                                 };
120                         };                        217                         };
121                 };                                218                 };
122                                                   219 
123                 CPU1: cpu@100 {                   220                 CPU1: cpu@100 {
124                         device_type = "cpu";      221                         device_type = "cpu";
125                         compatible = "qcom,kry    222                         compatible = "qcom,kryo385";
126                         reg = <0x0 0x100>;        223                         reg = <0x0 0x100>;
127                         clocks = <&cpufreq_hw  << 
128                         enable-method = "psci"    224                         enable-method = "psci";
129                         capacity-dmips-mhz = < !! 225                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130                         dynamic-power-coeffici !! 226                                            &LITTLE_CPU_SLEEP_1
                                                   >> 227                                            &CLUSTER_SLEEP_0>;
                                                   >> 228                         capacity-dmips-mhz = <607>;
                                                   >> 229                         dynamic-power-coefficient = <100>;
131                         qcom,freq-domain = <&c    230                         qcom,freq-domain = <&cpufreq_hw 0>;
132                         operating-points-v2 =     231                         operating-points-v2 = <&cpu0_opp_table>;
133                         interconnects = <&glad    232                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134                                         <&osm_    233                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135                         power-domains = <&CPU_ << 
136                         power-domain-names = " << 
137                         #cooling-cells = <2>;     234                         #cooling-cells = <2>;
138                         next-level-cache = <&L    235                         next-level-cache = <&L2_100>;
139                         L2_100: l2-cache {        236                         L2_100: l2-cache {
140                                 compatible = "    237                                 compatible = "cache";
141                                 cache-level =  << 
142                                 cache-unified; << 
143                                 next-level-cac    238                                 next-level-cache = <&L3_0>;
144                         };                        239                         };
145                 };                                240                 };
146                                                   241 
147                 CPU2: cpu@200 {                   242                 CPU2: cpu@200 {
148                         device_type = "cpu";      243                         device_type = "cpu";
149                         compatible = "qcom,kry    244                         compatible = "qcom,kryo385";
150                         reg = <0x0 0x200>;        245                         reg = <0x0 0x200>;
151                         clocks = <&cpufreq_hw  << 
152                         enable-method = "psci"    246                         enable-method = "psci";
153                         capacity-dmips-mhz = < !! 247                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154                         dynamic-power-coeffici !! 248                                            &LITTLE_CPU_SLEEP_1
                                                   >> 249                                            &CLUSTER_SLEEP_0>;
                                                   >> 250                         capacity-dmips-mhz = <607>;
                                                   >> 251                         dynamic-power-coefficient = <100>;
155                         qcom,freq-domain = <&c    252                         qcom,freq-domain = <&cpufreq_hw 0>;
156                         operating-points-v2 =     253                         operating-points-v2 = <&cpu0_opp_table>;
157                         interconnects = <&glad    254                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158                                         <&osm_    255                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159                         power-domains = <&CPU_ << 
160                         power-domain-names = " << 
161                         #cooling-cells = <2>;     256                         #cooling-cells = <2>;
162                         next-level-cache = <&L    257                         next-level-cache = <&L2_200>;
163                         L2_200: l2-cache {        258                         L2_200: l2-cache {
164                                 compatible = "    259                                 compatible = "cache";
165                                 cache-level =  << 
166                                 cache-unified; << 
167                                 next-level-cac    260                                 next-level-cache = <&L3_0>;
168                         };                        261                         };
169                 };                                262                 };
170                                                   263 
171                 CPU3: cpu@300 {                   264                 CPU3: cpu@300 {
172                         device_type = "cpu";      265                         device_type = "cpu";
173                         compatible = "qcom,kry    266                         compatible = "qcom,kryo385";
174                         reg = <0x0 0x300>;        267                         reg = <0x0 0x300>;
175                         clocks = <&cpufreq_hw  << 
176                         enable-method = "psci"    268                         enable-method = "psci";
177                         capacity-dmips-mhz = < !! 269                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178                         dynamic-power-coeffici !! 270                                            &LITTLE_CPU_SLEEP_1
                                                   >> 271                                            &CLUSTER_SLEEP_0>;
                                                   >> 272                         capacity-dmips-mhz = <607>;
                                                   >> 273                         dynamic-power-coefficient = <100>;
179                         qcom,freq-domain = <&c    274                         qcom,freq-domain = <&cpufreq_hw 0>;
180                         operating-points-v2 =     275                         operating-points-v2 = <&cpu0_opp_table>;
181                         interconnects = <&glad    276                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182                                         <&osm_    277                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183                         #cooling-cells = <2>;     278                         #cooling-cells = <2>;
184                         power-domains = <&CPU_ << 
185                         power-domain-names = " << 
186                         next-level-cache = <&L    279                         next-level-cache = <&L2_300>;
187                         L2_300: l2-cache {        280                         L2_300: l2-cache {
188                                 compatible = "    281                                 compatible = "cache";
189                                 cache-level =  << 
190                                 cache-unified; << 
191                                 next-level-cac    282                                 next-level-cache = <&L3_0>;
192                         };                        283                         };
193                 };                                284                 };
194                                                   285 
195                 CPU4: cpu@400 {                   286                 CPU4: cpu@400 {
196                         device_type = "cpu";      287                         device_type = "cpu";
197                         compatible = "qcom,kry    288                         compatible = "qcom,kryo385";
198                         reg = <0x0 0x400>;        289                         reg = <0x0 0x400>;
199                         clocks = <&cpufreq_hw  << 
200                         enable-method = "psci"    290                         enable-method = "psci";
201                         capacity-dmips-mhz = <    291                         capacity-dmips-mhz = <1024>;
202                         dynamic-power-coeffici !! 292                         cpu-idle-states = <&BIG_CPU_SLEEP_0
                                                   >> 293                                            &BIG_CPU_SLEEP_1
                                                   >> 294                                            &CLUSTER_SLEEP_0>;
                                                   >> 295                         dynamic-power-coefficient = <396>;
203                         qcom,freq-domain = <&c    296                         qcom,freq-domain = <&cpufreq_hw 1>;
204                         operating-points-v2 =     297                         operating-points-v2 = <&cpu4_opp_table>;
205                         interconnects = <&glad    298                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206                                         <&osm_    299                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207                         power-domains = <&CPU_ << 
208                         power-domain-names = " << 
209                         #cooling-cells = <2>;     300                         #cooling-cells = <2>;
210                         next-level-cache = <&L    301                         next-level-cache = <&L2_400>;
211                         L2_400: l2-cache {        302                         L2_400: l2-cache {
212                                 compatible = "    303                                 compatible = "cache";
213                                 cache-level =  << 
214                                 cache-unified; << 
215                                 next-level-cac    304                                 next-level-cache = <&L3_0>;
216                         };                        305                         };
217                 };                                306                 };
218                                                   307 
219                 CPU5: cpu@500 {                   308                 CPU5: cpu@500 {
220                         device_type = "cpu";      309                         device_type = "cpu";
221                         compatible = "qcom,kry    310                         compatible = "qcom,kryo385";
222                         reg = <0x0 0x500>;        311                         reg = <0x0 0x500>;
223                         clocks = <&cpufreq_hw  << 
224                         enable-method = "psci"    312                         enable-method = "psci";
225                         capacity-dmips-mhz = <    313                         capacity-dmips-mhz = <1024>;
226                         dynamic-power-coeffici !! 314                         cpu-idle-states = <&BIG_CPU_SLEEP_0
                                                   >> 315                                            &BIG_CPU_SLEEP_1
                                                   >> 316                                            &CLUSTER_SLEEP_0>;
                                                   >> 317                         dynamic-power-coefficient = <396>;
227                         qcom,freq-domain = <&c    318                         qcom,freq-domain = <&cpufreq_hw 1>;
228                         operating-points-v2 =     319                         operating-points-v2 = <&cpu4_opp_table>;
229                         interconnects = <&glad    320                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230                                         <&osm_    321                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231                         power-domains = <&CPU_ << 
232                         power-domain-names = " << 
233                         #cooling-cells = <2>;     322                         #cooling-cells = <2>;
234                         next-level-cache = <&L    323                         next-level-cache = <&L2_500>;
235                         L2_500: l2-cache {        324                         L2_500: l2-cache {
236                                 compatible = "    325                                 compatible = "cache";
237                                 cache-level =  << 
238                                 cache-unified; << 
239                                 next-level-cac    326                                 next-level-cache = <&L3_0>;
240                         };                        327                         };
241                 };                                328                 };
242                                                   329 
243                 CPU6: cpu@600 {                   330                 CPU6: cpu@600 {
244                         device_type = "cpu";      331                         device_type = "cpu";
245                         compatible = "qcom,kry    332                         compatible = "qcom,kryo385";
246                         reg = <0x0 0x600>;        333                         reg = <0x0 0x600>;
247                         clocks = <&cpufreq_hw  << 
248                         enable-method = "psci"    334                         enable-method = "psci";
249                         capacity-dmips-mhz = <    335                         capacity-dmips-mhz = <1024>;
250                         dynamic-power-coeffici !! 336                         cpu-idle-states = <&BIG_CPU_SLEEP_0
                                                   >> 337                                            &BIG_CPU_SLEEP_1
                                                   >> 338                                            &CLUSTER_SLEEP_0>;
                                                   >> 339                         dynamic-power-coefficient = <396>;
251                         qcom,freq-domain = <&c    340                         qcom,freq-domain = <&cpufreq_hw 1>;
252                         operating-points-v2 =     341                         operating-points-v2 = <&cpu4_opp_table>;
253                         interconnects = <&glad    342                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254                                         <&osm_    343                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255                         power-domains = <&CPU_ << 
256                         power-domain-names = " << 
257                         #cooling-cells = <2>;     344                         #cooling-cells = <2>;
258                         next-level-cache = <&L    345                         next-level-cache = <&L2_600>;
259                         L2_600: l2-cache {        346                         L2_600: l2-cache {
260                                 compatible = "    347                                 compatible = "cache";
261                                 cache-level =  << 
262                                 cache-unified; << 
263                                 next-level-cac    348                                 next-level-cache = <&L3_0>;
264                         };                        349                         };
265                 };                                350                 };
266                                                   351 
267                 CPU7: cpu@700 {                   352                 CPU7: cpu@700 {
268                         device_type = "cpu";      353                         device_type = "cpu";
269                         compatible = "qcom,kry    354                         compatible = "qcom,kryo385";
270                         reg = <0x0 0x700>;        355                         reg = <0x0 0x700>;
271                         clocks = <&cpufreq_hw  << 
272                         enable-method = "psci"    356                         enable-method = "psci";
273                         capacity-dmips-mhz = <    357                         capacity-dmips-mhz = <1024>;
274                         dynamic-power-coeffici !! 358                         cpu-idle-states = <&BIG_CPU_SLEEP_0
                                                   >> 359                                            &BIG_CPU_SLEEP_1
                                                   >> 360                                            &CLUSTER_SLEEP_0>;
                                                   >> 361                         dynamic-power-coefficient = <396>;
275                         qcom,freq-domain = <&c    362                         qcom,freq-domain = <&cpufreq_hw 1>;
276                         operating-points-v2 =     363                         operating-points-v2 = <&cpu4_opp_table>;
277                         interconnects = <&glad    364                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278                                         <&osm_    365                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279                         power-domains = <&CPU_ << 
280                         power-domain-names = " << 
281                         #cooling-cells = <2>;     366                         #cooling-cells = <2>;
282                         next-level-cache = <&L    367                         next-level-cache = <&L2_700>;
283                         L2_700: l2-cache {        368                         L2_700: l2-cache {
284                                 compatible = "    369                                 compatible = "cache";
285                                 cache-level =  << 
286                                 cache-unified; << 
287                                 next-level-cac    370                                 next-level-cache = <&L3_0>;
288                         };                        371                         };
289                 };                                372                 };
290                                                   373 
291                 cpu-map {                         374                 cpu-map {
292                         cluster0 {                375                         cluster0 {
293                                 core0 {           376                                 core0 {
294                                         cpu =     377                                         cpu = <&CPU0>;
295                                 };                378                                 };
296                                                   379 
297                                 core1 {           380                                 core1 {
298                                         cpu =     381                                         cpu = <&CPU1>;
299                                 };                382                                 };
300                                                   383 
301                                 core2 {           384                                 core2 {
302                                         cpu =     385                                         cpu = <&CPU2>;
303                                 };                386                                 };
304                                                   387 
305                                 core3 {           388                                 core3 {
306                                         cpu =     389                                         cpu = <&CPU3>;
307                                 };                390                                 };
308                                                   391 
309                                 core4 {           392                                 core4 {
310                                         cpu =     393                                         cpu = <&CPU4>;
311                                 };                394                                 };
312                                                   395 
313                                 core5 {           396                                 core5 {
314                                         cpu =     397                                         cpu = <&CPU5>;
315                                 };                398                                 };
316                                                   399 
317                                 core6 {           400                                 core6 {
318                                         cpu =     401                                         cpu = <&CPU6>;
319                                 };                402                                 };
320                                                   403 
321                                 core7 {           404                                 core7 {
322                                         cpu =     405                                         cpu = <&CPU7>;
323                                 };                406                                 };
324                         };                        407                         };
325                 };                                408                 };
326                                                   409 
327                 cpu_idle_states: idle-states { !! 410                 idle-states {
328                         entry-method = "psci";    411                         entry-method = "psci";
329                                                   412 
330                         LITTLE_CPU_SLEEP_0: cp    413                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331                                 compatible = "    414                                 compatible = "arm,idle-state";
332                                 idle-state-nam !! 415                                 idle-state-name = "little-power-down";
333                                 arm,psci-suspe !! 416                                 arm,psci-suspend-param = <0x40000003>;
334                                 entry-latency-    417                                 entry-latency-us = <350>;
335                                 exit-latency-u    418                                 exit-latency-us = <461>;
336                                 min-residency-    419                                 min-residency-us = <1890>;
337                                 local-timer-st    420                                 local-timer-stop;
338                         };                        421                         };
339                                                   422 
340                         BIG_CPU_SLEEP_0: cpu-s !! 423                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341                                 compatible = "    424                                 compatible = "arm,idle-state";
342                                 idle-state-nam !! 425                                 idle-state-name = "little-rail-power-down";
343                                 arm,psci-suspe    426                                 arm,psci-suspend-param = <0x40000004>;
                                                   >> 427                                 entry-latency-us = <360>;
                                                   >> 428                                 exit-latency-us = <531>;
                                                   >> 429                                 min-residency-us = <3934>;
                                                   >> 430                                 local-timer-stop;
                                                   >> 431                         };
                                                   >> 432 
                                                   >> 433                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
                                                   >> 434                                 compatible = "arm,idle-state";
                                                   >> 435                                 idle-state-name = "big-power-down";
                                                   >> 436                                 arm,psci-suspend-param = <0x40000003>;
344                                 entry-latency-    437                                 entry-latency-us = <264>;
345                                 exit-latency-u    438                                 exit-latency-us = <621>;
346                                 min-residency-    439                                 min-residency-us = <952>;
347                                 local-timer-st    440                                 local-timer-stop;
348                         };                        441                         };
349                 };                             << 
350                                                   442 
351                 domain-idle-states {           !! 443                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
                                                   >> 444                                 compatible = "arm,idle-state";
                                                   >> 445                                 idle-state-name = "big-rail-power-down";
                                                   >> 446                                 arm,psci-suspend-param = <0x40000004>;
                                                   >> 447                                 entry-latency-us = <702>;
                                                   >> 448                                 exit-latency-us = <1061>;
                                                   >> 449                                 min-residency-us = <4488>;
                                                   >> 450                                 local-timer-stop;
                                                   >> 451                         };
                                                   >> 452 
352                         CLUSTER_SLEEP_0: clust    453                         CLUSTER_SLEEP_0: cluster-sleep-0 {
353                                 compatible = " !! 454                                 compatible = "arm,idle-state";
354                                 arm,psci-suspe !! 455                                 idle-state-name = "cluster-power-down";
                                                   >> 456                                 arm,psci-suspend-param = <0x400000F4>;
355                                 entry-latency-    457                                 entry-latency-us = <3263>;
356                                 exit-latency-u    458                                 exit-latency-us = <6562>;
357                                 min-residency-    459                                 min-residency-us = <9987>;
                                                   >> 460                                 local-timer-stop;
358                         };                        461                         };
359                 };                                462                 };
360         };                                        463         };
361                                                   464 
362         firmware {                             !! 465         cpu0_opp_table: cpu0_opp_table {
363                 scm {                          << 
364                         compatible = "qcom,scm << 
365                 };                             << 
366         };                                     << 
367                                                << 
368         memory@80000000 {                      << 
369                 device_type = "memory";        << 
370                 /* We expect the bootloader to << 
371                 reg = <0 0x80000000 0 0>;      << 
372         };                                     << 
373                                                << 
374         cpu0_opp_table: opp-table-cpu0 {       << 
375                 compatible = "operating-points    466                 compatible = "operating-points-v2";
376                 opp-shared;                       467                 opp-shared;
377                                                   468 
378                 cpu0_opp1: opp-300000000 {        469                 cpu0_opp1: opp-300000000 {
379                         opp-hz = /bits/ 64 <30    470                         opp-hz = /bits/ 64 <300000000>;
380                         opp-peak-kBps = <80000    471                         opp-peak-kBps = <800000 4800000>;
381                 };                                472                 };
382                                                   473 
383                 cpu0_opp2: opp-403200000 {        474                 cpu0_opp2: opp-403200000 {
384                         opp-hz = /bits/ 64 <40    475                         opp-hz = /bits/ 64 <403200000>;
385                         opp-peak-kBps = <80000    476                         opp-peak-kBps = <800000 4800000>;
386                 };                                477                 };
387                                                   478 
388                 cpu0_opp3: opp-480000000 {        479                 cpu0_opp3: opp-480000000 {
389                         opp-hz = /bits/ 64 <48    480                         opp-hz = /bits/ 64 <480000000>;
390                         opp-peak-kBps = <80000    481                         opp-peak-kBps = <800000 6451200>;
391                 };                                482                 };
392                                                   483 
393                 cpu0_opp4: opp-576000000 {        484                 cpu0_opp4: opp-576000000 {
394                         opp-hz = /bits/ 64 <57    485                         opp-hz = /bits/ 64 <576000000>;
395                         opp-peak-kBps = <80000    486                         opp-peak-kBps = <800000 6451200>;
396                 };                                487                 };
397                                                   488 
398                 cpu0_opp5: opp-652800000 {        489                 cpu0_opp5: opp-652800000 {
399                         opp-hz = /bits/ 64 <65    490                         opp-hz = /bits/ 64 <652800000>;
400                         opp-peak-kBps = <80000    491                         opp-peak-kBps = <800000 7680000>;
401                 };                                492                 };
402                                                   493 
403                 cpu0_opp6: opp-748800000 {        494                 cpu0_opp6: opp-748800000 {
404                         opp-hz = /bits/ 64 <74    495                         opp-hz = /bits/ 64 <748800000>;
405                         opp-peak-kBps = <18040    496                         opp-peak-kBps = <1804000 9216000>;
406                 };                                497                 };
407                                                   498 
408                 cpu0_opp7: opp-825600000 {        499                 cpu0_opp7: opp-825600000 {
409                         opp-hz = /bits/ 64 <82    500                         opp-hz = /bits/ 64 <825600000>;
410                         opp-peak-kBps = <18040    501                         opp-peak-kBps = <1804000 9216000>;
411                 };                                502                 };
412                                                   503 
413                 cpu0_opp8: opp-902400000 {        504                 cpu0_opp8: opp-902400000 {
414                         opp-hz = /bits/ 64 <90    505                         opp-hz = /bits/ 64 <902400000>;
415                         opp-peak-kBps = <18040    506                         opp-peak-kBps = <1804000 10444800>;
416                 };                                507                 };
417                                                   508 
418                 cpu0_opp9: opp-979200000 {        509                 cpu0_opp9: opp-979200000 {
419                         opp-hz = /bits/ 64 <97    510                         opp-hz = /bits/ 64 <979200000>;
420                         opp-peak-kBps = <18040    511                         opp-peak-kBps = <1804000 11980800>;
421                 };                                512                 };
422                                                   513 
423                 cpu0_opp10: opp-1056000000 {      514                 cpu0_opp10: opp-1056000000 {
424                         opp-hz = /bits/ 64 <10    515                         opp-hz = /bits/ 64 <1056000000>;
425                         opp-peak-kBps = <18040    516                         opp-peak-kBps = <1804000 11980800>;
426                 };                                517                 };
427                                                   518 
428                 cpu0_opp11: opp-1132800000 {      519                 cpu0_opp11: opp-1132800000 {
429                         opp-hz = /bits/ 64 <11    520                         opp-hz = /bits/ 64 <1132800000>;
430                         opp-peak-kBps = <21880    521                         opp-peak-kBps = <2188000 13516800>;
431                 };                                522                 };
432                                                   523 
433                 cpu0_opp12: opp-1228800000 {      524                 cpu0_opp12: opp-1228800000 {
434                         opp-hz = /bits/ 64 <12    525                         opp-hz = /bits/ 64 <1228800000>;
435                         opp-peak-kBps = <21880    526                         opp-peak-kBps = <2188000 15052800>;
436                 };                                527                 };
437                                                   528 
438                 cpu0_opp13: opp-1324800000 {      529                 cpu0_opp13: opp-1324800000 {
439                         opp-hz = /bits/ 64 <13    530                         opp-hz = /bits/ 64 <1324800000>;
440                         opp-peak-kBps = <21880    531                         opp-peak-kBps = <2188000 16588800>;
441                 };                                532                 };
442                                                   533 
443                 cpu0_opp14: opp-1420800000 {      534                 cpu0_opp14: opp-1420800000 {
444                         opp-hz = /bits/ 64 <14    535                         opp-hz = /bits/ 64 <1420800000>;
445                         opp-peak-kBps = <30720    536                         opp-peak-kBps = <3072000 18124800>;
446                 };                                537                 };
447                                                   538 
448                 cpu0_opp15: opp-1516800000 {      539                 cpu0_opp15: opp-1516800000 {
449                         opp-hz = /bits/ 64 <15    540                         opp-hz = /bits/ 64 <1516800000>;
450                         opp-peak-kBps = <30720    541                         opp-peak-kBps = <3072000 19353600>;
451                 };                                542                 };
452                                                   543 
453                 cpu0_opp16: opp-1612800000 {      544                 cpu0_opp16: opp-1612800000 {
454                         opp-hz = /bits/ 64 <16    545                         opp-hz = /bits/ 64 <1612800000>;
455                         opp-peak-kBps = <40680    546                         opp-peak-kBps = <4068000 19353600>;
456                 };                                547                 };
457                                                   548 
458                 cpu0_opp17: opp-1689600000 {      549                 cpu0_opp17: opp-1689600000 {
459                         opp-hz = /bits/ 64 <16    550                         opp-hz = /bits/ 64 <1689600000>;
460                         opp-peak-kBps = <40680    551                         opp-peak-kBps = <4068000 20889600>;
461                 };                                552                 };
462                                                   553 
463                 cpu0_opp18: opp-1766400000 {      554                 cpu0_opp18: opp-1766400000 {
464                         opp-hz = /bits/ 64 <17    555                         opp-hz = /bits/ 64 <1766400000>;
465                         opp-peak-kBps = <40680    556                         opp-peak-kBps = <4068000 22425600>;
466                 };                                557                 };
467         };                                        558         };
468                                                   559 
469         cpu4_opp_table: opp-table-cpu4 {       !! 560         cpu4_opp_table: cpu4_opp_table {
470                 compatible = "operating-points    561                 compatible = "operating-points-v2";
471                 opp-shared;                       562                 opp-shared;
472                                                   563 
473                 cpu4_opp1: opp-300000000 {        564                 cpu4_opp1: opp-300000000 {
474                         opp-hz = /bits/ 64 <30    565                         opp-hz = /bits/ 64 <300000000>;
475                         opp-peak-kBps = <80000    566                         opp-peak-kBps = <800000 4800000>;
476                 };                                567                 };
477                                                   568 
478                 cpu4_opp2: opp-403200000 {        569                 cpu4_opp2: opp-403200000 {
479                         opp-hz = /bits/ 64 <40    570                         opp-hz = /bits/ 64 <403200000>;
480                         opp-peak-kBps = <80000    571                         opp-peak-kBps = <800000 4800000>;
481                 };                                572                 };
482                                                   573 
483                 cpu4_opp3: opp-480000000 {        574                 cpu4_opp3: opp-480000000 {
484                         opp-hz = /bits/ 64 <48    575                         opp-hz = /bits/ 64 <480000000>;
485                         opp-peak-kBps = <18040    576                         opp-peak-kBps = <1804000 4800000>;
486                 };                                577                 };
487                                                   578 
488                 cpu4_opp4: opp-576000000 {        579                 cpu4_opp4: opp-576000000 {
489                         opp-hz = /bits/ 64 <57    580                         opp-hz = /bits/ 64 <576000000>;
490                         opp-peak-kBps = <18040    581                         opp-peak-kBps = <1804000 4800000>;
491                 };                                582                 };
492                                                   583 
493                 cpu4_opp5: opp-652800000 {        584                 cpu4_opp5: opp-652800000 {
494                         opp-hz = /bits/ 64 <65    585                         opp-hz = /bits/ 64 <652800000>;
495                         opp-peak-kBps = <18040    586                         opp-peak-kBps = <1804000 4800000>;
496                 };                                587                 };
497                                                   588 
498                 cpu4_opp6: opp-748800000 {        589                 cpu4_opp6: opp-748800000 {
499                         opp-hz = /bits/ 64 <74    590                         opp-hz = /bits/ 64 <748800000>;
500                         opp-peak-kBps = <18040    591                         opp-peak-kBps = <1804000 4800000>;
501                 };                                592                 };
502                                                   593 
503                 cpu4_opp7: opp-825600000 {        594                 cpu4_opp7: opp-825600000 {
504                         opp-hz = /bits/ 64 <82    595                         opp-hz = /bits/ 64 <825600000>;
505                         opp-peak-kBps = <21880    596                         opp-peak-kBps = <2188000 9216000>;
506                 };                                597                 };
507                                                   598 
508                 cpu4_opp8: opp-902400000 {        599                 cpu4_opp8: opp-902400000 {
509                         opp-hz = /bits/ 64 <90    600                         opp-hz = /bits/ 64 <902400000>;
510                         opp-peak-kBps = <21880    601                         opp-peak-kBps = <2188000 9216000>;
511                 };                                602                 };
512                                                   603 
513                 cpu4_opp9: opp-979200000 {        604                 cpu4_opp9: opp-979200000 {
514                         opp-hz = /bits/ 64 <97    605                         opp-hz = /bits/ 64 <979200000>;
515                         opp-peak-kBps = <21880    606                         opp-peak-kBps = <2188000 9216000>;
516                 };                                607                 };
517                                                   608 
518                 cpu4_opp10: opp-1056000000 {      609                 cpu4_opp10: opp-1056000000 {
519                         opp-hz = /bits/ 64 <10    610                         opp-hz = /bits/ 64 <1056000000>;
520                         opp-peak-kBps = <30720    611                         opp-peak-kBps = <3072000 9216000>;
521                 };                                612                 };
522                                                   613 
523                 cpu4_opp11: opp-1132800000 {      614                 cpu4_opp11: opp-1132800000 {
524                         opp-hz = /bits/ 64 <11    615                         opp-hz = /bits/ 64 <1132800000>;
525                         opp-peak-kBps = <30720    616                         opp-peak-kBps = <3072000 11980800>;
526                 };                                617                 };
527                                                   618 
528                 cpu4_opp12: opp-1209600000 {      619                 cpu4_opp12: opp-1209600000 {
529                         opp-hz = /bits/ 64 <12    620                         opp-hz = /bits/ 64 <1209600000>;
530                         opp-peak-kBps = <40680    621                         opp-peak-kBps = <4068000 11980800>;
531                 };                                622                 };
532                                                   623 
533                 cpu4_opp13: opp-1286400000 {      624                 cpu4_opp13: opp-1286400000 {
534                         opp-hz = /bits/ 64 <12    625                         opp-hz = /bits/ 64 <1286400000>;
535                         opp-peak-kBps = <40680    626                         opp-peak-kBps = <4068000 11980800>;
536                 };                                627                 };
537                                                   628 
538                 cpu4_opp14: opp-1363200000 {      629                 cpu4_opp14: opp-1363200000 {
539                         opp-hz = /bits/ 64 <13    630                         opp-hz = /bits/ 64 <1363200000>;
540                         opp-peak-kBps = <40680    631                         opp-peak-kBps = <4068000 15052800>;
541                 };                                632                 };
542                                                   633 
543                 cpu4_opp15: opp-1459200000 {      634                 cpu4_opp15: opp-1459200000 {
544                         opp-hz = /bits/ 64 <14    635                         opp-hz = /bits/ 64 <1459200000>;
545                         opp-peak-kBps = <40680    636                         opp-peak-kBps = <4068000 15052800>;
546                 };                                637                 };
547                                                   638 
548                 cpu4_opp16: opp-1536000000 {      639                 cpu4_opp16: opp-1536000000 {
549                         opp-hz = /bits/ 64 <15    640                         opp-hz = /bits/ 64 <1536000000>;
550                         opp-peak-kBps = <54120    641                         opp-peak-kBps = <5412000 15052800>;
551                 };                                642                 };
552                                                   643 
553                 cpu4_opp17: opp-1612800000 {      644                 cpu4_opp17: opp-1612800000 {
554                         opp-hz = /bits/ 64 <16    645                         opp-hz = /bits/ 64 <1612800000>;
555                         opp-peak-kBps = <54120    646                         opp-peak-kBps = <5412000 15052800>;
556                 };                                647                 };
557                                                   648 
558                 cpu4_opp18: opp-1689600000 {      649                 cpu4_opp18: opp-1689600000 {
559                         opp-hz = /bits/ 64 <16    650                         opp-hz = /bits/ 64 <1689600000>;
560                         opp-peak-kBps = <54120    651                         opp-peak-kBps = <5412000 19353600>;
561                 };                                652                 };
562                                                   653 
563                 cpu4_opp19: opp-1766400000 {      654                 cpu4_opp19: opp-1766400000 {
564                         opp-hz = /bits/ 64 <17    655                         opp-hz = /bits/ 64 <1766400000>;
565                         opp-peak-kBps = <62200    656                         opp-peak-kBps = <6220000 19353600>;
566                 };                                657                 };
567                                                   658 
568                 cpu4_opp20: opp-1843200000 {      659                 cpu4_opp20: opp-1843200000 {
569                         opp-hz = /bits/ 64 <18    660                         opp-hz = /bits/ 64 <1843200000>;
570                         opp-peak-kBps = <62200    661                         opp-peak-kBps = <6220000 19353600>;
571                 };                                662                 };
572                                                   663 
573                 cpu4_opp21: opp-1920000000 {      664                 cpu4_opp21: opp-1920000000 {
574                         opp-hz = /bits/ 64 <19    665                         opp-hz = /bits/ 64 <1920000000>;
575                         opp-peak-kBps = <72160    666                         opp-peak-kBps = <7216000 19353600>;
576                 };                                667                 };
577                                                   668 
578                 cpu4_opp22: opp-1996800000 {      669                 cpu4_opp22: opp-1996800000 {
579                         opp-hz = /bits/ 64 <19    670                         opp-hz = /bits/ 64 <1996800000>;
580                         opp-peak-kBps = <72160    671                         opp-peak-kBps = <7216000 20889600>;
581                 };                                672                 };
582                                                   673 
583                 cpu4_opp23: opp-2092800000 {      674                 cpu4_opp23: opp-2092800000 {
584                         opp-hz = /bits/ 64 <20    675                         opp-hz = /bits/ 64 <2092800000>;
585                         opp-peak-kBps = <72160    676                         opp-peak-kBps = <7216000 20889600>;
586                 };                                677                 };
587                                                   678 
588                 cpu4_opp24: opp-2169600000 {      679                 cpu4_opp24: opp-2169600000 {
589                         opp-hz = /bits/ 64 <21    680                         opp-hz = /bits/ 64 <2169600000>;
590                         opp-peak-kBps = <72160    681                         opp-peak-kBps = <7216000 20889600>;
591                 };                                682                 };
592                                                   683 
593                 cpu4_opp25: opp-2246400000 {      684                 cpu4_opp25: opp-2246400000 {
594                         opp-hz = /bits/ 64 <22    685                         opp-hz = /bits/ 64 <2246400000>;
595                         opp-peak-kBps = <72160    686                         opp-peak-kBps = <7216000 20889600>;
596                 };                                687                 };
597                                                   688 
598                 cpu4_opp26: opp-2323200000 {      689                 cpu4_opp26: opp-2323200000 {
599                         opp-hz = /bits/ 64 <23    690                         opp-hz = /bits/ 64 <2323200000>;
600                         opp-peak-kBps = <72160    691                         opp-peak-kBps = <7216000 20889600>;
601                 };                                692                 };
602                                                   693 
603                 cpu4_opp27: opp-2400000000 {      694                 cpu4_opp27: opp-2400000000 {
604                         opp-hz = /bits/ 64 <24    695                         opp-hz = /bits/ 64 <2400000000>;
605                         opp-peak-kBps = <72160    696                         opp-peak-kBps = <7216000 22425600>;
606                 };                                697                 };
607                                                   698 
608                 cpu4_opp28: opp-2476800000 {      699                 cpu4_opp28: opp-2476800000 {
609                         opp-hz = /bits/ 64 <24    700                         opp-hz = /bits/ 64 <2476800000>;
610                         opp-peak-kBps = <72160    701                         opp-peak-kBps = <7216000 22425600>;
611                 };                                702                 };
612                                                   703 
613                 cpu4_opp29: opp-2553600000 {      704                 cpu4_opp29: opp-2553600000 {
614                         opp-hz = /bits/ 64 <25    705                         opp-hz = /bits/ 64 <2553600000>;
615                         opp-peak-kBps = <72160    706                         opp-peak-kBps = <7216000 22425600>;
616                 };                                707                 };
617                                                   708 
618                 cpu4_opp30: opp-2649600000 {      709                 cpu4_opp30: opp-2649600000 {
619                         opp-hz = /bits/ 64 <26    710                         opp-hz = /bits/ 64 <2649600000>;
620                         opp-peak-kBps = <72160    711                         opp-peak-kBps = <7216000 22425600>;
621                 };                                712                 };
622                                                   713 
623                 cpu4_opp31: opp-2745600000 {      714                 cpu4_opp31: opp-2745600000 {
624                         opp-hz = /bits/ 64 <27    715                         opp-hz = /bits/ 64 <2745600000>;
625                         opp-peak-kBps = <72160    716                         opp-peak-kBps = <7216000 25497600>;
626                 };                                717                 };
627                                                   718 
628                 cpu4_opp32: opp-2803200000 {      719                 cpu4_opp32: opp-2803200000 {
629                         opp-hz = /bits/ 64 <28    720                         opp-hz = /bits/ 64 <2803200000>;
630                         opp-peak-kBps = <72160    721                         opp-peak-kBps = <7216000 25497600>;
631                 };                                722                 };
632         };                                        723         };
633                                                   724 
634         dsi_opp_table: opp-table-dsi {         << 
635                 compatible = "operating-points << 
636                                                << 
637                 opp-19200000 {                 << 
638                         opp-hz = /bits/ 64 <19 << 
639                         required-opps = <&rpmh << 
640                 };                             << 
641                                                << 
642                 opp-180000000 {                << 
643                         opp-hz = /bits/ 64 <18 << 
644                         required-opps = <&rpmh << 
645                 };                             << 
646                                                << 
647                 opp-275000000 {                << 
648                         opp-hz = /bits/ 64 <27 << 
649                         required-opps = <&rpmh << 
650                 };                             << 
651                                                << 
652                 opp-328580000 {                << 
653                         opp-hz = /bits/ 64 <32 << 
654                         required-opps = <&rpmh << 
655                 };                             << 
656                                                << 
657                 opp-358000000 {                << 
658                         opp-hz = /bits/ 64 <35 << 
659                         required-opps = <&rpmh << 
660                 };                             << 
661         };                                     << 
662                                                << 
663         qspi_opp_table: opp-table-qspi {       << 
664                 compatible = "operating-points << 
665                                                << 
666                 opp-19200000 {                 << 
667                         opp-hz = /bits/ 64 <19 << 
668                         required-opps = <&rpmh << 
669                 };                             << 
670                                                << 
671                 opp-100000000 {                << 
672                         opp-hz = /bits/ 64 <10 << 
673                         required-opps = <&rpmh << 
674                 };                             << 
675                                                << 
676                 opp-150000000 {                << 
677                         opp-hz = /bits/ 64 <15 << 
678                         required-opps = <&rpmh << 
679                 };                             << 
680                                                << 
681                 opp-300000000 {                << 
682                         opp-hz = /bits/ 64 <30 << 
683                         required-opps = <&rpmh << 
684                 };                             << 
685         };                                     << 
686                                                << 
687         qup_opp_table: opp-table-qup {         << 
688                 compatible = "operating-points << 
689                                                << 
690                 opp-50000000 {                 << 
691                         opp-hz = /bits/ 64 <50 << 
692                         required-opps = <&rpmh << 
693                 };                             << 
694                                                << 
695                 opp-75000000 {                 << 
696                         opp-hz = /bits/ 64 <75 << 
697                         required-opps = <&rpmh << 
698                 };                             << 
699                                                << 
700                 opp-100000000 {                << 
701                         opp-hz = /bits/ 64 <10 << 
702                         required-opps = <&rpmh << 
703                 };                             << 
704                                                << 
705                 opp-128000000 {                << 
706                         opp-hz = /bits/ 64 <12 << 
707                         required-opps = <&rpmh << 
708                 };                             << 
709         };                                     << 
710                                                << 
711         pmu {                                     725         pmu {
712                 compatible = "arm,armv8-pmuv3"    726                 compatible = "arm,armv8-pmuv3";
713                 interrupts = <GIC_PPI 5 IRQ_TY    727                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714         };                                        728         };
715                                                   729 
716         psci: psci {                           !! 730         timer {
717                 compatible = "arm,psci-1.0";   !! 731                 compatible = "arm,armv8-timer";
718                 method = "smc";                !! 732                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719                                                !! 733                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720                 CPU_PD0: power-domain-cpu0 {   !! 734                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721                         #power-domain-cells =  !! 735                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722                         power-domains = <&CLUS << 
723                         domain-idle-states = < << 
724                 };                             << 
725                                                << 
726                 CPU_PD1: power-domain-cpu1 {   << 
727                         #power-domain-cells =  << 
728                         power-domains = <&CLUS << 
729                         domain-idle-states = < << 
730                 };                             << 
731                                                << 
732                 CPU_PD2: power-domain-cpu2 {   << 
733                         #power-domain-cells =  << 
734                         power-domains = <&CLUS << 
735                         domain-idle-states = < << 
736                 };                             << 
737                                                << 
738                 CPU_PD3: power-domain-cpu3 {   << 
739                         #power-domain-cells =  << 
740                         power-domains = <&CLUS << 
741                         domain-idle-states = < << 
742                 };                             << 
743                                                << 
744                 CPU_PD4: power-domain-cpu4 {   << 
745                         #power-domain-cells =  << 
746                         power-domains = <&CLUS << 
747                         domain-idle-states = < << 
748                 };                             << 
749                                                << 
750                 CPU_PD5: power-domain-cpu5 {   << 
751                         #power-domain-cells =  << 
752                         power-domains = <&CLUS << 
753                         domain-idle-states = < << 
754                 };                             << 
755                                                << 
756                 CPU_PD6: power-domain-cpu6 {   << 
757                         #power-domain-cells =  << 
758                         power-domains = <&CLUS << 
759                         domain-idle-states = < << 
760                 };                             << 
761                                                << 
762                 CPU_PD7: power-domain-cpu7 {   << 
763                         #power-domain-cells =  << 
764                         power-domains = <&CLUS << 
765                         domain-idle-states = < << 
766                 };                             << 
767                                                << 
768                 CLUSTER_PD: power-domain-clust << 
769                         #power-domain-cells =  << 
770                         domain-idle-states = < << 
771                 };                             << 
772         };                                        736         };
773                                                   737 
774         reserved-memory {                      !! 738         clocks {
775                 #address-cells = <2>;          !! 739                 xo_board: xo-board {
776                 #size-cells = <2>;             !! 740                         compatible = "fixed-clock";
777                 ranges;                        !! 741                         #clock-cells = <0>;
778                                                !! 742                         clock-frequency = <38400000>;
779                 hyp_mem: hyp-mem@85700000 {    !! 743                         clock-output-names = "xo_board";
780                         reg = <0 0x85700000 0  << 
781                         no-map;                << 
782                 };                             << 
783                                                << 
784                 xbl_mem: xbl-mem@85e00000 {    << 
785                         reg = <0 0x85e00000 0  << 
786                         no-map;                << 
787                 };                             << 
788                                                << 
789                 aop_mem: aop-mem@85fc0000 {    << 
790                         reg = <0 0x85fc0000 0  << 
791                         no-map;                << 
792                 };                             << 
793                                                << 
794                 aop_cmd_db_mem: aop-cmd-db-mem << 
795                         compatible = "qcom,cmd << 
796                         reg = <0x0 0x85fe0000  << 
797                         no-map;                << 
798                 };                             << 
799                                                << 
800                 smem@86000000 {                << 
801                         compatible = "qcom,sme << 
802                         reg = <0x0 0x86000000  << 
803                         no-map;                << 
804                         hwlocks = <&tcsr_mutex << 
805                 };                             << 
806                                                << 
807                 tz_mem: tz@86200000 {          << 
808                         reg = <0 0x86200000 0  << 
809                         no-map;                << 
810                 };                             << 
811                                                << 
812                 rmtfs_mem: rmtfs@88f00000 {    << 
813                         compatible = "qcom,rmt << 
814                         reg = <0 0x88f00000 0  << 
815                         no-map;                << 
816                                                << 
817                         qcom,client-id = <1>;  << 
818                         qcom,vmid = <QCOM_SCM_ << 
819                 };                             << 
820                                                << 
821                 qseecom_mem: qseecom@8ab00000  << 
822                         reg = <0 0x8ab00000 0  << 
823                         no-map;                << 
824                 };                             << 
825                                                << 
826                 camera_mem: camera-mem@8bf0000 << 
827                         reg = <0 0x8bf00000 0  << 
828                         no-map;                << 
829                 };                             << 
830                                                << 
831                 ipa_fw_mem: ipa-fw@8c400000 {  << 
832                         reg = <0 0x8c400000 0  << 
833                         no-map;                << 
834                 };                             << 
835                                                << 
836                 ipa_gsi_mem: ipa-gsi@8c410000  << 
837                         reg = <0 0x8c410000 0  << 
838                         no-map;                << 
839                 };                             << 
840                                                << 
841                 gpu_mem: gpu@8c415000 {        << 
842                         reg = <0 0x8c415000 0  << 
843                         no-map;                << 
844                 };                             << 
845                                                << 
846                 adsp_mem: adsp@8c500000 {      << 
847                         reg = <0 0x8c500000 0  << 
848                         no-map;                << 
849                 };                             << 
850                                                << 
851                 wlan_msa_mem: wlan-msa@8df0000 << 
852                         reg = <0 0x8df00000 0  << 
853                         no-map;                << 
854                 };                             << 
855                                                << 
856                 mpss_region: mpss@8e000000 {   << 
857                         reg = <0 0x8e000000 0  << 
858                         no-map;                << 
859                 };                             << 
860                                                << 
861                 venus_mem: venus@95800000 {    << 
862                         reg = <0 0x95800000 0  << 
863                         no-map;                << 
864                 };                             << 
865                                                << 
866                 cdsp_mem: cdsp@95d00000 {      << 
867                         reg = <0 0x95d00000 0  << 
868                         no-map;                << 
869                 };                             << 
870                                                << 
871                 mba_region: mba@96500000 {     << 
872                         reg = <0 0x96500000 0  << 
873                         no-map;                << 
874                 };                             << 
875                                                << 
876                 slpi_mem: slpi@96700000 {      << 
877                         reg = <0 0x96700000 0  << 
878                         no-map;                << 
879                 };                             << 
880                                                << 
881                 spss_mem: spss@97b00000 {      << 
882                         reg = <0 0x97b00000 0  << 
883                         no-map;                << 
884                 };                                744                 };
885                                                   745 
886                 mdata_mem: mpss-metadata {     !! 746                 sleep_clk: sleep-clk {
887                         alloc-ranges = <0 0xa0 !! 747                         compatible = "fixed-clock";
888                         size = <0 0x4000>;     !! 748                         #clock-cells = <0>;
889                         no-map;                !! 749                         clock-frequency = <32764>;
890                 };                                750                 };
                                                   >> 751         };
891                                                   752 
892                 fastrpc_mem: fastrpc {         !! 753         firmware {
893                         compatible = "shared-d !! 754                 scm {
894                         alloc-ranges = <0x0 0x !! 755                         compatible = "qcom,scm-sdm845", "qcom,scm";
895                         alignment = <0x0 0x400 << 
896                         size = <0x0 0x1000000> << 
897                         reusable;              << 
898                 };                                756                 };
899         };                                        757         };
900                                                   758 
901         adsp_pas: remoteproc-adsp {               759         adsp_pas: remoteproc-adsp {
902                 compatible = "qcom,sdm845-adsp    760                 compatible = "qcom,sdm845-adsp-pas";
903                                                   761 
904                 interrupts-extended = <&intc G    762                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905                                       <&adsp_s    763                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906                                       <&adsp_s    764                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907                                       <&adsp_s    765                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908                                       <&adsp_s    766                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909                 interrupt-names = "wdog", "fat    767                 interrupt-names = "wdog", "fatal", "ready",
910                                   "handover",     768                                   "handover", "stop-ack";
911                                                   769 
912                 clocks = <&rpmhcc RPMH_CXO_CLK    770                 clocks = <&rpmhcc RPMH_CXO_CLK>;
913                 clock-names = "xo";               771                 clock-names = "xo";
914                                                   772 
915                 memory-region = <&adsp_mem>;      773                 memory-region = <&adsp_mem>;
916                                                   774 
917                 qcom,qmp = <&aoss_qmp>;           775                 qcom,qmp = <&aoss_qmp>;
918                                                   776 
919                 qcom,smem-states = <&adsp_smp2    777                 qcom,smem-states = <&adsp_smp2p_out 0>;
920                 qcom,smem-state-names = "stop"    778                 qcom,smem-state-names = "stop";
921                                                   779 
922                 status = "disabled";              780                 status = "disabled";
923                                                   781 
924                 glink-edge {                      782                 glink-edge {
925                         interrupts = <GIC_SPI     783                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926                         label = "lpass";          784                         label = "lpass";
927                         qcom,remote-pid = <2>;    785                         qcom,remote-pid = <2>;
928                         mboxes = <&apss_shared    786                         mboxes = <&apss_shared 8>;
929                                                   787 
930                         apr {                     788                         apr {
931                                 compatible = "    789                                 compatible = "qcom,apr-v2";
932                                 qcom,glink-cha    790                                 qcom,glink-channels = "apr_audio_svc";
933                                 qcom,domain =     791                                 qcom,domain = <APR_DOMAIN_ADSP>;
934                                 #address-cells    792                                 #address-cells = <1>;
935                                 #size-cells =     793                                 #size-cells = <0>;
936                                 qcom,intents =    794                                 qcom,intents = <512 20>;
937                                                   795 
938                                 service@3 {    !! 796                                 apr-service@3 {
939                                         reg =     797                                         reg = <APR_SVC_ADSP_CORE>;
940                                         compat    798                                         compatible = "qcom,q6core";
941                                         qcom,p    799                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942                                 };                800                                 };
943                                                   801 
944                                 q6afe: service !! 802                                 q6afe: apr-service@4 {
945                                         compat    803                                         compatible = "qcom,q6afe";
946                                         reg =     804                                         reg = <APR_SVC_AFE>;
947                                         qcom,p    805                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948                                         q6afed    806                                         q6afedai: dais {
949                                                   807                                                 compatible = "qcom,q6afe-dais";
950                                                   808                                                 #address-cells = <1>;
951                                                   809                                                 #size-cells = <0>;
952                                                   810                                                 #sound-dai-cells = <1>;
953                                         };        811                                         };
954                                 };                812                                 };
955                                                   813 
956                                 q6asm: service !! 814                                 q6asm: apr-service@7 {
957                                         compat    815                                         compatible = "qcom,q6asm";
958                                         reg =     816                                         reg = <APR_SVC_ASM>;
959                                         qcom,p    817                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960                                         q6asmd    818                                         q6asmdai: dais {
961                                                   819                                                 compatible = "qcom,q6asm-dais";
962                                                   820                                                 #address-cells = <1>;
963                                                   821                                                 #size-cells = <0>;
964                                                   822                                                 #sound-dai-cells = <1>;
965                                                   823                                                 iommus = <&apps_smmu 0x1821 0x0>;
966                                         };        824                                         };
967                                 };                825                                 };
968                                                   826 
969                                 q6adm: service !! 827                                 q6adm: apr-service@8 {
970                                         compat    828                                         compatible = "qcom,q6adm";
971                                         reg =     829                                         reg = <APR_SVC_ADM>;
972                                         qcom,p    830                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973                                         q6rout    831                                         q6routing: routing {
974                                                   832                                                 compatible = "qcom,q6adm-routing";
975                                                   833                                                 #sound-dai-cells = <0>;
976                                         };        834                                         };
977                                 };                835                                 };
978                         };                        836                         };
979                                                   837 
980                         fastrpc {                 838                         fastrpc {
981                                 compatible = "    839                                 compatible = "qcom,fastrpc";
982                                 qcom,glink-cha    840                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
983                                 label = "adsp"    841                                 label = "adsp";
984                                 qcom,non-secur    842                                 qcom,non-secure-domain;
985                                 #address-cells    843                                 #address-cells = <1>;
986                                 #size-cells =     844                                 #size-cells = <0>;
987                                                   845 
988                                 compute-cb@3 {    846                                 compute-cb@3 {
989                                         compat    847                                         compatible = "qcom,fastrpc-compute-cb";
990                                         reg =     848                                         reg = <3>;
991                                         iommus    849                                         iommus = <&apps_smmu 0x1823 0x0>;
992                                 };                850                                 };
993                                                   851 
994                                 compute-cb@4 {    852                                 compute-cb@4 {
995                                         compat    853                                         compatible = "qcom,fastrpc-compute-cb";
996                                         reg =     854                                         reg = <4>;
997                                         iommus    855                                         iommus = <&apps_smmu 0x1824 0x0>;
998                                 };                856                                 };
999                         };                        857                         };
1000                 };                               858                 };
1001         };                                       859         };
1002                                                  860 
1003         cdsp_pas: remoteproc-cdsp {              861         cdsp_pas: remoteproc-cdsp {
1004                 compatible = "qcom,sdm845-cds    862                 compatible = "qcom,sdm845-cdsp-pas";
1005                                                  863 
1006                 interrupts-extended = <&intc     864                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007                                       <&cdsp_    865                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008                                       <&cdsp_    866                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009                                       <&cdsp_    867                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010                                       <&cdsp_    868                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011                 interrupt-names = "wdog", "fa    869                 interrupt-names = "wdog", "fatal", "ready",
1012                                   "handover",    870                                   "handover", "stop-ack";
1013                                                  871 
1014                 clocks = <&rpmhcc RPMH_CXO_CL    872                 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015                 clock-names = "xo";              873                 clock-names = "xo";
1016                                                  874 
1017                 memory-region = <&cdsp_mem>;     875                 memory-region = <&cdsp_mem>;
1018                                                  876 
1019                 qcom,qmp = <&aoss_qmp>;          877                 qcom,qmp = <&aoss_qmp>;
1020                                                  878 
1021                 qcom,smem-states = <&cdsp_smp    879                 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022                 qcom,smem-state-names = "stop    880                 qcom,smem-state-names = "stop";
1023                                                  881 
1024                 status = "disabled";             882                 status = "disabled";
1025                                                  883 
1026                 glink-edge {                     884                 glink-edge {
1027                         interrupts = <GIC_SPI    885                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028                         label = "turing";        886                         label = "turing";
1029                         qcom,remote-pid = <5>    887                         qcom,remote-pid = <5>;
1030                         mboxes = <&apss_share    888                         mboxes = <&apss_shared 4>;
1031                         fastrpc {                889                         fastrpc {
1032                                 compatible =     890                                 compatible = "qcom,fastrpc";
1033                                 qcom,glink-ch    891                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034                                 label = "cdsp    892                                 label = "cdsp";
1035                                 qcom,non-secu    893                                 qcom,non-secure-domain;
1036                                 #address-cell    894                                 #address-cells = <1>;
1037                                 #size-cells =    895                                 #size-cells = <0>;
1038                                                  896 
1039                                 compute-cb@1     897                                 compute-cb@1 {
1040                                         compa    898                                         compatible = "qcom,fastrpc-compute-cb";
1041                                         reg =    899                                         reg = <1>;
1042                                         iommu    900                                         iommus = <&apps_smmu 0x1401 0x30>;
1043                                 };               901                                 };
1044                                                  902 
1045                                 compute-cb@2     903                                 compute-cb@2 {
1046                                         compa    904                                         compatible = "qcom,fastrpc-compute-cb";
1047                                         reg =    905                                         reg = <2>;
1048                                         iommu    906                                         iommus = <&apps_smmu 0x1402 0x30>;
1049                                 };               907                                 };
1050                                                  908 
1051                                 compute-cb@3     909                                 compute-cb@3 {
1052                                         compa    910                                         compatible = "qcom,fastrpc-compute-cb";
1053                                         reg =    911                                         reg = <3>;
1054                                         iommu    912                                         iommus = <&apps_smmu 0x1403 0x30>;
1055                                 };               913                                 };
1056                                                  914 
1057                                 compute-cb@4     915                                 compute-cb@4 {
1058                                         compa    916                                         compatible = "qcom,fastrpc-compute-cb";
1059                                         reg =    917                                         reg = <4>;
1060                                         iommu    918                                         iommus = <&apps_smmu 0x1404 0x30>;
1061                                 };               919                                 };
1062                                                  920 
1063                                 compute-cb@5     921                                 compute-cb@5 {
1064                                         compa    922                                         compatible = "qcom,fastrpc-compute-cb";
1065                                         reg =    923                                         reg = <5>;
1066                                         iommu    924                                         iommus = <&apps_smmu 0x1405 0x30>;
1067                                 };               925                                 };
1068                                                  926 
1069                                 compute-cb@6     927                                 compute-cb@6 {
1070                                         compa    928                                         compatible = "qcom,fastrpc-compute-cb";
1071                                         reg =    929                                         reg = <6>;
1072                                         iommu    930                                         iommus = <&apps_smmu 0x1406 0x30>;
1073                                 };               931                                 };
1074                                                  932 
1075                                 compute-cb@7     933                                 compute-cb@7 {
1076                                         compa    934                                         compatible = "qcom,fastrpc-compute-cb";
1077                                         reg =    935                                         reg = <7>;
1078                                         iommu    936                                         iommus = <&apps_smmu 0x1407 0x30>;
1079                                 };               937                                 };
1080                                                  938 
1081                                 compute-cb@8     939                                 compute-cb@8 {
1082                                         compa    940                                         compatible = "qcom,fastrpc-compute-cb";
1083                                         reg =    941                                         reg = <8>;
1084                                         iommu    942                                         iommus = <&apps_smmu 0x1408 0x30>;
1085                                 };               943                                 };
1086                         };                       944                         };
1087                 };                               945                 };
1088         };                                       946         };
1089                                                  947 
                                                   >> 948         tcsr_mutex: hwlock {
                                                   >> 949                 compatible = "qcom,tcsr-mutex";
                                                   >> 950                 syscon = <&tcsr_mutex_regs 0 0x1000>;
                                                   >> 951                 #hwlock-cells = <1>;
                                                   >> 952         };
                                                   >> 953 
1090         smp2p-cdsp {                             954         smp2p-cdsp {
1091                 compatible = "qcom,smp2p";       955                 compatible = "qcom,smp2p";
1092                 qcom,smem = <94>, <432>;         956                 qcom,smem = <94>, <432>;
1093                                                  957 
1094                 interrupts = <GIC_SPI 576 IRQ    958                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095                                                  959 
1096                 mboxes = <&apss_shared 6>;       960                 mboxes = <&apss_shared 6>;
1097                                                  961 
1098                 qcom,local-pid = <0>;            962                 qcom,local-pid = <0>;
1099                 qcom,remote-pid = <5>;           963                 qcom,remote-pid = <5>;
1100                                                  964 
1101                 cdsp_smp2p_out: master-kernel    965                 cdsp_smp2p_out: master-kernel {
1102                         qcom,entry-name = "ma    966                         qcom,entry-name = "master-kernel";
1103                         #qcom,smem-state-cell    967                         #qcom,smem-state-cells = <1>;
1104                 };                               968                 };
1105                                                  969 
1106                 cdsp_smp2p_in: slave-kernel {    970                 cdsp_smp2p_in: slave-kernel {
1107                         qcom,entry-name = "sl    971                         qcom,entry-name = "slave-kernel";
1108                                                  972 
1109                         interrupt-controller;    973                         interrupt-controller;
1110                         #interrupt-cells = <2    974                         #interrupt-cells = <2>;
1111                 };                               975                 };
1112         };                                       976         };
1113                                                  977 
1114         smp2p-lpass {                            978         smp2p-lpass {
1115                 compatible = "qcom,smp2p";       979                 compatible = "qcom,smp2p";
1116                 qcom,smem = <443>, <429>;        980                 qcom,smem = <443>, <429>;
1117                                                  981 
1118                 interrupts = <GIC_SPI 158 IRQ    982                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119                                                  983 
1120                 mboxes = <&apss_shared 10>;      984                 mboxes = <&apss_shared 10>;
1121                                                  985 
1122                 qcom,local-pid = <0>;            986                 qcom,local-pid = <0>;
1123                 qcom,remote-pid = <2>;           987                 qcom,remote-pid = <2>;
1124                                                  988 
1125                 adsp_smp2p_out: master-kernel    989                 adsp_smp2p_out: master-kernel {
1126                         qcom,entry-name = "ma    990                         qcom,entry-name = "master-kernel";
1127                         #qcom,smem-state-cell    991                         #qcom,smem-state-cells = <1>;
1128                 };                               992                 };
1129                                                  993 
1130                 adsp_smp2p_in: slave-kernel {    994                 adsp_smp2p_in: slave-kernel {
1131                         qcom,entry-name = "sl    995                         qcom,entry-name = "slave-kernel";
1132                                                  996 
1133                         interrupt-controller;    997                         interrupt-controller;
1134                         #interrupt-cells = <2    998                         #interrupt-cells = <2>;
1135                 };                               999                 };
1136         };                                       1000         };
1137                                                  1001 
1138         smp2p-mpss {                             1002         smp2p-mpss {
1139                 compatible = "qcom,smp2p";       1003                 compatible = "qcom,smp2p";
1140                 qcom,smem = <435>, <428>;        1004                 qcom,smem = <435>, <428>;
1141                 interrupts = <GIC_SPI 451 IRQ    1005                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142                 mboxes = <&apss_shared 14>;      1006                 mboxes = <&apss_shared 14>;
1143                 qcom,local-pid = <0>;            1007                 qcom,local-pid = <0>;
1144                 qcom,remote-pid = <1>;           1008                 qcom,remote-pid = <1>;
1145                                                  1009 
1146                 modem_smp2p_out: master-kerne    1010                 modem_smp2p_out: master-kernel {
1147                         qcom,entry-name = "ma    1011                         qcom,entry-name = "master-kernel";
1148                         #qcom,smem-state-cell    1012                         #qcom,smem-state-cells = <1>;
1149                 };                               1013                 };
1150                                                  1014 
1151                 modem_smp2p_in: slave-kernel     1015                 modem_smp2p_in: slave-kernel {
1152                         qcom,entry-name = "sl    1016                         qcom,entry-name = "slave-kernel";
1153                         interrupt-controller;    1017                         interrupt-controller;
1154                         #interrupt-cells = <2    1018                         #interrupt-cells = <2>;
1155                 };                               1019                 };
1156                                                  1020 
1157                 ipa_smp2p_out: ipa-ap-to-mode    1021                 ipa_smp2p_out: ipa-ap-to-modem {
1158                         qcom,entry-name = "ip    1022                         qcom,entry-name = "ipa";
1159                         #qcom,smem-state-cell    1023                         #qcom,smem-state-cells = <1>;
1160                 };                               1024                 };
1161                                                  1025 
1162                 ipa_smp2p_in: ipa-modem-to-ap    1026                 ipa_smp2p_in: ipa-modem-to-ap {
1163                         qcom,entry-name = "ip    1027                         qcom,entry-name = "ipa";
1164                         interrupt-controller;    1028                         interrupt-controller;
1165                         #interrupt-cells = <2    1029                         #interrupt-cells = <2>;
1166                 };                               1030                 };
1167         };                                       1031         };
1168                                                  1032 
1169         smp2p-slpi {                             1033         smp2p-slpi {
1170                 compatible = "qcom,smp2p";       1034                 compatible = "qcom,smp2p";
1171                 qcom,smem = <481>, <430>;        1035                 qcom,smem = <481>, <430>;
1172                 interrupts = <GIC_SPI 172 IRQ    1036                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173                 mboxes = <&apss_shared 26>;      1037                 mboxes = <&apss_shared 26>;
1174                 qcom,local-pid = <0>;            1038                 qcom,local-pid = <0>;
1175                 qcom,remote-pid = <3>;           1039                 qcom,remote-pid = <3>;
1176                                                  1040 
1177                 slpi_smp2p_out: master-kernel    1041                 slpi_smp2p_out: master-kernel {
1178                         qcom,entry-name = "ma    1042                         qcom,entry-name = "master-kernel";
1179                         #qcom,smem-state-cell    1043                         #qcom,smem-state-cells = <1>;
1180                 };                               1044                 };
1181                                                  1045 
1182                 slpi_smp2p_in: slave-kernel {    1046                 slpi_smp2p_in: slave-kernel {
1183                         qcom,entry-name = "sl    1047                         qcom,entry-name = "slave-kernel";
1184                         interrupt-controller;    1048                         interrupt-controller;
1185                         #interrupt-cells = <2    1049                         #interrupt-cells = <2>;
1186                 };                               1050                 };
1187         };                                       1051         };
1188                                                  1052 
                                                   >> 1053         psci {
                                                   >> 1054                 compatible = "arm,psci-1.0";
                                                   >> 1055                 method = "smc";
                                                   >> 1056         };
                                                   >> 1057 
1189         soc: soc@0 {                             1058         soc: soc@0 {
1190                 #address-cells = <2>;            1059                 #address-cells = <2>;
1191                 #size-cells = <2>;               1060                 #size-cells = <2>;
1192                 ranges = <0 0 0 0 0x10 0>;       1061                 ranges = <0 0 0 0 0x10 0>;
1193                 dma-ranges = <0 0 0 0 0x10 0>    1062                 dma-ranges = <0 0 0 0 0x10 0>;
1194                 compatible = "simple-bus";       1063                 compatible = "simple-bus";
1195                                                  1064 
1196                 gcc: clock-controller@100000     1065                 gcc: clock-controller@100000 {
1197                         compatible = "qcom,gc    1066                         compatible = "qcom,gcc-sdm845";
1198                         reg = <0 0x00100000 0    1067                         reg = <0 0x00100000 0 0x1f0000>;
1199                         clocks = <&rpmhcc RPM    1068                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1200                                  <&rpmhcc RPM    1069                                  <&rpmhcc RPMH_CXO_CLK_A>,
1201                                  <&sleep_clk>    1070                                  <&sleep_clk>,
1202                                  <&pcie0_phy> !! 1071                                  <&pcie0_lane>,
1203                                  <&pcie1_phy> !! 1072                                  <&pcie1_lane>;
1204                         clock-names = "bi_tcx    1073                         clock-names = "bi_tcxo",
1205                                       "bi_tcx    1074                                       "bi_tcxo_ao",
1206                                       "sleep_    1075                                       "sleep_clk",
1207                                       "pcie_0    1076                                       "pcie_0_pipe_clk",
1208                                       "pcie_1    1077                                       "pcie_1_pipe_clk";
1209                         #clock-cells = <1>;      1078                         #clock-cells = <1>;
1210                         #reset-cells = <1>;      1079                         #reset-cells = <1>;
1211                         #power-domain-cells =    1080                         #power-domain-cells = <1>;
1212                         power-domains = <&rpm << 
1213                 };                               1081                 };
1214                                                  1082 
1215                 qfprom@784000 {                  1083                 qfprom@784000 {
1216                         compatible = "qcom,sd    1084                         compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217                         reg = <0 0x00784000 0    1085                         reg = <0 0x00784000 0 0x8ff>;
1218                         #address-cells = <1>;    1086                         #address-cells = <1>;
1219                         #size-cells = <1>;       1087                         #size-cells = <1>;
1220                                                  1088 
1221                         qusb2p_hstx_trim: hst    1089                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222                                 reg = <0x1eb     1090                                 reg = <0x1eb 0x1>;
1223                                 bits = <1 4>;    1091                                 bits = <1 4>;
1224                         };                       1092                         };
1225                                                  1093 
1226                         qusb2s_hstx_trim: hst    1094                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227                                 reg = <0x1eb     1095                                 reg = <0x1eb 0x2>;
1228                                 bits = <6 4>;    1096                                 bits = <6 4>;
1229                         };                       1097                         };
1230                 };                               1098                 };
1231                                                  1099 
1232                 rng: rng@793000 {                1100                 rng: rng@793000 {
1233                         compatible = "qcom,pr    1101                         compatible = "qcom,prng-ee";
1234                         reg = <0 0x00793000 0    1102                         reg = <0 0x00793000 0 0x1000>;
1235                         clocks = <&gcc GCC_PR    1103                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236                         clock-names = "core";    1104                         clock-names = "core";
1237                 };                               1105                 };
1238                                                  1106 
                                                   >> 1107                 qup_opp_table: qup-opp-table {
                                                   >> 1108                         compatible = "operating-points-v2";
                                                   >> 1109 
                                                   >> 1110                         opp-50000000 {
                                                   >> 1111                                 opp-hz = /bits/ 64 <50000000>;
                                                   >> 1112                                 required-opps = <&rpmhpd_opp_min_svs>;
                                                   >> 1113                         };
                                                   >> 1114 
                                                   >> 1115                         opp-75000000 {
                                                   >> 1116                                 opp-hz = /bits/ 64 <75000000>;
                                                   >> 1117                                 required-opps = <&rpmhpd_opp_low_svs>;
                                                   >> 1118                         };
                                                   >> 1119 
                                                   >> 1120                         opp-100000000 {
                                                   >> 1121                                 opp-hz = /bits/ 64 <100000000>;
                                                   >> 1122                                 required-opps = <&rpmhpd_opp_svs>;
                                                   >> 1123                         };
                                                   >> 1124 
                                                   >> 1125                         opp-128000000 {
                                                   >> 1126                                 opp-hz = /bits/ 64 <128000000>;
                                                   >> 1127                                 required-opps = <&rpmhpd_opp_nom>;
                                                   >> 1128                         };
                                                   >> 1129                 };
                                                   >> 1130 
1239                 gpi_dma0: dma-controller@8000    1131                 gpi_dma0: dma-controller@800000 {
1240                         #dma-cells = <3>;        1132                         #dma-cells = <3>;
1241                         compatible = "qcom,sd    1133                         compatible = "qcom,sdm845-gpi-dma";
1242                         reg = <0 0x00800000 0    1134                         reg = <0 0x00800000 0 0x60000>;
1243                         interrupts = <GIC_SPI    1135                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244                                      <GIC_SPI    1136                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245                                      <GIC_SPI    1137                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246                                      <GIC_SPI    1138                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247                                      <GIC_SPI    1139                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI    1140                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI    1141                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250                                      <GIC_SPI    1142                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251                                      <GIC_SPI    1143                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252                                      <GIC_SPI    1144                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253                                      <GIC_SPI    1145                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254                                      <GIC_SPI    1146                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255                                      <GIC_SPI    1147                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256                         dma-channels = <13>;     1148                         dma-channels = <13>;
1257                         dma-channel-mask = <0    1149                         dma-channel-mask = <0xfa>;
1258                         iommus = <&apps_smmu     1150                         iommus = <&apps_smmu 0x0016 0x0>;
1259                         status = "disabled";     1151                         status = "disabled";
1260                 };                               1152                 };
1261                                                  1153 
1262                 qupv3_id_0: geniqup@8c0000 {     1154                 qupv3_id_0: geniqup@8c0000 {
1263                         compatible = "qcom,ge    1155                         compatible = "qcom,geni-se-qup";
1264                         reg = <0 0x008c0000 0    1156                         reg = <0 0x008c0000 0 0x6000>;
1265                         clock-names = "m-ahb"    1157                         clock-names = "m-ahb", "s-ahb";
1266                         clocks = <&gcc GCC_QU    1158                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267                                  <&gcc GCC_QU    1159                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268                         iommus = <&apps_smmu     1160                         iommus = <&apps_smmu 0x3 0x0>;
1269                         #address-cells = <2>;    1161                         #address-cells = <2>;
1270                         #size-cells = <2>;       1162                         #size-cells = <2>;
1271                         ranges;                  1163                         ranges;
1272                         interconnects = <&agg    1164                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273                         interconnect-names =     1165                         interconnect-names = "qup-core";
1274                         status = "disabled";     1166                         status = "disabled";
1275                                                  1167 
1276                         i2c0: i2c@880000 {       1168                         i2c0: i2c@880000 {
1277                                 compatible =     1169                                 compatible = "qcom,geni-i2c";
1278                                 reg = <0 0x00    1170                                 reg = <0 0x00880000 0 0x4000>;
1279                                 clock-names =    1171                                 clock-names = "se";
1280                                 clocks = <&gc    1172                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281                                 pinctrl-names    1173                                 pinctrl-names = "default";
1282                                 pinctrl-0 = <    1174                                 pinctrl-0 = <&qup_i2c0_default>;
1283                                 interrupts =     1175                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284                                 #address-cell    1176                                 #address-cells = <1>;
1285                                 #size-cells =    1177                                 #size-cells = <0>;
1286                                 power-domains    1178                                 power-domains = <&rpmhpd SDM845_CX>;
1287                                 operating-poi    1179                                 operating-points-v2 = <&qup_opp_table>;
1288                                 interconnects    1180                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289                                                  1181                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290                                                  1182                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291                                 interconnect-    1183                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292                                 dmas = <&gpi_ << 
1293                                        <&gpi_ << 
1294                                 dma-names = " << 
1295                                 status = "dis    1184                                 status = "disabled";
1296                         };                       1185                         };
1297                                                  1186 
1298                         spi0: spi@880000 {       1187                         spi0: spi@880000 {
1299                                 compatible =     1188                                 compatible = "qcom,geni-spi";
1300                                 reg = <0 0x00    1189                                 reg = <0 0x00880000 0 0x4000>;
1301                                 clock-names =    1190                                 clock-names = "se";
1302                                 clocks = <&gc    1191                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303                                 pinctrl-names    1192                                 pinctrl-names = "default";
1304                                 pinctrl-0 = <    1193                                 pinctrl-0 = <&qup_spi0_default>;
1305                                 interrupts =     1194                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306                                 #address-cell    1195                                 #address-cells = <1>;
1307                                 #size-cells =    1196                                 #size-cells = <0>;
1308                                 interconnects    1197                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309                                                  1198                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310                                 interconnect-    1199                                 interconnect-names = "qup-core", "qup-config";
1311                                 dmas = <&gpi_    1200                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312                                        <&gpi_    1201                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313                                 dma-names = "    1202                                 dma-names = "tx", "rx";
1314                                 status = "dis    1203                                 status = "disabled";
1315                         };                       1204                         };
1316                                                  1205 
1317                         uart0: serial@880000     1206                         uart0: serial@880000 {
1318                                 compatible =     1207                                 compatible = "qcom,geni-uart";
1319                                 reg = <0 0x00    1208                                 reg = <0 0x00880000 0 0x4000>;
1320                                 clock-names =    1209                                 clock-names = "se";
1321                                 clocks = <&gc    1210                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322                                 pinctrl-names    1211                                 pinctrl-names = "default";
1323                                 pinctrl-0 = <    1212                                 pinctrl-0 = <&qup_uart0_default>;
1324                                 interrupts =     1213                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325                                 power-domains    1214                                 power-domains = <&rpmhpd SDM845_CX>;
1326                                 operating-poi    1215                                 operating-points-v2 = <&qup_opp_table>;
1327                                 interconnects    1216                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328                                                  1217                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329                                 interconnect-    1218                                 interconnect-names = "qup-core", "qup-config";
1330                                 status = "dis    1219                                 status = "disabled";
1331                         };                       1220                         };
1332                                                  1221 
1333                         i2c1: i2c@884000 {       1222                         i2c1: i2c@884000 {
1334                                 compatible =     1223                                 compatible = "qcom,geni-i2c";
1335                                 reg = <0 0x00    1224                                 reg = <0 0x00884000 0 0x4000>;
1336                                 clock-names =    1225                                 clock-names = "se";
1337                                 clocks = <&gc    1226                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338                                 pinctrl-names    1227                                 pinctrl-names = "default";
1339                                 pinctrl-0 = <    1228                                 pinctrl-0 = <&qup_i2c1_default>;
1340                                 interrupts =     1229                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341                                 #address-cell    1230                                 #address-cells = <1>;
1342                                 #size-cells =    1231                                 #size-cells = <0>;
1343                                 power-domains    1232                                 power-domains = <&rpmhpd SDM845_CX>;
1344                                 operating-poi    1233                                 operating-points-v2 = <&qup_opp_table>;
1345                                 interconnects    1234                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346                                                  1235                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347                                                  1236                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348                                 interconnect-    1237                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349                                 dmas = <&gpi_ << 
1350                                        <&gpi_ << 
1351                                 dma-names = " << 
1352                                 status = "dis    1238                                 status = "disabled";
1353                         };                       1239                         };
1354                                                  1240 
1355                         spi1: spi@884000 {       1241                         spi1: spi@884000 {
1356                                 compatible =     1242                                 compatible = "qcom,geni-spi";
1357                                 reg = <0 0x00    1243                                 reg = <0 0x00884000 0 0x4000>;
1358                                 clock-names =    1244                                 clock-names = "se";
1359                                 clocks = <&gc    1245                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360                                 pinctrl-names    1246                                 pinctrl-names = "default";
1361                                 pinctrl-0 = <    1247                                 pinctrl-0 = <&qup_spi1_default>;
1362                                 interrupts =     1248                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363                                 #address-cell    1249                                 #address-cells = <1>;
1364                                 #size-cells =    1250                                 #size-cells = <0>;
1365                                 interconnects    1251                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366                                                  1252                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367                                 interconnect-    1253                                 interconnect-names = "qup-core", "qup-config";
1368                                 dmas = <&gpi_ << 
1369                                        <&gpi_ << 
1370                                 dma-names = " << 
1371                                 status = "dis    1254                                 status = "disabled";
1372                         };                       1255                         };
1373                                                  1256 
1374                         uart1: serial@884000     1257                         uart1: serial@884000 {
1375                                 compatible =     1258                                 compatible = "qcom,geni-uart";
1376                                 reg = <0 0x00    1259                                 reg = <0 0x00884000 0 0x4000>;
1377                                 clock-names =    1260                                 clock-names = "se";
1378                                 clocks = <&gc    1261                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379                                 pinctrl-names    1262                                 pinctrl-names = "default";
1380                                 pinctrl-0 = <    1263                                 pinctrl-0 = <&qup_uart1_default>;
1381                                 interrupts =     1264                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382                                 power-domains    1265                                 power-domains = <&rpmhpd SDM845_CX>;
1383                                 operating-poi    1266                                 operating-points-v2 = <&qup_opp_table>;
1384                                 interconnects    1267                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385                                                  1268                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386                                 interconnect-    1269                                 interconnect-names = "qup-core", "qup-config";
1387                                 status = "dis    1270                                 status = "disabled";
1388                         };                       1271                         };
1389                                                  1272 
1390                         i2c2: i2c@888000 {       1273                         i2c2: i2c@888000 {
1391                                 compatible =     1274                                 compatible = "qcom,geni-i2c";
1392                                 reg = <0 0x00    1275                                 reg = <0 0x00888000 0 0x4000>;
1393                                 clock-names =    1276                                 clock-names = "se";
1394                                 clocks = <&gc    1277                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395                                 pinctrl-names    1278                                 pinctrl-names = "default";
1396                                 pinctrl-0 = <    1279                                 pinctrl-0 = <&qup_i2c2_default>;
1397                                 interrupts =     1280                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398                                 #address-cell    1281                                 #address-cells = <1>;
1399                                 #size-cells =    1282                                 #size-cells = <0>;
1400                                 power-domains    1283                                 power-domains = <&rpmhpd SDM845_CX>;
1401                                 operating-poi    1284                                 operating-points-v2 = <&qup_opp_table>;
1402                                 interconnects    1285                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403                                                  1286                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404                                                  1287                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405                                 interconnect-    1288                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406                                 dmas = <&gpi_ << 
1407                                        <&gpi_ << 
1408                                 dma-names = " << 
1409                                 status = "dis    1289                                 status = "disabled";
1410                         };                       1290                         };
1411                                                  1291 
1412                         spi2: spi@888000 {       1292                         spi2: spi@888000 {
1413                                 compatible =     1293                                 compatible = "qcom,geni-spi";
1414                                 reg = <0 0x00    1294                                 reg = <0 0x00888000 0 0x4000>;
1415                                 clock-names =    1295                                 clock-names = "se";
1416                                 clocks = <&gc    1296                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417                                 pinctrl-names    1297                                 pinctrl-names = "default";
1418                                 pinctrl-0 = <    1298                                 pinctrl-0 = <&qup_spi2_default>;
1419                                 interrupts =     1299                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420                                 #address-cell    1300                                 #address-cells = <1>;
1421                                 #size-cells =    1301                                 #size-cells = <0>;
1422                                 interconnects    1302                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423                                                  1303                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424                                 interconnect-    1304                                 interconnect-names = "qup-core", "qup-config";
1425                                 dmas = <&gpi_ << 
1426                                        <&gpi_ << 
1427                                 dma-names = " << 
1428                                 status = "dis    1305                                 status = "disabled";
1429                         };                       1306                         };
1430                                                  1307 
1431                         uart2: serial@888000     1308                         uart2: serial@888000 {
1432                                 compatible =     1309                                 compatible = "qcom,geni-uart";
1433                                 reg = <0 0x00    1310                                 reg = <0 0x00888000 0 0x4000>;
1434                                 clock-names =    1311                                 clock-names = "se";
1435                                 clocks = <&gc    1312                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436                                 pinctrl-names    1313                                 pinctrl-names = "default";
1437                                 pinctrl-0 = <    1314                                 pinctrl-0 = <&qup_uart2_default>;
1438                                 interrupts =     1315                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439                                 power-domains    1316                                 power-domains = <&rpmhpd SDM845_CX>;
1440                                 operating-poi    1317                                 operating-points-v2 = <&qup_opp_table>;
1441                                 interconnects    1318                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442                                                  1319                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443                                 interconnect-    1320                                 interconnect-names = "qup-core", "qup-config";
1444                                 status = "dis    1321                                 status = "disabled";
1445                         };                       1322                         };
1446                                                  1323 
1447                         i2c3: i2c@88c000 {       1324                         i2c3: i2c@88c000 {
1448                                 compatible =     1325                                 compatible = "qcom,geni-i2c";
1449                                 reg = <0 0x00    1326                                 reg = <0 0x0088c000 0 0x4000>;
1450                                 clock-names =    1327                                 clock-names = "se";
1451                                 clocks = <&gc    1328                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452                                 pinctrl-names    1329                                 pinctrl-names = "default";
1453                                 pinctrl-0 = <    1330                                 pinctrl-0 = <&qup_i2c3_default>;
1454                                 interrupts =     1331                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455                                 #address-cell    1332                                 #address-cells = <1>;
1456                                 #size-cells =    1333                                 #size-cells = <0>;
1457                                 power-domains    1334                                 power-domains = <&rpmhpd SDM845_CX>;
1458                                 operating-poi    1335                                 operating-points-v2 = <&qup_opp_table>;
1459                                 interconnects    1336                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460                                                  1337                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461                                                  1338                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462                                 interconnect-    1339                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463                                 dmas = <&gpi_ << 
1464                                        <&gpi_ << 
1465                                 dma-names = " << 
1466                                 status = "dis    1340                                 status = "disabled";
1467                         };                       1341                         };
1468                                                  1342 
1469                         spi3: spi@88c000 {       1343                         spi3: spi@88c000 {
1470                                 compatible =     1344                                 compatible = "qcom,geni-spi";
1471                                 reg = <0 0x00    1345                                 reg = <0 0x0088c000 0 0x4000>;
1472                                 clock-names =    1346                                 clock-names = "se";
1473                                 clocks = <&gc    1347                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474                                 pinctrl-names    1348                                 pinctrl-names = "default";
1475                                 pinctrl-0 = <    1349                                 pinctrl-0 = <&qup_spi3_default>;
1476                                 interrupts =     1350                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477                                 #address-cell    1351                                 #address-cells = <1>;
1478                                 #size-cells =    1352                                 #size-cells = <0>;
1479                                 interconnects    1353                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480                                                  1354                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481                                 interconnect-    1355                                 interconnect-names = "qup-core", "qup-config";
1482                                 dmas = <&gpi_ << 
1483                                        <&gpi_ << 
1484                                 dma-names = " << 
1485                                 status = "dis    1356                                 status = "disabled";
1486                         };                       1357                         };
1487                                                  1358 
1488                         uart3: serial@88c000     1359                         uart3: serial@88c000 {
1489                                 compatible =     1360                                 compatible = "qcom,geni-uart";
1490                                 reg = <0 0x00    1361                                 reg = <0 0x0088c000 0 0x4000>;
1491                                 clock-names =    1362                                 clock-names = "se";
1492                                 clocks = <&gc    1363                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493                                 pinctrl-names    1364                                 pinctrl-names = "default";
1494                                 pinctrl-0 = <    1365                                 pinctrl-0 = <&qup_uart3_default>;
1495                                 interrupts =     1366                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496                                 power-domains    1367                                 power-domains = <&rpmhpd SDM845_CX>;
1497                                 operating-poi    1368                                 operating-points-v2 = <&qup_opp_table>;
1498                                 interconnects    1369                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499                                                  1370                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500                                 interconnect-    1371                                 interconnect-names = "qup-core", "qup-config";
1501                                 status = "dis    1372                                 status = "disabled";
1502                         };                       1373                         };
1503                                                  1374 
1504                         i2c4: i2c@890000 {       1375                         i2c4: i2c@890000 {
1505                                 compatible =     1376                                 compatible = "qcom,geni-i2c";
1506                                 reg = <0 0x00    1377                                 reg = <0 0x00890000 0 0x4000>;
1507                                 clock-names =    1378                                 clock-names = "se";
1508                                 clocks = <&gc    1379                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509                                 pinctrl-names    1380                                 pinctrl-names = "default";
1510                                 pinctrl-0 = <    1381                                 pinctrl-0 = <&qup_i2c4_default>;
1511                                 interrupts =     1382                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512                                 #address-cell    1383                                 #address-cells = <1>;
1513                                 #size-cells =    1384                                 #size-cells = <0>;
1514                                 power-domains    1385                                 power-domains = <&rpmhpd SDM845_CX>;
1515                                 operating-poi    1386                                 operating-points-v2 = <&qup_opp_table>;
1516                                 interconnects    1387                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517                                                  1388                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518                                                  1389                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519                                 interconnect-    1390                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520                                 dmas = <&gpi_ << 
1521                                        <&gpi_ << 
1522                                 dma-names = " << 
1523                                 status = "dis    1391                                 status = "disabled";
1524                         };                       1392                         };
1525                                                  1393 
1526                         spi4: spi@890000 {       1394                         spi4: spi@890000 {
1527                                 compatible =     1395                                 compatible = "qcom,geni-spi";
1528                                 reg = <0 0x00    1396                                 reg = <0 0x00890000 0 0x4000>;
1529                                 clock-names =    1397                                 clock-names = "se";
1530                                 clocks = <&gc    1398                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531                                 pinctrl-names    1399                                 pinctrl-names = "default";
1532                                 pinctrl-0 = <    1400                                 pinctrl-0 = <&qup_spi4_default>;
1533                                 interrupts =     1401                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534                                 #address-cell    1402                                 #address-cells = <1>;
1535                                 #size-cells =    1403                                 #size-cells = <0>;
1536                                 interconnects    1404                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537                                                  1405                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538                                 interconnect-    1406                                 interconnect-names = "qup-core", "qup-config";
1539                                 dmas = <&gpi_ << 
1540                                        <&gpi_ << 
1541                                 dma-names = " << 
1542                                 status = "dis    1407                                 status = "disabled";
1543                         };                       1408                         };
1544                                                  1409 
1545                         uart4: serial@890000     1410                         uart4: serial@890000 {
1546                                 compatible =     1411                                 compatible = "qcom,geni-uart";
1547                                 reg = <0 0x00    1412                                 reg = <0 0x00890000 0 0x4000>;
1548                                 clock-names =    1413                                 clock-names = "se";
1549                                 clocks = <&gc    1414                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550                                 pinctrl-names    1415                                 pinctrl-names = "default";
1551                                 pinctrl-0 = <    1416                                 pinctrl-0 = <&qup_uart4_default>;
1552                                 interrupts =     1417                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553                                 power-domains    1418                                 power-domains = <&rpmhpd SDM845_CX>;
1554                                 operating-poi    1419                                 operating-points-v2 = <&qup_opp_table>;
1555                                 interconnects    1420                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556                                                  1421                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557                                 interconnect-    1422                                 interconnect-names = "qup-core", "qup-config";
1558                                 status = "dis    1423                                 status = "disabled";
1559                         };                       1424                         };
1560                                                  1425 
1561                         i2c5: i2c@894000 {       1426                         i2c5: i2c@894000 {
1562                                 compatible =     1427                                 compatible = "qcom,geni-i2c";
1563                                 reg = <0 0x00    1428                                 reg = <0 0x00894000 0 0x4000>;
1564                                 clock-names =    1429                                 clock-names = "se";
1565                                 clocks = <&gc    1430                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566                                 pinctrl-names    1431                                 pinctrl-names = "default";
1567                                 pinctrl-0 = <    1432                                 pinctrl-0 = <&qup_i2c5_default>;
1568                                 interrupts =     1433                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569                                 #address-cell    1434                                 #address-cells = <1>;
1570                                 #size-cells =    1435                                 #size-cells = <0>;
1571                                 power-domains    1436                                 power-domains = <&rpmhpd SDM845_CX>;
1572                                 operating-poi    1437                                 operating-points-v2 = <&qup_opp_table>;
1573                                 interconnects    1438                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574                                                  1439                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575                                                  1440                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576                                 interconnect-    1441                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577                                 dmas = <&gpi_ << 
1578                                        <&gpi_ << 
1579                                 dma-names = " << 
1580                                 status = "dis    1442                                 status = "disabled";
1581                         };                       1443                         };
1582                                                  1444 
1583                         spi5: spi@894000 {       1445                         spi5: spi@894000 {
1584                                 compatible =     1446                                 compatible = "qcom,geni-spi";
1585                                 reg = <0 0x00    1447                                 reg = <0 0x00894000 0 0x4000>;
1586                                 clock-names =    1448                                 clock-names = "se";
1587                                 clocks = <&gc    1449                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588                                 pinctrl-names    1450                                 pinctrl-names = "default";
1589                                 pinctrl-0 = <    1451                                 pinctrl-0 = <&qup_spi5_default>;
1590                                 interrupts =     1452                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591                                 #address-cell    1453                                 #address-cells = <1>;
1592                                 #size-cells =    1454                                 #size-cells = <0>;
1593                                 interconnects    1455                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594                                                  1456                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595                                 interconnect-    1457                                 interconnect-names = "qup-core", "qup-config";
1596                                 dmas = <&gpi_ << 
1597                                        <&gpi_ << 
1598                                 dma-names = " << 
1599                                 status = "dis    1458                                 status = "disabled";
1600                         };                       1459                         };
1601                                                  1460 
1602                         uart5: serial@894000     1461                         uart5: serial@894000 {
1603                                 compatible =     1462                                 compatible = "qcom,geni-uart";
1604                                 reg = <0 0x00    1463                                 reg = <0 0x00894000 0 0x4000>;
1605                                 clock-names =    1464                                 clock-names = "se";
1606                                 clocks = <&gc    1465                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607                                 pinctrl-names    1466                                 pinctrl-names = "default";
1608                                 pinctrl-0 = <    1467                                 pinctrl-0 = <&qup_uart5_default>;
1609                                 interrupts =     1468                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610                                 power-domains    1469                                 power-domains = <&rpmhpd SDM845_CX>;
1611                                 operating-poi    1470                                 operating-points-v2 = <&qup_opp_table>;
1612                                 interconnects    1471                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613                                                  1472                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614                                 interconnect-    1473                                 interconnect-names = "qup-core", "qup-config";
1615                                 status = "dis    1474                                 status = "disabled";
1616                         };                       1475                         };
1617                                                  1476 
1618                         i2c6: i2c@898000 {       1477                         i2c6: i2c@898000 {
1619                                 compatible =     1478                                 compatible = "qcom,geni-i2c";
1620                                 reg = <0 0x00    1479                                 reg = <0 0x00898000 0 0x4000>;
1621                                 clock-names =    1480                                 clock-names = "se";
1622                                 clocks = <&gc    1481                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623                                 pinctrl-names    1482                                 pinctrl-names = "default";
1624                                 pinctrl-0 = <    1483                                 pinctrl-0 = <&qup_i2c6_default>;
1625                                 interrupts =     1484                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626                                 #address-cell    1485                                 #address-cells = <1>;
1627                                 #size-cells =    1486                                 #size-cells = <0>;
1628                                 power-domains    1487                                 power-domains = <&rpmhpd SDM845_CX>;
1629                                 operating-poi    1488                                 operating-points-v2 = <&qup_opp_table>;
1630                                 interconnects    1489                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631                                                  1490                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632                                                  1491                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633                                 interconnect-    1492                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634                                 dmas = <&gpi_ << 
1635                                        <&gpi_ << 
1636                                 dma-names = " << 
1637                                 status = "dis    1493                                 status = "disabled";
1638                         };                       1494                         };
1639                                                  1495 
1640                         spi6: spi@898000 {       1496                         spi6: spi@898000 {
1641                                 compatible =     1497                                 compatible = "qcom,geni-spi";
1642                                 reg = <0 0x00    1498                                 reg = <0 0x00898000 0 0x4000>;
1643                                 clock-names =    1499                                 clock-names = "se";
1644                                 clocks = <&gc    1500                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645                                 pinctrl-names    1501                                 pinctrl-names = "default";
1646                                 pinctrl-0 = <    1502                                 pinctrl-0 = <&qup_spi6_default>;
1647                                 interrupts =     1503                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648                                 #address-cell    1504                                 #address-cells = <1>;
1649                                 #size-cells =    1505                                 #size-cells = <0>;
1650                                 interconnects    1506                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651                                                  1507                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652                                 interconnect-    1508                                 interconnect-names = "qup-core", "qup-config";
1653                                 dmas = <&gpi_ << 
1654                                        <&gpi_ << 
1655                                 dma-names = " << 
1656                                 status = "dis    1509                                 status = "disabled";
1657                         };                       1510                         };
1658                                                  1511 
1659                         uart6: serial@898000     1512                         uart6: serial@898000 {
1660                                 compatible =     1513                                 compatible = "qcom,geni-uart";
1661                                 reg = <0 0x00    1514                                 reg = <0 0x00898000 0 0x4000>;
1662                                 clock-names =    1515                                 clock-names = "se";
1663                                 clocks = <&gc    1516                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664                                 pinctrl-names    1517                                 pinctrl-names = "default";
1665                                 pinctrl-0 = <    1518                                 pinctrl-0 = <&qup_uart6_default>;
1666                                 interrupts =     1519                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667                                 power-domains    1520                                 power-domains = <&rpmhpd SDM845_CX>;
1668                                 operating-poi    1521                                 operating-points-v2 = <&qup_opp_table>;
1669                                 interconnects    1522                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670                                                  1523                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671                                 interconnect-    1524                                 interconnect-names = "qup-core", "qup-config";
1672                                 status = "dis    1525                                 status = "disabled";
1673                         };                       1526                         };
1674                                                  1527 
1675                         i2c7: i2c@89c000 {       1528                         i2c7: i2c@89c000 {
1676                                 compatible =     1529                                 compatible = "qcom,geni-i2c";
1677                                 reg = <0 0x00    1530                                 reg = <0 0x0089c000 0 0x4000>;
1678                                 clock-names =    1531                                 clock-names = "se";
1679                                 clocks = <&gc    1532                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680                                 pinctrl-names    1533                                 pinctrl-names = "default";
1681                                 pinctrl-0 = <    1534                                 pinctrl-0 = <&qup_i2c7_default>;
1682                                 interrupts =     1535                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683                                 #address-cell    1536                                 #address-cells = <1>;
1684                                 #size-cells =    1537                                 #size-cells = <0>;
1685                                 power-domains    1538                                 power-domains = <&rpmhpd SDM845_CX>;
1686                                 operating-poi    1539                                 operating-points-v2 = <&qup_opp_table>;
1687                                 status = "dis    1540                                 status = "disabled";
1688                         };                       1541                         };
1689                                                  1542 
1690                         spi7: spi@89c000 {       1543                         spi7: spi@89c000 {
1691                                 compatible =     1544                                 compatible = "qcom,geni-spi";
1692                                 reg = <0 0x00    1545                                 reg = <0 0x0089c000 0 0x4000>;
1693                                 clock-names =    1546                                 clock-names = "se";
1694                                 clocks = <&gc    1547                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695                                 pinctrl-names    1548                                 pinctrl-names = "default";
1696                                 pinctrl-0 = <    1549                                 pinctrl-0 = <&qup_spi7_default>;
1697                                 interrupts =     1550                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698                                 #address-cell    1551                                 #address-cells = <1>;
1699                                 #size-cells =    1552                                 #size-cells = <0>;
1700                                 interconnects    1553                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701                                                  1554                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702                                 interconnect-    1555                                 interconnect-names = "qup-core", "qup-config";
1703                                 dmas = <&gpi_ << 
1704                                        <&gpi_ << 
1705                                 dma-names = " << 
1706                                 status = "dis    1556                                 status = "disabled";
1707                         };                       1557                         };
1708                                                  1558 
1709                         uart7: serial@89c000     1559                         uart7: serial@89c000 {
1710                                 compatible =     1560                                 compatible = "qcom,geni-uart";
1711                                 reg = <0 0x00    1561                                 reg = <0 0x0089c000 0 0x4000>;
1712                                 clock-names =    1562                                 clock-names = "se";
1713                                 clocks = <&gc    1563                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714                                 pinctrl-names    1564                                 pinctrl-names = "default";
1715                                 pinctrl-0 = <    1565                                 pinctrl-0 = <&qup_uart7_default>;
1716                                 interrupts =     1566                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717                                 power-domains    1567                                 power-domains = <&rpmhpd SDM845_CX>;
1718                                 operating-poi    1568                                 operating-points-v2 = <&qup_opp_table>;
1719                                 interconnects    1569                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720                                                  1570                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721                                 interconnect-    1571                                 interconnect-names = "qup-core", "qup-config";
1722                                 status = "dis    1572                                 status = "disabled";
1723                         };                       1573                         };
1724                 };                               1574                 };
1725                                                  1575 
1726                 gpi_dma1: dma-controller@a000 !! 1576                 gpi_dma1: dma-controller@0xa00000 {
1727                         #dma-cells = <3>;        1577                         #dma-cells = <3>;
1728                         compatible = "qcom,sd    1578                         compatible = "qcom,sdm845-gpi-dma";
1729                         reg = <0 0x00a00000 0    1579                         reg = <0 0x00a00000 0 0x60000>;
1730                         interrupts = <GIC_SPI    1580                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731                                      <GIC_SPI    1581                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732                                      <GIC_SPI    1582                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733                                      <GIC_SPI    1583                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734                                      <GIC_SPI    1584                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI    1585                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736                                      <GIC_SPI    1586                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI    1587                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738                                      <GIC_SPI    1588                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI    1589                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740                                      <GIC_SPI    1590                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741                                      <GIC_SPI    1591                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742                                      <GIC_SPI    1592                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743                         dma-channels = <13>;     1593                         dma-channels = <13>;
1744                         dma-channel-mask = <0    1594                         dma-channel-mask = <0xfa>;
1745                         iommus = <&apps_smmu     1595                         iommus = <&apps_smmu 0x06d6 0x0>;
1746                         status = "disabled";     1596                         status = "disabled";
1747                 };                               1597                 };
1748                                                  1598 
1749                 qupv3_id_1: geniqup@ac0000 {     1599                 qupv3_id_1: geniqup@ac0000 {
1750                         compatible = "qcom,ge    1600                         compatible = "qcom,geni-se-qup";
1751                         reg = <0 0x00ac0000 0    1601                         reg = <0 0x00ac0000 0 0x6000>;
1752                         clock-names = "m-ahb"    1602                         clock-names = "m-ahb", "s-ahb";
1753                         clocks = <&gcc GCC_QU    1603                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754                                  <&gcc GCC_QU    1604                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755                         iommus = <&apps_smmu     1605                         iommus = <&apps_smmu 0x6c3 0x0>;
1756                         #address-cells = <2>;    1606                         #address-cells = <2>;
1757                         #size-cells = <2>;       1607                         #size-cells = <2>;
1758                         ranges;                  1608                         ranges;
1759                         interconnects = <&agg    1609                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760                         interconnect-names =     1610                         interconnect-names = "qup-core";
1761                         status = "disabled";     1611                         status = "disabled";
1762                                                  1612 
1763                         i2c8: i2c@a80000 {       1613                         i2c8: i2c@a80000 {
1764                                 compatible =     1614                                 compatible = "qcom,geni-i2c";
1765                                 reg = <0 0x00    1615                                 reg = <0 0x00a80000 0 0x4000>;
1766                                 clock-names =    1616                                 clock-names = "se";
1767                                 clocks = <&gc    1617                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768                                 pinctrl-names    1618                                 pinctrl-names = "default";
1769                                 pinctrl-0 = <    1619                                 pinctrl-0 = <&qup_i2c8_default>;
1770                                 interrupts =     1620                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771                                 #address-cell    1621                                 #address-cells = <1>;
1772                                 #size-cells =    1622                                 #size-cells = <0>;
1773                                 power-domains    1623                                 power-domains = <&rpmhpd SDM845_CX>;
1774                                 operating-poi    1624                                 operating-points-v2 = <&qup_opp_table>;
1775                                 interconnects    1625                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776                                                  1626                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777                                                  1627                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778                                 interconnect-    1628                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779                                 dmas = <&gpi_ << 
1780                                        <&gpi_ << 
1781                                 dma-names = " << 
1782                                 status = "dis    1629                                 status = "disabled";
1783                         };                       1630                         };
1784                                                  1631 
1785                         spi8: spi@a80000 {       1632                         spi8: spi@a80000 {
1786                                 compatible =     1633                                 compatible = "qcom,geni-spi";
1787                                 reg = <0 0x00    1634                                 reg = <0 0x00a80000 0 0x4000>;
1788                                 clock-names =    1635                                 clock-names = "se";
1789                                 clocks = <&gc    1636                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790                                 pinctrl-names    1637                                 pinctrl-names = "default";
1791                                 pinctrl-0 = <    1638                                 pinctrl-0 = <&qup_spi8_default>;
1792                                 interrupts =     1639                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793                                 #address-cell    1640                                 #address-cells = <1>;
1794                                 #size-cells =    1641                                 #size-cells = <0>;
1795                                 interconnects    1642                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796                                                  1643                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797                                 interconnect-    1644                                 interconnect-names = "qup-core", "qup-config";
1798                                 dmas = <&gpi_ << 
1799                                        <&gpi_ << 
1800                                 dma-names = " << 
1801                                 status = "dis    1645                                 status = "disabled";
1802                         };                       1646                         };
1803                                                  1647 
1804                         uart8: serial@a80000     1648                         uart8: serial@a80000 {
1805                                 compatible =     1649                                 compatible = "qcom,geni-uart";
1806                                 reg = <0 0x00    1650                                 reg = <0 0x00a80000 0 0x4000>;
1807                                 clock-names =    1651                                 clock-names = "se";
1808                                 clocks = <&gc    1652                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809                                 pinctrl-names    1653                                 pinctrl-names = "default";
1810                                 pinctrl-0 = <    1654                                 pinctrl-0 = <&qup_uart8_default>;
1811                                 interrupts =     1655                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812                                 power-domains    1656                                 power-domains = <&rpmhpd SDM845_CX>;
1813                                 operating-poi    1657                                 operating-points-v2 = <&qup_opp_table>;
1814                                 interconnects    1658                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815                                                  1659                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816                                 interconnect-    1660                                 interconnect-names = "qup-core", "qup-config";
1817                                 status = "dis    1661                                 status = "disabled";
1818                         };                       1662                         };
1819                                                  1663 
1820                         i2c9: i2c@a84000 {       1664                         i2c9: i2c@a84000 {
1821                                 compatible =     1665                                 compatible = "qcom,geni-i2c";
1822                                 reg = <0 0x00    1666                                 reg = <0 0x00a84000 0 0x4000>;
1823                                 clock-names =    1667                                 clock-names = "se";
1824                                 clocks = <&gc    1668                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825                                 pinctrl-names    1669                                 pinctrl-names = "default";
1826                                 pinctrl-0 = <    1670                                 pinctrl-0 = <&qup_i2c9_default>;
1827                                 interrupts =     1671                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828                                 #address-cell    1672                                 #address-cells = <1>;
1829                                 #size-cells =    1673                                 #size-cells = <0>;
1830                                 power-domains    1674                                 power-domains = <&rpmhpd SDM845_CX>;
1831                                 operating-poi    1675                                 operating-points-v2 = <&qup_opp_table>;
1832                                 interconnects    1676                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833                                                  1677                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834                                                  1678                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835                                 interconnect-    1679                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836                                 dmas = <&gpi_ << 
1837                                        <&gpi_ << 
1838                                 dma-names = " << 
1839                                 status = "dis    1680                                 status = "disabled";
1840                         };                       1681                         };
1841                                                  1682 
1842                         spi9: spi@a84000 {       1683                         spi9: spi@a84000 {
1843                                 compatible =     1684                                 compatible = "qcom,geni-spi";
1844                                 reg = <0 0x00    1685                                 reg = <0 0x00a84000 0 0x4000>;
1845                                 clock-names =    1686                                 clock-names = "se";
1846                                 clocks = <&gc    1687                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847                                 pinctrl-names    1688                                 pinctrl-names = "default";
1848                                 pinctrl-0 = <    1689                                 pinctrl-0 = <&qup_spi9_default>;
1849                                 interrupts =     1690                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850                                 #address-cell    1691                                 #address-cells = <1>;
1851                                 #size-cells =    1692                                 #size-cells = <0>;
1852                                 interconnects    1693                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853                                                  1694                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854                                 interconnect-    1695                                 interconnect-names = "qup-core", "qup-config";
1855                                 dmas = <&gpi_ << 
1856                                        <&gpi_ << 
1857                                 dma-names = " << 
1858                                 status = "dis    1696                                 status = "disabled";
1859                         };                       1697                         };
1860                                                  1698 
1861                         uart9: serial@a84000     1699                         uart9: serial@a84000 {
1862                                 compatible =     1700                                 compatible = "qcom,geni-debug-uart";
1863                                 reg = <0 0x00    1701                                 reg = <0 0x00a84000 0 0x4000>;
1864                                 clock-names =    1702                                 clock-names = "se";
1865                                 clocks = <&gc    1703                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866                                 pinctrl-names    1704                                 pinctrl-names = "default";
1867                                 pinctrl-0 = <    1705                                 pinctrl-0 = <&qup_uart9_default>;
1868                                 interrupts =     1706                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869                                 power-domains    1707                                 power-domains = <&rpmhpd SDM845_CX>;
1870                                 operating-poi    1708                                 operating-points-v2 = <&qup_opp_table>;
1871                                 interconnects    1709                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872                                                  1710                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873                                 interconnect-    1711                                 interconnect-names = "qup-core", "qup-config";
1874                                 status = "dis    1712                                 status = "disabled";
1875                         };                       1713                         };
1876                                                  1714 
1877                         i2c10: i2c@a88000 {      1715                         i2c10: i2c@a88000 {
1878                                 compatible =     1716                                 compatible = "qcom,geni-i2c";
1879                                 reg = <0 0x00    1717                                 reg = <0 0x00a88000 0 0x4000>;
1880                                 clock-names =    1718                                 clock-names = "se";
1881                                 clocks = <&gc    1719                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882                                 pinctrl-names    1720                                 pinctrl-names = "default";
1883                                 pinctrl-0 = <    1721                                 pinctrl-0 = <&qup_i2c10_default>;
1884                                 interrupts =     1722                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885                                 #address-cell    1723                                 #address-cells = <1>;
1886                                 #size-cells =    1724                                 #size-cells = <0>;
1887                                 power-domains    1725                                 power-domains = <&rpmhpd SDM845_CX>;
1888                                 operating-poi    1726                                 operating-points-v2 = <&qup_opp_table>;
1889                                 interconnects    1727                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890                                                  1728                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891                                                  1729                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892                                 interconnect-    1730                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893                                 dmas = <&gpi_ << 
1894                                        <&gpi_ << 
1895                                 dma-names = " << 
1896                                 status = "dis    1731                                 status = "disabled";
1897                         };                       1732                         };
1898                                                  1733 
1899                         spi10: spi@a88000 {      1734                         spi10: spi@a88000 {
1900                                 compatible =     1735                                 compatible = "qcom,geni-spi";
1901                                 reg = <0 0x00    1736                                 reg = <0 0x00a88000 0 0x4000>;
1902                                 clock-names =    1737                                 clock-names = "se";
1903                                 clocks = <&gc    1738                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904                                 pinctrl-names    1739                                 pinctrl-names = "default";
1905                                 pinctrl-0 = <    1740                                 pinctrl-0 = <&qup_spi10_default>;
1906                                 interrupts =     1741                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907                                 #address-cell    1742                                 #address-cells = <1>;
1908                                 #size-cells =    1743                                 #size-cells = <0>;
1909                                 interconnects    1744                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910                                                  1745                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911                                 interconnect-    1746                                 interconnect-names = "qup-core", "qup-config";
1912                                 dmas = <&gpi_ << 
1913                                        <&gpi_ << 
1914                                 dma-names = " << 
1915                                 status = "dis    1747                                 status = "disabled";
1916                         };                       1748                         };
1917                                                  1749 
1918                         uart10: serial@a88000    1750                         uart10: serial@a88000 {
1919                                 compatible =     1751                                 compatible = "qcom,geni-uart";
1920                                 reg = <0 0x00    1752                                 reg = <0 0x00a88000 0 0x4000>;
1921                                 clock-names =    1753                                 clock-names = "se";
1922                                 clocks = <&gc    1754                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923                                 pinctrl-names    1755                                 pinctrl-names = "default";
1924                                 pinctrl-0 = <    1756                                 pinctrl-0 = <&qup_uart10_default>;
1925                                 interrupts =     1757                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926                                 power-domains    1758                                 power-domains = <&rpmhpd SDM845_CX>;
1927                                 operating-poi    1759                                 operating-points-v2 = <&qup_opp_table>;
1928                                 interconnects    1760                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929                                                  1761                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930                                 interconnect-    1762                                 interconnect-names = "qup-core", "qup-config";
1931                                 status = "dis    1763                                 status = "disabled";
1932                         };                       1764                         };
1933                                                  1765 
1934                         i2c11: i2c@a8c000 {      1766                         i2c11: i2c@a8c000 {
1935                                 compatible =     1767                                 compatible = "qcom,geni-i2c";
1936                                 reg = <0 0x00    1768                                 reg = <0 0x00a8c000 0 0x4000>;
1937                                 clock-names =    1769                                 clock-names = "se";
1938                                 clocks = <&gc    1770                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939                                 pinctrl-names    1771                                 pinctrl-names = "default";
1940                                 pinctrl-0 = <    1772                                 pinctrl-0 = <&qup_i2c11_default>;
1941                                 interrupts =     1773                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942                                 #address-cell    1774                                 #address-cells = <1>;
1943                                 #size-cells =    1775                                 #size-cells = <0>;
1944                                 power-domains    1776                                 power-domains = <&rpmhpd SDM845_CX>;
1945                                 operating-poi    1777                                 operating-points-v2 = <&qup_opp_table>;
1946                                 interconnects    1778                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947                                                  1779                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948                                                  1780                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949                                 interconnect-    1781                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950                                 dmas = <&gpi_ << 
1951                                        <&gpi_ << 
1952                                 dma-names = " << 
1953                                 status = "dis    1782                                 status = "disabled";
1954                         };                       1783                         };
1955                                                  1784 
1956                         spi11: spi@a8c000 {      1785                         spi11: spi@a8c000 {
1957                                 compatible =     1786                                 compatible = "qcom,geni-spi";
1958                                 reg = <0 0x00    1787                                 reg = <0 0x00a8c000 0 0x4000>;
1959                                 clock-names =    1788                                 clock-names = "se";
1960                                 clocks = <&gc    1789                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961                                 pinctrl-names    1790                                 pinctrl-names = "default";
1962                                 pinctrl-0 = <    1791                                 pinctrl-0 = <&qup_spi11_default>;
1963                                 interrupts =     1792                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964                                 #address-cell    1793                                 #address-cells = <1>;
1965                                 #size-cells =    1794                                 #size-cells = <0>;
1966                                 interconnects    1795                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967                                                  1796                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968                                 interconnect-    1797                                 interconnect-names = "qup-core", "qup-config";
1969                                 dmas = <&gpi_ << 
1970                                        <&gpi_ << 
1971                                 dma-names = " << 
1972                                 status = "dis    1798                                 status = "disabled";
1973                         };                       1799                         };
1974                                                  1800 
1975                         uart11: serial@a8c000    1801                         uart11: serial@a8c000 {
1976                                 compatible =     1802                                 compatible = "qcom,geni-uart";
1977                                 reg = <0 0x00    1803                                 reg = <0 0x00a8c000 0 0x4000>;
1978                                 clock-names =    1804                                 clock-names = "se";
1979                                 clocks = <&gc    1805                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980                                 pinctrl-names    1806                                 pinctrl-names = "default";
1981                                 pinctrl-0 = <    1807                                 pinctrl-0 = <&qup_uart11_default>;
1982                                 interrupts =     1808                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983                                 power-domains    1809                                 power-domains = <&rpmhpd SDM845_CX>;
1984                                 operating-poi    1810                                 operating-points-v2 = <&qup_opp_table>;
1985                                 interconnects    1811                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986                                                  1812                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987                                 interconnect-    1813                                 interconnect-names = "qup-core", "qup-config";
1988                                 status = "dis    1814                                 status = "disabled";
1989                         };                       1815                         };
1990                                                  1816 
1991                         i2c12: i2c@a90000 {      1817                         i2c12: i2c@a90000 {
1992                                 compatible =     1818                                 compatible = "qcom,geni-i2c";
1993                                 reg = <0 0x00    1819                                 reg = <0 0x00a90000 0 0x4000>;
1994                                 clock-names =    1820                                 clock-names = "se";
1995                                 clocks = <&gc    1821                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996                                 pinctrl-names    1822                                 pinctrl-names = "default";
1997                                 pinctrl-0 = <    1823                                 pinctrl-0 = <&qup_i2c12_default>;
1998                                 interrupts =     1824                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999                                 #address-cell    1825                                 #address-cells = <1>;
2000                                 #size-cells =    1826                                 #size-cells = <0>;
2001                                 power-domains    1827                                 power-domains = <&rpmhpd SDM845_CX>;
2002                                 operating-poi    1828                                 operating-points-v2 = <&qup_opp_table>;
2003                                 interconnects    1829                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004                                                  1830                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005                                                  1831                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006                                 interconnect-    1832                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007                                 dmas = <&gpi_ << 
2008                                        <&gpi_ << 
2009                                 dma-names = " << 
2010                                 status = "dis    1833                                 status = "disabled";
2011                         };                       1834                         };
2012                                                  1835 
2013                         spi12: spi@a90000 {      1836                         spi12: spi@a90000 {
2014                                 compatible =     1837                                 compatible = "qcom,geni-spi";
2015                                 reg = <0 0x00    1838                                 reg = <0 0x00a90000 0 0x4000>;
2016                                 clock-names =    1839                                 clock-names = "se";
2017                                 clocks = <&gc    1840                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018                                 pinctrl-names    1841                                 pinctrl-names = "default";
2019                                 pinctrl-0 = <    1842                                 pinctrl-0 = <&qup_spi12_default>;
2020                                 interrupts =     1843                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021                                 #address-cell    1844                                 #address-cells = <1>;
2022                                 #size-cells =    1845                                 #size-cells = <0>;
2023                                 interconnects    1846                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024                                                  1847                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025                                 interconnect-    1848                                 interconnect-names = "qup-core", "qup-config";
2026                                 dmas = <&gpi_ << 
2027                                        <&gpi_ << 
2028                                 dma-names = " << 
2029                                 status = "dis    1849                                 status = "disabled";
2030                         };                       1850                         };
2031                                                  1851 
2032                         uart12: serial@a90000    1852                         uart12: serial@a90000 {
2033                                 compatible =     1853                                 compatible = "qcom,geni-uart";
2034                                 reg = <0 0x00    1854                                 reg = <0 0x00a90000 0 0x4000>;
2035                                 clock-names =    1855                                 clock-names = "se";
2036                                 clocks = <&gc    1856                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037                                 pinctrl-names    1857                                 pinctrl-names = "default";
2038                                 pinctrl-0 = <    1858                                 pinctrl-0 = <&qup_uart12_default>;
2039                                 interrupts =     1859                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040                                 power-domains    1860                                 power-domains = <&rpmhpd SDM845_CX>;
2041                                 operating-poi    1861                                 operating-points-v2 = <&qup_opp_table>;
2042                                 interconnects    1862                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043                                                  1863                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044                                 interconnect-    1864                                 interconnect-names = "qup-core", "qup-config";
2045                                 status = "dis    1865                                 status = "disabled";
2046                         };                       1866                         };
2047                                                  1867 
2048                         i2c13: i2c@a94000 {      1868                         i2c13: i2c@a94000 {
2049                                 compatible =     1869                                 compatible = "qcom,geni-i2c";
2050                                 reg = <0 0x00    1870                                 reg = <0 0x00a94000 0 0x4000>;
2051                                 clock-names =    1871                                 clock-names = "se";
2052                                 clocks = <&gc    1872                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053                                 pinctrl-names    1873                                 pinctrl-names = "default";
2054                                 pinctrl-0 = <    1874                                 pinctrl-0 = <&qup_i2c13_default>;
2055                                 interrupts =     1875                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056                                 #address-cell    1876                                 #address-cells = <1>;
2057                                 #size-cells =    1877                                 #size-cells = <0>;
2058                                 power-domains    1878                                 power-domains = <&rpmhpd SDM845_CX>;
2059                                 operating-poi    1879                                 operating-points-v2 = <&qup_opp_table>;
2060                                 interconnects    1880                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061                                                  1881                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062                                                  1882                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063                                 interconnect-    1883                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064                                 dmas = <&gpi_ << 
2065                                        <&gpi_ << 
2066                                 dma-names = " << 
2067                                 status = "dis    1884                                 status = "disabled";
2068                         };                       1885                         };
2069                                                  1886 
2070                         spi13: spi@a94000 {      1887                         spi13: spi@a94000 {
2071                                 compatible =     1888                                 compatible = "qcom,geni-spi";
2072                                 reg = <0 0x00    1889                                 reg = <0 0x00a94000 0 0x4000>;
2073                                 clock-names =    1890                                 clock-names = "se";
2074                                 clocks = <&gc    1891                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075                                 pinctrl-names    1892                                 pinctrl-names = "default";
2076                                 pinctrl-0 = <    1893                                 pinctrl-0 = <&qup_spi13_default>;
2077                                 interrupts =     1894                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078                                 #address-cell    1895                                 #address-cells = <1>;
2079                                 #size-cells =    1896                                 #size-cells = <0>;
2080                                 interconnects    1897                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081                                                  1898                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082                                 interconnect-    1899                                 interconnect-names = "qup-core", "qup-config";
2083                                 dmas = <&gpi_ << 
2084                                        <&gpi_ << 
2085                                 dma-names = " << 
2086                                 status = "dis    1900                                 status = "disabled";
2087                         };                       1901                         };
2088                                                  1902 
2089                         uart13: serial@a94000    1903                         uart13: serial@a94000 {
2090                                 compatible =     1904                                 compatible = "qcom,geni-uart";
2091                                 reg = <0 0x00    1905                                 reg = <0 0x00a94000 0 0x4000>;
2092                                 clock-names =    1906                                 clock-names = "se";
2093                                 clocks = <&gc    1907                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094                                 pinctrl-names    1908                                 pinctrl-names = "default";
2095                                 pinctrl-0 = <    1909                                 pinctrl-0 = <&qup_uart13_default>;
2096                                 interrupts =     1910                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097                                 power-domains    1911                                 power-domains = <&rpmhpd SDM845_CX>;
2098                                 operating-poi    1912                                 operating-points-v2 = <&qup_opp_table>;
2099                                 interconnects    1913                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100                                                  1914                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101                                 interconnect-    1915                                 interconnect-names = "qup-core", "qup-config";
2102                                 status = "dis    1916                                 status = "disabled";
2103                         };                       1917                         };
2104                                                  1918 
2105                         i2c14: i2c@a98000 {      1919                         i2c14: i2c@a98000 {
2106                                 compatible =     1920                                 compatible = "qcom,geni-i2c";
2107                                 reg = <0 0x00    1921                                 reg = <0 0x00a98000 0 0x4000>;
2108                                 clock-names =    1922                                 clock-names = "se";
2109                                 clocks = <&gc    1923                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110                                 pinctrl-names    1924                                 pinctrl-names = "default";
2111                                 pinctrl-0 = <    1925                                 pinctrl-0 = <&qup_i2c14_default>;
2112                                 interrupts =     1926                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113                                 #address-cell    1927                                 #address-cells = <1>;
2114                                 #size-cells =    1928                                 #size-cells = <0>;
2115                                 power-domains    1929                                 power-domains = <&rpmhpd SDM845_CX>;
2116                                 operating-poi    1930                                 operating-points-v2 = <&qup_opp_table>;
2117                                 interconnects    1931                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118                                                  1932                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119                                                  1933                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120                                 interconnect-    1934                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121                                 dmas = <&gpi_ << 
2122                                        <&gpi_ << 
2123                                 dma-names = " << 
2124                                 status = "dis    1935                                 status = "disabled";
2125                         };                       1936                         };
2126                                                  1937 
2127                         spi14: spi@a98000 {      1938                         spi14: spi@a98000 {
2128                                 compatible =     1939                                 compatible = "qcom,geni-spi";
2129                                 reg = <0 0x00    1940                                 reg = <0 0x00a98000 0 0x4000>;
2130                                 clock-names =    1941                                 clock-names = "se";
2131                                 clocks = <&gc    1942                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132                                 pinctrl-names    1943                                 pinctrl-names = "default";
2133                                 pinctrl-0 = <    1944                                 pinctrl-0 = <&qup_spi14_default>;
2134                                 interrupts =     1945                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135                                 #address-cell    1946                                 #address-cells = <1>;
2136                                 #size-cells =    1947                                 #size-cells = <0>;
2137                                 interconnects    1948                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138                                                  1949                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139                                 interconnect-    1950                                 interconnect-names = "qup-core", "qup-config";
2140                                 dmas = <&gpi_ << 
2141                                        <&gpi_ << 
2142                                 dma-names = " << 
2143                                 status = "dis    1951                                 status = "disabled";
2144                         };                       1952                         };
2145                                                  1953 
2146                         uart14: serial@a98000    1954                         uart14: serial@a98000 {
2147                                 compatible =     1955                                 compatible = "qcom,geni-uart";
2148                                 reg = <0 0x00    1956                                 reg = <0 0x00a98000 0 0x4000>;
2149                                 clock-names =    1957                                 clock-names = "se";
2150                                 clocks = <&gc    1958                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151                                 pinctrl-names    1959                                 pinctrl-names = "default";
2152                                 pinctrl-0 = <    1960                                 pinctrl-0 = <&qup_uart14_default>;
2153                                 interrupts =     1961                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154                                 power-domains    1962                                 power-domains = <&rpmhpd SDM845_CX>;
2155                                 operating-poi    1963                                 operating-points-v2 = <&qup_opp_table>;
2156                                 interconnects    1964                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157                                                  1965                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158                                 interconnect-    1966                                 interconnect-names = "qup-core", "qup-config";
2159                                 status = "dis    1967                                 status = "disabled";
2160                         };                       1968                         };
2161                                                  1969 
2162                         i2c15: i2c@a9c000 {      1970                         i2c15: i2c@a9c000 {
2163                                 compatible =     1971                                 compatible = "qcom,geni-i2c";
2164                                 reg = <0 0x00    1972                                 reg = <0 0x00a9c000 0 0x4000>;
2165                                 clock-names =    1973                                 clock-names = "se";
2166                                 clocks = <&gc    1974                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167                                 pinctrl-names    1975                                 pinctrl-names = "default";
2168                                 pinctrl-0 = <    1976                                 pinctrl-0 = <&qup_i2c15_default>;
2169                                 interrupts =     1977                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170                                 #address-cell    1978                                 #address-cells = <1>;
2171                                 #size-cells =    1979                                 #size-cells = <0>;
2172                                 power-domains    1980                                 power-domains = <&rpmhpd SDM845_CX>;
2173                                 operating-poi    1981                                 operating-points-v2 = <&qup_opp_table>;
2174                                 status = "dis    1982                                 status = "disabled";
2175                                 interconnects    1983                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176                                                  1984                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177                                                  1985                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178                                 interconnect-    1986                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179                                 dmas = <&gpi_ << 
2180                                        <&gpi_ << 
2181                                 dma-names = " << 
2182                         };                       1987                         };
2183                                                  1988 
2184                         spi15: spi@a9c000 {      1989                         spi15: spi@a9c000 {
2185                                 compatible =     1990                                 compatible = "qcom,geni-spi";
2186                                 reg = <0 0x00    1991                                 reg = <0 0x00a9c000 0 0x4000>;
2187                                 clock-names =    1992                                 clock-names = "se";
2188                                 clocks = <&gc    1993                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189                                 pinctrl-names    1994                                 pinctrl-names = "default";
2190                                 pinctrl-0 = <    1995                                 pinctrl-0 = <&qup_spi15_default>;
2191                                 interrupts =     1996                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192                                 #address-cell    1997                                 #address-cells = <1>;
2193                                 #size-cells =    1998                                 #size-cells = <0>;
2194                                 interconnects    1999                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195                                                  2000                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196                                 interconnect-    2001                                 interconnect-names = "qup-core", "qup-config";
2197                                 dmas = <&gpi_ << 
2198                                        <&gpi_ << 
2199                                 dma-names = " << 
2200                                 status = "dis    2002                                 status = "disabled";
2201                         };                       2003                         };
2202                                                  2004 
2203                         uart15: serial@a9c000    2005                         uart15: serial@a9c000 {
2204                                 compatible =     2006                                 compatible = "qcom,geni-uart";
2205                                 reg = <0 0x00    2007                                 reg = <0 0x00a9c000 0 0x4000>;
2206                                 clock-names =    2008                                 clock-names = "se";
2207                                 clocks = <&gc    2009                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208                                 pinctrl-names    2010                                 pinctrl-names = "default";
2209                                 pinctrl-0 = <    2011                                 pinctrl-0 = <&qup_uart15_default>;
2210                                 interrupts =     2012                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211                                 power-domains    2013                                 power-domains = <&rpmhpd SDM845_CX>;
2212                                 operating-poi    2014                                 operating-points-v2 = <&qup_opp_table>;
2213                                 interconnects    2015                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214                                                  2016                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215                                 interconnect-    2017                                 interconnect-names = "qup-core", "qup-config";
2216                                 status = "dis    2018                                 status = "disabled";
2217                         };                       2019                         };
2218                 };                               2020                 };
2219                                                  2021 
2220                 llcc: system-cache-controller    2022                 llcc: system-cache-controller@1100000 {
2221                         compatible = "qcom,sd    2023                         compatible = "qcom,sdm845-llcc";
2222                         reg = <0 0x01100000 0 !! 2024                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223                               <0 0x01200000 0 !! 2025                         reg-names = "llcc_base", "llcc_broadcast_base";
2224                               <0 0x01300000 0 << 
2225                         reg-names = "llcc0_ba << 
2226                                     "llcc3_ba << 
2227                         interrupts = <GIC_SPI    2026                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228                 };                               2027                 };
2229                                                  2028 
2230                 dma@10a2000 {                 !! 2029                 pcie0: pci@1c00000 {
2231                         compatible = "qcom,sd !! 2030                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2232                         reg = <0x0 0x010a2000 << 
2233                               <0x0 0x010ae000 << 
2234                 };                            << 
2235                                               << 
2236                 pmu@114a000 {                 << 
2237                         compatible = "qcom,sd << 
2238                         reg = <0 0x0114a000 0 << 
2239                         interrupts = <GIC_SPI << 
2240                         interconnects = <&mem << 
2241                                               << 
2242                         operating-points-v2 = << 
2243                                               << 
2244                         llcc_bwmon_opp_table: << 
2245                                 compatible =  << 
2246                                               << 
2247                                 /*            << 
2248                                  * The interc << 
2249                                  * cpu4_opp_t << 
2250                                  * interconne << 
2251                                  * bandwidth  << 
2252                                  * bus width: << 
2253                                  * kernel.    << 
2254                                  */           << 
2255                                 opp-0 {       << 
2256                                         opp-p << 
2257                                 };            << 
2258                                 opp-1 {       << 
2259                                         opp-p << 
2260                                 };            << 
2261                                 opp-2 {       << 
2262                                         opp-p << 
2263                                 };            << 
2264                                 opp-3 {       << 
2265                                         opp-p << 
2266                                 };            << 
2267                                 opp-4 {       << 
2268                                         opp-p << 
2269                                 };            << 
2270                         };                    << 
2271                 };                            << 
2272                                               << 
2273                 pmu@1436400 {                 << 
2274                         compatible = "qcom,sd << 
2275                         reg = <0 0x01436400 0 << 
2276                         interrupts = <GIC_SPI << 
2277                         interconnects = <&gla << 
2278                                               << 
2279                         operating-points-v2 = << 
2280                                               << 
2281                         cpu_bwmon_opp_table:  << 
2282                                 compatible =  << 
2283                                               << 
2284                                 /*            << 
2285                                  * The interc << 
2286                                  * cpu4_opp_t << 
2287                                  * interconne << 
2288                                  * from bandw << 
2289                                  * (qcom,core << 
2290                                  * from msm-4 << 
2291                                  */           << 
2292                                 opp-0 {       << 
2293                                         opp-p << 
2294                                 };            << 
2295                                 opp-1 {       << 
2296                                         opp-p << 
2297                                 };            << 
2298                                 opp-2 {       << 
2299                                         opp-p << 
2300                                 };            << 
2301                                 opp-3 {       << 
2302                                         opp-p << 
2303                                 };            << 
2304                                 opp-4 {       << 
2305                                         opp-p << 
2306                                 };            << 
2307                         };                    << 
2308                 };                            << 
2309                                               << 
2310                 pcie0: pcie@1c00000 {         << 
2311                         compatible = "qcom,pc << 
2312                         reg = <0 0x01c00000 0    2031                         reg = <0 0x01c00000 0 0x2000>,
2313                               <0 0x60000000 0    2032                               <0 0x60000000 0 0xf1d>,
2314                               <0 0x60000f20 0    2033                               <0 0x60000f20 0 0xa8>,
2315                               <0 0x60100000 0 !! 2034                               <0 0x60100000 0 0x100000>;
2316                               <0 0x01c07000 0 !! 2035                         reg-names = "parf", "dbi", "elbi", "config";
2317                         reg-names = "parf", " << 
2318                         device_type = "pci";     2036                         device_type = "pci";
2319                         linux,pci-domain = <0    2037                         linux,pci-domain = <0>;
2320                         bus-range = <0x00 0xf    2038                         bus-range = <0x00 0xff>;
2321                         num-lanes = <1>;         2039                         num-lanes = <1>;
2322                                                  2040 
2323                         #address-cells = <3>;    2041                         #address-cells = <3>;
2324                         #size-cells = <2>;       2042                         #size-cells = <2>;
2325                                                  2043 
2326                         ranges = <0x01000000  !! 2044                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327                                  <0x02000000  !! 2045                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328                                                  2046 
2329                         interrupts = <GIC_SPI    2047                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330                         interrupt-names = "ms    2048                         interrupt-names = "msi";
2331                         #interrupt-cells = <1    2049                         #interrupt-cells = <1>;
2332                         interrupt-map-mask =     2050                         interrupt-map-mask = <0 0 0 0x7>;
2333                         interrupt-map = <0 0     2051                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334                                         <0 0     2052                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335                                         <0 0     2053                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336                                         <0 0     2054                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337                                                  2055 
2338                         clocks = <&gcc GCC_PC    2056                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339                                  <&gcc GCC_PC    2057                                  <&gcc GCC_PCIE_0_AUX_CLK>,
2340                                  <&gcc GCC_PC    2058                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341                                  <&gcc GCC_PC    2059                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342                                  <&gcc GCC_PC    2060                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343                                  <&gcc GCC_PC    2061                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344                                  <&gcc GCC_AG    2062                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345                         clock-names = "pipe",    2063                         clock-names = "pipe",
2346                                       "aux",     2064                                       "aux",
2347                                       "cfg",     2065                                       "cfg",
2348                                       "bus_ma    2066                                       "bus_master",
2349                                       "bus_sl    2067                                       "bus_slave",
2350                                       "slave_    2068                                       "slave_q2a",
2351                                       "tbu";     2069                                       "tbu";
2352                                                  2070 
                                                   >> 2071                         iommus = <&apps_smmu 0x1c10 0xf>;
2353                         iommu-map = <0x0   &a    2072                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
2354                                     <0x100 &a    2073                                     <0x100 &apps_smmu 0x1c11 0x1>,
2355                                     <0x200 &a    2074                                     <0x200 &apps_smmu 0x1c12 0x1>,
2356                                     <0x300 &a    2075                                     <0x300 &apps_smmu 0x1c13 0x1>,
2357                                     <0x400 &a    2076                                     <0x400 &apps_smmu 0x1c14 0x1>,
2358                                     <0x500 &a    2077                                     <0x500 &apps_smmu 0x1c15 0x1>,
2359                                     <0x600 &a    2078                                     <0x600 &apps_smmu 0x1c16 0x1>,
2360                                     <0x700 &a    2079                                     <0x700 &apps_smmu 0x1c17 0x1>,
2361                                     <0x800 &a    2080                                     <0x800 &apps_smmu 0x1c18 0x1>,
2362                                     <0x900 &a    2081                                     <0x900 &apps_smmu 0x1c19 0x1>,
2363                                     <0xa00 &a    2082                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
2364                                     <0xb00 &a    2083                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
2365                                     <0xc00 &a    2084                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
2366                                     <0xd00 &a    2085                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
2367                                     <0xe00 &a    2086                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
2368                                     <0xf00 &a    2087                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
2369                                                  2088 
2370                         resets = <&gcc GCC_PC    2089                         resets = <&gcc GCC_PCIE_0_BCR>;
2371                         reset-names = "pci";     2090                         reset-names = "pci";
2372                                                  2091 
2373                         power-domains = <&gcc    2092                         power-domains = <&gcc PCIE_0_GDSC>;
2374                                                  2093 
2375                         phys = <&pcie0_phy>;  !! 2094                         phys = <&pcie0_lane>;
2376                         phy-names = "pciephy"    2095                         phy-names = "pciephy";
2377                                                  2096 
2378                         status = "disabled";     2097                         status = "disabled";
2379                                               << 
2380                         pcie@0 {              << 
2381                                 device_type = << 
2382                                 reg = <0x0 0x << 
2383                                 bus-range = < << 
2384                                               << 
2385                                 #address-cell << 
2386                                 #size-cells = << 
2387                                 ranges;       << 
2388                         };                    << 
2389                 };                               2098                 };
2390                                                  2099 
2391                 pcie0_phy: phy@1c06000 {         2100                 pcie0_phy: phy@1c06000 {
2392                         compatible = "qcom,sd    2101                         compatible = "qcom,sdm845-qmp-pcie-phy";
2393                         reg = <0 0x01c06000 0 !! 2102                         reg = <0 0x01c06000 0 0x18c>;
                                                   >> 2103                         #address-cells = <2>;
                                                   >> 2104                         #size-cells = <2>;
                                                   >> 2105                         ranges;
2394                         clocks = <&gcc GCC_PC    2106                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395                                  <&gcc GCC_PC    2107                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396                                  <&gcc GCC_PC    2108                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397                                  <&gcc GCC_PC !! 2109                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398                                  <&gcc GCC_PC !! 2110                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399                         clock-names = "aux",  << 
2400                                       "cfg_ah << 
2401                                       "ref",  << 
2402                                       "refgen << 
2403                                       "pipe"; << 
2404                                               << 
2405                         clock-output-names =  << 
2406                         #clock-cells = <0>;   << 
2407                                               << 
2408                         #phy-cells = <0>;     << 
2409                                                  2111 
2410                         resets = <&gcc GCC_PC    2112                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411                         reset-names = "phy";     2113                         reset-names = "phy";
2412                                                  2114 
2413                         assigned-clocks = <&g    2115                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414                         assigned-clock-rates     2116                         assigned-clock-rates = <100000000>;
2415                                                  2117 
2416                         status = "disabled";     2118                         status = "disabled";
                                                   >> 2119 
                                                   >> 2120                         pcie0_lane: phy@1c06200 {
                                                   >> 2121                                 reg = <0 0x01c06200 0 0x128>,
                                                   >> 2122                                       <0 0x01c06400 0 0x1fc>,
                                                   >> 2123                                       <0 0x01c06800 0 0x218>,
                                                   >> 2124                                       <0 0x01c06600 0 0x70>;
                                                   >> 2125                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
                                                   >> 2126                                 clock-names = "pipe0";
                                                   >> 2127 
                                                   >> 2128                                 #clock-cells = <0>;
                                                   >> 2129                                 #phy-cells = <0>;
                                                   >> 2130                                 clock-output-names = "pcie_0_pipe_clk";
                                                   >> 2131                         };
2417                 };                               2132                 };
2418                                                  2133 
2419                 pcie1: pcie@1c08000 {         !! 2134                 pcie1: pci@1c08000 {
2420                         compatible = "qcom,pc !! 2135                         compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2421                         reg = <0 0x01c08000 0    2136                         reg = <0 0x01c08000 0 0x2000>,
2422                               <0 0x40000000 0    2137                               <0 0x40000000 0 0xf1d>,
2423                               <0 0x40000f20 0    2138                               <0 0x40000f20 0 0xa8>,
2424                               <0 0x40100000 0 !! 2139                               <0 0x40100000 0 0x100000>;
2425                               <0 0x01c0c000 0 !! 2140                         reg-names = "parf", "dbi", "elbi", "config";
2426                         reg-names = "parf", " << 
2427                         device_type = "pci";     2141                         device_type = "pci";
2428                         linux,pci-domain = <1    2142                         linux,pci-domain = <1>;
2429                         bus-range = <0x00 0xf    2143                         bus-range = <0x00 0xff>;
2430                         num-lanes = <1>;         2144                         num-lanes = <1>;
2431                                                  2145 
2432                         #address-cells = <3>;    2146                         #address-cells = <3>;
2433                         #size-cells = <2>;       2147                         #size-cells = <2>;
2434                                                  2148 
2435                         ranges = <0x01000000  !! 2149                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436                                  <0x02000000     2150                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437                                                  2151 
2438                         interrupts = <GIC_SPI    2152                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439                         interrupt-names = "ms    2153                         interrupt-names = "msi";
2440                         #interrupt-cells = <1    2154                         #interrupt-cells = <1>;
2441                         interrupt-map-mask =     2155                         interrupt-map-mask = <0 0 0 0x7>;
2442                         interrupt-map = <0 0     2156                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443                                         <0 0     2157                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444                                         <0 0     2158                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445                                         <0 0     2159                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446                                                  2160 
2447                         clocks = <&gcc GCC_PC    2161                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448                                  <&gcc GCC_PC    2162                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2449                                  <&gcc GCC_PC    2163                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450                                  <&gcc GCC_PC    2164                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451                                  <&gcc GCC_PC    2165                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452                                  <&gcc GCC_PC    2166                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453                                  <&gcc GCC_PC    2167                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454                                  <&gcc GCC_AG    2168                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455                         clock-names = "pipe",    2169                         clock-names = "pipe",
2456                                       "aux",     2170                                       "aux",
2457                                       "cfg",     2171                                       "cfg",
2458                                       "bus_ma    2172                                       "bus_master",
2459                                       "bus_sl    2173                                       "bus_slave",
2460                                       "slave_    2174                                       "slave_q2a",
2461                                       "ref",     2175                                       "ref",
2462                                       "tbu";     2176                                       "tbu";
2463                                                  2177 
2464                         assigned-clocks = <&g    2178                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465                         assigned-clock-rates     2179                         assigned-clock-rates = <19200000>;
2466                                                  2180 
                                                   >> 2181                         iommus = <&apps_smmu 0x1c00 0xf>;
2467                         iommu-map = <0x0   &a    2182                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2468                                     <0x100 &a    2183                                     <0x100 &apps_smmu 0x1c01 0x1>,
2469                                     <0x200 &a    2184                                     <0x200 &apps_smmu 0x1c02 0x1>,
2470                                     <0x300 &a    2185                                     <0x300 &apps_smmu 0x1c03 0x1>,
2471                                     <0x400 &a    2186                                     <0x400 &apps_smmu 0x1c04 0x1>,
2472                                     <0x500 &a    2187                                     <0x500 &apps_smmu 0x1c05 0x1>,
2473                                     <0x600 &a    2188                                     <0x600 &apps_smmu 0x1c06 0x1>,
2474                                     <0x700 &a    2189                                     <0x700 &apps_smmu 0x1c07 0x1>,
2475                                     <0x800 &a    2190                                     <0x800 &apps_smmu 0x1c08 0x1>,
2476                                     <0x900 &a    2191                                     <0x900 &apps_smmu 0x1c09 0x1>,
2477                                     <0xa00 &a    2192                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
2478                                     <0xb00 &a    2193                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
2479                                     <0xc00 &a    2194                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
2480                                     <0xd00 &a    2195                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
2481                                     <0xe00 &a    2196                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
2482                                     <0xf00 &a    2197                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
2483                                                  2198 
2484                         resets = <&gcc GCC_PC    2199                         resets = <&gcc GCC_PCIE_1_BCR>;
2485                         reset-names = "pci";     2200                         reset-names = "pci";
2486                                                  2201 
2487                         power-domains = <&gcc    2202                         power-domains = <&gcc PCIE_1_GDSC>;
2488                                                  2203 
2489                         phys = <&pcie1_phy>;  !! 2204                         phys = <&pcie1_lane>;
2490                         phy-names = "pciephy"    2205                         phy-names = "pciephy";
2491                                                  2206 
2492                         status = "disabled";     2207                         status = "disabled";
2493                                               << 
2494                         pcie@0 {              << 
2495                                 device_type = << 
2496                                 reg = <0x0 0x << 
2497                                 bus-range = < << 
2498                                               << 
2499                                 #address-cell << 
2500                                 #size-cells = << 
2501                                 ranges;       << 
2502                         };                    << 
2503                 };                               2208                 };
2504                                                  2209 
2505                 pcie1_phy: phy@1c0a000 {         2210                 pcie1_phy: phy@1c0a000 {
2506                         compatible = "qcom,sd    2211                         compatible = "qcom,sdm845-qhp-pcie-phy";
2507                         reg = <0 0x01c0a000 0 !! 2212                         reg = <0 0x01c0a000 0 0x800>;
                                                   >> 2213                         #address-cells = <2>;
                                                   >> 2214                         #size-cells = <2>;
                                                   >> 2215                         ranges;
2508                         clocks = <&gcc GCC_PC    2216                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509                                  <&gcc GCC_PC    2217                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510                                  <&gcc GCC_PC    2218                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511                                  <&gcc GCC_PC !! 2219                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512                                  <&gcc GCC_PC !! 2220                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513                         clock-names = "aux",  << 
2514                                       "cfg_ah << 
2515                                       "ref",  << 
2516                                       "refgen << 
2517                                       "pipe"; << 
2518                                               << 
2519                         clock-output-names =  << 
2520                         #clock-cells = <0>;   << 
2521                                               << 
2522                         #phy-cells = <0>;     << 
2523                                                  2221 
2524                         resets = <&gcc GCC_PC    2222                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525                         reset-names = "phy";     2223                         reset-names = "phy";
2526                                                  2224 
2527                         assigned-clocks = <&g    2225                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528                         assigned-clock-rates     2226                         assigned-clock-rates = <100000000>;
2529                                                  2227 
2530                         status = "disabled";     2228                         status = "disabled";
                                                   >> 2229 
                                                   >> 2230                         pcie1_lane: phy@1c06200 {
                                                   >> 2231                                 reg = <0 0x01c0a800 0 0x800>,
                                                   >> 2232                                       <0 0x01c0a800 0 0x800>,
                                                   >> 2233                                       <0 0x01c0b800 0 0x400>;
                                                   >> 2234                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
                                                   >> 2235                                 clock-names = "pipe0";
                                                   >> 2236 
                                                   >> 2237                                 #clock-cells = <0>;
                                                   >> 2238                                 #phy-cells = <0>;
                                                   >> 2239                                 clock-output-names = "pcie_1_pipe_clk";
                                                   >> 2240                         };
2531                 };                               2241                 };
2532                                                  2242 
2533                 mem_noc: interconnect@1380000    2243                 mem_noc: interconnect@1380000 {
2534                         compatible = "qcom,sd    2244                         compatible = "qcom,sdm845-mem-noc";
2535                         reg = <0 0x01380000 0    2245                         reg = <0 0x01380000 0 0x27200>;
2536                         #interconnect-cells =    2246                         #interconnect-cells = <2>;
2537                         qcom,bcm-voters = <&a    2247                         qcom,bcm-voters = <&apps_bcm_voter>;
2538                 };                               2248                 };
2539                                                  2249 
2540                 dc_noc: interconnect@14e0000     2250                 dc_noc: interconnect@14e0000 {
2541                         compatible = "qcom,sd    2251                         compatible = "qcom,sdm845-dc-noc";
2542                         reg = <0 0x014e0000 0    2252                         reg = <0 0x014e0000 0 0x400>;
2543                         #interconnect-cells =    2253                         #interconnect-cells = <2>;
2544                         qcom,bcm-voters = <&a    2254                         qcom,bcm-voters = <&apps_bcm_voter>;
2545                 };                               2255                 };
2546                                                  2256 
2547                 config_noc: interconnect@1500    2257                 config_noc: interconnect@1500000 {
2548                         compatible = "qcom,sd    2258                         compatible = "qcom,sdm845-config-noc";
2549                         reg = <0 0x01500000 0    2259                         reg = <0 0x01500000 0 0x5080>;
2550                         #interconnect-cells =    2260                         #interconnect-cells = <2>;
2551                         qcom,bcm-voters = <&a    2261                         qcom,bcm-voters = <&apps_bcm_voter>;
2552                 };                               2262                 };
2553                                                  2263 
2554                 system_noc: interconnect@1620    2264                 system_noc: interconnect@1620000 {
2555                         compatible = "qcom,sd    2265                         compatible = "qcom,sdm845-system-noc";
2556                         reg = <0 0x01620000 0    2266                         reg = <0 0x01620000 0 0x18080>;
2557                         #interconnect-cells =    2267                         #interconnect-cells = <2>;
2558                         qcom,bcm-voters = <&a    2268                         qcom,bcm-voters = <&apps_bcm_voter>;
2559                 };                               2269                 };
2560                                                  2270 
2561                 aggre1_noc: interconnect@16e0    2271                 aggre1_noc: interconnect@16e0000 {
2562                         compatible = "qcom,sd    2272                         compatible = "qcom,sdm845-aggre1-noc";
2563                         reg = <0 0x016e0000 0    2273                         reg = <0 0x016e0000 0 0x15080>;
2564                         #interconnect-cells =    2274                         #interconnect-cells = <2>;
2565                         qcom,bcm-voters = <&a    2275                         qcom,bcm-voters = <&apps_bcm_voter>;
2566                 };                               2276                 };
2567                                                  2277 
2568                 aggre2_noc: interconnect@1700    2278                 aggre2_noc: interconnect@1700000 {
2569                         compatible = "qcom,sd    2279                         compatible = "qcom,sdm845-aggre2-noc";
2570                         reg = <0 0x01700000 0    2280                         reg = <0 0x01700000 0 0x1f300>;
2571                         #interconnect-cells =    2281                         #interconnect-cells = <2>;
2572                         qcom,bcm-voters = <&a    2282                         qcom,bcm-voters = <&apps_bcm_voter>;
2573                 };                               2283                 };
2574                                                  2284 
2575                 mmss_noc: interconnect@174000    2285                 mmss_noc: interconnect@1740000 {
2576                         compatible = "qcom,sd    2286                         compatible = "qcom,sdm845-mmss-noc";
2577                         reg = <0 0x01740000 0    2287                         reg = <0 0x01740000 0 0x1c100>;
2578                         #interconnect-cells =    2288                         #interconnect-cells = <2>;
2579                         qcom,bcm-voters = <&a    2289                         qcom,bcm-voters = <&apps_bcm_voter>;
2580                 };                               2290                 };
2581                                                  2291 
2582                 ufs_mem_hc: ufshc@1d84000 {      2292                 ufs_mem_hc: ufshc@1d84000 {
2583                         compatible = "qcom,sd    2293                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584                                      "jedec,u    2294                                      "jedec,ufs-2.0";
2585                         reg = <0 0x01d84000 0    2295                         reg = <0 0x01d84000 0 0x2500>,
2586                               <0 0x01d90000 0    2296                               <0 0x01d90000 0 0x8000>;
2587                         reg-names = "std", "i    2297                         reg-names = "std", "ice";
2588                         interrupts = <GIC_SPI    2298                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589                         phys = <&ufs_mem_phy> !! 2299                         phys = <&ufs_mem_phy_lanes>;
2590                         phy-names = "ufsphy";    2300                         phy-names = "ufsphy";
2591                         lanes-per-direction =    2301                         lanes-per-direction = <2>;
2592                         power-domains = <&gcc    2302                         power-domains = <&gcc UFS_PHY_GDSC>;
2593                         #reset-cells = <1>;      2303                         #reset-cells = <1>;
2594                         resets = <&gcc GCC_UF    2304                         resets = <&gcc GCC_UFS_PHY_BCR>;
2595                         reset-names = "rst";     2305                         reset-names = "rst";
2596                                                  2306 
2597                         iommus = <&apps_smmu     2307                         iommus = <&apps_smmu 0x100 0xf>;
2598                                                  2308 
2599                         clock-names =            2309                         clock-names =
2600                                 "core_clk",      2310                                 "core_clk",
2601                                 "bus_aggr_clk    2311                                 "bus_aggr_clk",
2602                                 "iface_clk",     2312                                 "iface_clk",
2603                                 "core_clk_uni    2313                                 "core_clk_unipro",
2604                                 "ref_clk",       2314                                 "ref_clk",
2605                                 "tx_lane0_syn    2315                                 "tx_lane0_sync_clk",
2606                                 "rx_lane0_syn    2316                                 "rx_lane0_sync_clk",
2607                                 "rx_lane1_syn    2317                                 "rx_lane1_sync_clk",
2608                                 "ice_core_clk    2318                                 "ice_core_clk";
2609                         clocks =                 2319                         clocks =
2610                                 <&gcc GCC_UFS    2320                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611                                 <&gcc GCC_AGG    2321                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612                                 <&gcc GCC_UFS    2322                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613                                 <&gcc GCC_UFS    2323                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614                                 <&rpmhcc RPMH    2324                                 <&rpmhcc RPMH_CXO_CLK>,
2615                                 <&gcc GCC_UFS    2325                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616                                 <&gcc GCC_UFS    2326                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617                                 <&gcc GCC_UFS    2327                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618                                 <&gcc GCC_UFS    2328                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619                                               !! 2329                         freq-table-hz =
2620                         operating-points-v2 = !! 2330                                 <50000000 200000000>,
2621                                               !! 2331                                 <0 0>,
2622                         interconnects = <&agg !! 2332                                 <0 0>,
2623                                         <&gla !! 2333                                 <37500000 150000000>,
2624                         interconnect-names =  !! 2334                                 <0 0>,
                                                   >> 2335                                 <0 0>,
                                                   >> 2336                                 <0 0>,
                                                   >> 2337                                 <0 0>,
                                                   >> 2338                                 <0 300000000>;
2625                                                  2339 
2626                         status = "disabled";     2340                         status = "disabled";
2627                                               << 
2628                         ufs_opp_table: opp-ta << 
2629                                 compatible =  << 
2630                                               << 
2631                                 opp-50000000  << 
2632                                         opp-h << 
2633                                               << 
2634                                               << 
2635                                               << 
2636                                               << 
2637                                               << 
2638                                               << 
2639                                               << 
2640                                               << 
2641                                         requi << 
2642                                 };            << 
2643                                               << 
2644                                 opp-200000000 << 
2645                                         opp-h << 
2646                                               << 
2647                                               << 
2648                                               << 
2649                                               << 
2650                                               << 
2651                                               << 
2652                                               << 
2653                                               << 
2654                                         requi << 
2655                                 };            << 
2656                         };                    << 
2657                 };                               2341                 };
2658                                                  2342 
2659                 ufs_mem_phy: phy@1d87000 {       2343                 ufs_mem_phy: phy@1d87000 {
2660                         compatible = "qcom,sd    2344                         compatible = "qcom,sdm845-qmp-ufs-phy";
2661                         reg = <0 0x01d87000 0 !! 2345                         reg = <0 0x01d87000 0 0x18c>;
2662                                               !! 2346                         #address-cells = <2>;
2663                         clocks = <&rpmhcc RPM !! 2347                         #size-cells = <2>;
2664                                  <&gcc GCC_UF !! 2348                         ranges;
2665                                  <&gcc GCC_UF << 
2666                         clock-names = "ref",     2349                         clock-names = "ref",
2667                                       "ref_au !! 2350                                       "ref_aux";
2668                                       "qref"; !! 2351                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669                                               !! 2352                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670                         power-domains = <&gcc << 
2671                                                  2353 
2672                         resets = <&ufs_mem_hc    2354                         resets = <&ufs_mem_hc 0>;
2673                         reset-names = "ufsphy    2355                         reset-names = "ufsphy";
2674                                               << 
2675                         #phy-cells = <0>;     << 
2676                         status = "disabled";     2356                         status = "disabled";
                                                   >> 2357 
                                                   >> 2358                         ufs_mem_phy_lanes: phy@1d87400 {
                                                   >> 2359                                 reg = <0 0x01d87400 0 0x108>,
                                                   >> 2360                                       <0 0x01d87600 0 0x1e0>,
                                                   >> 2361                                       <0 0x01d87c00 0 0x1dc>,
                                                   >> 2362                                       <0 0x01d87800 0 0x108>,
                                                   >> 2363                                       <0 0x01d87a00 0 0x1e0>;
                                                   >> 2364                                 #phy-cells = <0>;
                                                   >> 2365                         };
2677                 };                               2366                 };
2678                                                  2367 
2679                 cryptobam: dma-controller@1dc    2368                 cryptobam: dma-controller@1dc4000 {
2680                         compatible = "qcom,ba !! 2369                         compatible = "qcom,bam-v1.7.0";
2681                         reg = <0 0x01dc4000 0    2370                         reg = <0 0x01dc4000 0 0x24000>;
2682                         interrupts = <GIC_SPI    2371                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683                         clocks = <&rpmhcc RPM    2372                         clocks = <&rpmhcc RPMH_CE_CLK>;
2684                         clock-names = "bam_cl    2373                         clock-names = "bam_clk";
2685                         #dma-cells = <1>;        2374                         #dma-cells = <1>;
2686                         qcom,ee = <0>;           2375                         qcom,ee = <0>;
2687                         qcom,controlled-remot    2376                         qcom,controlled-remotely;
2688                         iommus = <&apps_smmu     2377                         iommus = <&apps_smmu 0x704 0x1>,
2689                                  <&apps_smmu     2378                                  <&apps_smmu 0x706 0x1>,
2690                                  <&apps_smmu     2379                                  <&apps_smmu 0x714 0x1>,
2691                                  <&apps_smmu     2380                                  <&apps_smmu 0x716 0x1>;
2692                 };                               2381                 };
2693                                                  2382 
2694                 crypto: crypto@1dfa000 {         2383                 crypto: crypto@1dfa000 {
2695                         compatible = "qcom,cr    2384                         compatible = "qcom,crypto-v5.4";
2696                         reg = <0 0x01dfa000 0    2385                         reg = <0 0x01dfa000 0 0x6000>;
2697                         clocks = <&gcc GCC_CE    2386                         clocks = <&gcc GCC_CE1_AHB_CLK>,
2698                                  <&gcc GCC_CE    2387                                  <&gcc GCC_CE1_AXI_CLK>,
2699                                  <&rpmhcc RPM    2388                                  <&rpmhcc RPMH_CE_CLK>;
2700                         clock-names = "iface"    2389                         clock-names = "iface", "bus", "core";
2701                         dmas = <&cryptobam 6>    2390                         dmas = <&cryptobam 6>, <&cryptobam 7>;
2702                         dma-names = "rx", "tx    2391                         dma-names = "rx", "tx";
2703                         iommus = <&apps_smmu     2392                         iommus = <&apps_smmu 0x704 0x1>,
2704                                  <&apps_smmu     2393                                  <&apps_smmu 0x706 0x1>,
2705                                  <&apps_smmu     2394                                  <&apps_smmu 0x714 0x1>,
2706                                  <&apps_smmu     2395                                  <&apps_smmu 0x716 0x1>;
2707                 };                               2396                 };
2708                                                  2397 
2709                 ipa: ipa@1e40000 {               2398                 ipa: ipa@1e40000 {
2710                         compatible = "qcom,sd    2399                         compatible = "qcom,sdm845-ipa";
2711                                                  2400 
2712                         iommus = <&apps_smmu     2401                         iommus = <&apps_smmu 0x720 0x0>,
2713                                  <&apps_smmu     2402                                  <&apps_smmu 0x722 0x0>;
2714                         reg = <0 0x01e40000 0 !! 2403                         reg = <0 0x1e40000 0 0x7000>,
2715                               <0 0x01e47000 0 !! 2404                               <0 0x1e47000 0 0x2000>,
2716                               <0 0x01e04000 0 !! 2405                               <0 0x1e04000 0 0x2c000>;
2717                         reg-names = "ipa-reg"    2406                         reg-names = "ipa-reg",
2718                                     "ipa-shar    2407                                     "ipa-shared",
2719                                     "gsi";       2408                                     "gsi";
2720                                                  2409 
2721                         interrupts-extended =    2410                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722                                                  2411                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723                                                  2412                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724                                                  2413                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725                         interrupt-names = "ip    2414                         interrupt-names = "ipa",
2726                                           "gs    2415                                           "gsi",
2727                                           "ip    2416                                           "ipa-clock-query",
2728                                           "ip    2417                                           "ipa-setup-ready";
2729                                                  2418 
2730                         clocks = <&rpmhcc RPM    2419                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2731                         clock-names = "core";    2420                         clock-names = "core";
2732                                                  2421 
2733                         interconnects = <&agg    2422                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734                                         <&agg    2423                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735                                         <&gla    2424                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736                         interconnect-names =     2425                         interconnect-names = "memory",
2737                                                  2426                                              "imem",
2738                                                  2427                                              "config";
2739                                                  2428 
2740                         qcom,smem-states = <&    2429                         qcom,smem-states = <&ipa_smp2p_out 0>,
2741                                            <&    2430                                            <&ipa_smp2p_out 1>;
2742                         qcom,smem-state-names    2431                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2743                                                  2432                                                 "ipa-clock-enabled";
2744                                                  2433 
2745                         status = "disabled";     2434                         status = "disabled";
2746                 };                               2435                 };
2747                                                  2436 
2748                 tcsr_mutex: hwlock@1f40000 {  !! 2437                 tcsr_mutex_regs: syscon@1f40000 {
2749                         compatible = "qcom,tc !! 2438                         compatible = "syscon";
2750                         reg = <0 0x01f40000 0 !! 2439                         reg = <0 0x01f40000 0 0x40000>;
2751                         #hwlock-cells = <1>;  << 
2752                 };                            << 
2753                                               << 
2754                 tcsr_regs_1: syscon@1f60000 { << 
2755                         compatible = "qcom,sd << 
2756                         reg = <0 0x01f60000 0 << 
2757                 };                               2440                 };
2758                                                  2441 
2759                 tlmm: pinctrl@3400000 {          2442                 tlmm: pinctrl@3400000 {
2760                         compatible = "qcom,sd    2443                         compatible = "qcom,sdm845-pinctrl";
2761                         reg = <0 0x03400000 0    2444                         reg = <0 0x03400000 0 0xc00000>;
2762                         interrupts = <GIC_SPI    2445                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763                         gpio-controller;         2446                         gpio-controller;
2764                         #gpio-cells = <2>;       2447                         #gpio-cells = <2>;
2765                         interrupt-controller;    2448                         interrupt-controller;
2766                         #interrupt-cells = <2    2449                         #interrupt-cells = <2>;
2767                         gpio-ranges = <&tlmm     2450                         gpio-ranges = <&tlmm 0 0 151>;
2768                         wakeup-parent = <&pdc    2451                         wakeup-parent = <&pdc_intc>;
2769                                                  2452 
2770                         cci0_default: cci0-de !! 2453                         cci0_default: cci0-default {
2771                                 /* SDA, SCL *    2454                                 /* SDA, SCL */
2772                                 pins = "gpio1    2455                                 pins = "gpio17", "gpio18";
2773                                 function = "c    2456                                 function = "cci_i2c";
2774                                                  2457 
2775                                 bias-pull-up;    2458                                 bias-pull-up;
2776                                 drive-strengt    2459                                 drive-strength = <2>; /* 2 mA */
2777                         };                       2460                         };
2778                                                  2461 
2779                         cci0_sleep: cci0-slee !! 2462                         cci0_sleep: cci0-sleep {
2780                                 /* SDA, SCL *    2463                                 /* SDA, SCL */
2781                                 pins = "gpio1    2464                                 pins = "gpio17", "gpio18";
2782                                 function = "c    2465                                 function = "cci_i2c";
2783                                                  2466 
2784                                 drive-strengt    2467                                 drive-strength = <2>; /* 2 mA */
2785                                 bias-pull-dow    2468                                 bias-pull-down;
2786                         };                       2469                         };
2787                                                  2470 
2788                         cci1_default: cci1-de !! 2471                         cci1_default: cci1-default {
2789                                 /* SDA, SCL *    2472                                 /* SDA, SCL */
2790                                 pins = "gpio1    2473                                 pins = "gpio19", "gpio20";
2791                                 function = "c    2474                                 function = "cci_i2c";
2792                                                  2475 
2793                                 bias-pull-up;    2476                                 bias-pull-up;
2794                                 drive-strengt    2477                                 drive-strength = <2>; /* 2 mA */
2795                         };                       2478                         };
2796                                                  2479 
2797                         cci1_sleep: cci1-slee !! 2480                         cci1_sleep: cci1-sleep {
2798                                 /* SDA, SCL *    2481                                 /* SDA, SCL */
2799                                 pins = "gpio1    2482                                 pins = "gpio19", "gpio20";
2800                                 function = "c    2483                                 function = "cci_i2c";
2801                                                  2484 
2802                                 drive-strengt    2485                                 drive-strength = <2>; /* 2 mA */
2803                                 bias-pull-dow    2486                                 bias-pull-down;
2804                         };                       2487                         };
2805                                                  2488 
2806                         qspi_clk: qspi-clk-st !! 2489                         qspi_clk: qspi-clk {
2807                                 pins = "gpio9 !! 2490                                 pinmux {
2808                                 function = "q !! 2491                                         pins = "gpio95";
2809                         };                    !! 2492                                         function = "qspi_clk";
2810                                               !! 2493                                 };
2811                         qspi_cs0: qspi-cs0-st << 
2812                                 pins = "gpio9 << 
2813                                 function = "q << 
2814                         };                       2494                         };
2815                                                  2495 
2816                         qspi_cs1: qspi-cs1-st !! 2496                         qspi_cs0: qspi-cs0 {
2817                                 pins = "gpio8 !! 2497                                 pinmux {
2818                                 function = "q !! 2498                                         pins = "gpio90";
                                                   >> 2499                                         function = "qspi_cs";
                                                   >> 2500                                 };
2819                         };                       2501                         };
2820                                                  2502 
2821                         qspi_data0: qspi-data !! 2503                         qspi_cs1: qspi-cs1 {
2822                                 pins = "gpio9 !! 2504                                 pinmux {
2823                                 function = "q !! 2505                                         pins = "gpio89";
                                                   >> 2506                                         function = "qspi_cs";
                                                   >> 2507                                 };
2824                         };                       2508                         };
2825                                                  2509 
2826                         qspi_data1: qspi-data !! 2510                         qspi_data01: qspi-data01 {
2827                                 pins = "gpio9 !! 2511                                 pinmux-data {
2828                                 function = "q !! 2512                                         pins = "gpio91", "gpio92";
                                                   >> 2513                                         function = "qspi_data";
                                                   >> 2514                                 };
2829                         };                       2515                         };
2830                                                  2516 
2831                         qspi_data23: qspi-dat !! 2517                         qspi_data12: qspi-data12 {
2832                                 pins = "gpio9 !! 2518                                 pinmux-data {
2833                                 function = "q !! 2519                                         pins = "gpio93", "gpio94";
                                                   >> 2520                                         function = "qspi_data";
                                                   >> 2521                                 };
2834                         };                       2522                         };
2835                                                  2523 
2836                         qup_i2c0_default: qup !! 2524                         qup_i2c0_default: qup-i2c0-default {
2837                                 pins = "gpio0 !! 2525                                 pinmux {
2838                                 function = "q !! 2526                                         pins = "gpio0", "gpio1";
                                                   >> 2527                                         function = "qup0";
                                                   >> 2528                                 };
2839                         };                       2529                         };
2840                                                  2530 
2841                         qup_i2c1_default: qup !! 2531                         qup_i2c1_default: qup-i2c1-default {
2842                                 pins = "gpio1 !! 2532                                 pinmux {
2843                                 function = "q !! 2533                                         pins = "gpio17", "gpio18";
                                                   >> 2534                                         function = "qup1";
                                                   >> 2535                                 };
2844                         };                       2536                         };
2845                                                  2537 
2846                         qup_i2c2_default: qup !! 2538                         qup_i2c2_default: qup-i2c2-default {
2847                                 pins = "gpio2 !! 2539                                 pinmux {
2848                                 function = "q !! 2540                                         pins = "gpio27", "gpio28";
                                                   >> 2541                                         function = "qup2";
                                                   >> 2542                                 };
2849                         };                       2543                         };
2850                                                  2544 
2851                         qup_i2c3_default: qup !! 2545                         qup_i2c3_default: qup-i2c3-default {
2852                                 pins = "gpio4 !! 2546                                 pinmux {
2853                                 function = "q !! 2547                                         pins = "gpio41", "gpio42";
                                                   >> 2548                                         function = "qup3";
                                                   >> 2549                                 };
2854                         };                       2550                         };
2855                                                  2551 
2856                         qup_i2c4_default: qup !! 2552                         qup_i2c4_default: qup-i2c4-default {
2857                                 pins = "gpio8 !! 2553                                 pinmux {
2858                                 function = "q !! 2554                                         pins = "gpio89", "gpio90";
                                                   >> 2555                                         function = "qup4";
                                                   >> 2556                                 };
2859                         };                       2557                         };
2860                                                  2558 
2861                         qup_i2c5_default: qup !! 2559                         qup_i2c5_default: qup-i2c5-default {
2862                                 pins = "gpio8 !! 2560                                 pinmux {
2863                                 function = "q !! 2561                                         pins = "gpio85", "gpio86";
                                                   >> 2562                                         function = "qup5";
                                                   >> 2563                                 };
2864                         };                       2564                         };
2865                                                  2565 
2866                         qup_i2c6_default: qup !! 2566                         qup_i2c6_default: qup-i2c6-default {
2867                                 pins = "gpio4 !! 2567                                 pinmux {
2868                                 function = "q !! 2568                                         pins = "gpio45", "gpio46";
                                                   >> 2569                                         function = "qup6";
                                                   >> 2570                                 };
2869                         };                       2571                         };
2870                                                  2572 
2871                         qup_i2c7_default: qup !! 2573                         qup_i2c7_default: qup-i2c7-default {
2872                                 pins = "gpio9 !! 2574                                 pinmux {
2873                                 function = "q !! 2575                                         pins = "gpio93", "gpio94";
                                                   >> 2576                                         function = "qup7";
                                                   >> 2577                                 };
2874                         };                       2578                         };
2875                                                  2579 
2876                         qup_i2c8_default: qup !! 2580                         qup_i2c8_default: qup-i2c8-default {
2877                                 pins = "gpio6 !! 2581                                 pinmux {
2878                                 function = "q !! 2582                                         pins = "gpio65", "gpio66";
                                                   >> 2583                                         function = "qup8";
                                                   >> 2584                                 };
2879                         };                       2585                         };
2880                                                  2586 
2881                         qup_i2c9_default: qup !! 2587                         qup_i2c9_default: qup-i2c9-default {
2882                                 pins = "gpio6 !! 2588                                 pinmux {
2883                                 function = "q !! 2589                                         pins = "gpio6", "gpio7";
                                                   >> 2590                                         function = "qup9";
                                                   >> 2591                                 };
2884                         };                       2592                         };
2885                                                  2593 
2886                         qup_i2c10_default: qu !! 2594                         qup_i2c10_default: qup-i2c10-default {
2887                                 pins = "gpio5 !! 2595                                 pinmux {
2888                                 function = "q !! 2596                                         pins = "gpio55", "gpio56";
                                                   >> 2597                                         function = "qup10";
                                                   >> 2598                                 };
2889                         };                       2599                         };
2890                                                  2600 
2891                         qup_i2c11_default: qu !! 2601                         qup_i2c11_default: qup-i2c11-default {
2892                                 pins = "gpio3 !! 2602                                 pinmux {
2893                                 function = "q !! 2603                                         pins = "gpio31", "gpio32";
                                                   >> 2604                                         function = "qup11";
                                                   >> 2605                                 };
2894                         };                       2606                         };
2895                                                  2607 
2896                         qup_i2c12_default: qu !! 2608                         qup_i2c12_default: qup-i2c12-default {
2897                                 pins = "gpio4 !! 2609                                 pinmux {
2898                                 function = "q !! 2610                                         pins = "gpio49", "gpio50";
                                                   >> 2611                                         function = "qup12";
                                                   >> 2612                                 };
2899                         };                       2613                         };
2900                                                  2614 
2901                         qup_i2c13_default: qu !! 2615                         qup_i2c13_default: qup-i2c13-default {
2902                                 pins = "gpio1 !! 2616                                 pinmux {
2903                                 function = "q !! 2617                                         pins = "gpio105", "gpio106";
                                                   >> 2618                                         function = "qup13";
                                                   >> 2619                                 };
2904                         };                       2620                         };
2905                                                  2621 
2906                         qup_i2c14_default: qu !! 2622                         qup_i2c14_default: qup-i2c14-default {
2907                                 pins = "gpio3 !! 2623                                 pinmux {
2908                                 function = "q !! 2624                                         pins = "gpio33", "gpio34";
                                                   >> 2625                                         function = "qup14";
                                                   >> 2626                                 };
2909                         };                       2627                         };
2910                                                  2628 
2911                         qup_i2c15_default: qu !! 2629                         qup_i2c15_default: qup-i2c15-default {
2912                                 pins = "gpio8 !! 2630                                 pinmux {
2913                                 function = "q !! 2631                                         pins = "gpio81", "gpio82";
                                                   >> 2632                                         function = "qup15";
                                                   >> 2633                                 };
2914                         };                       2634                         };
2915                                                  2635 
2916                         qup_spi0_default: qup !! 2636                         qup_spi0_default: qup-spi0-default {
2917                                 pins = "gpio0 !! 2637                                 pinmux {
2918                                 function = "q !! 2638                                         pins = "gpio0", "gpio1",
2919                         };                    !! 2639                                                "gpio2", "gpio3";
                                                   >> 2640                                         function = "qup0";
                                                   >> 2641                                 };
2920                                                  2642 
2921                         qup_spi1_default: qup !! 2643                                 config {
2922                                 pins = "gpio1 !! 2644                                         pins = "gpio0", "gpio1",
2923                                 function = "q !! 2645                                                "gpio2", "gpio3";
                                                   >> 2646                                         drive-strength = <6>;
                                                   >> 2647                                         bias-disable;
                                                   >> 2648                                 };
2924                         };                       2649                         };
2925                                                  2650 
2926                         qup_spi2_default: qup !! 2651                         qup_spi1_default: qup-spi1-default {
2927                                 pins = "gpio2 !! 2652                                 pinmux {
2928                                 function = "q !! 2653                                         pins = "gpio17", "gpio18",
                                                   >> 2654                                                "gpio19", "gpio20";
                                                   >> 2655                                         function = "qup1";
                                                   >> 2656                                 };
2929                         };                       2657                         };
2930                                                  2658 
2931                         qup_spi3_default: qup !! 2659                         qup_spi2_default: qup-spi2-default {
2932                                 pins = "gpio4 !! 2660                                 pinmux {
2933                                 function = "q !! 2661                                         pins = "gpio27", "gpio28",
                                                   >> 2662                                                "gpio29", "gpio30";
                                                   >> 2663                                         function = "qup2";
                                                   >> 2664                                 };
2934                         };                       2665                         };
2935                                                  2666 
2936                         qup_spi4_default: qup !! 2667                         qup_spi3_default: qup-spi3-default {
2937                                 pins = "gpio8 !! 2668                                 pinmux {
2938                                 function = "q !! 2669                                         pins = "gpio41", "gpio42",
                                                   >> 2670                                                "gpio43", "gpio44";
                                                   >> 2671                                         function = "qup3";
                                                   >> 2672                                 };
2939                         };                       2673                         };
2940                                                  2674 
2941                         qup_spi5_default: qup !! 2675                         qup_spi4_default: qup-spi4-default {
2942                                 pins = "gpio8 !! 2676                                 pinmux {
2943                                 function = "q !! 2677                                         pins = "gpio89", "gpio90",
                                                   >> 2678                                                "gpio91", "gpio92";
                                                   >> 2679                                         function = "qup4";
                                                   >> 2680                                 };
2944                         };                       2681                         };
2945                                                  2682 
2946                         qup_spi6_default: qup !! 2683                         qup_spi5_default: qup-spi5-default {
2947                                 pins = "gpio4 !! 2684                                 pinmux {
2948                                 function = "q !! 2685                                         pins = "gpio85", "gpio86",
                                                   >> 2686                                                "gpio87", "gpio88";
                                                   >> 2687                                         function = "qup5";
                                                   >> 2688                                 };
2949                         };                       2689                         };
2950                                                  2690 
2951                         qup_spi7_default: qup !! 2691                         qup_spi6_default: qup-spi6-default {
2952                                 pins = "gpio9 !! 2692                                 pinmux {
2953                                 function = "q !! 2693                                         pins = "gpio45", "gpio46",
                                                   >> 2694                                                "gpio47", "gpio48";
                                                   >> 2695                                         function = "qup6";
                                                   >> 2696                                 };
2954                         };                       2697                         };
2955                                                  2698 
2956                         qup_spi8_default: qup !! 2699                         qup_spi7_default: qup-spi7-default {
2957                                 pins = "gpio6 !! 2700                                 pinmux {
2958                                 function = "q !! 2701                                         pins = "gpio93", "gpio94",
                                                   >> 2702                                                "gpio95", "gpio96";
                                                   >> 2703                                         function = "qup7";
                                                   >> 2704                                 };
2959                         };                       2705                         };
2960                                                  2706 
2961                         qup_spi9_default: qup !! 2707                         qup_spi8_default: qup-spi8-default {
2962                                 pins = "gpio6 !! 2708                                 pinmux {
2963                                 function = "q !! 2709                                         pins = "gpio65", "gpio66",
                                                   >> 2710                                                "gpio67", "gpio68";
                                                   >> 2711                                         function = "qup8";
                                                   >> 2712                                 };
2964                         };                       2713                         };
2965                                                  2714 
2966                         qup_spi10_default: qu !! 2715                         qup_spi9_default: qup-spi9-default {
2967                                 pins = "gpio5 !! 2716                                 pinmux {
2968                                 function = "q !! 2717                                         pins = "gpio6", "gpio7",
                                                   >> 2718                                                "gpio4", "gpio5";
                                                   >> 2719                                         function = "qup9";
                                                   >> 2720                                 };
2969                         };                       2721                         };
2970                                                  2722 
2971                         qup_spi11_default: qu !! 2723                         qup_spi10_default: qup-spi10-default {
2972                                 pins = "gpio3 !! 2724                                 pinmux {
2973                                 function = "q !! 2725                                         pins = "gpio55", "gpio56",
                                                   >> 2726                                                "gpio53", "gpio54";
                                                   >> 2727                                         function = "qup10";
                                                   >> 2728                                 };
2974                         };                       2729                         };
2975                                                  2730 
2976                         qup_spi12_default: qu !! 2731                         qup_spi11_default: qup-spi11-default {
2977                                 pins = "gpio4 !! 2732                                 pinmux {
2978                                 function = "q !! 2733                                         pins = "gpio31", "gpio32",
                                                   >> 2734                                                "gpio33", "gpio34";
                                                   >> 2735                                         function = "qup11";
                                                   >> 2736                                 };
2979                         };                       2737                         };
2980                                                  2738 
2981                         qup_spi13_default: qu !! 2739                         qup_spi12_default: qup-spi12-default {
2982                                 pins = "gpio1 !! 2740                                 pinmux {
2983                                 function = "q !! 2741                                         pins = "gpio49", "gpio50",
                                                   >> 2742                                                "gpio51", "gpio52";
                                                   >> 2743                                         function = "qup12";
                                                   >> 2744                                 };
2984                         };                       2745                         };
2985                                                  2746 
2986                         qup_spi14_default: qu !! 2747                         qup_spi13_default: qup-spi13-default {
2987                                 pins = "gpio3 !! 2748                                 pinmux {
2988                                 function = "q !! 2749                                         pins = "gpio105", "gpio106",
                                                   >> 2750                                                "gpio107", "gpio108";
                                                   >> 2751                                         function = "qup13";
                                                   >> 2752                                 };
2989                         };                       2753                         };
2990                                                  2754 
2991                         qup_spi15_default: qu !! 2755                         qup_spi14_default: qup-spi14-default {
2992                                 pins = "gpio8 !! 2756                                 pinmux {
2993                                 function = "q !! 2757                                         pins = "gpio33", "gpio34",
                                                   >> 2758                                                "gpio31", "gpio32";
                                                   >> 2759                                         function = "qup14";
                                                   >> 2760                                 };
2994                         };                       2761                         };
2995                                                  2762 
2996                         qup_uart0_default: qu !! 2763                         qup_spi15_default: qup-spi15-default {
2997                                 qup_uart0_tx: !! 2764                                 pinmux {
2998                                         pins  !! 2765                                         pins = "gpio81", "gpio82",
2999                                         funct !! 2766                                                "gpio83", "gpio84";
                                                   >> 2767                                         function = "qup15";
3000                                 };               2768                                 };
                                                   >> 2769                         };
3001                                                  2770 
3002                                 qup_uart0_rx: !! 2771                         qup_uart0_default: qup-uart0-default {
3003                                         pins  !! 2772                                 pinmux {
                                                   >> 2773                                         pins = "gpio2", "gpio3";
3004                                         funct    2774                                         function = "qup0";
3005                                 };               2775                                 };
3006                         };                       2776                         };
3007                                                  2777 
3008                         qup_uart1_default: qu !! 2778                         qup_uart1_default: qup-uart1-default {
3009                                 qup_uart1_tx: !! 2779                                 pinmux {
3010                                         pins  !! 2780                                         pins = "gpio19", "gpio20";
3011                                         funct << 
3012                                 };            << 
3013                                               << 
3014                                 qup_uart1_rx: << 
3015                                         pins  << 
3016                                         funct    2781                                         function = "qup1";
3017                                 };               2782                                 };
3018                         };                       2783                         };
3019                                                  2784 
3020                         qup_uart2_default: qu !! 2785                         qup_uart2_default: qup-uart2-default {
3021                                 qup_uart2_tx: !! 2786                                 pinmux {
3022                                         pins  !! 2787                                         pins = "gpio29", "gpio30";
3023                                         funct << 
3024                                 };            << 
3025                                               << 
3026                                 qup_uart2_rx: << 
3027                                         pins  << 
3028                                         funct    2788                                         function = "qup2";
3029                                 };               2789                                 };
3030                         };                       2790                         };
3031                                                  2791 
3032                         qup_uart3_default: qu !! 2792                         qup_uart3_default: qup-uart3-default {
3033                                 qup_uart3_tx: !! 2793                                 pinmux {
3034                                         pins  !! 2794                                         pins = "gpio43", "gpio44";
3035                                         funct << 
3036                                 };            << 
3037                                               << 
3038                                 qup_uart3_rx: << 
3039                                         pins  << 
3040                                         funct    2795                                         function = "qup3";
3041                                 };               2796                                 };
3042                         };                       2797                         };
3043                                                  2798 
3044                         qup_uart3_4pin: qup-u !! 2799                         qup_uart4_default: qup-uart4-default {
3045                                 qup_uart3_4pi !! 2800                                 pinmux {
3046                                         pins  !! 2801                                         pins = "gpio91", "gpio92";
3047                                         funct !! 2802                                         function = "qup4";
3048                                 };               2803                                 };
                                                   >> 2804                         };
3049                                                  2805 
3050                                 qup_uart3_4pi !! 2806                         qup_uart5_default: qup-uart5-default {
3051                                         pins  !! 2807                                 pinmux {
3052                                         funct !! 2808                                         pins = "gpio87", "gpio88";
                                                   >> 2809                                         function = "qup5";
3053                                 };               2810                                 };
                                                   >> 2811                         };
3054                                                  2812 
3055                                 qup_uart3_4pi !! 2813                         qup_uart6_default: qup-uart6-default {
3056                                         pins  !! 2814                                 pinmux {
3057                                         funct !! 2815                                         pins = "gpio47", "gpio48";
                                                   >> 2816                                         function = "qup6";
3058                                 };               2817                                 };
3059                         };                       2818                         };
3060                                                  2819 
3061                         qup_uart4_default: qu !! 2820                         qup_uart7_default: qup-uart7-default {
3062                                 qup_uart4_tx: !! 2821                                 pinmux {
3063                                         pins  !! 2822                                         pins = "gpio95", "gpio96";
3064                                         funct !! 2823                                         function = "qup7";
3065                                 };               2824                                 };
                                                   >> 2825                         };
3066                                                  2826 
3067                                 qup_uart4_rx: !! 2827                         qup_uart8_default: qup-uart8-default {
3068                                         pins  !! 2828                                 pinmux {
3069                                         funct !! 2829                                         pins = "gpio67", "gpio68";
                                                   >> 2830                                         function = "qup8";
3070                                 };               2831                                 };
3071                         };                       2832                         };
3072                                                  2833 
3073                         qup_uart5_default: qu !! 2834                         qup_uart9_default: qup-uart9-default {
3074                                 qup_uart5_tx: !! 2835                                 pinmux {
3075                                         pins  !! 2836                                         pins = "gpio4", "gpio5";
3076                                         funct !! 2837                                         function = "qup9";
3077                                 };               2838                                 };
                                                   >> 2839                         };
3078                                                  2840 
3079                                 qup_uart5_rx: !! 2841                         qup_uart10_default: qup-uart10-default {
3080                                         pins  !! 2842                                 pinmux {
3081                                         funct !! 2843                                         pins = "gpio53", "gpio54";
                                                   >> 2844                                         function = "qup10";
3082                                 };               2845                                 };
3083                         };                       2846                         };
3084                                                  2847 
3085                         qup_uart6_default: qu !! 2848                         qup_uart11_default: qup-uart11-default {
3086                                 qup_uart6_tx: !! 2849                                 pinmux {
3087                                         pins  !! 2850                                         pins = "gpio33", "gpio34";
3088                                         funct !! 2851                                         function = "qup11";
3089                                 };               2852                                 };
                                                   >> 2853                         };
3090                                                  2854 
3091                                 qup_uart6_rx: !! 2855                         qup_uart12_default: qup-uart12-default {
3092                                         pins  !! 2856                                 pinmux {
3093                                         funct !! 2857                                         pins = "gpio51", "gpio52";
                                                   >> 2858                                         function = "qup12";
3094                                 };               2859                                 };
3095                         };                       2860                         };
3096                                                  2861 
3097                         qup_uart6_4pin: qup-u !! 2862                         qup_uart13_default: qup-uart13-default {
3098                                 qup_uart6_4pi !! 2863                                 pinmux {
3099                                         pins  !! 2864                                         pins = "gpio107", "gpio108";
3100                                         funct !! 2865                                         function = "qup13";
3101                                         bias- << 
3102                                 };               2866                                 };
                                                   >> 2867                         };
3103                                                  2868 
3104                                 qup_uart6_4pi !! 2869                         qup_uart14_default: qup-uart14-default {
3105                                         pins  !! 2870                                 pinmux {
3106                                         funct !! 2871                                         pins = "gpio31", "gpio32";
3107                                         drive !! 2872                                         function = "qup14";
3108                                         bias- << 
3109                                 };               2873                                 };
                                                   >> 2874                         };
3110                                                  2875 
3111                                 qup_uart6_4pi !! 2876                         qup_uart15_default: qup-uart15-default {
3112                                         pins  !! 2877                                 pinmux {
3113                                         funct !! 2878                                         pins = "gpio83", "gpio84";
3114                                         bias- !! 2879                                         function = "qup15";
3115                                 };               2880                                 };
3116                         };                       2881                         };
3117                                                  2882 
3118                         qup_uart7_default: qu !! 2883                         quat_mi2s_sleep: quat_mi2s_sleep {
3119                                 qup_uart7_tx: !! 2884                                 mux {
3120                                         pins  !! 2885                                         pins = "gpio58", "gpio59";
3121                                         funct !! 2886                                         function = "gpio";
3122                                 };               2887                                 };
3123                                                  2888 
3124                                 qup_uart7_rx: !! 2889                                 config {
3125                                         pins  !! 2890                                         pins = "gpio58", "gpio59";
3126                                         funct !! 2891                                         drive-strength = <2>;
                                                   >> 2892                                         bias-pull-down;
                                                   >> 2893                                         input-enable;
3127                                 };               2894                                 };
3128                         };                       2895                         };
3129                                                  2896 
3130                         qup_uart8_default: qu !! 2897                         quat_mi2s_active: quat_mi2s_active {
3131                                 qup_uart8_tx: !! 2898                                 mux {
3132                                         pins  !! 2899                                         pins = "gpio58", "gpio59";
3133                                         funct !! 2900                                         function = "qua_mi2s";
3134                                 };               2901                                 };
3135                                                  2902 
3136                                 qup_uart8_rx: !! 2903                                 config {
3137                                         pins  !! 2904                                         pins = "gpio58", "gpio59";
3138                                         funct !! 2905                                         drive-strength = <8>;
                                                   >> 2906                                         bias-disable;
                                                   >> 2907                                         output-high;
3139                                 };               2908                                 };
3140                         };                       2909                         };
3141                                                  2910 
3142                         qup_uart9_default: qu !! 2911                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143                                 qup_uart9_tx: !! 2912                                 mux {
3144                                         pins  !! 2913                                         pins = "gpio60";
3145                                         funct !! 2914                                         function = "gpio";
3146                                 };               2915                                 };
3147                                                  2916 
3148                                 qup_uart9_rx: !! 2917                                 config {
3149                                         pins  !! 2918                                         pins = "gpio60";
3150                                         funct !! 2919                                         drive-strength = <2>;
                                                   >> 2920                                         bias-pull-down;
                                                   >> 2921                                         input-enable;
3151                                 };               2922                                 };
3152                         };                       2923                         };
3153                                                  2924 
3154                         qup_uart10_default: q !! 2925                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155                                 qup_uart10_tx !! 2926                                 mux {
3156                                         pins  !! 2927                                         pins = "gpio60";
3157                                         funct !! 2928                                         function = "qua_mi2s";
3158                                 };               2929                                 };
3159                                                  2930 
3160                                 qup_uart10_rx !! 2931                                 config {
3161                                         pins  !! 2932                                         pins = "gpio60";
3162                                         funct !! 2933                                         drive-strength = <8>;
                                                   >> 2934                                         bias-disable;
3163                                 };               2935                                 };
3164                         };                       2936                         };
3165                                                  2937 
3166                         qup_uart11_default: q !! 2938                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167                                 qup_uart11_tx !! 2939                                 mux {
3168                                         pins  !! 2940                                         pins = "gpio61";
3169                                         funct !! 2941                                         function = "gpio";
3170                                 };               2942                                 };
3171                                                  2943 
3172                                 qup_uart11_rx !! 2944                                 config {
3173                                         pins  !! 2945                                         pins = "gpio61";
3174                                         funct !! 2946                                         drive-strength = <2>;
                                                   >> 2947                                         bias-pull-down;
                                                   >> 2948                                         input-enable;
3175                                 };               2949                                 };
3176                         };                       2950                         };
3177                                                  2951 
3178                         qup_uart12_default: q !! 2952                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179                                 qup_uart12_tx !! 2953                                 mux {
3180                                         pins  !! 2954                                         pins = "gpio61";
3181                                         funct !! 2955                                         function = "qua_mi2s";
3182                                 };               2956                                 };
3183                                                  2957 
3184                                 qup_uart12_rx !! 2958                                 config {
3185                                         pins  !! 2959                                         pins = "gpio61";
3186                                         funct !! 2960                                         drive-strength = <8>;
                                                   >> 2961                                         bias-disable;
3187                                 };               2962                                 };
3188                         };                       2963                         };
3189                                                  2964 
3190                         qup_uart13_default: q !! 2965                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191                                 qup_uart13_tx !! 2966                                 mux {
3192                                         pins  !! 2967                                         pins = "gpio62";
3193                                         funct !! 2968                                         function = "gpio";
3194                                 };               2969                                 };
3195                                                  2970 
3196                                 qup_uart13_rx !! 2971                                 config {
3197                                         pins  !! 2972                                         pins = "gpio62";
3198                                         funct !! 2973                                         drive-strength = <2>;
                                                   >> 2974                                         bias-pull-down;
                                                   >> 2975                                         input-enable;
3199                                 };               2976                                 };
3200                         };                       2977                         };
3201                                                  2978 
3202                         qup_uart14_default: q !! 2979                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203                                 qup_uart14_tx !! 2980                                 mux {
3204                                         pins  !! 2981                                         pins = "gpio62";
3205                                         funct !! 2982                                         function = "qua_mi2s";
3206                                 };               2983                                 };
3207                                                  2984 
3208                                 qup_uart14_rx !! 2985                                 config {
3209                                         pins  !! 2986                                         pins = "gpio62";
3210                                         funct !! 2987                                         drive-strength = <8>;
                                                   >> 2988                                         bias-disable;
3211                                 };               2989                                 };
3212                         };                       2990                         };
3213                                                  2991 
3214                         qup_uart15_default: q !! 2992                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215                                 qup_uart15_tx !! 2993                                 mux {
3216                                         pins  !! 2994                                         pins = "gpio63";
3217                                         funct !! 2995                                         function = "gpio";
3218                                 };               2996                                 };
3219                                                  2997 
3220                                 qup_uart15_rx !! 2998                                 config {
3221                                         pins  !! 2999                                         pins = "gpio63";
3222                                         funct !! 3000                                         drive-strength = <2>;
                                                   >> 3001                                         bias-pull-down;
                                                   >> 3002                                         input-enable;
3223                                 };               3003                                 };
3224                         };                       3004                         };
3225                                                  3005 
3226                         quat_mi2s_sleep: quat !! 3006                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227                                 pins = "gpio5 !! 3007                                 mux {
3228                                 function = "g !! 3008                                         pins = "gpio63";
3229                                 drive-strengt !! 3009                                         function = "qua_mi2s";
3230                                 bias-pull-dow !! 3010                                 };
3231                         };                    << 
3232                                               << 
3233                         quat_mi2s_active: qua << 
3234                                 pins = "gpio5 << 
3235                                 function = "q << 
3236                                 drive-strengt << 
3237                                 bias-disable; << 
3238                                 output-high;  << 
3239                         };                    << 
3240                                               << 
3241                         quat_mi2s_sd0_sleep:  << 
3242                                 pins = "gpio6 << 
3243                                 function = "g << 
3244                                 drive-strengt << 
3245                                 bias-pull-dow << 
3246                         };                    << 
3247                                               << 
3248                         quat_mi2s_sd0_active: << 
3249                                 pins = "gpio6 << 
3250                                 function = "q << 
3251                                 drive-strengt << 
3252                                 bias-disable; << 
3253                         };                    << 
3254                                               << 
3255                         quat_mi2s_sd1_sleep:  << 
3256                                 pins = "gpio6 << 
3257                                 function = "g << 
3258                                 drive-strengt << 
3259                                 bias-pull-dow << 
3260                         };                    << 
3261                                               << 
3262                         quat_mi2s_sd1_active: << 
3263                                 pins = "gpio6 << 
3264                                 function = "q << 
3265                                 drive-strengt << 
3266                                 bias-disable; << 
3267                         };                    << 
3268                                               << 
3269                         quat_mi2s_sd2_sleep:  << 
3270                                 pins = "gpio6 << 
3271                                 function = "g << 
3272                                 drive-strengt << 
3273                                 bias-pull-dow << 
3274                         };                    << 
3275                                               << 
3276                         quat_mi2s_sd2_active: << 
3277                                 pins = "gpio6 << 
3278                                 function = "q << 
3279                                 drive-strengt << 
3280                                 bias-disable; << 
3281                         };                    << 
3282                                               << 
3283                         quat_mi2s_sd3_sleep:  << 
3284                                 pins = "gpio6 << 
3285                                 function = "g << 
3286                                 drive-strengt << 
3287                                 bias-pull-dow << 
3288                         };                    << 
3289                                                  3011 
3290                         quat_mi2s_sd3_active: !! 3012                                 config {
3291                                 pins = "gpio6 !! 3013                                         pins = "gpio63";
3292                                 function = "q !! 3014                                         drive-strength = <8>;
3293                                 drive-strengt !! 3015                                         bias-disable;
3294                                 bias-disable; !! 3016                                 };
3295                         };                       3017                         };
3296                 };                               3018                 };
3297                                                  3019 
3298                 mss_pil: remoteproc@4080000 {    3020                 mss_pil: remoteproc@4080000 {
3299                         compatible = "qcom,sd    3021                         compatible = "qcom,sdm845-mss-pil";
3300                         reg = <0 0x04080000 0    3022                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301                         reg-names = "qdsp6",     3023                         reg-names = "qdsp6", "rmb";
3302                                                  3024 
3303                         interrupts-extended =    3025                         interrupts-extended =
3304                                 <&intc GIC_SP    3026                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305                                 <&modem_smp2p    3027                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306                                 <&modem_smp2p    3028                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307                                 <&modem_smp2p    3029                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308                                 <&modem_smp2p    3030                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309                                 <&modem_smp2p    3031                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310                         interrupt-names = "wd    3032                         interrupt-names = "wdog", "fatal", "ready",
3311                                           "ha    3033                                           "handover", "stop-ack",
3312                                           "sh    3034                                           "shutdown-ack";
3313                                                  3035 
3314                         clocks = <&gcc GCC_MS    3036                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315                                  <&gcc GCC_MS    3037                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316                                  <&gcc GCC_BO    3038                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317                                  <&gcc GCC_MS    3039                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318                                  <&gcc GCC_MS    3040                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319                                  <&gcc GCC_MS    3041                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320                                  <&gcc GCC_PR    3042                                  <&gcc GCC_PRNG_AHB_CLK>,
3321                                  <&rpmhcc RPM    3043                                  <&rpmhcc RPMH_CXO_CLK>;
3322                         clock-names = "iface"    3044                         clock-names = "iface", "bus", "mem", "gpll0_mss",
3323                                       "snoc_a    3045                                       "snoc_axi", "mnoc_axi", "prng", "xo";
3324                                                  3046 
3325                         qcom,qmp = <&aoss_qmp    3047                         qcom,qmp = <&aoss_qmp>;
3326                                                  3048 
3327                         qcom,smem-states = <&    3049                         qcom,smem-states = <&modem_smp2p_out 0>;
3328                         qcom,smem-state-names    3050                         qcom,smem-state-names = "stop";
3329                                                  3051 
3330                         resets = <&aoss_reset    3052                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331                                  <&pdc_reset     3053                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332                         reset-names = "mss_re    3054                         reset-names = "mss_restart", "pdc_reset";
3333                                                  3055 
3334                         qcom,halt-regs = <&tc !! 3056                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335                                                  3057 
3336                         power-domains = <&rpm    3058                         power-domains = <&rpmhpd SDM845_CX>,
3337                                         <&rpm    3059                                         <&rpmhpd SDM845_MX>,
3338                                         <&rpm    3060                                         <&rpmhpd SDM845_MSS>;
3339                         power-domain-names =     3061                         power-domain-names = "cx", "mx", "mss";
3340                                                  3062 
3341                         status = "disabled";     3063                         status = "disabled";
3342                                                  3064 
3343                         mba {                    3065                         mba {
3344                                 memory-region    3066                                 memory-region = <&mba_region>;
3345                         };                       3067                         };
3346                                                  3068 
3347                         mpss {                   3069                         mpss {
3348                                 memory-region    3070                                 memory-region = <&mpss_region>;
3349                         };                       3071                         };
3350                                                  3072 
3351                         metadata {            << 
3352                                 memory-region << 
3353                         };                    << 
3354                                               << 
3355                         glink-edge {             3073                         glink-edge {
3356                                 interrupts =     3074                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357                                 label = "mode    3075                                 label = "modem";
3358                                 qcom,remote-p    3076                                 qcom,remote-pid = <1>;
3359                                 mboxes = <&ap    3077                                 mboxes = <&apss_shared 12>;
3360                         };                       3078                         };
3361                 };                               3079                 };
3362                                                  3080 
3363                 gpucc: clock-controller@50900    3081                 gpucc: clock-controller@5090000 {
3364                         compatible = "qcom,sd    3082                         compatible = "qcom,sdm845-gpucc";
3365                         reg = <0 0x05090000 0    3083                         reg = <0 0x05090000 0 0x9000>;
3366                         #clock-cells = <1>;      3084                         #clock-cells = <1>;
3367                         #reset-cells = <1>;      3085                         #reset-cells = <1>;
3368                         #power-domain-cells =    3086                         #power-domain-cells = <1>;
3369                         clocks = <&rpmhcc RPM    3087                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3370                                  <&gcc GCC_GP    3088                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371                                  <&gcc GCC_GP    3089                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372                         clock-names = "bi_tcx    3090                         clock-names = "bi_tcxo",
3373                                       "gcc_gp    3091                                       "gcc_gpu_gpll0_clk_src",
3374                                       "gcc_gp    3092                                       "gcc_gpu_gpll0_div_clk_src";
3375                 };                               3093                 };
3376                                                  3094 
3377                 slpi_pas: remoteproc@5c00000  << 
3378                         compatible = "qcom,sd << 
3379                         reg = <0 0x5c00000 0  << 
3380                                               << 
3381                         interrupts-extended = << 
3382                                               << 
3383                                               << 
3384                                               << 
3385                                               << 
3386                         interrupt-names = "wd << 
3387                                               << 
3388                                               << 
3389                         clocks = <&rpmhcc RPM << 
3390                         clock-names = "xo";   << 
3391                                               << 
3392                         qcom,qmp = <&aoss_qmp << 
3393                                               << 
3394                         power-domains = <&rpm << 
3395                                         <&rpm << 
3396                         power-domain-names =  << 
3397                                               << 
3398                         memory-region = <&slp << 
3399                                               << 
3400                         qcom,smem-states = <& << 
3401                         qcom,smem-state-names << 
3402                                               << 
3403                         status = "disabled";  << 
3404                                               << 
3405                         glink-edge {          << 
3406                                 interrupts =  << 
3407                                 label = "dsps << 
3408                                 qcom,remote-p << 
3409                                 mboxes = <&ap << 
3410                                               << 
3411                                 fastrpc {     << 
3412                                         compa << 
3413                                         qcom, << 
3414                                         label << 
3415                                         qcom, << 
3416                                         qcom, << 
3417                                               << 
3418                                         memor << 
3419                                         #addr << 
3420                                         #size << 
3421                                               << 
3422                                         compu << 
3423                                               << 
3424                                               << 
3425                                         };    << 
3426                                 };            << 
3427                         };                    << 
3428                 };                            << 
3429                                               << 
3430                 stm@6002000 {                    3095                 stm@6002000 {
3431                         compatible = "arm,cor    3096                         compatible = "arm,coresight-stm", "arm,primecell";
3432                         reg = <0 0x06002000 0    3097                         reg = <0 0x06002000 0 0x1000>,
3433                               <0 0x16280000 0    3098                               <0 0x16280000 0 0x180000>;
3434                         reg-names = "stm-base    3099                         reg-names = "stm-base", "stm-stimulus-base";
3435                                                  3100 
3436                         clocks = <&aoss_qmp>;    3101                         clocks = <&aoss_qmp>;
3437                         clock-names = "apb_pc    3102                         clock-names = "apb_pclk";
3438                                                  3103 
3439                         out-ports {              3104                         out-ports {
3440                                 port {           3105                                 port {
3441                                         stm_o    3106                                         stm_out: endpoint {
3442                                                  3107                                                 remote-endpoint =
3443                                                  3108                                                   <&funnel0_in7>;
3444                                         };       3109                                         };
3445                                 };               3110                                 };
3446                         };                       3111                         };
3447                 };                               3112                 };
3448                                                  3113 
3449                 funnel@6041000 {                 3114                 funnel@6041000 {
3450                         compatible = "arm,cor    3115                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451                         reg = <0 0x06041000 0    3116                         reg = <0 0x06041000 0 0x1000>;
3452                                                  3117 
3453                         clocks = <&aoss_qmp>;    3118                         clocks = <&aoss_qmp>;
3454                         clock-names = "apb_pc    3119                         clock-names = "apb_pclk";
3455                                                  3120 
3456                         out-ports {              3121                         out-ports {
3457                                 port {           3122                                 port {
3458                                         funne    3123                                         funnel0_out: endpoint {
3459                                                  3124                                                 remote-endpoint =
3460                                                  3125                                                   <&merge_funnel_in0>;
3461                                         };       3126                                         };
3462                                 };               3127                                 };
3463                         };                       3128                         };
3464                                                  3129 
3465                         in-ports {               3130                         in-ports {
3466                                 #address-cell    3131                                 #address-cells = <1>;
3467                                 #size-cells =    3132                                 #size-cells = <0>;
3468                                                  3133 
3469                                 port@7 {         3134                                 port@7 {
3470                                         reg =    3135                                         reg = <7>;
3471                                         funne    3136                                         funnel0_in7: endpoint {
3472                                                  3137                                                 remote-endpoint = <&stm_out>;
3473                                         };       3138                                         };
3474                                 };               3139                                 };
3475                         };                       3140                         };
3476                 };                               3141                 };
3477                                                  3142 
3478                 funnel@6043000 {                 3143                 funnel@6043000 {
3479                         compatible = "arm,cor    3144                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480                         reg = <0 0x06043000 0    3145                         reg = <0 0x06043000 0 0x1000>;
3481                                                  3146 
3482                         clocks = <&aoss_qmp>;    3147                         clocks = <&aoss_qmp>;
3483                         clock-names = "apb_pc    3148                         clock-names = "apb_pclk";
3484                                                  3149 
3485                         out-ports {              3150                         out-ports {
3486                                 port {           3151                                 port {
3487                                         funne    3152                                         funnel2_out: endpoint {
3488                                                  3153                                                 remote-endpoint =
3489                                                  3154                                                   <&merge_funnel_in2>;
3490                                         };       3155                                         };
3491                                 };               3156                                 };
3492                         };                       3157                         };
3493                                                  3158 
3494                         in-ports {               3159                         in-ports {
3495                                 #address-cell    3160                                 #address-cells = <1>;
3496                                 #size-cells =    3161                                 #size-cells = <0>;
3497                                                  3162 
3498                                 port@5 {         3163                                 port@5 {
3499                                         reg =    3164                                         reg = <5>;
3500                                         funne    3165                                         funnel2_in5: endpoint {
3501                                                  3166                                                 remote-endpoint =
3502                                                  3167                                                   <&apss_merge_funnel_out>;
3503                                         };       3168                                         };
3504                                 };               3169                                 };
3505                         };                       3170                         };
3506                 };                               3171                 };
3507                                                  3172 
3508                 funnel@6045000 {                 3173                 funnel@6045000 {
3509                         compatible = "arm,cor    3174                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510                         reg = <0 0x06045000 0    3175                         reg = <0 0x06045000 0 0x1000>;
3511                                                  3176 
3512                         clocks = <&aoss_qmp>;    3177                         clocks = <&aoss_qmp>;
3513                         clock-names = "apb_pc    3178                         clock-names = "apb_pclk";
3514                                                  3179 
3515                         out-ports {              3180                         out-ports {
3516                                 port {           3181                                 port {
3517                                         merge    3182                                         merge_funnel_out: endpoint {
3518                                                  3183                                                 remote-endpoint = <&etf_in>;
3519                                         };       3184                                         };
3520                                 };               3185                                 };
3521                         };                       3186                         };
3522                                                  3187 
3523                         in-ports {               3188                         in-ports {
3524                                 #address-cell    3189                                 #address-cells = <1>;
3525                                 #size-cells =    3190                                 #size-cells = <0>;
3526                                                  3191 
3527                                 port@0 {         3192                                 port@0 {
3528                                         reg =    3193                                         reg = <0>;
3529                                         merge    3194                                         merge_funnel_in0: endpoint {
3530                                                  3195                                                 remote-endpoint =
3531                                                  3196                                                   <&funnel0_out>;
3532                                         };       3197                                         };
3533                                 };               3198                                 };
3534                                                  3199 
3535                                 port@2 {         3200                                 port@2 {
3536                                         reg =    3201                                         reg = <2>;
3537                                         merge    3202                                         merge_funnel_in2: endpoint {
3538                                                  3203                                                 remote-endpoint =
3539                                                  3204                                                   <&funnel2_out>;
3540                                         };       3205                                         };
3541                                 };               3206                                 };
3542                         };                       3207                         };
3543                 };                               3208                 };
3544                                                  3209 
3545                 replicator@6046000 {             3210                 replicator@6046000 {
3546                         compatible = "arm,cor    3211                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547                         reg = <0 0x06046000 0    3212                         reg = <0 0x06046000 0 0x1000>;
3548                                                  3213 
3549                         clocks = <&aoss_qmp>;    3214                         clocks = <&aoss_qmp>;
3550                         clock-names = "apb_pc    3215                         clock-names = "apb_pclk";
3551                                                  3216 
3552                         out-ports {              3217                         out-ports {
3553                                 port {           3218                                 port {
3554                                         repli    3219                                         replicator_out: endpoint {
3555                                                  3220                                                 remote-endpoint = <&etr_in>;
3556                                         };       3221                                         };
3557                                 };               3222                                 };
3558                         };                       3223                         };
3559                                                  3224 
3560                         in-ports {               3225                         in-ports {
3561                                 port {           3226                                 port {
3562                                         repli    3227                                         replicator_in: endpoint {
3563                                                  3228                                                 remote-endpoint = <&etf_out>;
3564                                         };       3229                                         };
3565                                 };               3230                                 };
3566                         };                       3231                         };
3567                 };                               3232                 };
3568                                                  3233 
3569                 etf@6047000 {                    3234                 etf@6047000 {
3570                         compatible = "arm,cor    3235                         compatible = "arm,coresight-tmc", "arm,primecell";
3571                         reg = <0 0x06047000 0    3236                         reg = <0 0x06047000 0 0x1000>;
3572                                                  3237 
3573                         clocks = <&aoss_qmp>;    3238                         clocks = <&aoss_qmp>;
3574                         clock-names = "apb_pc    3239                         clock-names = "apb_pclk";
3575                                                  3240 
3576                         out-ports {              3241                         out-ports {
3577                                 port {           3242                                 port {
3578                                         etf_o    3243                                         etf_out: endpoint {
3579                                                  3244                                                 remote-endpoint =
3580                                                  3245                                                   <&replicator_in>;
3581                                         };       3246                                         };
3582                                 };               3247                                 };
3583                         };                       3248                         };
3584                                                  3249 
3585                         in-ports {               3250                         in-ports {
                                                   >> 3251                                 #address-cells = <1>;
                                                   >> 3252                                 #size-cells = <0>;
3586                                                  3253 
3587                                 port {        !! 3254                                 port@1 {
                                                   >> 3255                                         reg = <1>;
3588                                         etf_i    3256                                         etf_in: endpoint {
3589                                                  3257                                                 remote-endpoint =
3590                                                  3258                                                   <&merge_funnel_out>;
3591                                         };       3259                                         };
3592                                 };               3260                                 };
3593                         };                       3261                         };
3594                 };                               3262                 };
3595                                                  3263 
3596                 etr@6048000 {                    3264                 etr@6048000 {
3597                         compatible = "arm,cor    3265                         compatible = "arm,coresight-tmc", "arm,primecell";
3598                         reg = <0 0x06048000 0    3266                         reg = <0 0x06048000 0 0x1000>;
3599                                                  3267 
3600                         clocks = <&aoss_qmp>;    3268                         clocks = <&aoss_qmp>;
3601                         clock-names = "apb_pc    3269                         clock-names = "apb_pclk";
3602                         arm,scatter-gather;      3270                         arm,scatter-gather;
3603                                                  3271 
3604                         in-ports {               3272                         in-ports {
3605                                 port {           3273                                 port {
3606                                         etr_i    3274                                         etr_in: endpoint {
3607                                                  3275                                                 remote-endpoint =
3608                                                  3276                                                   <&replicator_out>;
3609                                         };       3277                                         };
3610                                 };               3278                                 };
3611                         };                       3279                         };
3612                 };                               3280                 };
3613                                                  3281 
3614                 etm@7040000 {                    3282                 etm@7040000 {
3615                         compatible = "arm,cor    3283                         compatible = "arm,coresight-etm4x", "arm,primecell";
3616                         reg = <0 0x07040000 0    3284                         reg = <0 0x07040000 0 0x1000>;
3617                                                  3285 
3618                         cpu = <&CPU0>;           3286                         cpu = <&CPU0>;
3619                                                  3287 
3620                         clocks = <&aoss_qmp>;    3288                         clocks = <&aoss_qmp>;
3621                         clock-names = "apb_pc    3289                         clock-names = "apb_pclk";
3622                         arm,coresight-loses-c    3290                         arm,coresight-loses-context-with-cpu;
3623                                                  3291 
3624                         out-ports {              3292                         out-ports {
3625                                 port {           3293                                 port {
3626                                         etm0_    3294                                         etm0_out: endpoint {
3627                                                  3295                                                 remote-endpoint =
3628                                                  3296                                                   <&apss_funnel_in0>;
3629                                         };       3297                                         };
3630                                 };               3298                                 };
3631                         };                       3299                         };
3632                 };                               3300                 };
3633                                                  3301 
3634                 etm@7140000 {                    3302                 etm@7140000 {
3635                         compatible = "arm,cor    3303                         compatible = "arm,coresight-etm4x", "arm,primecell";
3636                         reg = <0 0x07140000 0    3304                         reg = <0 0x07140000 0 0x1000>;
3637                                                  3305 
3638                         cpu = <&CPU1>;           3306                         cpu = <&CPU1>;
3639                                                  3307 
3640                         clocks = <&aoss_qmp>;    3308                         clocks = <&aoss_qmp>;
3641                         clock-names = "apb_pc    3309                         clock-names = "apb_pclk";
3642                         arm,coresight-loses-c    3310                         arm,coresight-loses-context-with-cpu;
3643                                                  3311 
3644                         out-ports {              3312                         out-ports {
3645                                 port {           3313                                 port {
3646                                         etm1_    3314                                         etm1_out: endpoint {
3647                                                  3315                                                 remote-endpoint =
3648                                                  3316                                                   <&apss_funnel_in1>;
3649                                         };       3317                                         };
3650                                 };               3318                                 };
3651                         };                       3319                         };
3652                 };                               3320                 };
3653                                                  3321 
3654                 etm@7240000 {                    3322                 etm@7240000 {
3655                         compatible = "arm,cor    3323                         compatible = "arm,coresight-etm4x", "arm,primecell";
3656                         reg = <0 0x07240000 0    3324                         reg = <0 0x07240000 0 0x1000>;
3657                                                  3325 
3658                         cpu = <&CPU2>;           3326                         cpu = <&CPU2>;
3659                                                  3327 
3660                         clocks = <&aoss_qmp>;    3328                         clocks = <&aoss_qmp>;
3661                         clock-names = "apb_pc    3329                         clock-names = "apb_pclk";
3662                         arm,coresight-loses-c    3330                         arm,coresight-loses-context-with-cpu;
3663                                                  3331 
3664                         out-ports {              3332                         out-ports {
3665                                 port {           3333                                 port {
3666                                         etm2_    3334                                         etm2_out: endpoint {
3667                                                  3335                                                 remote-endpoint =
3668                                                  3336                                                   <&apss_funnel_in2>;
3669                                         };       3337                                         };
3670                                 };               3338                                 };
3671                         };                       3339                         };
3672                 };                               3340                 };
3673                                                  3341 
3674                 etm@7340000 {                    3342                 etm@7340000 {
3675                         compatible = "arm,cor    3343                         compatible = "arm,coresight-etm4x", "arm,primecell";
3676                         reg = <0 0x07340000 0    3344                         reg = <0 0x07340000 0 0x1000>;
3677                                                  3345 
3678                         cpu = <&CPU3>;           3346                         cpu = <&CPU3>;
3679                                                  3347 
3680                         clocks = <&aoss_qmp>;    3348                         clocks = <&aoss_qmp>;
3681                         clock-names = "apb_pc    3349                         clock-names = "apb_pclk";
3682                         arm,coresight-loses-c    3350                         arm,coresight-loses-context-with-cpu;
3683                                                  3351 
3684                         out-ports {              3352                         out-ports {
3685                                 port {           3353                                 port {
3686                                         etm3_    3354                                         etm3_out: endpoint {
3687                                                  3355                                                 remote-endpoint =
3688                                                  3356                                                   <&apss_funnel_in3>;
3689                                         };       3357                                         };
3690                                 };               3358                                 };
3691                         };                       3359                         };
3692                 };                               3360                 };
3693                                                  3361 
3694                 etm@7440000 {                    3362                 etm@7440000 {
3695                         compatible = "arm,cor    3363                         compatible = "arm,coresight-etm4x", "arm,primecell";
3696                         reg = <0 0x07440000 0    3364                         reg = <0 0x07440000 0 0x1000>;
3697                                                  3365 
3698                         cpu = <&CPU4>;           3366                         cpu = <&CPU4>;
3699                                                  3367 
3700                         clocks = <&aoss_qmp>;    3368                         clocks = <&aoss_qmp>;
3701                         clock-names = "apb_pc    3369                         clock-names = "apb_pclk";
3702                         arm,coresight-loses-c    3370                         arm,coresight-loses-context-with-cpu;
3703                                                  3371 
3704                         out-ports {              3372                         out-ports {
3705                                 port {           3373                                 port {
3706                                         etm4_    3374                                         etm4_out: endpoint {
3707                                                  3375                                                 remote-endpoint =
3708                                                  3376                                                   <&apss_funnel_in4>;
3709                                         };       3377                                         };
3710                                 };               3378                                 };
3711                         };                       3379                         };
3712                 };                               3380                 };
3713                                                  3381 
3714                 etm@7540000 {                    3382                 etm@7540000 {
3715                         compatible = "arm,cor    3383                         compatible = "arm,coresight-etm4x", "arm,primecell";
3716                         reg = <0 0x07540000 0    3384                         reg = <0 0x07540000 0 0x1000>;
3717                                                  3385 
3718                         cpu = <&CPU5>;           3386                         cpu = <&CPU5>;
3719                                                  3387 
3720                         clocks = <&aoss_qmp>;    3388                         clocks = <&aoss_qmp>;
3721                         clock-names = "apb_pc    3389                         clock-names = "apb_pclk";
3722                         arm,coresight-loses-c    3390                         arm,coresight-loses-context-with-cpu;
3723                                                  3391 
3724                         out-ports {              3392                         out-ports {
3725                                 port {           3393                                 port {
3726                                         etm5_    3394                                         etm5_out: endpoint {
3727                                                  3395                                                 remote-endpoint =
3728                                                  3396                                                   <&apss_funnel_in5>;
3729                                         };       3397                                         };
3730                                 };               3398                                 };
3731                         };                       3399                         };
3732                 };                               3400                 };
3733                                                  3401 
3734                 etm@7640000 {                    3402                 etm@7640000 {
3735                         compatible = "arm,cor    3403                         compatible = "arm,coresight-etm4x", "arm,primecell";
3736                         reg = <0 0x07640000 0    3404                         reg = <0 0x07640000 0 0x1000>;
3737                                                  3405 
3738                         cpu = <&CPU6>;           3406                         cpu = <&CPU6>;
3739                                                  3407 
3740                         clocks = <&aoss_qmp>;    3408                         clocks = <&aoss_qmp>;
3741                         clock-names = "apb_pc    3409                         clock-names = "apb_pclk";
3742                         arm,coresight-loses-c    3410                         arm,coresight-loses-context-with-cpu;
3743                                                  3411 
3744                         out-ports {              3412                         out-ports {
3745                                 port {           3413                                 port {
3746                                         etm6_    3414                                         etm6_out: endpoint {
3747                                                  3415                                                 remote-endpoint =
3748                                                  3416                                                   <&apss_funnel_in6>;
3749                                         };       3417                                         };
3750                                 };               3418                                 };
3751                         };                       3419                         };
3752                 };                               3420                 };
3753                                                  3421 
3754                 etm@7740000 {                    3422                 etm@7740000 {
3755                         compatible = "arm,cor    3423                         compatible = "arm,coresight-etm4x", "arm,primecell";
3756                         reg = <0 0x07740000 0    3424                         reg = <0 0x07740000 0 0x1000>;
3757                                                  3425 
3758                         cpu = <&CPU7>;           3426                         cpu = <&CPU7>;
3759                                                  3427 
3760                         clocks = <&aoss_qmp>;    3428                         clocks = <&aoss_qmp>;
3761                         clock-names = "apb_pc    3429                         clock-names = "apb_pclk";
3762                         arm,coresight-loses-c    3430                         arm,coresight-loses-context-with-cpu;
3763                                                  3431 
3764                         out-ports {              3432                         out-ports {
3765                                 port {           3433                                 port {
3766                                         etm7_    3434                                         etm7_out: endpoint {
3767                                                  3435                                                 remote-endpoint =
3768                                                  3436                                                   <&apss_funnel_in7>;
3769                                         };       3437                                         };
3770                                 };               3438                                 };
3771                         };                       3439                         };
3772                 };                               3440                 };
3773                                                  3441 
3774                 funnel@7800000 { /* APSS Funn    3442                 funnel@7800000 { /* APSS Funnel */
3775                         compatible = "arm,cor    3443                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776                         reg = <0 0x07800000 0    3444                         reg = <0 0x07800000 0 0x1000>;
3777                                                  3445 
3778                         clocks = <&aoss_qmp>;    3446                         clocks = <&aoss_qmp>;
3779                         clock-names = "apb_pc    3447                         clock-names = "apb_pclk";
3780                                                  3448 
3781                         out-ports {              3449                         out-ports {
3782                                 port {           3450                                 port {
3783                                         apss_    3451                                         apss_funnel_out: endpoint {
3784                                                  3452                                                 remote-endpoint =
3785                                                  3453                                                   <&apss_merge_funnel_in>;
3786                                         };       3454                                         };
3787                                 };               3455                                 };
3788                         };                       3456                         };
3789                                                  3457 
3790                         in-ports {               3458                         in-ports {
3791                                 #address-cell    3459                                 #address-cells = <1>;
3792                                 #size-cells =    3460                                 #size-cells = <0>;
3793                                                  3461 
3794                                 port@0 {         3462                                 port@0 {
3795                                         reg =    3463                                         reg = <0>;
3796                                         apss_    3464                                         apss_funnel_in0: endpoint {
3797                                                  3465                                                 remote-endpoint =
3798                                                  3466                                                   <&etm0_out>;
3799                                         };       3467                                         };
3800                                 };               3468                                 };
3801                                                  3469 
3802                                 port@1 {         3470                                 port@1 {
3803                                         reg =    3471                                         reg = <1>;
3804                                         apss_    3472                                         apss_funnel_in1: endpoint {
3805                                                  3473                                                 remote-endpoint =
3806                                                  3474                                                   <&etm1_out>;
3807                                         };       3475                                         };
3808                                 };               3476                                 };
3809                                                  3477 
3810                                 port@2 {         3478                                 port@2 {
3811                                         reg =    3479                                         reg = <2>;
3812                                         apss_    3480                                         apss_funnel_in2: endpoint {
3813                                                  3481                                                 remote-endpoint =
3814                                                  3482                                                   <&etm2_out>;
3815                                         };       3483                                         };
3816                                 };               3484                                 };
3817                                                  3485 
3818                                 port@3 {         3486                                 port@3 {
3819                                         reg =    3487                                         reg = <3>;
3820                                         apss_    3488                                         apss_funnel_in3: endpoint {
3821                                                  3489                                                 remote-endpoint =
3822                                                  3490                                                   <&etm3_out>;
3823                                         };       3491                                         };
3824                                 };               3492                                 };
3825                                                  3493 
3826                                 port@4 {         3494                                 port@4 {
3827                                         reg =    3495                                         reg = <4>;
3828                                         apss_    3496                                         apss_funnel_in4: endpoint {
3829                                                  3497                                                 remote-endpoint =
3830                                                  3498                                                   <&etm4_out>;
3831                                         };       3499                                         };
3832                                 };               3500                                 };
3833                                                  3501 
3834                                 port@5 {         3502                                 port@5 {
3835                                         reg =    3503                                         reg = <5>;
3836                                         apss_    3504                                         apss_funnel_in5: endpoint {
3837                                                  3505                                                 remote-endpoint =
3838                                                  3506                                                   <&etm5_out>;
3839                                         };       3507                                         };
3840                                 };               3508                                 };
3841                                                  3509 
3842                                 port@6 {         3510                                 port@6 {
3843                                         reg =    3511                                         reg = <6>;
3844                                         apss_    3512                                         apss_funnel_in6: endpoint {
3845                                                  3513                                                 remote-endpoint =
3846                                                  3514                                                   <&etm6_out>;
3847                                         };       3515                                         };
3848                                 };               3516                                 };
3849                                                  3517 
3850                                 port@7 {         3518                                 port@7 {
3851                                         reg =    3519                                         reg = <7>;
3852                                         apss_    3520                                         apss_funnel_in7: endpoint {
3853                                                  3521                                                 remote-endpoint =
3854                                                  3522                                                   <&etm7_out>;
3855                                         };       3523                                         };
3856                                 };               3524                                 };
3857                         };                       3525                         };
3858                 };                               3526                 };
3859                                                  3527 
3860                 funnel@7810000 {                 3528                 funnel@7810000 {
3861                         compatible = "arm,cor    3529                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862                         reg = <0 0x07810000 0    3530                         reg = <0 0x07810000 0 0x1000>;
3863                                                  3531 
3864                         clocks = <&aoss_qmp>;    3532                         clocks = <&aoss_qmp>;
3865                         clock-names = "apb_pc    3533                         clock-names = "apb_pclk";
3866                                                  3534 
3867                         out-ports {              3535                         out-ports {
3868                                 port {           3536                                 port {
3869                                         apss_    3537                                         apss_merge_funnel_out: endpoint {
3870                                                  3538                                                 remote-endpoint =
3871                                                  3539                                                   <&funnel2_in5>;
3872                                         };       3540                                         };
3873                                 };               3541                                 };
3874                         };                       3542                         };
3875                                                  3543 
3876                         in-ports {               3544                         in-ports {
3877                                 port {           3545                                 port {
3878                                         apss_    3546                                         apss_merge_funnel_in: endpoint {
3879                                                  3547                                                 remote-endpoint =
3880                                                  3548                                                   <&apss_funnel_out>;
3881                                         };       3549                                         };
3882                                 };               3550                                 };
3883                         };                       3551                         };
3884                 };                               3552                 };
3885                                                  3553 
3886                 sdhc_2: mmc@8804000 {         !! 3554                 sdhc_2: sdhci@8804000 {
3887                         compatible = "qcom,sd    3555                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888                         reg = <0 0x08804000 0    3556                         reg = <0 0x08804000 0 0x1000>;
3889                                                  3557 
3890                         interrupts = <GIC_SPI    3558                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI    3559                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892                         interrupt-names = "hc    3560                         interrupt-names = "hc_irq", "pwr_irq";
3893                                                  3561 
3894                         clocks = <&gcc GCC_SD    3562                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895                                  <&gcc GCC_SD    3563                                  <&gcc GCC_SDCC2_APPS_CLK>,
3896                                  <&rpmhcc RPM    3564                                  <&rpmhcc RPMH_CXO_CLK>;
3897                         clock-names = "iface"    3565                         clock-names = "iface", "core", "xo";
3898                         iommus = <&apps_smmu     3566                         iommus = <&apps_smmu 0xa0 0xf>;
3899                         power-domains = <&rpm    3567                         power-domains = <&rpmhpd SDM845_CX>;
3900                         operating-points-v2 =    3568                         operating-points-v2 = <&sdhc2_opp_table>;
3901                                                  3569 
3902                         status = "disabled";     3570                         status = "disabled";
3903                                                  3571 
3904                         sdhc2_opp_table: opp- !! 3572                         sdhc2_opp_table: sdhc2-opp-table {
3905                                 compatible =     3573                                 compatible = "operating-points-v2";
3906                                                  3574 
3907                                 opp-9600000 {    3575                                 opp-9600000 {
3908                                         opp-h    3576                                         opp-hz = /bits/ 64 <9600000>;
3909                                         requi    3577                                         required-opps = <&rpmhpd_opp_min_svs>;
3910                                 };               3578                                 };
3911                                                  3579 
3912                                 opp-19200000     3580                                 opp-19200000 {
3913                                         opp-h    3581                                         opp-hz = /bits/ 64 <19200000>;
3914                                         requi    3582                                         required-opps = <&rpmhpd_opp_low_svs>;
3915                                 };               3583                                 };
3916                                                  3584 
3917                                 opp-100000000    3585                                 opp-100000000 {
3918                                         opp-h    3586                                         opp-hz = /bits/ 64 <100000000>;
3919                                         requi    3587                                         required-opps = <&rpmhpd_opp_svs>;
3920                                 };               3588                                 };
3921                                                  3589 
3922                                 opp-201500000    3590                                 opp-201500000 {
3923                                         opp-h    3591                                         opp-hz = /bits/ 64 <201500000>;
3924                                         requi    3592                                         required-opps = <&rpmhpd_opp_svs_l1>;
3925                                 };               3593                                 };
3926                         };                       3594                         };
3927                 };                               3595                 };
3928                                                  3596 
                                                   >> 3597                 qspi_opp_table: qspi-opp-table {
                                                   >> 3598                         compatible = "operating-points-v2";
                                                   >> 3599 
                                                   >> 3600                         opp-19200000 {
                                                   >> 3601                                 opp-hz = /bits/ 64 <19200000>;
                                                   >> 3602                                 required-opps = <&rpmhpd_opp_min_svs>;
                                                   >> 3603                         };
                                                   >> 3604 
                                                   >> 3605                         opp-100000000 {
                                                   >> 3606                                 opp-hz = /bits/ 64 <100000000>;
                                                   >> 3607                                 required-opps = <&rpmhpd_opp_low_svs>;
                                                   >> 3608                         };
                                                   >> 3609 
                                                   >> 3610                         opp-150000000 {
                                                   >> 3611                                 opp-hz = /bits/ 64 <150000000>;
                                                   >> 3612                                 required-opps = <&rpmhpd_opp_svs>;
                                                   >> 3613                         };
                                                   >> 3614 
                                                   >> 3615                         opp-300000000 {
                                                   >> 3616                                 opp-hz = /bits/ 64 <300000000>;
                                                   >> 3617                                 required-opps = <&rpmhpd_opp_nom>;
                                                   >> 3618                         };
                                                   >> 3619                 };
                                                   >> 3620 
3929                 qspi: spi@88df000 {              3621                 qspi: spi@88df000 {
3930                         compatible = "qcom,sd    3622                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931                         reg = <0 0x088df000 0    3623                         reg = <0 0x088df000 0 0x600>;
3932                         iommus = <&apps_smmu  << 
3933                         #address-cells = <1>;    3624                         #address-cells = <1>;
3934                         #size-cells = <0>;       3625                         #size-cells = <0>;
3935                         interrupts = <GIC_SPI    3626                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936                         clocks = <&gcc GCC_QS    3627                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937                                  <&gcc GCC_QS    3628                                  <&gcc GCC_QSPI_CORE_CLK>;
3938                         clock-names = "iface"    3629                         clock-names = "iface", "core";
3939                         power-domains = <&rpm    3630                         power-domains = <&rpmhpd SDM845_CX>;
3940                         operating-points-v2 =    3631                         operating-points-v2 = <&qspi_opp_table>;
3941                         status = "disabled";     3632                         status = "disabled";
3942                 };                               3633                 };
3943                                                  3634 
3944                 slim: slim-ngd@171c0000 {     !! 3635                 slim: slim@171c0000 {
3945                         compatible = "qcom,sl    3636                         compatible = "qcom,slim-ngd-v2.1.0";
3946                         reg = <0 0x171c0000 0    3637                         reg = <0 0x171c0000 0 0x2c000>;
3947                         interrupts = <GIC_SPI    3638                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948                                                  3639 
3949                         dmas = <&slimbam 3>,  !! 3640                         qcom,apps-ch-pipes = <0x780000>;
3950                         dma-names = "rx", "tx !! 3641                         qcom,ea-pc = <0x270>;
                                                   >> 3642                         status = "okay";
                                                   >> 3643                         dmas =  <&slimbam 3>, <&slimbam 4>,
                                                   >> 3644                                 <&slimbam 5>, <&slimbam 6>;
                                                   >> 3645                         dma-names = "rx", "tx", "tx2", "rx2";
3951                                                  3646 
3952                         iommus = <&apps_smmu     3647                         iommus = <&apps_smmu 0x1806 0x0>;
3953                         #address-cells = <1>;    3648                         #address-cells = <1>;
3954                         #size-cells = <0>;       3649                         #size-cells = <0>;
3955                         status = "disabled";  !! 3650 
                                                   >> 3651                         ngd@1 {
                                                   >> 3652                                 reg = <1>;
                                                   >> 3653                                 #address-cells = <2>;
                                                   >> 3654                                 #size-cells = <0>;
                                                   >> 3655 
                                                   >> 3656                                 wcd9340_ifd: ifd@0{
                                                   >> 3657                                         compatible = "slim217,250";
                                                   >> 3658                                         reg  = <0 0>;
                                                   >> 3659                                 };
                                                   >> 3660 
                                                   >> 3661                                 wcd9340: codec@1{
                                                   >> 3662                                         compatible = "slim217,250";
                                                   >> 3663                                         reg  = <1 0>;
                                                   >> 3664                                         slim-ifc-dev  = <&wcd9340_ifd>;
                                                   >> 3665 
                                                   >> 3666                                         #sound-dai-cells = <1>;
                                                   >> 3667 
                                                   >> 3668                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 3669                                         interrupt-controller;
                                                   >> 3670                                         #interrupt-cells = <1>;
                                                   >> 3671 
                                                   >> 3672                                         #clock-cells = <0>;
                                                   >> 3673                                         clock-frequency = <9600000>;
                                                   >> 3674                                         clock-output-names = "mclk";
                                                   >> 3675                                         qcom,micbias1-microvolt = <1800000>;
                                                   >> 3676                                         qcom,micbias2-microvolt = <1800000>;
                                                   >> 3677                                         qcom,micbias3-microvolt = <1800000>;
                                                   >> 3678                                         qcom,micbias4-microvolt = <1800000>;
                                                   >> 3679 
                                                   >> 3680                                         #address-cells = <1>;
                                                   >> 3681                                         #size-cells = <1>;
                                                   >> 3682 
                                                   >> 3683                                         wcdgpio: gpio-controller@42 {
                                                   >> 3684                                                 compatible = "qcom,wcd9340-gpio";
                                                   >> 3685                                                 gpio-controller;
                                                   >> 3686                                                 #gpio-cells = <2>;
                                                   >> 3687                                                 reg = <0x42 0x2>;
                                                   >> 3688                                         };
                                                   >> 3689 
                                                   >> 3690                                         swm: swm@c85 {
                                                   >> 3691                                                 compatible = "qcom,soundwire-v1.3.0";
                                                   >> 3692                                                 reg = <0xc85 0x40>;
                                                   >> 3693                                                 interrupts-extended = <&wcd9340 20>;
                                                   >> 3694 
                                                   >> 3695                                                 qcom,dout-ports = <6>;
                                                   >> 3696                                                 qcom,din-ports  = <2>;
                                                   >> 3697                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
                                                   >> 3698                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
                                                   >> 3699                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
                                                   >> 3700 
                                                   >> 3701                                                 #sound-dai-cells = <1>;
                                                   >> 3702                                                 clocks = <&wcd9340>;
                                                   >> 3703                                                 clock-names = "iface";
                                                   >> 3704                                                 #address-cells = <2>;
                                                   >> 3705                                                 #size-cells = <0>;
                                                   >> 3706 
                                                   >> 3707 
                                                   >> 3708                                         };
                                                   >> 3709                                 };
                                                   >> 3710                         };
3956                 };                               3711                 };
3957                                                  3712 
3958                 lmh_cluster1: lmh@17d70800 {     3713                 lmh_cluster1: lmh@17d70800 {
3959                         compatible = "qcom,sd    3714                         compatible = "qcom,sdm845-lmh";
3960                         reg = <0 0x17d70800 0    3715                         reg = <0 0x17d70800 0 0x400>;
3961                         interrupts = <GIC_SPI    3716                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962                         cpus = <&CPU4>;          3717                         cpus = <&CPU4>;
3963                         qcom,lmh-temp-arm-mil    3718                         qcom,lmh-temp-arm-millicelsius = <65000>;
3964                         qcom,lmh-temp-low-mil    3719                         qcom,lmh-temp-low-millicelsius = <94500>;
3965                         qcom,lmh-temp-high-mi    3720                         qcom,lmh-temp-high-millicelsius = <95000>;
3966                         interrupt-controller;    3721                         interrupt-controller;
3967                         #interrupt-cells = <1    3722                         #interrupt-cells = <1>;
3968                 };                               3723                 };
3969                                                  3724 
3970                 lmh_cluster0: lmh@17d78800 {     3725                 lmh_cluster0: lmh@17d78800 {
3971                         compatible = "qcom,sd    3726                         compatible = "qcom,sdm845-lmh";
3972                         reg = <0 0x17d78800 0    3727                         reg = <0 0x17d78800 0 0x400>;
3973                         interrupts = <GIC_SPI    3728                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974                         cpus = <&CPU0>;          3729                         cpus = <&CPU0>;
3975                         qcom,lmh-temp-arm-mil    3730                         qcom,lmh-temp-arm-millicelsius = <65000>;
3976                         qcom,lmh-temp-low-mil    3731                         qcom,lmh-temp-low-millicelsius = <94500>;
3977                         qcom,lmh-temp-high-mi    3732                         qcom,lmh-temp-high-millicelsius = <95000>;
3978                         interrupt-controller;    3733                         interrupt-controller;
3979                         #interrupt-cells = <1    3734                         #interrupt-cells = <1>;
3980                 };                               3735                 };
3981                                                  3736 
                                                   >> 3737                 sound: sound {
                                                   >> 3738                 };
                                                   >> 3739 
3982                 usb_1_hsphy: phy@88e2000 {       3740                 usb_1_hsphy: phy@88e2000 {
3983                         compatible = "qcom,sd    3741                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984                         reg = <0 0x088e2000 0    3742                         reg = <0 0x088e2000 0 0x400>;
3985                         status = "disabled";     3743                         status = "disabled";
3986                         #phy-cells = <0>;        3744                         #phy-cells = <0>;
3987                                                  3745 
3988                         clocks = <&gcc GCC_US    3746                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989                                  <&rpmhcc RPM    3747                                  <&rpmhcc RPMH_CXO_CLK>;
3990                         clock-names = "cfg_ah    3748                         clock-names = "cfg_ahb", "ref";
3991                                                  3749 
3992                         resets = <&gcc GCC_QU    3750                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993                                                  3751 
3994                         nvmem-cells = <&qusb2    3752                         nvmem-cells = <&qusb2p_hstx_trim>;
3995                 };                               3753                 };
3996                                                  3754 
3997                 usb_2_hsphy: phy@88e3000 {       3755                 usb_2_hsphy: phy@88e3000 {
3998                         compatible = "qcom,sd    3756                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999                         reg = <0 0x088e3000 0    3757                         reg = <0 0x088e3000 0 0x400>;
4000                         status = "disabled";     3758                         status = "disabled";
4001                         #phy-cells = <0>;        3759                         #phy-cells = <0>;
4002                                                  3760 
4003                         clocks = <&gcc GCC_US    3761                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004                                  <&rpmhcc RPM    3762                                  <&rpmhcc RPMH_CXO_CLK>;
4005                         clock-names = "cfg_ah    3763                         clock-names = "cfg_ahb", "ref";
4006                                                  3764 
4007                         resets = <&gcc GCC_QU    3765                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008                                                  3766 
4009                         nvmem-cells = <&qusb2    3767                         nvmem-cells = <&qusb2s_hstx_trim>;
4010                 };                               3768                 };
4011                                                  3769 
4012                 usb_1_qmpphy: phy@88e8000 {   !! 3770                 usb_1_qmpphy: phy@88e9000 {
4013                         compatible = "qcom,sd !! 3771                         compatible = "qcom,sdm845-qmp-usb3-phy";
4014                         reg = <0 0x088e8000 0 !! 3772                         reg = <0 0x088e9000 0 0x18c>,
                                                   >> 3773                               <0 0x088e8000 0 0x10>;
4015                         status = "disabled";     3774                         status = "disabled";
                                                   >> 3775                         #address-cells = <2>;
                                                   >> 3776                         #size-cells = <2>;
                                                   >> 3777                         ranges;
4016                                                  3778 
4017                         clocks = <&gcc GCC_US    3779                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
                                                   >> 3780                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018                                  <&gcc GCC_US    3781                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019                                  <&gcc GCC_US !! 3782                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020                                  <&gcc GCC_US !! 3783                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021                                  <&gcc GCC_US << 
4022                         clock-names = "aux",  << 
4023                                       "ref",  << 
4024                                       "com_au << 
4025                                       "usb3_p << 
4026                                       "cfg_ah << 
4027                                                  3784 
4028                         resets = <&gcc GCC_US !! 3785                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029                                  <&gcc GCC_US !! 3786                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030                         reset-names = "phy",     3787                         reset-names = "phy", "common";
4031                                                  3788 
4032                         #clock-cells = <1>;   !! 3789                         usb_1_ssphy: phy@88e9200 {
4033                         #phy-cells = <1>;     !! 3790                                 reg = <0 0x088e9200 0 0x128>,
4034                         orientation-switch;   !! 3791                                       <0 0x088e9400 0 0x200>,
4035                                               !! 3792                                       <0 0x088e9c00 0 0x218>,
4036                         ports {               !! 3793                                       <0 0x088e9600 0 0x128>,
4037                                 #address-cell !! 3794                                       <0 0x088e9800 0 0x200>,
4038                                 #size-cells = !! 3795                                       <0 0x088e9a00 0 0x100>;
4039                                               !! 3796                                 #clock-cells = <0>;
4040                                 port@0 {      !! 3797                                 #phy-cells = <0>;
4041                                         reg = !! 3798                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042                                               !! 3799                                 clock-names = "pipe0";
4043                                         usb_1 !! 3800                                 clock-output-names = "usb3_phy_pipe_clk_src";
4044                                         };    << 
4045                                 };            << 
4046                                               << 
4047                                 port@1 {      << 
4048                                         reg = << 
4049                                               << 
4050                                         usb_1 << 
4051                                               << 
4052                                         };    << 
4053                                 };            << 
4054                                               << 
4055                                 port@2 {      << 
4056                                         reg = << 
4057                                               << 
4058                                         usb_1 << 
4059                                               << 
4060                                         };    << 
4061                                 };            << 
4062                         };                       3801                         };
4063                 };                               3802                 };
4064                                                  3803 
4065                 usb_2_qmpphy: phy@88eb000 {      3804                 usb_2_qmpphy: phy@88eb000 {
4066                         compatible = "qcom,sd    3805                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067                         reg = <0 0x088eb000 0 !! 3806                         reg = <0 0x088eb000 0 0x18c>;
                                                   >> 3807                         status = "disabled";
                                                   >> 3808                         #address-cells = <2>;
                                                   >> 3809                         #size-cells = <2>;
                                                   >> 3810                         ranges;
4068                                                  3811 
4069                         clocks = <&gcc GCC_US    3812                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070                                  <&gcc GCC_US    3813                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071                                  <&gcc GCC_US    3814                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072                                  <&gcc GCC_US !! 3815                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073                                  <&gcc GCC_US !! 3816                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074                         clock-names = "aux",  << 
4075                                       "cfg_ah << 
4076                                       "ref",  << 
4077                                       "com_au << 
4078                                       "pipe"; << 
4079                         clock-output-names =  << 
4080                         #clock-cells = <0>;   << 
4081                         #phy-cells = <0>;     << 
4082                                                  3817 
4083                         resets = <&gcc GCC_US !! 3818                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084                                  <&gcc GCC_US !! 3819                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
4085                         reset-names = "phy",  !! 3820                         reset-names = "phy", "common";
4086                                       "phy_ph << 
4087                                                  3821 
4088                         status = "disabled";  !! 3822                         usb_2_ssphy: phy@88eb200 {
                                                   >> 3823                                 reg = <0 0x088eb200 0 0x128>,
                                                   >> 3824                                       <0 0x088eb400 0 0x1fc>,
                                                   >> 3825                                       <0 0x088eb800 0 0x218>,
                                                   >> 3826                                       <0 0x088eb600 0 0x70>;
                                                   >> 3827                                 #clock-cells = <0>;
                                                   >> 3828                                 #phy-cells = <0>;
                                                   >> 3829                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
                                                   >> 3830                                 clock-names = "pipe0";
                                                   >> 3831                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
                                                   >> 3832                         };
4089                 };                               3833                 };
4090                                                  3834 
4091                 usb_1: usb@a6f8800 {             3835                 usb_1: usb@a6f8800 {
4092                         compatible = "qcom,sd    3836                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093                         reg = <0 0x0a6f8800 0    3837                         reg = <0 0x0a6f8800 0 0x400>;
4094                         status = "disabled";     3838                         status = "disabled";
4095                         #address-cells = <2>;    3839                         #address-cells = <2>;
4096                         #size-cells = <2>;       3840                         #size-cells = <2>;
4097                         ranges;                  3841                         ranges;
4098                         dma-ranges;              3842                         dma-ranges;
4099                                                  3843 
4100                         clocks = <&gcc GCC_CF    3844                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101                                  <&gcc GCC_US    3845                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102                                  <&gcc GCC_AG    3846                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103                                  <&gcc GCC_US !! 3847                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104                                  <&gcc GCC_US !! 3848                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105                         clock-names = "cfg_no !! 3849                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106                                       "core", !! 3850                                       "sleep";
4107                                       "iface" << 
4108                                       "sleep" << 
4109                                       "mock_u << 
4110                                                  3851 
4111                         assigned-clocks = <&g    3852                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112                                           <&g    3853                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113                         assigned-clock-rates     3854                         assigned-clock-rates = <19200000>, <150000000>;
4114                                                  3855 
4115                         interrupts-extended = !! 3856                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116                                               !! 3857                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117                                               !! 3858                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118                                               !! 3859                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119                                               !! 3860                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120                         interrupt-names = "pw !! 3861                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
4121                                           "hs << 
4122                                           "dp << 
4123                                           "dm << 
4124                                           "ss << 
4125                                                  3862 
4126                         power-domains = <&gcc    3863                         power-domains = <&gcc USB30_PRIM_GDSC>;
4127                                                  3864 
4128                         resets = <&gcc GCC_US    3865                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4129                                                  3866 
4130                         interconnects = <&agg    3867                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131                                         <&gla    3868                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132                         interconnect-names =     3869                         interconnect-names = "usb-ddr", "apps-usb";
4133                                                  3870 
4134                         usb_1_dwc3: usb@a6000 !! 3871                         usb_1_dwc3: dwc3@a600000 {
4135                                 compatible =     3872                                 compatible = "snps,dwc3";
4136                                 reg = <0 0x0a    3873                                 reg = <0 0x0a600000 0 0xcd00>;
4137                                 interrupts =     3874                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138                                 iommus = <&ap    3875                                 iommus = <&apps_smmu 0x740 0>;
4139                                 snps,dis_u2_s    3876                                 snps,dis_u2_susphy_quirk;
4140                                 snps,dis_enbl    3877                                 snps,dis_enblslpm_quirk;
4141                                 snps,parkmode !! 3878                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142                                 phys = <&usb_ << 
4143                                 phy-names = "    3879                                 phy-names = "usb2-phy", "usb3-phy";
4144                                               << 
4145                                 ports {       << 
4146                                         #addr << 
4147                                         #size << 
4148                                               << 
4149                                         port@ << 
4150                                               << 
4151                                               << 
4152                                               << 
4153                                               << 
4154                                         };    << 
4155                                               << 
4156                                         port@ << 
4157                                               << 
4158                                               << 
4159                                               << 
4160                                               << 
4161                                               << 
4162                                         };    << 
4163                                 };            << 
4164                         };                       3880                         };
4165                 };                               3881                 };
4166                                                  3882 
4167                 usb_2: usb@a8f8800 {             3883                 usb_2: usb@a8f8800 {
4168                         compatible = "qcom,sd    3884                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169                         reg = <0 0x0a8f8800 0    3885                         reg = <0 0x0a8f8800 0 0x400>;
4170                         status = "disabled";     3886                         status = "disabled";
4171                         #address-cells = <2>;    3887                         #address-cells = <2>;
4172                         #size-cells = <2>;       3888                         #size-cells = <2>;
4173                         ranges;                  3889                         ranges;
4174                         dma-ranges;              3890                         dma-ranges;
4175                                                  3891 
4176                         clocks = <&gcc GCC_CF    3892                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177                                  <&gcc GCC_US    3893                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178                                  <&gcc GCC_AG    3894                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179                                  <&gcc GCC_US !! 3895                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180                                  <&gcc GCC_US !! 3896                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181                         clock-names = "cfg_no !! 3897                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182                                       "core", !! 3898                                       "sleep";
4183                                       "iface" << 
4184                                       "sleep" << 
4185                                       "mock_u << 
4186                                                  3899 
4187                         assigned-clocks = <&g    3900                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188                                           <&g    3901                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189                         assigned-clock-rates     3902                         assigned-clock-rates = <19200000>, <150000000>;
4190                                                  3903 
4191                         interrupts-extended = !! 3904                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192                                               !! 3905                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193                                               !! 3906                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194                                               !! 3907                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195                                               !! 3908                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196                         interrupt-names = "pw !! 3909                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
4197                                           "hs << 
4198                                           "dp << 
4199                                           "dm << 
4200                                           "ss << 
4201                                                  3910 
4202                         power-domains = <&gcc    3911                         power-domains = <&gcc USB30_SEC_GDSC>;
4203                                                  3912 
4204                         resets = <&gcc GCC_US    3913                         resets = <&gcc GCC_USB30_SEC_BCR>;
4205                                                  3914 
4206                         interconnects = <&agg    3915                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207                                         <&gla    3916                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208                         interconnect-names =     3917                         interconnect-names = "usb-ddr", "apps-usb";
4209                                                  3918 
4210                         usb_2_dwc3: usb@a8000 !! 3919                         usb_2_dwc3: dwc3@a800000 {
4211                                 compatible =     3920                                 compatible = "snps,dwc3";
4212                                 reg = <0 0x0a    3921                                 reg = <0 0x0a800000 0 0xcd00>;
4213                                 interrupts =     3922                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214                                 iommus = <&ap    3923                                 iommus = <&apps_smmu 0x760 0>;
4215                                 snps,dis_u2_s    3924                                 snps,dis_u2_susphy_quirk;
4216                                 snps,dis_enbl    3925                                 snps,dis_enblslpm_quirk;
4217                                 snps,parkmode !! 3926                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218                                 phys = <&usb_ << 
4219                                 phy-names = "    3927                                 phy-names = "usb2-phy", "usb3-phy";
4220                         };                       3928                         };
4221                 };                               3929                 };
4222                                                  3930 
4223                 venus: video-codec@aa00000 {     3931                 venus: video-codec@aa00000 {
4224                         compatible = "qcom,sd    3932                         compatible = "qcom,sdm845-venus-v2";
4225                         reg = <0 0x0aa00000 0    3933                         reg = <0 0x0aa00000 0 0xff000>;
4226                         interrupts = <GIC_SPI    3934                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227                         power-domains = <&vid    3935                         power-domains = <&videocc VENUS_GDSC>,
4228                                         <&vid    3936                                         <&videocc VCODEC0_GDSC>,
4229                                         <&vid    3937                                         <&videocc VCODEC1_GDSC>,
4230                                         <&rpm    3938                                         <&rpmhpd SDM845_CX>;
4231                         power-domain-names =     3939                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232                         operating-points-v2 =    3940                         operating-points-v2 = <&venus_opp_table>;
4233                         clocks = <&videocc VI    3941                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234                                  <&videocc VI    3942                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235                                  <&videocc VI    3943                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236                                  <&videocc VI    3944                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237                                  <&videocc VI    3945                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238                                  <&videocc VI    3946                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239                                  <&videocc VI    3947                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240                         clock-names = "core",    3948                         clock-names = "core", "iface", "bus",
4241                                       "vcodec    3949                                       "vcodec0_core", "vcodec0_bus",
4242                                       "vcodec    3950                                       "vcodec1_core", "vcodec1_bus";
4243                         iommus = <&apps_smmu     3951                         iommus = <&apps_smmu 0x10a0 0x8>,
4244                                  <&apps_smmu     3952                                  <&apps_smmu 0x10b0 0x0>;
4245                         memory-region = <&ven    3953                         memory-region = <&venus_mem>;
4246                         interconnects = <&mms    3954                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247                                         <&gla    3955                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248                         interconnect-names =     3956                         interconnect-names = "video-mem", "cpu-cfg";
4249                                                  3957 
4250                         status = "disabled";     3958                         status = "disabled";
4251                                                  3959 
4252                         video-core0 {            3960                         video-core0 {
4253                                 compatible =     3961                                 compatible = "venus-decoder";
4254                         };                       3962                         };
4255                                                  3963 
4256                         video-core1 {            3964                         video-core1 {
4257                                 compatible =     3965                                 compatible = "venus-encoder";
4258                         };                       3966                         };
4259                                                  3967 
4260                         venus_opp_table: opp- !! 3968                         venus_opp_table: venus-opp-table {
4261                                 compatible =     3969                                 compatible = "operating-points-v2";
4262                                                  3970 
4263                                 opp-100000000    3971                                 opp-100000000 {
4264                                         opp-h    3972                                         opp-hz = /bits/ 64 <100000000>;
4265                                         requi    3973                                         required-opps = <&rpmhpd_opp_min_svs>;
4266                                 };               3974                                 };
4267                                                  3975 
4268                                 opp-200000000    3976                                 opp-200000000 {
4269                                         opp-h    3977                                         opp-hz = /bits/ 64 <200000000>;
4270                                         requi    3978                                         required-opps = <&rpmhpd_opp_low_svs>;
4271                                 };               3979                                 };
4272                                                  3980 
4273                                 opp-320000000    3981                                 opp-320000000 {
4274                                         opp-h    3982                                         opp-hz = /bits/ 64 <320000000>;
4275                                         requi    3983                                         required-opps = <&rpmhpd_opp_svs>;
4276                                 };               3984                                 };
4277                                                  3985 
4278                                 opp-380000000    3986                                 opp-380000000 {
4279                                         opp-h    3987                                         opp-hz = /bits/ 64 <380000000>;
4280                                         requi    3988                                         required-opps = <&rpmhpd_opp_svs_l1>;
4281                                 };               3989                                 };
4282                                                  3990 
4283                                 opp-444000000    3991                                 opp-444000000 {
4284                                         opp-h    3992                                         opp-hz = /bits/ 64 <444000000>;
4285                                         requi    3993                                         required-opps = <&rpmhpd_opp_nom>;
4286                                 };               3994                                 };
4287                                                  3995 
4288                                 opp-533000097    3996                                 opp-533000097 {
4289                                         opp-h    3997                                         opp-hz = /bits/ 64 <533000097>;
4290                                         requi    3998                                         required-opps = <&rpmhpd_opp_turbo>;
4291                                 };               3999                                 };
4292                         };                       4000                         };
4293                 };                               4001                 };
4294                                                  4002 
4295                 videocc: clock-controller@ab0    4003                 videocc: clock-controller@ab00000 {
4296                         compatible = "qcom,sd    4004                         compatible = "qcom,sdm845-videocc";
4297                         reg = <0 0x0ab00000 0    4005                         reg = <0 0x0ab00000 0 0x10000>;
4298                         clocks = <&rpmhcc RPM    4006                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4299                         clock-names = "bi_tcx    4007                         clock-names = "bi_tcxo";
4300                         #clock-cells = <1>;      4008                         #clock-cells = <1>;
4301                         #power-domain-cells =    4009                         #power-domain-cells = <1>;
4302                         #reset-cells = <1>;      4010                         #reset-cells = <1>;
4303                 };                               4011                 };
4304                                                  4012 
4305                 camss: camss@acb3000 {        !! 4013                 camss: camss@a00000 {
4306                         compatible = "qcom,sd    4014                         compatible = "qcom,sdm845-camss";
4307                                                  4015 
4308                         reg = <0 0x0acb3000 0 !! 4016                         reg = <0 0xacb3000 0 0x1000>,
4309                                 <0 0x0acba000 !! 4017                                 <0 0xacba000 0 0x1000>,
4310                                 <0 0x0acc8000 !! 4018                                 <0 0xacc8000 0 0x1000>,
4311                                 <0 0x0ac65000 !! 4019                                 <0 0xac65000 0 0x1000>,
4312                                 <0 0x0ac66000 !! 4020                                 <0 0xac66000 0 0x1000>,
4313                                 <0 0x0ac67000 !! 4021                                 <0 0xac67000 0 0x1000>,
4314                                 <0 0x0ac68000 !! 4022                                 <0 0xac68000 0 0x1000>,
4315                                 <0 0x0acaf000 !! 4023                                 <0 0xacaf000 0 0x4000>,
4316                                 <0 0x0acb6000 !! 4024                                 <0 0xacb6000 0 0x4000>,
4317                                 <0 0x0acc4000 !! 4025                                 <0 0xacc4000 0 0x4000>;
4318                         reg-names = "csid0",     4026                         reg-names = "csid0",
4319                                 "csid1",         4027                                 "csid1",
4320                                 "csid2",         4028                                 "csid2",
4321                                 "csiphy0",       4029                                 "csiphy0",
4322                                 "csiphy1",       4030                                 "csiphy1",
4323                                 "csiphy2",       4031                                 "csiphy2",
4324                                 "csiphy3",       4032                                 "csiphy3",
4325                                 "vfe0",          4033                                 "vfe0",
4326                                 "vfe1",          4034                                 "vfe1",
4327                                 "vfe_lite";      4035                                 "vfe_lite";
4328                                                  4036 
4329                         interrupts = <GIC_SPI    4037                         interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330                                 <GIC_SPI 466     4038                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331                                 <GIC_SPI 468     4039                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332                                 <GIC_SPI 477     4040                                 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333                                 <GIC_SPI 478     4041                                 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334                                 <GIC_SPI 479     4042                                 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335                                 <GIC_SPI 448     4043                                 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336                                 <GIC_SPI 465     4044                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337                                 <GIC_SPI 467     4045                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338                                 <GIC_SPI 469     4046                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339                         interrupt-names = "cs    4047                         interrupt-names = "csid0",
4340                                 "csid1",         4048                                 "csid1",
4341                                 "csid2",         4049                                 "csid2",
4342                                 "csiphy0",       4050                                 "csiphy0",
4343                                 "csiphy1",       4051                                 "csiphy1",
4344                                 "csiphy2",       4052                                 "csiphy2",
4345                                 "csiphy3",       4053                                 "csiphy3",
4346                                 "vfe0",          4054                                 "vfe0",
4347                                 "vfe1",          4055                                 "vfe1",
4348                                 "vfe_lite";      4056                                 "vfe_lite";
4349                                                  4057 
4350                         power-domains = <&clo    4058                         power-domains = <&clock_camcc IFE_0_GDSC>,
4351                                 <&clock_camcc    4059                                 <&clock_camcc IFE_1_GDSC>,
4352                                 <&clock_camcc    4060                                 <&clock_camcc TITAN_TOP_GDSC>;
4353                                                  4061 
4354                         clocks = <&clock_camc    4062                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355                                 <&clock_camcc    4063                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356                                 <&clock_camcc    4064                                 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357                                 <&clock_camcc    4065                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358                                 <&clock_camcc    4066                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359                                 <&clock_camcc    4067                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360                                 <&clock_camcc    4068                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361                                 <&clock_camcc    4069                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362                                 <&clock_camcc    4070                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363                                 <&clock_camcc    4071                                 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364                                 <&clock_camcc    4072                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365                                 <&clock_camcc    4073                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366                                 <&clock_camcc    4074                                 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367                                 <&clock_camcc    4075                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368                                 <&clock_camcc    4076                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369                                 <&clock_camcc    4077                                 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370                                 <&clock_camcc    4078                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371                                 <&clock_camcc    4079                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372                                 <&clock_camcc    4080                                 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373                                 <&clock_camcc    4081                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374                                 <&clock_camcc    4082                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375                                 <&gcc GCC_CAM    4083                                 <&gcc GCC_CAMERA_AHB_CLK>,
4376                                 <&gcc GCC_CAM    4084                                 <&gcc GCC_CAMERA_AXI_CLK>,
4377                                 <&clock_camcc    4085                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378                                 <&clock_camcc    4086                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379                                 <&clock_camcc    4087                                 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380                                 <&clock_camcc    4088                                 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381                                 <&clock_camcc    4089                                 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382                                 <&clock_camcc    4090                                 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383                                 <&clock_camcc    4091                                 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384                                 <&clock_camcc    4092                                 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385                                 <&clock_camcc    4093                                 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386                                 <&clock_camcc    4094                                 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387                                 <&clock_camcc    4095                                 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388                                 <&clock_camcc    4096                                 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389                                 <&clock_camcc    4097                                 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390                         clock-names = "camnoc    4098                         clock-names = "camnoc_axi",
4391                                 "cpas_ahb",      4099                                 "cpas_ahb",
4392                                 "cphy_rx_src"    4100                                 "cphy_rx_src",
4393                                 "csi0",          4101                                 "csi0",
4394                                 "csi0_src",      4102                                 "csi0_src",
4395                                 "csi1",          4103                                 "csi1",
4396                                 "csi1_src",      4104                                 "csi1_src",
4397                                 "csi2",          4105                                 "csi2",
4398                                 "csi2_src",      4106                                 "csi2_src",
4399                                 "csiphy0",       4107                                 "csiphy0",
4400                                 "csiphy0_time    4108                                 "csiphy0_timer",
4401                                 "csiphy0_time    4109                                 "csiphy0_timer_src",
4402                                 "csiphy1",       4110                                 "csiphy1",
4403                                 "csiphy1_time    4111                                 "csiphy1_timer",
4404                                 "csiphy1_time    4112                                 "csiphy1_timer_src",
4405                                 "csiphy2",       4113                                 "csiphy2",
4406                                 "csiphy2_time    4114                                 "csiphy2_timer",
4407                                 "csiphy2_time    4115                                 "csiphy2_timer_src",
4408                                 "csiphy3",       4116                                 "csiphy3",
4409                                 "csiphy3_time    4117                                 "csiphy3_timer",
4410                                 "csiphy3_time    4118                                 "csiphy3_timer_src",
4411                                 "gcc_camera_a    4119                                 "gcc_camera_ahb",
4412                                 "gcc_camera_a    4120                                 "gcc_camera_axi",
4413                                 "slow_ahb_src    4121                                 "slow_ahb_src",
4414                                 "soc_ahb",       4122                                 "soc_ahb",
4415                                 "vfe0_axi",      4123                                 "vfe0_axi",
4416                                 "vfe0",          4124                                 "vfe0",
4417                                 "vfe0_cphy_rx    4125                                 "vfe0_cphy_rx",
4418                                 "vfe0_src",      4126                                 "vfe0_src",
4419                                 "vfe1_axi",      4127                                 "vfe1_axi",
4420                                 "vfe1",          4128                                 "vfe1",
4421                                 "vfe1_cphy_rx    4129                                 "vfe1_cphy_rx",
4422                                 "vfe1_src",      4130                                 "vfe1_src",
4423                                 "vfe_lite",      4131                                 "vfe_lite",
4424                                 "vfe_lite_cph    4132                                 "vfe_lite_cphy_rx",
4425                                 "vfe_lite_src    4133                                 "vfe_lite_src";
4426                                                  4134 
4427                         iommus = <&apps_smmu     4135                         iommus = <&apps_smmu 0x0808 0x0>,
4428                                  <&apps_smmu     4136                                  <&apps_smmu 0x0810 0x8>,
4429                                  <&apps_smmu     4137                                  <&apps_smmu 0x0c08 0x0>,
4430                                  <&apps_smmu     4138                                  <&apps_smmu 0x0c10 0x8>;
4431                                                  4139 
4432                         status = "disabled";     4140                         status = "disabled";
4433                                                  4141 
4434                         ports {                  4142                         ports {
4435                                 #address-cell    4143                                 #address-cells = <1>;
4436                                 #size-cells =    4144                                 #size-cells = <0>;
4437                                               << 
4438                                 port@0 {      << 
4439                                         reg = << 
4440                                 };            << 
4441                                               << 
4442                                 port@1 {      << 
4443                                         reg = << 
4444                                 };            << 
4445                                               << 
4446                                 port@2 {      << 
4447                                         reg = << 
4448                                 };            << 
4449                                               << 
4450                                 port@3 {      << 
4451                                         reg = << 
4452                                 };            << 
4453                         };                       4145                         };
4454                 };                               4146                 };
4455                                                  4147 
4456                 cci: cci@ac4a000 {               4148                 cci: cci@ac4a000 {
4457                         compatible = "qcom,sd !! 4149                         compatible = "qcom,sdm845-cci";
4458                         #address-cells = <1>;    4150                         #address-cells = <1>;
4459                         #size-cells = <0>;       4151                         #size-cells = <0>;
4460                                                  4152 
4461                         reg = <0 0x0ac4a000 0    4153                         reg = <0 0x0ac4a000 0 0x4000>;
4462                         interrupts = <GIC_SPI    4154                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463                         power-domains = <&clo    4155                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464                                                  4156 
4465                         clocks = <&clock_camc    4157                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466                                 <&clock_camcc    4158                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467                                 <&clock_camcc    4159                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468                                 <&clock_camcc    4160                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469                                 <&clock_camcc    4161                                 <&clock_camcc CAM_CC_CCI_CLK>,
4470                                 <&clock_camcc    4162                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471                         clock-names = "camnoc    4163                         clock-names = "camnoc_axi",
4472                                 "soc_ahb",       4164                                 "soc_ahb",
4473                                 "slow_ahb_src    4165                                 "slow_ahb_src",
4474                                 "cpas_ahb",      4166                                 "cpas_ahb",
4475                                 "cci",           4167                                 "cci",
4476                                 "cci_src";       4168                                 "cci_src";
4477                                                  4169 
4478                         assigned-clocks = <&c    4170                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479                                 <&clock_camcc    4171                                 <&clock_camcc CAM_CC_CCI_CLK>;
4480                         assigned-clock-rates     4172                         assigned-clock-rates = <80000000>, <37500000>;
4481                                                  4173 
4482                         pinctrl-names = "defa    4174                         pinctrl-names = "default", "sleep";
4483                         pinctrl-0 = <&cci0_de    4175                         pinctrl-0 = <&cci0_default &cci1_default>;
4484                         pinctrl-1 = <&cci0_sl    4176                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485                                                  4177 
4486                         status = "disabled";     4178                         status = "disabled";
4487                                                  4179 
4488                         cci_i2c0: i2c-bus@0 {    4180                         cci_i2c0: i2c-bus@0 {
4489                                 reg = <0>;       4181                                 reg = <0>;
4490                                 clock-frequen    4182                                 clock-frequency = <1000000>;
4491                                 #address-cell    4183                                 #address-cells = <1>;
4492                                 #size-cells =    4184                                 #size-cells = <0>;
4493                         };                       4185                         };
4494                                                  4186 
4495                         cci_i2c1: i2c-bus@1 {    4187                         cci_i2c1: i2c-bus@1 {
4496                                 reg = <1>;       4188                                 reg = <1>;
4497                                 clock-frequen    4189                                 clock-frequency = <1000000>;
4498                                 #address-cell    4190                                 #address-cells = <1>;
4499                                 #size-cells =    4191                                 #size-cells = <0>;
4500                         };                       4192                         };
4501                 };                               4193                 };
4502                                                  4194 
4503                 clock_camcc: clock-controller    4195                 clock_camcc: clock-controller@ad00000 {
4504                         compatible = "qcom,sd    4196                         compatible = "qcom,sdm845-camcc";
4505                         reg = <0 0x0ad00000 0    4197                         reg = <0 0x0ad00000 0 0x10000>;
4506                         #clock-cells = <1>;      4198                         #clock-cells = <1>;
4507                         #reset-cells = <1>;      4199                         #reset-cells = <1>;
4508                         #power-domain-cells =    4200                         #power-domain-cells = <1>;
4509                         clocks = <&rpmhcc RPM    4201                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4510                         clock-names = "bi_tcx    4202                         clock-names = "bi_tcxo";
4511                 };                               4203                 };
4512                                                  4204 
4513                 mdss: display-subsystem@ae000 !! 4205                 dsi_opp_table: dsi-opp-table {
                                                   >> 4206                         compatible = "operating-points-v2";
                                                   >> 4207 
                                                   >> 4208                         opp-19200000 {
                                                   >> 4209                                 opp-hz = /bits/ 64 <19200000>;
                                                   >> 4210                                 required-opps = <&rpmhpd_opp_min_svs>;
                                                   >> 4211                         };
                                                   >> 4212 
                                                   >> 4213                         opp-180000000 {
                                                   >> 4214                                 opp-hz = /bits/ 64 <180000000>;
                                                   >> 4215                                 required-opps = <&rpmhpd_opp_low_svs>;
                                                   >> 4216                         };
                                                   >> 4217 
                                                   >> 4218                         opp-275000000 {
                                                   >> 4219                                 opp-hz = /bits/ 64 <275000000>;
                                                   >> 4220                                 required-opps = <&rpmhpd_opp_svs>;
                                                   >> 4221                         };
                                                   >> 4222 
                                                   >> 4223                         opp-328580000 {
                                                   >> 4224                                 opp-hz = /bits/ 64 <328580000>;
                                                   >> 4225                                 required-opps = <&rpmhpd_opp_svs_l1>;
                                                   >> 4226                         };
                                                   >> 4227 
                                                   >> 4228                         opp-358000000 {
                                                   >> 4229                                 opp-hz = /bits/ 64 <358000000>;
                                                   >> 4230                                 required-opps = <&rpmhpd_opp_nom>;
                                                   >> 4231                         };
                                                   >> 4232                 };
                                                   >> 4233 
                                                   >> 4234                 mdss: mdss@ae00000 {
4514                         compatible = "qcom,sd    4235                         compatible = "qcom,sdm845-mdss";
4515                         reg = <0 0x0ae00000 0    4236                         reg = <0 0x0ae00000 0 0x1000>;
4516                         reg-names = "mdss";      4237                         reg-names = "mdss";
4517                                                  4238 
4518                         power-domains = <&dis    4239                         power-domains = <&dispcc MDSS_GDSC>;
4519                                                  4240 
4520                         clocks = <&dispcc DIS    4241                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521                                  <&dispcc DIS    4242                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522                         clock-names = "iface"    4243                         clock-names = "iface", "core";
4523                                                  4244 
                                                   >> 4245                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
                                                   >> 4246                         assigned-clock-rates = <300000000>;
                                                   >> 4247 
4524                         interrupts = <GIC_SPI    4248                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525                         interrupt-controller;    4249                         interrupt-controller;
4526                         #interrupt-cells = <1    4250                         #interrupt-cells = <1>;
4527                                                  4251 
4528                         interconnects = <&mms    4252                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529                                         <&mms    4253                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530                         interconnect-names =     4254                         interconnect-names = "mdp0-mem", "mdp1-mem";
4531                                                  4255 
4532                         iommus = <&apps_smmu     4256                         iommus = <&apps_smmu 0x880 0x8>,
4533                                  <&apps_smmu     4257                                  <&apps_smmu 0xc80 0x8>;
4534                                                  4258 
4535                         status = "disabled";     4259                         status = "disabled";
4536                                                  4260 
4537                         #address-cells = <2>;    4261                         #address-cells = <2>;
4538                         #size-cells = <2>;       4262                         #size-cells = <2>;
4539                         ranges;                  4263                         ranges;
4540                                                  4264 
4541                         mdss_mdp: display-con !! 4265                         mdss_mdp: mdp@ae01000 {
4542                                 compatible =     4266                                 compatible = "qcom,sdm845-dpu";
4543                                 reg = <0 0x0a    4267                                 reg = <0 0x0ae01000 0 0x8f000>,
4544                                       <0 0x0a    4268                                       <0 0x0aeb0000 0 0x2008>;
4545                                 reg-names = "    4269                                 reg-names = "mdp", "vbif";
4546                                                  4270 
4547                                 clocks = <&gc    4271                                 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548                                          <&di    4272                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549                                          <&di    4273                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550                                          <&di    4274                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551                                          <&di    4275                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552                                 clock-names =    4276                                 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553                                                  4277 
4554                                 assigned-cloc !! 4278                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555                                 assigned-cloc !! 4279                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
                                                   >> 4280                                 assigned-clock-rates = <300000000>,
                                                   >> 4281                                                        <19200000>;
4556                                 operating-poi    4282                                 operating-points-v2 = <&mdp_opp_table>;
4557                                 power-domains    4283                                 power-domains = <&rpmhpd SDM845_CX>;
4558                                                  4284 
4559                                 interrupt-par    4285                                 interrupt-parent = <&mdss>;
4560                                 interrupts =  !! 4286                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4561                                                  4287 
4562                                 ports {          4288                                 ports {
4563                                         #addr    4289                                         #address-cells = <1>;
4564                                         #size    4290                                         #size-cells = <0>;
4565                                                  4291 
4566                                         port@    4292                                         port@0 {
4567                                                  4293                                                 reg = <0>;
4568                                               !! 4294                                                 dpu_intf1_out: endpoint {
4569                                               !! 4295                                                         remote-endpoint = <&dsi0_in>;
4570                                                  4296                                                 };
4571                                         };       4297                                         };
4572                                                  4298 
4573                                         port@    4299                                         port@1 {
4574                                                  4300                                                 reg = <1>;
4575                                               << 
4576                                               << 
4577                                               << 
4578                                         };    << 
4579                                               << 
4580                                         port@ << 
4581                                               << 
4582                                                  4301                                                 dpu_intf2_out: endpoint {
4583                                               !! 4302                                                         remote-endpoint = <&dsi1_in>;
4584                                                  4303                                                 };
4585                                         };       4304                                         };
4586                                 };               4305                                 };
4587                                                  4306 
4588                                 mdp_opp_table !! 4307                                 mdp_opp_table: mdp-opp-table {
4589                                         compa    4308                                         compatible = "operating-points-v2";
4590                                                  4309 
4591                                         opp-1    4310                                         opp-19200000 {
4592                                                  4311                                                 opp-hz = /bits/ 64 <19200000>;
4593                                                  4312                                                 required-opps = <&rpmhpd_opp_min_svs>;
4594                                         };       4313                                         };
4595                                                  4314 
4596                                         opp-1    4315                                         opp-171428571 {
4597                                                  4316                                                 opp-hz = /bits/ 64 <171428571>;
4598                                                  4317                                                 required-opps = <&rpmhpd_opp_low_svs>;
4599                                         };       4318                                         };
4600                                                  4319 
4601                                         opp-3    4320                                         opp-344000000 {
4602                                                  4321                                                 opp-hz = /bits/ 64 <344000000>;
4603                                                  4322                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4604                                         };       4323                                         };
4605                                                  4324 
4606                                         opp-4    4325                                         opp-430000000 {
4607                                                  4326                                                 opp-hz = /bits/ 64 <430000000>;
4608                                                  4327                                                 required-opps = <&rpmhpd_opp_nom>;
4609                                         };       4328                                         };
4610                                 };               4329                                 };
4611                         };                       4330                         };
4612                                                  4331 
4613                         mdss_dp: displayport- !! 4332                         dsi0: dsi@ae94000 {
4614                                 status = "dis !! 4333                                 compatible = "qcom,mdss-dsi-ctrl";
4615                                 compatible =  << 
4616                                               << 
4617                                 reg = <0 0x0a << 
4618                                       <0 0x0a << 
4619                                       <0 0x0a << 
4620                                       <0 0x0a << 
4621                                       <0 0x0a << 
4622                                               << 
4623                                 interrupt-par << 
4624                                 interrupts =  << 
4625                                               << 
4626                                 clocks = <&di << 
4627                                          <&di << 
4628                                          <&di << 
4629                                          <&di << 
4630                                          <&di << 
4631                                 clock-names = << 
4632                                               << 
4633                                 assigned-cloc << 
4634                                               << 
4635                                 assigned-cloc << 
4636                                               << 
4637                                 phys = <&usb_ << 
4638                                 phy-names = " << 
4639                                               << 
4640                                 operating-poi << 
4641                                 power-domains << 
4642                                               << 
4643                                 ports {       << 
4644                                         #addr << 
4645                                         #size << 
4646                                         port@ << 
4647                                               << 
4648                                               << 
4649                                               << 
4650                                               << 
4651                                         };    << 
4652                                               << 
4653                                         port@ << 
4654                                               << 
4655                                               << 
4656                                               << 
4657                                               << 
4658                                         };    << 
4659                                 };            << 
4660                                               << 
4661                                 dp_opp_table: << 
4662                                         compa << 
4663                                               << 
4664                                         opp-1 << 
4665                                               << 
4666                                               << 
4667                                         };    << 
4668                                               << 
4669                                         opp-2 << 
4670                                               << 
4671                                               << 
4672                                         };    << 
4673                                               << 
4674                                         opp-5 << 
4675                                               << 
4676                                               << 
4677                                         };    << 
4678                                               << 
4679                                         opp-8 << 
4680                                               << 
4681                                               << 
4682                                         };    << 
4683                                 };            << 
4684                         };                    << 
4685                                               << 
4686                         mdss_dsi0: dsi@ae9400 << 
4687                                 compatible =  << 
4688                                               << 
4689                                 reg = <0 0x0a    4334                                 reg = <0 0x0ae94000 0 0x400>;
4690                                 reg-names = "    4335                                 reg-names = "dsi_ctrl";
4691                                                  4336 
4692                                 interrupt-par    4337                                 interrupt-parent = <&mdss>;
4693                                 interrupts =  !! 4338                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694                                                  4339 
4695                                 clocks = <&di    4340                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696                                          <&di    4341                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697                                          <&di    4342                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698                                          <&di    4343                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699                                          <&di    4344                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700                                          <&di    4345                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701                                 clock-names =    4346                                 clock-names = "byte",
4702                                                  4347                                               "byte_intf",
4703                                                  4348                                               "pixel",
4704                                                  4349                                               "core",
4705                                                  4350                                               "iface",
4706                                                  4351                                               "bus";
4707                                 assigned-cloc    4352                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708                                 assigned-cloc !! 4353                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4709                                                  4354 
4710                                 operating-poi    4355                                 operating-points-v2 = <&dsi_opp_table>;
4711                                 power-domains    4356                                 power-domains = <&rpmhpd SDM845_CX>;
4712                                                  4357 
4713                                 phys = <&mdss !! 4358                                 phys = <&dsi0_phy>;
                                                   >> 4359                                 phy-names = "dsi";
4714                                                  4360 
4715                                 status = "dis    4361                                 status = "disabled";
4716                                                  4362 
4717                                 #address-cell    4363                                 #address-cells = <1>;
4718                                 #size-cells =    4364                                 #size-cells = <0>;
4719                                                  4365 
4720                                 ports {          4366                                 ports {
4721                                         #addr    4367                                         #address-cells = <1>;
4722                                         #size    4368                                         #size-cells = <0>;
4723                                                  4369 
4724                                         port@    4370                                         port@0 {
4725                                                  4371                                                 reg = <0>;
4726                                               !! 4372                                                 dsi0_in: endpoint {
4727                                                  4373                                                         remote-endpoint = <&dpu_intf1_out>;
4728                                                  4374                                                 };
4729                                         };       4375                                         };
4730                                                  4376 
4731                                         port@    4377                                         port@1 {
4732                                                  4378                                                 reg = <1>;
4733                                               !! 4379                                                 dsi0_out: endpoint {
4734                                                  4380                                                 };
4735                                         };       4381                                         };
4736                                 };               4382                                 };
4737                         };                       4383                         };
4738                                                  4384 
4739                         mdss_dsi0_phy: phy@ae !! 4385                         dsi0_phy: dsi-phy@ae94400 {
4740                                 compatible =     4386                                 compatible = "qcom,dsi-phy-10nm";
4741                                 reg = <0 0x0a    4387                                 reg = <0 0x0ae94400 0 0x200>,
4742                                       <0 0x0a    4388                                       <0 0x0ae94600 0 0x280>,
4743                                       <0 0x0a    4389                                       <0 0x0ae94a00 0 0x1e0>;
4744                                 reg-names = "    4390                                 reg-names = "dsi_phy",
4745                                             "    4391                                             "dsi_phy_lane",
4746                                             "    4392                                             "dsi_pll";
4747                                                  4393 
4748                                 #clock-cells     4394                                 #clock-cells = <1>;
4749                                 #phy-cells =     4395                                 #phy-cells = <0>;
4750                                                  4396 
4751                                 clocks = <&di    4397                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752                                          <&rp    4398                                          <&rpmhcc RPMH_CXO_CLK>;
4753                                 clock-names =    4399                                 clock-names = "iface", "ref";
4754                                                  4400 
4755                                 status = "dis    4401                                 status = "disabled";
4756                         };                       4402                         };
4757                                                  4403 
4758                         mdss_dsi1: dsi@ae9600 !! 4404                         dsi1: dsi@ae96000 {
4759                                 compatible =  !! 4405                                 compatible = "qcom,mdss-dsi-ctrl";
4760                                               << 
4761                                 reg = <0 0x0a    4406                                 reg = <0 0x0ae96000 0 0x400>;
4762                                 reg-names = "    4407                                 reg-names = "dsi_ctrl";
4763                                                  4408 
4764                                 interrupt-par    4409                                 interrupt-parent = <&mdss>;
4765                                 interrupts =  !! 4410                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766                                                  4411 
4767                                 clocks = <&di    4412                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768                                          <&di    4413                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769                                          <&di    4414                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770                                          <&di    4415                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771                                          <&di    4416                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772                                          <&di    4417                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773                                 clock-names =    4418                                 clock-names = "byte",
4774                                                  4419                                               "byte_intf",
4775                                                  4420                                               "pixel",
4776                                                  4421                                               "core",
4777                                                  4422                                               "iface",
4778                                                  4423                                               "bus";
4779                                 assigned-cloc    4424                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780                                 assigned-cloc !! 4425                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4781                                                  4426 
4782                                 operating-poi    4427                                 operating-points-v2 = <&dsi_opp_table>;
4783                                 power-domains    4428                                 power-domains = <&rpmhpd SDM845_CX>;
4784                                                  4429 
4785                                 phys = <&mdss !! 4430                                 phys = <&dsi1_phy>;
                                                   >> 4431                                 phy-names = "dsi";
4786                                                  4432 
4787                                 status = "dis    4433                                 status = "disabled";
4788                                                  4434 
4789                                 #address-cell    4435                                 #address-cells = <1>;
4790                                 #size-cells =    4436                                 #size-cells = <0>;
4791                                                  4437 
4792                                 ports {          4438                                 ports {
4793                                         #addr    4439                                         #address-cells = <1>;
4794                                         #size    4440                                         #size-cells = <0>;
4795                                                  4441 
4796                                         port@    4442                                         port@0 {
4797                                                  4443                                                 reg = <0>;
4798                                               !! 4444                                                 dsi1_in: endpoint {
4799                                                  4445                                                         remote-endpoint = <&dpu_intf2_out>;
4800                                                  4446                                                 };
4801                                         };       4447                                         };
4802                                                  4448 
4803                                         port@    4449                                         port@1 {
4804                                                  4450                                                 reg = <1>;
4805                                               !! 4451                                                 dsi1_out: endpoint {
4806                                                  4452                                                 };
4807                                         };       4453                                         };
4808                                 };               4454                                 };
4809                         };                       4455                         };
4810                                                  4456 
4811                         mdss_dsi1_phy: phy@ae !! 4457                         dsi1_phy: dsi-phy@ae96400 {
4812                                 compatible =     4458                                 compatible = "qcom,dsi-phy-10nm";
4813                                 reg = <0 0x0a    4459                                 reg = <0 0x0ae96400 0 0x200>,
4814                                       <0 0x0a    4460                                       <0 0x0ae96600 0 0x280>,
4815                                       <0 0x0a    4461                                       <0 0x0ae96a00 0 0x10e>;
4816                                 reg-names = "    4462                                 reg-names = "dsi_phy",
4817                                             "    4463                                             "dsi_phy_lane",
4818                                             "    4464                                             "dsi_pll";
4819                                                  4465 
4820                                 #clock-cells     4466                                 #clock-cells = <1>;
4821                                 #phy-cells =     4467                                 #phy-cells = <0>;
4822                                                  4468 
4823                                 clocks = <&di    4469                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824                                          <&rp    4470                                          <&rpmhcc RPMH_CXO_CLK>;
4825                                 clock-names =    4471                                 clock-names = "iface", "ref";
4826                                                  4472 
4827                                 status = "dis    4473                                 status = "disabled";
4828                         };                       4474                         };
4829                 };                               4475                 };
4830                                                  4476 
4831                 gpu: gpu@5000000 {               4477                 gpu: gpu@5000000 {
4832                         compatible = "qcom,ad    4478                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4833                                                  4479 
4834                         reg = <0 0x05000000 0 !! 4480                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835                         reg-names = "kgsl_3d0    4481                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836                                                  4482 
4837                         /*                       4483                         /*
4838                          * Look ma, no clocks    4484                          * Look ma, no clocks! The GPU clocks and power are
4839                          * controlled entirel    4485                          * controlled entirely by the GMU
4840                          */                      4486                          */
4841                                                  4487 
4842                         interrupts = <GIC_SPI    4488                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843                                                  4489 
4844                         iommus = <&adreno_smm    4490                         iommus = <&adreno_smmu 0>;
4845                                                  4491 
4846                         operating-points-v2 =    4492                         operating-points-v2 = <&gpu_opp_table>;
4847                                                  4493 
4848                         qcom,gmu = <&gmu>;       4494                         qcom,gmu = <&gmu>;
4849                         #cooling-cells = <2>; << 
4850                                                  4495 
4851                         interconnects = <&mem    4496                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852                         interconnect-names =     4497                         interconnect-names = "gfx-mem";
4853                                                  4498 
4854                         status = "disabled";     4499                         status = "disabled";
4855                                                  4500 
4856                         gpu_opp_table: opp-ta    4501                         gpu_opp_table: opp-table {
4857                                 compatible =     4502                                 compatible = "operating-points-v2";
4858                                                  4503 
4859                                 opp-710000000    4504                                 opp-710000000 {
4860                                         opp-h    4505                                         opp-hz = /bits/ 64 <710000000>;
4861                                         opp-l    4506                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862                                         opp-p    4507                                         opp-peak-kBps = <7216000>;
4863                                 };               4508                                 };
4864                                                  4509 
4865                                 opp-675000000    4510                                 opp-675000000 {
4866                                         opp-h    4511                                         opp-hz = /bits/ 64 <675000000>;
4867                                         opp-l    4512                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868                                         opp-p    4513                                         opp-peak-kBps = <7216000>;
4869                                 };               4514                                 };
4870                                                  4515 
4871                                 opp-596000000    4516                                 opp-596000000 {
4872                                         opp-h    4517                                         opp-hz = /bits/ 64 <596000000>;
4873                                         opp-l    4518                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874                                         opp-p    4519                                         opp-peak-kBps = <6220000>;
4875                                 };               4520                                 };
4876                                                  4521 
4877                                 opp-520000000    4522                                 opp-520000000 {
4878                                         opp-h    4523                                         opp-hz = /bits/ 64 <520000000>;
4879                                         opp-l    4524                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880                                         opp-p    4525                                         opp-peak-kBps = <6220000>;
4881                                 };               4526                                 };
4882                                                  4527 
4883                                 opp-414000000    4528                                 opp-414000000 {
4884                                         opp-h    4529                                         opp-hz = /bits/ 64 <414000000>;
4885                                         opp-l    4530                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886                                         opp-p    4531                                         opp-peak-kBps = <4068000>;
4887                                 };               4532                                 };
4888                                                  4533 
4889                                 opp-342000000    4534                                 opp-342000000 {
4890                                         opp-h    4535                                         opp-hz = /bits/ 64 <342000000>;
4891                                         opp-l    4536                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892                                         opp-p    4537                                         opp-peak-kBps = <2724000>;
4893                                 };               4538                                 };
4894                                                  4539 
4895                                 opp-257000000    4540                                 opp-257000000 {
4896                                         opp-h    4541                                         opp-hz = /bits/ 64 <257000000>;
4897                                         opp-l    4542                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898                                         opp-p    4543                                         opp-peak-kBps = <1648000>;
4899                                 };               4544                                 };
4900                         };                       4545                         };
4901                 };                               4546                 };
4902                                                  4547 
4903                 adreno_smmu: iommu@5040000 {     4548                 adreno_smmu: iommu@5040000 {
4904                         compatible = "qcom,sd    4549                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905                         reg = <0 0x05040000 0 !! 4550                         reg = <0 0x5040000 0 0x10000>;
4906                         #iommu-cells = <1>;      4551                         #iommu-cells = <1>;
4907                         #global-interrupts =     4552                         #global-interrupts = <2>;
4908                         interrupts = <GIC_SPI    4553                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909                                      <GIC_SPI    4554                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910                                      <GIC_SPI    4555                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911                                      <GIC_SPI    4556                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912                                      <GIC_SPI    4557                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913                                      <GIC_SPI    4558                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914                                      <GIC_SPI    4559                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915                                      <GIC_SPI    4560                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916                                      <GIC_SPI    4561                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917                                      <GIC_SPI    4562                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918                         clocks = <&gcc GCC_GP    4563                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919                                  <&gcc GCC_GP    4564                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4920                         clock-names = "bus",     4565                         clock-names = "bus", "iface";
4921                                                  4566 
4922                         power-domains = <&gpu    4567                         power-domains = <&gpucc GPU_CX_GDSC>;
4923                 };                               4568                 };
4924                                                  4569 
4925                 gmu: gmu@506a000 {               4570                 gmu: gmu@506a000 {
4926                         compatible = "qcom,ad !! 4571                         compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927                                                  4572 
4928                         reg = <0 0x0506a000 0 !! 4573                         reg = <0 0x506a000 0 0x30000>,
4929                               <0 0x0b280000 0 !! 4574                               <0 0xb280000 0 0x10000>,
4930                               <0 0x0b480000 0 !! 4575                               <0 0xb480000 0 0x10000>;
4931                         reg-names = "gmu", "g    4576                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932                                                  4577 
4933                         interrupts = <GIC_SPI    4578                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934                                      <GIC_SPI    4579                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935                         interrupt-names = "hf    4580                         interrupt-names = "hfi", "gmu";
4936                                                  4581 
4937                         clocks = <&gpucc GPU_    4582                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938                                  <&gpucc GPU_    4583                                  <&gpucc GPU_CC_CXO_CLK>,
4939                                  <&gcc GCC_DD    4584                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940                                  <&gcc GCC_GP    4585                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941                         clock-names = "gmu",     4586                         clock-names = "gmu", "cxo", "axi", "memnoc";
4942                                                  4587 
4943                         power-domains = <&gpu    4588                         power-domains = <&gpucc GPU_CX_GDSC>,
4944                                         <&gpu    4589                                         <&gpucc GPU_GX_GDSC>;
4945                         power-domain-names =     4590                         power-domain-names = "cx", "gx";
4946                                                  4591 
4947                         iommus = <&adreno_smm    4592                         iommus = <&adreno_smmu 5>;
4948                                                  4593 
4949                         operating-points-v2 =    4594                         operating-points-v2 = <&gmu_opp_table>;
4950                                                  4595 
4951                         status = "disabled";     4596                         status = "disabled";
4952                                                  4597 
4953                         gmu_opp_table: opp-ta    4598                         gmu_opp_table: opp-table {
4954                                 compatible =     4599                                 compatible = "operating-points-v2";
4955                                                  4600 
4956                                 opp-400000000    4601                                 opp-400000000 {
4957                                         opp-h    4602                                         opp-hz = /bits/ 64 <400000000>;
4958                                         opp-l    4603                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959                                 };               4604                                 };
4960                                                  4605 
4961                                 opp-200000000    4606                                 opp-200000000 {
4962                                         opp-h    4607                                         opp-hz = /bits/ 64 <200000000>;
4963                                         opp-l    4608                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964                                 };               4609                                 };
4965                         };                       4610                         };
4966                 };                               4611                 };
4967                                                  4612 
4968                 dispcc: clock-controller@af00    4613                 dispcc: clock-controller@af00000 {
4969                         compatible = "qcom,sd    4614                         compatible = "qcom,sdm845-dispcc";
4970                         reg = <0 0x0af00000 0    4615                         reg = <0 0x0af00000 0 0x10000>;
4971                         clocks = <&rpmhcc RPM    4616                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4972                                  <&gcc GCC_DI    4617                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973                                  <&gcc GCC_DI    4618                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974                                  <&mdss_dsi0_ !! 4619                                  <&dsi0_phy 0>,
4975                                  <&mdss_dsi0_ !! 4620                                  <&dsi0_phy 1>,
4976                                  <&mdss_dsi1_ !! 4621                                  <&dsi1_phy 0>,
4977                                  <&mdss_dsi1_ !! 4622                                  <&dsi1_phy 1>,
4978                                  <&usb_1_qmpp !! 4623                                  <0>,
4979                                  <&usb_1_qmpp !! 4624                                  <0>;
4980                         clock-names = "bi_tcx    4625                         clock-names = "bi_tcxo",
4981                                       "gcc_di    4626                                       "gcc_disp_gpll0_clk_src",
4982                                       "gcc_di    4627                                       "gcc_disp_gpll0_div_clk_src",
4983                                       "dsi0_p    4628                                       "dsi0_phy_pll_out_byteclk",
4984                                       "dsi0_p    4629                                       "dsi0_phy_pll_out_dsiclk",
4985                                       "dsi1_p    4630                                       "dsi1_phy_pll_out_byteclk",
4986                                       "dsi1_p    4631                                       "dsi1_phy_pll_out_dsiclk",
4987                                       "dp_lin    4632                                       "dp_link_clk_divsel_ten",
4988                                       "dp_vco    4633                                       "dp_vco_divided_clk_src_mux";
4989                         #clock-cells = <1>;      4634                         #clock-cells = <1>;
4990                         #reset-cells = <1>;      4635                         #reset-cells = <1>;
4991                         #power-domain-cells =    4636                         #power-domain-cells = <1>;
4992                 };                               4637                 };
4993                                                  4638 
4994                 pdc_intc: interrupt-controlle    4639                 pdc_intc: interrupt-controller@b220000 {
4995                         compatible = "qcom,sd    4640                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996                         reg = <0 0x0b220000 0    4641                         reg = <0 0x0b220000 0 0x30000>;
4997                         qcom,pdc-ranges = <0     4642                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998                         #interrupt-cells = <2    4643                         #interrupt-cells = <2>;
4999                         interrupt-parent = <&    4644                         interrupt-parent = <&intc>;
5000                         interrupt-controller;    4645                         interrupt-controller;
5001                 };                               4646                 };
5002                                                  4647 
5003                 pdc_reset: reset-controller@b    4648                 pdc_reset: reset-controller@b2e0000 {
5004                         compatible = "qcom,sd    4649                         compatible = "qcom,sdm845-pdc-global";
5005                         reg = <0 0x0b2e0000 0    4650                         reg = <0 0x0b2e0000 0 0x20000>;
5006                         #reset-cells = <1>;      4651                         #reset-cells = <1>;
5007                 };                               4652                 };
5008                                                  4653 
5009                 tsens0: thermal-sensor@c26300    4654                 tsens0: thermal-sensor@c263000 {
5010                         compatible = "qcom,sd    4655                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011                         reg = <0 0x0c263000 0    4656                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012                               <0 0x0c222000 0    4657                               <0 0x0c222000 0 0x1ff>; /* SROT */
5013                         #qcom,sensors = <13>;    4658                         #qcom,sensors = <13>;
5014                         interrupts = <GIC_SPI    4659                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015                                      <GIC_SPI    4660                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016                         interrupt-names = "up    4661                         interrupt-names = "uplow", "critical";
5017                         #thermal-sensor-cells    4662                         #thermal-sensor-cells = <1>;
5018                 };                               4663                 };
5019                                                  4664 
5020                 tsens1: thermal-sensor@c26500    4665                 tsens1: thermal-sensor@c265000 {
5021                         compatible = "qcom,sd    4666                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022                         reg = <0 0x0c265000 0    4667                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023                               <0 0x0c223000 0    4668                               <0 0x0c223000 0 0x1ff>; /* SROT */
5024                         #qcom,sensors = <8>;     4669                         #qcom,sensors = <8>;
5025                         interrupts = <GIC_SPI    4670                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026                                      <GIC_SPI    4671                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027                         interrupt-names = "up    4672                         interrupt-names = "uplow", "critical";
5028                         #thermal-sensor-cells    4673                         #thermal-sensor-cells = <1>;
5029                 };                               4674                 };
5030                                                  4675 
5031                 aoss_reset: reset-controller@    4676                 aoss_reset: reset-controller@c2a0000 {
5032                         compatible = "qcom,sd    4677                         compatible = "qcom,sdm845-aoss-cc";
5033                         reg = <0 0x0c2a0000 0    4678                         reg = <0 0x0c2a0000 0 0x31000>;
5034                         #reset-cells = <1>;      4679                         #reset-cells = <1>;
5035                 };                               4680                 };
5036                                                  4681 
5037                 aoss_qmp: power-management@c3 !! 4682                 aoss_qmp: power-controller@c300000 {
5038                         compatible = "qcom,sd    4683                         compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039                         reg = <0 0x0c300000 0 !! 4684                         reg = <0 0x0c300000 0 0x100000>;
5040                         interrupts = <GIC_SPI    4685                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041                         mboxes = <&apss_share    4686                         mboxes = <&apss_shared 0>;
5042                                                  4687 
5043                         #clock-cells = <0>;      4688                         #clock-cells = <0>;
5044                                                  4689 
5045                         cx_cdev: cx {            4690                         cx_cdev: cx {
5046                                 #cooling-cell    4691                                 #cooling-cells = <2>;
5047                         };                       4692                         };
5048                                                  4693 
5049                         ebi_cdev: ebi {          4694                         ebi_cdev: ebi {
5050                                 #cooling-cell    4695                                 #cooling-cells = <2>;
5051                         };                       4696                         };
5052                 };                               4697                 };
5053                                                  4698 
5054                 sram@c3f0000 {                << 
5055                         compatible = "qcom,sd << 
5056                         reg = <0 0x0c3f0000 0 << 
5057                 };                            << 
5058                                               << 
5059                 spmi_bus: spmi@c440000 {         4699                 spmi_bus: spmi@c440000 {
5060                         compatible = "qcom,sp    4700                         compatible = "qcom,spmi-pmic-arb";
5061                         reg = <0 0x0c440000 0    4701                         reg = <0 0x0c440000 0 0x1100>,
5062                               <0 0x0c600000 0    4702                               <0 0x0c600000 0 0x2000000>,
5063                               <0 0x0e600000 0    4703                               <0 0x0e600000 0 0x100000>,
5064                               <0 0x0e700000 0    4704                               <0 0x0e700000 0 0xa0000>,
5065                               <0 0x0c40a000 0    4705                               <0 0x0c40a000 0 0x26000>;
5066                         reg-names = "core", "    4706                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067                         interrupt-names = "pe    4707                         interrupt-names = "periph_irq";
5068                         interrupts = <GIC_SPI    4708                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069                         qcom,ee = <0>;           4709                         qcom,ee = <0>;
5070                         qcom,channel = <0>;      4710                         qcom,channel = <0>;
5071                         #address-cells = <2>;    4711                         #address-cells = <2>;
5072                         #size-cells = <0>;       4712                         #size-cells = <0>;
5073                         interrupt-controller;    4713                         interrupt-controller;
5074                         #interrupt-cells = <4    4714                         #interrupt-cells = <4>;
                                                   >> 4715                         cell-index = <0>;
5075                 };                               4716                 };
5076                                                  4717 
5077                 sram@146bf000 {               !! 4718                 imem@146bf000 {
5078                         compatible = "qcom,sd !! 4719                         compatible = "simple-mfd";
5079                         reg = <0 0x146bf000 0    4720                         reg = <0 0x146bf000 0 0x1000>;
5080                                                  4721 
5081                         #address-cells = <1>;    4722                         #address-cells = <1>;
5082                         #size-cells = <1>;       4723                         #size-cells = <1>;
5083                                                  4724 
5084                         ranges = <0 0 0x146bf    4725                         ranges = <0 0 0x146bf000 0x1000>;
5085                                                  4726 
5086                         pil-reloc@94c {          4727                         pil-reloc@94c {
5087                                 compatible =     4728                                 compatible = "qcom,pil-reloc-info";
5088                                 reg = <0x94c     4729                                 reg = <0x94c 0xc8>;
5089                         };                       4730                         };
5090                 };                               4731                 };
5091                                                  4732 
5092                 apps_smmu: iommu@15000000 {      4733                 apps_smmu: iommu@15000000 {
5093                         compatible = "qcom,sd    4734                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094                         reg = <0 0x15000000 0    4735                         reg = <0 0x15000000 0 0x80000>;
5095                         #iommu-cells = <2>;      4736                         #iommu-cells = <2>;
5096                         #global-interrupts =     4737                         #global-interrupts = <1>;
5097                         interrupts = <GIC_SPI    4738                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098                                      <GIC_SPI    4739                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099                                      <GIC_SPI    4740                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100                                      <GIC_SPI    4741                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101                                      <GIC_SPI    4742                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102                                      <GIC_SPI    4743                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103                                      <GIC_SPI    4744                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104                                      <GIC_SPI    4745                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105                                      <GIC_SPI    4746                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106                                      <GIC_SPI    4747                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107                                      <GIC_SPI    4748                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108                                      <GIC_SPI    4749                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109                                      <GIC_SPI    4750                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110                                      <GIC_SPI    4751                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111                                      <GIC_SPI    4752                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112                                      <GIC_SPI    4753                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113                                      <GIC_SPI    4754                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114                                      <GIC_SPI    4755                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115                                      <GIC_SPI    4756                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116                                      <GIC_SPI    4757                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117                                      <GIC_SPI    4758                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118                                      <GIC_SPI    4759                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119                                      <GIC_SPI    4760                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120                                      <GIC_SPI    4761                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121                                      <GIC_SPI    4762                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122                                      <GIC_SPI    4763                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123                                      <GIC_SPI    4764                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124                                      <GIC_SPI    4765                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125                                      <GIC_SPI    4766                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126                                      <GIC_SPI    4767                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127                                      <GIC_SPI    4768                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128                                      <GIC_SPI    4769                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129                                      <GIC_SPI    4770                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130                                      <GIC_SPI    4771                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131                                      <GIC_SPI    4772                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132                                      <GIC_SPI    4773                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133                                      <GIC_SPI    4774                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134                                      <GIC_SPI    4775                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135                                      <GIC_SPI    4776                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136                                      <GIC_SPI    4777                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137                                      <GIC_SPI    4778                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138                                      <GIC_SPI    4779                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139                                      <GIC_SPI    4780                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140                                      <GIC_SPI    4781                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141                                      <GIC_SPI    4782                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142                                      <GIC_SPI    4783                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143                                      <GIC_SPI    4784                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144                                      <GIC_SPI    4785                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145                                      <GIC_SPI    4786                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146                                      <GIC_SPI    4787                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147                                      <GIC_SPI    4788                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148                                      <GIC_SPI    4789                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149                                      <GIC_SPI    4790                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150                                      <GIC_SPI    4791                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151                                      <GIC_SPI    4792                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152                                      <GIC_SPI    4793                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153                                      <GIC_SPI    4794                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154                                      <GIC_SPI    4795                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155                                      <GIC_SPI    4796                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156                                      <GIC_SPI    4797                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157                                      <GIC_SPI    4798                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158                                      <GIC_SPI    4799                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159                                      <GIC_SPI    4800                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160                                      <GIC_SPI    4801                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161                                      <GIC_SPI    4802                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162                 };                               4803                 };
5163                                                  4804 
5164                 anoc_1_tbu: tbu@150c5000 {    << 
5165                         compatible = "qcom,sd << 
5166                         reg = <0x0 0x150c5000 << 
5167                         interconnects = <&sys << 
5168                                          &con << 
5169                         power-domains = <&gcc << 
5170                         qcom,stream-id-range  << 
5171                 };                            << 
5172                                               << 
5173                 anoc_2_tbu: tbu@150c9000 {    << 
5174                         compatible = "qcom,sd << 
5175                         reg = <0x0 0x150c9000 << 
5176                         interconnects = <&sys << 
5177                                          &con << 
5178                         power-domains = <&gcc << 
5179                         qcom,stream-id-range  << 
5180                 };                            << 
5181                                               << 
5182                 mnoc_hf_0_tbu: tbu@150cd000 { << 
5183                         compatible = "qcom,sd << 
5184                         reg = <0x0 0x150cd000 << 
5185                         interconnects = <&mms << 
5186                                          &mms << 
5187                         power-domains = <&gcc << 
5188                         qcom,stream-id-range  << 
5189                 };                            << 
5190                                               << 
5191                 mnoc_hf_1_tbu: tbu@150d1000 { << 
5192                         compatible = "qcom,sd << 
5193                         reg = <0x0 0x150d1000 << 
5194                         interconnects = <&mms << 
5195                                          &mms << 
5196                         power-domains = <&gcc << 
5197                         qcom,stream-id-range  << 
5198                 };                            << 
5199                                               << 
5200                 mnoc_sf_0_tbu: tbu@150d5000 { << 
5201                         compatible = "qcom,sd << 
5202                         reg = <0x0 0x150d5000 << 
5203                         interconnects = <&mms << 
5204                                          &mms << 
5205                         power-domains = <&gcc << 
5206                         qcom,stream-id-range  << 
5207                 };                            << 
5208                                               << 
5209                 compute_dsp_tbu: tbu@150d9000 << 
5210                         compatible = "qcom,sd << 
5211                         reg = <0x0 0x150d9000 << 
5212                         interconnects = <&sys << 
5213                                          &con << 
5214                         qcom,stream-id-range  << 
5215                 };                            << 
5216                                               << 
5217                 adsp_tbu: tbu@150dd000 {      << 
5218                         compatible = "qcom,sd << 
5219                         reg = <0x0 0x150dd000 << 
5220                         interconnects = <&sys << 
5221                                          &con << 
5222                         power-domains = <&gcc << 
5223                         qcom,stream-id-range  << 
5224                 };                            << 
5225                                               << 
5226                 anoc_1_pcie_tbu: tbu@150e1000 << 
5227                         compatible = "qcom,sd << 
5228                         reg = <0x0 0x150e1000 << 
5229                         clocks = <&gcc GCC_AG << 
5230                         interconnects = <&sys << 
5231                                          &con << 
5232                         power-domains = <&gcc << 
5233                         qcom,stream-id-range  << 
5234                 };                            << 
5235                                               << 
5236                 lpasscc: clock-controller@170    4805                 lpasscc: clock-controller@17014000 {
5237                         compatible = "qcom,sd    4806                         compatible = "qcom,sdm845-lpasscc";
5238                         reg = <0 0x17014000 0    4807                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239                         reg-names = "cc", "qd    4808                         reg-names = "cc", "qdsp6ss";
5240                         #clock-cells = <1>;      4809                         #clock-cells = <1>;
5241                         status = "disabled";     4810                         status = "disabled";
5242                 };                               4811                 };
5243                                                  4812 
5244                 gladiator_noc: interconnect@1    4813                 gladiator_noc: interconnect@17900000 {
5245                         compatible = "qcom,sd    4814                         compatible = "qcom,sdm845-gladiator-noc";
5246                         reg = <0 0x17900000 0    4815                         reg = <0 0x17900000 0 0xd080>;
5247                         #interconnect-cells =    4816                         #interconnect-cells = <2>;
5248                         qcom,bcm-voters = <&a    4817                         qcom,bcm-voters = <&apps_bcm_voter>;
5249                 };                               4818                 };
5250                                                  4819 
5251                 watchdog@17980000 {              4820                 watchdog@17980000 {
5252                         compatible = "qcom,ap    4821                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253                         reg = <0 0x17980000 0    4822                         reg = <0 0x17980000 0 0x1000>;
5254                         clocks = <&sleep_clk>    4823                         clocks = <&sleep_clk>;
5255                         interrupts = <GIC_SPI !! 4824                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256                 };                               4825                 };
5257                                                  4826 
5258                 apss_shared: mailbox@17990000    4827                 apss_shared: mailbox@17990000 {
5259                         compatible = "qcom,sd    4828                         compatible = "qcom,sdm845-apss-shared";
5260                         reg = <0 0x17990000 0    4829                         reg = <0 0x17990000 0 0x1000>;
5261                         #mbox-cells = <1>;       4830                         #mbox-cells = <1>;
5262                 };                               4831                 };
5263                                                  4832 
5264                 apps_rsc: rsc@179c0000 {         4833                 apps_rsc: rsc@179c0000 {
5265                         label = "apps_rsc";      4834                         label = "apps_rsc";
5266                         compatible = "qcom,rp    4835                         compatible = "qcom,rpmh-rsc";
5267                         reg = <0 0x179c0000 0    4836                         reg = <0 0x179c0000 0 0x10000>,
5268                               <0 0x179d0000 0    4837                               <0 0x179d0000 0 0x10000>,
5269                               <0 0x179e0000 0    4838                               <0 0x179e0000 0 0x10000>;
5270                         reg-names = "drv-0",     4839                         reg-names = "drv-0", "drv-1", "drv-2";
5271                         interrupts = <GIC_SPI    4840                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272                                      <GIC_SPI    4841                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273                                      <GIC_SPI    4842                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274                         qcom,tcs-offset = <0x    4843                         qcom,tcs-offset = <0xd00>;
5275                         qcom,drv-id = <2>;       4844                         qcom,drv-id = <2>;
5276                         qcom,tcs-config = <AC    4845                         qcom,tcs-config = <ACTIVE_TCS  2>,
5277                                           <SL    4846                                           <SLEEP_TCS   3>,
5278                                           <WA    4847                                           <WAKE_TCS    3>,
5279                                           <CO    4848                                           <CONTROL_TCS 1>;
5280                         power-domains = <&CLU << 
5281                                                  4849 
5282                         apps_bcm_voter: bcm-v    4850                         apps_bcm_voter: bcm-voter {
5283                                 compatible =     4851                                 compatible = "qcom,bcm-voter";
5284                         };                       4852                         };
5285                                                  4853 
5286                         rpmhcc: clock-control    4854                         rpmhcc: clock-controller {
5287                                 compatible =     4855                                 compatible = "qcom,sdm845-rpmh-clk";
5288                                 #clock-cells     4856                                 #clock-cells = <1>;
5289                                 clock-names =    4857                                 clock-names = "xo";
5290                                 clocks = <&xo    4858                                 clocks = <&xo_board>;
5291                         };                       4859                         };
5292                                                  4860 
5293                         rpmhpd: power-control    4861                         rpmhpd: power-controller {
5294                                 compatible =     4862                                 compatible = "qcom,sdm845-rpmhpd";
5295                                 #power-domain    4863                                 #power-domain-cells = <1>;
5296                                 operating-poi    4864                                 operating-points-v2 = <&rpmhpd_opp_table>;
5297                                                  4865 
5298                                 rpmhpd_opp_ta    4866                                 rpmhpd_opp_table: opp-table {
5299                                         compa    4867                                         compatible = "operating-points-v2";
5300                                                  4868 
5301                                         rpmhp    4869                                         rpmhpd_opp_ret: opp1 {
5302                                                  4870                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303                                         };       4871                                         };
5304                                                  4872 
5305                                         rpmhp    4873                                         rpmhpd_opp_min_svs: opp2 {
5306                                                  4874                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307                                         };       4875                                         };
5308                                                  4876 
5309                                         rpmhp    4877                                         rpmhpd_opp_low_svs: opp3 {
5310                                                  4878                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311                                         };       4879                                         };
5312                                                  4880 
5313                                         rpmhp    4881                                         rpmhpd_opp_svs: opp4 {
5314                                                  4882                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315                                         };       4883                                         };
5316                                                  4884 
5317                                         rpmhp    4885                                         rpmhpd_opp_svs_l1: opp5 {
5318                                                  4886                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319                                         };       4887                                         };
5320                                                  4888 
5321                                         rpmhp    4889                                         rpmhpd_opp_nom: opp6 {
5322                                                  4890                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323                                         };       4891                                         };
5324                                                  4892 
5325                                         rpmhp    4893                                         rpmhpd_opp_nom_l1: opp7 {
5326                                                  4894                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327                                         };       4895                                         };
5328                                                  4896 
5329                                         rpmhp    4897                                         rpmhpd_opp_nom_l2: opp8 {
5330                                                  4898                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331                                         };       4899                                         };
5332                                                  4900 
5333                                         rpmhp    4901                                         rpmhpd_opp_turbo: opp9 {
5334                                                  4902                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335                                         };       4903                                         };
5336                                                  4904 
5337                                         rpmhp    4905                                         rpmhpd_opp_turbo_l1: opp10 {
5338                                                  4906                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339                                         };       4907                                         };
5340                                 };               4908                                 };
5341                         };                       4909                         };
5342                 };                               4910                 };
5343                                                  4911 
5344                 intc: interrupt-controller@17    4912                 intc: interrupt-controller@17a00000 {
5345                         compatible = "arm,gic    4913                         compatible = "arm,gic-v3";
5346                         #address-cells = <2>;    4914                         #address-cells = <2>;
5347                         #size-cells = <2>;       4915                         #size-cells = <2>;
5348                         ranges;                  4916                         ranges;
5349                         #interrupt-cells = <3    4917                         #interrupt-cells = <3>;
5350                         interrupt-controller;    4918                         interrupt-controller;
5351                         reg = <0 0x17a00000 0    4919                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
5352                               <0 0x17a60000 0    4920                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
5353                         interrupts = <GIC_PPI    4921                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354                                                  4922 
5355                         msi-controller@17a400    4923                         msi-controller@17a40000 {
5356                                 compatible =     4924                                 compatible = "arm,gic-v3-its";
5357                                 msi-controlle    4925                                 msi-controller;
5358                                 #msi-cells =     4926                                 #msi-cells = <1>;
5359                                 reg = <0 0x17    4927                                 reg = <0 0x17a40000 0 0x20000>;
5360                                 status = "dis    4928                                 status = "disabled";
5361                         };                       4929                         };
5362                 };                               4930                 };
5363                                                  4931 
5364                 slimbam: dma-controller@17184    4932                 slimbam: dma-controller@17184000 {
5365                         compatible = "qcom,ba !! 4933                         compatible = "qcom,bam-v1.7.0";
5366                         qcom,controlled-remot    4934                         qcom,controlled-remotely;
5367                         reg = <0 0x17184000 0    4935                         reg = <0 0x17184000 0 0x2a000>;
5368                         num-channels = <31>;  !! 4936                         num-channels  = <31>;
5369                         interrupts = <GIC_SPI    4937                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370                         #dma-cells = <1>;        4938                         #dma-cells = <1>;
5371                         qcom,ee = <1>;           4939                         qcom,ee = <1>;
5372                         qcom,num-ees = <2>;      4940                         qcom,num-ees = <2>;
5373                         iommus = <&apps_smmu     4941                         iommus = <&apps_smmu 0x1806 0x0>;
5374                 };                               4942                 };
5375                                                  4943 
5376                 timer@17c90000 {                 4944                 timer@17c90000 {
5377                         #address-cells = <1>;    4945                         #address-cells = <1>;
5378                         #size-cells = <1>;       4946                         #size-cells = <1>;
5379                         ranges = <0 0 0 0x200    4947                         ranges = <0 0 0 0x20000000>;
5380                         compatible = "arm,arm    4948                         compatible = "arm,armv7-timer-mem";
5381                         reg = <0 0x17c90000 0    4949                         reg = <0 0x17c90000 0 0x1000>;
5382                                                  4950 
5383                         frame@17ca0000 {         4951                         frame@17ca0000 {
5384                                 frame-number     4952                                 frame-number = <0>;
5385                                 interrupts =     4953                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386                                                  4954                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387                                 reg = <0x17ca    4955                                 reg = <0x17ca0000 0x1000>,
5388                                       <0x17cb    4956                                       <0x17cb0000 0x1000>;
5389                         };                       4957                         };
5390                                                  4958 
5391                         frame@17cc0000 {         4959                         frame@17cc0000 {
5392                                 frame-number     4960                                 frame-number = <1>;
5393                                 interrupts =     4961                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394                                 reg = <0x17cc    4962                                 reg = <0x17cc0000 0x1000>;
5395                                 status = "dis    4963                                 status = "disabled";
5396                         };                       4964                         };
5397                                                  4965 
5398                         frame@17cd0000 {         4966                         frame@17cd0000 {
5399                                 frame-number     4967                                 frame-number = <2>;
5400                                 interrupts =     4968                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401                                 reg = <0x17cd    4969                                 reg = <0x17cd0000 0x1000>;
5402                                 status = "dis    4970                                 status = "disabled";
5403                         };                       4971                         };
5404                                                  4972 
5405                         frame@17ce0000 {         4973                         frame@17ce0000 {
5406                                 frame-number     4974                                 frame-number = <3>;
5407                                 interrupts =     4975                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408                                 reg = <0x17ce    4976                                 reg = <0x17ce0000 0x1000>;
5409                                 status = "dis    4977                                 status = "disabled";
5410                         };                       4978                         };
5411                                                  4979 
5412                         frame@17cf0000 {         4980                         frame@17cf0000 {
5413                                 frame-number     4981                                 frame-number = <4>;
5414                                 interrupts =     4982                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415                                 reg = <0x17cf    4983                                 reg = <0x17cf0000 0x1000>;
5416                                 status = "dis    4984                                 status = "disabled";
5417                         };                       4985                         };
5418                                                  4986 
5419                         frame@17d00000 {         4987                         frame@17d00000 {
5420                                 frame-number     4988                                 frame-number = <5>;
5421                                 interrupts =     4989                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422                                 reg = <0x17d0    4990                                 reg = <0x17d00000 0x1000>;
5423                                 status = "dis    4991                                 status = "disabled";
5424                         };                       4992                         };
5425                                                  4993 
5426                         frame@17d10000 {         4994                         frame@17d10000 {
5427                                 frame-number     4995                                 frame-number = <6>;
5428                                 interrupts =     4996                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429                                 reg = <0x17d1    4997                                 reg = <0x17d10000 0x1000>;
5430                                 status = "dis    4998                                 status = "disabled";
5431                         };                       4999                         };
5432                 };                               5000                 };
5433                                                  5001 
5434                 osm_l3: interconnect@17d41000    5002                 osm_l3: interconnect@17d41000 {
5435                         compatible = "qcom,sd !! 5003                         compatible = "qcom,sdm845-osm-l3";
5436                         reg = <0 0x17d41000 0    5004                         reg = <0 0x17d41000 0 0x1400>;
5437                                                  5005 
5438                         clocks = <&rpmhcc RPM    5006                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439                         clock-names = "xo", "    5007                         clock-names = "xo", "alternate";
5440                                                  5008 
5441                         #interconnect-cells =    5009                         #interconnect-cells = <1>;
5442                 };                               5010                 };
5443                                                  5011 
5444                 cpufreq_hw: cpufreq@17d43000     5012                 cpufreq_hw: cpufreq@17d43000 {
5445                         compatible = "qcom,sd !! 5013                         compatible = "qcom,cpufreq-hw";
5446                         reg = <0 0x17d43000 0    5014                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447                         reg-names = "freq-dom    5015                         reg-names = "freq-domain0", "freq-domain1";
5448                                                  5016 
5449                         interrupts-extended =    5017                         interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450                                                  5018 
5451                         clocks = <&rpmhcc RPM    5019                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452                         clock-names = "xo", "    5020                         clock-names = "xo", "alternate";
5453                                                  5021 
5454                         #freq-domain-cells =     5022                         #freq-domain-cells = <1>;
5455                         #clock-cells = <1>;   << 
5456                 };                               5023                 };
5457                                                  5024 
5458                 wifi: wifi@18800000 {            5025                 wifi: wifi@18800000 {
5459                         compatible = "qcom,wc    5026                         compatible = "qcom,wcn3990-wifi";
5460                         status = "disabled";     5027                         status = "disabled";
5461                         reg = <0 0x18800000 0    5028                         reg = <0 0x18800000 0 0x800000>;
5462                         reg-names = "membase"    5029                         reg-names = "membase";
5463                         memory-region = <&wla    5030                         memory-region = <&wlan_msa_mem>;
5464                         clock-names = "cxo_re    5031                         clock-names = "cxo_ref_clk_pin";
5465                         clocks = <&rpmhcc RPM    5032                         clocks = <&rpmhcc RPMH_RF_CLK2>;
5466                         interrupts =             5033                         interrupts =
5467                                 <GIC_SPI 414     5034                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468                                 <GIC_SPI 415     5035                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469                                 <GIC_SPI 416     5036                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470                                 <GIC_SPI 417     5037                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471                                 <GIC_SPI 418     5038                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472                                 <GIC_SPI 419     5039                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473                                 <GIC_SPI 420     5040                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474                                 <GIC_SPI 421     5041                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475                                 <GIC_SPI 422     5042                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476                                 <GIC_SPI 423     5043                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477                                 <GIC_SPI 424     5044                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478                                 <GIC_SPI 425     5045                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479                         iommus = <&apps_smmu     5046                         iommus = <&apps_smmu 0x0040 0x1>;
5480                 };                               5047                 };
5481         };                                       5048         };
5482                                                  5049 
5483         sound: sound {                        << 
5484         };                                    << 
5485                                               << 
5486         thermal-zones {                          5050         thermal-zones {
5487                 cpu0-thermal {                   5051                 cpu0-thermal {
5488                         polling-delay-passive    5052                         polling-delay-passive = <250>;
                                                   >> 5053                         polling-delay = <1000>;
5489                                                  5054 
5490                         thermal-sensors = <&t    5055                         thermal-sensors = <&tsens0 1>;
5491                                                  5056 
5492                         trips {                  5057                         trips {
5493                                 cpu0_alert0:     5058                                 cpu0_alert0: trip-point0 {
5494                                         tempe    5059                                         temperature = <90000>;
5495                                         hyste    5060                                         hysteresis = <2000>;
5496                                         type     5061                                         type = "passive";
5497                                 };               5062                                 };
5498                                                  5063 
5499                                 cpu0_alert1:     5064                                 cpu0_alert1: trip-point1 {
5500                                         tempe    5065                                         temperature = <95000>;
5501                                         hyste    5066                                         hysteresis = <2000>;
5502                                         type     5067                                         type = "passive";
5503                                 };               5068                                 };
5504                                                  5069 
5505                                 cpu0_crit: cp !! 5070                                 cpu0_crit: cpu_crit {
5506                                         tempe    5071                                         temperature = <110000>;
5507                                         hyste    5072                                         hysteresis = <1000>;
5508                                         type     5073                                         type = "critical";
5509                                 };               5074                                 };
5510                         };                       5075                         };
5511                 };                               5076                 };
5512                                                  5077 
5513                 cpu1-thermal {                   5078                 cpu1-thermal {
5514                         polling-delay-passive    5079                         polling-delay-passive = <250>;
                                                   >> 5080                         polling-delay = <1000>;
5515                                                  5081 
5516                         thermal-sensors = <&t    5082                         thermal-sensors = <&tsens0 2>;
5517                                                  5083 
5518                         trips {                  5084                         trips {
5519                                 cpu1_alert0:     5085                                 cpu1_alert0: trip-point0 {
5520                                         tempe    5086                                         temperature = <90000>;
5521                                         hyste    5087                                         hysteresis = <2000>;
5522                                         type     5088                                         type = "passive";
5523                                 };               5089                                 };
5524                                                  5090 
5525                                 cpu1_alert1:     5091                                 cpu1_alert1: trip-point1 {
5526                                         tempe    5092                                         temperature = <95000>;
5527                                         hyste    5093                                         hysteresis = <2000>;
5528                                         type     5094                                         type = "passive";
5529                                 };               5095                                 };
5530                                                  5096 
5531                                 cpu1_crit: cp !! 5097                                 cpu1_crit: cpu_crit {
5532                                         tempe    5098                                         temperature = <110000>;
5533                                         hyste    5099                                         hysteresis = <1000>;
5534                                         type     5100                                         type = "critical";
5535                                 };               5101                                 };
5536                         };                       5102                         };
5537                 };                               5103                 };
5538                                                  5104 
5539                 cpu2-thermal {                   5105                 cpu2-thermal {
5540                         polling-delay-passive    5106                         polling-delay-passive = <250>;
                                                   >> 5107                         polling-delay = <1000>;
5541                                                  5108 
5542                         thermal-sensors = <&t    5109                         thermal-sensors = <&tsens0 3>;
5543                                                  5110 
5544                         trips {                  5111                         trips {
5545                                 cpu2_alert0:     5112                                 cpu2_alert0: trip-point0 {
5546                                         tempe    5113                                         temperature = <90000>;
5547                                         hyste    5114                                         hysteresis = <2000>;
5548                                         type     5115                                         type = "passive";
5549                                 };               5116                                 };
5550                                                  5117 
5551                                 cpu2_alert1:     5118                                 cpu2_alert1: trip-point1 {
5552                                         tempe    5119                                         temperature = <95000>;
5553                                         hyste    5120                                         hysteresis = <2000>;
5554                                         type     5121                                         type = "passive";
5555                                 };               5122                                 };
5556                                                  5123 
5557                                 cpu2_crit: cp !! 5124                                 cpu2_crit: cpu_crit {
5558                                         tempe    5125                                         temperature = <110000>;
5559                                         hyste    5126                                         hysteresis = <1000>;
5560                                         type     5127                                         type = "critical";
5561                                 };               5128                                 };
5562                         };                       5129                         };
5563                 };                               5130                 };
5564                                                  5131 
5565                 cpu3-thermal {                   5132                 cpu3-thermal {
5566                         polling-delay-passive    5133                         polling-delay-passive = <250>;
                                                   >> 5134                         polling-delay = <1000>;
5567                                                  5135 
5568                         thermal-sensors = <&t    5136                         thermal-sensors = <&tsens0 4>;
5569                                                  5137 
5570                         trips {                  5138                         trips {
5571                                 cpu3_alert0:     5139                                 cpu3_alert0: trip-point0 {
5572                                         tempe    5140                                         temperature = <90000>;
5573                                         hyste    5141                                         hysteresis = <2000>;
5574                                         type     5142                                         type = "passive";
5575                                 };               5143                                 };
5576                                                  5144 
5577                                 cpu3_alert1:     5145                                 cpu3_alert1: trip-point1 {
5578                                         tempe    5146                                         temperature = <95000>;
5579                                         hyste    5147                                         hysteresis = <2000>;
5580                                         type     5148                                         type = "passive";
5581                                 };               5149                                 };
5582                                                  5150 
5583                                 cpu3_crit: cp !! 5151                                 cpu3_crit: cpu_crit {
5584                                         tempe    5152                                         temperature = <110000>;
5585                                         hyste    5153                                         hysteresis = <1000>;
5586                                         type     5154                                         type = "critical";
5587                                 };               5155                                 };
5588                         };                       5156                         };
5589                 };                               5157                 };
5590                                                  5158 
5591                 cpu4-thermal {                   5159                 cpu4-thermal {
5592                         polling-delay-passive    5160                         polling-delay-passive = <250>;
                                                   >> 5161                         polling-delay = <1000>;
5593                                                  5162 
5594                         thermal-sensors = <&t    5163                         thermal-sensors = <&tsens0 7>;
5595                                                  5164 
5596                         trips {                  5165                         trips {
5597                                 cpu4_alert0:     5166                                 cpu4_alert0: trip-point0 {
5598                                         tempe    5167                                         temperature = <90000>;
5599                                         hyste    5168                                         hysteresis = <2000>;
5600                                         type     5169                                         type = "passive";
5601                                 };               5170                                 };
5602                                                  5171 
5603                                 cpu4_alert1:     5172                                 cpu4_alert1: trip-point1 {
5604                                         tempe    5173                                         temperature = <95000>;
5605                                         hyste    5174                                         hysteresis = <2000>;
5606                                         type     5175                                         type = "passive";
5607                                 };               5176                                 };
5608                                                  5177 
5609                                 cpu4_crit: cp !! 5178                                 cpu4_crit: cpu_crit {
5610                                         tempe    5179                                         temperature = <110000>;
5611                                         hyste    5180                                         hysteresis = <1000>;
5612                                         type     5181                                         type = "critical";
5613                                 };               5182                                 };
5614                         };                       5183                         };
5615                 };                               5184                 };
5616                                                  5185 
5617                 cpu5-thermal {                   5186                 cpu5-thermal {
5618                         polling-delay-passive    5187                         polling-delay-passive = <250>;
                                                   >> 5188                         polling-delay = <1000>;
5619                                                  5189 
5620                         thermal-sensors = <&t    5190                         thermal-sensors = <&tsens0 8>;
5621                                                  5191 
5622                         trips {                  5192                         trips {
5623                                 cpu5_alert0:     5193                                 cpu5_alert0: trip-point0 {
5624                                         tempe    5194                                         temperature = <90000>;
5625                                         hyste    5195                                         hysteresis = <2000>;
5626                                         type     5196                                         type = "passive";
5627                                 };               5197                                 };
5628                                                  5198 
5629                                 cpu5_alert1:     5199                                 cpu5_alert1: trip-point1 {
5630                                         tempe    5200                                         temperature = <95000>;
5631                                         hyste    5201                                         hysteresis = <2000>;
5632                                         type     5202                                         type = "passive";
5633                                 };               5203                                 };
5634                                                  5204 
5635                                 cpu5_crit: cp !! 5205                                 cpu5_crit: cpu_crit {
5636                                         tempe    5206                                         temperature = <110000>;
5637                                         hyste    5207                                         hysteresis = <1000>;
5638                                         type     5208                                         type = "critical";
5639                                 };               5209                                 };
5640                         };                       5210                         };
5641                 };                               5211                 };
5642                                                  5212 
5643                 cpu6-thermal {                   5213                 cpu6-thermal {
5644                         polling-delay-passive    5214                         polling-delay-passive = <250>;
                                                   >> 5215                         polling-delay = <1000>;
5645                                                  5216 
5646                         thermal-sensors = <&t    5217                         thermal-sensors = <&tsens0 9>;
5647                                                  5218 
5648                         trips {                  5219                         trips {
5649                                 cpu6_alert0:     5220                                 cpu6_alert0: trip-point0 {
5650                                         tempe    5221                                         temperature = <90000>;
5651                                         hyste    5222                                         hysteresis = <2000>;
5652                                         type     5223                                         type = "passive";
5653                                 };               5224                                 };
5654                                                  5225 
5655                                 cpu6_alert1:     5226                                 cpu6_alert1: trip-point1 {
5656                                         tempe    5227                                         temperature = <95000>;
5657                                         hyste    5228                                         hysteresis = <2000>;
5658                                         type     5229                                         type = "passive";
5659                                 };               5230                                 };
5660                                                  5231 
5661                                 cpu6_crit: cp !! 5232                                 cpu6_crit: cpu_crit {
5662                                         tempe    5233                                         temperature = <110000>;
5663                                         hyste    5234                                         hysteresis = <1000>;
5664                                         type     5235                                         type = "critical";
5665                                 };               5236                                 };
5666                         };                       5237                         };
5667                 };                               5238                 };
5668                                                  5239 
5669                 cpu7-thermal {                   5240                 cpu7-thermal {
5670                         polling-delay-passive    5241                         polling-delay-passive = <250>;
                                                   >> 5242                         polling-delay = <1000>;
5671                                                  5243 
5672                         thermal-sensors = <&t    5244                         thermal-sensors = <&tsens0 10>;
5673                                                  5245 
5674                         trips {                  5246                         trips {
5675                                 cpu7_alert0:     5247                                 cpu7_alert0: trip-point0 {
5676                                         tempe    5248                                         temperature = <90000>;
5677                                         hyste    5249                                         hysteresis = <2000>;
5678                                         type     5250                                         type = "passive";
5679                                 };               5251                                 };
5680                                                  5252 
5681                                 cpu7_alert1:     5253                                 cpu7_alert1: trip-point1 {
5682                                         tempe    5254                                         temperature = <95000>;
5683                                         hyste    5255                                         hysteresis = <2000>;
5684                                         type     5256                                         type = "passive";
5685                                 };               5257                                 };
5686                                                  5258 
5687                                 cpu7_crit: cp !! 5259                                 cpu7_crit: cpu_crit {
5688                                         tempe    5260                                         temperature = <110000>;
5689                                         hyste    5261                                         hysteresis = <1000>;
5690                                         type     5262                                         type = "critical";
5691                                 };               5263                                 };
5692                         };                       5264                         };
5693                 };                               5265                 };
5694                                                  5266 
5695                 aoss0-thermal {                  5267                 aoss0-thermal {
5696                         polling-delay-passive    5268                         polling-delay-passive = <250>;
                                                   >> 5269                         polling-delay = <1000>;
5697                                                  5270 
5698                         thermal-sensors = <&t    5271                         thermal-sensors = <&tsens0 0>;
5699                                                  5272 
5700                         trips {                  5273                         trips {
5701                                 aoss0_alert0:    5274                                 aoss0_alert0: trip-point0 {
5702                                         tempe    5275                                         temperature = <90000>;
5703                                         hyste    5276                                         hysteresis = <2000>;
5704                                         type     5277                                         type = "hot";
5705                                 };               5278                                 };
5706                         };                       5279                         };
5707                 };                               5280                 };
5708                                                  5281 
5709                 cluster0-thermal {               5282                 cluster0-thermal {
5710                         polling-delay-passive    5283                         polling-delay-passive = <250>;
                                                   >> 5284                         polling-delay = <1000>;
5711                                                  5285 
5712                         thermal-sensors = <&t    5286                         thermal-sensors = <&tsens0 5>;
5713                                                  5287 
5714                         trips {                  5288                         trips {
5715                                 cluster0_aler    5289                                 cluster0_alert0: trip-point0 {
5716                                         tempe    5290                                         temperature = <90000>;
5717                                         hyste    5291                                         hysteresis = <2000>;
5718                                         type     5292                                         type = "hot";
5719                                 };               5293                                 };
5720                                 cluster0_crit !! 5294                                 cluster0_crit: cluster0_crit {
5721                                         tempe    5295                                         temperature = <110000>;
5722                                         hyste    5296                                         hysteresis = <2000>;
5723                                         type     5297                                         type = "critical";
5724                                 };               5298                                 };
5725                         };                       5299                         };
5726                 };                               5300                 };
5727                                                  5301 
5728                 cluster1-thermal {               5302                 cluster1-thermal {
5729                         polling-delay-passive    5303                         polling-delay-passive = <250>;
                                                   >> 5304                         polling-delay = <1000>;
5730                                                  5305 
5731                         thermal-sensors = <&t    5306                         thermal-sensors = <&tsens0 6>;
5732                                                  5307 
5733                         trips {                  5308                         trips {
5734                                 cluster1_aler    5309                                 cluster1_alert0: trip-point0 {
5735                                         tempe    5310                                         temperature = <90000>;
5736                                         hyste    5311                                         hysteresis = <2000>;
5737                                         type     5312                                         type = "hot";
5738                                 };               5313                                 };
5739                                 cluster1_crit !! 5314                                 cluster1_crit: cluster1_crit {
5740                                         tempe    5315                                         temperature = <110000>;
5741                                         hyste    5316                                         hysteresis = <2000>;
5742                                         type     5317                                         type = "critical";
5743                                 };               5318                                 };
5744                         };                       5319                         };
5745                 };                               5320                 };
5746                                                  5321 
5747                 gpu-top-thermal {                5322                 gpu-top-thermal {
5748                         polling-delay-passive    5323                         polling-delay-passive = <250>;
                                                   >> 5324                         polling-delay = <1000>;
5749                                                  5325 
5750                         thermal-sensors = <&t    5326                         thermal-sensors = <&tsens0 11>;
5751                                                  5327 
5752                         cooling-maps {        << 
5753                                 map0 {        << 
5754                                         trip  << 
5755                                         cooli << 
5756                                 };            << 
5757                         };                    << 
5758                                               << 
5759                         trips {                  5328                         trips {
5760                                 gpu_top_alert !! 5329                                 gpu1_alert0: trip-point0 {
5761                                         tempe << 
5762                                         hyste << 
5763                                         type  << 
5764                                 };            << 
5765                                               << 
5766                                 trip-point1 { << 
5767                                         tempe    5330                                         temperature = <90000>;
5768                                         hyste !! 5331                                         hysteresis = <2000>;
5769                                         type     5332                                         type = "hot";
5770                                 };               5333                                 };
5771                                               << 
5772                                 trip-point2 { << 
5773                                         tempe << 
5774                                         hyste << 
5775                                         type  << 
5776                                 };            << 
5777                         };                       5334                         };
5778                 };                               5335                 };
5779                                                  5336 
5780                 gpu-bottom-thermal {             5337                 gpu-bottom-thermal {
5781                         polling-delay-passive    5338                         polling-delay-passive = <250>;
                                                   >> 5339                         polling-delay = <1000>;
5782                                                  5340 
5783                         thermal-sensors = <&t    5341                         thermal-sensors = <&tsens0 12>;
5784                                                  5342 
5785                         cooling-maps {        << 
5786                                 map0 {        << 
5787                                         trip  << 
5788                                         cooli << 
5789                                 };            << 
5790                         };                    << 
5791                                               << 
5792                         trips {                  5343                         trips {
5793                                 gpu_bottom_al !! 5344                                 gpu2_alert0: trip-point0 {
5794                                         tempe << 
5795                                         hyste << 
5796                                         type  << 
5797                                 };            << 
5798                                               << 
5799                                 trip-point1 { << 
5800                                         tempe    5345                                         temperature = <90000>;
5801                                         hyste !! 5346                                         hysteresis = <2000>;
5802                                         type     5347                                         type = "hot";
5803                                 };               5348                                 };
5804                                               << 
5805                                 trip-point2 { << 
5806                                         tempe << 
5807                                         hyste << 
5808                                         type  << 
5809                                 };            << 
5810                         };                       5349                         };
5811                 };                               5350                 };
5812                                                  5351 
5813                 aoss1-thermal {                  5352                 aoss1-thermal {
5814                         polling-delay-passive    5353                         polling-delay-passive = <250>;
                                                   >> 5354                         polling-delay = <1000>;
5815                                                  5355 
5816                         thermal-sensors = <&t    5356                         thermal-sensors = <&tsens1 0>;
5817                                                  5357 
5818                         trips {                  5358                         trips {
5819                                 aoss1_alert0:    5359                                 aoss1_alert0: trip-point0 {
5820                                         tempe    5360                                         temperature = <90000>;
5821                                         hyste    5361                                         hysteresis = <2000>;
5822                                         type     5362                                         type = "hot";
5823                                 };               5363                                 };
5824                         };                       5364                         };
5825                 };                               5365                 };
5826                                                  5366 
5827                 q6-modem-thermal {               5367                 q6-modem-thermal {
5828                         polling-delay-passive    5368                         polling-delay-passive = <250>;
                                                   >> 5369                         polling-delay = <1000>;
5829                                                  5370 
5830                         thermal-sensors = <&t    5371                         thermal-sensors = <&tsens1 1>;
5831                                                  5372 
5832                         trips {                  5373                         trips {
5833                                 q6_modem_aler    5374                                 q6_modem_alert0: trip-point0 {
5834                                         tempe    5375                                         temperature = <90000>;
5835                                         hyste    5376                                         hysteresis = <2000>;
5836                                         type     5377                                         type = "hot";
5837                                 };               5378                                 };
5838                         };                       5379                         };
5839                 };                               5380                 };
5840                                                  5381 
5841                 mem-thermal {                    5382                 mem-thermal {
5842                         polling-delay-passive    5383                         polling-delay-passive = <250>;
                                                   >> 5384                         polling-delay = <1000>;
5843                                                  5385 
5844                         thermal-sensors = <&t    5386                         thermal-sensors = <&tsens1 2>;
5845                                                  5387 
5846                         trips {                  5388                         trips {
5847                                 mem_alert0: t    5389                                 mem_alert0: trip-point0 {
5848                                         tempe    5390                                         temperature = <90000>;
5849                                         hyste    5391                                         hysteresis = <2000>;
5850                                         type     5392                                         type = "hot";
5851                                 };               5393                                 };
5852                         };                       5394                         };
5853                 };                               5395                 };
5854                                                  5396 
5855                 wlan-thermal {                   5397                 wlan-thermal {
5856                         polling-delay-passive    5398                         polling-delay-passive = <250>;
                                                   >> 5399                         polling-delay = <1000>;
5857                                                  5400 
5858                         thermal-sensors = <&t    5401                         thermal-sensors = <&tsens1 3>;
5859                                                  5402 
5860                         trips {                  5403                         trips {
5861                                 wlan_alert0:     5404                                 wlan_alert0: trip-point0 {
5862                                         tempe    5405                                         temperature = <90000>;
5863                                         hyste    5406                                         hysteresis = <2000>;
5864                                         type     5407                                         type = "hot";
5865                                 };               5408                                 };
5866                         };                       5409                         };
5867                 };                               5410                 };
5868                                                  5411 
5869                 q6-hvx-thermal {                 5412                 q6-hvx-thermal {
5870                         polling-delay-passive    5413                         polling-delay-passive = <250>;
                                                   >> 5414                         polling-delay = <1000>;
5871                                                  5415 
5872                         thermal-sensors = <&t    5416                         thermal-sensors = <&tsens1 4>;
5873                                                  5417 
5874                         trips {                  5418                         trips {
5875                                 q6_hvx_alert0    5419                                 q6_hvx_alert0: trip-point0 {
5876                                         tempe    5420                                         temperature = <90000>;
5877                                         hyste    5421                                         hysteresis = <2000>;
5878                                         type     5422                                         type = "hot";
5879                                 };               5423                                 };
5880                         };                       5424                         };
5881                 };                               5425                 };
5882                                                  5426 
5883                 camera-thermal {                 5427                 camera-thermal {
5884                         polling-delay-passive    5428                         polling-delay-passive = <250>;
                                                   >> 5429                         polling-delay = <1000>;
5885                                                  5430 
5886                         thermal-sensors = <&t    5431                         thermal-sensors = <&tsens1 5>;
5887                                                  5432 
5888                         trips {                  5433                         trips {
5889                                 camera_alert0    5434                                 camera_alert0: trip-point0 {
5890                                         tempe    5435                                         temperature = <90000>;
5891                                         hyste    5436                                         hysteresis = <2000>;
5892                                         type     5437                                         type = "hot";
5893                                 };               5438                                 };
5894                         };                       5439                         };
5895                 };                               5440                 };
5896                                                  5441 
5897                 video-thermal {                  5442                 video-thermal {
5898                         polling-delay-passive    5443                         polling-delay-passive = <250>;
                                                   >> 5444                         polling-delay = <1000>;
5899                                                  5445 
5900                         thermal-sensors = <&t    5446                         thermal-sensors = <&tsens1 6>;
5901                                                  5447 
5902                         trips {                  5448                         trips {
5903                                 video_alert0:    5449                                 video_alert0: trip-point0 {
5904                                         tempe    5450                                         temperature = <90000>;
5905                                         hyste    5451                                         hysteresis = <2000>;
5906                                         type     5452                                         type = "hot";
5907                                 };               5453                                 };
5908                         };                       5454                         };
5909                 };                               5455                 };
5910                                                  5456 
5911                 modem-thermal {                  5457                 modem-thermal {
5912                         polling-delay-passive    5458                         polling-delay-passive = <250>;
                                                   >> 5459                         polling-delay = <1000>;
5913                                                  5460 
5914                         thermal-sensors = <&t    5461                         thermal-sensors = <&tsens1 7>;
5915                                                  5462 
5916                         trips {                  5463                         trips {
5917                                 modem_alert0:    5464                                 modem_alert0: trip-point0 {
5918                                         tempe    5465                                         temperature = <90000>;
5919                                         hyste    5466                                         hysteresis = <2000>;
5920                                         type     5467                                         type = "hot";
5921                                 };               5468                                 };
5922                         };                       5469                         };
5923                 };                               5470                 };
5924         };                                    << 
5925                                               << 
5926         timer {                               << 
5927                 compatible = "arm,armv8-timer << 
5928                 interrupts = <GIC_PPI 1 IRQ_T << 
5929                              <GIC_PPI 2 IRQ_T << 
5930                              <GIC_PPI 3 IRQ_T << 
5931                              <GIC_PPI 0 IRQ_T << 
5932         };                                       5471         };
5933 };                                               5472 };
                                                      

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