1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. <<
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> <<
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 <<
20 #include <dt-bindings/interconnect/qcom,sdm845 14 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> <<
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 21 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
31 23
32 / { 24 / {
33 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
34 26
35 #address-cells = <2>; 27 #address-cells = <2>;
36 #size-cells = <2>; 28 #size-cells = <2>;
37 29
38 aliases { 30 aliases {
39 i2c0 = &i2c0; 31 i2c0 = &i2c0;
40 i2c1 = &i2c1; 32 i2c1 = &i2c1;
41 i2c2 = &i2c2; 33 i2c2 = &i2c2;
42 i2c3 = &i2c3; 34 i2c3 = &i2c3;
43 i2c4 = &i2c4; 35 i2c4 = &i2c4;
44 i2c5 = &i2c5; 36 i2c5 = &i2c5;
45 i2c6 = &i2c6; 37 i2c6 = &i2c6;
46 i2c7 = &i2c7; 38 i2c7 = &i2c7;
47 i2c8 = &i2c8; 39 i2c8 = &i2c8;
48 i2c9 = &i2c9; 40 i2c9 = &i2c9;
49 i2c10 = &i2c10; 41 i2c10 = &i2c10;
50 i2c11 = &i2c11; 42 i2c11 = &i2c11;
51 i2c12 = &i2c12; 43 i2c12 = &i2c12;
52 i2c13 = &i2c13; 44 i2c13 = &i2c13;
53 i2c14 = &i2c14; 45 i2c14 = &i2c14;
54 i2c15 = &i2c15; 46 i2c15 = &i2c15;
55 spi0 = &spi0; 47 spi0 = &spi0;
56 spi1 = &spi1; 48 spi1 = &spi1;
57 spi2 = &spi2; 49 spi2 = &spi2;
58 spi3 = &spi3; 50 spi3 = &spi3;
59 spi4 = &spi4; 51 spi4 = &spi4;
60 spi5 = &spi5; 52 spi5 = &spi5;
61 spi6 = &spi6; 53 spi6 = &spi6;
62 spi7 = &spi7; 54 spi7 = &spi7;
63 spi8 = &spi8; 55 spi8 = &spi8;
64 spi9 = &spi9; 56 spi9 = &spi9;
65 spi10 = &spi10; 57 spi10 = &spi10;
66 spi11 = &spi11; 58 spi11 = &spi11;
67 spi12 = &spi12; 59 spi12 = &spi12;
68 spi13 = &spi13; 60 spi13 = &spi13;
69 spi14 = &spi14; 61 spi14 = &spi14;
70 spi15 = &spi15; 62 spi15 = &spi15;
71 }; 63 };
72 64
73 chosen { }; 65 chosen { };
74 66
75 clocks { !! 67 memory@80000000 {
76 xo_board: xo-board { !! 68 device_type = "memory";
77 compatible = "fixed-cl !! 69 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 70 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 71 };
80 clock-output-names = " !! 72
>> 73 reserved-memory {
>> 74 #address-cells = <2>;
>> 75 #size-cells = <2>;
>> 76 ranges;
>> 77
>> 78 hyp_mem: memory@85700000 {
>> 79 reg = <0 0x85700000 0 0x600000>;
>> 80 no-map;
81 }; 81 };
82 82
83 sleep_clk: sleep-clk { !! 83 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 84 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 85 no-map;
86 clock-frequency = <327 !! 86 };
>> 87
>> 88 aop_mem: memory@85fc0000 {
>> 89 reg = <0 0x85fc0000 0 0x20000>;
>> 90 no-map;
>> 91 };
>> 92
>> 93 aop_cmd_db_mem: memory@85fe0000 {
>> 94 compatible = "qcom,cmd-db";
>> 95 reg = <0x0 0x85fe0000 0 0x20000>;
>> 96 no-map;
>> 97 };
>> 98
>> 99 smem_mem: memory@86000000 {
>> 100 reg = <0x0 0x86000000 0 0x200000>;
>> 101 no-map;
>> 102 };
>> 103
>> 104 tz_mem: memory@86200000 {
>> 105 reg = <0 0x86200000 0 0x2d00000>;
>> 106 no-map;
>> 107 };
>> 108
>> 109 rmtfs_mem: memory@88f00000 {
>> 110 compatible = "qcom,rmtfs-mem";
>> 111 reg = <0 0x88f00000 0 0x200000>;
>> 112 no-map;
>> 113
>> 114 qcom,client-id = <1>;
>> 115 qcom,vmid = <15>;
>> 116 };
>> 117
>> 118 qseecom_mem: memory@8ab00000 {
>> 119 reg = <0 0x8ab00000 0 0x1400000>;
>> 120 no-map;
>> 121 };
>> 122
>> 123 camera_mem: memory@8bf00000 {
>> 124 reg = <0 0x8bf00000 0 0x500000>;
>> 125 no-map;
>> 126 };
>> 127
>> 128 ipa_fw_mem: memory@8c400000 {
>> 129 reg = <0 0x8c400000 0 0x10000>;
>> 130 no-map;
>> 131 };
>> 132
>> 133 ipa_gsi_mem: memory@8c410000 {
>> 134 reg = <0 0x8c410000 0 0x5000>;
>> 135 no-map;
>> 136 };
>> 137
>> 138 gpu_mem: memory@8c415000 {
>> 139 reg = <0 0x8c415000 0 0x2000>;
>> 140 no-map;
>> 141 };
>> 142
>> 143 adsp_mem: memory@8c500000 {
>> 144 reg = <0 0x8c500000 0 0x1a00000>;
>> 145 no-map;
>> 146 };
>> 147
>> 148 wlan_msa_mem: memory@8df00000 {
>> 149 reg = <0 0x8df00000 0 0x100000>;
>> 150 no-map;
>> 151 };
>> 152
>> 153 mpss_region: memory@8e000000 {
>> 154 reg = <0 0x8e000000 0 0x7800000>;
>> 155 no-map;
>> 156 };
>> 157
>> 158 venus_mem: memory@95800000 {
>> 159 reg = <0 0x95800000 0 0x500000>;
>> 160 no-map;
>> 161 };
>> 162
>> 163 cdsp_mem: memory@95d00000 {
>> 164 reg = <0 0x95d00000 0 0x800000>;
>> 165 no-map;
>> 166 };
>> 167
>> 168 mba_region: memory@96500000 {
>> 169 reg = <0 0x96500000 0 0x200000>;
>> 170 no-map;
>> 171 };
>> 172
>> 173 slpi_mem: memory@96700000 {
>> 174 reg = <0 0x96700000 0 0x1400000>;
>> 175 no-map;
>> 176 };
>> 177
>> 178 spss_mem: memory@97b00000 {
>> 179 reg = <0 0x97b00000 0 0x100000>;
>> 180 no-map;
87 }; 181 };
88 }; 182 };
89 183
90 cpus: cpus { !! 184 cpus {
91 #address-cells = <2>; 185 #address-cells = <2>;
92 #size-cells = <0>; 186 #size-cells = <0>;
93 187
94 CPU0: cpu@0 { 188 CPU0: cpu@0 {
95 device_type = "cpu"; 189 device_type = "cpu";
96 compatible = "qcom,kry 190 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 191 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 192 enable-method = "psci";
100 capacity-dmips-mhz = < !! 193 capacity-dmips-mhz = <607>;
101 dynamic-power-coeffici <<
102 qcom,freq-domain = <&c 194 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = <<
104 interconnects = <&glad <<
105 <&osm_ <<
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 195 #cooling-cells = <2>;
109 next-level-cache = <&L 196 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 197 L2_0: l2-cache {
111 compatible = " 198 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 199 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 200 L3_0: l3-cache {
116 compat !! 201 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 202 };
120 }; 203 };
121 }; 204 };
122 205
123 CPU1: cpu@100 { 206 CPU1: cpu@100 {
124 device_type = "cpu"; 207 device_type = "cpu";
125 compatible = "qcom,kry 208 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 209 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 210 enable-method = "psci";
129 capacity-dmips-mhz = < !! 211 capacity-dmips-mhz = <607>;
130 dynamic-power-coeffici <<
131 qcom,freq-domain = <&c 212 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <<
133 interconnects = <&glad <<
134 <&osm_ <<
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 213 #cooling-cells = <2>;
138 next-level-cache = <&L 214 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 215 L2_100: l2-cache {
140 compatible = " 216 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 217 next-level-cache = <&L3_0>;
144 }; 218 };
145 }; 219 };
146 220
147 CPU2: cpu@200 { 221 CPU2: cpu@200 {
148 device_type = "cpu"; 222 device_type = "cpu";
149 compatible = "qcom,kry 223 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 224 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 225 enable-method = "psci";
153 capacity-dmips-mhz = < !! 226 capacity-dmips-mhz = <607>;
154 dynamic-power-coeffici <<
155 qcom,freq-domain = <&c 227 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = <<
157 interconnects = <&glad <<
158 <&osm_ <<
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 228 #cooling-cells = <2>;
162 next-level-cache = <&L 229 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 230 L2_200: l2-cache {
164 compatible = " 231 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 232 next-level-cache = <&L3_0>;
168 }; 233 };
169 }; 234 };
170 235
171 CPU3: cpu@300 { 236 CPU3: cpu@300 {
172 device_type = "cpu"; 237 device_type = "cpu";
173 compatible = "qcom,kry 238 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 239 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 240 enable-method = "psci";
177 capacity-dmips-mhz = < !! 241 capacity-dmips-mhz = <607>;
178 dynamic-power-coeffici <<
179 qcom,freq-domain = <&c 242 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = <<
181 interconnects = <&glad <<
182 <&osm_ <<
183 #cooling-cells = <2>; 243 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 244 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 245 L2_300: l2-cache {
188 compatible = " 246 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 247 next-level-cache = <&L3_0>;
192 }; 248 };
193 }; 249 };
194 250
195 CPU4: cpu@400 { 251 CPU4: cpu@400 {
196 device_type = "cpu"; 252 device_type = "cpu";
197 compatible = "qcom,kry 253 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 254 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 255 enable-method = "psci";
201 capacity-dmips-mhz = < 256 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici <<
203 qcom,freq-domain = <&c 257 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = <<
205 interconnects = <&glad <<
206 <&osm_ <<
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 258 #cooling-cells = <2>;
210 next-level-cache = <&L 259 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 260 L2_400: l2-cache {
212 compatible = " 261 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 262 next-level-cache = <&L3_0>;
216 }; 263 };
217 }; 264 };
218 265
219 CPU5: cpu@500 { 266 CPU5: cpu@500 {
220 device_type = "cpu"; 267 device_type = "cpu";
221 compatible = "qcom,kry 268 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 269 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 270 enable-method = "psci";
225 capacity-dmips-mhz = < 271 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici <<
227 qcom,freq-domain = <&c 272 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = <<
229 interconnects = <&glad <<
230 <&osm_ <<
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 273 #cooling-cells = <2>;
234 next-level-cache = <&L 274 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 275 L2_500: l2-cache {
236 compatible = " 276 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 277 next-level-cache = <&L3_0>;
240 }; 278 };
241 }; 279 };
242 280
243 CPU6: cpu@600 { 281 CPU6: cpu@600 {
244 device_type = "cpu"; 282 device_type = "cpu";
245 compatible = "qcom,kry 283 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 284 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 285 enable-method = "psci";
249 capacity-dmips-mhz = < 286 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici <<
251 qcom,freq-domain = <&c 287 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = <<
253 interconnects = <&glad <<
254 <&osm_ <<
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 288 #cooling-cells = <2>;
258 next-level-cache = <&L 289 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 290 L2_600: l2-cache {
260 compatible = " 291 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 292 next-level-cache = <&L3_0>;
264 }; 293 };
265 }; 294 };
266 295
267 CPU7: cpu@700 { 296 CPU7: cpu@700 {
268 device_type = "cpu"; 297 device_type = "cpu";
269 compatible = "qcom,kry 298 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 299 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 300 enable-method = "psci";
273 capacity-dmips-mhz = < 301 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici <<
275 qcom,freq-domain = <&c 302 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = <<
277 interconnects = <&glad <<
278 <&osm_ <<
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 303 #cooling-cells = <2>;
282 next-level-cache = <&L 304 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 305 L2_700: l2-cache {
284 compatible = " 306 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 307 next-level-cache = <&L3_0>;
288 }; 308 };
289 }; 309 };
290 310
291 cpu-map { 311 cpu-map {
292 cluster0 { 312 cluster0 {
293 core0 { 313 core0 {
294 cpu = 314 cpu = <&CPU0>;
295 }; 315 };
296 316
297 core1 { 317 core1 {
298 cpu = 318 cpu = <&CPU1>;
299 }; 319 };
300 320
301 core2 { 321 core2 {
302 cpu = 322 cpu = <&CPU2>;
303 }; 323 };
304 324
305 core3 { 325 core3 {
306 cpu = 326 cpu = <&CPU3>;
307 }; 327 };
>> 328 };
308 329
309 core4 { !! 330 cluster1 {
>> 331 core0 {
310 cpu = 332 cpu = <&CPU4>;
311 }; 333 };
312 334
313 core5 { !! 335 core1 {
314 cpu = 336 cpu = <&CPU5>;
315 }; 337 };
316 338
317 core6 { !! 339 core2 {
318 cpu = 340 cpu = <&CPU6>;
319 }; 341 };
320 342
321 core7 { !! 343 core3 {
322 cpu = 344 cpu = <&CPU7>;
323 }; 345 };
324 }; 346 };
325 }; 347 };
326 <<
327 cpu_idle_states: idle-states { <<
328 entry-method = "psci"; <<
329 <<
330 LITTLE_CPU_SLEEP_0: cp <<
331 compatible = " <<
332 idle-state-nam <<
333 arm,psci-suspe <<
334 entry-latency- <<
335 exit-latency-u <<
336 min-residency- <<
337 local-timer-st <<
338 }; <<
339 <<
340 BIG_CPU_SLEEP_0: cpu-s <<
341 compatible = " <<
342 idle-state-nam <<
343 arm,psci-suspe <<
344 entry-latency- <<
345 exit-latency-u <<
346 min-residency- <<
347 local-timer-st <<
348 }; <<
349 }; <<
350 <<
351 domain-idle-states { <<
352 CLUSTER_SLEEP_0: clust <<
353 compatible = " <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 }; <<
359 }; <<
360 }; <<
361 <<
362 firmware { <<
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points <<
376 opp-shared; <<
377 <<
378 cpu0_opp1: opp-300000000 { <<
379 opp-hz = /bits/ 64 <30 <<
380 opp-peak-kBps = <80000 <<
381 }; <<
382 <<
383 cpu0_opp2: opp-403200000 { <<
384 opp-hz = /bits/ 64 <40 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp3: opp-480000000 { <<
389 opp-hz = /bits/ 64 <48 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp4: opp-576000000 { <<
394 opp-hz = /bits/ 64 <57 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp5: opp-652800000 { <<
399 opp-hz = /bits/ 64 <65 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp6: opp-748800000 { <<
404 opp-hz = /bits/ 64 <74 <<
405 opp-peak-kBps = <18040 <<
406 }; <<
407 <<
408 cpu0_opp7: opp-825600000 { <<
409 opp-hz = /bits/ 64 <82 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp8: opp-902400000 { <<
414 opp-hz = /bits/ 64 <90 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp9: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp10: opp-1056000000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp11: opp-1132800000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu0_opp12: opp-1228800000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <21880 <<
436 }; <<
437 <<
438 cpu0_opp13: opp-1324800000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp14: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <30720 <<
446 }; <<
447 <<
448 cpu0_opp15: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp16: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <40680 <<
456 }; <<
457 <<
458 cpu0_opp17: opp-1689600000 { <<
459 opp-hz = /bits/ 64 <16 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp18: opp-1766400000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-300000000 { <<
474 opp-hz = /bits/ 64 <30 <<
475 opp-peak-kBps = <80000 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-403200000 { <<
479 opp-hz = /bits/ 64 <40 <<
480 opp-peak-kBps = <80000 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-480000000 { <<
484 opp-hz = /bits/ 64 <48 <<
485 opp-peak-kBps = <18040 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-576000000 { <<
489 opp-hz = /bits/ 64 <57 <<
490 opp-peak-kBps = <18040 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-652800000 { <<
494 opp-hz = /bits/ 64 <65 <<
495 opp-peak-kBps = <18040 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-748800000 { <<
499 opp-hz = /bits/ 64 <74 <<
500 opp-peak-kBps = <18040 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-825600000 { <<
504 opp-hz = /bits/ 64 <82 <<
505 opp-peak-kBps = <21880 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-902400000 { <<
509 opp-hz = /bits/ 64 <90 <<
510 opp-peak-kBps = <21880 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-979200000 { <<
514 opp-hz = /bits/ 64 <97 <<
515 opp-peak-kBps = <21880 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1056000000 { <<
519 opp-hz = /bits/ 64 <10 <<
520 opp-peak-kBps = <30720 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1132800000 { <<
524 opp-hz = /bits/ 64 <11 <<
525 opp-peak-kBps = <30720 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1209600000 { <<
529 opp-hz = /bits/ 64 <12 <<
530 opp-peak-kBps = <40680 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1286400000 { <<
534 opp-hz = /bits/ 64 <12 <<
535 opp-peak-kBps = <40680 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-1363200000 { <<
539 opp-hz = /bits/ 64 <13 <<
540 opp-peak-kBps = <40680 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-1459200000 { <<
544 opp-hz = /bits/ 64 <14 <<
545 opp-peak-kBps = <40680 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-1536000000 { <<
549 opp-hz = /bits/ 64 <15 <<
550 opp-peak-kBps = <54120 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-1612800000 { <<
554 opp-hz = /bits/ 64 <16 <<
555 opp-peak-kBps = <54120 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-1689600000 { <<
559 opp-hz = /bits/ 64 <16 <<
560 opp-peak-kBps = <54120 <<
561 }; <<
562 <<
563 cpu4_opp19: opp-1766400000 { <<
564 opp-hz = /bits/ 64 <17 <<
565 opp-peak-kBps = <62200 <<
566 }; <<
567 <<
568 cpu4_opp20: opp-1843200000 { <<
569 opp-hz = /bits/ 64 <18 <<
570 opp-peak-kBps = <62200 <<
571 }; <<
572 <<
573 cpu4_opp21: opp-1920000000 { <<
574 opp-hz = /bits/ 64 <19 <<
575 opp-peak-kBps = <72160 <<
576 }; <<
577 <<
578 cpu4_opp22: opp-1996800000 { <<
579 opp-hz = /bits/ 64 <19 <<
580 opp-peak-kBps = <72160 <<
581 }; <<
582 <<
583 cpu4_opp23: opp-2092800000 { <<
584 opp-hz = /bits/ 64 <20 <<
585 opp-peak-kBps = <72160 <<
586 }; <<
587 <<
588 cpu4_opp24: opp-2169600000 { <<
589 opp-hz = /bits/ 64 <21 <<
590 opp-peak-kBps = <72160 <<
591 }; <<
592 <<
593 cpu4_opp25: opp-2246400000 { <<
594 opp-hz = /bits/ 64 <22 <<
595 opp-peak-kBps = <72160 <<
596 }; <<
597 <<
598 cpu4_opp26: opp-2323200000 { <<
599 opp-hz = /bits/ 64 <23 <<
600 opp-peak-kBps = <72160 <<
601 }; <<
602 <<
603 cpu4_opp27: opp-2400000000 { <<
604 opp-hz = /bits/ 64 <24 <<
605 opp-peak-kBps = <72160 <<
606 }; <<
607 <<
608 cpu4_opp28: opp-2476800000 { <<
609 opp-hz = /bits/ 64 <24 <<
610 opp-peak-kBps = <72160 <<
611 }; <<
612 <<
613 cpu4_opp29: opp-2553600000 { <<
614 opp-hz = /bits/ 64 <25 <<
615 opp-peak-kBps = <72160 <<
616 }; <<
617 <<
618 cpu4_opp30: opp-2649600000 { <<
619 opp-hz = /bits/ 64 <26 <<
620 opp-peak-kBps = <72160 <<
621 }; <<
622 <<
623 cpu4_opp31: opp-2745600000 { <<
624 opp-hz = /bits/ 64 <27 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu4_opp32: opp-2803200000 { <<
629 opp-hz = /bits/ 64 <28 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 }; <<
633 <<
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; 348 };
710 349
711 pmu { 350 pmu {
712 compatible = "arm,armv8-pmuv3" 351 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 352 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 353 };
715 354
716 psci: psci { !! 355 timer {
717 compatible = "arm,psci-1.0"; !! 356 compatible = "arm,armv8-timer";
718 method = "smc"; !! 357 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 358 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 359 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 360 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 361 };
773 362
774 reserved-memory { !! 363 clocks {
775 #address-cells = <2>; !! 364 xo_board: xo-board {
776 #size-cells = <2>; !! 365 compatible = "fixed-clock";
777 ranges; !! 366 #clock-cells = <0>;
778 !! 367 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 368 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 369 };
885 370
886 mdata_mem: mpss-metadata { !! 371 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 372 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 373 #clock-cells = <0>;
889 no-map; !! 374 clock-frequency = <32764>;
890 }; 375 };
>> 376 };
891 377
892 fastrpc_mem: fastrpc { !! 378 firmware {
893 compatible = "shared-d !! 379 scm {
894 alloc-ranges = <0x0 0x !! 380 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 381 };
899 }; 382 };
900 383
901 adsp_pas: remoteproc-adsp { 384 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 385 compatible = "qcom,sdm845-adsp-pas";
903 386
904 interrupts-extended = <&intc G 387 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 388 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 389 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 390 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 391 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 392 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 393 "handover", "stop-ack";
911 394
912 clocks = <&rpmhcc RPMH_CXO_CLK 395 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 396 clock-names = "xo";
914 397
915 memory-region = <&adsp_mem>; 398 memory-region = <&adsp_mem>;
916 399
917 qcom,qmp = <&aoss_qmp>; <<
918 <<
919 qcom,smem-states = <&adsp_smp2 400 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 401 qcom,smem-state-names = "stop";
921 402
922 status = "disabled"; 403 status = "disabled";
923 404
924 glink-edge { 405 glink-edge {
925 interrupts = <GIC_SPI 406 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 407 label = "lpass";
927 qcom,remote-pid = <2>; 408 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 409 mboxes = <&apss_shared 8>;
929 <<
930 apr { <<
931 compatible = " <<
932 qcom,glink-cha <<
933 qcom,domain = <<
934 #address-cells <<
935 #size-cells = <<
936 qcom,intents = <<
937 <<
938 service@3 { <<
939 reg = <<
940 compat <<
941 qcom,p <<
942 }; <<
943 <<
944 q6afe: service <<
945 compat <<
946 reg = <<
947 qcom,p <<
948 q6afed <<
949 <<
950 <<
951 <<
952 <<
953 }; <<
954 }; <<
955 <<
956 q6asm: service <<
957 compat <<
958 reg = <<
959 qcom,p <<
960 q6asmd <<
961 <<
962 <<
963 <<
964 <<
965 <<
966 }; <<
967 }; <<
968 <<
969 q6adm: service <<
970 compat <<
971 reg = <<
972 qcom,p <<
973 q6rout <<
974 <<
975 <<
976 }; <<
977 }; <<
978 }; <<
979 <<
980 fastrpc { <<
981 compatible = " <<
982 qcom,glink-cha <<
983 label = "adsp" <<
984 qcom,non-secur <<
985 #address-cells <<
986 #size-cells = <<
987 <<
988 compute-cb@3 { <<
989 compat <<
990 reg = <<
991 iommus <<
992 }; <<
993 <<
994 compute-cb@4 { <<
995 compat <<
996 reg = <<
997 iommus <<
998 }; <<
999 }; <<
1000 }; 410 };
1001 }; 411 };
1002 412
1003 cdsp_pas: remoteproc-cdsp { 413 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 414 compatible = "qcom,sdm845-cdsp-pas";
1005 415
1006 interrupts-extended = <&intc 416 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 417 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 418 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 419 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 420 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 421 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 422 "handover", "stop-ack";
1013 423
1014 clocks = <&rpmhcc RPMH_CXO_CL 424 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 425 clock-names = "xo";
1016 426
1017 memory-region = <&cdsp_mem>; 427 memory-region = <&cdsp_mem>;
1018 428
1019 qcom,qmp = <&aoss_qmp>; <<
1020 <<
1021 qcom,smem-states = <&cdsp_smp 429 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 430 qcom,smem-state-names = "stop";
1023 431
1024 status = "disabled"; 432 status = "disabled";
1025 433
1026 glink-edge { 434 glink-edge {
1027 interrupts = <GIC_SPI 435 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 436 label = "turing";
1029 qcom,remote-pid = <5> 437 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 438 mboxes = <&apss_shared 4>;
1031 fastrpc { !! 439 };
1032 compatible = !! 440 };
1033 qcom,glink-ch <<
1034 label = "cdsp <<
1035 qcom,non-secu <<
1036 #address-cell <<
1037 #size-cells = <<
1038 <<
1039 compute-cb@1 <<
1040 compa <<
1041 reg = <<
1042 iommu <<
1043 }; <<
1044 <<
1045 compute-cb@2 <<
1046 compa <<
1047 reg = <<
1048 iommu <<
1049 }; <<
1050 <<
1051 compute-cb@3 <<
1052 compa <<
1053 reg = <<
1054 iommu <<
1055 }; <<
1056 <<
1057 compute-cb@4 <<
1058 compa <<
1059 reg = <<
1060 iommu <<
1061 }; <<
1062 <<
1063 compute-cb@5 <<
1064 compa <<
1065 reg = <<
1066 iommu <<
1067 }; <<
1068 <<
1069 compute-cb@6 <<
1070 compa <<
1071 reg = <<
1072 iommu <<
1073 }; <<
1074 441
1075 compute-cb@7 !! 442 tcsr_mutex: hwlock {
1076 compa !! 443 compatible = "qcom,tcsr-mutex";
1077 reg = !! 444 syscon = <&tcsr_mutex_regs 0 0x1000>;
1078 iommu !! 445 #hwlock-cells = <1>;
1079 }; !! 446 };
1080 447
1081 compute-cb@8 !! 448 smem {
1082 compa !! 449 compatible = "qcom,smem";
1083 reg = !! 450 memory-region = <&smem_mem>;
1084 iommu !! 451 hwlocks = <&tcsr_mutex 3>;
1085 }; <<
1086 }; <<
1087 }; <<
1088 }; 452 };
1089 453
1090 smp2p-cdsp { 454 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 455 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 456 qcom,smem = <94>, <432>;
1093 457
1094 interrupts = <GIC_SPI 576 IRQ 458 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 459
1096 mboxes = <&apss_shared 6>; 460 mboxes = <&apss_shared 6>;
1097 461
1098 qcom,local-pid = <0>; 462 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 463 qcom,remote-pid = <5>;
1100 464
1101 cdsp_smp2p_out: master-kernel 465 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 466 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 467 #qcom,smem-state-cells = <1>;
1104 }; 468 };
1105 469
1106 cdsp_smp2p_in: slave-kernel { 470 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 471 qcom,entry-name = "slave-kernel";
1108 472
1109 interrupt-controller; 473 interrupt-controller;
1110 #interrupt-cells = <2 474 #interrupt-cells = <2>;
1111 }; 475 };
1112 }; 476 };
1113 477
1114 smp2p-lpass { 478 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 479 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 480 qcom,smem = <443>, <429>;
1117 481
1118 interrupts = <GIC_SPI 158 IRQ 482 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 483
1120 mboxes = <&apss_shared 10>; 484 mboxes = <&apss_shared 10>;
1121 485
1122 qcom,local-pid = <0>; 486 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 487 qcom,remote-pid = <2>;
1124 488
1125 adsp_smp2p_out: master-kernel 489 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 490 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 491 #qcom,smem-state-cells = <1>;
1128 }; 492 };
1129 493
1130 adsp_smp2p_in: slave-kernel { 494 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 495 qcom,entry-name = "slave-kernel";
1132 496
1133 interrupt-controller; 497 interrupt-controller;
1134 #interrupt-cells = <2 498 #interrupt-cells = <2>;
1135 }; 499 };
1136 }; 500 };
1137 501
1138 smp2p-mpss { 502 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 503 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 504 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 505 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 506 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 507 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 508 qcom,remote-pid = <1>;
1145 509
1146 modem_smp2p_out: master-kerne 510 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 511 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 512 #qcom,smem-state-cells = <1>;
1149 }; 513 };
1150 514
1151 modem_smp2p_in: slave-kernel 515 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 516 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 517 interrupt-controller;
1154 #interrupt-cells = <2 518 #interrupt-cells = <2>;
1155 }; 519 };
1156 <<
1157 ipa_smp2p_out: ipa-ap-to-mode <<
1158 qcom,entry-name = "ip <<
1159 #qcom,smem-state-cell <<
1160 }; <<
1161 <<
1162 ipa_smp2p_in: ipa-modem-to-ap <<
1163 qcom,entry-name = "ip <<
1164 interrupt-controller; <<
1165 #interrupt-cells = <2 <<
1166 }; <<
1167 }; 520 };
1168 521
1169 smp2p-slpi { 522 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 523 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 524 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 525 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 526 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 527 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 528 qcom,remote-pid = <3>;
1176 529
1177 slpi_smp2p_out: master-kernel 530 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 531 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 532 #qcom,smem-state-cells = <1>;
1180 }; 533 };
1181 534
1182 slpi_smp2p_in: slave-kernel { 535 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 536 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 537 interrupt-controller;
1185 #interrupt-cells = <2 538 #interrupt-cells = <2>;
1186 }; 539 };
1187 }; 540 };
1188 541
1189 soc: soc@0 { !! 542 psci {
>> 543 compatible = "arm,psci-1.0";
>> 544 method = "smc";
>> 545 };
>> 546
>> 547 soc: soc {
1190 #address-cells = <2>; 548 #address-cells = <2>;
1191 #size-cells = <2>; 549 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 550 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 551 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 552 compatible = "simple-bus";
1195 553
1196 gcc: clock-controller@100000 554 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 555 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 556 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM <<
1200 <&rpmhcc RPM <<
1201 <&sleep_clk> <<
1202 <&pcie0_phy> <<
1203 <&pcie1_phy> <<
1204 clock-names = "bi_tcx <<
1205 "bi_tcx <<
1206 "sleep_ <<
1207 "pcie_0 <<
1208 "pcie_1 <<
1209 #clock-cells = <1>; 557 #clock-cells = <1>;
1210 #reset-cells = <1>; 558 #reset-cells = <1>;
1211 #power-domain-cells = 559 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 560 };
1214 561
1215 qfprom@784000 { 562 qfprom@784000 {
1216 compatible = "qcom,sd !! 563 compatible = "qcom,qfprom";
1217 reg = <0 0x00784000 0 564 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 565 #address-cells = <1>;
1219 #size-cells = <1>; 566 #size-cells = <1>;
1220 567
1221 qusb2p_hstx_trim: hst 568 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 569 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 570 bits = <1 4>;
1224 }; 571 };
1225 572
1226 qusb2s_hstx_trim: hst 573 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 574 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 575 bits = <6 4>;
1229 }; 576 };
1230 }; 577 };
1231 578
1232 rng: rng@793000 { 579 rng: rng@793000 {
1233 compatible = "qcom,pr 580 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 581 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 582 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 583 clock-names = "core";
1237 }; 584 };
1238 585
1239 gpi_dma0: dma-controller@8000 <<
1240 #dma-cells = <3>; <<
1241 compatible = "qcom,sd <<
1242 reg = <0 0x00800000 0 <<
1243 interrupts = <GIC_SPI <<
1244 <GIC_SPI <<
1245 <GIC_SPI <<
1246 <GIC_SPI <<
1247 <GIC_SPI <<
1248 <GIC_SPI <<
1249 <GIC_SPI <<
1250 <GIC_SPI <<
1251 <GIC_SPI <<
1252 <GIC_SPI <<
1253 <GIC_SPI <<
1254 <GIC_SPI <<
1255 <GIC_SPI <<
1256 dma-channels = <13>; <<
1257 dma-channel-mask = <0 <<
1258 iommus = <&apps_smmu <<
1259 status = "disabled"; <<
1260 }; <<
1261 <<
1262 qupv3_id_0: geniqup@8c0000 { 586 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 587 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 588 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 589 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 590 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 591 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu <<
1269 #address-cells = <2>; 592 #address-cells = <2>;
1270 #size-cells = <2>; 593 #size-cells = <2>;
1271 ranges; 594 ranges;
1272 interconnects = <&agg <<
1273 interconnect-names = <<
1274 status = "disabled"; 595 status = "disabled";
1275 596
1276 i2c0: i2c@880000 { 597 i2c0: i2c@880000 {
1277 compatible = 598 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 599 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 600 clock-names = "se";
1280 clocks = <&gc 601 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 602 pinctrl-names = "default";
1282 pinctrl-0 = < 603 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 604 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 605 #address-cells = <1>;
1285 #size-cells = 606 #size-cells = <0>;
1286 power-domains <<
1287 operating-poi <<
1288 interconnects <<
1289 <<
1290 <<
1291 interconnect- <<
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 607 status = "disabled";
1296 }; 608 };
1297 609
1298 spi0: spi@880000 { 610 spi0: spi@880000 {
1299 compatible = 611 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 612 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 613 clock-names = "se";
1302 clocks = <&gc 614 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 615 pinctrl-names = "default";
1304 pinctrl-0 = < 616 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 617 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 618 #address-cells = <1>;
1307 #size-cells = 619 #size-cells = <0>;
1308 interconnects <<
1309 <<
1310 interconnect- <<
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 620 status = "disabled";
1315 }; 621 };
1316 622
1317 uart0: serial@880000 623 uart0: serial@880000 {
1318 compatible = 624 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 625 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 626 clock-names = "se";
1321 clocks = <&gc 627 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 628 pinctrl-names = "default";
1323 pinctrl-0 = < 629 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 630 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains <<
1326 operating-poi <<
1327 interconnects <<
1328 <<
1329 interconnect- <<
1330 status = "dis 631 status = "disabled";
1331 }; 632 };
1332 633
1333 i2c1: i2c@884000 { 634 i2c1: i2c@884000 {
1334 compatible = 635 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 636 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 637 clock-names = "se";
1337 clocks = <&gc 638 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 639 pinctrl-names = "default";
1339 pinctrl-0 = < 640 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 641 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 642 #address-cells = <1>;
1342 #size-cells = 643 #size-cells = <0>;
1343 power-domains <<
1344 operating-poi <<
1345 interconnects <<
1346 <<
1347 <<
1348 interconnect- <<
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 644 status = "disabled";
1353 }; 645 };
1354 646
1355 spi1: spi@884000 { 647 spi1: spi@884000 {
1356 compatible = 648 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 649 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 650 clock-names = "se";
1359 clocks = <&gc 651 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 652 pinctrl-names = "default";
1361 pinctrl-0 = < 653 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 654 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 655 #address-cells = <1>;
1364 #size-cells = 656 #size-cells = <0>;
1365 interconnects <<
1366 <<
1367 interconnect- <<
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 657 status = "disabled";
1372 }; 658 };
1373 659
1374 uart1: serial@884000 660 uart1: serial@884000 {
1375 compatible = 661 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 662 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 663 clock-names = "se";
1378 clocks = <&gc 664 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 665 pinctrl-names = "default";
1380 pinctrl-0 = < 666 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 667 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains <<
1383 operating-poi <<
1384 interconnects <<
1385 <<
1386 interconnect- <<
1387 status = "dis 668 status = "disabled";
1388 }; 669 };
1389 670
1390 i2c2: i2c@888000 { 671 i2c2: i2c@888000 {
1391 compatible = 672 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 673 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 674 clock-names = "se";
1394 clocks = <&gc 675 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 676 pinctrl-names = "default";
1396 pinctrl-0 = < 677 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 678 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 679 #address-cells = <1>;
1399 #size-cells = 680 #size-cells = <0>;
1400 power-domains <<
1401 operating-poi <<
1402 interconnects <<
1403 <<
1404 <<
1405 interconnect- <<
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 681 status = "disabled";
1410 }; 682 };
1411 683
1412 spi2: spi@888000 { 684 spi2: spi@888000 {
1413 compatible = 685 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 686 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 687 clock-names = "se";
1416 clocks = <&gc 688 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 689 pinctrl-names = "default";
1418 pinctrl-0 = < 690 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 691 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 692 #address-cells = <1>;
1421 #size-cells = 693 #size-cells = <0>;
1422 interconnects <<
1423 <<
1424 interconnect- <<
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 694 status = "disabled";
1429 }; 695 };
1430 696
1431 uart2: serial@888000 697 uart2: serial@888000 {
1432 compatible = 698 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 699 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 700 clock-names = "se";
1435 clocks = <&gc 701 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 702 pinctrl-names = "default";
1437 pinctrl-0 = < 703 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 704 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains <<
1440 operating-poi <<
1441 interconnects <<
1442 <<
1443 interconnect- <<
1444 status = "dis 705 status = "disabled";
1445 }; 706 };
1446 707
1447 i2c3: i2c@88c000 { 708 i2c3: i2c@88c000 {
1448 compatible = 709 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 710 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 711 clock-names = "se";
1451 clocks = <&gc 712 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 713 pinctrl-names = "default";
1453 pinctrl-0 = < 714 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 715 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 716 #address-cells = <1>;
1456 #size-cells = 717 #size-cells = <0>;
1457 power-domains <<
1458 operating-poi <<
1459 interconnects <<
1460 <<
1461 <<
1462 interconnect- <<
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 718 status = "disabled";
1467 }; 719 };
1468 720
1469 spi3: spi@88c000 { 721 spi3: spi@88c000 {
1470 compatible = 722 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 723 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 724 clock-names = "se";
1473 clocks = <&gc 725 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 726 pinctrl-names = "default";
1475 pinctrl-0 = < 727 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 728 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 729 #address-cells = <1>;
1478 #size-cells = 730 #size-cells = <0>;
1479 interconnects <<
1480 <<
1481 interconnect- <<
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 731 status = "disabled";
1486 }; 732 };
1487 733
1488 uart3: serial@88c000 734 uart3: serial@88c000 {
1489 compatible = 735 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 736 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 737 clock-names = "se";
1492 clocks = <&gc 738 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 739 pinctrl-names = "default";
1494 pinctrl-0 = < 740 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 741 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains <<
1497 operating-poi <<
1498 interconnects <<
1499 <<
1500 interconnect- <<
1501 status = "dis 742 status = "disabled";
1502 }; 743 };
1503 744
1504 i2c4: i2c@890000 { 745 i2c4: i2c@890000 {
1505 compatible = 746 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 747 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 748 clock-names = "se";
1508 clocks = <&gc 749 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 750 pinctrl-names = "default";
1510 pinctrl-0 = < 751 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 752 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 753 #address-cells = <1>;
1513 #size-cells = 754 #size-cells = <0>;
1514 power-domains <<
1515 operating-poi <<
1516 interconnects <<
1517 <<
1518 <<
1519 interconnect- <<
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 755 status = "disabled";
1524 }; 756 };
1525 757
1526 spi4: spi@890000 { 758 spi4: spi@890000 {
1527 compatible = 759 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 760 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 761 clock-names = "se";
1530 clocks = <&gc 762 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 763 pinctrl-names = "default";
1532 pinctrl-0 = < 764 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 765 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 766 #address-cells = <1>;
1535 #size-cells = 767 #size-cells = <0>;
1536 interconnects <<
1537 <<
1538 interconnect- <<
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 768 status = "disabled";
1543 }; 769 };
1544 770
1545 uart4: serial@890000 771 uart4: serial@890000 {
1546 compatible = 772 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 773 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 774 clock-names = "se";
1549 clocks = <&gc 775 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 776 pinctrl-names = "default";
1551 pinctrl-0 = < 777 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 778 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains <<
1554 operating-poi <<
1555 interconnects <<
1556 <<
1557 interconnect- <<
1558 status = "dis 779 status = "disabled";
1559 }; 780 };
1560 781
1561 i2c5: i2c@894000 { 782 i2c5: i2c@894000 {
1562 compatible = 783 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 784 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 785 clock-names = "se";
1565 clocks = <&gc 786 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 787 pinctrl-names = "default";
1567 pinctrl-0 = < 788 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 789 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 790 #address-cells = <1>;
1570 #size-cells = 791 #size-cells = <0>;
1571 power-domains <<
1572 operating-poi <<
1573 interconnects <<
1574 <<
1575 <<
1576 interconnect- <<
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 792 status = "disabled";
1581 }; 793 };
1582 794
1583 spi5: spi@894000 { 795 spi5: spi@894000 {
1584 compatible = 796 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 797 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 798 clock-names = "se";
1587 clocks = <&gc 799 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 800 pinctrl-names = "default";
1589 pinctrl-0 = < 801 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 802 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 803 #address-cells = <1>;
1592 #size-cells = 804 #size-cells = <0>;
1593 interconnects <<
1594 <<
1595 interconnect- <<
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 805 status = "disabled";
1600 }; 806 };
1601 807
1602 uart5: serial@894000 808 uart5: serial@894000 {
1603 compatible = 809 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 810 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 811 clock-names = "se";
1606 clocks = <&gc 812 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 813 pinctrl-names = "default";
1608 pinctrl-0 = < 814 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 815 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains <<
1611 operating-poi <<
1612 interconnects <<
1613 <<
1614 interconnect- <<
1615 status = "dis 816 status = "disabled";
1616 }; 817 };
1617 818
1618 i2c6: i2c@898000 { 819 i2c6: i2c@898000 {
1619 compatible = 820 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 821 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 822 clock-names = "se";
1622 clocks = <&gc 823 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 824 pinctrl-names = "default";
1624 pinctrl-0 = < 825 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 826 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 827 #address-cells = <1>;
1627 #size-cells = 828 #size-cells = <0>;
1628 power-domains <<
1629 operating-poi <<
1630 interconnects <<
1631 <<
1632 <<
1633 interconnect- <<
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 829 status = "disabled";
1638 }; 830 };
1639 831
1640 spi6: spi@898000 { 832 spi6: spi@898000 {
1641 compatible = 833 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 834 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 835 clock-names = "se";
1644 clocks = <&gc 836 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 837 pinctrl-names = "default";
1646 pinctrl-0 = < 838 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 839 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 840 #address-cells = <1>;
1649 #size-cells = 841 #size-cells = <0>;
1650 interconnects <<
1651 <<
1652 interconnect- <<
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 842 status = "disabled";
1657 }; 843 };
1658 844
1659 uart6: serial@898000 845 uart6: serial@898000 {
1660 compatible = 846 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 847 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 848 clock-names = "se";
1663 clocks = <&gc 849 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 850 pinctrl-names = "default";
1665 pinctrl-0 = < 851 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 852 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains <<
1668 operating-poi <<
1669 interconnects <<
1670 <<
1671 interconnect- <<
1672 status = "dis 853 status = "disabled";
1673 }; 854 };
1674 855
1675 i2c7: i2c@89c000 { 856 i2c7: i2c@89c000 {
1676 compatible = 857 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 858 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 859 clock-names = "se";
1679 clocks = <&gc 860 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 861 pinctrl-names = "default";
1681 pinctrl-0 = < 862 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 863 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 864 #address-cells = <1>;
1684 #size-cells = 865 #size-cells = <0>;
1685 power-domains <<
1686 operating-poi <<
1687 status = "dis 866 status = "disabled";
1688 }; 867 };
1689 868
1690 spi7: spi@89c000 { 869 spi7: spi@89c000 {
1691 compatible = 870 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 871 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 872 clock-names = "se";
1694 clocks = <&gc 873 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 874 pinctrl-names = "default";
1696 pinctrl-0 = < 875 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 876 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 877 #address-cells = <1>;
1699 #size-cells = 878 #size-cells = <0>;
1700 interconnects <<
1701 <<
1702 interconnect- <<
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 879 status = "disabled";
1707 }; 880 };
1708 881
1709 uart7: serial@89c000 882 uart7: serial@89c000 {
1710 compatible = 883 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 884 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 885 clock-names = "se";
1713 clocks = <&gc 886 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 887 pinctrl-names = "default";
1715 pinctrl-0 = < 888 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 889 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains <<
1718 operating-poi <<
1719 interconnects <<
1720 <<
1721 interconnect- <<
1722 status = "dis 890 status = "disabled";
1723 }; 891 };
1724 }; 892 };
1725 893
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 894 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 895 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 896 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 897 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 898 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 899 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu <<
1756 #address-cells = <2>; 900 #address-cells = <2>;
1757 #size-cells = <2>; 901 #size-cells = <2>;
1758 ranges; 902 ranges;
1759 interconnects = <&agg <<
1760 interconnect-names = <<
1761 status = "disabled"; 903 status = "disabled";
1762 904
1763 i2c8: i2c@a80000 { 905 i2c8: i2c@a80000 {
1764 compatible = 906 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 907 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 908 clock-names = "se";
1767 clocks = <&gc 909 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 910 pinctrl-names = "default";
1769 pinctrl-0 = < 911 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 912 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 913 #address-cells = <1>;
1772 #size-cells = 914 #size-cells = <0>;
1773 power-domains <<
1774 operating-poi <<
1775 interconnects <<
1776 <<
1777 <<
1778 interconnect- <<
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 915 status = "disabled";
1783 }; 916 };
1784 917
1785 spi8: spi@a80000 { 918 spi8: spi@a80000 {
1786 compatible = 919 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 920 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 921 clock-names = "se";
1789 clocks = <&gc 922 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 923 pinctrl-names = "default";
1791 pinctrl-0 = < 924 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 925 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 926 #address-cells = <1>;
1794 #size-cells = 927 #size-cells = <0>;
1795 interconnects <<
1796 <<
1797 interconnect- <<
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 928 status = "disabled";
1802 }; 929 };
1803 930
1804 uart8: serial@a80000 931 uart8: serial@a80000 {
1805 compatible = 932 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 933 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 934 clock-names = "se";
1808 clocks = <&gc 935 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 936 pinctrl-names = "default";
1810 pinctrl-0 = < 937 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 938 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains <<
1813 operating-poi <<
1814 interconnects <<
1815 <<
1816 interconnect- <<
1817 status = "dis 939 status = "disabled";
1818 }; 940 };
1819 941
1820 i2c9: i2c@a84000 { 942 i2c9: i2c@a84000 {
1821 compatible = 943 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 944 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 945 clock-names = "se";
1824 clocks = <&gc 946 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 947 pinctrl-names = "default";
1826 pinctrl-0 = < 948 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 949 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 950 #address-cells = <1>;
1829 #size-cells = 951 #size-cells = <0>;
1830 power-domains <<
1831 operating-poi <<
1832 interconnects <<
1833 <<
1834 <<
1835 interconnect- <<
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 952 status = "disabled";
1840 }; 953 };
1841 954
1842 spi9: spi@a84000 { 955 spi9: spi@a84000 {
1843 compatible = 956 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 957 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 958 clock-names = "se";
1846 clocks = <&gc 959 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 960 pinctrl-names = "default";
1848 pinctrl-0 = < 961 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 962 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 963 #address-cells = <1>;
1851 #size-cells = 964 #size-cells = <0>;
1852 interconnects <<
1853 <<
1854 interconnect- <<
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 965 status = "disabled";
1859 }; 966 };
1860 967
1861 uart9: serial@a84000 968 uart9: serial@a84000 {
1862 compatible = 969 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 970 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 971 clock-names = "se";
1865 clocks = <&gc 972 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 973 pinctrl-names = "default";
1867 pinctrl-0 = < 974 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 975 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains <<
1870 operating-poi <<
1871 interconnects <<
1872 <<
1873 interconnect- <<
1874 status = "dis 976 status = "disabled";
1875 }; 977 };
1876 978
1877 i2c10: i2c@a88000 { 979 i2c10: i2c@a88000 {
1878 compatible = 980 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 981 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 982 clock-names = "se";
1881 clocks = <&gc 983 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 984 pinctrl-names = "default";
1883 pinctrl-0 = < 985 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 986 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 987 #address-cells = <1>;
1886 #size-cells = 988 #size-cells = <0>;
1887 power-domains <<
1888 operating-poi <<
1889 interconnects <<
1890 <<
1891 <<
1892 interconnect- <<
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 989 status = "disabled";
1897 }; 990 };
1898 991
1899 spi10: spi@a88000 { 992 spi10: spi@a88000 {
1900 compatible = 993 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 994 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 995 clock-names = "se";
1903 clocks = <&gc 996 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 997 pinctrl-names = "default";
1905 pinctrl-0 = < 998 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 999 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1000 #address-cells = <1>;
1908 #size-cells = 1001 #size-cells = <0>;
1909 interconnects <<
1910 <<
1911 interconnect- <<
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1002 status = "disabled";
1916 }; 1003 };
1917 1004
1918 uart10: serial@a88000 1005 uart10: serial@a88000 {
1919 compatible = 1006 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1007 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1008 clock-names = "se";
1922 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1010 pinctrl-names = "default";
1924 pinctrl-0 = < 1011 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1012 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains <<
1927 operating-poi <<
1928 interconnects <<
1929 <<
1930 interconnect- <<
1931 status = "dis 1013 status = "disabled";
1932 }; 1014 };
1933 1015
1934 i2c11: i2c@a8c000 { 1016 i2c11: i2c@a8c000 {
1935 compatible = 1017 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1018 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1019 clock-names = "se";
1938 clocks = <&gc 1020 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1021 pinctrl-names = "default";
1940 pinctrl-0 = < 1022 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1023 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1024 #address-cells = <1>;
1943 #size-cells = 1025 #size-cells = <0>;
1944 power-domains <<
1945 operating-poi <<
1946 interconnects <<
1947 <<
1948 <<
1949 interconnect- <<
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1026 status = "disabled";
1954 }; 1027 };
1955 1028
1956 spi11: spi@a8c000 { 1029 spi11: spi@a8c000 {
1957 compatible = 1030 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1031 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1032 clock-names = "se";
1960 clocks = <&gc 1033 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1034 pinctrl-names = "default";
1962 pinctrl-0 = < 1035 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1036 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1037 #address-cells = <1>;
1965 #size-cells = 1038 #size-cells = <0>;
1966 interconnects <<
1967 <<
1968 interconnect- <<
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1039 status = "disabled";
1973 }; 1040 };
1974 1041
1975 uart11: serial@a8c000 1042 uart11: serial@a8c000 {
1976 compatible = 1043 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1044 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1045 clock-names = "se";
1979 clocks = <&gc 1046 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1047 pinctrl-names = "default";
1981 pinctrl-0 = < 1048 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1049 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains <<
1984 operating-poi <<
1985 interconnects <<
1986 <<
1987 interconnect- <<
1988 status = "dis 1050 status = "disabled";
1989 }; 1051 };
1990 1052
1991 i2c12: i2c@a90000 { 1053 i2c12: i2c@a90000 {
1992 compatible = 1054 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1055 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1056 clock-names = "se";
1995 clocks = <&gc 1057 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1058 pinctrl-names = "default";
1997 pinctrl-0 = < 1059 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1060 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1061 #address-cells = <1>;
2000 #size-cells = 1062 #size-cells = <0>;
2001 power-domains <<
2002 operating-poi <<
2003 interconnects <<
2004 <<
2005 <<
2006 interconnect- <<
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1063 status = "disabled";
2011 }; 1064 };
2012 1065
2013 spi12: spi@a90000 { 1066 spi12: spi@a90000 {
2014 compatible = 1067 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1068 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1069 clock-names = "se";
2017 clocks = <&gc 1070 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1071 pinctrl-names = "default";
2019 pinctrl-0 = < 1072 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1073 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1074 #address-cells = <1>;
2022 #size-cells = 1075 #size-cells = <0>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1076 status = "disabled";
2030 }; 1077 };
2031 1078
2032 uart12: serial@a90000 1079 uart12: serial@a90000 {
2033 compatible = 1080 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1081 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1082 clock-names = "se";
2036 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1084 pinctrl-names = "default";
2038 pinctrl-0 = < 1085 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1086 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains <<
2041 operating-poi <<
2042 interconnects <<
2043 <<
2044 interconnect- <<
2045 status = "dis 1087 status = "disabled";
2046 }; 1088 };
2047 1089
2048 i2c13: i2c@a94000 { 1090 i2c13: i2c@a94000 {
2049 compatible = 1091 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1092 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1093 clock-names = "se";
2052 clocks = <&gc 1094 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1095 pinctrl-names = "default";
2054 pinctrl-0 = < 1096 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1097 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1098 #address-cells = <1>;
2057 #size-cells = 1099 #size-cells = <0>;
2058 power-domains <<
2059 operating-poi <<
2060 interconnects <<
2061 <<
2062 <<
2063 interconnect- <<
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1100 status = "disabled";
2068 }; 1101 };
2069 1102
2070 spi13: spi@a94000 { 1103 spi13: spi@a94000 {
2071 compatible = 1104 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1105 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1106 clock-names = "se";
2074 clocks = <&gc 1107 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1108 pinctrl-names = "default";
2076 pinctrl-0 = < 1109 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1110 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1111 #address-cells = <1>;
2079 #size-cells = 1112 #size-cells = <0>;
2080 interconnects <<
2081 <<
2082 interconnect- <<
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1113 status = "disabled";
2087 }; 1114 };
2088 1115
2089 uart13: serial@a94000 1116 uart13: serial@a94000 {
2090 compatible = 1117 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1118 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1119 clock-names = "se";
2093 clocks = <&gc 1120 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1121 pinctrl-names = "default";
2095 pinctrl-0 = < 1122 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1123 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains <<
2098 operating-poi <<
2099 interconnects <<
2100 <<
2101 interconnect- <<
2102 status = "dis 1124 status = "disabled";
2103 }; 1125 };
2104 1126
2105 i2c14: i2c@a98000 { 1127 i2c14: i2c@a98000 {
2106 compatible = 1128 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1129 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1130 clock-names = "se";
2109 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1132 pinctrl-names = "default";
2111 pinctrl-0 = < 1133 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1134 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1135 #address-cells = <1>;
2114 #size-cells = 1136 #size-cells = <0>;
2115 power-domains <<
2116 operating-poi <<
2117 interconnects <<
2118 <<
2119 <<
2120 interconnect- <<
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1137 status = "disabled";
2125 }; 1138 };
2126 1139
2127 spi14: spi@a98000 { 1140 spi14: spi@a98000 {
2128 compatible = 1141 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1142 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1143 clock-names = "se";
2131 clocks = <&gc 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1145 pinctrl-names = "default";
2133 pinctrl-0 = < 1146 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1147 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1148 #address-cells = <1>;
2136 #size-cells = 1149 #size-cells = <0>;
2137 interconnects <<
2138 <<
2139 interconnect- <<
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1150 status = "disabled";
2144 }; 1151 };
2145 1152
2146 uart14: serial@a98000 1153 uart14: serial@a98000 {
2147 compatible = 1154 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1155 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1156 clock-names = "se";
2150 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1158 pinctrl-names = "default";
2152 pinctrl-0 = < 1159 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1160 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains <<
2155 operating-poi <<
2156 interconnects <<
2157 <<
2158 interconnect- <<
2159 status = "dis 1161 status = "disabled";
2160 }; 1162 };
2161 1163
2162 i2c15: i2c@a9c000 { 1164 i2c15: i2c@a9c000 {
2163 compatible = 1165 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1166 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1167 clock-names = "se";
2166 clocks = <&gc 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1169 pinctrl-names = "default";
2168 pinctrl-0 = < 1170 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1171 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1172 #address-cells = <1>;
2171 #size-cells = 1173 #size-cells = <0>;
2172 power-domains <<
2173 operating-poi <<
2174 status = "dis 1174 status = "disabled";
2175 interconnects <<
2176 <<
2177 <<
2178 interconnect- <<
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1175 };
2183 1176
2184 spi15: spi@a9c000 { 1177 spi15: spi@a9c000 {
2185 compatible = 1178 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1179 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1180 clock-names = "se";
2188 clocks = <&gc 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1182 pinctrl-names = "default";
2190 pinctrl-0 = < 1183 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1184 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1185 #address-cells = <1>;
2193 #size-cells = 1186 #size-cells = <0>;
2194 interconnects <<
2195 <<
2196 interconnect- <<
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1187 status = "disabled";
2201 }; 1188 };
2202 1189
2203 uart15: serial@a9c000 1190 uart15: serial@a9c000 {
2204 compatible = 1191 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1192 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1193 clock-names = "se";
2207 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1195 pinctrl-names = "default";
2209 pinctrl-0 = < 1196 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1197 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains <<
2212 operating-poi <<
2213 interconnects <<
2214 <<
2215 interconnect- <<
2216 status = "dis 1198 status = "disabled";
2217 }; 1199 };
2218 }; 1200 };
2219 1201
2220 llcc: system-cache-controller <<
2221 compatible = "qcom,sd <<
2222 reg = <0 0x01100000 0 <<
2223 <0 0x01200000 0 <<
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI <<
2228 }; <<
2229 <<
2230 dma@10a2000 { <<
2231 compatible = "qcom,sd <<
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 <<
2313 <0 0x60000000 0 <<
2314 <0 0x60000f20 0 <<
2315 <0 0x60100000 0 <<
2316 <0 0x01c07000 0 <<
2317 reg-names = "parf", " <<
2318 device_type = "pci"; <<
2319 linux,pci-domain = <0 <<
2320 bus-range = <0x00 0xf <<
2321 num-lanes = <1>; <<
2322 <<
2323 #address-cells = <3>; <<
2324 #size-cells = <2>; <<
2325 <<
2326 ranges = <0x01000000 <<
2327 <0x02000000 <<
2328 <<
2329 interrupts = <GIC_SPI <<
2330 interrupt-names = "ms <<
2331 #interrupt-cells = <1 <<
2332 interrupt-map-mask = <<
2333 interrupt-map = <0 0 <<
2334 <0 0 <<
2335 <0 0 <<
2336 <0 0 <<
2337 <<
2338 clocks = <&gcc GCC_PC <<
2339 <&gcc GCC_PC <<
2340 <&gcc GCC_PC <<
2341 <&gcc GCC_PC <<
2342 <&gcc GCC_PC <<
2343 <&gcc GCC_PC <<
2344 <&gcc GCC_AG <<
2345 clock-names = "pipe", <<
2346 "aux", <<
2347 "cfg", <<
2348 "bus_ma <<
2349 "bus_sl <<
2350 "slave_ <<
2351 "tbu"; <<
2352 <<
2353 iommu-map = <0x0 &a <<
2354 <0x100 &a <<
2355 <0x200 &a <<
2356 <0x300 &a <<
2357 <0x400 &a <<
2358 <0x500 &a <<
2359 <0x600 &a <<
2360 <0x700 &a <<
2361 <0x800 &a <<
2362 <0x900 &a <<
2363 <0xa00 &a <<
2364 <0xb00 &a <<
2365 <0xc00 &a <<
2366 <0xd00 &a <<
2367 <0xe00 &a <<
2368 <0xf00 &a <<
2369 <<
2370 resets = <&gcc GCC_PC <<
2371 reset-names = "pci"; <<
2372 <<
2373 power-domains = <&gcc <<
2374 <<
2375 phys = <&pcie0_phy>; <<
2376 phy-names = "pciephy" <<
2377 <<
2378 status = "disabled"; <<
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; <<
2390 <<
2391 pcie0_phy: phy@1c06000 { <<
2392 compatible = "qcom,sd <<
2393 reg = <0 0x01c06000 0 <<
2394 clocks = <&gcc GCC_PC <<
2395 <&gcc GCC_PC <<
2396 <&gcc GCC_PC <<
2397 <&gcc GCC_PC <<
2398 <&gcc GCC_PC <<
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 <<
2410 resets = <&gcc GCC_PC <<
2411 reset-names = "phy"; <<
2412 <<
2413 assigned-clocks = <&g <<
2414 assigned-clock-rates <<
2415 <<
2416 status = "disabled"; <<
2417 }; <<
2418 <<
2419 pcie1: pcie@1c08000 { <<
2420 compatible = "qcom,pc <<
2421 reg = <0 0x01c08000 0 <<
2422 <0 0x40000000 0 <<
2423 <0 0x40000f20 0 <<
2424 <0 0x40100000 0 <<
2425 <0 0x01c0c000 0 <<
2426 reg-names = "parf", " <<
2427 device_type = "pci"; <<
2428 linux,pci-domain = <1 <<
2429 bus-range = <0x00 0xf <<
2430 num-lanes = <1>; <<
2431 <<
2432 #address-cells = <3>; <<
2433 #size-cells = <2>; <<
2434 <<
2435 ranges = <0x01000000 <<
2436 <0x02000000 <<
2437 <<
2438 interrupts = <GIC_SPI <<
2439 interrupt-names = "ms <<
2440 #interrupt-cells = <1 <<
2441 interrupt-map-mask = <<
2442 interrupt-map = <0 0 <<
2443 <0 0 <<
2444 <0 0 <<
2445 <0 0 <<
2446 <<
2447 clocks = <&gcc GCC_PC <<
2448 <&gcc GCC_PC <<
2449 <&gcc GCC_PC <<
2450 <&gcc GCC_PC <<
2451 <&gcc GCC_PC <<
2452 <&gcc GCC_PC <<
2453 <&gcc GCC_PC <<
2454 <&gcc GCC_AG <<
2455 clock-names = "pipe", <<
2456 "aux", <<
2457 "cfg", <<
2458 "bus_ma <<
2459 "bus_sl <<
2460 "slave_ <<
2461 "ref", <<
2462 "tbu"; <<
2463 <<
2464 assigned-clocks = <&g <<
2465 assigned-clock-rates <<
2466 <<
2467 iommu-map = <0x0 &a <<
2468 <0x100 &a <<
2469 <0x200 &a <<
2470 <0x300 &a <<
2471 <0x400 &a <<
2472 <0x500 &a <<
2473 <0x600 &a <<
2474 <0x700 &a <<
2475 <0x800 &a <<
2476 <0x900 &a <<
2477 <0xa00 &a <<
2478 <0xb00 &a <<
2479 <0xc00 &a <<
2480 <0xd00 &a <<
2481 <0xe00 &a <<
2482 <0xf00 &a <<
2483 <<
2484 resets = <&gcc GCC_PC <<
2485 reset-names = "pci"; <<
2486 <<
2487 power-domains = <&gcc <<
2488 <<
2489 phys = <&pcie1_phy>; <<
2490 phy-names = "pciephy" <<
2491 <<
2492 status = "disabled"; <<
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; <<
2504 <<
2505 pcie1_phy: phy@1c0a000 { <<
2506 compatible = "qcom,sd <<
2507 reg = <0 0x01c0a000 0 <<
2508 clocks = <&gcc GCC_PC <<
2509 <&gcc GCC_PC <<
2510 <&gcc GCC_PC <<
2511 <&gcc GCC_PC <<
2512 <&gcc GCC_PC <<
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 <<
2524 resets = <&gcc GCC_PC <<
2525 reset-names = "phy"; <<
2526 <<
2527 assigned-clocks = <&g <<
2528 assigned-clock-rates <<
2529 <<
2530 status = "disabled"; <<
2531 }; <<
2532 <<
2533 mem_noc: interconnect@1380000 <<
2534 compatible = "qcom,sd <<
2535 reg = <0 0x01380000 0 <<
2536 #interconnect-cells = <<
2537 qcom,bcm-voters = <&a <<
2538 }; <<
2539 <<
2540 dc_noc: interconnect@14e0000 <<
2541 compatible = "qcom,sd <<
2542 reg = <0 0x014e0000 0 <<
2543 #interconnect-cells = <<
2544 qcom,bcm-voters = <&a <<
2545 }; <<
2546 <<
2547 config_noc: interconnect@1500 <<
2548 compatible = "qcom,sd <<
2549 reg = <0 0x01500000 0 <<
2550 #interconnect-cells = <<
2551 qcom,bcm-voters = <&a <<
2552 }; <<
2553 <<
2554 system_noc: interconnect@1620 <<
2555 compatible = "qcom,sd <<
2556 reg = <0 0x01620000 0 <<
2557 #interconnect-cells = <<
2558 qcom,bcm-voters = <&a <<
2559 }; <<
2560 <<
2561 aggre1_noc: interconnect@16e0 <<
2562 compatible = "qcom,sd <<
2563 reg = <0 0x016e0000 0 <<
2564 #interconnect-cells = <<
2565 qcom,bcm-voters = <&a <<
2566 }; <<
2567 <<
2568 aggre2_noc: interconnect@1700 <<
2569 compatible = "qcom,sd <<
2570 reg = <0 0x01700000 0 <<
2571 #interconnect-cells = <<
2572 qcom,bcm-voters = <&a <<
2573 }; <<
2574 <<
2575 mmss_noc: interconnect@174000 <<
2576 compatible = "qcom,sd <<
2577 reg = <0 0x01740000 0 <<
2578 #interconnect-cells = <<
2579 qcom,bcm-voters = <&a <<
2580 }; <<
2581 <<
2582 ufs_mem_hc: ufshc@1d84000 { 1202 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 1203 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 1204 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 !! 1205 reg = <0 0x01d84000 0 0x2500>;
2586 <0 0x01d90000 0 <<
2587 reg-names = "std", "i <<
2588 interrupts = <GIC_SPI 1206 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 1207 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 1208 phy-names = "ufsphy";
2591 lanes-per-direction = 1209 lanes-per-direction = <2>;
2592 power-domains = <&gcc 1210 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 1211 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF <<
2595 reset-names = "rst"; <<
2596 1212
2597 iommus = <&apps_smmu 1213 iommus = <&apps_smmu 0x100 0xf>;
2598 1214
2599 clock-names = 1215 clock-names =
2600 "core_clk", 1216 "core_clk",
2601 "bus_aggr_clk 1217 "bus_aggr_clk",
2602 "iface_clk", 1218 "iface_clk",
2603 "core_clk_uni 1219 "core_clk_unipro",
2604 "ref_clk", 1220 "ref_clk",
2605 "tx_lane0_syn 1221 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 1222 "rx_lane0_sync_clk",
2607 "rx_lane1_syn !! 1223 "rx_lane1_sync_clk";
2608 "ice_core_clk <<
2609 clocks = 1224 clocks =
2610 <&gcc GCC_UFS 1225 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 1226 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 1227 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 1228 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 1229 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 1230 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 1231 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS !! 1232 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2618 <&gcc GCC_UFS !! 1233 freq-table-hz =
2619 !! 1234 <50000000 200000000>,
2620 operating-points-v2 = !! 1235 <0 0>,
2621 !! 1236 <0 0>,
2622 interconnects = <&agg !! 1237 <37500000 150000000>,
2623 <&gla !! 1238 <0 0>,
2624 interconnect-names = !! 1239 <0 0>,
>> 1240 <0 0>,
>> 1241 <0 0>;
2625 1242
2626 status = "disabled"; 1243 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 1244 };
2658 1245
2659 ufs_mem_phy: phy@1d87000 { 1246 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 1247 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 1248 reg = <0 0x01d87000 0 0x18c>;
2662 !! 1249 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 1250 #size-cells = <2>;
2664 <&gcc GCC_UF !! 1251 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 1252 clock-names = "ref",
2667 "ref_au !! 1253 "ref_aux";
2668 "qref"; !! 1254 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 1255 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 1256
2672 resets = <&ufs_mem_hc 1257 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 1258 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; <<
2677 }; <<
2678 <<
2679 cryptobam: dma-controller@1dc <<
2680 compatible = "qcom,ba <<
2681 reg = <0 0x01dc4000 0 <<
2682 interrupts = <GIC_SPI <<
2683 clocks = <&rpmhcc RPM <<
2684 clock-names = "bam_cl <<
2685 #dma-cells = <1>; <<
2686 qcom,ee = <0>; <<
2687 qcom,controlled-remot <<
2688 iommus = <&apps_smmu <<
2689 <&apps_smmu <<
2690 <&apps_smmu <<
2691 <&apps_smmu <<
2692 }; <<
2693 <<
2694 crypto: crypto@1dfa000 { <<
2695 compatible = "qcom,cr <<
2696 reg = <0 0x01dfa000 0 <<
2697 clocks = <&gcc GCC_CE <<
2698 <&gcc GCC_CE <<
2699 <&rpmhcc RPM <<
2700 clock-names = "iface" <<
2701 dmas = <&cryptobam 6> <<
2702 dma-names = "rx", "tx <<
2703 iommus = <&apps_smmu <<
2704 <&apps_smmu <<
2705 <&apps_smmu <<
2706 <&apps_smmu <<
2707 }; <<
2708 <<
2709 ipa: ipa@1e40000 { <<
2710 compatible = "qcom,sd <<
2711 <<
2712 iommus = <&apps_smmu <<
2713 <&apps_smmu <<
2714 reg = <0 0x01e40000 0 <<
2715 <0 0x01e47000 0 <<
2716 <0 0x01e04000 0 <<
2717 reg-names = "ipa-reg" <<
2718 "ipa-shar <<
2719 "gsi"; <<
2720 <<
2721 interrupts-extended = <<
2722 <<
2723 <<
2724 <<
2725 interrupt-names = "ip <<
2726 "gs <<
2727 "ip <<
2728 "ip <<
2729 <<
2730 clocks = <&rpmhcc RPM <<
2731 clock-names = "core"; <<
2732 <<
2733 interconnects = <&agg <<
2734 <&agg <<
2735 <&gla <<
2736 interconnect-names = <<
2737 <<
2738 <<
2739 <<
2740 qcom,smem-states = <& <<
2741 <& <<
2742 qcom,smem-state-names <<
2743 <<
2744 <<
2745 status = "disabled"; 1259 status = "disabled";
2746 }; <<
2747 1260
2748 tcsr_mutex: hwlock@1f40000 { !! 1261 ufs_mem_phy_lanes: lanes@1d87400 {
2749 compatible = "qcom,tc !! 1262 reg = <0 0x01d87400 0 0x108>,
2750 reg = <0 0x01f40000 0 !! 1263 <0 0x01d87600 0 0x1e0>,
2751 #hwlock-cells = <1>; !! 1264 <0 0x01d87c00 0 0x1dc>,
>> 1265 <0 0x01d87800 0 0x108>,
>> 1266 <0 0x01d87a00 0 0x1e0>;
>> 1267 #phy-cells = <0>;
>> 1268 };
2752 }; 1269 };
2753 1270
2754 tcsr_regs_1: syscon@1f60000 { !! 1271 tcsr_mutex_regs: syscon@1f40000 {
2755 compatible = "qcom,sd !! 1272 compatible = "syscon";
2756 reg = <0 0x01f60000 0 !! 1273 reg = <0 0x01f40000 0 0x40000>;
2757 }; 1274 };
2758 1275
2759 tlmm: pinctrl@3400000 { 1276 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 1277 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 1278 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 1279 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 1280 gpio-controller;
2764 #gpio-cells = <2>; 1281 #gpio-cells = <2>;
2765 interrupt-controller; 1282 interrupt-controller;
2766 #interrupt-cells = <2 1283 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm !! 1284 gpio-ranges = <&tlmm 0 0 150>;
2768 wakeup-parent = <&pdc <<
2769 <<
2770 cci0_default: cci0-de <<
2771 /* SDA, SCL * <<
2772 pins = "gpio1 <<
2773 function = "c <<
2774 <<
2775 bias-pull-up; <<
2776 drive-strengt <<
2777 }; <<
2778 <<
2779 cci0_sleep: cci0-slee <<
2780 /* SDA, SCL * <<
2781 pins = "gpio1 <<
2782 function = "c <<
2783 <<
2784 drive-strengt <<
2785 bias-pull-dow <<
2786 }; <<
2787 <<
2788 cci1_default: cci1-de <<
2789 /* SDA, SCL * <<
2790 pins = "gpio1 <<
2791 function = "c <<
2792 <<
2793 bias-pull-up; <<
2794 drive-strengt <<
2795 }; <<
2796 <<
2797 cci1_sleep: cci1-slee <<
2798 /* SDA, SCL * <<
2799 pins = "gpio1 <<
2800 function = "c <<
2801 <<
2802 drive-strengt <<
2803 bias-pull-dow <<
2804 }; <<
2805 <<
2806 qspi_clk: qspi-clk-st <<
2807 pins = "gpio9 <<
2808 function = "q <<
2809 }; <<
2810 <<
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; <<
2820 <<
2821 qspi_data0: qspi-data <<
2822 pins = "gpio9 <<
2823 function = "q <<
2824 }; <<
2825 <<
2826 qspi_data1: qspi-data <<
2827 pins = "gpio9 <<
2828 function = "q <<
2829 }; <<
2830 <<
2831 qspi_data23: qspi-dat <<
2832 pins = "gpio9 <<
2833 function = "q <<
2834 }; <<
2835 <<
2836 qup_i2c0_default: qup <<
2837 pins = "gpio0 <<
2838 function = "q <<
2839 }; <<
2840 <<
2841 qup_i2c1_default: qup <<
2842 pins = "gpio1 <<
2843 function = "q <<
2844 }; <<
2845 <<
2846 qup_i2c2_default: qup <<
2847 pins = "gpio2 <<
2848 function = "q <<
2849 }; <<
2850 <<
2851 qup_i2c3_default: qup <<
2852 pins = "gpio4 <<
2853 function = "q <<
2854 }; <<
2855 <<
2856 qup_i2c4_default: qup <<
2857 pins = "gpio8 <<
2858 function = "q <<
2859 }; <<
2860 <<
2861 qup_i2c5_default: qup <<
2862 pins = "gpio8 <<
2863 function = "q <<
2864 }; <<
2865 <<
2866 qup_i2c6_default: qup <<
2867 pins = "gpio4 <<
2868 function = "q <<
2869 }; <<
2870 <<
2871 qup_i2c7_default: qup <<
2872 pins = "gpio9 <<
2873 function = "q <<
2874 }; <<
2875 <<
2876 qup_i2c8_default: qup <<
2877 pins = "gpio6 <<
2878 function = "q <<
2879 }; <<
2880 <<
2881 qup_i2c9_default: qup <<
2882 pins = "gpio6 <<
2883 function = "q <<
2884 }; <<
2885 <<
2886 qup_i2c10_default: qu <<
2887 pins = "gpio5 <<
2888 function = "q <<
2889 }; <<
2890 <<
2891 qup_i2c11_default: qu <<
2892 pins = "gpio3 <<
2893 function = "q <<
2894 }; <<
2895 <<
2896 qup_i2c12_default: qu <<
2897 pins = "gpio4 <<
2898 function = "q <<
2899 }; <<
2900 <<
2901 qup_i2c13_default: qu <<
2902 pins = "gpio1 <<
2903 function = "q <<
2904 }; <<
2905 <<
2906 qup_i2c14_default: qu <<
2907 pins = "gpio3 <<
2908 function = "q <<
2909 }; <<
2910 <<
2911 qup_i2c15_default: qu <<
2912 pins = "gpio8 <<
2913 function = "q <<
2914 }; <<
2915 <<
2916 qup_spi0_default: qup <<
2917 pins = "gpio0 <<
2918 function = "q <<
2919 }; <<
2920 <<
2921 qup_spi1_default: qup <<
2922 pins = "gpio1 <<
2923 function = "q <<
2924 }; <<
2925 <<
2926 qup_spi2_default: qup <<
2927 pins = "gpio2 <<
2928 function = "q <<
2929 }; <<
2930 <<
2931 qup_spi3_default: qup <<
2932 pins = "gpio4 <<
2933 function = "q <<
2934 }; <<
2935 <<
2936 qup_spi4_default: qup <<
2937 pins = "gpio8 <<
2938 function = "q <<
2939 }; <<
2940 <<
2941 qup_spi5_default: qup <<
2942 pins = "gpio8 <<
2943 function = "q <<
2944 }; <<
2945 <<
2946 qup_spi6_default: qup <<
2947 pins = "gpio4 <<
2948 function = "q <<
2949 }; <<
2950 <<
2951 qup_spi7_default: qup <<
2952 pins = "gpio9 <<
2953 function = "q <<
2954 }; <<
2955 1285
2956 qup_spi8_default: qup !! 1286 qspi_clk: qspi-clk {
2957 pins = "gpio6 !! 1287 pinmux {
2958 function = "q !! 1288 pins = "gpio95";
2959 }; !! 1289 function = "qspi_clk";
2960 !! 1290 };
2961 qup_spi9_default: qup <<
2962 pins = "gpio6 <<
2963 function = "q <<
2964 }; <<
2965 <<
2966 qup_spi10_default: qu <<
2967 pins = "gpio5 <<
2968 function = "q <<
2969 }; <<
2970 <<
2971 qup_spi11_default: qu <<
2972 pins = "gpio3 <<
2973 function = "q <<
2974 }; <<
2975 <<
2976 qup_spi12_default: qu <<
2977 pins = "gpio4 <<
2978 function = "q <<
2979 }; 1291 };
2980 1292
2981 qup_spi13_default: qu !! 1293 qspi_cs0: qspi-cs0 {
2982 pins = "gpio1 !! 1294 pinmux {
2983 function = "q !! 1295 pins = "gpio90";
>> 1296 function = "qspi_cs";
>> 1297 };
2984 }; 1298 };
2985 1299
2986 qup_spi14_default: qu !! 1300 qspi_cs1: qspi-cs1 {
2987 pins = "gpio3 !! 1301 pinmux {
2988 function = "q !! 1302 pins = "gpio89";
>> 1303 function = "qspi_cs";
>> 1304 };
2989 }; 1305 };
2990 1306
2991 qup_spi15_default: qu !! 1307 qspi_data01: qspi-data01 {
2992 pins = "gpio8 !! 1308 pinmux-data {
2993 function = "q !! 1309 pins = "gpio91", "gpio92";
>> 1310 function = "qspi_data";
>> 1311 };
2994 }; 1312 };
2995 1313
2996 qup_uart0_default: qu !! 1314 qspi_data12: qspi-data12 {
2997 qup_uart0_tx: !! 1315 pinmux-data {
2998 pins !! 1316 pins = "gpio93", "gpio94";
2999 funct !! 1317 function = "qspi_data";
3000 }; 1318 };
>> 1319 };
3001 1320
3002 qup_uart0_rx: !! 1321 qup_i2c0_default: qup-i2c0-default {
3003 pins !! 1322 pinmux {
>> 1323 pins = "gpio0", "gpio1";
3004 funct 1324 function = "qup0";
3005 }; 1325 };
3006 }; 1326 };
3007 1327
3008 qup_uart1_default: qu !! 1328 qup_i2c1_default: qup-i2c1-default {
3009 qup_uart1_tx: !! 1329 pinmux {
3010 pins !! 1330 pins = "gpio17", "gpio18";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 1331 function = "qup1";
3017 }; 1332 };
3018 }; 1333 };
3019 1334
3020 qup_uart2_default: qu !! 1335 qup_i2c2_default: qup-i2c2-default {
3021 qup_uart2_tx: !! 1336 pinmux {
3022 pins !! 1337 pins = "gpio27", "gpio28";
3023 funct 1338 function = "qup2";
3024 }; 1339 };
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct <<
3029 }; <<
3030 }; <<
3031 <<
3032 qup_uart3_default: qu <<
3033 qup_uart3_tx: <<
3034 pins <<
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct <<
3041 }; <<
3042 }; 1340 };
3043 1341
3044 qup_uart3_4pin: qup-u !! 1342 qup_i2c3_default: qup-i2c3-default {
3045 qup_uart3_4pi !! 1343 pinmux {
3046 pins !! 1344 pins = "gpio41", "gpio42";
3047 funct <<
3048 }; <<
3049 <<
3050 qup_uart3_4pi <<
3051 pins <<
3052 funct <<
3053 }; <<
3054 <<
3055 qup_uart3_4pi <<
3056 pins <<
3057 funct 1345 function = "qup3";
3058 }; 1346 };
3059 }; 1347 };
3060 1348
3061 qup_uart4_default: qu !! 1349 qup_i2c4_default: qup-i2c4-default {
3062 qup_uart4_tx: !! 1350 pinmux {
3063 pins !! 1351 pins = "gpio89", "gpio90";
3064 funct <<
3065 }; <<
3066 <<
3067 qup_uart4_rx: <<
3068 pins <<
3069 funct 1352 function = "qup4";
3070 }; 1353 };
3071 }; 1354 };
3072 1355
3073 qup_uart5_default: qu !! 1356 qup_i2c5_default: qup-i2c5-default {
3074 qup_uart5_tx: !! 1357 pinmux {
3075 pins !! 1358 pins = "gpio85", "gpio86";
3076 funct <<
3077 }; <<
3078 <<
3079 qup_uart5_rx: <<
3080 pins <<
3081 funct 1359 function = "qup5";
3082 }; 1360 };
3083 }; 1361 };
3084 1362
3085 qup_uart6_default: qu !! 1363 qup_i2c6_default: qup-i2c6-default {
3086 qup_uart6_tx: !! 1364 pinmux {
3087 pins !! 1365 pins = "gpio45", "gpio46";
3088 funct <<
3089 }; <<
3090 <<
3091 qup_uart6_rx: <<
3092 pins <<
3093 funct 1366 function = "qup6";
3094 }; 1367 };
3095 }; 1368 };
3096 1369
3097 qup_uart6_4pin: qup-u !! 1370 qup_i2c7_default: qup-i2c7-default {
3098 qup_uart6_4pi !! 1371 pinmux {
3099 pins !! 1372 pins = "gpio93", "gpio94";
3100 funct <<
3101 bias- <<
3102 }; <<
3103 <<
3104 qup_uart6_4pi <<
3105 pins <<
3106 funct <<
3107 drive <<
3108 bias- <<
3109 }; <<
3110 <<
3111 qup_uart6_4pi <<
3112 pins <<
3113 funct <<
3114 bias- <<
3115 }; <<
3116 }; <<
3117 <<
3118 qup_uart7_default: qu <<
3119 qup_uart7_tx: <<
3120 pins <<
3121 funct <<
3122 }; <<
3123 <<
3124 qup_uart7_rx: <<
3125 pins <<
3126 funct 1373 function = "qup7";
3127 }; 1374 };
3128 }; 1375 };
3129 1376
3130 qup_uart8_default: qu !! 1377 qup_i2c8_default: qup-i2c8-default {
3131 qup_uart8_tx: !! 1378 pinmux {
3132 pins !! 1379 pins = "gpio65", "gpio66";
3133 funct <<
3134 }; <<
3135 <<
3136 qup_uart8_rx: <<
3137 pins <<
3138 funct 1380 function = "qup8";
3139 }; 1381 };
3140 }; 1382 };
3141 1383
3142 qup_uart9_default: qu !! 1384 qup_i2c9_default: qup-i2c9-default {
3143 qup_uart9_tx: !! 1385 pinmux {
3144 pins !! 1386 pins = "gpio6", "gpio7";
3145 funct <<
3146 }; <<
3147 <<
3148 qup_uart9_rx: <<
3149 pins <<
3150 funct 1387 function = "qup9";
3151 }; 1388 };
3152 }; 1389 };
3153 1390
3154 qup_uart10_default: q !! 1391 qup_i2c10_default: qup-i2c10-default {
3155 qup_uart10_tx !! 1392 pinmux {
3156 pins !! 1393 pins = "gpio55", "gpio56";
3157 funct <<
3158 }; <<
3159 <<
3160 qup_uart10_rx <<
3161 pins <<
3162 funct 1394 function = "qup10";
3163 }; 1395 };
3164 }; 1396 };
3165 1397
3166 qup_uart11_default: q !! 1398 qup_i2c11_default: qup-i2c11-default {
3167 qup_uart11_tx !! 1399 pinmux {
3168 pins !! 1400 pins = "gpio31", "gpio32";
3169 funct <<
3170 }; <<
3171 <<
3172 qup_uart11_rx <<
3173 pins <<
3174 funct 1401 function = "qup11";
3175 }; 1402 };
3176 }; 1403 };
3177 1404
3178 qup_uart12_default: q !! 1405 qup_i2c12_default: qup-i2c12-default {
3179 qup_uart12_tx !! 1406 pinmux {
3180 pins !! 1407 pins = "gpio49", "gpio50";
3181 funct !! 1408 function = "qup12";
3182 }; <<
3183 <<
3184 qup_uart12_rx <<
3185 pins <<
3186 funct <<
3187 }; 1409 };
3188 }; 1410 };
3189 1411
3190 qup_uart13_default: q !! 1412 qup_i2c13_default: qup-i2c13-default {
3191 qup_uart13_tx !! 1413 pinmux {
3192 pins !! 1414 pins = "gpio105", "gpio106";
3193 funct <<
3194 }; <<
3195 <<
3196 qup_uart13_rx <<
3197 pins <<
3198 funct 1415 function = "qup13";
3199 }; 1416 };
3200 }; 1417 };
3201 1418
3202 qup_uart14_default: q !! 1419 qup_i2c14_default: qup-i2c14-default {
3203 qup_uart14_tx !! 1420 pinmux {
3204 pins !! 1421 pins = "gpio33", "gpio34";
3205 funct <<
3206 }; <<
3207 <<
3208 qup_uart14_rx <<
3209 pins <<
3210 funct 1422 function = "qup14";
3211 }; 1423 };
3212 }; 1424 };
3213 1425
3214 qup_uart15_default: q !! 1426 qup_i2c15_default: qup-i2c15-default {
3215 qup_uart15_tx !! 1427 pinmux {
3216 pins !! 1428 pins = "gpio81", "gpio82";
3217 funct <<
3218 }; <<
3219 <<
3220 qup_uart15_rx <<
3221 pins <<
3222 funct 1429 function = "qup15";
3223 }; 1430 };
3224 }; 1431 };
3225 1432
3226 quat_mi2s_sleep: quat !! 1433 qup_spi0_default: qup-spi0-default {
3227 pins = "gpio5 !! 1434 pinmux {
3228 function = "g !! 1435 pins = "gpio0", "gpio1",
3229 drive-strengt !! 1436 "gpio2", "gpio3";
3230 bias-pull-dow !! 1437 function = "qup0";
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 <<
3290 quat_mi2s_sd3_active: <<
3291 pins = "gpio6 <<
3292 function = "q <<
3293 drive-strengt <<
3294 bias-disable; <<
3295 }; <<
3296 }; <<
3297 <<
3298 mss_pil: remoteproc@4080000 { <<
3299 compatible = "qcom,sd <<
3300 reg = <0 0x04080000 0 <<
3301 reg-names = "qdsp6", <<
3302 <<
3303 interrupts-extended = <<
3304 <&intc GIC_SP <<
3305 <&modem_smp2p <<
3306 <&modem_smp2p <<
3307 <&modem_smp2p <<
3308 <&modem_smp2p <<
3309 <&modem_smp2p <<
3310 interrupt-names = "wd <<
3311 "ha <<
3312 "sh <<
3313 <<
3314 clocks = <&gcc GCC_MS <<
3315 <&gcc GCC_MS <<
3316 <&gcc GCC_BO <<
3317 <&gcc GCC_MS <<
3318 <&gcc GCC_MS <<
3319 <&gcc GCC_MS <<
3320 <&gcc GCC_PR <<
3321 <&rpmhcc RPM <<
3322 clock-names = "iface" <<
3323 "snoc_a <<
3324 <<
3325 qcom,qmp = <&aoss_qmp <<
3326 <<
3327 qcom,smem-states = <& <<
3328 qcom,smem-state-names <<
3329 <<
3330 resets = <&aoss_reset <<
3331 <&pdc_reset <<
3332 reset-names = "mss_re <<
3333 <<
3334 qcom,halt-regs = <&tc <<
3335 <<
3336 power-domains = <&rpm <<
3337 <&rpm <<
3338 <&rpm <<
3339 power-domain-names = <<
3340 <<
3341 status = "disabled"; <<
3342 <<
3343 mba { <<
3344 memory-region <<
3345 }; <<
3346 <<
3347 mpss { <<
3348 memory-region <<
3349 }; <<
3350 <<
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { <<
3356 interrupts = <<
3357 label = "mode <<
3358 qcom,remote-p <<
3359 mboxes = <&ap <<
3360 }; <<
3361 }; <<
3362 <<
3363 gpucc: clock-controller@50900 <<
3364 compatible = "qcom,sd <<
3365 reg = <0 0x05090000 0 <<
3366 #clock-cells = <1>; <<
3367 #reset-cells = <1>; <<
3368 #power-domain-cells = <<
3369 clocks = <&rpmhcc RPM <<
3370 <&gcc GCC_GP <<
3371 <&gcc GCC_GP <<
3372 clock-names = "bi_tcx <<
3373 "gcc_gp <<
3374 "gcc_gp <<
3375 }; <<
3376 <<
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; 1438 };
3427 }; 1439 };
3428 }; <<
3429 1440
3430 stm@6002000 { !! 1441 qup_spi1_default: qup-spi1-default {
3431 compatible = "arm,cor !! 1442 pinmux {
3432 reg = <0 0x06002000 0 !! 1443 pins = "gpio17", "gpio18",
3433 <0 0x16280000 0 !! 1444 "gpio19", "gpio20";
3434 reg-names = "stm-base !! 1445 function = "qup1";
3435 <<
3436 clocks = <&aoss_qmp>; <<
3437 clock-names = "apb_pc <<
3438 <<
3439 out-ports { <<
3440 port { <<
3441 stm_o <<
3442 <<
3443 <<
3444 }; <<
3445 }; 1446 };
3446 }; 1447 };
3447 }; <<
3448 1448
3449 funnel@6041000 { !! 1449 qup_spi2_default: qup-spi2-default {
3450 compatible = "arm,cor !! 1450 pinmux {
3451 reg = <0 0x06041000 0 !! 1451 pins = "gpio27", "gpio28",
3452 !! 1452 "gpio29", "gpio30";
3453 clocks = <&aoss_qmp>; !! 1453 function = "qup2";
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 funne <<
3459 <<
3460 <<
3461 }; <<
3462 }; 1454 };
3463 }; 1455 };
3464 1456
3465 in-ports { !! 1457 qup_spi3_default: qup-spi3-default {
3466 #address-cell !! 1458 pinmux {
3467 #size-cells = !! 1459 pins = "gpio41", "gpio42",
3468 !! 1460 "gpio43", "gpio44";
3469 port@7 { !! 1461 function = "qup3";
3470 reg = <<
3471 funne <<
3472 <<
3473 }; <<
3474 }; 1462 };
3475 }; 1463 };
3476 }; <<
3477 1464
3478 funnel@6043000 { !! 1465 qup_spi4_default: qup-spi4-default {
3479 compatible = "arm,cor !! 1466 pinmux {
3480 reg = <0 0x06043000 0 !! 1467 pins = "gpio89", "gpio90",
3481 !! 1468 "gpio91", "gpio92";
3482 clocks = <&aoss_qmp>; !! 1469 function = "qup4";
3483 clock-names = "apb_pc <<
3484 <<
3485 out-ports { <<
3486 port { <<
3487 funne <<
3488 <<
3489 <<
3490 }; <<
3491 }; 1470 };
3492 }; 1471 };
3493 1472
3494 in-ports { !! 1473 qup_spi5_default: qup-spi5-default {
3495 #address-cell !! 1474 pinmux {
3496 #size-cells = !! 1475 pins = "gpio85", "gpio86",
3497 !! 1476 "gpio87", "gpio88";
3498 port@5 { !! 1477 function = "qup5";
3499 reg = <<
3500 funne <<
3501 <<
3502 <<
3503 }; <<
3504 }; 1478 };
3505 }; 1479 };
3506 }; <<
3507 1480
3508 funnel@6045000 { !! 1481 qup_spi6_default: qup-spi6-default {
3509 compatible = "arm,cor !! 1482 pinmux {
3510 reg = <0 0x06045000 0 !! 1483 pins = "gpio45", "gpio46",
3511 !! 1484 "gpio47", "gpio48";
3512 clocks = <&aoss_qmp>; !! 1485 function = "qup6";
3513 clock-names = "apb_pc <<
3514 <<
3515 out-ports { <<
3516 port { <<
3517 merge <<
3518 <<
3519 }; <<
3520 }; 1486 };
3521 }; 1487 };
3522 1488
3523 in-ports { !! 1489 qup_spi7_default: qup-spi7-default {
3524 #address-cell !! 1490 pinmux {
3525 #size-cells = !! 1491 pins = "gpio93", "gpio94",
3526 !! 1492 "gpio95", "gpio96";
3527 port@0 { !! 1493 function = "qup7";
3528 reg = <<
3529 merge <<
3530 <<
3531 <<
3532 }; <<
3533 }; <<
3534 <<
3535 port@2 { <<
3536 reg = <<
3537 merge <<
3538 <<
3539 <<
3540 }; <<
3541 }; 1494 };
3542 }; 1495 };
3543 }; <<
3544 1496
3545 replicator@6046000 { !! 1497 qup_spi8_default: qup-spi8-default {
3546 compatible = "arm,cor !! 1498 pinmux {
3547 reg = <0 0x06046000 0 !! 1499 pins = "gpio65", "gpio66",
3548 !! 1500 "gpio67", "gpio68";
3549 clocks = <&aoss_qmp>; !! 1501 function = "qup8";
3550 clock-names = "apb_pc <<
3551 <<
3552 out-ports { <<
3553 port { <<
3554 repli <<
3555 <<
3556 }; <<
3557 }; 1502 };
3558 }; 1503 };
3559 1504
3560 in-ports { !! 1505 qup_spi9_default: qup-spi9-default {
3561 port { !! 1506 pinmux {
3562 repli !! 1507 pins = "gpio6", "gpio7",
3563 !! 1508 "gpio4", "gpio5";
3564 }; !! 1509 function = "qup9";
3565 }; 1510 };
3566 }; 1511 };
3567 }; <<
3568 1512
3569 etf@6047000 { !! 1513 qup_spi10_default: qup-spi10-default {
3570 compatible = "arm,cor !! 1514 pinmux {
3571 reg = <0 0x06047000 0 !! 1515 pins = "gpio55", "gpio56",
3572 !! 1516 "gpio53", "gpio54";
3573 clocks = <&aoss_qmp>; !! 1517 function = "qup10";
3574 clock-names = "apb_pc <<
3575 <<
3576 out-ports { <<
3577 port { <<
3578 etf_o <<
3579 <<
3580 <<
3581 }; <<
3582 }; 1518 };
3583 }; 1519 };
3584 1520
3585 in-ports { !! 1521 qup_spi11_default: qup-spi11-default {
3586 !! 1522 pinmux {
3587 port { !! 1523 pins = "gpio31", "gpio32",
3588 etf_i !! 1524 "gpio33", "gpio34";
3589 !! 1525 function = "qup11";
3590 <<
3591 }; <<
3592 }; 1526 };
3593 }; 1527 };
3594 }; <<
3595 1528
3596 etr@6048000 { !! 1529 qup_spi12_default: qup-spi12-default {
3597 compatible = "arm,cor !! 1530 pinmux {
3598 reg = <0 0x06048000 0 !! 1531 pins = "gpio49", "gpio50",
3599 !! 1532 "gpio51", "gpio52";
3600 clocks = <&aoss_qmp>; !! 1533 function = "qup12";
3601 clock-names = "apb_pc <<
3602 arm,scatter-gather; <<
3603 <<
3604 in-ports { <<
3605 port { <<
3606 etr_i <<
3607 <<
3608 <<
3609 }; <<
3610 }; 1534 };
3611 }; 1535 };
3612 }; <<
3613 1536
3614 etm@7040000 { !! 1537 qup_spi13_default: qup-spi13-default {
3615 compatible = "arm,cor !! 1538 pinmux {
3616 reg = <0 0x07040000 0 !! 1539 pins = "gpio105", "gpio106",
3617 !! 1540 "gpio107", "gpio108";
3618 cpu = <&CPU0>; !! 1541 function = "qup13";
3619 <<
3620 clocks = <&aoss_qmp>; <<
3621 clock-names = "apb_pc <<
3622 arm,coresight-loses-c <<
3623 <<
3624 out-ports { <<
3625 port { <<
3626 etm0_ <<
3627 <<
3628 <<
3629 }; <<
3630 }; 1542 };
3631 }; 1543 };
3632 }; <<
3633 1544
3634 etm@7140000 { !! 1545 qup_spi14_default: qup-spi14-default {
3635 compatible = "arm,cor !! 1546 pinmux {
3636 reg = <0 0x07140000 0 !! 1547 pins = "gpio33", "gpio34",
3637 !! 1548 "gpio31", "gpio32";
3638 cpu = <&CPU1>; !! 1549 function = "qup14";
3639 <<
3640 clocks = <&aoss_qmp>; <<
3641 clock-names = "apb_pc <<
3642 arm,coresight-loses-c <<
3643 <<
3644 out-ports { <<
3645 port { <<
3646 etm1_ <<
3647 <<
3648 <<
3649 }; <<
3650 }; 1550 };
3651 }; 1551 };
3652 }; <<
3653 1552
3654 etm@7240000 { !! 1553 qup_spi15_default: qup-spi15-default {
3655 compatible = "arm,cor !! 1554 pinmux {
3656 reg = <0 0x07240000 0 !! 1555 pins = "gpio81", "gpio82",
3657 !! 1556 "gpio83", "gpio84";
3658 cpu = <&CPU2>; !! 1557 function = "qup15";
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm2_ <<
3667 <<
3668 <<
3669 }; <<
3670 }; 1558 };
3671 }; 1559 };
3672 }; <<
3673 1560
3674 etm@7340000 { !! 1561 qup_uart0_default: qup-uart0-default {
3675 compatible = "arm,cor !! 1562 pinmux {
3676 reg = <0 0x07340000 0 !! 1563 pins = "gpio2", "gpio3";
3677 !! 1564 function = "qup0";
3678 cpu = <&CPU3>; <<
3679 <<
3680 clocks = <&aoss_qmp>; <<
3681 clock-names = "apb_pc <<
3682 arm,coresight-loses-c <<
3683 <<
3684 out-ports { <<
3685 port { <<
3686 etm3_ <<
3687 <<
3688 <<
3689 }; <<
3690 }; 1565 };
3691 }; 1566 };
3692 }; <<
3693 1567
3694 etm@7440000 { !! 1568 qup_uart1_default: qup-uart1-default {
3695 compatible = "arm,cor !! 1569 pinmux {
3696 reg = <0 0x07440000 0 !! 1570 pins = "gpio19", "gpio20";
3697 !! 1571 function = "qup1";
3698 cpu = <&CPU4>; <<
3699 <<
3700 clocks = <&aoss_qmp>; <<
3701 clock-names = "apb_pc <<
3702 arm,coresight-loses-c <<
3703 <<
3704 out-ports { <<
3705 port { <<
3706 etm4_ <<
3707 <<
3708 <<
3709 }; <<
3710 }; 1572 };
3711 }; 1573 };
3712 }; <<
3713 1574
3714 etm@7540000 { !! 1575 qup_uart2_default: qup-uart2-default {
3715 compatible = "arm,cor !! 1576 pinmux {
3716 reg = <0 0x07540000 0 !! 1577 pins = "gpio29", "gpio30";
3717 !! 1578 function = "qup2";
3718 cpu = <&CPU5>; <<
3719 <<
3720 clocks = <&aoss_qmp>; <<
3721 clock-names = "apb_pc <<
3722 arm,coresight-loses-c <<
3723 <<
3724 out-ports { <<
3725 port { <<
3726 etm5_ <<
3727 <<
3728 <<
3729 }; <<
3730 }; 1579 };
3731 }; 1580 };
3732 }; <<
3733 1581
3734 etm@7640000 { !! 1582 qup_uart3_default: qup-uart3-default {
3735 compatible = "arm,cor !! 1583 pinmux {
3736 reg = <0 0x07640000 0 !! 1584 pins = "gpio43", "gpio44";
3737 !! 1585 function = "qup3";
3738 cpu = <&CPU6>; <<
3739 <<
3740 clocks = <&aoss_qmp>; <<
3741 clock-names = "apb_pc <<
3742 arm,coresight-loses-c <<
3743 <<
3744 out-ports { <<
3745 port { <<
3746 etm6_ <<
3747 <<
3748 <<
3749 }; <<
3750 }; 1586 };
3751 }; 1587 };
3752 }; <<
3753 1588
3754 etm@7740000 { !! 1589 qup_uart4_default: qup-uart4-default {
3755 compatible = "arm,cor !! 1590 pinmux {
3756 reg = <0 0x07740000 0 !! 1591 pins = "gpio91", "gpio92";
3757 !! 1592 function = "qup4";
3758 cpu = <&CPU7>; <<
3759 <<
3760 clocks = <&aoss_qmp>; <<
3761 clock-names = "apb_pc <<
3762 arm,coresight-loses-c <<
3763 <<
3764 out-ports { <<
3765 port { <<
3766 etm7_ <<
3767 <<
3768 <<
3769 }; <<
3770 }; 1593 };
3771 }; 1594 };
3772 }; <<
3773 1595
3774 funnel@7800000 { /* APSS Funn !! 1596 qup_uart5_default: qup-uart5-default {
3775 compatible = "arm,cor !! 1597 pinmux {
3776 reg = <0 0x07800000 0 !! 1598 pins = "gpio87", "gpio88";
3777 !! 1599 function = "qup5";
3778 clocks = <&aoss_qmp>; <<
3779 clock-names = "apb_pc <<
3780 <<
3781 out-ports { <<
3782 port { <<
3783 apss_ <<
3784 <<
3785 <<
3786 }; <<
3787 }; 1600 };
3788 }; 1601 };
3789 1602
3790 in-ports { !! 1603 qup_uart6_default: qup-uart6-default {
3791 #address-cell !! 1604 pinmux {
3792 #size-cells = !! 1605 pins = "gpio47", "gpio48";
3793 !! 1606 function = "qup6";
3794 port@0 { <<
3795 reg = <<
3796 apss_ <<
3797 <<
3798 <<
3799 }; <<
3800 }; 1607 };
>> 1608 };
3801 1609
3802 port@1 { !! 1610 qup_uart7_default: qup-uart7-default {
3803 reg = !! 1611 pinmux {
3804 apss_ !! 1612 pins = "gpio95", "gpio96";
3805 !! 1613 function = "qup7";
3806 <<
3807 }; <<
3808 }; 1614 };
>> 1615 };
3809 1616
3810 port@2 { !! 1617 qup_uart8_default: qup-uart8-default {
3811 reg = !! 1618 pinmux {
3812 apss_ !! 1619 pins = "gpio67", "gpio68";
3813 !! 1620 function = "qup8";
3814 <<
3815 }; <<
3816 }; 1621 };
>> 1622 };
3817 1623
3818 port@3 { !! 1624 qup_uart9_default: qup-uart9-default {
3819 reg = !! 1625 pinmux {
3820 apss_ !! 1626 pins = "gpio4", "gpio5";
3821 !! 1627 function = "qup9";
3822 <<
3823 }; <<
3824 }; 1628 };
>> 1629 };
3825 1630
3826 port@4 { !! 1631 qup_uart10_default: qup-uart10-default {
3827 reg = !! 1632 pinmux {
3828 apss_ !! 1633 pins = "gpio53", "gpio54";
3829 !! 1634 function = "qup10";
3830 <<
3831 }; <<
3832 }; 1635 };
>> 1636 };
3833 1637
3834 port@5 { !! 1638 qup_uart11_default: qup-uart11-default {
3835 reg = !! 1639 pinmux {
3836 apss_ !! 1640 pins = "gpio33", "gpio34";
3837 !! 1641 function = "qup11";
3838 <<
3839 }; <<
3840 }; 1642 };
>> 1643 };
3841 1644
3842 port@6 { !! 1645 qup_uart12_default: qup-uart12-default {
3843 reg = !! 1646 pinmux {
3844 apss_ !! 1647 pins = "gpio51", "gpio52";
3845 !! 1648 function = "qup12";
3846 <<
3847 }; <<
3848 }; 1649 };
>> 1650 };
3849 1651
3850 port@7 { !! 1652 qup_uart13_default: qup-uart13-default {
3851 reg = !! 1653 pinmux {
3852 apss_ !! 1654 pins = "gpio107", "gpio108";
3853 !! 1655 function = "qup13";
3854 <<
3855 }; <<
3856 }; 1656 };
3857 }; 1657 };
3858 }; <<
3859 1658
3860 funnel@7810000 { !! 1659 qup_uart14_default: qup-uart14-default {
3861 compatible = "arm,cor !! 1660 pinmux {
3862 reg = <0 0x07810000 0 !! 1661 pins = "gpio31", "gpio32";
3863 !! 1662 function = "qup14";
3864 clocks = <&aoss_qmp>; <<
3865 clock-names = "apb_pc <<
3866 <<
3867 out-ports { <<
3868 port { <<
3869 apss_ <<
3870 <<
3871 <<
3872 }; <<
3873 }; 1663 };
3874 }; 1664 };
3875 1665
3876 in-ports { !! 1666 qup_uart15_default: qup-uart15-default {
3877 port { !! 1667 pinmux {
3878 apss_ !! 1668 pins = "gpio83", "gpio84";
3879 !! 1669 function = "qup15";
3880 <<
3881 }; <<
3882 }; 1670 };
3883 }; 1671 };
3884 }; 1672 };
3885 1673
3886 sdhc_2: mmc@8804000 { !! 1674 gpucc: clock-controller@5090000 {
>> 1675 compatible = "qcom,sdm845-gpucc";
>> 1676 reg = <0 0x05090000 0 0x9000>;
>> 1677 #clock-cells = <1>;
>> 1678 #reset-cells = <1>;
>> 1679 #power-domain-cells = <1>;
>> 1680 clocks = <&rpmhcc RPMH_CXO_CLK>;
>> 1681 clock-names = "xo";
>> 1682 };
>> 1683
>> 1684 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 1685 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 1686 reg = <0 0x08804000 0 0x1000>;
3889 1687
3890 interrupts = <GIC_SPI 1688 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 1689 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 1690 interrupt-names = "hc_irq", "pwr_irq";
3893 1691
3894 clocks = <&gcc GCC_SD 1692 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD !! 1693 <&gcc GCC_SDCC2_APPS_CLK>;
3896 <&rpmhcc RPM !! 1694 clock-names = "iface", "core";
3897 clock-names = "iface" <<
3898 iommus = <&apps_smmu 1695 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm <<
3900 operating-points-v2 = <<
3901 1696
3902 status = "disabled"; 1697 status = "disabled";
3903 <<
3904 sdhc2_opp_table: opp- <<
3905 compatible = <<
3906 <<
3907 opp-9600000 { <<
3908 opp-h <<
3909 requi <<
3910 }; <<
3911 <<
3912 opp-19200000 <<
3913 opp-h <<
3914 requi <<
3915 }; <<
3916 <<
3917 opp-100000000 <<
3918 opp-h <<
3919 requi <<
3920 }; <<
3921 <<
3922 opp-201500000 <<
3923 opp-h <<
3924 requi <<
3925 }; <<
3926 }; <<
3927 }; 1698 };
3928 1699
3929 qspi: spi@88df000 { 1700 qspi: spi@88df000 {
3930 compatible = "qcom,sd 1701 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 1702 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 1703 #address-cells = <1>;
3934 #size-cells = <0>; 1704 #size-cells = <0>;
3935 interrupts = <GIC_SPI 1705 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 1706 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 1707 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 1708 clock-names = "iface", "core";
3939 power-domains = <&rpm <<
3940 operating-points-v2 = <<
3941 status = "disabled"; 1709 status = "disabled";
3942 }; 1710 };
3943 1711
3944 slim: slim-ngd@171c0000 { <<
3945 compatible = "qcom,sl <<
3946 reg = <0 0x171c0000 0 <<
3947 interrupts = <GIC_SPI <<
3948 <<
3949 dmas = <&slimbam 3>, <<
3950 dma-names = "rx", "tx <<
3951 <<
3952 iommus = <&apps_smmu <<
3953 #address-cells = <1>; <<
3954 #size-cells = <0>; <<
3955 status = "disabled"; <<
3956 }; <<
3957 <<
3958 lmh_cluster1: lmh@17d70800 { <<
3959 compatible = "qcom,sd <<
3960 reg = <0 0x17d70800 0 <<
3961 interrupts = <GIC_SPI <<
3962 cpus = <&CPU4>; <<
3963 qcom,lmh-temp-arm-mil <<
3964 qcom,lmh-temp-low-mil <<
3965 qcom,lmh-temp-high-mi <<
3966 interrupt-controller; <<
3967 #interrupt-cells = <1 <<
3968 }; <<
3969 <<
3970 lmh_cluster0: lmh@17d78800 { <<
3971 compatible = "qcom,sd <<
3972 reg = <0 0x17d78800 0 <<
3973 interrupts = <GIC_SPI <<
3974 cpus = <&CPU0>; <<
3975 qcom,lmh-temp-arm-mil <<
3976 qcom,lmh-temp-low-mil <<
3977 qcom,lmh-temp-high-mi <<
3978 interrupt-controller; <<
3979 #interrupt-cells = <1 <<
3980 }; <<
3981 <<
3982 usb_1_hsphy: phy@88e2000 { 1712 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd !! 1713 compatible = "qcom,sdm845-qusb2-phy";
3984 reg = <0 0x088e2000 0 1714 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 1715 status = "disabled";
3986 #phy-cells = <0>; 1716 #phy-cells = <0>;
3987 1717
3988 clocks = <&gcc GCC_US 1718 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 1719 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 1720 clock-names = "cfg_ahb", "ref";
3991 1721
3992 resets = <&gcc GCC_QU 1722 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 1723
3994 nvmem-cells = <&qusb2 1724 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 1725 };
3996 1726
3997 usb_2_hsphy: phy@88e3000 { 1727 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd !! 1728 compatible = "qcom,sdm845-qusb2-phy";
3999 reg = <0 0x088e3000 0 1729 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 1730 status = "disabled";
4001 #phy-cells = <0>; 1731 #phy-cells = <0>;
4002 1732
4003 clocks = <&gcc GCC_US 1733 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 1734 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 1735 clock-names = "cfg_ahb", "ref";
4006 1736
4007 resets = <&gcc GCC_QU 1737 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 1738
4009 nvmem-cells = <&qusb2 1739 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 1740 };
4011 1741
4012 usb_1_qmpphy: phy@88e8000 { !! 1742 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 1743 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 1744 reg = <0 0x088e9000 0 0x18c>,
>> 1745 <0 0x088e8000 0 0x10>;
>> 1746 reg-names = "reg-base", "dp_com";
4015 status = "disabled"; 1747 status = "disabled";
>> 1748 #clock-cells = <1>;
>> 1749 #address-cells = <2>;
>> 1750 #size-cells = <2>;
>> 1751 ranges;
4016 1752
4017 clocks = <&gcc GCC_US 1753 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 1754 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 1755 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 1756 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 1757 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 1758
4028 resets = <&gcc GCC_US !! 1759 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 1760 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 1761 reset-names = "phy", "common";
4031 1762
4032 #clock-cells = <1>; !! 1763 usb_1_ssphy: lanes@88e9200 {
4033 #phy-cells = <1>; !! 1764 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 1765 <0 0x088e9400 0 0x200>,
4035 !! 1766 <0 0x088e9c00 0 0x218>,
4036 ports { !! 1767 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 1768 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 1769 <0 0x088e9a00 0 0x100>;
4039 !! 1770 #phy-cells = <0>;
4040 port@0 { !! 1771 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4041 reg = !! 1772 clock-names = "pipe0";
4042 !! 1773 clock-output-names = "usb3_phy_pipe_clk_src";
4043 usb_1 <<
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 1774 };
4063 }; 1775 };
4064 1776
4065 usb_2_qmpphy: phy@88eb000 { 1777 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 1778 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 1779 reg = <0 0x088eb000 0 0x18c>;
>> 1780 status = "disabled";
>> 1781 #clock-cells = <1>;
>> 1782 #address-cells = <2>;
>> 1783 #size-cells = <2>;
>> 1784 ranges;
4068 1785
4069 clocks = <&gcc GCC_US 1786 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 1787 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 1788 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 1789 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 1790 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 1791
4083 resets = <&gcc GCC_US !! 1792 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 1793 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 1794 reset-names = "phy", "common";
4086 "phy_ph <<
4087 1795
4088 status = "disabled"; !! 1796 usb_2_ssphy: lane@88eb200 {
>> 1797 reg = <0 0x088eb200 0 0x128>,
>> 1798 <0 0x088eb400 0 0x1fc>,
>> 1799 <0 0x088eb800 0 0x218>,
>> 1800 <0 0x088eb600 0 0x70>;
>> 1801 #phy-cells = <0>;
>> 1802 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 1803 clock-names = "pipe0";
>> 1804 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 1805 };
4089 }; 1806 };
4090 1807
4091 usb_1: usb@a6f8800 { 1808 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 1809 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 1810 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 1811 status = "disabled";
4095 #address-cells = <2>; 1812 #address-cells = <2>;
4096 #size-cells = <2>; 1813 #size-cells = <2>;
4097 ranges; 1814 ranges;
4098 dma-ranges; 1815 dma-ranges;
4099 1816
4100 clocks = <&gcc GCC_CF 1817 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 1818 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 1819 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 1820 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 1821 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 1822 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 1823 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 1824
4111 assigned-clocks = <&g 1825 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 1826 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 1827 assigned-clock-rates = <19200000>, <150000000>;
4114 1828
4115 interrupts-extended = !! 1829 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 1830 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 1831 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 1832 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 1833 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 1834 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 1835
4126 power-domains = <&gcc 1836 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 1837
4128 resets = <&gcc GCC_US 1838 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 1839
4130 interconnects = <&agg !! 1840 usb_1_dwc3: dwc3@a600000 {
4131 <&gla <<
4132 interconnect-names = <<
4133 <<
4134 usb_1_dwc3: usb@a6000 <<
4135 compatible = 1841 compatible = "snps,dwc3";
4136 reg = <0 0x0a 1842 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 1843 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 1844 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 1845 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 1846 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 1847 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 1848 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 1849 };
4165 }; 1850 };
4166 1851
4167 usb_2: usb@a8f8800 { 1852 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 1853 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 1854 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 1855 status = "disabled";
4171 #address-cells = <2>; 1856 #address-cells = <2>;
4172 #size-cells = <2>; 1857 #size-cells = <2>;
4173 ranges; 1858 ranges;
4174 dma-ranges; 1859 dma-ranges;
4175 1860
4176 clocks = <&gcc GCC_CF 1861 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 1862 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 1863 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 1864 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 1865 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 1866 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 1867 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 1868
4187 assigned-clocks = <&g 1869 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 1870 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 1871 assigned-clock-rates = <19200000>, <150000000>;
4190 1872
4191 interrupts-extended = !! 1873 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 1874 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 1875 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 1876 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 1877 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 1878 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 1879
4202 power-domains = <&gcc 1880 power-domains = <&gcc USB30_SEC_GDSC>;
4203 1881
4204 resets = <&gcc GCC_US 1882 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 1883
4206 interconnects = <&agg !! 1884 usb_2_dwc3: dwc3@a800000 {
4207 <&gla <<
4208 interconnect-names = <<
4209 <<
4210 usb_2_dwc3: usb@a8000 <<
4211 compatible = 1885 compatible = "snps,dwc3";
4212 reg = <0 0x0a 1886 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 1887 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 1888 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 1889 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 1890 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 1891 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 1892 phy-names = "usb2-phy", "usb3-phy";
4220 }; 1893 };
4221 }; 1894 };
4222 1895
4223 venus: video-codec@aa00000 { <<
4224 compatible = "qcom,sd <<
4225 reg = <0 0x0aa00000 0 <<
4226 interrupts = <GIC_SPI <<
4227 power-domains = <&vid <<
4228 <&vid <<
4229 <&vid <<
4230 <&rpm <<
4231 power-domain-names = <<
4232 operating-points-v2 = <<
4233 clocks = <&videocc VI <<
4234 <&videocc VI <<
4235 <&videocc VI <<
4236 <&videocc VI <<
4237 <&videocc VI <<
4238 <&videocc VI <<
4239 <&videocc VI <<
4240 clock-names = "core", <<
4241 "vcodec <<
4242 "vcodec <<
4243 iommus = <&apps_smmu <<
4244 <&apps_smmu <<
4245 memory-region = <&ven <<
4246 interconnects = <&mms <<
4247 <&gla <<
4248 interconnect-names = <<
4249 <<
4250 status = "disabled"; <<
4251 <<
4252 video-core0 { <<
4253 compatible = <<
4254 }; <<
4255 <<
4256 video-core1 { <<
4257 compatible = <<
4258 }; <<
4259 <<
4260 venus_opp_table: opp- <<
4261 compatible = <<
4262 <<
4263 opp-100000000 <<
4264 opp-h <<
4265 requi <<
4266 }; <<
4267 <<
4268 opp-200000000 <<
4269 opp-h <<
4270 requi <<
4271 }; <<
4272 <<
4273 opp-320000000 <<
4274 opp-h <<
4275 requi <<
4276 }; <<
4277 <<
4278 opp-380000000 <<
4279 opp-h <<
4280 requi <<
4281 }; <<
4282 <<
4283 opp-444000000 <<
4284 opp-h <<
4285 requi <<
4286 }; <<
4287 <<
4288 opp-533000097 <<
4289 opp-h <<
4290 requi <<
4291 }; <<
4292 }; <<
4293 }; <<
4294 <<
4295 videocc: clock-controller@ab0 1896 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 1897 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 1898 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM <<
4299 clock-names = "bi_tcx <<
4300 #clock-cells = <1>; 1899 #clock-cells = <1>;
4301 #power-domain-cells = 1900 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 1901 #reset-cells = <1>;
4303 }; 1902 };
4304 1903
4305 camss: camss@acb3000 { !! 1904 mdss: mdss@ae00000 {
4306 compatible = "qcom,sd <<
4307 <<
4308 reg = <0 0x0acb3000 0 <<
4309 <0 0x0acba000 <<
4310 <0 0x0acc8000 <<
4311 <0 0x0ac65000 <<
4312 <0 0x0ac66000 <<
4313 <0 0x0ac67000 <<
4314 <0 0x0ac68000 <<
4315 <0 0x0acaf000 <<
4316 <0 0x0acb6000 <<
4317 <0 0x0acc4000 <<
4318 reg-names = "csid0", <<
4319 "csid1", <<
4320 "csid2", <<
4321 "csiphy0", <<
4322 "csiphy1", <<
4323 "csiphy2", <<
4324 "csiphy3", <<
4325 "vfe0", <<
4326 "vfe1", <<
4327 "vfe_lite"; <<
4328 <<
4329 interrupts = <GIC_SPI <<
4330 <GIC_SPI 466 <<
4331 <GIC_SPI 468 <<
4332 <GIC_SPI 477 <<
4333 <GIC_SPI 478 <<
4334 <GIC_SPI 479 <<
4335 <GIC_SPI 448 <<
4336 <GIC_SPI 465 <<
4337 <GIC_SPI 467 <<
4338 <GIC_SPI 469 <<
4339 interrupt-names = "cs <<
4340 "csid1", <<
4341 "csid2", <<
4342 "csiphy0", <<
4343 "csiphy1", <<
4344 "csiphy2", <<
4345 "csiphy3", <<
4346 "vfe0", <<
4347 "vfe1", <<
4348 "vfe_lite"; <<
4349 <<
4350 power-domains = <&clo <<
4351 <&clock_camcc <<
4352 <&clock_camcc <<
4353 <<
4354 clocks = <&clock_camc <<
4355 <&clock_camcc <<
4356 <&clock_camcc <<
4357 <&clock_camcc <<
4358 <&clock_camcc <<
4359 <&clock_camcc <<
4360 <&clock_camcc <<
4361 <&clock_camcc <<
4362 <&clock_camcc <<
4363 <&clock_camcc <<
4364 <&clock_camcc <<
4365 <&clock_camcc <<
4366 <&clock_camcc <<
4367 <&clock_camcc <<
4368 <&clock_camcc <<
4369 <&clock_camcc <<
4370 <&clock_camcc <<
4371 <&clock_camcc <<
4372 <&clock_camcc <<
4373 <&clock_camcc <<
4374 <&clock_camcc <<
4375 <&gcc GCC_CAM <<
4376 <&gcc GCC_CAM <<
4377 <&clock_camcc <<
4378 <&clock_camcc <<
4379 <&clock_camcc <<
4380 <&clock_camcc <<
4381 <&clock_camcc <<
4382 <&clock_camcc <<
4383 <&clock_camcc <<
4384 <&clock_camcc <<
4385 <&clock_camcc <<
4386 <&clock_camcc <<
4387 <&clock_camcc <<
4388 <&clock_camcc <<
4389 <&clock_camcc <<
4390 clock-names = "camnoc <<
4391 "cpas_ahb", <<
4392 "cphy_rx_src" <<
4393 "csi0", <<
4394 "csi0_src", <<
4395 "csi1", <<
4396 "csi1_src", <<
4397 "csi2", <<
4398 "csi2_src", <<
4399 "csiphy0", <<
4400 "csiphy0_time <<
4401 "csiphy0_time <<
4402 "csiphy1", <<
4403 "csiphy1_time <<
4404 "csiphy1_time <<
4405 "csiphy2", <<
4406 "csiphy2_time <<
4407 "csiphy2_time <<
4408 "csiphy3", <<
4409 "csiphy3_time <<
4410 "csiphy3_time <<
4411 "gcc_camera_a <<
4412 "gcc_camera_a <<
4413 "slow_ahb_src <<
4414 "soc_ahb", <<
4415 "vfe0_axi", <<
4416 "vfe0", <<
4417 "vfe0_cphy_rx <<
4418 "vfe0_src", <<
4419 "vfe1_axi", <<
4420 "vfe1", <<
4421 "vfe1_cphy_rx <<
4422 "vfe1_src", <<
4423 "vfe_lite", <<
4424 "vfe_lite_cph <<
4425 "vfe_lite_src <<
4426 <<
4427 iommus = <&apps_smmu <<
4428 <&apps_smmu <<
4429 <&apps_smmu <<
4430 <&apps_smmu <<
4431 <<
4432 status = "disabled"; <<
4433 <<
4434 ports { <<
4435 #address-cell <<
4436 #size-cells = <<
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; <<
4454 }; <<
4455 <<
4456 cci: cci@ac4a000 { <<
4457 compatible = "qcom,sd <<
4458 #address-cells = <1>; <<
4459 #size-cells = <0>; <<
4460 <<
4461 reg = <0 0x0ac4a000 0 <<
4462 interrupts = <GIC_SPI <<
4463 power-domains = <&clo <<
4464 <<
4465 clocks = <&clock_camc <<
4466 <&clock_camcc <<
4467 <&clock_camcc <<
4468 <&clock_camcc <<
4469 <&clock_camcc <<
4470 <&clock_camcc <<
4471 clock-names = "camnoc <<
4472 "soc_ahb", <<
4473 "slow_ahb_src <<
4474 "cpas_ahb", <<
4475 "cci", <<
4476 "cci_src"; <<
4477 <<
4478 assigned-clocks = <&c <<
4479 <&clock_camcc <<
4480 assigned-clock-rates <<
4481 <<
4482 pinctrl-names = "defa <<
4483 pinctrl-0 = <&cci0_de <<
4484 pinctrl-1 = <&cci0_sl <<
4485 <<
4486 status = "disabled"; <<
4487 <<
4488 cci_i2c0: i2c-bus@0 { <<
4489 reg = <0>; <<
4490 clock-frequen <<
4491 #address-cell <<
4492 #size-cells = <<
4493 }; <<
4494 <<
4495 cci_i2c1: i2c-bus@1 { <<
4496 reg = <1>; <<
4497 clock-frequen <<
4498 #address-cell <<
4499 #size-cells = <<
4500 }; <<
4501 }; <<
4502 <<
4503 clock_camcc: clock-controller <<
4504 compatible = "qcom,sd <<
4505 reg = <0 0x0ad00000 0 <<
4506 #clock-cells = <1>; <<
4507 #reset-cells = <1>; <<
4508 #power-domain-cells = <<
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; <<
4512 <<
4513 mdss: display-subsystem@ae000 <<
4514 compatible = "qcom,sd 1905 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 1906 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 1907 reg-names = "mdss";
4517 1908
4518 power-domains = <&dis 1909 power-domains = <&dispcc MDSS_GDSC>;
4519 1910
4520 clocks = <&dispcc DIS !! 1911 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 1912 <&gcc GCC_DISP_AXI_CLK>,
4521 <&dispcc DIS 1913 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" !! 1914 clock-names = "iface", "bus", "core";
>> 1915
>> 1916 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 1917 assigned-clock-rates = <300000000>;
4523 1918
4524 interrupts = <GIC_SPI 1919 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 1920 interrupt-controller;
4526 #interrupt-cells = <1 1921 #interrupt-cells = <1>;
4527 1922
4528 interconnects = <&mms <<
4529 <&mms <<
4530 interconnect-names = <<
4531 <<
4532 iommus = <&apps_smmu 1923 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 1924 <&apps_smmu 0xc80 0x8>;
4534 1925
4535 status = "disabled"; 1926 status = "disabled";
4536 1927
4537 #address-cells = <2>; 1928 #address-cells = <2>;
4538 #size-cells = <2>; 1929 #size-cells = <2>;
4539 ranges; 1930 ranges;
4540 1931
4541 mdss_mdp: display-con !! 1932 mdss_mdp: mdp@ae01000 {
4542 compatible = 1933 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 1934 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 1935 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 1936 reg-names = "mdp", "vbif";
4546 1937
4547 clocks = <&gc !! 1938 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4548 <&di <<
4549 <&di 1939 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 1940 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 1941 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = !! 1942 clock-names = "iface", "bus", "core", "vsync";
4553 1943
4554 assigned-cloc !! 1944 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 1945 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4556 operating-poi !! 1946 assigned-clock-rates = <300000000>,
4557 power-domains !! 1947 <19200000>;
4558 1948
4559 interrupt-par 1949 interrupt-parent = <&mdss>;
4560 interrupts = !! 1950 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4561 <<
4562 ports { <<
4563 #addr <<
4564 #size <<
4565 <<
4566 port@ <<
4567 <<
4568 <<
4569 <<
4570 <<
4571 }; <<
4572 <<
4573 port@ <<
4574 <<
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 1951
4580 port@ <<
4581 <<
4582 <<
4583 <<
4584 <<
4585 }; <<
4586 }; <<
4587 <<
4588 mdp_opp_table <<
4589 compa <<
4590 <<
4591 opp-1 <<
4592 <<
4593 <<
4594 }; <<
4595 <<
4596 opp-1 <<
4597 <<
4598 <<
4599 }; <<
4600 <<
4601 opp-3 <<
4602 <<
4603 <<
4604 }; <<
4605 <<
4606 opp-4 <<
4607 <<
4608 <<
4609 }; <<
4610 }; <<
4611 }; <<
4612 <<
4613 mdss_dp: displayport- <<
4614 status = "dis 1952 status = "disabled";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 1953
4643 ports { 1954 ports {
4644 #addr 1955 #address-cells = <1>;
4645 #size 1956 #size-cells = <0>;
>> 1957
4646 port@ 1958 port@0 {
4647 1959 reg = <0>;
4648 !! 1960 dpu_intf1_out: endpoint {
4649 !! 1961 remote-endpoint = <&dsi0_in>;
4650 1962 };
4651 }; 1963 };
4652 1964
4653 port@ 1965 port@1 {
4654 1966 reg = <1>;
4655 !! 1967 dpu_intf2_out: endpoint {
4656 !! 1968 remote-endpoint = <&dsi1_in>;
4657 1969 };
4658 }; 1970 };
4659 }; 1971 };
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; 1972 };
4685 1973
4686 mdss_dsi0: dsi@ae9400 !! 1974 dsi0: dsi@ae94000 {
4687 compatible = !! 1975 compatible = "qcom,mdss-dsi-ctrl";
4688 <<
4689 reg = <0 0x0a 1976 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 1977 reg-names = "dsi_ctrl";
4691 1978
4692 interrupt-par 1979 interrupt-parent = <&mdss>;
4693 interrupts = !! 1980 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 1981
4695 clocks = <&di 1982 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 1983 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 1984 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 1985 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 1986 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 1987 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 1988 clock-names = "byte",
4702 1989 "byte_intf",
4703 1990 "pixel",
4704 1991 "core",
4705 1992 "iface",
4706 1993 "bus";
4707 assigned-cloc <<
4708 assigned-cloc <<
4709 <<
4710 operating-poi <<
4711 power-domains <<
4712 1994
4713 phys = <&mdss !! 1995 phys = <&dsi0_phy>;
>> 1996 phy-names = "dsi";
4714 1997
4715 status = "dis 1998 status = "disabled";
4716 1999
4717 #address-cell 2000 #address-cells = <1>;
4718 #size-cells = 2001 #size-cells = <0>;
4719 2002
4720 ports { 2003 ports {
4721 #addr 2004 #address-cells = <1>;
4722 #size 2005 #size-cells = <0>;
4723 2006
4724 port@ 2007 port@0 {
4725 2008 reg = <0>;
4726 !! 2009 dsi0_in: endpoint {
4727 2010 remote-endpoint = <&dpu_intf1_out>;
4728 2011 };
4729 }; 2012 };
4730 2013
4731 port@ 2014 port@1 {
4732 2015 reg = <1>;
4733 !! 2016 dsi0_out: endpoint {
4734 2017 };
4735 }; 2018 };
4736 }; 2019 };
4737 }; 2020 };
4738 2021
4739 mdss_dsi0_phy: phy@ae !! 2022 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 2023 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 2024 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 2025 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 2026 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 2027 reg-names = "dsi_phy",
4745 " 2028 "dsi_phy_lane",
4746 " 2029 "dsi_pll";
4747 2030
4748 #clock-cells 2031 #clock-cells = <1>;
4749 #phy-cells = 2032 #phy-cells = <0>;
4750 2033
4751 clocks = <&di 2034 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 2035 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 2036 clock-names = "iface", "ref";
4754 2037
4755 status = "dis 2038 status = "disabled";
4756 }; 2039 };
4757 2040
4758 mdss_dsi1: dsi@ae9600 !! 2041 dsi1: dsi@ae96000 {
4759 compatible = !! 2042 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 2043 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 2044 reg-names = "dsi_ctrl";
4763 2045
4764 interrupt-par 2046 interrupt-parent = <&mdss>;
4765 interrupts = !! 2047 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 2048
4767 clocks = <&di 2049 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 2050 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 2051 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 2052 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 2053 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 2054 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 2055 clock-names = "byte",
4774 2056 "byte_intf",
4775 2057 "pixel",
4776 2058 "core",
4777 2059 "iface",
4778 2060 "bus";
4779 assigned-cloc <<
4780 assigned-cloc <<
4781 <<
4782 operating-poi <<
4783 power-domains <<
4784 2061
4785 phys = <&mdss !! 2062 phys = <&dsi1_phy>;
>> 2063 phy-names = "dsi";
4786 2064
4787 status = "dis 2065 status = "disabled";
4788 2066
4789 #address-cell 2067 #address-cells = <1>;
4790 #size-cells = 2068 #size-cells = <0>;
4791 2069
4792 ports { 2070 ports {
4793 #addr 2071 #address-cells = <1>;
4794 #size 2072 #size-cells = <0>;
4795 2073
4796 port@ 2074 port@0 {
4797 2075 reg = <0>;
4798 !! 2076 dsi1_in: endpoint {
4799 2077 remote-endpoint = <&dpu_intf2_out>;
4800 2078 };
4801 }; 2079 };
4802 2080
4803 port@ 2081 port@1 {
4804 2082 reg = <1>;
4805 !! 2083 dsi1_out: endpoint {
4806 2084 };
4807 }; 2085 };
4808 }; 2086 };
4809 }; 2087 };
4810 2088
4811 mdss_dsi1_phy: phy@ae !! 2089 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 2090 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 2091 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 2092 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 2093 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 2094 reg-names = "dsi_phy",
4817 " 2095 "dsi_phy_lane",
4818 " 2096 "dsi_pll";
4819 2097
4820 #clock-cells 2098 #clock-cells = <1>;
4821 #phy-cells = 2099 #phy-cells = <0>;
4822 2100
4823 clocks = <&di 2101 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 2102 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 2103 clock-names = "iface", "ref";
4826 2104
4827 status = "dis 2105 status = "disabled";
4828 }; 2106 };
4829 }; 2107 };
4830 2108
4831 gpu: gpu@5000000 { <<
4832 compatible = "qcom,ad <<
4833 <<
4834 reg = <0 0x05000000 0 <<
4835 reg-names = "kgsl_3d0 <<
4836 <<
4837 /* <<
4838 * Look ma, no clocks <<
4839 * controlled entirel <<
4840 */ <<
4841 <<
4842 interrupts = <GIC_SPI <<
4843 <<
4844 iommus = <&adreno_smm <<
4845 <<
4846 operating-points-v2 = <<
4847 <<
4848 qcom,gmu = <&gmu>; <<
4849 #cooling-cells = <2>; <<
4850 <<
4851 interconnects = <&mem <<
4852 interconnect-names = <<
4853 <<
4854 status = "disabled"; <<
4855 <<
4856 gpu_opp_table: opp-ta <<
4857 compatible = <<
4858 <<
4859 opp-710000000 <<
4860 opp-h <<
4861 opp-l <<
4862 opp-p <<
4863 }; <<
4864 <<
4865 opp-675000000 <<
4866 opp-h <<
4867 opp-l <<
4868 opp-p <<
4869 }; <<
4870 <<
4871 opp-596000000 <<
4872 opp-h <<
4873 opp-l <<
4874 opp-p <<
4875 }; <<
4876 <<
4877 opp-520000000 <<
4878 opp-h <<
4879 opp-l <<
4880 opp-p <<
4881 }; <<
4882 <<
4883 opp-414000000 <<
4884 opp-h <<
4885 opp-l <<
4886 opp-p <<
4887 }; <<
4888 <<
4889 opp-342000000 <<
4890 opp-h <<
4891 opp-l <<
4892 opp-p <<
4893 }; <<
4894 <<
4895 opp-257000000 <<
4896 opp-h <<
4897 opp-l <<
4898 opp-p <<
4899 }; <<
4900 }; <<
4901 }; <<
4902 <<
4903 adreno_smmu: iommu@5040000 { <<
4904 compatible = "qcom,sd <<
4905 reg = <0 0x05040000 0 <<
4906 #iommu-cells = <1>; <<
4907 #global-interrupts = <<
4908 interrupts = <GIC_SPI <<
4909 <GIC_SPI <<
4910 <GIC_SPI <<
4911 <GIC_SPI <<
4912 <GIC_SPI <<
4913 <GIC_SPI <<
4914 <GIC_SPI <<
4915 <GIC_SPI <<
4916 <GIC_SPI <<
4917 <GIC_SPI <<
4918 clocks = <&gcc GCC_GP <<
4919 <&gcc GCC_GP <<
4920 clock-names = "bus", <<
4921 <<
4922 power-domains = <&gpu <<
4923 }; <<
4924 <<
4925 gmu: gmu@506a000 { <<
4926 compatible = "qcom,ad <<
4927 <<
4928 reg = <0 0x0506a000 0 <<
4929 <0 0x0b280000 0 <<
4930 <0 0x0b480000 0 <<
4931 reg-names = "gmu", "g <<
4932 <<
4933 interrupts = <GIC_SPI <<
4934 <GIC_SPI <<
4935 interrupt-names = "hf <<
4936 <<
4937 clocks = <&gpucc GPU_ <<
4938 <&gpucc GPU_ <<
4939 <&gcc GCC_DD <<
4940 <&gcc GCC_GP <<
4941 clock-names = "gmu", <<
4942 <<
4943 power-domains = <&gpu <<
4944 <&gpu <<
4945 power-domain-names = <<
4946 <<
4947 iommus = <&adreno_smm <<
4948 <<
4949 operating-points-v2 = <<
4950 <<
4951 status = "disabled"; <<
4952 <<
4953 gmu_opp_table: opp-ta <<
4954 compatible = <<
4955 <<
4956 opp-400000000 <<
4957 opp-h <<
4958 opp-l <<
4959 }; <<
4960 <<
4961 opp-200000000 <<
4962 opp-h <<
4963 opp-l <<
4964 }; <<
4965 }; <<
4966 }; <<
4967 <<
4968 dispcc: clock-controller@af00 2109 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 2110 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 2111 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM <<
4972 <&gcc GCC_DI <<
4973 <&gcc GCC_DI <<
4974 <&mdss_dsi0_ <<
4975 <&mdss_dsi0_ <<
4976 <&mdss_dsi1_ <<
4977 <&mdss_dsi1_ <<
4978 <&usb_1_qmpp <<
4979 <&usb_1_qmpp <<
4980 clock-names = "bi_tcx <<
4981 "gcc_di <<
4982 "gcc_di <<
4983 "dsi0_p <<
4984 "dsi0_p <<
4985 "dsi1_p <<
4986 "dsi1_p <<
4987 "dp_lin <<
4988 "dp_vco <<
4989 #clock-cells = <1>; 2112 #clock-cells = <1>;
4990 #reset-cells = <1>; 2113 #reset-cells = <1>;
4991 #power-domain-cells = 2114 #power-domain-cells = <1>;
4992 }; 2115 };
4993 2116
4994 pdc_intc: interrupt-controlle <<
4995 compatible = "qcom,sd <<
4996 reg = <0 0x0b220000 0 <<
4997 qcom,pdc-ranges = <0 <<
4998 #interrupt-cells = <2 <<
4999 interrupt-parent = <& <<
5000 interrupt-controller; <<
5001 }; <<
5002 <<
5003 pdc_reset: reset-controller@b 2117 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 2118 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 2119 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 2120 #reset-cells = <1>;
5007 }; 2121 };
5008 2122
5009 tsens0: thermal-sensor@c26300 2123 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 2124 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 2125 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 2126 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 2127 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI <<
5015 <GIC_SPI <<
5016 interrupt-names = "up <<
5017 #thermal-sensor-cells 2128 #thermal-sensor-cells = <1>;
5018 }; 2129 };
5019 2130
5020 tsens1: thermal-sensor@c26500 2131 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 2132 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 2133 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 2134 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 2135 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI <<
5026 <GIC_SPI <<
5027 interrupt-names = "up <<
5028 #thermal-sensor-cells 2136 #thermal-sensor-cells = <1>;
5029 }; 2137 };
5030 2138
5031 aoss_reset: reset-controller@ 2139 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 2140 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 2141 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 2142 #reset-cells = <1>;
5035 }; 2143 };
5036 2144
5037 aoss_qmp: power-management@c3 <<
5038 compatible = "qcom,sd <<
5039 reg = <0 0x0c300000 0 <<
5040 interrupts = <GIC_SPI <<
5041 mboxes = <&apss_share <<
5042 <<
5043 #clock-cells = <0>; <<
5044 <<
5045 cx_cdev: cx { <<
5046 #cooling-cell <<
5047 }; <<
5048 <<
5049 ebi_cdev: ebi { <<
5050 #cooling-cell <<
5051 }; <<
5052 }; <<
5053 <<
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 2145 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 2146 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 2147 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 2148 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 2149 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 2150 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 2151 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 2152 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 2153 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 2154 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 2155 qcom,ee = <0>;
5070 qcom,channel = <0>; 2156 qcom,channel = <0>;
5071 #address-cells = <2>; 2157 #address-cells = <2>;
5072 #size-cells = <0>; 2158 #size-cells = <0>;
5073 interrupt-controller; 2159 interrupt-controller;
5074 #interrupt-cells = <4 2160 #interrupt-cells = <4>;
5075 }; !! 2161 cell-index = <0>;
5076 <<
5077 sram@146bf000 { <<
5078 compatible = "qcom,sd <<
5079 reg = <0 0x146bf000 0 <<
5080 <<
5081 #address-cells = <1>; <<
5082 #size-cells = <1>; <<
5083 <<
5084 ranges = <0 0 0x146bf <<
5085 <<
5086 pil-reloc@94c { <<
5087 compatible = <<
5088 reg = <0x94c <<
5089 }; <<
5090 }; 2162 };
5091 2163
5092 apps_smmu: iommu@15000000 { 2164 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 2165 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 2166 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 2167 #iommu-cells = <2>;
5096 #global-interrupts = 2168 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 2169 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 2170 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 2171 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 2172 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 2173 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 2174 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 2175 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 2176 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 2177 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 2178 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 2179 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 2180 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 2181 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 2182 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 2183 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 2184 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 2185 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 2186 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 2187 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 2188 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 2189 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 2190 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 2191 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 2192 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 2193 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 2194 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 2195 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 2196 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 2197 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 2198 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 2199 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 2200 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 2201 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 2202 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 2203 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 2204 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 2205 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 2206 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 2207 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 2208 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 2209 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 2210 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 2211 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 2212 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 2213 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 2214 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 2215 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 2216 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 2217 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 2218 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 2219 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 2220 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 2221 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 2222 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 2223 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 2224 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 2225 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 2226 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 2227 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 2228 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 2229 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 2230 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 2231 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 2232 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 2233 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 2234 };
5163 2235
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 2236 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 2237 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 2238 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 2239 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 2240 #clock-cells = <1>;
5241 status = "disabled"; 2241 status = "disabled";
5242 }; 2242 };
5243 2243
5244 gladiator_noc: interconnect@1 <<
5245 compatible = "qcom,sd <<
5246 reg = <0 0x17900000 0 <<
5247 #interconnect-cells = <<
5248 qcom,bcm-voters = <&a <<
5249 }; <<
5250 <<
5251 watchdog@17980000 { <<
5252 compatible = "qcom,ap <<
5253 reg = <0 0x17980000 0 <<
5254 clocks = <&sleep_clk> <<
5255 interrupts = <GIC_SPI <<
5256 }; <<
5257 <<
5258 apss_shared: mailbox@17990000 2244 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 2245 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 2246 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 2247 #mbox-cells = <1>;
5262 }; 2248 };
5263 2249
5264 apps_rsc: rsc@179c0000 { 2250 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 2251 label = "apps_rsc";
5266 compatible = "qcom,rp 2252 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 2253 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 2254 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 2255 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 2256 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 2257 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 2258 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 2259 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 2260 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 2261 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 2262 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 2263 <SLEEP_TCS 3>,
5278 <WA 2264 <WAKE_TCS 3>,
5279 <CO 2265 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 <<
5282 apps_bcm_voter: bcm-v <<
5283 compatible = <<
5284 }; <<
5285 2266
5286 rpmhcc: clock-control 2267 rpmhcc: clock-controller {
5287 compatible = 2268 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 2269 #clock-cells = <1>;
5289 clock-names = <<
5290 clocks = <&xo <<
5291 }; 2270 };
5292 2271
5293 rpmhpd: power-control 2272 rpmhpd: power-controller {
5294 compatible = 2273 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 2274 #power-domain-cells = <1>;
5296 operating-poi 2275 operating-points-v2 = <&rpmhpd_opp_table>;
5297 2276
5298 rpmhpd_opp_ta 2277 rpmhpd_opp_table: opp-table {
5299 compa 2278 compatible = "operating-points-v2";
5300 2279
5301 rpmhp 2280 rpmhpd_opp_ret: opp1 {
5302 2281 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 2282 };
5304 2283
5305 rpmhp 2284 rpmhpd_opp_min_svs: opp2 {
5306 2285 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 2286 };
5308 2287
5309 rpmhp 2288 rpmhpd_opp_low_svs: opp3 {
5310 2289 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 2290 };
5312 2291
5313 rpmhp 2292 rpmhpd_opp_svs: opp4 {
5314 2293 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 2294 };
5316 2295
5317 rpmhp 2296 rpmhpd_opp_svs_l1: opp5 {
5318 2297 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 2298 };
5320 2299
5321 rpmhp 2300 rpmhpd_opp_nom: opp6 {
5322 2301 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 2302 };
5324 2303
5325 rpmhp 2304 rpmhpd_opp_nom_l1: opp7 {
5326 2305 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 2306 };
5328 2307
5329 rpmhp 2308 rpmhpd_opp_nom_l2: opp8 {
5330 2309 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 2310 };
5332 2311
5333 rpmhp 2312 rpmhpd_opp_turbo: opp9 {
5334 2313 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 2314 };
5336 2315
5337 rpmhp 2316 rpmhpd_opp_turbo_l1: opp10 {
5338 2317 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 2318 };
5340 }; 2319 };
5341 }; 2320 };
>> 2321
>> 2322 rsc_hlos: interconnect {
>> 2323 compatible = "qcom,sdm845-rsc-hlos";
>> 2324 #interconnect-cells = <1>;
>> 2325 };
5342 }; 2326 };
5343 2327
5344 intc: interrupt-controller@17 2328 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 2329 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 2330 #address-cells = <2>;
5347 #size-cells = <2>; 2331 #size-cells = <2>;
5348 ranges; 2332 ranges;
5349 #interrupt-cells = <3 2333 #interrupt-cells = <3>;
5350 interrupt-controller; 2334 interrupt-controller;
5351 reg = <0 0x17a00000 0 2335 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 2336 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 2337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 2338
5355 msi-controller@17a400 !! 2339 gic-its@17a40000 {
5356 compatible = 2340 compatible = "arm,gic-v3-its";
5357 msi-controlle 2341 msi-controller;
5358 #msi-cells = 2342 #msi-cells = <1>;
5359 reg = <0 0x17 2343 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 2344 status = "disabled";
5361 }; 2345 };
5362 }; 2346 };
5363 2347
5364 slimbam: dma-controller@17184 <<
5365 compatible = "qcom,ba <<
5366 qcom,controlled-remot <<
5367 reg = <0 0x17184000 0 <<
5368 num-channels = <31>; <<
5369 interrupts = <GIC_SPI <<
5370 #dma-cells = <1>; <<
5371 qcom,ee = <1>; <<
5372 qcom,num-ees = <2>; <<
5373 iommus = <&apps_smmu <<
5374 }; <<
5375 <<
5376 timer@17c90000 { 2348 timer@17c90000 {
5377 #address-cells = <1>; !! 2349 #address-cells = <2>;
5378 #size-cells = <1>; !! 2350 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 2351 ranges;
5380 compatible = "arm,arm 2352 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 2353 reg = <0 0x17c90000 0 0x1000>;
5382 2354
5383 frame@17ca0000 { 2355 frame@17ca0000 {
5384 frame-number 2356 frame-number = <0>;
5385 interrupts = 2357 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 2358 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 2359 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 2360 <0 0x17cb0000 0 0x1000>;
5389 }; 2361 };
5390 2362
5391 frame@17cc0000 { 2363 frame@17cc0000 {
5392 frame-number 2364 frame-number = <1>;
5393 interrupts = 2365 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 2366 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 2367 status = "disabled";
5396 }; 2368 };
5397 2369
5398 frame@17cd0000 { 2370 frame@17cd0000 {
5399 frame-number 2371 frame-number = <2>;
5400 interrupts = 2372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 2373 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 2374 status = "disabled";
5403 }; 2375 };
5404 2376
5405 frame@17ce0000 { 2377 frame@17ce0000 {
5406 frame-number 2378 frame-number = <3>;
5407 interrupts = 2379 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 2380 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 2381 status = "disabled";
5410 }; 2382 };
5411 2383
5412 frame@17cf0000 { 2384 frame@17cf0000 {
5413 frame-number 2385 frame-number = <4>;
5414 interrupts = 2386 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 2387 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 2388 status = "disabled";
5417 }; 2389 };
5418 2390
5419 frame@17d00000 { 2391 frame@17d00000 {
5420 frame-number 2392 frame-number = <5>;
5421 interrupts = 2393 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 2394 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 2395 status = "disabled";
5424 }; 2396 };
5425 2397
5426 frame@17d10000 { 2398 frame@17d10000 {
5427 frame-number 2399 frame-number = <6>;
5428 interrupts = 2400 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 2401 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 2402 status = "disabled";
5431 }; 2403 };
5432 }; 2404 };
5433 2405
5434 osm_l3: interconnect@17d41000 <<
5435 compatible = "qcom,sd <<
5436 reg = <0 0x17d41000 0 <<
5437 <<
5438 clocks = <&rpmhcc RPM <<
5439 clock-names = "xo", " <<
5440 <<
5441 #interconnect-cells = <<
5442 }; <<
5443 <<
5444 cpufreq_hw: cpufreq@17d43000 2406 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 2407 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 2408 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 2409 reg-names = "freq-domain0", "freq-domain1";
5448 2410
5449 interrupts-extended = <<
5450 <<
5451 clocks = <&rpmhcc RPM 2411 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 2412 clock-names = "xo", "alternate";
5453 2413
5454 #freq-domain-cells = 2414 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 2415 };
5457 2416
5458 wifi: wifi@18800000 { 2417 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 2418 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 2419 status = "disabled";
5461 reg = <0 0x18800000 0 2420 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 2421 reg-names = "membase";
5463 memory-region = <&wla 2422 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 2423 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 2424 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 2425 interrupts =
5467 <GIC_SPI 414 2426 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 2427 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 2428 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 2429 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 2430 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 2431 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 2432 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 2433 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 2434 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 2435 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 2436 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 2437 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 2438 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 2439 };
5481 }; 2440 };
5482 2441
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 2442 thermal-zones {
5487 cpu0-thermal { 2443 cpu0-thermal {
5488 polling-delay-passive 2444 polling-delay-passive = <250>;
>> 2445 polling-delay = <1000>;
5489 2446
5490 thermal-sensors = <&t 2447 thermal-sensors = <&tsens0 1>;
5491 2448
5492 trips { 2449 trips {
5493 cpu0_alert0: !! 2450 cpu0_alert0: trip-point@0 {
5494 tempe 2451 temperature = <90000>;
5495 hyste 2452 hysteresis = <2000>;
5496 type 2453 type = "passive";
5497 }; 2454 };
5498 2455
5499 cpu0_alert1: !! 2456 cpu0_alert1: trip-point@1 {
5500 tempe 2457 temperature = <95000>;
5501 hyste 2458 hysteresis = <2000>;
5502 type 2459 type = "passive";
5503 }; 2460 };
5504 2461
5505 cpu0_crit: cp !! 2462 cpu0_crit: cpu_crit {
5506 tempe 2463 temperature = <110000>;
5507 hyste 2464 hysteresis = <1000>;
5508 type 2465 type = "critical";
5509 }; 2466 };
5510 }; 2467 };
>> 2468
>> 2469 cooling-maps {
>> 2470 map0 {
>> 2471 trip = <&cpu0_alert0>;
>> 2472 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2473 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2474 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2475 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2476 };
>> 2477 map1 {
>> 2478 trip = <&cpu0_alert1>;
>> 2479 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2480 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2481 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2482 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2483 };
>> 2484 };
5511 }; 2485 };
5512 2486
5513 cpu1-thermal { 2487 cpu1-thermal {
5514 polling-delay-passive 2488 polling-delay-passive = <250>;
>> 2489 polling-delay = <1000>;
5515 2490
5516 thermal-sensors = <&t 2491 thermal-sensors = <&tsens0 2>;
5517 2492
5518 trips { 2493 trips {
5519 cpu1_alert0: !! 2494 cpu1_alert0: trip-point@0 {
5520 tempe 2495 temperature = <90000>;
5521 hyste 2496 hysteresis = <2000>;
5522 type 2497 type = "passive";
5523 }; 2498 };
5524 2499
5525 cpu1_alert1: !! 2500 cpu1_alert1: trip-point@1 {
5526 tempe 2501 temperature = <95000>;
5527 hyste 2502 hysteresis = <2000>;
5528 type 2503 type = "passive";
5529 }; 2504 };
5530 2505
5531 cpu1_crit: cp !! 2506 cpu1_crit: cpu_crit {
5532 tempe 2507 temperature = <110000>;
5533 hyste 2508 hysteresis = <1000>;
5534 type 2509 type = "critical";
5535 }; 2510 };
5536 }; 2511 };
>> 2512
>> 2513 cooling-maps {
>> 2514 map0 {
>> 2515 trip = <&cpu1_alert0>;
>> 2516 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2517 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2518 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2519 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2520 };
>> 2521 map1 {
>> 2522 trip = <&cpu1_alert1>;
>> 2523 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2524 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2525 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2526 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2527 };
>> 2528 };
5537 }; 2529 };
5538 2530
5539 cpu2-thermal { 2531 cpu2-thermal {
5540 polling-delay-passive 2532 polling-delay-passive = <250>;
>> 2533 polling-delay = <1000>;
5541 2534
5542 thermal-sensors = <&t 2535 thermal-sensors = <&tsens0 3>;
5543 2536
5544 trips { 2537 trips {
5545 cpu2_alert0: !! 2538 cpu2_alert0: trip-point@0 {
5546 tempe 2539 temperature = <90000>;
5547 hyste 2540 hysteresis = <2000>;
5548 type 2541 type = "passive";
5549 }; 2542 };
5550 2543
5551 cpu2_alert1: !! 2544 cpu2_alert1: trip-point@1 {
5552 tempe 2545 temperature = <95000>;
5553 hyste 2546 hysteresis = <2000>;
5554 type 2547 type = "passive";
5555 }; 2548 };
5556 2549
5557 cpu2_crit: cp !! 2550 cpu2_crit: cpu_crit {
5558 tempe 2551 temperature = <110000>;
5559 hyste 2552 hysteresis = <1000>;
5560 type 2553 type = "critical";
5561 }; 2554 };
5562 }; 2555 };
>> 2556
>> 2557 cooling-maps {
>> 2558 map0 {
>> 2559 trip = <&cpu2_alert0>;
>> 2560 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2561 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2562 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2563 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2564 };
>> 2565 map1 {
>> 2566 trip = <&cpu2_alert1>;
>> 2567 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2568 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2569 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2570 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2571 };
>> 2572 };
5563 }; 2573 };
5564 2574
5565 cpu3-thermal { 2575 cpu3-thermal {
5566 polling-delay-passive 2576 polling-delay-passive = <250>;
>> 2577 polling-delay = <1000>;
5567 2578
5568 thermal-sensors = <&t 2579 thermal-sensors = <&tsens0 4>;
5569 2580
5570 trips { 2581 trips {
5571 cpu3_alert0: !! 2582 cpu3_alert0: trip-point@0 {
5572 tempe 2583 temperature = <90000>;
5573 hyste 2584 hysteresis = <2000>;
5574 type 2585 type = "passive";
5575 }; 2586 };
5576 2587
5577 cpu3_alert1: !! 2588 cpu3_alert1: trip-point@1 {
5578 tempe 2589 temperature = <95000>;
5579 hyste 2590 hysteresis = <2000>;
5580 type 2591 type = "passive";
5581 }; 2592 };
5582 2593
5583 cpu3_crit: cp !! 2594 cpu3_crit: cpu_crit {
5584 tempe 2595 temperature = <110000>;
5585 hyste 2596 hysteresis = <1000>;
5586 type 2597 type = "critical";
5587 }; 2598 };
5588 }; 2599 };
>> 2600
>> 2601 cooling-maps {
>> 2602 map0 {
>> 2603 trip = <&cpu3_alert0>;
>> 2604 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2605 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2606 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2607 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2608 };
>> 2609 map1 {
>> 2610 trip = <&cpu3_alert1>;
>> 2611 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2612 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2613 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2614 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2615 };
>> 2616 };
5589 }; 2617 };
5590 2618
5591 cpu4-thermal { 2619 cpu4-thermal {
5592 polling-delay-passive 2620 polling-delay-passive = <250>;
>> 2621 polling-delay = <1000>;
5593 2622
5594 thermal-sensors = <&t 2623 thermal-sensors = <&tsens0 7>;
5595 2624
5596 trips { 2625 trips {
5597 cpu4_alert0: !! 2626 cpu4_alert0: trip-point@0 {
5598 tempe 2627 temperature = <90000>;
5599 hyste 2628 hysteresis = <2000>;
5600 type 2629 type = "passive";
5601 }; 2630 };
5602 2631
5603 cpu4_alert1: !! 2632 cpu4_alert1: trip-point@1 {
5604 tempe 2633 temperature = <95000>;
5605 hyste 2634 hysteresis = <2000>;
5606 type 2635 type = "passive";
5607 }; 2636 };
5608 2637
5609 cpu4_crit: cp !! 2638 cpu4_crit: cpu_crit {
5610 tempe 2639 temperature = <110000>;
5611 hyste 2640 hysteresis = <1000>;
5612 type 2641 type = "critical";
5613 }; 2642 };
5614 }; 2643 };
>> 2644
>> 2645 cooling-maps {
>> 2646 map0 {
>> 2647 trip = <&cpu4_alert0>;
>> 2648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2652 };
>> 2653 map1 {
>> 2654 trip = <&cpu4_alert1>;
>> 2655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2659 };
>> 2660 };
5615 }; 2661 };
5616 2662
5617 cpu5-thermal { 2663 cpu5-thermal {
5618 polling-delay-passive 2664 polling-delay-passive = <250>;
>> 2665 polling-delay = <1000>;
5619 2666
5620 thermal-sensors = <&t 2667 thermal-sensors = <&tsens0 8>;
5621 2668
5622 trips { 2669 trips {
5623 cpu5_alert0: !! 2670 cpu5_alert0: trip-point@0 {
5624 tempe 2671 temperature = <90000>;
5625 hyste 2672 hysteresis = <2000>;
5626 type 2673 type = "passive";
5627 }; 2674 };
5628 2675
5629 cpu5_alert1: !! 2676 cpu5_alert1: trip-point@1 {
5630 tempe 2677 temperature = <95000>;
5631 hyste 2678 hysteresis = <2000>;
5632 type 2679 type = "passive";
5633 }; 2680 };
5634 2681
5635 cpu5_crit: cp !! 2682 cpu5_crit: cpu_crit {
5636 tempe 2683 temperature = <110000>;
5637 hyste 2684 hysteresis = <1000>;
5638 type 2685 type = "critical";
5639 }; 2686 };
5640 }; 2687 };
>> 2688
>> 2689 cooling-maps {
>> 2690 map0 {
>> 2691 trip = <&cpu5_alert0>;
>> 2692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2696 };
>> 2697 map1 {
>> 2698 trip = <&cpu5_alert1>;
>> 2699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2703 };
>> 2704 };
5641 }; 2705 };
5642 2706
5643 cpu6-thermal { 2707 cpu6-thermal {
5644 polling-delay-passive 2708 polling-delay-passive = <250>;
>> 2709 polling-delay = <1000>;
5645 2710
5646 thermal-sensors = <&t 2711 thermal-sensors = <&tsens0 9>;
5647 2712
5648 trips { 2713 trips {
5649 cpu6_alert0: !! 2714 cpu6_alert0: trip-point@0 {
5650 tempe 2715 temperature = <90000>;
5651 hyste 2716 hysteresis = <2000>;
5652 type 2717 type = "passive";
5653 }; 2718 };
5654 2719
5655 cpu6_alert1: !! 2720 cpu6_alert1: trip-point@1 {
5656 tempe 2721 temperature = <95000>;
5657 hyste 2722 hysteresis = <2000>;
5658 type 2723 type = "passive";
5659 }; 2724 };
5660 2725
5661 cpu6_crit: cp !! 2726 cpu6_crit: cpu_crit {
5662 tempe 2727 temperature = <110000>;
5663 hyste 2728 hysteresis = <1000>;
5664 type 2729 type = "critical";
5665 }; 2730 };
5666 }; 2731 };
>> 2732
>> 2733 cooling-maps {
>> 2734 map0 {
>> 2735 trip = <&cpu6_alert0>;
>> 2736 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2737 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2738 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2739 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2740 };
>> 2741 map1 {
>> 2742 trip = <&cpu6_alert1>;
>> 2743 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2744 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2745 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2746 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2747 };
>> 2748 };
5667 }; 2749 };
5668 2750
5669 cpu7-thermal { 2751 cpu7-thermal {
5670 polling-delay-passive 2752 polling-delay-passive = <250>;
>> 2753 polling-delay = <1000>;
5671 2754
5672 thermal-sensors = <&t 2755 thermal-sensors = <&tsens0 10>;
5673 2756
5674 trips { 2757 trips {
5675 cpu7_alert0: !! 2758 cpu7_alert0: trip-point@0 {
5676 tempe 2759 temperature = <90000>;
5677 hyste 2760 hysteresis = <2000>;
5678 type 2761 type = "passive";
5679 }; 2762 };
5680 2763
5681 cpu7_alert1: !! 2764 cpu7_alert1: trip-point@1 {
5682 tempe 2765 temperature = <95000>;
5683 hyste 2766 hysteresis = <2000>;
5684 type 2767 type = "passive";
5685 }; 2768 };
5686 2769
5687 cpu7_crit: cp !! 2770 cpu7_crit: cpu_crit {
5688 tempe 2771 temperature = <110000>;
5689 hyste 2772 hysteresis = <1000>;
5690 type 2773 type = "critical";
5691 }; 2774 };
5692 }; 2775 };
>> 2776
>> 2777 cooling-maps {
>> 2778 map0 {
>> 2779 trip = <&cpu7_alert0>;
>> 2780 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2782 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2783 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2784 };
>> 2785 map1 {
>> 2786 trip = <&cpu7_alert1>;
>> 2787 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2788 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2789 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 2790 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 2791 };
>> 2792 };
5693 }; 2793 };
5694 2794
5695 aoss0-thermal { 2795 aoss0-thermal {
5696 polling-delay-passive 2796 polling-delay-passive = <250>;
>> 2797 polling-delay = <1000>;
5697 2798
5698 thermal-sensors = <&t 2799 thermal-sensors = <&tsens0 0>;
5699 2800
5700 trips { 2801 trips {
5701 aoss0_alert0: !! 2802 aoss0_alert0: trip-point@0 {
5702 tempe 2803 temperature = <90000>;
5703 hyste 2804 hysteresis = <2000>;
5704 type 2805 type = "hot";
5705 }; 2806 };
5706 }; 2807 };
5707 }; 2808 };
5708 2809
5709 cluster0-thermal { 2810 cluster0-thermal {
5710 polling-delay-passive 2811 polling-delay-passive = <250>;
>> 2812 polling-delay = <1000>;
5711 2813
5712 thermal-sensors = <&t 2814 thermal-sensors = <&tsens0 5>;
5713 2815
5714 trips { 2816 trips {
5715 cluster0_aler !! 2817 cluster0_alert0: trip-point@0 {
5716 tempe 2818 temperature = <90000>;
5717 hyste 2819 hysteresis = <2000>;
5718 type 2820 type = "hot";
5719 }; 2821 };
5720 cluster0_crit !! 2822 cluster0_crit: cluster0_crit {
5721 tempe 2823 temperature = <110000>;
5722 hyste 2824 hysteresis = <2000>;
5723 type 2825 type = "critical";
5724 }; 2826 };
5725 }; 2827 };
5726 }; 2828 };
5727 2829
5728 cluster1-thermal { 2830 cluster1-thermal {
5729 polling-delay-passive 2831 polling-delay-passive = <250>;
>> 2832 polling-delay = <1000>;
5730 2833
5731 thermal-sensors = <&t 2834 thermal-sensors = <&tsens0 6>;
5732 2835
5733 trips { 2836 trips {
5734 cluster1_aler !! 2837 cluster1_alert0: trip-point@0 {
5735 tempe 2838 temperature = <90000>;
5736 hyste 2839 hysteresis = <2000>;
5737 type 2840 type = "hot";
5738 }; 2841 };
5739 cluster1_crit !! 2842 cluster1_crit: cluster1_crit {
5740 tempe 2843 temperature = <110000>;
5741 hyste 2844 hysteresis = <2000>;
5742 type 2845 type = "critical";
5743 }; 2846 };
5744 }; 2847 };
5745 }; 2848 };
5746 2849
5747 gpu-top-thermal { !! 2850 gpu-thermal-top {
5748 polling-delay-passive 2851 polling-delay-passive = <250>;
>> 2852 polling-delay = <1000>;
5749 2853
5750 thermal-sensors = <&t 2854 thermal-sensors = <&tsens0 11>;
5751 2855
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 2856 trips {
5760 gpu_top_alert !! 2857 gpu1_alert0: trip-point@0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 2858 temperature = <90000>;
5768 hyste !! 2859 hysteresis = <2000>;
5769 type 2860 type = "hot";
5770 }; 2861 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 2862 };
5778 }; 2863 };
5779 2864
5780 gpu-bottom-thermal { !! 2865 gpu-thermal-bottom {
5781 polling-delay-passive 2866 polling-delay-passive = <250>;
>> 2867 polling-delay = <1000>;
5782 2868
5783 thermal-sensors = <&t 2869 thermal-sensors = <&tsens0 12>;
5784 2870
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 2871 trips {
5793 gpu_bottom_al !! 2872 gpu2_alert0: trip-point@0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 2873 temperature = <90000>;
5801 hyste !! 2874 hysteresis = <2000>;
5802 type 2875 type = "hot";
5803 }; 2876 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 2877 };
5811 }; 2878 };
5812 2879
5813 aoss1-thermal { 2880 aoss1-thermal {
5814 polling-delay-passive 2881 polling-delay-passive = <250>;
>> 2882 polling-delay = <1000>;
5815 2883
5816 thermal-sensors = <&t 2884 thermal-sensors = <&tsens1 0>;
5817 2885
5818 trips { 2886 trips {
5819 aoss1_alert0: !! 2887 aoss1_alert0: trip-point@0 {
5820 tempe 2888 temperature = <90000>;
5821 hyste 2889 hysteresis = <2000>;
5822 type 2890 type = "hot";
5823 }; 2891 };
5824 }; 2892 };
5825 }; 2893 };
5826 2894
5827 q6-modem-thermal { 2895 q6-modem-thermal {
5828 polling-delay-passive 2896 polling-delay-passive = <250>;
>> 2897 polling-delay = <1000>;
5829 2898
5830 thermal-sensors = <&t 2899 thermal-sensors = <&tsens1 1>;
5831 2900
5832 trips { 2901 trips {
5833 q6_modem_aler !! 2902 q6_modem_alert0: trip-point@0 {
5834 tempe 2903 temperature = <90000>;
5835 hyste 2904 hysteresis = <2000>;
5836 type 2905 type = "hot";
5837 }; 2906 };
5838 }; 2907 };
5839 }; 2908 };
5840 2909
5841 mem-thermal { 2910 mem-thermal {
5842 polling-delay-passive 2911 polling-delay-passive = <250>;
>> 2912 polling-delay = <1000>;
5843 2913
5844 thermal-sensors = <&t 2914 thermal-sensors = <&tsens1 2>;
5845 2915
5846 trips { 2916 trips {
5847 mem_alert0: t !! 2917 mem_alert0: trip-point@0 {
5848 tempe 2918 temperature = <90000>;
5849 hyste 2919 hysteresis = <2000>;
5850 type 2920 type = "hot";
5851 }; 2921 };
5852 }; 2922 };
5853 }; 2923 };
5854 2924
5855 wlan-thermal { 2925 wlan-thermal {
5856 polling-delay-passive 2926 polling-delay-passive = <250>;
>> 2927 polling-delay = <1000>;
5857 2928
5858 thermal-sensors = <&t 2929 thermal-sensors = <&tsens1 3>;
5859 2930
5860 trips { 2931 trips {
5861 wlan_alert0: !! 2932 wlan_alert0: trip-point@0 {
5862 tempe 2933 temperature = <90000>;
5863 hyste 2934 hysteresis = <2000>;
5864 type 2935 type = "hot";
5865 }; 2936 };
5866 }; 2937 };
5867 }; 2938 };
5868 2939
5869 q6-hvx-thermal { 2940 q6-hvx-thermal {
5870 polling-delay-passive 2941 polling-delay-passive = <250>;
>> 2942 polling-delay = <1000>;
5871 2943
5872 thermal-sensors = <&t 2944 thermal-sensors = <&tsens1 4>;
5873 2945
5874 trips { 2946 trips {
5875 q6_hvx_alert0 !! 2947 q6_hvx_alert0: trip-point@0 {
5876 tempe 2948 temperature = <90000>;
5877 hyste 2949 hysteresis = <2000>;
5878 type 2950 type = "hot";
5879 }; 2951 };
5880 }; 2952 };
5881 }; 2953 };
5882 2954
5883 camera-thermal { 2955 camera-thermal {
5884 polling-delay-passive 2956 polling-delay-passive = <250>;
>> 2957 polling-delay = <1000>;
5885 2958
5886 thermal-sensors = <&t 2959 thermal-sensors = <&tsens1 5>;
5887 2960
5888 trips { 2961 trips {
5889 camera_alert0 !! 2962 camera_alert0: trip-point@0 {
5890 tempe 2963 temperature = <90000>;
5891 hyste 2964 hysteresis = <2000>;
5892 type 2965 type = "hot";
5893 }; 2966 };
5894 }; 2967 };
5895 }; 2968 };
5896 2969
5897 video-thermal { 2970 video-thermal {
5898 polling-delay-passive 2971 polling-delay-passive = <250>;
>> 2972 polling-delay = <1000>;
5899 2973
5900 thermal-sensors = <&t 2974 thermal-sensors = <&tsens1 6>;
5901 2975
5902 trips { 2976 trips {
5903 video_alert0: !! 2977 video_alert0: trip-point@0 {
5904 tempe 2978 temperature = <90000>;
5905 hyste 2979 hysteresis = <2000>;
5906 type 2980 type = "hot";
5907 }; 2981 };
5908 }; 2982 };
5909 }; 2983 };
5910 2984
5911 modem-thermal { 2985 modem-thermal {
5912 polling-delay-passive 2986 polling-delay-passive = <250>;
>> 2987 polling-delay = <1000>;
5913 2988
5914 thermal-sensors = <&t 2989 thermal-sensors = <&tsens1 7>;
5915 2990
5916 trips { 2991 trips {
5917 modem_alert0: !! 2992 modem_alert0: trip-point@0 {
5918 tempe 2993 temperature = <90000>;
5919 hyste 2994 hysteresis = <2000>;
5920 type 2995 type = "hot";
5921 }; 2996 };
5922 }; 2997 };
5923 }; 2998 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 2999 };
5933 }; 3000 };
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