1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. <<
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 8 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 9 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 10 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 11 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 13 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> <<
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 <<
20 #include <dt-bindings/interconnect/qcom,sdm845 14 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 16 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 18 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 19 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> <<
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 21 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
31 23
32 / { 24 / {
33 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
34 26
35 #address-cells = <2>; 27 #address-cells = <2>;
36 #size-cells = <2>; 28 #size-cells = <2>;
37 29
38 aliases { 30 aliases {
39 i2c0 = &i2c0; 31 i2c0 = &i2c0;
40 i2c1 = &i2c1; 32 i2c1 = &i2c1;
41 i2c2 = &i2c2; 33 i2c2 = &i2c2;
42 i2c3 = &i2c3; 34 i2c3 = &i2c3;
43 i2c4 = &i2c4; 35 i2c4 = &i2c4;
44 i2c5 = &i2c5; 36 i2c5 = &i2c5;
45 i2c6 = &i2c6; 37 i2c6 = &i2c6;
46 i2c7 = &i2c7; 38 i2c7 = &i2c7;
47 i2c8 = &i2c8; 39 i2c8 = &i2c8;
48 i2c9 = &i2c9; 40 i2c9 = &i2c9;
49 i2c10 = &i2c10; 41 i2c10 = &i2c10;
50 i2c11 = &i2c11; 42 i2c11 = &i2c11;
51 i2c12 = &i2c12; 43 i2c12 = &i2c12;
52 i2c13 = &i2c13; 44 i2c13 = &i2c13;
53 i2c14 = &i2c14; 45 i2c14 = &i2c14;
54 i2c15 = &i2c15; 46 i2c15 = &i2c15;
55 spi0 = &spi0; 47 spi0 = &spi0;
56 spi1 = &spi1; 48 spi1 = &spi1;
57 spi2 = &spi2; 49 spi2 = &spi2;
58 spi3 = &spi3; 50 spi3 = &spi3;
59 spi4 = &spi4; 51 spi4 = &spi4;
60 spi5 = &spi5; 52 spi5 = &spi5;
61 spi6 = &spi6; 53 spi6 = &spi6;
62 spi7 = &spi7; 54 spi7 = &spi7;
63 spi8 = &spi8; 55 spi8 = &spi8;
64 spi9 = &spi9; 56 spi9 = &spi9;
65 spi10 = &spi10; 57 spi10 = &spi10;
66 spi11 = &spi11; 58 spi11 = &spi11;
67 spi12 = &spi12; 59 spi12 = &spi12;
68 spi13 = &spi13; 60 spi13 = &spi13;
69 spi14 = &spi14; 61 spi14 = &spi14;
70 spi15 = &spi15; 62 spi15 = &spi15;
71 }; 63 };
72 64
73 chosen { }; 65 chosen { };
74 66
75 clocks { !! 67 memory@80000000 {
76 xo_board: xo-board { !! 68 device_type = "memory";
77 compatible = "fixed-cl !! 69 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 70 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 71 };
80 clock-output-names = " !! 72
>> 73 reserved-memory {
>> 74 #address-cells = <2>;
>> 75 #size-cells = <2>;
>> 76 ranges;
>> 77
>> 78 hyp_mem: memory@85700000 {
>> 79 reg = <0 0x85700000 0 0x600000>;
>> 80 no-map;
81 }; 81 };
82 82
83 sleep_clk: sleep-clk { !! 83 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 84 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 85 no-map;
86 clock-frequency = <327 !! 86 };
>> 87
>> 88 aop_mem: memory@85fc0000 {
>> 89 reg = <0 0x85fc0000 0 0x20000>;
>> 90 no-map;
>> 91 };
>> 92
>> 93 aop_cmd_db_mem: memory@85fe0000 {
>> 94 compatible = "qcom,cmd-db";
>> 95 reg = <0x0 0x85fe0000 0 0x20000>;
>> 96 no-map;
>> 97 };
>> 98
>> 99 smem_mem: memory@86000000 {
>> 100 reg = <0x0 0x86000000 0 0x200000>;
>> 101 no-map;
>> 102 };
>> 103
>> 104 tz_mem: memory@86200000 {
>> 105 reg = <0 0x86200000 0 0x2d00000>;
>> 106 no-map;
>> 107 };
>> 108
>> 109 rmtfs_mem: memory@88f00000 {
>> 110 compatible = "qcom,rmtfs-mem";
>> 111 reg = <0 0x88f00000 0 0x200000>;
>> 112 no-map;
>> 113
>> 114 qcom,client-id = <1>;
>> 115 qcom,vmid = <15>;
>> 116 };
>> 117
>> 118 qseecom_mem: memory@8ab00000 {
>> 119 reg = <0 0x8ab00000 0 0x1400000>;
>> 120 no-map;
>> 121 };
>> 122
>> 123 camera_mem: memory@8bf00000 {
>> 124 reg = <0 0x8bf00000 0 0x500000>;
>> 125 no-map;
>> 126 };
>> 127
>> 128 ipa_fw_mem: memory@8c400000 {
>> 129 reg = <0 0x8c400000 0 0x10000>;
>> 130 no-map;
>> 131 };
>> 132
>> 133 ipa_gsi_mem: memory@8c410000 {
>> 134 reg = <0 0x8c410000 0 0x5000>;
>> 135 no-map;
>> 136 };
>> 137
>> 138 gpu_mem: memory@8c415000 {
>> 139 reg = <0 0x8c415000 0 0x2000>;
>> 140 no-map;
>> 141 };
>> 142
>> 143 adsp_mem: memory@8c500000 {
>> 144 reg = <0 0x8c500000 0 0x1a00000>;
>> 145 no-map;
>> 146 };
>> 147
>> 148 wlan_msa_mem: memory@8df00000 {
>> 149 reg = <0 0x8df00000 0 0x100000>;
>> 150 no-map;
>> 151 };
>> 152
>> 153 mpss_region: memory@8e000000 {
>> 154 reg = <0 0x8e000000 0 0x7800000>;
>> 155 no-map;
>> 156 };
>> 157
>> 158 venus_mem: memory@95800000 {
>> 159 reg = <0 0x95800000 0 0x500000>;
>> 160 no-map;
>> 161 };
>> 162
>> 163 cdsp_mem: memory@95d00000 {
>> 164 reg = <0 0x95d00000 0 0x800000>;
>> 165 no-map;
>> 166 };
>> 167
>> 168 mba_region: memory@96500000 {
>> 169 reg = <0 0x96500000 0 0x200000>;
>> 170 no-map;
>> 171 };
>> 172
>> 173 slpi_mem: memory@96700000 {
>> 174 reg = <0 0x96700000 0 0x1400000>;
>> 175 no-map;
>> 176 };
>> 177
>> 178 spss_mem: memory@97b00000 {
>> 179 reg = <0 0x97b00000 0 0x100000>;
>> 180 no-map;
87 }; 181 };
88 }; 182 };
89 183
90 cpus: cpus { !! 184 cpus {
91 #address-cells = <2>; 185 #address-cells = <2>;
92 #size-cells = <0>; 186 #size-cells = <0>;
93 187
94 CPU0: cpu@0 { 188 CPU0: cpu@0 {
95 device_type = "cpu"; 189 device_type = "cpu";
96 compatible = "qcom,kry 190 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 191 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 192 enable-method = "psci";
100 capacity-dmips-mhz = < !! 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101 dynamic-power-coeffici !! 194 &LITTLE_CPU_SLEEP_1
>> 195 &CLUSTER_SLEEP_0>;
>> 196 capacity-dmips-mhz = <607>;
>> 197 dynamic-power-coefficient = <100>;
102 qcom,freq-domain = <&c 198 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = <<
104 interconnects = <&glad <<
105 <&osm_ <<
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 199 #cooling-cells = <2>;
109 next-level-cache = <&L 200 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 201 L2_0: l2-cache {
111 compatible = " 202 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 203 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 204 L3_0: l3-cache {
116 compat !! 205 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 206 };
120 }; 207 };
121 }; 208 };
122 209
123 CPU1: cpu@100 { 210 CPU1: cpu@100 {
124 device_type = "cpu"; 211 device_type = "cpu";
125 compatible = "qcom,kry 212 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 213 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 214 enable-method = "psci";
129 capacity-dmips-mhz = < !! 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130 dynamic-power-coeffici !! 216 &LITTLE_CPU_SLEEP_1
>> 217 &CLUSTER_SLEEP_0>;
>> 218 capacity-dmips-mhz = <607>;
>> 219 dynamic-power-coefficient = <100>;
131 qcom,freq-domain = <&c 220 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <<
133 interconnects = <&glad <<
134 <&osm_ <<
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 221 #cooling-cells = <2>;
138 next-level-cache = <&L 222 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 223 L2_100: l2-cache {
140 compatible = " 224 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 225 next-level-cache = <&L3_0>;
144 }; 226 };
145 }; 227 };
146 228
147 CPU2: cpu@200 { 229 CPU2: cpu@200 {
148 device_type = "cpu"; 230 device_type = "cpu";
149 compatible = "qcom,kry 231 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 232 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 233 enable-method = "psci";
153 capacity-dmips-mhz = < !! 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154 dynamic-power-coeffici !! 235 &LITTLE_CPU_SLEEP_1
>> 236 &CLUSTER_SLEEP_0>;
>> 237 capacity-dmips-mhz = <607>;
>> 238 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&c 239 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = <<
157 interconnects = <&glad <<
158 <&osm_ <<
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 240 #cooling-cells = <2>;
162 next-level-cache = <&L 241 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 242 L2_200: l2-cache {
164 compatible = " 243 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 244 next-level-cache = <&L3_0>;
168 }; 245 };
169 }; 246 };
170 247
171 CPU3: cpu@300 { 248 CPU3: cpu@300 {
172 device_type = "cpu"; 249 device_type = "cpu";
173 compatible = "qcom,kry 250 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 251 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 252 enable-method = "psci";
177 capacity-dmips-mhz = < !! 253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178 dynamic-power-coeffici !! 254 &LITTLE_CPU_SLEEP_1
>> 255 &CLUSTER_SLEEP_0>;
>> 256 capacity-dmips-mhz = <607>;
>> 257 dynamic-power-coefficient = <100>;
179 qcom,freq-domain = <&c 258 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = <<
181 interconnects = <&glad <<
182 <&osm_ <<
183 #cooling-cells = <2>; 259 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 260 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 261 L2_300: l2-cache {
188 compatible = " 262 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 263 next-level-cache = <&L3_0>;
192 }; 264 };
193 }; 265 };
194 266
195 CPU4: cpu@400 { 267 CPU4: cpu@400 {
196 device_type = "cpu"; 268 device_type = "cpu";
197 compatible = "qcom,kry 269 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 270 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 271 enable-method = "psci";
201 capacity-dmips-mhz = < 272 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici !! 273 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 274 &BIG_CPU_SLEEP_1
>> 275 &CLUSTER_SLEEP_0>;
>> 276 dynamic-power-coefficient = <396>;
203 qcom,freq-domain = <&c 277 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = <<
205 interconnects = <&glad <<
206 <&osm_ <<
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 278 #cooling-cells = <2>;
210 next-level-cache = <&L 279 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 280 L2_400: l2-cache {
212 compatible = " 281 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 282 next-level-cache = <&L3_0>;
216 }; 283 };
217 }; 284 };
218 285
219 CPU5: cpu@500 { 286 CPU5: cpu@500 {
220 device_type = "cpu"; 287 device_type = "cpu";
221 compatible = "qcom,kry 288 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 289 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 290 enable-method = "psci";
225 capacity-dmips-mhz = < 291 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici !! 292 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 293 &BIG_CPU_SLEEP_1
>> 294 &CLUSTER_SLEEP_0>;
>> 295 dynamic-power-coefficient = <396>;
227 qcom,freq-domain = <&c 296 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = <<
229 interconnects = <&glad <<
230 <&osm_ <<
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 297 #cooling-cells = <2>;
234 next-level-cache = <&L 298 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 299 L2_500: l2-cache {
236 compatible = " 300 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 301 next-level-cache = <&L3_0>;
240 }; 302 };
241 }; 303 };
242 304
243 CPU6: cpu@600 { 305 CPU6: cpu@600 {
244 device_type = "cpu"; 306 device_type = "cpu";
245 compatible = "qcom,kry 307 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 308 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 309 enable-method = "psci";
249 capacity-dmips-mhz = < 310 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici !! 311 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 312 &BIG_CPU_SLEEP_1
>> 313 &CLUSTER_SLEEP_0>;
>> 314 dynamic-power-coefficient = <396>;
251 qcom,freq-domain = <&c 315 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = <<
253 interconnects = <&glad <<
254 <&osm_ <<
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 316 #cooling-cells = <2>;
258 next-level-cache = <&L 317 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 318 L2_600: l2-cache {
260 compatible = " 319 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 320 next-level-cache = <&L3_0>;
264 }; 321 };
265 }; 322 };
266 323
267 CPU7: cpu@700 { 324 CPU7: cpu@700 {
268 device_type = "cpu"; 325 device_type = "cpu";
269 compatible = "qcom,kry 326 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 327 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 328 enable-method = "psci";
273 capacity-dmips-mhz = < 329 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici !! 330 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 331 &BIG_CPU_SLEEP_1
>> 332 &CLUSTER_SLEEP_0>;
>> 333 dynamic-power-coefficient = <396>;
275 qcom,freq-domain = <&c 334 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = <<
277 interconnects = <&glad <<
278 <&osm_ <<
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 335 #cooling-cells = <2>;
282 next-level-cache = <&L 336 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 337 L2_700: l2-cache {
284 compatible = " 338 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 339 next-level-cache = <&L3_0>;
288 }; 340 };
289 }; 341 };
290 342
291 cpu-map { 343 cpu-map {
292 cluster0 { 344 cluster0 {
293 core0 { 345 core0 {
294 cpu = 346 cpu = <&CPU0>;
295 }; 347 };
296 348
297 core1 { 349 core1 {
298 cpu = 350 cpu = <&CPU1>;
299 }; 351 };
300 352
301 core2 { 353 core2 {
302 cpu = 354 cpu = <&CPU2>;
303 }; 355 };
304 356
305 core3 { 357 core3 {
306 cpu = 358 cpu = <&CPU3>;
307 }; 359 };
308 360
309 core4 { 361 core4 {
310 cpu = 362 cpu = <&CPU4>;
311 }; 363 };
312 364
313 core5 { 365 core5 {
314 cpu = 366 cpu = <&CPU5>;
315 }; 367 };
316 368
317 core6 { 369 core6 {
318 cpu = 370 cpu = <&CPU6>;
319 }; 371 };
320 372
321 core7 { 373 core7 {
322 cpu = 374 cpu = <&CPU7>;
323 }; 375 };
324 }; 376 };
325 }; 377 };
326 378
327 cpu_idle_states: idle-states { !! 379 idle-states {
328 entry-method = "psci"; 380 entry-method = "psci";
329 381
330 LITTLE_CPU_SLEEP_0: cp 382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 383 compatible = "arm,idle-state";
332 idle-state-nam !! 384 idle-state-name = "little-power-down";
333 arm,psci-suspe !! 385 arm,psci-suspend-param = <0x40000003>;
334 entry-latency- 386 entry-latency-us = <350>;
335 exit-latency-u 387 exit-latency-us = <461>;
336 min-residency- 388 min-residency-us = <1890>;
337 local-timer-st 389 local-timer-stop;
338 }; 390 };
339 391
340 BIG_CPU_SLEEP_0: cpu-s !! 392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341 compatible = " 393 compatible = "arm,idle-state";
342 idle-state-nam !! 394 idle-state-name = "little-rail-power-down";
343 arm,psci-suspe 395 arm,psci-suspend-param = <0x40000004>;
>> 396 entry-latency-us = <360>;
>> 397 exit-latency-us = <531>;
>> 398 min-residency-us = <3934>;
>> 399 local-timer-stop;
>> 400 };
>> 401
>> 402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> 403 compatible = "arm,idle-state";
>> 404 idle-state-name = "big-power-down";
>> 405 arm,psci-suspend-param = <0x40000003>;
344 entry-latency- 406 entry-latency-us = <264>;
345 exit-latency-u 407 exit-latency-us = <621>;
346 min-residency- 408 min-residency-us = <952>;
347 local-timer-st 409 local-timer-stop;
348 }; 410 };
349 }; <<
350 411
351 domain-idle-states { !! 412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
>> 413 compatible = "arm,idle-state";
>> 414 idle-state-name = "big-rail-power-down";
>> 415 arm,psci-suspend-param = <0x40000004>;
>> 416 entry-latency-us = <702>;
>> 417 exit-latency-us = <1061>;
>> 418 min-residency-us = <4488>;
>> 419 local-timer-stop;
>> 420 };
>> 421
352 CLUSTER_SLEEP_0: clust 422 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " !! 423 compatible = "arm,idle-state";
354 arm,psci-suspe !! 424 idle-state-name = "cluster-power-down";
>> 425 arm,psci-suspend-param = <0x400000F4>;
355 entry-latency- 426 entry-latency-us = <3263>;
356 exit-latency-u 427 exit-latency-us = <6562>;
357 min-residency- 428 min-residency-us = <9987>;
>> 429 local-timer-stop;
358 }; 430 };
359 }; 431 };
360 }; 432 };
361 433
362 firmware { <<
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points <<
376 opp-shared; <<
377 <<
378 cpu0_opp1: opp-300000000 { <<
379 opp-hz = /bits/ 64 <30 <<
380 opp-peak-kBps = <80000 <<
381 }; <<
382 <<
383 cpu0_opp2: opp-403200000 { <<
384 opp-hz = /bits/ 64 <40 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp3: opp-480000000 { <<
389 opp-hz = /bits/ 64 <48 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp4: opp-576000000 { <<
394 opp-hz = /bits/ 64 <57 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp5: opp-652800000 { <<
399 opp-hz = /bits/ 64 <65 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp6: opp-748800000 { <<
404 opp-hz = /bits/ 64 <74 <<
405 opp-peak-kBps = <18040 <<
406 }; <<
407 <<
408 cpu0_opp7: opp-825600000 { <<
409 opp-hz = /bits/ 64 <82 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp8: opp-902400000 { <<
414 opp-hz = /bits/ 64 <90 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp9: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp10: opp-1056000000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp11: opp-1132800000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu0_opp12: opp-1228800000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <21880 <<
436 }; <<
437 <<
438 cpu0_opp13: opp-1324800000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp14: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <30720 <<
446 }; <<
447 <<
448 cpu0_opp15: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp16: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <40680 <<
456 }; <<
457 <<
458 cpu0_opp17: opp-1689600000 { <<
459 opp-hz = /bits/ 64 <16 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp18: opp-1766400000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-300000000 { <<
474 opp-hz = /bits/ 64 <30 <<
475 opp-peak-kBps = <80000 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-403200000 { <<
479 opp-hz = /bits/ 64 <40 <<
480 opp-peak-kBps = <80000 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-480000000 { <<
484 opp-hz = /bits/ 64 <48 <<
485 opp-peak-kBps = <18040 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-576000000 { <<
489 opp-hz = /bits/ 64 <57 <<
490 opp-peak-kBps = <18040 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-652800000 { <<
494 opp-hz = /bits/ 64 <65 <<
495 opp-peak-kBps = <18040 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-748800000 { <<
499 opp-hz = /bits/ 64 <74 <<
500 opp-peak-kBps = <18040 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-825600000 { <<
504 opp-hz = /bits/ 64 <82 <<
505 opp-peak-kBps = <21880 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-902400000 { <<
509 opp-hz = /bits/ 64 <90 <<
510 opp-peak-kBps = <21880 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-979200000 { <<
514 opp-hz = /bits/ 64 <97 <<
515 opp-peak-kBps = <21880 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1056000000 { <<
519 opp-hz = /bits/ 64 <10 <<
520 opp-peak-kBps = <30720 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1132800000 { <<
524 opp-hz = /bits/ 64 <11 <<
525 opp-peak-kBps = <30720 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1209600000 { <<
529 opp-hz = /bits/ 64 <12 <<
530 opp-peak-kBps = <40680 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1286400000 { <<
534 opp-hz = /bits/ 64 <12 <<
535 opp-peak-kBps = <40680 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-1363200000 { <<
539 opp-hz = /bits/ 64 <13 <<
540 opp-peak-kBps = <40680 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-1459200000 { <<
544 opp-hz = /bits/ 64 <14 <<
545 opp-peak-kBps = <40680 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-1536000000 { <<
549 opp-hz = /bits/ 64 <15 <<
550 opp-peak-kBps = <54120 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-1612800000 { <<
554 opp-hz = /bits/ 64 <16 <<
555 opp-peak-kBps = <54120 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-1689600000 { <<
559 opp-hz = /bits/ 64 <16 <<
560 opp-peak-kBps = <54120 <<
561 }; <<
562 <<
563 cpu4_opp19: opp-1766400000 { <<
564 opp-hz = /bits/ 64 <17 <<
565 opp-peak-kBps = <62200 <<
566 }; <<
567 <<
568 cpu4_opp20: opp-1843200000 { <<
569 opp-hz = /bits/ 64 <18 <<
570 opp-peak-kBps = <62200 <<
571 }; <<
572 <<
573 cpu4_opp21: opp-1920000000 { <<
574 opp-hz = /bits/ 64 <19 <<
575 opp-peak-kBps = <72160 <<
576 }; <<
577 <<
578 cpu4_opp22: opp-1996800000 { <<
579 opp-hz = /bits/ 64 <19 <<
580 opp-peak-kBps = <72160 <<
581 }; <<
582 <<
583 cpu4_opp23: opp-2092800000 { <<
584 opp-hz = /bits/ 64 <20 <<
585 opp-peak-kBps = <72160 <<
586 }; <<
587 <<
588 cpu4_opp24: opp-2169600000 { <<
589 opp-hz = /bits/ 64 <21 <<
590 opp-peak-kBps = <72160 <<
591 }; <<
592 <<
593 cpu4_opp25: opp-2246400000 { <<
594 opp-hz = /bits/ 64 <22 <<
595 opp-peak-kBps = <72160 <<
596 }; <<
597 <<
598 cpu4_opp26: opp-2323200000 { <<
599 opp-hz = /bits/ 64 <23 <<
600 opp-peak-kBps = <72160 <<
601 }; <<
602 <<
603 cpu4_opp27: opp-2400000000 { <<
604 opp-hz = /bits/ 64 <24 <<
605 opp-peak-kBps = <72160 <<
606 }; <<
607 <<
608 cpu4_opp28: opp-2476800000 { <<
609 opp-hz = /bits/ 64 <24 <<
610 opp-peak-kBps = <72160 <<
611 }; <<
612 <<
613 cpu4_opp29: opp-2553600000 { <<
614 opp-hz = /bits/ 64 <25 <<
615 opp-peak-kBps = <72160 <<
616 }; <<
617 <<
618 cpu4_opp30: opp-2649600000 { <<
619 opp-hz = /bits/ 64 <26 <<
620 opp-peak-kBps = <72160 <<
621 }; <<
622 <<
623 cpu4_opp31: opp-2745600000 { <<
624 opp-hz = /bits/ 64 <27 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu4_opp32: opp-2803200000 { <<
629 opp-hz = /bits/ 64 <28 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 }; <<
633 <<
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 434 pmu {
712 compatible = "arm,armv8-pmuv3" 435 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 437 };
715 438
716 psci: psci { !! 439 timer {
717 compatible = "arm,psci-1.0"; !! 440 compatible = "arm,armv8-timer";
718 method = "smc"; !! 441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 445 };
773 446
774 reserved-memory { !! 447 clocks {
775 #address-cells = <2>; !! 448 xo_board: xo-board {
776 #size-cells = <2>; !! 449 compatible = "fixed-clock";
777 ranges; !! 450 #clock-cells = <0>;
778 !! 451 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 452 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 453 };
885 454
886 mdata_mem: mpss-metadata { !! 455 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 456 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 457 #clock-cells = <0>;
889 no-map; !! 458 clock-frequency = <32764>;
890 }; 459 };
>> 460 };
891 461
892 fastrpc_mem: fastrpc { !! 462 firmware {
893 compatible = "shared-d !! 463 scm {
894 alloc-ranges = <0x0 0x !! 464 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 465 };
899 }; 466 };
900 467
901 adsp_pas: remoteproc-adsp { 468 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 469 compatible = "qcom,sdm845-adsp-pas";
903 470
904 interrupts-extended = <&intc G 471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 476 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 477 "handover", "stop-ack";
911 478
912 clocks = <&rpmhcc RPMH_CXO_CLK 479 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 480 clock-names = "xo";
914 481
915 memory-region = <&adsp_mem>; 482 memory-region = <&adsp_mem>;
916 483
917 qcom,qmp = <&aoss_qmp>; <<
918 <<
919 qcom,smem-states = <&adsp_smp2 484 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 485 qcom,smem-state-names = "stop";
921 486
922 status = "disabled"; 487 status = "disabled";
923 488
924 glink-edge { 489 glink-edge {
925 interrupts = <GIC_SPI 490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 491 label = "lpass";
927 qcom,remote-pid = <2>; 492 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 493 mboxes = <&apss_shared 8>;
929 <<
930 apr { <<
931 compatible = " <<
932 qcom,glink-cha <<
933 qcom,domain = <<
934 #address-cells <<
935 #size-cells = <<
936 qcom,intents = <<
937 <<
938 service@3 { <<
939 reg = <<
940 compat <<
941 qcom,p <<
942 }; <<
943 <<
944 q6afe: service <<
945 compat <<
946 reg = <<
947 qcom,p <<
948 q6afed <<
949 <<
950 <<
951 <<
952 <<
953 }; <<
954 }; <<
955 <<
956 q6asm: service <<
957 compat <<
958 reg = <<
959 qcom,p <<
960 q6asmd <<
961 <<
962 <<
963 <<
964 <<
965 <<
966 }; <<
967 }; <<
968 <<
969 q6adm: service <<
970 compat <<
971 reg = <<
972 qcom,p <<
973 q6rout <<
974 <<
975 <<
976 }; <<
977 }; <<
978 }; <<
979 <<
980 fastrpc { 494 fastrpc {
981 compatible = " 495 compatible = "qcom,fastrpc";
982 qcom,glink-cha 496 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 497 label = "adsp";
984 qcom,non-secur <<
985 #address-cells 498 #address-cells = <1>;
986 #size-cells = 499 #size-cells = <0>;
987 500
988 compute-cb@3 { 501 compute-cb@3 {
989 compat 502 compatible = "qcom,fastrpc-compute-cb";
990 reg = 503 reg = <3>;
991 iommus 504 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 505 };
993 506
994 compute-cb@4 { 507 compute-cb@4 {
995 compat 508 compatible = "qcom,fastrpc-compute-cb";
996 reg = 509 reg = <4>;
997 iommus 510 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 511 };
999 }; 512 };
1000 }; 513 };
1001 }; 514 };
1002 515
1003 cdsp_pas: remoteproc-cdsp { 516 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 517 compatible = "qcom,sdm845-cdsp-pas";
1005 518
1006 interrupts-extended = <&intc 519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 524 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 525 "handover", "stop-ack";
1013 526
1014 clocks = <&rpmhcc RPMH_CXO_CL 527 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 528 clock-names = "xo";
1016 529
1017 memory-region = <&cdsp_mem>; 530 memory-region = <&cdsp_mem>;
1018 531
1019 qcom,qmp = <&aoss_qmp>; <<
1020 <<
1021 qcom,smem-states = <&cdsp_smp 532 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 533 qcom,smem-state-names = "stop";
1023 534
1024 status = "disabled"; 535 status = "disabled";
1025 536
1026 glink-edge { 537 glink-edge {
1027 interrupts = <GIC_SPI 538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 539 label = "turing";
1029 qcom,remote-pid = <5> 540 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 541 mboxes = <&apss_shared 4>;
1031 fastrpc { 542 fastrpc {
1032 compatible = 543 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 544 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 545 label = "cdsp";
1035 qcom,non-secu <<
1036 #address-cell 546 #address-cells = <1>;
1037 #size-cells = 547 #size-cells = <0>;
1038 548
1039 compute-cb@1 549 compute-cb@1 {
1040 compa 550 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 551 reg = <1>;
1042 iommu 552 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 553 };
1044 554
1045 compute-cb@2 555 compute-cb@2 {
1046 compa 556 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 557 reg = <2>;
1048 iommu 558 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 559 };
1050 560
1051 compute-cb@3 561 compute-cb@3 {
1052 compa 562 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 563 reg = <3>;
1054 iommu 564 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 565 };
1056 566
1057 compute-cb@4 567 compute-cb@4 {
1058 compa 568 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 569 reg = <4>;
1060 iommu 570 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 571 };
1062 572
1063 compute-cb@5 573 compute-cb@5 {
1064 compa 574 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 575 reg = <5>;
1066 iommu 576 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 577 };
1068 578
1069 compute-cb@6 579 compute-cb@6 {
1070 compa 580 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 581 reg = <6>;
1072 iommu 582 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 583 };
1074 584
1075 compute-cb@7 585 compute-cb@7 {
1076 compa 586 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 587 reg = <7>;
1078 iommu 588 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 589 };
1080 590
1081 compute-cb@8 591 compute-cb@8 {
1082 compa 592 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 593 reg = <8>;
1084 iommu 594 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 595 };
1086 }; 596 };
1087 }; 597 };
1088 }; 598 };
1089 599
>> 600 tcsr_mutex: hwlock {
>> 601 compatible = "qcom,tcsr-mutex";
>> 602 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 603 #hwlock-cells = <1>;
>> 604 };
>> 605
>> 606 smem {
>> 607 compatible = "qcom,smem";
>> 608 memory-region = <&smem_mem>;
>> 609 hwlocks = <&tcsr_mutex 3>;
>> 610 };
>> 611
1090 smp2p-cdsp { 612 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 613 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 614 qcom,smem = <94>, <432>;
1093 615
1094 interrupts = <GIC_SPI 576 IRQ 616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 617
1096 mboxes = <&apss_shared 6>; 618 mboxes = <&apss_shared 6>;
1097 619
1098 qcom,local-pid = <0>; 620 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 621 qcom,remote-pid = <5>;
1100 622
1101 cdsp_smp2p_out: master-kernel 623 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 624 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 625 #qcom,smem-state-cells = <1>;
1104 }; 626 };
1105 627
1106 cdsp_smp2p_in: slave-kernel { 628 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 629 qcom,entry-name = "slave-kernel";
1108 630
1109 interrupt-controller; 631 interrupt-controller;
1110 #interrupt-cells = <2 632 #interrupt-cells = <2>;
1111 }; 633 };
1112 }; 634 };
1113 635
1114 smp2p-lpass { 636 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 637 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 638 qcom,smem = <443>, <429>;
1117 639
1118 interrupts = <GIC_SPI 158 IRQ 640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 641
1120 mboxes = <&apss_shared 10>; 642 mboxes = <&apss_shared 10>;
1121 643
1122 qcom,local-pid = <0>; 644 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 645 qcom,remote-pid = <2>;
1124 646
1125 adsp_smp2p_out: master-kernel 647 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 648 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 649 #qcom,smem-state-cells = <1>;
1128 }; 650 };
1129 651
1130 adsp_smp2p_in: slave-kernel { 652 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 653 qcom,entry-name = "slave-kernel";
1132 654
1133 interrupt-controller; 655 interrupt-controller;
1134 #interrupt-cells = <2 656 #interrupt-cells = <2>;
1135 }; 657 };
1136 }; 658 };
1137 659
1138 smp2p-mpss { 660 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 661 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 662 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 664 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 665 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 666 qcom,remote-pid = <1>;
1145 667
1146 modem_smp2p_out: master-kerne 668 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 669 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 670 #qcom,smem-state-cells = <1>;
1149 }; 671 };
1150 672
1151 modem_smp2p_in: slave-kernel 673 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 674 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 675 interrupt-controller;
1154 #interrupt-cells = <2 676 #interrupt-cells = <2>;
1155 }; 677 };
1156 <<
1157 ipa_smp2p_out: ipa-ap-to-mode <<
1158 qcom,entry-name = "ip <<
1159 #qcom,smem-state-cell <<
1160 }; <<
1161 <<
1162 ipa_smp2p_in: ipa-modem-to-ap <<
1163 qcom,entry-name = "ip <<
1164 interrupt-controller; <<
1165 #interrupt-cells = <2 <<
1166 }; <<
1167 }; 678 };
1168 679
1169 smp2p-slpi { 680 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 681 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 682 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 684 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 685 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 686 qcom,remote-pid = <3>;
1176 687
1177 slpi_smp2p_out: master-kernel 688 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 689 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 690 #qcom,smem-state-cells = <1>;
1180 }; 691 };
1181 692
1182 slpi_smp2p_in: slave-kernel { 693 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 694 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 695 interrupt-controller;
1185 #interrupt-cells = <2 696 #interrupt-cells = <2>;
1186 }; 697 };
1187 }; 698 };
1188 699
>> 700 psci {
>> 701 compatible = "arm,psci-1.0";
>> 702 method = "smc";
>> 703 };
>> 704
1189 soc: soc@0 { 705 soc: soc@0 {
1190 #address-cells = <2>; 706 #address-cells = <2>;
1191 #size-cells = <2>; 707 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 708 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 709 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 710 compatible = "simple-bus";
1195 711
1196 gcc: clock-controller@100000 712 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 713 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 714 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM <<
1200 <&rpmhcc RPM <<
1201 <&sleep_clk> <<
1202 <&pcie0_phy> <<
1203 <&pcie1_phy> <<
1204 clock-names = "bi_tcx <<
1205 "bi_tcx <<
1206 "sleep_ <<
1207 "pcie_0 <<
1208 "pcie_1 <<
1209 #clock-cells = <1>; 715 #clock-cells = <1>;
1210 #reset-cells = <1>; 716 #reset-cells = <1>;
1211 #power-domain-cells = 717 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 718 };
1214 719
1215 qfprom@784000 { 720 qfprom@784000 {
1216 compatible = "qcom,sd !! 721 compatible = "qcom,qfprom";
1217 reg = <0 0x00784000 0 722 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 723 #address-cells = <1>;
1219 #size-cells = <1>; 724 #size-cells = <1>;
1220 725
1221 qusb2p_hstx_trim: hst 726 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 727 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 728 bits = <1 4>;
1224 }; 729 };
1225 730
1226 qusb2s_hstx_trim: hst 731 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 732 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 733 bits = <6 4>;
1229 }; 734 };
1230 }; 735 };
1231 736
1232 rng: rng@793000 { 737 rng: rng@793000 {
1233 compatible = "qcom,pr 738 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 739 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 740 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 741 clock-names = "core";
1237 }; 742 };
1238 743
1239 gpi_dma0: dma-controller@8000 <<
1240 #dma-cells = <3>; <<
1241 compatible = "qcom,sd <<
1242 reg = <0 0x00800000 0 <<
1243 interrupts = <GIC_SPI <<
1244 <GIC_SPI <<
1245 <GIC_SPI <<
1246 <GIC_SPI <<
1247 <GIC_SPI <<
1248 <GIC_SPI <<
1249 <GIC_SPI <<
1250 <GIC_SPI <<
1251 <GIC_SPI <<
1252 <GIC_SPI <<
1253 <GIC_SPI <<
1254 <GIC_SPI <<
1255 <GIC_SPI <<
1256 dma-channels = <13>; <<
1257 dma-channel-mask = <0 <<
1258 iommus = <&apps_smmu <<
1259 status = "disabled"; <<
1260 }; <<
1261 <<
1262 qupv3_id_0: geniqup@8c0000 { 744 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 745 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 746 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 747 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 748 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 749 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu <<
1269 #address-cells = <2>; 750 #address-cells = <2>;
1270 #size-cells = <2>; 751 #size-cells = <2>;
1271 ranges; 752 ranges;
1272 interconnects = <&agg <<
1273 interconnect-names = <<
1274 status = "disabled"; 753 status = "disabled";
1275 754
1276 i2c0: i2c@880000 { 755 i2c0: i2c@880000 {
1277 compatible = 756 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 757 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 758 clock-names = "se";
1280 clocks = <&gc 759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 760 pinctrl-names = "default";
1282 pinctrl-0 = < 761 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 763 #address-cells = <1>;
1285 #size-cells = 764 #size-cells = <0>;
1286 power-domains <<
1287 operating-poi <<
1288 interconnects <<
1289 <<
1290 <<
1291 interconnect- <<
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 765 status = "disabled";
1296 }; 766 };
1297 767
1298 spi0: spi@880000 { 768 spi0: spi@880000 {
1299 compatible = 769 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 770 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 771 clock-names = "se";
1302 clocks = <&gc 772 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 773 pinctrl-names = "default";
1304 pinctrl-0 = < 774 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 775 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 776 #address-cells = <1>;
1307 #size-cells = 777 #size-cells = <0>;
1308 interconnects <<
1309 <<
1310 interconnect- <<
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 778 status = "disabled";
1315 }; 779 };
1316 780
1317 uart0: serial@880000 781 uart0: serial@880000 {
1318 compatible = 782 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 783 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 784 clock-names = "se";
1321 clocks = <&gc 785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 786 pinctrl-names = "default";
1323 pinctrl-0 = < 787 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains <<
1326 operating-poi <<
1327 interconnects <<
1328 <<
1329 interconnect- <<
1330 status = "dis 789 status = "disabled";
1331 }; 790 };
1332 791
1333 i2c1: i2c@884000 { 792 i2c1: i2c@884000 {
1334 compatible = 793 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 794 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 795 clock-names = "se";
1337 clocks = <&gc 796 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 797 pinctrl-names = "default";
1339 pinctrl-0 = < 798 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 799 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 800 #address-cells = <1>;
1342 #size-cells = 801 #size-cells = <0>;
1343 power-domains <<
1344 operating-poi <<
1345 interconnects <<
1346 <<
1347 <<
1348 interconnect- <<
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 802 status = "disabled";
1353 }; 803 };
1354 804
1355 spi1: spi@884000 { 805 spi1: spi@884000 {
1356 compatible = 806 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 807 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 808 clock-names = "se";
1359 clocks = <&gc 809 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 810 pinctrl-names = "default";
1361 pinctrl-0 = < 811 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 812 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 813 #address-cells = <1>;
1364 #size-cells = 814 #size-cells = <0>;
1365 interconnects <<
1366 <<
1367 interconnect- <<
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 815 status = "disabled";
1372 }; 816 };
1373 817
1374 uart1: serial@884000 818 uart1: serial@884000 {
1375 compatible = 819 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 820 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 821 clock-names = "se";
1378 clocks = <&gc 822 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 823 pinctrl-names = "default";
1380 pinctrl-0 = < 824 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 825 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains <<
1383 operating-poi <<
1384 interconnects <<
1385 <<
1386 interconnect- <<
1387 status = "dis 826 status = "disabled";
1388 }; 827 };
1389 828
1390 i2c2: i2c@888000 { 829 i2c2: i2c@888000 {
1391 compatible = 830 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 831 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 832 clock-names = "se";
1394 clocks = <&gc 833 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 834 pinctrl-names = "default";
1396 pinctrl-0 = < 835 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 836 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 837 #address-cells = <1>;
1399 #size-cells = 838 #size-cells = <0>;
1400 power-domains <<
1401 operating-poi <<
1402 interconnects <<
1403 <<
1404 <<
1405 interconnect- <<
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 839 status = "disabled";
1410 }; 840 };
1411 841
1412 spi2: spi@888000 { 842 spi2: spi@888000 {
1413 compatible = 843 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 844 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 845 clock-names = "se";
1416 clocks = <&gc 846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 847 pinctrl-names = "default";
1418 pinctrl-0 = < 848 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 849 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 850 #address-cells = <1>;
1421 #size-cells = 851 #size-cells = <0>;
1422 interconnects <<
1423 <<
1424 interconnect- <<
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 852 status = "disabled";
1429 }; 853 };
1430 854
1431 uart2: serial@888000 855 uart2: serial@888000 {
1432 compatible = 856 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 857 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 858 clock-names = "se";
1435 clocks = <&gc 859 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 860 pinctrl-names = "default";
1437 pinctrl-0 = < 861 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 862 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains <<
1440 operating-poi <<
1441 interconnects <<
1442 <<
1443 interconnect- <<
1444 status = "dis 863 status = "disabled";
1445 }; 864 };
1446 865
1447 i2c3: i2c@88c000 { 866 i2c3: i2c@88c000 {
1448 compatible = 867 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 868 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 869 clock-names = "se";
1451 clocks = <&gc 870 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 871 pinctrl-names = "default";
1453 pinctrl-0 = < 872 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 873 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 874 #address-cells = <1>;
1456 #size-cells = 875 #size-cells = <0>;
1457 power-domains <<
1458 operating-poi <<
1459 interconnects <<
1460 <<
1461 <<
1462 interconnect- <<
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 876 status = "disabled";
1467 }; 877 };
1468 878
1469 spi3: spi@88c000 { 879 spi3: spi@88c000 {
1470 compatible = 880 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 881 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 882 clock-names = "se";
1473 clocks = <&gc 883 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 884 pinctrl-names = "default";
1475 pinctrl-0 = < 885 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 886 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 887 #address-cells = <1>;
1478 #size-cells = 888 #size-cells = <0>;
1479 interconnects <<
1480 <<
1481 interconnect- <<
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 889 status = "disabled";
1486 }; 890 };
1487 891
1488 uart3: serial@88c000 892 uart3: serial@88c000 {
1489 compatible = 893 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 894 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 895 clock-names = "se";
1492 clocks = <&gc 896 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 897 pinctrl-names = "default";
1494 pinctrl-0 = < 898 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 899 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains <<
1497 operating-poi <<
1498 interconnects <<
1499 <<
1500 interconnect- <<
1501 status = "dis 900 status = "disabled";
1502 }; 901 };
1503 902
1504 i2c4: i2c@890000 { 903 i2c4: i2c@890000 {
1505 compatible = 904 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 905 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 906 clock-names = "se";
1508 clocks = <&gc 907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 908 pinctrl-names = "default";
1510 pinctrl-0 = < 909 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 910 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 911 #address-cells = <1>;
1513 #size-cells = 912 #size-cells = <0>;
1514 power-domains <<
1515 operating-poi <<
1516 interconnects <<
1517 <<
1518 <<
1519 interconnect- <<
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 913 status = "disabled";
1524 }; 914 };
1525 915
1526 spi4: spi@890000 { 916 spi4: spi@890000 {
1527 compatible = 917 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 918 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 919 clock-names = "se";
1530 clocks = <&gc 920 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 921 pinctrl-names = "default";
1532 pinctrl-0 = < 922 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 923 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 924 #address-cells = <1>;
1535 #size-cells = 925 #size-cells = <0>;
1536 interconnects <<
1537 <<
1538 interconnect- <<
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 926 status = "disabled";
1543 }; 927 };
1544 928
1545 uart4: serial@890000 929 uart4: serial@890000 {
1546 compatible = 930 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 931 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 932 clock-names = "se";
1549 clocks = <&gc 933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 934 pinctrl-names = "default";
1551 pinctrl-0 = < 935 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 936 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains <<
1554 operating-poi <<
1555 interconnects <<
1556 <<
1557 interconnect- <<
1558 status = "dis 937 status = "disabled";
1559 }; 938 };
1560 939
1561 i2c5: i2c@894000 { 940 i2c5: i2c@894000 {
1562 compatible = 941 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 942 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 943 clock-names = "se";
1565 clocks = <&gc 944 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 945 pinctrl-names = "default";
1567 pinctrl-0 = < 946 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 947 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 948 #address-cells = <1>;
1570 #size-cells = 949 #size-cells = <0>;
1571 power-domains <<
1572 operating-poi <<
1573 interconnects <<
1574 <<
1575 <<
1576 interconnect- <<
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 950 status = "disabled";
1581 }; 951 };
1582 952
1583 spi5: spi@894000 { 953 spi5: spi@894000 {
1584 compatible = 954 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 955 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 956 clock-names = "se";
1587 clocks = <&gc 957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 958 pinctrl-names = "default";
1589 pinctrl-0 = < 959 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 960 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 961 #address-cells = <1>;
1592 #size-cells = 962 #size-cells = <0>;
1593 interconnects <<
1594 <<
1595 interconnect- <<
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 963 status = "disabled";
1600 }; 964 };
1601 965
1602 uart5: serial@894000 966 uart5: serial@894000 {
1603 compatible = 967 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 968 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 969 clock-names = "se";
1606 clocks = <&gc 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 971 pinctrl-names = "default";
1608 pinctrl-0 = < 972 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 973 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains <<
1611 operating-poi <<
1612 interconnects <<
1613 <<
1614 interconnect- <<
1615 status = "dis 974 status = "disabled";
1616 }; 975 };
1617 976
1618 i2c6: i2c@898000 { 977 i2c6: i2c@898000 {
1619 compatible = 978 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 979 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 980 clock-names = "se";
1622 clocks = <&gc 981 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 982 pinctrl-names = "default";
1624 pinctrl-0 = < 983 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 984 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 985 #address-cells = <1>;
1627 #size-cells = 986 #size-cells = <0>;
1628 power-domains <<
1629 operating-poi <<
1630 interconnects <<
1631 <<
1632 <<
1633 interconnect- <<
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 987 status = "disabled";
1638 }; 988 };
1639 989
1640 spi6: spi@898000 { 990 spi6: spi@898000 {
1641 compatible = 991 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 992 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 993 clock-names = "se";
1644 clocks = <&gc 994 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 995 pinctrl-names = "default";
1646 pinctrl-0 = < 996 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 997 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 998 #address-cells = <1>;
1649 #size-cells = 999 #size-cells = <0>;
1650 interconnects <<
1651 <<
1652 interconnect- <<
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 1000 status = "disabled";
1657 }; 1001 };
1658 1002
1659 uart6: serial@898000 1003 uart6: serial@898000 {
1660 compatible = 1004 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1005 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1006 clock-names = "se";
1663 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1008 pinctrl-names = "default";
1665 pinctrl-0 = < 1009 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1010 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains <<
1668 operating-poi <<
1669 interconnects <<
1670 <<
1671 interconnect- <<
1672 status = "dis 1011 status = "disabled";
1673 }; 1012 };
1674 1013
1675 i2c7: i2c@89c000 { 1014 i2c7: i2c@89c000 {
1676 compatible = 1015 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1016 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1017 clock-names = "se";
1679 clocks = <&gc 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1019 pinctrl-names = "default";
1681 pinctrl-0 = < 1020 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1021 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1022 #address-cells = <1>;
1684 #size-cells = 1023 #size-cells = <0>;
1685 power-domains <<
1686 operating-poi <<
1687 status = "dis 1024 status = "disabled";
1688 }; 1025 };
1689 1026
1690 spi7: spi@89c000 { 1027 spi7: spi@89c000 {
1691 compatible = 1028 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1029 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1030 clock-names = "se";
1694 clocks = <&gc 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1032 pinctrl-names = "default";
1696 pinctrl-0 = < 1033 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1034 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1035 #address-cells = <1>;
1699 #size-cells = 1036 #size-cells = <0>;
1700 interconnects <<
1701 <<
1702 interconnect- <<
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 1037 status = "disabled";
1707 }; 1038 };
1708 1039
1709 uart7: serial@89c000 1040 uart7: serial@89c000 {
1710 compatible = 1041 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1042 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1043 clock-names = "se";
1713 clocks = <&gc 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1045 pinctrl-names = "default";
1715 pinctrl-0 = < 1046 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains <<
1718 operating-poi <<
1719 interconnects <<
1720 <<
1721 interconnect- <<
1722 status = "dis 1048 status = "disabled";
1723 }; 1049 };
1724 }; 1050 };
1725 1051
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 1052 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1053 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1054 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1055 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu <<
1756 #address-cells = <2>; 1058 #address-cells = <2>;
1757 #size-cells = <2>; 1059 #size-cells = <2>;
1758 ranges; 1060 ranges;
1759 interconnects = <&agg <<
1760 interconnect-names = <<
1761 status = "disabled"; 1061 status = "disabled";
1762 1062
1763 i2c8: i2c@a80000 { 1063 i2c8: i2c@a80000 {
1764 compatible = 1064 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1065 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1066 clock-names = "se";
1767 clocks = <&gc 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1068 pinctrl-names = "default";
1769 pinctrl-0 = < 1069 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1070 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1071 #address-cells = <1>;
1772 #size-cells = 1072 #size-cells = <0>;
1773 power-domains <<
1774 operating-poi <<
1775 interconnects <<
1776 <<
1777 <<
1778 interconnect- <<
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 1073 status = "disabled";
1783 }; 1074 };
1784 1075
1785 spi8: spi@a80000 { 1076 spi8: spi@a80000 {
1786 compatible = 1077 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1078 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1079 clock-names = "se";
1789 clocks = <&gc 1080 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1081 pinctrl-names = "default";
1791 pinctrl-0 = < 1082 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1084 #address-cells = <1>;
1794 #size-cells = 1085 #size-cells = <0>;
1795 interconnects <<
1796 <<
1797 interconnect- <<
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 1086 status = "disabled";
1802 }; 1087 };
1803 1088
1804 uart8: serial@a80000 1089 uart8: serial@a80000 {
1805 compatible = 1090 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1091 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1092 clock-names = "se";
1808 clocks = <&gc 1093 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1094 pinctrl-names = "default";
1810 pinctrl-0 = < 1095 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1096 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains <<
1813 operating-poi <<
1814 interconnects <<
1815 <<
1816 interconnect- <<
1817 status = "dis 1097 status = "disabled";
1818 }; 1098 };
1819 1099
1820 i2c9: i2c@a84000 { 1100 i2c9: i2c@a84000 {
1821 compatible = 1101 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1102 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1103 clock-names = "se";
1824 clocks = <&gc 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1105 pinctrl-names = "default";
1826 pinctrl-0 = < 1106 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1107 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1108 #address-cells = <1>;
1829 #size-cells = 1109 #size-cells = <0>;
1830 power-domains <<
1831 operating-poi <<
1832 interconnects <<
1833 <<
1834 <<
1835 interconnect- <<
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 1110 status = "disabled";
1840 }; 1111 };
1841 1112
1842 spi9: spi@a84000 { 1113 spi9: spi@a84000 {
1843 compatible = 1114 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1115 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1116 clock-names = "se";
1846 clocks = <&gc 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1118 pinctrl-names = "default";
1848 pinctrl-0 = < 1119 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1121 #address-cells = <1>;
1851 #size-cells = 1122 #size-cells = <0>;
1852 interconnects <<
1853 <<
1854 interconnect- <<
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 1123 status = "disabled";
1859 }; 1124 };
1860 1125
1861 uart9: serial@a84000 1126 uart9: serial@a84000 {
1862 compatible = 1127 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1128 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1129 clock-names = "se";
1865 clocks = <&gc 1130 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1131 pinctrl-names = "default";
1867 pinctrl-0 = < 1132 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1133 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains <<
1870 operating-poi <<
1871 interconnects <<
1872 <<
1873 interconnect- <<
1874 status = "dis 1134 status = "disabled";
1875 }; 1135 };
1876 1136
1877 i2c10: i2c@a88000 { 1137 i2c10: i2c@a88000 {
1878 compatible = 1138 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1139 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1140 clock-names = "se";
1881 clocks = <&gc 1141 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1142 pinctrl-names = "default";
1883 pinctrl-0 = < 1143 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1144 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1145 #address-cells = <1>;
1886 #size-cells = 1146 #size-cells = <0>;
1887 power-domains <<
1888 operating-poi <<
1889 interconnects <<
1890 <<
1891 <<
1892 interconnect- <<
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 1147 status = "disabled";
1897 }; 1148 };
1898 1149
1899 spi10: spi@a88000 { 1150 spi10: spi@a88000 {
1900 compatible = 1151 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1152 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1153 clock-names = "se";
1903 clocks = <&gc 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1155 pinctrl-names = "default";
1905 pinctrl-0 = < 1156 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1158 #address-cells = <1>;
1908 #size-cells = 1159 #size-cells = <0>;
1909 interconnects <<
1910 <<
1911 interconnect- <<
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1160 status = "disabled";
1916 }; 1161 };
1917 1162
1918 uart10: serial@a88000 1163 uart10: serial@a88000 {
1919 compatible = 1164 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1165 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1166 clock-names = "se";
1922 clocks = <&gc 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1168 pinctrl-names = "default";
1924 pinctrl-0 = < 1169 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains <<
1927 operating-poi <<
1928 interconnects <<
1929 <<
1930 interconnect- <<
1931 status = "dis 1171 status = "disabled";
1932 }; 1172 };
1933 1173
1934 i2c11: i2c@a8c000 { 1174 i2c11: i2c@a8c000 {
1935 compatible = 1175 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1176 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1177 clock-names = "se";
1938 clocks = <&gc 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1179 pinctrl-names = "default";
1940 pinctrl-0 = < 1180 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1181 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1182 #address-cells = <1>;
1943 #size-cells = 1183 #size-cells = <0>;
1944 power-domains <<
1945 operating-poi <<
1946 interconnects <<
1947 <<
1948 <<
1949 interconnect- <<
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1184 status = "disabled";
1954 }; 1185 };
1955 1186
1956 spi11: spi@a8c000 { 1187 spi11: spi@a8c000 {
1957 compatible = 1188 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1189 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1190 clock-names = "se";
1960 clocks = <&gc 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1192 pinctrl-names = "default";
1962 pinctrl-0 = < 1193 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1194 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1195 #address-cells = <1>;
1965 #size-cells = 1196 #size-cells = <0>;
1966 interconnects <<
1967 <<
1968 interconnect- <<
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1197 status = "disabled";
1973 }; 1198 };
1974 1199
1975 uart11: serial@a8c000 1200 uart11: serial@a8c000 {
1976 compatible = 1201 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1202 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1203 clock-names = "se";
1979 clocks = <&gc 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1205 pinctrl-names = "default";
1981 pinctrl-0 = < 1206 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1207 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains <<
1984 operating-poi <<
1985 interconnects <<
1986 <<
1987 interconnect- <<
1988 status = "dis 1208 status = "disabled";
1989 }; 1209 };
1990 1210
1991 i2c12: i2c@a90000 { 1211 i2c12: i2c@a90000 {
1992 compatible = 1212 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1213 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1214 clock-names = "se";
1995 clocks = <&gc 1215 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1216 pinctrl-names = "default";
1997 pinctrl-0 = < 1217 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1218 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1219 #address-cells = <1>;
2000 #size-cells = 1220 #size-cells = <0>;
2001 power-domains <<
2002 operating-poi <<
2003 interconnects <<
2004 <<
2005 <<
2006 interconnect- <<
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1221 status = "disabled";
2011 }; 1222 };
2012 1223
2013 spi12: spi@a90000 { 1224 spi12: spi@a90000 {
2014 compatible = 1225 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1226 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1227 clock-names = "se";
2017 clocks = <&gc 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1229 pinctrl-names = "default";
2019 pinctrl-0 = < 1230 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1231 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1232 #address-cells = <1>;
2022 #size-cells = 1233 #size-cells = <0>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1234 status = "disabled";
2030 }; 1235 };
2031 1236
2032 uart12: serial@a90000 1237 uart12: serial@a90000 {
2033 compatible = 1238 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1239 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1240 clock-names = "se";
2036 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1242 pinctrl-names = "default";
2038 pinctrl-0 = < 1243 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1244 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains <<
2041 operating-poi <<
2042 interconnects <<
2043 <<
2044 interconnect- <<
2045 status = "dis 1245 status = "disabled";
2046 }; 1246 };
2047 1247
2048 i2c13: i2c@a94000 { 1248 i2c13: i2c@a94000 {
2049 compatible = 1249 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1250 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1251 clock-names = "se";
2052 clocks = <&gc 1252 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1253 pinctrl-names = "default";
2054 pinctrl-0 = < 1254 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1255 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1256 #address-cells = <1>;
2057 #size-cells = 1257 #size-cells = <0>;
2058 power-domains <<
2059 operating-poi <<
2060 interconnects <<
2061 <<
2062 <<
2063 interconnect- <<
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1258 status = "disabled";
2068 }; 1259 };
2069 1260
2070 spi13: spi@a94000 { 1261 spi13: spi@a94000 {
2071 compatible = 1262 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1263 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1264 clock-names = "se";
2074 clocks = <&gc 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1266 pinctrl-names = "default";
2076 pinctrl-0 = < 1267 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1268 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1269 #address-cells = <1>;
2079 #size-cells = 1270 #size-cells = <0>;
2080 interconnects <<
2081 <<
2082 interconnect- <<
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1271 status = "disabled";
2087 }; 1272 };
2088 1273
2089 uart13: serial@a94000 1274 uart13: serial@a94000 {
2090 compatible = 1275 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1276 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1277 clock-names = "se";
2093 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1279 pinctrl-names = "default";
2095 pinctrl-0 = < 1280 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1281 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains <<
2098 operating-poi <<
2099 interconnects <<
2100 <<
2101 interconnect- <<
2102 status = "dis 1282 status = "disabled";
2103 }; 1283 };
2104 1284
2105 i2c14: i2c@a98000 { 1285 i2c14: i2c@a98000 {
2106 compatible = 1286 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1287 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1288 clock-names = "se";
2109 clocks = <&gc 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1290 pinctrl-names = "default";
2111 pinctrl-0 = < 1291 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1292 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1293 #address-cells = <1>;
2114 #size-cells = 1294 #size-cells = <0>;
2115 power-domains <<
2116 operating-poi <<
2117 interconnects <<
2118 <<
2119 <<
2120 interconnect- <<
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1295 status = "disabled";
2125 }; 1296 };
2126 1297
2127 spi14: spi@a98000 { 1298 spi14: spi@a98000 {
2128 compatible = 1299 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1300 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1301 clock-names = "se";
2131 clocks = <&gc 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1303 pinctrl-names = "default";
2133 pinctrl-0 = < 1304 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1305 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1306 #address-cells = <1>;
2136 #size-cells = 1307 #size-cells = <0>;
2137 interconnects <<
2138 <<
2139 interconnect- <<
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1308 status = "disabled";
2144 }; 1309 };
2145 1310
2146 uart14: serial@a98000 1311 uart14: serial@a98000 {
2147 compatible = 1312 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1313 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1314 clock-names = "se";
2150 clocks = <&gc 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1316 pinctrl-names = "default";
2152 pinctrl-0 = < 1317 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1318 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains <<
2155 operating-poi <<
2156 interconnects <<
2157 <<
2158 interconnect- <<
2159 status = "dis 1319 status = "disabled";
2160 }; 1320 };
2161 1321
2162 i2c15: i2c@a9c000 { 1322 i2c15: i2c@a9c000 {
2163 compatible = 1323 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1324 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1325 clock-names = "se";
2166 clocks = <&gc 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1327 pinctrl-names = "default";
2168 pinctrl-0 = < 1328 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1329 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1330 #address-cells = <1>;
2171 #size-cells = 1331 #size-cells = <0>;
2172 power-domains <<
2173 operating-poi <<
2174 status = "dis 1332 status = "disabled";
2175 interconnects <<
2176 <<
2177 <<
2178 interconnect- <<
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1333 };
2183 1334
2184 spi15: spi@a9c000 { 1335 spi15: spi@a9c000 {
2185 compatible = 1336 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1337 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1338 clock-names = "se";
2188 clocks = <&gc 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1340 pinctrl-names = "default";
2190 pinctrl-0 = < 1341 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1342 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1343 #address-cells = <1>;
2193 #size-cells = 1344 #size-cells = <0>;
2194 interconnects <<
2195 <<
2196 interconnect- <<
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1345 status = "disabled";
2201 }; 1346 };
2202 1347
2203 uart15: serial@a9c000 1348 uart15: serial@a9c000 {
2204 compatible = 1349 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1350 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1351 clock-names = "se";
2207 clocks = <&gc 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1353 pinctrl-names = "default";
2209 pinctrl-0 = < 1354 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1355 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains <<
2212 operating-poi <<
2213 interconnects <<
2214 <<
2215 interconnect- <<
2216 status = "dis 1356 status = "disabled";
2217 }; 1357 };
2218 }; 1358 };
2219 1359
2220 llcc: system-cache-controller !! 1360 system-cache-controller@1100000 {
2221 compatible = "qcom,sd 1361 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 1362 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 1363 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 1364 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 1365 };
2229 1366
2230 dma@10a2000 { <<
2231 compatible = "qcom,sd <<
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 <<
2313 <0 0x60000000 0 <<
2314 <0 0x60000f20 0 <<
2315 <0 0x60100000 0 <<
2316 <0 0x01c07000 0 <<
2317 reg-names = "parf", " <<
2318 device_type = "pci"; <<
2319 linux,pci-domain = <0 <<
2320 bus-range = <0x00 0xf <<
2321 num-lanes = <1>; <<
2322 <<
2323 #address-cells = <3>; <<
2324 #size-cells = <2>; <<
2325 <<
2326 ranges = <0x01000000 <<
2327 <0x02000000 <<
2328 <<
2329 interrupts = <GIC_SPI <<
2330 interrupt-names = "ms <<
2331 #interrupt-cells = <1 <<
2332 interrupt-map-mask = <<
2333 interrupt-map = <0 0 <<
2334 <0 0 <<
2335 <0 0 <<
2336 <0 0 <<
2337 <<
2338 clocks = <&gcc GCC_PC <<
2339 <&gcc GCC_PC <<
2340 <&gcc GCC_PC <<
2341 <&gcc GCC_PC <<
2342 <&gcc GCC_PC <<
2343 <&gcc GCC_PC <<
2344 <&gcc GCC_AG <<
2345 clock-names = "pipe", <<
2346 "aux", <<
2347 "cfg", <<
2348 "bus_ma <<
2349 "bus_sl <<
2350 "slave_ <<
2351 "tbu"; <<
2352 <<
2353 iommu-map = <0x0 &a <<
2354 <0x100 &a <<
2355 <0x200 &a <<
2356 <0x300 &a <<
2357 <0x400 &a <<
2358 <0x500 &a <<
2359 <0x600 &a <<
2360 <0x700 &a <<
2361 <0x800 &a <<
2362 <0x900 &a <<
2363 <0xa00 &a <<
2364 <0xb00 &a <<
2365 <0xc00 &a <<
2366 <0xd00 &a <<
2367 <0xe00 &a <<
2368 <0xf00 &a <<
2369 <<
2370 resets = <&gcc GCC_PC <<
2371 reset-names = "pci"; <<
2372 <<
2373 power-domains = <&gcc <<
2374 <<
2375 phys = <&pcie0_phy>; <<
2376 phy-names = "pciephy" <<
2377 <<
2378 status = "disabled"; <<
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; <<
2390 <<
2391 pcie0_phy: phy@1c06000 { <<
2392 compatible = "qcom,sd <<
2393 reg = <0 0x01c06000 0 <<
2394 clocks = <&gcc GCC_PC <<
2395 <&gcc GCC_PC <<
2396 <&gcc GCC_PC <<
2397 <&gcc GCC_PC <<
2398 <&gcc GCC_PC <<
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 <<
2410 resets = <&gcc GCC_PC <<
2411 reset-names = "phy"; <<
2412 <<
2413 assigned-clocks = <&g <<
2414 assigned-clock-rates <<
2415 <<
2416 status = "disabled"; <<
2417 }; <<
2418 <<
2419 pcie1: pcie@1c08000 { <<
2420 compatible = "qcom,pc <<
2421 reg = <0 0x01c08000 0 <<
2422 <0 0x40000000 0 <<
2423 <0 0x40000f20 0 <<
2424 <0 0x40100000 0 <<
2425 <0 0x01c0c000 0 <<
2426 reg-names = "parf", " <<
2427 device_type = "pci"; <<
2428 linux,pci-domain = <1 <<
2429 bus-range = <0x00 0xf <<
2430 num-lanes = <1>; <<
2431 <<
2432 #address-cells = <3>; <<
2433 #size-cells = <2>; <<
2434 <<
2435 ranges = <0x01000000 <<
2436 <0x02000000 <<
2437 <<
2438 interrupts = <GIC_SPI <<
2439 interrupt-names = "ms <<
2440 #interrupt-cells = <1 <<
2441 interrupt-map-mask = <<
2442 interrupt-map = <0 0 <<
2443 <0 0 <<
2444 <0 0 <<
2445 <0 0 <<
2446 <<
2447 clocks = <&gcc GCC_PC <<
2448 <&gcc GCC_PC <<
2449 <&gcc GCC_PC <<
2450 <&gcc GCC_PC <<
2451 <&gcc GCC_PC <<
2452 <&gcc GCC_PC <<
2453 <&gcc GCC_PC <<
2454 <&gcc GCC_AG <<
2455 clock-names = "pipe", <<
2456 "aux", <<
2457 "cfg", <<
2458 "bus_ma <<
2459 "bus_sl <<
2460 "slave_ <<
2461 "ref", <<
2462 "tbu"; <<
2463 <<
2464 assigned-clocks = <&g <<
2465 assigned-clock-rates <<
2466 <<
2467 iommu-map = <0x0 &a <<
2468 <0x100 &a <<
2469 <0x200 &a <<
2470 <0x300 &a <<
2471 <0x400 &a <<
2472 <0x500 &a <<
2473 <0x600 &a <<
2474 <0x700 &a <<
2475 <0x800 &a <<
2476 <0x900 &a <<
2477 <0xa00 &a <<
2478 <0xb00 &a <<
2479 <0xc00 &a <<
2480 <0xd00 &a <<
2481 <0xe00 &a <<
2482 <0xf00 &a <<
2483 <<
2484 resets = <&gcc GCC_PC <<
2485 reset-names = "pci"; <<
2486 <<
2487 power-domains = <&gcc <<
2488 <<
2489 phys = <&pcie1_phy>; <<
2490 phy-names = "pciephy" <<
2491 <<
2492 status = "disabled"; <<
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; <<
2504 <<
2505 pcie1_phy: phy@1c0a000 { <<
2506 compatible = "qcom,sd <<
2507 reg = <0 0x01c0a000 0 <<
2508 clocks = <&gcc GCC_PC <<
2509 <&gcc GCC_PC <<
2510 <&gcc GCC_PC <<
2511 <&gcc GCC_PC <<
2512 <&gcc GCC_PC <<
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 <<
2524 resets = <&gcc GCC_PC <<
2525 reset-names = "phy"; <<
2526 <<
2527 assigned-clocks = <&g <<
2528 assigned-clock-rates <<
2529 <<
2530 status = "disabled"; <<
2531 }; <<
2532 <<
2533 mem_noc: interconnect@1380000 <<
2534 compatible = "qcom,sd <<
2535 reg = <0 0x01380000 0 <<
2536 #interconnect-cells = <<
2537 qcom,bcm-voters = <&a <<
2538 }; <<
2539 <<
2540 dc_noc: interconnect@14e0000 <<
2541 compatible = "qcom,sd <<
2542 reg = <0 0x014e0000 0 <<
2543 #interconnect-cells = <<
2544 qcom,bcm-voters = <&a <<
2545 }; <<
2546 <<
2547 config_noc: interconnect@1500 <<
2548 compatible = "qcom,sd <<
2549 reg = <0 0x01500000 0 <<
2550 #interconnect-cells = <<
2551 qcom,bcm-voters = <&a <<
2552 }; <<
2553 <<
2554 system_noc: interconnect@1620 <<
2555 compatible = "qcom,sd <<
2556 reg = <0 0x01620000 0 <<
2557 #interconnect-cells = <<
2558 qcom,bcm-voters = <&a <<
2559 }; <<
2560 <<
2561 aggre1_noc: interconnect@16e0 <<
2562 compatible = "qcom,sd <<
2563 reg = <0 0x016e0000 0 <<
2564 #interconnect-cells = <<
2565 qcom,bcm-voters = <&a <<
2566 }; <<
2567 <<
2568 aggre2_noc: interconnect@1700 <<
2569 compatible = "qcom,sd <<
2570 reg = <0 0x01700000 0 <<
2571 #interconnect-cells = <<
2572 qcom,bcm-voters = <&a <<
2573 }; <<
2574 <<
2575 mmss_noc: interconnect@174000 <<
2576 compatible = "qcom,sd <<
2577 reg = <0 0x01740000 0 <<
2578 #interconnect-cells = <<
2579 qcom,bcm-voters = <&a <<
2580 }; <<
2581 <<
2582 ufs_mem_hc: ufshc@1d84000 { 1367 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 1368 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 1369 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 !! 1370 reg = <0 0x01d84000 0 0x2500>;
2586 <0 0x01d90000 0 <<
2587 reg-names = "std", "i <<
2588 interrupts = <GIC_SPI 1371 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 1372 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 1373 phy-names = "ufsphy";
2591 lanes-per-direction = 1374 lanes-per-direction = <2>;
2592 power-domains = <&gcc 1375 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 1376 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 1377 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 1378 reset-names = "rst";
2596 1379
2597 iommus = <&apps_smmu 1380 iommus = <&apps_smmu 0x100 0xf>;
2598 1381
2599 clock-names = 1382 clock-names =
2600 "core_clk", 1383 "core_clk",
2601 "bus_aggr_clk 1384 "bus_aggr_clk",
2602 "iface_clk", 1385 "iface_clk",
2603 "core_clk_uni 1386 "core_clk_unipro",
2604 "ref_clk", 1387 "ref_clk",
2605 "tx_lane0_syn 1388 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 1389 "rx_lane0_sync_clk",
2607 "rx_lane1_syn !! 1390 "rx_lane1_sync_clk";
2608 "ice_core_clk <<
2609 clocks = 1391 clocks =
2610 <&gcc GCC_UFS 1392 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 1393 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 1394 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 1395 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 1396 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 1397 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 1398 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS !! 1399 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2618 <&gcc GCC_UFS !! 1400 freq-table-hz =
2619 !! 1401 <50000000 200000000>,
2620 operating-points-v2 = !! 1402 <0 0>,
2621 !! 1403 <0 0>,
2622 interconnects = <&agg !! 1404 <37500000 150000000>,
2623 <&gla !! 1405 <0 0>,
2624 interconnect-names = !! 1406 <0 0>,
>> 1407 <0 0>,
>> 1408 <0 0>;
2625 1409
2626 status = "disabled"; 1410 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 1411 };
2658 1412
2659 ufs_mem_phy: phy@1d87000 { 1413 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 1414 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 1415 reg = <0 0x01d87000 0 0x18c>;
2662 !! 1416 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 1417 #size-cells = <2>;
2664 <&gcc GCC_UF !! 1418 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 1419 clock-names = "ref",
2667 "ref_au !! 1420 "ref_aux";
2668 "qref"; !! 1421 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 1422 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 1423
2672 resets = <&ufs_mem_hc 1424 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 1425 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; <<
2677 }; <<
2678 <<
2679 cryptobam: dma-controller@1dc <<
2680 compatible = "qcom,ba <<
2681 reg = <0 0x01dc4000 0 <<
2682 interrupts = <GIC_SPI <<
2683 clocks = <&rpmhcc RPM <<
2684 clock-names = "bam_cl <<
2685 #dma-cells = <1>; <<
2686 qcom,ee = <0>; <<
2687 qcom,controlled-remot <<
2688 iommus = <&apps_smmu <<
2689 <&apps_smmu <<
2690 <&apps_smmu <<
2691 <&apps_smmu <<
2692 }; <<
2693 <<
2694 crypto: crypto@1dfa000 { <<
2695 compatible = "qcom,cr <<
2696 reg = <0 0x01dfa000 0 <<
2697 clocks = <&gcc GCC_CE <<
2698 <&gcc GCC_CE <<
2699 <&rpmhcc RPM <<
2700 clock-names = "iface" <<
2701 dmas = <&cryptobam 6> <<
2702 dma-names = "rx", "tx <<
2703 iommus = <&apps_smmu <<
2704 <&apps_smmu <<
2705 <&apps_smmu <<
2706 <&apps_smmu <<
2707 }; <<
2708 <<
2709 ipa: ipa@1e40000 { <<
2710 compatible = "qcom,sd <<
2711 <<
2712 iommus = <&apps_smmu <<
2713 <&apps_smmu <<
2714 reg = <0 0x01e40000 0 <<
2715 <0 0x01e47000 0 <<
2716 <0 0x01e04000 0 <<
2717 reg-names = "ipa-reg" <<
2718 "ipa-shar <<
2719 "gsi"; <<
2720 <<
2721 interrupts-extended = <<
2722 <<
2723 <<
2724 <<
2725 interrupt-names = "ip <<
2726 "gs <<
2727 "ip <<
2728 "ip <<
2729 <<
2730 clocks = <&rpmhcc RPM <<
2731 clock-names = "core"; <<
2732 <<
2733 interconnects = <&agg <<
2734 <&agg <<
2735 <&gla <<
2736 interconnect-names = <<
2737 <<
2738 <<
2739 <<
2740 qcom,smem-states = <& <<
2741 <& <<
2742 qcom,smem-state-names <<
2743 <<
2744 <<
2745 status = "disabled"; 1426 status = "disabled";
2746 }; <<
2747 1427
2748 tcsr_mutex: hwlock@1f40000 { !! 1428 ufs_mem_phy_lanes: lanes@1d87400 {
2749 compatible = "qcom,tc !! 1429 reg = <0 0x01d87400 0 0x108>,
2750 reg = <0 0x01f40000 0 !! 1430 <0 0x01d87600 0 0x1e0>,
2751 #hwlock-cells = <1>; !! 1431 <0 0x01d87c00 0 0x1dc>,
>> 1432 <0 0x01d87800 0 0x108>,
>> 1433 <0 0x01d87a00 0 0x1e0>;
>> 1434 #phy-cells = <0>;
>> 1435 };
2752 }; 1436 };
2753 1437
2754 tcsr_regs_1: syscon@1f60000 { !! 1438 tcsr_mutex_regs: syscon@1f40000 {
2755 compatible = "qcom,sd !! 1439 compatible = "syscon";
2756 reg = <0 0x01f60000 0 !! 1440 reg = <0 0x01f40000 0 0x40000>;
2757 }; 1441 };
2758 1442
2759 tlmm: pinctrl@3400000 { 1443 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 1444 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 1445 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 1446 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 1447 gpio-controller;
2764 #gpio-cells = <2>; 1448 #gpio-cells = <2>;
2765 interrupt-controller; 1449 interrupt-controller;
2766 #interrupt-cells = <2 1450 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm !! 1451 gpio-ranges = <&tlmm 0 0 150>;
2768 wakeup-parent = <&pdc 1452 wakeup-parent = <&pdc_intc>;
2769 1453
2770 cci0_default: cci0-de !! 1454 qspi_clk: qspi-clk {
2771 /* SDA, SCL * !! 1455 pinmux {
2772 pins = "gpio1 !! 1456 pins = "gpio95";
2773 function = "c !! 1457 function = "qspi_clk";
2774 !! 1458 };
2775 bias-pull-up; <<
2776 drive-strengt <<
2777 }; <<
2778 <<
2779 cci0_sleep: cci0-slee <<
2780 /* SDA, SCL * <<
2781 pins = "gpio1 <<
2782 function = "c <<
2783 <<
2784 drive-strengt <<
2785 bias-pull-dow <<
2786 }; <<
2787 <<
2788 cci1_default: cci1-de <<
2789 /* SDA, SCL * <<
2790 pins = "gpio1 <<
2791 function = "c <<
2792 <<
2793 bias-pull-up; <<
2794 drive-strengt <<
2795 }; <<
2796 <<
2797 cci1_sleep: cci1-slee <<
2798 /* SDA, SCL * <<
2799 pins = "gpio1 <<
2800 function = "c <<
2801 <<
2802 drive-strengt <<
2803 bias-pull-dow <<
2804 }; <<
2805 <<
2806 qspi_clk: qspi-clk-st <<
2807 pins = "gpio9 <<
2808 function = "q <<
2809 }; <<
2810 <<
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; 1459 };
2820 1460
2821 qspi_data0: qspi-data !! 1461 qspi_cs0: qspi-cs0 {
2822 pins = "gpio9 !! 1462 pinmux {
2823 function = "q !! 1463 pins = "gpio90";
>> 1464 function = "qspi_cs";
>> 1465 };
2824 }; 1466 };
2825 1467
2826 qspi_data1: qspi-data !! 1468 qspi_cs1: qspi-cs1 {
2827 pins = "gpio9 !! 1469 pinmux {
2828 function = "q !! 1470 pins = "gpio89";
>> 1471 function = "qspi_cs";
>> 1472 };
2829 }; 1473 };
2830 1474
2831 qspi_data23: qspi-dat !! 1475 qspi_data01: qspi-data01 {
2832 pins = "gpio9 !! 1476 pinmux-data {
2833 function = "q !! 1477 pins = "gpio91", "gpio92";
>> 1478 function = "qspi_data";
>> 1479 };
2834 }; 1480 };
2835 1481
2836 qup_i2c0_default: qup !! 1482 qspi_data12: qspi-data12 {
2837 pins = "gpio0 !! 1483 pinmux-data {
2838 function = "q !! 1484 pins = "gpio93", "gpio94";
>> 1485 function = "qspi_data";
>> 1486 };
2839 }; 1487 };
2840 1488
2841 qup_i2c1_default: qup !! 1489 qup_i2c0_default: qup-i2c0-default {
2842 pins = "gpio1 !! 1490 pinmux {
2843 function = "q !! 1491 pins = "gpio0", "gpio1";
>> 1492 function = "qup0";
>> 1493 };
2844 }; 1494 };
2845 1495
2846 qup_i2c2_default: qup !! 1496 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio2 !! 1497 pinmux {
2848 function = "q !! 1498 pins = "gpio17", "gpio18";
>> 1499 function = "qup1";
>> 1500 };
2849 }; 1501 };
2850 1502
2851 qup_i2c3_default: qup !! 1503 qup_i2c2_default: qup-i2c2-default {
2852 pins = "gpio4 !! 1504 pinmux {
2853 function = "q !! 1505 pins = "gpio27", "gpio28";
>> 1506 function = "qup2";
>> 1507 };
2854 }; 1508 };
2855 1509
2856 qup_i2c4_default: qup !! 1510 qup_i2c3_default: qup-i2c3-default {
2857 pins = "gpio8 !! 1511 pinmux {
2858 function = "q !! 1512 pins = "gpio41", "gpio42";
>> 1513 function = "qup3";
>> 1514 };
2859 }; 1515 };
2860 1516
2861 qup_i2c5_default: qup !! 1517 qup_i2c4_default: qup-i2c4-default {
2862 pins = "gpio8 !! 1518 pinmux {
2863 function = "q !! 1519 pins = "gpio89", "gpio90";
>> 1520 function = "qup4";
>> 1521 };
2864 }; 1522 };
2865 1523
2866 qup_i2c6_default: qup !! 1524 qup_i2c5_default: qup-i2c5-default {
2867 pins = "gpio4 !! 1525 pinmux {
2868 function = "q !! 1526 pins = "gpio85", "gpio86";
>> 1527 function = "qup5";
>> 1528 };
2869 }; 1529 };
2870 1530
2871 qup_i2c7_default: qup !! 1531 qup_i2c6_default: qup-i2c6-default {
2872 pins = "gpio9 !! 1532 pinmux {
2873 function = "q !! 1533 pins = "gpio45", "gpio46";
>> 1534 function = "qup6";
>> 1535 };
2874 }; 1536 };
2875 1537
2876 qup_i2c8_default: qup !! 1538 qup_i2c7_default: qup-i2c7-default {
2877 pins = "gpio6 !! 1539 pinmux {
2878 function = "q !! 1540 pins = "gpio93", "gpio94";
>> 1541 function = "qup7";
>> 1542 };
2879 }; 1543 };
2880 1544
2881 qup_i2c9_default: qup !! 1545 qup_i2c8_default: qup-i2c8-default {
2882 pins = "gpio6 !! 1546 pinmux {
2883 function = "q !! 1547 pins = "gpio65", "gpio66";
>> 1548 function = "qup8";
>> 1549 };
2884 }; 1550 };
2885 1551
2886 qup_i2c10_default: qu !! 1552 qup_i2c9_default: qup-i2c9-default {
2887 pins = "gpio5 !! 1553 pinmux {
2888 function = "q !! 1554 pins = "gpio6", "gpio7";
>> 1555 function = "qup9";
>> 1556 };
2889 }; 1557 };
2890 1558
2891 qup_i2c11_default: qu !! 1559 qup_i2c10_default: qup-i2c10-default {
2892 pins = "gpio3 !! 1560 pinmux {
2893 function = "q !! 1561 pins = "gpio55", "gpio56";
>> 1562 function = "qup10";
>> 1563 };
2894 }; 1564 };
2895 1565
2896 qup_i2c12_default: qu !! 1566 qup_i2c11_default: qup-i2c11-default {
2897 pins = "gpio4 !! 1567 pinmux {
2898 function = "q !! 1568 pins = "gpio31", "gpio32";
>> 1569 function = "qup11";
>> 1570 };
2899 }; 1571 };
2900 1572
2901 qup_i2c13_default: qu !! 1573 qup_i2c12_default: qup-i2c12-default {
2902 pins = "gpio1 !! 1574 pinmux {
2903 function = "q !! 1575 pins = "gpio49", "gpio50";
>> 1576 function = "qup12";
>> 1577 };
2904 }; 1578 };
2905 1579
2906 qup_i2c14_default: qu !! 1580 qup_i2c13_default: qup-i2c13-default {
2907 pins = "gpio3 !! 1581 pinmux {
2908 function = "q !! 1582 pins = "gpio105", "gpio106";
>> 1583 function = "qup13";
>> 1584 };
2909 }; 1585 };
2910 1586
2911 qup_i2c15_default: qu !! 1587 qup_i2c14_default: qup-i2c14-default {
2912 pins = "gpio8 !! 1588 pinmux {
2913 function = "q !! 1589 pins = "gpio33", "gpio34";
>> 1590 function = "qup14";
>> 1591 };
2914 }; 1592 };
2915 1593
2916 qup_spi0_default: qup !! 1594 qup_i2c15_default: qup-i2c15-default {
2917 pins = "gpio0 !! 1595 pinmux {
2918 function = "q !! 1596 pins = "gpio81", "gpio82";
>> 1597 function = "qup15";
>> 1598 };
2919 }; 1599 };
2920 1600
2921 qup_spi1_default: qup !! 1601 qup_spi0_default: qup-spi0-default {
2922 pins = "gpio1 !! 1602 pinmux {
2923 function = "q !! 1603 pins = "gpio0", "gpio1",
>> 1604 "gpio2", "gpio3";
>> 1605 function = "qup0";
>> 1606 };
2924 }; 1607 };
2925 1608
2926 qup_spi2_default: qup !! 1609 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 1610 pinmux {
2928 function = "q !! 1611 pins = "gpio17", "gpio18",
>> 1612 "gpio19", "gpio20";
>> 1613 function = "qup1";
>> 1614 };
2929 }; 1615 };
2930 1616
2931 qup_spi3_default: qup !! 1617 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 1618 pinmux {
2933 function = "q !! 1619 pins = "gpio27", "gpio28",
>> 1620 "gpio29", "gpio30";
>> 1621 function = "qup2";
>> 1622 };
2934 }; 1623 };
2935 1624
2936 qup_spi4_default: qup !! 1625 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 1626 pinmux {
2938 function = "q !! 1627 pins = "gpio41", "gpio42",
>> 1628 "gpio43", "gpio44";
>> 1629 function = "qup3";
>> 1630 };
2939 }; 1631 };
2940 1632
2941 qup_spi5_default: qup !! 1633 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 1634 pinmux {
2943 function = "q !! 1635 pins = "gpio89", "gpio90",
>> 1636 "gpio91", "gpio92";
>> 1637 function = "qup4";
>> 1638 };
2944 }; 1639 };
2945 1640
2946 qup_spi6_default: qup !! 1641 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 1642 pinmux {
2948 function = "q !! 1643 pins = "gpio85", "gpio86",
>> 1644 "gpio87", "gpio88";
>> 1645 function = "qup5";
>> 1646 };
2949 }; 1647 };
2950 1648
2951 qup_spi7_default: qup !! 1649 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 1650 pinmux {
2953 function = "q !! 1651 pins = "gpio45", "gpio46",
>> 1652 "gpio47", "gpio48";
>> 1653 function = "qup6";
>> 1654 };
2954 }; 1655 };
2955 1656
2956 qup_spi8_default: qup !! 1657 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 1658 pinmux {
2958 function = "q !! 1659 pins = "gpio93", "gpio94",
>> 1660 "gpio95", "gpio96";
>> 1661 function = "qup7";
>> 1662 };
2959 }; 1663 };
2960 1664
2961 qup_spi9_default: qup !! 1665 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 1666 pinmux {
2963 function = "q !! 1667 pins = "gpio65", "gpio66",
>> 1668 "gpio67", "gpio68";
>> 1669 function = "qup8";
>> 1670 };
2964 }; 1671 };
2965 1672
2966 qup_spi10_default: qu !! 1673 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 1674 pinmux {
2968 function = "q !! 1675 pins = "gpio6", "gpio7",
>> 1676 "gpio4", "gpio5";
>> 1677 function = "qup9";
>> 1678 };
2969 }; 1679 };
2970 1680
2971 qup_spi11_default: qu !! 1681 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 1682 pinmux {
2973 function = "q !! 1683 pins = "gpio55", "gpio56",
>> 1684 "gpio53", "gpio54";
>> 1685 function = "qup10";
>> 1686 };
2974 }; 1687 };
2975 1688
2976 qup_spi12_default: qu !! 1689 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 1690 pinmux {
2978 function = "q !! 1691 pins = "gpio31", "gpio32",
>> 1692 "gpio33", "gpio34";
>> 1693 function = "qup11";
>> 1694 };
2979 }; 1695 };
2980 1696
2981 qup_spi13_default: qu !! 1697 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 1698 pinmux {
2983 function = "q !! 1699 pins = "gpio49", "gpio50",
>> 1700 "gpio51", "gpio52";
>> 1701 function = "qup12";
>> 1702 };
2984 }; 1703 };
2985 1704
2986 qup_spi14_default: qu !! 1705 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 1706 pinmux {
2988 function = "q !! 1707 pins = "gpio105", "gpio106",
>> 1708 "gpio107", "gpio108";
>> 1709 function = "qup13";
>> 1710 };
2989 }; 1711 };
2990 1712
2991 qup_spi15_default: qu !! 1713 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 1714 pinmux {
2993 function = "q !! 1715 pins = "gpio33", "gpio34",
>> 1716 "gpio31", "gpio32";
>> 1717 function = "qup14";
>> 1718 };
2994 }; 1719 };
2995 1720
2996 qup_uart0_default: qu !! 1721 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 1722 pinmux {
2998 pins !! 1723 pins = "gpio81", "gpio82",
2999 funct !! 1724 "gpio83", "gpio84";
>> 1725 function = "qup15";
3000 }; 1726 };
>> 1727 };
3001 1728
3002 qup_uart0_rx: !! 1729 qup_uart0_default: qup-uart0-default {
3003 pins !! 1730 pinmux {
>> 1731 pins = "gpio2", "gpio3";
3004 funct 1732 function = "qup0";
3005 }; 1733 };
3006 }; 1734 };
3007 1735
3008 qup_uart1_default: qu !! 1736 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 1737 pinmux {
3010 pins !! 1738 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 1739 function = "qup1";
3017 }; 1740 };
3018 }; 1741 };
3019 1742
3020 qup_uart2_default: qu !! 1743 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 1744 pinmux {
3022 pins !! 1745 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 1746 function = "qup2";
3029 }; 1747 };
3030 }; 1748 };
3031 1749
3032 qup_uart3_default: qu !! 1750 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 1751 pinmux {
3034 pins !! 1752 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct <<
3041 }; <<
3042 }; <<
3043 <<
3044 qup_uart3_4pin: qup-u <<
3045 qup_uart3_4pi <<
3046 pins <<
3047 funct <<
3048 }; <<
3049 <<
3050 qup_uart3_4pi <<
3051 pins <<
3052 funct <<
3053 }; <<
3054 <<
3055 qup_uart3_4pi <<
3056 pins <<
3057 funct 1753 function = "qup3";
3058 }; 1754 };
3059 }; 1755 };
3060 1756
3061 qup_uart4_default: qu !! 1757 qup_uart4_default: qup-uart4-default {
3062 qup_uart4_tx: !! 1758 pinmux {
3063 pins !! 1759 pins = "gpio91", "gpio92";
3064 funct <<
3065 }; <<
3066 <<
3067 qup_uart4_rx: <<
3068 pins <<
3069 funct 1760 function = "qup4";
3070 }; 1761 };
3071 }; 1762 };
3072 1763
3073 qup_uart5_default: qu !! 1764 qup_uart5_default: qup-uart5-default {
3074 qup_uart5_tx: !! 1765 pinmux {
3075 pins !! 1766 pins = "gpio87", "gpio88";
3076 funct 1767 function = "qup5";
3077 }; 1768 };
3078 <<
3079 qup_uart5_rx: <<
3080 pins <<
3081 funct <<
3082 }; <<
3083 }; <<
3084 <<
3085 qup_uart6_default: qu <<
3086 qup_uart6_tx: <<
3087 pins <<
3088 funct <<
3089 }; <<
3090 <<
3091 qup_uart6_rx: <<
3092 pins <<
3093 funct <<
3094 }; <<
3095 }; 1769 };
3096 1770
3097 qup_uart6_4pin: qup-u !! 1771 qup_uart6_default: qup-uart6-default {
3098 qup_uart6_4pi !! 1772 pinmux {
3099 pins !! 1773 pins = "gpio47", "gpio48";
3100 funct 1774 function = "qup6";
3101 bias- <<
3102 }; <<
3103 <<
3104 qup_uart6_4pi <<
3105 pins <<
3106 funct <<
3107 drive <<
3108 bias- <<
3109 }; <<
3110 <<
3111 qup_uart6_4pi <<
3112 pins <<
3113 funct <<
3114 bias- <<
3115 }; 1775 };
3116 }; 1776 };
3117 1777
3118 qup_uart7_default: qu !! 1778 qup_uart7_default: qup-uart7-default {
3119 qup_uart7_tx: !! 1779 pinmux {
3120 pins !! 1780 pins = "gpio95", "gpio96";
3121 funct <<
3122 }; <<
3123 <<
3124 qup_uart7_rx: <<
3125 pins <<
3126 funct 1781 function = "qup7";
3127 }; 1782 };
3128 }; 1783 };
3129 1784
3130 qup_uart8_default: qu !! 1785 qup_uart8_default: qup-uart8-default {
3131 qup_uart8_tx: !! 1786 pinmux {
3132 pins !! 1787 pins = "gpio67", "gpio68";
3133 funct <<
3134 }; <<
3135 <<
3136 qup_uart8_rx: <<
3137 pins <<
3138 funct 1788 function = "qup8";
3139 }; 1789 };
3140 }; 1790 };
3141 1791
3142 qup_uart9_default: qu !! 1792 qup_uart9_default: qup-uart9-default {
3143 qup_uart9_tx: !! 1793 pinmux {
3144 pins !! 1794 pins = "gpio4", "gpio5";
3145 funct <<
3146 }; <<
3147 <<
3148 qup_uart9_rx: <<
3149 pins <<
3150 funct 1795 function = "qup9";
3151 }; 1796 };
3152 }; 1797 };
3153 1798
3154 qup_uart10_default: q !! 1799 qup_uart10_default: qup-uart10-default {
3155 qup_uart10_tx !! 1800 pinmux {
3156 pins !! 1801 pins = "gpio53", "gpio54";
3157 funct <<
3158 }; <<
3159 <<
3160 qup_uart10_rx <<
3161 pins <<
3162 funct 1802 function = "qup10";
3163 }; 1803 };
3164 }; 1804 };
3165 1805
3166 qup_uart11_default: q !! 1806 qup_uart11_default: qup-uart11-default {
3167 qup_uart11_tx !! 1807 pinmux {
3168 pins !! 1808 pins = "gpio33", "gpio34";
3169 funct <<
3170 }; <<
3171 <<
3172 qup_uart11_rx <<
3173 pins <<
3174 funct 1809 function = "qup11";
3175 }; 1810 };
3176 }; 1811 };
3177 1812
3178 qup_uart12_default: q !! 1813 qup_uart12_default: qup-uart12-default {
3179 qup_uart12_tx !! 1814 pinmux {
3180 pins !! 1815 pins = "gpio51", "gpio52";
3181 funct !! 1816 function = "qup12";
3182 }; <<
3183 <<
3184 qup_uart12_rx <<
3185 pins <<
3186 funct <<
3187 }; 1817 };
3188 }; 1818 };
3189 1819
3190 qup_uart13_default: q !! 1820 qup_uart13_default: qup-uart13-default {
3191 qup_uart13_tx !! 1821 pinmux {
3192 pins !! 1822 pins = "gpio107", "gpio108";
3193 funct <<
3194 }; <<
3195 <<
3196 qup_uart13_rx <<
3197 pins <<
3198 funct 1823 function = "qup13";
3199 }; 1824 };
3200 }; 1825 };
3201 1826
3202 qup_uart14_default: q !! 1827 qup_uart14_default: qup-uart14-default {
3203 qup_uart14_tx !! 1828 pinmux {
3204 pins !! 1829 pins = "gpio31", "gpio32";
3205 funct <<
3206 }; <<
3207 <<
3208 qup_uart14_rx <<
3209 pins <<
3210 funct 1830 function = "qup14";
3211 }; 1831 };
3212 }; 1832 };
3213 1833
3214 qup_uart15_default: q !! 1834 qup_uart15_default: qup-uart15-default {
3215 qup_uart15_tx !! 1835 pinmux {
3216 pins !! 1836 pins = "gpio83", "gpio84";
3217 funct <<
3218 }; <<
3219 <<
3220 qup_uart15_rx <<
3221 pins <<
3222 funct 1837 function = "qup15";
3223 }; 1838 };
3224 }; 1839 };
3225 <<
3226 quat_mi2s_sleep: quat <<
3227 pins = "gpio5 <<
3228 function = "g <<
3229 drive-strengt <<
3230 bias-pull-dow <<
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 <<
3290 quat_mi2s_sd3_active: <<
3291 pins = "gpio6 <<
3292 function = "q <<
3293 drive-strengt <<
3294 bias-disable; <<
3295 }; <<
3296 }; 1840 };
3297 1841
3298 mss_pil: remoteproc@4080000 { 1842 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 1843 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 1844 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 1845 reg-names = "qdsp6", "rmb";
3302 1846
3303 interrupts-extended = 1847 interrupts-extended =
3304 <&intc GIC_SP 1848 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 1849 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 1850 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 1851 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 1852 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 1853 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 1854 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 1855 "handover", "stop-ack",
3312 "sh 1856 "shutdown-ack";
3313 1857
3314 clocks = <&gcc GCC_MS 1858 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 1859 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 1860 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 1861 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 1862 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 1863 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 1864 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 1865 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 1866 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 1867 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 1868
3325 qcom,qmp = <&aoss_qmp <<
3326 <<
3327 qcom,smem-states = <& 1869 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 1870 qcom,smem-state-names = "stop";
3329 1871
3330 resets = <&aoss_reset 1872 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 1873 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 1874 reset-names = "mss_restart", "pdc_reset";
3333 1875
3334 qcom,halt-regs = <&tc !! 1876 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 1877
3336 power-domains = <&rpm !! 1878 power-domains = <&aoss_qmp 2>,
>> 1879 <&rpmhpd SDM845_CX>,
3337 <&rpm 1880 <&rpmhpd SDM845_MX>,
3338 <&rpm 1881 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = !! 1882 power-domain-names = "load_state", "cx", "mx", "mss";
3340 <<
3341 status = "disabled"; <<
3342 1883
3343 mba { 1884 mba {
3344 memory-region 1885 memory-region = <&mba_region>;
3345 }; 1886 };
3346 1887
3347 mpss { 1888 mpss {
3348 memory-region 1889 memory-region = <&mpss_region>;
3349 }; 1890 };
3350 1891
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 1892 glink-edge {
3356 interrupts = 1893 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 1894 label = "modem";
3358 qcom,remote-p 1895 qcom,remote-pid = <1>;
3359 mboxes = <&ap 1896 mboxes = <&apss_shared 12>;
3360 }; 1897 };
3361 }; 1898 };
3362 1899
3363 gpucc: clock-controller@50900 1900 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 1901 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 1902 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 1903 #clock-cells = <1>;
3367 #reset-cells = <1>; 1904 #reset-cells = <1>;
3368 #power-domain-cells = 1905 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM <<
3370 <&gcc GCC_GP <<
3371 <&gcc GCC_GP <<
3372 clock-names = "bi_tcx <<
3373 "gcc_gp <<
3374 "gcc_gp <<
3375 }; <<
3376 <<
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM 1906 clocks = <&rpmhcc RPMH_CXO_CLK>;
3390 clock-names = "xo"; 1907 clock-names = "xo";
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; 1908 };
3429 1909
3430 stm@6002000 { 1910 stm@6002000 {
3431 compatible = "arm,cor 1911 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 1912 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 1913 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 1914 reg-names = "stm-base", "stm-stimulus-base";
3435 1915
3436 clocks = <&aoss_qmp>; 1916 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 1917 clock-names = "apb_pclk";
3438 1918
3439 out-ports { 1919 out-ports {
3440 port { 1920 port {
3441 stm_o 1921 stm_out: endpoint {
3442 1922 remote-endpoint =
3443 1923 <&funnel0_in7>;
3444 }; 1924 };
3445 }; 1925 };
3446 }; 1926 };
3447 }; 1927 };
3448 1928
3449 funnel@6041000 { 1929 funnel@6041000 {
3450 compatible = "arm,cor 1930 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 1931 reg = <0 0x06041000 0 0x1000>;
3452 1932
3453 clocks = <&aoss_qmp>; 1933 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 1934 clock-names = "apb_pclk";
3455 1935
3456 out-ports { 1936 out-ports {
3457 port { 1937 port {
3458 funne 1938 funnel0_out: endpoint {
3459 1939 remote-endpoint =
3460 1940 <&merge_funnel_in0>;
3461 }; 1941 };
3462 }; 1942 };
3463 }; 1943 };
3464 1944
3465 in-ports { 1945 in-ports {
3466 #address-cell 1946 #address-cells = <1>;
3467 #size-cells = 1947 #size-cells = <0>;
3468 1948
3469 port@7 { 1949 port@7 {
3470 reg = 1950 reg = <7>;
3471 funne 1951 funnel0_in7: endpoint {
3472 1952 remote-endpoint = <&stm_out>;
3473 }; 1953 };
3474 }; 1954 };
3475 }; 1955 };
3476 }; 1956 };
3477 1957
3478 funnel@6043000 { 1958 funnel@6043000 {
3479 compatible = "arm,cor 1959 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 1960 reg = <0 0x06043000 0 0x1000>;
3481 1961
3482 clocks = <&aoss_qmp>; 1962 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 1963 clock-names = "apb_pclk";
3484 1964
3485 out-ports { 1965 out-ports {
3486 port { 1966 port {
3487 funne 1967 funnel2_out: endpoint {
3488 1968 remote-endpoint =
3489 1969 <&merge_funnel_in2>;
3490 }; 1970 };
3491 }; 1971 };
3492 }; 1972 };
3493 1973
3494 in-ports { 1974 in-ports {
3495 #address-cell 1975 #address-cells = <1>;
3496 #size-cells = 1976 #size-cells = <0>;
3497 1977
3498 port@5 { 1978 port@5 {
3499 reg = 1979 reg = <5>;
3500 funne 1980 funnel2_in5: endpoint {
3501 1981 remote-endpoint =
3502 1982 <&apss_merge_funnel_out>;
3503 }; 1983 };
3504 }; 1984 };
3505 }; 1985 };
3506 }; 1986 };
3507 1987
3508 funnel@6045000 { 1988 funnel@6045000 {
3509 compatible = "arm,cor 1989 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 1990 reg = <0 0x06045000 0 0x1000>;
3511 1991
3512 clocks = <&aoss_qmp>; 1992 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 1993 clock-names = "apb_pclk";
3514 1994
3515 out-ports { 1995 out-ports {
3516 port { 1996 port {
3517 merge 1997 merge_funnel_out: endpoint {
3518 1998 remote-endpoint = <&etf_in>;
3519 }; 1999 };
3520 }; 2000 };
3521 }; 2001 };
3522 2002
3523 in-ports { 2003 in-ports {
3524 #address-cell 2004 #address-cells = <1>;
3525 #size-cells = 2005 #size-cells = <0>;
3526 2006
3527 port@0 { 2007 port@0 {
3528 reg = 2008 reg = <0>;
3529 merge 2009 merge_funnel_in0: endpoint {
3530 2010 remote-endpoint =
3531 2011 <&funnel0_out>;
3532 }; 2012 };
3533 }; 2013 };
3534 2014
3535 port@2 { 2015 port@2 {
3536 reg = 2016 reg = <2>;
3537 merge 2017 merge_funnel_in2: endpoint {
3538 2018 remote-endpoint =
3539 2019 <&funnel2_out>;
3540 }; 2020 };
3541 }; 2021 };
3542 }; 2022 };
3543 }; 2023 };
3544 2024
3545 replicator@6046000 { 2025 replicator@6046000 {
3546 compatible = "arm,cor 2026 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 2027 reg = <0 0x06046000 0 0x1000>;
3548 2028
3549 clocks = <&aoss_qmp>; 2029 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 2030 clock-names = "apb_pclk";
3551 2031
3552 out-ports { 2032 out-ports {
3553 port { 2033 port {
3554 repli 2034 replicator_out: endpoint {
3555 2035 remote-endpoint = <&etr_in>;
3556 }; 2036 };
3557 }; 2037 };
3558 }; 2038 };
3559 2039
3560 in-ports { 2040 in-ports {
3561 port { 2041 port {
3562 repli 2042 replicator_in: endpoint {
3563 2043 remote-endpoint = <&etf_out>;
3564 }; 2044 };
3565 }; 2045 };
3566 }; 2046 };
3567 }; 2047 };
3568 2048
3569 etf@6047000 { 2049 etf@6047000 {
3570 compatible = "arm,cor 2050 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 2051 reg = <0 0x06047000 0 0x1000>;
3572 2052
3573 clocks = <&aoss_qmp>; 2053 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 2054 clock-names = "apb_pclk";
3575 2055
3576 out-ports { 2056 out-ports {
3577 port { 2057 port {
3578 etf_o 2058 etf_out: endpoint {
3579 2059 remote-endpoint =
3580 2060 <&replicator_in>;
3581 }; 2061 };
3582 }; 2062 };
3583 }; 2063 };
3584 2064
3585 in-ports { 2065 in-ports {
>> 2066 #address-cells = <1>;
>> 2067 #size-cells = <0>;
3586 2068
3587 port { !! 2069 port@1 {
>> 2070 reg = <1>;
3588 etf_i 2071 etf_in: endpoint {
3589 2072 remote-endpoint =
3590 2073 <&merge_funnel_out>;
3591 }; 2074 };
3592 }; 2075 };
3593 }; 2076 };
3594 }; 2077 };
3595 2078
3596 etr@6048000 { 2079 etr@6048000 {
3597 compatible = "arm,cor 2080 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 2081 reg = <0 0x06048000 0 0x1000>;
3599 2082
3600 clocks = <&aoss_qmp>; 2083 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 2084 clock-names = "apb_pclk";
3602 arm,scatter-gather; 2085 arm,scatter-gather;
3603 2086
3604 in-ports { 2087 in-ports {
3605 port { 2088 port {
3606 etr_i 2089 etr_in: endpoint {
3607 2090 remote-endpoint =
3608 2091 <&replicator_out>;
3609 }; 2092 };
3610 }; 2093 };
3611 }; 2094 };
3612 }; 2095 };
3613 2096
3614 etm@7040000 { 2097 etm@7040000 {
3615 compatible = "arm,cor 2098 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 2099 reg = <0 0x07040000 0 0x1000>;
3617 2100
3618 cpu = <&CPU0>; 2101 cpu = <&CPU0>;
3619 2102
3620 clocks = <&aoss_qmp>; 2103 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 2104 clock-names = "apb_pclk";
3622 arm,coresight-loses-c <<
3623 2105
3624 out-ports { 2106 out-ports {
3625 port { 2107 port {
3626 etm0_ 2108 etm0_out: endpoint {
3627 2109 remote-endpoint =
3628 2110 <&apss_funnel_in0>;
3629 }; 2111 };
3630 }; 2112 };
3631 }; 2113 };
3632 }; 2114 };
3633 2115
3634 etm@7140000 { 2116 etm@7140000 {
3635 compatible = "arm,cor 2117 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 2118 reg = <0 0x07140000 0 0x1000>;
3637 2119
3638 cpu = <&CPU1>; 2120 cpu = <&CPU1>;
3639 2121
3640 clocks = <&aoss_qmp>; 2122 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 2123 clock-names = "apb_pclk";
3642 arm,coresight-loses-c <<
3643 2124
3644 out-ports { 2125 out-ports {
3645 port { 2126 port {
3646 etm1_ 2127 etm1_out: endpoint {
3647 2128 remote-endpoint =
3648 2129 <&apss_funnel_in1>;
3649 }; 2130 };
3650 }; 2131 };
3651 }; 2132 };
3652 }; 2133 };
3653 2134
3654 etm@7240000 { 2135 etm@7240000 {
3655 compatible = "arm,cor 2136 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 2137 reg = <0 0x07240000 0 0x1000>;
3657 2138
3658 cpu = <&CPU2>; 2139 cpu = <&CPU2>;
3659 2140
3660 clocks = <&aoss_qmp>; 2141 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 2142 clock-names = "apb_pclk";
3662 arm,coresight-loses-c <<
3663 2143
3664 out-ports { 2144 out-ports {
3665 port { 2145 port {
3666 etm2_ 2146 etm2_out: endpoint {
3667 2147 remote-endpoint =
3668 2148 <&apss_funnel_in2>;
3669 }; 2149 };
3670 }; 2150 };
3671 }; 2151 };
3672 }; 2152 };
3673 2153
3674 etm@7340000 { 2154 etm@7340000 {
3675 compatible = "arm,cor 2155 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 2156 reg = <0 0x07340000 0 0x1000>;
3677 2157
3678 cpu = <&CPU3>; 2158 cpu = <&CPU3>;
3679 2159
3680 clocks = <&aoss_qmp>; 2160 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 2161 clock-names = "apb_pclk";
3682 arm,coresight-loses-c <<
3683 2162
3684 out-ports { 2163 out-ports {
3685 port { 2164 port {
3686 etm3_ 2165 etm3_out: endpoint {
3687 2166 remote-endpoint =
3688 2167 <&apss_funnel_in3>;
3689 }; 2168 };
3690 }; 2169 };
3691 }; 2170 };
3692 }; 2171 };
3693 2172
3694 etm@7440000 { 2173 etm@7440000 {
3695 compatible = "arm,cor 2174 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 2175 reg = <0 0x07440000 0 0x1000>;
3697 2176
3698 cpu = <&CPU4>; 2177 cpu = <&CPU4>;
3699 2178
3700 clocks = <&aoss_qmp>; 2179 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 2180 clock-names = "apb_pclk";
3702 arm,coresight-loses-c <<
3703 2181
3704 out-ports { 2182 out-ports {
3705 port { 2183 port {
3706 etm4_ 2184 etm4_out: endpoint {
3707 2185 remote-endpoint =
3708 2186 <&apss_funnel_in4>;
3709 }; 2187 };
3710 }; 2188 };
3711 }; 2189 };
3712 }; 2190 };
3713 2191
3714 etm@7540000 { 2192 etm@7540000 {
3715 compatible = "arm,cor 2193 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 2194 reg = <0 0x07540000 0 0x1000>;
3717 2195
3718 cpu = <&CPU5>; 2196 cpu = <&CPU5>;
3719 2197
3720 clocks = <&aoss_qmp>; 2198 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 2199 clock-names = "apb_pclk";
3722 arm,coresight-loses-c <<
3723 2200
3724 out-ports { 2201 out-ports {
3725 port { 2202 port {
3726 etm5_ 2203 etm5_out: endpoint {
3727 2204 remote-endpoint =
3728 2205 <&apss_funnel_in5>;
3729 }; 2206 };
3730 }; 2207 };
3731 }; 2208 };
3732 }; 2209 };
3733 2210
3734 etm@7640000 { 2211 etm@7640000 {
3735 compatible = "arm,cor 2212 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 2213 reg = <0 0x07640000 0 0x1000>;
3737 2214
3738 cpu = <&CPU6>; 2215 cpu = <&CPU6>;
3739 2216
3740 clocks = <&aoss_qmp>; 2217 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 2218 clock-names = "apb_pclk";
3742 arm,coresight-loses-c <<
3743 2219
3744 out-ports { 2220 out-ports {
3745 port { 2221 port {
3746 etm6_ 2222 etm6_out: endpoint {
3747 2223 remote-endpoint =
3748 2224 <&apss_funnel_in6>;
3749 }; 2225 };
3750 }; 2226 };
3751 }; 2227 };
3752 }; 2228 };
3753 2229
3754 etm@7740000 { 2230 etm@7740000 {
3755 compatible = "arm,cor 2231 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 2232 reg = <0 0x07740000 0 0x1000>;
3757 2233
3758 cpu = <&CPU7>; 2234 cpu = <&CPU7>;
3759 2235
3760 clocks = <&aoss_qmp>; 2236 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 2237 clock-names = "apb_pclk";
3762 arm,coresight-loses-c <<
3763 2238
3764 out-ports { 2239 out-ports {
3765 port { 2240 port {
3766 etm7_ 2241 etm7_out: endpoint {
3767 2242 remote-endpoint =
3768 2243 <&apss_funnel_in7>;
3769 }; 2244 };
3770 }; 2245 };
3771 }; 2246 };
3772 }; 2247 };
3773 2248
3774 funnel@7800000 { /* APSS Funn 2249 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 2250 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 2251 reg = <0 0x07800000 0 0x1000>;
3777 2252
3778 clocks = <&aoss_qmp>; 2253 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 2254 clock-names = "apb_pclk";
3780 2255
3781 out-ports { 2256 out-ports {
3782 port { 2257 port {
3783 apss_ 2258 apss_funnel_out: endpoint {
3784 2259 remote-endpoint =
3785 2260 <&apss_merge_funnel_in>;
3786 }; 2261 };
3787 }; 2262 };
3788 }; 2263 };
3789 2264
3790 in-ports { 2265 in-ports {
3791 #address-cell 2266 #address-cells = <1>;
3792 #size-cells = 2267 #size-cells = <0>;
3793 2268
3794 port@0 { 2269 port@0 {
3795 reg = 2270 reg = <0>;
3796 apss_ 2271 apss_funnel_in0: endpoint {
3797 2272 remote-endpoint =
3798 2273 <&etm0_out>;
3799 }; 2274 };
3800 }; 2275 };
3801 2276
3802 port@1 { 2277 port@1 {
3803 reg = 2278 reg = <1>;
3804 apss_ 2279 apss_funnel_in1: endpoint {
3805 2280 remote-endpoint =
3806 2281 <&etm1_out>;
3807 }; 2282 };
3808 }; 2283 };
3809 2284
3810 port@2 { 2285 port@2 {
3811 reg = 2286 reg = <2>;
3812 apss_ 2287 apss_funnel_in2: endpoint {
3813 2288 remote-endpoint =
3814 2289 <&etm2_out>;
3815 }; 2290 };
3816 }; 2291 };
3817 2292
3818 port@3 { 2293 port@3 {
3819 reg = 2294 reg = <3>;
3820 apss_ 2295 apss_funnel_in3: endpoint {
3821 2296 remote-endpoint =
3822 2297 <&etm3_out>;
3823 }; 2298 };
3824 }; 2299 };
3825 2300
3826 port@4 { 2301 port@4 {
3827 reg = 2302 reg = <4>;
3828 apss_ 2303 apss_funnel_in4: endpoint {
3829 2304 remote-endpoint =
3830 2305 <&etm4_out>;
3831 }; 2306 };
3832 }; 2307 };
3833 2308
3834 port@5 { 2309 port@5 {
3835 reg = 2310 reg = <5>;
3836 apss_ 2311 apss_funnel_in5: endpoint {
3837 2312 remote-endpoint =
3838 2313 <&etm5_out>;
3839 }; 2314 };
3840 }; 2315 };
3841 2316
3842 port@6 { 2317 port@6 {
3843 reg = 2318 reg = <6>;
3844 apss_ 2319 apss_funnel_in6: endpoint {
3845 2320 remote-endpoint =
3846 2321 <&etm6_out>;
3847 }; 2322 };
3848 }; 2323 };
3849 2324
3850 port@7 { 2325 port@7 {
3851 reg = 2326 reg = <7>;
3852 apss_ 2327 apss_funnel_in7: endpoint {
3853 2328 remote-endpoint =
3854 2329 <&etm7_out>;
3855 }; 2330 };
3856 }; 2331 };
3857 }; 2332 };
3858 }; 2333 };
3859 2334
3860 funnel@7810000 { 2335 funnel@7810000 {
3861 compatible = "arm,cor 2336 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 2337 reg = <0 0x07810000 0 0x1000>;
3863 2338
3864 clocks = <&aoss_qmp>; 2339 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 2340 clock-names = "apb_pclk";
3866 2341
3867 out-ports { 2342 out-ports {
3868 port { 2343 port {
3869 apss_ 2344 apss_merge_funnel_out: endpoint {
3870 2345 remote-endpoint =
3871 2346 <&funnel2_in5>;
3872 }; 2347 };
3873 }; 2348 };
3874 }; 2349 };
3875 2350
3876 in-ports { 2351 in-ports {
3877 port { 2352 port {
3878 apss_ 2353 apss_merge_funnel_in: endpoint {
3879 2354 remote-endpoint =
3880 2355 <&apss_funnel_out>;
3881 }; 2356 };
3882 }; 2357 };
3883 }; 2358 };
3884 }; 2359 };
3885 2360
3886 sdhc_2: mmc@8804000 { !! 2361 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 2362 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 2363 reg = <0 0x08804000 0 0x1000>;
3889 2364
3890 interrupts = <GIC_SPI 2365 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 2366 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 2367 interrupt-names = "hc_irq", "pwr_irq";
3893 2368
3894 clocks = <&gcc GCC_SD 2369 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD !! 2370 <&gcc GCC_SDCC2_APPS_CLK>;
3896 <&rpmhcc RPM !! 2371 clock-names = "iface", "core";
3897 clock-names = "iface" <<
3898 iommus = <&apps_smmu 2372 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm <<
3900 operating-points-v2 = <<
3901 2373
3902 status = "disabled"; 2374 status = "disabled";
3903 <<
3904 sdhc2_opp_table: opp- <<
3905 compatible = <<
3906 <<
3907 opp-9600000 { <<
3908 opp-h <<
3909 requi <<
3910 }; <<
3911 <<
3912 opp-19200000 <<
3913 opp-h <<
3914 requi <<
3915 }; <<
3916 <<
3917 opp-100000000 <<
3918 opp-h <<
3919 requi <<
3920 }; <<
3921 <<
3922 opp-201500000 <<
3923 opp-h <<
3924 requi <<
3925 }; <<
3926 }; <<
3927 }; 2375 };
3928 2376
3929 qspi: spi@88df000 { 2377 qspi: spi@88df000 {
3930 compatible = "qcom,sd 2378 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 2379 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 2380 #address-cells = <1>;
3934 #size-cells = <0>; 2381 #size-cells = <0>;
3935 interrupts = <GIC_SPI 2382 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 2383 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 2384 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 2385 clock-names = "iface", "core";
3939 power-domains = <&rpm <<
3940 operating-points-v2 = <<
3941 status = "disabled"; <<
3942 }; <<
3943 <<
3944 slim: slim-ngd@171c0000 { <<
3945 compatible = "qcom,sl <<
3946 reg = <0 0x171c0000 0 <<
3947 interrupts = <GIC_SPI <<
3948 <<
3949 dmas = <&slimbam 3>, <<
3950 dma-names = "rx", "tx <<
3951 <<
3952 iommus = <&apps_smmu <<
3953 #address-cells = <1>; <<
3954 #size-cells = <0>; <<
3955 status = "disabled"; 2386 status = "disabled";
3956 }; 2387 };
3957 2388
3958 lmh_cluster1: lmh@17d70800 { <<
3959 compatible = "qcom,sd <<
3960 reg = <0 0x17d70800 0 <<
3961 interrupts = <GIC_SPI <<
3962 cpus = <&CPU4>; <<
3963 qcom,lmh-temp-arm-mil <<
3964 qcom,lmh-temp-low-mil <<
3965 qcom,lmh-temp-high-mi <<
3966 interrupt-controller; <<
3967 #interrupt-cells = <1 <<
3968 }; <<
3969 <<
3970 lmh_cluster0: lmh@17d78800 { <<
3971 compatible = "qcom,sd <<
3972 reg = <0 0x17d78800 0 <<
3973 interrupts = <GIC_SPI <<
3974 cpus = <&CPU0>; <<
3975 qcom,lmh-temp-arm-mil <<
3976 qcom,lmh-temp-low-mil <<
3977 qcom,lmh-temp-high-mi <<
3978 interrupt-controller; <<
3979 #interrupt-cells = <1 <<
3980 }; <<
3981 <<
3982 usb_1_hsphy: phy@88e2000 { 2389 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd !! 2390 compatible = "qcom,sdm845-qusb2-phy";
3984 reg = <0 0x088e2000 0 2391 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 2392 status = "disabled";
3986 #phy-cells = <0>; 2393 #phy-cells = <0>;
3987 2394
3988 clocks = <&gcc GCC_US 2395 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 2396 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 2397 clock-names = "cfg_ahb", "ref";
3991 2398
3992 resets = <&gcc GCC_QU 2399 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 2400
3994 nvmem-cells = <&qusb2 2401 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 2402 };
3996 2403
3997 usb_2_hsphy: phy@88e3000 { 2404 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd !! 2405 compatible = "qcom,sdm845-qusb2-phy";
3999 reg = <0 0x088e3000 0 2406 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 2407 status = "disabled";
4001 #phy-cells = <0>; 2408 #phy-cells = <0>;
4002 2409
4003 clocks = <&gcc GCC_US 2410 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 2411 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 2412 clock-names = "cfg_ahb", "ref";
4006 2413
4007 resets = <&gcc GCC_QU 2414 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 2415
4009 nvmem-cells = <&qusb2 2416 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 2417 };
4011 2418
4012 usb_1_qmpphy: phy@88e8000 { !! 2419 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 2420 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 2421 reg = <0 0x088e9000 0 0x18c>,
>> 2422 <0 0x088e8000 0 0x10>;
>> 2423 reg-names = "reg-base", "dp_com";
4015 status = "disabled"; 2424 status = "disabled";
>> 2425 #clock-cells = <1>;
>> 2426 #address-cells = <2>;
>> 2427 #size-cells = <2>;
>> 2428 ranges;
4016 2429
4017 clocks = <&gcc GCC_US 2430 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2431 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 2432 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 2433 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 2434 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 2435
4028 resets = <&gcc GCC_US !! 2436 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 2437 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 2438 reset-names = "phy", "common";
4031 2439
4032 #clock-cells = <1>; !! 2440 usb_1_ssphy: lanes@88e9200 {
4033 #phy-cells = <1>; !! 2441 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 2442 <0 0x088e9400 0 0x200>,
4035 !! 2443 <0 0x088e9c00 0 0x218>,
4036 ports { !! 2444 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 2445 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 2446 <0 0x088e9a00 0 0x100>;
4039 !! 2447 #phy-cells = <0>;
4040 port@0 { !! 2448 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4041 reg = !! 2449 clock-names = "pipe0";
4042 !! 2450 clock-output-names = "usb3_phy_pipe_clk_src";
4043 usb_1 <<
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 2451 };
4063 }; 2452 };
4064 2453
4065 usb_2_qmpphy: phy@88eb000 { 2454 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 2455 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 2456 reg = <0 0x088eb000 0 0x18c>;
>> 2457 status = "disabled";
>> 2458 #clock-cells = <1>;
>> 2459 #address-cells = <2>;
>> 2460 #size-cells = <2>;
>> 2461 ranges;
4068 2462
4069 clocks = <&gcc GCC_US 2463 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 2464 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 2465 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 2466 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 2467 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 2468
4083 resets = <&gcc GCC_US !! 2469 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 2470 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 2471 reset-names = "phy", "common";
4086 "phy_ph <<
4087 2472
4088 status = "disabled"; !! 2473 usb_2_ssphy: lane@88eb200 {
>> 2474 reg = <0 0x088eb200 0 0x128>,
>> 2475 <0 0x088eb400 0 0x1fc>,
>> 2476 <0 0x088eb800 0 0x218>,
>> 2477 <0 0x088eb600 0 0x70>;
>> 2478 #phy-cells = <0>;
>> 2479 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2480 clock-names = "pipe0";
>> 2481 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2482 };
4089 }; 2483 };
4090 2484
4091 usb_1: usb@a6f8800 { 2485 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 2486 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 2487 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 2488 status = "disabled";
4095 #address-cells = <2>; 2489 #address-cells = <2>;
4096 #size-cells = <2>; 2490 #size-cells = <2>;
4097 ranges; 2491 ranges;
4098 dma-ranges; 2492 dma-ranges;
4099 2493
4100 clocks = <&gcc GCC_CF 2494 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 2495 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 2496 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 2497 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 2498 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 2499 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 2500 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 2501
4111 assigned-clocks = <&g 2502 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 2503 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 2504 assigned-clock-rates = <19200000>, <150000000>;
4114 2505
4115 interrupts-extended = !! 2506 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 2507 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 2508 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 2509 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 2510 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 2511 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 2512
4126 power-domains = <&gcc 2513 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 2514
4128 resets = <&gcc GCC_US 2515 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 2516
4130 interconnects = <&agg !! 2517 usb_1_dwc3: dwc3@a600000 {
4131 <&gla <<
4132 interconnect-names = <<
4133 <<
4134 usb_1_dwc3: usb@a6000 <<
4135 compatible = 2518 compatible = "snps,dwc3";
4136 reg = <0 0x0a 2519 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 2520 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 2521 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 2522 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 2523 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 2524 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 2525 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 2526 };
4165 }; 2527 };
4166 2528
4167 usb_2: usb@a8f8800 { 2529 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 2530 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 2531 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 2532 status = "disabled";
4171 #address-cells = <2>; 2533 #address-cells = <2>;
4172 #size-cells = <2>; 2534 #size-cells = <2>;
4173 ranges; 2535 ranges;
4174 dma-ranges; 2536 dma-ranges;
4175 2537
4176 clocks = <&gcc GCC_CF 2538 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 2539 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 2540 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 2541 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 2542 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 2543 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 2544 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 2545
4187 assigned-clocks = <&g 2546 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 2547 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 2548 assigned-clock-rates = <19200000>, <150000000>;
4190 2549
4191 interrupts-extended = !! 2550 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 2551 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 2552 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 2553 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 2554 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 2555 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 2556
4202 power-domains = <&gcc 2557 power-domains = <&gcc USB30_SEC_GDSC>;
4203 2558
4204 resets = <&gcc GCC_US 2559 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 2560
4206 interconnects = <&agg !! 2561 usb_2_dwc3: dwc3@a800000 {
4207 <&gla <<
4208 interconnect-names = <<
4209 <<
4210 usb_2_dwc3: usb@a8000 <<
4211 compatible = 2562 compatible = "snps,dwc3";
4212 reg = <0 0x0a 2563 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 2564 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 2565 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 2566 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 2567 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 2568 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 2569 phy-names = "usb2-phy", "usb3-phy";
4220 }; 2570 };
4221 }; 2571 };
4222 2572
4223 venus: video-codec@aa00000 { !! 2573 video-codec@aa00000 {
4224 compatible = "qcom,sd !! 2574 compatible = "qcom,sdm845-venus";
4225 reg = <0 0x0aa00000 0 2575 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 2576 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid !! 2577 power-domains = <&videocc VENUS_GDSC>;
4228 <&vid <<
4229 <&vid <<
4230 <&rpm <<
4231 power-domain-names = <<
4232 operating-points-v2 = <<
4233 clocks = <&videocc VI 2578 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 2579 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI !! 2580 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
4236 <&videocc VI !! 2581 clock-names = "core", "iface", "bus";
4237 <&videocc VI <<
4238 <&videocc VI <<
4239 <&videocc VI <<
4240 clock-names = "core", <<
4241 "vcodec <<
4242 "vcodec <<
4243 iommus = <&apps_smmu 2582 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 2583 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 2584 memory-region = <&venus_mem>;
4246 interconnects = <&mms <<
4247 <&gla <<
4248 interconnect-names = <<
4249 <<
4250 status = "disabled"; <<
4251 2585
4252 video-core0 { 2586 video-core0 {
4253 compatible = 2587 compatible = "venus-decoder";
>> 2588 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
>> 2589 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
>> 2590 clock-names = "core", "bus";
>> 2591 power-domains = <&videocc VCODEC0_GDSC>;
4254 }; 2592 };
4255 2593
4256 video-core1 { 2594 video-core1 {
4257 compatible = 2595 compatible = "venus-encoder";
4258 }; !! 2596 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4259 !! 2597 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4260 venus_opp_table: opp- !! 2598 clock-names = "core", "bus";
4261 compatible = !! 2599 power-domains = <&videocc VCODEC1_GDSC>;
4262 <<
4263 opp-100000000 <<
4264 opp-h <<
4265 requi <<
4266 }; <<
4267 <<
4268 opp-200000000 <<
4269 opp-h <<
4270 requi <<
4271 }; <<
4272 <<
4273 opp-320000000 <<
4274 opp-h <<
4275 requi <<
4276 }; <<
4277 <<
4278 opp-380000000 <<
4279 opp-h <<
4280 requi <<
4281 }; <<
4282 <<
4283 opp-444000000 <<
4284 opp-h <<
4285 requi <<
4286 }; <<
4287 <<
4288 opp-533000097 <<
4289 opp-h <<
4290 requi <<
4291 }; <<
4292 }; 2600 };
4293 }; 2601 };
4294 2602
4295 videocc: clock-controller@ab0 2603 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 2604 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 2605 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM <<
4299 clock-names = "bi_tcx <<
4300 #clock-cells = <1>; 2606 #clock-cells = <1>;
4301 #power-domain-cells = 2607 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 2608 #reset-cells = <1>;
4303 }; 2609 };
4304 2610
4305 camss: camss@acb3000 { !! 2611 mdss: mdss@ae00000 {
4306 compatible = "qcom,sd <<
4307 <<
4308 reg = <0 0x0acb3000 0 <<
4309 <0 0x0acba000 <<
4310 <0 0x0acc8000 <<
4311 <0 0x0ac65000 <<
4312 <0 0x0ac66000 <<
4313 <0 0x0ac67000 <<
4314 <0 0x0ac68000 <<
4315 <0 0x0acaf000 <<
4316 <0 0x0acb6000 <<
4317 <0 0x0acc4000 <<
4318 reg-names = "csid0", <<
4319 "csid1", <<
4320 "csid2", <<
4321 "csiphy0", <<
4322 "csiphy1", <<
4323 "csiphy2", <<
4324 "csiphy3", <<
4325 "vfe0", <<
4326 "vfe1", <<
4327 "vfe_lite"; <<
4328 <<
4329 interrupts = <GIC_SPI <<
4330 <GIC_SPI 466 <<
4331 <GIC_SPI 468 <<
4332 <GIC_SPI 477 <<
4333 <GIC_SPI 478 <<
4334 <GIC_SPI 479 <<
4335 <GIC_SPI 448 <<
4336 <GIC_SPI 465 <<
4337 <GIC_SPI 467 <<
4338 <GIC_SPI 469 <<
4339 interrupt-names = "cs <<
4340 "csid1", <<
4341 "csid2", <<
4342 "csiphy0", <<
4343 "csiphy1", <<
4344 "csiphy2", <<
4345 "csiphy3", <<
4346 "vfe0", <<
4347 "vfe1", <<
4348 "vfe_lite"; <<
4349 <<
4350 power-domains = <&clo <<
4351 <&clock_camcc <<
4352 <&clock_camcc <<
4353 <<
4354 clocks = <&clock_camc <<
4355 <&clock_camcc <<
4356 <&clock_camcc <<
4357 <&clock_camcc <<
4358 <&clock_camcc <<
4359 <&clock_camcc <<
4360 <&clock_camcc <<
4361 <&clock_camcc <<
4362 <&clock_camcc <<
4363 <&clock_camcc <<
4364 <&clock_camcc <<
4365 <&clock_camcc <<
4366 <&clock_camcc <<
4367 <&clock_camcc <<
4368 <&clock_camcc <<
4369 <&clock_camcc <<
4370 <&clock_camcc <<
4371 <&clock_camcc <<
4372 <&clock_camcc <<
4373 <&clock_camcc <<
4374 <&clock_camcc <<
4375 <&gcc GCC_CAM <<
4376 <&gcc GCC_CAM <<
4377 <&clock_camcc <<
4378 <&clock_camcc <<
4379 <&clock_camcc <<
4380 <&clock_camcc <<
4381 <&clock_camcc <<
4382 <&clock_camcc <<
4383 <&clock_camcc <<
4384 <&clock_camcc <<
4385 <&clock_camcc <<
4386 <&clock_camcc <<
4387 <&clock_camcc <<
4388 <&clock_camcc <<
4389 <&clock_camcc <<
4390 clock-names = "camnoc <<
4391 "cpas_ahb", <<
4392 "cphy_rx_src" <<
4393 "csi0", <<
4394 "csi0_src", <<
4395 "csi1", <<
4396 "csi1_src", <<
4397 "csi2", <<
4398 "csi2_src", <<
4399 "csiphy0", <<
4400 "csiphy0_time <<
4401 "csiphy0_time <<
4402 "csiphy1", <<
4403 "csiphy1_time <<
4404 "csiphy1_time <<
4405 "csiphy2", <<
4406 "csiphy2_time <<
4407 "csiphy2_time <<
4408 "csiphy3", <<
4409 "csiphy3_time <<
4410 "csiphy3_time <<
4411 "gcc_camera_a <<
4412 "gcc_camera_a <<
4413 "slow_ahb_src <<
4414 "soc_ahb", <<
4415 "vfe0_axi", <<
4416 "vfe0", <<
4417 "vfe0_cphy_rx <<
4418 "vfe0_src", <<
4419 "vfe1_axi", <<
4420 "vfe1", <<
4421 "vfe1_cphy_rx <<
4422 "vfe1_src", <<
4423 "vfe_lite", <<
4424 "vfe_lite_cph <<
4425 "vfe_lite_src <<
4426 <<
4427 iommus = <&apps_smmu <<
4428 <&apps_smmu <<
4429 <&apps_smmu <<
4430 <&apps_smmu <<
4431 <<
4432 status = "disabled"; <<
4433 <<
4434 ports { <<
4435 #address-cell <<
4436 #size-cells = <<
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; <<
4454 }; <<
4455 <<
4456 cci: cci@ac4a000 { <<
4457 compatible = "qcom,sd <<
4458 #address-cells = <1>; <<
4459 #size-cells = <0>; <<
4460 <<
4461 reg = <0 0x0ac4a000 0 <<
4462 interrupts = <GIC_SPI <<
4463 power-domains = <&clo <<
4464 <<
4465 clocks = <&clock_camc <<
4466 <&clock_camcc <<
4467 <&clock_camcc <<
4468 <&clock_camcc <<
4469 <&clock_camcc <<
4470 <&clock_camcc <<
4471 clock-names = "camnoc <<
4472 "soc_ahb", <<
4473 "slow_ahb_src <<
4474 "cpas_ahb", <<
4475 "cci", <<
4476 "cci_src"; <<
4477 <<
4478 assigned-clocks = <&c <<
4479 <&clock_camcc <<
4480 assigned-clock-rates <<
4481 <<
4482 pinctrl-names = "defa <<
4483 pinctrl-0 = <&cci0_de <<
4484 pinctrl-1 = <&cci0_sl <<
4485 <<
4486 status = "disabled"; <<
4487 <<
4488 cci_i2c0: i2c-bus@0 { <<
4489 reg = <0>; <<
4490 clock-frequen <<
4491 #address-cell <<
4492 #size-cells = <<
4493 }; <<
4494 <<
4495 cci_i2c1: i2c-bus@1 { <<
4496 reg = <1>; <<
4497 clock-frequen <<
4498 #address-cell <<
4499 #size-cells = <<
4500 }; <<
4501 }; <<
4502 <<
4503 clock_camcc: clock-controller <<
4504 compatible = "qcom,sd <<
4505 reg = <0 0x0ad00000 0 <<
4506 #clock-cells = <1>; <<
4507 #reset-cells = <1>; <<
4508 #power-domain-cells = <<
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; <<
4512 <<
4513 mdss: display-subsystem@ae000 <<
4514 compatible = "qcom,sd 2612 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 2613 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 2614 reg-names = "mdss";
4517 2615
4518 power-domains = <&dis 2616 power-domains = <&dispcc MDSS_GDSC>;
4519 2617
4520 clocks = <&dispcc DIS !! 2618 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 2619 <&gcc GCC_DISP_AXI_CLK>,
4521 <&dispcc DIS 2620 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" !! 2621 clock-names = "iface", "bus", "core";
>> 2622
>> 2623 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2624 assigned-clock-rates = <300000000>;
4523 2625
4524 interrupts = <GIC_SPI 2626 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 2627 interrupt-controller;
4526 #interrupt-cells = <1 2628 #interrupt-cells = <1>;
4527 2629
4528 interconnects = <&mms <<
4529 <&mms <<
4530 interconnect-names = <<
4531 <<
4532 iommus = <&apps_smmu 2630 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 2631 <&apps_smmu 0xc80 0x8>;
4534 2632
4535 status = "disabled"; 2633 status = "disabled";
4536 2634
4537 #address-cells = <2>; 2635 #address-cells = <2>;
4538 #size-cells = <2>; 2636 #size-cells = <2>;
4539 ranges; 2637 ranges;
4540 2638
4541 mdss_mdp: display-con !! 2639 mdss_mdp: mdp@ae01000 {
4542 compatible = 2640 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 2641 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 2642 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 2643 reg-names = "mdp", "vbif";
4546 2644
4547 clocks = <&gc !! 2645 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4548 <&di <<
4549 <&di 2646 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 2647 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 2648 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = !! 2649 clock-names = "iface", "bus", "core", "vsync";
4553 2650
4554 assigned-cloc !! 2651 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 2652 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4556 operating-poi !! 2653 assigned-clock-rates = <300000000>,
4557 power-domains !! 2654 <19200000>;
4558 2655
4559 interrupt-par 2656 interrupt-parent = <&mdss>;
4560 interrupts = !! 2657 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> 2658
>> 2659 status = "disabled";
4561 2660
4562 ports { 2661 ports {
4563 #addr 2662 #address-cells = <1>;
4564 #size 2663 #size-cells = <0>;
4565 2664
4566 port@ 2665 port@0 {
4567 2666 reg = <0>;
4568 !! 2667 dpu_intf1_out: endpoint {
4569 !! 2668 remote-endpoint = <&dsi0_in>;
4570 2669 };
4571 }; 2670 };
4572 2671
4573 port@ 2672 port@1 {
4574 2673 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 2674 dpu_intf2_out: endpoint {
4583 !! 2675 remote-endpoint = <&dsi1_in>;
4584 2676 };
4585 }; 2677 };
4586 }; 2678 };
4587 <<
4588 mdp_opp_table <<
4589 compa <<
4590 <<
4591 opp-1 <<
4592 <<
4593 <<
4594 }; <<
4595 <<
4596 opp-1 <<
4597 <<
4598 <<
4599 }; <<
4600 <<
4601 opp-3 <<
4602 <<
4603 <<
4604 }; <<
4605 <<
4606 opp-4 <<
4607 <<
4608 <<
4609 }; <<
4610 }; <<
4611 }; 2679 };
4612 2680
4613 mdss_dp: displayport- !! 2681 dsi0: dsi@ae94000 {
4614 status = "dis !! 2682 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 2683 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 2684 reg-names = "dsi_ctrl";
4691 2685
4692 interrupt-par 2686 interrupt-parent = <&mdss>;
4693 interrupts = !! 2687 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 2688
4695 clocks = <&di 2689 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 2690 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 2691 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 2692 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 2693 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 2694 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 2695 clock-names = "byte",
4702 2696 "byte_intf",
4703 2697 "pixel",
4704 2698 "core",
4705 2699 "iface",
4706 2700 "bus";
4707 assigned-cloc <<
4708 assigned-cloc <<
4709 2701
4710 operating-poi !! 2702 phys = <&dsi0_phy>;
4711 power-domains !! 2703 phy-names = "dsi";
4712 <<
4713 phys = <&mdss <<
4714 2704
4715 status = "dis 2705 status = "disabled";
4716 2706
4717 #address-cell <<
4718 #size-cells = <<
4719 <<
4720 ports { 2707 ports {
4721 #addr 2708 #address-cells = <1>;
4722 #size 2709 #size-cells = <0>;
4723 2710
4724 port@ 2711 port@0 {
4725 2712 reg = <0>;
4726 !! 2713 dsi0_in: endpoint {
4727 2714 remote-endpoint = <&dpu_intf1_out>;
4728 2715 };
4729 }; 2716 };
4730 2717
4731 port@ 2718 port@1 {
4732 2719 reg = <1>;
4733 !! 2720 dsi0_out: endpoint {
4734 2721 };
4735 }; 2722 };
4736 }; 2723 };
4737 }; 2724 };
4738 2725
4739 mdss_dsi0_phy: phy@ae !! 2726 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 2727 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 2728 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 2729 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 2730 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 2731 reg-names = "dsi_phy",
4745 " 2732 "dsi_phy_lane",
4746 " 2733 "dsi_pll";
4747 2734
4748 #clock-cells 2735 #clock-cells = <1>;
4749 #phy-cells = 2736 #phy-cells = <0>;
4750 2737
4751 clocks = <&di 2738 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 2739 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 2740 clock-names = "iface", "ref";
4754 2741
4755 status = "dis 2742 status = "disabled";
4756 }; 2743 };
4757 2744
4758 mdss_dsi1: dsi@ae9600 !! 2745 dsi1: dsi@ae96000 {
4759 compatible = !! 2746 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 2747 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 2748 reg-names = "dsi_ctrl";
4763 2749
4764 interrupt-par 2750 interrupt-parent = <&mdss>;
4765 interrupts = !! 2751 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 2752
4767 clocks = <&di 2753 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 2754 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 2755 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 2756 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 2757 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 2758 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 2759 clock-names = "byte",
4774 2760 "byte_intf",
4775 2761 "pixel",
4776 2762 "core",
4777 2763 "iface",
4778 2764 "bus";
4779 assigned-cloc <<
4780 assigned-cloc <<
4781 2765
4782 operating-poi !! 2766 phys = <&dsi1_phy>;
4783 power-domains !! 2767 phy-names = "dsi";
4784 <<
4785 phys = <&mdss <<
4786 2768
4787 status = "dis 2769 status = "disabled";
4788 2770
4789 #address-cell <<
4790 #size-cells = <<
4791 <<
4792 ports { 2771 ports {
4793 #addr 2772 #address-cells = <1>;
4794 #size 2773 #size-cells = <0>;
4795 2774
4796 port@ 2775 port@0 {
4797 2776 reg = <0>;
4798 !! 2777 dsi1_in: endpoint {
4799 2778 remote-endpoint = <&dpu_intf2_out>;
4800 2779 };
4801 }; 2780 };
4802 2781
4803 port@ 2782 port@1 {
4804 2783 reg = <1>;
4805 !! 2784 dsi1_out: endpoint {
4806 2785 };
4807 }; 2786 };
4808 }; 2787 };
4809 }; 2788 };
4810 2789
4811 mdss_dsi1_phy: phy@ae !! 2790 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 2791 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 2792 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 2793 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 2794 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 2795 reg-names = "dsi_phy",
4817 " 2796 "dsi_phy_lane",
4818 " 2797 "dsi_pll";
4819 2798
4820 #clock-cells 2799 #clock-cells = <1>;
4821 #phy-cells = 2800 #phy-cells = <0>;
4822 2801
4823 clocks = <&di 2802 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 2803 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 2804 clock-names = "iface", "ref";
4826 2805
4827 status = "dis 2806 status = "disabled";
4828 }; 2807 };
4829 }; 2808 };
4830 2809
4831 gpu: gpu@5000000 { 2810 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 2811 compatible = "qcom,adreno-630.2", "qcom,adreno";
>> 2812 #stream-id-cells = <16>;
4833 2813
4834 reg = <0 0x05000000 0 !! 2814 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 2815 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 2816
4837 /* 2817 /*
4838 * Look ma, no clocks 2818 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 2819 * controlled entirely by the GMU
4840 */ 2820 */
4841 2821
4842 interrupts = <GIC_SPI 2822 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 2823
4844 iommus = <&adreno_smm 2824 iommus = <&adreno_smmu 0>;
4845 2825
4846 operating-points-v2 = 2826 operating-points-v2 = <&gpu_opp_table>;
4847 2827
4848 qcom,gmu = <&gmu>; 2828 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 <<
4851 interconnects = <&mem <<
4852 interconnect-names = <<
4853 <<
4854 status = "disabled"; <<
4855 2829
4856 gpu_opp_table: opp-ta 2830 gpu_opp_table: opp-table {
4857 compatible = 2831 compatible = "operating-points-v2";
4858 2832
4859 opp-710000000 2833 opp-710000000 {
4860 opp-h 2834 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 2835 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p <<
4863 }; 2836 };
4864 2837
4865 opp-675000000 2838 opp-675000000 {
4866 opp-h 2839 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 2840 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p <<
4869 }; 2841 };
4870 2842
4871 opp-596000000 2843 opp-596000000 {
4872 opp-h 2844 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 2845 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p <<
4875 }; 2846 };
4876 2847
4877 opp-520000000 2848 opp-520000000 {
4878 opp-h 2849 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 2850 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p <<
4881 }; 2851 };
4882 2852
4883 opp-414000000 2853 opp-414000000 {
4884 opp-h 2854 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 2855 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p <<
4887 }; 2856 };
4888 2857
4889 opp-342000000 2858 opp-342000000 {
4890 opp-h 2859 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 2860 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p <<
4893 }; 2861 };
4894 2862
4895 opp-257000000 2863 opp-257000000 {
4896 opp-h 2864 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 2865 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p <<
4899 }; 2866 };
4900 }; 2867 };
4901 }; 2868 };
4902 2869
4903 adreno_smmu: iommu@5040000 { 2870 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd !! 2871 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 2872 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 2873 #iommu-cells = <1>;
4907 #global-interrupts = 2874 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 2875 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 2876 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 2877 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 2878 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 2879 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 2880 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 2881 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 2882 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 2883 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 2884 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 2885 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 2886 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 2887 clock-names = "bus", "iface";
4921 2888
4922 power-domains = <&gpu 2889 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 2890 };
4924 2891
4925 gmu: gmu@506a000 { 2892 gmu: gmu@506a000 {
4926 compatible = "qcom,ad !! 2893 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 2894
4928 reg = <0 0x0506a000 0 !! 2895 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 2896 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 2897 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 2898 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 2899
4933 interrupts = <GIC_SPI 2900 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 2901 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 2902 interrupt-names = "hfi", "gmu";
4936 2903
4937 clocks = <&gpucc GPU_ 2904 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 2905 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 2906 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 2907 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 2908 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 2909
4943 power-domains = <&gpu 2910 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 2911 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 2912 power-domain-names = "cx", "gx";
4946 2913
4947 iommus = <&adreno_smm 2914 iommus = <&adreno_smmu 5>;
4948 2915
4949 operating-points-v2 = 2916 operating-points-v2 = <&gmu_opp_table>;
4950 2917
4951 status = "disabled"; <<
4952 <<
4953 gmu_opp_table: opp-ta 2918 gmu_opp_table: opp-table {
4954 compatible = 2919 compatible = "operating-points-v2";
4955 2920
4956 opp-400000000 2921 opp-400000000 {
4957 opp-h 2922 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 2923 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 2924 };
4960 2925
4961 opp-200000000 2926 opp-200000000 {
4962 opp-h 2927 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 2928 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 2929 };
4965 }; 2930 };
4966 }; 2931 };
4967 2932
4968 dispcc: clock-controller@af00 2933 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 2934 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 2935 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM <<
4972 <&gcc GCC_DI <<
4973 <&gcc GCC_DI <<
4974 <&mdss_dsi0_ <<
4975 <&mdss_dsi0_ <<
4976 <&mdss_dsi1_ <<
4977 <&mdss_dsi1_ <<
4978 <&usb_1_qmpp <<
4979 <&usb_1_qmpp <<
4980 clock-names = "bi_tcx <<
4981 "gcc_di <<
4982 "gcc_di <<
4983 "dsi0_p <<
4984 "dsi0_p <<
4985 "dsi1_p <<
4986 "dsi1_p <<
4987 "dp_lin <<
4988 "dp_vco <<
4989 #clock-cells = <1>; 2936 #clock-cells = <1>;
4990 #reset-cells = <1>; 2937 #reset-cells = <1>;
4991 #power-domain-cells = 2938 #power-domain-cells = <1>;
4992 }; 2939 };
4993 2940
4994 pdc_intc: interrupt-controlle 2941 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 2942 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 2943 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 2944 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 2945 #interrupt-cells = <2>;
4999 interrupt-parent = <& 2946 interrupt-parent = <&intc>;
5000 interrupt-controller; 2947 interrupt-controller;
5001 }; 2948 };
5002 2949
5003 pdc_reset: reset-controller@b 2950 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 2951 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 2952 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 2953 #reset-cells = <1>;
5007 }; 2954 };
5008 2955
5009 tsens0: thermal-sensor@c26300 2956 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 2957 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 2958 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 2959 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 2960 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 2961 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 2962 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 2963 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 2964 #thermal-sensor-cells = <1>;
5018 }; 2965 };
5019 2966
5020 tsens1: thermal-sensor@c26500 2967 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 2968 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 2969 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 2970 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 2971 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 2972 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 2973 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 2974 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 2975 #thermal-sensor-cells = <1>;
5029 }; 2976 };
5030 2977
5031 aoss_reset: reset-controller@ 2978 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 2979 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 2980 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 2981 #reset-cells = <1>;
5035 }; 2982 };
5036 2983
5037 aoss_qmp: power-management@c3 !! 2984 aoss_qmp: qmp@c300000 {
5038 compatible = "qcom,sd !! 2985 compatible = "qcom,sdm845-aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 2986 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 2987 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 2988 mboxes = <&apss_shared 0>;
5042 2989
5043 #clock-cells = <0>; 2990 #clock-cells = <0>;
>> 2991 #power-domain-cells = <1>;
5044 2992
5045 cx_cdev: cx { 2993 cx_cdev: cx {
5046 #cooling-cell 2994 #cooling-cells = <2>;
5047 }; 2995 };
5048 2996
5049 ebi_cdev: ebi { 2997 ebi_cdev: ebi {
5050 #cooling-cell 2998 #cooling-cells = <2>;
5051 }; 2999 };
5052 }; 3000 };
5053 3001
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 3002 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 3003 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 3004 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 3005 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 3006 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 3007 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 3008 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 3009 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 3010 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 3011 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 3012 qcom,ee = <0>;
5070 qcom,channel = <0>; 3013 qcom,channel = <0>;
5071 #address-cells = <2>; 3014 #address-cells = <2>;
5072 #size-cells = <0>; 3015 #size-cells = <0>;
5073 interrupt-controller; 3016 interrupt-controller;
5074 #interrupt-cells = <4 3017 #interrupt-cells = <4>;
5075 }; !! 3018 cell-index = <0>;
5076 <<
5077 sram@146bf000 { <<
5078 compatible = "qcom,sd <<
5079 reg = <0 0x146bf000 0 <<
5080 <<
5081 #address-cells = <1>; <<
5082 #size-cells = <1>; <<
5083 <<
5084 ranges = <0 0 0x146bf <<
5085 <<
5086 pil-reloc@94c { <<
5087 compatible = <<
5088 reg = <0x94c <<
5089 }; <<
5090 }; 3019 };
5091 3020
5092 apps_smmu: iommu@15000000 { 3021 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 3022 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 3023 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 3024 #iommu-cells = <2>;
5096 #global-interrupts = 3025 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 3026 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 3027 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 3028 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 3029 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 3030 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 3031 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 3032 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 3033 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 3034 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 3035 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 3036 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 3037 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 3038 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 3039 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 3040 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 3041 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 3042 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 3043 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 3044 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 3045 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 3046 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 3047 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 3048 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 3049 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 3050 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 3051 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 3052 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 3053 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 3054 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 3055 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 3056 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 3057 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 3058 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 3059 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 3060 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 3061 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 3062 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 3063 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 3064 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 3065 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 3066 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 3067 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 3068 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 3069 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 3070 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 3071 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 3072 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 3073 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 3074 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 3075 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 3076 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 3077 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 3078 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 3079 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 3080 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 3081 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 3082 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 3083 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 3084 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 3085 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 3086 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 3087 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 3088 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 3089 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 3090 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 3091 };
5163 3092
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 3093 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 3094 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 3095 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 3096 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 3097 #clock-cells = <1>;
5241 status = "disabled"; 3098 status = "disabled";
5242 }; 3099 };
5243 3100
5244 gladiator_noc: interconnect@1 <<
5245 compatible = "qcom,sd <<
5246 reg = <0 0x17900000 0 <<
5247 #interconnect-cells = <<
5248 qcom,bcm-voters = <&a <<
5249 }; <<
5250 <<
5251 watchdog@17980000 { 3101 watchdog@17980000 {
5252 compatible = "qcom,ap 3102 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 3103 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 3104 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI <<
5256 }; 3105 };
5257 3106
5258 apss_shared: mailbox@17990000 3107 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 3108 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 3109 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 3110 #mbox-cells = <1>;
5262 }; 3111 };
5263 3112
5264 apps_rsc: rsc@179c0000 { 3113 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 3114 label = "apps_rsc";
5266 compatible = "qcom,rp 3115 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 3116 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 3117 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 3118 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 3119 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 3120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 3121 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 3122 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 3123 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 3124 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 3125 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 3126 <SLEEP_TCS 3>,
5278 <WA 3127 <WAKE_TCS 3>,
5279 <CO 3128 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 <<
5282 apps_bcm_voter: bcm-v <<
5283 compatible = <<
5284 }; <<
5285 3129
5286 rpmhcc: clock-control 3130 rpmhcc: clock-controller {
5287 compatible = 3131 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 3132 #clock-cells = <1>;
5289 clock-names = 3133 clock-names = "xo";
5290 clocks = <&xo 3134 clocks = <&xo_board>;
5291 }; 3135 };
5292 3136
5293 rpmhpd: power-control 3137 rpmhpd: power-controller {
5294 compatible = 3138 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 3139 #power-domain-cells = <1>;
5296 operating-poi 3140 operating-points-v2 = <&rpmhpd_opp_table>;
5297 3141
5298 rpmhpd_opp_ta 3142 rpmhpd_opp_table: opp-table {
5299 compa 3143 compatible = "operating-points-v2";
5300 3144
5301 rpmhp 3145 rpmhpd_opp_ret: opp1 {
5302 3146 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 3147 };
5304 3148
5305 rpmhp 3149 rpmhpd_opp_min_svs: opp2 {
5306 3150 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 3151 };
5308 3152
5309 rpmhp 3153 rpmhpd_opp_low_svs: opp3 {
5310 3154 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 3155 };
5312 3156
5313 rpmhp 3157 rpmhpd_opp_svs: opp4 {
5314 3158 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 3159 };
5316 3160
5317 rpmhp 3161 rpmhpd_opp_svs_l1: opp5 {
5318 3162 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 3163 };
5320 3164
5321 rpmhp 3165 rpmhpd_opp_nom: opp6 {
5322 3166 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 3167 };
5324 3168
5325 rpmhp 3169 rpmhpd_opp_nom_l1: opp7 {
5326 3170 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 3171 };
5328 3172
5329 rpmhp 3173 rpmhpd_opp_nom_l2: opp8 {
5330 3174 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 3175 };
5332 3176
5333 rpmhp 3177 rpmhpd_opp_turbo: opp9 {
5334 3178 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 3179 };
5336 3180
5337 rpmhp 3181 rpmhpd_opp_turbo_l1: opp10 {
5338 3182 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 3183 };
5340 }; 3184 };
5341 }; 3185 };
>> 3186
>> 3187 rsc_hlos: interconnect {
>> 3188 compatible = "qcom,sdm845-rsc-hlos";
>> 3189 #interconnect-cells = <1>;
>> 3190 };
5342 }; 3191 };
5343 3192
5344 intc: interrupt-controller@17 3193 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 3194 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 3195 #address-cells = <2>;
5347 #size-cells = <2>; 3196 #size-cells = <2>;
5348 ranges; 3197 ranges;
5349 #interrupt-cells = <3 3198 #interrupt-cells = <3>;
5350 interrupt-controller; 3199 interrupt-controller;
5351 reg = <0 0x17a00000 0 3200 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 3201 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 3202 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 3203
5355 msi-controller@17a400 3204 msi-controller@17a40000 {
5356 compatible = 3205 compatible = "arm,gic-v3-its";
5357 msi-controlle 3206 msi-controller;
5358 #msi-cells = 3207 #msi-cells = <1>;
5359 reg = <0 0x17 3208 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 3209 status = "disabled";
5361 }; 3210 };
5362 }; 3211 };
5363 3212
5364 slimbam: dma-controller@17184 <<
5365 compatible = "qcom,ba <<
5366 qcom,controlled-remot <<
5367 reg = <0 0x17184000 0 <<
5368 num-channels = <31>; <<
5369 interrupts = <GIC_SPI <<
5370 #dma-cells = <1>; <<
5371 qcom,ee = <1>; <<
5372 qcom,num-ees = <2>; <<
5373 iommus = <&apps_smmu <<
5374 }; <<
5375 <<
5376 timer@17c90000 { 3213 timer@17c90000 {
5377 #address-cells = <1>; !! 3214 #address-cells = <2>;
5378 #size-cells = <1>; !! 3215 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 3216 ranges;
5380 compatible = "arm,arm 3217 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 3218 reg = <0 0x17c90000 0 0x1000>;
5382 3219
5383 frame@17ca0000 { 3220 frame@17ca0000 {
5384 frame-number 3221 frame-number = <0>;
5385 interrupts = 3222 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 3223 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 3224 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 3225 <0 0x17cb0000 0 0x1000>;
5389 }; 3226 };
5390 3227
5391 frame@17cc0000 { 3228 frame@17cc0000 {
5392 frame-number 3229 frame-number = <1>;
5393 interrupts = 3230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 3231 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 3232 status = "disabled";
5396 }; 3233 };
5397 3234
5398 frame@17cd0000 { 3235 frame@17cd0000 {
5399 frame-number 3236 frame-number = <2>;
5400 interrupts = 3237 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 3238 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 3239 status = "disabled";
5403 }; 3240 };
5404 3241
5405 frame@17ce0000 { 3242 frame@17ce0000 {
5406 frame-number 3243 frame-number = <3>;
5407 interrupts = 3244 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 3245 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 3246 status = "disabled";
5410 }; 3247 };
5411 3248
5412 frame@17cf0000 { 3249 frame@17cf0000 {
5413 frame-number 3250 frame-number = <4>;
5414 interrupts = 3251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 3252 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 3253 status = "disabled";
5417 }; 3254 };
5418 3255
5419 frame@17d00000 { 3256 frame@17d00000 {
5420 frame-number 3257 frame-number = <5>;
5421 interrupts = 3258 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 3259 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 3260 status = "disabled";
5424 }; 3261 };
5425 3262
5426 frame@17d10000 { 3263 frame@17d10000 {
5427 frame-number 3264 frame-number = <6>;
5428 interrupts = 3265 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 3266 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 3267 status = "disabled";
5431 }; 3268 };
5432 }; 3269 };
5433 3270
5434 osm_l3: interconnect@17d41000 <<
5435 compatible = "qcom,sd <<
5436 reg = <0 0x17d41000 0 <<
5437 <<
5438 clocks = <&rpmhcc RPM <<
5439 clock-names = "xo", " <<
5440 <<
5441 #interconnect-cells = <<
5442 }; <<
5443 <<
5444 cpufreq_hw: cpufreq@17d43000 3271 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 3272 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 3273 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 3274 reg-names = "freq-domain0", "freq-domain1";
5448 3275
5449 interrupts-extended = <<
5450 <<
5451 clocks = <&rpmhcc RPM 3276 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 3277 clock-names = "xo", "alternate";
5453 3278
5454 #freq-domain-cells = 3279 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 3280 };
5457 3281
5458 wifi: wifi@18800000 { 3282 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 3283 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 3284 status = "disabled";
5461 reg = <0 0x18800000 0 3285 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 3286 reg-names = "membase";
5463 memory-region = <&wla 3287 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 3288 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 3289 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 3290 interrupts =
5467 <GIC_SPI 414 3291 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 3292 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 3293 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 3294 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 3295 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 3296 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 3297 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 3298 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 3299 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 3300 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 3301 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 3302 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 3303 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 3304 };
5481 }; 3305 };
5482 3306
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 3307 thermal-zones {
5487 cpu0-thermal { 3308 cpu0-thermal {
5488 polling-delay-passive 3309 polling-delay-passive = <250>;
>> 3310 polling-delay = <1000>;
5489 3311
5490 thermal-sensors = <&t 3312 thermal-sensors = <&tsens0 1>;
5491 3313
5492 trips { 3314 trips {
5493 cpu0_alert0: 3315 cpu0_alert0: trip-point0 {
5494 tempe 3316 temperature = <90000>;
5495 hyste 3317 hysteresis = <2000>;
5496 type 3318 type = "passive";
5497 }; 3319 };
5498 3320
5499 cpu0_alert1: 3321 cpu0_alert1: trip-point1 {
5500 tempe 3322 temperature = <95000>;
5501 hyste 3323 hysteresis = <2000>;
5502 type 3324 type = "passive";
5503 }; 3325 };
5504 3326
5505 cpu0_crit: cp !! 3327 cpu0_crit: cpu_crit {
5506 tempe 3328 temperature = <110000>;
5507 hyste 3329 hysteresis = <1000>;
5508 type 3330 type = "critical";
5509 }; 3331 };
5510 }; 3332 };
>> 3333
>> 3334 cooling-maps {
>> 3335 map0 {
>> 3336 trip = <&cpu0_alert0>;
>> 3337 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3338 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3339 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3340 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3341 };
>> 3342 map1 {
>> 3343 trip = <&cpu0_alert1>;
>> 3344 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3345 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3346 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3347 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3348 };
>> 3349 };
5511 }; 3350 };
5512 3351
5513 cpu1-thermal { 3352 cpu1-thermal {
5514 polling-delay-passive 3353 polling-delay-passive = <250>;
>> 3354 polling-delay = <1000>;
5515 3355
5516 thermal-sensors = <&t 3356 thermal-sensors = <&tsens0 2>;
5517 3357
5518 trips { 3358 trips {
5519 cpu1_alert0: 3359 cpu1_alert0: trip-point0 {
5520 tempe 3360 temperature = <90000>;
5521 hyste 3361 hysteresis = <2000>;
5522 type 3362 type = "passive";
5523 }; 3363 };
5524 3364
5525 cpu1_alert1: 3365 cpu1_alert1: trip-point1 {
5526 tempe 3366 temperature = <95000>;
5527 hyste 3367 hysteresis = <2000>;
5528 type 3368 type = "passive";
5529 }; 3369 };
5530 3370
5531 cpu1_crit: cp !! 3371 cpu1_crit: cpu_crit {
5532 tempe 3372 temperature = <110000>;
5533 hyste 3373 hysteresis = <1000>;
5534 type 3374 type = "critical";
5535 }; 3375 };
5536 }; 3376 };
>> 3377
>> 3378 cooling-maps {
>> 3379 map0 {
>> 3380 trip = <&cpu1_alert0>;
>> 3381 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3382 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3383 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3384 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3385 };
>> 3386 map1 {
>> 3387 trip = <&cpu1_alert1>;
>> 3388 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3389 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3390 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3391 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3392 };
>> 3393 };
5537 }; 3394 };
5538 3395
5539 cpu2-thermal { 3396 cpu2-thermal {
5540 polling-delay-passive 3397 polling-delay-passive = <250>;
>> 3398 polling-delay = <1000>;
5541 3399
5542 thermal-sensors = <&t 3400 thermal-sensors = <&tsens0 3>;
5543 3401
5544 trips { 3402 trips {
5545 cpu2_alert0: 3403 cpu2_alert0: trip-point0 {
5546 tempe 3404 temperature = <90000>;
5547 hyste 3405 hysteresis = <2000>;
5548 type 3406 type = "passive";
5549 }; 3407 };
5550 3408
5551 cpu2_alert1: 3409 cpu2_alert1: trip-point1 {
5552 tempe 3410 temperature = <95000>;
5553 hyste 3411 hysteresis = <2000>;
5554 type 3412 type = "passive";
5555 }; 3413 };
5556 3414
5557 cpu2_crit: cp !! 3415 cpu2_crit: cpu_crit {
5558 tempe 3416 temperature = <110000>;
5559 hyste 3417 hysteresis = <1000>;
5560 type 3418 type = "critical";
5561 }; 3419 };
5562 }; 3420 };
>> 3421
>> 3422 cooling-maps {
>> 3423 map0 {
>> 3424 trip = <&cpu2_alert0>;
>> 3425 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3426 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3427 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3428 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3429 };
>> 3430 map1 {
>> 3431 trip = <&cpu2_alert1>;
>> 3432 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3433 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3434 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3435 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3436 };
>> 3437 };
5563 }; 3438 };
5564 3439
5565 cpu3-thermal { 3440 cpu3-thermal {
5566 polling-delay-passive 3441 polling-delay-passive = <250>;
>> 3442 polling-delay = <1000>;
5567 3443
5568 thermal-sensors = <&t 3444 thermal-sensors = <&tsens0 4>;
5569 3445
5570 trips { 3446 trips {
5571 cpu3_alert0: 3447 cpu3_alert0: trip-point0 {
5572 tempe 3448 temperature = <90000>;
5573 hyste 3449 hysteresis = <2000>;
5574 type 3450 type = "passive";
5575 }; 3451 };
5576 3452
5577 cpu3_alert1: 3453 cpu3_alert1: trip-point1 {
5578 tempe 3454 temperature = <95000>;
5579 hyste 3455 hysteresis = <2000>;
5580 type 3456 type = "passive";
5581 }; 3457 };
5582 3458
5583 cpu3_crit: cp !! 3459 cpu3_crit: cpu_crit {
5584 tempe 3460 temperature = <110000>;
5585 hyste 3461 hysteresis = <1000>;
5586 type 3462 type = "critical";
5587 }; 3463 };
5588 }; 3464 };
>> 3465
>> 3466 cooling-maps {
>> 3467 map0 {
>> 3468 trip = <&cpu3_alert0>;
>> 3469 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3470 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3471 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3472 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3473 };
>> 3474 map1 {
>> 3475 trip = <&cpu3_alert1>;
>> 3476 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3477 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3478 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3479 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3480 };
>> 3481 };
5589 }; 3482 };
5590 3483
5591 cpu4-thermal { 3484 cpu4-thermal {
5592 polling-delay-passive 3485 polling-delay-passive = <250>;
>> 3486 polling-delay = <1000>;
5593 3487
5594 thermal-sensors = <&t 3488 thermal-sensors = <&tsens0 7>;
5595 3489
5596 trips { 3490 trips {
5597 cpu4_alert0: 3491 cpu4_alert0: trip-point0 {
5598 tempe 3492 temperature = <90000>;
5599 hyste 3493 hysteresis = <2000>;
5600 type 3494 type = "passive";
5601 }; 3495 };
5602 3496
5603 cpu4_alert1: 3497 cpu4_alert1: trip-point1 {
5604 tempe 3498 temperature = <95000>;
5605 hyste 3499 hysteresis = <2000>;
5606 type 3500 type = "passive";
5607 }; 3501 };
5608 3502
5609 cpu4_crit: cp !! 3503 cpu4_crit: cpu_crit {
5610 tempe 3504 temperature = <110000>;
5611 hyste 3505 hysteresis = <1000>;
5612 type 3506 type = "critical";
5613 }; 3507 };
5614 }; 3508 };
>> 3509
>> 3510 cooling-maps {
>> 3511 map0 {
>> 3512 trip = <&cpu4_alert0>;
>> 3513 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3514 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3515 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3516 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3517 };
>> 3518 map1 {
>> 3519 trip = <&cpu4_alert1>;
>> 3520 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3521 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3522 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3523 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3524 };
>> 3525 };
5615 }; 3526 };
5616 3527
5617 cpu5-thermal { 3528 cpu5-thermal {
5618 polling-delay-passive 3529 polling-delay-passive = <250>;
>> 3530 polling-delay = <1000>;
5619 3531
5620 thermal-sensors = <&t 3532 thermal-sensors = <&tsens0 8>;
5621 3533
5622 trips { 3534 trips {
5623 cpu5_alert0: 3535 cpu5_alert0: trip-point0 {
5624 tempe 3536 temperature = <90000>;
5625 hyste 3537 hysteresis = <2000>;
5626 type 3538 type = "passive";
5627 }; 3539 };
5628 3540
5629 cpu5_alert1: 3541 cpu5_alert1: trip-point1 {
5630 tempe 3542 temperature = <95000>;
5631 hyste 3543 hysteresis = <2000>;
5632 type 3544 type = "passive";
5633 }; 3545 };
5634 3546
5635 cpu5_crit: cp !! 3547 cpu5_crit: cpu_crit {
5636 tempe 3548 temperature = <110000>;
5637 hyste 3549 hysteresis = <1000>;
5638 type 3550 type = "critical";
5639 }; 3551 };
5640 }; 3552 };
>> 3553
>> 3554 cooling-maps {
>> 3555 map0 {
>> 3556 trip = <&cpu5_alert0>;
>> 3557 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3558 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3559 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3560 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3561 };
>> 3562 map1 {
>> 3563 trip = <&cpu5_alert1>;
>> 3564 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3565 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3566 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3567 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3568 };
>> 3569 };
5641 }; 3570 };
5642 3571
5643 cpu6-thermal { 3572 cpu6-thermal {
5644 polling-delay-passive 3573 polling-delay-passive = <250>;
>> 3574 polling-delay = <1000>;
5645 3575
5646 thermal-sensors = <&t 3576 thermal-sensors = <&tsens0 9>;
5647 3577
5648 trips { 3578 trips {
5649 cpu6_alert0: 3579 cpu6_alert0: trip-point0 {
5650 tempe 3580 temperature = <90000>;
5651 hyste 3581 hysteresis = <2000>;
5652 type 3582 type = "passive";
5653 }; 3583 };
5654 3584
5655 cpu6_alert1: 3585 cpu6_alert1: trip-point1 {
5656 tempe 3586 temperature = <95000>;
5657 hyste 3587 hysteresis = <2000>;
5658 type 3588 type = "passive";
5659 }; 3589 };
5660 3590
5661 cpu6_crit: cp !! 3591 cpu6_crit: cpu_crit {
5662 tempe 3592 temperature = <110000>;
5663 hyste 3593 hysteresis = <1000>;
5664 type 3594 type = "critical";
5665 }; 3595 };
5666 }; 3596 };
>> 3597
>> 3598 cooling-maps {
>> 3599 map0 {
>> 3600 trip = <&cpu6_alert0>;
>> 3601 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3602 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3603 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3604 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3605 };
>> 3606 map1 {
>> 3607 trip = <&cpu6_alert1>;
>> 3608 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3609 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3610 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3611 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3612 };
>> 3613 };
5667 }; 3614 };
5668 3615
5669 cpu7-thermal { 3616 cpu7-thermal {
5670 polling-delay-passive 3617 polling-delay-passive = <250>;
>> 3618 polling-delay = <1000>;
5671 3619
5672 thermal-sensors = <&t 3620 thermal-sensors = <&tsens0 10>;
5673 3621
5674 trips { 3622 trips {
5675 cpu7_alert0: 3623 cpu7_alert0: trip-point0 {
5676 tempe 3624 temperature = <90000>;
5677 hyste 3625 hysteresis = <2000>;
5678 type 3626 type = "passive";
5679 }; 3627 };
5680 3628
5681 cpu7_alert1: 3629 cpu7_alert1: trip-point1 {
5682 tempe 3630 temperature = <95000>;
5683 hyste 3631 hysteresis = <2000>;
5684 type 3632 type = "passive";
5685 }; 3633 };
5686 3634
5687 cpu7_crit: cp !! 3635 cpu7_crit: cpu_crit {
5688 tempe 3636 temperature = <110000>;
5689 hyste 3637 hysteresis = <1000>;
5690 type 3638 type = "critical";
5691 }; 3639 };
5692 }; 3640 };
>> 3641
>> 3642 cooling-maps {
>> 3643 map0 {
>> 3644 trip = <&cpu7_alert0>;
>> 3645 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3646 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3647 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3648 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3649 };
>> 3650 map1 {
>> 3651 trip = <&cpu7_alert1>;
>> 3652 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3653 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3654 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 3655 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 3656 };
>> 3657 };
5693 }; 3658 };
5694 3659
5695 aoss0-thermal { 3660 aoss0-thermal {
5696 polling-delay-passive 3661 polling-delay-passive = <250>;
>> 3662 polling-delay = <1000>;
5697 3663
5698 thermal-sensors = <&t 3664 thermal-sensors = <&tsens0 0>;
5699 3665
5700 trips { 3666 trips {
5701 aoss0_alert0: 3667 aoss0_alert0: trip-point0 {
5702 tempe 3668 temperature = <90000>;
5703 hyste 3669 hysteresis = <2000>;
5704 type 3670 type = "hot";
5705 }; 3671 };
5706 }; 3672 };
5707 }; 3673 };
5708 3674
5709 cluster0-thermal { 3675 cluster0-thermal {
5710 polling-delay-passive 3676 polling-delay-passive = <250>;
>> 3677 polling-delay = <1000>;
5711 3678
5712 thermal-sensors = <&t 3679 thermal-sensors = <&tsens0 5>;
5713 3680
5714 trips { 3681 trips {
5715 cluster0_aler 3682 cluster0_alert0: trip-point0 {
5716 tempe 3683 temperature = <90000>;
5717 hyste 3684 hysteresis = <2000>;
5718 type 3685 type = "hot";
5719 }; 3686 };
5720 cluster0_crit !! 3687 cluster0_crit: cluster0_crit {
5721 tempe 3688 temperature = <110000>;
5722 hyste 3689 hysteresis = <2000>;
5723 type 3690 type = "critical";
5724 }; 3691 };
5725 }; 3692 };
5726 }; 3693 };
5727 3694
5728 cluster1-thermal { 3695 cluster1-thermal {
5729 polling-delay-passive 3696 polling-delay-passive = <250>;
>> 3697 polling-delay = <1000>;
5730 3698
5731 thermal-sensors = <&t 3699 thermal-sensors = <&tsens0 6>;
5732 3700
5733 trips { 3701 trips {
5734 cluster1_aler 3702 cluster1_alert0: trip-point0 {
5735 tempe 3703 temperature = <90000>;
5736 hyste 3704 hysteresis = <2000>;
5737 type 3705 type = "hot";
5738 }; 3706 };
5739 cluster1_crit !! 3707 cluster1_crit: cluster1_crit {
5740 tempe 3708 temperature = <110000>;
5741 hyste 3709 hysteresis = <2000>;
5742 type 3710 type = "critical";
5743 }; 3711 };
5744 }; 3712 };
5745 }; 3713 };
5746 3714
5747 gpu-top-thermal { !! 3715 gpu-thermal-top {
5748 polling-delay-passive 3716 polling-delay-passive = <250>;
>> 3717 polling-delay = <1000>;
5749 3718
5750 thermal-sensors = <&t 3719 thermal-sensors = <&tsens0 11>;
5751 3720
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 3721 trips {
5760 gpu_top_alert !! 3722 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 3723 temperature = <90000>;
5768 hyste !! 3724 hysteresis = <2000>;
5769 type 3725 type = "hot";
5770 }; 3726 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 3727 };
5778 }; 3728 };
5779 3729
5780 gpu-bottom-thermal { !! 3730 gpu-thermal-bottom {
5781 polling-delay-passive 3731 polling-delay-passive = <250>;
>> 3732 polling-delay = <1000>;
5782 3733
5783 thermal-sensors = <&t 3734 thermal-sensors = <&tsens0 12>;
5784 3735
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 3736 trips {
5793 gpu_bottom_al !! 3737 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 3738 temperature = <90000>;
5801 hyste !! 3739 hysteresis = <2000>;
5802 type 3740 type = "hot";
5803 }; 3741 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 3742 };
5811 }; 3743 };
5812 3744
5813 aoss1-thermal { 3745 aoss1-thermal {
5814 polling-delay-passive 3746 polling-delay-passive = <250>;
>> 3747 polling-delay = <1000>;
5815 3748
5816 thermal-sensors = <&t 3749 thermal-sensors = <&tsens1 0>;
5817 3750
5818 trips { 3751 trips {
5819 aoss1_alert0: 3752 aoss1_alert0: trip-point0 {
5820 tempe 3753 temperature = <90000>;
5821 hyste 3754 hysteresis = <2000>;
5822 type 3755 type = "hot";
5823 }; 3756 };
5824 }; 3757 };
5825 }; 3758 };
5826 3759
5827 q6-modem-thermal { 3760 q6-modem-thermal {
5828 polling-delay-passive 3761 polling-delay-passive = <250>;
>> 3762 polling-delay = <1000>;
5829 3763
5830 thermal-sensors = <&t 3764 thermal-sensors = <&tsens1 1>;
5831 3765
5832 trips { 3766 trips {
5833 q6_modem_aler 3767 q6_modem_alert0: trip-point0 {
5834 tempe 3768 temperature = <90000>;
5835 hyste 3769 hysteresis = <2000>;
5836 type 3770 type = "hot";
5837 }; 3771 };
5838 }; 3772 };
5839 }; 3773 };
5840 3774
5841 mem-thermal { 3775 mem-thermal {
5842 polling-delay-passive 3776 polling-delay-passive = <250>;
>> 3777 polling-delay = <1000>;
5843 3778
5844 thermal-sensors = <&t 3779 thermal-sensors = <&tsens1 2>;
5845 3780
5846 trips { 3781 trips {
5847 mem_alert0: t 3782 mem_alert0: trip-point0 {
5848 tempe 3783 temperature = <90000>;
5849 hyste 3784 hysteresis = <2000>;
5850 type 3785 type = "hot";
5851 }; 3786 };
5852 }; 3787 };
5853 }; 3788 };
5854 3789
5855 wlan-thermal { 3790 wlan-thermal {
5856 polling-delay-passive 3791 polling-delay-passive = <250>;
>> 3792 polling-delay = <1000>;
5857 3793
5858 thermal-sensors = <&t 3794 thermal-sensors = <&tsens1 3>;
5859 3795
5860 trips { 3796 trips {
5861 wlan_alert0: 3797 wlan_alert0: trip-point0 {
5862 tempe 3798 temperature = <90000>;
5863 hyste 3799 hysteresis = <2000>;
5864 type 3800 type = "hot";
5865 }; 3801 };
5866 }; 3802 };
5867 }; 3803 };
5868 3804
5869 q6-hvx-thermal { 3805 q6-hvx-thermal {
5870 polling-delay-passive 3806 polling-delay-passive = <250>;
>> 3807 polling-delay = <1000>;
5871 3808
5872 thermal-sensors = <&t 3809 thermal-sensors = <&tsens1 4>;
5873 3810
5874 trips { 3811 trips {
5875 q6_hvx_alert0 3812 q6_hvx_alert0: trip-point0 {
5876 tempe 3813 temperature = <90000>;
5877 hyste 3814 hysteresis = <2000>;
5878 type 3815 type = "hot";
5879 }; 3816 };
5880 }; 3817 };
5881 }; 3818 };
5882 3819
5883 camera-thermal { 3820 camera-thermal {
5884 polling-delay-passive 3821 polling-delay-passive = <250>;
>> 3822 polling-delay = <1000>;
5885 3823
5886 thermal-sensors = <&t 3824 thermal-sensors = <&tsens1 5>;
5887 3825
5888 trips { 3826 trips {
5889 camera_alert0 3827 camera_alert0: trip-point0 {
5890 tempe 3828 temperature = <90000>;
5891 hyste 3829 hysteresis = <2000>;
5892 type 3830 type = "hot";
5893 }; 3831 };
5894 }; 3832 };
5895 }; 3833 };
5896 3834
5897 video-thermal { 3835 video-thermal {
5898 polling-delay-passive 3836 polling-delay-passive = <250>;
>> 3837 polling-delay = <1000>;
5899 3838
5900 thermal-sensors = <&t 3839 thermal-sensors = <&tsens1 6>;
5901 3840
5902 trips { 3841 trips {
5903 video_alert0: 3842 video_alert0: trip-point0 {
5904 tempe 3843 temperature = <90000>;
5905 hyste 3844 hysteresis = <2000>;
5906 type 3845 type = "hot";
5907 }; 3846 };
5908 }; 3847 };
5909 }; 3848 };
5910 3849
5911 modem-thermal { 3850 modem-thermal {
5912 polling-delay-passive 3851 polling-delay-passive = <250>;
>> 3852 polling-delay = <1000>;
5913 3853
5914 thermal-sensors = <&t 3854 thermal-sensors = <&tsens1 7>;
5915 3855
5916 trips { 3856 trips {
5917 modem_alert0: 3857 modem_alert0: trip-point0 {
5918 tempe 3858 temperature = <90000>;
5919 hyste 3859 hysteresis = <2000>;
5920 type 3860 type = "hot";
5921 }; 3861 };
5922 }; 3862 };
5923 }; 3863 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 3864 };
5933 }; 3865 };
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