1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> <<
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 <<
20 #include <dt-bindings/interconnect/qcom,sdm845 15 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 16 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 21 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 23 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 24 #include <dt-bindings/thermal/thermal.h>
31 25
32 / { 26 / {
33 interrupt-parent = <&intc>; 27 interrupt-parent = <&intc>;
34 28
35 #address-cells = <2>; 29 #address-cells = <2>;
36 #size-cells = <2>; 30 #size-cells = <2>;
37 31
38 aliases { 32 aliases {
39 i2c0 = &i2c0; 33 i2c0 = &i2c0;
40 i2c1 = &i2c1; 34 i2c1 = &i2c1;
41 i2c2 = &i2c2; 35 i2c2 = &i2c2;
42 i2c3 = &i2c3; 36 i2c3 = &i2c3;
43 i2c4 = &i2c4; 37 i2c4 = &i2c4;
44 i2c5 = &i2c5; 38 i2c5 = &i2c5;
45 i2c6 = &i2c6; 39 i2c6 = &i2c6;
46 i2c7 = &i2c7; 40 i2c7 = &i2c7;
47 i2c8 = &i2c8; 41 i2c8 = &i2c8;
48 i2c9 = &i2c9; 42 i2c9 = &i2c9;
49 i2c10 = &i2c10; 43 i2c10 = &i2c10;
50 i2c11 = &i2c11; 44 i2c11 = &i2c11;
51 i2c12 = &i2c12; 45 i2c12 = &i2c12;
52 i2c13 = &i2c13; 46 i2c13 = &i2c13;
53 i2c14 = &i2c14; 47 i2c14 = &i2c14;
54 i2c15 = &i2c15; 48 i2c15 = &i2c15;
55 spi0 = &spi0; 49 spi0 = &spi0;
56 spi1 = &spi1; 50 spi1 = &spi1;
57 spi2 = &spi2; 51 spi2 = &spi2;
58 spi3 = &spi3; 52 spi3 = &spi3;
59 spi4 = &spi4; 53 spi4 = &spi4;
60 spi5 = &spi5; 54 spi5 = &spi5;
61 spi6 = &spi6; 55 spi6 = &spi6;
62 spi7 = &spi7; 56 spi7 = &spi7;
63 spi8 = &spi8; 57 spi8 = &spi8;
64 spi9 = &spi9; 58 spi9 = &spi9;
65 spi10 = &spi10; 59 spi10 = &spi10;
66 spi11 = &spi11; 60 spi11 = &spi11;
67 spi12 = &spi12; 61 spi12 = &spi12;
68 spi13 = &spi13; 62 spi13 = &spi13;
69 spi14 = &spi14; 63 spi14 = &spi14;
70 spi15 = &spi15; 64 spi15 = &spi15;
71 }; 65 };
72 66
73 chosen { }; 67 chosen { };
74 68
75 clocks { !! 69 memory@80000000 {
76 xo_board: xo-board { !! 70 device_type = "memory";
77 compatible = "fixed-cl !! 71 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 72 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 73 };
80 clock-output-names = " !! 74
>> 75 reserved-memory {
>> 76 #address-cells = <2>;
>> 77 #size-cells = <2>;
>> 78 ranges;
>> 79
>> 80 hyp_mem: memory@85700000 {
>> 81 reg = <0 0x85700000 0 0x600000>;
>> 82 no-map;
81 }; 83 };
82 84
83 sleep_clk: sleep-clk { !! 85 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 86 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 87 no-map;
86 clock-frequency = <327 !! 88 };
>> 89
>> 90 aop_mem: memory@85fc0000 {
>> 91 reg = <0 0x85fc0000 0 0x20000>;
>> 92 no-map;
>> 93 };
>> 94
>> 95 aop_cmd_db_mem: memory@85fe0000 {
>> 96 compatible = "qcom,cmd-db";
>> 97 reg = <0x0 0x85fe0000 0 0x20000>;
>> 98 no-map;
>> 99 };
>> 100
>> 101 smem_mem: memory@86000000 {
>> 102 reg = <0x0 0x86000000 0 0x200000>;
>> 103 no-map;
>> 104 };
>> 105
>> 106 tz_mem: memory@86200000 {
>> 107 reg = <0 0x86200000 0 0x2d00000>;
>> 108 no-map;
>> 109 };
>> 110
>> 111 rmtfs_mem: memory@88f00000 {
>> 112 compatible = "qcom,rmtfs-mem";
>> 113 reg = <0 0x88f00000 0 0x200000>;
>> 114 no-map;
>> 115
>> 116 qcom,client-id = <1>;
>> 117 qcom,vmid = <15>;
>> 118 };
>> 119
>> 120 qseecom_mem: memory@8ab00000 {
>> 121 reg = <0 0x8ab00000 0 0x1400000>;
>> 122 no-map;
>> 123 };
>> 124
>> 125 camera_mem: memory@8bf00000 {
>> 126 reg = <0 0x8bf00000 0 0x500000>;
>> 127 no-map;
>> 128 };
>> 129
>> 130 ipa_fw_mem: memory@8c400000 {
>> 131 reg = <0 0x8c400000 0 0x10000>;
>> 132 no-map;
>> 133 };
>> 134
>> 135 ipa_gsi_mem: memory@8c410000 {
>> 136 reg = <0 0x8c410000 0 0x5000>;
>> 137 no-map;
>> 138 };
>> 139
>> 140 gpu_mem: memory@8c415000 {
>> 141 reg = <0 0x8c415000 0 0x2000>;
>> 142 no-map;
>> 143 };
>> 144
>> 145 adsp_mem: memory@8c500000 {
>> 146 reg = <0 0x8c500000 0 0x1a00000>;
>> 147 no-map;
>> 148 };
>> 149
>> 150 wlan_msa_mem: memory@8df00000 {
>> 151 reg = <0 0x8df00000 0 0x100000>;
>> 152 no-map;
>> 153 };
>> 154
>> 155 mpss_region: memory@8e000000 {
>> 156 reg = <0 0x8e000000 0 0x7800000>;
>> 157 no-map;
>> 158 };
>> 159
>> 160 venus_mem: memory@95800000 {
>> 161 reg = <0 0x95800000 0 0x500000>;
>> 162 no-map;
>> 163 };
>> 164
>> 165 cdsp_mem: memory@95d00000 {
>> 166 reg = <0 0x95d00000 0 0x800000>;
>> 167 no-map;
>> 168 };
>> 169
>> 170 mba_region: memory@96500000 {
>> 171 reg = <0 0x96500000 0 0x200000>;
>> 172 no-map;
>> 173 };
>> 174
>> 175 slpi_mem: memory@96700000 {
>> 176 reg = <0 0x96700000 0 0x1400000>;
>> 177 no-map;
>> 178 };
>> 179
>> 180 spss_mem: memory@97b00000 {
>> 181 reg = <0 0x97b00000 0 0x100000>;
>> 182 no-map;
87 }; 183 };
88 }; 184 };
89 185
90 cpus: cpus { !! 186 cpus {
91 #address-cells = <2>; 187 #address-cells = <2>;
92 #size-cells = <0>; 188 #size-cells = <0>;
93 189
94 CPU0: cpu@0 { 190 CPU0: cpu@0 {
95 device_type = "cpu"; 191 device_type = "cpu";
96 compatible = "qcom,kry 192 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 193 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 194 enable-method = "psci";
100 capacity-dmips-mhz = < !! 195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101 dynamic-power-coeffici !! 196 &LITTLE_CPU_SLEEP_1
>> 197 &CLUSTER_SLEEP_0>;
>> 198 capacity-dmips-mhz = <607>;
>> 199 dynamic-power-coefficient = <100>;
102 qcom,freq-domain = <&c 200 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = <<
104 interconnects = <&glad <<
105 <&osm_ <<
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 201 #cooling-cells = <2>;
109 next-level-cache = <&L 202 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 203 L2_0: l2-cache {
111 compatible = " 204 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 205 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 206 L3_0: l3-cache {
116 compat !! 207 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 208 };
120 }; 209 };
121 }; 210 };
122 211
123 CPU1: cpu@100 { 212 CPU1: cpu@100 {
124 device_type = "cpu"; 213 device_type = "cpu";
125 compatible = "qcom,kry 214 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 215 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 216 enable-method = "psci";
129 capacity-dmips-mhz = < !! 217 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130 dynamic-power-coeffici !! 218 &LITTLE_CPU_SLEEP_1
>> 219 &CLUSTER_SLEEP_0>;
>> 220 capacity-dmips-mhz = <607>;
>> 221 dynamic-power-coefficient = <100>;
131 qcom,freq-domain = <&c 222 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <<
133 interconnects = <&glad <<
134 <&osm_ <<
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 223 #cooling-cells = <2>;
138 next-level-cache = <&L 224 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 225 L2_100: l2-cache {
140 compatible = " 226 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 227 next-level-cache = <&L3_0>;
144 }; 228 };
145 }; 229 };
146 230
147 CPU2: cpu@200 { 231 CPU2: cpu@200 {
148 device_type = "cpu"; 232 device_type = "cpu";
149 compatible = "qcom,kry 233 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 234 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 235 enable-method = "psci";
153 capacity-dmips-mhz = < !! 236 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154 dynamic-power-coeffici !! 237 &LITTLE_CPU_SLEEP_1
>> 238 &CLUSTER_SLEEP_0>;
>> 239 capacity-dmips-mhz = <607>;
>> 240 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&c 241 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = <<
157 interconnects = <&glad <<
158 <&osm_ <<
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 242 #cooling-cells = <2>;
162 next-level-cache = <&L 243 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 244 L2_200: l2-cache {
164 compatible = " 245 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 246 next-level-cache = <&L3_0>;
168 }; 247 };
169 }; 248 };
170 249
171 CPU3: cpu@300 { 250 CPU3: cpu@300 {
172 device_type = "cpu"; 251 device_type = "cpu";
173 compatible = "qcom,kry 252 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 253 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 254 enable-method = "psci";
177 capacity-dmips-mhz = < !! 255 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178 dynamic-power-coeffici !! 256 &LITTLE_CPU_SLEEP_1
>> 257 &CLUSTER_SLEEP_0>;
>> 258 capacity-dmips-mhz = <607>;
>> 259 dynamic-power-coefficient = <100>;
179 qcom,freq-domain = <&c 260 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = <<
181 interconnects = <&glad <<
182 <&osm_ <<
183 #cooling-cells = <2>; 261 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 262 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 263 L2_300: l2-cache {
188 compatible = " 264 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 265 next-level-cache = <&L3_0>;
192 }; 266 };
193 }; 267 };
194 268
195 CPU4: cpu@400 { 269 CPU4: cpu@400 {
196 device_type = "cpu"; 270 device_type = "cpu";
197 compatible = "qcom,kry 271 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 272 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 273 enable-method = "psci";
201 capacity-dmips-mhz = < 274 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici !! 275 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 276 &BIG_CPU_SLEEP_1
>> 277 &CLUSTER_SLEEP_0>;
>> 278 dynamic-power-coefficient = <396>;
203 qcom,freq-domain = <&c 279 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = <<
205 interconnects = <&glad <<
206 <&osm_ <<
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 280 #cooling-cells = <2>;
210 next-level-cache = <&L 281 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 282 L2_400: l2-cache {
212 compatible = " 283 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 284 next-level-cache = <&L3_0>;
216 }; 285 };
217 }; 286 };
218 287
219 CPU5: cpu@500 { 288 CPU5: cpu@500 {
220 device_type = "cpu"; 289 device_type = "cpu";
221 compatible = "qcom,kry 290 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 291 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 292 enable-method = "psci";
225 capacity-dmips-mhz = < 293 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici !! 294 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 295 &BIG_CPU_SLEEP_1
>> 296 &CLUSTER_SLEEP_0>;
>> 297 dynamic-power-coefficient = <396>;
227 qcom,freq-domain = <&c 298 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = <<
229 interconnects = <&glad <<
230 <&osm_ <<
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 299 #cooling-cells = <2>;
234 next-level-cache = <&L 300 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 301 L2_500: l2-cache {
236 compatible = " 302 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 303 next-level-cache = <&L3_0>;
240 }; 304 };
241 }; 305 };
242 306
243 CPU6: cpu@600 { 307 CPU6: cpu@600 {
244 device_type = "cpu"; 308 device_type = "cpu";
245 compatible = "qcom,kry 309 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 310 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 311 enable-method = "psci";
249 capacity-dmips-mhz = < 312 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici !! 313 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 314 &BIG_CPU_SLEEP_1
>> 315 &CLUSTER_SLEEP_0>;
>> 316 dynamic-power-coefficient = <396>;
251 qcom,freq-domain = <&c 317 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = <<
253 interconnects = <&glad <<
254 <&osm_ <<
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 318 #cooling-cells = <2>;
258 next-level-cache = <&L 319 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 320 L2_600: l2-cache {
260 compatible = " 321 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 322 next-level-cache = <&L3_0>;
264 }; 323 };
265 }; 324 };
266 325
267 CPU7: cpu@700 { 326 CPU7: cpu@700 {
268 device_type = "cpu"; 327 device_type = "cpu";
269 compatible = "qcom,kry 328 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 329 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 330 enable-method = "psci";
273 capacity-dmips-mhz = < 331 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici !! 332 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 333 &BIG_CPU_SLEEP_1
>> 334 &CLUSTER_SLEEP_0>;
>> 335 dynamic-power-coefficient = <396>;
275 qcom,freq-domain = <&c 336 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = <<
277 interconnects = <&glad <<
278 <&osm_ <<
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 337 #cooling-cells = <2>;
282 next-level-cache = <&L 338 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 339 L2_700: l2-cache {
284 compatible = " 340 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 341 next-level-cache = <&L3_0>;
288 }; 342 };
289 }; 343 };
290 344
291 cpu-map { 345 cpu-map {
292 cluster0 { 346 cluster0 {
293 core0 { 347 core0 {
294 cpu = 348 cpu = <&CPU0>;
295 }; 349 };
296 350
297 core1 { 351 core1 {
298 cpu = 352 cpu = <&CPU1>;
299 }; 353 };
300 354
301 core2 { 355 core2 {
302 cpu = 356 cpu = <&CPU2>;
303 }; 357 };
304 358
305 core3 { 359 core3 {
306 cpu = 360 cpu = <&CPU3>;
307 }; 361 };
308 362
309 core4 { 363 core4 {
310 cpu = 364 cpu = <&CPU4>;
311 }; 365 };
312 366
313 core5 { 367 core5 {
314 cpu = 368 cpu = <&CPU5>;
315 }; 369 };
316 370
317 core6 { 371 core6 {
318 cpu = 372 cpu = <&CPU6>;
319 }; 373 };
320 374
321 core7 { 375 core7 {
322 cpu = 376 cpu = <&CPU7>;
323 }; 377 };
324 }; 378 };
325 }; 379 };
326 380
327 cpu_idle_states: idle-states { !! 381 idle-states {
328 entry-method = "psci"; 382 entry-method = "psci";
329 383
330 LITTLE_CPU_SLEEP_0: cp 384 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 385 compatible = "arm,idle-state";
332 idle-state-nam !! 386 idle-state-name = "little-power-down";
333 arm,psci-suspe !! 387 arm,psci-suspend-param = <0x40000003>;
334 entry-latency- 388 entry-latency-us = <350>;
335 exit-latency-u 389 exit-latency-us = <461>;
336 min-residency- 390 min-residency-us = <1890>;
337 local-timer-st 391 local-timer-stop;
338 }; 392 };
339 393
340 BIG_CPU_SLEEP_0: cpu-s !! 394 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341 compatible = " 395 compatible = "arm,idle-state";
342 idle-state-nam !! 396 idle-state-name = "little-rail-power-down";
343 arm,psci-suspe 397 arm,psci-suspend-param = <0x40000004>;
>> 398 entry-latency-us = <360>;
>> 399 exit-latency-us = <531>;
>> 400 min-residency-us = <3934>;
>> 401 local-timer-stop;
>> 402 };
>> 403
>> 404 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> 405 compatible = "arm,idle-state";
>> 406 idle-state-name = "big-power-down";
>> 407 arm,psci-suspend-param = <0x40000003>;
344 entry-latency- 408 entry-latency-us = <264>;
345 exit-latency-u 409 exit-latency-us = <621>;
346 min-residency- 410 min-residency-us = <952>;
347 local-timer-st 411 local-timer-stop;
348 }; 412 };
349 }; <<
350 413
351 domain-idle-states { !! 414 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
>> 415 compatible = "arm,idle-state";
>> 416 idle-state-name = "big-rail-power-down";
>> 417 arm,psci-suspend-param = <0x40000004>;
>> 418 entry-latency-us = <702>;
>> 419 exit-latency-us = <1061>;
>> 420 min-residency-us = <4488>;
>> 421 local-timer-stop;
>> 422 };
>> 423
352 CLUSTER_SLEEP_0: clust 424 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " !! 425 compatible = "arm,idle-state";
354 arm,psci-suspe !! 426 idle-state-name = "cluster-power-down";
>> 427 arm,psci-suspend-param = <0x400000F4>;
355 entry-latency- 428 entry-latency-us = <3263>;
356 exit-latency-u 429 exit-latency-us = <6562>;
357 min-residency- 430 min-residency-us = <9987>;
>> 431 local-timer-stop;
358 }; 432 };
359 }; 433 };
360 }; 434 };
361 435
362 firmware { <<
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points <<
376 opp-shared; <<
377 <<
378 cpu0_opp1: opp-300000000 { <<
379 opp-hz = /bits/ 64 <30 <<
380 opp-peak-kBps = <80000 <<
381 }; <<
382 <<
383 cpu0_opp2: opp-403200000 { <<
384 opp-hz = /bits/ 64 <40 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp3: opp-480000000 { <<
389 opp-hz = /bits/ 64 <48 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp4: opp-576000000 { <<
394 opp-hz = /bits/ 64 <57 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp5: opp-652800000 { <<
399 opp-hz = /bits/ 64 <65 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp6: opp-748800000 { <<
404 opp-hz = /bits/ 64 <74 <<
405 opp-peak-kBps = <18040 <<
406 }; <<
407 <<
408 cpu0_opp7: opp-825600000 { <<
409 opp-hz = /bits/ 64 <82 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp8: opp-902400000 { <<
414 opp-hz = /bits/ 64 <90 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp9: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp10: opp-1056000000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp11: opp-1132800000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu0_opp12: opp-1228800000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <21880 <<
436 }; <<
437 <<
438 cpu0_opp13: opp-1324800000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp14: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <30720 <<
446 }; <<
447 <<
448 cpu0_opp15: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp16: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <40680 <<
456 }; <<
457 <<
458 cpu0_opp17: opp-1689600000 { <<
459 opp-hz = /bits/ 64 <16 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp18: opp-1766400000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-300000000 { <<
474 opp-hz = /bits/ 64 <30 <<
475 opp-peak-kBps = <80000 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-403200000 { <<
479 opp-hz = /bits/ 64 <40 <<
480 opp-peak-kBps = <80000 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-480000000 { <<
484 opp-hz = /bits/ 64 <48 <<
485 opp-peak-kBps = <18040 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-576000000 { <<
489 opp-hz = /bits/ 64 <57 <<
490 opp-peak-kBps = <18040 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-652800000 { <<
494 opp-hz = /bits/ 64 <65 <<
495 opp-peak-kBps = <18040 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-748800000 { <<
499 opp-hz = /bits/ 64 <74 <<
500 opp-peak-kBps = <18040 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-825600000 { <<
504 opp-hz = /bits/ 64 <82 <<
505 opp-peak-kBps = <21880 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-902400000 { <<
509 opp-hz = /bits/ 64 <90 <<
510 opp-peak-kBps = <21880 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-979200000 { <<
514 opp-hz = /bits/ 64 <97 <<
515 opp-peak-kBps = <21880 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1056000000 { <<
519 opp-hz = /bits/ 64 <10 <<
520 opp-peak-kBps = <30720 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1132800000 { <<
524 opp-hz = /bits/ 64 <11 <<
525 opp-peak-kBps = <30720 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1209600000 { <<
529 opp-hz = /bits/ 64 <12 <<
530 opp-peak-kBps = <40680 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1286400000 { <<
534 opp-hz = /bits/ 64 <12 <<
535 opp-peak-kBps = <40680 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-1363200000 { <<
539 opp-hz = /bits/ 64 <13 <<
540 opp-peak-kBps = <40680 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-1459200000 { <<
544 opp-hz = /bits/ 64 <14 <<
545 opp-peak-kBps = <40680 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-1536000000 { <<
549 opp-hz = /bits/ 64 <15 <<
550 opp-peak-kBps = <54120 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-1612800000 { <<
554 opp-hz = /bits/ 64 <16 <<
555 opp-peak-kBps = <54120 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-1689600000 { <<
559 opp-hz = /bits/ 64 <16 <<
560 opp-peak-kBps = <54120 <<
561 }; <<
562 <<
563 cpu4_opp19: opp-1766400000 { <<
564 opp-hz = /bits/ 64 <17 <<
565 opp-peak-kBps = <62200 <<
566 }; <<
567 <<
568 cpu4_opp20: opp-1843200000 { <<
569 opp-hz = /bits/ 64 <18 <<
570 opp-peak-kBps = <62200 <<
571 }; <<
572 <<
573 cpu4_opp21: opp-1920000000 { <<
574 opp-hz = /bits/ 64 <19 <<
575 opp-peak-kBps = <72160 <<
576 }; <<
577 <<
578 cpu4_opp22: opp-1996800000 { <<
579 opp-hz = /bits/ 64 <19 <<
580 opp-peak-kBps = <72160 <<
581 }; <<
582 <<
583 cpu4_opp23: opp-2092800000 { <<
584 opp-hz = /bits/ 64 <20 <<
585 opp-peak-kBps = <72160 <<
586 }; <<
587 <<
588 cpu4_opp24: opp-2169600000 { <<
589 opp-hz = /bits/ 64 <21 <<
590 opp-peak-kBps = <72160 <<
591 }; <<
592 <<
593 cpu4_opp25: opp-2246400000 { <<
594 opp-hz = /bits/ 64 <22 <<
595 opp-peak-kBps = <72160 <<
596 }; <<
597 <<
598 cpu4_opp26: opp-2323200000 { <<
599 opp-hz = /bits/ 64 <23 <<
600 opp-peak-kBps = <72160 <<
601 }; <<
602 <<
603 cpu4_opp27: opp-2400000000 { <<
604 opp-hz = /bits/ 64 <24 <<
605 opp-peak-kBps = <72160 <<
606 }; <<
607 <<
608 cpu4_opp28: opp-2476800000 { <<
609 opp-hz = /bits/ 64 <24 <<
610 opp-peak-kBps = <72160 <<
611 }; <<
612 <<
613 cpu4_opp29: opp-2553600000 { <<
614 opp-hz = /bits/ 64 <25 <<
615 opp-peak-kBps = <72160 <<
616 }; <<
617 <<
618 cpu4_opp30: opp-2649600000 { <<
619 opp-hz = /bits/ 64 <26 <<
620 opp-peak-kBps = <72160 <<
621 }; <<
622 <<
623 cpu4_opp31: opp-2745600000 { <<
624 opp-hz = /bits/ 64 <27 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu4_opp32: opp-2803200000 { <<
629 opp-hz = /bits/ 64 <28 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 }; <<
633 <<
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 436 pmu {
712 compatible = "arm,armv8-pmuv3" 437 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 438 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 439 };
715 440
716 psci: psci { !! 441 timer {
717 compatible = "arm,psci-1.0"; !! 442 compatible = "arm,armv8-timer";
718 method = "smc"; !! 443 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 444 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 445 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 446 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 447 };
773 448
774 reserved-memory { !! 449 clocks {
775 #address-cells = <2>; !! 450 xo_board: xo-board {
776 #size-cells = <2>; !! 451 compatible = "fixed-clock";
777 ranges; !! 452 #clock-cells = <0>;
778 !! 453 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 454 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 455 };
885 456
886 mdata_mem: mpss-metadata { !! 457 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 458 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 459 #clock-cells = <0>;
889 no-map; !! 460 clock-frequency = <32764>;
890 }; 461 };
>> 462 };
891 463
892 fastrpc_mem: fastrpc { !! 464 firmware {
893 compatible = "shared-d !! 465 scm {
894 alloc-ranges = <0x0 0x !! 466 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 467 };
899 }; 468 };
900 469
901 adsp_pas: remoteproc-adsp { 470 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 471 compatible = "qcom,sdm845-adsp-pas";
903 472
904 interrupts-extended = <&intc G 473 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 474 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 475 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 476 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 477 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 478 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 479 "handover", "stop-ack";
911 480
912 clocks = <&rpmhcc RPMH_CXO_CLK 481 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 482 clock-names = "xo";
914 483
915 memory-region = <&adsp_mem>; 484 memory-region = <&adsp_mem>;
916 485
917 qcom,qmp = <&aoss_qmp>; <<
918 <<
919 qcom,smem-states = <&adsp_smp2 486 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 487 qcom,smem-state-names = "stop";
921 488
922 status = "disabled"; 489 status = "disabled";
923 490
924 glink-edge { 491 glink-edge {
925 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 493 label = "lpass";
927 qcom,remote-pid = <2>; 494 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 495 mboxes = <&apss_shared 8>;
929 496
930 apr { 497 apr {
931 compatible = " 498 compatible = "qcom,apr-v2";
932 qcom,glink-cha 499 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = !! 500 qcom,apr-domain = <APR_DOMAIN_ADSP>;
934 #address-cells 501 #address-cells = <1>;
935 #size-cells = 502 #size-cells = <0>;
936 qcom,intents = 503 qcom,intents = <512 20>;
937 504
938 service@3 { !! 505 apr-service@3 {
939 reg = 506 reg = <APR_SVC_ADSP_CORE>;
940 compat 507 compatible = "qcom,q6core";
941 qcom,p 508 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 509 };
943 510
944 q6afe: service !! 511 q6afe: apr-service@4 {
945 compat 512 compatible = "qcom,q6afe";
946 reg = 513 reg = <APR_SVC_AFE>;
947 qcom,p 514 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 515 q6afedai: dais {
949 516 compatible = "qcom,q6afe-dais";
950 517 #address-cells = <1>;
951 518 #size-cells = <0>;
952 519 #sound-dai-cells = <1>;
953 }; 520 };
954 }; 521 };
955 522
956 q6asm: service !! 523 q6asm: apr-service@7 {
957 compat 524 compatible = "qcom,q6asm";
958 reg = 525 reg = <APR_SVC_ASM>;
959 qcom,p 526 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 527 q6asmdai: dais {
961 528 compatible = "qcom,q6asm-dais";
962 529 #address-cells = <1>;
963 530 #size-cells = <0>;
964 531 #sound-dai-cells = <1>;
965 532 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 533 };
967 }; 534 };
968 535
969 q6adm: service !! 536 q6adm: apr-service@8 {
970 compat 537 compatible = "qcom,q6adm";
971 reg = 538 reg = <APR_SVC_ADM>;
972 qcom,p 539 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 540 q6routing: routing {
974 541 compatible = "qcom,q6adm-routing";
975 542 #sound-dai-cells = <0>;
976 }; 543 };
977 }; 544 };
978 }; 545 };
979 546
980 fastrpc { 547 fastrpc {
981 compatible = " 548 compatible = "qcom,fastrpc";
982 qcom,glink-cha 549 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 550 label = "adsp";
984 qcom,non-secur <<
985 #address-cells 551 #address-cells = <1>;
986 #size-cells = 552 #size-cells = <0>;
987 553
988 compute-cb@3 { 554 compute-cb@3 {
989 compat 555 compatible = "qcom,fastrpc-compute-cb";
990 reg = 556 reg = <3>;
991 iommus 557 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 558 };
993 559
994 compute-cb@4 { 560 compute-cb@4 {
995 compat 561 compatible = "qcom,fastrpc-compute-cb";
996 reg = 562 reg = <4>;
997 iommus 563 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 564 };
999 }; 565 };
1000 }; 566 };
1001 }; 567 };
1002 568
1003 cdsp_pas: remoteproc-cdsp { 569 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 570 compatible = "qcom,sdm845-cdsp-pas";
1005 571
1006 interrupts-extended = <&intc 572 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 573 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 574 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 575 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 576 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 577 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 578 "handover", "stop-ack";
1013 579
1014 clocks = <&rpmhcc RPMH_CXO_CL 580 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 581 clock-names = "xo";
1016 582
1017 memory-region = <&cdsp_mem>; 583 memory-region = <&cdsp_mem>;
1018 584
1019 qcom,qmp = <&aoss_qmp>; <<
1020 <<
1021 qcom,smem-states = <&cdsp_smp 585 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 586 qcom,smem-state-names = "stop";
1023 587
1024 status = "disabled"; 588 status = "disabled";
1025 589
1026 glink-edge { 590 glink-edge {
1027 interrupts = <GIC_SPI 591 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 592 label = "turing";
1029 qcom,remote-pid = <5> 593 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 594 mboxes = <&apss_shared 4>;
1031 fastrpc { 595 fastrpc {
1032 compatible = 596 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 597 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 598 label = "cdsp";
1035 qcom,non-secu <<
1036 #address-cell 599 #address-cells = <1>;
1037 #size-cells = 600 #size-cells = <0>;
1038 601
1039 compute-cb@1 602 compute-cb@1 {
1040 compa 603 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 604 reg = <1>;
1042 iommu 605 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 606 };
1044 607
1045 compute-cb@2 608 compute-cb@2 {
1046 compa 609 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 610 reg = <2>;
1048 iommu 611 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 612 };
1050 613
1051 compute-cb@3 614 compute-cb@3 {
1052 compa 615 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 616 reg = <3>;
1054 iommu 617 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 618 };
1056 619
1057 compute-cb@4 620 compute-cb@4 {
1058 compa 621 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 622 reg = <4>;
1060 iommu 623 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 624 };
1062 625
1063 compute-cb@5 626 compute-cb@5 {
1064 compa 627 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 628 reg = <5>;
1066 iommu 629 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 630 };
1068 631
1069 compute-cb@6 632 compute-cb@6 {
1070 compa 633 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 634 reg = <6>;
1072 iommu 635 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 636 };
1074 637
1075 compute-cb@7 638 compute-cb@7 {
1076 compa 639 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 640 reg = <7>;
1078 iommu 641 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 642 };
1080 643
1081 compute-cb@8 644 compute-cb@8 {
1082 compa 645 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 646 reg = <8>;
1084 iommu 647 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 648 };
1086 }; 649 };
1087 }; 650 };
1088 }; 651 };
1089 652
>> 653 tcsr_mutex: hwlock {
>> 654 compatible = "qcom,tcsr-mutex";
>> 655 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 656 #hwlock-cells = <1>;
>> 657 };
>> 658
>> 659 smem {
>> 660 compatible = "qcom,smem";
>> 661 memory-region = <&smem_mem>;
>> 662 hwlocks = <&tcsr_mutex 3>;
>> 663 };
>> 664
1090 smp2p-cdsp { 665 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 666 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 667 qcom,smem = <94>, <432>;
1093 668
1094 interrupts = <GIC_SPI 576 IRQ 669 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 670
1096 mboxes = <&apss_shared 6>; 671 mboxes = <&apss_shared 6>;
1097 672
1098 qcom,local-pid = <0>; 673 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 674 qcom,remote-pid = <5>;
1100 675
1101 cdsp_smp2p_out: master-kernel 676 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 677 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 678 #qcom,smem-state-cells = <1>;
1104 }; 679 };
1105 680
1106 cdsp_smp2p_in: slave-kernel { 681 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 682 qcom,entry-name = "slave-kernel";
1108 683
1109 interrupt-controller; 684 interrupt-controller;
1110 #interrupt-cells = <2 685 #interrupt-cells = <2>;
1111 }; 686 };
1112 }; 687 };
1113 688
1114 smp2p-lpass { 689 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 690 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 691 qcom,smem = <443>, <429>;
1117 692
1118 interrupts = <GIC_SPI 158 IRQ 693 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 694
1120 mboxes = <&apss_shared 10>; 695 mboxes = <&apss_shared 10>;
1121 696
1122 qcom,local-pid = <0>; 697 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 698 qcom,remote-pid = <2>;
1124 699
1125 adsp_smp2p_out: master-kernel 700 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 701 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 702 #qcom,smem-state-cells = <1>;
1128 }; 703 };
1129 704
1130 adsp_smp2p_in: slave-kernel { 705 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 706 qcom,entry-name = "slave-kernel";
1132 707
1133 interrupt-controller; 708 interrupt-controller;
1134 #interrupt-cells = <2 709 #interrupt-cells = <2>;
1135 }; 710 };
1136 }; 711 };
1137 712
1138 smp2p-mpss { 713 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 714 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 715 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 716 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 717 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 718 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 719 qcom,remote-pid = <1>;
1145 720
1146 modem_smp2p_out: master-kerne 721 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 722 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 723 #qcom,smem-state-cells = <1>;
1149 }; 724 };
1150 725
1151 modem_smp2p_in: slave-kernel 726 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 727 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 728 interrupt-controller;
1154 #interrupt-cells = <2 729 #interrupt-cells = <2>;
1155 }; 730 };
1156 731
1157 ipa_smp2p_out: ipa-ap-to-mode 732 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 733 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 734 #qcom,smem-state-cells = <1>;
1160 }; 735 };
1161 736
1162 ipa_smp2p_in: ipa-modem-to-ap 737 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 738 qcom,entry-name = "ipa";
1164 interrupt-controller; 739 interrupt-controller;
1165 #interrupt-cells = <2 740 #interrupt-cells = <2>;
1166 }; 741 };
1167 }; 742 };
1168 743
1169 smp2p-slpi { 744 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 745 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 746 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 747 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 748 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 749 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 750 qcom,remote-pid = <3>;
1176 751
1177 slpi_smp2p_out: master-kernel 752 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 753 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 754 #qcom,smem-state-cells = <1>;
1180 }; 755 };
1181 756
1182 slpi_smp2p_in: slave-kernel { 757 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 758 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 759 interrupt-controller;
1185 #interrupt-cells = <2 760 #interrupt-cells = <2>;
1186 }; 761 };
1187 }; 762 };
1188 763
>> 764 psci {
>> 765 compatible = "arm,psci-1.0";
>> 766 method = "smc";
>> 767 };
>> 768
1189 soc: soc@0 { 769 soc: soc@0 {
1190 #address-cells = <2>; 770 #address-cells = <2>;
1191 #size-cells = <2>; 771 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 772 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 773 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 774 compatible = "simple-bus";
1195 775
1196 gcc: clock-controller@100000 776 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 777 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 778 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM <<
1200 <&rpmhcc RPM <<
1201 <&sleep_clk> <<
1202 <&pcie0_phy> <<
1203 <&pcie1_phy> <<
1204 clock-names = "bi_tcx <<
1205 "bi_tcx <<
1206 "sleep_ <<
1207 "pcie_0 <<
1208 "pcie_1 <<
1209 #clock-cells = <1>; 779 #clock-cells = <1>;
1210 #reset-cells = <1>; 780 #reset-cells = <1>;
1211 #power-domain-cells = 781 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 782 };
1214 783
1215 qfprom@784000 { 784 qfprom@784000 {
1216 compatible = "qcom,sd !! 785 compatible = "qcom,qfprom";
1217 reg = <0 0x00784000 0 786 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 787 #address-cells = <1>;
1219 #size-cells = <1>; 788 #size-cells = <1>;
1220 789
1221 qusb2p_hstx_trim: hst 790 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 791 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 792 bits = <1 4>;
1224 }; 793 };
1225 794
1226 qusb2s_hstx_trim: hst 795 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 796 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 797 bits = <6 4>;
1229 }; 798 };
1230 }; 799 };
1231 800
1232 rng: rng@793000 { 801 rng: rng@793000 {
1233 compatible = "qcom,pr 802 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 803 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 804 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 805 clock-names = "core";
1237 }; 806 };
1238 807
1239 gpi_dma0: dma-controller@8000 <<
1240 #dma-cells = <3>; <<
1241 compatible = "qcom,sd <<
1242 reg = <0 0x00800000 0 <<
1243 interrupts = <GIC_SPI <<
1244 <GIC_SPI <<
1245 <GIC_SPI <<
1246 <GIC_SPI <<
1247 <GIC_SPI <<
1248 <GIC_SPI <<
1249 <GIC_SPI <<
1250 <GIC_SPI <<
1251 <GIC_SPI <<
1252 <GIC_SPI <<
1253 <GIC_SPI <<
1254 <GIC_SPI <<
1255 <GIC_SPI <<
1256 dma-channels = <13>; <<
1257 dma-channel-mask = <0 <<
1258 iommus = <&apps_smmu <<
1259 status = "disabled"; <<
1260 }; <<
1261 <<
1262 qupv3_id_0: geniqup@8c0000 { 808 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 809 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 810 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 811 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 812 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 813 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu <<
1269 #address-cells = <2>; 814 #address-cells = <2>;
1270 #size-cells = <2>; 815 #size-cells = <2>;
1271 ranges; 816 ranges;
1272 interconnects = <&agg <<
1273 interconnect-names = <<
1274 status = "disabled"; 817 status = "disabled";
1275 818
1276 i2c0: i2c@880000 { 819 i2c0: i2c@880000 {
1277 compatible = 820 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 821 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 822 clock-names = "se";
1280 clocks = <&gc 823 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 824 pinctrl-names = "default";
1282 pinctrl-0 = < 825 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 826 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 827 #address-cells = <1>;
1285 #size-cells = 828 #size-cells = <0>;
1286 power-domains <<
1287 operating-poi <<
1288 interconnects <<
1289 <<
1290 <<
1291 interconnect- <<
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 829 status = "disabled";
1296 }; 830 };
1297 831
1298 spi0: spi@880000 { 832 spi0: spi@880000 {
1299 compatible = 833 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 834 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 835 clock-names = "se";
1302 clocks = <&gc 836 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 837 pinctrl-names = "default";
1304 pinctrl-0 = < 838 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 839 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 840 #address-cells = <1>;
1307 #size-cells = 841 #size-cells = <0>;
1308 interconnects <<
1309 <<
1310 interconnect- <<
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 842 status = "disabled";
1315 }; 843 };
1316 844
1317 uart0: serial@880000 845 uart0: serial@880000 {
1318 compatible = 846 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 847 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 848 clock-names = "se";
1321 clocks = <&gc 849 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 850 pinctrl-names = "default";
1323 pinctrl-0 = < 851 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 852 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains <<
1326 operating-poi <<
1327 interconnects <<
1328 <<
1329 interconnect- <<
1330 status = "dis 853 status = "disabled";
1331 }; 854 };
1332 855
1333 i2c1: i2c@884000 { 856 i2c1: i2c@884000 {
1334 compatible = 857 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 858 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 859 clock-names = "se";
1337 clocks = <&gc 860 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 861 pinctrl-names = "default";
1339 pinctrl-0 = < 862 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 864 #address-cells = <1>;
1342 #size-cells = 865 #size-cells = <0>;
1343 power-domains <<
1344 operating-poi <<
1345 interconnects <<
1346 <<
1347 <<
1348 interconnect- <<
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 866 status = "disabled";
1353 }; 867 };
1354 868
1355 spi1: spi@884000 { 869 spi1: spi@884000 {
1356 compatible = 870 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 871 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 872 clock-names = "se";
1359 clocks = <&gc 873 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 874 pinctrl-names = "default";
1361 pinctrl-0 = < 875 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 876 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 877 #address-cells = <1>;
1364 #size-cells = 878 #size-cells = <0>;
1365 interconnects <<
1366 <<
1367 interconnect- <<
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 879 status = "disabled";
1372 }; 880 };
1373 881
1374 uart1: serial@884000 882 uart1: serial@884000 {
1375 compatible = 883 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 884 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 885 clock-names = "se";
1378 clocks = <&gc 886 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 887 pinctrl-names = "default";
1380 pinctrl-0 = < 888 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 889 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains <<
1383 operating-poi <<
1384 interconnects <<
1385 <<
1386 interconnect- <<
1387 status = "dis 890 status = "disabled";
1388 }; 891 };
1389 892
1390 i2c2: i2c@888000 { 893 i2c2: i2c@888000 {
1391 compatible = 894 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 895 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 896 clock-names = "se";
1394 clocks = <&gc 897 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 898 pinctrl-names = "default";
1396 pinctrl-0 = < 899 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 900 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 901 #address-cells = <1>;
1399 #size-cells = 902 #size-cells = <0>;
1400 power-domains <<
1401 operating-poi <<
1402 interconnects <<
1403 <<
1404 <<
1405 interconnect- <<
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 903 status = "disabled";
1410 }; 904 };
1411 905
1412 spi2: spi@888000 { 906 spi2: spi@888000 {
1413 compatible = 907 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 908 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 909 clock-names = "se";
1416 clocks = <&gc 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 911 pinctrl-names = "default";
1418 pinctrl-0 = < 912 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 914 #address-cells = <1>;
1421 #size-cells = 915 #size-cells = <0>;
1422 interconnects <<
1423 <<
1424 interconnect- <<
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 916 status = "disabled";
1429 }; 917 };
1430 918
1431 uart2: serial@888000 919 uart2: serial@888000 {
1432 compatible = 920 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 921 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 922 clock-names = "se";
1435 clocks = <&gc 923 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 924 pinctrl-names = "default";
1437 pinctrl-0 = < 925 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 926 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains <<
1440 operating-poi <<
1441 interconnects <<
1442 <<
1443 interconnect- <<
1444 status = "dis 927 status = "disabled";
1445 }; 928 };
1446 929
1447 i2c3: i2c@88c000 { 930 i2c3: i2c@88c000 {
1448 compatible = 931 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 932 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 933 clock-names = "se";
1451 clocks = <&gc 934 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 935 pinctrl-names = "default";
1453 pinctrl-0 = < 936 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 937 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 938 #address-cells = <1>;
1456 #size-cells = 939 #size-cells = <0>;
1457 power-domains <<
1458 operating-poi <<
1459 interconnects <<
1460 <<
1461 <<
1462 interconnect- <<
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 940 status = "disabled";
1467 }; 941 };
1468 942
1469 spi3: spi@88c000 { 943 spi3: spi@88c000 {
1470 compatible = 944 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 945 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 946 clock-names = "se";
1473 clocks = <&gc 947 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 948 pinctrl-names = "default";
1475 pinctrl-0 = < 949 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 950 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 951 #address-cells = <1>;
1478 #size-cells = 952 #size-cells = <0>;
1479 interconnects <<
1480 <<
1481 interconnect- <<
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 953 status = "disabled";
1486 }; 954 };
1487 955
1488 uart3: serial@88c000 956 uart3: serial@88c000 {
1489 compatible = 957 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 958 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 959 clock-names = "se";
1492 clocks = <&gc 960 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 961 pinctrl-names = "default";
1494 pinctrl-0 = < 962 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 963 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains <<
1497 operating-poi <<
1498 interconnects <<
1499 <<
1500 interconnect- <<
1501 status = "dis 964 status = "disabled";
1502 }; 965 };
1503 966
1504 i2c4: i2c@890000 { 967 i2c4: i2c@890000 {
1505 compatible = 968 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 969 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 970 clock-names = "se";
1508 clocks = <&gc 971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 972 pinctrl-names = "default";
1510 pinctrl-0 = < 973 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 974 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 975 #address-cells = <1>;
1513 #size-cells = 976 #size-cells = <0>;
1514 power-domains <<
1515 operating-poi <<
1516 interconnects <<
1517 <<
1518 <<
1519 interconnect- <<
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 977 status = "disabled";
1524 }; 978 };
1525 979
1526 spi4: spi@890000 { 980 spi4: spi@890000 {
1527 compatible = 981 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 982 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 983 clock-names = "se";
1530 clocks = <&gc 984 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 985 pinctrl-names = "default";
1532 pinctrl-0 = < 986 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 987 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 988 #address-cells = <1>;
1535 #size-cells = 989 #size-cells = <0>;
1536 interconnects <<
1537 <<
1538 interconnect- <<
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 990 status = "disabled";
1543 }; 991 };
1544 992
1545 uart4: serial@890000 993 uart4: serial@890000 {
1546 compatible = 994 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 995 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 996 clock-names = "se";
1549 clocks = <&gc 997 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 998 pinctrl-names = "default";
1551 pinctrl-0 = < 999 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1000 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains <<
1554 operating-poi <<
1555 interconnects <<
1556 <<
1557 interconnect- <<
1558 status = "dis 1001 status = "disabled";
1559 }; 1002 };
1560 1003
1561 i2c5: i2c@894000 { 1004 i2c5: i2c@894000 {
1562 compatible = 1005 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1006 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1007 clock-names = "se";
1565 clocks = <&gc 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1009 pinctrl-names = "default";
1567 pinctrl-0 = < 1010 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1011 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1012 #address-cells = <1>;
1570 #size-cells = 1013 #size-cells = <0>;
1571 power-domains <<
1572 operating-poi <<
1573 interconnects <<
1574 <<
1575 <<
1576 interconnect- <<
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 1014 status = "disabled";
1581 }; 1015 };
1582 1016
1583 spi5: spi@894000 { 1017 spi5: spi@894000 {
1584 compatible = 1018 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1019 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1020 clock-names = "se";
1587 clocks = <&gc 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1022 pinctrl-names = "default";
1589 pinctrl-0 = < 1023 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1024 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1025 #address-cells = <1>;
1592 #size-cells = 1026 #size-cells = <0>;
1593 interconnects <<
1594 <<
1595 interconnect- <<
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 1027 status = "disabled";
1600 }; 1028 };
1601 1029
1602 uart5: serial@894000 1030 uart5: serial@894000 {
1603 compatible = 1031 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1032 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1033 clock-names = "se";
1606 clocks = <&gc 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1035 pinctrl-names = "default";
1608 pinctrl-0 = < 1036 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains <<
1611 operating-poi <<
1612 interconnects <<
1613 <<
1614 interconnect- <<
1615 status = "dis 1038 status = "disabled";
1616 }; 1039 };
1617 1040
1618 i2c6: i2c@898000 { 1041 i2c6: i2c@898000 {
1619 compatible = 1042 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1043 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1044 clock-names = "se";
1622 clocks = <&gc 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1046 pinctrl-names = "default";
1624 pinctrl-0 = < 1047 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1048 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1049 #address-cells = <1>;
1627 #size-cells = 1050 #size-cells = <0>;
1628 power-domains <<
1629 operating-poi <<
1630 interconnects <<
1631 <<
1632 <<
1633 interconnect- <<
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 1051 status = "disabled";
1638 }; 1052 };
1639 1053
1640 spi6: spi@898000 { 1054 spi6: spi@898000 {
1641 compatible = 1055 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1056 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1057 clock-names = "se";
1644 clocks = <&gc 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1059 pinctrl-names = "default";
1646 pinctrl-0 = < 1060 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1061 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1062 #address-cells = <1>;
1649 #size-cells = 1063 #size-cells = <0>;
1650 interconnects <<
1651 <<
1652 interconnect- <<
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 1064 status = "disabled";
1657 }; 1065 };
1658 1066
1659 uart6: serial@898000 1067 uart6: serial@898000 {
1660 compatible = 1068 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1069 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1070 clock-names = "se";
1663 clocks = <&gc 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1072 pinctrl-names = "default";
1665 pinctrl-0 = < 1073 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1074 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains <<
1668 operating-poi <<
1669 interconnects <<
1670 <<
1671 interconnect- <<
1672 status = "dis 1075 status = "disabled";
1673 }; 1076 };
1674 1077
1675 i2c7: i2c@89c000 { 1078 i2c7: i2c@89c000 {
1676 compatible = 1079 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1080 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1081 clock-names = "se";
1679 clocks = <&gc 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1083 pinctrl-names = "default";
1681 pinctrl-0 = < 1084 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1085 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1086 #address-cells = <1>;
1684 #size-cells = 1087 #size-cells = <0>;
1685 power-domains <<
1686 operating-poi <<
1687 status = "dis 1088 status = "disabled";
1688 }; 1089 };
1689 1090
1690 spi7: spi@89c000 { 1091 spi7: spi@89c000 {
1691 compatible = 1092 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1093 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1094 clock-names = "se";
1694 clocks = <&gc 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1096 pinctrl-names = "default";
1696 pinctrl-0 = < 1097 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1098 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1099 #address-cells = <1>;
1699 #size-cells = 1100 #size-cells = <0>;
1700 interconnects <<
1701 <<
1702 interconnect- <<
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 1101 status = "disabled";
1707 }; 1102 };
1708 1103
1709 uart7: serial@89c000 1104 uart7: serial@89c000 {
1710 compatible = 1105 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1106 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1107 clock-names = "se";
1713 clocks = <&gc 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1109 pinctrl-names = "default";
1715 pinctrl-0 = < 1110 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1111 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains <<
1718 operating-poi <<
1719 interconnects <<
1720 <<
1721 interconnect- <<
1722 status = "dis 1112 status = "disabled";
1723 }; 1113 };
1724 }; 1114 };
1725 1115
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 1116 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1117 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1118 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1119 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1120 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1121 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu <<
1756 #address-cells = <2>; 1122 #address-cells = <2>;
1757 #size-cells = <2>; 1123 #size-cells = <2>;
1758 ranges; 1124 ranges;
1759 interconnects = <&agg <<
1760 interconnect-names = <<
1761 status = "disabled"; 1125 status = "disabled";
1762 1126
1763 i2c8: i2c@a80000 { 1127 i2c8: i2c@a80000 {
1764 compatible = 1128 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1129 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1130 clock-names = "se";
1767 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1132 pinctrl-names = "default";
1769 pinctrl-0 = < 1133 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1134 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1135 #address-cells = <1>;
1772 #size-cells = 1136 #size-cells = <0>;
1773 power-domains <<
1774 operating-poi <<
1775 interconnects <<
1776 <<
1777 <<
1778 interconnect- <<
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 1137 status = "disabled";
1783 }; 1138 };
1784 1139
1785 spi8: spi@a80000 { 1140 spi8: spi@a80000 {
1786 compatible = 1141 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1142 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1143 clock-names = "se";
1789 clocks = <&gc 1144 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1145 pinctrl-names = "default";
1791 pinctrl-0 = < 1146 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1147 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1148 #address-cells = <1>;
1794 #size-cells = 1149 #size-cells = <0>;
1795 interconnects <<
1796 <<
1797 interconnect- <<
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 1150 status = "disabled";
1802 }; 1151 };
1803 1152
1804 uart8: serial@a80000 1153 uart8: serial@a80000 {
1805 compatible = 1154 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1155 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1156 clock-names = "se";
1808 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1158 pinctrl-names = "default";
1810 pinctrl-0 = < 1159 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1160 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains <<
1813 operating-poi <<
1814 interconnects <<
1815 <<
1816 interconnect- <<
1817 status = "dis 1161 status = "disabled";
1818 }; 1162 };
1819 1163
1820 i2c9: i2c@a84000 { 1164 i2c9: i2c@a84000 {
1821 compatible = 1165 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1166 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1167 clock-names = "se";
1824 clocks = <&gc 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1169 pinctrl-names = "default";
1826 pinctrl-0 = < 1170 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1171 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1172 #address-cells = <1>;
1829 #size-cells = 1173 #size-cells = <0>;
1830 power-domains <<
1831 operating-poi <<
1832 interconnects <<
1833 <<
1834 <<
1835 interconnect- <<
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 1174 status = "disabled";
1840 }; 1175 };
1841 1176
1842 spi9: spi@a84000 { 1177 spi9: spi@a84000 {
1843 compatible = 1178 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1179 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1180 clock-names = "se";
1846 clocks = <&gc 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1182 pinctrl-names = "default";
1848 pinctrl-0 = < 1183 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1184 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1185 #address-cells = <1>;
1851 #size-cells = 1186 #size-cells = <0>;
1852 interconnects <<
1853 <<
1854 interconnect- <<
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 1187 status = "disabled";
1859 }; 1188 };
1860 1189
1861 uart9: serial@a84000 1190 uart9: serial@a84000 {
1862 compatible = 1191 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1192 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1193 clock-names = "se";
1865 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1195 pinctrl-names = "default";
1867 pinctrl-0 = < 1196 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1197 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains <<
1870 operating-poi <<
1871 interconnects <<
1872 <<
1873 interconnect- <<
1874 status = "dis 1198 status = "disabled";
1875 }; 1199 };
1876 1200
1877 i2c10: i2c@a88000 { 1201 i2c10: i2c@a88000 {
1878 compatible = 1202 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1203 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1204 clock-names = "se";
1881 clocks = <&gc 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1206 pinctrl-names = "default";
1883 pinctrl-0 = < 1207 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1208 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1209 #address-cells = <1>;
1886 #size-cells = 1210 #size-cells = <0>;
1887 power-domains <<
1888 operating-poi <<
1889 interconnects <<
1890 <<
1891 <<
1892 interconnect- <<
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 1211 status = "disabled";
1897 }; 1212 };
1898 1213
1899 spi10: spi@a88000 { 1214 spi10: spi@a88000 {
1900 compatible = 1215 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1216 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1217 clock-names = "se";
1903 clocks = <&gc 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1219 pinctrl-names = "default";
1905 pinctrl-0 = < 1220 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1221 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1222 #address-cells = <1>;
1908 #size-cells = 1223 #size-cells = <0>;
1909 interconnects <<
1910 <<
1911 interconnect- <<
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1224 status = "disabled";
1916 }; 1225 };
1917 1226
1918 uart10: serial@a88000 1227 uart10: serial@a88000 {
1919 compatible = 1228 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1229 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1230 clock-names = "se";
1922 clocks = <&gc 1231 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1232 pinctrl-names = "default";
1924 pinctrl-0 = < 1233 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1234 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains <<
1927 operating-poi <<
1928 interconnects <<
1929 <<
1930 interconnect- <<
1931 status = "dis 1235 status = "disabled";
1932 }; 1236 };
1933 1237
1934 i2c11: i2c@a8c000 { 1238 i2c11: i2c@a8c000 {
1935 compatible = 1239 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1240 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1241 clock-names = "se";
1938 clocks = <&gc 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1243 pinctrl-names = "default";
1940 pinctrl-0 = < 1244 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1245 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1246 #address-cells = <1>;
1943 #size-cells = 1247 #size-cells = <0>;
1944 power-domains <<
1945 operating-poi <<
1946 interconnects <<
1947 <<
1948 <<
1949 interconnect- <<
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1248 status = "disabled";
1954 }; 1249 };
1955 1250
1956 spi11: spi@a8c000 { 1251 spi11: spi@a8c000 {
1957 compatible = 1252 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1253 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1254 clock-names = "se";
1960 clocks = <&gc 1255 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1256 pinctrl-names = "default";
1962 pinctrl-0 = < 1257 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1258 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1259 #address-cells = <1>;
1965 #size-cells = 1260 #size-cells = <0>;
1966 interconnects <<
1967 <<
1968 interconnect- <<
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1261 status = "disabled";
1973 }; 1262 };
1974 1263
1975 uart11: serial@a8c000 1264 uart11: serial@a8c000 {
1976 compatible = 1265 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1266 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1267 clock-names = "se";
1979 clocks = <&gc 1268 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1269 pinctrl-names = "default";
1981 pinctrl-0 = < 1270 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1271 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains <<
1984 operating-poi <<
1985 interconnects <<
1986 <<
1987 interconnect- <<
1988 status = "dis 1272 status = "disabled";
1989 }; 1273 };
1990 1274
1991 i2c12: i2c@a90000 { 1275 i2c12: i2c@a90000 {
1992 compatible = 1276 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1277 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1278 clock-names = "se";
1995 clocks = <&gc 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1280 pinctrl-names = "default";
1997 pinctrl-0 = < 1281 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1282 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1283 #address-cells = <1>;
2000 #size-cells = 1284 #size-cells = <0>;
2001 power-domains <<
2002 operating-poi <<
2003 interconnects <<
2004 <<
2005 <<
2006 interconnect- <<
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1285 status = "disabled";
2011 }; 1286 };
2012 1287
2013 spi12: spi@a90000 { 1288 spi12: spi@a90000 {
2014 compatible = 1289 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1290 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1291 clock-names = "se";
2017 clocks = <&gc 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1293 pinctrl-names = "default";
2019 pinctrl-0 = < 1294 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1295 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1296 #address-cells = <1>;
2022 #size-cells = 1297 #size-cells = <0>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1298 status = "disabled";
2030 }; 1299 };
2031 1300
2032 uart12: serial@a90000 1301 uart12: serial@a90000 {
2033 compatible = 1302 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1303 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1304 clock-names = "se";
2036 clocks = <&gc 1305 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1306 pinctrl-names = "default";
2038 pinctrl-0 = < 1307 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains <<
2041 operating-poi <<
2042 interconnects <<
2043 <<
2044 interconnect- <<
2045 status = "dis 1309 status = "disabled";
2046 }; 1310 };
2047 1311
2048 i2c13: i2c@a94000 { 1312 i2c13: i2c@a94000 {
2049 compatible = 1313 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1314 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1315 clock-names = "se";
2052 clocks = <&gc 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1317 pinctrl-names = "default";
2054 pinctrl-0 = < 1318 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1320 #address-cells = <1>;
2057 #size-cells = 1321 #size-cells = <0>;
2058 power-domains <<
2059 operating-poi <<
2060 interconnects <<
2061 <<
2062 <<
2063 interconnect- <<
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1322 status = "disabled";
2068 }; 1323 };
2069 1324
2070 spi13: spi@a94000 { 1325 spi13: spi@a94000 {
2071 compatible = 1326 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1327 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1328 clock-names = "se";
2074 clocks = <&gc 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1330 pinctrl-names = "default";
2076 pinctrl-0 = < 1331 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1332 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1333 #address-cells = <1>;
2079 #size-cells = 1334 #size-cells = <0>;
2080 interconnects <<
2081 <<
2082 interconnect- <<
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1335 status = "disabled";
2087 }; 1336 };
2088 1337
2089 uart13: serial@a94000 1338 uart13: serial@a94000 {
2090 compatible = 1339 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1340 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1341 clock-names = "se";
2093 clocks = <&gc 1342 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1343 pinctrl-names = "default";
2095 pinctrl-0 = < 1344 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1345 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains <<
2098 operating-poi <<
2099 interconnects <<
2100 <<
2101 interconnect- <<
2102 status = "dis 1346 status = "disabled";
2103 }; 1347 };
2104 1348
2105 i2c14: i2c@a98000 { 1349 i2c14: i2c@a98000 {
2106 compatible = 1350 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1351 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1352 clock-names = "se";
2109 clocks = <&gc 1353 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1354 pinctrl-names = "default";
2111 pinctrl-0 = < 1355 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1356 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1357 #address-cells = <1>;
2114 #size-cells = 1358 #size-cells = <0>;
2115 power-domains <<
2116 operating-poi <<
2117 interconnects <<
2118 <<
2119 <<
2120 interconnect- <<
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1359 status = "disabled";
2125 }; 1360 };
2126 1361
2127 spi14: spi@a98000 { 1362 spi14: spi@a98000 {
2128 compatible = 1363 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1364 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1365 clock-names = "se";
2131 clocks = <&gc 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1367 pinctrl-names = "default";
2133 pinctrl-0 = < 1368 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1369 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1370 #address-cells = <1>;
2136 #size-cells = 1371 #size-cells = <0>;
2137 interconnects <<
2138 <<
2139 interconnect- <<
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1372 status = "disabled";
2144 }; 1373 };
2145 1374
2146 uart14: serial@a98000 1375 uart14: serial@a98000 {
2147 compatible = 1376 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1377 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1378 clock-names = "se";
2150 clocks = <&gc 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1380 pinctrl-names = "default";
2152 pinctrl-0 = < 1381 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1382 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains <<
2155 operating-poi <<
2156 interconnects <<
2157 <<
2158 interconnect- <<
2159 status = "dis 1383 status = "disabled";
2160 }; 1384 };
2161 1385
2162 i2c15: i2c@a9c000 { 1386 i2c15: i2c@a9c000 {
2163 compatible = 1387 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1388 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1389 clock-names = "se";
2166 clocks = <&gc 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1391 pinctrl-names = "default";
2168 pinctrl-0 = < 1392 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1393 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1394 #address-cells = <1>;
2171 #size-cells = 1395 #size-cells = <0>;
2172 power-domains <<
2173 operating-poi <<
2174 status = "dis 1396 status = "disabled";
2175 interconnects <<
2176 <<
2177 <<
2178 interconnect- <<
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1397 };
2183 1398
2184 spi15: spi@a9c000 { 1399 spi15: spi@a9c000 {
2185 compatible = 1400 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1401 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1402 clock-names = "se";
2188 clocks = <&gc 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1404 pinctrl-names = "default";
2190 pinctrl-0 = < 1405 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1406 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1407 #address-cells = <1>;
2193 #size-cells = 1408 #size-cells = <0>;
2194 interconnects <<
2195 <<
2196 interconnect- <<
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1409 status = "disabled";
2201 }; 1410 };
2202 1411
2203 uart15: serial@a9c000 1412 uart15: serial@a9c000 {
2204 compatible = 1413 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1414 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1415 clock-names = "se";
2207 clocks = <&gc 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1417 pinctrl-names = "default";
2209 pinctrl-0 = < 1418 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1419 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains <<
2212 operating-poi <<
2213 interconnects <<
2214 <<
2215 interconnect- <<
2216 status = "dis 1420 status = "disabled";
2217 }; 1421 };
2218 }; 1422 };
2219 1423
2220 llcc: system-cache-controller !! 1424 system-cache-controller@1100000 {
2221 compatible = "qcom,sd 1425 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 1426 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 1427 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 1428 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 1429 };
2229 1430
2230 dma@10a2000 { !! 1431 pcie0: pci@1c00000 {
2231 compatible = "qcom,sd !! 1432 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 1433 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 1434 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 1435 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 1436 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 1437 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 1438 device_type = "pci";
2319 linux,pci-domain = <0 1439 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 1440 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 1441 num-lanes = <1>;
2322 1442
2323 #address-cells = <3>; 1443 #address-cells = <3>;
2324 #size-cells = <2>; 1444 #size-cells = <2>;
2325 1445
2326 ranges = <0x01000000 !! 1446 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327 <0x02000000 !! 1447 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328 1448
2329 interrupts = <GIC_SPI 1449 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 1450 interrupt-names = "msi";
2331 #interrupt-cells = <1 1451 #interrupt-cells = <1>;
2332 interrupt-map-mask = 1452 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 !! 1453 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 !! 1454 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 !! 1455 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 !! 1456 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 1457
2338 clocks = <&gcc GCC_PC 1458 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 1459 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 1460 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 1461 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 1462 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 1463 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 1464 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 1465 clock-names = "pipe",
2346 "aux", 1466 "aux",
2347 "cfg", 1467 "cfg",
2348 "bus_ma 1468 "bus_master",
2349 "bus_sl 1469 "bus_slave",
2350 "slave_ 1470 "slave_q2a",
2351 "tbu"; 1471 "tbu";
2352 1472
>> 1473 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 1474 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 1475 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 1476 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 1477 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 1478 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 1479 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 1480 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 1481 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 1482 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 1483 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 1484 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 1485 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 1486 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 1487 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 1488 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 1489 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 1490
2370 resets = <&gcc GCC_PC 1491 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 1492 reset-names = "pci";
2372 1493
2373 power-domains = <&gcc 1494 power-domains = <&gcc PCIE_0_GDSC>;
2374 1495
2375 phys = <&pcie0_phy>; !! 1496 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 1497 phy-names = "pciephy";
2377 1498
2378 status = "disabled"; 1499 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 1500 };
2390 1501
2391 pcie0_phy: phy@1c06000 { 1502 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 1503 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 1504 reg = <0 0x01c06000 0 0x18c>;
>> 1505 #address-cells = <2>;
>> 1506 #size-cells = <2>;
>> 1507 ranges;
2394 clocks = <&gcc GCC_PC 1508 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 1509 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 1510 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 1511 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 1512 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 1513
2410 resets = <&gcc GCC_PC 1514 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 1515 reset-names = "phy";
2412 1516
2413 assigned-clocks = <&g 1517 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 1518 assigned-clock-rates = <100000000>;
2415 1519
2416 status = "disabled"; 1520 status = "disabled";
>> 1521
>> 1522 pcie0_lane: lanes@1c06200 {
>> 1523 reg = <0 0x01c06200 0 0x128>,
>> 1524 <0 0x01c06400 0 0x1fc>,
>> 1525 <0 0x01c06800 0 0x218>,
>> 1526 <0 0x01c06600 0 0x70>;
>> 1527 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1528 clock-names = "pipe0";
>> 1529
>> 1530 #phy-cells = <0>;
>> 1531 clock-output-names = "pcie_0_pipe_clk";
>> 1532 };
2417 }; 1533 };
2418 1534
2419 pcie1: pcie@1c08000 { !! 1535 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc !! 1536 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2421 reg = <0 0x01c08000 0 1537 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 1538 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 1539 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 1540 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 1541 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 1542 device_type = "pci";
2428 linux,pci-domain = <1 1543 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 1544 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 1545 num-lanes = <1>;
2431 1546
2432 #address-cells = <3>; 1547 #address-cells = <3>;
2433 #size-cells = <2>; 1548 #size-cells = <2>;
2434 1549
2435 ranges = <0x01000000 !! 1550 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 1551 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 1552
2438 interrupts = <GIC_SPI 1553 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 1554 interrupt-names = "msi";
2440 #interrupt-cells = <1 1555 #interrupt-cells = <1>;
2441 interrupt-map-mask = 1556 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 !! 1557 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 !! 1558 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 !! 1559 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 !! 1560 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 1561
2447 clocks = <&gcc GCC_PC 1562 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 1563 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 1564 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 1565 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 1566 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 1567 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 1568 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 1569 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 1570 clock-names = "pipe",
2456 "aux", 1571 "aux",
2457 "cfg", 1572 "cfg",
2458 "bus_ma 1573 "bus_master",
2459 "bus_sl 1574 "bus_slave",
2460 "slave_ 1575 "slave_q2a",
2461 "ref", 1576 "ref",
2462 "tbu"; 1577 "tbu";
2463 1578
2464 assigned-clocks = <&g 1579 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 1580 assigned-clock-rates = <19200000>;
2466 1581
>> 1582 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 1583 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 1584 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 1585 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 1586 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 1587 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 1588 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 1589 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 1590 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 1591 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 1592 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 1593 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 1594 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 1595 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 1596 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 1597 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 1598 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 1599
2484 resets = <&gcc GCC_PC 1600 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 1601 reset-names = "pci";
2486 1602
2487 power-domains = <&gcc 1603 power-domains = <&gcc PCIE_1_GDSC>;
2488 1604
2489 phys = <&pcie1_phy>; !! 1605 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 1606 phy-names = "pciephy";
2491 1607
2492 status = "disabled"; 1608 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 1609 };
2504 1610
2505 pcie1_phy: phy@1c0a000 { 1611 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 1612 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 1613 reg = <0 0x01c0a000 0 0x800>;
>> 1614 #address-cells = <2>;
>> 1615 #size-cells = <2>;
>> 1616 ranges;
2508 clocks = <&gcc GCC_PC 1617 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 1618 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 1619 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 1620 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 1621 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 1622
2524 resets = <&gcc GCC_PC 1623 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 1624 reset-names = "phy";
2526 1625
2527 assigned-clocks = <&g 1626 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 1627 assigned-clock-rates = <100000000>;
2529 1628
2530 status = "disabled"; 1629 status = "disabled";
>> 1630
>> 1631 pcie1_lane: lanes@1c06200 {
>> 1632 reg = <0 0x01c0a800 0 0x800>,
>> 1633 <0 0x01c0a800 0 0x800>,
>> 1634 <0 0x01c0b800 0 0x400>;
>> 1635 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1636 clock-names = "pipe0";
>> 1637
>> 1638 #phy-cells = <0>;
>> 1639 clock-output-names = "pcie_1_pipe_clk";
>> 1640 };
2531 }; 1641 };
2532 1642
2533 mem_noc: interconnect@1380000 1643 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 1644 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 1645 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = !! 1646 #interconnect-cells = <1>;
2537 qcom,bcm-voters = <&a 1647 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 1648 };
2539 1649
2540 dc_noc: interconnect@14e0000 1650 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 1651 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 1652 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = !! 1653 #interconnect-cells = <1>;
2544 qcom,bcm-voters = <&a 1654 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 1655 };
2546 1656
2547 config_noc: interconnect@1500 1657 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 1658 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 1659 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = !! 1660 #interconnect-cells = <1>;
2551 qcom,bcm-voters = <&a 1661 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 1662 };
2553 1663
2554 system_noc: interconnect@1620 1664 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 1665 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 1666 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = !! 1667 #interconnect-cells = <1>;
2558 qcom,bcm-voters = <&a 1668 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 1669 };
2560 1670
2561 aggre1_noc: interconnect@16e0 1671 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 1672 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 1673 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = !! 1674 #interconnect-cells = <1>;
2565 qcom,bcm-voters = <&a 1675 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 1676 };
2567 1677
2568 aggre2_noc: interconnect@1700 1678 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 1679 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 1680 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = !! 1681 #interconnect-cells = <1>;
2572 qcom,bcm-voters = <&a 1682 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 1683 };
2574 1684
2575 mmss_noc: interconnect@174000 1685 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 1686 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 1687 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = !! 1688 #interconnect-cells = <1>;
2579 qcom,bcm-voters = <&a 1689 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 1690 };
2581 1691
2582 ufs_mem_hc: ufshc@1d84000 { 1692 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 1693 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 1694 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 !! 1695 reg = <0 0x01d84000 0 0x2500>;
2586 <0 0x01d90000 0 <<
2587 reg-names = "std", "i <<
2588 interrupts = <GIC_SPI 1696 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 1697 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 1698 phy-names = "ufsphy";
2591 lanes-per-direction = 1699 lanes-per-direction = <2>;
2592 power-domains = <&gcc 1700 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 1701 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 1702 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 1703 reset-names = "rst";
2596 1704
2597 iommus = <&apps_smmu 1705 iommus = <&apps_smmu 0x100 0xf>;
2598 1706
2599 clock-names = 1707 clock-names =
2600 "core_clk", 1708 "core_clk",
2601 "bus_aggr_clk 1709 "bus_aggr_clk",
2602 "iface_clk", 1710 "iface_clk",
2603 "core_clk_uni 1711 "core_clk_unipro",
2604 "ref_clk", 1712 "ref_clk",
2605 "tx_lane0_syn 1713 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 1714 "rx_lane0_sync_clk",
2607 "rx_lane1_syn !! 1715 "rx_lane1_sync_clk";
2608 "ice_core_clk <<
2609 clocks = 1716 clocks =
2610 <&gcc GCC_UFS 1717 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 1718 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 1719 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 1720 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 1721 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 1722 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 1723 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS !! 1724 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2618 <&gcc GCC_UFS !! 1725 freq-table-hz =
2619 !! 1726 <50000000 200000000>,
2620 operating-points-v2 = !! 1727 <0 0>,
2621 !! 1728 <0 0>,
2622 interconnects = <&agg !! 1729 <37500000 150000000>,
2623 <&gla !! 1730 <0 0>,
2624 interconnect-names = !! 1731 <0 0>,
>> 1732 <0 0>,
>> 1733 <0 0>;
2625 1734
2626 status = "disabled"; 1735 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 1736 };
2658 1737
2659 ufs_mem_phy: phy@1d87000 { 1738 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 1739 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 1740 reg = <0 0x01d87000 0 0x18c>;
2662 !! 1741 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 1742 #size-cells = <2>;
2664 <&gcc GCC_UF !! 1743 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 1744 clock-names = "ref",
2667 "ref_au !! 1745 "ref_aux";
2668 "qref"; !! 1746 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 1747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 1748
2672 resets = <&ufs_mem_hc 1749 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 1750 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 1751 status = "disabled";
2677 }; <<
2678 <<
2679 cryptobam: dma-controller@1dc <<
2680 compatible = "qcom,ba <<
2681 reg = <0 0x01dc4000 0 <<
2682 interrupts = <GIC_SPI <<
2683 clocks = <&rpmhcc RPM <<
2684 clock-names = "bam_cl <<
2685 #dma-cells = <1>; <<
2686 qcom,ee = <0>; <<
2687 qcom,controlled-remot <<
2688 iommus = <&apps_smmu <<
2689 <&apps_smmu <<
2690 <&apps_smmu <<
2691 <&apps_smmu <<
2692 }; <<
2693 1752
2694 crypto: crypto@1dfa000 { !! 1753 ufs_mem_phy_lanes: lanes@1d87400 {
2695 compatible = "qcom,cr !! 1754 reg = <0 0x01d87400 0 0x108>,
2696 reg = <0 0x01dfa000 0 !! 1755 <0 0x01d87600 0 0x1e0>,
2697 clocks = <&gcc GCC_CE !! 1756 <0 0x01d87c00 0 0x1dc>,
2698 <&gcc GCC_CE !! 1757 <0 0x01d87800 0 0x108>,
2699 <&rpmhcc RPM !! 1758 <0 0x01d87a00 0 0x1e0>;
2700 clock-names = "iface" !! 1759 #phy-cells = <0>;
2701 dmas = <&cryptobam 6> !! 1760 };
2702 dma-names = "rx", "tx <<
2703 iommus = <&apps_smmu <<
2704 <&apps_smmu <<
2705 <&apps_smmu <<
2706 <&apps_smmu <<
2707 }; 1761 };
2708 1762
2709 ipa: ipa@1e40000 { 1763 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 1764 compatible = "qcom,sdm845-ipa";
2711 1765
2712 iommus = <&apps_smmu !! 1766 iommus = <&apps_smmu 0x720 0x3>;
2713 <&apps_smmu !! 1767 reg = <0 0x1e40000 0 0x7000>,
2714 reg = <0 0x01e40000 0 !! 1768 <0 0x1e47000 0 0x2000>,
2715 <0 0x01e47000 0 !! 1769 <0 0x1e04000 0 0x2c000>;
2716 <0 0x01e04000 0 <<
2717 reg-names = "ipa-reg" 1770 reg-names = "ipa-reg",
2718 "ipa-shar 1771 "ipa-shared",
2719 "gsi"; 1772 "gsi";
2720 1773
2721 interrupts-extended = !! 1774 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
2722 !! 1775 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
2723 1776 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 1777 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 1778 interrupt-names = "ipa",
2726 "gs 1779 "gsi",
2727 "ip 1780 "ipa-clock-query",
2728 "ip 1781 "ipa-setup-ready";
2729 1782
2730 clocks = <&rpmhcc RPM 1783 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 1784 clock-names = "core";
2732 1785
2733 interconnects = <&agg !! 1786 interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>,
2734 <&agg !! 1787 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
2735 <&gla !! 1788 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
2736 interconnect-names = 1789 interconnect-names = "memory",
2737 1790 "imem",
2738 1791 "config";
2739 1792
2740 qcom,smem-states = <& 1793 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 1794 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 1795 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 1796 "ipa-clock-enabled";
2744 1797
2745 status = "disabled"; !! 1798 modem-remoteproc = <&mss_pil>;
2746 }; <<
2747 1799
2748 tcsr_mutex: hwlock@1f40000 { !! 1800 status = "disabled";
2749 compatible = "qcom,tc <<
2750 reg = <0 0x01f40000 0 <<
2751 #hwlock-cells = <1>; <<
2752 }; 1801 };
2753 1802
2754 tcsr_regs_1: syscon@1f60000 { !! 1803 tcsr_mutex_regs: syscon@1f40000 {
2755 compatible = "qcom,sd !! 1804 compatible = "syscon";
2756 reg = <0 0x01f60000 0 !! 1805 reg = <0 0x01f40000 0 0x40000>;
2757 }; 1806 };
2758 1807
2759 tlmm: pinctrl@3400000 { 1808 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 1809 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 1810 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 1811 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 1812 gpio-controller;
2764 #gpio-cells = <2>; 1813 #gpio-cells = <2>;
2765 interrupt-controller; 1814 interrupt-controller;
2766 #interrupt-cells = <2 1815 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm !! 1816 gpio-ranges = <&tlmm 0 0 150>;
2768 wakeup-parent = <&pdc 1817 wakeup-parent = <&pdc_intc>;
2769 1818
2770 cci0_default: cci0-de !! 1819 cci0_default: cci0-default {
2771 /* SDA, SCL * 1820 /* SDA, SCL */
2772 pins = "gpio1 1821 pins = "gpio17", "gpio18";
2773 function = "c 1822 function = "cci_i2c";
2774 1823
2775 bias-pull-up; 1824 bias-pull-up;
2776 drive-strengt 1825 drive-strength = <2>; /* 2 mA */
2777 }; 1826 };
2778 1827
2779 cci0_sleep: cci0-slee !! 1828 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 1829 /* SDA, SCL */
2781 pins = "gpio1 1830 pins = "gpio17", "gpio18";
2782 function = "c 1831 function = "cci_i2c";
2783 1832
2784 drive-strengt 1833 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 1834 bias-pull-down;
2786 }; 1835 };
2787 1836
2788 cci1_default: cci1-de !! 1837 cci1_default: cci1-default {
2789 /* SDA, SCL * 1838 /* SDA, SCL */
2790 pins = "gpio1 1839 pins = "gpio19", "gpio20";
2791 function = "c 1840 function = "cci_i2c";
2792 1841
2793 bias-pull-up; 1842 bias-pull-up;
2794 drive-strengt 1843 drive-strength = <2>; /* 2 mA */
2795 }; 1844 };
2796 1845
2797 cci1_sleep: cci1-slee !! 1846 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 1847 /* SDA, SCL */
2799 pins = "gpio1 1848 pins = "gpio19", "gpio20";
2800 function = "c 1849 function = "cci_i2c";
2801 1850
2802 drive-strengt 1851 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 1852 bias-pull-down;
2804 }; 1853 };
2805 1854
2806 qspi_clk: qspi-clk-st !! 1855 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 1856 pinmux {
2808 function = "q !! 1857 pins = "gpio95";
2809 }; !! 1858 function = "qspi_clk";
2810 !! 1859 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; 1860 };
2820 1861
2821 qspi_data0: qspi-data !! 1862 qspi_cs0: qspi-cs0 {
2822 pins = "gpio9 !! 1863 pinmux {
2823 function = "q !! 1864 pins = "gpio90";
>> 1865 function = "qspi_cs";
>> 1866 };
2824 }; 1867 };
2825 1868
2826 qspi_data1: qspi-data !! 1869 qspi_cs1: qspi-cs1 {
2827 pins = "gpio9 !! 1870 pinmux {
2828 function = "q !! 1871 pins = "gpio89";
>> 1872 function = "qspi_cs";
>> 1873 };
2829 }; 1874 };
2830 1875
2831 qspi_data23: qspi-dat !! 1876 qspi_data01: qspi-data01 {
2832 pins = "gpio9 !! 1877 pinmux-data {
2833 function = "q !! 1878 pins = "gpio91", "gpio92";
>> 1879 function = "qspi_data";
>> 1880 };
2834 }; 1881 };
2835 1882
2836 qup_i2c0_default: qup !! 1883 qspi_data12: qspi-data12 {
2837 pins = "gpio0 !! 1884 pinmux-data {
2838 function = "q !! 1885 pins = "gpio93", "gpio94";
>> 1886 function = "qspi_data";
>> 1887 };
2839 }; 1888 };
2840 1889
2841 qup_i2c1_default: qup !! 1890 qup_i2c0_default: qup-i2c0-default {
2842 pins = "gpio1 !! 1891 pinmux {
2843 function = "q !! 1892 pins = "gpio0", "gpio1";
>> 1893 function = "qup0";
>> 1894 };
2844 }; 1895 };
2845 1896
2846 qup_i2c2_default: qup !! 1897 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio2 !! 1898 pinmux {
2848 function = "q !! 1899 pins = "gpio17", "gpio18";
>> 1900 function = "qup1";
>> 1901 };
2849 }; 1902 };
2850 1903
2851 qup_i2c3_default: qup !! 1904 qup_i2c2_default: qup-i2c2-default {
2852 pins = "gpio4 !! 1905 pinmux {
2853 function = "q !! 1906 pins = "gpio27", "gpio28";
>> 1907 function = "qup2";
>> 1908 };
2854 }; 1909 };
2855 1910
2856 qup_i2c4_default: qup !! 1911 qup_i2c3_default: qup-i2c3-default {
2857 pins = "gpio8 !! 1912 pinmux {
2858 function = "q !! 1913 pins = "gpio41", "gpio42";
>> 1914 function = "qup3";
>> 1915 };
2859 }; 1916 };
2860 1917
2861 qup_i2c5_default: qup !! 1918 qup_i2c4_default: qup-i2c4-default {
2862 pins = "gpio8 !! 1919 pinmux {
2863 function = "q !! 1920 pins = "gpio89", "gpio90";
>> 1921 function = "qup4";
>> 1922 };
2864 }; 1923 };
2865 1924
2866 qup_i2c6_default: qup !! 1925 qup_i2c5_default: qup-i2c5-default {
2867 pins = "gpio4 !! 1926 pinmux {
2868 function = "q !! 1927 pins = "gpio85", "gpio86";
>> 1928 function = "qup5";
>> 1929 };
2869 }; 1930 };
2870 1931
2871 qup_i2c7_default: qup !! 1932 qup_i2c6_default: qup-i2c6-default {
2872 pins = "gpio9 !! 1933 pinmux {
2873 function = "q !! 1934 pins = "gpio45", "gpio46";
>> 1935 function = "qup6";
>> 1936 };
2874 }; 1937 };
2875 1938
2876 qup_i2c8_default: qup !! 1939 qup_i2c7_default: qup-i2c7-default {
2877 pins = "gpio6 !! 1940 pinmux {
2878 function = "q !! 1941 pins = "gpio93", "gpio94";
>> 1942 function = "qup7";
>> 1943 };
2879 }; 1944 };
2880 1945
2881 qup_i2c9_default: qup !! 1946 qup_i2c8_default: qup-i2c8-default {
2882 pins = "gpio6 !! 1947 pinmux {
2883 function = "q !! 1948 pins = "gpio65", "gpio66";
>> 1949 function = "qup8";
>> 1950 };
2884 }; 1951 };
2885 1952
2886 qup_i2c10_default: qu !! 1953 qup_i2c9_default: qup-i2c9-default {
2887 pins = "gpio5 !! 1954 pinmux {
2888 function = "q !! 1955 pins = "gpio6", "gpio7";
>> 1956 function = "qup9";
>> 1957 };
2889 }; 1958 };
2890 1959
2891 qup_i2c11_default: qu !! 1960 qup_i2c10_default: qup-i2c10-default {
2892 pins = "gpio3 !! 1961 pinmux {
2893 function = "q !! 1962 pins = "gpio55", "gpio56";
>> 1963 function = "qup10";
>> 1964 };
2894 }; 1965 };
2895 1966
2896 qup_i2c12_default: qu !! 1967 qup_i2c11_default: qup-i2c11-default {
2897 pins = "gpio4 !! 1968 pinmux {
2898 function = "q !! 1969 pins = "gpio31", "gpio32";
>> 1970 function = "qup11";
>> 1971 };
2899 }; 1972 };
2900 1973
2901 qup_i2c13_default: qu !! 1974 qup_i2c12_default: qup-i2c12-default {
2902 pins = "gpio1 !! 1975 pinmux {
2903 function = "q !! 1976 pins = "gpio49", "gpio50";
>> 1977 function = "qup12";
>> 1978 };
2904 }; 1979 };
2905 1980
2906 qup_i2c14_default: qu !! 1981 qup_i2c13_default: qup-i2c13-default {
2907 pins = "gpio3 !! 1982 pinmux {
2908 function = "q !! 1983 pins = "gpio105", "gpio106";
>> 1984 function = "qup13";
>> 1985 };
2909 }; 1986 };
2910 1987
2911 qup_i2c15_default: qu !! 1988 qup_i2c14_default: qup-i2c14-default {
2912 pins = "gpio8 !! 1989 pinmux {
2913 function = "q !! 1990 pins = "gpio33", "gpio34";
>> 1991 function = "qup14";
>> 1992 };
2914 }; 1993 };
2915 1994
2916 qup_spi0_default: qup !! 1995 qup_i2c15_default: qup-i2c15-default {
2917 pins = "gpio0 !! 1996 pinmux {
2918 function = "q !! 1997 pins = "gpio81", "gpio82";
>> 1998 function = "qup15";
>> 1999 };
2919 }; 2000 };
2920 2001
2921 qup_spi1_default: qup !! 2002 qup_spi0_default: qup-spi0-default {
2922 pins = "gpio1 !! 2003 pinmux {
2923 function = "q !! 2004 pins = "gpio0", "gpio1",
>> 2005 "gpio2", "gpio3";
>> 2006 function = "qup0";
>> 2007 };
2924 }; 2008 };
2925 2009
2926 qup_spi2_default: qup !! 2010 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2011 pinmux {
2928 function = "q !! 2012 pins = "gpio17", "gpio18",
>> 2013 "gpio19", "gpio20";
>> 2014 function = "qup1";
>> 2015 };
2929 }; 2016 };
2930 2017
2931 qup_spi3_default: qup !! 2018 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2019 pinmux {
2933 function = "q !! 2020 pins = "gpio27", "gpio28",
>> 2021 "gpio29", "gpio30";
>> 2022 function = "qup2";
>> 2023 };
2934 }; 2024 };
2935 2025
2936 qup_spi4_default: qup !! 2026 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2027 pinmux {
2938 function = "q !! 2028 pins = "gpio41", "gpio42",
>> 2029 "gpio43", "gpio44";
>> 2030 function = "qup3";
>> 2031 };
2939 }; 2032 };
2940 2033
2941 qup_spi5_default: qup !! 2034 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2035 pinmux {
2943 function = "q !! 2036 pins = "gpio89", "gpio90",
>> 2037 "gpio91", "gpio92";
>> 2038 function = "qup4";
>> 2039 };
2944 }; 2040 };
2945 2041
2946 qup_spi6_default: qup !! 2042 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2043 pinmux {
2948 function = "q !! 2044 pins = "gpio85", "gpio86",
>> 2045 "gpio87", "gpio88";
>> 2046 function = "qup5";
>> 2047 };
2949 }; 2048 };
2950 2049
2951 qup_spi7_default: qup !! 2050 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2051 pinmux {
2953 function = "q !! 2052 pins = "gpio45", "gpio46",
>> 2053 "gpio47", "gpio48";
>> 2054 function = "qup6";
>> 2055 };
2954 }; 2056 };
2955 2057
2956 qup_spi8_default: qup !! 2058 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2059 pinmux {
2958 function = "q !! 2060 pins = "gpio93", "gpio94",
>> 2061 "gpio95", "gpio96";
>> 2062 function = "qup7";
>> 2063 };
2959 }; 2064 };
2960 2065
2961 qup_spi9_default: qup !! 2066 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2067 pinmux {
2963 function = "q !! 2068 pins = "gpio65", "gpio66",
>> 2069 "gpio67", "gpio68";
>> 2070 function = "qup8";
>> 2071 };
2964 }; 2072 };
2965 2073
2966 qup_spi10_default: qu !! 2074 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2075 pinmux {
2968 function = "q !! 2076 pins = "gpio6", "gpio7",
>> 2077 "gpio4", "gpio5";
>> 2078 function = "qup9";
>> 2079 };
2969 }; 2080 };
2970 2081
2971 qup_spi11_default: qu !! 2082 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2083 pinmux {
2973 function = "q !! 2084 pins = "gpio55", "gpio56",
>> 2085 "gpio53", "gpio54";
>> 2086 function = "qup10";
>> 2087 };
2974 }; 2088 };
2975 2089
2976 qup_spi12_default: qu !! 2090 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2091 pinmux {
2978 function = "q !! 2092 pins = "gpio31", "gpio32",
>> 2093 "gpio33", "gpio34";
>> 2094 function = "qup11";
>> 2095 };
2979 }; 2096 };
2980 2097
2981 qup_spi13_default: qu !! 2098 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2099 pinmux {
2983 function = "q !! 2100 pins = "gpio49", "gpio50",
>> 2101 "gpio51", "gpio52";
>> 2102 function = "qup12";
>> 2103 };
2984 }; 2104 };
2985 2105
2986 qup_spi14_default: qu !! 2106 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2107 pinmux {
2988 function = "q !! 2108 pins = "gpio105", "gpio106",
>> 2109 "gpio107", "gpio108";
>> 2110 function = "qup13";
>> 2111 };
2989 }; 2112 };
2990 2113
2991 qup_spi15_default: qu !! 2114 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2115 pinmux {
2993 function = "q !! 2116 pins = "gpio33", "gpio34",
>> 2117 "gpio31", "gpio32";
>> 2118 function = "qup14";
>> 2119 };
2994 }; 2120 };
2995 2121
2996 qup_uart0_default: qu !! 2122 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2123 pinmux {
2998 pins !! 2124 pins = "gpio81", "gpio82",
2999 funct !! 2125 "gpio83", "gpio84";
>> 2126 function = "qup15";
3000 }; 2127 };
>> 2128 };
3001 2129
3002 qup_uart0_rx: !! 2130 qup_uart0_default: qup-uart0-default {
3003 pins !! 2131 pinmux {
>> 2132 pins = "gpio2", "gpio3";
3004 funct 2133 function = "qup0";
3005 }; 2134 };
3006 }; 2135 };
3007 2136
3008 qup_uart1_default: qu !! 2137 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2138 pinmux {
3010 pins !! 2139 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2140 function = "qup1";
3017 }; 2141 };
3018 }; 2142 };
3019 2143
3020 qup_uart2_default: qu !! 2144 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2145 pinmux {
3022 pins !! 2146 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2147 function = "qup2";
3029 }; 2148 };
3030 }; 2149 };
3031 2150
3032 qup_uart3_default: qu !! 2151 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2152 pinmux {
3034 pins !! 2153 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2154 function = "qup3";
3041 }; 2155 };
3042 }; 2156 };
3043 2157
3044 qup_uart3_4pin: qup-u !! 2158 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2159 pinmux {
3046 pins !! 2160 pins = "gpio91", "gpio92";
3047 funct !! 2161 function = "qup4";
3048 }; 2162 };
>> 2163 };
3049 2164
3050 qup_uart3_4pi !! 2165 qup_uart5_default: qup-uart5-default {
3051 pins !! 2166 pinmux {
3052 funct !! 2167 pins = "gpio87", "gpio88";
>> 2168 function = "qup5";
3053 }; 2169 };
>> 2170 };
3054 2171
3055 qup_uart3_4pi !! 2172 qup_uart6_default: qup-uart6-default {
3056 pins !! 2173 pinmux {
3057 funct !! 2174 pins = "gpio47", "gpio48";
>> 2175 function = "qup6";
3058 }; 2176 };
3059 }; 2177 };
3060 2178
3061 qup_uart4_default: qu !! 2179 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 2180 pinmux {
3063 pins !! 2181 pins = "gpio95", "gpio96";
3064 funct !! 2182 function = "qup7";
3065 }; 2183 };
>> 2184 };
3066 2185
3067 qup_uart4_rx: !! 2186 qup_uart8_default: qup-uart8-default {
3068 pins !! 2187 pinmux {
3069 funct !! 2188 pins = "gpio67", "gpio68";
>> 2189 function = "qup8";
3070 }; 2190 };
3071 }; 2191 };
3072 2192
3073 qup_uart5_default: qu !! 2193 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 2194 pinmux {
3075 pins !! 2195 pins = "gpio4", "gpio5";
3076 funct !! 2196 function = "qup9";
3077 }; 2197 };
>> 2198 };
3078 2199
3079 qup_uart5_rx: !! 2200 qup_uart10_default: qup-uart10-default {
3080 pins !! 2201 pinmux {
3081 funct !! 2202 pins = "gpio53", "gpio54";
>> 2203 function = "qup10";
3082 }; 2204 };
3083 }; 2205 };
3084 2206
3085 qup_uart6_default: qu !! 2207 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 2208 pinmux {
3087 pins !! 2209 pins = "gpio33", "gpio34";
3088 funct !! 2210 function = "qup11";
3089 }; 2211 };
>> 2212 };
3090 2213
3091 qup_uart6_rx: !! 2214 qup_uart12_default: qup-uart12-default {
3092 pins !! 2215 pinmux {
3093 funct !! 2216 pins = "gpio51", "gpio52";
>> 2217 function = "qup12";
3094 }; 2218 };
3095 }; 2219 };
3096 2220
3097 qup_uart6_4pin: qup-u !! 2221 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 2222 pinmux {
3099 pins !! 2223 pins = "gpio107", "gpio108";
3100 funct !! 2224 function = "qup13";
3101 bias- <<
3102 }; 2225 };
>> 2226 };
3103 2227
3104 qup_uart6_4pi !! 2228 qup_uart14_default: qup-uart14-default {
3105 pins !! 2229 pinmux {
3106 funct !! 2230 pins = "gpio31", "gpio32";
3107 drive !! 2231 function = "qup14";
3108 bias- <<
3109 }; 2232 };
>> 2233 };
3110 2234
3111 qup_uart6_4pi !! 2235 qup_uart15_default: qup-uart15-default {
3112 pins !! 2236 pinmux {
3113 funct !! 2237 pins = "gpio83", "gpio84";
3114 bias- !! 2238 function = "qup15";
3115 }; 2239 };
3116 }; 2240 };
3117 2241
3118 qup_uart7_default: qu !! 2242 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 2243 mux {
3120 pins !! 2244 pins = "gpio58", "gpio59";
3121 funct !! 2245 function = "gpio";
3122 }; 2246 };
3123 2247
3124 qup_uart7_rx: !! 2248 config {
3125 pins !! 2249 pins = "gpio58", "gpio59";
3126 funct !! 2250 drive-strength = <2>;
>> 2251 bias-pull-down;
>> 2252 input-enable;
3127 }; 2253 };
3128 }; 2254 };
3129 2255
3130 qup_uart8_default: qu !! 2256 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 2257 mux {
3132 pins !! 2258 pins = "gpio58", "gpio59";
3133 funct !! 2259 function = "qua_mi2s";
3134 }; 2260 };
3135 2261
3136 qup_uart8_rx: !! 2262 config {
3137 pins !! 2263 pins = "gpio58", "gpio59";
3138 funct !! 2264 drive-strength = <8>;
>> 2265 bias-disable;
>> 2266 output-high;
3139 }; 2267 };
3140 }; 2268 };
3141 2269
3142 qup_uart9_default: qu !! 2270 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 2271 mux {
3144 pins !! 2272 pins = "gpio60";
3145 funct !! 2273 function = "gpio";
3146 }; 2274 };
3147 2275
3148 qup_uart9_rx: !! 2276 config {
3149 pins !! 2277 pins = "gpio60";
3150 funct !! 2278 drive-strength = <2>;
>> 2279 bias-pull-down;
>> 2280 input-enable;
3151 }; 2281 };
3152 }; 2282 };
3153 2283
3154 qup_uart10_default: q !! 2284 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 2285 mux {
3156 pins !! 2286 pins = "gpio60";
3157 funct !! 2287 function = "qua_mi2s";
3158 }; 2288 };
3159 2289
3160 qup_uart10_rx !! 2290 config {
3161 pins !! 2291 pins = "gpio60";
3162 funct !! 2292 drive-strength = <8>;
>> 2293 bias-disable;
3163 }; 2294 };
3164 }; 2295 };
3165 2296
3166 qup_uart11_default: q !! 2297 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 2298 mux {
3168 pins !! 2299 pins = "gpio61";
3169 funct !! 2300 function = "gpio";
3170 }; 2301 };
3171 2302
3172 qup_uart11_rx !! 2303 config {
3173 pins !! 2304 pins = "gpio61";
3174 funct !! 2305 drive-strength = <2>;
>> 2306 bias-pull-down;
>> 2307 input-enable;
3175 }; 2308 };
3176 }; 2309 };
3177 2310
3178 qup_uart12_default: q !! 2311 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 2312 mux {
3180 pins !! 2313 pins = "gpio61";
3181 funct !! 2314 function = "qua_mi2s";
3182 }; 2315 };
3183 2316
3184 qup_uart12_rx !! 2317 config {
3185 pins !! 2318 pins = "gpio61";
3186 funct !! 2319 drive-strength = <8>;
>> 2320 bias-disable;
3187 }; 2321 };
3188 }; 2322 };
3189 2323
3190 qup_uart13_default: q !! 2324 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 2325 mux {
3192 pins !! 2326 pins = "gpio62";
3193 funct !! 2327 function = "gpio";
3194 }; 2328 };
3195 2329
3196 qup_uart13_rx !! 2330 config {
3197 pins !! 2331 pins = "gpio62";
3198 funct !! 2332 drive-strength = <2>;
>> 2333 bias-pull-down;
>> 2334 input-enable;
3199 }; 2335 };
3200 }; 2336 };
3201 2337
3202 qup_uart14_default: q !! 2338 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 2339 mux {
3204 pins !! 2340 pins = "gpio62";
3205 funct !! 2341 function = "qua_mi2s";
3206 }; 2342 };
3207 2343
3208 qup_uart14_rx !! 2344 config {
3209 pins !! 2345 pins = "gpio62";
3210 funct !! 2346 drive-strength = <8>;
>> 2347 bias-disable;
3211 }; 2348 };
3212 }; 2349 };
3213 2350
3214 qup_uart15_default: q !! 2351 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 2352 mux {
3216 pins !! 2353 pins = "gpio63";
3217 funct !! 2354 function = "gpio";
3218 }; 2355 };
3219 2356
3220 qup_uart15_rx !! 2357 config {
3221 pins !! 2358 pins = "gpio63";
3222 funct !! 2359 drive-strength = <2>;
>> 2360 bias-pull-down;
>> 2361 input-enable;
3223 }; 2362 };
3224 }; 2363 };
3225 2364
3226 quat_mi2s_sleep: quat !! 2365 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 2366 mux {
3228 function = "g !! 2367 pins = "gpio63";
3229 drive-strengt !! 2368 function = "qua_mi2s";
3230 bias-pull-dow !! 2369 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 2370
3290 quat_mi2s_sd3_active: !! 2371 config {
3291 pins = "gpio6 !! 2372 pins = "gpio63";
3292 function = "q !! 2373 drive-strength = <8>;
3293 drive-strengt !! 2374 bias-disable;
3294 bias-disable; !! 2375 };
3295 }; 2376 };
3296 }; 2377 };
3297 2378
3298 mss_pil: remoteproc@4080000 { 2379 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 2380 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 2381 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 2382 reg-names = "qdsp6", "rmb";
3302 2383
3303 interrupts-extended = 2384 interrupts-extended =
3304 <&intc GIC_SP 2385 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 2386 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 2387 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 2388 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 2389 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 2390 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 2391 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 2392 "handover", "stop-ack",
3312 "sh 2393 "shutdown-ack";
3313 2394
3314 clocks = <&gcc GCC_MS 2395 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 2396 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 2397 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 2398 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 2399 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 2400 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 2401 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 2402 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 2403 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 2404 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 2405
3325 qcom,qmp = <&aoss_qmp <<
3326 <<
3327 qcom,smem-states = <& 2406 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 2407 qcom,smem-state-names = "stop";
3329 2408
3330 resets = <&aoss_reset 2409 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 2410 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 2411 reset-names = "mss_restart", "pdc_reset";
3333 2412
3334 qcom,halt-regs = <&tc !! 2413 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 2414
3336 power-domains = <&rpm !! 2415 power-domains = <&aoss_qmp 2>,
>> 2416 <&rpmhpd SDM845_CX>,
3337 <&rpm 2417 <&rpmhpd SDM845_MX>,
3338 <&rpm 2418 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = !! 2419 power-domain-names = "load_state", "cx", "mx", "mss";
3340 <<
3341 status = "disabled"; <<
3342 2420
3343 mba { 2421 mba {
3344 memory-region 2422 memory-region = <&mba_region>;
3345 }; 2423 };
3346 2424
3347 mpss { 2425 mpss {
3348 memory-region 2426 memory-region = <&mpss_region>;
3349 }; 2427 };
3350 2428
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 2429 glink-edge {
3356 interrupts = 2430 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 2431 label = "modem";
3358 qcom,remote-p 2432 qcom,remote-pid = <1>;
3359 mboxes = <&ap 2433 mboxes = <&apss_shared 12>;
3360 }; 2434 };
3361 }; 2435 };
3362 2436
3363 gpucc: clock-controller@50900 2437 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 2438 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 2439 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 2440 #clock-cells = <1>;
3367 #reset-cells = <1>; 2441 #reset-cells = <1>;
3368 #power-domain-cells = 2442 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 2443 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 2444 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 2445 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 2446 clock-names = "bi_tcxo",
3373 "gcc_gp 2447 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 2448 "gcc_gpu_gpll0_div_clk_src";
3375 }; 2449 };
3376 2450
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 2451 stm@6002000 {
3431 compatible = "arm,cor 2452 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 2453 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 2454 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 2455 reg-names = "stm-base", "stm-stimulus-base";
3435 2456
3436 clocks = <&aoss_qmp>; 2457 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 2458 clock-names = "apb_pclk";
3438 2459
3439 out-ports { 2460 out-ports {
3440 port { 2461 port {
3441 stm_o 2462 stm_out: endpoint {
3442 2463 remote-endpoint =
3443 2464 <&funnel0_in7>;
3444 }; 2465 };
3445 }; 2466 };
3446 }; 2467 };
3447 }; 2468 };
3448 2469
3449 funnel@6041000 { 2470 funnel@6041000 {
3450 compatible = "arm,cor 2471 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 2472 reg = <0 0x06041000 0 0x1000>;
3452 2473
3453 clocks = <&aoss_qmp>; 2474 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 2475 clock-names = "apb_pclk";
3455 2476
3456 out-ports { 2477 out-ports {
3457 port { 2478 port {
3458 funne 2479 funnel0_out: endpoint {
3459 2480 remote-endpoint =
3460 2481 <&merge_funnel_in0>;
3461 }; 2482 };
3462 }; 2483 };
3463 }; 2484 };
3464 2485
3465 in-ports { 2486 in-ports {
3466 #address-cell 2487 #address-cells = <1>;
3467 #size-cells = 2488 #size-cells = <0>;
3468 2489
3469 port@7 { 2490 port@7 {
3470 reg = 2491 reg = <7>;
3471 funne 2492 funnel0_in7: endpoint {
3472 2493 remote-endpoint = <&stm_out>;
3473 }; 2494 };
3474 }; 2495 };
3475 }; 2496 };
3476 }; 2497 };
3477 2498
3478 funnel@6043000 { 2499 funnel@6043000 {
3479 compatible = "arm,cor 2500 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 2501 reg = <0 0x06043000 0 0x1000>;
3481 2502
3482 clocks = <&aoss_qmp>; 2503 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 2504 clock-names = "apb_pclk";
3484 2505
3485 out-ports { 2506 out-ports {
3486 port { 2507 port {
3487 funne 2508 funnel2_out: endpoint {
3488 2509 remote-endpoint =
3489 2510 <&merge_funnel_in2>;
3490 }; 2511 };
3491 }; 2512 };
3492 }; 2513 };
3493 2514
3494 in-ports { 2515 in-ports {
3495 #address-cell 2516 #address-cells = <1>;
3496 #size-cells = 2517 #size-cells = <0>;
3497 2518
3498 port@5 { 2519 port@5 {
3499 reg = 2520 reg = <5>;
3500 funne 2521 funnel2_in5: endpoint {
3501 2522 remote-endpoint =
3502 2523 <&apss_merge_funnel_out>;
3503 }; 2524 };
3504 }; 2525 };
3505 }; 2526 };
3506 }; 2527 };
3507 2528
3508 funnel@6045000 { 2529 funnel@6045000 {
3509 compatible = "arm,cor 2530 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 2531 reg = <0 0x06045000 0 0x1000>;
3511 2532
3512 clocks = <&aoss_qmp>; 2533 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 2534 clock-names = "apb_pclk";
3514 2535
3515 out-ports { 2536 out-ports {
3516 port { 2537 port {
3517 merge 2538 merge_funnel_out: endpoint {
3518 2539 remote-endpoint = <&etf_in>;
3519 }; 2540 };
3520 }; 2541 };
3521 }; 2542 };
3522 2543
3523 in-ports { 2544 in-ports {
3524 #address-cell 2545 #address-cells = <1>;
3525 #size-cells = 2546 #size-cells = <0>;
3526 2547
3527 port@0 { 2548 port@0 {
3528 reg = 2549 reg = <0>;
3529 merge 2550 merge_funnel_in0: endpoint {
3530 2551 remote-endpoint =
3531 2552 <&funnel0_out>;
3532 }; 2553 };
3533 }; 2554 };
3534 2555
3535 port@2 { 2556 port@2 {
3536 reg = 2557 reg = <2>;
3537 merge 2558 merge_funnel_in2: endpoint {
3538 2559 remote-endpoint =
3539 2560 <&funnel2_out>;
3540 }; 2561 };
3541 }; 2562 };
3542 }; 2563 };
3543 }; 2564 };
3544 2565
3545 replicator@6046000 { 2566 replicator@6046000 {
3546 compatible = "arm,cor 2567 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 2568 reg = <0 0x06046000 0 0x1000>;
3548 2569
3549 clocks = <&aoss_qmp>; 2570 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 2571 clock-names = "apb_pclk";
3551 2572
3552 out-ports { 2573 out-ports {
3553 port { 2574 port {
3554 repli 2575 replicator_out: endpoint {
3555 2576 remote-endpoint = <&etr_in>;
3556 }; 2577 };
3557 }; 2578 };
3558 }; 2579 };
3559 2580
3560 in-ports { 2581 in-ports {
3561 port { 2582 port {
3562 repli 2583 replicator_in: endpoint {
3563 2584 remote-endpoint = <&etf_out>;
3564 }; 2585 };
3565 }; 2586 };
3566 }; 2587 };
3567 }; 2588 };
3568 2589
3569 etf@6047000 { 2590 etf@6047000 {
3570 compatible = "arm,cor 2591 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 2592 reg = <0 0x06047000 0 0x1000>;
3572 2593
3573 clocks = <&aoss_qmp>; 2594 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 2595 clock-names = "apb_pclk";
3575 2596
3576 out-ports { 2597 out-ports {
3577 port { 2598 port {
3578 etf_o 2599 etf_out: endpoint {
3579 2600 remote-endpoint =
3580 2601 <&replicator_in>;
3581 }; 2602 };
3582 }; 2603 };
3583 }; 2604 };
3584 2605
3585 in-ports { 2606 in-ports {
>> 2607 #address-cells = <1>;
>> 2608 #size-cells = <0>;
3586 2609
3587 port { !! 2610 port@1 {
>> 2611 reg = <1>;
3588 etf_i 2612 etf_in: endpoint {
3589 2613 remote-endpoint =
3590 2614 <&merge_funnel_out>;
3591 }; 2615 };
3592 }; 2616 };
3593 }; 2617 };
3594 }; 2618 };
3595 2619
3596 etr@6048000 { 2620 etr@6048000 {
3597 compatible = "arm,cor 2621 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 2622 reg = <0 0x06048000 0 0x1000>;
3599 2623
3600 clocks = <&aoss_qmp>; 2624 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 2625 clock-names = "apb_pclk";
3602 arm,scatter-gather; 2626 arm,scatter-gather;
3603 2627
3604 in-ports { 2628 in-ports {
3605 port { 2629 port {
3606 etr_i 2630 etr_in: endpoint {
3607 2631 remote-endpoint =
3608 2632 <&replicator_out>;
3609 }; 2633 };
3610 }; 2634 };
3611 }; 2635 };
3612 }; 2636 };
3613 2637
3614 etm@7040000 { 2638 etm@7040000 {
3615 compatible = "arm,cor 2639 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 2640 reg = <0 0x07040000 0 0x1000>;
3617 2641
3618 cpu = <&CPU0>; 2642 cpu = <&CPU0>;
3619 2643
3620 clocks = <&aoss_qmp>; 2644 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 2645 clock-names = "apb_pclk";
3622 arm,coresight-loses-c <<
3623 2646
3624 out-ports { 2647 out-ports {
3625 port { 2648 port {
3626 etm0_ 2649 etm0_out: endpoint {
3627 2650 remote-endpoint =
3628 2651 <&apss_funnel_in0>;
3629 }; 2652 };
3630 }; 2653 };
3631 }; 2654 };
3632 }; 2655 };
3633 2656
3634 etm@7140000 { 2657 etm@7140000 {
3635 compatible = "arm,cor 2658 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 2659 reg = <0 0x07140000 0 0x1000>;
3637 2660
3638 cpu = <&CPU1>; 2661 cpu = <&CPU1>;
3639 2662
3640 clocks = <&aoss_qmp>; 2663 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 2664 clock-names = "apb_pclk";
3642 arm,coresight-loses-c <<
3643 2665
3644 out-ports { 2666 out-ports {
3645 port { 2667 port {
3646 etm1_ 2668 etm1_out: endpoint {
3647 2669 remote-endpoint =
3648 2670 <&apss_funnel_in1>;
3649 }; 2671 };
3650 }; 2672 };
3651 }; 2673 };
3652 }; 2674 };
3653 2675
3654 etm@7240000 { 2676 etm@7240000 {
3655 compatible = "arm,cor 2677 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 2678 reg = <0 0x07240000 0 0x1000>;
3657 2679
3658 cpu = <&CPU2>; 2680 cpu = <&CPU2>;
3659 2681
3660 clocks = <&aoss_qmp>; 2682 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 2683 clock-names = "apb_pclk";
3662 arm,coresight-loses-c <<
3663 2684
3664 out-ports { 2685 out-ports {
3665 port { 2686 port {
3666 etm2_ 2687 etm2_out: endpoint {
3667 2688 remote-endpoint =
3668 2689 <&apss_funnel_in2>;
3669 }; 2690 };
3670 }; 2691 };
3671 }; 2692 };
3672 }; 2693 };
3673 2694
3674 etm@7340000 { 2695 etm@7340000 {
3675 compatible = "arm,cor 2696 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 2697 reg = <0 0x07340000 0 0x1000>;
3677 2698
3678 cpu = <&CPU3>; 2699 cpu = <&CPU3>;
3679 2700
3680 clocks = <&aoss_qmp>; 2701 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 2702 clock-names = "apb_pclk";
3682 arm,coresight-loses-c <<
3683 2703
3684 out-ports { 2704 out-ports {
3685 port { 2705 port {
3686 etm3_ 2706 etm3_out: endpoint {
3687 2707 remote-endpoint =
3688 2708 <&apss_funnel_in3>;
3689 }; 2709 };
3690 }; 2710 };
3691 }; 2711 };
3692 }; 2712 };
3693 2713
3694 etm@7440000 { 2714 etm@7440000 {
3695 compatible = "arm,cor 2715 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 2716 reg = <0 0x07440000 0 0x1000>;
3697 2717
3698 cpu = <&CPU4>; 2718 cpu = <&CPU4>;
3699 2719
3700 clocks = <&aoss_qmp>; 2720 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 2721 clock-names = "apb_pclk";
3702 arm,coresight-loses-c <<
3703 2722
3704 out-ports { 2723 out-ports {
3705 port { 2724 port {
3706 etm4_ 2725 etm4_out: endpoint {
3707 2726 remote-endpoint =
3708 2727 <&apss_funnel_in4>;
3709 }; 2728 };
3710 }; 2729 };
3711 }; 2730 };
3712 }; 2731 };
3713 2732
3714 etm@7540000 { 2733 etm@7540000 {
3715 compatible = "arm,cor 2734 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 2735 reg = <0 0x07540000 0 0x1000>;
3717 2736
3718 cpu = <&CPU5>; 2737 cpu = <&CPU5>;
3719 2738
3720 clocks = <&aoss_qmp>; 2739 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 2740 clock-names = "apb_pclk";
3722 arm,coresight-loses-c <<
3723 2741
3724 out-ports { 2742 out-ports {
3725 port { 2743 port {
3726 etm5_ 2744 etm5_out: endpoint {
3727 2745 remote-endpoint =
3728 2746 <&apss_funnel_in5>;
3729 }; 2747 };
3730 }; 2748 };
3731 }; 2749 };
3732 }; 2750 };
3733 2751
3734 etm@7640000 { 2752 etm@7640000 {
3735 compatible = "arm,cor 2753 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 2754 reg = <0 0x07640000 0 0x1000>;
3737 2755
3738 cpu = <&CPU6>; 2756 cpu = <&CPU6>;
3739 2757
3740 clocks = <&aoss_qmp>; 2758 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 2759 clock-names = "apb_pclk";
3742 arm,coresight-loses-c <<
3743 2760
3744 out-ports { 2761 out-ports {
3745 port { 2762 port {
3746 etm6_ 2763 etm6_out: endpoint {
3747 2764 remote-endpoint =
3748 2765 <&apss_funnel_in6>;
3749 }; 2766 };
3750 }; 2767 };
3751 }; 2768 };
3752 }; 2769 };
3753 2770
3754 etm@7740000 { 2771 etm@7740000 {
3755 compatible = "arm,cor 2772 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 2773 reg = <0 0x07740000 0 0x1000>;
3757 2774
3758 cpu = <&CPU7>; 2775 cpu = <&CPU7>;
3759 2776
3760 clocks = <&aoss_qmp>; 2777 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 2778 clock-names = "apb_pclk";
3762 arm,coresight-loses-c <<
3763 2779
3764 out-ports { 2780 out-ports {
3765 port { 2781 port {
3766 etm7_ 2782 etm7_out: endpoint {
3767 2783 remote-endpoint =
3768 2784 <&apss_funnel_in7>;
3769 }; 2785 };
3770 }; 2786 };
3771 }; 2787 };
3772 }; 2788 };
3773 2789
3774 funnel@7800000 { /* APSS Funn 2790 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 2791 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 2792 reg = <0 0x07800000 0 0x1000>;
3777 2793
3778 clocks = <&aoss_qmp>; 2794 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 2795 clock-names = "apb_pclk";
3780 2796
3781 out-ports { 2797 out-ports {
3782 port { 2798 port {
3783 apss_ 2799 apss_funnel_out: endpoint {
3784 2800 remote-endpoint =
3785 2801 <&apss_merge_funnel_in>;
3786 }; 2802 };
3787 }; 2803 };
3788 }; 2804 };
3789 2805
3790 in-ports { 2806 in-ports {
3791 #address-cell 2807 #address-cells = <1>;
3792 #size-cells = 2808 #size-cells = <0>;
3793 2809
3794 port@0 { 2810 port@0 {
3795 reg = 2811 reg = <0>;
3796 apss_ 2812 apss_funnel_in0: endpoint {
3797 2813 remote-endpoint =
3798 2814 <&etm0_out>;
3799 }; 2815 };
3800 }; 2816 };
3801 2817
3802 port@1 { 2818 port@1 {
3803 reg = 2819 reg = <1>;
3804 apss_ 2820 apss_funnel_in1: endpoint {
3805 2821 remote-endpoint =
3806 2822 <&etm1_out>;
3807 }; 2823 };
3808 }; 2824 };
3809 2825
3810 port@2 { 2826 port@2 {
3811 reg = 2827 reg = <2>;
3812 apss_ 2828 apss_funnel_in2: endpoint {
3813 2829 remote-endpoint =
3814 2830 <&etm2_out>;
3815 }; 2831 };
3816 }; 2832 };
3817 2833
3818 port@3 { 2834 port@3 {
3819 reg = 2835 reg = <3>;
3820 apss_ 2836 apss_funnel_in3: endpoint {
3821 2837 remote-endpoint =
3822 2838 <&etm3_out>;
3823 }; 2839 };
3824 }; 2840 };
3825 2841
3826 port@4 { 2842 port@4 {
3827 reg = 2843 reg = <4>;
3828 apss_ 2844 apss_funnel_in4: endpoint {
3829 2845 remote-endpoint =
3830 2846 <&etm4_out>;
3831 }; 2847 };
3832 }; 2848 };
3833 2849
3834 port@5 { 2850 port@5 {
3835 reg = 2851 reg = <5>;
3836 apss_ 2852 apss_funnel_in5: endpoint {
3837 2853 remote-endpoint =
3838 2854 <&etm5_out>;
3839 }; 2855 };
3840 }; 2856 };
3841 2857
3842 port@6 { 2858 port@6 {
3843 reg = 2859 reg = <6>;
3844 apss_ 2860 apss_funnel_in6: endpoint {
3845 2861 remote-endpoint =
3846 2862 <&etm6_out>;
3847 }; 2863 };
3848 }; 2864 };
3849 2865
3850 port@7 { 2866 port@7 {
3851 reg = 2867 reg = <7>;
3852 apss_ 2868 apss_funnel_in7: endpoint {
3853 2869 remote-endpoint =
3854 2870 <&etm7_out>;
3855 }; 2871 };
3856 }; 2872 };
3857 }; 2873 };
3858 }; 2874 };
3859 2875
3860 funnel@7810000 { 2876 funnel@7810000 {
3861 compatible = "arm,cor 2877 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 2878 reg = <0 0x07810000 0 0x1000>;
3863 2879
3864 clocks = <&aoss_qmp>; 2880 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 2881 clock-names = "apb_pclk";
3866 2882
3867 out-ports { 2883 out-ports {
3868 port { 2884 port {
3869 apss_ 2885 apss_merge_funnel_out: endpoint {
3870 2886 remote-endpoint =
3871 2887 <&funnel2_in5>;
3872 }; 2888 };
3873 }; 2889 };
3874 }; 2890 };
3875 2891
3876 in-ports { 2892 in-ports {
3877 port { 2893 port {
3878 apss_ 2894 apss_merge_funnel_in: endpoint {
3879 2895 remote-endpoint =
3880 2896 <&apss_funnel_out>;
3881 }; 2897 };
3882 }; 2898 };
3883 }; 2899 };
3884 }; 2900 };
3885 2901
3886 sdhc_2: mmc@8804000 { !! 2902 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 2903 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 2904 reg = <0 0x08804000 0 0x1000>;
3889 2905
3890 interrupts = <GIC_SPI 2906 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 2907 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 2908 interrupt-names = "hc_irq", "pwr_irq";
3893 2909
3894 clocks = <&gcc GCC_SD 2910 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD !! 2911 <&gcc GCC_SDCC2_APPS_CLK>;
3896 <&rpmhcc RPM !! 2912 clock-names = "iface", "core";
3897 clock-names = "iface" <<
3898 iommus = <&apps_smmu 2913 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm <<
3900 operating-points-v2 = <<
3901 2914
3902 status = "disabled"; 2915 status = "disabled";
3903 <<
3904 sdhc2_opp_table: opp- <<
3905 compatible = <<
3906 <<
3907 opp-9600000 { <<
3908 opp-h <<
3909 requi <<
3910 }; <<
3911 <<
3912 opp-19200000 <<
3913 opp-h <<
3914 requi <<
3915 }; <<
3916 <<
3917 opp-100000000 <<
3918 opp-h <<
3919 requi <<
3920 }; <<
3921 <<
3922 opp-201500000 <<
3923 opp-h <<
3924 requi <<
3925 }; <<
3926 }; <<
3927 }; 2916 };
3928 2917
3929 qspi: spi@88df000 { 2918 qspi: spi@88df000 {
3930 compatible = "qcom,sd 2919 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 2920 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 2921 #address-cells = <1>;
3934 #size-cells = <0>; 2922 #size-cells = <0>;
3935 interrupts = <GIC_SPI 2923 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 2924 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 2925 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 2926 clock-names = "iface", "core";
3939 power-domains = <&rpm <<
3940 operating-points-v2 = <<
3941 status = "disabled"; 2927 status = "disabled";
3942 }; 2928 };
3943 2929
3944 slim: slim-ngd@171c0000 { !! 2930 slim: slim@171c0000 {
3945 compatible = "qcom,sl 2931 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 2932 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 2933 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 2934
3949 dmas = <&slimbam 3>, !! 2935 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 2936 qcom,ea-pc = <0x270>;
>> 2937 status = "okay";
>> 2938 dmas = <&slimbam 3>, <&slimbam 4>,
>> 2939 <&slimbam 5>, <&slimbam 6>;
>> 2940 dma-names = "rx", "tx", "tx2", "rx2";
3951 2941
3952 iommus = <&apps_smmu 2942 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 2943 #address-cells = <1>;
3954 #size-cells = <0>; 2944 #size-cells = <0>;
3955 status = "disabled"; <<
3956 }; <<
3957 2945
3958 lmh_cluster1: lmh@17d70800 { !! 2946 ngd@1 {
3959 compatible = "qcom,sd !! 2947 reg = <1>;
3960 reg = <0 0x17d70800 0 !! 2948 #address-cells = <2>;
3961 interrupts = <GIC_SPI !! 2949 #size-cells = <0>;
3962 cpus = <&CPU4>; !! 2950
3963 qcom,lmh-temp-arm-mil !! 2951 wcd9340_ifd: ifd@0{
3964 qcom,lmh-temp-low-mil !! 2952 compatible = "slim217,250";
3965 qcom,lmh-temp-high-mi !! 2953 reg = <0 0>;
3966 interrupt-controller; !! 2954 };
3967 #interrupt-cells = <1 !! 2955
>> 2956 wcd9340: codec@1{
>> 2957 compatible = "slim217,250";
>> 2958 reg = <1 0>;
>> 2959 slim-ifc-dev = <&wcd9340_ifd>;
>> 2960
>> 2961 #sound-dai-cells = <1>;
>> 2962
>> 2963 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 2964 interrupt-controller;
>> 2965 #interrupt-cells = <1>;
>> 2966
>> 2967 #clock-cells = <0>;
>> 2968 clock-frequency = <9600000>;
>> 2969 clock-output-names = "mclk";
>> 2970 qcom,micbias1-millivolt = <1800>;
>> 2971 qcom,micbias2-millivolt = <1800>;
>> 2972 qcom,micbias3-millivolt = <1800>;
>> 2973 qcom,micbias4-millivolt = <1800>;
>> 2974
>> 2975 #address-cells = <1>;
>> 2976 #size-cells = <1>;
>> 2977
>> 2978 wcdgpio: gpio-controller@42 {
>> 2979 compatible = "qcom,wcd9340-gpio";
>> 2980 gpio-controller;
>> 2981 #gpio-cells = <2>;
>> 2982 reg = <0x42 0x2>;
>> 2983 };
>> 2984
>> 2985 swm: swm@c85 {
>> 2986 compatible = "qcom,soundwire-v1.3.0";
>> 2987 reg = <0xc85 0x40>;
>> 2988 interrupts-extended = <&wcd9340 20>;
>> 2989
>> 2990 qcom,dout-ports = <6>;
>> 2991 qcom,din-ports = <2>;
>> 2992 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 2993 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 2994 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 2995
>> 2996 #sound-dai-cells = <1>;
>> 2997 clocks = <&wcd9340>;
>> 2998 clock-names = "iface";
>> 2999 #address-cells = <2>;
>> 3000 #size-cells = <0>;
>> 3001
>> 3002
>> 3003 };
>> 3004 };
>> 3005 };
3968 }; 3006 };
3969 3007
3970 lmh_cluster0: lmh@17d78800 { !! 3008 sound: sound {
3971 compatible = "qcom,sd <<
3972 reg = <0 0x17d78800 0 <<
3973 interrupts = <GIC_SPI <<
3974 cpus = <&CPU0>; <<
3975 qcom,lmh-temp-arm-mil <<
3976 qcom,lmh-temp-low-mil <<
3977 qcom,lmh-temp-high-mi <<
3978 interrupt-controller; <<
3979 #interrupt-cells = <1 <<
3980 }; 3009 };
3981 3010
3982 usb_1_hsphy: phy@88e2000 { 3011 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3012 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3013 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3014 status = "disabled";
3986 #phy-cells = <0>; 3015 #phy-cells = <0>;
3987 3016
3988 clocks = <&gcc GCC_US 3017 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3018 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3019 clock-names = "cfg_ahb", "ref";
3991 3020
3992 resets = <&gcc GCC_QU 3021 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3022
3994 nvmem-cells = <&qusb2 3023 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3024 };
3996 3025
3997 usb_2_hsphy: phy@88e3000 { 3026 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3027 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3028 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3029 status = "disabled";
4001 #phy-cells = <0>; 3030 #phy-cells = <0>;
4002 3031
4003 clocks = <&gcc GCC_US 3032 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3033 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3034 clock-names = "cfg_ahb", "ref";
4006 3035
4007 resets = <&gcc GCC_QU 3036 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3037
4009 nvmem-cells = <&qusb2 3038 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3039 };
4011 3040
4012 usb_1_qmpphy: phy@88e8000 { !! 3041 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3042 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3043 reg = <0 0x088e9000 0 0x18c>,
>> 3044 <0 0x088e8000 0 0x10>;
>> 3045 reg-names = "reg-base", "dp_com";
4015 status = "disabled"; 3046 status = "disabled";
>> 3047 #clock-cells = <1>;
>> 3048 #address-cells = <2>;
>> 3049 #size-cells = <2>;
>> 3050 ranges;
4016 3051
4017 clocks = <&gcc GCC_US 3052 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3053 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3054 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3055 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3056 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3057
4028 resets = <&gcc GCC_US !! 3058 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3059 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3060 reset-names = "phy", "common";
4031 3061
4032 #clock-cells = <1>; !! 3062 usb_1_ssphy: lanes@88e9200 {
4033 #phy-cells = <1>; !! 3063 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3064 <0 0x088e9400 0 0x200>,
4035 !! 3065 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3066 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3067 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3068 <0 0x088e9a00 0 0x100>;
4039 !! 3069 #phy-cells = <0>;
4040 port@0 { !! 3070 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4041 reg = !! 3071 clock-names = "pipe0";
4042 !! 3072 clock-output-names = "usb3_phy_pipe_clk_src";
4043 usb_1 <<
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3073 };
4063 }; 3074 };
4064 3075
4065 usb_2_qmpphy: phy@88eb000 { 3076 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3077 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 3078 reg = <0 0x088eb000 0 0x18c>;
>> 3079 status = "disabled";
>> 3080 #clock-cells = <1>;
>> 3081 #address-cells = <2>;
>> 3082 #size-cells = <2>;
>> 3083 ranges;
4068 3084
4069 clocks = <&gcc GCC_US 3085 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 3086 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 3087 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 3088 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 3089 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 3090
4083 resets = <&gcc GCC_US !! 3091 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 3092 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 3093 reset-names = "phy", "common";
4086 "phy_ph <<
4087 3094
4088 status = "disabled"; !! 3095 usb_2_ssphy: lane@88eb200 {
>> 3096 reg = <0 0x088eb200 0 0x128>,
>> 3097 <0 0x088eb400 0 0x1fc>,
>> 3098 <0 0x088eb800 0 0x218>,
>> 3099 <0 0x088eb600 0 0x70>;
>> 3100 #phy-cells = <0>;
>> 3101 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3102 clock-names = "pipe0";
>> 3103 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3104 };
4089 }; 3105 };
4090 3106
4091 usb_1: usb@a6f8800 { 3107 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 3108 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 3109 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 3110 status = "disabled";
4095 #address-cells = <2>; 3111 #address-cells = <2>;
4096 #size-cells = <2>; 3112 #size-cells = <2>;
4097 ranges; 3113 ranges;
4098 dma-ranges; 3114 dma-ranges;
4099 3115
4100 clocks = <&gcc GCC_CF 3116 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 3117 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 3118 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 3119 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 3120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 3121 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 3122 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 3123
4111 assigned-clocks = <&g 3124 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 3125 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 3126 assigned-clock-rates = <19200000>, <150000000>;
4114 3127
4115 interrupts-extended = !! 3128 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 3129 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 3130 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 3131 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 3132 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 3133 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 3134
4126 power-domains = <&gcc 3135 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 3136
4128 resets = <&gcc GCC_US 3137 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 3138
4130 interconnects = <&agg !! 3139 interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>,
4131 <&gla !! 3140 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
4132 interconnect-names = 3141 interconnect-names = "usb-ddr", "apps-usb";
4133 3142
4134 usb_1_dwc3: usb@a6000 !! 3143 usb_1_dwc3: dwc3@a600000 {
4135 compatible = 3144 compatible = "snps,dwc3";
4136 reg = <0 0x0a 3145 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 3146 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 3147 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 3148 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 3149 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 3150 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 3151 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 3152 };
4165 }; 3153 };
4166 3154
4167 usb_2: usb@a8f8800 { 3155 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 3156 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 3157 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 3158 status = "disabled";
4171 #address-cells = <2>; 3159 #address-cells = <2>;
4172 #size-cells = <2>; 3160 #size-cells = <2>;
4173 ranges; 3161 ranges;
4174 dma-ranges; 3162 dma-ranges;
4175 3163
4176 clocks = <&gcc GCC_CF 3164 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 3165 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 3166 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 3167 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 3168 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 3169 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 3170 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 3171
4187 assigned-clocks = <&g 3172 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 3173 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 3174 assigned-clock-rates = <19200000>, <150000000>;
4190 3175
4191 interrupts-extended = !! 3176 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 3177 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 3178 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 3179 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 3180 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 3181 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 3182
4202 power-domains = <&gcc 3183 power-domains = <&gcc USB30_SEC_GDSC>;
4203 3184
4204 resets = <&gcc GCC_US 3185 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 3186
4206 interconnects = <&agg !! 3187 interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>,
4207 <&gla !! 3188 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
4208 interconnect-names = 3189 interconnect-names = "usb-ddr", "apps-usb";
4209 3190
4210 usb_2_dwc3: usb@a8000 !! 3191 usb_2_dwc3: dwc3@a800000 {
4211 compatible = 3192 compatible = "snps,dwc3";
4212 reg = <0 0x0a 3193 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 3194 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 3195 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 3196 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 3197 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 3198 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 3199 phy-names = "usb2-phy", "usb3-phy";
4220 }; 3200 };
4221 }; 3201 };
4222 3202
4223 venus: video-codec@aa00000 { 3203 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 3204 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 3205 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 3206 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 3207 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 3208 <&videocc VCODEC0_GDSC>,
4229 <&vid !! 3209 <&videocc VCODEC1_GDSC>;
4230 <&rpm !! 3210 power-domain-names = "venus", "vcodec0", "vcodec1";
4231 power-domain-names = <<
4232 operating-points-v2 = <<
4233 clocks = <&videocc VI 3211 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 3212 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 3213 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 3214 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 3215 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 3216 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 3217 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 3218 clock-names = "core", "iface", "bus",
4241 "vcodec 3219 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 3220 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 3221 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 3222 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 3223 memory-region = <&venus_mem>;
4246 interconnects = <&mms <<
4247 <&gla <<
4248 interconnect-names = <<
4249 <<
4250 status = "disabled"; <<
4251 3224
4252 video-core0 { 3225 video-core0 {
4253 compatible = 3226 compatible = "venus-decoder";
4254 }; 3227 };
4255 3228
4256 video-core1 { 3229 video-core1 {
4257 compatible = 3230 compatible = "venus-encoder";
4258 }; 3231 };
4259 <<
4260 venus_opp_table: opp- <<
4261 compatible = <<
4262 <<
4263 opp-100000000 <<
4264 opp-h <<
4265 requi <<
4266 }; <<
4267 <<
4268 opp-200000000 <<
4269 opp-h <<
4270 requi <<
4271 }; <<
4272 <<
4273 opp-320000000 <<
4274 opp-h <<
4275 requi <<
4276 }; <<
4277 <<
4278 opp-380000000 <<
4279 opp-h <<
4280 requi <<
4281 }; <<
4282 <<
4283 opp-444000000 <<
4284 opp-h <<
4285 requi <<
4286 }; <<
4287 <<
4288 opp-533000097 <<
4289 opp-h <<
4290 requi <<
4291 }; <<
4292 }; <<
4293 }; 3232 };
4294 3233
4295 videocc: clock-controller@ab0 3234 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 3235 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 3236 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 3237 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 3238 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 3239 #clock-cells = <1>;
4301 #power-domain-cells = 3240 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 3241 #reset-cells = <1>;
4303 }; 3242 };
4304 3243
4305 camss: camss@acb3000 { <<
4306 compatible = "qcom,sd <<
4307 <<
4308 reg = <0 0x0acb3000 0 <<
4309 <0 0x0acba000 <<
4310 <0 0x0acc8000 <<
4311 <0 0x0ac65000 <<
4312 <0 0x0ac66000 <<
4313 <0 0x0ac67000 <<
4314 <0 0x0ac68000 <<
4315 <0 0x0acaf000 <<
4316 <0 0x0acb6000 <<
4317 <0 0x0acc4000 <<
4318 reg-names = "csid0", <<
4319 "csid1", <<
4320 "csid2", <<
4321 "csiphy0", <<
4322 "csiphy1", <<
4323 "csiphy2", <<
4324 "csiphy3", <<
4325 "vfe0", <<
4326 "vfe1", <<
4327 "vfe_lite"; <<
4328 <<
4329 interrupts = <GIC_SPI <<
4330 <GIC_SPI 466 <<
4331 <GIC_SPI 468 <<
4332 <GIC_SPI 477 <<
4333 <GIC_SPI 478 <<
4334 <GIC_SPI 479 <<
4335 <GIC_SPI 448 <<
4336 <GIC_SPI 465 <<
4337 <GIC_SPI 467 <<
4338 <GIC_SPI 469 <<
4339 interrupt-names = "cs <<
4340 "csid1", <<
4341 "csid2", <<
4342 "csiphy0", <<
4343 "csiphy1", <<
4344 "csiphy2", <<
4345 "csiphy3", <<
4346 "vfe0", <<
4347 "vfe1", <<
4348 "vfe_lite"; <<
4349 <<
4350 power-domains = <&clo <<
4351 <&clock_camcc <<
4352 <&clock_camcc <<
4353 <<
4354 clocks = <&clock_camc <<
4355 <&clock_camcc <<
4356 <&clock_camcc <<
4357 <&clock_camcc <<
4358 <&clock_camcc <<
4359 <&clock_camcc <<
4360 <&clock_camcc <<
4361 <&clock_camcc <<
4362 <&clock_camcc <<
4363 <&clock_camcc <<
4364 <&clock_camcc <<
4365 <&clock_camcc <<
4366 <&clock_camcc <<
4367 <&clock_camcc <<
4368 <&clock_camcc <<
4369 <&clock_camcc <<
4370 <&clock_camcc <<
4371 <&clock_camcc <<
4372 <&clock_camcc <<
4373 <&clock_camcc <<
4374 <&clock_camcc <<
4375 <&gcc GCC_CAM <<
4376 <&gcc GCC_CAM <<
4377 <&clock_camcc <<
4378 <&clock_camcc <<
4379 <&clock_camcc <<
4380 <&clock_camcc <<
4381 <&clock_camcc <<
4382 <&clock_camcc <<
4383 <&clock_camcc <<
4384 <&clock_camcc <<
4385 <&clock_camcc <<
4386 <&clock_camcc <<
4387 <&clock_camcc <<
4388 <&clock_camcc <<
4389 <&clock_camcc <<
4390 clock-names = "camnoc <<
4391 "cpas_ahb", <<
4392 "cphy_rx_src" <<
4393 "csi0", <<
4394 "csi0_src", <<
4395 "csi1", <<
4396 "csi1_src", <<
4397 "csi2", <<
4398 "csi2_src", <<
4399 "csiphy0", <<
4400 "csiphy0_time <<
4401 "csiphy0_time <<
4402 "csiphy1", <<
4403 "csiphy1_time <<
4404 "csiphy1_time <<
4405 "csiphy2", <<
4406 "csiphy2_time <<
4407 "csiphy2_time <<
4408 "csiphy3", <<
4409 "csiphy3_time <<
4410 "csiphy3_time <<
4411 "gcc_camera_a <<
4412 "gcc_camera_a <<
4413 "slow_ahb_src <<
4414 "soc_ahb", <<
4415 "vfe0_axi", <<
4416 "vfe0", <<
4417 "vfe0_cphy_rx <<
4418 "vfe0_src", <<
4419 "vfe1_axi", <<
4420 "vfe1", <<
4421 "vfe1_cphy_rx <<
4422 "vfe1_src", <<
4423 "vfe_lite", <<
4424 "vfe_lite_cph <<
4425 "vfe_lite_src <<
4426 <<
4427 iommus = <&apps_smmu <<
4428 <&apps_smmu <<
4429 <&apps_smmu <<
4430 <&apps_smmu <<
4431 <<
4432 status = "disabled"; <<
4433 <<
4434 ports { <<
4435 #address-cell <<
4436 #size-cells = <<
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; <<
4454 }; <<
4455 <<
4456 cci: cci@ac4a000 { 3244 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 3245 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 3246 #address-cells = <1>;
4459 #size-cells = <0>; 3247 #size-cells = <0>;
4460 3248
4461 reg = <0 0x0ac4a000 0 3249 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 3250 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 3251 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 3252
4465 clocks = <&clock_camc 3253 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 3254 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 3255 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 3256 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 3257 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 3258 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 3259 clock-names = "camnoc_axi",
4472 "soc_ahb", 3260 "soc_ahb",
4473 "slow_ahb_src 3261 "slow_ahb_src",
4474 "cpas_ahb", 3262 "cpas_ahb",
4475 "cci", 3263 "cci",
4476 "cci_src"; 3264 "cci_src";
4477 3265
4478 assigned-clocks = <&c 3266 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 3267 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 3268 assigned-clock-rates = <80000000>, <37500000>;
4481 3269
4482 pinctrl-names = "defa 3270 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 3271 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 3272 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 3273
4486 status = "disabled"; 3274 status = "disabled";
4487 3275
4488 cci_i2c0: i2c-bus@0 { 3276 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 3277 reg = <0>;
4490 clock-frequen 3278 clock-frequency = <1000000>;
4491 #address-cell 3279 #address-cells = <1>;
4492 #size-cells = 3280 #size-cells = <0>;
4493 }; 3281 };
4494 3282
4495 cci_i2c1: i2c-bus@1 { 3283 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 3284 reg = <1>;
4497 clock-frequen 3285 clock-frequency = <1000000>;
4498 #address-cell 3286 #address-cells = <1>;
4499 #size-cells = 3287 #size-cells = <0>;
4500 }; 3288 };
4501 }; 3289 };
4502 3290
4503 clock_camcc: clock-controller 3291 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 3292 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 3293 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 3294 #clock-cells = <1>;
4507 #reset-cells = <1>; 3295 #reset-cells = <1>;
4508 #power-domain-cells = 3296 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; 3297 };
4512 3298
4513 mdss: display-subsystem@ae000 !! 3299 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 3300 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 3301 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 3302 reg-names = "mdss";
4517 3303
4518 power-domains = <&dis 3304 power-domains = <&dispcc MDSS_GDSC>;
4519 3305
4520 clocks = <&dispcc DIS !! 3306 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 3307 <&gcc GCC_DISP_AXI_CLK>,
4521 <&dispcc DIS 3308 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" !! 3309 clock-names = "iface", "bus", "core";
>> 3310
>> 3311 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 3312 assigned-clock-rates = <300000000>;
4523 3313
4524 interrupts = <GIC_SPI 3314 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 3315 interrupt-controller;
4526 #interrupt-cells = <1 3316 #interrupt-cells = <1>;
4527 3317
4528 interconnects = <&mms <<
4529 <&mms <<
4530 interconnect-names = <<
4531 <<
4532 iommus = <&apps_smmu 3318 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 3319 <&apps_smmu 0xc80 0x8>;
4534 3320
4535 status = "disabled"; 3321 status = "disabled";
4536 3322
4537 #address-cells = <2>; 3323 #address-cells = <2>;
4538 #size-cells = <2>; 3324 #size-cells = <2>;
4539 ranges; 3325 ranges;
4540 3326
4541 mdss_mdp: display-con !! 3327 mdss_mdp: mdp@ae01000 {
4542 compatible = 3328 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 3329 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 3330 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 3331 reg-names = "mdp", "vbif";
4546 3332
4547 clocks = <&gc !! 3333 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4548 <&di <<
4549 <&di 3334 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 3335 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 3336 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = !! 3337 clock-names = "iface", "bus", "core", "vsync";
4553 3338
4554 assigned-cloc !! 3339 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 3340 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4556 operating-poi !! 3341 assigned-clock-rates = <300000000>,
4557 power-domains !! 3342 <19200000>;
4558 3343
4559 interrupt-par 3344 interrupt-parent = <&mdss>;
4560 interrupts = !! 3345 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4561 <<
4562 ports { <<
4563 #addr <<
4564 #size <<
4565 <<
4566 port@ <<
4567 <<
4568 <<
4569 <<
4570 <<
4571 }; <<
4572 <<
4573 port@ <<
4574 <<
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 <<
4583 <<
4584 <<
4585 }; <<
4586 }; <<
4587 <<
4588 mdp_opp_table <<
4589 compa <<
4590 <<
4591 opp-1 <<
4592 <<
4593 <<
4594 }; <<
4595 3346
4596 opp-1 <<
4597 <<
4598 <<
4599 }; <<
4600 <<
4601 opp-3 <<
4602 <<
4603 <<
4604 }; <<
4605 <<
4606 opp-4 <<
4607 <<
4608 <<
4609 }; <<
4610 }; <<
4611 }; <<
4612 <<
4613 mdss_dp: displayport- <<
4614 status = "dis 3347 status = "disabled";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 3348
4643 ports { 3349 ports {
4644 #addr 3350 #address-cells = <1>;
4645 #size 3351 #size-cells = <0>;
>> 3352
4646 port@ 3353 port@0 {
4647 3354 reg = <0>;
4648 !! 3355 dpu_intf1_out: endpoint {
4649 !! 3356 remote-endpoint = <&dsi0_in>;
4650 3357 };
4651 }; 3358 };
4652 3359
4653 port@ 3360 port@1 {
4654 3361 reg = <1>;
4655 !! 3362 dpu_intf2_out: endpoint {
4656 !! 3363 remote-endpoint = <&dsi1_in>;
4657 3364 };
4658 }; 3365 };
4659 }; 3366 };
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; 3367 };
4685 3368
4686 mdss_dsi0: dsi@ae9400 !! 3369 dsi0: dsi@ae94000 {
4687 compatible = !! 3370 compatible = "qcom,mdss-dsi-ctrl";
4688 <<
4689 reg = <0 0x0a 3371 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 3372 reg-names = "dsi_ctrl";
4691 3373
4692 interrupt-par 3374 interrupt-parent = <&mdss>;
4693 interrupts = !! 3375 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 3376
4695 clocks = <&di 3377 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 3378 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 3379 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 3380 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 3381 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 3382 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 3383 clock-names = "byte",
4702 3384 "byte_intf",
4703 3385 "pixel",
4704 3386 "core",
4705 3387 "iface",
4706 3388 "bus";
4707 assigned-cloc <<
4708 assigned-cloc <<
4709 <<
4710 operating-poi <<
4711 power-domains <<
4712 3389
4713 phys = <&mdss !! 3390 phys = <&dsi0_phy>;
>> 3391 phy-names = "dsi";
4714 3392
4715 status = "dis 3393 status = "disabled";
4716 3394
4717 #address-cell <<
4718 #size-cells = <<
4719 <<
4720 ports { 3395 ports {
4721 #addr 3396 #address-cells = <1>;
4722 #size 3397 #size-cells = <0>;
4723 3398
4724 port@ 3399 port@0 {
4725 3400 reg = <0>;
4726 !! 3401 dsi0_in: endpoint {
4727 3402 remote-endpoint = <&dpu_intf1_out>;
4728 3403 };
4729 }; 3404 };
4730 3405
4731 port@ 3406 port@1 {
4732 3407 reg = <1>;
4733 !! 3408 dsi0_out: endpoint {
4734 3409 };
4735 }; 3410 };
4736 }; 3411 };
4737 }; 3412 };
4738 3413
4739 mdss_dsi0_phy: phy@ae !! 3414 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 3415 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 3416 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 3417 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 3418 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 3419 reg-names = "dsi_phy",
4745 " 3420 "dsi_phy_lane",
4746 " 3421 "dsi_pll";
4747 3422
4748 #clock-cells 3423 #clock-cells = <1>;
4749 #phy-cells = 3424 #phy-cells = <0>;
4750 3425
4751 clocks = <&di 3426 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 3427 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 3428 clock-names = "iface", "ref";
4754 3429
4755 status = "dis 3430 status = "disabled";
4756 }; 3431 };
4757 3432
4758 mdss_dsi1: dsi@ae9600 !! 3433 dsi1: dsi@ae96000 {
4759 compatible = !! 3434 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 3435 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 3436 reg-names = "dsi_ctrl";
4763 3437
4764 interrupt-par 3438 interrupt-parent = <&mdss>;
4765 interrupts = !! 3439 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 3440
4767 clocks = <&di 3441 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 3442 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 3443 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 3444 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 3445 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 3446 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 3447 clock-names = "byte",
4774 3448 "byte_intf",
4775 3449 "pixel",
4776 3450 "core",
4777 3451 "iface",
4778 3452 "bus";
4779 assigned-cloc <<
4780 assigned-cloc <<
4781 <<
4782 operating-poi <<
4783 power-domains <<
4784 3453
4785 phys = <&mdss !! 3454 phys = <&dsi1_phy>;
>> 3455 phy-names = "dsi";
4786 3456
4787 status = "dis 3457 status = "disabled";
4788 3458
4789 #address-cell <<
4790 #size-cells = <<
4791 <<
4792 ports { 3459 ports {
4793 #addr 3460 #address-cells = <1>;
4794 #size 3461 #size-cells = <0>;
4795 3462
4796 port@ 3463 port@0 {
4797 3464 reg = <0>;
4798 !! 3465 dsi1_in: endpoint {
4799 3466 remote-endpoint = <&dpu_intf2_out>;
4800 3467 };
4801 }; 3468 };
4802 3469
4803 port@ 3470 port@1 {
4804 3471 reg = <1>;
4805 !! 3472 dsi1_out: endpoint {
4806 3473 };
4807 }; 3474 };
4808 }; 3475 };
4809 }; 3476 };
4810 3477
4811 mdss_dsi1_phy: phy@ae !! 3478 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 3479 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 3480 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 3481 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 3482 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 3483 reg-names = "dsi_phy",
4817 " 3484 "dsi_phy_lane",
4818 " 3485 "dsi_pll";
4819 3486
4820 #clock-cells 3487 #clock-cells = <1>;
4821 #phy-cells = 3488 #phy-cells = <0>;
4822 3489
4823 clocks = <&di 3490 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 3491 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 3492 clock-names = "iface", "ref";
4826 3493
4827 status = "dis 3494 status = "disabled";
4828 }; 3495 };
4829 }; 3496 };
4830 3497
4831 gpu: gpu@5000000 { 3498 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 3499 compatible = "qcom,adreno-630.2", "qcom,adreno";
>> 3500 #stream-id-cells = <16>;
4833 3501
4834 reg = <0 0x05000000 0 !! 3502 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 3503 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 3504
4837 /* 3505 /*
4838 * Look ma, no clocks 3506 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 3507 * controlled entirely by the GMU
4840 */ 3508 */
4841 3509
4842 interrupts = <GIC_SPI 3510 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 3511
4844 iommus = <&adreno_smm 3512 iommus = <&adreno_smmu 0>;
4845 3513
4846 operating-points-v2 = 3514 operating-points-v2 = <&gpu_opp_table>;
4847 3515
4848 qcom,gmu = <&gmu>; 3516 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 <<
4851 interconnects = <&mem <<
4852 interconnect-names = <<
4853 <<
4854 status = "disabled"; <<
4855 3517
4856 gpu_opp_table: opp-ta 3518 gpu_opp_table: opp-table {
4857 compatible = 3519 compatible = "operating-points-v2";
4858 3520
4859 opp-710000000 3521 opp-710000000 {
4860 opp-h 3522 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 3523 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p <<
4863 }; 3524 };
4864 3525
4865 opp-675000000 3526 opp-675000000 {
4866 opp-h 3527 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 3528 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p <<
4869 }; 3529 };
4870 3530
4871 opp-596000000 3531 opp-596000000 {
4872 opp-h 3532 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 3533 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p <<
4875 }; 3534 };
4876 3535
4877 opp-520000000 3536 opp-520000000 {
4878 opp-h 3537 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 3538 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p <<
4881 }; 3539 };
4882 3540
4883 opp-414000000 3541 opp-414000000 {
4884 opp-h 3542 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 3543 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p <<
4887 }; 3544 };
4888 3545
4889 opp-342000000 3546 opp-342000000 {
4890 opp-h 3547 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 3548 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p <<
4893 }; 3549 };
4894 3550
4895 opp-257000000 3551 opp-257000000 {
4896 opp-h 3552 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 3553 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p <<
4899 }; 3554 };
4900 }; 3555 };
4901 }; 3556 };
4902 3557
4903 adreno_smmu: iommu@5040000 { 3558 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd !! 3559 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 3560 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 3561 #iommu-cells = <1>;
4907 #global-interrupts = 3562 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 3563 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 3564 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 3565 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 3566 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 3567 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 3568 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 3569 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 3570 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 3571 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 3572 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 3573 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 3574 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 3575 clock-names = "bus", "iface";
4921 3576
4922 power-domains = <&gpu 3577 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 3578 };
4924 3579
4925 gmu: gmu@506a000 { 3580 gmu: gmu@506a000 {
4926 compatible = "qcom,ad !! 3581 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 3582
4928 reg = <0 0x0506a000 0 !! 3583 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 3584 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 3585 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 3586 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 3587
4933 interrupts = <GIC_SPI 3588 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 3589 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 3590 interrupt-names = "hfi", "gmu";
4936 3591
4937 clocks = <&gpucc GPU_ 3592 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 3593 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 3594 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 3595 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 3596 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 3597
4943 power-domains = <&gpu 3598 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 3599 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 3600 power-domain-names = "cx", "gx";
4946 3601
4947 iommus = <&adreno_smm 3602 iommus = <&adreno_smmu 5>;
4948 3603
4949 operating-points-v2 = 3604 operating-points-v2 = <&gmu_opp_table>;
4950 3605
4951 status = "disabled"; <<
4952 <<
4953 gmu_opp_table: opp-ta 3606 gmu_opp_table: opp-table {
4954 compatible = 3607 compatible = "operating-points-v2";
4955 3608
4956 opp-400000000 3609 opp-400000000 {
4957 opp-h 3610 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 3611 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 3612 };
4960 3613
4961 opp-200000000 3614 opp-200000000 {
4962 opp-h 3615 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 3616 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 3617 };
4965 }; 3618 };
4966 }; 3619 };
4967 3620
4968 dispcc: clock-controller@af00 3621 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 3622 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 3623 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 3624 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 3625 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 3626 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 3627 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 3628 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 3629 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 3630 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 3631 <0>,
4979 <&usb_1_qmpp !! 3632 <0>;
4980 clock-names = "bi_tcx 3633 clock-names = "bi_tcxo",
4981 "gcc_di 3634 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 3635 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 3636 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 3637 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 3638 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 3639 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 3640 "dp_link_clk_divsel_ten",
4988 "dp_vco 3641 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 3642 #clock-cells = <1>;
4990 #reset-cells = <1>; 3643 #reset-cells = <1>;
4991 #power-domain-cells = 3644 #power-domain-cells = <1>;
4992 }; 3645 };
4993 3646
4994 pdc_intc: interrupt-controlle 3647 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 3648 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 3649 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 3650 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 3651 #interrupt-cells = <2>;
4999 interrupt-parent = <& 3652 interrupt-parent = <&intc>;
5000 interrupt-controller; 3653 interrupt-controller;
5001 }; 3654 };
5002 3655
5003 pdc_reset: reset-controller@b 3656 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 3657 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 3658 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 3659 #reset-cells = <1>;
5007 }; 3660 };
5008 3661
5009 tsens0: thermal-sensor@c26300 3662 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 3663 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 3664 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 3665 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 3666 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 3667 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 3668 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 3669 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 3670 #thermal-sensor-cells = <1>;
5018 }; 3671 };
5019 3672
5020 tsens1: thermal-sensor@c26500 3673 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 3674 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 3675 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 3676 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 3677 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 3678 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 3679 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 3680 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 3681 #thermal-sensor-cells = <1>;
5029 }; 3682 };
5030 3683
5031 aoss_reset: reset-controller@ 3684 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 3685 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 3686 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 3687 #reset-cells = <1>;
5035 }; 3688 };
5036 3689
5037 aoss_qmp: power-management@c3 !! 3690 aoss_qmp: qmp@c300000 {
5038 compatible = "qcom,sd !! 3691 compatible = "qcom,sdm845-aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 3692 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 3693 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 3694 mboxes = <&apss_shared 0>;
5042 3695
5043 #clock-cells = <0>; 3696 #clock-cells = <0>;
>> 3697 #power-domain-cells = <1>;
5044 3698
5045 cx_cdev: cx { 3699 cx_cdev: cx {
5046 #cooling-cell 3700 #cooling-cells = <2>;
5047 }; 3701 };
5048 3702
5049 ebi_cdev: ebi { 3703 ebi_cdev: ebi {
5050 #cooling-cell 3704 #cooling-cells = <2>;
5051 }; 3705 };
5052 }; 3706 };
5053 3707
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 3708 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 3709 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 3710 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 3711 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 3712 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 3713 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 3714 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 3715 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 3716 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 3717 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 3718 qcom,ee = <0>;
5070 qcom,channel = <0>; 3719 qcom,channel = <0>;
5071 #address-cells = <2>; 3720 #address-cells = <2>;
5072 #size-cells = <0>; 3721 #size-cells = <0>;
5073 interrupt-controller; 3722 interrupt-controller;
5074 #interrupt-cells = <4 3723 #interrupt-cells = <4>;
5075 }; !! 3724 cell-index = <0>;
5076 <<
5077 sram@146bf000 { <<
5078 compatible = "qcom,sd <<
5079 reg = <0 0x146bf000 0 <<
5080 <<
5081 #address-cells = <1>; <<
5082 #size-cells = <1>; <<
5083 <<
5084 ranges = <0 0 0x146bf <<
5085 <<
5086 pil-reloc@94c { <<
5087 compatible = <<
5088 reg = <0x94c <<
5089 }; <<
5090 }; 3725 };
5091 3726
5092 apps_smmu: iommu@15000000 { 3727 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 3728 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 3729 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 3730 #iommu-cells = <2>;
5096 #global-interrupts = 3731 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 3732 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 3733 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 3734 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 3735 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 3736 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 3737 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 3738 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 3739 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 3740 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 3741 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 3742 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 3743 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 3744 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 3745 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 3746 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 3747 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 3748 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 3749 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 3750 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 3751 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 3752 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 3753 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 3754 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 3755 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 3756 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 3757 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 3758 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 3759 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 3760 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 3761 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 3762 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 3763 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 3764 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 3765 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 3766 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 3767 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 3768 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 3769 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 3770 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 3771 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 3772 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 3773 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 3774 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 3775 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 3776 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 3777 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 3778 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 3779 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 3780 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 3781 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 3782 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 3783 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 3784 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 3785 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 3786 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 3787 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 3788 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 3789 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 3790 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 3791 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 3792 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 3793 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 3794 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 3795 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 3796 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 3797 };
5163 3798
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 3799 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 3800 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 3801 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 3802 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 3803 #clock-cells = <1>;
5241 status = "disabled"; 3804 status = "disabled";
5242 }; 3805 };
5243 3806
5244 gladiator_noc: interconnect@1 3807 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 3808 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 3809 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = !! 3810 #interconnect-cells = <1>;
5248 qcom,bcm-voters = <&a 3811 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 3812 };
5250 3813
5251 watchdog@17980000 { 3814 watchdog@17980000 {
5252 compatible = "qcom,ap 3815 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 3816 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 3817 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI <<
5256 }; 3818 };
5257 3819
5258 apss_shared: mailbox@17990000 3820 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 3821 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 3822 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 3823 #mbox-cells = <1>;
5262 }; 3824 };
5263 3825
5264 apps_rsc: rsc@179c0000 { 3826 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 3827 label = "apps_rsc";
5266 compatible = "qcom,rp 3828 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 3829 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 3830 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 3831 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 3832 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 3833 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 3834 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 3835 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 3836 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 3837 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 3838 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 3839 <SLEEP_TCS 3>,
5278 <WA 3840 <WAKE_TCS 3>,
5279 <CO 3841 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 3842
5282 apps_bcm_voter: bcm-v 3843 apps_bcm_voter: bcm-voter {
5283 compatible = 3844 compatible = "qcom,bcm-voter";
5284 }; 3845 };
5285 3846
5286 rpmhcc: clock-control 3847 rpmhcc: clock-controller {
5287 compatible = 3848 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 3849 #clock-cells = <1>;
5289 clock-names = 3850 clock-names = "xo";
5290 clocks = <&xo 3851 clocks = <&xo_board>;
5291 }; 3852 };
5292 3853
5293 rpmhpd: power-control 3854 rpmhpd: power-controller {
5294 compatible = 3855 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 3856 #power-domain-cells = <1>;
5296 operating-poi 3857 operating-points-v2 = <&rpmhpd_opp_table>;
5297 3858
5298 rpmhpd_opp_ta 3859 rpmhpd_opp_table: opp-table {
5299 compa 3860 compatible = "operating-points-v2";
5300 3861
5301 rpmhp 3862 rpmhpd_opp_ret: opp1 {
5302 3863 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 3864 };
5304 3865
5305 rpmhp 3866 rpmhpd_opp_min_svs: opp2 {
5306 3867 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 3868 };
5308 3869
5309 rpmhp 3870 rpmhpd_opp_low_svs: opp3 {
5310 3871 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 3872 };
5312 3873
5313 rpmhp 3874 rpmhpd_opp_svs: opp4 {
5314 3875 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 3876 };
5316 3877
5317 rpmhp 3878 rpmhpd_opp_svs_l1: opp5 {
5318 3879 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 3880 };
5320 3881
5321 rpmhp 3882 rpmhpd_opp_nom: opp6 {
5322 3883 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 3884 };
5324 3885
5325 rpmhp 3886 rpmhpd_opp_nom_l1: opp7 {
5326 3887 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 3888 };
5328 3889
5329 rpmhp 3890 rpmhpd_opp_nom_l2: opp8 {
5330 3891 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 3892 };
5332 3893
5333 rpmhp 3894 rpmhpd_opp_turbo: opp9 {
5334 3895 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 3896 };
5336 3897
5337 rpmhp 3898 rpmhpd_opp_turbo_l1: opp10 {
5338 3899 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 3900 };
5340 }; 3901 };
5341 }; 3902 };
5342 }; 3903 };
5343 3904
5344 intc: interrupt-controller@17 3905 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 3906 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 3907 #address-cells = <2>;
5347 #size-cells = <2>; 3908 #size-cells = <2>;
5348 ranges; 3909 ranges;
5349 #interrupt-cells = <3 3910 #interrupt-cells = <3>;
5350 interrupt-controller; 3911 interrupt-controller;
5351 reg = <0 0x17a00000 0 3912 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 3913 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 3914 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 3915
5355 msi-controller@17a400 3916 msi-controller@17a40000 {
5356 compatible = 3917 compatible = "arm,gic-v3-its";
5357 msi-controlle 3918 msi-controller;
5358 #msi-cells = 3919 #msi-cells = <1>;
5359 reg = <0 0x17 3920 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 3921 status = "disabled";
5361 }; 3922 };
5362 }; 3923 };
5363 3924
5364 slimbam: dma-controller@17184 !! 3925 slimbam: dma@17184000 {
5365 compatible = "qcom,ba !! 3926 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 3927 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 3928 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; !! 3929 num-channels = <31>;
5369 interrupts = <GIC_SPI 3930 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 3931 #dma-cells = <1>;
5371 qcom,ee = <1>; 3932 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 3933 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 3934 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 3935 };
5375 3936
5376 timer@17c90000 { 3937 timer@17c90000 {
5377 #address-cells = <1>; !! 3938 #address-cells = <2>;
5378 #size-cells = <1>; !! 3939 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 3940 ranges;
5380 compatible = "arm,arm 3941 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 3942 reg = <0 0x17c90000 0 0x1000>;
5382 3943
5383 frame@17ca0000 { 3944 frame@17ca0000 {
5384 frame-number 3945 frame-number = <0>;
5385 interrupts = 3946 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 3947 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 3948 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 3949 <0 0x17cb0000 0 0x1000>;
5389 }; 3950 };
5390 3951
5391 frame@17cc0000 { 3952 frame@17cc0000 {
5392 frame-number 3953 frame-number = <1>;
5393 interrupts = 3954 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 3955 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 3956 status = "disabled";
5396 }; 3957 };
5397 3958
5398 frame@17cd0000 { 3959 frame@17cd0000 {
5399 frame-number 3960 frame-number = <2>;
5400 interrupts = 3961 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 3962 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 3963 status = "disabled";
5403 }; 3964 };
5404 3965
5405 frame@17ce0000 { 3966 frame@17ce0000 {
5406 frame-number 3967 frame-number = <3>;
5407 interrupts = 3968 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 3969 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 3970 status = "disabled";
5410 }; 3971 };
5411 3972
5412 frame@17cf0000 { 3973 frame@17cf0000 {
5413 frame-number 3974 frame-number = <4>;
5414 interrupts = 3975 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 3976 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 3977 status = "disabled";
5417 }; 3978 };
5418 3979
5419 frame@17d00000 { 3980 frame@17d00000 {
5420 frame-number 3981 frame-number = <5>;
5421 interrupts = 3982 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 3983 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 3984 status = "disabled";
5424 }; 3985 };
5425 3986
5426 frame@17d10000 { 3987 frame@17d10000 {
5427 frame-number 3988 frame-number = <6>;
5428 interrupts = 3989 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 3990 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 3991 status = "disabled";
5431 }; 3992 };
5432 }; 3993 };
5433 3994
5434 osm_l3: interconnect@17d41000 3995 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 3996 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 3997 reg = <0 0x17d41000 0 0x1400>;
5437 3998
5438 clocks = <&rpmhcc RPM 3999 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 4000 clock-names = "xo", "alternate";
5440 4001
5441 #interconnect-cells = 4002 #interconnect-cells = <1>;
5442 }; 4003 };
5443 4004
5444 cpufreq_hw: cpufreq@17d43000 4005 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 4006 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 4007 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 4008 reg-names = "freq-domain0", "freq-domain1";
5448 4009
5449 interrupts-extended = <<
5450 <<
5451 clocks = <&rpmhcc RPM 4010 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 4011 clock-names = "xo", "alternate";
5453 4012
5454 #freq-domain-cells = 4013 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 4014 };
5457 4015
5458 wifi: wifi@18800000 { 4016 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 4017 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 4018 status = "disabled";
5461 reg = <0 0x18800000 0 4019 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 4020 reg-names = "membase";
5463 memory-region = <&wla 4021 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 4022 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 4023 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 4024 interrupts =
5467 <GIC_SPI 414 4025 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 4026 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 4027 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 4028 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 4029 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 4030 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 4031 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 4032 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 4033 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 4034 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 4035 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 4036 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 4037 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 4038 };
5481 }; 4039 };
5482 4040
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 4041 thermal-zones {
5487 cpu0-thermal { 4042 cpu0-thermal {
5488 polling-delay-passive 4043 polling-delay-passive = <250>;
>> 4044 polling-delay = <1000>;
5489 4045
5490 thermal-sensors = <&t 4046 thermal-sensors = <&tsens0 1>;
5491 4047
5492 trips { 4048 trips {
5493 cpu0_alert0: 4049 cpu0_alert0: trip-point0 {
5494 tempe 4050 temperature = <90000>;
5495 hyste 4051 hysteresis = <2000>;
5496 type 4052 type = "passive";
5497 }; 4053 };
5498 4054
5499 cpu0_alert1: 4055 cpu0_alert1: trip-point1 {
5500 tempe 4056 temperature = <95000>;
5501 hyste 4057 hysteresis = <2000>;
5502 type 4058 type = "passive";
5503 }; 4059 };
5504 4060
5505 cpu0_crit: cp !! 4061 cpu0_crit: cpu_crit {
5506 tempe 4062 temperature = <110000>;
5507 hyste 4063 hysteresis = <1000>;
5508 type 4064 type = "critical";
5509 }; 4065 };
5510 }; 4066 };
>> 4067
>> 4068 cooling-maps {
>> 4069 map0 {
>> 4070 trip = <&cpu0_alert0>;
>> 4071 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4072 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4073 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4074 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4075 };
>> 4076 map1 {
>> 4077 trip = <&cpu0_alert1>;
>> 4078 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4079 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4080 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4081 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4082 };
>> 4083 };
5511 }; 4084 };
5512 4085
5513 cpu1-thermal { 4086 cpu1-thermal {
5514 polling-delay-passive 4087 polling-delay-passive = <250>;
>> 4088 polling-delay = <1000>;
5515 4089
5516 thermal-sensors = <&t 4090 thermal-sensors = <&tsens0 2>;
5517 4091
5518 trips { 4092 trips {
5519 cpu1_alert0: 4093 cpu1_alert0: trip-point0 {
5520 tempe 4094 temperature = <90000>;
5521 hyste 4095 hysteresis = <2000>;
5522 type 4096 type = "passive";
5523 }; 4097 };
5524 4098
5525 cpu1_alert1: 4099 cpu1_alert1: trip-point1 {
5526 tempe 4100 temperature = <95000>;
5527 hyste 4101 hysteresis = <2000>;
5528 type 4102 type = "passive";
5529 }; 4103 };
5530 4104
5531 cpu1_crit: cp !! 4105 cpu1_crit: cpu_crit {
5532 tempe 4106 temperature = <110000>;
5533 hyste 4107 hysteresis = <1000>;
5534 type 4108 type = "critical";
5535 }; 4109 };
5536 }; 4110 };
>> 4111
>> 4112 cooling-maps {
>> 4113 map0 {
>> 4114 trip = <&cpu1_alert0>;
>> 4115 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4116 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4117 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4118 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4119 };
>> 4120 map1 {
>> 4121 trip = <&cpu1_alert1>;
>> 4122 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4123 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4124 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4125 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4126 };
>> 4127 };
5537 }; 4128 };
5538 4129
5539 cpu2-thermal { 4130 cpu2-thermal {
5540 polling-delay-passive 4131 polling-delay-passive = <250>;
>> 4132 polling-delay = <1000>;
5541 4133
5542 thermal-sensors = <&t 4134 thermal-sensors = <&tsens0 3>;
5543 4135
5544 trips { 4136 trips {
5545 cpu2_alert0: 4137 cpu2_alert0: trip-point0 {
5546 tempe 4138 temperature = <90000>;
5547 hyste 4139 hysteresis = <2000>;
5548 type 4140 type = "passive";
5549 }; 4141 };
5550 4142
5551 cpu2_alert1: 4143 cpu2_alert1: trip-point1 {
5552 tempe 4144 temperature = <95000>;
5553 hyste 4145 hysteresis = <2000>;
5554 type 4146 type = "passive";
5555 }; 4147 };
5556 4148
5557 cpu2_crit: cp !! 4149 cpu2_crit: cpu_crit {
5558 tempe 4150 temperature = <110000>;
5559 hyste 4151 hysteresis = <1000>;
5560 type 4152 type = "critical";
5561 }; 4153 };
5562 }; 4154 };
>> 4155
>> 4156 cooling-maps {
>> 4157 map0 {
>> 4158 trip = <&cpu2_alert0>;
>> 4159 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4160 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4161 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4162 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4163 };
>> 4164 map1 {
>> 4165 trip = <&cpu2_alert1>;
>> 4166 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4167 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4168 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4169 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4170 };
>> 4171 };
5563 }; 4172 };
5564 4173
5565 cpu3-thermal { 4174 cpu3-thermal {
5566 polling-delay-passive 4175 polling-delay-passive = <250>;
>> 4176 polling-delay = <1000>;
5567 4177
5568 thermal-sensors = <&t 4178 thermal-sensors = <&tsens0 4>;
5569 4179
5570 trips { 4180 trips {
5571 cpu3_alert0: 4181 cpu3_alert0: trip-point0 {
5572 tempe 4182 temperature = <90000>;
5573 hyste 4183 hysteresis = <2000>;
5574 type 4184 type = "passive";
5575 }; 4185 };
5576 4186
5577 cpu3_alert1: 4187 cpu3_alert1: trip-point1 {
5578 tempe 4188 temperature = <95000>;
5579 hyste 4189 hysteresis = <2000>;
5580 type 4190 type = "passive";
5581 }; 4191 };
5582 4192
5583 cpu3_crit: cp !! 4193 cpu3_crit: cpu_crit {
5584 tempe 4194 temperature = <110000>;
5585 hyste 4195 hysteresis = <1000>;
5586 type 4196 type = "critical";
5587 }; 4197 };
5588 }; 4198 };
>> 4199
>> 4200 cooling-maps {
>> 4201 map0 {
>> 4202 trip = <&cpu3_alert0>;
>> 4203 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4204 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4205 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4206 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4207 };
>> 4208 map1 {
>> 4209 trip = <&cpu3_alert1>;
>> 4210 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4211 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4212 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4213 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4214 };
>> 4215 };
5589 }; 4216 };
5590 4217
5591 cpu4-thermal { 4218 cpu4-thermal {
5592 polling-delay-passive 4219 polling-delay-passive = <250>;
>> 4220 polling-delay = <1000>;
5593 4221
5594 thermal-sensors = <&t 4222 thermal-sensors = <&tsens0 7>;
5595 4223
5596 trips { 4224 trips {
5597 cpu4_alert0: 4225 cpu4_alert0: trip-point0 {
5598 tempe 4226 temperature = <90000>;
5599 hyste 4227 hysteresis = <2000>;
5600 type 4228 type = "passive";
5601 }; 4229 };
5602 4230
5603 cpu4_alert1: 4231 cpu4_alert1: trip-point1 {
5604 tempe 4232 temperature = <95000>;
5605 hyste 4233 hysteresis = <2000>;
5606 type 4234 type = "passive";
5607 }; 4235 };
5608 4236
5609 cpu4_crit: cp !! 4237 cpu4_crit: cpu_crit {
5610 tempe 4238 temperature = <110000>;
5611 hyste 4239 hysteresis = <1000>;
5612 type 4240 type = "critical";
5613 }; 4241 };
5614 }; 4242 };
>> 4243
>> 4244 cooling-maps {
>> 4245 map0 {
>> 4246 trip = <&cpu4_alert0>;
>> 4247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4249 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4250 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4251 };
>> 4252 map1 {
>> 4253 trip = <&cpu4_alert1>;
>> 4254 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4255 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4256 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4257 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4258 };
>> 4259 };
5615 }; 4260 };
5616 4261
5617 cpu5-thermal { 4262 cpu5-thermal {
5618 polling-delay-passive 4263 polling-delay-passive = <250>;
>> 4264 polling-delay = <1000>;
5619 4265
5620 thermal-sensors = <&t 4266 thermal-sensors = <&tsens0 8>;
5621 4267
5622 trips { 4268 trips {
5623 cpu5_alert0: 4269 cpu5_alert0: trip-point0 {
5624 tempe 4270 temperature = <90000>;
5625 hyste 4271 hysteresis = <2000>;
5626 type 4272 type = "passive";
5627 }; 4273 };
5628 4274
5629 cpu5_alert1: 4275 cpu5_alert1: trip-point1 {
5630 tempe 4276 temperature = <95000>;
5631 hyste 4277 hysteresis = <2000>;
5632 type 4278 type = "passive";
5633 }; 4279 };
5634 4280
5635 cpu5_crit: cp !! 4281 cpu5_crit: cpu_crit {
5636 tempe 4282 temperature = <110000>;
5637 hyste 4283 hysteresis = <1000>;
5638 type 4284 type = "critical";
5639 }; 4285 };
5640 }; 4286 };
>> 4287
>> 4288 cooling-maps {
>> 4289 map0 {
>> 4290 trip = <&cpu5_alert0>;
>> 4291 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4292 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4293 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4294 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4295 };
>> 4296 map1 {
>> 4297 trip = <&cpu5_alert1>;
>> 4298 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4299 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4300 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4301 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4302 };
>> 4303 };
5641 }; 4304 };
5642 4305
5643 cpu6-thermal { 4306 cpu6-thermal {
5644 polling-delay-passive 4307 polling-delay-passive = <250>;
>> 4308 polling-delay = <1000>;
5645 4309
5646 thermal-sensors = <&t 4310 thermal-sensors = <&tsens0 9>;
5647 4311
5648 trips { 4312 trips {
5649 cpu6_alert0: 4313 cpu6_alert0: trip-point0 {
5650 tempe 4314 temperature = <90000>;
5651 hyste 4315 hysteresis = <2000>;
5652 type 4316 type = "passive";
5653 }; 4317 };
5654 4318
5655 cpu6_alert1: 4319 cpu6_alert1: trip-point1 {
5656 tempe 4320 temperature = <95000>;
5657 hyste 4321 hysteresis = <2000>;
5658 type 4322 type = "passive";
5659 }; 4323 };
5660 4324
5661 cpu6_crit: cp !! 4325 cpu6_crit: cpu_crit {
5662 tempe 4326 temperature = <110000>;
5663 hyste 4327 hysteresis = <1000>;
5664 type 4328 type = "critical";
5665 }; 4329 };
5666 }; 4330 };
>> 4331
>> 4332 cooling-maps {
>> 4333 map0 {
>> 4334 trip = <&cpu6_alert0>;
>> 4335 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4336 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4337 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4338 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4339 };
>> 4340 map1 {
>> 4341 trip = <&cpu6_alert1>;
>> 4342 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4343 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4344 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4345 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4346 };
>> 4347 };
5667 }; 4348 };
5668 4349
5669 cpu7-thermal { 4350 cpu7-thermal {
5670 polling-delay-passive 4351 polling-delay-passive = <250>;
>> 4352 polling-delay = <1000>;
5671 4353
5672 thermal-sensors = <&t 4354 thermal-sensors = <&tsens0 10>;
5673 4355
5674 trips { 4356 trips {
5675 cpu7_alert0: 4357 cpu7_alert0: trip-point0 {
5676 tempe 4358 temperature = <90000>;
5677 hyste 4359 hysteresis = <2000>;
5678 type 4360 type = "passive";
5679 }; 4361 };
5680 4362
5681 cpu7_alert1: 4363 cpu7_alert1: trip-point1 {
5682 tempe 4364 temperature = <95000>;
5683 hyste 4365 hysteresis = <2000>;
5684 type 4366 type = "passive";
5685 }; 4367 };
5686 4368
5687 cpu7_crit: cp !! 4369 cpu7_crit: cpu_crit {
5688 tempe 4370 temperature = <110000>;
5689 hyste 4371 hysteresis = <1000>;
5690 type 4372 type = "critical";
5691 }; 4373 };
5692 }; 4374 };
>> 4375
>> 4376 cooling-maps {
>> 4377 map0 {
>> 4378 trip = <&cpu7_alert0>;
>> 4379 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4380 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4381 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4382 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4383 };
>> 4384 map1 {
>> 4385 trip = <&cpu7_alert1>;
>> 4386 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4387 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4388 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4389 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4390 };
>> 4391 };
5693 }; 4392 };
5694 4393
5695 aoss0-thermal { 4394 aoss0-thermal {
5696 polling-delay-passive 4395 polling-delay-passive = <250>;
>> 4396 polling-delay = <1000>;
5697 4397
5698 thermal-sensors = <&t 4398 thermal-sensors = <&tsens0 0>;
5699 4399
5700 trips { 4400 trips {
5701 aoss0_alert0: 4401 aoss0_alert0: trip-point0 {
5702 tempe 4402 temperature = <90000>;
5703 hyste 4403 hysteresis = <2000>;
5704 type 4404 type = "hot";
5705 }; 4405 };
5706 }; 4406 };
5707 }; 4407 };
5708 4408
5709 cluster0-thermal { 4409 cluster0-thermal {
5710 polling-delay-passive 4410 polling-delay-passive = <250>;
>> 4411 polling-delay = <1000>;
5711 4412
5712 thermal-sensors = <&t 4413 thermal-sensors = <&tsens0 5>;
5713 4414
5714 trips { 4415 trips {
5715 cluster0_aler 4416 cluster0_alert0: trip-point0 {
5716 tempe 4417 temperature = <90000>;
5717 hyste 4418 hysteresis = <2000>;
5718 type 4419 type = "hot";
5719 }; 4420 };
5720 cluster0_crit !! 4421 cluster0_crit: cluster0_crit {
5721 tempe 4422 temperature = <110000>;
5722 hyste 4423 hysteresis = <2000>;
5723 type 4424 type = "critical";
5724 }; 4425 };
5725 }; 4426 };
5726 }; 4427 };
5727 4428
5728 cluster1-thermal { 4429 cluster1-thermal {
5729 polling-delay-passive 4430 polling-delay-passive = <250>;
>> 4431 polling-delay = <1000>;
5730 4432
5731 thermal-sensors = <&t 4433 thermal-sensors = <&tsens0 6>;
5732 4434
5733 trips { 4435 trips {
5734 cluster1_aler 4436 cluster1_alert0: trip-point0 {
5735 tempe 4437 temperature = <90000>;
5736 hyste 4438 hysteresis = <2000>;
5737 type 4439 type = "hot";
5738 }; 4440 };
5739 cluster1_crit !! 4441 cluster1_crit: cluster1_crit {
5740 tempe 4442 temperature = <110000>;
5741 hyste 4443 hysteresis = <2000>;
5742 type 4444 type = "critical";
5743 }; 4445 };
5744 }; 4446 };
5745 }; 4447 };
5746 4448
5747 gpu-top-thermal { !! 4449 gpu-thermal-top {
5748 polling-delay-passive 4450 polling-delay-passive = <250>;
>> 4451 polling-delay = <1000>;
5749 4452
5750 thermal-sensors = <&t 4453 thermal-sensors = <&tsens0 11>;
5751 4454
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 4455 trips {
5760 gpu_top_alert !! 4456 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 4457 temperature = <90000>;
5768 hyste !! 4458 hysteresis = <2000>;
5769 type 4459 type = "hot";
5770 }; 4460 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 4461 };
5778 }; 4462 };
5779 4463
5780 gpu-bottom-thermal { !! 4464 gpu-thermal-bottom {
5781 polling-delay-passive 4465 polling-delay-passive = <250>;
>> 4466 polling-delay = <1000>;
5782 4467
5783 thermal-sensors = <&t 4468 thermal-sensors = <&tsens0 12>;
5784 4469
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 4470 trips {
5793 gpu_bottom_al !! 4471 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 4472 temperature = <90000>;
5801 hyste !! 4473 hysteresis = <2000>;
5802 type 4474 type = "hot";
5803 }; 4475 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 4476 };
5811 }; 4477 };
5812 4478
5813 aoss1-thermal { 4479 aoss1-thermal {
5814 polling-delay-passive 4480 polling-delay-passive = <250>;
>> 4481 polling-delay = <1000>;
5815 4482
5816 thermal-sensors = <&t 4483 thermal-sensors = <&tsens1 0>;
5817 4484
5818 trips { 4485 trips {
5819 aoss1_alert0: 4486 aoss1_alert0: trip-point0 {
5820 tempe 4487 temperature = <90000>;
5821 hyste 4488 hysteresis = <2000>;
5822 type 4489 type = "hot";
5823 }; 4490 };
5824 }; 4491 };
5825 }; 4492 };
5826 4493
5827 q6-modem-thermal { 4494 q6-modem-thermal {
5828 polling-delay-passive 4495 polling-delay-passive = <250>;
>> 4496 polling-delay = <1000>;
5829 4497
5830 thermal-sensors = <&t 4498 thermal-sensors = <&tsens1 1>;
5831 4499
5832 trips { 4500 trips {
5833 q6_modem_aler 4501 q6_modem_alert0: trip-point0 {
5834 tempe 4502 temperature = <90000>;
5835 hyste 4503 hysteresis = <2000>;
5836 type 4504 type = "hot";
5837 }; 4505 };
5838 }; 4506 };
5839 }; 4507 };
5840 4508
5841 mem-thermal { 4509 mem-thermal {
5842 polling-delay-passive 4510 polling-delay-passive = <250>;
>> 4511 polling-delay = <1000>;
5843 4512
5844 thermal-sensors = <&t 4513 thermal-sensors = <&tsens1 2>;
5845 4514
5846 trips { 4515 trips {
5847 mem_alert0: t 4516 mem_alert0: trip-point0 {
5848 tempe 4517 temperature = <90000>;
5849 hyste 4518 hysteresis = <2000>;
5850 type 4519 type = "hot";
5851 }; 4520 };
5852 }; 4521 };
5853 }; 4522 };
5854 4523
5855 wlan-thermal { 4524 wlan-thermal {
5856 polling-delay-passive 4525 polling-delay-passive = <250>;
>> 4526 polling-delay = <1000>;
5857 4527
5858 thermal-sensors = <&t 4528 thermal-sensors = <&tsens1 3>;
5859 4529
5860 trips { 4530 trips {
5861 wlan_alert0: 4531 wlan_alert0: trip-point0 {
5862 tempe 4532 temperature = <90000>;
5863 hyste 4533 hysteresis = <2000>;
5864 type 4534 type = "hot";
5865 }; 4535 };
5866 }; 4536 };
5867 }; 4537 };
5868 4538
5869 q6-hvx-thermal { 4539 q6-hvx-thermal {
5870 polling-delay-passive 4540 polling-delay-passive = <250>;
>> 4541 polling-delay = <1000>;
5871 4542
5872 thermal-sensors = <&t 4543 thermal-sensors = <&tsens1 4>;
5873 4544
5874 trips { 4545 trips {
5875 q6_hvx_alert0 4546 q6_hvx_alert0: trip-point0 {
5876 tempe 4547 temperature = <90000>;
5877 hyste 4548 hysteresis = <2000>;
5878 type 4549 type = "hot";
5879 }; 4550 };
5880 }; 4551 };
5881 }; 4552 };
5882 4553
5883 camera-thermal { 4554 camera-thermal {
5884 polling-delay-passive 4555 polling-delay-passive = <250>;
>> 4556 polling-delay = <1000>;
5885 4557
5886 thermal-sensors = <&t 4558 thermal-sensors = <&tsens1 5>;
5887 4559
5888 trips { 4560 trips {
5889 camera_alert0 4561 camera_alert0: trip-point0 {
5890 tempe 4562 temperature = <90000>;
5891 hyste 4563 hysteresis = <2000>;
5892 type 4564 type = "hot";
5893 }; 4565 };
5894 }; 4566 };
5895 }; 4567 };
5896 4568
5897 video-thermal { 4569 video-thermal {
5898 polling-delay-passive 4570 polling-delay-passive = <250>;
>> 4571 polling-delay = <1000>;
5899 4572
5900 thermal-sensors = <&t 4573 thermal-sensors = <&tsens1 6>;
5901 4574
5902 trips { 4575 trips {
5903 video_alert0: 4576 video_alert0: trip-point0 {
5904 tempe 4577 temperature = <90000>;
5905 hyste 4578 hysteresis = <2000>;
5906 type 4579 type = "hot";
5907 }; 4580 };
5908 }; 4581 };
5909 }; 4582 };
5910 4583
5911 modem-thermal { 4584 modem-thermal {
5912 polling-delay-passive 4585 polling-delay-passive = <250>;
>> 4586 polling-delay = <1000>;
5913 4587
5914 thermal-sensors = <&t 4588 thermal-sensors = <&tsens1 7>;
5915 4589
5916 trips { 4590 trips {
5917 modem_alert0: 4591 modem_alert0: trip-point0 {
5918 tempe 4592 temperature = <90000>;
5919 hyste 4593 hysteresis = <2000>;
5920 type 4594 type = "hot";
5921 }; 4595 };
5922 }; 4596 };
5923 }; 4597 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 4598 };
5933 }; 4599 };
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