1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> <<
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> <<
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 16 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 17 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 19 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 22 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 24 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 25 #include <dt-bindings/thermal/thermal.h>
31 26
32 / { 27 / {
33 interrupt-parent = <&intc>; 28 interrupt-parent = <&intc>;
34 29
35 #address-cells = <2>; 30 #address-cells = <2>;
36 #size-cells = <2>; 31 #size-cells = <2>;
37 32
38 aliases { 33 aliases {
39 i2c0 = &i2c0; 34 i2c0 = &i2c0;
40 i2c1 = &i2c1; 35 i2c1 = &i2c1;
41 i2c2 = &i2c2; 36 i2c2 = &i2c2;
42 i2c3 = &i2c3; 37 i2c3 = &i2c3;
43 i2c4 = &i2c4; 38 i2c4 = &i2c4;
44 i2c5 = &i2c5; 39 i2c5 = &i2c5;
45 i2c6 = &i2c6; 40 i2c6 = &i2c6;
46 i2c7 = &i2c7; 41 i2c7 = &i2c7;
47 i2c8 = &i2c8; 42 i2c8 = &i2c8;
48 i2c9 = &i2c9; 43 i2c9 = &i2c9;
49 i2c10 = &i2c10; 44 i2c10 = &i2c10;
50 i2c11 = &i2c11; 45 i2c11 = &i2c11;
51 i2c12 = &i2c12; 46 i2c12 = &i2c12;
52 i2c13 = &i2c13; 47 i2c13 = &i2c13;
53 i2c14 = &i2c14; 48 i2c14 = &i2c14;
54 i2c15 = &i2c15; 49 i2c15 = &i2c15;
55 spi0 = &spi0; 50 spi0 = &spi0;
56 spi1 = &spi1; 51 spi1 = &spi1;
57 spi2 = &spi2; 52 spi2 = &spi2;
58 spi3 = &spi3; 53 spi3 = &spi3;
59 spi4 = &spi4; 54 spi4 = &spi4;
60 spi5 = &spi5; 55 spi5 = &spi5;
61 spi6 = &spi6; 56 spi6 = &spi6;
62 spi7 = &spi7; 57 spi7 = &spi7;
63 spi8 = &spi8; 58 spi8 = &spi8;
64 spi9 = &spi9; 59 spi9 = &spi9;
65 spi10 = &spi10; 60 spi10 = &spi10;
66 spi11 = &spi11; 61 spi11 = &spi11;
67 spi12 = &spi12; 62 spi12 = &spi12;
68 spi13 = &spi13; 63 spi13 = &spi13;
69 spi14 = &spi14; 64 spi14 = &spi14;
70 spi15 = &spi15; 65 spi15 = &spi15;
71 }; 66 };
72 67
73 chosen { }; 68 chosen { };
74 69
75 clocks { !! 70 memory@80000000 {
76 xo_board: xo-board { !! 71 device_type = "memory";
77 compatible = "fixed-cl !! 72 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 73 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 74 };
80 clock-output-names = " !! 75
>> 76 reserved-memory {
>> 77 #address-cells = <2>;
>> 78 #size-cells = <2>;
>> 79 ranges;
>> 80
>> 81 hyp_mem: memory@85700000 {
>> 82 reg = <0 0x85700000 0 0x600000>;
>> 83 no-map;
81 }; 84 };
82 85
83 sleep_clk: sleep-clk { !! 86 xbl_mem: memory@85e00000 {
84 compatible = "fixed-cl !! 87 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 88 no-map;
86 clock-frequency = <327 !! 89 };
>> 90
>> 91 aop_mem: memory@85fc0000 {
>> 92 reg = <0 0x85fc0000 0 0x20000>;
>> 93 no-map;
>> 94 };
>> 95
>> 96 aop_cmd_db_mem: memory@85fe0000 {
>> 97 compatible = "qcom,cmd-db";
>> 98 reg = <0x0 0x85fe0000 0 0x20000>;
>> 99 no-map;
>> 100 };
>> 101
>> 102 smem_mem: memory@86000000 {
>> 103 reg = <0x0 0x86000000 0 0x200000>;
>> 104 no-map;
>> 105 };
>> 106
>> 107 tz_mem: memory@86200000 {
>> 108 reg = <0 0x86200000 0 0x2d00000>;
>> 109 no-map;
>> 110 };
>> 111
>> 112 rmtfs_mem: memory@88f00000 {
>> 113 compatible = "qcom,rmtfs-mem";
>> 114 reg = <0 0x88f00000 0 0x200000>;
>> 115 no-map;
>> 116
>> 117 qcom,client-id = <1>;
>> 118 qcom,vmid = <15>;
>> 119 };
>> 120
>> 121 qseecom_mem: memory@8ab00000 {
>> 122 reg = <0 0x8ab00000 0 0x1400000>;
>> 123 no-map;
>> 124 };
>> 125
>> 126 camera_mem: memory@8bf00000 {
>> 127 reg = <0 0x8bf00000 0 0x500000>;
>> 128 no-map;
>> 129 };
>> 130
>> 131 ipa_fw_mem: memory@8c400000 {
>> 132 reg = <0 0x8c400000 0 0x10000>;
>> 133 no-map;
>> 134 };
>> 135
>> 136 ipa_gsi_mem: memory@8c410000 {
>> 137 reg = <0 0x8c410000 0 0x5000>;
>> 138 no-map;
>> 139 };
>> 140
>> 141 gpu_mem: memory@8c415000 {
>> 142 reg = <0 0x8c415000 0 0x2000>;
>> 143 no-map;
>> 144 };
>> 145
>> 146 adsp_mem: memory@8c500000 {
>> 147 reg = <0 0x8c500000 0 0x1a00000>;
>> 148 no-map;
>> 149 };
>> 150
>> 151 wlan_msa_mem: memory@8df00000 {
>> 152 reg = <0 0x8df00000 0 0x100000>;
>> 153 no-map;
>> 154 };
>> 155
>> 156 mpss_region: memory@8e000000 {
>> 157 reg = <0 0x8e000000 0 0x7800000>;
>> 158 no-map;
>> 159 };
>> 160
>> 161 venus_mem: memory@95800000 {
>> 162 reg = <0 0x95800000 0 0x500000>;
>> 163 no-map;
>> 164 };
>> 165
>> 166 cdsp_mem: memory@95d00000 {
>> 167 reg = <0 0x95d00000 0 0x800000>;
>> 168 no-map;
>> 169 };
>> 170
>> 171 mba_region: memory@96500000 {
>> 172 reg = <0 0x96500000 0 0x200000>;
>> 173 no-map;
>> 174 };
>> 175
>> 176 slpi_mem: memory@96700000 {
>> 177 reg = <0 0x96700000 0 0x1400000>;
>> 178 no-map;
>> 179 };
>> 180
>> 181 spss_mem: memory@97b00000 {
>> 182 reg = <0 0x97b00000 0 0x100000>;
>> 183 no-map;
87 }; 184 };
88 }; 185 };
89 186
90 cpus: cpus { !! 187 cpus {
91 #address-cells = <2>; 188 #address-cells = <2>;
92 #size-cells = <0>; 189 #size-cells = <0>;
93 190
94 CPU0: cpu@0 { 191 CPU0: cpu@0 {
95 device_type = "cpu"; 192 device_type = "cpu";
96 compatible = "qcom,kry 193 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 194 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 195 enable-method = "psci";
100 capacity-dmips-mhz = < !! 196 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
101 dynamic-power-coeffici !! 197 &LITTLE_CPU_SLEEP_1
>> 198 &CLUSTER_SLEEP_0>;
>> 199 capacity-dmips-mhz = <607>;
>> 200 dynamic-power-coefficient = <100>;
102 qcom,freq-domain = <&c 201 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 202 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad !! 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
105 <&osm_ 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ <<
107 power-domain-names = " <<
108 #cooling-cells = <2>; 205 #cooling-cells = <2>;
109 next-level-cache = <&L 206 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 207 L2_0: l2-cache {
111 compatible = " 208 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 209 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 210 L3_0: l3-cache {
116 compat !! 211 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 212 };
120 }; 213 };
121 }; 214 };
122 215
123 CPU1: cpu@100 { 216 CPU1: cpu@100 {
124 device_type = "cpu"; 217 device_type = "cpu";
125 compatible = "qcom,kry 218 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 219 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 220 enable-method = "psci";
129 capacity-dmips-mhz = < !! 221 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
130 dynamic-power-coeffici !! 222 &LITTLE_CPU_SLEEP_1
>> 223 &CLUSTER_SLEEP_0>;
>> 224 capacity-dmips-mhz = <607>;
>> 225 dynamic-power-coefficient = <100>;
131 qcom,freq-domain = <&c 226 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 227 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad !! 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
134 <&osm_ 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ <<
136 power-domain-names = " <<
137 #cooling-cells = <2>; 230 #cooling-cells = <2>;
138 next-level-cache = <&L 231 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 232 L2_100: l2-cache {
140 compatible = " 233 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 234 next-level-cache = <&L3_0>;
144 }; 235 };
145 }; 236 };
146 237
147 CPU2: cpu@200 { 238 CPU2: cpu@200 {
148 device_type = "cpu"; 239 device_type = "cpu";
149 compatible = "qcom,kry 240 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 241 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 242 enable-method = "psci";
153 capacity-dmips-mhz = < !! 243 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
154 dynamic-power-coeffici !! 244 &LITTLE_CPU_SLEEP_1
>> 245 &CLUSTER_SLEEP_0>;
>> 246 capacity-dmips-mhz = <607>;
>> 247 dynamic-power-coefficient = <100>;
155 qcom,freq-domain = <&c 248 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 249 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad !! 250 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
158 <&osm_ 251 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ <<
160 power-domain-names = " <<
161 #cooling-cells = <2>; 252 #cooling-cells = <2>;
162 next-level-cache = <&L 253 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 254 L2_200: l2-cache {
164 compatible = " 255 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 256 next-level-cache = <&L3_0>;
168 }; 257 };
169 }; 258 };
170 259
171 CPU3: cpu@300 { 260 CPU3: cpu@300 {
172 device_type = "cpu"; 261 device_type = "cpu";
173 compatible = "qcom,kry 262 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 263 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 264 enable-method = "psci";
177 capacity-dmips-mhz = < !! 265 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
178 dynamic-power-coeffici !! 266 &LITTLE_CPU_SLEEP_1
>> 267 &CLUSTER_SLEEP_0>;
>> 268 capacity-dmips-mhz = <607>;
>> 269 dynamic-power-coefficient = <100>;
179 qcom,freq-domain = <&c 270 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 271 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad !! 272 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
182 <&osm_ 273 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 274 #cooling-cells = <2>;
184 power-domains = <&CPU_ <<
185 power-domain-names = " <<
186 next-level-cache = <&L 275 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 276 L2_300: l2-cache {
188 compatible = " 277 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 278 next-level-cache = <&L3_0>;
192 }; 279 };
193 }; 280 };
194 281
195 CPU4: cpu@400 { 282 CPU4: cpu@400 {
196 device_type = "cpu"; 283 device_type = "cpu";
197 compatible = "qcom,kry 284 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 285 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 286 enable-method = "psci";
201 capacity-dmips-mhz = < 287 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici !! 288 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 289 &BIG_CPU_SLEEP_1
>> 290 &CLUSTER_SLEEP_0>;
>> 291 dynamic-power-coefficient = <396>;
203 qcom,freq-domain = <&c 292 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 293 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad !! 294 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
206 <&osm_ 295 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ <<
208 power-domain-names = " <<
209 #cooling-cells = <2>; 296 #cooling-cells = <2>;
210 next-level-cache = <&L 297 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 298 L2_400: l2-cache {
212 compatible = " 299 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 300 next-level-cache = <&L3_0>;
216 }; 301 };
217 }; 302 };
218 303
219 CPU5: cpu@500 { 304 CPU5: cpu@500 {
220 device_type = "cpu"; 305 device_type = "cpu";
221 compatible = "qcom,kry 306 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 307 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 308 enable-method = "psci";
225 capacity-dmips-mhz = < 309 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici !! 310 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 311 &BIG_CPU_SLEEP_1
>> 312 &CLUSTER_SLEEP_0>;
>> 313 dynamic-power-coefficient = <396>;
227 qcom,freq-domain = <&c 314 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 315 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad !! 316 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
230 <&osm_ 317 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ <<
232 power-domain-names = " <<
233 #cooling-cells = <2>; 318 #cooling-cells = <2>;
234 next-level-cache = <&L 319 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 320 L2_500: l2-cache {
236 compatible = " 321 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 322 next-level-cache = <&L3_0>;
240 }; 323 };
241 }; 324 };
242 325
243 CPU6: cpu@600 { 326 CPU6: cpu@600 {
244 device_type = "cpu"; 327 device_type = "cpu";
245 compatible = "qcom,kry 328 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 329 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 330 enable-method = "psci";
249 capacity-dmips-mhz = < 331 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici !! 332 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 333 &BIG_CPU_SLEEP_1
>> 334 &CLUSTER_SLEEP_0>;
>> 335 dynamic-power-coefficient = <396>;
251 qcom,freq-domain = <&c 336 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 337 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad !! 338 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
254 <&osm_ 339 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ <<
256 power-domain-names = " <<
257 #cooling-cells = <2>; 340 #cooling-cells = <2>;
258 next-level-cache = <&L 341 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 342 L2_600: l2-cache {
260 compatible = " 343 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 344 next-level-cache = <&L3_0>;
264 }; 345 };
265 }; 346 };
266 347
267 CPU7: cpu@700 { 348 CPU7: cpu@700 {
268 device_type = "cpu"; 349 device_type = "cpu";
269 compatible = "qcom,kry 350 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 351 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 352 enable-method = "psci";
273 capacity-dmips-mhz = < 353 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici !! 354 cpu-idle-states = <&BIG_CPU_SLEEP_0
>> 355 &BIG_CPU_SLEEP_1
>> 356 &CLUSTER_SLEEP_0>;
>> 357 dynamic-power-coefficient = <396>;
275 qcom,freq-domain = <&c 358 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 359 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad !! 360 interconnects = <&gladiator_noc MASTER_APPSS_PROC &mem_noc SLAVE_EBI1>,
278 <&osm_ 361 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ <<
280 power-domain-names = " <<
281 #cooling-cells = <2>; 362 #cooling-cells = <2>;
282 next-level-cache = <&L 363 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 364 L2_700: l2-cache {
284 compatible = " 365 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 366 next-level-cache = <&L3_0>;
288 }; 367 };
289 }; 368 };
290 369
291 cpu-map { 370 cpu-map {
292 cluster0 { 371 cluster0 {
293 core0 { 372 core0 {
294 cpu = 373 cpu = <&CPU0>;
295 }; 374 };
296 375
297 core1 { 376 core1 {
298 cpu = 377 cpu = <&CPU1>;
299 }; 378 };
300 379
301 core2 { 380 core2 {
302 cpu = 381 cpu = <&CPU2>;
303 }; 382 };
304 383
305 core3 { 384 core3 {
306 cpu = 385 cpu = <&CPU3>;
307 }; 386 };
308 387
309 core4 { 388 core4 {
310 cpu = 389 cpu = <&CPU4>;
311 }; 390 };
312 391
313 core5 { 392 core5 {
314 cpu = 393 cpu = <&CPU5>;
315 }; 394 };
316 395
317 core6 { 396 core6 {
318 cpu = 397 cpu = <&CPU6>;
319 }; 398 };
320 399
321 core7 { 400 core7 {
322 cpu = 401 cpu = <&CPU7>;
323 }; 402 };
324 }; 403 };
325 }; 404 };
326 405
327 cpu_idle_states: idle-states { !! 406 idle-states {
328 entry-method = "psci"; 407 entry-method = "psci";
329 408
330 LITTLE_CPU_SLEEP_0: cp 409 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 410 compatible = "arm,idle-state";
332 idle-state-nam !! 411 idle-state-name = "little-power-down";
333 arm,psci-suspe !! 412 arm,psci-suspend-param = <0x40000003>;
334 entry-latency- 413 entry-latency-us = <350>;
335 exit-latency-u 414 exit-latency-us = <461>;
336 min-residency- 415 min-residency-us = <1890>;
337 local-timer-st 416 local-timer-stop;
338 }; 417 };
339 418
340 BIG_CPU_SLEEP_0: cpu-s !! 419 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
341 compatible = " 420 compatible = "arm,idle-state";
342 idle-state-nam !! 421 idle-state-name = "little-rail-power-down";
343 arm,psci-suspe 422 arm,psci-suspend-param = <0x40000004>;
>> 423 entry-latency-us = <360>;
>> 424 exit-latency-us = <531>;
>> 425 min-residency-us = <3934>;
>> 426 local-timer-stop;
>> 427 };
>> 428
>> 429 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
>> 430 compatible = "arm,idle-state";
>> 431 idle-state-name = "big-power-down";
>> 432 arm,psci-suspend-param = <0x40000003>;
344 entry-latency- 433 entry-latency-us = <264>;
345 exit-latency-u 434 exit-latency-us = <621>;
346 min-residency- 435 min-residency-us = <952>;
347 local-timer-st 436 local-timer-stop;
348 }; 437 };
349 }; <<
350 438
351 domain-idle-states { !! 439 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
>> 440 compatible = "arm,idle-state";
>> 441 idle-state-name = "big-rail-power-down";
>> 442 arm,psci-suspend-param = <0x40000004>;
>> 443 entry-latency-us = <702>;
>> 444 exit-latency-us = <1061>;
>> 445 min-residency-us = <4488>;
>> 446 local-timer-stop;
>> 447 };
>> 448
352 CLUSTER_SLEEP_0: clust 449 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " !! 450 compatible = "arm,idle-state";
354 arm,psci-suspe !! 451 idle-state-name = "cluster-power-down";
>> 452 arm,psci-suspend-param = <0x400000F4>;
355 entry-latency- 453 entry-latency-us = <3263>;
356 exit-latency-u 454 exit-latency-us = <6562>;
357 min-residency- 455 min-residency-us = <9987>;
>> 456 local-timer-stop;
358 }; 457 };
359 }; 458 };
360 }; 459 };
361 460
362 firmware { !! 461 cpu0_opp_table: cpu0_opp_table {
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { <<
375 compatible = "operating-points 462 compatible = "operating-points-v2";
376 opp-shared; 463 opp-shared;
377 464
378 cpu0_opp1: opp-300000000 { 465 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 466 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 467 opp-peak-kBps = <800000 4800000>;
381 }; 468 };
382 469
383 cpu0_opp2: opp-403200000 { 470 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 471 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 472 opp-peak-kBps = <800000 4800000>;
386 }; 473 };
387 474
388 cpu0_opp3: opp-480000000 { 475 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 476 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 477 opp-peak-kBps = <800000 6451200>;
391 }; 478 };
392 479
393 cpu0_opp4: opp-576000000 { 480 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 481 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 482 opp-peak-kBps = <800000 6451200>;
396 }; 483 };
397 484
398 cpu0_opp5: opp-652800000 { 485 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 486 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 487 opp-peak-kBps = <800000 7680000>;
401 }; 488 };
402 489
403 cpu0_opp6: opp-748800000 { 490 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 491 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 492 opp-peak-kBps = <1804000 9216000>;
406 }; 493 };
407 494
408 cpu0_opp7: opp-825600000 { 495 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 496 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 497 opp-peak-kBps = <1804000 9216000>;
411 }; 498 };
412 499
413 cpu0_opp8: opp-902400000 { 500 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 501 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 502 opp-peak-kBps = <1804000 10444800>;
416 }; 503 };
417 504
418 cpu0_opp9: opp-979200000 { 505 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 506 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 507 opp-peak-kBps = <1804000 11980800>;
421 }; 508 };
422 509
423 cpu0_opp10: opp-1056000000 { 510 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 511 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 512 opp-peak-kBps = <1804000 11980800>;
426 }; 513 };
427 514
428 cpu0_opp11: opp-1132800000 { 515 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 516 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 517 opp-peak-kBps = <2188000 13516800>;
431 }; 518 };
432 519
433 cpu0_opp12: opp-1228800000 { 520 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 521 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 522 opp-peak-kBps = <2188000 15052800>;
436 }; 523 };
437 524
438 cpu0_opp13: opp-1324800000 { 525 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 526 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 527 opp-peak-kBps = <2188000 16588800>;
441 }; 528 };
442 529
443 cpu0_opp14: opp-1420800000 { 530 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 531 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 532 opp-peak-kBps = <3072000 18124800>;
446 }; 533 };
447 534
448 cpu0_opp15: opp-1516800000 { 535 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 536 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 537 opp-peak-kBps = <3072000 19353600>;
451 }; 538 };
452 539
453 cpu0_opp16: opp-1612800000 { 540 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 541 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 542 opp-peak-kBps = <4068000 19353600>;
456 }; 543 };
457 544
458 cpu0_opp17: opp-1689600000 { 545 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 546 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 547 opp-peak-kBps = <4068000 20889600>;
461 }; 548 };
462 549
463 cpu0_opp18: opp-1766400000 { 550 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 551 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 552 opp-peak-kBps = <4068000 22425600>;
466 }; 553 };
467 }; 554 };
468 555
469 cpu4_opp_table: opp-table-cpu4 { !! 556 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 557 compatible = "operating-points-v2";
471 opp-shared; 558 opp-shared;
472 559
473 cpu4_opp1: opp-300000000 { 560 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 561 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 562 opp-peak-kBps = <800000 4800000>;
476 }; 563 };
477 564
478 cpu4_opp2: opp-403200000 { 565 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 566 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 567 opp-peak-kBps = <800000 4800000>;
481 }; 568 };
482 569
483 cpu4_opp3: opp-480000000 { 570 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 571 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 572 opp-peak-kBps = <1804000 4800000>;
486 }; 573 };
487 574
488 cpu4_opp4: opp-576000000 { 575 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 576 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 577 opp-peak-kBps = <1804000 4800000>;
491 }; 578 };
492 579
493 cpu4_opp5: opp-652800000 { 580 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 581 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 582 opp-peak-kBps = <1804000 4800000>;
496 }; 583 };
497 584
498 cpu4_opp6: opp-748800000 { 585 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 586 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 587 opp-peak-kBps = <1804000 4800000>;
501 }; 588 };
502 589
503 cpu4_opp7: opp-825600000 { 590 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 591 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 592 opp-peak-kBps = <2188000 9216000>;
506 }; 593 };
507 594
508 cpu4_opp8: opp-902400000 { 595 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 596 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 597 opp-peak-kBps = <2188000 9216000>;
511 }; 598 };
512 599
513 cpu4_opp9: opp-979200000 { 600 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 601 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 602 opp-peak-kBps = <2188000 9216000>;
516 }; 603 };
517 604
518 cpu4_opp10: opp-1056000000 { 605 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 606 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 607 opp-peak-kBps = <3072000 9216000>;
521 }; 608 };
522 609
523 cpu4_opp11: opp-1132800000 { 610 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 611 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 612 opp-peak-kBps = <3072000 11980800>;
526 }; 613 };
527 614
528 cpu4_opp12: opp-1209600000 { 615 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 616 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 617 opp-peak-kBps = <4068000 11980800>;
531 }; 618 };
532 619
533 cpu4_opp13: opp-1286400000 { 620 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 621 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 622 opp-peak-kBps = <4068000 11980800>;
536 }; 623 };
537 624
538 cpu4_opp14: opp-1363200000 { 625 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 626 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 627 opp-peak-kBps = <4068000 15052800>;
541 }; 628 };
542 629
543 cpu4_opp15: opp-1459200000 { 630 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 631 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 632 opp-peak-kBps = <4068000 15052800>;
546 }; 633 };
547 634
548 cpu4_opp16: opp-1536000000 { 635 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 636 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 637 opp-peak-kBps = <5412000 15052800>;
551 }; 638 };
552 639
553 cpu4_opp17: opp-1612800000 { 640 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 641 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 642 opp-peak-kBps = <5412000 15052800>;
556 }; 643 };
557 644
558 cpu4_opp18: opp-1689600000 { 645 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 646 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 647 opp-peak-kBps = <5412000 19353600>;
561 }; 648 };
562 649
563 cpu4_opp19: opp-1766400000 { 650 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 651 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 652 opp-peak-kBps = <6220000 19353600>;
566 }; 653 };
567 654
568 cpu4_opp20: opp-1843200000 { 655 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 656 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 657 opp-peak-kBps = <6220000 19353600>;
571 }; 658 };
572 659
573 cpu4_opp21: opp-1920000000 { 660 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 661 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 662 opp-peak-kBps = <7216000 19353600>;
576 }; 663 };
577 664
578 cpu4_opp22: opp-1996800000 { 665 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 666 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 667 opp-peak-kBps = <7216000 20889600>;
581 }; 668 };
582 669
583 cpu4_opp23: opp-2092800000 { 670 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 671 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 672 opp-peak-kBps = <7216000 20889600>;
586 }; 673 };
587 674
588 cpu4_opp24: opp-2169600000 { 675 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 676 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 677 opp-peak-kBps = <7216000 20889600>;
591 }; 678 };
592 679
593 cpu4_opp25: opp-2246400000 { 680 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 681 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 682 opp-peak-kBps = <7216000 20889600>;
596 }; 683 };
597 684
598 cpu4_opp26: opp-2323200000 { 685 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 686 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 687 opp-peak-kBps = <7216000 20889600>;
601 }; 688 };
602 689
603 cpu4_opp27: opp-2400000000 { 690 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 691 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 692 opp-peak-kBps = <7216000 22425600>;
606 }; 693 };
607 694
608 cpu4_opp28: opp-2476800000 { 695 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 696 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 697 opp-peak-kBps = <7216000 22425600>;
611 }; 698 };
612 699
613 cpu4_opp29: opp-2553600000 { 700 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 701 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 702 opp-peak-kBps = <7216000 22425600>;
616 }; 703 };
617 704
618 cpu4_opp30: opp-2649600000 { 705 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 706 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 707 opp-peak-kBps = <7216000 22425600>;
621 }; 708 };
622 709
623 cpu4_opp31: opp-2745600000 { 710 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 711 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 712 opp-peak-kBps = <7216000 25497600>;
626 }; 713 };
627 714
628 cpu4_opp32: opp-2803200000 { 715 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 716 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 717 opp-peak-kBps = <7216000 25497600>;
631 }; 718 };
632 }; 719 };
633 720
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 721 pmu {
712 compatible = "arm,armv8-pmuv3" 722 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 723 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 724 };
715 725
716 psci: psci { !! 726 timer {
717 compatible = "arm,psci-1.0"; !! 727 compatible = "arm,armv8-timer";
718 method = "smc"; !! 728 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 729 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 730 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 731 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 732 };
773 733
774 reserved-memory { !! 734 clocks {
775 #address-cells = <2>; !! 735 xo_board: xo-board {
776 #size-cells = <2>; !! 736 compatible = "fixed-clock";
777 ranges; !! 737 #clock-cells = <0>;
778 !! 738 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 739 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 740 };
885 741
886 mdata_mem: mpss-metadata { !! 742 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 743 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 744 #clock-cells = <0>;
889 no-map; !! 745 clock-frequency = <32764>;
890 }; 746 };
>> 747 };
891 748
892 fastrpc_mem: fastrpc { !! 749 firmware {
893 compatible = "shared-d !! 750 scm {
894 alloc-ranges = <0x0 0x !! 751 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 752 };
899 }; 753 };
900 754
901 adsp_pas: remoteproc-adsp { 755 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 756 compatible = "qcom,sdm845-adsp-pas";
903 757
904 interrupts-extended = <&intc G 758 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 759 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 760 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 761 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 762 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 763 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 764 "handover", "stop-ack";
911 765
912 clocks = <&rpmhcc RPMH_CXO_CLK 766 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 767 clock-names = "xo";
914 768
915 memory-region = <&adsp_mem>; 769 memory-region = <&adsp_mem>;
916 770
917 qcom,qmp = <&aoss_qmp>; <<
918 <<
919 qcom,smem-states = <&adsp_smp2 771 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 772 qcom,smem-state-names = "stop";
921 773
922 status = "disabled"; 774 status = "disabled";
923 775
924 glink-edge { 776 glink-edge {
925 interrupts = <GIC_SPI 777 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 778 label = "lpass";
927 qcom,remote-pid = <2>; 779 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 780 mboxes = <&apss_shared 8>;
929 781
930 apr { 782 apr {
931 compatible = " 783 compatible = "qcom,apr-v2";
932 qcom,glink-cha 784 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = !! 785 qcom,apr-domain = <APR_DOMAIN_ADSP>;
934 #address-cells 786 #address-cells = <1>;
935 #size-cells = 787 #size-cells = <0>;
936 qcom,intents = 788 qcom,intents = <512 20>;
937 789
938 service@3 { !! 790 apr-service@3 {
939 reg = 791 reg = <APR_SVC_ADSP_CORE>;
940 compat 792 compatible = "qcom,q6core";
941 qcom,p 793 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 794 };
943 795
944 q6afe: service !! 796 q6afe: apr-service@4 {
945 compat 797 compatible = "qcom,q6afe";
946 reg = 798 reg = <APR_SVC_AFE>;
947 qcom,p 799 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 800 q6afedai: dais {
949 801 compatible = "qcom,q6afe-dais";
950 802 #address-cells = <1>;
951 803 #size-cells = <0>;
952 804 #sound-dai-cells = <1>;
953 }; 805 };
954 }; 806 };
955 807
956 q6asm: service !! 808 q6asm: apr-service@7 {
957 compat 809 compatible = "qcom,q6asm";
958 reg = 810 reg = <APR_SVC_ASM>;
959 qcom,p 811 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 812 q6asmdai: dais {
961 813 compatible = "qcom,q6asm-dais";
962 814 #address-cells = <1>;
963 815 #size-cells = <0>;
964 816 #sound-dai-cells = <1>;
965 817 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 818 };
967 }; 819 };
968 820
969 q6adm: service !! 821 q6adm: apr-service@8 {
970 compat 822 compatible = "qcom,q6adm";
971 reg = 823 reg = <APR_SVC_ADM>;
972 qcom,p 824 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 825 q6routing: routing {
974 826 compatible = "qcom,q6adm-routing";
975 827 #sound-dai-cells = <0>;
976 }; 828 };
977 }; 829 };
978 }; 830 };
979 831
980 fastrpc { 832 fastrpc {
981 compatible = " 833 compatible = "qcom,fastrpc";
982 qcom,glink-cha 834 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 835 label = "adsp";
984 qcom,non-secur <<
985 #address-cells 836 #address-cells = <1>;
986 #size-cells = 837 #size-cells = <0>;
987 838
988 compute-cb@3 { 839 compute-cb@3 {
989 compat 840 compatible = "qcom,fastrpc-compute-cb";
990 reg = 841 reg = <3>;
991 iommus 842 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 843 };
993 844
994 compute-cb@4 { 845 compute-cb@4 {
995 compat 846 compatible = "qcom,fastrpc-compute-cb";
996 reg = 847 reg = <4>;
997 iommus 848 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 849 };
999 }; 850 };
1000 }; 851 };
1001 }; 852 };
1002 853
1003 cdsp_pas: remoteproc-cdsp { 854 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 855 compatible = "qcom,sdm845-cdsp-pas";
1005 856
1006 interrupts-extended = <&intc 857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 858 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 859 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 860 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 861 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 862 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 863 "handover", "stop-ack";
1013 864
1014 clocks = <&rpmhcc RPMH_CXO_CL 865 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 866 clock-names = "xo";
1016 867
1017 memory-region = <&cdsp_mem>; 868 memory-region = <&cdsp_mem>;
1018 869
1019 qcom,qmp = <&aoss_qmp>; <<
1020 <<
1021 qcom,smem-states = <&cdsp_smp 870 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 871 qcom,smem-state-names = "stop";
1023 872
1024 status = "disabled"; 873 status = "disabled";
1025 874
1026 glink-edge { 875 glink-edge {
1027 interrupts = <GIC_SPI 876 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 877 label = "turing";
1029 qcom,remote-pid = <5> 878 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 879 mboxes = <&apss_shared 4>;
1031 fastrpc { 880 fastrpc {
1032 compatible = 881 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 882 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 883 label = "cdsp";
1035 qcom,non-secu <<
1036 #address-cell 884 #address-cells = <1>;
1037 #size-cells = 885 #size-cells = <0>;
1038 886
1039 compute-cb@1 887 compute-cb@1 {
1040 compa 888 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 889 reg = <1>;
1042 iommu 890 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 891 };
1044 892
1045 compute-cb@2 893 compute-cb@2 {
1046 compa 894 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 895 reg = <2>;
1048 iommu 896 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 897 };
1050 898
1051 compute-cb@3 899 compute-cb@3 {
1052 compa 900 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 901 reg = <3>;
1054 iommu 902 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 903 };
1056 904
1057 compute-cb@4 905 compute-cb@4 {
1058 compa 906 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 907 reg = <4>;
1060 iommu 908 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 909 };
1062 910
1063 compute-cb@5 911 compute-cb@5 {
1064 compa 912 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 913 reg = <5>;
1066 iommu 914 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 915 };
1068 916
1069 compute-cb@6 917 compute-cb@6 {
1070 compa 918 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 919 reg = <6>;
1072 iommu 920 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 921 };
1074 922
1075 compute-cb@7 923 compute-cb@7 {
1076 compa 924 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 925 reg = <7>;
1078 iommu 926 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 927 };
1080 928
1081 compute-cb@8 929 compute-cb@8 {
1082 compa 930 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 931 reg = <8>;
1084 iommu 932 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 933 };
1086 }; 934 };
1087 }; 935 };
1088 }; 936 };
1089 937
>> 938 tcsr_mutex: hwlock {
>> 939 compatible = "qcom,tcsr-mutex";
>> 940 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 941 #hwlock-cells = <1>;
>> 942 };
>> 943
>> 944 smem {
>> 945 compatible = "qcom,smem";
>> 946 memory-region = <&smem_mem>;
>> 947 hwlocks = <&tcsr_mutex 3>;
>> 948 };
>> 949
1090 smp2p-cdsp { 950 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 951 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 952 qcom,smem = <94>, <432>;
1093 953
1094 interrupts = <GIC_SPI 576 IRQ 954 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 955
1096 mboxes = <&apss_shared 6>; 956 mboxes = <&apss_shared 6>;
1097 957
1098 qcom,local-pid = <0>; 958 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 959 qcom,remote-pid = <5>;
1100 960
1101 cdsp_smp2p_out: master-kernel 961 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 962 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 963 #qcom,smem-state-cells = <1>;
1104 }; 964 };
1105 965
1106 cdsp_smp2p_in: slave-kernel { 966 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 967 qcom,entry-name = "slave-kernel";
1108 968
1109 interrupt-controller; 969 interrupt-controller;
1110 #interrupt-cells = <2 970 #interrupt-cells = <2>;
1111 }; 971 };
1112 }; 972 };
1113 973
1114 smp2p-lpass { 974 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 975 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 976 qcom,smem = <443>, <429>;
1117 977
1118 interrupts = <GIC_SPI 158 IRQ 978 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 979
1120 mboxes = <&apss_shared 10>; 980 mboxes = <&apss_shared 10>;
1121 981
1122 qcom,local-pid = <0>; 982 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 983 qcom,remote-pid = <2>;
1124 984
1125 adsp_smp2p_out: master-kernel 985 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 986 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 987 #qcom,smem-state-cells = <1>;
1128 }; 988 };
1129 989
1130 adsp_smp2p_in: slave-kernel { 990 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 991 qcom,entry-name = "slave-kernel";
1132 992
1133 interrupt-controller; 993 interrupt-controller;
1134 #interrupt-cells = <2 994 #interrupt-cells = <2>;
1135 }; 995 };
1136 }; 996 };
1137 997
1138 smp2p-mpss { 998 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 999 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 1000 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 1001 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 1002 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 1003 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 1004 qcom,remote-pid = <1>;
1145 1005
1146 modem_smp2p_out: master-kerne 1006 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 1007 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 1008 #qcom,smem-state-cells = <1>;
1149 }; 1009 };
1150 1010
1151 modem_smp2p_in: slave-kernel 1011 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 1012 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 1013 interrupt-controller;
1154 #interrupt-cells = <2 1014 #interrupt-cells = <2>;
1155 }; 1015 };
1156 1016
1157 ipa_smp2p_out: ipa-ap-to-mode 1017 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 1018 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 1019 #qcom,smem-state-cells = <1>;
1160 }; 1020 };
1161 1021
1162 ipa_smp2p_in: ipa-modem-to-ap 1022 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1023 qcom,entry-name = "ipa";
1164 interrupt-controller; 1024 interrupt-controller;
1165 #interrupt-cells = <2 1025 #interrupt-cells = <2>;
1166 }; 1026 };
1167 }; 1027 };
1168 1028
1169 smp2p-slpi { 1029 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1030 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1031 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1032 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1033 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1034 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1035 qcom,remote-pid = <3>;
1176 1036
1177 slpi_smp2p_out: master-kernel 1037 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1038 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1039 #qcom,smem-state-cells = <1>;
1180 }; 1040 };
1181 1041
1182 slpi_smp2p_in: slave-kernel { 1042 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1043 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1044 interrupt-controller;
1185 #interrupt-cells = <2 1045 #interrupt-cells = <2>;
1186 }; 1046 };
1187 }; 1047 };
1188 1048
>> 1049 psci {
>> 1050 compatible = "arm,psci-1.0";
>> 1051 method = "smc";
>> 1052 };
>> 1053
1189 soc: soc@0 { 1054 soc: soc@0 {
1190 #address-cells = <2>; 1055 #address-cells = <2>;
1191 #size-cells = <2>; 1056 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1057 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1058 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1059 compatible = "simple-bus";
1195 1060
1196 gcc: clock-controller@100000 1061 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1062 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1063 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM <<
1200 <&rpmhcc RPM <<
1201 <&sleep_clk> <<
1202 <&pcie0_phy> <<
1203 <&pcie1_phy> <<
1204 clock-names = "bi_tcx <<
1205 "bi_tcx <<
1206 "sleep_ <<
1207 "pcie_0 <<
1208 "pcie_1 <<
1209 #clock-cells = <1>; 1064 #clock-cells = <1>;
1210 #reset-cells = <1>; 1065 #reset-cells = <1>;
1211 #power-domain-cells = 1066 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 1067 };
1214 1068
1215 qfprom@784000 { 1069 qfprom@784000 {
1216 compatible = "qcom,sd !! 1070 compatible = "qcom,qfprom";
1217 reg = <0 0x00784000 0 1071 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1072 #address-cells = <1>;
1219 #size-cells = <1>; 1073 #size-cells = <1>;
1220 1074
1221 qusb2p_hstx_trim: hst 1075 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1076 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1077 bits = <1 4>;
1224 }; 1078 };
1225 1079
1226 qusb2s_hstx_trim: hst 1080 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1081 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1082 bits = <6 4>;
1229 }; 1083 };
1230 }; 1084 };
1231 1085
1232 rng: rng@793000 { 1086 rng: rng@793000 {
1233 compatible = "qcom,pr 1087 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1088 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1089 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1090 clock-names = "core";
1237 }; 1091 };
1238 1092
1239 gpi_dma0: dma-controller@8000 !! 1093 qup_opp_table: qup-opp-table {
1240 #dma-cells = <3>; !! 1094 compatible = "operating-points-v2";
1241 compatible = "qcom,sd !! 1095
1242 reg = <0 0x00800000 0 !! 1096 opp-50000000 {
1243 interrupts = <GIC_SPI !! 1097 opp-hz = /bits/ 64 <50000000>;
1244 <GIC_SPI !! 1098 required-opps = <&rpmhpd_opp_min_svs>;
1245 <GIC_SPI !! 1099 };
1246 <GIC_SPI !! 1100
1247 <GIC_SPI !! 1101 opp-75000000 {
1248 <GIC_SPI !! 1102 opp-hz = /bits/ 64 <75000000>;
1249 <GIC_SPI !! 1103 required-opps = <&rpmhpd_opp_low_svs>;
1250 <GIC_SPI !! 1104 };
1251 <GIC_SPI !! 1105
1252 <GIC_SPI !! 1106 opp-100000000 {
1253 <GIC_SPI !! 1107 opp-hz = /bits/ 64 <100000000>;
1254 <GIC_SPI !! 1108 required-opps = <&rpmhpd_opp_svs>;
1255 <GIC_SPI !! 1109 };
1256 dma-channels = <13>; !! 1110
1257 dma-channel-mask = <0 !! 1111 opp-128000000 {
1258 iommus = <&apps_smmu !! 1112 opp-hz = /bits/ 64 <128000000>;
1259 status = "disabled"; !! 1113 required-opps = <&rpmhpd_opp_nom>;
>> 1114 };
1260 }; 1115 };
1261 1116
1262 qupv3_id_0: geniqup@8c0000 { 1117 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1118 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1119 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1120 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1121 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1122 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu <<
1269 #address-cells = <2>; 1123 #address-cells = <2>;
1270 #size-cells = <2>; 1124 #size-cells = <2>;
1271 ranges; 1125 ranges;
1272 interconnects = <&agg <<
1273 interconnect-names = <<
1274 status = "disabled"; 1126 status = "disabled";
1275 1127
1276 i2c0: i2c@880000 { 1128 i2c0: i2c@880000 {
1277 compatible = 1129 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1130 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1131 clock-names = "se";
1280 clocks = <&gc 1132 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1133 pinctrl-names = "default";
1282 pinctrl-0 = < 1134 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1135 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1136 #address-cells = <1>;
1285 #size-cells = 1137 #size-cells = <0>;
1286 power-domains 1138 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1139 operating-points-v2 = <&qup_opp_table>;
1288 interconnects <<
1289 <<
1290 <<
1291 interconnect- <<
1292 dmas = <&gpi_ <<
1293 <&gpi_ <<
1294 dma-names = " <<
1295 status = "dis 1140 status = "disabled";
1296 }; 1141 };
1297 1142
1298 spi0: spi@880000 { 1143 spi0: spi@880000 {
1299 compatible = 1144 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1145 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1146 clock-names = "se";
1302 clocks = <&gc 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1148 pinctrl-names = "default";
1304 pinctrl-0 = < 1149 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1150 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1151 #address-cells = <1>;
1307 #size-cells = 1152 #size-cells = <0>;
1308 interconnects <<
1309 <<
1310 interconnect- <<
1311 dmas = <&gpi_ <<
1312 <&gpi_ <<
1313 dma-names = " <<
1314 status = "dis 1153 status = "disabled";
1315 }; 1154 };
1316 1155
1317 uart0: serial@880000 1156 uart0: serial@880000 {
1318 compatible = 1157 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1158 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1159 clock-names = "se";
1321 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1161 pinctrl-names = "default";
1323 pinctrl-0 = < 1162 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1163 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1164 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1165 operating-points-v2 = <&qup_opp_table>;
1327 interconnects <<
1328 <<
1329 interconnect- <<
1330 status = "dis 1166 status = "disabled";
1331 }; 1167 };
1332 1168
1333 i2c1: i2c@884000 { 1169 i2c1: i2c@884000 {
1334 compatible = 1170 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1171 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1172 clock-names = "se";
1337 clocks = <&gc 1173 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1174 pinctrl-names = "default";
1339 pinctrl-0 = < 1175 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1176 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1177 #address-cells = <1>;
1342 #size-cells = 1178 #size-cells = <0>;
1343 power-domains 1179 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1180 operating-points-v2 = <&qup_opp_table>;
1345 interconnects <<
1346 <<
1347 <<
1348 interconnect- <<
1349 dmas = <&gpi_ <<
1350 <&gpi_ <<
1351 dma-names = " <<
1352 status = "dis 1181 status = "disabled";
1353 }; 1182 };
1354 1183
1355 spi1: spi@884000 { 1184 spi1: spi@884000 {
1356 compatible = 1185 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1186 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1187 clock-names = "se";
1359 clocks = <&gc 1188 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1189 pinctrl-names = "default";
1361 pinctrl-0 = < 1190 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1191 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1192 #address-cells = <1>;
1364 #size-cells = 1193 #size-cells = <0>;
1365 interconnects <<
1366 <<
1367 interconnect- <<
1368 dmas = <&gpi_ <<
1369 <&gpi_ <<
1370 dma-names = " <<
1371 status = "dis 1194 status = "disabled";
1372 }; 1195 };
1373 1196
1374 uart1: serial@884000 1197 uart1: serial@884000 {
1375 compatible = 1198 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1199 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1200 clock-names = "se";
1378 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1202 pinctrl-names = "default";
1380 pinctrl-0 = < 1203 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1204 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1205 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1206 operating-points-v2 = <&qup_opp_table>;
1384 interconnects <<
1385 <<
1386 interconnect- <<
1387 status = "dis 1207 status = "disabled";
1388 }; 1208 };
1389 1209
1390 i2c2: i2c@888000 { 1210 i2c2: i2c@888000 {
1391 compatible = 1211 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1212 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1213 clock-names = "se";
1394 clocks = <&gc 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1215 pinctrl-names = "default";
1396 pinctrl-0 = < 1216 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1217 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1218 #address-cells = <1>;
1399 #size-cells = 1219 #size-cells = <0>;
1400 power-domains 1220 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1221 operating-points-v2 = <&qup_opp_table>;
1402 interconnects <<
1403 <<
1404 <<
1405 interconnect- <<
1406 dmas = <&gpi_ <<
1407 <&gpi_ <<
1408 dma-names = " <<
1409 status = "dis 1222 status = "disabled";
1410 }; 1223 };
1411 1224
1412 spi2: spi@888000 { 1225 spi2: spi@888000 {
1413 compatible = 1226 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1227 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1228 clock-names = "se";
1416 clocks = <&gc 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1230 pinctrl-names = "default";
1418 pinctrl-0 = < 1231 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1232 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1233 #address-cells = <1>;
1421 #size-cells = 1234 #size-cells = <0>;
1422 interconnects <<
1423 <<
1424 interconnect- <<
1425 dmas = <&gpi_ <<
1426 <&gpi_ <<
1427 dma-names = " <<
1428 status = "dis 1235 status = "disabled";
1429 }; 1236 };
1430 1237
1431 uart2: serial@888000 1238 uart2: serial@888000 {
1432 compatible = 1239 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1240 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1241 clock-names = "se";
1435 clocks = <&gc 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1243 pinctrl-names = "default";
1437 pinctrl-0 = < 1244 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1245 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1246 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1247 operating-points-v2 = <&qup_opp_table>;
1441 interconnects <<
1442 <<
1443 interconnect- <<
1444 status = "dis 1248 status = "disabled";
1445 }; 1249 };
1446 1250
1447 i2c3: i2c@88c000 { 1251 i2c3: i2c@88c000 {
1448 compatible = 1252 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1253 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1254 clock-names = "se";
1451 clocks = <&gc 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1256 pinctrl-names = "default";
1453 pinctrl-0 = < 1257 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1258 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1259 #address-cells = <1>;
1456 #size-cells = 1260 #size-cells = <0>;
1457 power-domains 1261 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1262 operating-points-v2 = <&qup_opp_table>;
1459 interconnects <<
1460 <<
1461 <<
1462 interconnect- <<
1463 dmas = <&gpi_ <<
1464 <&gpi_ <<
1465 dma-names = " <<
1466 status = "dis 1263 status = "disabled";
1467 }; 1264 };
1468 1265
1469 spi3: spi@88c000 { 1266 spi3: spi@88c000 {
1470 compatible = 1267 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1268 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1269 clock-names = "se";
1473 clocks = <&gc 1270 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1271 pinctrl-names = "default";
1475 pinctrl-0 = < 1272 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1273 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1274 #address-cells = <1>;
1478 #size-cells = 1275 #size-cells = <0>;
1479 interconnects <<
1480 <<
1481 interconnect- <<
1482 dmas = <&gpi_ <<
1483 <&gpi_ <<
1484 dma-names = " <<
1485 status = "dis 1276 status = "disabled";
1486 }; 1277 };
1487 1278
1488 uart3: serial@88c000 1279 uart3: serial@88c000 {
1489 compatible = 1280 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1281 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1282 clock-names = "se";
1492 clocks = <&gc 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1284 pinctrl-names = "default";
1494 pinctrl-0 = < 1285 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1286 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1287 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1288 operating-points-v2 = <&qup_opp_table>;
1498 interconnects <<
1499 <<
1500 interconnect- <<
1501 status = "dis 1289 status = "disabled";
1502 }; 1290 };
1503 1291
1504 i2c4: i2c@890000 { 1292 i2c4: i2c@890000 {
1505 compatible = 1293 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1294 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1295 clock-names = "se";
1508 clocks = <&gc 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1297 pinctrl-names = "default";
1510 pinctrl-0 = < 1298 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1299 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1300 #address-cells = <1>;
1513 #size-cells = 1301 #size-cells = <0>;
1514 power-domains 1302 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1303 operating-points-v2 = <&qup_opp_table>;
1516 interconnects <<
1517 <<
1518 <<
1519 interconnect- <<
1520 dmas = <&gpi_ <<
1521 <&gpi_ <<
1522 dma-names = " <<
1523 status = "dis 1304 status = "disabled";
1524 }; 1305 };
1525 1306
1526 spi4: spi@890000 { 1307 spi4: spi@890000 {
1527 compatible = 1308 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1309 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1310 clock-names = "se";
1530 clocks = <&gc 1311 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1312 pinctrl-names = "default";
1532 pinctrl-0 = < 1313 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1314 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1315 #address-cells = <1>;
1535 #size-cells = 1316 #size-cells = <0>;
1536 interconnects <<
1537 <<
1538 interconnect- <<
1539 dmas = <&gpi_ <<
1540 <&gpi_ <<
1541 dma-names = " <<
1542 status = "dis 1317 status = "disabled";
1543 }; 1318 };
1544 1319
1545 uart4: serial@890000 1320 uart4: serial@890000 {
1546 compatible = 1321 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1322 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1323 clock-names = "se";
1549 clocks = <&gc 1324 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1325 pinctrl-names = "default";
1551 pinctrl-0 = < 1326 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1327 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1328 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1329 operating-points-v2 = <&qup_opp_table>;
1555 interconnects <<
1556 <<
1557 interconnect- <<
1558 status = "dis 1330 status = "disabled";
1559 }; 1331 };
1560 1332
1561 i2c5: i2c@894000 { 1333 i2c5: i2c@894000 {
1562 compatible = 1334 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1335 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1336 clock-names = "se";
1565 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1338 pinctrl-names = "default";
1567 pinctrl-0 = < 1339 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1340 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1341 #address-cells = <1>;
1570 #size-cells = 1342 #size-cells = <0>;
1571 power-domains 1343 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1344 operating-points-v2 = <&qup_opp_table>;
1573 interconnects <<
1574 <<
1575 <<
1576 interconnect- <<
1577 dmas = <&gpi_ <<
1578 <&gpi_ <<
1579 dma-names = " <<
1580 status = "dis 1345 status = "disabled";
1581 }; 1346 };
1582 1347
1583 spi5: spi@894000 { 1348 spi5: spi@894000 {
1584 compatible = 1349 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1350 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1351 clock-names = "se";
1587 clocks = <&gc 1352 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1353 pinctrl-names = "default";
1589 pinctrl-0 = < 1354 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1355 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1356 #address-cells = <1>;
1592 #size-cells = 1357 #size-cells = <0>;
1593 interconnects <<
1594 <<
1595 interconnect- <<
1596 dmas = <&gpi_ <<
1597 <&gpi_ <<
1598 dma-names = " <<
1599 status = "dis 1358 status = "disabled";
1600 }; 1359 };
1601 1360
1602 uart5: serial@894000 1361 uart5: serial@894000 {
1603 compatible = 1362 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1363 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1364 clock-names = "se";
1606 clocks = <&gc 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1366 pinctrl-names = "default";
1608 pinctrl-0 = < 1367 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1368 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1369 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1370 operating-points-v2 = <&qup_opp_table>;
1612 interconnects <<
1613 <<
1614 interconnect- <<
1615 status = "dis 1371 status = "disabled";
1616 }; 1372 };
1617 1373
1618 i2c6: i2c@898000 { 1374 i2c6: i2c@898000 {
1619 compatible = 1375 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1376 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1377 clock-names = "se";
1622 clocks = <&gc 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1379 pinctrl-names = "default";
1624 pinctrl-0 = < 1380 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1381 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1382 #address-cells = <1>;
1627 #size-cells = 1383 #size-cells = <0>;
1628 power-domains 1384 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1385 operating-points-v2 = <&qup_opp_table>;
1630 interconnects <<
1631 <<
1632 <<
1633 interconnect- <<
1634 dmas = <&gpi_ <<
1635 <&gpi_ <<
1636 dma-names = " <<
1637 status = "dis 1386 status = "disabled";
1638 }; 1387 };
1639 1388
1640 spi6: spi@898000 { 1389 spi6: spi@898000 {
1641 compatible = 1390 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1391 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1392 clock-names = "se";
1644 clocks = <&gc 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1394 pinctrl-names = "default";
1646 pinctrl-0 = < 1395 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1396 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1397 #address-cells = <1>;
1649 #size-cells = 1398 #size-cells = <0>;
1650 interconnects <<
1651 <<
1652 interconnect- <<
1653 dmas = <&gpi_ <<
1654 <&gpi_ <<
1655 dma-names = " <<
1656 status = "dis 1399 status = "disabled";
1657 }; 1400 };
1658 1401
1659 uart6: serial@898000 1402 uart6: serial@898000 {
1660 compatible = 1403 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1404 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1405 clock-names = "se";
1663 clocks = <&gc 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1407 pinctrl-names = "default";
1665 pinctrl-0 = < 1408 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1409 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1410 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1411 operating-points-v2 = <&qup_opp_table>;
1669 interconnects <<
1670 <<
1671 interconnect- <<
1672 status = "dis 1412 status = "disabled";
1673 }; 1413 };
1674 1414
1675 i2c7: i2c@89c000 { 1415 i2c7: i2c@89c000 {
1676 compatible = 1416 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1417 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1418 clock-names = "se";
1679 clocks = <&gc 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1420 pinctrl-names = "default";
1681 pinctrl-0 = < 1421 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1422 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1423 #address-cells = <1>;
1684 #size-cells = 1424 #size-cells = <0>;
1685 power-domains 1425 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1426 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1427 status = "disabled";
1688 }; 1428 };
1689 1429
1690 spi7: spi@89c000 { 1430 spi7: spi@89c000 {
1691 compatible = 1431 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1432 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1433 clock-names = "se";
1694 clocks = <&gc 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1435 pinctrl-names = "default";
1696 pinctrl-0 = < 1436 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1437 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1438 #address-cells = <1>;
1699 #size-cells = 1439 #size-cells = <0>;
1700 interconnects <<
1701 <<
1702 interconnect- <<
1703 dmas = <&gpi_ <<
1704 <&gpi_ <<
1705 dma-names = " <<
1706 status = "dis 1440 status = "disabled";
1707 }; 1441 };
1708 1442
1709 uart7: serial@89c000 1443 uart7: serial@89c000 {
1710 compatible = 1444 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1445 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1446 clock-names = "se";
1713 clocks = <&gc 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1448 pinctrl-names = "default";
1715 pinctrl-0 = < 1449 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1450 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1451 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1452 operating-points-v2 = <&qup_opp_table>;
1719 interconnects <<
1720 <<
1721 interconnect- <<
1722 status = "dis 1453 status = "disabled";
1723 }; 1454 };
1724 }; 1455 };
1725 1456
1726 gpi_dma1: dma-controller@a000 <<
1727 #dma-cells = <3>; <<
1728 compatible = "qcom,sd <<
1729 reg = <0 0x00a00000 0 <<
1730 interrupts = <GIC_SPI <<
1731 <GIC_SPI <<
1732 <GIC_SPI <<
1733 <GIC_SPI <<
1734 <GIC_SPI <<
1735 <GIC_SPI <<
1736 <GIC_SPI <<
1737 <GIC_SPI <<
1738 <GIC_SPI <<
1739 <GIC_SPI <<
1740 <GIC_SPI <<
1741 <GIC_SPI <<
1742 <GIC_SPI <<
1743 dma-channels = <13>; <<
1744 dma-channel-mask = <0 <<
1745 iommus = <&apps_smmu <<
1746 status = "disabled"; <<
1747 }; <<
1748 <<
1749 qupv3_id_1: geniqup@ac0000 { 1457 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1458 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1459 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1460 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1461 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1462 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu <<
1756 #address-cells = <2>; 1463 #address-cells = <2>;
1757 #size-cells = <2>; 1464 #size-cells = <2>;
1758 ranges; 1465 ranges;
1759 interconnects = <&agg <<
1760 interconnect-names = <<
1761 status = "disabled"; 1466 status = "disabled";
1762 1467
1763 i2c8: i2c@a80000 { 1468 i2c8: i2c@a80000 {
1764 compatible = 1469 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1470 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1471 clock-names = "se";
1767 clocks = <&gc 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1473 pinctrl-names = "default";
1769 pinctrl-0 = < 1474 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1475 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1476 #address-cells = <1>;
1772 #size-cells = 1477 #size-cells = <0>;
1773 power-domains 1478 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1479 operating-points-v2 = <&qup_opp_table>;
1775 interconnects <<
1776 <<
1777 <<
1778 interconnect- <<
1779 dmas = <&gpi_ <<
1780 <&gpi_ <<
1781 dma-names = " <<
1782 status = "dis 1480 status = "disabled";
1783 }; 1481 };
1784 1482
1785 spi8: spi@a80000 { 1483 spi8: spi@a80000 {
1786 compatible = 1484 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1485 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1486 clock-names = "se";
1789 clocks = <&gc 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1488 pinctrl-names = "default";
1791 pinctrl-0 = < 1489 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1490 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1491 #address-cells = <1>;
1794 #size-cells = 1492 #size-cells = <0>;
1795 interconnects <<
1796 <<
1797 interconnect- <<
1798 dmas = <&gpi_ <<
1799 <&gpi_ <<
1800 dma-names = " <<
1801 status = "dis 1493 status = "disabled";
1802 }; 1494 };
1803 1495
1804 uart8: serial@a80000 1496 uart8: serial@a80000 {
1805 compatible = 1497 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1498 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1499 clock-names = "se";
1808 clocks = <&gc 1500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1501 pinctrl-names = "default";
1810 pinctrl-0 = < 1502 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1504 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1505 operating-points-v2 = <&qup_opp_table>;
1814 interconnects <<
1815 <<
1816 interconnect- <<
1817 status = "dis 1506 status = "disabled";
1818 }; 1507 };
1819 1508
1820 i2c9: i2c@a84000 { 1509 i2c9: i2c@a84000 {
1821 compatible = 1510 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1511 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1512 clock-names = "se";
1824 clocks = <&gc 1513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1514 pinctrl-names = "default";
1826 pinctrl-0 = < 1515 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1516 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1517 #address-cells = <1>;
1829 #size-cells = 1518 #size-cells = <0>;
1830 power-domains 1519 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1520 operating-points-v2 = <&qup_opp_table>;
1832 interconnects <<
1833 <<
1834 <<
1835 interconnect- <<
1836 dmas = <&gpi_ <<
1837 <&gpi_ <<
1838 dma-names = " <<
1839 status = "dis 1521 status = "disabled";
1840 }; 1522 };
1841 1523
1842 spi9: spi@a84000 { 1524 spi9: spi@a84000 {
1843 compatible = 1525 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1526 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1527 clock-names = "se";
1846 clocks = <&gc 1528 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1529 pinctrl-names = "default";
1848 pinctrl-0 = < 1530 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1531 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1532 #address-cells = <1>;
1851 #size-cells = 1533 #size-cells = <0>;
1852 interconnects <<
1853 <<
1854 interconnect- <<
1855 dmas = <&gpi_ <<
1856 <&gpi_ <<
1857 dma-names = " <<
1858 status = "dis 1534 status = "disabled";
1859 }; 1535 };
1860 1536
1861 uart9: serial@a84000 1537 uart9: serial@a84000 {
1862 compatible = 1538 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1539 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1540 clock-names = "se";
1865 clocks = <&gc 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1542 pinctrl-names = "default";
1867 pinctrl-0 = < 1543 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1544 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1545 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1546 operating-points-v2 = <&qup_opp_table>;
1871 interconnects <<
1872 <<
1873 interconnect- <<
1874 status = "dis 1547 status = "disabled";
1875 }; 1548 };
1876 1549
1877 i2c10: i2c@a88000 { 1550 i2c10: i2c@a88000 {
1878 compatible = 1551 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1552 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1553 clock-names = "se";
1881 clocks = <&gc 1554 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1555 pinctrl-names = "default";
1883 pinctrl-0 = < 1556 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1558 #address-cells = <1>;
1886 #size-cells = 1559 #size-cells = <0>;
1887 power-domains 1560 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1561 operating-points-v2 = <&qup_opp_table>;
1889 interconnects <<
1890 <<
1891 <<
1892 interconnect- <<
1893 dmas = <&gpi_ <<
1894 <&gpi_ <<
1895 dma-names = " <<
1896 status = "dis 1562 status = "disabled";
1897 }; 1563 };
1898 1564
1899 spi10: spi@a88000 { 1565 spi10: spi@a88000 {
1900 compatible = 1566 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1567 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1568 clock-names = "se";
1903 clocks = <&gc 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1570 pinctrl-names = "default";
1905 pinctrl-0 = < 1571 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1572 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1573 #address-cells = <1>;
1908 #size-cells = 1574 #size-cells = <0>;
1909 interconnects <<
1910 <<
1911 interconnect- <<
1912 dmas = <&gpi_ <<
1913 <&gpi_ <<
1914 dma-names = " <<
1915 status = "dis 1575 status = "disabled";
1916 }; 1576 };
1917 1577
1918 uart10: serial@a88000 1578 uart10: serial@a88000 {
1919 compatible = 1579 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1580 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1581 clock-names = "se";
1922 clocks = <&gc 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1583 pinctrl-names = "default";
1924 pinctrl-0 = < 1584 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1585 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1586 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1587 operating-points-v2 = <&qup_opp_table>;
1928 interconnects <<
1929 <<
1930 interconnect- <<
1931 status = "dis 1588 status = "disabled";
1932 }; 1589 };
1933 1590
1934 i2c11: i2c@a8c000 { 1591 i2c11: i2c@a8c000 {
1935 compatible = 1592 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1593 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1594 clock-names = "se";
1938 clocks = <&gc 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1596 pinctrl-names = "default";
1940 pinctrl-0 = < 1597 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1598 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1599 #address-cells = <1>;
1943 #size-cells = 1600 #size-cells = <0>;
1944 power-domains 1601 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1602 operating-points-v2 = <&qup_opp_table>;
1946 interconnects <<
1947 <<
1948 <<
1949 interconnect- <<
1950 dmas = <&gpi_ <<
1951 <&gpi_ <<
1952 dma-names = " <<
1953 status = "dis 1603 status = "disabled";
1954 }; 1604 };
1955 1605
1956 spi11: spi@a8c000 { 1606 spi11: spi@a8c000 {
1957 compatible = 1607 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1608 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1609 clock-names = "se";
1960 clocks = <&gc 1610 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1611 pinctrl-names = "default";
1962 pinctrl-0 = < 1612 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1613 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1614 #address-cells = <1>;
1965 #size-cells = 1615 #size-cells = <0>;
1966 interconnects <<
1967 <<
1968 interconnect- <<
1969 dmas = <&gpi_ <<
1970 <&gpi_ <<
1971 dma-names = " <<
1972 status = "dis 1616 status = "disabled";
1973 }; 1617 };
1974 1618
1975 uart11: serial@a8c000 1619 uart11: serial@a8c000 {
1976 compatible = 1620 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1621 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1622 clock-names = "se";
1979 clocks = <&gc 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1624 pinctrl-names = "default";
1981 pinctrl-0 = < 1625 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1626 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1627 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1628 operating-points-v2 = <&qup_opp_table>;
1985 interconnects <<
1986 <<
1987 interconnect- <<
1988 status = "dis 1629 status = "disabled";
1989 }; 1630 };
1990 1631
1991 i2c12: i2c@a90000 { 1632 i2c12: i2c@a90000 {
1992 compatible = 1633 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1634 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1635 clock-names = "se";
1995 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1637 pinctrl-names = "default";
1997 pinctrl-0 = < 1638 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1640 #address-cells = <1>;
2000 #size-cells = 1641 #size-cells = <0>;
2001 power-domains 1642 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1643 operating-points-v2 = <&qup_opp_table>;
2003 interconnects <<
2004 <<
2005 <<
2006 interconnect- <<
2007 dmas = <&gpi_ <<
2008 <&gpi_ <<
2009 dma-names = " <<
2010 status = "dis 1644 status = "disabled";
2011 }; 1645 };
2012 1646
2013 spi12: spi@a90000 { 1647 spi12: spi@a90000 {
2014 compatible = 1648 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1649 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1650 clock-names = "se";
2017 clocks = <&gc 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1652 pinctrl-names = "default";
2019 pinctrl-0 = < 1653 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1654 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1655 #address-cells = <1>;
2022 #size-cells = 1656 #size-cells = <0>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 dmas = <&gpi_ <<
2027 <&gpi_ <<
2028 dma-names = " <<
2029 status = "dis 1657 status = "disabled";
2030 }; 1658 };
2031 1659
2032 uart12: serial@a90000 1660 uart12: serial@a90000 {
2033 compatible = 1661 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1662 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1663 clock-names = "se";
2036 clocks = <&gc 1664 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1665 pinctrl-names = "default";
2038 pinctrl-0 = < 1666 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1667 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1668 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1669 operating-points-v2 = <&qup_opp_table>;
2042 interconnects <<
2043 <<
2044 interconnect- <<
2045 status = "dis 1670 status = "disabled";
2046 }; 1671 };
2047 1672
2048 i2c13: i2c@a94000 { 1673 i2c13: i2c@a94000 {
2049 compatible = 1674 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1675 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1676 clock-names = "se";
2052 clocks = <&gc 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1678 pinctrl-names = "default";
2054 pinctrl-0 = < 1679 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1680 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1681 #address-cells = <1>;
2057 #size-cells = 1682 #size-cells = <0>;
2058 power-domains 1683 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1684 operating-points-v2 = <&qup_opp_table>;
2060 interconnects <<
2061 <<
2062 <<
2063 interconnect- <<
2064 dmas = <&gpi_ <<
2065 <&gpi_ <<
2066 dma-names = " <<
2067 status = "dis 1685 status = "disabled";
2068 }; 1686 };
2069 1687
2070 spi13: spi@a94000 { 1688 spi13: spi@a94000 {
2071 compatible = 1689 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1690 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1691 clock-names = "se";
2074 clocks = <&gc 1692 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1693 pinctrl-names = "default";
2076 pinctrl-0 = < 1694 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1695 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1696 #address-cells = <1>;
2079 #size-cells = 1697 #size-cells = <0>;
2080 interconnects <<
2081 <<
2082 interconnect- <<
2083 dmas = <&gpi_ <<
2084 <&gpi_ <<
2085 dma-names = " <<
2086 status = "dis 1698 status = "disabled";
2087 }; 1699 };
2088 1700
2089 uart13: serial@a94000 1701 uart13: serial@a94000 {
2090 compatible = 1702 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 1703 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 1704 clock-names = "se";
2093 clocks = <&gc 1705 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 1706 pinctrl-names = "default";
2095 pinctrl-0 = < 1707 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 1708 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 1709 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 1710 operating-points-v2 = <&qup_opp_table>;
2099 interconnects <<
2100 <<
2101 interconnect- <<
2102 status = "dis 1711 status = "disabled";
2103 }; 1712 };
2104 1713
2105 i2c14: i2c@a98000 { 1714 i2c14: i2c@a98000 {
2106 compatible = 1715 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 1716 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 1717 clock-names = "se";
2109 clocks = <&gc 1718 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 1719 pinctrl-names = "default";
2111 pinctrl-0 = < 1720 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 1721 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 1722 #address-cells = <1>;
2114 #size-cells = 1723 #size-cells = <0>;
2115 power-domains 1724 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 1725 operating-points-v2 = <&qup_opp_table>;
2117 interconnects <<
2118 <<
2119 <<
2120 interconnect- <<
2121 dmas = <&gpi_ <<
2122 <&gpi_ <<
2123 dma-names = " <<
2124 status = "dis 1726 status = "disabled";
2125 }; 1727 };
2126 1728
2127 spi14: spi@a98000 { 1729 spi14: spi@a98000 {
2128 compatible = 1730 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 1731 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 1732 clock-names = "se";
2131 clocks = <&gc 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 1734 pinctrl-names = "default";
2133 pinctrl-0 = < 1735 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 1736 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 1737 #address-cells = <1>;
2136 #size-cells = 1738 #size-cells = <0>;
2137 interconnects <<
2138 <<
2139 interconnect- <<
2140 dmas = <&gpi_ <<
2141 <&gpi_ <<
2142 dma-names = " <<
2143 status = "dis 1739 status = "disabled";
2144 }; 1740 };
2145 1741
2146 uart14: serial@a98000 1742 uart14: serial@a98000 {
2147 compatible = 1743 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 1744 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 1745 clock-names = "se";
2150 clocks = <&gc 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 1747 pinctrl-names = "default";
2152 pinctrl-0 = < 1748 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 1749 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 1750 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 1751 operating-points-v2 = <&qup_opp_table>;
2156 interconnects <<
2157 <<
2158 interconnect- <<
2159 status = "dis 1752 status = "disabled";
2160 }; 1753 };
2161 1754
2162 i2c15: i2c@a9c000 { 1755 i2c15: i2c@a9c000 {
2163 compatible = 1756 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 1757 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 1758 clock-names = "se";
2166 clocks = <&gc 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 1760 pinctrl-names = "default";
2168 pinctrl-0 = < 1761 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 1762 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 1763 #address-cells = <1>;
2171 #size-cells = 1764 #size-cells = <0>;
2172 power-domains 1765 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 1766 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 1767 status = "disabled";
2175 interconnects <<
2176 <<
2177 <<
2178 interconnect- <<
2179 dmas = <&gpi_ <<
2180 <&gpi_ <<
2181 dma-names = " <<
2182 }; 1768 };
2183 1769
2184 spi15: spi@a9c000 { 1770 spi15: spi@a9c000 {
2185 compatible = 1771 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 1772 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 1773 clock-names = "se";
2188 clocks = <&gc 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 1775 pinctrl-names = "default";
2190 pinctrl-0 = < 1776 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 1777 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 1778 #address-cells = <1>;
2193 #size-cells = 1779 #size-cells = <0>;
2194 interconnects <<
2195 <<
2196 interconnect- <<
2197 dmas = <&gpi_ <<
2198 <&gpi_ <<
2199 dma-names = " <<
2200 status = "dis 1780 status = "disabled";
2201 }; 1781 };
2202 1782
2203 uart15: serial@a9c000 1783 uart15: serial@a9c000 {
2204 compatible = 1784 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 1785 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 1786 clock-names = "se";
2207 clocks = <&gc 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 1788 pinctrl-names = "default";
2209 pinctrl-0 = < 1789 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 1790 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 1791 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 1792 operating-points-v2 = <&qup_opp_table>;
2213 interconnects <<
2214 <<
2215 interconnect- <<
2216 status = "dis 1793 status = "disabled";
2217 }; 1794 };
2218 }; 1795 };
2219 1796
2220 llcc: system-cache-controller !! 1797 system-cache-controller@1100000 {
2221 compatible = "qcom,sd 1798 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 1799 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 1800 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 1801 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 1802 };
2229 1803
2230 dma@10a2000 { !! 1804 pcie0: pci@1c00000 {
2231 compatible = "qcom,sd !! 1805 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { <<
2274 compatible = "qcom,sd <<
2275 reg = <0 0x01436400 0 <<
2276 interrupts = <GIC_SPI <<
2277 interconnects = <&gla <<
2278 <<
2279 operating-points-v2 = <<
2280 <<
2281 cpu_bwmon_opp_table: <<
2282 compatible = <<
2283 <<
2284 /* <<
2285 * The interc <<
2286 * cpu4_opp_t <<
2287 * interconne <<
2288 * from bandw <<
2289 * (qcom,core <<
2290 * from msm-4 <<
2291 */ <<
2292 opp-0 { <<
2293 opp-p <<
2294 }; <<
2295 opp-1 { <<
2296 opp-p <<
2297 }; <<
2298 opp-2 { <<
2299 opp-p <<
2300 }; <<
2301 opp-3 { <<
2302 opp-p <<
2303 }; <<
2304 opp-4 { <<
2305 opp-p <<
2306 }; <<
2307 }; <<
2308 }; <<
2309 <<
2310 pcie0: pcie@1c00000 { <<
2311 compatible = "qcom,pc <<
2312 reg = <0 0x01c00000 0 1806 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 1807 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 1808 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 1809 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 1810 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 1811 device_type = "pci";
2319 linux,pci-domain = <0 1812 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 1813 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 1814 num-lanes = <1>;
2322 1815
2323 #address-cells = <3>; 1816 #address-cells = <3>;
2324 #size-cells = <2>; 1817 #size-cells = <2>;
2325 1818
2326 ranges = <0x01000000 !! 1819 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327 <0x02000000 !! 1820 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328 1821
2329 interrupts = <GIC_SPI 1822 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 1823 interrupt-names = "msi";
2331 #interrupt-cells = <1 1824 #interrupt-cells = <1>;
2332 interrupt-map-mask = 1825 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 !! 1826 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 !! 1827 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 !! 1828 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 !! 1829 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 1830
2338 clocks = <&gcc GCC_PC 1831 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 1832 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 1833 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 1834 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 1835 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 1836 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 1837 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 1838 clock-names = "pipe",
2346 "aux", 1839 "aux",
2347 "cfg", 1840 "cfg",
2348 "bus_ma 1841 "bus_master",
2349 "bus_sl 1842 "bus_slave",
2350 "slave_ 1843 "slave_q2a",
2351 "tbu"; 1844 "tbu";
2352 1845
>> 1846 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 1847 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 1848 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 1849 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 1850 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 1851 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 1852 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 1853 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 1854 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 1855 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 1856 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 1857 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 1858 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 1859 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 1860 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 1861 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 1862 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 1863
2370 resets = <&gcc GCC_PC 1864 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 1865 reset-names = "pci";
2372 1866
2373 power-domains = <&gcc 1867 power-domains = <&gcc PCIE_0_GDSC>;
2374 1868
2375 phys = <&pcie0_phy>; !! 1869 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 1870 phy-names = "pciephy";
2377 1871
2378 status = "disabled"; 1872 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 1873 };
2390 1874
2391 pcie0_phy: phy@1c06000 { 1875 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 1876 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 1877 reg = <0 0x01c06000 0 0x18c>;
>> 1878 #address-cells = <2>;
>> 1879 #size-cells = <2>;
>> 1880 ranges;
2394 clocks = <&gcc GCC_PC 1881 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 1882 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 1883 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 1884 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 1885 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 1886
2410 resets = <&gcc GCC_PC 1887 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 1888 reset-names = "phy";
2412 1889
2413 assigned-clocks = <&g 1890 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 1891 assigned-clock-rates = <100000000>;
2415 1892
2416 status = "disabled"; 1893 status = "disabled";
>> 1894
>> 1895 pcie0_lane: lanes@1c06200 {
>> 1896 reg = <0 0x01c06200 0 0x128>,
>> 1897 <0 0x01c06400 0 0x1fc>,
>> 1898 <0 0x01c06800 0 0x218>,
>> 1899 <0 0x01c06600 0 0x70>;
>> 1900 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1901 clock-names = "pipe0";
>> 1902
>> 1903 #phy-cells = <0>;
>> 1904 clock-output-names = "pcie_0_pipe_clk";
>> 1905 };
2417 }; 1906 };
2418 1907
2419 pcie1: pcie@1c08000 { !! 1908 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc !! 1909 compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
2421 reg = <0 0x01c08000 0 1910 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 1911 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 1912 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 1913 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 1914 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 1915 device_type = "pci";
2428 linux,pci-domain = <1 1916 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 1917 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 1918 num-lanes = <1>;
2431 1919
2432 #address-cells = <3>; 1920 #address-cells = <3>;
2433 #size-cells = <2>; 1921 #size-cells = <2>;
2434 1922
2435 ranges = <0x01000000 !! 1923 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 1924 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 1925
2438 interrupts = <GIC_SPI 1926 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 1927 interrupt-names = "msi";
2440 #interrupt-cells = <1 1928 #interrupt-cells = <1>;
2441 interrupt-map-mask = 1929 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 !! 1930 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 !! 1931 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 !! 1932 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 !! 1933 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 1934
2447 clocks = <&gcc GCC_PC 1935 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 1936 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 1937 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 1938 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 1939 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 1940 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 1941 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 1942 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 1943 clock-names = "pipe",
2456 "aux", 1944 "aux",
2457 "cfg", 1945 "cfg",
2458 "bus_ma 1946 "bus_master",
2459 "bus_sl 1947 "bus_slave",
2460 "slave_ 1948 "slave_q2a",
2461 "ref", 1949 "ref",
2462 "tbu"; 1950 "tbu";
2463 1951
2464 assigned-clocks = <&g 1952 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 1953 assigned-clock-rates = <19200000>;
2466 1954
>> 1955 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 1956 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 1957 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 1958 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 1959 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 1960 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 1961 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 1962 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 1963 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 1964 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 1965 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 1966 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 1967 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 1968 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 1969 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 1970 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 1971 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 1972
2484 resets = <&gcc GCC_PC 1973 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 1974 reset-names = "pci";
2486 1975
2487 power-domains = <&gcc 1976 power-domains = <&gcc PCIE_1_GDSC>;
2488 1977
2489 phys = <&pcie1_phy>; !! 1978 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 1979 phy-names = "pciephy";
2491 1980
2492 status = "disabled"; 1981 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 1982 };
2504 1983
2505 pcie1_phy: phy@1c0a000 { 1984 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 1985 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 1986 reg = <0 0x01c0a000 0 0x800>;
>> 1987 #address-cells = <2>;
>> 1988 #size-cells = <2>;
>> 1989 ranges;
2508 clocks = <&gcc GCC_PC 1990 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 1991 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 1992 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 1993 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 1994 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 1995
2524 resets = <&gcc GCC_PC 1996 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 1997 reset-names = "phy";
2526 1998
2527 assigned-clocks = <&g 1999 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2000 assigned-clock-rates = <100000000>;
2529 2001
2530 status = "disabled"; 2002 status = "disabled";
>> 2003
>> 2004 pcie1_lane: lanes@1c06200 {
>> 2005 reg = <0 0x01c0a800 0 0x800>,
>> 2006 <0 0x01c0a800 0 0x800>,
>> 2007 <0 0x01c0b800 0 0x400>;
>> 2008 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2009 clock-names = "pipe0";
>> 2010
>> 2011 #phy-cells = <0>;
>> 2012 clock-output-names = "pcie_1_pipe_clk";
>> 2013 };
2531 }; 2014 };
2532 2015
2533 mem_noc: interconnect@1380000 2016 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2017 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2018 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = !! 2019 #interconnect-cells = <1>;
2537 qcom,bcm-voters = <&a 2020 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2021 };
2539 2022
2540 dc_noc: interconnect@14e0000 2023 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2024 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2025 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = !! 2026 #interconnect-cells = <1>;
2544 qcom,bcm-voters = <&a 2027 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2028 };
2546 2029
2547 config_noc: interconnect@1500 2030 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2031 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2032 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = !! 2033 #interconnect-cells = <1>;
2551 qcom,bcm-voters = <&a 2034 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2035 };
2553 2036
2554 system_noc: interconnect@1620 2037 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2038 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2039 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = !! 2040 #interconnect-cells = <1>;
2558 qcom,bcm-voters = <&a 2041 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2042 };
2560 2043
2561 aggre1_noc: interconnect@16e0 2044 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2045 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2046 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = !! 2047 #interconnect-cells = <1>;
2565 qcom,bcm-voters = <&a 2048 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2049 };
2567 2050
2568 aggre2_noc: interconnect@1700 2051 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2052 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2053 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = !! 2054 #interconnect-cells = <1>;
2572 qcom,bcm-voters = <&a 2055 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2056 };
2574 2057
2575 mmss_noc: interconnect@174000 2058 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2059 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2060 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = !! 2061 #interconnect-cells = <1>;
2579 qcom,bcm-voters = <&a 2062 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2063 };
2581 2064
2582 ufs_mem_hc: ufshc@1d84000 { 2065 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2066 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2067 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2068 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2069 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2070 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2071 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2072 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2073 phy-names = "ufsphy";
2591 lanes-per-direction = 2074 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2075 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2076 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2077 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2078 reset-names = "rst";
2596 2079
2597 iommus = <&apps_smmu 2080 iommus = <&apps_smmu 0x100 0xf>;
2598 2081
2599 clock-names = 2082 clock-names =
2600 "core_clk", 2083 "core_clk",
2601 "bus_aggr_clk 2084 "bus_aggr_clk",
2602 "iface_clk", 2085 "iface_clk",
2603 "core_clk_uni 2086 "core_clk_unipro",
2604 "ref_clk", 2087 "ref_clk",
2605 "tx_lane0_syn 2088 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2089 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2090 "rx_lane1_sync_clk",
2608 "ice_core_clk 2091 "ice_core_clk";
2609 clocks = 2092 clocks =
2610 <&gcc GCC_UFS 2093 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2094 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2095 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2096 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2097 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2098 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2100 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2101 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2102 freq-table-hz =
2620 operating-points-v2 = !! 2103 <50000000 200000000>,
2621 !! 2104 <0 0>,
2622 interconnects = <&agg !! 2105 <0 0>,
2623 <&gla !! 2106 <37500000 150000000>,
2624 interconnect-names = !! 2107 <0 0>,
>> 2108 <0 0>,
>> 2109 <0 0>,
>> 2110 <0 0>,
>> 2111 <0 300000000>;
2625 2112
2626 status = "disabled"; 2113 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2114 };
2658 2115
2659 ufs_mem_phy: phy@1d87000 { 2116 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2117 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2118 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2119 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2120 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2121 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2122 clock-names = "ref",
2667 "ref_au !! 2123 "ref_aux";
2668 "qref"; !! 2124 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2125 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2126
2672 resets = <&ufs_mem_hc 2127 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2128 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2129 status = "disabled";
2677 }; <<
2678 2130
2679 cryptobam: dma-controller@1dc !! 2131 ufs_mem_phy_lanes: lanes@1d87400 {
2680 compatible = "qcom,ba !! 2132 reg = <0 0x01d87400 0 0x108>,
2681 reg = <0 0x01dc4000 0 !! 2133 <0 0x01d87600 0 0x1e0>,
2682 interrupts = <GIC_SPI !! 2134 <0 0x01d87c00 0 0x1dc>,
2683 clocks = <&rpmhcc RPM !! 2135 <0 0x01d87800 0 0x108>,
2684 clock-names = "bam_cl !! 2136 <0 0x01d87a00 0 0x1e0>;
2685 #dma-cells = <1>; !! 2137 #phy-cells = <0>;
2686 qcom,ee = <0>; !! 2138 };
2687 qcom,controlled-remot <<
2688 iommus = <&apps_smmu <<
2689 <&apps_smmu <<
2690 <&apps_smmu <<
2691 <&apps_smmu <<
2692 }; <<
2693 <<
2694 crypto: crypto@1dfa000 { <<
2695 compatible = "qcom,cr <<
2696 reg = <0 0x01dfa000 0 <<
2697 clocks = <&gcc GCC_CE <<
2698 <&gcc GCC_CE <<
2699 <&rpmhcc RPM <<
2700 clock-names = "iface" <<
2701 dmas = <&cryptobam 6> <<
2702 dma-names = "rx", "tx <<
2703 iommus = <&apps_smmu <<
2704 <&apps_smmu <<
2705 <&apps_smmu <<
2706 <&apps_smmu <<
2707 }; 2139 };
2708 2140
2709 ipa: ipa@1e40000 { 2141 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2142 compatible = "qcom,sdm845-ipa";
2711 2143
2712 iommus = <&apps_smmu !! 2144 iommus = <&apps_smmu 0x720 0x3>;
2713 <&apps_smmu !! 2145 reg = <0 0x1e40000 0 0x7000>,
2714 reg = <0 0x01e40000 0 !! 2146 <0 0x1e47000 0 0x2000>,
2715 <0 0x01e47000 0 !! 2147 <0 0x1e04000 0 0x2c000>;
2716 <0 0x01e04000 0 <<
2717 reg-names = "ipa-reg" 2148 reg-names = "ipa-reg",
2718 "ipa-shar 2149 "ipa-shared",
2719 "gsi"; 2150 "gsi";
2720 2151
2721 interrupts-extended = !! 2152 interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
2722 !! 2153 <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2154 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2155 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2156 interrupt-names = "ipa",
2726 "gs 2157 "gsi",
2727 "ip 2158 "ipa-clock-query",
2728 "ip 2159 "ipa-setup-ready";
2729 2160
2730 clocks = <&rpmhcc RPM 2161 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2162 clock-names = "core";
2732 2163
2733 interconnects = <&agg !! 2164 interconnects = <&aggre2_noc MASTER_IPA &mem_noc SLAVE_EBI1>,
2734 <&agg !! 2165 <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>,
2735 <&gla !! 2166 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
2736 interconnect-names = 2167 interconnect-names = "memory",
2737 2168 "imem",
2738 2169 "config";
2739 2170
2740 qcom,smem-states = <& 2171 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2172 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2173 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2174 "ipa-clock-enabled";
2744 2175
2745 status = "disabled"; !! 2176 modem-remoteproc = <&mss_pil>;
2746 }; <<
2747 2177
2748 tcsr_mutex: hwlock@1f40000 { !! 2178 status = "disabled";
2749 compatible = "qcom,tc <<
2750 reg = <0 0x01f40000 0 <<
2751 #hwlock-cells = <1>; <<
2752 }; 2179 };
2753 2180
2754 tcsr_regs_1: syscon@1f60000 { !! 2181 tcsr_mutex_regs: syscon@1f40000 {
2755 compatible = "qcom,sd !! 2182 compatible = "syscon";
2756 reg = <0 0x01f60000 0 !! 2183 reg = <0 0x01f40000 0 0x40000>;
2757 }; 2184 };
2758 2185
2759 tlmm: pinctrl@3400000 { 2186 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2187 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2188 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2189 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2190 gpio-controller;
2764 #gpio-cells = <2>; 2191 #gpio-cells = <2>;
2765 interrupt-controller; 2192 interrupt-controller;
2766 #interrupt-cells = <2 2193 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm !! 2194 gpio-ranges = <&tlmm 0 0 150>;
2768 wakeup-parent = <&pdc 2195 wakeup-parent = <&pdc_intc>;
2769 2196
2770 cci0_default: cci0-de !! 2197 cci0_default: cci0-default {
2771 /* SDA, SCL * 2198 /* SDA, SCL */
2772 pins = "gpio1 2199 pins = "gpio17", "gpio18";
2773 function = "c 2200 function = "cci_i2c";
2774 2201
2775 bias-pull-up; 2202 bias-pull-up;
2776 drive-strengt 2203 drive-strength = <2>; /* 2 mA */
2777 }; 2204 };
2778 2205
2779 cci0_sleep: cci0-slee !! 2206 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2207 /* SDA, SCL */
2781 pins = "gpio1 2208 pins = "gpio17", "gpio18";
2782 function = "c 2209 function = "cci_i2c";
2783 2210
2784 drive-strengt 2211 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2212 bias-pull-down;
2786 }; 2213 };
2787 2214
2788 cci1_default: cci1-de !! 2215 cci1_default: cci1-default {
2789 /* SDA, SCL * 2216 /* SDA, SCL */
2790 pins = "gpio1 2217 pins = "gpio19", "gpio20";
2791 function = "c 2218 function = "cci_i2c";
2792 2219
2793 bias-pull-up; 2220 bias-pull-up;
2794 drive-strengt 2221 drive-strength = <2>; /* 2 mA */
2795 }; 2222 };
2796 2223
2797 cci1_sleep: cci1-slee !! 2224 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2225 /* SDA, SCL */
2799 pins = "gpio1 2226 pins = "gpio19", "gpio20";
2800 function = "c 2227 function = "cci_i2c";
2801 2228
2802 drive-strengt 2229 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2230 bias-pull-down;
2804 }; 2231 };
2805 2232
2806 qspi_clk: qspi-clk-st !! 2233 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2234 pinmux {
2808 function = "q !! 2235 pins = "gpio95";
2809 }; !! 2236 function = "qspi_clk";
2810 !! 2237 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; <<
2815 <<
2816 qspi_cs1: qspi-cs1-st <<
2817 pins = "gpio8 <<
2818 function = "q <<
2819 }; 2238 };
2820 2239
2821 qspi_data0: qspi-data !! 2240 qspi_cs0: qspi-cs0 {
2822 pins = "gpio9 !! 2241 pinmux {
2823 function = "q !! 2242 pins = "gpio90";
>> 2243 function = "qspi_cs";
>> 2244 };
2824 }; 2245 };
2825 2246
2826 qspi_data1: qspi-data !! 2247 qspi_cs1: qspi-cs1 {
2827 pins = "gpio9 !! 2248 pinmux {
2828 function = "q !! 2249 pins = "gpio89";
>> 2250 function = "qspi_cs";
>> 2251 };
2829 }; 2252 };
2830 2253
2831 qspi_data23: qspi-dat !! 2254 qspi_data01: qspi-data01 {
2832 pins = "gpio9 !! 2255 pinmux-data {
2833 function = "q !! 2256 pins = "gpio91", "gpio92";
>> 2257 function = "qspi_data";
>> 2258 };
2834 }; 2259 };
2835 2260
2836 qup_i2c0_default: qup !! 2261 qspi_data12: qspi-data12 {
2837 pins = "gpio0 !! 2262 pinmux-data {
2838 function = "q !! 2263 pins = "gpio93", "gpio94";
>> 2264 function = "qspi_data";
>> 2265 };
2839 }; 2266 };
2840 2267
2841 qup_i2c1_default: qup !! 2268 qup_i2c0_default: qup-i2c0-default {
2842 pins = "gpio1 !! 2269 pinmux {
2843 function = "q !! 2270 pins = "gpio0", "gpio1";
>> 2271 function = "qup0";
>> 2272 };
2844 }; 2273 };
2845 2274
2846 qup_i2c2_default: qup !! 2275 qup_i2c1_default: qup-i2c1-default {
2847 pins = "gpio2 !! 2276 pinmux {
2848 function = "q !! 2277 pins = "gpio17", "gpio18";
>> 2278 function = "qup1";
>> 2279 };
2849 }; 2280 };
2850 2281
2851 qup_i2c3_default: qup !! 2282 qup_i2c2_default: qup-i2c2-default {
2852 pins = "gpio4 !! 2283 pinmux {
2853 function = "q !! 2284 pins = "gpio27", "gpio28";
>> 2285 function = "qup2";
>> 2286 };
2854 }; 2287 };
2855 2288
2856 qup_i2c4_default: qup !! 2289 qup_i2c3_default: qup-i2c3-default {
2857 pins = "gpio8 !! 2290 pinmux {
2858 function = "q !! 2291 pins = "gpio41", "gpio42";
>> 2292 function = "qup3";
>> 2293 };
2859 }; 2294 };
2860 2295
2861 qup_i2c5_default: qup !! 2296 qup_i2c4_default: qup-i2c4-default {
2862 pins = "gpio8 !! 2297 pinmux {
2863 function = "q !! 2298 pins = "gpio89", "gpio90";
>> 2299 function = "qup4";
>> 2300 };
2864 }; 2301 };
2865 2302
2866 qup_i2c6_default: qup !! 2303 qup_i2c5_default: qup-i2c5-default {
2867 pins = "gpio4 !! 2304 pinmux {
2868 function = "q !! 2305 pins = "gpio85", "gpio86";
>> 2306 function = "qup5";
>> 2307 };
2869 }; 2308 };
2870 2309
2871 qup_i2c7_default: qup !! 2310 qup_i2c6_default: qup-i2c6-default {
2872 pins = "gpio9 !! 2311 pinmux {
2873 function = "q !! 2312 pins = "gpio45", "gpio46";
>> 2313 function = "qup6";
>> 2314 };
2874 }; 2315 };
2875 2316
2876 qup_i2c8_default: qup !! 2317 qup_i2c7_default: qup-i2c7-default {
2877 pins = "gpio6 !! 2318 pinmux {
2878 function = "q !! 2319 pins = "gpio93", "gpio94";
>> 2320 function = "qup7";
>> 2321 };
2879 }; 2322 };
2880 2323
2881 qup_i2c9_default: qup !! 2324 qup_i2c8_default: qup-i2c8-default {
2882 pins = "gpio6 !! 2325 pinmux {
2883 function = "q !! 2326 pins = "gpio65", "gpio66";
>> 2327 function = "qup8";
>> 2328 };
2884 }; 2329 };
2885 2330
2886 qup_i2c10_default: qu !! 2331 qup_i2c9_default: qup-i2c9-default {
2887 pins = "gpio5 !! 2332 pinmux {
2888 function = "q !! 2333 pins = "gpio6", "gpio7";
>> 2334 function = "qup9";
>> 2335 };
2889 }; 2336 };
2890 2337
2891 qup_i2c11_default: qu !! 2338 qup_i2c10_default: qup-i2c10-default {
2892 pins = "gpio3 !! 2339 pinmux {
2893 function = "q !! 2340 pins = "gpio55", "gpio56";
>> 2341 function = "qup10";
>> 2342 };
2894 }; 2343 };
2895 2344
2896 qup_i2c12_default: qu !! 2345 qup_i2c11_default: qup-i2c11-default {
2897 pins = "gpio4 !! 2346 pinmux {
2898 function = "q !! 2347 pins = "gpio31", "gpio32";
>> 2348 function = "qup11";
>> 2349 };
2899 }; 2350 };
2900 2351
2901 qup_i2c13_default: qu !! 2352 qup_i2c12_default: qup-i2c12-default {
2902 pins = "gpio1 !! 2353 pinmux {
2903 function = "q !! 2354 pins = "gpio49", "gpio50";
>> 2355 function = "qup12";
>> 2356 };
2904 }; 2357 };
2905 2358
2906 qup_i2c14_default: qu !! 2359 qup_i2c13_default: qup-i2c13-default {
2907 pins = "gpio3 !! 2360 pinmux {
2908 function = "q !! 2361 pins = "gpio105", "gpio106";
>> 2362 function = "qup13";
>> 2363 };
2909 }; 2364 };
2910 2365
2911 qup_i2c15_default: qu !! 2366 qup_i2c14_default: qup-i2c14-default {
2912 pins = "gpio8 !! 2367 pinmux {
2913 function = "q !! 2368 pins = "gpio33", "gpio34";
>> 2369 function = "qup14";
>> 2370 };
2914 }; 2371 };
2915 2372
2916 qup_spi0_default: qup !! 2373 qup_i2c15_default: qup-i2c15-default {
2917 pins = "gpio0 !! 2374 pinmux {
2918 function = "q !! 2375 pins = "gpio81", "gpio82";
>> 2376 function = "qup15";
>> 2377 };
2919 }; 2378 };
2920 2379
2921 qup_spi1_default: qup !! 2380 qup_spi0_default: qup-spi0-default {
2922 pins = "gpio1 !! 2381 pinmux {
2923 function = "q !! 2382 pins = "gpio0", "gpio1",
>> 2383 "gpio2", "gpio3";
>> 2384 function = "qup0";
>> 2385 };
2924 }; 2386 };
2925 2387
2926 qup_spi2_default: qup !! 2388 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2389 pinmux {
2928 function = "q !! 2390 pins = "gpio17", "gpio18",
>> 2391 "gpio19", "gpio20";
>> 2392 function = "qup1";
>> 2393 };
2929 }; 2394 };
2930 2395
2931 qup_spi3_default: qup !! 2396 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2397 pinmux {
2933 function = "q !! 2398 pins = "gpio27", "gpio28",
>> 2399 "gpio29", "gpio30";
>> 2400 function = "qup2";
>> 2401 };
2934 }; 2402 };
2935 2403
2936 qup_spi4_default: qup !! 2404 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2405 pinmux {
2938 function = "q !! 2406 pins = "gpio41", "gpio42",
>> 2407 "gpio43", "gpio44";
>> 2408 function = "qup3";
>> 2409 };
2939 }; 2410 };
2940 2411
2941 qup_spi5_default: qup !! 2412 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2413 pinmux {
2943 function = "q !! 2414 pins = "gpio89", "gpio90",
>> 2415 "gpio91", "gpio92";
>> 2416 function = "qup4";
>> 2417 };
2944 }; 2418 };
2945 2419
2946 qup_spi6_default: qup !! 2420 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2421 pinmux {
2948 function = "q !! 2422 pins = "gpio85", "gpio86",
>> 2423 "gpio87", "gpio88";
>> 2424 function = "qup5";
>> 2425 };
2949 }; 2426 };
2950 2427
2951 qup_spi7_default: qup !! 2428 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2429 pinmux {
2953 function = "q !! 2430 pins = "gpio45", "gpio46",
>> 2431 "gpio47", "gpio48";
>> 2432 function = "qup6";
>> 2433 };
2954 }; 2434 };
2955 2435
2956 qup_spi8_default: qup !! 2436 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2437 pinmux {
2958 function = "q !! 2438 pins = "gpio93", "gpio94",
>> 2439 "gpio95", "gpio96";
>> 2440 function = "qup7";
>> 2441 };
2959 }; 2442 };
2960 2443
2961 qup_spi9_default: qup !! 2444 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2445 pinmux {
2963 function = "q !! 2446 pins = "gpio65", "gpio66",
>> 2447 "gpio67", "gpio68";
>> 2448 function = "qup8";
>> 2449 };
2964 }; 2450 };
2965 2451
2966 qup_spi10_default: qu !! 2452 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2453 pinmux {
2968 function = "q !! 2454 pins = "gpio6", "gpio7",
>> 2455 "gpio4", "gpio5";
>> 2456 function = "qup9";
>> 2457 };
2969 }; 2458 };
2970 2459
2971 qup_spi11_default: qu !! 2460 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2461 pinmux {
2973 function = "q !! 2462 pins = "gpio55", "gpio56",
>> 2463 "gpio53", "gpio54";
>> 2464 function = "qup10";
>> 2465 };
2974 }; 2466 };
2975 2467
2976 qup_spi12_default: qu !! 2468 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2469 pinmux {
2978 function = "q !! 2470 pins = "gpio31", "gpio32",
>> 2471 "gpio33", "gpio34";
>> 2472 function = "qup11";
>> 2473 };
2979 }; 2474 };
2980 2475
2981 qup_spi13_default: qu !! 2476 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2477 pinmux {
2983 function = "q !! 2478 pins = "gpio49", "gpio50",
>> 2479 "gpio51", "gpio52";
>> 2480 function = "qup12";
>> 2481 };
2984 }; 2482 };
2985 2483
2986 qup_spi14_default: qu !! 2484 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2485 pinmux {
2988 function = "q !! 2486 pins = "gpio105", "gpio106",
>> 2487 "gpio107", "gpio108";
>> 2488 function = "qup13";
>> 2489 };
2989 }; 2490 };
2990 2491
2991 qup_spi15_default: qu !! 2492 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2493 pinmux {
2993 function = "q !! 2494 pins = "gpio33", "gpio34",
>> 2495 "gpio31", "gpio32";
>> 2496 function = "qup14";
>> 2497 };
2994 }; 2498 };
2995 2499
2996 qup_uart0_default: qu !! 2500 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2501 pinmux {
2998 pins !! 2502 pins = "gpio81", "gpio82",
2999 funct !! 2503 "gpio83", "gpio84";
>> 2504 function = "qup15";
3000 }; 2505 };
>> 2506 };
3001 2507
3002 qup_uart0_rx: !! 2508 qup_uart0_default: qup-uart0-default {
3003 pins !! 2509 pinmux {
>> 2510 pins = "gpio2", "gpio3";
3004 funct 2511 function = "qup0";
3005 }; 2512 };
3006 }; 2513 };
3007 2514
3008 qup_uart1_default: qu !! 2515 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2516 pinmux {
3010 pins !! 2517 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2518 function = "qup1";
3017 }; 2519 };
3018 }; 2520 };
3019 2521
3020 qup_uart2_default: qu !! 2522 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2523 pinmux {
3022 pins !! 2524 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2525 function = "qup2";
3029 }; 2526 };
3030 }; 2527 };
3031 2528
3032 qup_uart3_default: qu !! 2529 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2530 pinmux {
3034 pins !! 2531 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2532 function = "qup3";
3041 }; 2533 };
3042 }; 2534 };
3043 2535
3044 qup_uart3_4pin: qup-u !! 2536 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2537 pinmux {
3046 pins !! 2538 pins = "gpio91", "gpio92";
3047 funct !! 2539 function = "qup4";
3048 }; 2540 };
>> 2541 };
3049 2542
3050 qup_uart3_4pi !! 2543 qup_uart5_default: qup-uart5-default {
3051 pins !! 2544 pinmux {
3052 funct !! 2545 pins = "gpio87", "gpio88";
>> 2546 function = "qup5";
3053 }; 2547 };
>> 2548 };
3054 2549
3055 qup_uart3_4pi !! 2550 qup_uart6_default: qup-uart6-default {
3056 pins !! 2551 pinmux {
3057 funct !! 2552 pins = "gpio47", "gpio48";
>> 2553 function = "qup6";
3058 }; 2554 };
3059 }; 2555 };
3060 2556
3061 qup_uart4_default: qu !! 2557 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 2558 pinmux {
3063 pins !! 2559 pins = "gpio95", "gpio96";
3064 funct !! 2560 function = "qup7";
3065 }; 2561 };
>> 2562 };
3066 2563
3067 qup_uart4_rx: !! 2564 qup_uart8_default: qup-uart8-default {
3068 pins !! 2565 pinmux {
3069 funct !! 2566 pins = "gpio67", "gpio68";
>> 2567 function = "qup8";
3070 }; 2568 };
3071 }; 2569 };
3072 2570
3073 qup_uart5_default: qu !! 2571 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 2572 pinmux {
3075 pins !! 2573 pins = "gpio4", "gpio5";
3076 funct !! 2574 function = "qup9";
3077 }; 2575 };
>> 2576 };
3078 2577
3079 qup_uart5_rx: !! 2578 qup_uart10_default: qup-uart10-default {
3080 pins !! 2579 pinmux {
3081 funct !! 2580 pins = "gpio53", "gpio54";
>> 2581 function = "qup10";
3082 }; 2582 };
3083 }; 2583 };
3084 2584
3085 qup_uart6_default: qu !! 2585 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 2586 pinmux {
3087 pins !! 2587 pins = "gpio33", "gpio34";
3088 funct !! 2588 function = "qup11";
3089 }; 2589 };
>> 2590 };
3090 2591
3091 qup_uart6_rx: !! 2592 qup_uart12_default: qup-uart12-default {
3092 pins !! 2593 pinmux {
3093 funct !! 2594 pins = "gpio51", "gpio52";
>> 2595 function = "qup12";
3094 }; 2596 };
3095 }; 2597 };
3096 2598
3097 qup_uart6_4pin: qup-u !! 2599 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 2600 pinmux {
3099 pins !! 2601 pins = "gpio107", "gpio108";
3100 funct !! 2602 function = "qup13";
3101 bias- <<
3102 }; 2603 };
>> 2604 };
3103 2605
3104 qup_uart6_4pi !! 2606 qup_uart14_default: qup-uart14-default {
3105 pins !! 2607 pinmux {
3106 funct !! 2608 pins = "gpio31", "gpio32";
3107 drive !! 2609 function = "qup14";
3108 bias- <<
3109 }; 2610 };
>> 2611 };
3110 2612
3111 qup_uart6_4pi !! 2613 qup_uart15_default: qup-uart15-default {
3112 pins !! 2614 pinmux {
3113 funct !! 2615 pins = "gpio83", "gpio84";
3114 bias- !! 2616 function = "qup15";
3115 }; 2617 };
3116 }; 2618 };
3117 2619
3118 qup_uart7_default: qu !! 2620 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 2621 mux {
3120 pins !! 2622 pins = "gpio58", "gpio59";
3121 funct !! 2623 function = "gpio";
3122 }; 2624 };
3123 2625
3124 qup_uart7_rx: !! 2626 config {
3125 pins !! 2627 pins = "gpio58", "gpio59";
3126 funct !! 2628 drive-strength = <2>;
>> 2629 bias-pull-down;
>> 2630 input-enable;
3127 }; 2631 };
3128 }; 2632 };
3129 2633
3130 qup_uart8_default: qu !! 2634 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 2635 mux {
3132 pins !! 2636 pins = "gpio58", "gpio59";
3133 funct !! 2637 function = "qua_mi2s";
3134 }; 2638 };
3135 2639
3136 qup_uart8_rx: !! 2640 config {
3137 pins !! 2641 pins = "gpio58", "gpio59";
3138 funct !! 2642 drive-strength = <8>;
>> 2643 bias-disable;
>> 2644 output-high;
3139 }; 2645 };
3140 }; 2646 };
3141 2647
3142 qup_uart9_default: qu !! 2648 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 2649 mux {
3144 pins !! 2650 pins = "gpio60";
3145 funct !! 2651 function = "gpio";
3146 }; 2652 };
3147 2653
3148 qup_uart9_rx: !! 2654 config {
3149 pins !! 2655 pins = "gpio60";
3150 funct !! 2656 drive-strength = <2>;
>> 2657 bias-pull-down;
>> 2658 input-enable;
3151 }; 2659 };
3152 }; 2660 };
3153 2661
3154 qup_uart10_default: q !! 2662 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 2663 mux {
3156 pins !! 2664 pins = "gpio60";
3157 funct !! 2665 function = "qua_mi2s";
3158 }; 2666 };
3159 2667
3160 qup_uart10_rx !! 2668 config {
3161 pins !! 2669 pins = "gpio60";
3162 funct !! 2670 drive-strength = <8>;
>> 2671 bias-disable;
3163 }; 2672 };
3164 }; 2673 };
3165 2674
3166 qup_uart11_default: q !! 2675 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 2676 mux {
3168 pins !! 2677 pins = "gpio61";
3169 funct !! 2678 function = "gpio";
3170 }; 2679 };
3171 2680
3172 qup_uart11_rx !! 2681 config {
3173 pins !! 2682 pins = "gpio61";
3174 funct !! 2683 drive-strength = <2>;
>> 2684 bias-pull-down;
>> 2685 input-enable;
3175 }; 2686 };
3176 }; 2687 };
3177 2688
3178 qup_uart12_default: q !! 2689 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 2690 mux {
3180 pins !! 2691 pins = "gpio61";
3181 funct !! 2692 function = "qua_mi2s";
3182 }; 2693 };
3183 2694
3184 qup_uart12_rx !! 2695 config {
3185 pins !! 2696 pins = "gpio61";
3186 funct !! 2697 drive-strength = <8>;
>> 2698 bias-disable;
3187 }; 2699 };
3188 }; 2700 };
3189 2701
3190 qup_uart13_default: q !! 2702 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 2703 mux {
3192 pins !! 2704 pins = "gpio62";
3193 funct !! 2705 function = "gpio";
3194 }; 2706 };
3195 2707
3196 qup_uart13_rx !! 2708 config {
3197 pins !! 2709 pins = "gpio62";
3198 funct !! 2710 drive-strength = <2>;
>> 2711 bias-pull-down;
>> 2712 input-enable;
3199 }; 2713 };
3200 }; 2714 };
3201 2715
3202 qup_uart14_default: q !! 2716 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 2717 mux {
3204 pins !! 2718 pins = "gpio62";
3205 funct !! 2719 function = "qua_mi2s";
3206 }; 2720 };
3207 2721
3208 qup_uart14_rx !! 2722 config {
3209 pins !! 2723 pins = "gpio62";
3210 funct !! 2724 drive-strength = <8>;
>> 2725 bias-disable;
3211 }; 2726 };
3212 }; 2727 };
3213 2728
3214 qup_uart15_default: q !! 2729 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 2730 mux {
3216 pins !! 2731 pins = "gpio63";
3217 funct !! 2732 function = "gpio";
3218 }; 2733 };
3219 2734
3220 qup_uart15_rx !! 2735 config {
3221 pins !! 2736 pins = "gpio63";
3222 funct !! 2737 drive-strength = <2>;
>> 2738 bias-pull-down;
>> 2739 input-enable;
3223 }; 2740 };
3224 }; 2741 };
3225 2742
3226 quat_mi2s_sleep: quat !! 2743 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 2744 mux {
3228 function = "g !! 2745 pins = "gpio63";
3229 drive-strengt !! 2746 function = "qua_mi2s";
3230 bias-pull-dow !! 2747 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 2748
3290 quat_mi2s_sd3_active: !! 2749 config {
3291 pins = "gpio6 !! 2750 pins = "gpio63";
3292 function = "q !! 2751 drive-strength = <8>;
3293 drive-strengt !! 2752 bias-disable;
3294 bias-disable; !! 2753 };
3295 }; 2754 };
3296 }; 2755 };
3297 2756
3298 mss_pil: remoteproc@4080000 { 2757 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 2758 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 2759 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 2760 reg-names = "qdsp6", "rmb";
3302 2761
3303 interrupts-extended = 2762 interrupts-extended =
3304 <&intc GIC_SP 2763 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 2764 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 2765 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 2766 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 2767 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 2768 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 2769 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 2770 "handover", "stop-ack",
3312 "sh 2771 "shutdown-ack";
3313 2772
3314 clocks = <&gcc GCC_MS 2773 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 2774 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 2775 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 2776 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 2777 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 2778 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 2779 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 2780 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 2781 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 2782 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 2783
3325 qcom,qmp = <&aoss_qmp <<
3326 <<
3327 qcom,smem-states = <& 2784 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 2785 qcom,smem-state-names = "stop";
3329 2786
3330 resets = <&aoss_reset 2787 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 2788 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 2789 reset-names = "mss_restart", "pdc_reset";
3333 2790
3334 qcom,halt-regs = <&tc !! 2791 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 2792
3336 power-domains = <&rpm !! 2793 power-domains = <&aoss_qmp 2>,
>> 2794 <&rpmhpd SDM845_CX>,
3337 <&rpm 2795 <&rpmhpd SDM845_MX>,
3338 <&rpm 2796 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = !! 2797 power-domain-names = "load_state", "cx", "mx", "mss";
3340 <<
3341 status = "disabled"; <<
3342 2798
3343 mba { 2799 mba {
3344 memory-region 2800 memory-region = <&mba_region>;
3345 }; 2801 };
3346 2802
3347 mpss { 2803 mpss {
3348 memory-region 2804 memory-region = <&mpss_region>;
3349 }; 2805 };
3350 2806
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 2807 glink-edge {
3356 interrupts = 2808 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 2809 label = "modem";
3358 qcom,remote-p 2810 qcom,remote-pid = <1>;
3359 mboxes = <&ap 2811 mboxes = <&apss_shared 12>;
3360 }; 2812 };
3361 }; 2813 };
3362 2814
3363 gpucc: clock-controller@50900 2815 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 2816 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 2817 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 2818 #clock-cells = <1>;
3367 #reset-cells = <1>; 2819 #reset-cells = <1>;
3368 #power-domain-cells = 2820 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 2821 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 2822 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 2823 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 2824 clock-names = "bi_tcxo",
3373 "gcc_gp 2825 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 2826 "gcc_gpu_gpll0_div_clk_src";
3375 }; 2827 };
3376 2828
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 2829 stm@6002000 {
3431 compatible = "arm,cor 2830 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 2831 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 2832 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 2833 reg-names = "stm-base", "stm-stimulus-base";
3435 2834
3436 clocks = <&aoss_qmp>; 2835 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 2836 clock-names = "apb_pclk";
3438 2837
3439 out-ports { 2838 out-ports {
3440 port { 2839 port {
3441 stm_o 2840 stm_out: endpoint {
3442 2841 remote-endpoint =
3443 2842 <&funnel0_in7>;
3444 }; 2843 };
3445 }; 2844 };
3446 }; 2845 };
3447 }; 2846 };
3448 2847
3449 funnel@6041000 { 2848 funnel@6041000 {
3450 compatible = "arm,cor 2849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 2850 reg = <0 0x06041000 0 0x1000>;
3452 2851
3453 clocks = <&aoss_qmp>; 2852 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 2853 clock-names = "apb_pclk";
3455 2854
3456 out-ports { 2855 out-ports {
3457 port { 2856 port {
3458 funne 2857 funnel0_out: endpoint {
3459 2858 remote-endpoint =
3460 2859 <&merge_funnel_in0>;
3461 }; 2860 };
3462 }; 2861 };
3463 }; 2862 };
3464 2863
3465 in-ports { 2864 in-ports {
3466 #address-cell 2865 #address-cells = <1>;
3467 #size-cells = 2866 #size-cells = <0>;
3468 2867
3469 port@7 { 2868 port@7 {
3470 reg = 2869 reg = <7>;
3471 funne 2870 funnel0_in7: endpoint {
3472 2871 remote-endpoint = <&stm_out>;
3473 }; 2872 };
3474 }; 2873 };
3475 }; 2874 };
3476 }; 2875 };
3477 2876
3478 funnel@6043000 { 2877 funnel@6043000 {
3479 compatible = "arm,cor 2878 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 2879 reg = <0 0x06043000 0 0x1000>;
3481 2880
3482 clocks = <&aoss_qmp>; 2881 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 2882 clock-names = "apb_pclk";
3484 2883
3485 out-ports { 2884 out-ports {
3486 port { 2885 port {
3487 funne 2886 funnel2_out: endpoint {
3488 2887 remote-endpoint =
3489 2888 <&merge_funnel_in2>;
3490 }; 2889 };
3491 }; 2890 };
3492 }; 2891 };
3493 2892
3494 in-ports { 2893 in-ports {
3495 #address-cell 2894 #address-cells = <1>;
3496 #size-cells = 2895 #size-cells = <0>;
3497 2896
3498 port@5 { 2897 port@5 {
3499 reg = 2898 reg = <5>;
3500 funne 2899 funnel2_in5: endpoint {
3501 2900 remote-endpoint =
3502 2901 <&apss_merge_funnel_out>;
3503 }; 2902 };
3504 }; 2903 };
3505 }; 2904 };
3506 }; 2905 };
3507 2906
3508 funnel@6045000 { 2907 funnel@6045000 {
3509 compatible = "arm,cor 2908 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 2909 reg = <0 0x06045000 0 0x1000>;
3511 2910
3512 clocks = <&aoss_qmp>; 2911 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 2912 clock-names = "apb_pclk";
3514 2913
3515 out-ports { 2914 out-ports {
3516 port { 2915 port {
3517 merge 2916 merge_funnel_out: endpoint {
3518 2917 remote-endpoint = <&etf_in>;
3519 }; 2918 };
3520 }; 2919 };
3521 }; 2920 };
3522 2921
3523 in-ports { 2922 in-ports {
3524 #address-cell 2923 #address-cells = <1>;
3525 #size-cells = 2924 #size-cells = <0>;
3526 2925
3527 port@0 { 2926 port@0 {
3528 reg = 2927 reg = <0>;
3529 merge 2928 merge_funnel_in0: endpoint {
3530 2929 remote-endpoint =
3531 2930 <&funnel0_out>;
3532 }; 2931 };
3533 }; 2932 };
3534 2933
3535 port@2 { 2934 port@2 {
3536 reg = 2935 reg = <2>;
3537 merge 2936 merge_funnel_in2: endpoint {
3538 2937 remote-endpoint =
3539 2938 <&funnel2_out>;
3540 }; 2939 };
3541 }; 2940 };
3542 }; 2941 };
3543 }; 2942 };
3544 2943
3545 replicator@6046000 { 2944 replicator@6046000 {
3546 compatible = "arm,cor 2945 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 2946 reg = <0 0x06046000 0 0x1000>;
3548 2947
3549 clocks = <&aoss_qmp>; 2948 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 2949 clock-names = "apb_pclk";
3551 2950
3552 out-ports { 2951 out-ports {
3553 port { 2952 port {
3554 repli 2953 replicator_out: endpoint {
3555 2954 remote-endpoint = <&etr_in>;
3556 }; 2955 };
3557 }; 2956 };
3558 }; 2957 };
3559 2958
3560 in-ports { 2959 in-ports {
3561 port { 2960 port {
3562 repli 2961 replicator_in: endpoint {
3563 2962 remote-endpoint = <&etf_out>;
3564 }; 2963 };
3565 }; 2964 };
3566 }; 2965 };
3567 }; 2966 };
3568 2967
3569 etf@6047000 { 2968 etf@6047000 {
3570 compatible = "arm,cor 2969 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 2970 reg = <0 0x06047000 0 0x1000>;
3572 2971
3573 clocks = <&aoss_qmp>; 2972 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 2973 clock-names = "apb_pclk";
3575 2974
3576 out-ports { 2975 out-ports {
3577 port { 2976 port {
3578 etf_o 2977 etf_out: endpoint {
3579 2978 remote-endpoint =
3580 2979 <&replicator_in>;
3581 }; 2980 };
3582 }; 2981 };
3583 }; 2982 };
3584 2983
3585 in-ports { 2984 in-ports {
>> 2985 #address-cells = <1>;
>> 2986 #size-cells = <0>;
3586 2987
3587 port { !! 2988 port@1 {
>> 2989 reg = <1>;
3588 etf_i 2990 etf_in: endpoint {
3589 2991 remote-endpoint =
3590 2992 <&merge_funnel_out>;
3591 }; 2993 };
3592 }; 2994 };
3593 }; 2995 };
3594 }; 2996 };
3595 2997
3596 etr@6048000 { 2998 etr@6048000 {
3597 compatible = "arm,cor 2999 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3000 reg = <0 0x06048000 0 0x1000>;
3599 3001
3600 clocks = <&aoss_qmp>; 3002 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3003 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3004 arm,scatter-gather;
3603 3005
3604 in-ports { 3006 in-ports {
3605 port { 3007 port {
3606 etr_i 3008 etr_in: endpoint {
3607 3009 remote-endpoint =
3608 3010 <&replicator_out>;
3609 }; 3011 };
3610 }; 3012 };
3611 }; 3013 };
3612 }; 3014 };
3613 3015
3614 etm@7040000 { 3016 etm@7040000 {
3615 compatible = "arm,cor 3017 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3018 reg = <0 0x07040000 0 0x1000>;
3617 3019
3618 cpu = <&CPU0>; 3020 cpu = <&CPU0>;
3619 3021
3620 clocks = <&aoss_qmp>; 3022 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3023 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3024 arm,coresight-loses-context-with-cpu;
3623 3025
3624 out-ports { 3026 out-ports {
3625 port { 3027 port {
3626 etm0_ 3028 etm0_out: endpoint {
3627 3029 remote-endpoint =
3628 3030 <&apss_funnel_in0>;
3629 }; 3031 };
3630 }; 3032 };
3631 }; 3033 };
3632 }; 3034 };
3633 3035
3634 etm@7140000 { 3036 etm@7140000 {
3635 compatible = "arm,cor 3037 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3038 reg = <0 0x07140000 0 0x1000>;
3637 3039
3638 cpu = <&CPU1>; 3040 cpu = <&CPU1>;
3639 3041
3640 clocks = <&aoss_qmp>; 3042 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3043 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3044 arm,coresight-loses-context-with-cpu;
3643 3045
3644 out-ports { 3046 out-ports {
3645 port { 3047 port {
3646 etm1_ 3048 etm1_out: endpoint {
3647 3049 remote-endpoint =
3648 3050 <&apss_funnel_in1>;
3649 }; 3051 };
3650 }; 3052 };
3651 }; 3053 };
3652 }; 3054 };
3653 3055
3654 etm@7240000 { 3056 etm@7240000 {
3655 compatible = "arm,cor 3057 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3058 reg = <0 0x07240000 0 0x1000>;
3657 3059
3658 cpu = <&CPU2>; 3060 cpu = <&CPU2>;
3659 3061
3660 clocks = <&aoss_qmp>; 3062 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3063 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3064 arm,coresight-loses-context-with-cpu;
3663 3065
3664 out-ports { 3066 out-ports {
3665 port { 3067 port {
3666 etm2_ 3068 etm2_out: endpoint {
3667 3069 remote-endpoint =
3668 3070 <&apss_funnel_in2>;
3669 }; 3071 };
3670 }; 3072 };
3671 }; 3073 };
3672 }; 3074 };
3673 3075
3674 etm@7340000 { 3076 etm@7340000 {
3675 compatible = "arm,cor 3077 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3078 reg = <0 0x07340000 0 0x1000>;
3677 3079
3678 cpu = <&CPU3>; 3080 cpu = <&CPU3>;
3679 3081
3680 clocks = <&aoss_qmp>; 3082 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3083 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3084 arm,coresight-loses-context-with-cpu;
3683 3085
3684 out-ports { 3086 out-ports {
3685 port { 3087 port {
3686 etm3_ 3088 etm3_out: endpoint {
3687 3089 remote-endpoint =
3688 3090 <&apss_funnel_in3>;
3689 }; 3091 };
3690 }; 3092 };
3691 }; 3093 };
3692 }; 3094 };
3693 3095
3694 etm@7440000 { 3096 etm@7440000 {
3695 compatible = "arm,cor 3097 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3098 reg = <0 0x07440000 0 0x1000>;
3697 3099
3698 cpu = <&CPU4>; 3100 cpu = <&CPU4>;
3699 3101
3700 clocks = <&aoss_qmp>; 3102 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3103 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3104 arm,coresight-loses-context-with-cpu;
3703 3105
3704 out-ports { 3106 out-ports {
3705 port { 3107 port {
3706 etm4_ 3108 etm4_out: endpoint {
3707 3109 remote-endpoint =
3708 3110 <&apss_funnel_in4>;
3709 }; 3111 };
3710 }; 3112 };
3711 }; 3113 };
3712 }; 3114 };
3713 3115
3714 etm@7540000 { 3116 etm@7540000 {
3715 compatible = "arm,cor 3117 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3118 reg = <0 0x07540000 0 0x1000>;
3717 3119
3718 cpu = <&CPU5>; 3120 cpu = <&CPU5>;
3719 3121
3720 clocks = <&aoss_qmp>; 3122 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3123 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3124 arm,coresight-loses-context-with-cpu;
3723 3125
3724 out-ports { 3126 out-ports {
3725 port { 3127 port {
3726 etm5_ 3128 etm5_out: endpoint {
3727 3129 remote-endpoint =
3728 3130 <&apss_funnel_in5>;
3729 }; 3131 };
3730 }; 3132 };
3731 }; 3133 };
3732 }; 3134 };
3733 3135
3734 etm@7640000 { 3136 etm@7640000 {
3735 compatible = "arm,cor 3137 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3138 reg = <0 0x07640000 0 0x1000>;
3737 3139
3738 cpu = <&CPU6>; 3140 cpu = <&CPU6>;
3739 3141
3740 clocks = <&aoss_qmp>; 3142 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3143 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3144 arm,coresight-loses-context-with-cpu;
3743 3145
3744 out-ports { 3146 out-ports {
3745 port { 3147 port {
3746 etm6_ 3148 etm6_out: endpoint {
3747 3149 remote-endpoint =
3748 3150 <&apss_funnel_in6>;
3749 }; 3151 };
3750 }; 3152 };
3751 }; 3153 };
3752 }; 3154 };
3753 3155
3754 etm@7740000 { 3156 etm@7740000 {
3755 compatible = "arm,cor 3157 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3158 reg = <0 0x07740000 0 0x1000>;
3757 3159
3758 cpu = <&CPU7>; 3160 cpu = <&CPU7>;
3759 3161
3760 clocks = <&aoss_qmp>; 3162 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3163 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3164 arm,coresight-loses-context-with-cpu;
3763 3165
3764 out-ports { 3166 out-ports {
3765 port { 3167 port {
3766 etm7_ 3168 etm7_out: endpoint {
3767 3169 remote-endpoint =
3768 3170 <&apss_funnel_in7>;
3769 }; 3171 };
3770 }; 3172 };
3771 }; 3173 };
3772 }; 3174 };
3773 3175
3774 funnel@7800000 { /* APSS Funn 3176 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3177 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3178 reg = <0 0x07800000 0 0x1000>;
3777 3179
3778 clocks = <&aoss_qmp>; 3180 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3181 clock-names = "apb_pclk";
3780 3182
3781 out-ports { 3183 out-ports {
3782 port { 3184 port {
3783 apss_ 3185 apss_funnel_out: endpoint {
3784 3186 remote-endpoint =
3785 3187 <&apss_merge_funnel_in>;
3786 }; 3188 };
3787 }; 3189 };
3788 }; 3190 };
3789 3191
3790 in-ports { 3192 in-ports {
3791 #address-cell 3193 #address-cells = <1>;
3792 #size-cells = 3194 #size-cells = <0>;
3793 3195
3794 port@0 { 3196 port@0 {
3795 reg = 3197 reg = <0>;
3796 apss_ 3198 apss_funnel_in0: endpoint {
3797 3199 remote-endpoint =
3798 3200 <&etm0_out>;
3799 }; 3201 };
3800 }; 3202 };
3801 3203
3802 port@1 { 3204 port@1 {
3803 reg = 3205 reg = <1>;
3804 apss_ 3206 apss_funnel_in1: endpoint {
3805 3207 remote-endpoint =
3806 3208 <&etm1_out>;
3807 }; 3209 };
3808 }; 3210 };
3809 3211
3810 port@2 { 3212 port@2 {
3811 reg = 3213 reg = <2>;
3812 apss_ 3214 apss_funnel_in2: endpoint {
3813 3215 remote-endpoint =
3814 3216 <&etm2_out>;
3815 }; 3217 };
3816 }; 3218 };
3817 3219
3818 port@3 { 3220 port@3 {
3819 reg = 3221 reg = <3>;
3820 apss_ 3222 apss_funnel_in3: endpoint {
3821 3223 remote-endpoint =
3822 3224 <&etm3_out>;
3823 }; 3225 };
3824 }; 3226 };
3825 3227
3826 port@4 { 3228 port@4 {
3827 reg = 3229 reg = <4>;
3828 apss_ 3230 apss_funnel_in4: endpoint {
3829 3231 remote-endpoint =
3830 3232 <&etm4_out>;
3831 }; 3233 };
3832 }; 3234 };
3833 3235
3834 port@5 { 3236 port@5 {
3835 reg = 3237 reg = <5>;
3836 apss_ 3238 apss_funnel_in5: endpoint {
3837 3239 remote-endpoint =
3838 3240 <&etm5_out>;
3839 }; 3241 };
3840 }; 3242 };
3841 3243
3842 port@6 { 3244 port@6 {
3843 reg = 3245 reg = <6>;
3844 apss_ 3246 apss_funnel_in6: endpoint {
3845 3247 remote-endpoint =
3846 3248 <&etm6_out>;
3847 }; 3249 };
3848 }; 3250 };
3849 3251
3850 port@7 { 3252 port@7 {
3851 reg = 3253 reg = <7>;
3852 apss_ 3254 apss_funnel_in7: endpoint {
3853 3255 remote-endpoint =
3854 3256 <&etm7_out>;
3855 }; 3257 };
3856 }; 3258 };
3857 }; 3259 };
3858 }; 3260 };
3859 3261
3860 funnel@7810000 { 3262 funnel@7810000 {
3861 compatible = "arm,cor 3263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3264 reg = <0 0x07810000 0 0x1000>;
3863 3265
3864 clocks = <&aoss_qmp>; 3266 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3267 clock-names = "apb_pclk";
3866 3268
3867 out-ports { 3269 out-ports {
3868 port { 3270 port {
3869 apss_ 3271 apss_merge_funnel_out: endpoint {
3870 3272 remote-endpoint =
3871 3273 <&funnel2_in5>;
3872 }; 3274 };
3873 }; 3275 };
3874 }; 3276 };
3875 3277
3876 in-ports { 3278 in-ports {
3877 port { 3279 port {
3878 apss_ 3280 apss_merge_funnel_in: endpoint {
3879 3281 remote-endpoint =
3880 3282 <&apss_funnel_out>;
3881 }; 3283 };
3882 }; 3284 };
3883 }; 3285 };
3884 }; 3286 };
3885 3287
3886 sdhc_2: mmc@8804000 { !! 3288 sdhc_2: sdhci@8804000 {
3887 compatible = "qcom,sd 3289 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3290 reg = <0 0x08804000 0 0x1000>;
3889 3291
3890 interrupts = <GIC_SPI 3292 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3293 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3294 interrupt-names = "hc_irq", "pwr_irq";
3893 3295
3894 clocks = <&gcc GCC_SD 3296 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD !! 3297 <&gcc GCC_SDCC2_APPS_CLK>;
3896 <&rpmhcc RPM !! 3298 clock-names = "iface", "core";
3897 clock-names = "iface" <<
3898 iommus = <&apps_smmu 3299 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3300 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3301 operating-points-v2 = <&sdhc2_opp_table>;
3901 3302
3902 status = "disabled"; 3303 status = "disabled";
3903 3304
3904 sdhc2_opp_table: opp- !! 3305 sdhc2_opp_table: sdhc2-opp-table {
3905 compatible = 3306 compatible = "operating-points-v2";
3906 3307
3907 opp-9600000 { 3308 opp-9600000 {
3908 opp-h 3309 opp-hz = /bits/ 64 <9600000>;
3909 requi 3310 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3311 };
3911 3312
3912 opp-19200000 3313 opp-19200000 {
3913 opp-h 3314 opp-hz = /bits/ 64 <19200000>;
3914 requi 3315 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3316 };
3916 3317
3917 opp-100000000 3318 opp-100000000 {
3918 opp-h 3319 opp-hz = /bits/ 64 <100000000>;
3919 requi 3320 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3321 };
3921 3322
3922 opp-201500000 3323 opp-201500000 {
3923 opp-h 3324 opp-hz = /bits/ 64 <201500000>;
3924 requi 3325 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3326 };
3926 }; 3327 };
3927 }; 3328 };
3928 3329
>> 3330 qspi_opp_table: qspi-opp-table {
>> 3331 compatible = "operating-points-v2";
>> 3332
>> 3333 opp-19200000 {
>> 3334 opp-hz = /bits/ 64 <19200000>;
>> 3335 required-opps = <&rpmhpd_opp_min_svs>;
>> 3336 };
>> 3337
>> 3338 opp-100000000 {
>> 3339 opp-hz = /bits/ 64 <100000000>;
>> 3340 required-opps = <&rpmhpd_opp_low_svs>;
>> 3341 };
>> 3342
>> 3343 opp-150000000 {
>> 3344 opp-hz = /bits/ 64 <150000000>;
>> 3345 required-opps = <&rpmhpd_opp_svs>;
>> 3346 };
>> 3347
>> 3348 opp-300000000 {
>> 3349 opp-hz = /bits/ 64 <300000000>;
>> 3350 required-opps = <&rpmhpd_opp_nom>;
>> 3351 };
>> 3352 };
>> 3353
3929 qspi: spi@88df000 { 3354 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3355 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3356 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3357 #address-cells = <1>;
3934 #size-cells = <0>; 3358 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3359 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3360 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3361 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3362 clock-names = "iface", "core";
3939 power-domains = <&rpm 3363 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3364 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3365 status = "disabled";
3942 }; 3366 };
3943 3367
3944 slim: slim-ngd@171c0000 { !! 3368 slim: slim@171c0000 {
3945 compatible = "qcom,sl 3369 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3370 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3371 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3372
3949 dmas = <&slimbam 3>, !! 3373 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 3374 qcom,ea-pc = <0x270>;
>> 3375 status = "okay";
>> 3376 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3377 <&slimbam 5>, <&slimbam 6>;
>> 3378 dma-names = "rx", "tx", "tx2", "rx2";
3951 3379
3952 iommus = <&apps_smmu 3380 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3381 #address-cells = <1>;
3954 #size-cells = <0>; 3382 #size-cells = <0>;
3955 status = "disabled"; <<
3956 }; <<
3957 3383
3958 lmh_cluster1: lmh@17d70800 { !! 3384 ngd@1 {
3959 compatible = "qcom,sd !! 3385 reg = <1>;
3960 reg = <0 0x17d70800 0 !! 3386 #address-cells = <2>;
3961 interrupts = <GIC_SPI !! 3387 #size-cells = <0>;
3962 cpus = <&CPU4>; !! 3388
3963 qcom,lmh-temp-arm-mil !! 3389 wcd9340_ifd: ifd@0{
3964 qcom,lmh-temp-low-mil !! 3390 compatible = "slim217,250";
3965 qcom,lmh-temp-high-mi !! 3391 reg = <0 0>;
3966 interrupt-controller; !! 3392 };
3967 #interrupt-cells = <1 !! 3393
>> 3394 wcd9340: codec@1{
>> 3395 compatible = "slim217,250";
>> 3396 reg = <1 0>;
>> 3397 slim-ifc-dev = <&wcd9340_ifd>;
>> 3398
>> 3399 #sound-dai-cells = <1>;
>> 3400
>> 3401 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3402 interrupt-controller;
>> 3403 #interrupt-cells = <1>;
>> 3404
>> 3405 #clock-cells = <0>;
>> 3406 clock-frequency = <9600000>;
>> 3407 clock-output-names = "mclk";
>> 3408 qcom,micbias1-millivolt = <1800>;
>> 3409 qcom,micbias2-millivolt = <1800>;
>> 3410 qcom,micbias3-millivolt = <1800>;
>> 3411 qcom,micbias4-millivolt = <1800>;
>> 3412
>> 3413 #address-cells = <1>;
>> 3414 #size-cells = <1>;
>> 3415
>> 3416 wcdgpio: gpio-controller@42 {
>> 3417 compatible = "qcom,wcd9340-gpio";
>> 3418 gpio-controller;
>> 3419 #gpio-cells = <2>;
>> 3420 reg = <0x42 0x2>;
>> 3421 };
>> 3422
>> 3423 swm: swm@c85 {
>> 3424 compatible = "qcom,soundwire-v1.3.0";
>> 3425 reg = <0xc85 0x40>;
>> 3426 interrupts-extended = <&wcd9340 20>;
>> 3427
>> 3428 qcom,dout-ports = <6>;
>> 3429 qcom,din-ports = <2>;
>> 3430 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3431 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3432 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3433
>> 3434 #sound-dai-cells = <1>;
>> 3435 clocks = <&wcd9340>;
>> 3436 clock-names = "iface";
>> 3437 #address-cells = <2>;
>> 3438 #size-cells = <0>;
>> 3439
>> 3440
>> 3441 };
>> 3442 };
>> 3443 };
3968 }; 3444 };
3969 3445
3970 lmh_cluster0: lmh@17d78800 { !! 3446 sound: sound {
3971 compatible = "qcom,sd <<
3972 reg = <0 0x17d78800 0 <<
3973 interrupts = <GIC_SPI <<
3974 cpus = <&CPU0>; <<
3975 qcom,lmh-temp-arm-mil <<
3976 qcom,lmh-temp-low-mil <<
3977 qcom,lmh-temp-high-mi <<
3978 interrupt-controller; <<
3979 #interrupt-cells = <1 <<
3980 }; 3447 };
3981 3448
3982 usb_1_hsphy: phy@88e2000 { 3449 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3450 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3451 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3452 status = "disabled";
3986 #phy-cells = <0>; 3453 #phy-cells = <0>;
3987 3454
3988 clocks = <&gcc GCC_US 3455 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3456 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3457 clock-names = "cfg_ahb", "ref";
3991 3458
3992 resets = <&gcc GCC_QU 3459 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3460
3994 nvmem-cells = <&qusb2 3461 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3462 };
3996 3463
3997 usb_2_hsphy: phy@88e3000 { 3464 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3465 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3466 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3467 status = "disabled";
4001 #phy-cells = <0>; 3468 #phy-cells = <0>;
4002 3469
4003 clocks = <&gcc GCC_US 3470 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3471 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3472 clock-names = "cfg_ahb", "ref";
4006 3473
4007 resets = <&gcc GCC_QU 3474 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3475
4009 nvmem-cells = <&qusb2 3476 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3477 };
4011 3478
4012 usb_1_qmpphy: phy@88e8000 { !! 3479 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3480 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3481 reg = <0 0x088e9000 0 0x18c>,
>> 3482 <0 0x088e8000 0 0x10>;
>> 3483 reg-names = "reg-base", "dp_com";
4015 status = "disabled"; 3484 status = "disabled";
>> 3485 #clock-cells = <1>;
>> 3486 #address-cells = <2>;
>> 3487 #size-cells = <2>;
>> 3488 ranges;
4016 3489
4017 clocks = <&gcc GCC_US 3490 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3491 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3492 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3493 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3494 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3495
4028 resets = <&gcc GCC_US !! 3496 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3497 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3498 reset-names = "phy", "common";
4031 3499
4032 #clock-cells = <1>; !! 3500 usb_1_ssphy: lanes@88e9200 {
4033 #phy-cells = <1>; !! 3501 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3502 <0 0x088e9400 0 0x200>,
4035 !! 3503 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3504 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3505 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3506 <0 0x088e9a00 0 0x100>;
4039 !! 3507 #phy-cells = <0>;
4040 port@0 { !! 3508 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4041 reg = !! 3509 clock-names = "pipe0";
4042 !! 3510 clock-output-names = "usb3_phy_pipe_clk_src";
4043 usb_1 <<
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3511 };
4063 }; 3512 };
4064 3513
4065 usb_2_qmpphy: phy@88eb000 { 3514 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3515 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 3516 reg = <0 0x088eb000 0 0x18c>;
>> 3517 status = "disabled";
>> 3518 #clock-cells = <1>;
>> 3519 #address-cells = <2>;
>> 3520 #size-cells = <2>;
>> 3521 ranges;
4068 3522
4069 clocks = <&gcc GCC_US 3523 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 3524 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 3525 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 3526 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 3527 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 3528
4083 resets = <&gcc GCC_US !! 3529 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 3530 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 3531 reset-names = "phy", "common";
4086 "phy_ph <<
4087 3532
4088 status = "disabled"; !! 3533 usb_2_ssphy: lane@88eb200 {
>> 3534 reg = <0 0x088eb200 0 0x128>,
>> 3535 <0 0x088eb400 0 0x1fc>,
>> 3536 <0 0x088eb800 0 0x218>,
>> 3537 <0 0x088eb600 0 0x70>;
>> 3538 #phy-cells = <0>;
>> 3539 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3540 clock-names = "pipe0";
>> 3541 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3542 };
4089 }; 3543 };
4090 3544
4091 usb_1: usb@a6f8800 { 3545 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 3546 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 3547 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 3548 status = "disabled";
4095 #address-cells = <2>; 3549 #address-cells = <2>;
4096 #size-cells = <2>; 3550 #size-cells = <2>;
4097 ranges; 3551 ranges;
4098 dma-ranges; 3552 dma-ranges;
4099 3553
4100 clocks = <&gcc GCC_CF 3554 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 3555 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 3556 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US !! 3557 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4104 <&gcc GCC_US !! 3558 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
4105 clock-names = "cfg_no !! 3559 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4106 "core", !! 3560 "sleep";
4107 "iface" <<
4108 "sleep" <<
4109 "mock_u <<
4110 3561
4111 assigned-clocks = <&g 3562 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 3563 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 3564 assigned-clock-rates = <19200000>, <150000000>;
4114 3565
4115 interrupts-extended = !! 3566 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 3567 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 3568 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 3569 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 3570 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 3571 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 3572
4126 power-domains = <&gcc 3573 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 3574
4128 resets = <&gcc GCC_US 3575 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 3576
4130 interconnects = <&agg !! 3577 interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>,
4131 <&gla !! 3578 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
4132 interconnect-names = 3579 interconnect-names = "usb-ddr", "apps-usb";
4133 3580
4134 usb_1_dwc3: usb@a6000 !! 3581 usb_1_dwc3: dwc3@a600000 {
4135 compatible = 3582 compatible = "snps,dwc3";
4136 reg = <0 0x0a 3583 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 3584 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 3585 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 3586 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 3587 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 3588 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 3589 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 3590 };
4165 }; 3591 };
4166 3592
4167 usb_2: usb@a8f8800 { 3593 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 3594 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 3595 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 3596 status = "disabled";
4171 #address-cells = <2>; 3597 #address-cells = <2>;
4172 #size-cells = <2>; 3598 #size-cells = <2>;
4173 ranges; 3599 ranges;
4174 dma-ranges; 3600 dma-ranges;
4175 3601
4176 clocks = <&gcc GCC_CF 3602 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 3603 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 3604 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US !! 3605 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4180 <&gcc GCC_US !! 3606 <&gcc GCC_USB30_SEC_SLEEP_CLK>;
4181 clock-names = "cfg_no !! 3607 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4182 "core", !! 3608 "sleep";
4183 "iface" <<
4184 "sleep" <<
4185 "mock_u <<
4186 3609
4187 assigned-clocks = <&g 3610 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 3611 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 3612 assigned-clock-rates = <19200000>, <150000000>;
4190 3613
4191 interrupts-extended = !! 3614 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 3615 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 3616 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 3617 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 3618 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 3619 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 3620
4202 power-domains = <&gcc 3621 power-domains = <&gcc USB30_SEC_GDSC>;
4203 3622
4204 resets = <&gcc GCC_US 3623 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 3624
4206 interconnects = <&agg !! 3625 interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>,
4207 <&gla !! 3626 <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
4208 interconnect-names = 3627 interconnect-names = "usb-ddr", "apps-usb";
4209 3628
4210 usb_2_dwc3: usb@a8000 !! 3629 usb_2_dwc3: dwc3@a800000 {
4211 compatible = 3630 compatible = "snps,dwc3";
4212 reg = <0 0x0a 3631 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 3632 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 3633 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 3634 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 3635 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 3636 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 3637 phy-names = "usb2-phy", "usb3-phy";
4220 }; 3638 };
4221 }; 3639 };
4222 3640
4223 venus: video-codec@aa00000 { 3641 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 3642 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 3643 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 3644 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 3645 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 3646 <&videocc VCODEC0_GDSC>,
4229 <&vid !! 3647 <&videocc VCODEC1_GDSC>;
4230 <&rpm !! 3648 power-domain-names = "venus", "vcodec0", "vcodec1";
4231 power-domain-names = <<
4232 operating-points-v2 = <<
4233 clocks = <&videocc VI 3649 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 3650 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 3651 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 3652 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 3653 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 3654 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 3655 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 3656 clock-names = "core", "iface", "bus",
4241 "vcodec 3657 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 3658 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 3659 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 3660 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 3661 memory-region = <&venus_mem>;
4246 interconnects = <&mms <<
4247 <&gla <<
4248 interconnect-names = <<
4249 <<
4250 status = "disabled"; <<
4251 3662
4252 video-core0 { 3663 video-core0 {
4253 compatible = 3664 compatible = "venus-decoder";
4254 }; 3665 };
4255 3666
4256 video-core1 { 3667 video-core1 {
4257 compatible = 3668 compatible = "venus-encoder";
4258 }; 3669 };
4259 <<
4260 venus_opp_table: opp- <<
4261 compatible = <<
4262 <<
4263 opp-100000000 <<
4264 opp-h <<
4265 requi <<
4266 }; <<
4267 <<
4268 opp-200000000 <<
4269 opp-h <<
4270 requi <<
4271 }; <<
4272 <<
4273 opp-320000000 <<
4274 opp-h <<
4275 requi <<
4276 }; <<
4277 <<
4278 opp-380000000 <<
4279 opp-h <<
4280 requi <<
4281 }; <<
4282 <<
4283 opp-444000000 <<
4284 opp-h <<
4285 requi <<
4286 }; <<
4287 <<
4288 opp-533000097 <<
4289 opp-h <<
4290 requi <<
4291 }; <<
4292 }; <<
4293 }; 3670 };
4294 3671
4295 videocc: clock-controller@ab0 3672 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 3673 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 3674 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 3675 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 3676 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 3677 #clock-cells = <1>;
4301 #power-domain-cells = 3678 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 3679 #reset-cells = <1>;
4303 }; 3680 };
4304 3681
4305 camss: camss@acb3000 { <<
4306 compatible = "qcom,sd <<
4307 <<
4308 reg = <0 0x0acb3000 0 <<
4309 <0 0x0acba000 <<
4310 <0 0x0acc8000 <<
4311 <0 0x0ac65000 <<
4312 <0 0x0ac66000 <<
4313 <0 0x0ac67000 <<
4314 <0 0x0ac68000 <<
4315 <0 0x0acaf000 <<
4316 <0 0x0acb6000 <<
4317 <0 0x0acc4000 <<
4318 reg-names = "csid0", <<
4319 "csid1", <<
4320 "csid2", <<
4321 "csiphy0", <<
4322 "csiphy1", <<
4323 "csiphy2", <<
4324 "csiphy3", <<
4325 "vfe0", <<
4326 "vfe1", <<
4327 "vfe_lite"; <<
4328 <<
4329 interrupts = <GIC_SPI <<
4330 <GIC_SPI 466 <<
4331 <GIC_SPI 468 <<
4332 <GIC_SPI 477 <<
4333 <GIC_SPI 478 <<
4334 <GIC_SPI 479 <<
4335 <GIC_SPI 448 <<
4336 <GIC_SPI 465 <<
4337 <GIC_SPI 467 <<
4338 <GIC_SPI 469 <<
4339 interrupt-names = "cs <<
4340 "csid1", <<
4341 "csid2", <<
4342 "csiphy0", <<
4343 "csiphy1", <<
4344 "csiphy2", <<
4345 "csiphy3", <<
4346 "vfe0", <<
4347 "vfe1", <<
4348 "vfe_lite"; <<
4349 <<
4350 power-domains = <&clo <<
4351 <&clock_camcc <<
4352 <&clock_camcc <<
4353 <<
4354 clocks = <&clock_camc <<
4355 <&clock_camcc <<
4356 <&clock_camcc <<
4357 <&clock_camcc <<
4358 <&clock_camcc <<
4359 <&clock_camcc <<
4360 <&clock_camcc <<
4361 <&clock_camcc <<
4362 <&clock_camcc <<
4363 <&clock_camcc <<
4364 <&clock_camcc <<
4365 <&clock_camcc <<
4366 <&clock_camcc <<
4367 <&clock_camcc <<
4368 <&clock_camcc <<
4369 <&clock_camcc <<
4370 <&clock_camcc <<
4371 <&clock_camcc <<
4372 <&clock_camcc <<
4373 <&clock_camcc <<
4374 <&clock_camcc <<
4375 <&gcc GCC_CAM <<
4376 <&gcc GCC_CAM <<
4377 <&clock_camcc <<
4378 <&clock_camcc <<
4379 <&clock_camcc <<
4380 <&clock_camcc <<
4381 <&clock_camcc <<
4382 <&clock_camcc <<
4383 <&clock_camcc <<
4384 <&clock_camcc <<
4385 <&clock_camcc <<
4386 <&clock_camcc <<
4387 <&clock_camcc <<
4388 <&clock_camcc <<
4389 <&clock_camcc <<
4390 clock-names = "camnoc <<
4391 "cpas_ahb", <<
4392 "cphy_rx_src" <<
4393 "csi0", <<
4394 "csi0_src", <<
4395 "csi1", <<
4396 "csi1_src", <<
4397 "csi2", <<
4398 "csi2_src", <<
4399 "csiphy0", <<
4400 "csiphy0_time <<
4401 "csiphy0_time <<
4402 "csiphy1", <<
4403 "csiphy1_time <<
4404 "csiphy1_time <<
4405 "csiphy2", <<
4406 "csiphy2_time <<
4407 "csiphy2_time <<
4408 "csiphy3", <<
4409 "csiphy3_time <<
4410 "csiphy3_time <<
4411 "gcc_camera_a <<
4412 "gcc_camera_a <<
4413 "slow_ahb_src <<
4414 "soc_ahb", <<
4415 "vfe0_axi", <<
4416 "vfe0", <<
4417 "vfe0_cphy_rx <<
4418 "vfe0_src", <<
4419 "vfe1_axi", <<
4420 "vfe1", <<
4421 "vfe1_cphy_rx <<
4422 "vfe1_src", <<
4423 "vfe_lite", <<
4424 "vfe_lite_cph <<
4425 "vfe_lite_src <<
4426 <<
4427 iommus = <&apps_smmu <<
4428 <&apps_smmu <<
4429 <&apps_smmu <<
4430 <&apps_smmu <<
4431 <<
4432 status = "disabled"; <<
4433 <<
4434 ports { <<
4435 #address-cell <<
4436 #size-cells = <<
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; <<
4454 }; <<
4455 <<
4456 cci: cci@ac4a000 { 3682 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 3683 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 3684 #address-cells = <1>;
4459 #size-cells = <0>; 3685 #size-cells = <0>;
4460 3686
4461 reg = <0 0x0ac4a000 0 3687 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 3688 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 3689 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 3690
4465 clocks = <&clock_camc 3691 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 3692 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 3693 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 3694 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 3695 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 3696 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 3697 clock-names = "camnoc_axi",
4472 "soc_ahb", 3698 "soc_ahb",
4473 "slow_ahb_src 3699 "slow_ahb_src",
4474 "cpas_ahb", 3700 "cpas_ahb",
4475 "cci", 3701 "cci",
4476 "cci_src"; 3702 "cci_src";
4477 3703
4478 assigned-clocks = <&c 3704 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 3705 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 3706 assigned-clock-rates = <80000000>, <37500000>;
4481 3707
4482 pinctrl-names = "defa 3708 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 3709 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 3710 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 3711
4486 status = "disabled"; 3712 status = "disabled";
4487 3713
4488 cci_i2c0: i2c-bus@0 { 3714 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 3715 reg = <0>;
4490 clock-frequen 3716 clock-frequency = <1000000>;
4491 #address-cell 3717 #address-cells = <1>;
4492 #size-cells = 3718 #size-cells = <0>;
4493 }; 3719 };
4494 3720
4495 cci_i2c1: i2c-bus@1 { 3721 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 3722 reg = <1>;
4497 clock-frequen 3723 clock-frequency = <1000000>;
4498 #address-cell 3724 #address-cells = <1>;
4499 #size-cells = 3725 #size-cells = <0>;
4500 }; 3726 };
4501 }; 3727 };
4502 3728
4503 clock_camcc: clock-controller 3729 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 3730 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 3731 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 3732 #clock-cells = <1>;
4507 #reset-cells = <1>; 3733 #reset-cells = <1>;
4508 #power-domain-cells = 3734 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM <<
4510 clock-names = "bi_tcx <<
4511 }; 3735 };
4512 3736
4513 mdss: display-subsystem@ae000 !! 3737 dsi_opp_table: dsi-opp-table {
>> 3738 compatible = "operating-points-v2";
>> 3739
>> 3740 opp-19200000 {
>> 3741 opp-hz = /bits/ 64 <19200000>;
>> 3742 required-opps = <&rpmhpd_opp_min_svs>;
>> 3743 };
>> 3744
>> 3745 opp-180000000 {
>> 3746 opp-hz = /bits/ 64 <180000000>;
>> 3747 required-opps = <&rpmhpd_opp_low_svs>;
>> 3748 };
>> 3749
>> 3750 opp-275000000 {
>> 3751 opp-hz = /bits/ 64 <275000000>;
>> 3752 required-opps = <&rpmhpd_opp_svs>;
>> 3753 };
>> 3754
>> 3755 opp-328580000 {
>> 3756 opp-hz = /bits/ 64 <328580000>;
>> 3757 required-opps = <&rpmhpd_opp_svs_l1>;
>> 3758 };
>> 3759
>> 3760 opp-358000000 {
>> 3761 opp-hz = /bits/ 64 <358000000>;
>> 3762 required-opps = <&rpmhpd_opp_nom>;
>> 3763 };
>> 3764 };
>> 3765
>> 3766 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 3767 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 3768 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 3769 reg-names = "mdss";
4517 3770
4518 power-domains = <&dis 3771 power-domains = <&dispcc MDSS_GDSC>;
4519 3772
4520 clocks = <&dispcc DIS !! 3773 clocks = <&gcc GCC_DISP_AHB_CLK>,
>> 3774 <&gcc GCC_DISP_AXI_CLK>,
4521 <&dispcc DIS 3775 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" !! 3776 clock-names = "iface", "bus", "core";
>> 3777
>> 3778 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 3779 assigned-clock-rates = <300000000>;
4523 3780
4524 interrupts = <GIC_SPI 3781 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 3782 interrupt-controller;
4526 #interrupt-cells = <1 3783 #interrupt-cells = <1>;
4527 3784
4528 interconnects = <&mms <<
4529 <&mms <<
4530 interconnect-names = <<
4531 <<
4532 iommus = <&apps_smmu 3785 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 3786 <&apps_smmu 0xc80 0x8>;
4534 3787
4535 status = "disabled"; 3788 status = "disabled";
4536 3789
4537 #address-cells = <2>; 3790 #address-cells = <2>;
4538 #size-cells = <2>; 3791 #size-cells = <2>;
4539 ranges; 3792 ranges;
4540 3793
4541 mdss_mdp: display-con !! 3794 mdss_mdp: mdp@ae01000 {
4542 compatible = 3795 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 3796 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 3797 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 3798 reg-names = "mdp", "vbif";
4546 3799
4547 clocks = <&gc !! 3800 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4548 <&di <<
4549 <&di 3801 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 3802 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 3803 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = !! 3804 clock-names = "iface", "bus", "core", "vsync";
4553 3805
4554 assigned-cloc !! 3806 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4555 assigned-cloc !! 3807 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 3808 assigned-clock-rates = <300000000>,
>> 3809 <19200000>;
4556 operating-poi 3810 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 3811 power-domains = <&rpmhpd SDM845_CX>;
4558 3812
4559 interrupt-par 3813 interrupt-parent = <&mdss>;
4560 interrupts = !! 3814 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> 3815
>> 3816 status = "disabled";
4561 3817
4562 ports { 3818 ports {
4563 #addr 3819 #address-cells = <1>;
4564 #size 3820 #size-cells = <0>;
4565 3821
4566 port@ 3822 port@0 {
4567 3823 reg = <0>;
4568 !! 3824 dpu_intf1_out: endpoint {
4569 !! 3825 remote-endpoint = <&dsi0_in>;
4570 3826 };
4571 }; 3827 };
4572 3828
4573 port@ 3829 port@1 {
4574 3830 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 3831 dpu_intf2_out: endpoint {
4583 !! 3832 remote-endpoint = <&dsi1_in>;
4584 3833 };
4585 }; 3834 };
4586 }; 3835 };
4587 3836
4588 mdp_opp_table !! 3837 mdp_opp_table: mdp-opp-table {
4589 compa 3838 compatible = "operating-points-v2";
4590 3839
4591 opp-1 3840 opp-19200000 {
4592 3841 opp-hz = /bits/ 64 <19200000>;
4593 3842 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 3843 };
4595 3844
4596 opp-1 3845 opp-171428571 {
4597 3846 opp-hz = /bits/ 64 <171428571>;
4598 3847 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 3848 };
4600 3849
4601 opp-3 3850 opp-344000000 {
4602 3851 opp-hz = /bits/ 64 <344000000>;
4603 3852 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 3853 };
4605 3854
4606 opp-4 3855 opp-430000000 {
4607 3856 opp-hz = /bits/ 64 <430000000>;
4608 3857 required-opps = <&rpmhpd_opp_nom>;
4609 }; 3858 };
4610 }; 3859 };
4611 }; 3860 };
4612 3861
4613 mdss_dp: displayport- !! 3862 dsi0: dsi@ae94000 {
4614 status = "dis !! 3863 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 3864 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 3865 reg-names = "dsi_ctrl";
4691 3866
4692 interrupt-par 3867 interrupt-parent = <&mdss>;
4693 interrupts = !! 3868 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4694 3869
4695 clocks = <&di 3870 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 3871 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 3872 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 3873 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 3874 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 3875 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 3876 clock-names = "byte",
4702 3877 "byte_intf",
4703 3878 "pixel",
4704 3879 "core",
4705 3880 "iface",
4706 3881 "bus";
4707 assigned-cloc <<
4708 assigned-cloc <<
4709 <<
4710 operating-poi 3882 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 3883 power-domains = <&rpmhpd SDM845_CX>;
4712 3884
4713 phys = <&mdss !! 3885 phys = <&dsi0_phy>;
>> 3886 phy-names = "dsi";
4714 3887
4715 status = "dis 3888 status = "disabled";
4716 3889
4717 #address-cell <<
4718 #size-cells = <<
4719 <<
4720 ports { 3890 ports {
4721 #addr 3891 #address-cells = <1>;
4722 #size 3892 #size-cells = <0>;
4723 3893
4724 port@ 3894 port@0 {
4725 3895 reg = <0>;
4726 !! 3896 dsi0_in: endpoint {
4727 3897 remote-endpoint = <&dpu_intf1_out>;
4728 3898 };
4729 }; 3899 };
4730 3900
4731 port@ 3901 port@1 {
4732 3902 reg = <1>;
4733 !! 3903 dsi0_out: endpoint {
4734 3904 };
4735 }; 3905 };
4736 }; 3906 };
4737 }; 3907 };
4738 3908
4739 mdss_dsi0_phy: phy@ae !! 3909 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 3910 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 3911 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 3912 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 3913 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 3914 reg-names = "dsi_phy",
4745 " 3915 "dsi_phy_lane",
4746 " 3916 "dsi_pll";
4747 3917
4748 #clock-cells 3918 #clock-cells = <1>;
4749 #phy-cells = 3919 #phy-cells = <0>;
4750 3920
4751 clocks = <&di 3921 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 3922 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 3923 clock-names = "iface", "ref";
4754 3924
4755 status = "dis 3925 status = "disabled";
4756 }; 3926 };
4757 3927
4758 mdss_dsi1: dsi@ae9600 !! 3928 dsi1: dsi@ae96000 {
4759 compatible = !! 3929 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 3930 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 3931 reg-names = "dsi_ctrl";
4763 3932
4764 interrupt-par 3933 interrupt-parent = <&mdss>;
4765 interrupts = !! 3934 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4766 3935
4767 clocks = <&di 3936 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 3937 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 3938 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 3939 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 3940 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 3941 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 3942 clock-names = "byte",
4774 3943 "byte_intf",
4775 3944 "pixel",
4776 3945 "core",
4777 3946 "iface",
4778 3947 "bus";
4779 assigned-cloc <<
4780 assigned-cloc <<
4781 <<
4782 operating-poi 3948 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 3949 power-domains = <&rpmhpd SDM845_CX>;
4784 3950
4785 phys = <&mdss !! 3951 phys = <&dsi1_phy>;
>> 3952 phy-names = "dsi";
4786 3953
4787 status = "dis 3954 status = "disabled";
4788 3955
4789 #address-cell <<
4790 #size-cells = <<
4791 <<
4792 ports { 3956 ports {
4793 #addr 3957 #address-cells = <1>;
4794 #size 3958 #size-cells = <0>;
4795 3959
4796 port@ 3960 port@0 {
4797 3961 reg = <0>;
4798 !! 3962 dsi1_in: endpoint {
4799 3963 remote-endpoint = <&dpu_intf2_out>;
4800 3964 };
4801 }; 3965 };
4802 3966
4803 port@ 3967 port@1 {
4804 3968 reg = <1>;
4805 !! 3969 dsi1_out: endpoint {
4806 3970 };
4807 }; 3971 };
4808 }; 3972 };
4809 }; 3973 };
4810 3974
4811 mdss_dsi1_phy: phy@ae !! 3975 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 3976 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 3977 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 3978 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 3979 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 3980 reg-names = "dsi_phy",
4817 " 3981 "dsi_phy_lane",
4818 " 3982 "dsi_pll";
4819 3983
4820 #clock-cells 3984 #clock-cells = <1>;
4821 #phy-cells = 3985 #phy-cells = <0>;
4822 3986
4823 clocks = <&di 3987 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 3988 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 3989 clock-names = "iface", "ref";
4826 3990
4827 status = "dis 3991 status = "disabled";
4828 }; 3992 };
4829 }; 3993 };
4830 3994
4831 gpu: gpu@5000000 { 3995 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 3996 compatible = "qcom,adreno-630.2", "qcom,adreno";
>> 3997 #stream-id-cells = <16>;
4833 3998
4834 reg = <0 0x05000000 0 !! 3999 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4000 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4001
4837 /* 4002 /*
4838 * Look ma, no clocks 4003 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4004 * controlled entirely by the GMU
4840 */ 4005 */
4841 4006
4842 interrupts = <GIC_SPI 4007 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4008
4844 iommus = <&adreno_smm 4009 iommus = <&adreno_smmu 0>;
4845 4010
4846 operating-points-v2 = 4011 operating-points-v2 = <&gpu_opp_table>;
4847 4012
4848 qcom,gmu = <&gmu>; 4013 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4014
4851 interconnects = <&mem !! 4015 interconnects = <&mem_noc MASTER_GFX3D &mem_noc SLAVE_EBI1>;
4852 interconnect-names = 4016 interconnect-names = "gfx-mem";
4853 4017
4854 status = "disabled"; <<
4855 <<
4856 gpu_opp_table: opp-ta 4018 gpu_opp_table: opp-table {
4857 compatible = 4019 compatible = "operating-points-v2";
4858 4020
4859 opp-710000000 4021 opp-710000000 {
4860 opp-h 4022 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4023 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4024 opp-peak-kBps = <7216000>;
4863 }; 4025 };
4864 4026
4865 opp-675000000 4027 opp-675000000 {
4866 opp-h 4028 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4029 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4030 opp-peak-kBps = <7216000>;
4869 }; 4031 };
4870 4032
4871 opp-596000000 4033 opp-596000000 {
4872 opp-h 4034 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4035 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4036 opp-peak-kBps = <6220000>;
4875 }; 4037 };
4876 4038
4877 opp-520000000 4039 opp-520000000 {
4878 opp-h 4040 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4041 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4042 opp-peak-kBps = <6220000>;
4881 }; 4043 };
4882 4044
4883 opp-414000000 4045 opp-414000000 {
4884 opp-h 4046 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4047 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4048 opp-peak-kBps = <4068000>;
4887 }; 4049 };
4888 4050
4889 opp-342000000 4051 opp-342000000 {
4890 opp-h 4052 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4053 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4054 opp-peak-kBps = <2724000>;
4893 }; 4055 };
4894 4056
4895 opp-257000000 4057 opp-257000000 {
4896 opp-h 4058 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4059 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4060 opp-peak-kBps = <1648000>;
4899 }; 4061 };
4900 }; 4062 };
4901 }; 4063 };
4902 4064
4903 adreno_smmu: iommu@5040000 { 4065 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd !! 4066 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4067 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4068 #iommu-cells = <1>;
4907 #global-interrupts = 4069 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4070 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4071 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4072 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4073 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4074 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4075 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4076 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4077 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4078 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4079 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4080 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4081 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4082 clock-names = "bus", "iface";
4921 4083
4922 power-domains = <&gpu 4084 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4085 };
4924 4086
4925 gmu: gmu@506a000 { 4087 gmu: gmu@506a000 {
4926 compatible = "qcom,ad !! 4088 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4089
4928 reg = <0 0x0506a000 0 !! 4090 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4091 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4092 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4093 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4094
4933 interrupts = <GIC_SPI 4095 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4096 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4097 interrupt-names = "hfi", "gmu";
4936 4098
4937 clocks = <&gpucc GPU_ 4099 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4100 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4101 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4102 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4103 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4104
4943 power-domains = <&gpu 4105 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4106 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4107 power-domain-names = "cx", "gx";
4946 4108
4947 iommus = <&adreno_smm 4109 iommus = <&adreno_smmu 5>;
4948 4110
4949 operating-points-v2 = 4111 operating-points-v2 = <&gmu_opp_table>;
4950 4112
4951 status = "disabled"; <<
4952 <<
4953 gmu_opp_table: opp-ta 4113 gmu_opp_table: opp-table {
4954 compatible = 4114 compatible = "operating-points-v2";
4955 4115
4956 opp-400000000 4116 opp-400000000 {
4957 opp-h 4117 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4118 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4119 };
4960 4120
4961 opp-200000000 4121 opp-200000000 {
4962 opp-h 4122 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4123 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4124 };
4965 }; 4125 };
4966 }; 4126 };
4967 4127
4968 dispcc: clock-controller@af00 4128 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4129 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4130 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4131 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4132 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4133 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4134 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4135 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4136 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4137 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4138 <0>,
4979 <&usb_1_qmpp !! 4139 <0>;
4980 clock-names = "bi_tcx 4140 clock-names = "bi_tcxo",
4981 "gcc_di 4141 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4142 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4143 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4144 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4145 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4146 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4147 "dp_link_clk_divsel_ten",
4988 "dp_vco 4148 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4149 #clock-cells = <1>;
4990 #reset-cells = <1>; 4150 #reset-cells = <1>;
4991 #power-domain-cells = 4151 #power-domain-cells = <1>;
4992 }; 4152 };
4993 4153
4994 pdc_intc: interrupt-controlle 4154 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4155 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4156 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4157 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4158 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4159 interrupt-parent = <&intc>;
5000 interrupt-controller; 4160 interrupt-controller;
5001 }; 4161 };
5002 4162
5003 pdc_reset: reset-controller@b 4163 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4164 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4165 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4166 #reset-cells = <1>;
5007 }; 4167 };
5008 4168
5009 tsens0: thermal-sensor@c26300 4169 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4170 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4171 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4172 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4173 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4174 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4175 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4176 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4177 #thermal-sensor-cells = <1>;
5018 }; 4178 };
5019 4179
5020 tsens1: thermal-sensor@c26500 4180 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4181 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4182 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4183 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4184 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4185 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4186 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4187 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4188 #thermal-sensor-cells = <1>;
5029 }; 4189 };
5030 4190
5031 aoss_reset: reset-controller@ 4191 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4192 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4193 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4194 #reset-cells = <1>;
5035 }; 4195 };
5036 4196
5037 aoss_qmp: power-management@c3 !! 4197 aoss_qmp: qmp@c300000 {
5038 compatible = "qcom,sd !! 4198 compatible = "qcom,sdm845-aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 4199 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 4200 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4201 mboxes = <&apss_shared 0>;
5042 4202
5043 #clock-cells = <0>; 4203 #clock-cells = <0>;
>> 4204 #power-domain-cells = <1>;
5044 4205
5045 cx_cdev: cx { 4206 cx_cdev: cx {
5046 #cooling-cell 4207 #cooling-cells = <2>;
5047 }; 4208 };
5048 4209
5049 ebi_cdev: ebi { 4210 ebi_cdev: ebi {
5050 #cooling-cell 4211 #cooling-cells = <2>;
5051 }; 4212 };
5052 }; 4213 };
5053 4214
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 4215 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4216 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4217 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4218 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4219 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4220 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4221 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 4222 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 4223 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 4224 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 4225 qcom,ee = <0>;
5070 qcom,channel = <0>; 4226 qcom,channel = <0>;
5071 #address-cells = <2>; 4227 #address-cells = <2>;
5072 #size-cells = <0>; 4228 #size-cells = <0>;
5073 interrupt-controller; 4229 interrupt-controller;
5074 #interrupt-cells = <4 4230 #interrupt-cells = <4>;
>> 4231 cell-index = <0>;
5075 }; 4232 };
5076 4233
5077 sram@146bf000 { !! 4234 imem@146bf000 {
5078 compatible = "qcom,sd !! 4235 compatible = "simple-mfd";
5079 reg = <0 0x146bf000 0 4236 reg = <0 0x146bf000 0 0x1000>;
5080 4237
5081 #address-cells = <1>; 4238 #address-cells = <1>;
5082 #size-cells = <1>; 4239 #size-cells = <1>;
5083 4240
5084 ranges = <0 0 0x146bf 4241 ranges = <0 0 0x146bf000 0x1000>;
5085 4242
5086 pil-reloc@94c { 4243 pil-reloc@94c {
5087 compatible = 4244 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 4245 reg = <0x94c 0xc8>;
5089 }; 4246 };
5090 }; 4247 };
5091 4248
5092 apps_smmu: iommu@15000000 { 4249 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 4250 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 4251 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 4252 #iommu-cells = <2>;
5096 #global-interrupts = 4253 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 4254 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 4255 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 4256 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 4257 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 4258 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 4259 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 4260 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 4261 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 4262 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 4263 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4264 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4265 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 4266 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 4267 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 4268 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 4269 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 4270 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 4271 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 4272 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 4273 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 4274 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 4275 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 4276 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 4277 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 4278 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 4279 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 4280 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 4281 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 4282 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 4283 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 4284 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 4285 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 4286 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 4287 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 4288 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4289 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 4290 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 4291 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 4292 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 4293 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 4294 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4295 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 4296 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 4297 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 4298 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 4299 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 4300 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4301 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 4302 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 4303 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 4304 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 4305 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 4306 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 4307 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 4308 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 4309 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 4310 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 4311 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 4312 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 4313 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 4314 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 4315 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 4316 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 4317 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 4318 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 4319 };
5163 4320
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 4321 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 4322 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 4323 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 4324 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 4325 #clock-cells = <1>;
5241 status = "disabled"; 4326 status = "disabled";
5242 }; 4327 };
5243 4328
5244 gladiator_noc: interconnect@1 4329 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 4330 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 4331 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = !! 4332 #interconnect-cells = <1>;
5248 qcom,bcm-voters = <&a 4333 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 4334 };
5250 4335
5251 watchdog@17980000 { 4336 watchdog@17980000 {
5252 compatible = "qcom,ap 4337 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 4338 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 4339 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI <<
5256 }; 4340 };
5257 4341
5258 apss_shared: mailbox@17990000 4342 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 4343 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 4344 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 4345 #mbox-cells = <1>;
5262 }; 4346 };
5263 4347
5264 apps_rsc: rsc@179c0000 { 4348 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 4349 label = "apps_rsc";
5266 compatible = "qcom,rp 4350 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 4351 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 4352 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 4353 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 4354 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 4355 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 4356 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 4357 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 4358 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 4359 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 4360 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 4361 <SLEEP_TCS 3>,
5278 <WA 4362 <WAKE_TCS 3>,
5279 <CO 4363 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 4364
5282 apps_bcm_voter: bcm-v 4365 apps_bcm_voter: bcm-voter {
5283 compatible = 4366 compatible = "qcom,bcm-voter";
5284 }; 4367 };
5285 4368
5286 rpmhcc: clock-control 4369 rpmhcc: clock-controller {
5287 compatible = 4370 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 4371 #clock-cells = <1>;
5289 clock-names = 4372 clock-names = "xo";
5290 clocks = <&xo 4373 clocks = <&xo_board>;
5291 }; 4374 };
5292 4375
5293 rpmhpd: power-control 4376 rpmhpd: power-controller {
5294 compatible = 4377 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 4378 #power-domain-cells = <1>;
5296 operating-poi 4379 operating-points-v2 = <&rpmhpd_opp_table>;
5297 4380
5298 rpmhpd_opp_ta 4381 rpmhpd_opp_table: opp-table {
5299 compa 4382 compatible = "operating-points-v2";
5300 4383
5301 rpmhp 4384 rpmhpd_opp_ret: opp1 {
5302 4385 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 4386 };
5304 4387
5305 rpmhp 4388 rpmhpd_opp_min_svs: opp2 {
5306 4389 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 4390 };
5308 4391
5309 rpmhp 4392 rpmhpd_opp_low_svs: opp3 {
5310 4393 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 4394 };
5312 4395
5313 rpmhp 4396 rpmhpd_opp_svs: opp4 {
5314 4397 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 4398 };
5316 4399
5317 rpmhp 4400 rpmhpd_opp_svs_l1: opp5 {
5318 4401 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 4402 };
5320 4403
5321 rpmhp 4404 rpmhpd_opp_nom: opp6 {
5322 4405 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 4406 };
5324 4407
5325 rpmhp 4408 rpmhpd_opp_nom_l1: opp7 {
5326 4409 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 4410 };
5328 4411
5329 rpmhp 4412 rpmhpd_opp_nom_l2: opp8 {
5330 4413 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 4414 };
5332 4415
5333 rpmhp 4416 rpmhpd_opp_turbo: opp9 {
5334 4417 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 4418 };
5336 4419
5337 rpmhp 4420 rpmhpd_opp_turbo_l1: opp10 {
5338 4421 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 4422 };
5340 }; 4423 };
5341 }; 4424 };
5342 }; 4425 };
5343 4426
5344 intc: interrupt-controller@17 4427 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 4428 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 4429 #address-cells = <2>;
5347 #size-cells = <2>; 4430 #size-cells = <2>;
5348 ranges; 4431 ranges;
5349 #interrupt-cells = <3 4432 #interrupt-cells = <3>;
5350 interrupt-controller; 4433 interrupt-controller;
5351 reg = <0 0x17a00000 0 4434 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 4435 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 4436 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 4437
5355 msi-controller@17a400 4438 msi-controller@17a40000 {
5356 compatible = 4439 compatible = "arm,gic-v3-its";
5357 msi-controlle 4440 msi-controller;
5358 #msi-cells = 4441 #msi-cells = <1>;
5359 reg = <0 0x17 4442 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 4443 status = "disabled";
5361 }; 4444 };
5362 }; 4445 };
5363 4446
5364 slimbam: dma-controller@17184 !! 4447 slimbam: dma@17184000 {
5365 compatible = "qcom,ba !! 4448 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 4449 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 4450 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; !! 4451 num-channels = <31>;
5369 interrupts = <GIC_SPI 4452 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 4453 #dma-cells = <1>;
5371 qcom,ee = <1>; 4454 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 4455 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 4456 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 4457 };
5375 4458
5376 timer@17c90000 { 4459 timer@17c90000 {
5377 #address-cells = <1>; !! 4460 #address-cells = <2>;
5378 #size-cells = <1>; !! 4461 #size-cells = <2>;
5379 ranges = <0 0 0 0x200 !! 4462 ranges;
5380 compatible = "arm,arm 4463 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 4464 reg = <0 0x17c90000 0 0x1000>;
5382 4465
5383 frame@17ca0000 { 4466 frame@17ca0000 {
5384 frame-number 4467 frame-number = <0>;
5385 interrupts = 4468 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 4469 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca !! 4470 reg = <0 0x17ca0000 0 0x1000>,
5388 <0x17cb !! 4471 <0 0x17cb0000 0 0x1000>;
5389 }; 4472 };
5390 4473
5391 frame@17cc0000 { 4474 frame@17cc0000 {
5392 frame-number 4475 frame-number = <1>;
5393 interrupts = 4476 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc !! 4477 reg = <0 0x17cc0000 0 0x1000>;
5395 status = "dis 4478 status = "disabled";
5396 }; 4479 };
5397 4480
5398 frame@17cd0000 { 4481 frame@17cd0000 {
5399 frame-number 4482 frame-number = <2>;
5400 interrupts = 4483 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd !! 4484 reg = <0 0x17cd0000 0 0x1000>;
5402 status = "dis 4485 status = "disabled";
5403 }; 4486 };
5404 4487
5405 frame@17ce0000 { 4488 frame@17ce0000 {
5406 frame-number 4489 frame-number = <3>;
5407 interrupts = 4490 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce !! 4491 reg = <0 0x17ce0000 0 0x1000>;
5409 status = "dis 4492 status = "disabled";
5410 }; 4493 };
5411 4494
5412 frame@17cf0000 { 4495 frame@17cf0000 {
5413 frame-number 4496 frame-number = <4>;
5414 interrupts = 4497 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf !! 4498 reg = <0 0x17cf0000 0 0x1000>;
5416 status = "dis 4499 status = "disabled";
5417 }; 4500 };
5418 4501
5419 frame@17d00000 { 4502 frame@17d00000 {
5420 frame-number 4503 frame-number = <5>;
5421 interrupts = 4504 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 !! 4505 reg = <0 0x17d00000 0 0x1000>;
5423 status = "dis 4506 status = "disabled";
5424 }; 4507 };
5425 4508
5426 frame@17d10000 { 4509 frame@17d10000 {
5427 frame-number 4510 frame-number = <6>;
5428 interrupts = 4511 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 !! 4512 reg = <0 0x17d10000 0 0x1000>;
5430 status = "dis 4513 status = "disabled";
5431 }; 4514 };
5432 }; 4515 };
5433 4516
5434 osm_l3: interconnect@17d41000 4517 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 4518 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 4519 reg = <0 0x17d41000 0 0x1400>;
5437 4520
5438 clocks = <&rpmhcc RPM 4521 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 4522 clock-names = "xo", "alternate";
5440 4523
5441 #interconnect-cells = 4524 #interconnect-cells = <1>;
5442 }; 4525 };
5443 4526
5444 cpufreq_hw: cpufreq@17d43000 4527 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 4528 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 4529 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 4530 reg-names = "freq-domain0", "freq-domain1";
5448 4531
5449 interrupts-extended = <<
5450 <<
5451 clocks = <&rpmhcc RPM 4532 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 4533 clock-names = "xo", "alternate";
5453 4534
5454 #freq-domain-cells = 4535 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 4536 };
5457 4537
5458 wifi: wifi@18800000 { 4538 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 4539 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 4540 status = "disabled";
5461 reg = <0 0x18800000 0 4541 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 4542 reg-names = "membase";
5463 memory-region = <&wla 4543 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 4544 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 4545 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 4546 interrupts =
5467 <GIC_SPI 414 4547 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 4548 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 4549 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 4550 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 4551 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 4552 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 4553 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 4554 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 4555 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 4556 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 4557 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 4558 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 4559 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 4560 };
5481 }; 4561 };
5482 4562
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 4563 thermal-zones {
5487 cpu0-thermal { 4564 cpu0-thermal {
5488 polling-delay-passive 4565 polling-delay-passive = <250>;
>> 4566 polling-delay = <1000>;
5489 4567
5490 thermal-sensors = <&t 4568 thermal-sensors = <&tsens0 1>;
5491 4569
5492 trips { 4570 trips {
5493 cpu0_alert0: 4571 cpu0_alert0: trip-point0 {
5494 tempe 4572 temperature = <90000>;
5495 hyste 4573 hysteresis = <2000>;
5496 type 4574 type = "passive";
5497 }; 4575 };
5498 4576
5499 cpu0_alert1: 4577 cpu0_alert1: trip-point1 {
5500 tempe 4578 temperature = <95000>;
5501 hyste 4579 hysteresis = <2000>;
5502 type 4580 type = "passive";
5503 }; 4581 };
5504 4582
5505 cpu0_crit: cp !! 4583 cpu0_crit: cpu_crit {
5506 tempe 4584 temperature = <110000>;
5507 hyste 4585 hysteresis = <1000>;
5508 type 4586 type = "critical";
5509 }; 4587 };
5510 }; 4588 };
>> 4589
>> 4590 cooling-maps {
>> 4591 map0 {
>> 4592 trip = <&cpu0_alert0>;
>> 4593 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4594 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4595 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4596 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4597 };
>> 4598 map1 {
>> 4599 trip = <&cpu0_alert1>;
>> 4600 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4601 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4602 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4603 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4604 };
>> 4605 };
5511 }; 4606 };
5512 4607
5513 cpu1-thermal { 4608 cpu1-thermal {
5514 polling-delay-passive 4609 polling-delay-passive = <250>;
>> 4610 polling-delay = <1000>;
5515 4611
5516 thermal-sensors = <&t 4612 thermal-sensors = <&tsens0 2>;
5517 4613
5518 trips { 4614 trips {
5519 cpu1_alert0: 4615 cpu1_alert0: trip-point0 {
5520 tempe 4616 temperature = <90000>;
5521 hyste 4617 hysteresis = <2000>;
5522 type 4618 type = "passive";
5523 }; 4619 };
5524 4620
5525 cpu1_alert1: 4621 cpu1_alert1: trip-point1 {
5526 tempe 4622 temperature = <95000>;
5527 hyste 4623 hysteresis = <2000>;
5528 type 4624 type = "passive";
5529 }; 4625 };
5530 4626
5531 cpu1_crit: cp !! 4627 cpu1_crit: cpu_crit {
5532 tempe 4628 temperature = <110000>;
5533 hyste 4629 hysteresis = <1000>;
5534 type 4630 type = "critical";
5535 }; 4631 };
5536 }; 4632 };
>> 4633
>> 4634 cooling-maps {
>> 4635 map0 {
>> 4636 trip = <&cpu1_alert0>;
>> 4637 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4638 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4639 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4640 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4641 };
>> 4642 map1 {
>> 4643 trip = <&cpu1_alert1>;
>> 4644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4645 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4646 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4647 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4648 };
>> 4649 };
5537 }; 4650 };
5538 4651
5539 cpu2-thermal { 4652 cpu2-thermal {
5540 polling-delay-passive 4653 polling-delay-passive = <250>;
>> 4654 polling-delay = <1000>;
5541 4655
5542 thermal-sensors = <&t 4656 thermal-sensors = <&tsens0 3>;
5543 4657
5544 trips { 4658 trips {
5545 cpu2_alert0: 4659 cpu2_alert0: trip-point0 {
5546 tempe 4660 temperature = <90000>;
5547 hyste 4661 hysteresis = <2000>;
5548 type 4662 type = "passive";
5549 }; 4663 };
5550 4664
5551 cpu2_alert1: 4665 cpu2_alert1: trip-point1 {
5552 tempe 4666 temperature = <95000>;
5553 hyste 4667 hysteresis = <2000>;
5554 type 4668 type = "passive";
5555 }; 4669 };
5556 4670
5557 cpu2_crit: cp !! 4671 cpu2_crit: cpu_crit {
5558 tempe 4672 temperature = <110000>;
5559 hyste 4673 hysteresis = <1000>;
5560 type 4674 type = "critical";
5561 }; 4675 };
5562 }; 4676 };
>> 4677
>> 4678 cooling-maps {
>> 4679 map0 {
>> 4680 trip = <&cpu2_alert0>;
>> 4681 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4682 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4683 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4684 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4685 };
>> 4686 map1 {
>> 4687 trip = <&cpu2_alert1>;
>> 4688 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4689 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4690 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4691 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4692 };
>> 4693 };
5563 }; 4694 };
5564 4695
5565 cpu3-thermal { 4696 cpu3-thermal {
5566 polling-delay-passive 4697 polling-delay-passive = <250>;
>> 4698 polling-delay = <1000>;
5567 4699
5568 thermal-sensors = <&t 4700 thermal-sensors = <&tsens0 4>;
5569 4701
5570 trips { 4702 trips {
5571 cpu3_alert0: 4703 cpu3_alert0: trip-point0 {
5572 tempe 4704 temperature = <90000>;
5573 hyste 4705 hysteresis = <2000>;
5574 type 4706 type = "passive";
5575 }; 4707 };
5576 4708
5577 cpu3_alert1: 4709 cpu3_alert1: trip-point1 {
5578 tempe 4710 temperature = <95000>;
5579 hyste 4711 hysteresis = <2000>;
5580 type 4712 type = "passive";
5581 }; 4713 };
5582 4714
5583 cpu3_crit: cp !! 4715 cpu3_crit: cpu_crit {
5584 tempe 4716 temperature = <110000>;
5585 hyste 4717 hysteresis = <1000>;
5586 type 4718 type = "critical";
5587 }; 4719 };
5588 }; 4720 };
>> 4721
>> 4722 cooling-maps {
>> 4723 map0 {
>> 4724 trip = <&cpu3_alert0>;
>> 4725 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4726 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4727 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4728 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4729 };
>> 4730 map1 {
>> 4731 trip = <&cpu3_alert1>;
>> 4732 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4733 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4734 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4735 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4736 };
>> 4737 };
5589 }; 4738 };
5590 4739
5591 cpu4-thermal { 4740 cpu4-thermal {
5592 polling-delay-passive 4741 polling-delay-passive = <250>;
>> 4742 polling-delay = <1000>;
5593 4743
5594 thermal-sensors = <&t 4744 thermal-sensors = <&tsens0 7>;
5595 4745
5596 trips { 4746 trips {
5597 cpu4_alert0: 4747 cpu4_alert0: trip-point0 {
5598 tempe 4748 temperature = <90000>;
5599 hyste 4749 hysteresis = <2000>;
5600 type 4750 type = "passive";
5601 }; 4751 };
5602 4752
5603 cpu4_alert1: 4753 cpu4_alert1: trip-point1 {
5604 tempe 4754 temperature = <95000>;
5605 hyste 4755 hysteresis = <2000>;
5606 type 4756 type = "passive";
5607 }; 4757 };
5608 4758
5609 cpu4_crit: cp !! 4759 cpu4_crit: cpu_crit {
5610 tempe 4760 temperature = <110000>;
5611 hyste 4761 hysteresis = <1000>;
5612 type 4762 type = "critical";
5613 }; 4763 };
5614 }; 4764 };
>> 4765
>> 4766 cooling-maps {
>> 4767 map0 {
>> 4768 trip = <&cpu4_alert0>;
>> 4769 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4771 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4772 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4773 };
>> 4774 map1 {
>> 4775 trip = <&cpu4_alert1>;
>> 4776 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4777 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4778 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4779 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4780 };
>> 4781 };
5615 }; 4782 };
5616 4783
5617 cpu5-thermal { 4784 cpu5-thermal {
5618 polling-delay-passive 4785 polling-delay-passive = <250>;
>> 4786 polling-delay = <1000>;
5619 4787
5620 thermal-sensors = <&t 4788 thermal-sensors = <&tsens0 8>;
5621 4789
5622 trips { 4790 trips {
5623 cpu5_alert0: 4791 cpu5_alert0: trip-point0 {
5624 tempe 4792 temperature = <90000>;
5625 hyste 4793 hysteresis = <2000>;
5626 type 4794 type = "passive";
5627 }; 4795 };
5628 4796
5629 cpu5_alert1: 4797 cpu5_alert1: trip-point1 {
5630 tempe 4798 temperature = <95000>;
5631 hyste 4799 hysteresis = <2000>;
5632 type 4800 type = "passive";
5633 }; 4801 };
5634 4802
5635 cpu5_crit: cp !! 4803 cpu5_crit: cpu_crit {
5636 tempe 4804 temperature = <110000>;
5637 hyste 4805 hysteresis = <1000>;
5638 type 4806 type = "critical";
5639 }; 4807 };
5640 }; 4808 };
>> 4809
>> 4810 cooling-maps {
>> 4811 map0 {
>> 4812 trip = <&cpu5_alert0>;
>> 4813 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4814 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4815 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4816 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4817 };
>> 4818 map1 {
>> 4819 trip = <&cpu5_alert1>;
>> 4820 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4821 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4822 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4823 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4824 };
>> 4825 };
5641 }; 4826 };
5642 4827
5643 cpu6-thermal { 4828 cpu6-thermal {
5644 polling-delay-passive 4829 polling-delay-passive = <250>;
>> 4830 polling-delay = <1000>;
5645 4831
5646 thermal-sensors = <&t 4832 thermal-sensors = <&tsens0 9>;
5647 4833
5648 trips { 4834 trips {
5649 cpu6_alert0: 4835 cpu6_alert0: trip-point0 {
5650 tempe 4836 temperature = <90000>;
5651 hyste 4837 hysteresis = <2000>;
5652 type 4838 type = "passive";
5653 }; 4839 };
5654 4840
5655 cpu6_alert1: 4841 cpu6_alert1: trip-point1 {
5656 tempe 4842 temperature = <95000>;
5657 hyste 4843 hysteresis = <2000>;
5658 type 4844 type = "passive";
5659 }; 4845 };
5660 4846
5661 cpu6_crit: cp !! 4847 cpu6_crit: cpu_crit {
5662 tempe 4848 temperature = <110000>;
5663 hyste 4849 hysteresis = <1000>;
5664 type 4850 type = "critical";
5665 }; 4851 };
5666 }; 4852 };
>> 4853
>> 4854 cooling-maps {
>> 4855 map0 {
>> 4856 trip = <&cpu6_alert0>;
>> 4857 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4858 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4859 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4860 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4861 };
>> 4862 map1 {
>> 4863 trip = <&cpu6_alert1>;
>> 4864 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4865 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4866 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4867 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4868 };
>> 4869 };
5667 }; 4870 };
5668 4871
5669 cpu7-thermal { 4872 cpu7-thermal {
5670 polling-delay-passive 4873 polling-delay-passive = <250>;
>> 4874 polling-delay = <1000>;
5671 4875
5672 thermal-sensors = <&t 4876 thermal-sensors = <&tsens0 10>;
5673 4877
5674 trips { 4878 trips {
5675 cpu7_alert0: 4879 cpu7_alert0: trip-point0 {
5676 tempe 4880 temperature = <90000>;
5677 hyste 4881 hysteresis = <2000>;
5678 type 4882 type = "passive";
5679 }; 4883 };
5680 4884
5681 cpu7_alert1: 4885 cpu7_alert1: trip-point1 {
5682 tempe 4886 temperature = <95000>;
5683 hyste 4887 hysteresis = <2000>;
5684 type 4888 type = "passive";
5685 }; 4889 };
5686 4890
5687 cpu7_crit: cp !! 4891 cpu7_crit: cpu_crit {
5688 tempe 4892 temperature = <110000>;
5689 hyste 4893 hysteresis = <1000>;
5690 type 4894 type = "critical";
5691 }; 4895 };
5692 }; 4896 };
>> 4897
>> 4898 cooling-maps {
>> 4899 map0 {
>> 4900 trip = <&cpu7_alert0>;
>> 4901 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4902 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4903 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4904 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4905 };
>> 4906 map1 {
>> 4907 trip = <&cpu7_alert1>;
>> 4908 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4910 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
>> 4911 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 4912 };
>> 4913 };
5693 }; 4914 };
5694 4915
5695 aoss0-thermal { 4916 aoss0-thermal {
5696 polling-delay-passive 4917 polling-delay-passive = <250>;
>> 4918 polling-delay = <1000>;
5697 4919
5698 thermal-sensors = <&t 4920 thermal-sensors = <&tsens0 0>;
5699 4921
5700 trips { 4922 trips {
5701 aoss0_alert0: 4923 aoss0_alert0: trip-point0 {
5702 tempe 4924 temperature = <90000>;
5703 hyste 4925 hysteresis = <2000>;
5704 type 4926 type = "hot";
5705 }; 4927 };
5706 }; 4928 };
5707 }; 4929 };
5708 4930
5709 cluster0-thermal { 4931 cluster0-thermal {
5710 polling-delay-passive 4932 polling-delay-passive = <250>;
>> 4933 polling-delay = <1000>;
5711 4934
5712 thermal-sensors = <&t 4935 thermal-sensors = <&tsens0 5>;
5713 4936
5714 trips { 4937 trips {
5715 cluster0_aler 4938 cluster0_alert0: trip-point0 {
5716 tempe 4939 temperature = <90000>;
5717 hyste 4940 hysteresis = <2000>;
5718 type 4941 type = "hot";
5719 }; 4942 };
5720 cluster0_crit !! 4943 cluster0_crit: cluster0_crit {
5721 tempe 4944 temperature = <110000>;
5722 hyste 4945 hysteresis = <2000>;
5723 type 4946 type = "critical";
5724 }; 4947 };
5725 }; 4948 };
5726 }; 4949 };
5727 4950
5728 cluster1-thermal { 4951 cluster1-thermal {
5729 polling-delay-passive 4952 polling-delay-passive = <250>;
>> 4953 polling-delay = <1000>;
5730 4954
5731 thermal-sensors = <&t 4955 thermal-sensors = <&tsens0 6>;
5732 4956
5733 trips { 4957 trips {
5734 cluster1_aler 4958 cluster1_alert0: trip-point0 {
5735 tempe 4959 temperature = <90000>;
5736 hyste 4960 hysteresis = <2000>;
5737 type 4961 type = "hot";
5738 }; 4962 };
5739 cluster1_crit !! 4963 cluster1_crit: cluster1_crit {
5740 tempe 4964 temperature = <110000>;
5741 hyste 4965 hysteresis = <2000>;
5742 type 4966 type = "critical";
5743 }; 4967 };
5744 }; 4968 };
5745 }; 4969 };
5746 4970
5747 gpu-top-thermal { !! 4971 gpu-thermal-top {
5748 polling-delay-passive 4972 polling-delay-passive = <250>;
>> 4973 polling-delay = <1000>;
5749 4974
5750 thermal-sensors = <&t 4975 thermal-sensors = <&tsens0 11>;
5751 4976
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 4977 trips {
5760 gpu_top_alert !! 4978 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 4979 temperature = <90000>;
5768 hyste !! 4980 hysteresis = <2000>;
5769 type 4981 type = "hot";
5770 }; 4982 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 4983 };
5778 }; 4984 };
5779 4985
5780 gpu-bottom-thermal { !! 4986 gpu-thermal-bottom {
5781 polling-delay-passive 4987 polling-delay-passive = <250>;
>> 4988 polling-delay = <1000>;
5782 4989
5783 thermal-sensors = <&t 4990 thermal-sensors = <&tsens0 12>;
5784 4991
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 4992 trips {
5793 gpu_bottom_al !! 4993 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 4994 temperature = <90000>;
5801 hyste !! 4995 hysteresis = <2000>;
5802 type 4996 type = "hot";
5803 }; 4997 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 4998 };
5811 }; 4999 };
5812 5000
5813 aoss1-thermal { 5001 aoss1-thermal {
5814 polling-delay-passive 5002 polling-delay-passive = <250>;
>> 5003 polling-delay = <1000>;
5815 5004
5816 thermal-sensors = <&t 5005 thermal-sensors = <&tsens1 0>;
5817 5006
5818 trips { 5007 trips {
5819 aoss1_alert0: 5008 aoss1_alert0: trip-point0 {
5820 tempe 5009 temperature = <90000>;
5821 hyste 5010 hysteresis = <2000>;
5822 type 5011 type = "hot";
5823 }; 5012 };
5824 }; 5013 };
5825 }; 5014 };
5826 5015
5827 q6-modem-thermal { 5016 q6-modem-thermal {
5828 polling-delay-passive 5017 polling-delay-passive = <250>;
>> 5018 polling-delay = <1000>;
5829 5019
5830 thermal-sensors = <&t 5020 thermal-sensors = <&tsens1 1>;
5831 5021
5832 trips { 5022 trips {
5833 q6_modem_aler 5023 q6_modem_alert0: trip-point0 {
5834 tempe 5024 temperature = <90000>;
5835 hyste 5025 hysteresis = <2000>;
5836 type 5026 type = "hot";
5837 }; 5027 };
5838 }; 5028 };
5839 }; 5029 };
5840 5030
5841 mem-thermal { 5031 mem-thermal {
5842 polling-delay-passive 5032 polling-delay-passive = <250>;
>> 5033 polling-delay = <1000>;
5843 5034
5844 thermal-sensors = <&t 5035 thermal-sensors = <&tsens1 2>;
5845 5036
5846 trips { 5037 trips {
5847 mem_alert0: t 5038 mem_alert0: trip-point0 {
5848 tempe 5039 temperature = <90000>;
5849 hyste 5040 hysteresis = <2000>;
5850 type 5041 type = "hot";
5851 }; 5042 };
5852 }; 5043 };
5853 }; 5044 };
5854 5045
5855 wlan-thermal { 5046 wlan-thermal {
5856 polling-delay-passive 5047 polling-delay-passive = <250>;
>> 5048 polling-delay = <1000>;
5857 5049
5858 thermal-sensors = <&t 5050 thermal-sensors = <&tsens1 3>;
5859 5051
5860 trips { 5052 trips {
5861 wlan_alert0: 5053 wlan_alert0: trip-point0 {
5862 tempe 5054 temperature = <90000>;
5863 hyste 5055 hysteresis = <2000>;
5864 type 5056 type = "hot";
5865 }; 5057 };
5866 }; 5058 };
5867 }; 5059 };
5868 5060
5869 q6-hvx-thermal { 5061 q6-hvx-thermal {
5870 polling-delay-passive 5062 polling-delay-passive = <250>;
>> 5063 polling-delay = <1000>;
5871 5064
5872 thermal-sensors = <&t 5065 thermal-sensors = <&tsens1 4>;
5873 5066
5874 trips { 5067 trips {
5875 q6_hvx_alert0 5068 q6_hvx_alert0: trip-point0 {
5876 tempe 5069 temperature = <90000>;
5877 hyste 5070 hysteresis = <2000>;
5878 type 5071 type = "hot";
5879 }; 5072 };
5880 }; 5073 };
5881 }; 5074 };
5882 5075
5883 camera-thermal { 5076 camera-thermal {
5884 polling-delay-passive 5077 polling-delay-passive = <250>;
>> 5078 polling-delay = <1000>;
5885 5079
5886 thermal-sensors = <&t 5080 thermal-sensors = <&tsens1 5>;
5887 5081
5888 trips { 5082 trips {
5889 camera_alert0 5083 camera_alert0: trip-point0 {
5890 tempe 5084 temperature = <90000>;
5891 hyste 5085 hysteresis = <2000>;
5892 type 5086 type = "hot";
5893 }; 5087 };
5894 }; 5088 };
5895 }; 5089 };
5896 5090
5897 video-thermal { 5091 video-thermal {
5898 polling-delay-passive 5092 polling-delay-passive = <250>;
>> 5093 polling-delay = <1000>;
5899 5094
5900 thermal-sensors = <&t 5095 thermal-sensors = <&tsens1 6>;
5901 5096
5902 trips { 5097 trips {
5903 video_alert0: 5098 video_alert0: trip-point0 {
5904 tempe 5099 temperature = <90000>;
5905 hyste 5100 hysteresis = <2000>;
5906 type 5101 type = "hot";
5907 }; 5102 };
5908 }; 5103 };
5909 }; 5104 };
5910 5105
5911 modem-thermal { 5106 modem-thermal {
5912 polling-delay-passive 5107 polling-delay-passive = <250>;
>> 5108 polling-delay = <1000>;
5913 5109
5914 thermal-sensors = <&t 5110 thermal-sensors = <&tsens1 7>;
5915 5111
5916 trips { 5112 trips {
5917 modem_alert0: 5113 modem_alert0: trip-point0 {
5918 tempe 5114 temperature = <90000>;
5919 hyste 5115 hysteresis = <2000>;
5920 type 5116 type = "hot";
5921 }; 5117 };
5922 }; 5118 };
5923 }; 5119 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5120 };
5933 }; 5121 };
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