1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> 15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 18 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 19 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 21 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 24 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 27 #include <dt-bindings/thermal/thermal.h>
31 28
32 / { 29 / {
33 interrupt-parent = <&intc>; 30 interrupt-parent = <&intc>;
34 31
35 #address-cells = <2>; 32 #address-cells = <2>;
36 #size-cells = <2>; 33 #size-cells = <2>;
37 34
38 aliases { 35 aliases {
39 i2c0 = &i2c0; 36 i2c0 = &i2c0;
40 i2c1 = &i2c1; 37 i2c1 = &i2c1;
41 i2c2 = &i2c2; 38 i2c2 = &i2c2;
42 i2c3 = &i2c3; 39 i2c3 = &i2c3;
43 i2c4 = &i2c4; 40 i2c4 = &i2c4;
44 i2c5 = &i2c5; 41 i2c5 = &i2c5;
45 i2c6 = &i2c6; 42 i2c6 = &i2c6;
46 i2c7 = &i2c7; 43 i2c7 = &i2c7;
47 i2c8 = &i2c8; 44 i2c8 = &i2c8;
48 i2c9 = &i2c9; 45 i2c9 = &i2c9;
49 i2c10 = &i2c10; 46 i2c10 = &i2c10;
50 i2c11 = &i2c11; 47 i2c11 = &i2c11;
51 i2c12 = &i2c12; 48 i2c12 = &i2c12;
52 i2c13 = &i2c13; 49 i2c13 = &i2c13;
53 i2c14 = &i2c14; 50 i2c14 = &i2c14;
54 i2c15 = &i2c15; 51 i2c15 = &i2c15;
55 spi0 = &spi0; 52 spi0 = &spi0;
56 spi1 = &spi1; 53 spi1 = &spi1;
57 spi2 = &spi2; 54 spi2 = &spi2;
58 spi3 = &spi3; 55 spi3 = &spi3;
59 spi4 = &spi4; 56 spi4 = &spi4;
60 spi5 = &spi5; 57 spi5 = &spi5;
61 spi6 = &spi6; 58 spi6 = &spi6;
62 spi7 = &spi7; 59 spi7 = &spi7;
63 spi8 = &spi8; 60 spi8 = &spi8;
64 spi9 = &spi9; 61 spi9 = &spi9;
65 spi10 = &spi10; 62 spi10 = &spi10;
66 spi11 = &spi11; 63 spi11 = &spi11;
67 spi12 = &spi12; 64 spi12 = &spi12;
68 spi13 = &spi13; 65 spi13 = &spi13;
69 spi14 = &spi14; 66 spi14 = &spi14;
70 spi15 = &spi15; 67 spi15 = &spi15;
71 }; 68 };
72 69
73 chosen { }; 70 chosen { };
74 71
75 clocks { !! 72 memory@80000000 {
76 xo_board: xo-board { !! 73 device_type = "memory";
77 compatible = "fixed-cl !! 74 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 75 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 76 };
80 clock-output-names = " !! 77
>> 78 reserved-memory {
>> 79 #address-cells = <2>;
>> 80 #size-cells = <2>;
>> 81 ranges;
>> 82
>> 83 hyp_mem: hyp-mem@85700000 {
>> 84 reg = <0 0x85700000 0 0x600000>;
>> 85 no-map;
81 }; 86 };
82 87
83 sleep_clk: sleep-clk { !! 88 xbl_mem: xbl-mem@85e00000 {
84 compatible = "fixed-cl !! 89 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 90 no-map;
86 clock-frequency = <327 !! 91 };
>> 92
>> 93 aop_mem: aop-mem@85fc0000 {
>> 94 reg = <0 0x85fc0000 0 0x20000>;
>> 95 no-map;
>> 96 };
>> 97
>> 98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
>> 99 compatible = "qcom,cmd-db";
>> 100 reg = <0x0 0x85fe0000 0 0x20000>;
>> 101 no-map;
>> 102 };
>> 103
>> 104 smem@86000000 {
>> 105 compatible = "qcom,smem";
>> 106 reg = <0x0 0x86000000 0 0x200000>;
>> 107 no-map;
>> 108 hwlocks = <&tcsr_mutex 3>;
>> 109 };
>> 110
>> 111 tz_mem: tz@86200000 {
>> 112 reg = <0 0x86200000 0 0x2d00000>;
>> 113 no-map;
>> 114 };
>> 115
>> 116 rmtfs_mem: rmtfs@88f00000 {
>> 117 compatible = "qcom,rmtfs-mem";
>> 118 reg = <0 0x88f00000 0 0x200000>;
>> 119 no-map;
>> 120
>> 121 qcom,client-id = <1>;
>> 122 qcom,vmid = <15>;
>> 123 };
>> 124
>> 125 qseecom_mem: qseecom@8ab00000 {
>> 126 reg = <0 0x8ab00000 0 0x1400000>;
>> 127 no-map;
>> 128 };
>> 129
>> 130 camera_mem: camera-mem@8bf00000 {
>> 131 reg = <0 0x8bf00000 0 0x500000>;
>> 132 no-map;
>> 133 };
>> 134
>> 135 ipa_fw_mem: ipa-fw@8c400000 {
>> 136 reg = <0 0x8c400000 0 0x10000>;
>> 137 no-map;
>> 138 };
>> 139
>> 140 ipa_gsi_mem: ipa-gsi@8c410000 {
>> 141 reg = <0 0x8c410000 0 0x5000>;
>> 142 no-map;
>> 143 };
>> 144
>> 145 gpu_mem: gpu@8c415000 {
>> 146 reg = <0 0x8c415000 0 0x2000>;
>> 147 no-map;
>> 148 };
>> 149
>> 150 adsp_mem: adsp@8c500000 {
>> 151 reg = <0 0x8c500000 0 0x1a00000>;
>> 152 no-map;
>> 153 };
>> 154
>> 155 wlan_msa_mem: wlan-msa@8df00000 {
>> 156 reg = <0 0x8df00000 0 0x100000>;
>> 157 no-map;
>> 158 };
>> 159
>> 160 mpss_region: mpss@8e000000 {
>> 161 reg = <0 0x8e000000 0 0x7800000>;
>> 162 no-map;
>> 163 };
>> 164
>> 165 venus_mem: venus@95800000 {
>> 166 reg = <0 0x95800000 0 0x500000>;
>> 167 no-map;
>> 168 };
>> 169
>> 170 cdsp_mem: cdsp@95d00000 {
>> 171 reg = <0 0x95d00000 0 0x800000>;
>> 172 no-map;
>> 173 };
>> 174
>> 175 mba_region: mba@96500000 {
>> 176 reg = <0 0x96500000 0 0x200000>;
>> 177 no-map;
>> 178 };
>> 179
>> 180 slpi_mem: slpi@96700000 {
>> 181 reg = <0 0x96700000 0 0x1400000>;
>> 182 no-map;
>> 183 };
>> 184
>> 185 spss_mem: spss@97b00000 {
>> 186 reg = <0 0x97b00000 0 0x100000>;
>> 187 no-map;
87 }; 188 };
88 }; 189 };
89 190
90 cpus: cpus { 191 cpus: cpus {
91 #address-cells = <2>; 192 #address-cells = <2>;
92 #size-cells = <0>; 193 #size-cells = <0>;
93 194
94 CPU0: cpu@0 { 195 CPU0: cpu@0 {
95 device_type = "cpu"; 196 device_type = "cpu";
96 compatible = "qcom,kry 197 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 198 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 199 enable-method = "psci";
100 capacity-dmips-mhz = < 200 capacity-dmips-mhz = <611>;
101 dynamic-power-coeffici !! 201 dynamic-power-coefficient = <290>;
102 qcom,freq-domain = <&c 202 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 203 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ 206 power-domains = <&CPU_PD0>;
107 power-domain-names = " 207 power-domain-names = "psci";
108 #cooling-cells = <2>; 208 #cooling-cells = <2>;
109 next-level-cache = <&L 209 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 210 L2_0: l2-cache {
111 compatible = " 211 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 212 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 213 L3_0: l3-cache {
116 compat !! 214 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 215 };
120 }; 216 };
121 }; 217 };
122 218
123 CPU1: cpu@100 { 219 CPU1: cpu@100 {
124 device_type = "cpu"; 220 device_type = "cpu";
125 compatible = "qcom,kry 221 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 222 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 223 enable-method = "psci";
129 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <611>;
130 dynamic-power-coeffici !! 225 dynamic-power-coefficient = <290>;
131 qcom,freq-domain = <&c 226 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 227 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ 230 power-domains = <&CPU_PD1>;
136 power-domain-names = " 231 power-domain-names = "psci";
137 #cooling-cells = <2>; 232 #cooling-cells = <2>;
138 next-level-cache = <&L 233 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 234 L2_100: l2-cache {
140 compatible = " 235 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 236 next-level-cache = <&L3_0>;
144 }; 237 };
145 }; 238 };
146 239
147 CPU2: cpu@200 { 240 CPU2: cpu@200 {
148 device_type = "cpu"; 241 device_type = "cpu";
149 compatible = "qcom,kry 242 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 243 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 244 enable-method = "psci";
153 capacity-dmips-mhz = < 245 capacity-dmips-mhz = <611>;
154 dynamic-power-coeffici !! 246 dynamic-power-coefficient = <290>;
155 qcom,freq-domain = <&c 247 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 248 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 249 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ 251 power-domains = <&CPU_PD2>;
160 power-domain-names = " 252 power-domain-names = "psci";
161 #cooling-cells = <2>; 253 #cooling-cells = <2>;
162 next-level-cache = <&L 254 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 255 L2_200: l2-cache {
164 compatible = " 256 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 257 next-level-cache = <&L3_0>;
168 }; 258 };
169 }; 259 };
170 260
171 CPU3: cpu@300 { 261 CPU3: cpu@300 {
172 device_type = "cpu"; 262 device_type = "cpu";
173 compatible = "qcom,kry 263 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 264 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 265 enable-method = "psci";
177 capacity-dmips-mhz = < 266 capacity-dmips-mhz = <611>;
178 dynamic-power-coeffici !! 267 dynamic-power-coefficient = <290>;
179 qcom,freq-domain = <&c 268 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 269 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 270 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 271 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 272 #cooling-cells = <2>;
184 power-domains = <&CPU_ 273 power-domains = <&CPU_PD3>;
185 power-domain-names = " 274 power-domain-names = "psci";
186 next-level-cache = <&L 275 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 276 L2_300: l2-cache {
188 compatible = " 277 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 278 next-level-cache = <&L3_0>;
192 }; 279 };
193 }; 280 };
194 281
195 CPU4: cpu@400 { 282 CPU4: cpu@400 {
196 device_type = "cpu"; 283 device_type = "cpu";
197 compatible = "qcom,kry 284 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 285 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 286 enable-method = "psci";
201 capacity-dmips-mhz = < 287 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici 288 dynamic-power-coefficient = <442>;
203 qcom,freq-domain = <&c 289 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 290 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 291 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 292 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ 293 power-domains = <&CPU_PD4>;
208 power-domain-names = " 294 power-domain-names = "psci";
209 #cooling-cells = <2>; 295 #cooling-cells = <2>;
210 next-level-cache = <&L 296 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 297 L2_400: l2-cache {
212 compatible = " 298 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 299 next-level-cache = <&L3_0>;
216 }; 300 };
217 }; 301 };
218 302
219 CPU5: cpu@500 { 303 CPU5: cpu@500 {
220 device_type = "cpu"; 304 device_type = "cpu";
221 compatible = "qcom,kry 305 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 306 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 307 enable-method = "psci";
225 capacity-dmips-mhz = < 308 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici 309 dynamic-power-coefficient = <442>;
227 qcom,freq-domain = <&c 310 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 311 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 312 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 313 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ 314 power-domains = <&CPU_PD5>;
232 power-domain-names = " 315 power-domain-names = "psci";
233 #cooling-cells = <2>; 316 #cooling-cells = <2>;
234 next-level-cache = <&L 317 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 318 L2_500: l2-cache {
236 compatible = " 319 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 320 next-level-cache = <&L3_0>;
240 }; 321 };
241 }; 322 };
242 323
243 CPU6: cpu@600 { 324 CPU6: cpu@600 {
244 device_type = "cpu"; 325 device_type = "cpu";
245 compatible = "qcom,kry 326 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 327 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 328 enable-method = "psci";
249 capacity-dmips-mhz = < 329 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici 330 dynamic-power-coefficient = <442>;
251 qcom,freq-domain = <&c 331 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 332 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ 335 power-domains = <&CPU_PD6>;
256 power-domain-names = " 336 power-domain-names = "psci";
257 #cooling-cells = <2>; 337 #cooling-cells = <2>;
258 next-level-cache = <&L 338 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 339 L2_600: l2-cache {
260 compatible = " 340 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 341 next-level-cache = <&L3_0>;
264 }; 342 };
265 }; 343 };
266 344
267 CPU7: cpu@700 { 345 CPU7: cpu@700 {
268 device_type = "cpu"; 346 device_type = "cpu";
269 compatible = "qcom,kry 347 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 348 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 349 enable-method = "psci";
273 capacity-dmips-mhz = < 350 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici 351 dynamic-power-coefficient = <442>;
275 qcom,freq-domain = <&c 352 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 353 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 354 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 355 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ 356 power-domains = <&CPU_PD7>;
280 power-domain-names = " 357 power-domain-names = "psci";
281 #cooling-cells = <2>; 358 #cooling-cells = <2>;
282 next-level-cache = <&L 359 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 360 L2_700: l2-cache {
284 compatible = " 361 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 362 next-level-cache = <&L3_0>;
288 }; 363 };
289 }; 364 };
290 365
291 cpu-map { 366 cpu-map {
292 cluster0 { 367 cluster0 {
293 core0 { 368 core0 {
294 cpu = 369 cpu = <&CPU0>;
295 }; 370 };
296 371
297 core1 { 372 core1 {
298 cpu = 373 cpu = <&CPU1>;
299 }; 374 };
300 375
301 core2 { 376 core2 {
302 cpu = 377 cpu = <&CPU2>;
303 }; 378 };
304 379
305 core3 { 380 core3 {
306 cpu = 381 cpu = <&CPU3>;
307 }; 382 };
308 383
309 core4 { 384 core4 {
310 cpu = 385 cpu = <&CPU4>;
311 }; 386 };
312 387
313 core5 { 388 core5 {
314 cpu = 389 cpu = <&CPU5>;
315 }; 390 };
316 391
317 core6 { 392 core6 {
318 cpu = 393 cpu = <&CPU6>;
319 }; 394 };
320 395
321 core7 { 396 core7 {
322 cpu = 397 cpu = <&CPU7>;
323 }; 398 };
324 }; 399 };
325 }; 400 };
326 401
327 cpu_idle_states: idle-states { 402 cpu_idle_states: idle-states {
328 entry-method = "psci"; 403 entry-method = "psci";
329 404
330 LITTLE_CPU_SLEEP_0: cp 405 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 406 compatible = "arm,idle-state";
332 idle-state-nam 407 idle-state-name = "little-rail-power-collapse";
333 arm,psci-suspe 408 arm,psci-suspend-param = <0x40000004>;
334 entry-latency- 409 entry-latency-us = <350>;
335 exit-latency-u 410 exit-latency-us = <461>;
336 min-residency- 411 min-residency-us = <1890>;
337 local-timer-st 412 local-timer-stop;
338 }; 413 };
339 414
340 BIG_CPU_SLEEP_0: cpu-s 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 compatible = " 416 compatible = "arm,idle-state";
342 idle-state-nam 417 idle-state-name = "big-rail-power-collapse";
343 arm,psci-suspe 418 arm,psci-suspend-param = <0x40000004>;
344 entry-latency- 419 entry-latency-us = <264>;
345 exit-latency-u 420 exit-latency-us = <621>;
346 min-residency- 421 min-residency-us = <952>;
347 local-timer-st 422 local-timer-stop;
348 }; 423 };
349 }; 424 };
350 425
351 domain-idle-states { 426 domain-idle-states {
352 CLUSTER_SLEEP_0: clust 427 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " 428 compatible = "domain-idle-state";
>> 429 idle-state-name = "cluster-power-collapse";
354 arm,psci-suspe 430 arm,psci-suspend-param = <0x4100c244>;
355 entry-latency- 431 entry-latency-us = <3263>;
356 exit-latency-u 432 exit-latency-us = <6562>;
357 min-residency- 433 min-residency-us = <9987>;
>> 434 local-timer-stop;
358 }; 435 };
359 }; 436 };
360 }; 437 };
361 438
362 firmware { <<
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { 439 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points 440 compatible = "operating-points-v2";
376 opp-shared; 441 opp-shared;
377 442
378 cpu0_opp1: opp-300000000 { 443 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 444 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 445 opp-peak-kBps = <800000 4800000>;
381 }; 446 };
382 447
383 cpu0_opp2: opp-403200000 { 448 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 449 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 450 opp-peak-kBps = <800000 4800000>;
386 }; 451 };
387 452
388 cpu0_opp3: opp-480000000 { 453 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 454 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 455 opp-peak-kBps = <800000 6451200>;
391 }; 456 };
392 457
393 cpu0_opp4: opp-576000000 { 458 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 459 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 460 opp-peak-kBps = <800000 6451200>;
396 }; 461 };
397 462
398 cpu0_opp5: opp-652800000 { 463 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 464 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 465 opp-peak-kBps = <800000 7680000>;
401 }; 466 };
402 467
403 cpu0_opp6: opp-748800000 { 468 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 469 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 470 opp-peak-kBps = <1804000 9216000>;
406 }; 471 };
407 472
408 cpu0_opp7: opp-825600000 { 473 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 474 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 475 opp-peak-kBps = <1804000 9216000>;
411 }; 476 };
412 477
413 cpu0_opp8: opp-902400000 { 478 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 479 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 480 opp-peak-kBps = <1804000 10444800>;
416 }; 481 };
417 482
418 cpu0_opp9: opp-979200000 { 483 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 484 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 485 opp-peak-kBps = <1804000 11980800>;
421 }; 486 };
422 487
423 cpu0_opp10: opp-1056000000 { 488 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 489 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 490 opp-peak-kBps = <1804000 11980800>;
426 }; 491 };
427 492
428 cpu0_opp11: opp-1132800000 { 493 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 494 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 495 opp-peak-kBps = <2188000 13516800>;
431 }; 496 };
432 497
433 cpu0_opp12: opp-1228800000 { 498 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 499 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 500 opp-peak-kBps = <2188000 15052800>;
436 }; 501 };
437 502
438 cpu0_opp13: opp-1324800000 { 503 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 504 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 505 opp-peak-kBps = <2188000 16588800>;
441 }; 506 };
442 507
443 cpu0_opp14: opp-1420800000 { 508 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 509 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 510 opp-peak-kBps = <3072000 18124800>;
446 }; 511 };
447 512
448 cpu0_opp15: opp-1516800000 { 513 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 514 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 515 opp-peak-kBps = <3072000 19353600>;
451 }; 516 };
452 517
453 cpu0_opp16: opp-1612800000 { 518 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 519 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 520 opp-peak-kBps = <4068000 19353600>;
456 }; 521 };
457 522
458 cpu0_opp17: opp-1689600000 { 523 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 524 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 525 opp-peak-kBps = <4068000 20889600>;
461 }; 526 };
462 527
463 cpu0_opp18: opp-1766400000 { 528 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 529 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 530 opp-peak-kBps = <4068000 22425600>;
466 }; 531 };
467 }; 532 };
468 533
469 cpu4_opp_table: opp-table-cpu4 { 534 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 535 compatible = "operating-points-v2";
471 opp-shared; 536 opp-shared;
472 537
473 cpu4_opp1: opp-300000000 { 538 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 539 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 540 opp-peak-kBps = <800000 4800000>;
476 }; 541 };
477 542
478 cpu4_opp2: opp-403200000 { 543 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 544 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 545 opp-peak-kBps = <800000 4800000>;
481 }; 546 };
482 547
483 cpu4_opp3: opp-480000000 { 548 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 549 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 550 opp-peak-kBps = <1804000 4800000>;
486 }; 551 };
487 552
488 cpu4_opp4: opp-576000000 { 553 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 554 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 555 opp-peak-kBps = <1804000 4800000>;
491 }; 556 };
492 557
493 cpu4_opp5: opp-652800000 { 558 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 559 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 560 opp-peak-kBps = <1804000 4800000>;
496 }; 561 };
497 562
498 cpu4_opp6: opp-748800000 { 563 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 564 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 565 opp-peak-kBps = <1804000 4800000>;
501 }; 566 };
502 567
503 cpu4_opp7: opp-825600000 { 568 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 569 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 570 opp-peak-kBps = <2188000 9216000>;
506 }; 571 };
507 572
508 cpu4_opp8: opp-902400000 { 573 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 574 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 575 opp-peak-kBps = <2188000 9216000>;
511 }; 576 };
512 577
513 cpu4_opp9: opp-979200000 { 578 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 579 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 580 opp-peak-kBps = <2188000 9216000>;
516 }; 581 };
517 582
518 cpu4_opp10: opp-1056000000 { 583 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 584 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 585 opp-peak-kBps = <3072000 9216000>;
521 }; 586 };
522 587
523 cpu4_opp11: opp-1132800000 { 588 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 589 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 590 opp-peak-kBps = <3072000 11980800>;
526 }; 591 };
527 592
528 cpu4_opp12: opp-1209600000 { 593 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 594 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 595 opp-peak-kBps = <4068000 11980800>;
531 }; 596 };
532 597
533 cpu4_opp13: opp-1286400000 { 598 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 599 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 600 opp-peak-kBps = <4068000 11980800>;
536 }; 601 };
537 602
538 cpu4_opp14: opp-1363200000 { 603 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 604 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 605 opp-peak-kBps = <4068000 15052800>;
541 }; 606 };
542 607
543 cpu4_opp15: opp-1459200000 { 608 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 609 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 610 opp-peak-kBps = <4068000 15052800>;
546 }; 611 };
547 612
548 cpu4_opp16: opp-1536000000 { 613 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 614 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 615 opp-peak-kBps = <5412000 15052800>;
551 }; 616 };
552 617
553 cpu4_opp17: opp-1612800000 { 618 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 619 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 620 opp-peak-kBps = <5412000 15052800>;
556 }; 621 };
557 622
558 cpu4_opp18: opp-1689600000 { 623 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 624 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 625 opp-peak-kBps = <5412000 19353600>;
561 }; 626 };
562 627
563 cpu4_opp19: opp-1766400000 { 628 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 629 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 630 opp-peak-kBps = <6220000 19353600>;
566 }; 631 };
567 632
568 cpu4_opp20: opp-1843200000 { 633 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 634 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 635 opp-peak-kBps = <6220000 19353600>;
571 }; 636 };
572 637
573 cpu4_opp21: opp-1920000000 { 638 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 639 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 640 opp-peak-kBps = <7216000 19353600>;
576 }; 641 };
577 642
578 cpu4_opp22: opp-1996800000 { 643 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 644 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 645 opp-peak-kBps = <7216000 20889600>;
581 }; 646 };
582 647
583 cpu4_opp23: opp-2092800000 { 648 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 649 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 650 opp-peak-kBps = <7216000 20889600>;
586 }; 651 };
587 652
588 cpu4_opp24: opp-2169600000 { 653 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 654 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 655 opp-peak-kBps = <7216000 20889600>;
591 }; 656 };
592 657
593 cpu4_opp25: opp-2246400000 { 658 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 659 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 660 opp-peak-kBps = <7216000 20889600>;
596 }; 661 };
597 662
598 cpu4_opp26: opp-2323200000 { 663 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 664 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 665 opp-peak-kBps = <7216000 20889600>;
601 }; 666 };
602 667
603 cpu4_opp27: opp-2400000000 { 668 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 669 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 670 opp-peak-kBps = <7216000 22425600>;
606 }; 671 };
607 672
608 cpu4_opp28: opp-2476800000 { 673 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 674 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 675 opp-peak-kBps = <7216000 22425600>;
611 }; 676 };
612 677
613 cpu4_opp29: opp-2553600000 { 678 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 679 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 680 opp-peak-kBps = <7216000 22425600>;
616 }; 681 };
617 682
618 cpu4_opp30: opp-2649600000 { 683 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 684 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 685 opp-peak-kBps = <7216000 22425600>;
621 }; 686 };
622 687
623 cpu4_opp31: opp-2745600000 { 688 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 689 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 690 opp-peak-kBps = <7216000 25497600>;
626 }; 691 };
627 692
628 cpu4_opp32: opp-2803200000 { 693 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 694 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 695 opp-peak-kBps = <7216000 25497600>;
631 }; 696 };
632 }; 697 };
633 698
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 699 pmu {
712 compatible = "arm,armv8-pmuv3" 700 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 701 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 702 };
715 703
716 psci: psci { !! 704 timer {
717 compatible = "arm,psci-1.0"; !! 705 compatible = "arm,armv8-timer";
718 method = "smc"; !! 706 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 707 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 708 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 709 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 710 };
773 711
774 reserved-memory { !! 712 clocks {
775 #address-cells = <2>; !! 713 xo_board: xo-board {
776 #size-cells = <2>; !! 714 compatible = "fixed-clock";
777 ranges; !! 715 #clock-cells = <0>;
778 !! 716 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 717 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 718 };
885 719
886 mdata_mem: mpss-metadata { !! 720 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 721 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 722 #clock-cells = <0>;
889 no-map; !! 723 clock-frequency = <32764>;
890 }; 724 };
>> 725 };
891 726
892 fastrpc_mem: fastrpc { !! 727 firmware {
893 compatible = "shared-d !! 728 scm {
894 alloc-ranges = <0x0 0x !! 729 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 730 };
899 }; 731 };
900 732
901 adsp_pas: remoteproc-adsp { 733 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 734 compatible = "qcom,sdm845-adsp-pas";
903 735
904 interrupts-extended = <&intc G 736 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 737 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 738 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 739 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 740 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 741 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 742 "handover", "stop-ack";
911 743
912 clocks = <&rpmhcc RPMH_CXO_CLK 744 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 745 clock-names = "xo";
914 746
915 memory-region = <&adsp_mem>; 747 memory-region = <&adsp_mem>;
916 748
917 qcom,qmp = <&aoss_qmp>; 749 qcom,qmp = <&aoss_qmp>;
918 750
919 qcom,smem-states = <&adsp_smp2 751 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 752 qcom,smem-state-names = "stop";
921 753
922 status = "disabled"; 754 status = "disabled";
923 755
924 glink-edge { 756 glink-edge {
925 interrupts = <GIC_SPI 757 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 758 label = "lpass";
927 qcom,remote-pid = <2>; 759 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 760 mboxes = <&apss_shared 8>;
929 761
930 apr { 762 apr {
931 compatible = " 763 compatible = "qcom,apr-v2";
932 qcom,glink-cha 764 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = 765 qcom,domain = <APR_DOMAIN_ADSP>;
934 #address-cells 766 #address-cells = <1>;
935 #size-cells = 767 #size-cells = <0>;
936 qcom,intents = 768 qcom,intents = <512 20>;
937 769
938 service@3 { !! 770 apr-service@3 {
939 reg = 771 reg = <APR_SVC_ADSP_CORE>;
940 compat 772 compatible = "qcom,q6core";
941 qcom,p 773 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 774 };
943 775
944 q6afe: service !! 776 q6afe: apr-service@4 {
945 compat 777 compatible = "qcom,q6afe";
946 reg = 778 reg = <APR_SVC_AFE>;
947 qcom,p 779 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 780 q6afedai: dais {
949 781 compatible = "qcom,q6afe-dais";
950 782 #address-cells = <1>;
951 783 #size-cells = <0>;
952 784 #sound-dai-cells = <1>;
953 }; 785 };
954 }; 786 };
955 787
956 q6asm: service !! 788 q6asm: apr-service@7 {
957 compat 789 compatible = "qcom,q6asm";
958 reg = 790 reg = <APR_SVC_ASM>;
959 qcom,p 791 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 792 q6asmdai: dais {
961 793 compatible = "qcom,q6asm-dais";
962 794 #address-cells = <1>;
963 795 #size-cells = <0>;
964 796 #sound-dai-cells = <1>;
965 797 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 798 };
967 }; 799 };
968 800
969 q6adm: service !! 801 q6adm: apr-service@8 {
970 compat 802 compatible = "qcom,q6adm";
971 reg = 803 reg = <APR_SVC_ADM>;
972 qcom,p 804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 805 q6routing: routing {
974 806 compatible = "qcom,q6adm-routing";
975 807 #sound-dai-cells = <0>;
976 }; 808 };
977 }; 809 };
978 }; 810 };
979 811
980 fastrpc { 812 fastrpc {
981 compatible = " 813 compatible = "qcom,fastrpc";
982 qcom,glink-cha 814 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 815 label = "adsp";
984 qcom,non-secur 816 qcom,non-secure-domain;
985 #address-cells 817 #address-cells = <1>;
986 #size-cells = 818 #size-cells = <0>;
987 819
988 compute-cb@3 { 820 compute-cb@3 {
989 compat 821 compatible = "qcom,fastrpc-compute-cb";
990 reg = 822 reg = <3>;
991 iommus 823 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 824 };
993 825
994 compute-cb@4 { 826 compute-cb@4 {
995 compat 827 compatible = "qcom,fastrpc-compute-cb";
996 reg = 828 reg = <4>;
997 iommus 829 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 830 };
999 }; 831 };
1000 }; 832 };
1001 }; 833 };
1002 834
1003 cdsp_pas: remoteproc-cdsp { 835 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 836 compatible = "qcom,sdm845-cdsp-pas";
1005 837
1006 interrupts-extended = <&intc 838 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 839 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 840 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 841 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 842 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 843 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 844 "handover", "stop-ack";
1013 845
1014 clocks = <&rpmhcc RPMH_CXO_CL 846 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 847 clock-names = "xo";
1016 848
1017 memory-region = <&cdsp_mem>; 849 memory-region = <&cdsp_mem>;
1018 850
1019 qcom,qmp = <&aoss_qmp>; 851 qcom,qmp = <&aoss_qmp>;
1020 852
1021 qcom,smem-states = <&cdsp_smp 853 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 854 qcom,smem-state-names = "stop";
1023 855
1024 status = "disabled"; 856 status = "disabled";
1025 857
1026 glink-edge { 858 glink-edge {
1027 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 860 label = "turing";
1029 qcom,remote-pid = <5> 861 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 862 mboxes = <&apss_shared 4>;
1031 fastrpc { 863 fastrpc {
1032 compatible = 864 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 865 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 866 label = "cdsp";
1035 qcom,non-secu 867 qcom,non-secure-domain;
1036 #address-cell 868 #address-cells = <1>;
1037 #size-cells = 869 #size-cells = <0>;
1038 870
1039 compute-cb@1 871 compute-cb@1 {
1040 compa 872 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 873 reg = <1>;
1042 iommu 874 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 875 };
1044 876
1045 compute-cb@2 877 compute-cb@2 {
1046 compa 878 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 879 reg = <2>;
1048 iommu 880 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 881 };
1050 882
1051 compute-cb@3 883 compute-cb@3 {
1052 compa 884 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 885 reg = <3>;
1054 iommu 886 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 887 };
1056 888
1057 compute-cb@4 889 compute-cb@4 {
1058 compa 890 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 891 reg = <4>;
1060 iommu 892 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 893 };
1062 894
1063 compute-cb@5 895 compute-cb@5 {
1064 compa 896 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 897 reg = <5>;
1066 iommu 898 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 899 };
1068 900
1069 compute-cb@6 901 compute-cb@6 {
1070 compa 902 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 903 reg = <6>;
1072 iommu 904 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 905 };
1074 906
1075 compute-cb@7 907 compute-cb@7 {
1076 compa 908 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 909 reg = <7>;
1078 iommu 910 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 911 };
1080 912
1081 compute-cb@8 913 compute-cb@8 {
1082 compa 914 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 915 reg = <8>;
1084 iommu 916 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 917 };
1086 }; 918 };
1087 }; 919 };
1088 }; 920 };
1089 921
>> 922 tcsr_mutex: hwlock {
>> 923 compatible = "qcom,tcsr-mutex";
>> 924 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 925 #hwlock-cells = <1>;
>> 926 };
>> 927
1090 smp2p-cdsp { 928 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 929 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 930 qcom,smem = <94>, <432>;
1093 931
1094 interrupts = <GIC_SPI 576 IRQ 932 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 933
1096 mboxes = <&apss_shared 6>; 934 mboxes = <&apss_shared 6>;
1097 935
1098 qcom,local-pid = <0>; 936 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 937 qcom,remote-pid = <5>;
1100 938
1101 cdsp_smp2p_out: master-kernel 939 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 940 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 941 #qcom,smem-state-cells = <1>;
1104 }; 942 };
1105 943
1106 cdsp_smp2p_in: slave-kernel { 944 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 945 qcom,entry-name = "slave-kernel";
1108 946
1109 interrupt-controller; 947 interrupt-controller;
1110 #interrupt-cells = <2 948 #interrupt-cells = <2>;
1111 }; 949 };
1112 }; 950 };
1113 951
1114 smp2p-lpass { 952 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 953 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 954 qcom,smem = <443>, <429>;
1117 955
1118 interrupts = <GIC_SPI 158 IRQ 956 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 957
1120 mboxes = <&apss_shared 10>; 958 mboxes = <&apss_shared 10>;
1121 959
1122 qcom,local-pid = <0>; 960 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 961 qcom,remote-pid = <2>;
1124 962
1125 adsp_smp2p_out: master-kernel 963 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 964 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 965 #qcom,smem-state-cells = <1>;
1128 }; 966 };
1129 967
1130 adsp_smp2p_in: slave-kernel { 968 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 969 qcom,entry-name = "slave-kernel";
1132 970
1133 interrupt-controller; 971 interrupt-controller;
1134 #interrupt-cells = <2 972 #interrupt-cells = <2>;
1135 }; 973 };
1136 }; 974 };
1137 975
1138 smp2p-mpss { 976 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 977 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 978 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 979 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 980 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 981 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 982 qcom,remote-pid = <1>;
1145 983
1146 modem_smp2p_out: master-kerne 984 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 985 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 986 #qcom,smem-state-cells = <1>;
1149 }; 987 };
1150 988
1151 modem_smp2p_in: slave-kernel 989 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 990 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 991 interrupt-controller;
1154 #interrupt-cells = <2 992 #interrupt-cells = <2>;
1155 }; 993 };
1156 994
1157 ipa_smp2p_out: ipa-ap-to-mode 995 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 996 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 997 #qcom,smem-state-cells = <1>;
1160 }; 998 };
1161 999
1162 ipa_smp2p_in: ipa-modem-to-ap 1000 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1001 qcom,entry-name = "ipa";
1164 interrupt-controller; 1002 interrupt-controller;
1165 #interrupt-cells = <2 1003 #interrupt-cells = <2>;
1166 }; 1004 };
1167 }; 1005 };
1168 1006
1169 smp2p-slpi { 1007 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1008 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1009 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1010 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1011 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1012 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1013 qcom,remote-pid = <3>;
1176 1014
1177 slpi_smp2p_out: master-kernel 1015 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1016 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1017 #qcom,smem-state-cells = <1>;
1180 }; 1018 };
1181 1019
1182 slpi_smp2p_in: slave-kernel { 1020 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1021 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1022 interrupt-controller;
1185 #interrupt-cells = <2 1023 #interrupt-cells = <2>;
1186 }; 1024 };
1187 }; 1025 };
1188 1026
>> 1027 psci: psci {
>> 1028 compatible = "arm,psci-1.0";
>> 1029 method = "smc";
>> 1030
>> 1031 CPU_PD0: power-domain-cpu0 {
>> 1032 #power-domain-cells = <0>;
>> 1033 power-domains = <&CLUSTER_PD>;
>> 1034 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1035 };
>> 1036
>> 1037 CPU_PD1: power-domain-cpu1 {
>> 1038 #power-domain-cells = <0>;
>> 1039 power-domains = <&CLUSTER_PD>;
>> 1040 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1041 };
>> 1042
>> 1043 CPU_PD2: power-domain-cpu2 {
>> 1044 #power-domain-cells = <0>;
>> 1045 power-domains = <&CLUSTER_PD>;
>> 1046 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1047 };
>> 1048
>> 1049 CPU_PD3: power-domain-cpu3 {
>> 1050 #power-domain-cells = <0>;
>> 1051 power-domains = <&CLUSTER_PD>;
>> 1052 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1053 };
>> 1054
>> 1055 CPU_PD4: power-domain-cpu4 {
>> 1056 #power-domain-cells = <0>;
>> 1057 power-domains = <&CLUSTER_PD>;
>> 1058 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1059 };
>> 1060
>> 1061 CPU_PD5: power-domain-cpu5 {
>> 1062 #power-domain-cells = <0>;
>> 1063 power-domains = <&CLUSTER_PD>;
>> 1064 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1065 };
>> 1066
>> 1067 CPU_PD6: power-domain-cpu6 {
>> 1068 #power-domain-cells = <0>;
>> 1069 power-domains = <&CLUSTER_PD>;
>> 1070 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1071 };
>> 1072
>> 1073 CPU_PD7: power-domain-cpu7 {
>> 1074 #power-domain-cells = <0>;
>> 1075 power-domains = <&CLUSTER_PD>;
>> 1076 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1077 };
>> 1078
>> 1079 CLUSTER_PD: power-domain-cluster {
>> 1080 #power-domain-cells = <0>;
>> 1081 domain-idle-states = <&CLUSTER_SLEEP_0>;
>> 1082 };
>> 1083 };
>> 1084
1189 soc: soc@0 { 1085 soc: soc@0 {
1190 #address-cells = <2>; 1086 #address-cells = <2>;
1191 #size-cells = <2>; 1087 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1088 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1089 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1090 compatible = "simple-bus";
1195 1091
1196 gcc: clock-controller@100000 1092 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1093 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1094 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1095 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1096 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1097 <&sleep_clk>,
1202 <&pcie0_phy> !! 1098 <&pcie0_lane>,
1203 <&pcie1_phy> !! 1099 <&pcie1_lane>;
1204 clock-names = "bi_tcx 1100 clock-names = "bi_tcxo",
1205 "bi_tcx 1101 "bi_tcxo_ao",
1206 "sleep_ 1102 "sleep_clk",
1207 "pcie_0 1103 "pcie_0_pipe_clk",
1208 "pcie_1 1104 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1105 #clock-cells = <1>;
1210 #reset-cells = <1>; 1106 #reset-cells = <1>;
1211 #power-domain-cells = 1107 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 1108 };
1214 1109
1215 qfprom@784000 { 1110 qfprom@784000 {
1216 compatible = "qcom,sd 1111 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 reg = <0 0x00784000 0 1112 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1113 #address-cells = <1>;
1219 #size-cells = <1>; 1114 #size-cells = <1>;
1220 1115
1221 qusb2p_hstx_trim: hst 1116 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1117 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1118 bits = <1 4>;
1224 }; 1119 };
1225 1120
1226 qusb2s_hstx_trim: hst 1121 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1122 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1123 bits = <6 4>;
1229 }; 1124 };
1230 }; 1125 };
1231 1126
1232 rng: rng@793000 { 1127 rng: rng@793000 {
1233 compatible = "qcom,pr 1128 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1129 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1130 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1131 clock-names = "core";
1237 }; 1132 };
1238 1133
>> 1134 qup_opp_table: opp-table-qup {
>> 1135 compatible = "operating-points-v2";
>> 1136
>> 1137 opp-50000000 {
>> 1138 opp-hz = /bits/ 64 <50000000>;
>> 1139 required-opps = <&rpmhpd_opp_min_svs>;
>> 1140 };
>> 1141
>> 1142 opp-75000000 {
>> 1143 opp-hz = /bits/ 64 <75000000>;
>> 1144 required-opps = <&rpmhpd_opp_low_svs>;
>> 1145 };
>> 1146
>> 1147 opp-100000000 {
>> 1148 opp-hz = /bits/ 64 <100000000>;
>> 1149 required-opps = <&rpmhpd_opp_svs>;
>> 1150 };
>> 1151
>> 1152 opp-128000000 {
>> 1153 opp-hz = /bits/ 64 <128000000>;
>> 1154 required-opps = <&rpmhpd_opp_nom>;
>> 1155 };
>> 1156 };
>> 1157
1239 gpi_dma0: dma-controller@8000 1158 gpi_dma0: dma-controller@800000 {
1240 #dma-cells = <3>; 1159 #dma-cells = <3>;
1241 compatible = "qcom,sd 1160 compatible = "qcom,sdm845-gpi-dma";
1242 reg = <0 0x00800000 0 1161 reg = <0 0x00800000 0 0x60000>;
1243 interrupts = <GIC_SPI 1162 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 1163 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 1164 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 1165 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 1166 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 1167 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 1168 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 1169 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 1170 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 1171 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 1172 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 1173 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 1174 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256 dma-channels = <13>; 1175 dma-channels = <13>;
1257 dma-channel-mask = <0 1176 dma-channel-mask = <0xfa>;
1258 iommus = <&apps_smmu 1177 iommus = <&apps_smmu 0x0016 0x0>;
1259 status = "disabled"; 1178 status = "disabled";
1260 }; 1179 };
1261 1180
1262 qupv3_id_0: geniqup@8c0000 { 1181 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1182 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1183 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1184 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1185 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1186 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1187 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1188 #address-cells = <2>;
1270 #size-cells = <2>; 1189 #size-cells = <2>;
1271 ranges; 1190 ranges;
1272 interconnects = <&agg 1191 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1192 interconnect-names = "qup-core";
1274 status = "disabled"; 1193 status = "disabled";
1275 1194
1276 i2c0: i2c@880000 { 1195 i2c0: i2c@880000 {
1277 compatible = 1196 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1197 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1198 clock-names = "se";
1280 clocks = <&gc 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1200 pinctrl-names = "default";
1282 pinctrl-0 = < 1201 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1202 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1203 #address-cells = <1>;
1285 #size-cells = 1204 #size-cells = <0>;
1286 power-domains 1205 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1206 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1207 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1208 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1209 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1210 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ 1211 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293 <&gpi_ 1212 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1294 dma-names = " 1213 dma-names = "tx", "rx";
1295 status = "dis 1214 status = "disabled";
1296 }; 1215 };
1297 1216
1298 spi0: spi@880000 { 1217 spi0: spi@880000 {
1299 compatible = 1218 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1219 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1220 clock-names = "se";
1302 clocks = <&gc 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1222 pinctrl-names = "default";
1304 pinctrl-0 = < 1223 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1224 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1225 #address-cells = <1>;
1307 #size-cells = 1226 #size-cells = <0>;
1308 interconnects 1227 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1228 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1229 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ 1230 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_ 1231 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313 dma-names = " 1232 dma-names = "tx", "rx";
1314 status = "dis 1233 status = "disabled";
1315 }; 1234 };
1316 1235
1317 uart0: serial@880000 1236 uart0: serial@880000 {
1318 compatible = 1237 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1238 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1239 clock-names = "se";
1321 clocks = <&gc 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1241 pinctrl-names = "default";
1323 pinctrl-0 = < 1242 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1243 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1244 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1245 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1246 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1247 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1248 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1249 status = "disabled";
1331 }; 1250 };
1332 1251
1333 i2c1: i2c@884000 { 1252 i2c1: i2c@884000 {
1334 compatible = 1253 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1254 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1255 clock-names = "se";
1337 clocks = <&gc 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1257 pinctrl-names = "default";
1339 pinctrl-0 = < 1258 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1259 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1260 #address-cells = <1>;
1342 #size-cells = 1261 #size-cells = <0>;
1343 power-domains 1262 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1263 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1264 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1265 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1266 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1267 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ 1268 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1350 <&gpi_ 1269 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1351 dma-names = " 1270 dma-names = "tx", "rx";
1352 status = "dis 1271 status = "disabled";
1353 }; 1272 };
1354 1273
1355 spi1: spi@884000 { 1274 spi1: spi@884000 {
1356 compatible = 1275 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1276 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1277 clock-names = "se";
1359 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1279 pinctrl-names = "default";
1361 pinctrl-0 = < 1280 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1281 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1282 #address-cells = <1>;
1364 #size-cells = 1283 #size-cells = <0>;
1365 interconnects 1284 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1285 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1286 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ 1287 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1369 <&gpi_ 1288 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1370 dma-names = " 1289 dma-names = "tx", "rx";
1371 status = "dis 1290 status = "disabled";
1372 }; 1291 };
1373 1292
1374 uart1: serial@884000 1293 uart1: serial@884000 {
1375 compatible = 1294 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1295 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1296 clock-names = "se";
1378 clocks = <&gc 1297 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1298 pinctrl-names = "default";
1380 pinctrl-0 = < 1299 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1300 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1301 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1302 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1303 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1304 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1305 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1306 status = "disabled";
1388 }; 1307 };
1389 1308
1390 i2c2: i2c@888000 { 1309 i2c2: i2c@888000 {
1391 compatible = 1310 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1311 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1312 clock-names = "se";
1394 clocks = <&gc 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1314 pinctrl-names = "default";
1396 pinctrl-0 = < 1315 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1316 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1317 #address-cells = <1>;
1399 #size-cells = 1318 #size-cells = <0>;
1400 power-domains 1319 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1320 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1321 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1322 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1323 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1324 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ 1325 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1407 <&gpi_ 1326 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1408 dma-names = " 1327 dma-names = "tx", "rx";
1409 status = "dis 1328 status = "disabled";
1410 }; 1329 };
1411 1330
1412 spi2: spi@888000 { 1331 spi2: spi@888000 {
1413 compatible = 1332 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1333 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1334 clock-names = "se";
1416 clocks = <&gc 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1336 pinctrl-names = "default";
1418 pinctrl-0 = < 1337 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1338 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1339 #address-cells = <1>;
1421 #size-cells = 1340 #size-cells = <0>;
1422 interconnects 1341 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1342 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1343 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ 1344 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1426 <&gpi_ 1345 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1427 dma-names = " 1346 dma-names = "tx", "rx";
1428 status = "dis 1347 status = "disabled";
1429 }; 1348 };
1430 1349
1431 uart2: serial@888000 1350 uart2: serial@888000 {
1432 compatible = 1351 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1352 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1353 clock-names = "se";
1435 clocks = <&gc 1354 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1355 pinctrl-names = "default";
1437 pinctrl-0 = < 1356 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1357 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1358 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1359 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1360 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1361 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1362 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1363 status = "disabled";
1445 }; 1364 };
1446 1365
1447 i2c3: i2c@88c000 { 1366 i2c3: i2c@88c000 {
1448 compatible = 1367 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1368 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1369 clock-names = "se";
1451 clocks = <&gc 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1371 pinctrl-names = "default";
1453 pinctrl-0 = < 1372 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1373 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1374 #address-cells = <1>;
1456 #size-cells = 1375 #size-cells = <0>;
1457 power-domains 1376 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1377 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1378 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1379 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1380 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1381 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ 1382 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1464 <&gpi_ 1383 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1465 dma-names = " 1384 dma-names = "tx", "rx";
1466 status = "dis 1385 status = "disabled";
1467 }; 1386 };
1468 1387
1469 spi3: spi@88c000 { 1388 spi3: spi@88c000 {
1470 compatible = 1389 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1390 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1391 clock-names = "se";
1473 clocks = <&gc 1392 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1393 pinctrl-names = "default";
1475 pinctrl-0 = < 1394 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1395 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1396 #address-cells = <1>;
1478 #size-cells = 1397 #size-cells = <0>;
1479 interconnects 1398 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1399 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1400 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ 1401 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1483 <&gpi_ 1402 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1484 dma-names = " 1403 dma-names = "tx", "rx";
1485 status = "dis 1404 status = "disabled";
1486 }; 1405 };
1487 1406
1488 uart3: serial@88c000 1407 uart3: serial@88c000 {
1489 compatible = 1408 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1409 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1410 clock-names = "se";
1492 clocks = <&gc 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1412 pinctrl-names = "default";
1494 pinctrl-0 = < 1413 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1414 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1415 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1416 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1417 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1418 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1419 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1420 status = "disabled";
1502 }; 1421 };
1503 1422
1504 i2c4: i2c@890000 { 1423 i2c4: i2c@890000 {
1505 compatible = 1424 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1425 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1426 clock-names = "se";
1508 clocks = <&gc 1427 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1428 pinctrl-names = "default";
1510 pinctrl-0 = < 1429 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1430 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1431 #address-cells = <1>;
1513 #size-cells = 1432 #size-cells = <0>;
1514 power-domains 1433 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1434 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1435 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1436 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1437 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1438 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ 1439 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521 <&gpi_ 1440 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522 dma-names = " 1441 dma-names = "tx", "rx";
1523 status = "dis 1442 status = "disabled";
1524 }; 1443 };
1525 1444
1526 spi4: spi@890000 { 1445 spi4: spi@890000 {
1527 compatible = 1446 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1447 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1448 clock-names = "se";
1530 clocks = <&gc 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1450 pinctrl-names = "default";
1532 pinctrl-0 = < 1451 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1452 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1453 #address-cells = <1>;
1535 #size-cells = 1454 #size-cells = <0>;
1536 interconnects 1455 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1456 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1457 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ 1458 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1540 <&gpi_ 1459 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1541 dma-names = " 1460 dma-names = "tx", "rx";
1542 status = "dis 1461 status = "disabled";
1543 }; 1462 };
1544 1463
1545 uart4: serial@890000 1464 uart4: serial@890000 {
1546 compatible = 1465 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1466 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1467 clock-names = "se";
1549 clocks = <&gc 1468 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1469 pinctrl-names = "default";
1551 pinctrl-0 = < 1470 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1471 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1472 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1473 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1474 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1475 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1476 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1477 status = "disabled";
1559 }; 1478 };
1560 1479
1561 i2c5: i2c@894000 { 1480 i2c5: i2c@894000 {
1562 compatible = 1481 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1482 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1483 clock-names = "se";
1565 clocks = <&gc 1484 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1485 pinctrl-names = "default";
1567 pinctrl-0 = < 1486 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1487 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1488 #address-cells = <1>;
1570 #size-cells = 1489 #size-cells = <0>;
1571 power-domains 1490 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1491 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1492 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1493 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1494 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1495 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ 1496 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1578 <&gpi_ 1497 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1579 dma-names = " 1498 dma-names = "tx", "rx";
1580 status = "dis 1499 status = "disabled";
1581 }; 1500 };
1582 1501
1583 spi5: spi@894000 { 1502 spi5: spi@894000 {
1584 compatible = 1503 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1504 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1505 clock-names = "se";
1587 clocks = <&gc 1506 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1507 pinctrl-names = "default";
1589 pinctrl-0 = < 1508 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1509 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1510 #address-cells = <1>;
1592 #size-cells = 1511 #size-cells = <0>;
1593 interconnects 1512 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1513 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1514 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ 1515 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1597 <&gpi_ 1516 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1598 dma-names = " 1517 dma-names = "tx", "rx";
1599 status = "dis 1518 status = "disabled";
1600 }; 1519 };
1601 1520
1602 uart5: serial@894000 1521 uart5: serial@894000 {
1603 compatible = 1522 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1523 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1524 clock-names = "se";
1606 clocks = <&gc 1525 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1526 pinctrl-names = "default";
1608 pinctrl-0 = < 1527 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1528 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1529 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1530 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1531 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1532 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1533 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1534 status = "disabled";
1616 }; 1535 };
1617 1536
1618 i2c6: i2c@898000 { 1537 i2c6: i2c@898000 {
1619 compatible = 1538 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1539 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1540 clock-names = "se";
1622 clocks = <&gc 1541 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1542 pinctrl-names = "default";
1624 pinctrl-0 = < 1543 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1544 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1545 #address-cells = <1>;
1627 #size-cells = 1546 #size-cells = <0>;
1628 power-domains 1547 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1548 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1549 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1550 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1551 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1552 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ 1553 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1635 <&gpi_ 1554 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1636 dma-names = " 1555 dma-names = "tx", "rx";
1637 status = "dis 1556 status = "disabled";
1638 }; 1557 };
1639 1558
1640 spi6: spi@898000 { 1559 spi6: spi@898000 {
1641 compatible = 1560 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1561 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1562 clock-names = "se";
1644 clocks = <&gc 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1564 pinctrl-names = "default";
1646 pinctrl-0 = < 1565 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1566 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1567 #address-cells = <1>;
1649 #size-cells = 1568 #size-cells = <0>;
1650 interconnects 1569 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1570 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1571 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ 1572 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1654 <&gpi_ 1573 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1655 dma-names = " 1574 dma-names = "tx", "rx";
1656 status = "dis 1575 status = "disabled";
1657 }; 1576 };
1658 1577
1659 uart6: serial@898000 1578 uart6: serial@898000 {
1660 compatible = 1579 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1580 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1581 clock-names = "se";
1663 clocks = <&gc 1582 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1583 pinctrl-names = "default";
1665 pinctrl-0 = < 1584 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1585 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1586 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1587 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1588 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1589 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1590 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1591 status = "disabled";
1673 }; 1592 };
1674 1593
1675 i2c7: i2c@89c000 { 1594 i2c7: i2c@89c000 {
1676 compatible = 1595 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1596 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1597 clock-names = "se";
1679 clocks = <&gc 1598 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1599 pinctrl-names = "default";
1681 pinctrl-0 = < 1600 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1601 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1602 #address-cells = <1>;
1684 #size-cells = 1603 #size-cells = <0>;
1685 power-domains 1604 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1605 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1606 status = "disabled";
1688 }; 1607 };
1689 1608
1690 spi7: spi@89c000 { 1609 spi7: spi@89c000 {
1691 compatible = 1610 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1611 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1612 clock-names = "se";
1694 clocks = <&gc 1613 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1614 pinctrl-names = "default";
1696 pinctrl-0 = < 1615 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1616 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1617 #address-cells = <1>;
1699 #size-cells = 1618 #size-cells = <0>;
1700 interconnects 1619 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1620 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1621 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ 1622 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1704 <&gpi_ 1623 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1705 dma-names = " 1624 dma-names = "tx", "rx";
1706 status = "dis 1625 status = "disabled";
1707 }; 1626 };
1708 1627
1709 uart7: serial@89c000 1628 uart7: serial@89c000 {
1710 compatible = 1629 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1630 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1631 clock-names = "se";
1713 clocks = <&gc 1632 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1633 pinctrl-names = "default";
1715 pinctrl-0 = < 1634 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1635 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1636 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1637 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1638 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1639 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1640 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1641 status = "disabled";
1723 }; 1642 };
1724 }; 1643 };
1725 1644
1726 gpi_dma1: dma-controller@a000 !! 1645 gpi_dma1: dma-controller@0xa00000 {
1727 #dma-cells = <3>; 1646 #dma-cells = <3>;
1728 compatible = "qcom,sd 1647 compatible = "qcom,sdm845-gpi-dma";
1729 reg = <0 0x00a00000 0 1648 reg = <0 0x00a00000 0 0x60000>;
1730 interrupts = <GIC_SPI 1649 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1650 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 1651 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 1652 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 1653 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 1654 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 1655 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1656 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1657 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1658 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1659 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1660 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1661 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743 dma-channels = <13>; 1662 dma-channels = <13>;
1744 dma-channel-mask = <0 1663 dma-channel-mask = <0xfa>;
1745 iommus = <&apps_smmu 1664 iommus = <&apps_smmu 0x06d6 0x0>;
1746 status = "disabled"; 1665 status = "disabled";
1747 }; 1666 };
1748 1667
1749 qupv3_id_1: geniqup@ac0000 { 1668 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1669 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1670 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1671 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1672 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1673 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1674 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1675 #address-cells = <2>;
1757 #size-cells = <2>; 1676 #size-cells = <2>;
1758 ranges; 1677 ranges;
1759 interconnects = <&agg 1678 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1679 interconnect-names = "qup-core";
1761 status = "disabled"; 1680 status = "disabled";
1762 1681
1763 i2c8: i2c@a80000 { 1682 i2c8: i2c@a80000 {
1764 compatible = 1683 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1684 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1685 clock-names = "se";
1767 clocks = <&gc 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1687 pinctrl-names = "default";
1769 pinctrl-0 = < 1688 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1689 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1690 #address-cells = <1>;
1772 #size-cells = 1691 #size-cells = <0>;
1773 power-domains 1692 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1693 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1694 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1695 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1696 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1697 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ 1698 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780 <&gpi_ 1699 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1781 dma-names = " 1700 dma-names = "tx", "rx";
1782 status = "dis 1701 status = "disabled";
1783 }; 1702 };
1784 1703
1785 spi8: spi@a80000 { 1704 spi8: spi@a80000 {
1786 compatible = 1705 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1706 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1707 clock-names = "se";
1789 clocks = <&gc 1708 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1709 pinctrl-names = "default";
1791 pinctrl-0 = < 1710 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1711 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1712 #address-cells = <1>;
1794 #size-cells = 1713 #size-cells = <0>;
1795 interconnects 1714 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1715 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1716 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ 1717 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799 <&gpi_ 1718 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1800 dma-names = " 1719 dma-names = "tx", "rx";
1801 status = "dis 1720 status = "disabled";
1802 }; 1721 };
1803 1722
1804 uart8: serial@a80000 1723 uart8: serial@a80000 {
1805 compatible = 1724 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1725 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1726 clock-names = "se";
1808 clocks = <&gc 1727 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1728 pinctrl-names = "default";
1810 pinctrl-0 = < 1729 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1730 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1731 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1732 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1733 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1734 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1735 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1736 status = "disabled";
1818 }; 1737 };
1819 1738
1820 i2c9: i2c@a84000 { 1739 i2c9: i2c@a84000 {
1821 compatible = 1740 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1741 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1742 clock-names = "se";
1824 clocks = <&gc 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1744 pinctrl-names = "default";
1826 pinctrl-0 = < 1745 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1746 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1747 #address-cells = <1>;
1829 #size-cells = 1748 #size-cells = <0>;
1830 power-domains 1749 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1750 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1751 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1752 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1753 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1754 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ 1755 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1837 <&gpi_ 1756 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1838 dma-names = " 1757 dma-names = "tx", "rx";
1839 status = "dis 1758 status = "disabled";
1840 }; 1759 };
1841 1760
1842 spi9: spi@a84000 { 1761 spi9: spi@a84000 {
1843 compatible = 1762 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1763 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1764 clock-names = "se";
1846 clocks = <&gc 1765 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1766 pinctrl-names = "default";
1848 pinctrl-0 = < 1767 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1768 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1769 #address-cells = <1>;
1851 #size-cells = 1770 #size-cells = <0>;
1852 interconnects 1771 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1772 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1773 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ 1774 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1856 <&gpi_ 1775 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1857 dma-names = " 1776 dma-names = "tx", "rx";
1858 status = "dis 1777 status = "disabled";
1859 }; 1778 };
1860 1779
1861 uart9: serial@a84000 1780 uart9: serial@a84000 {
1862 compatible = 1781 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1782 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1783 clock-names = "se";
1865 clocks = <&gc 1784 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1785 pinctrl-names = "default";
1867 pinctrl-0 = < 1786 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1787 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1788 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1789 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1790 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1791 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1792 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1793 status = "disabled";
1875 }; 1794 };
1876 1795
1877 i2c10: i2c@a88000 { 1796 i2c10: i2c@a88000 {
1878 compatible = 1797 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1798 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1799 clock-names = "se";
1881 clocks = <&gc 1800 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1801 pinctrl-names = "default";
1883 pinctrl-0 = < 1802 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1803 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1804 #address-cells = <1>;
1886 #size-cells = 1805 #size-cells = <0>;
1887 power-domains 1806 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1807 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1808 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1809 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1810 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1811 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ 1812 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1894 <&gpi_ 1813 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1895 dma-names = " 1814 dma-names = "tx", "rx";
1896 status = "dis 1815 status = "disabled";
1897 }; 1816 };
1898 1817
1899 spi10: spi@a88000 { 1818 spi10: spi@a88000 {
1900 compatible = 1819 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1820 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1821 clock-names = "se";
1903 clocks = <&gc 1822 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1823 pinctrl-names = "default";
1905 pinctrl-0 = < 1824 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1825 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1826 #address-cells = <1>;
1908 #size-cells = 1827 #size-cells = <0>;
1909 interconnects 1828 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1829 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1830 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ 1831 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913 <&gpi_ 1832 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1914 dma-names = " 1833 dma-names = "tx", "rx";
1915 status = "dis 1834 status = "disabled";
1916 }; 1835 };
1917 1836
1918 uart10: serial@a88000 1837 uart10: serial@a88000 {
1919 compatible = 1838 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1839 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1840 clock-names = "se";
1922 clocks = <&gc 1841 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1842 pinctrl-names = "default";
1924 pinctrl-0 = < 1843 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1844 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1845 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1846 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1847 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1848 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1849 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1850 status = "disabled";
1932 }; 1851 };
1933 1852
1934 i2c11: i2c@a8c000 { 1853 i2c11: i2c@a8c000 {
1935 compatible = 1854 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1855 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1856 clock-names = "se";
1938 clocks = <&gc 1857 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1858 pinctrl-names = "default";
1940 pinctrl-0 = < 1859 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1860 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1861 #address-cells = <1>;
1943 #size-cells = 1862 #size-cells = <0>;
1944 power-domains 1863 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1864 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1865 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1866 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1867 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1868 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ 1869 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1951 <&gpi_ 1870 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1952 dma-names = " 1871 dma-names = "tx", "rx";
1953 status = "dis 1872 status = "disabled";
1954 }; 1873 };
1955 1874
1956 spi11: spi@a8c000 { 1875 spi11: spi@a8c000 {
1957 compatible = 1876 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1877 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1878 clock-names = "se";
1960 clocks = <&gc 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1880 pinctrl-names = "default";
1962 pinctrl-0 = < 1881 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1882 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1883 #address-cells = <1>;
1965 #size-cells = 1884 #size-cells = <0>;
1966 interconnects 1885 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1886 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1887 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ 1888 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1970 <&gpi_ 1889 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1971 dma-names = " 1890 dma-names = "tx", "rx";
1972 status = "dis 1891 status = "disabled";
1973 }; 1892 };
1974 1893
1975 uart11: serial@a8c000 1894 uart11: serial@a8c000 {
1976 compatible = 1895 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1896 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1897 clock-names = "se";
1979 clocks = <&gc 1898 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1899 pinctrl-names = "default";
1981 pinctrl-0 = < 1900 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1901 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1902 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1903 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1904 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1905 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1906 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1907 status = "disabled";
1989 }; 1908 };
1990 1909
1991 i2c12: i2c@a90000 { 1910 i2c12: i2c@a90000 {
1992 compatible = 1911 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1912 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1913 clock-names = "se";
1995 clocks = <&gc 1914 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1915 pinctrl-names = "default";
1997 pinctrl-0 = < 1916 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1917 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1918 #address-cells = <1>;
2000 #size-cells = 1919 #size-cells = <0>;
2001 power-domains 1920 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1921 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 1922 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 1923 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 1924 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 1925 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ 1926 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2008 <&gpi_ 1927 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2009 dma-names = " 1928 dma-names = "tx", "rx";
2010 status = "dis 1929 status = "disabled";
2011 }; 1930 };
2012 1931
2013 spi12: spi@a90000 { 1932 spi12: spi@a90000 {
2014 compatible = 1933 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1934 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1935 clock-names = "se";
2017 clocks = <&gc 1936 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1937 pinctrl-names = "default";
2019 pinctrl-0 = < 1938 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1939 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1940 #address-cells = <1>;
2022 #size-cells = 1941 #size-cells = <0>;
2023 interconnects 1942 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 1943 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 1944 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ 1945 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2027 <&gpi_ 1946 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2028 dma-names = " 1947 dma-names = "tx", "rx";
2029 status = "dis 1948 status = "disabled";
2030 }; 1949 };
2031 1950
2032 uart12: serial@a90000 1951 uart12: serial@a90000 {
2033 compatible = 1952 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1953 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1954 clock-names = "se";
2036 clocks = <&gc 1955 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1956 pinctrl-names = "default";
2038 pinctrl-0 = < 1957 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1958 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1959 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1960 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 1961 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 1962 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 1963 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 1964 status = "disabled";
2046 }; 1965 };
2047 1966
2048 i2c13: i2c@a94000 { 1967 i2c13: i2c@a94000 {
2049 compatible = 1968 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1969 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1970 clock-names = "se";
2052 clocks = <&gc 1971 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1972 pinctrl-names = "default";
2054 pinctrl-0 = < 1973 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1974 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1975 #address-cells = <1>;
2057 #size-cells = 1976 #size-cells = <0>;
2058 power-domains 1977 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1978 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 1979 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 1980 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 1981 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 1982 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ 1983 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2065 <&gpi_ 1984 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2066 dma-names = " 1985 dma-names = "tx", "rx";
2067 status = "dis 1986 status = "disabled";
2068 }; 1987 };
2069 1988
2070 spi13: spi@a94000 { 1989 spi13: spi@a94000 {
2071 compatible = 1990 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1991 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1992 clock-names = "se";
2074 clocks = <&gc 1993 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1994 pinctrl-names = "default";
2076 pinctrl-0 = < 1995 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1996 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1997 #address-cells = <1>;
2079 #size-cells = 1998 #size-cells = <0>;
2080 interconnects 1999 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 2000 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 2001 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ 2002 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2084 <&gpi_ 2003 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2085 dma-names = " 2004 dma-names = "tx", "rx";
2086 status = "dis 2005 status = "disabled";
2087 }; 2006 };
2088 2007
2089 uart13: serial@a94000 2008 uart13: serial@a94000 {
2090 compatible = 2009 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 2010 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 2011 clock-names = "se";
2093 clocks = <&gc 2012 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 2013 pinctrl-names = "default";
2095 pinctrl-0 = < 2014 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 2015 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 2016 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 2017 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 2018 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 2019 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 2020 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 2021 status = "disabled";
2103 }; 2022 };
2104 2023
2105 i2c14: i2c@a98000 { 2024 i2c14: i2c@a98000 {
2106 compatible = 2025 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 2026 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 2027 clock-names = "se";
2109 clocks = <&gc 2028 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 2029 pinctrl-names = "default";
2111 pinctrl-0 = < 2030 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 2031 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 2032 #address-cells = <1>;
2114 #size-cells = 2033 #size-cells = <0>;
2115 power-domains 2034 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 2035 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 2036 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 2037 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 2038 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 2039 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ 2040 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2122 <&gpi_ 2041 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2123 dma-names = " 2042 dma-names = "tx", "rx";
2124 status = "dis 2043 status = "disabled";
2125 }; 2044 };
2126 2045
2127 spi14: spi@a98000 { 2046 spi14: spi@a98000 {
2128 compatible = 2047 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 2048 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 2049 clock-names = "se";
2131 clocks = <&gc 2050 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 2051 pinctrl-names = "default";
2133 pinctrl-0 = < 2052 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 2053 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 2054 #address-cells = <1>;
2136 #size-cells = 2055 #size-cells = <0>;
2137 interconnects 2056 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 2057 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 2058 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ 2059 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2141 <&gpi_ 2060 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2142 dma-names = " 2061 dma-names = "tx", "rx";
2143 status = "dis 2062 status = "disabled";
2144 }; 2063 };
2145 2064
2146 uart14: serial@a98000 2065 uart14: serial@a98000 {
2147 compatible = 2066 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 2067 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 2068 clock-names = "se";
2150 clocks = <&gc 2069 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 2070 pinctrl-names = "default";
2152 pinctrl-0 = < 2071 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 2072 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 2073 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 2074 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 2075 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 2076 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 2077 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 2078 status = "disabled";
2160 }; 2079 };
2161 2080
2162 i2c15: i2c@a9c000 { 2081 i2c15: i2c@a9c000 {
2163 compatible = 2082 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 2083 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 2084 clock-names = "se";
2166 clocks = <&gc 2085 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 2086 pinctrl-names = "default";
2168 pinctrl-0 = < 2087 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 2088 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 2089 #address-cells = <1>;
2171 #size-cells = 2090 #size-cells = <0>;
2172 power-domains 2091 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 2092 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 2093 status = "disabled";
2175 interconnects 2094 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 2095 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 2096 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 2097 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ 2098 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2180 <&gpi_ 2099 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2181 dma-names = " 2100 dma-names = "tx", "rx";
2182 }; 2101 };
2183 2102
2184 spi15: spi@a9c000 { 2103 spi15: spi@a9c000 {
2185 compatible = 2104 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 2105 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 2106 clock-names = "se";
2188 clocks = <&gc 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 2108 pinctrl-names = "default";
2190 pinctrl-0 = < 2109 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 2110 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 2111 #address-cells = <1>;
2193 #size-cells = 2112 #size-cells = <0>;
2194 interconnects 2113 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 2114 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 2115 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ 2116 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2198 <&gpi_ 2117 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2199 dma-names = " 2118 dma-names = "tx", "rx";
2200 status = "dis 2119 status = "disabled";
2201 }; 2120 };
2202 2121
2203 uart15: serial@a9c000 2122 uart15: serial@a9c000 {
2204 compatible = 2123 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 2124 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 2125 clock-names = "se";
2207 clocks = <&gc 2126 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 2127 pinctrl-names = "default";
2209 pinctrl-0 = < 2128 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 2129 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 2130 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 2131 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 2132 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 2133 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 2134 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 2135 status = "disabled";
2217 }; 2136 };
2218 }; 2137 };
2219 2138
2220 llcc: system-cache-controller 2139 llcc: system-cache-controller@1100000 {
2221 compatible = "qcom,sd 2140 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 2141 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 2142 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 2143 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 2144 };
2229 2145
2230 dma@10a2000 { <<
2231 compatible = "qcom,sd <<
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { <<
2237 compatible = "qcom,sd <<
2238 reg = <0 0x0114a000 0 <<
2239 interrupts = <GIC_SPI <<
2240 interconnects = <&mem <<
2241 <<
2242 operating-points-v2 = <<
2243 <<
2244 llcc_bwmon_opp_table: <<
2245 compatible = <<
2246 <<
2247 /* <<
2248 * The interc <<
2249 * cpu4_opp_t <<
2250 * interconne <<
2251 * bandwidth <<
2252 * bus width: <<
2253 * kernel. <<
2254 */ <<
2255 opp-0 { <<
2256 opp-p <<
2257 }; <<
2258 opp-1 { <<
2259 opp-p <<
2260 }; <<
2261 opp-2 { <<
2262 opp-p <<
2263 }; <<
2264 opp-3 { <<
2265 opp-p <<
2266 }; <<
2267 opp-4 { <<
2268 opp-p <<
2269 }; <<
2270 }; <<
2271 }; <<
2272 <<
2273 pmu@1436400 { 2146 pmu@1436400 {
2274 compatible = "qcom,sd !! 2147 compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
2275 reg = <0 0x01436400 0 2148 reg = <0 0x01436400 0 0x600>;
2276 interrupts = <GIC_SPI 2149 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2277 interconnects = <&gla 2150 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278 2151
2279 operating-points-v2 = 2152 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 2153
2281 cpu_bwmon_opp_table: 2154 cpu_bwmon_opp_table: opp-table {
2282 compatible = 2155 compatible = "operating-points-v2";
2283 2156
2284 /* 2157 /*
2285 * The interc 2158 * The interconnect path bandwidth taken from
2286 * cpu4_opp_t 2159 * cpu4_opp_table bandwidth for OSM L3
2287 * interconne 2160 * interconnect. This also matches the OSM L3
2288 * from bandw 2161 * from bandwidth table of qcom,cpu4-l3lat-mon
2289 * (qcom,core 2162 * (qcom,core-dev-table, bus width: 16 bytes)
2290 * from msm-4 2163 * from msm-4.9 downstream kernel.
2291 */ 2164 */
2292 opp-0 { 2165 opp-0 {
2293 opp-p 2166 opp-peak-kBps = <4800000>;
2294 }; 2167 };
2295 opp-1 { 2168 opp-1 {
2296 opp-p 2169 opp-peak-kBps = <9216000>;
2297 }; 2170 };
2298 opp-2 { 2171 opp-2 {
2299 opp-p 2172 opp-peak-kBps = <15052800>;
2300 }; 2173 };
2301 opp-3 { 2174 opp-3 {
2302 opp-p 2175 opp-peak-kBps = <20889600>;
2303 }; 2176 };
2304 opp-4 { 2177 opp-4 {
2305 opp-p 2178 opp-peak-kBps = <25497600>;
2306 }; 2179 };
2307 }; 2180 };
2308 }; 2181 };
2309 2182
2310 pcie0: pcie@1c00000 { !! 2183 pcie0: pci@1c00000 {
2311 compatible = "qcom,pc 2184 compatible = "qcom,pcie-sdm845";
2312 reg = <0 0x01c00000 0 2185 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 2186 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 2187 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 2188 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 2189 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 2190 device_type = "pci";
2319 linux,pci-domain = <0 2191 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 2192 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 2193 num-lanes = <1>;
2322 2194
2323 #address-cells = <3>; 2195 #address-cells = <3>;
2324 #size-cells = <2>; 2196 #size-cells = <2>;
2325 2197
2326 ranges = <0x01000000 !! 2198 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2327 <0x02000000 !! 2199 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
2328 2200
2329 interrupts = <GIC_SPI 2201 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 2202 interrupt-names = "msi";
2331 #interrupt-cells = <1 2203 #interrupt-cells = <1>;
2332 interrupt-map-mask = 2204 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 2205 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 2206 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 2207 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 2208 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2209
2338 clocks = <&gcc GCC_PC 2210 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2211 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2212 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2213 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2214 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2215 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2216 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2217 clock-names = "pipe",
2346 "aux", 2218 "aux",
2347 "cfg", 2219 "cfg",
2348 "bus_ma 2220 "bus_master",
2349 "bus_sl 2221 "bus_slave",
2350 "slave_ 2222 "slave_q2a",
2351 "tbu"; 2223 "tbu";
2352 2224
>> 2225 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 2226 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2227 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2228 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2229 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2230 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2231 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2232 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2233 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2234 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2235 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2236 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2237 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2238 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2239 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2240 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2241 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2242
2370 resets = <&gcc GCC_PC 2243 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2244 reset-names = "pci";
2372 2245
2373 power-domains = <&gcc 2246 power-domains = <&gcc PCIE_0_GDSC>;
2374 2247
2375 phys = <&pcie0_phy>; !! 2248 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2249 phy-names = "pciephy";
2377 2250
2378 status = "disabled"; 2251 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2252 };
2390 2253
2391 pcie0_phy: phy@1c06000 { 2254 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2255 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2256 reg = <0 0x01c06000 0 0x18c>;
>> 2257 #address-cells = <2>;
>> 2258 #size-cells = <2>;
>> 2259 ranges;
2394 clocks = <&gcc GCC_PC 2260 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2261 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2262 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2263 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2264 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2265
2410 resets = <&gcc GCC_PC 2266 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2267 reset-names = "phy";
2412 2268
2413 assigned-clocks = <&g 2269 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2270 assigned-clock-rates = <100000000>;
2415 2271
2416 status = "disabled"; 2272 status = "disabled";
>> 2273
>> 2274 pcie0_lane: phy@1c06200 {
>> 2275 reg = <0 0x01c06200 0 0x128>,
>> 2276 <0 0x01c06400 0 0x1fc>,
>> 2277 <0 0x01c06800 0 0x218>,
>> 2278 <0 0x01c06600 0 0x70>;
>> 2279 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2280 clock-names = "pipe0";
>> 2281
>> 2282 #clock-cells = <0>;
>> 2283 #phy-cells = <0>;
>> 2284 clock-output-names = "pcie_0_pipe_clk";
>> 2285 };
2417 }; 2286 };
2418 2287
2419 pcie1: pcie@1c08000 { !! 2288 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc 2289 compatible = "qcom,pcie-sdm845";
2421 reg = <0 0x01c08000 0 2290 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2291 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2292 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 2293 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 2294 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 2295 device_type = "pci";
2428 linux,pci-domain = <1 2296 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2297 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2298 num-lanes = <1>;
2431 2299
2432 #address-cells = <3>; 2300 #address-cells = <3>;
2433 #size-cells = <2>; 2301 #size-cells = <2>;
2434 2302
2435 ranges = <0x01000000 !! 2303 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2304 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2305
2438 interrupts = <GIC_SPI 2306 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2307 interrupt-names = "msi";
2440 #interrupt-cells = <1 2308 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2309 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 2310 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 2311 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 2312 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 2313 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2314
2447 clocks = <&gcc GCC_PC 2315 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2316 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2317 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2318 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2319 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2320 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2321 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2322 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2323 clock-names = "pipe",
2456 "aux", 2324 "aux",
2457 "cfg", 2325 "cfg",
2458 "bus_ma 2326 "bus_master",
2459 "bus_sl 2327 "bus_slave",
2460 "slave_ 2328 "slave_q2a",
2461 "ref", 2329 "ref",
2462 "tbu"; 2330 "tbu";
2463 2331
2464 assigned-clocks = <&g 2332 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2333 assigned-clock-rates = <19200000>;
2466 2334
>> 2335 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 2336 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2337 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2338 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2339 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2340 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2341 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2342 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2343 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2344 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2345 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2346 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2347 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2348 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2349 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2350 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2351 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2352
2484 resets = <&gcc GCC_PC 2353 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2354 reset-names = "pci";
2486 2355
2487 power-domains = <&gcc 2356 power-domains = <&gcc PCIE_1_GDSC>;
2488 2357
2489 phys = <&pcie1_phy>; !! 2358 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2359 phy-names = "pciephy";
2491 2360
2492 status = "disabled"; 2361 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2362 };
2504 2363
2505 pcie1_phy: phy@1c0a000 { 2364 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2365 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2366 reg = <0 0x01c0a000 0 0x800>;
>> 2367 #address-cells = <2>;
>> 2368 #size-cells = <2>;
>> 2369 ranges;
2508 clocks = <&gcc GCC_PC 2370 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2371 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2372 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2373 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2374 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2375
2524 resets = <&gcc GCC_PC 2376 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2377 reset-names = "phy";
2526 2378
2527 assigned-clocks = <&g 2379 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2380 assigned-clock-rates = <100000000>;
2529 2381
2530 status = "disabled"; 2382 status = "disabled";
>> 2383
>> 2384 pcie1_lane: phy@1c06200 {
>> 2385 reg = <0 0x01c0a800 0 0x800>,
>> 2386 <0 0x01c0a800 0 0x800>,
>> 2387 <0 0x01c0b800 0 0x400>;
>> 2388 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2389 clock-names = "pipe0";
>> 2390
>> 2391 #clock-cells = <0>;
>> 2392 #phy-cells = <0>;
>> 2393 clock-output-names = "pcie_1_pipe_clk";
>> 2394 };
2531 }; 2395 };
2532 2396
2533 mem_noc: interconnect@1380000 2397 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2398 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2399 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2400 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2401 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2402 };
2539 2403
2540 dc_noc: interconnect@14e0000 2404 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2405 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2406 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2407 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2408 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2409 };
2546 2410
2547 config_noc: interconnect@1500 2411 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2412 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2413 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2414 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2415 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2416 };
2553 2417
2554 system_noc: interconnect@1620 2418 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2419 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2420 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2421 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2422 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2423 };
2560 2424
2561 aggre1_noc: interconnect@16e0 2425 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2426 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2427 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2428 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2429 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2430 };
2567 2431
2568 aggre2_noc: interconnect@1700 2432 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2433 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2434 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2435 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2436 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2437 };
2574 2438
2575 mmss_noc: interconnect@174000 2439 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2440 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2441 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2442 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2443 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2444 };
2581 2445
2582 ufs_mem_hc: ufshc@1d84000 { 2446 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2447 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2448 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2449 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2450 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2451 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2452 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2453 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2454 phy-names = "ufsphy";
2591 lanes-per-direction = 2455 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2456 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2457 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2458 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2459 reset-names = "rst";
2596 2460
2597 iommus = <&apps_smmu 2461 iommus = <&apps_smmu 0x100 0xf>;
2598 2462
2599 clock-names = 2463 clock-names =
2600 "core_clk", 2464 "core_clk",
2601 "bus_aggr_clk 2465 "bus_aggr_clk",
2602 "iface_clk", 2466 "iface_clk",
2603 "core_clk_uni 2467 "core_clk_unipro",
2604 "ref_clk", 2468 "ref_clk",
2605 "tx_lane0_syn 2469 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2470 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2471 "rx_lane1_sync_clk",
2608 "ice_core_clk 2472 "ice_core_clk";
2609 clocks = 2473 clocks =
2610 <&gcc GCC_UFS 2474 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2475 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2476 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2477 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2478 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2479 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2480 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2481 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2482 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2483 freq-table-hz =
2620 operating-points-v2 = !! 2484 <50000000 200000000>,
2621 !! 2485 <0 0>,
2622 interconnects = <&agg !! 2486 <0 0>,
2623 <&gla !! 2487 <37500000 150000000>,
2624 interconnect-names = !! 2488 <0 0>,
>> 2489 <0 0>,
>> 2490 <0 0>,
>> 2491 <0 0>,
>> 2492 <0 300000000>;
2625 2493
2626 status = "disabled"; 2494 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2495 };
2658 2496
2659 ufs_mem_phy: phy@1d87000 { 2497 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2498 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2499 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2500 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2501 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2502 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2503 clock-names = "ref",
2667 "ref_au !! 2504 "ref_aux";
2668 "qref"; !! 2505 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2506 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2507
2672 resets = <&ufs_mem_hc 2508 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2509 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2510 status = "disabled";
>> 2511
>> 2512 ufs_mem_phy_lanes: phy@1d87400 {
>> 2513 reg = <0 0x01d87400 0 0x108>,
>> 2514 <0 0x01d87600 0 0x1e0>,
>> 2515 <0 0x01d87c00 0 0x1dc>,
>> 2516 <0 0x01d87800 0 0x108>,
>> 2517 <0 0x01d87a00 0 0x1e0>;
>> 2518 #phy-cells = <0>;
>> 2519 };
2677 }; 2520 };
2678 2521
2679 cryptobam: dma-controller@1dc 2522 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,ba !! 2523 compatible = "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2524 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2525 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2526 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2527 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2528 #dma-cells = <1>;
2686 qcom,ee = <0>; 2529 qcom,ee = <0>;
2687 qcom,controlled-remot 2530 qcom,controlled-remotely;
2688 iommus = <&apps_smmu 2531 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2532 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2533 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2534 <&apps_smmu 0x716 0x1>;
2692 }; 2535 };
2693 2536
2694 crypto: crypto@1dfa000 { 2537 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2538 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2539 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2540 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2541 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2542 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2543 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2544 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2545 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2546 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2547 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2548 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2549 <&apps_smmu 0x716 0x1>;
2707 }; 2550 };
2708 2551
2709 ipa: ipa@1e40000 { 2552 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2553 compatible = "qcom,sdm845-ipa";
2711 2554
2712 iommus = <&apps_smmu 2555 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2556 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 !! 2557 reg = <0 0x1e40000 0 0x7000>,
2715 <0 0x01e47000 0 !! 2558 <0 0x1e47000 0 0x2000>,
2716 <0 0x01e04000 0 !! 2559 <0 0x1e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2560 reg-names = "ipa-reg",
2718 "ipa-shar 2561 "ipa-shared",
2719 "gsi"; 2562 "gsi";
2720 2563
2721 interrupts-extended = 2564 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2565 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2566 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2567 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2568 interrupt-names = "ipa",
2726 "gs 2569 "gsi",
2727 "ip 2570 "ipa-clock-query",
2728 "ip 2571 "ipa-setup-ready";
2729 2572
2730 clocks = <&rpmhcc RPM 2573 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2574 clock-names = "core";
2732 2575
2733 interconnects = <&agg 2576 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2577 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2578 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2579 interconnect-names = "memory",
2737 2580 "imem",
2738 2581 "config";
2739 2582
2740 qcom,smem-states = <& 2583 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2584 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2585 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2586 "ipa-clock-enabled";
2744 2587
2745 status = "disabled"; 2588 status = "disabled";
2746 }; 2589 };
2747 2590
2748 tcsr_mutex: hwlock@1f40000 { !! 2591 tcsr_mutex_regs: syscon@1f40000 {
2749 compatible = "qcom,tc !! 2592 compatible = "syscon";
2750 reg = <0 0x01f40000 0 !! 2593 reg = <0 0x01f40000 0 0x40000>;
2751 #hwlock-cells = <1>; <<
2752 }; <<
2753 <<
2754 tcsr_regs_1: syscon@1f60000 { <<
2755 compatible = "qcom,sd <<
2756 reg = <0 0x01f60000 0 <<
2757 }; 2594 };
2758 2595
2759 tlmm: pinctrl@3400000 { 2596 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2597 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2598 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2599 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2600 gpio-controller;
2764 #gpio-cells = <2>; 2601 #gpio-cells = <2>;
2765 interrupt-controller; 2602 interrupt-controller;
2766 #interrupt-cells = <2 2603 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2604 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2605 wakeup-parent = <&pdc_intc>;
2769 2606
2770 cci0_default: cci0-de !! 2607 cci0_default: cci0-default {
2771 /* SDA, SCL * 2608 /* SDA, SCL */
2772 pins = "gpio1 2609 pins = "gpio17", "gpio18";
2773 function = "c 2610 function = "cci_i2c";
2774 2611
2775 bias-pull-up; 2612 bias-pull-up;
2776 drive-strengt 2613 drive-strength = <2>; /* 2 mA */
2777 }; 2614 };
2778 2615
2779 cci0_sleep: cci0-slee !! 2616 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2617 /* SDA, SCL */
2781 pins = "gpio1 2618 pins = "gpio17", "gpio18";
2782 function = "c 2619 function = "cci_i2c";
2783 2620
2784 drive-strengt 2621 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2622 bias-pull-down;
2786 }; 2623 };
2787 2624
2788 cci1_default: cci1-de !! 2625 cci1_default: cci1-default {
2789 /* SDA, SCL * 2626 /* SDA, SCL */
2790 pins = "gpio1 2627 pins = "gpio19", "gpio20";
2791 function = "c 2628 function = "cci_i2c";
2792 2629
2793 bias-pull-up; 2630 bias-pull-up;
2794 drive-strengt 2631 drive-strength = <2>; /* 2 mA */
2795 }; 2632 };
2796 2633
2797 cci1_sleep: cci1-slee !! 2634 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2635 /* SDA, SCL */
2799 pins = "gpio1 2636 pins = "gpio19", "gpio20";
2800 function = "c 2637 function = "cci_i2c";
2801 2638
2802 drive-strengt 2639 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2640 bias-pull-down;
2804 }; 2641 };
2805 2642
2806 qspi_clk: qspi-clk-st !! 2643 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2644 pinmux {
2808 function = "q !! 2645 pins = "gpio95";
2809 }; !! 2646 function = "qspi_clk";
2810 !! 2647 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; 2648 };
2815 2649
2816 qspi_cs1: qspi-cs1-st !! 2650 qspi_cs0: qspi-cs0 {
2817 pins = "gpio8 !! 2651 pinmux {
2818 function = "q !! 2652 pins = "gpio90";
>> 2653 function = "qspi_cs";
>> 2654 };
2819 }; 2655 };
2820 2656
2821 qspi_data0: qspi-data !! 2657 qspi_cs1: qspi-cs1 {
2822 pins = "gpio9 !! 2658 pinmux {
2823 function = "q !! 2659 pins = "gpio89";
>> 2660 function = "qspi_cs";
>> 2661 };
2824 }; 2662 };
2825 2663
2826 qspi_data1: qspi-data !! 2664 qspi_data01: qspi-data01 {
2827 pins = "gpio9 !! 2665 pinmux-data {
2828 function = "q !! 2666 pins = "gpio91", "gpio92";
>> 2667 function = "qspi_data";
>> 2668 };
2829 }; 2669 };
2830 2670
2831 qspi_data23: qspi-dat !! 2671 qspi_data12: qspi-data12 {
2832 pins = "gpio9 !! 2672 pinmux-data {
2833 function = "q !! 2673 pins = "gpio93", "gpio94";
>> 2674 function = "qspi_data";
>> 2675 };
2834 }; 2676 };
2835 2677
2836 qup_i2c0_default: qup !! 2678 qup_i2c0_default: qup-i2c0-default {
2837 pins = "gpio0 !! 2679 pinmux {
2838 function = "q !! 2680 pins = "gpio0", "gpio1";
>> 2681 function = "qup0";
>> 2682 };
2839 }; 2683 };
2840 2684
2841 qup_i2c1_default: qup !! 2685 qup_i2c1_default: qup-i2c1-default {
2842 pins = "gpio1 !! 2686 pinmux {
2843 function = "q !! 2687 pins = "gpio17", "gpio18";
>> 2688 function = "qup1";
>> 2689 };
2844 }; 2690 };
2845 2691
2846 qup_i2c2_default: qup !! 2692 qup_i2c2_default: qup-i2c2-default {
2847 pins = "gpio2 !! 2693 pinmux {
2848 function = "q !! 2694 pins = "gpio27", "gpio28";
>> 2695 function = "qup2";
>> 2696 };
2849 }; 2697 };
2850 2698
2851 qup_i2c3_default: qup !! 2699 qup_i2c3_default: qup-i2c3-default {
2852 pins = "gpio4 !! 2700 pinmux {
2853 function = "q !! 2701 pins = "gpio41", "gpio42";
>> 2702 function = "qup3";
>> 2703 };
2854 }; 2704 };
2855 2705
2856 qup_i2c4_default: qup !! 2706 qup_i2c4_default: qup-i2c4-default {
2857 pins = "gpio8 !! 2707 pinmux {
2858 function = "q !! 2708 pins = "gpio89", "gpio90";
>> 2709 function = "qup4";
>> 2710 };
2859 }; 2711 };
2860 2712
2861 qup_i2c5_default: qup !! 2713 qup_i2c5_default: qup-i2c5-default {
2862 pins = "gpio8 !! 2714 pinmux {
2863 function = "q !! 2715 pins = "gpio85", "gpio86";
>> 2716 function = "qup5";
>> 2717 };
2864 }; 2718 };
2865 2719
2866 qup_i2c6_default: qup !! 2720 qup_i2c6_default: qup-i2c6-default {
2867 pins = "gpio4 !! 2721 pinmux {
2868 function = "q !! 2722 pins = "gpio45", "gpio46";
>> 2723 function = "qup6";
>> 2724 };
2869 }; 2725 };
2870 2726
2871 qup_i2c7_default: qup !! 2727 qup_i2c7_default: qup-i2c7-default {
2872 pins = "gpio9 !! 2728 pinmux {
2873 function = "q !! 2729 pins = "gpio93", "gpio94";
>> 2730 function = "qup7";
>> 2731 };
2874 }; 2732 };
2875 2733
2876 qup_i2c8_default: qup !! 2734 qup_i2c8_default: qup-i2c8-default {
2877 pins = "gpio6 !! 2735 pinmux {
2878 function = "q !! 2736 pins = "gpio65", "gpio66";
>> 2737 function = "qup8";
>> 2738 };
2879 }; 2739 };
2880 2740
2881 qup_i2c9_default: qup !! 2741 qup_i2c9_default: qup-i2c9-default {
2882 pins = "gpio6 !! 2742 pinmux {
2883 function = "q !! 2743 pins = "gpio6", "gpio7";
>> 2744 function = "qup9";
>> 2745 };
2884 }; 2746 };
2885 2747
2886 qup_i2c10_default: qu !! 2748 qup_i2c10_default: qup-i2c10-default {
2887 pins = "gpio5 !! 2749 pinmux {
2888 function = "q !! 2750 pins = "gpio55", "gpio56";
>> 2751 function = "qup10";
>> 2752 };
2889 }; 2753 };
2890 2754
2891 qup_i2c11_default: qu !! 2755 qup_i2c11_default: qup-i2c11-default {
2892 pins = "gpio3 !! 2756 pinmux {
2893 function = "q !! 2757 pins = "gpio31", "gpio32";
>> 2758 function = "qup11";
>> 2759 };
2894 }; 2760 };
2895 2761
2896 qup_i2c12_default: qu !! 2762 qup_i2c12_default: qup-i2c12-default {
2897 pins = "gpio4 !! 2763 pinmux {
2898 function = "q !! 2764 pins = "gpio49", "gpio50";
>> 2765 function = "qup12";
>> 2766 };
2899 }; 2767 };
2900 2768
2901 qup_i2c13_default: qu !! 2769 qup_i2c13_default: qup-i2c13-default {
2902 pins = "gpio1 !! 2770 pinmux {
2903 function = "q !! 2771 pins = "gpio105", "gpio106";
>> 2772 function = "qup13";
>> 2773 };
2904 }; 2774 };
2905 2775
2906 qup_i2c14_default: qu !! 2776 qup_i2c14_default: qup-i2c14-default {
2907 pins = "gpio3 !! 2777 pinmux {
2908 function = "q !! 2778 pins = "gpio33", "gpio34";
>> 2779 function = "qup14";
>> 2780 };
2909 }; 2781 };
2910 2782
2911 qup_i2c15_default: qu !! 2783 qup_i2c15_default: qup-i2c15-default {
2912 pins = "gpio8 !! 2784 pinmux {
2913 function = "q !! 2785 pins = "gpio81", "gpio82";
>> 2786 function = "qup15";
>> 2787 };
2914 }; 2788 };
2915 2789
2916 qup_spi0_default: qup !! 2790 qup_spi0_default: qup-spi0-default {
2917 pins = "gpio0 !! 2791 pinmux {
2918 function = "q !! 2792 pins = "gpio0", "gpio1",
2919 }; !! 2793 "gpio2", "gpio3";
>> 2794 function = "qup0";
>> 2795 };
2920 2796
2921 qup_spi1_default: qup !! 2797 config {
2922 pins = "gpio1 !! 2798 pins = "gpio0", "gpio1",
2923 function = "q !! 2799 "gpio2", "gpio3";
>> 2800 drive-strength = <6>;
>> 2801 bias-disable;
>> 2802 };
2924 }; 2803 };
2925 2804
2926 qup_spi2_default: qup !! 2805 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2806 pinmux {
2928 function = "q !! 2807 pins = "gpio17", "gpio18",
>> 2808 "gpio19", "gpio20";
>> 2809 function = "qup1";
>> 2810 };
2929 }; 2811 };
2930 2812
2931 qup_spi3_default: qup !! 2813 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2814 pinmux {
2933 function = "q !! 2815 pins = "gpio27", "gpio28",
>> 2816 "gpio29", "gpio30";
>> 2817 function = "qup2";
>> 2818 };
2934 }; 2819 };
2935 2820
2936 qup_spi4_default: qup !! 2821 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2822 pinmux {
2938 function = "q !! 2823 pins = "gpio41", "gpio42",
>> 2824 "gpio43", "gpio44";
>> 2825 function = "qup3";
>> 2826 };
2939 }; 2827 };
2940 2828
2941 qup_spi5_default: qup !! 2829 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2830 pinmux {
2943 function = "q !! 2831 pins = "gpio89", "gpio90",
>> 2832 "gpio91", "gpio92";
>> 2833 function = "qup4";
>> 2834 };
2944 }; 2835 };
2945 2836
2946 qup_spi6_default: qup !! 2837 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2838 pinmux {
2948 function = "q !! 2839 pins = "gpio85", "gpio86",
>> 2840 "gpio87", "gpio88";
>> 2841 function = "qup5";
>> 2842 };
2949 }; 2843 };
2950 2844
2951 qup_spi7_default: qup !! 2845 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2846 pinmux {
2953 function = "q !! 2847 pins = "gpio45", "gpio46",
>> 2848 "gpio47", "gpio48";
>> 2849 function = "qup6";
>> 2850 };
2954 }; 2851 };
2955 2852
2956 qup_spi8_default: qup !! 2853 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2854 pinmux {
2958 function = "q !! 2855 pins = "gpio93", "gpio94",
>> 2856 "gpio95", "gpio96";
>> 2857 function = "qup7";
>> 2858 };
2959 }; 2859 };
2960 2860
2961 qup_spi9_default: qup !! 2861 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2862 pinmux {
2963 function = "q !! 2863 pins = "gpio65", "gpio66",
>> 2864 "gpio67", "gpio68";
>> 2865 function = "qup8";
>> 2866 };
2964 }; 2867 };
2965 2868
2966 qup_spi10_default: qu !! 2869 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2870 pinmux {
2968 function = "q !! 2871 pins = "gpio6", "gpio7",
>> 2872 "gpio4", "gpio5";
>> 2873 function = "qup9";
>> 2874 };
2969 }; 2875 };
2970 2876
2971 qup_spi11_default: qu !! 2877 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2878 pinmux {
2973 function = "q !! 2879 pins = "gpio55", "gpio56",
>> 2880 "gpio53", "gpio54";
>> 2881 function = "qup10";
>> 2882 };
2974 }; 2883 };
2975 2884
2976 qup_spi12_default: qu !! 2885 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2886 pinmux {
2978 function = "q !! 2887 pins = "gpio31", "gpio32",
>> 2888 "gpio33", "gpio34";
>> 2889 function = "qup11";
>> 2890 };
2979 }; 2891 };
2980 2892
2981 qup_spi13_default: qu !! 2893 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2894 pinmux {
2983 function = "q !! 2895 pins = "gpio49", "gpio50",
>> 2896 "gpio51", "gpio52";
>> 2897 function = "qup12";
>> 2898 };
2984 }; 2899 };
2985 2900
2986 qup_spi14_default: qu !! 2901 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2902 pinmux {
2988 function = "q !! 2903 pins = "gpio105", "gpio106",
>> 2904 "gpio107", "gpio108";
>> 2905 function = "qup13";
>> 2906 };
2989 }; 2907 };
2990 2908
2991 qup_spi15_default: qu !! 2909 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2910 pinmux {
2993 function = "q !! 2911 pins = "gpio33", "gpio34",
>> 2912 "gpio31", "gpio32";
>> 2913 function = "qup14";
>> 2914 };
2994 }; 2915 };
2995 2916
2996 qup_uart0_default: qu !! 2917 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2918 pinmux {
2998 pins !! 2919 pins = "gpio81", "gpio82",
2999 funct !! 2920 "gpio83", "gpio84";
>> 2921 function = "qup15";
3000 }; 2922 };
>> 2923 };
3001 2924
3002 qup_uart0_rx: !! 2925 qup_uart0_default: qup-uart0-default {
3003 pins !! 2926 pinmux {
>> 2927 pins = "gpio2", "gpio3";
3004 funct 2928 function = "qup0";
3005 }; 2929 };
3006 }; 2930 };
3007 2931
3008 qup_uart1_default: qu !! 2932 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2933 pinmux {
3010 pins !! 2934 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2935 function = "qup1";
3017 }; 2936 };
3018 }; 2937 };
3019 2938
3020 qup_uart2_default: qu !! 2939 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2940 pinmux {
3022 pins !! 2941 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2942 function = "qup2";
3029 }; 2943 };
3030 }; 2944 };
3031 2945
3032 qup_uart3_default: qu !! 2946 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2947 pinmux {
3034 pins !! 2948 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2949 function = "qup3";
3041 }; 2950 };
3042 }; 2951 };
3043 2952
3044 qup_uart3_4pin: qup-u !! 2953 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2954 pinmux {
3046 pins !! 2955 pins = "gpio91", "gpio92";
3047 funct !! 2956 function = "qup4";
3048 }; 2957 };
>> 2958 };
3049 2959
3050 qup_uart3_4pi !! 2960 qup_uart5_default: qup-uart5-default {
3051 pins !! 2961 pinmux {
3052 funct !! 2962 pins = "gpio87", "gpio88";
>> 2963 function = "qup5";
3053 }; 2964 };
>> 2965 };
3054 2966
3055 qup_uart3_4pi !! 2967 qup_uart6_default: qup-uart6-default {
3056 pins !! 2968 pinmux {
3057 funct !! 2969 pins = "gpio47", "gpio48";
>> 2970 function = "qup6";
3058 }; 2971 };
3059 }; 2972 };
3060 2973
3061 qup_uart4_default: qu !! 2974 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 2975 pinmux {
3063 pins !! 2976 pins = "gpio95", "gpio96";
3064 funct !! 2977 function = "qup7";
3065 }; 2978 };
>> 2979 };
3066 2980
3067 qup_uart4_rx: !! 2981 qup_uart8_default: qup-uart8-default {
3068 pins !! 2982 pinmux {
3069 funct !! 2983 pins = "gpio67", "gpio68";
>> 2984 function = "qup8";
3070 }; 2985 };
3071 }; 2986 };
3072 2987
3073 qup_uart5_default: qu !! 2988 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 2989 pinmux {
3075 pins !! 2990 pins = "gpio4", "gpio5";
3076 funct !! 2991 function = "qup9";
3077 }; 2992 };
>> 2993 };
3078 2994
3079 qup_uart5_rx: !! 2995 qup_uart10_default: qup-uart10-default {
3080 pins !! 2996 pinmux {
3081 funct !! 2997 pins = "gpio53", "gpio54";
>> 2998 function = "qup10";
3082 }; 2999 };
3083 }; 3000 };
3084 3001
3085 qup_uart6_default: qu !! 3002 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 3003 pinmux {
3087 pins !! 3004 pins = "gpio33", "gpio34";
3088 funct !! 3005 function = "qup11";
3089 }; 3006 };
>> 3007 };
3090 3008
3091 qup_uart6_rx: !! 3009 qup_uart12_default: qup-uart12-default {
3092 pins !! 3010 pinmux {
3093 funct !! 3011 pins = "gpio51", "gpio52";
>> 3012 function = "qup12";
3094 }; 3013 };
3095 }; 3014 };
3096 3015
3097 qup_uart6_4pin: qup-u !! 3016 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 3017 pinmux {
3099 pins !! 3018 pins = "gpio107", "gpio108";
3100 funct !! 3019 function = "qup13";
3101 bias- <<
3102 }; 3020 };
>> 3021 };
3103 3022
3104 qup_uart6_4pi !! 3023 qup_uart14_default: qup-uart14-default {
3105 pins !! 3024 pinmux {
3106 funct !! 3025 pins = "gpio31", "gpio32";
3107 drive !! 3026 function = "qup14";
3108 bias- <<
3109 }; 3027 };
>> 3028 };
3110 3029
3111 qup_uart6_4pi !! 3030 qup_uart15_default: qup-uart15-default {
3112 pins !! 3031 pinmux {
3113 funct !! 3032 pins = "gpio83", "gpio84";
3114 bias- !! 3033 function = "qup15";
3115 }; 3034 };
3116 }; 3035 };
3117 3036
3118 qup_uart7_default: qu !! 3037 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 3038 mux {
3120 pins !! 3039 pins = "gpio58", "gpio59";
3121 funct !! 3040 function = "gpio";
3122 }; 3041 };
3123 3042
3124 qup_uart7_rx: !! 3043 config {
3125 pins !! 3044 pins = "gpio58", "gpio59";
3126 funct !! 3045 drive-strength = <2>;
>> 3046 bias-pull-down;
>> 3047 input-enable;
3127 }; 3048 };
3128 }; 3049 };
3129 3050
3130 qup_uart8_default: qu !! 3051 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 3052 mux {
3132 pins !! 3053 pins = "gpio58", "gpio59";
3133 funct !! 3054 function = "qua_mi2s";
3134 }; 3055 };
3135 3056
3136 qup_uart8_rx: !! 3057 config {
3137 pins !! 3058 pins = "gpio58", "gpio59";
3138 funct !! 3059 drive-strength = <8>;
>> 3060 bias-disable;
>> 3061 output-high;
3139 }; 3062 };
3140 }; 3063 };
3141 3064
3142 qup_uart9_default: qu !! 3065 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 3066 mux {
3144 pins !! 3067 pins = "gpio60";
3145 funct !! 3068 function = "gpio";
3146 }; 3069 };
3147 3070
3148 qup_uart9_rx: !! 3071 config {
3149 pins !! 3072 pins = "gpio60";
3150 funct !! 3073 drive-strength = <2>;
>> 3074 bias-pull-down;
>> 3075 input-enable;
3151 }; 3076 };
3152 }; 3077 };
3153 3078
3154 qup_uart10_default: q !! 3079 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 3080 mux {
3156 pins !! 3081 pins = "gpio60";
3157 funct !! 3082 function = "qua_mi2s";
3158 }; 3083 };
3159 3084
3160 qup_uart10_rx !! 3085 config {
3161 pins !! 3086 pins = "gpio60";
3162 funct !! 3087 drive-strength = <8>;
>> 3088 bias-disable;
3163 }; 3089 };
3164 }; 3090 };
3165 3091
3166 qup_uart11_default: q !! 3092 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 3093 mux {
3168 pins !! 3094 pins = "gpio61";
3169 funct !! 3095 function = "gpio";
3170 }; 3096 };
3171 3097
3172 qup_uart11_rx !! 3098 config {
3173 pins !! 3099 pins = "gpio61";
3174 funct !! 3100 drive-strength = <2>;
>> 3101 bias-pull-down;
>> 3102 input-enable;
3175 }; 3103 };
3176 }; 3104 };
3177 3105
3178 qup_uart12_default: q !! 3106 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 3107 mux {
3180 pins !! 3108 pins = "gpio61";
3181 funct !! 3109 function = "qua_mi2s";
3182 }; 3110 };
3183 3111
3184 qup_uart12_rx !! 3112 config {
3185 pins !! 3113 pins = "gpio61";
3186 funct !! 3114 drive-strength = <8>;
>> 3115 bias-disable;
3187 }; 3116 };
3188 }; 3117 };
3189 3118
3190 qup_uart13_default: q !! 3119 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 3120 mux {
3192 pins !! 3121 pins = "gpio62";
3193 funct !! 3122 function = "gpio";
3194 }; 3123 };
3195 3124
3196 qup_uart13_rx !! 3125 config {
3197 pins !! 3126 pins = "gpio62";
3198 funct !! 3127 drive-strength = <2>;
>> 3128 bias-pull-down;
>> 3129 input-enable;
3199 }; 3130 };
3200 }; 3131 };
3201 3132
3202 qup_uart14_default: q !! 3133 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 3134 mux {
3204 pins !! 3135 pins = "gpio62";
3205 funct !! 3136 function = "qua_mi2s";
3206 }; 3137 };
3207 3138
3208 qup_uart14_rx !! 3139 config {
3209 pins !! 3140 pins = "gpio62";
3210 funct !! 3141 drive-strength = <8>;
>> 3142 bias-disable;
3211 }; 3143 };
3212 }; 3144 };
3213 3145
3214 qup_uart15_default: q !! 3146 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 3147 mux {
3216 pins !! 3148 pins = "gpio63";
3217 funct !! 3149 function = "gpio";
3218 }; 3150 };
3219 3151
3220 qup_uart15_rx !! 3152 config {
3221 pins !! 3153 pins = "gpio63";
3222 funct !! 3154 drive-strength = <2>;
>> 3155 bias-pull-down;
>> 3156 input-enable;
3223 }; 3157 };
3224 }; 3158 };
3225 3159
3226 quat_mi2s_sleep: quat !! 3160 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 3161 mux {
3228 function = "g !! 3162 pins = "gpio63";
3229 drive-strengt !! 3163 function = "qua_mi2s";
3230 bias-pull-dow !! 3164 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 3165
3290 quat_mi2s_sd3_active: !! 3166 config {
3291 pins = "gpio6 !! 3167 pins = "gpio63";
3292 function = "q !! 3168 drive-strength = <8>;
3293 drive-strengt !! 3169 bias-disable;
3294 bias-disable; !! 3170 };
3295 }; 3171 };
3296 }; 3172 };
3297 3173
3298 mss_pil: remoteproc@4080000 { 3174 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 3175 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 3176 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 3177 reg-names = "qdsp6", "rmb";
3302 3178
3303 interrupts-extended = 3179 interrupts-extended =
3304 <&intc GIC_SP 3180 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 3181 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 3182 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 3183 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 3184 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 3185 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 3186 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 3187 "handover", "stop-ack",
3312 "sh 3188 "shutdown-ack";
3313 3189
3314 clocks = <&gcc GCC_MS 3190 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 3191 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 3192 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 3193 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 3194 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 3195 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 3196 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 3197 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 3198 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 3199 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 3200
3325 qcom,qmp = <&aoss_qmp 3201 qcom,qmp = <&aoss_qmp>;
3326 3202
3327 qcom,smem-states = <& 3203 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 3204 qcom,smem-state-names = "stop";
3329 3205
3330 resets = <&aoss_reset 3206 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 3207 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 3208 reset-names = "mss_restart", "pdc_reset";
3333 3209
3334 qcom,halt-regs = <&tc !! 3210 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
3335 3211
3336 power-domains = <&rpm 3212 power-domains = <&rpmhpd SDM845_CX>,
3337 <&rpm 3213 <&rpmhpd SDM845_MX>,
3338 <&rpm 3214 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = 3215 power-domain-names = "cx", "mx", "mss";
3340 3216
3341 status = "disabled"; 3217 status = "disabled";
3342 3218
3343 mba { 3219 mba {
3344 memory-region 3220 memory-region = <&mba_region>;
3345 }; 3221 };
3346 3222
3347 mpss { 3223 mpss {
3348 memory-region 3224 memory-region = <&mpss_region>;
3349 }; 3225 };
3350 3226
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 3227 glink-edge {
3356 interrupts = 3228 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3229 label = "modem";
3358 qcom,remote-p 3230 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3231 mboxes = <&apss_shared 12>;
3360 }; 3232 };
3361 }; 3233 };
3362 3234
3363 gpucc: clock-controller@50900 3235 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3236 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3237 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3238 #clock-cells = <1>;
3367 #reset-cells = <1>; 3239 #reset-cells = <1>;
3368 #power-domain-cells = 3240 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3241 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3242 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3243 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3244 clock-names = "bi_tcxo",
3373 "gcc_gp 3245 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3246 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3247 };
3376 3248
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 3249 stm@6002000 {
3431 compatible = "arm,cor 3250 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3251 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3252 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3253 reg-names = "stm-base", "stm-stimulus-base";
3435 3254
3436 clocks = <&aoss_qmp>; 3255 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3256 clock-names = "apb_pclk";
3438 3257
3439 out-ports { 3258 out-ports {
3440 port { 3259 port {
3441 stm_o 3260 stm_out: endpoint {
3442 3261 remote-endpoint =
3443 3262 <&funnel0_in7>;
3444 }; 3263 };
3445 }; 3264 };
3446 }; 3265 };
3447 }; 3266 };
3448 3267
3449 funnel@6041000 { 3268 funnel@6041000 {
3450 compatible = "arm,cor 3269 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3270 reg = <0 0x06041000 0 0x1000>;
3452 3271
3453 clocks = <&aoss_qmp>; 3272 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3273 clock-names = "apb_pclk";
3455 3274
3456 out-ports { 3275 out-ports {
3457 port { 3276 port {
3458 funne 3277 funnel0_out: endpoint {
3459 3278 remote-endpoint =
3460 3279 <&merge_funnel_in0>;
3461 }; 3280 };
3462 }; 3281 };
3463 }; 3282 };
3464 3283
3465 in-ports { 3284 in-ports {
3466 #address-cell 3285 #address-cells = <1>;
3467 #size-cells = 3286 #size-cells = <0>;
3468 3287
3469 port@7 { 3288 port@7 {
3470 reg = 3289 reg = <7>;
3471 funne 3290 funnel0_in7: endpoint {
3472 3291 remote-endpoint = <&stm_out>;
3473 }; 3292 };
3474 }; 3293 };
3475 }; 3294 };
3476 }; 3295 };
3477 3296
3478 funnel@6043000 { 3297 funnel@6043000 {
3479 compatible = "arm,cor 3298 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3299 reg = <0 0x06043000 0 0x1000>;
3481 3300
3482 clocks = <&aoss_qmp>; 3301 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3302 clock-names = "apb_pclk";
3484 3303
3485 out-ports { 3304 out-ports {
3486 port { 3305 port {
3487 funne 3306 funnel2_out: endpoint {
3488 3307 remote-endpoint =
3489 3308 <&merge_funnel_in2>;
3490 }; 3309 };
3491 }; 3310 };
3492 }; 3311 };
3493 3312
3494 in-ports { 3313 in-ports {
3495 #address-cell 3314 #address-cells = <1>;
3496 #size-cells = 3315 #size-cells = <0>;
3497 3316
3498 port@5 { 3317 port@5 {
3499 reg = 3318 reg = <5>;
3500 funne 3319 funnel2_in5: endpoint {
3501 3320 remote-endpoint =
3502 3321 <&apss_merge_funnel_out>;
3503 }; 3322 };
3504 }; 3323 };
3505 }; 3324 };
3506 }; 3325 };
3507 3326
3508 funnel@6045000 { 3327 funnel@6045000 {
3509 compatible = "arm,cor 3328 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3329 reg = <0 0x06045000 0 0x1000>;
3511 3330
3512 clocks = <&aoss_qmp>; 3331 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3332 clock-names = "apb_pclk";
3514 3333
3515 out-ports { 3334 out-ports {
3516 port { 3335 port {
3517 merge 3336 merge_funnel_out: endpoint {
3518 3337 remote-endpoint = <&etf_in>;
3519 }; 3338 };
3520 }; 3339 };
3521 }; 3340 };
3522 3341
3523 in-ports { 3342 in-ports {
3524 #address-cell 3343 #address-cells = <1>;
3525 #size-cells = 3344 #size-cells = <0>;
3526 3345
3527 port@0 { 3346 port@0 {
3528 reg = 3347 reg = <0>;
3529 merge 3348 merge_funnel_in0: endpoint {
3530 3349 remote-endpoint =
3531 3350 <&funnel0_out>;
3532 }; 3351 };
3533 }; 3352 };
3534 3353
3535 port@2 { 3354 port@2 {
3536 reg = 3355 reg = <2>;
3537 merge 3356 merge_funnel_in2: endpoint {
3538 3357 remote-endpoint =
3539 3358 <&funnel2_out>;
3540 }; 3359 };
3541 }; 3360 };
3542 }; 3361 };
3543 }; 3362 };
3544 3363
3545 replicator@6046000 { 3364 replicator@6046000 {
3546 compatible = "arm,cor 3365 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3366 reg = <0 0x06046000 0 0x1000>;
3548 3367
3549 clocks = <&aoss_qmp>; 3368 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3369 clock-names = "apb_pclk";
3551 3370
3552 out-ports { 3371 out-ports {
3553 port { 3372 port {
3554 repli 3373 replicator_out: endpoint {
3555 3374 remote-endpoint = <&etr_in>;
3556 }; 3375 };
3557 }; 3376 };
3558 }; 3377 };
3559 3378
3560 in-ports { 3379 in-ports {
3561 port { 3380 port {
3562 repli 3381 replicator_in: endpoint {
3563 3382 remote-endpoint = <&etf_out>;
3564 }; 3383 };
3565 }; 3384 };
3566 }; 3385 };
3567 }; 3386 };
3568 3387
3569 etf@6047000 { 3388 etf@6047000 {
3570 compatible = "arm,cor 3389 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3390 reg = <0 0x06047000 0 0x1000>;
3572 3391
3573 clocks = <&aoss_qmp>; 3392 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3393 clock-names = "apb_pclk";
3575 3394
3576 out-ports { 3395 out-ports {
3577 port { 3396 port {
3578 etf_o 3397 etf_out: endpoint {
3579 3398 remote-endpoint =
3580 3399 <&replicator_in>;
3581 }; 3400 };
3582 }; 3401 };
3583 }; 3402 };
3584 3403
3585 in-ports { 3404 in-ports {
>> 3405 #address-cells = <1>;
>> 3406 #size-cells = <0>;
3586 3407
3587 port { !! 3408 port@1 {
>> 3409 reg = <1>;
3588 etf_i 3410 etf_in: endpoint {
3589 3411 remote-endpoint =
3590 3412 <&merge_funnel_out>;
3591 }; 3413 };
3592 }; 3414 };
3593 }; 3415 };
3594 }; 3416 };
3595 3417
3596 etr@6048000 { 3418 etr@6048000 {
3597 compatible = "arm,cor 3419 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3420 reg = <0 0x06048000 0 0x1000>;
3599 3421
3600 clocks = <&aoss_qmp>; 3422 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3423 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3424 arm,scatter-gather;
3603 3425
3604 in-ports { 3426 in-ports {
3605 port { 3427 port {
3606 etr_i 3428 etr_in: endpoint {
3607 3429 remote-endpoint =
3608 3430 <&replicator_out>;
3609 }; 3431 };
3610 }; 3432 };
3611 }; 3433 };
3612 }; 3434 };
3613 3435
3614 etm@7040000 { 3436 etm@7040000 {
3615 compatible = "arm,cor 3437 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3438 reg = <0 0x07040000 0 0x1000>;
3617 3439
3618 cpu = <&CPU0>; 3440 cpu = <&CPU0>;
3619 3441
3620 clocks = <&aoss_qmp>; 3442 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3443 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3444 arm,coresight-loses-context-with-cpu;
3623 3445
3624 out-ports { 3446 out-ports {
3625 port { 3447 port {
3626 etm0_ 3448 etm0_out: endpoint {
3627 3449 remote-endpoint =
3628 3450 <&apss_funnel_in0>;
3629 }; 3451 };
3630 }; 3452 };
3631 }; 3453 };
3632 }; 3454 };
3633 3455
3634 etm@7140000 { 3456 etm@7140000 {
3635 compatible = "arm,cor 3457 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3458 reg = <0 0x07140000 0 0x1000>;
3637 3459
3638 cpu = <&CPU1>; 3460 cpu = <&CPU1>;
3639 3461
3640 clocks = <&aoss_qmp>; 3462 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3463 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3464 arm,coresight-loses-context-with-cpu;
3643 3465
3644 out-ports { 3466 out-ports {
3645 port { 3467 port {
3646 etm1_ 3468 etm1_out: endpoint {
3647 3469 remote-endpoint =
3648 3470 <&apss_funnel_in1>;
3649 }; 3471 };
3650 }; 3472 };
3651 }; 3473 };
3652 }; 3474 };
3653 3475
3654 etm@7240000 { 3476 etm@7240000 {
3655 compatible = "arm,cor 3477 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3478 reg = <0 0x07240000 0 0x1000>;
3657 3479
3658 cpu = <&CPU2>; 3480 cpu = <&CPU2>;
3659 3481
3660 clocks = <&aoss_qmp>; 3482 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3483 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3484 arm,coresight-loses-context-with-cpu;
3663 3485
3664 out-ports { 3486 out-ports {
3665 port { 3487 port {
3666 etm2_ 3488 etm2_out: endpoint {
3667 3489 remote-endpoint =
3668 3490 <&apss_funnel_in2>;
3669 }; 3491 };
3670 }; 3492 };
3671 }; 3493 };
3672 }; 3494 };
3673 3495
3674 etm@7340000 { 3496 etm@7340000 {
3675 compatible = "arm,cor 3497 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3498 reg = <0 0x07340000 0 0x1000>;
3677 3499
3678 cpu = <&CPU3>; 3500 cpu = <&CPU3>;
3679 3501
3680 clocks = <&aoss_qmp>; 3502 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3503 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3504 arm,coresight-loses-context-with-cpu;
3683 3505
3684 out-ports { 3506 out-ports {
3685 port { 3507 port {
3686 etm3_ 3508 etm3_out: endpoint {
3687 3509 remote-endpoint =
3688 3510 <&apss_funnel_in3>;
3689 }; 3511 };
3690 }; 3512 };
3691 }; 3513 };
3692 }; 3514 };
3693 3515
3694 etm@7440000 { 3516 etm@7440000 {
3695 compatible = "arm,cor 3517 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3518 reg = <0 0x07440000 0 0x1000>;
3697 3519
3698 cpu = <&CPU4>; 3520 cpu = <&CPU4>;
3699 3521
3700 clocks = <&aoss_qmp>; 3522 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3523 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3524 arm,coresight-loses-context-with-cpu;
3703 3525
3704 out-ports { 3526 out-ports {
3705 port { 3527 port {
3706 etm4_ 3528 etm4_out: endpoint {
3707 3529 remote-endpoint =
3708 3530 <&apss_funnel_in4>;
3709 }; 3531 };
3710 }; 3532 };
3711 }; 3533 };
3712 }; 3534 };
3713 3535
3714 etm@7540000 { 3536 etm@7540000 {
3715 compatible = "arm,cor 3537 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3538 reg = <0 0x07540000 0 0x1000>;
3717 3539
3718 cpu = <&CPU5>; 3540 cpu = <&CPU5>;
3719 3541
3720 clocks = <&aoss_qmp>; 3542 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3543 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3544 arm,coresight-loses-context-with-cpu;
3723 3545
3724 out-ports { 3546 out-ports {
3725 port { 3547 port {
3726 etm5_ 3548 etm5_out: endpoint {
3727 3549 remote-endpoint =
3728 3550 <&apss_funnel_in5>;
3729 }; 3551 };
3730 }; 3552 };
3731 }; 3553 };
3732 }; 3554 };
3733 3555
3734 etm@7640000 { 3556 etm@7640000 {
3735 compatible = "arm,cor 3557 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3558 reg = <0 0x07640000 0 0x1000>;
3737 3559
3738 cpu = <&CPU6>; 3560 cpu = <&CPU6>;
3739 3561
3740 clocks = <&aoss_qmp>; 3562 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3563 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3564 arm,coresight-loses-context-with-cpu;
3743 3565
3744 out-ports { 3566 out-ports {
3745 port { 3567 port {
3746 etm6_ 3568 etm6_out: endpoint {
3747 3569 remote-endpoint =
3748 3570 <&apss_funnel_in6>;
3749 }; 3571 };
3750 }; 3572 };
3751 }; 3573 };
3752 }; 3574 };
3753 3575
3754 etm@7740000 { 3576 etm@7740000 {
3755 compatible = "arm,cor 3577 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3578 reg = <0 0x07740000 0 0x1000>;
3757 3579
3758 cpu = <&CPU7>; 3580 cpu = <&CPU7>;
3759 3581
3760 clocks = <&aoss_qmp>; 3582 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3583 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3584 arm,coresight-loses-context-with-cpu;
3763 3585
3764 out-ports { 3586 out-ports {
3765 port { 3587 port {
3766 etm7_ 3588 etm7_out: endpoint {
3767 3589 remote-endpoint =
3768 3590 <&apss_funnel_in7>;
3769 }; 3591 };
3770 }; 3592 };
3771 }; 3593 };
3772 }; 3594 };
3773 3595
3774 funnel@7800000 { /* APSS Funn 3596 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3597 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3598 reg = <0 0x07800000 0 0x1000>;
3777 3599
3778 clocks = <&aoss_qmp>; 3600 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3601 clock-names = "apb_pclk";
3780 3602
3781 out-ports { 3603 out-ports {
3782 port { 3604 port {
3783 apss_ 3605 apss_funnel_out: endpoint {
3784 3606 remote-endpoint =
3785 3607 <&apss_merge_funnel_in>;
3786 }; 3608 };
3787 }; 3609 };
3788 }; 3610 };
3789 3611
3790 in-ports { 3612 in-ports {
3791 #address-cell 3613 #address-cells = <1>;
3792 #size-cells = 3614 #size-cells = <0>;
3793 3615
3794 port@0 { 3616 port@0 {
3795 reg = 3617 reg = <0>;
3796 apss_ 3618 apss_funnel_in0: endpoint {
3797 3619 remote-endpoint =
3798 3620 <&etm0_out>;
3799 }; 3621 };
3800 }; 3622 };
3801 3623
3802 port@1 { 3624 port@1 {
3803 reg = 3625 reg = <1>;
3804 apss_ 3626 apss_funnel_in1: endpoint {
3805 3627 remote-endpoint =
3806 3628 <&etm1_out>;
3807 }; 3629 };
3808 }; 3630 };
3809 3631
3810 port@2 { 3632 port@2 {
3811 reg = 3633 reg = <2>;
3812 apss_ 3634 apss_funnel_in2: endpoint {
3813 3635 remote-endpoint =
3814 3636 <&etm2_out>;
3815 }; 3637 };
3816 }; 3638 };
3817 3639
3818 port@3 { 3640 port@3 {
3819 reg = 3641 reg = <3>;
3820 apss_ 3642 apss_funnel_in3: endpoint {
3821 3643 remote-endpoint =
3822 3644 <&etm3_out>;
3823 }; 3645 };
3824 }; 3646 };
3825 3647
3826 port@4 { 3648 port@4 {
3827 reg = 3649 reg = <4>;
3828 apss_ 3650 apss_funnel_in4: endpoint {
3829 3651 remote-endpoint =
3830 3652 <&etm4_out>;
3831 }; 3653 };
3832 }; 3654 };
3833 3655
3834 port@5 { 3656 port@5 {
3835 reg = 3657 reg = <5>;
3836 apss_ 3658 apss_funnel_in5: endpoint {
3837 3659 remote-endpoint =
3838 3660 <&etm5_out>;
3839 }; 3661 };
3840 }; 3662 };
3841 3663
3842 port@6 { 3664 port@6 {
3843 reg = 3665 reg = <6>;
3844 apss_ 3666 apss_funnel_in6: endpoint {
3845 3667 remote-endpoint =
3846 3668 <&etm6_out>;
3847 }; 3669 };
3848 }; 3670 };
3849 3671
3850 port@7 { 3672 port@7 {
3851 reg = 3673 reg = <7>;
3852 apss_ 3674 apss_funnel_in7: endpoint {
3853 3675 remote-endpoint =
3854 3676 <&etm7_out>;
3855 }; 3677 };
3856 }; 3678 };
3857 }; 3679 };
3858 }; 3680 };
3859 3681
3860 funnel@7810000 { 3682 funnel@7810000 {
3861 compatible = "arm,cor 3683 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3684 reg = <0 0x07810000 0 0x1000>;
3863 3685
3864 clocks = <&aoss_qmp>; 3686 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3687 clock-names = "apb_pclk";
3866 3688
3867 out-ports { 3689 out-ports {
3868 port { 3690 port {
3869 apss_ 3691 apss_merge_funnel_out: endpoint {
3870 3692 remote-endpoint =
3871 3693 <&funnel2_in5>;
3872 }; 3694 };
3873 }; 3695 };
3874 }; 3696 };
3875 3697
3876 in-ports { 3698 in-ports {
3877 port { 3699 port {
3878 apss_ 3700 apss_merge_funnel_in: endpoint {
3879 3701 remote-endpoint =
3880 3702 <&apss_funnel_out>;
3881 }; 3703 };
3882 }; 3704 };
3883 }; 3705 };
3884 }; 3706 };
3885 3707
3886 sdhc_2: mmc@8804000 { 3708 sdhc_2: mmc@8804000 {
3887 compatible = "qcom,sd 3709 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3710 reg = <0 0x08804000 0 0x1000>;
3889 3711
3890 interrupts = <GIC_SPI 3712 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3713 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3714 interrupt-names = "hc_irq", "pwr_irq";
3893 3715
3894 clocks = <&gcc GCC_SD 3716 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD 3717 <&gcc GCC_SDCC2_APPS_CLK>,
3896 <&rpmhcc RPM 3718 <&rpmhcc RPMH_CXO_CLK>;
3897 clock-names = "iface" 3719 clock-names = "iface", "core", "xo";
3898 iommus = <&apps_smmu 3720 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3721 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3722 operating-points-v2 = <&sdhc2_opp_table>;
3901 3723
3902 status = "disabled"; 3724 status = "disabled";
3903 3725
3904 sdhc2_opp_table: opp- 3726 sdhc2_opp_table: opp-table {
3905 compatible = 3727 compatible = "operating-points-v2";
3906 3728
3907 opp-9600000 { 3729 opp-9600000 {
3908 opp-h 3730 opp-hz = /bits/ 64 <9600000>;
3909 requi 3731 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3732 };
3911 3733
3912 opp-19200000 3734 opp-19200000 {
3913 opp-h 3735 opp-hz = /bits/ 64 <19200000>;
3914 requi 3736 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3737 };
3916 3738
3917 opp-100000000 3739 opp-100000000 {
3918 opp-h 3740 opp-hz = /bits/ 64 <100000000>;
3919 requi 3741 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3742 };
3921 3743
3922 opp-201500000 3744 opp-201500000 {
3923 opp-h 3745 opp-hz = /bits/ 64 <201500000>;
3924 requi 3746 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3747 };
3926 }; 3748 };
3927 }; 3749 };
3928 3750
>> 3751 qspi_opp_table: opp-table-qspi {
>> 3752 compatible = "operating-points-v2";
>> 3753
>> 3754 opp-19200000 {
>> 3755 opp-hz = /bits/ 64 <19200000>;
>> 3756 required-opps = <&rpmhpd_opp_min_svs>;
>> 3757 };
>> 3758
>> 3759 opp-100000000 {
>> 3760 opp-hz = /bits/ 64 <100000000>;
>> 3761 required-opps = <&rpmhpd_opp_low_svs>;
>> 3762 };
>> 3763
>> 3764 opp-150000000 {
>> 3765 opp-hz = /bits/ 64 <150000000>;
>> 3766 required-opps = <&rpmhpd_opp_svs>;
>> 3767 };
>> 3768
>> 3769 opp-300000000 {
>> 3770 opp-hz = /bits/ 64 <300000000>;
>> 3771 required-opps = <&rpmhpd_opp_nom>;
>> 3772 };
>> 3773 };
>> 3774
3929 qspi: spi@88df000 { 3775 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3776 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3777 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3778 #address-cells = <1>;
3934 #size-cells = <0>; 3779 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3780 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3781 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3782 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3783 clock-names = "iface", "core";
3939 power-domains = <&rpm 3784 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3785 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3786 status = "disabled";
3942 }; 3787 };
3943 3788
3944 slim: slim-ngd@171c0000 { !! 3789 slim: slim@171c0000 {
3945 compatible = "qcom,sl 3790 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3791 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3792 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3793
3949 dmas = <&slimbam 3>, !! 3794 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 3795 qcom,ea-pc = <0x270>;
>> 3796 status = "okay";
>> 3797 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3798 <&slimbam 5>, <&slimbam 6>;
>> 3799 dma-names = "rx", "tx", "tx2", "rx2";
3951 3800
3952 iommus = <&apps_smmu 3801 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3802 #address-cells = <1>;
3954 #size-cells = <0>; 3803 #size-cells = <0>;
3955 status = "disabled"; !! 3804
>> 3805 ngd@1 {
>> 3806 reg = <1>;
>> 3807 #address-cells = <2>;
>> 3808 #size-cells = <0>;
>> 3809
>> 3810 wcd9340_ifd: ifd@0{
>> 3811 compatible = "slim217,250";
>> 3812 reg = <0 0>;
>> 3813 };
>> 3814
>> 3815 wcd9340: codec@1{
>> 3816 compatible = "slim217,250";
>> 3817 reg = <1 0>;
>> 3818 slim-ifc-dev = <&wcd9340_ifd>;
>> 3819
>> 3820 #sound-dai-cells = <1>;
>> 3821
>> 3822 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3823 interrupt-controller;
>> 3824 #interrupt-cells = <1>;
>> 3825
>> 3826 #clock-cells = <0>;
>> 3827 clock-frequency = <9600000>;
>> 3828 clock-output-names = "mclk";
>> 3829 qcom,micbias1-microvolt = <1800000>;
>> 3830 qcom,micbias2-microvolt = <1800000>;
>> 3831 qcom,micbias3-microvolt = <1800000>;
>> 3832 qcom,micbias4-microvolt = <1800000>;
>> 3833
>> 3834 #address-cells = <1>;
>> 3835 #size-cells = <1>;
>> 3836
>> 3837 wcdgpio: gpio-controller@42 {
>> 3838 compatible = "qcom,wcd9340-gpio";
>> 3839 gpio-controller;
>> 3840 #gpio-cells = <2>;
>> 3841 reg = <0x42 0x2>;
>> 3842 };
>> 3843
>> 3844 swm: swm@c85 {
>> 3845 compatible = "qcom,soundwire-v1.3.0";
>> 3846 reg = <0xc85 0x40>;
>> 3847 interrupts-extended = <&wcd9340 20>;
>> 3848
>> 3849 qcom,dout-ports = <6>;
>> 3850 qcom,din-ports = <2>;
>> 3851 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3852 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3853 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3854
>> 3855 #sound-dai-cells = <1>;
>> 3856 clocks = <&wcd9340>;
>> 3857 clock-names = "iface";
>> 3858 #address-cells = <2>;
>> 3859 #size-cells = <0>;
>> 3860
>> 3861
>> 3862 };
>> 3863 };
>> 3864 };
3956 }; 3865 };
3957 3866
3958 lmh_cluster1: lmh@17d70800 { 3867 lmh_cluster1: lmh@17d70800 {
3959 compatible = "qcom,sd 3868 compatible = "qcom,sdm845-lmh";
3960 reg = <0 0x17d70800 0 3869 reg = <0 0x17d70800 0 0x400>;
3961 interrupts = <GIC_SPI 3870 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962 cpus = <&CPU4>; 3871 cpus = <&CPU4>;
3963 qcom,lmh-temp-arm-mil 3872 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-mil 3873 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-mi 3874 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller; 3875 interrupt-controller;
3967 #interrupt-cells = <1 3876 #interrupt-cells = <1>;
3968 }; 3877 };
3969 3878
3970 lmh_cluster0: lmh@17d78800 { 3879 lmh_cluster0: lmh@17d78800 {
3971 compatible = "qcom,sd 3880 compatible = "qcom,sdm845-lmh";
3972 reg = <0 0x17d78800 0 3881 reg = <0 0x17d78800 0 0x400>;
3973 interrupts = <GIC_SPI 3882 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974 cpus = <&CPU0>; 3883 cpus = <&CPU0>;
3975 qcom,lmh-temp-arm-mil 3884 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-mil 3885 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-mi 3886 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller; 3887 interrupt-controller;
3979 #interrupt-cells = <1 3888 #interrupt-cells = <1>;
3980 }; 3889 };
3981 3890
>> 3891 sound: sound {
>> 3892 };
>> 3893
3982 usb_1_hsphy: phy@88e2000 { 3894 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3895 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3896 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3897 status = "disabled";
3986 #phy-cells = <0>; 3898 #phy-cells = <0>;
3987 3899
3988 clocks = <&gcc GCC_US 3900 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3901 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3902 clock-names = "cfg_ahb", "ref";
3991 3903
3992 resets = <&gcc GCC_QU 3904 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3905
3994 nvmem-cells = <&qusb2 3906 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3907 };
3996 3908
3997 usb_2_hsphy: phy@88e3000 { 3909 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3910 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3911 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3912 status = "disabled";
4001 #phy-cells = <0>; 3913 #phy-cells = <0>;
4002 3914
4003 clocks = <&gcc GCC_US 3915 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3916 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3917 clock-names = "cfg_ahb", "ref";
4006 3918
4007 resets = <&gcc GCC_QU 3919 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3920
4009 nvmem-cells = <&qusb2 3921 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3922 };
4011 3923
4012 usb_1_qmpphy: phy@88e8000 { !! 3924 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3925 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3926 reg = <0 0x088e9000 0 0x18c>,
>> 3927 <0 0x088e8000 0 0x10>;
4015 status = "disabled"; 3928 status = "disabled";
>> 3929 #address-cells = <2>;
>> 3930 #size-cells = <2>;
>> 3931 ranges;
4016 3932
4017 clocks = <&gcc GCC_US 3933 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3934 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3935 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3936 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3937 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3938
4028 resets = <&gcc GCC_US !! 3939 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3940 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3941 reset-names = "phy", "common";
4031 3942
4032 #clock-cells = <1>; !! 3943 usb_1_ssphy: phy@88e9200 {
4033 #phy-cells = <1>; !! 3944 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3945 <0 0x088e9400 0 0x200>,
4035 !! 3946 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3947 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3948 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3949 <0 0x088e9a00 0 0x100>;
4039 !! 3950 #clock-cells = <0>;
4040 port@0 { !! 3951 #phy-cells = <0>;
4041 reg = !! 3952 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042 !! 3953 clock-names = "pipe0";
4043 usb_1 !! 3954 clock-output-names = "usb3_phy_pipe_clk_src";
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3955 };
4063 }; 3956 };
4064 3957
4065 usb_2_qmpphy: phy@88eb000 { 3958 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3959 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 3960 reg = <0 0x088eb000 0 0x18c>;
>> 3961 status = "disabled";
>> 3962 #address-cells = <2>;
>> 3963 #size-cells = <2>;
>> 3964 ranges;
4068 3965
4069 clocks = <&gcc GCC_US 3966 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 3967 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 3968 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 3969 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 3970 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 3971
4083 resets = <&gcc GCC_US !! 3972 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 3973 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 3974 reset-names = "phy", "common";
4086 "phy_ph <<
4087 3975
4088 status = "disabled"; !! 3976 usb_2_ssphy: phy@88eb200 {
>> 3977 reg = <0 0x088eb200 0 0x128>,
>> 3978 <0 0x088eb400 0 0x1fc>,
>> 3979 <0 0x088eb800 0 0x218>,
>> 3980 <0 0x088eb600 0 0x70>;
>> 3981 #clock-cells = <0>;
>> 3982 #phy-cells = <0>;
>> 3983 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3984 clock-names = "pipe0";
>> 3985 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3986 };
4089 }; 3987 };
4090 3988
4091 usb_1: usb@a6f8800 { 3989 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 3990 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 3991 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 3992 status = "disabled";
4095 #address-cells = <2>; 3993 #address-cells = <2>;
4096 #size-cells = <2>; 3994 #size-cells = <2>;
4097 ranges; 3995 ranges;
4098 dma-ranges; 3996 dma-ranges;
4099 3997
4100 clocks = <&gcc GCC_CF 3998 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 3999 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 4000 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US 4001 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4104 <&gcc GCC_US 4002 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4105 clock-names = "cfg_no 4003 clock-names = "cfg_noc",
4106 "core", 4004 "core",
4107 "iface" 4005 "iface",
4108 "sleep" 4006 "sleep",
4109 "mock_u 4007 "mock_utmi";
4110 4008
4111 assigned-clocks = <&g 4009 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 4010 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 4011 assigned-clock-rates = <19200000>, <150000000>;
4114 4012
4115 interrupts-extended = !! 4013 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 4014 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 4015 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 4016 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 4017 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 4018 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 4019
4126 power-domains = <&gcc 4020 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 4021
4128 resets = <&gcc GCC_US 4022 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 4023
4130 interconnects = <&agg 4024 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 4025 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 4026 interconnect-names = "usb-ddr", "apps-usb";
4133 4027
4134 usb_1_dwc3: usb@a6000 4028 usb_1_dwc3: usb@a600000 {
4135 compatible = 4029 compatible = "snps,dwc3";
4136 reg = <0 0x0a 4030 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 4031 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 4032 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 4033 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 4034 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 4035 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 4036 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 4037 };
4165 }; 4038 };
4166 4039
4167 usb_2: usb@a8f8800 { 4040 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 4041 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 4042 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 4043 status = "disabled";
4171 #address-cells = <2>; 4044 #address-cells = <2>;
4172 #size-cells = <2>; 4045 #size-cells = <2>;
4173 ranges; 4046 ranges;
4174 dma-ranges; 4047 dma-ranges;
4175 4048
4176 clocks = <&gcc GCC_CF 4049 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 4050 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 4051 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US 4052 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4180 <&gcc GCC_US 4053 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4181 clock-names = "cfg_no 4054 clock-names = "cfg_noc",
4182 "core", 4055 "core",
4183 "iface" 4056 "iface",
4184 "sleep" 4057 "sleep",
4185 "mock_u 4058 "mock_utmi";
4186 4059
4187 assigned-clocks = <&g 4060 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 4061 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 4062 assigned-clock-rates = <19200000>, <150000000>;
4190 4063
4191 interrupts-extended = !! 4064 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 4065 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 4066 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 4067 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 4068 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 4069 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 4070
4202 power-domains = <&gcc 4071 power-domains = <&gcc USB30_SEC_GDSC>;
4203 4072
4204 resets = <&gcc GCC_US 4073 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 4074
4206 interconnects = <&agg 4075 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 4076 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 4077 interconnect-names = "usb-ddr", "apps-usb";
4209 4078
4210 usb_2_dwc3: usb@a8000 4079 usb_2_dwc3: usb@a800000 {
4211 compatible = 4080 compatible = "snps,dwc3";
4212 reg = <0 0x0a 4081 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 4082 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 4083 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 4084 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 4085 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 4086 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 4087 phy-names = "usb2-phy", "usb3-phy";
4220 }; 4088 };
4221 }; 4089 };
4222 4090
4223 venus: video-codec@aa00000 { 4091 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 4092 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 4093 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 4094 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 4095 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 4096 <&videocc VCODEC0_GDSC>,
4229 <&vid 4097 <&videocc VCODEC1_GDSC>,
4230 <&rpm 4098 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 4099 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 4100 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 4101 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 4102 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 4103 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 4104 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 4105 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 4106 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 4107 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 4108 clock-names = "core", "iface", "bus",
4241 "vcodec 4109 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 4110 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 4111 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 4112 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 4113 memory-region = <&venus_mem>;
4246 interconnects = <&mms 4114 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 4115 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 4116 interconnect-names = "video-mem", "cpu-cfg";
4249 4117
4250 status = "disabled"; 4118 status = "disabled";
4251 4119
4252 video-core0 { 4120 video-core0 {
4253 compatible = 4121 compatible = "venus-decoder";
4254 }; 4122 };
4255 4123
4256 video-core1 { 4124 video-core1 {
4257 compatible = 4125 compatible = "venus-encoder";
4258 }; 4126 };
4259 4127
4260 venus_opp_table: opp- 4128 venus_opp_table: opp-table {
4261 compatible = 4129 compatible = "operating-points-v2";
4262 4130
4263 opp-100000000 4131 opp-100000000 {
4264 opp-h 4132 opp-hz = /bits/ 64 <100000000>;
4265 requi 4133 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 4134 };
4267 4135
4268 opp-200000000 4136 opp-200000000 {
4269 opp-h 4137 opp-hz = /bits/ 64 <200000000>;
4270 requi 4138 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 4139 };
4272 4140
4273 opp-320000000 4141 opp-320000000 {
4274 opp-h 4142 opp-hz = /bits/ 64 <320000000>;
4275 requi 4143 required-opps = <&rpmhpd_opp_svs>;
4276 }; 4144 };
4277 4145
4278 opp-380000000 4146 opp-380000000 {
4279 opp-h 4147 opp-hz = /bits/ 64 <380000000>;
4280 requi 4148 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 4149 };
4282 4150
4283 opp-444000000 4151 opp-444000000 {
4284 opp-h 4152 opp-hz = /bits/ 64 <444000000>;
4285 requi 4153 required-opps = <&rpmhpd_opp_nom>;
4286 }; 4154 };
4287 4155
4288 opp-533000097 4156 opp-533000097 {
4289 opp-h 4157 opp-hz = /bits/ 64 <533000097>;
4290 requi 4158 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 4159 };
4292 }; 4160 };
4293 }; 4161 };
4294 4162
4295 videocc: clock-controller@ab0 4163 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 4164 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 4165 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 4166 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 4167 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 4168 #clock-cells = <1>;
4301 #power-domain-cells = 4169 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 4170 #reset-cells = <1>;
4303 }; 4171 };
4304 4172
4305 camss: camss@acb3000 { !! 4173 camss: camss@a00000 {
4306 compatible = "qcom,sd 4174 compatible = "qcom,sdm845-camss";
4307 4175
4308 reg = <0 0x0acb3000 0 !! 4176 reg = <0 0xacb3000 0 0x1000>,
4309 <0 0x0acba000 !! 4177 <0 0xacba000 0 0x1000>,
4310 <0 0x0acc8000 !! 4178 <0 0xacc8000 0 0x1000>,
4311 <0 0x0ac65000 !! 4179 <0 0xac65000 0 0x1000>,
4312 <0 0x0ac66000 !! 4180 <0 0xac66000 0 0x1000>,
4313 <0 0x0ac67000 !! 4181 <0 0xac67000 0 0x1000>,
4314 <0 0x0ac68000 !! 4182 <0 0xac68000 0 0x1000>,
4315 <0 0x0acaf000 !! 4183 <0 0xacaf000 0 0x4000>,
4316 <0 0x0acb6000 !! 4184 <0 0xacb6000 0 0x4000>,
4317 <0 0x0acc4000 !! 4185 <0 0xacc4000 0 0x4000>;
4318 reg-names = "csid0", 4186 reg-names = "csid0",
4319 "csid1", 4187 "csid1",
4320 "csid2", 4188 "csid2",
4321 "csiphy0", 4189 "csiphy0",
4322 "csiphy1", 4190 "csiphy1",
4323 "csiphy2", 4191 "csiphy2",
4324 "csiphy3", 4192 "csiphy3",
4325 "vfe0", 4193 "vfe0",
4326 "vfe1", 4194 "vfe1",
4327 "vfe_lite"; 4195 "vfe_lite";
4328 4196
4329 interrupts = <GIC_SPI 4197 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 4198 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 4199 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 4200 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 4201 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 4202 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 4203 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 4204 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 4205 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 4206 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 4207 interrupt-names = "csid0",
4340 "csid1", 4208 "csid1",
4341 "csid2", 4209 "csid2",
4342 "csiphy0", 4210 "csiphy0",
4343 "csiphy1", 4211 "csiphy1",
4344 "csiphy2", 4212 "csiphy2",
4345 "csiphy3", 4213 "csiphy3",
4346 "vfe0", 4214 "vfe0",
4347 "vfe1", 4215 "vfe1",
4348 "vfe_lite"; 4216 "vfe_lite";
4349 4217
4350 power-domains = <&clo 4218 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 4219 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 4220 <&clock_camcc TITAN_TOP_GDSC>;
4353 4221
4354 clocks = <&clock_camc 4222 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 4223 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 4224 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 4225 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 4226 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 4227 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 4228 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 4229 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 4230 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 4231 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 4232 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 4233 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 4234 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 4235 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 4236 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 4237 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 4238 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 4239 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 4240 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 4241 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 4242 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 4243 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 4244 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 4245 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 4246 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 4247 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 4248 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4249 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4250 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4251 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4252 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4253 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4254 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4255 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4256 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4257 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4258 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4259 "cpas_ahb",
4392 "cphy_rx_src" 4260 "cphy_rx_src",
4393 "csi0", 4261 "csi0",
4394 "csi0_src", 4262 "csi0_src",
4395 "csi1", 4263 "csi1",
4396 "csi1_src", 4264 "csi1_src",
4397 "csi2", 4265 "csi2",
4398 "csi2_src", 4266 "csi2_src",
4399 "csiphy0", 4267 "csiphy0",
4400 "csiphy0_time 4268 "csiphy0_timer",
4401 "csiphy0_time 4269 "csiphy0_timer_src",
4402 "csiphy1", 4270 "csiphy1",
4403 "csiphy1_time 4271 "csiphy1_timer",
4404 "csiphy1_time 4272 "csiphy1_timer_src",
4405 "csiphy2", 4273 "csiphy2",
4406 "csiphy2_time 4274 "csiphy2_timer",
4407 "csiphy2_time 4275 "csiphy2_timer_src",
4408 "csiphy3", 4276 "csiphy3",
4409 "csiphy3_time 4277 "csiphy3_timer",
4410 "csiphy3_time 4278 "csiphy3_timer_src",
4411 "gcc_camera_a 4279 "gcc_camera_ahb",
4412 "gcc_camera_a 4280 "gcc_camera_axi",
4413 "slow_ahb_src 4281 "slow_ahb_src",
4414 "soc_ahb", 4282 "soc_ahb",
4415 "vfe0_axi", 4283 "vfe0_axi",
4416 "vfe0", 4284 "vfe0",
4417 "vfe0_cphy_rx 4285 "vfe0_cphy_rx",
4418 "vfe0_src", 4286 "vfe0_src",
4419 "vfe1_axi", 4287 "vfe1_axi",
4420 "vfe1", 4288 "vfe1",
4421 "vfe1_cphy_rx 4289 "vfe1_cphy_rx",
4422 "vfe1_src", 4290 "vfe1_src",
4423 "vfe_lite", 4291 "vfe_lite",
4424 "vfe_lite_cph 4292 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4293 "vfe_lite_src";
4426 4294
4427 iommus = <&apps_smmu 4295 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4296 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4297 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4298 <&apps_smmu 0x0c10 0x8>;
4431 4299
4432 status = "disabled"; 4300 status = "disabled";
4433 4301
4434 ports { 4302 ports {
4435 #address-cell 4303 #address-cells = <1>;
4436 #size-cells = 4304 #size-cells = <0>;
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; 4305 };
4454 }; 4306 };
4455 4307
4456 cci: cci@ac4a000 { 4308 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 4309 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 4310 #address-cells = <1>;
4459 #size-cells = <0>; 4311 #size-cells = <0>;
4460 4312
4461 reg = <0 0x0ac4a000 0 4313 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4314 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4315 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4316
4465 clocks = <&clock_camc 4317 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4318 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4319 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4320 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4321 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4322 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4323 clock-names = "camnoc_axi",
4472 "soc_ahb", 4324 "soc_ahb",
4473 "slow_ahb_src 4325 "slow_ahb_src",
4474 "cpas_ahb", 4326 "cpas_ahb",
4475 "cci", 4327 "cci",
4476 "cci_src"; 4328 "cci_src";
4477 4329
4478 assigned-clocks = <&c 4330 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4331 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4332 assigned-clock-rates = <80000000>, <37500000>;
4481 4333
4482 pinctrl-names = "defa 4334 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4335 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4336 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4337
4486 status = "disabled"; 4338 status = "disabled";
4487 4339
4488 cci_i2c0: i2c-bus@0 { 4340 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4341 reg = <0>;
4490 clock-frequen 4342 clock-frequency = <1000000>;
4491 #address-cell 4343 #address-cells = <1>;
4492 #size-cells = 4344 #size-cells = <0>;
4493 }; 4345 };
4494 4346
4495 cci_i2c1: i2c-bus@1 { 4347 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4348 reg = <1>;
4497 clock-frequen 4349 clock-frequency = <1000000>;
4498 #address-cell 4350 #address-cells = <1>;
4499 #size-cells = 4351 #size-cells = <0>;
4500 }; 4352 };
4501 }; 4353 };
4502 4354
4503 clock_camcc: clock-controller 4355 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4356 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4357 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4358 #clock-cells = <1>;
4507 #reset-cells = <1>; 4359 #reset-cells = <1>;
4508 #power-domain-cells = 4360 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM 4361 clocks = <&rpmhcc RPMH_CXO_CLK>;
4510 clock-names = "bi_tcx 4362 clock-names = "bi_tcxo";
4511 }; 4363 };
4512 4364
4513 mdss: display-subsystem@ae000 !! 4365 dsi_opp_table: opp-table-dsi {
>> 4366 compatible = "operating-points-v2";
>> 4367
>> 4368 opp-19200000 {
>> 4369 opp-hz = /bits/ 64 <19200000>;
>> 4370 required-opps = <&rpmhpd_opp_min_svs>;
>> 4371 };
>> 4372
>> 4373 opp-180000000 {
>> 4374 opp-hz = /bits/ 64 <180000000>;
>> 4375 required-opps = <&rpmhpd_opp_low_svs>;
>> 4376 };
>> 4377
>> 4378 opp-275000000 {
>> 4379 opp-hz = /bits/ 64 <275000000>;
>> 4380 required-opps = <&rpmhpd_opp_svs>;
>> 4381 };
>> 4382
>> 4383 opp-328580000 {
>> 4384 opp-hz = /bits/ 64 <328580000>;
>> 4385 required-opps = <&rpmhpd_opp_svs_l1>;
>> 4386 };
>> 4387
>> 4388 opp-358000000 {
>> 4389 opp-hz = /bits/ 64 <358000000>;
>> 4390 required-opps = <&rpmhpd_opp_nom>;
>> 4391 };
>> 4392 };
>> 4393
>> 4394 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 4395 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4396 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4397 reg-names = "mdss";
4517 4398
4518 power-domains = <&dis 4399 power-domains = <&dispcc MDSS_GDSC>;
4519 4400
4520 clocks = <&dispcc DIS 4401 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521 <&dispcc DIS 4402 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" 4403 clock-names = "iface", "core";
4523 4404
4524 interrupts = <GIC_SPI 4405 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4406 interrupt-controller;
4526 #interrupt-cells = <1 4407 #interrupt-cells = <1>;
4527 4408
4528 interconnects = <&mms 4409 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4410 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4411 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4412
4532 iommus = <&apps_smmu 4413 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4414 <&apps_smmu 0xc80 0x8>;
4534 4415
4535 status = "disabled"; 4416 status = "disabled";
4536 4417
4537 #address-cells = <2>; 4418 #address-cells = <2>;
4538 #size-cells = <2>; 4419 #size-cells = <2>;
4539 ranges; 4420 ranges;
4540 4421
4541 mdss_mdp: display-con 4422 mdss_mdp: display-controller@ae01000 {
4542 compatible = 4423 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4424 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4425 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4426 reg-names = "mdp", "vbif";
4546 4427
4547 clocks = <&gc 4428 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548 <&di 4429 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549 <&di 4430 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4431 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4432 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = 4433 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553 4434
4554 assigned-cloc 4435 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555 assigned-cloc 4436 assigned-clock-rates = <19200000>;
4556 operating-poi 4437 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4438 power-domains = <&rpmhpd SDM845_CX>;
4558 4439
4559 interrupt-par 4440 interrupt-parent = <&mdss>;
4560 interrupts = 4441 interrupts = <0>;
4561 4442
4562 ports { 4443 ports {
4563 #addr 4444 #address-cells = <1>;
4564 #size 4445 #size-cells = <0>;
4565 4446
4566 port@ 4447 port@0 {
4567 4448 reg = <0>;
4568 !! 4449 dpu_intf1_out: endpoint {
4569 !! 4450 remote-endpoint = <&dsi0_in>;
4570 4451 };
4571 }; 4452 };
4572 4453
4573 port@ 4454 port@1 {
4574 4455 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 4456 dpu_intf2_out: endpoint {
4583 !! 4457 remote-endpoint = <&dsi1_in>;
4584 4458 };
4585 }; 4459 };
4586 }; 4460 };
4587 4461
4588 mdp_opp_table 4462 mdp_opp_table: opp-table {
4589 compa 4463 compatible = "operating-points-v2";
4590 4464
4591 opp-1 4465 opp-19200000 {
4592 4466 opp-hz = /bits/ 64 <19200000>;
4593 4467 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4468 };
4595 4469
4596 opp-1 4470 opp-171428571 {
4597 4471 opp-hz = /bits/ 64 <171428571>;
4598 4472 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4473 };
4600 4474
4601 opp-3 4475 opp-344000000 {
4602 4476 opp-hz = /bits/ 64 <344000000>;
4603 4477 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4478 };
4605 4479
4606 opp-4 4480 opp-430000000 {
4607 4481 opp-hz = /bits/ 64 <430000000>;
4608 4482 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4483 };
4610 }; 4484 };
4611 }; 4485 };
4612 4486
4613 mdss_dp: displayport- !! 4487 dsi0: dsi@ae94000 {
4614 status = "dis !! 4488 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 4489 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4490 reg-names = "dsi_ctrl";
4691 4491
4692 interrupt-par 4492 interrupt-parent = <&mdss>;
4693 interrupts = 4493 interrupts = <4>;
4694 4494
4695 clocks = <&di 4495 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4496 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4497 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4498 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4499 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4500 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4501 clock-names = "byte",
4702 4502 "byte_intf",
4703 4503 "pixel",
4704 4504 "core",
4705 4505 "iface",
4706 4506 "bus";
4707 assigned-cloc 4507 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-cloc !! 4508 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4709 4509
4710 operating-poi 4510 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4511 power-domains = <&rpmhpd SDM845_CX>;
4712 4512
4713 phys = <&mdss !! 4513 phys = <&dsi0_phy>;
>> 4514 phy-names = "dsi";
4714 4515
4715 status = "dis 4516 status = "disabled";
4716 4517
4717 #address-cell 4518 #address-cells = <1>;
4718 #size-cells = 4519 #size-cells = <0>;
4719 4520
4720 ports { 4521 ports {
4721 #addr 4522 #address-cells = <1>;
4722 #size 4523 #size-cells = <0>;
4723 4524
4724 port@ 4525 port@0 {
4725 4526 reg = <0>;
4726 !! 4527 dsi0_in: endpoint {
4727 4528 remote-endpoint = <&dpu_intf1_out>;
4728 4529 };
4729 }; 4530 };
4730 4531
4731 port@ 4532 port@1 {
4732 4533 reg = <1>;
4733 !! 4534 dsi0_out: endpoint {
4734 4535 };
4735 }; 4536 };
4736 }; 4537 };
4737 }; 4538 };
4738 4539
4739 mdss_dsi0_phy: phy@ae !! 4540 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 4541 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4542 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4543 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4544 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4545 reg-names = "dsi_phy",
4745 " 4546 "dsi_phy_lane",
4746 " 4547 "dsi_pll";
4747 4548
4748 #clock-cells 4549 #clock-cells = <1>;
4749 #phy-cells = 4550 #phy-cells = <0>;
4750 4551
4751 clocks = <&di 4552 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4553 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4554 clock-names = "iface", "ref";
4754 4555
4755 status = "dis 4556 status = "disabled";
4756 }; 4557 };
4757 4558
4758 mdss_dsi1: dsi@ae9600 !! 4559 dsi1: dsi@ae96000 {
4759 compatible = !! 4560 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 4561 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4562 reg-names = "dsi_ctrl";
4763 4563
4764 interrupt-par 4564 interrupt-parent = <&mdss>;
4765 interrupts = 4565 interrupts = <5>;
4766 4566
4767 clocks = <&di 4567 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4568 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4569 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4570 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4571 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4572 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4573 clock-names = "byte",
4774 4574 "byte_intf",
4775 4575 "pixel",
4776 4576 "core",
4777 4577 "iface",
4778 4578 "bus";
4779 assigned-cloc 4579 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-cloc !! 4580 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4781 4581
4782 operating-poi 4582 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4583 power-domains = <&rpmhpd SDM845_CX>;
4784 4584
4785 phys = <&mdss !! 4585 phys = <&dsi1_phy>;
>> 4586 phy-names = "dsi";
4786 4587
4787 status = "dis 4588 status = "disabled";
4788 4589
4789 #address-cell 4590 #address-cells = <1>;
4790 #size-cells = 4591 #size-cells = <0>;
4791 4592
4792 ports { 4593 ports {
4793 #addr 4594 #address-cells = <1>;
4794 #size 4595 #size-cells = <0>;
4795 4596
4796 port@ 4597 port@0 {
4797 4598 reg = <0>;
4798 !! 4599 dsi1_in: endpoint {
4799 4600 remote-endpoint = <&dpu_intf2_out>;
4800 4601 };
4801 }; 4602 };
4802 4603
4803 port@ 4604 port@1 {
4804 4605 reg = <1>;
4805 !! 4606 dsi1_out: endpoint {
4806 4607 };
4807 }; 4608 };
4808 }; 4609 };
4809 }; 4610 };
4810 4611
4811 mdss_dsi1_phy: phy@ae !! 4612 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 4613 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4614 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4615 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4616 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4617 reg-names = "dsi_phy",
4817 " 4618 "dsi_phy_lane",
4818 " 4619 "dsi_pll";
4819 4620
4820 #clock-cells 4621 #clock-cells = <1>;
4821 #phy-cells = 4622 #phy-cells = <0>;
4822 4623
4823 clocks = <&di 4624 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4625 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4626 clock-names = "iface", "ref";
4826 4627
4827 status = "dis 4628 status = "disabled";
4828 }; 4629 };
4829 }; 4630 };
4830 4631
4831 gpu: gpu@5000000 { 4632 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4633 compatible = "qcom,adreno-630.2", "qcom,adreno";
4833 4634
4834 reg = <0 0x05000000 0 !! 4635 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4636 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4637
4837 /* 4638 /*
4838 * Look ma, no clocks 4639 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4640 * controlled entirely by the GMU
4840 */ 4641 */
4841 4642
4842 interrupts = <GIC_SPI 4643 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4644
4844 iommus = <&adreno_smm 4645 iommus = <&adreno_smmu 0>;
4845 4646
4846 operating-points-v2 = 4647 operating-points-v2 = <&gpu_opp_table>;
4847 4648
4848 qcom,gmu = <&gmu>; 4649 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4650
4851 interconnects = <&mem 4651 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4652 interconnect-names = "gfx-mem";
4853 4653
4854 status = "disabled"; 4654 status = "disabled";
4855 4655
4856 gpu_opp_table: opp-ta 4656 gpu_opp_table: opp-table {
4857 compatible = 4657 compatible = "operating-points-v2";
4858 4658
4859 opp-710000000 4659 opp-710000000 {
4860 opp-h 4660 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4661 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4662 opp-peak-kBps = <7216000>;
4863 }; 4663 };
4864 4664
4865 opp-675000000 4665 opp-675000000 {
4866 opp-h 4666 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4667 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4668 opp-peak-kBps = <7216000>;
4869 }; 4669 };
4870 4670
4871 opp-596000000 4671 opp-596000000 {
4872 opp-h 4672 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4673 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4674 opp-peak-kBps = <6220000>;
4875 }; 4675 };
4876 4676
4877 opp-520000000 4677 opp-520000000 {
4878 opp-h 4678 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4679 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4680 opp-peak-kBps = <6220000>;
4881 }; 4681 };
4882 4682
4883 opp-414000000 4683 opp-414000000 {
4884 opp-h 4684 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4685 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4686 opp-peak-kBps = <4068000>;
4887 }; 4687 };
4888 4688
4889 opp-342000000 4689 opp-342000000 {
4890 opp-h 4690 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4691 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4692 opp-peak-kBps = <2724000>;
4893 }; 4693 };
4894 4694
4895 opp-257000000 4695 opp-257000000 {
4896 opp-h 4696 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4697 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4698 opp-peak-kBps = <1648000>;
4899 }; 4699 };
4900 }; 4700 };
4901 }; 4701 };
4902 4702
4903 adreno_smmu: iommu@5040000 { 4703 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4704 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4705 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4706 #iommu-cells = <1>;
4907 #global-interrupts = 4707 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4708 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4709 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4710 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4711 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4712 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4713 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4714 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4715 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4716 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4717 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4718 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4719 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4720 clock-names = "bus", "iface";
4921 4721
4922 power-domains = <&gpu 4722 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4723 };
4924 4724
4925 gmu: gmu@506a000 { 4725 gmu: gmu@506a000 {
4926 compatible = "qcom,ad 4726 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4727
4928 reg = <0 0x0506a000 0 !! 4728 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4729 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4730 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4731 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4732
4933 interrupts = <GIC_SPI 4733 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4734 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4735 interrupt-names = "hfi", "gmu";
4936 4736
4937 clocks = <&gpucc GPU_ 4737 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4738 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4739 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4740 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4741 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4742
4943 power-domains = <&gpu 4743 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4744 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4745 power-domain-names = "cx", "gx";
4946 4746
4947 iommus = <&adreno_smm 4747 iommus = <&adreno_smmu 5>;
4948 4748
4949 operating-points-v2 = 4749 operating-points-v2 = <&gmu_opp_table>;
4950 4750
4951 status = "disabled"; 4751 status = "disabled";
4952 4752
4953 gmu_opp_table: opp-ta 4753 gmu_opp_table: opp-table {
4954 compatible = 4754 compatible = "operating-points-v2";
4955 4755
4956 opp-400000000 4756 opp-400000000 {
4957 opp-h 4757 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4758 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4759 };
4960 4760
4961 opp-200000000 4761 opp-200000000 {
4962 opp-h 4762 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4763 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4764 };
4965 }; 4765 };
4966 }; 4766 };
4967 4767
4968 dispcc: clock-controller@af00 4768 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4769 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4770 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4771 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4772 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4773 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4774 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4775 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4776 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4777 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4778 <0>,
4979 <&usb_1_qmpp !! 4779 <0>;
4980 clock-names = "bi_tcx 4780 clock-names = "bi_tcxo",
4981 "gcc_di 4781 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4782 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4783 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4784 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4785 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4786 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4787 "dp_link_clk_divsel_ten",
4988 "dp_vco 4788 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4789 #clock-cells = <1>;
4990 #reset-cells = <1>; 4790 #reset-cells = <1>;
4991 #power-domain-cells = 4791 #power-domain-cells = <1>;
4992 }; 4792 };
4993 4793
4994 pdc_intc: interrupt-controlle 4794 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4795 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4796 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4797 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4798 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4799 interrupt-parent = <&intc>;
5000 interrupt-controller; 4800 interrupt-controller;
5001 }; 4801 };
5002 4802
5003 pdc_reset: reset-controller@b 4803 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4804 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4805 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4806 #reset-cells = <1>;
5007 }; 4807 };
5008 4808
5009 tsens0: thermal-sensor@c26300 4809 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4810 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4811 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4812 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4813 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4814 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4815 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4816 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4817 #thermal-sensor-cells = <1>;
5018 }; 4818 };
5019 4819
5020 tsens1: thermal-sensor@c26500 4820 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4821 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4822 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4823 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4824 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4825 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4826 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4827 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4828 #thermal-sensor-cells = <1>;
5029 }; 4829 };
5030 4830
5031 aoss_reset: reset-controller@ 4831 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4832 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4833 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4834 #reset-cells = <1>;
5035 }; 4835 };
5036 4836
5037 aoss_qmp: power-management@c3 !! 4837 aoss_qmp: power-controller@c300000 {
5038 compatible = "qcom,sd 4838 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039 reg = <0 0x0c300000 0 !! 4839 reg = <0 0x0c300000 0 0x100000>;
5040 interrupts = <GIC_SPI 4840 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4841 mboxes = <&apss_shared 0>;
5042 4842
5043 #clock-cells = <0>; 4843 #clock-cells = <0>;
5044 4844
5045 cx_cdev: cx { 4845 cx_cdev: cx {
5046 #cooling-cell 4846 #cooling-cells = <2>;
5047 }; 4847 };
5048 4848
5049 ebi_cdev: ebi { 4849 ebi_cdev: ebi {
5050 #cooling-cell 4850 #cooling-cells = <2>;
5051 }; 4851 };
5052 }; 4852 };
5053 4853
5054 sram@c3f0000 { <<
5055 compatible = "qcom,sd <<
5056 reg = <0 0x0c3f0000 0 <<
5057 }; <<
5058 <<
5059 spmi_bus: spmi@c440000 { 4854 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4855 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4856 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4857 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4858 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4859 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4860 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 4861 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 4862 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 4863 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 4864 qcom,ee = <0>;
5070 qcom,channel = <0>; 4865 qcom,channel = <0>;
5071 #address-cells = <2>; 4866 #address-cells = <2>;
5072 #size-cells = <0>; 4867 #size-cells = <0>;
5073 interrupt-controller; 4868 interrupt-controller;
5074 #interrupt-cells = <4 4869 #interrupt-cells = <4>;
>> 4870 cell-index = <0>;
5075 }; 4871 };
5076 4872
5077 sram@146bf000 { 4873 sram@146bf000 {
5078 compatible = "qcom,sd 4874 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5079 reg = <0 0x146bf000 0 4875 reg = <0 0x146bf000 0 0x1000>;
5080 4876
5081 #address-cells = <1>; 4877 #address-cells = <1>;
5082 #size-cells = <1>; 4878 #size-cells = <1>;
5083 4879
5084 ranges = <0 0 0x146bf 4880 ranges = <0 0 0x146bf000 0x1000>;
5085 4881
5086 pil-reloc@94c { 4882 pil-reloc@94c {
5087 compatible = 4883 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 4884 reg = <0x94c 0xc8>;
5089 }; 4885 };
5090 }; 4886 };
5091 4887
5092 apps_smmu: iommu@15000000 { 4888 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 4889 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 4890 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 4891 #iommu-cells = <2>;
5096 #global-interrupts = 4892 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 4893 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 4894 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 4895 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 4896 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 4897 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 4898 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 4899 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 4900 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 4901 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 4902 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4903 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4904 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 4905 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 4906 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 4907 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 4908 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 4909 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 4910 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 4911 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 4912 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 4913 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 4914 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 4915 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 4916 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 4917 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 4918 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 4919 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 4920 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 4921 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 4922 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 4923 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 4924 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 4925 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 4926 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 4927 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4928 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 4929 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 4930 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 4931 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 4932 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 4933 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4934 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 4935 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 4936 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 4937 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 4938 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 4939 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4940 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 4941 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 4942 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 4943 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 4944 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 4945 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 4946 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 4947 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 4948 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 4949 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 4950 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 4951 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 4952 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 4953 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 4954 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 4955 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 4956 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 4957 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 4958 };
5163 4959
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 4960 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 4961 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 4962 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 4963 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 4964 #clock-cells = <1>;
5241 status = "disabled"; 4965 status = "disabled";
5242 }; 4966 };
5243 4967
5244 gladiator_noc: interconnect@1 4968 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 4969 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 4970 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 4971 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 4972 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 4973 };
5250 4974
5251 watchdog@17980000 { 4975 watchdog@17980000 {
5252 compatible = "qcom,ap 4976 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 4977 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 4978 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI !! 4979 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256 }; 4980 };
5257 4981
5258 apss_shared: mailbox@17990000 4982 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 4983 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 4984 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 4985 #mbox-cells = <1>;
5262 }; 4986 };
5263 4987
5264 apps_rsc: rsc@179c0000 { 4988 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 4989 label = "apps_rsc";
5266 compatible = "qcom,rp 4990 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 4991 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 4992 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 4993 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 4994 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 4995 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 4996 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 4997 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 4998 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 4999 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 5000 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 5001 <SLEEP_TCS 3>,
5278 <WA 5002 <WAKE_TCS 3>,
5279 <CO 5003 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 5004
5282 apps_bcm_voter: bcm-v 5005 apps_bcm_voter: bcm-voter {
5283 compatible = 5006 compatible = "qcom,bcm-voter";
5284 }; 5007 };
5285 5008
5286 rpmhcc: clock-control 5009 rpmhcc: clock-controller {
5287 compatible = 5010 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 5011 #clock-cells = <1>;
5289 clock-names = 5012 clock-names = "xo";
5290 clocks = <&xo 5013 clocks = <&xo_board>;
5291 }; 5014 };
5292 5015
5293 rpmhpd: power-control 5016 rpmhpd: power-controller {
5294 compatible = 5017 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 5018 #power-domain-cells = <1>;
5296 operating-poi 5019 operating-points-v2 = <&rpmhpd_opp_table>;
5297 5020
5298 rpmhpd_opp_ta 5021 rpmhpd_opp_table: opp-table {
5299 compa 5022 compatible = "operating-points-v2";
5300 5023
5301 rpmhp 5024 rpmhpd_opp_ret: opp1 {
5302 5025 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 5026 };
5304 5027
5305 rpmhp 5028 rpmhpd_opp_min_svs: opp2 {
5306 5029 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 5030 };
5308 5031
5309 rpmhp 5032 rpmhpd_opp_low_svs: opp3 {
5310 5033 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 5034 };
5312 5035
5313 rpmhp 5036 rpmhpd_opp_svs: opp4 {
5314 5037 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 5038 };
5316 5039
5317 rpmhp 5040 rpmhpd_opp_svs_l1: opp5 {
5318 5041 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 5042 };
5320 5043
5321 rpmhp 5044 rpmhpd_opp_nom: opp6 {
5322 5045 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 5046 };
5324 5047
5325 rpmhp 5048 rpmhpd_opp_nom_l1: opp7 {
5326 5049 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 5050 };
5328 5051
5329 rpmhp 5052 rpmhpd_opp_nom_l2: opp8 {
5330 5053 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 5054 };
5332 5055
5333 rpmhp 5056 rpmhpd_opp_turbo: opp9 {
5334 5057 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 5058 };
5336 5059
5337 rpmhp 5060 rpmhpd_opp_turbo_l1: opp10 {
5338 5061 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 5062 };
5340 }; 5063 };
5341 }; 5064 };
5342 }; 5065 };
5343 5066
5344 intc: interrupt-controller@17 5067 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 5068 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 5069 #address-cells = <2>;
5347 #size-cells = <2>; 5070 #size-cells = <2>;
5348 ranges; 5071 ranges;
5349 #interrupt-cells = <3 5072 #interrupt-cells = <3>;
5350 interrupt-controller; 5073 interrupt-controller;
5351 reg = <0 0x17a00000 0 5074 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 5075 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 5076 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 5077
5355 msi-controller@17a400 5078 msi-controller@17a40000 {
5356 compatible = 5079 compatible = "arm,gic-v3-its";
5357 msi-controlle 5080 msi-controller;
5358 #msi-cells = 5081 #msi-cells = <1>;
5359 reg = <0 0x17 5082 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 5083 status = "disabled";
5361 }; 5084 };
5362 }; 5085 };
5363 5086
5364 slimbam: dma-controller@17184 5087 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba !! 5088 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 5089 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 5090 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; 5091 num-channels = <31>;
5369 interrupts = <GIC_SPI 5092 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 5093 #dma-cells = <1>;
5371 qcom,ee = <1>; 5094 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 5095 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 5096 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 5097 };
5375 5098
5376 timer@17c90000 { 5099 timer@17c90000 {
5377 #address-cells = <1>; 5100 #address-cells = <1>;
5378 #size-cells = <1>; 5101 #size-cells = <1>;
5379 ranges = <0 0 0 0x200 5102 ranges = <0 0 0 0x20000000>;
5380 compatible = "arm,arm 5103 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 5104 reg = <0 0x17c90000 0 0x1000>;
5382 5105
5383 frame@17ca0000 { 5106 frame@17ca0000 {
5384 frame-number 5107 frame-number = <0>;
5385 interrupts = 5108 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 5109 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca 5110 reg = <0x17ca0000 0x1000>,
5388 <0x17cb 5111 <0x17cb0000 0x1000>;
5389 }; 5112 };
5390 5113
5391 frame@17cc0000 { 5114 frame@17cc0000 {
5392 frame-number 5115 frame-number = <1>;
5393 interrupts = 5116 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc 5117 reg = <0x17cc0000 0x1000>;
5395 status = "dis 5118 status = "disabled";
5396 }; 5119 };
5397 5120
5398 frame@17cd0000 { 5121 frame@17cd0000 {
5399 frame-number 5122 frame-number = <2>;
5400 interrupts = 5123 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd 5124 reg = <0x17cd0000 0x1000>;
5402 status = "dis 5125 status = "disabled";
5403 }; 5126 };
5404 5127
5405 frame@17ce0000 { 5128 frame@17ce0000 {
5406 frame-number 5129 frame-number = <3>;
5407 interrupts = 5130 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce 5131 reg = <0x17ce0000 0x1000>;
5409 status = "dis 5132 status = "disabled";
5410 }; 5133 };
5411 5134
5412 frame@17cf0000 { 5135 frame@17cf0000 {
5413 frame-number 5136 frame-number = <4>;
5414 interrupts = 5137 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf 5138 reg = <0x17cf0000 0x1000>;
5416 status = "dis 5139 status = "disabled";
5417 }; 5140 };
5418 5141
5419 frame@17d00000 { 5142 frame@17d00000 {
5420 frame-number 5143 frame-number = <5>;
5421 interrupts = 5144 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 5145 reg = <0x17d00000 0x1000>;
5423 status = "dis 5146 status = "disabled";
5424 }; 5147 };
5425 5148
5426 frame@17d10000 { 5149 frame@17d10000 {
5427 frame-number 5150 frame-number = <6>;
5428 interrupts = 5151 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 5152 reg = <0x17d10000 0x1000>;
5430 status = "dis 5153 status = "disabled";
5431 }; 5154 };
5432 }; 5155 };
5433 5156
5434 osm_l3: interconnect@17d41000 5157 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 5158 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 5159 reg = <0 0x17d41000 0 0x1400>;
5437 5160
5438 clocks = <&rpmhcc RPM 5161 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 5162 clock-names = "xo", "alternate";
5440 5163
5441 #interconnect-cells = 5164 #interconnect-cells = <1>;
5442 }; 5165 };
5443 5166
5444 cpufreq_hw: cpufreq@17d43000 5167 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 5168 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 5169 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 5170 reg-names = "freq-domain0", "freq-domain1";
5448 5171
5449 interrupts-extended = 5172 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450 5173
5451 clocks = <&rpmhcc RPM 5174 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 5175 clock-names = "xo", "alternate";
5453 5176
5454 #freq-domain-cells = 5177 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 5178 };
5457 5179
5458 wifi: wifi@18800000 { 5180 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 5181 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 5182 status = "disabled";
5461 reg = <0 0x18800000 0 5183 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 5184 reg-names = "membase";
5463 memory-region = <&wla 5185 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 5186 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 5187 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 5188 interrupts =
5467 <GIC_SPI 414 5189 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 5190 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 5191 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 5192 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 5193 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 5194 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 5195 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 5196 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 5197 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 5198 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 5199 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 5200 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 5201 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 5202 };
5481 }; 5203 };
5482 5204
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 5205 thermal-zones {
5487 cpu0-thermal { 5206 cpu0-thermal {
5488 polling-delay-passive 5207 polling-delay-passive = <250>;
>> 5208 polling-delay = <1000>;
5489 5209
5490 thermal-sensors = <&t 5210 thermal-sensors = <&tsens0 1>;
5491 5211
5492 trips { 5212 trips {
5493 cpu0_alert0: 5213 cpu0_alert0: trip-point0 {
5494 tempe 5214 temperature = <90000>;
5495 hyste 5215 hysteresis = <2000>;
5496 type 5216 type = "passive";
5497 }; 5217 };
5498 5218
5499 cpu0_alert1: 5219 cpu0_alert1: trip-point1 {
5500 tempe 5220 temperature = <95000>;
5501 hyste 5221 hysteresis = <2000>;
5502 type 5222 type = "passive";
5503 }; 5223 };
5504 5224
5505 cpu0_crit: cp !! 5225 cpu0_crit: cpu_crit {
5506 tempe 5226 temperature = <110000>;
5507 hyste 5227 hysteresis = <1000>;
5508 type 5228 type = "critical";
5509 }; 5229 };
5510 }; 5230 };
5511 }; 5231 };
5512 5232
5513 cpu1-thermal { 5233 cpu1-thermal {
5514 polling-delay-passive 5234 polling-delay-passive = <250>;
>> 5235 polling-delay = <1000>;
5515 5236
5516 thermal-sensors = <&t 5237 thermal-sensors = <&tsens0 2>;
5517 5238
5518 trips { 5239 trips {
5519 cpu1_alert0: 5240 cpu1_alert0: trip-point0 {
5520 tempe 5241 temperature = <90000>;
5521 hyste 5242 hysteresis = <2000>;
5522 type 5243 type = "passive";
5523 }; 5244 };
5524 5245
5525 cpu1_alert1: 5246 cpu1_alert1: trip-point1 {
5526 tempe 5247 temperature = <95000>;
5527 hyste 5248 hysteresis = <2000>;
5528 type 5249 type = "passive";
5529 }; 5250 };
5530 5251
5531 cpu1_crit: cp !! 5252 cpu1_crit: cpu_crit {
5532 tempe 5253 temperature = <110000>;
5533 hyste 5254 hysteresis = <1000>;
5534 type 5255 type = "critical";
5535 }; 5256 };
5536 }; 5257 };
5537 }; 5258 };
5538 5259
5539 cpu2-thermal { 5260 cpu2-thermal {
5540 polling-delay-passive 5261 polling-delay-passive = <250>;
>> 5262 polling-delay = <1000>;
5541 5263
5542 thermal-sensors = <&t 5264 thermal-sensors = <&tsens0 3>;
5543 5265
5544 trips { 5266 trips {
5545 cpu2_alert0: 5267 cpu2_alert0: trip-point0 {
5546 tempe 5268 temperature = <90000>;
5547 hyste 5269 hysteresis = <2000>;
5548 type 5270 type = "passive";
5549 }; 5271 };
5550 5272
5551 cpu2_alert1: 5273 cpu2_alert1: trip-point1 {
5552 tempe 5274 temperature = <95000>;
5553 hyste 5275 hysteresis = <2000>;
5554 type 5276 type = "passive";
5555 }; 5277 };
5556 5278
5557 cpu2_crit: cp !! 5279 cpu2_crit: cpu_crit {
5558 tempe 5280 temperature = <110000>;
5559 hyste 5281 hysteresis = <1000>;
5560 type 5282 type = "critical";
5561 }; 5283 };
5562 }; 5284 };
5563 }; 5285 };
5564 5286
5565 cpu3-thermal { 5287 cpu3-thermal {
5566 polling-delay-passive 5288 polling-delay-passive = <250>;
>> 5289 polling-delay = <1000>;
5567 5290
5568 thermal-sensors = <&t 5291 thermal-sensors = <&tsens0 4>;
5569 5292
5570 trips { 5293 trips {
5571 cpu3_alert0: 5294 cpu3_alert0: trip-point0 {
5572 tempe 5295 temperature = <90000>;
5573 hyste 5296 hysteresis = <2000>;
5574 type 5297 type = "passive";
5575 }; 5298 };
5576 5299
5577 cpu3_alert1: 5300 cpu3_alert1: trip-point1 {
5578 tempe 5301 temperature = <95000>;
5579 hyste 5302 hysteresis = <2000>;
5580 type 5303 type = "passive";
5581 }; 5304 };
5582 5305
5583 cpu3_crit: cp !! 5306 cpu3_crit: cpu_crit {
5584 tempe 5307 temperature = <110000>;
5585 hyste 5308 hysteresis = <1000>;
5586 type 5309 type = "critical";
5587 }; 5310 };
5588 }; 5311 };
5589 }; 5312 };
5590 5313
5591 cpu4-thermal { 5314 cpu4-thermal {
5592 polling-delay-passive 5315 polling-delay-passive = <250>;
>> 5316 polling-delay = <1000>;
5593 5317
5594 thermal-sensors = <&t 5318 thermal-sensors = <&tsens0 7>;
5595 5319
5596 trips { 5320 trips {
5597 cpu4_alert0: 5321 cpu4_alert0: trip-point0 {
5598 tempe 5322 temperature = <90000>;
5599 hyste 5323 hysteresis = <2000>;
5600 type 5324 type = "passive";
5601 }; 5325 };
5602 5326
5603 cpu4_alert1: 5327 cpu4_alert1: trip-point1 {
5604 tempe 5328 temperature = <95000>;
5605 hyste 5329 hysteresis = <2000>;
5606 type 5330 type = "passive";
5607 }; 5331 };
5608 5332
5609 cpu4_crit: cp !! 5333 cpu4_crit: cpu_crit {
5610 tempe 5334 temperature = <110000>;
5611 hyste 5335 hysteresis = <1000>;
5612 type 5336 type = "critical";
5613 }; 5337 };
5614 }; 5338 };
5615 }; 5339 };
5616 5340
5617 cpu5-thermal { 5341 cpu5-thermal {
5618 polling-delay-passive 5342 polling-delay-passive = <250>;
>> 5343 polling-delay = <1000>;
5619 5344
5620 thermal-sensors = <&t 5345 thermal-sensors = <&tsens0 8>;
5621 5346
5622 trips { 5347 trips {
5623 cpu5_alert0: 5348 cpu5_alert0: trip-point0 {
5624 tempe 5349 temperature = <90000>;
5625 hyste 5350 hysteresis = <2000>;
5626 type 5351 type = "passive";
5627 }; 5352 };
5628 5353
5629 cpu5_alert1: 5354 cpu5_alert1: trip-point1 {
5630 tempe 5355 temperature = <95000>;
5631 hyste 5356 hysteresis = <2000>;
5632 type 5357 type = "passive";
5633 }; 5358 };
5634 5359
5635 cpu5_crit: cp !! 5360 cpu5_crit: cpu_crit {
5636 tempe 5361 temperature = <110000>;
5637 hyste 5362 hysteresis = <1000>;
5638 type 5363 type = "critical";
5639 }; 5364 };
5640 }; 5365 };
5641 }; 5366 };
5642 5367
5643 cpu6-thermal { 5368 cpu6-thermal {
5644 polling-delay-passive 5369 polling-delay-passive = <250>;
>> 5370 polling-delay = <1000>;
5645 5371
5646 thermal-sensors = <&t 5372 thermal-sensors = <&tsens0 9>;
5647 5373
5648 trips { 5374 trips {
5649 cpu6_alert0: 5375 cpu6_alert0: trip-point0 {
5650 tempe 5376 temperature = <90000>;
5651 hyste 5377 hysteresis = <2000>;
5652 type 5378 type = "passive";
5653 }; 5379 };
5654 5380
5655 cpu6_alert1: 5381 cpu6_alert1: trip-point1 {
5656 tempe 5382 temperature = <95000>;
5657 hyste 5383 hysteresis = <2000>;
5658 type 5384 type = "passive";
5659 }; 5385 };
5660 5386
5661 cpu6_crit: cp !! 5387 cpu6_crit: cpu_crit {
5662 tempe 5388 temperature = <110000>;
5663 hyste 5389 hysteresis = <1000>;
5664 type 5390 type = "critical";
5665 }; 5391 };
5666 }; 5392 };
5667 }; 5393 };
5668 5394
5669 cpu7-thermal { 5395 cpu7-thermal {
5670 polling-delay-passive 5396 polling-delay-passive = <250>;
>> 5397 polling-delay = <1000>;
5671 5398
5672 thermal-sensors = <&t 5399 thermal-sensors = <&tsens0 10>;
5673 5400
5674 trips { 5401 trips {
5675 cpu7_alert0: 5402 cpu7_alert0: trip-point0 {
5676 tempe 5403 temperature = <90000>;
5677 hyste 5404 hysteresis = <2000>;
5678 type 5405 type = "passive";
5679 }; 5406 };
5680 5407
5681 cpu7_alert1: 5408 cpu7_alert1: trip-point1 {
5682 tempe 5409 temperature = <95000>;
5683 hyste 5410 hysteresis = <2000>;
5684 type 5411 type = "passive";
5685 }; 5412 };
5686 5413
5687 cpu7_crit: cp !! 5414 cpu7_crit: cpu_crit {
5688 tempe 5415 temperature = <110000>;
5689 hyste 5416 hysteresis = <1000>;
5690 type 5417 type = "critical";
5691 }; 5418 };
5692 }; 5419 };
5693 }; 5420 };
5694 5421
5695 aoss0-thermal { 5422 aoss0-thermal {
5696 polling-delay-passive 5423 polling-delay-passive = <250>;
>> 5424 polling-delay = <1000>;
5697 5425
5698 thermal-sensors = <&t 5426 thermal-sensors = <&tsens0 0>;
5699 5427
5700 trips { 5428 trips {
5701 aoss0_alert0: 5429 aoss0_alert0: trip-point0 {
5702 tempe 5430 temperature = <90000>;
5703 hyste 5431 hysteresis = <2000>;
5704 type 5432 type = "hot";
5705 }; 5433 };
5706 }; 5434 };
5707 }; 5435 };
5708 5436
5709 cluster0-thermal { 5437 cluster0-thermal {
5710 polling-delay-passive 5438 polling-delay-passive = <250>;
>> 5439 polling-delay = <1000>;
5711 5440
5712 thermal-sensors = <&t 5441 thermal-sensors = <&tsens0 5>;
5713 5442
5714 trips { 5443 trips {
5715 cluster0_aler 5444 cluster0_alert0: trip-point0 {
5716 tempe 5445 temperature = <90000>;
5717 hyste 5446 hysteresis = <2000>;
5718 type 5447 type = "hot";
5719 }; 5448 };
5720 cluster0_crit !! 5449 cluster0_crit: cluster0_crit {
5721 tempe 5450 temperature = <110000>;
5722 hyste 5451 hysteresis = <2000>;
5723 type 5452 type = "critical";
5724 }; 5453 };
5725 }; 5454 };
5726 }; 5455 };
5727 5456
5728 cluster1-thermal { 5457 cluster1-thermal {
5729 polling-delay-passive 5458 polling-delay-passive = <250>;
>> 5459 polling-delay = <1000>;
5730 5460
5731 thermal-sensors = <&t 5461 thermal-sensors = <&tsens0 6>;
5732 5462
5733 trips { 5463 trips {
5734 cluster1_aler 5464 cluster1_alert0: trip-point0 {
5735 tempe 5465 temperature = <90000>;
5736 hyste 5466 hysteresis = <2000>;
5737 type 5467 type = "hot";
5738 }; 5468 };
5739 cluster1_crit !! 5469 cluster1_crit: cluster1_crit {
5740 tempe 5470 temperature = <110000>;
5741 hyste 5471 hysteresis = <2000>;
5742 type 5472 type = "critical";
5743 }; 5473 };
5744 }; 5474 };
5745 }; 5475 };
5746 5476
5747 gpu-top-thermal { 5477 gpu-top-thermal {
5748 polling-delay-passive 5478 polling-delay-passive = <250>;
>> 5479 polling-delay = <1000>;
5749 5480
5750 thermal-sensors = <&t 5481 thermal-sensors = <&tsens0 11>;
5751 5482
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5483 trips {
5760 gpu_top_alert !! 5484 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5485 temperature = <90000>;
5768 hyste !! 5486 hysteresis = <2000>;
5769 type 5487 type = "hot";
5770 }; 5488 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5489 };
5778 }; 5490 };
5779 5491
5780 gpu-bottom-thermal { 5492 gpu-bottom-thermal {
5781 polling-delay-passive 5493 polling-delay-passive = <250>;
>> 5494 polling-delay = <1000>;
5782 5495
5783 thermal-sensors = <&t 5496 thermal-sensors = <&tsens0 12>;
5784 5497
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5498 trips {
5793 gpu_bottom_al !! 5499 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5500 temperature = <90000>;
5801 hyste !! 5501 hysteresis = <2000>;
5802 type 5502 type = "hot";
5803 }; 5503 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5504 };
5811 }; 5505 };
5812 5506
5813 aoss1-thermal { 5507 aoss1-thermal {
5814 polling-delay-passive 5508 polling-delay-passive = <250>;
>> 5509 polling-delay = <1000>;
5815 5510
5816 thermal-sensors = <&t 5511 thermal-sensors = <&tsens1 0>;
5817 5512
5818 trips { 5513 trips {
5819 aoss1_alert0: 5514 aoss1_alert0: trip-point0 {
5820 tempe 5515 temperature = <90000>;
5821 hyste 5516 hysteresis = <2000>;
5822 type 5517 type = "hot";
5823 }; 5518 };
5824 }; 5519 };
5825 }; 5520 };
5826 5521
5827 q6-modem-thermal { 5522 q6-modem-thermal {
5828 polling-delay-passive 5523 polling-delay-passive = <250>;
>> 5524 polling-delay = <1000>;
5829 5525
5830 thermal-sensors = <&t 5526 thermal-sensors = <&tsens1 1>;
5831 5527
5832 trips { 5528 trips {
5833 q6_modem_aler 5529 q6_modem_alert0: trip-point0 {
5834 tempe 5530 temperature = <90000>;
5835 hyste 5531 hysteresis = <2000>;
5836 type 5532 type = "hot";
5837 }; 5533 };
5838 }; 5534 };
5839 }; 5535 };
5840 5536
5841 mem-thermal { 5537 mem-thermal {
5842 polling-delay-passive 5538 polling-delay-passive = <250>;
>> 5539 polling-delay = <1000>;
5843 5540
5844 thermal-sensors = <&t 5541 thermal-sensors = <&tsens1 2>;
5845 5542
5846 trips { 5543 trips {
5847 mem_alert0: t 5544 mem_alert0: trip-point0 {
5848 tempe 5545 temperature = <90000>;
5849 hyste 5546 hysteresis = <2000>;
5850 type 5547 type = "hot";
5851 }; 5548 };
5852 }; 5549 };
5853 }; 5550 };
5854 5551
5855 wlan-thermal { 5552 wlan-thermal {
5856 polling-delay-passive 5553 polling-delay-passive = <250>;
>> 5554 polling-delay = <1000>;
5857 5555
5858 thermal-sensors = <&t 5556 thermal-sensors = <&tsens1 3>;
5859 5557
5860 trips { 5558 trips {
5861 wlan_alert0: 5559 wlan_alert0: trip-point0 {
5862 tempe 5560 temperature = <90000>;
5863 hyste 5561 hysteresis = <2000>;
5864 type 5562 type = "hot";
5865 }; 5563 };
5866 }; 5564 };
5867 }; 5565 };
5868 5566
5869 q6-hvx-thermal { 5567 q6-hvx-thermal {
5870 polling-delay-passive 5568 polling-delay-passive = <250>;
>> 5569 polling-delay = <1000>;
5871 5570
5872 thermal-sensors = <&t 5571 thermal-sensors = <&tsens1 4>;
5873 5572
5874 trips { 5573 trips {
5875 q6_hvx_alert0 5574 q6_hvx_alert0: trip-point0 {
5876 tempe 5575 temperature = <90000>;
5877 hyste 5576 hysteresis = <2000>;
5878 type 5577 type = "hot";
5879 }; 5578 };
5880 }; 5579 };
5881 }; 5580 };
5882 5581
5883 camera-thermal { 5582 camera-thermal {
5884 polling-delay-passive 5583 polling-delay-passive = <250>;
>> 5584 polling-delay = <1000>;
5885 5585
5886 thermal-sensors = <&t 5586 thermal-sensors = <&tsens1 5>;
5887 5587
5888 trips { 5588 trips {
5889 camera_alert0 5589 camera_alert0: trip-point0 {
5890 tempe 5590 temperature = <90000>;
5891 hyste 5591 hysteresis = <2000>;
5892 type 5592 type = "hot";
5893 }; 5593 };
5894 }; 5594 };
5895 }; 5595 };
5896 5596
5897 video-thermal { 5597 video-thermal {
5898 polling-delay-passive 5598 polling-delay-passive = <250>;
>> 5599 polling-delay = <1000>;
5899 5600
5900 thermal-sensors = <&t 5601 thermal-sensors = <&tsens1 6>;
5901 5602
5902 trips { 5603 trips {
5903 video_alert0: 5604 video_alert0: trip-point0 {
5904 tempe 5605 temperature = <90000>;
5905 hyste 5606 hysteresis = <2000>;
5906 type 5607 type = "hot";
5907 }; 5608 };
5908 }; 5609 };
5909 }; 5610 };
5910 5611
5911 modem-thermal { 5612 modem-thermal {
5912 polling-delay-passive 5613 polling-delay-passive = <250>;
>> 5614 polling-delay = <1000>;
5913 5615
5914 thermal-sensors = <&t 5616 thermal-sensors = <&tsens1 7>;
5915 5617
5916 trips { 5618 trips {
5917 modem_alert0: 5619 modem_alert0: trip-point0 {
5918 tempe 5620 temperature = <90000>;
5919 hyste 5621 hysteresis = <2000>;
5920 type 5622 type = "hot";
5921 }; 5623 };
5922 }; 5624 };
5923 }; 5625 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5626 };
5933 }; 5627 };
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