1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> 15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 18 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 19 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 21 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 24 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 27 #include <dt-bindings/thermal/thermal.h>
31 28
32 / { 29 / {
33 interrupt-parent = <&intc>; 30 interrupt-parent = <&intc>;
34 31
35 #address-cells = <2>; 32 #address-cells = <2>;
36 #size-cells = <2>; 33 #size-cells = <2>;
37 34
38 aliases { 35 aliases {
39 i2c0 = &i2c0; 36 i2c0 = &i2c0;
40 i2c1 = &i2c1; 37 i2c1 = &i2c1;
41 i2c2 = &i2c2; 38 i2c2 = &i2c2;
42 i2c3 = &i2c3; 39 i2c3 = &i2c3;
43 i2c4 = &i2c4; 40 i2c4 = &i2c4;
44 i2c5 = &i2c5; 41 i2c5 = &i2c5;
45 i2c6 = &i2c6; 42 i2c6 = &i2c6;
46 i2c7 = &i2c7; 43 i2c7 = &i2c7;
47 i2c8 = &i2c8; 44 i2c8 = &i2c8;
48 i2c9 = &i2c9; 45 i2c9 = &i2c9;
49 i2c10 = &i2c10; 46 i2c10 = &i2c10;
50 i2c11 = &i2c11; 47 i2c11 = &i2c11;
51 i2c12 = &i2c12; 48 i2c12 = &i2c12;
52 i2c13 = &i2c13; 49 i2c13 = &i2c13;
53 i2c14 = &i2c14; 50 i2c14 = &i2c14;
54 i2c15 = &i2c15; 51 i2c15 = &i2c15;
55 spi0 = &spi0; 52 spi0 = &spi0;
56 spi1 = &spi1; 53 spi1 = &spi1;
57 spi2 = &spi2; 54 spi2 = &spi2;
58 spi3 = &spi3; 55 spi3 = &spi3;
59 spi4 = &spi4; 56 spi4 = &spi4;
60 spi5 = &spi5; 57 spi5 = &spi5;
61 spi6 = &spi6; 58 spi6 = &spi6;
62 spi7 = &spi7; 59 spi7 = &spi7;
63 spi8 = &spi8; 60 spi8 = &spi8;
64 spi9 = &spi9; 61 spi9 = &spi9;
65 spi10 = &spi10; 62 spi10 = &spi10;
66 spi11 = &spi11; 63 spi11 = &spi11;
67 spi12 = &spi12; 64 spi12 = &spi12;
68 spi13 = &spi13; 65 spi13 = &spi13;
69 spi14 = &spi14; 66 spi14 = &spi14;
70 spi15 = &spi15; 67 spi15 = &spi15;
71 }; 68 };
72 69
73 chosen { }; 70 chosen { };
74 71
75 clocks { !! 72 memory@80000000 {
76 xo_board: xo-board { !! 73 device_type = "memory";
77 compatible = "fixed-cl !! 74 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 75 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 76 };
80 clock-output-names = " !! 77
>> 78 reserved-memory {
>> 79 #address-cells = <2>;
>> 80 #size-cells = <2>;
>> 81 ranges;
>> 82
>> 83 hyp_mem: hyp-mem@85700000 {
>> 84 reg = <0 0x85700000 0 0x600000>;
>> 85 no-map;
81 }; 86 };
82 87
83 sleep_clk: sleep-clk { !! 88 xbl_mem: xbl-mem@85e00000 {
84 compatible = "fixed-cl !! 89 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 90 no-map;
86 clock-frequency = <327 !! 91 };
>> 92
>> 93 aop_mem: aop-mem@85fc0000 {
>> 94 reg = <0 0x85fc0000 0 0x20000>;
>> 95 no-map;
>> 96 };
>> 97
>> 98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
>> 99 compatible = "qcom,cmd-db";
>> 100 reg = <0x0 0x85fe0000 0 0x20000>;
>> 101 no-map;
>> 102 };
>> 103
>> 104 smem@86000000 {
>> 105 compatible = "qcom,smem";
>> 106 reg = <0x0 0x86000000 0 0x200000>;
>> 107 no-map;
>> 108 hwlocks = <&tcsr_mutex 3>;
>> 109 };
>> 110
>> 111 tz_mem: tz@86200000 {
>> 112 reg = <0 0x86200000 0 0x2d00000>;
>> 113 no-map;
>> 114 };
>> 115
>> 116 rmtfs_mem: rmtfs@88f00000 {
>> 117 compatible = "qcom,rmtfs-mem";
>> 118 reg = <0 0x88f00000 0 0x200000>;
>> 119 no-map;
>> 120
>> 121 qcom,client-id = <1>;
>> 122 qcom,vmid = <15>;
>> 123 };
>> 124
>> 125 qseecom_mem: qseecom@8ab00000 {
>> 126 reg = <0 0x8ab00000 0 0x1400000>;
>> 127 no-map;
>> 128 };
>> 129
>> 130 camera_mem: camera-mem@8bf00000 {
>> 131 reg = <0 0x8bf00000 0 0x500000>;
>> 132 no-map;
>> 133 };
>> 134
>> 135 ipa_fw_mem: ipa-fw@8c400000 {
>> 136 reg = <0 0x8c400000 0 0x10000>;
>> 137 no-map;
>> 138 };
>> 139
>> 140 ipa_gsi_mem: ipa-gsi@8c410000 {
>> 141 reg = <0 0x8c410000 0 0x5000>;
>> 142 no-map;
>> 143 };
>> 144
>> 145 gpu_mem: gpu@8c415000 {
>> 146 reg = <0 0x8c415000 0 0x2000>;
>> 147 no-map;
>> 148 };
>> 149
>> 150 adsp_mem: adsp@8c500000 {
>> 151 reg = <0 0x8c500000 0 0x1a00000>;
>> 152 no-map;
>> 153 };
>> 154
>> 155 wlan_msa_mem: wlan-msa@8df00000 {
>> 156 reg = <0 0x8df00000 0 0x100000>;
>> 157 no-map;
>> 158 };
>> 159
>> 160 mpss_region: mpss@8e000000 {
>> 161 reg = <0 0x8e000000 0 0x7800000>;
>> 162 no-map;
>> 163 };
>> 164
>> 165 venus_mem: venus@95800000 {
>> 166 reg = <0 0x95800000 0 0x500000>;
>> 167 no-map;
>> 168 };
>> 169
>> 170 cdsp_mem: cdsp@95d00000 {
>> 171 reg = <0 0x95d00000 0 0x800000>;
>> 172 no-map;
>> 173 };
>> 174
>> 175 mba_region: mba@96500000 {
>> 176 reg = <0 0x96500000 0 0x200000>;
>> 177 no-map;
>> 178 };
>> 179
>> 180 slpi_mem: slpi@96700000 {
>> 181 reg = <0 0x96700000 0 0x1400000>;
>> 182 no-map;
>> 183 };
>> 184
>> 185 spss_mem: spss@97b00000 {
>> 186 reg = <0 0x97b00000 0 0x100000>;
>> 187 no-map;
87 }; 188 };
88 }; 189 };
89 190
90 cpus: cpus { 191 cpus: cpus {
91 #address-cells = <2>; 192 #address-cells = <2>;
92 #size-cells = <0>; 193 #size-cells = <0>;
93 194
94 CPU0: cpu@0 { 195 CPU0: cpu@0 {
95 device_type = "cpu"; 196 device_type = "cpu";
96 compatible = "qcom,kry 197 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 198 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 199 enable-method = "psci";
100 capacity-dmips-mhz = < 200 capacity-dmips-mhz = <611>;
101 dynamic-power-coeffici 201 dynamic-power-coefficient = <154>;
102 qcom,freq-domain = <&c 202 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 203 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ 206 power-domains = <&CPU_PD0>;
107 power-domain-names = " 207 power-domain-names = "psci";
108 #cooling-cells = <2>; 208 #cooling-cells = <2>;
109 next-level-cache = <&L 209 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 210 L2_0: l2-cache {
111 compatible = " 211 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 212 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 213 L3_0: l3-cache {
116 compat !! 214 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 215 };
120 }; 216 };
121 }; 217 };
122 218
123 CPU1: cpu@100 { 219 CPU1: cpu@100 {
124 device_type = "cpu"; 220 device_type = "cpu";
125 compatible = "qcom,kry 221 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 222 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 223 enable-method = "psci";
129 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <611>;
130 dynamic-power-coeffici 225 dynamic-power-coefficient = <154>;
131 qcom,freq-domain = <&c 226 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 227 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ 230 power-domains = <&CPU_PD1>;
136 power-domain-names = " 231 power-domain-names = "psci";
137 #cooling-cells = <2>; 232 #cooling-cells = <2>;
138 next-level-cache = <&L 233 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 234 L2_100: l2-cache {
140 compatible = " 235 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 236 next-level-cache = <&L3_0>;
144 }; 237 };
145 }; 238 };
146 239
147 CPU2: cpu@200 { 240 CPU2: cpu@200 {
148 device_type = "cpu"; 241 device_type = "cpu";
149 compatible = "qcom,kry 242 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 243 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 244 enable-method = "psci";
153 capacity-dmips-mhz = < 245 capacity-dmips-mhz = <611>;
154 dynamic-power-coeffici 246 dynamic-power-coefficient = <154>;
155 qcom,freq-domain = <&c 247 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 248 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 249 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ 251 power-domains = <&CPU_PD2>;
160 power-domain-names = " 252 power-domain-names = "psci";
161 #cooling-cells = <2>; 253 #cooling-cells = <2>;
162 next-level-cache = <&L 254 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 255 L2_200: l2-cache {
164 compatible = " 256 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 257 next-level-cache = <&L3_0>;
168 }; 258 };
169 }; 259 };
170 260
171 CPU3: cpu@300 { 261 CPU3: cpu@300 {
172 device_type = "cpu"; 262 device_type = "cpu";
173 compatible = "qcom,kry 263 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 264 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 265 enable-method = "psci";
177 capacity-dmips-mhz = < 266 capacity-dmips-mhz = <611>;
178 dynamic-power-coeffici 267 dynamic-power-coefficient = <154>;
179 qcom,freq-domain = <&c 268 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 269 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 270 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 271 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 272 #cooling-cells = <2>;
184 power-domains = <&CPU_ 273 power-domains = <&CPU_PD3>;
185 power-domain-names = " 274 power-domain-names = "psci";
186 next-level-cache = <&L 275 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 276 L2_300: l2-cache {
188 compatible = " 277 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 278 next-level-cache = <&L3_0>;
192 }; 279 };
193 }; 280 };
194 281
195 CPU4: cpu@400 { 282 CPU4: cpu@400 {
196 device_type = "cpu"; 283 device_type = "cpu";
197 compatible = "qcom,kry 284 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 285 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 286 enable-method = "psci";
201 capacity-dmips-mhz = < 287 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici 288 dynamic-power-coefficient = <442>;
203 qcom,freq-domain = <&c 289 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 290 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 291 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 292 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ 293 power-domains = <&CPU_PD4>;
208 power-domain-names = " 294 power-domain-names = "psci";
209 #cooling-cells = <2>; 295 #cooling-cells = <2>;
210 next-level-cache = <&L 296 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 297 L2_400: l2-cache {
212 compatible = " 298 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 299 next-level-cache = <&L3_0>;
216 }; 300 };
217 }; 301 };
218 302
219 CPU5: cpu@500 { 303 CPU5: cpu@500 {
220 device_type = "cpu"; 304 device_type = "cpu";
221 compatible = "qcom,kry 305 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 306 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 307 enable-method = "psci";
225 capacity-dmips-mhz = < 308 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici 309 dynamic-power-coefficient = <442>;
227 qcom,freq-domain = <&c 310 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 311 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 312 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 313 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ 314 power-domains = <&CPU_PD5>;
232 power-domain-names = " 315 power-domain-names = "psci";
233 #cooling-cells = <2>; 316 #cooling-cells = <2>;
234 next-level-cache = <&L 317 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 318 L2_500: l2-cache {
236 compatible = " 319 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 320 next-level-cache = <&L3_0>;
240 }; 321 };
241 }; 322 };
242 323
243 CPU6: cpu@600 { 324 CPU6: cpu@600 {
244 device_type = "cpu"; 325 device_type = "cpu";
245 compatible = "qcom,kry 326 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 327 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 328 enable-method = "psci";
249 capacity-dmips-mhz = < 329 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici 330 dynamic-power-coefficient = <442>;
251 qcom,freq-domain = <&c 331 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 332 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ 335 power-domains = <&CPU_PD6>;
256 power-domain-names = " 336 power-domain-names = "psci";
257 #cooling-cells = <2>; 337 #cooling-cells = <2>;
258 next-level-cache = <&L 338 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 339 L2_600: l2-cache {
260 compatible = " 340 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 341 next-level-cache = <&L3_0>;
264 }; 342 };
265 }; 343 };
266 344
267 CPU7: cpu@700 { 345 CPU7: cpu@700 {
268 device_type = "cpu"; 346 device_type = "cpu";
269 compatible = "qcom,kry 347 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 348 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 349 enable-method = "psci";
273 capacity-dmips-mhz = < 350 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici 351 dynamic-power-coefficient = <442>;
275 qcom,freq-domain = <&c 352 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 353 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 354 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 355 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ 356 power-domains = <&CPU_PD7>;
280 power-domain-names = " 357 power-domain-names = "psci";
281 #cooling-cells = <2>; 358 #cooling-cells = <2>;
282 next-level-cache = <&L 359 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 360 L2_700: l2-cache {
284 compatible = " 361 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 362 next-level-cache = <&L3_0>;
288 }; 363 };
289 }; 364 };
290 365
291 cpu-map { 366 cpu-map {
292 cluster0 { 367 cluster0 {
293 core0 { 368 core0 {
294 cpu = 369 cpu = <&CPU0>;
295 }; 370 };
296 371
297 core1 { 372 core1 {
298 cpu = 373 cpu = <&CPU1>;
299 }; 374 };
300 375
301 core2 { 376 core2 {
302 cpu = 377 cpu = <&CPU2>;
303 }; 378 };
304 379
305 core3 { 380 core3 {
306 cpu = 381 cpu = <&CPU3>;
307 }; 382 };
308 383
309 core4 { 384 core4 {
310 cpu = 385 cpu = <&CPU4>;
311 }; 386 };
312 387
313 core5 { 388 core5 {
314 cpu = 389 cpu = <&CPU5>;
315 }; 390 };
316 391
317 core6 { 392 core6 {
318 cpu = 393 cpu = <&CPU6>;
319 }; 394 };
320 395
321 core7 { 396 core7 {
322 cpu = 397 cpu = <&CPU7>;
323 }; 398 };
324 }; 399 };
325 }; 400 };
326 401
327 cpu_idle_states: idle-states { 402 cpu_idle_states: idle-states {
328 entry-method = "psci"; 403 entry-method = "psci";
329 404
330 LITTLE_CPU_SLEEP_0: cp 405 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 406 compatible = "arm,idle-state";
332 idle-state-nam 407 idle-state-name = "little-rail-power-collapse";
333 arm,psci-suspe 408 arm,psci-suspend-param = <0x40000004>;
334 entry-latency- 409 entry-latency-us = <350>;
335 exit-latency-u 410 exit-latency-us = <461>;
336 min-residency- 411 min-residency-us = <1890>;
337 local-timer-st 412 local-timer-stop;
338 }; 413 };
339 414
340 BIG_CPU_SLEEP_0: cpu-s 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 compatible = " 416 compatible = "arm,idle-state";
342 idle-state-nam 417 idle-state-name = "big-rail-power-collapse";
343 arm,psci-suspe 418 arm,psci-suspend-param = <0x40000004>;
344 entry-latency- 419 entry-latency-us = <264>;
345 exit-latency-u 420 exit-latency-us = <621>;
346 min-residency- 421 min-residency-us = <952>;
347 local-timer-st 422 local-timer-stop;
348 }; 423 };
349 }; 424 };
350 425
351 domain-idle-states { 426 domain-idle-states {
352 CLUSTER_SLEEP_0: clust 427 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " 428 compatible = "domain-idle-state";
>> 429 idle-state-name = "cluster-power-collapse";
354 arm,psci-suspe 430 arm,psci-suspend-param = <0x4100c244>;
355 entry-latency- 431 entry-latency-us = <3263>;
356 exit-latency-u 432 exit-latency-us = <6562>;
357 min-residency- 433 min-residency-us = <9987>;
>> 434 local-timer-stop;
358 }; 435 };
359 }; 436 };
360 }; 437 };
361 438
362 firmware { <<
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { 439 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points 440 compatible = "operating-points-v2";
376 opp-shared; 441 opp-shared;
377 442
378 cpu0_opp1: opp-300000000 { 443 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 444 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 445 opp-peak-kBps = <800000 4800000>;
381 }; 446 };
382 447
383 cpu0_opp2: opp-403200000 { 448 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 449 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 450 opp-peak-kBps = <800000 4800000>;
386 }; 451 };
387 452
388 cpu0_opp3: opp-480000000 { 453 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 454 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 455 opp-peak-kBps = <800000 6451200>;
391 }; 456 };
392 457
393 cpu0_opp4: opp-576000000 { 458 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 459 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 460 opp-peak-kBps = <800000 6451200>;
396 }; 461 };
397 462
398 cpu0_opp5: opp-652800000 { 463 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 464 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 465 opp-peak-kBps = <800000 7680000>;
401 }; 466 };
402 467
403 cpu0_opp6: opp-748800000 { 468 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 469 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 470 opp-peak-kBps = <1804000 9216000>;
406 }; 471 };
407 472
408 cpu0_opp7: opp-825600000 { 473 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 474 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 475 opp-peak-kBps = <1804000 9216000>;
411 }; 476 };
412 477
413 cpu0_opp8: opp-902400000 { 478 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 479 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 480 opp-peak-kBps = <1804000 10444800>;
416 }; 481 };
417 482
418 cpu0_opp9: opp-979200000 { 483 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 484 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 485 opp-peak-kBps = <1804000 11980800>;
421 }; 486 };
422 487
423 cpu0_opp10: opp-1056000000 { 488 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 489 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 490 opp-peak-kBps = <1804000 11980800>;
426 }; 491 };
427 492
428 cpu0_opp11: opp-1132800000 { 493 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 494 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 495 opp-peak-kBps = <2188000 13516800>;
431 }; 496 };
432 497
433 cpu0_opp12: opp-1228800000 { 498 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 499 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 500 opp-peak-kBps = <2188000 15052800>;
436 }; 501 };
437 502
438 cpu0_opp13: opp-1324800000 { 503 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 504 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 505 opp-peak-kBps = <2188000 16588800>;
441 }; 506 };
442 507
443 cpu0_opp14: opp-1420800000 { 508 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 509 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 510 opp-peak-kBps = <3072000 18124800>;
446 }; 511 };
447 512
448 cpu0_opp15: opp-1516800000 { 513 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 514 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 515 opp-peak-kBps = <3072000 19353600>;
451 }; 516 };
452 517
453 cpu0_opp16: opp-1612800000 { 518 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 519 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 520 opp-peak-kBps = <4068000 19353600>;
456 }; 521 };
457 522
458 cpu0_opp17: opp-1689600000 { 523 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 524 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 525 opp-peak-kBps = <4068000 20889600>;
461 }; 526 };
462 527
463 cpu0_opp18: opp-1766400000 { 528 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 529 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 530 opp-peak-kBps = <4068000 22425600>;
466 }; 531 };
467 }; 532 };
468 533
469 cpu4_opp_table: opp-table-cpu4 { 534 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 535 compatible = "operating-points-v2";
471 opp-shared; 536 opp-shared;
472 537
473 cpu4_opp1: opp-300000000 { 538 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 539 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 540 opp-peak-kBps = <800000 4800000>;
476 }; 541 };
477 542
478 cpu4_opp2: opp-403200000 { 543 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 544 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 545 opp-peak-kBps = <800000 4800000>;
481 }; 546 };
482 547
483 cpu4_opp3: opp-480000000 { 548 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 549 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 550 opp-peak-kBps = <1804000 4800000>;
486 }; 551 };
487 552
488 cpu4_opp4: opp-576000000 { 553 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 554 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 555 opp-peak-kBps = <1804000 4800000>;
491 }; 556 };
492 557
493 cpu4_opp5: opp-652800000 { 558 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 559 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 560 opp-peak-kBps = <1804000 4800000>;
496 }; 561 };
497 562
498 cpu4_opp6: opp-748800000 { 563 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 564 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 565 opp-peak-kBps = <1804000 4800000>;
501 }; 566 };
502 567
503 cpu4_opp7: opp-825600000 { 568 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 569 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 570 opp-peak-kBps = <2188000 9216000>;
506 }; 571 };
507 572
508 cpu4_opp8: opp-902400000 { 573 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 574 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 575 opp-peak-kBps = <2188000 9216000>;
511 }; 576 };
512 577
513 cpu4_opp9: opp-979200000 { 578 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 579 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 580 opp-peak-kBps = <2188000 9216000>;
516 }; 581 };
517 582
518 cpu4_opp10: opp-1056000000 { 583 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 584 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 585 opp-peak-kBps = <3072000 9216000>;
521 }; 586 };
522 587
523 cpu4_opp11: opp-1132800000 { 588 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 589 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 590 opp-peak-kBps = <3072000 11980800>;
526 }; 591 };
527 592
528 cpu4_opp12: opp-1209600000 { 593 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 594 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 595 opp-peak-kBps = <4068000 11980800>;
531 }; 596 };
532 597
533 cpu4_opp13: opp-1286400000 { 598 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 599 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 600 opp-peak-kBps = <4068000 11980800>;
536 }; 601 };
537 602
538 cpu4_opp14: opp-1363200000 { 603 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 604 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 605 opp-peak-kBps = <4068000 15052800>;
541 }; 606 };
542 607
543 cpu4_opp15: opp-1459200000 { 608 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 609 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 610 opp-peak-kBps = <4068000 15052800>;
546 }; 611 };
547 612
548 cpu4_opp16: opp-1536000000 { 613 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 614 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 615 opp-peak-kBps = <5412000 15052800>;
551 }; 616 };
552 617
553 cpu4_opp17: opp-1612800000 { 618 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 619 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 620 opp-peak-kBps = <5412000 15052800>;
556 }; 621 };
557 622
558 cpu4_opp18: opp-1689600000 { 623 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 624 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 625 opp-peak-kBps = <5412000 19353600>;
561 }; 626 };
562 627
563 cpu4_opp19: opp-1766400000 { 628 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 629 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 630 opp-peak-kBps = <6220000 19353600>;
566 }; 631 };
567 632
568 cpu4_opp20: opp-1843200000 { 633 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 634 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 635 opp-peak-kBps = <6220000 19353600>;
571 }; 636 };
572 637
573 cpu4_opp21: opp-1920000000 { 638 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 639 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 640 opp-peak-kBps = <7216000 19353600>;
576 }; 641 };
577 642
578 cpu4_opp22: opp-1996800000 { 643 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 644 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 645 opp-peak-kBps = <7216000 20889600>;
581 }; 646 };
582 647
583 cpu4_opp23: opp-2092800000 { 648 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 649 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 650 opp-peak-kBps = <7216000 20889600>;
586 }; 651 };
587 652
588 cpu4_opp24: opp-2169600000 { 653 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 654 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 655 opp-peak-kBps = <7216000 20889600>;
591 }; 656 };
592 657
593 cpu4_opp25: opp-2246400000 { 658 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 659 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 660 opp-peak-kBps = <7216000 20889600>;
596 }; 661 };
597 662
598 cpu4_opp26: opp-2323200000 { 663 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 664 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 665 opp-peak-kBps = <7216000 20889600>;
601 }; 666 };
602 667
603 cpu4_opp27: opp-2400000000 { 668 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 669 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 670 opp-peak-kBps = <7216000 22425600>;
606 }; 671 };
607 672
608 cpu4_opp28: opp-2476800000 { 673 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 674 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 675 opp-peak-kBps = <7216000 22425600>;
611 }; 676 };
612 677
613 cpu4_opp29: opp-2553600000 { 678 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 679 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 680 opp-peak-kBps = <7216000 22425600>;
616 }; 681 };
617 682
618 cpu4_opp30: opp-2649600000 { 683 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 684 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 685 opp-peak-kBps = <7216000 22425600>;
621 }; 686 };
622 687
623 cpu4_opp31: opp-2745600000 { 688 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 689 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 690 opp-peak-kBps = <7216000 25497600>;
626 }; 691 };
627 692
628 cpu4_opp32: opp-2803200000 { 693 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 694 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 695 opp-peak-kBps = <7216000 25497600>;
631 }; 696 };
632 }; 697 };
633 698
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 699 pmu {
712 compatible = "arm,armv8-pmuv3" 700 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 701 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 702 };
715 703
716 psci: psci { !! 704 timer {
717 compatible = "arm,psci-1.0"; !! 705 compatible = "arm,armv8-timer";
718 method = "smc"; !! 706 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 707 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 708 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 709 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 710 };
773 711
774 reserved-memory { !! 712 clocks {
775 #address-cells = <2>; !! 713 xo_board: xo-board {
776 #size-cells = <2>; !! 714 compatible = "fixed-clock";
777 ranges; !! 715 #clock-cells = <0>;
778 !! 716 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 717 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 718 };
885 719
886 mdata_mem: mpss-metadata { !! 720 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 721 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 722 #clock-cells = <0>;
889 no-map; !! 723 clock-frequency = <32764>;
890 }; 724 };
>> 725 };
891 726
892 fastrpc_mem: fastrpc { !! 727 firmware {
893 compatible = "shared-d !! 728 scm {
894 alloc-ranges = <0x0 0x !! 729 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 730 };
899 }; 731 };
900 732
901 adsp_pas: remoteproc-adsp { 733 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 734 compatible = "qcom,sdm845-adsp-pas";
903 735
904 interrupts-extended = <&intc G 736 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 737 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 738 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 739 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 740 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 741 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 742 "handover", "stop-ack";
911 743
912 clocks = <&rpmhcc RPMH_CXO_CLK 744 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 745 clock-names = "xo";
914 746
915 memory-region = <&adsp_mem>; 747 memory-region = <&adsp_mem>;
916 748
917 qcom,qmp = <&aoss_qmp>; 749 qcom,qmp = <&aoss_qmp>;
918 750
919 qcom,smem-states = <&adsp_smp2 751 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 752 qcom,smem-state-names = "stop";
921 753
922 status = "disabled"; 754 status = "disabled";
923 755
924 glink-edge { 756 glink-edge {
925 interrupts = <GIC_SPI 757 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 758 label = "lpass";
927 qcom,remote-pid = <2>; 759 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 760 mboxes = <&apss_shared 8>;
929 761
930 apr { 762 apr {
931 compatible = " 763 compatible = "qcom,apr-v2";
932 qcom,glink-cha 764 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = 765 qcom,domain = <APR_DOMAIN_ADSP>;
934 #address-cells 766 #address-cells = <1>;
935 #size-cells = 767 #size-cells = <0>;
936 qcom,intents = 768 qcom,intents = <512 20>;
937 769
938 service@3 { !! 770 apr-service@3 {
939 reg = 771 reg = <APR_SVC_ADSP_CORE>;
940 compat 772 compatible = "qcom,q6core";
941 qcom,p 773 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 774 };
943 775
944 q6afe: service !! 776 q6afe: apr-service@4 {
945 compat 777 compatible = "qcom,q6afe";
946 reg = 778 reg = <APR_SVC_AFE>;
947 qcom,p 779 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 780 q6afedai: dais {
949 781 compatible = "qcom,q6afe-dais";
950 782 #address-cells = <1>;
951 783 #size-cells = <0>;
952 784 #sound-dai-cells = <1>;
953 }; 785 };
954 }; 786 };
955 787
956 q6asm: service !! 788 q6asm: apr-service@7 {
957 compat 789 compatible = "qcom,q6asm";
958 reg = 790 reg = <APR_SVC_ASM>;
959 qcom,p 791 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 792 q6asmdai: dais {
961 793 compatible = "qcom,q6asm-dais";
962 794 #address-cells = <1>;
963 795 #size-cells = <0>;
964 796 #sound-dai-cells = <1>;
965 797 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 798 };
967 }; 799 };
968 800
969 q6adm: service !! 801 q6adm: apr-service@8 {
970 compat 802 compatible = "qcom,q6adm";
971 reg = 803 reg = <APR_SVC_ADM>;
972 qcom,p 804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 805 q6routing: routing {
974 806 compatible = "qcom,q6adm-routing";
975 807 #sound-dai-cells = <0>;
976 }; 808 };
977 }; 809 };
978 }; 810 };
979 811
980 fastrpc { 812 fastrpc {
981 compatible = " 813 compatible = "qcom,fastrpc";
982 qcom,glink-cha 814 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 815 label = "adsp";
984 qcom,non-secur 816 qcom,non-secure-domain;
985 #address-cells 817 #address-cells = <1>;
986 #size-cells = 818 #size-cells = <0>;
987 819
988 compute-cb@3 { 820 compute-cb@3 {
989 compat 821 compatible = "qcom,fastrpc-compute-cb";
990 reg = 822 reg = <3>;
991 iommus 823 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 824 };
993 825
994 compute-cb@4 { 826 compute-cb@4 {
995 compat 827 compatible = "qcom,fastrpc-compute-cb";
996 reg = 828 reg = <4>;
997 iommus 829 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 830 };
999 }; 831 };
1000 }; 832 };
1001 }; 833 };
1002 834
1003 cdsp_pas: remoteproc-cdsp { 835 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 836 compatible = "qcom,sdm845-cdsp-pas";
1005 837
1006 interrupts-extended = <&intc 838 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 839 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 840 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 841 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 842 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 843 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 844 "handover", "stop-ack";
1013 845
1014 clocks = <&rpmhcc RPMH_CXO_CL 846 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 847 clock-names = "xo";
1016 848
1017 memory-region = <&cdsp_mem>; 849 memory-region = <&cdsp_mem>;
1018 850
1019 qcom,qmp = <&aoss_qmp>; 851 qcom,qmp = <&aoss_qmp>;
1020 852
1021 qcom,smem-states = <&cdsp_smp 853 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 854 qcom,smem-state-names = "stop";
1023 855
1024 status = "disabled"; 856 status = "disabled";
1025 857
1026 glink-edge { 858 glink-edge {
1027 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 860 label = "turing";
1029 qcom,remote-pid = <5> 861 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 862 mboxes = <&apss_shared 4>;
1031 fastrpc { 863 fastrpc {
1032 compatible = 864 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 865 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 866 label = "cdsp";
1035 qcom,non-secu 867 qcom,non-secure-domain;
1036 #address-cell 868 #address-cells = <1>;
1037 #size-cells = 869 #size-cells = <0>;
1038 870
1039 compute-cb@1 871 compute-cb@1 {
1040 compa 872 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 873 reg = <1>;
1042 iommu 874 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 875 };
1044 876
1045 compute-cb@2 877 compute-cb@2 {
1046 compa 878 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 879 reg = <2>;
1048 iommu 880 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 881 };
1050 882
1051 compute-cb@3 883 compute-cb@3 {
1052 compa 884 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 885 reg = <3>;
1054 iommu 886 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 887 };
1056 888
1057 compute-cb@4 889 compute-cb@4 {
1058 compa 890 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 891 reg = <4>;
1060 iommu 892 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 893 };
1062 894
1063 compute-cb@5 895 compute-cb@5 {
1064 compa 896 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 897 reg = <5>;
1066 iommu 898 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 899 };
1068 900
1069 compute-cb@6 901 compute-cb@6 {
1070 compa 902 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 903 reg = <6>;
1072 iommu 904 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 905 };
1074 906
1075 compute-cb@7 907 compute-cb@7 {
1076 compa 908 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 909 reg = <7>;
1078 iommu 910 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 911 };
1080 912
1081 compute-cb@8 913 compute-cb@8 {
1082 compa 914 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 915 reg = <8>;
1084 iommu 916 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 917 };
1086 }; 918 };
1087 }; 919 };
1088 }; 920 };
1089 921
1090 smp2p-cdsp { 922 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 923 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 924 qcom,smem = <94>, <432>;
1093 925
1094 interrupts = <GIC_SPI 576 IRQ 926 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 927
1096 mboxes = <&apss_shared 6>; 928 mboxes = <&apss_shared 6>;
1097 929
1098 qcom,local-pid = <0>; 930 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 931 qcom,remote-pid = <5>;
1100 932
1101 cdsp_smp2p_out: master-kernel 933 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 934 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 935 #qcom,smem-state-cells = <1>;
1104 }; 936 };
1105 937
1106 cdsp_smp2p_in: slave-kernel { 938 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 939 qcom,entry-name = "slave-kernel";
1108 940
1109 interrupt-controller; 941 interrupt-controller;
1110 #interrupt-cells = <2 942 #interrupt-cells = <2>;
1111 }; 943 };
1112 }; 944 };
1113 945
1114 smp2p-lpass { 946 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 947 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 948 qcom,smem = <443>, <429>;
1117 949
1118 interrupts = <GIC_SPI 158 IRQ 950 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 951
1120 mboxes = <&apss_shared 10>; 952 mboxes = <&apss_shared 10>;
1121 953
1122 qcom,local-pid = <0>; 954 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 955 qcom,remote-pid = <2>;
1124 956
1125 adsp_smp2p_out: master-kernel 957 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 958 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 959 #qcom,smem-state-cells = <1>;
1128 }; 960 };
1129 961
1130 adsp_smp2p_in: slave-kernel { 962 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 963 qcom,entry-name = "slave-kernel";
1132 964
1133 interrupt-controller; 965 interrupt-controller;
1134 #interrupt-cells = <2 966 #interrupt-cells = <2>;
1135 }; 967 };
1136 }; 968 };
1137 969
1138 smp2p-mpss { 970 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 971 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 972 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 973 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 974 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 975 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 976 qcom,remote-pid = <1>;
1145 977
1146 modem_smp2p_out: master-kerne 978 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 979 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 980 #qcom,smem-state-cells = <1>;
1149 }; 981 };
1150 982
1151 modem_smp2p_in: slave-kernel 983 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 984 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 985 interrupt-controller;
1154 #interrupt-cells = <2 986 #interrupt-cells = <2>;
1155 }; 987 };
1156 988
1157 ipa_smp2p_out: ipa-ap-to-mode 989 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 990 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 991 #qcom,smem-state-cells = <1>;
1160 }; 992 };
1161 993
1162 ipa_smp2p_in: ipa-modem-to-ap 994 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 995 qcom,entry-name = "ipa";
1164 interrupt-controller; 996 interrupt-controller;
1165 #interrupt-cells = <2 997 #interrupt-cells = <2>;
1166 }; 998 };
1167 }; 999 };
1168 1000
1169 smp2p-slpi { 1001 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1002 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1003 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1004 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1005 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1006 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1007 qcom,remote-pid = <3>;
1176 1008
1177 slpi_smp2p_out: master-kernel 1009 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1010 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1011 #qcom,smem-state-cells = <1>;
1180 }; 1012 };
1181 1013
1182 slpi_smp2p_in: slave-kernel { 1014 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1015 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1016 interrupt-controller;
1185 #interrupt-cells = <2 1017 #interrupt-cells = <2>;
1186 }; 1018 };
1187 }; 1019 };
1188 1020
>> 1021 psci: psci {
>> 1022 compatible = "arm,psci-1.0";
>> 1023 method = "smc";
>> 1024
>> 1025 CPU_PD0: power-domain-cpu0 {
>> 1026 #power-domain-cells = <0>;
>> 1027 power-domains = <&CLUSTER_PD>;
>> 1028 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1029 };
>> 1030
>> 1031 CPU_PD1: power-domain-cpu1 {
>> 1032 #power-domain-cells = <0>;
>> 1033 power-domains = <&CLUSTER_PD>;
>> 1034 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1035 };
>> 1036
>> 1037 CPU_PD2: power-domain-cpu2 {
>> 1038 #power-domain-cells = <0>;
>> 1039 power-domains = <&CLUSTER_PD>;
>> 1040 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1041 };
>> 1042
>> 1043 CPU_PD3: power-domain-cpu3 {
>> 1044 #power-domain-cells = <0>;
>> 1045 power-domains = <&CLUSTER_PD>;
>> 1046 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1047 };
>> 1048
>> 1049 CPU_PD4: power-domain-cpu4 {
>> 1050 #power-domain-cells = <0>;
>> 1051 power-domains = <&CLUSTER_PD>;
>> 1052 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1053 };
>> 1054
>> 1055 CPU_PD5: power-domain-cpu5 {
>> 1056 #power-domain-cells = <0>;
>> 1057 power-domains = <&CLUSTER_PD>;
>> 1058 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1059 };
>> 1060
>> 1061 CPU_PD6: power-domain-cpu6 {
>> 1062 #power-domain-cells = <0>;
>> 1063 power-domains = <&CLUSTER_PD>;
>> 1064 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1065 };
>> 1066
>> 1067 CPU_PD7: power-domain-cpu7 {
>> 1068 #power-domain-cells = <0>;
>> 1069 power-domains = <&CLUSTER_PD>;
>> 1070 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1071 };
>> 1072
>> 1073 CLUSTER_PD: power-domain-cluster {
>> 1074 #power-domain-cells = <0>;
>> 1075 domain-idle-states = <&CLUSTER_SLEEP_0>;
>> 1076 };
>> 1077 };
>> 1078
1189 soc: soc@0 { 1079 soc: soc@0 {
1190 #address-cells = <2>; 1080 #address-cells = <2>;
1191 #size-cells = <2>; 1081 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1082 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1083 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1084 compatible = "simple-bus";
1195 1085
1196 gcc: clock-controller@100000 1086 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1087 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1088 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1089 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1090 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1091 <&sleep_clk>,
1202 <&pcie0_phy> !! 1092 <&pcie0_lane>,
1203 <&pcie1_phy> !! 1093 <&pcie1_lane>;
1204 clock-names = "bi_tcx 1094 clock-names = "bi_tcxo",
1205 "bi_tcx 1095 "bi_tcxo_ao",
1206 "sleep_ 1096 "sleep_clk",
1207 "pcie_0 1097 "pcie_0_pipe_clk",
1208 "pcie_1 1098 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1099 #clock-cells = <1>;
1210 #reset-cells = <1>; 1100 #reset-cells = <1>;
1211 #power-domain-cells = 1101 #power-domain-cells = <1>;
1212 power-domains = <&rpm 1102 power-domains = <&rpmhpd SDM845_CX>;
1213 }; 1103 };
1214 1104
1215 qfprom@784000 { 1105 qfprom@784000 {
1216 compatible = "qcom,sd 1106 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 reg = <0 0x00784000 0 1107 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1108 #address-cells = <1>;
1219 #size-cells = <1>; 1109 #size-cells = <1>;
1220 1110
1221 qusb2p_hstx_trim: hst 1111 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1112 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1113 bits = <1 4>;
1224 }; 1114 };
1225 1115
1226 qusb2s_hstx_trim: hst 1116 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1117 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1118 bits = <6 4>;
1229 }; 1119 };
1230 }; 1120 };
1231 1121
1232 rng: rng@793000 { 1122 rng: rng@793000 {
1233 compatible = "qcom,pr 1123 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1124 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1125 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1126 clock-names = "core";
1237 }; 1127 };
1238 1128
>> 1129 qup_opp_table: opp-table-qup {
>> 1130 compatible = "operating-points-v2";
>> 1131
>> 1132 opp-50000000 {
>> 1133 opp-hz = /bits/ 64 <50000000>;
>> 1134 required-opps = <&rpmhpd_opp_min_svs>;
>> 1135 };
>> 1136
>> 1137 opp-75000000 {
>> 1138 opp-hz = /bits/ 64 <75000000>;
>> 1139 required-opps = <&rpmhpd_opp_low_svs>;
>> 1140 };
>> 1141
>> 1142 opp-100000000 {
>> 1143 opp-hz = /bits/ 64 <100000000>;
>> 1144 required-opps = <&rpmhpd_opp_svs>;
>> 1145 };
>> 1146
>> 1147 opp-128000000 {
>> 1148 opp-hz = /bits/ 64 <128000000>;
>> 1149 required-opps = <&rpmhpd_opp_nom>;
>> 1150 };
>> 1151 };
>> 1152
1239 gpi_dma0: dma-controller@8000 1153 gpi_dma0: dma-controller@800000 {
1240 #dma-cells = <3>; 1154 #dma-cells = <3>;
1241 compatible = "qcom,sd 1155 compatible = "qcom,sdm845-gpi-dma";
1242 reg = <0 0x00800000 0 1156 reg = <0 0x00800000 0 0x60000>;
1243 interrupts = <GIC_SPI 1157 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 1158 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 1159 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 1160 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 1161 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 1162 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 1163 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 1164 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 1165 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 1166 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 1167 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 1168 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 1169 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256 dma-channels = <13>; 1170 dma-channels = <13>;
1257 dma-channel-mask = <0 1171 dma-channel-mask = <0xfa>;
1258 iommus = <&apps_smmu 1172 iommus = <&apps_smmu 0x0016 0x0>;
1259 status = "disabled"; 1173 status = "disabled";
1260 }; 1174 };
1261 1175
1262 qupv3_id_0: geniqup@8c0000 { 1176 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1177 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1178 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1179 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1180 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1181 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1182 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1183 #address-cells = <2>;
1270 #size-cells = <2>; 1184 #size-cells = <2>;
1271 ranges; 1185 ranges;
1272 interconnects = <&agg 1186 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1187 interconnect-names = "qup-core";
1274 status = "disabled"; 1188 status = "disabled";
1275 1189
1276 i2c0: i2c@880000 { 1190 i2c0: i2c@880000 {
1277 compatible = 1191 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1192 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1193 clock-names = "se";
1280 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1195 pinctrl-names = "default";
1282 pinctrl-0 = < 1196 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1197 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1198 #address-cells = <1>;
1285 #size-cells = 1199 #size-cells = <0>;
1286 power-domains 1200 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1201 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1202 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1203 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1204 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1205 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ 1206 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293 <&gpi_ 1207 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1294 dma-names = " 1208 dma-names = "tx", "rx";
1295 status = "dis 1209 status = "disabled";
1296 }; 1210 };
1297 1211
1298 spi0: spi@880000 { 1212 spi0: spi@880000 {
1299 compatible = 1213 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1214 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1215 clock-names = "se";
1302 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1217 pinctrl-names = "default";
1304 pinctrl-0 = < 1218 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1219 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1220 #address-cells = <1>;
1307 #size-cells = 1221 #size-cells = <0>;
1308 interconnects 1222 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1223 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1224 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ 1225 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_ 1226 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313 dma-names = " 1227 dma-names = "tx", "rx";
1314 status = "dis 1228 status = "disabled";
1315 }; 1229 };
1316 1230
1317 uart0: serial@880000 1231 uart0: serial@880000 {
1318 compatible = 1232 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1233 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1234 clock-names = "se";
1321 clocks = <&gc 1235 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1236 pinctrl-names = "default";
1323 pinctrl-0 = < 1237 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1238 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1239 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1240 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1241 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1242 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1243 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1244 status = "disabled";
1331 }; 1245 };
1332 1246
1333 i2c1: i2c@884000 { 1247 i2c1: i2c@884000 {
1334 compatible = 1248 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1249 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1250 clock-names = "se";
1337 clocks = <&gc 1251 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1252 pinctrl-names = "default";
1339 pinctrl-0 = < 1253 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1254 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1255 #address-cells = <1>;
1342 #size-cells = 1256 #size-cells = <0>;
1343 power-domains 1257 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1258 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1259 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1260 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1261 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1262 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ 1263 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1350 <&gpi_ 1264 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1351 dma-names = " 1265 dma-names = "tx", "rx";
1352 status = "dis 1266 status = "disabled";
1353 }; 1267 };
1354 1268
1355 spi1: spi@884000 { 1269 spi1: spi@884000 {
1356 compatible = 1270 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1271 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1272 clock-names = "se";
1359 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1274 pinctrl-names = "default";
1361 pinctrl-0 = < 1275 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1276 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1277 #address-cells = <1>;
1364 #size-cells = 1278 #size-cells = <0>;
1365 interconnects 1279 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1280 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1281 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ 1282 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1369 <&gpi_ 1283 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1370 dma-names = " 1284 dma-names = "tx", "rx";
1371 status = "dis 1285 status = "disabled";
1372 }; 1286 };
1373 1287
1374 uart1: serial@884000 1288 uart1: serial@884000 {
1375 compatible = 1289 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1290 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1291 clock-names = "se";
1378 clocks = <&gc 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1293 pinctrl-names = "default";
1380 pinctrl-0 = < 1294 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1295 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1296 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1297 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1298 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1299 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1300 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1301 status = "disabled";
1388 }; 1302 };
1389 1303
1390 i2c2: i2c@888000 { 1304 i2c2: i2c@888000 {
1391 compatible = 1305 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1306 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1307 clock-names = "se";
1394 clocks = <&gc 1308 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1309 pinctrl-names = "default";
1396 pinctrl-0 = < 1310 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1311 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1312 #address-cells = <1>;
1399 #size-cells = 1313 #size-cells = <0>;
1400 power-domains 1314 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1315 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1316 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1317 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1318 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1319 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ 1320 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1407 <&gpi_ 1321 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1408 dma-names = " 1322 dma-names = "tx", "rx";
1409 status = "dis 1323 status = "disabled";
1410 }; 1324 };
1411 1325
1412 spi2: spi@888000 { 1326 spi2: spi@888000 {
1413 compatible = 1327 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1328 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1329 clock-names = "se";
1416 clocks = <&gc 1330 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1331 pinctrl-names = "default";
1418 pinctrl-0 = < 1332 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1333 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1334 #address-cells = <1>;
1421 #size-cells = 1335 #size-cells = <0>;
1422 interconnects 1336 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1337 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1338 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ 1339 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1426 <&gpi_ 1340 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1427 dma-names = " 1341 dma-names = "tx", "rx";
1428 status = "dis 1342 status = "disabled";
1429 }; 1343 };
1430 1344
1431 uart2: serial@888000 1345 uart2: serial@888000 {
1432 compatible = 1346 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1347 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1348 clock-names = "se";
1435 clocks = <&gc 1349 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1350 pinctrl-names = "default";
1437 pinctrl-0 = < 1351 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1352 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1353 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1354 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1355 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1356 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1357 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1358 status = "disabled";
1445 }; 1359 };
1446 1360
1447 i2c3: i2c@88c000 { 1361 i2c3: i2c@88c000 {
1448 compatible = 1362 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1363 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1364 clock-names = "se";
1451 clocks = <&gc 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1366 pinctrl-names = "default";
1453 pinctrl-0 = < 1367 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1368 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1369 #address-cells = <1>;
1456 #size-cells = 1370 #size-cells = <0>;
1457 power-domains 1371 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1372 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1373 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1374 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1375 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1376 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ 1377 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1464 <&gpi_ 1378 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1465 dma-names = " 1379 dma-names = "tx", "rx";
1466 status = "dis 1380 status = "disabled";
1467 }; 1381 };
1468 1382
1469 spi3: spi@88c000 { 1383 spi3: spi@88c000 {
1470 compatible = 1384 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1385 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1386 clock-names = "se";
1473 clocks = <&gc 1387 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1388 pinctrl-names = "default";
1475 pinctrl-0 = < 1389 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1390 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1391 #address-cells = <1>;
1478 #size-cells = 1392 #size-cells = <0>;
1479 interconnects 1393 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1394 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1395 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ 1396 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1483 <&gpi_ 1397 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1484 dma-names = " 1398 dma-names = "tx", "rx";
1485 status = "dis 1399 status = "disabled";
1486 }; 1400 };
1487 1401
1488 uart3: serial@88c000 1402 uart3: serial@88c000 {
1489 compatible = 1403 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1404 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1405 clock-names = "se";
1492 clocks = <&gc 1406 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1407 pinctrl-names = "default";
1494 pinctrl-0 = < 1408 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1409 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1410 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1411 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1412 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1413 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1414 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1415 status = "disabled";
1502 }; 1416 };
1503 1417
1504 i2c4: i2c@890000 { 1418 i2c4: i2c@890000 {
1505 compatible = 1419 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1420 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1421 clock-names = "se";
1508 clocks = <&gc 1422 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1423 pinctrl-names = "default";
1510 pinctrl-0 = < 1424 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1425 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1426 #address-cells = <1>;
1513 #size-cells = 1427 #size-cells = <0>;
1514 power-domains 1428 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1429 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1430 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1431 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1432 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1433 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ 1434 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521 <&gpi_ 1435 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522 dma-names = " 1436 dma-names = "tx", "rx";
1523 status = "dis 1437 status = "disabled";
1524 }; 1438 };
1525 1439
1526 spi4: spi@890000 { 1440 spi4: spi@890000 {
1527 compatible = 1441 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1442 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1443 clock-names = "se";
1530 clocks = <&gc 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1445 pinctrl-names = "default";
1532 pinctrl-0 = < 1446 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1447 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1448 #address-cells = <1>;
1535 #size-cells = 1449 #size-cells = <0>;
1536 interconnects 1450 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1451 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1452 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ 1453 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1540 <&gpi_ 1454 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1541 dma-names = " 1455 dma-names = "tx", "rx";
1542 status = "dis 1456 status = "disabled";
1543 }; 1457 };
1544 1458
1545 uart4: serial@890000 1459 uart4: serial@890000 {
1546 compatible = 1460 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1461 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1462 clock-names = "se";
1549 clocks = <&gc 1463 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1464 pinctrl-names = "default";
1551 pinctrl-0 = < 1465 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1466 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1467 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1468 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1469 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1470 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1471 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1472 status = "disabled";
1559 }; 1473 };
1560 1474
1561 i2c5: i2c@894000 { 1475 i2c5: i2c@894000 {
1562 compatible = 1476 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1477 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1478 clock-names = "se";
1565 clocks = <&gc 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1480 pinctrl-names = "default";
1567 pinctrl-0 = < 1481 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1482 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1483 #address-cells = <1>;
1570 #size-cells = 1484 #size-cells = <0>;
1571 power-domains 1485 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1486 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1487 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1488 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1489 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1490 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ 1491 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1578 <&gpi_ 1492 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1579 dma-names = " 1493 dma-names = "tx", "rx";
1580 status = "dis 1494 status = "disabled";
1581 }; 1495 };
1582 1496
1583 spi5: spi@894000 { 1497 spi5: spi@894000 {
1584 compatible = 1498 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1499 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1500 clock-names = "se";
1587 clocks = <&gc 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1502 pinctrl-names = "default";
1589 pinctrl-0 = < 1503 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1504 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1505 #address-cells = <1>;
1592 #size-cells = 1506 #size-cells = <0>;
1593 interconnects 1507 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1508 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1509 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ 1510 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1597 <&gpi_ 1511 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1598 dma-names = " 1512 dma-names = "tx", "rx";
1599 status = "dis 1513 status = "disabled";
1600 }; 1514 };
1601 1515
1602 uart5: serial@894000 1516 uart5: serial@894000 {
1603 compatible = 1517 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1518 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1519 clock-names = "se";
1606 clocks = <&gc 1520 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1521 pinctrl-names = "default";
1608 pinctrl-0 = < 1522 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1523 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1524 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1525 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1526 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1527 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1528 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1529 status = "disabled";
1616 }; 1530 };
1617 1531
1618 i2c6: i2c@898000 { 1532 i2c6: i2c@898000 {
1619 compatible = 1533 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1534 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1535 clock-names = "se";
1622 clocks = <&gc 1536 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1537 pinctrl-names = "default";
1624 pinctrl-0 = < 1538 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1539 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1540 #address-cells = <1>;
1627 #size-cells = 1541 #size-cells = <0>;
1628 power-domains 1542 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1543 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1544 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1545 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1546 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1547 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ 1548 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1635 <&gpi_ 1549 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1636 dma-names = " 1550 dma-names = "tx", "rx";
1637 status = "dis 1551 status = "disabled";
1638 }; 1552 };
1639 1553
1640 spi6: spi@898000 { 1554 spi6: spi@898000 {
1641 compatible = 1555 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1556 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1557 clock-names = "se";
1644 clocks = <&gc 1558 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1559 pinctrl-names = "default";
1646 pinctrl-0 = < 1560 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1561 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1562 #address-cells = <1>;
1649 #size-cells = 1563 #size-cells = <0>;
1650 interconnects 1564 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1565 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1566 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ 1567 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1654 <&gpi_ 1568 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1655 dma-names = " 1569 dma-names = "tx", "rx";
1656 status = "dis 1570 status = "disabled";
1657 }; 1571 };
1658 1572
1659 uart6: serial@898000 1573 uart6: serial@898000 {
1660 compatible = 1574 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1575 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1576 clock-names = "se";
1663 clocks = <&gc 1577 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1578 pinctrl-names = "default";
1665 pinctrl-0 = < 1579 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1580 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1581 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1582 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1583 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1584 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1585 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1586 status = "disabled";
1673 }; 1587 };
1674 1588
1675 i2c7: i2c@89c000 { 1589 i2c7: i2c@89c000 {
1676 compatible = 1590 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1591 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1592 clock-names = "se";
1679 clocks = <&gc 1593 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1594 pinctrl-names = "default";
1681 pinctrl-0 = < 1595 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1596 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1597 #address-cells = <1>;
1684 #size-cells = 1598 #size-cells = <0>;
1685 power-domains 1599 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1600 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1601 status = "disabled";
1688 }; 1602 };
1689 1603
1690 spi7: spi@89c000 { 1604 spi7: spi@89c000 {
1691 compatible = 1605 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1606 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1607 clock-names = "se";
1694 clocks = <&gc 1608 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1609 pinctrl-names = "default";
1696 pinctrl-0 = < 1610 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1611 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1612 #address-cells = <1>;
1699 #size-cells = 1613 #size-cells = <0>;
1700 interconnects 1614 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1615 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1616 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ 1617 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1704 <&gpi_ 1618 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1705 dma-names = " 1619 dma-names = "tx", "rx";
1706 status = "dis 1620 status = "disabled";
1707 }; 1621 };
1708 1622
1709 uart7: serial@89c000 1623 uart7: serial@89c000 {
1710 compatible = 1624 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1625 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1626 clock-names = "se";
1713 clocks = <&gc 1627 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1628 pinctrl-names = "default";
1715 pinctrl-0 = < 1629 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1630 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1631 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1632 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1633 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1634 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1635 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1636 status = "disabled";
1723 }; 1637 };
1724 }; 1638 };
1725 1639
1726 gpi_dma1: dma-controller@a000 !! 1640 gpi_dma1: dma-controller@0xa00000 {
1727 #dma-cells = <3>; 1641 #dma-cells = <3>;
1728 compatible = "qcom,sd 1642 compatible = "qcom,sdm845-gpi-dma";
1729 reg = <0 0x00a00000 0 1643 reg = <0 0x00a00000 0 0x60000>;
1730 interrupts = <GIC_SPI 1644 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1645 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 1646 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 1647 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 1648 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 1649 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 1650 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1651 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1652 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1653 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1654 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1655 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1656 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743 dma-channels = <13>; 1657 dma-channels = <13>;
1744 dma-channel-mask = <0 1658 dma-channel-mask = <0xfa>;
1745 iommus = <&apps_smmu 1659 iommus = <&apps_smmu 0x06d6 0x0>;
1746 status = "disabled"; 1660 status = "disabled";
1747 }; 1661 };
1748 1662
1749 qupv3_id_1: geniqup@ac0000 { 1663 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1664 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1665 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1666 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1667 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1668 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1669 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1670 #address-cells = <2>;
1757 #size-cells = <2>; 1671 #size-cells = <2>;
1758 ranges; 1672 ranges;
1759 interconnects = <&agg 1673 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1674 interconnect-names = "qup-core";
1761 status = "disabled"; 1675 status = "disabled";
1762 1676
1763 i2c8: i2c@a80000 { 1677 i2c8: i2c@a80000 {
1764 compatible = 1678 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1679 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1680 clock-names = "se";
1767 clocks = <&gc 1681 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1682 pinctrl-names = "default";
1769 pinctrl-0 = < 1683 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1684 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1685 #address-cells = <1>;
1772 #size-cells = 1686 #size-cells = <0>;
1773 power-domains 1687 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1688 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1689 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1690 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1691 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1692 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ 1693 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780 <&gpi_ 1694 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1781 dma-names = " 1695 dma-names = "tx", "rx";
1782 status = "dis 1696 status = "disabled";
1783 }; 1697 };
1784 1698
1785 spi8: spi@a80000 { 1699 spi8: spi@a80000 {
1786 compatible = 1700 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1701 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1702 clock-names = "se";
1789 clocks = <&gc 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1704 pinctrl-names = "default";
1791 pinctrl-0 = < 1705 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1706 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1707 #address-cells = <1>;
1794 #size-cells = 1708 #size-cells = <0>;
1795 interconnects 1709 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1710 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1711 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ 1712 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799 <&gpi_ 1713 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1800 dma-names = " 1714 dma-names = "tx", "rx";
1801 status = "dis 1715 status = "disabled";
1802 }; 1716 };
1803 1717
1804 uart8: serial@a80000 1718 uart8: serial@a80000 {
1805 compatible = 1719 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1720 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1721 clock-names = "se";
1808 clocks = <&gc 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1723 pinctrl-names = "default";
1810 pinctrl-0 = < 1724 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1725 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1726 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1727 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1728 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1729 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1730 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1731 status = "disabled";
1818 }; 1732 };
1819 1733
1820 i2c9: i2c@a84000 { 1734 i2c9: i2c@a84000 {
1821 compatible = 1735 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1736 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1737 clock-names = "se";
1824 clocks = <&gc 1738 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1739 pinctrl-names = "default";
1826 pinctrl-0 = < 1740 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1741 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1742 #address-cells = <1>;
1829 #size-cells = 1743 #size-cells = <0>;
1830 power-domains 1744 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1745 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1746 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1747 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1748 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1749 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ 1750 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1837 <&gpi_ 1751 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1838 dma-names = " 1752 dma-names = "tx", "rx";
1839 status = "dis 1753 status = "disabled";
1840 }; 1754 };
1841 1755
1842 spi9: spi@a84000 { 1756 spi9: spi@a84000 {
1843 compatible = 1757 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1758 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1759 clock-names = "se";
1846 clocks = <&gc 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1761 pinctrl-names = "default";
1848 pinctrl-0 = < 1762 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1763 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1764 #address-cells = <1>;
1851 #size-cells = 1765 #size-cells = <0>;
1852 interconnects 1766 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1767 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1768 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ 1769 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1856 <&gpi_ 1770 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1857 dma-names = " 1771 dma-names = "tx", "rx";
1858 status = "dis 1772 status = "disabled";
1859 }; 1773 };
1860 1774
1861 uart9: serial@a84000 1775 uart9: serial@a84000 {
1862 compatible = 1776 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1777 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1778 clock-names = "se";
1865 clocks = <&gc 1779 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1780 pinctrl-names = "default";
1867 pinctrl-0 = < 1781 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1782 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1783 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1784 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1785 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1786 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1787 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1788 status = "disabled";
1875 }; 1789 };
1876 1790
1877 i2c10: i2c@a88000 { 1791 i2c10: i2c@a88000 {
1878 compatible = 1792 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1793 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1794 clock-names = "se";
1881 clocks = <&gc 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1796 pinctrl-names = "default";
1883 pinctrl-0 = < 1797 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1798 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1799 #address-cells = <1>;
1886 #size-cells = 1800 #size-cells = <0>;
1887 power-domains 1801 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1802 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1803 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1804 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1805 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1806 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ 1807 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1894 <&gpi_ 1808 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1895 dma-names = " 1809 dma-names = "tx", "rx";
1896 status = "dis 1810 status = "disabled";
1897 }; 1811 };
1898 1812
1899 spi10: spi@a88000 { 1813 spi10: spi@a88000 {
1900 compatible = 1814 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1815 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1816 clock-names = "se";
1903 clocks = <&gc 1817 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1818 pinctrl-names = "default";
1905 pinctrl-0 = < 1819 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1820 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1821 #address-cells = <1>;
1908 #size-cells = 1822 #size-cells = <0>;
1909 interconnects 1823 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1824 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1825 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ 1826 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913 <&gpi_ 1827 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1914 dma-names = " 1828 dma-names = "tx", "rx";
1915 status = "dis 1829 status = "disabled";
1916 }; 1830 };
1917 1831
1918 uart10: serial@a88000 1832 uart10: serial@a88000 {
1919 compatible = 1833 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1834 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1835 clock-names = "se";
1922 clocks = <&gc 1836 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1837 pinctrl-names = "default";
1924 pinctrl-0 = < 1838 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1839 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1840 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1841 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1842 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1843 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1844 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1845 status = "disabled";
1932 }; 1846 };
1933 1847
1934 i2c11: i2c@a8c000 { 1848 i2c11: i2c@a8c000 {
1935 compatible = 1849 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1850 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1851 clock-names = "se";
1938 clocks = <&gc 1852 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1853 pinctrl-names = "default";
1940 pinctrl-0 = < 1854 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1855 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1856 #address-cells = <1>;
1943 #size-cells = 1857 #size-cells = <0>;
1944 power-domains 1858 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1859 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1860 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1861 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1862 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1863 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ 1864 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1951 <&gpi_ 1865 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1952 dma-names = " 1866 dma-names = "tx", "rx";
1953 status = "dis 1867 status = "disabled";
1954 }; 1868 };
1955 1869
1956 spi11: spi@a8c000 { 1870 spi11: spi@a8c000 {
1957 compatible = 1871 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1872 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1873 clock-names = "se";
1960 clocks = <&gc 1874 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1875 pinctrl-names = "default";
1962 pinctrl-0 = < 1876 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1877 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1878 #address-cells = <1>;
1965 #size-cells = 1879 #size-cells = <0>;
1966 interconnects 1880 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1881 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1882 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ 1883 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1970 <&gpi_ 1884 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1971 dma-names = " 1885 dma-names = "tx", "rx";
1972 status = "dis 1886 status = "disabled";
1973 }; 1887 };
1974 1888
1975 uart11: serial@a8c000 1889 uart11: serial@a8c000 {
1976 compatible = 1890 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1891 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1892 clock-names = "se";
1979 clocks = <&gc 1893 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1894 pinctrl-names = "default";
1981 pinctrl-0 = < 1895 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1896 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1897 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1898 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1899 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1900 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1901 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1902 status = "disabled";
1989 }; 1903 };
1990 1904
1991 i2c12: i2c@a90000 { 1905 i2c12: i2c@a90000 {
1992 compatible = 1906 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1907 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1908 clock-names = "se";
1995 clocks = <&gc 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1910 pinctrl-names = "default";
1997 pinctrl-0 = < 1911 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1912 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1913 #address-cells = <1>;
2000 #size-cells = 1914 #size-cells = <0>;
2001 power-domains 1915 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1916 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 1917 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 1918 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 1919 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 1920 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ 1921 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2008 <&gpi_ 1922 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2009 dma-names = " 1923 dma-names = "tx", "rx";
2010 status = "dis 1924 status = "disabled";
2011 }; 1925 };
2012 1926
2013 spi12: spi@a90000 { 1927 spi12: spi@a90000 {
2014 compatible = 1928 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1929 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1930 clock-names = "se";
2017 clocks = <&gc 1931 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1932 pinctrl-names = "default";
2019 pinctrl-0 = < 1933 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1934 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1935 #address-cells = <1>;
2022 #size-cells = 1936 #size-cells = <0>;
2023 interconnects 1937 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 1938 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 1939 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ 1940 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2027 <&gpi_ 1941 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2028 dma-names = " 1942 dma-names = "tx", "rx";
2029 status = "dis 1943 status = "disabled";
2030 }; 1944 };
2031 1945
2032 uart12: serial@a90000 1946 uart12: serial@a90000 {
2033 compatible = 1947 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1948 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1949 clock-names = "se";
2036 clocks = <&gc 1950 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1951 pinctrl-names = "default";
2038 pinctrl-0 = < 1952 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1953 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1954 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1955 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 1956 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 1957 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 1958 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 1959 status = "disabled";
2046 }; 1960 };
2047 1961
2048 i2c13: i2c@a94000 { 1962 i2c13: i2c@a94000 {
2049 compatible = 1963 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1964 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1965 clock-names = "se";
2052 clocks = <&gc 1966 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1967 pinctrl-names = "default";
2054 pinctrl-0 = < 1968 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1969 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1970 #address-cells = <1>;
2057 #size-cells = 1971 #size-cells = <0>;
2058 power-domains 1972 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1973 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 1974 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 1975 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 1976 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 1977 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ 1978 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2065 <&gpi_ 1979 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2066 dma-names = " 1980 dma-names = "tx", "rx";
2067 status = "dis 1981 status = "disabled";
2068 }; 1982 };
2069 1983
2070 spi13: spi@a94000 { 1984 spi13: spi@a94000 {
2071 compatible = 1985 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1986 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1987 clock-names = "se";
2074 clocks = <&gc 1988 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1989 pinctrl-names = "default";
2076 pinctrl-0 = < 1990 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1991 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1992 #address-cells = <1>;
2079 #size-cells = 1993 #size-cells = <0>;
2080 interconnects 1994 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 1995 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 1996 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ 1997 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2084 <&gpi_ 1998 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2085 dma-names = " 1999 dma-names = "tx", "rx";
2086 status = "dis 2000 status = "disabled";
2087 }; 2001 };
2088 2002
2089 uart13: serial@a94000 2003 uart13: serial@a94000 {
2090 compatible = 2004 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 2005 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 2006 clock-names = "se";
2093 clocks = <&gc 2007 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 2008 pinctrl-names = "default";
2095 pinctrl-0 = < 2009 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 2010 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 2011 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 2012 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 2013 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 2014 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 2015 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 2016 status = "disabled";
2103 }; 2017 };
2104 2018
2105 i2c14: i2c@a98000 { 2019 i2c14: i2c@a98000 {
2106 compatible = 2020 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 2021 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 2022 clock-names = "se";
2109 clocks = <&gc 2023 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 2024 pinctrl-names = "default";
2111 pinctrl-0 = < 2025 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 2026 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 2027 #address-cells = <1>;
2114 #size-cells = 2028 #size-cells = <0>;
2115 power-domains 2029 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 2030 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 2031 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 2032 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 2033 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 2034 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ 2035 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2122 <&gpi_ 2036 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2123 dma-names = " 2037 dma-names = "tx", "rx";
2124 status = "dis 2038 status = "disabled";
2125 }; 2039 };
2126 2040
2127 spi14: spi@a98000 { 2041 spi14: spi@a98000 {
2128 compatible = 2042 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 2043 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 2044 clock-names = "se";
2131 clocks = <&gc 2045 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 2046 pinctrl-names = "default";
2133 pinctrl-0 = < 2047 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 2048 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 2049 #address-cells = <1>;
2136 #size-cells = 2050 #size-cells = <0>;
2137 interconnects 2051 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 2052 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 2053 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ 2054 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2141 <&gpi_ 2055 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2142 dma-names = " 2056 dma-names = "tx", "rx";
2143 status = "dis 2057 status = "disabled";
2144 }; 2058 };
2145 2059
2146 uart14: serial@a98000 2060 uart14: serial@a98000 {
2147 compatible = 2061 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 2062 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 2063 clock-names = "se";
2150 clocks = <&gc 2064 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 2065 pinctrl-names = "default";
2152 pinctrl-0 = < 2066 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 2067 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 2068 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 2069 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 2070 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 2071 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 2072 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 2073 status = "disabled";
2160 }; 2074 };
2161 2075
2162 i2c15: i2c@a9c000 { 2076 i2c15: i2c@a9c000 {
2163 compatible = 2077 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 2078 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 2079 clock-names = "se";
2166 clocks = <&gc 2080 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 2081 pinctrl-names = "default";
2168 pinctrl-0 = < 2082 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 2083 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 2084 #address-cells = <1>;
2171 #size-cells = 2085 #size-cells = <0>;
2172 power-domains 2086 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 2087 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 2088 status = "disabled";
2175 interconnects 2089 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 2090 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 2091 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 2092 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ 2093 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2180 <&gpi_ 2094 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2181 dma-names = " 2095 dma-names = "tx", "rx";
2182 }; 2096 };
2183 2097
2184 spi15: spi@a9c000 { 2098 spi15: spi@a9c000 {
2185 compatible = 2099 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 2100 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 2101 clock-names = "se";
2188 clocks = <&gc 2102 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 2103 pinctrl-names = "default";
2190 pinctrl-0 = < 2104 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 2105 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 2106 #address-cells = <1>;
2193 #size-cells = 2107 #size-cells = <0>;
2194 interconnects 2108 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 2109 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 2110 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ 2111 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2198 <&gpi_ 2112 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2199 dma-names = " 2113 dma-names = "tx", "rx";
2200 status = "dis 2114 status = "disabled";
2201 }; 2115 };
2202 2116
2203 uart15: serial@a9c000 2117 uart15: serial@a9c000 {
2204 compatible = 2118 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 2119 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 2120 clock-names = "se";
2207 clocks = <&gc 2121 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 2122 pinctrl-names = "default";
2209 pinctrl-0 = < 2123 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 2124 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 2125 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 2126 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 2127 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 2128 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 2129 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 2130 status = "disabled";
2217 }; 2131 };
2218 }; 2132 };
2219 2133
2220 llcc: system-cache-controller 2134 llcc: system-cache-controller@1100000 {
2221 compatible = "qcom,sd 2135 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 2136 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 2137 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 2138 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 2139 };
2229 2140
2230 dma@10a2000 { <<
2231 compatible = "qcom,sd <<
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { 2141 pmu@114a000 {
2237 compatible = "qcom,sd 2142 compatible = "qcom,sdm845-llcc-bwmon";
2238 reg = <0 0x0114a000 0 2143 reg = <0 0x0114a000 0 0x1000>;
2239 interrupts = <GIC_SPI 2144 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2240 interconnects = <&mem 2145 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2241 2146
2242 operating-points-v2 = 2147 operating-points-v2 = <&llcc_bwmon_opp_table>;
2243 2148
2244 llcc_bwmon_opp_table: 2149 llcc_bwmon_opp_table: opp-table {
2245 compatible = 2150 compatible = "operating-points-v2";
2246 2151
2247 /* 2152 /*
2248 * The interc 2153 * The interconnect path bandwidth taken from
2249 * cpu4_opp_t 2154 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2250 * interconne 2155 * interconnect. This also matches the
2251 * bandwidth 2156 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2252 * bus width: 2157 * bus width: 4 bytes) from msm-4.9 downstream
2253 * kernel. 2158 * kernel.
2254 */ 2159 */
2255 opp-0 { 2160 opp-0 {
2256 opp-p 2161 opp-peak-kBps = <800000>;
2257 }; 2162 };
2258 opp-1 { 2163 opp-1 {
2259 opp-p 2164 opp-peak-kBps = <1804000>;
2260 }; 2165 };
2261 opp-2 { 2166 opp-2 {
2262 opp-p 2167 opp-peak-kBps = <3072000>;
2263 }; 2168 };
2264 opp-3 { 2169 opp-3 {
2265 opp-p 2170 opp-peak-kBps = <5412000>;
2266 }; 2171 };
2267 opp-4 { 2172 opp-4 {
2268 opp-p 2173 opp-peak-kBps = <7216000>;
2269 }; 2174 };
2270 }; 2175 };
2271 }; 2176 };
2272 2177
2273 pmu@1436400 { 2178 pmu@1436400 {
2274 compatible = "qcom,sd !! 2179 compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
2275 reg = <0 0x01436400 0 2180 reg = <0 0x01436400 0 0x600>;
2276 interrupts = <GIC_SPI 2181 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2277 interconnects = <&gla 2182 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278 2183
2279 operating-points-v2 = 2184 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 2185
2281 cpu_bwmon_opp_table: 2186 cpu_bwmon_opp_table: opp-table {
2282 compatible = 2187 compatible = "operating-points-v2";
2283 2188
2284 /* 2189 /*
2285 * The interc 2190 * The interconnect path bandwidth taken from
2286 * cpu4_opp_t 2191 * cpu4_opp_table bandwidth for OSM L3
2287 * interconne 2192 * interconnect. This also matches the OSM L3
2288 * from bandw 2193 * from bandwidth table of qcom,cpu4-l3lat-mon
2289 * (qcom,core 2194 * (qcom,core-dev-table, bus width: 16 bytes)
2290 * from msm-4 2195 * from msm-4.9 downstream kernel.
2291 */ 2196 */
2292 opp-0 { 2197 opp-0 {
2293 opp-p 2198 opp-peak-kBps = <4800000>;
2294 }; 2199 };
2295 opp-1 { 2200 opp-1 {
2296 opp-p 2201 opp-peak-kBps = <9216000>;
2297 }; 2202 };
2298 opp-2 { 2203 opp-2 {
2299 opp-p 2204 opp-peak-kBps = <15052800>;
2300 }; 2205 };
2301 opp-3 { 2206 opp-3 {
2302 opp-p 2207 opp-peak-kBps = <20889600>;
2303 }; 2208 };
2304 opp-4 { 2209 opp-4 {
2305 opp-p 2210 opp-peak-kBps = <25497600>;
2306 }; 2211 };
2307 }; 2212 };
2308 }; 2213 };
2309 2214
2310 pcie0: pcie@1c00000 { !! 2215 pcie0: pci@1c00000 {
2311 compatible = "qcom,pc 2216 compatible = "qcom,pcie-sdm845";
2312 reg = <0 0x01c00000 0 2217 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 2218 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 2219 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 2220 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 2221 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 2222 device_type = "pci";
2319 linux,pci-domain = <0 2223 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 2224 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 2225 num-lanes = <1>;
2322 2226
2323 #address-cells = <3>; 2227 #address-cells = <3>;
2324 #size-cells = <2>; 2228 #size-cells = <2>;
2325 2229
2326 ranges = <0x01000000 2230 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2327 <0x02000000 2231 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2328 2232
2329 interrupts = <GIC_SPI 2233 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 2234 interrupt-names = "msi";
2331 #interrupt-cells = <1 2235 #interrupt-cells = <1>;
2332 interrupt-map-mask = 2236 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 2237 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 2238 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 2239 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 2240 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2241
2338 clocks = <&gcc GCC_PC 2242 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2243 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2244 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2245 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2246 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2247 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2248 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2249 clock-names = "pipe",
2346 "aux", 2250 "aux",
2347 "cfg", 2251 "cfg",
2348 "bus_ma 2252 "bus_master",
2349 "bus_sl 2253 "bus_slave",
2350 "slave_ 2254 "slave_q2a",
2351 "tbu"; 2255 "tbu";
2352 2256
>> 2257 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 2258 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2259 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2260 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2261 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2262 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2263 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2264 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2265 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2266 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2267 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2268 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2269 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2270 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2271 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2272 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2273 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2274
2370 resets = <&gcc GCC_PC 2275 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2276 reset-names = "pci";
2372 2277
2373 power-domains = <&gcc 2278 power-domains = <&gcc PCIE_0_GDSC>;
2374 2279
2375 phys = <&pcie0_phy>; !! 2280 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2281 phy-names = "pciephy";
2377 2282
2378 status = "disabled"; 2283 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2284 };
2390 2285
2391 pcie0_phy: phy@1c06000 { 2286 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2287 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2288 reg = <0 0x01c06000 0 0x18c>;
>> 2289 #address-cells = <2>;
>> 2290 #size-cells = <2>;
>> 2291 ranges;
2394 clocks = <&gcc GCC_PC 2292 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2293 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2294 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2295 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2296 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2297
2410 resets = <&gcc GCC_PC 2298 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2299 reset-names = "phy";
2412 2300
2413 assigned-clocks = <&g 2301 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2302 assigned-clock-rates = <100000000>;
2415 2303
2416 status = "disabled"; 2304 status = "disabled";
>> 2305
>> 2306 pcie0_lane: phy@1c06200 {
>> 2307 reg = <0 0x01c06200 0 0x128>,
>> 2308 <0 0x01c06400 0 0x1fc>,
>> 2309 <0 0x01c06800 0 0x218>,
>> 2310 <0 0x01c06600 0 0x70>;
>> 2311 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2312 clock-names = "pipe0";
>> 2313
>> 2314 #clock-cells = <0>;
>> 2315 #phy-cells = <0>;
>> 2316 clock-output-names = "pcie_0_pipe_clk";
>> 2317 };
2417 }; 2318 };
2418 2319
2419 pcie1: pcie@1c08000 { !! 2320 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc 2321 compatible = "qcom,pcie-sdm845";
2421 reg = <0 0x01c08000 0 2322 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2323 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2324 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 2325 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 2326 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 2327 device_type = "pci";
2428 linux,pci-domain = <1 2328 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2329 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2330 num-lanes = <1>;
2431 2331
2432 #address-cells = <3>; 2332 #address-cells = <3>;
2433 #size-cells = <2>; 2333 #size-cells = <2>;
2434 2334
2435 ranges = <0x01000000 2335 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2336 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2337
2438 interrupts = <GIC_SPI 2338 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2339 interrupt-names = "msi";
2440 #interrupt-cells = <1 2340 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2341 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 2342 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 2343 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 2344 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 2345 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2346
2447 clocks = <&gcc GCC_PC 2347 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2348 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2349 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2350 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2351 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2352 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2353 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2354 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2355 clock-names = "pipe",
2456 "aux", 2356 "aux",
2457 "cfg", 2357 "cfg",
2458 "bus_ma 2358 "bus_master",
2459 "bus_sl 2359 "bus_slave",
2460 "slave_ 2360 "slave_q2a",
2461 "ref", 2361 "ref",
2462 "tbu"; 2362 "tbu";
2463 2363
2464 assigned-clocks = <&g 2364 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2365 assigned-clock-rates = <19200000>;
2466 2366
>> 2367 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 2368 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2369 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2370 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2371 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2372 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2373 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2374 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2375 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2376 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2377 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2378 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2379 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2380 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2381 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2382 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2383 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2384
2484 resets = <&gcc GCC_PC 2385 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2386 reset-names = "pci";
2486 2387
2487 power-domains = <&gcc 2388 power-domains = <&gcc PCIE_1_GDSC>;
2488 2389
2489 phys = <&pcie1_phy>; !! 2390 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2391 phy-names = "pciephy";
2491 2392
2492 status = "disabled"; 2393 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2394 };
2504 2395
2505 pcie1_phy: phy@1c0a000 { 2396 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2397 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2398 reg = <0 0x01c0a000 0 0x800>;
>> 2399 #address-cells = <2>;
>> 2400 #size-cells = <2>;
>> 2401 ranges;
2508 clocks = <&gcc GCC_PC 2402 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2403 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2404 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2405 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2406 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2407
2524 resets = <&gcc GCC_PC 2408 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2409 reset-names = "phy";
2526 2410
2527 assigned-clocks = <&g 2411 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2412 assigned-clock-rates = <100000000>;
2529 2413
2530 status = "disabled"; 2414 status = "disabled";
>> 2415
>> 2416 pcie1_lane: phy@1c06200 {
>> 2417 reg = <0 0x01c0a800 0 0x800>,
>> 2418 <0 0x01c0a800 0 0x800>,
>> 2419 <0 0x01c0b800 0 0x400>;
>> 2420 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2421 clock-names = "pipe0";
>> 2422
>> 2423 #clock-cells = <0>;
>> 2424 #phy-cells = <0>;
>> 2425 clock-output-names = "pcie_1_pipe_clk";
>> 2426 };
2531 }; 2427 };
2532 2428
2533 mem_noc: interconnect@1380000 2429 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2430 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2431 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2432 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2433 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2434 };
2539 2435
2540 dc_noc: interconnect@14e0000 2436 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2437 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2438 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2439 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2440 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2441 };
2546 2442
2547 config_noc: interconnect@1500 2443 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2444 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2445 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2446 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2447 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2448 };
2553 2449
2554 system_noc: interconnect@1620 2450 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2451 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2452 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2453 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2454 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2455 };
2560 2456
2561 aggre1_noc: interconnect@16e0 2457 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2458 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2459 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2460 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2461 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2462 };
2567 2463
2568 aggre2_noc: interconnect@1700 2464 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2465 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2466 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2467 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2468 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2469 };
2574 2470
2575 mmss_noc: interconnect@174000 2471 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2472 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2473 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2474 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2475 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2476 };
2581 2477
2582 ufs_mem_hc: ufshc@1d84000 { 2478 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2479 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2480 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2481 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2482 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2483 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2484 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2485 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2486 phy-names = "ufsphy";
2591 lanes-per-direction = 2487 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2488 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2489 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2490 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2491 reset-names = "rst";
2596 2492
2597 iommus = <&apps_smmu 2493 iommus = <&apps_smmu 0x100 0xf>;
2598 2494
2599 clock-names = 2495 clock-names =
2600 "core_clk", 2496 "core_clk",
2601 "bus_aggr_clk 2497 "bus_aggr_clk",
2602 "iface_clk", 2498 "iface_clk",
2603 "core_clk_uni 2499 "core_clk_unipro",
2604 "ref_clk", 2500 "ref_clk",
2605 "tx_lane0_syn 2501 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2502 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2503 "rx_lane1_sync_clk",
2608 "ice_core_clk 2504 "ice_core_clk";
2609 clocks = 2505 clocks =
2610 <&gcc GCC_UFS 2506 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2507 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2508 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2509 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2510 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2511 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2512 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2513 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2514 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2515 freq-table-hz =
2620 operating-points-v2 = !! 2516 <50000000 200000000>,
2621 !! 2517 <0 0>,
2622 interconnects = <&agg !! 2518 <0 0>,
2623 <&gla !! 2519 <37500000 150000000>,
2624 interconnect-names = !! 2520 <0 0>,
>> 2521 <0 0>,
>> 2522 <0 0>,
>> 2523 <0 0>,
>> 2524 <75000000 300000000>;
2625 2525
2626 status = "disabled"; 2526 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2527 };
2658 2528
2659 ufs_mem_phy: phy@1d87000 { 2529 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2530 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2531 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2532 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2533 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2534 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2535 clock-names = "ref",
2667 "ref_au !! 2536 "ref_aux";
2668 "qref"; !! 2537 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>> 2538 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2669 2539
2670 power-domains = <&gcc 2540 power-domains = <&gcc UFS_PHY_GDSC>;
2671 2541
2672 resets = <&ufs_mem_hc 2542 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2543 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2544 status = "disabled";
>> 2545
>> 2546 ufs_mem_phy_lanes: phy@1d87400 {
>> 2547 reg = <0 0x01d87400 0 0x108>,
>> 2548 <0 0x01d87600 0 0x1e0>,
>> 2549 <0 0x01d87c00 0 0x1dc>,
>> 2550 <0 0x01d87800 0 0x108>,
>> 2551 <0 0x01d87a00 0 0x1e0>;
>> 2552 #phy-cells = <0>;
>> 2553 };
2677 }; 2554 };
2678 2555
2679 cryptobam: dma-controller@1dc 2556 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,ba !! 2557 compatible = "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2558 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2559 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2560 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2561 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2562 #dma-cells = <1>;
2686 qcom,ee = <0>; 2563 qcom,ee = <0>;
2687 qcom,controlled-remot 2564 qcom,controlled-remotely;
2688 iommus = <&apps_smmu 2565 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2566 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2567 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2568 <&apps_smmu 0x716 0x1>;
2692 }; 2569 };
2693 2570
2694 crypto: crypto@1dfa000 { 2571 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2572 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2573 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2574 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2575 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2576 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2577 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2578 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2579 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2580 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2581 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2582 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2583 <&apps_smmu 0x716 0x1>;
2707 }; 2584 };
2708 2585
2709 ipa: ipa@1e40000 { 2586 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2587 compatible = "qcom,sdm845-ipa";
2711 2588
2712 iommus = <&apps_smmu 2589 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2590 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 !! 2591 reg = <0 0x1e40000 0 0x7000>,
2715 <0 0x01e47000 0 !! 2592 <0 0x1e47000 0 0x2000>,
2716 <0 0x01e04000 0 !! 2593 <0 0x1e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2594 reg-names = "ipa-reg",
2718 "ipa-shar 2595 "ipa-shared",
2719 "gsi"; 2596 "gsi";
2720 2597
2721 interrupts-extended = 2598 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2599 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2600 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2601 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2602 interrupt-names = "ipa",
2726 "gs 2603 "gsi",
2727 "ip 2604 "ipa-clock-query",
2728 "ip 2605 "ipa-setup-ready";
2729 2606
2730 clocks = <&rpmhcc RPM 2607 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2608 clock-names = "core";
2732 2609
2733 interconnects = <&agg 2610 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2611 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2612 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2613 interconnect-names = "memory",
2737 2614 "imem",
2738 2615 "config";
2739 2616
2740 qcom,smem-states = <& 2617 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2618 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2619 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2620 "ipa-clock-enabled";
2744 2621
2745 status = "disabled"; 2622 status = "disabled";
2746 }; 2623 };
2747 2624
2748 tcsr_mutex: hwlock@1f40000 { 2625 tcsr_mutex: hwlock@1f40000 {
2749 compatible = "qcom,tc 2626 compatible = "qcom,tcsr-mutex";
2750 reg = <0 0x01f40000 0 2627 reg = <0 0x01f40000 0 0x20000>;
2751 #hwlock-cells = <1>; 2628 #hwlock-cells = <1>;
2752 }; 2629 };
2753 2630
2754 tcsr_regs_1: syscon@1f60000 { 2631 tcsr_regs_1: syscon@1f60000 {
2755 compatible = "qcom,sd 2632 compatible = "qcom,sdm845-tcsr", "syscon";
2756 reg = <0 0x01f60000 0 2633 reg = <0 0x01f60000 0 0x20000>;
2757 }; 2634 };
2758 2635
2759 tlmm: pinctrl@3400000 { 2636 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2637 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2638 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2639 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2640 gpio-controller;
2764 #gpio-cells = <2>; 2641 #gpio-cells = <2>;
2765 interrupt-controller; 2642 interrupt-controller;
2766 #interrupt-cells = <2 2643 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2644 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2645 wakeup-parent = <&pdc_intc>;
2769 2646
2770 cci0_default: cci0-de !! 2647 cci0_default: cci0-default {
2771 /* SDA, SCL * 2648 /* SDA, SCL */
2772 pins = "gpio1 2649 pins = "gpio17", "gpio18";
2773 function = "c 2650 function = "cci_i2c";
2774 2651
2775 bias-pull-up; 2652 bias-pull-up;
2776 drive-strengt 2653 drive-strength = <2>; /* 2 mA */
2777 }; 2654 };
2778 2655
2779 cci0_sleep: cci0-slee !! 2656 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2657 /* SDA, SCL */
2781 pins = "gpio1 2658 pins = "gpio17", "gpio18";
2782 function = "c 2659 function = "cci_i2c";
2783 2660
2784 drive-strengt 2661 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2662 bias-pull-down;
2786 }; 2663 };
2787 2664
2788 cci1_default: cci1-de !! 2665 cci1_default: cci1-default {
2789 /* SDA, SCL * 2666 /* SDA, SCL */
2790 pins = "gpio1 2667 pins = "gpio19", "gpio20";
2791 function = "c 2668 function = "cci_i2c";
2792 2669
2793 bias-pull-up; 2670 bias-pull-up;
2794 drive-strengt 2671 drive-strength = <2>; /* 2 mA */
2795 }; 2672 };
2796 2673
2797 cci1_sleep: cci1-slee !! 2674 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2675 /* SDA, SCL */
2799 pins = "gpio1 2676 pins = "gpio19", "gpio20";
2800 function = "c 2677 function = "cci_i2c";
2801 2678
2802 drive-strengt 2679 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2680 bias-pull-down;
2804 }; 2681 };
2805 2682
2806 qspi_clk: qspi-clk-st !! 2683 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2684 pinmux {
2808 function = "q !! 2685 pins = "gpio95";
2809 }; !! 2686 function = "qspi_clk";
2810 !! 2687 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; 2688 };
2815 2689
2816 qspi_cs1: qspi-cs1-st !! 2690 qspi_cs0: qspi-cs0 {
2817 pins = "gpio8 !! 2691 pinmux {
2818 function = "q !! 2692 pins = "gpio90";
>> 2693 function = "qspi_cs";
>> 2694 };
2819 }; 2695 };
2820 2696
2821 qspi_data0: qspi-data !! 2697 qspi_cs1: qspi-cs1 {
2822 pins = "gpio9 !! 2698 pinmux {
2823 function = "q !! 2699 pins = "gpio89";
>> 2700 function = "qspi_cs";
>> 2701 };
2824 }; 2702 };
2825 2703
2826 qspi_data1: qspi-data !! 2704 qspi_data01: qspi-data01 {
2827 pins = "gpio9 !! 2705 pinmux-data {
2828 function = "q !! 2706 pins = "gpio91", "gpio92";
>> 2707 function = "qspi_data";
>> 2708 };
2829 }; 2709 };
2830 2710
2831 qspi_data23: qspi-dat !! 2711 qspi_data12: qspi-data12 {
2832 pins = "gpio9 !! 2712 pinmux-data {
2833 function = "q !! 2713 pins = "gpio93", "gpio94";
>> 2714 function = "qspi_data";
>> 2715 };
2834 }; 2716 };
2835 2717
2836 qup_i2c0_default: qup !! 2718 qup_i2c0_default: qup-i2c0-default {
2837 pins = "gpio0 !! 2719 pinmux {
2838 function = "q !! 2720 pins = "gpio0", "gpio1";
>> 2721 function = "qup0";
>> 2722 };
2839 }; 2723 };
2840 2724
2841 qup_i2c1_default: qup !! 2725 qup_i2c1_default: qup-i2c1-default {
2842 pins = "gpio1 !! 2726 pinmux {
2843 function = "q !! 2727 pins = "gpio17", "gpio18";
>> 2728 function = "qup1";
>> 2729 };
2844 }; 2730 };
2845 2731
2846 qup_i2c2_default: qup !! 2732 qup_i2c2_default: qup-i2c2-default {
2847 pins = "gpio2 !! 2733 pinmux {
2848 function = "q !! 2734 pins = "gpio27", "gpio28";
>> 2735 function = "qup2";
>> 2736 };
2849 }; 2737 };
2850 2738
2851 qup_i2c3_default: qup !! 2739 qup_i2c3_default: qup-i2c3-default {
2852 pins = "gpio4 !! 2740 pinmux {
2853 function = "q !! 2741 pins = "gpio41", "gpio42";
>> 2742 function = "qup3";
>> 2743 };
2854 }; 2744 };
2855 2745
2856 qup_i2c4_default: qup !! 2746 qup_i2c4_default: qup-i2c4-default {
2857 pins = "gpio8 !! 2747 pinmux {
2858 function = "q !! 2748 pins = "gpio89", "gpio90";
>> 2749 function = "qup4";
>> 2750 };
2859 }; 2751 };
2860 2752
2861 qup_i2c5_default: qup !! 2753 qup_i2c5_default: qup-i2c5-default {
2862 pins = "gpio8 !! 2754 pinmux {
2863 function = "q !! 2755 pins = "gpio85", "gpio86";
>> 2756 function = "qup5";
>> 2757 };
2864 }; 2758 };
2865 2759
2866 qup_i2c6_default: qup !! 2760 qup_i2c6_default: qup-i2c6-default {
2867 pins = "gpio4 !! 2761 pinmux {
2868 function = "q !! 2762 pins = "gpio45", "gpio46";
>> 2763 function = "qup6";
>> 2764 };
2869 }; 2765 };
2870 2766
2871 qup_i2c7_default: qup !! 2767 qup_i2c7_default: qup-i2c7-default {
2872 pins = "gpio9 !! 2768 pinmux {
2873 function = "q !! 2769 pins = "gpio93", "gpio94";
>> 2770 function = "qup7";
>> 2771 };
2874 }; 2772 };
2875 2773
2876 qup_i2c8_default: qup !! 2774 qup_i2c8_default: qup-i2c8-default {
2877 pins = "gpio6 !! 2775 pinmux {
2878 function = "q !! 2776 pins = "gpio65", "gpio66";
>> 2777 function = "qup8";
>> 2778 };
2879 }; 2779 };
2880 2780
2881 qup_i2c9_default: qup !! 2781 qup_i2c9_default: qup-i2c9-default {
2882 pins = "gpio6 !! 2782 pinmux {
2883 function = "q !! 2783 pins = "gpio6", "gpio7";
>> 2784 function = "qup9";
>> 2785 };
2884 }; 2786 };
2885 2787
2886 qup_i2c10_default: qu !! 2788 qup_i2c10_default: qup-i2c10-default {
2887 pins = "gpio5 !! 2789 pinmux {
2888 function = "q !! 2790 pins = "gpio55", "gpio56";
>> 2791 function = "qup10";
>> 2792 };
2889 }; 2793 };
2890 2794
2891 qup_i2c11_default: qu !! 2795 qup_i2c11_default: qup-i2c11-default {
2892 pins = "gpio3 !! 2796 pinmux {
2893 function = "q !! 2797 pins = "gpio31", "gpio32";
>> 2798 function = "qup11";
>> 2799 };
2894 }; 2800 };
2895 2801
2896 qup_i2c12_default: qu !! 2802 qup_i2c12_default: qup-i2c12-default {
2897 pins = "gpio4 !! 2803 pinmux {
2898 function = "q !! 2804 pins = "gpio49", "gpio50";
>> 2805 function = "qup12";
>> 2806 };
2899 }; 2807 };
2900 2808
2901 qup_i2c13_default: qu !! 2809 qup_i2c13_default: qup-i2c13-default {
2902 pins = "gpio1 !! 2810 pinmux {
2903 function = "q !! 2811 pins = "gpio105", "gpio106";
>> 2812 function = "qup13";
>> 2813 };
2904 }; 2814 };
2905 2815
2906 qup_i2c14_default: qu !! 2816 qup_i2c14_default: qup-i2c14-default {
2907 pins = "gpio3 !! 2817 pinmux {
2908 function = "q !! 2818 pins = "gpio33", "gpio34";
>> 2819 function = "qup14";
>> 2820 };
2909 }; 2821 };
2910 2822
2911 qup_i2c15_default: qu !! 2823 qup_i2c15_default: qup-i2c15-default {
2912 pins = "gpio8 !! 2824 pinmux {
2913 function = "q !! 2825 pins = "gpio81", "gpio82";
>> 2826 function = "qup15";
>> 2827 };
2914 }; 2828 };
2915 2829
2916 qup_spi0_default: qup !! 2830 qup_spi0_default: qup-spi0-default {
2917 pins = "gpio0 !! 2831 pinmux {
2918 function = "q !! 2832 pins = "gpio0", "gpio1",
2919 }; !! 2833 "gpio2", "gpio3";
>> 2834 function = "qup0";
>> 2835 };
2920 2836
2921 qup_spi1_default: qup !! 2837 config {
2922 pins = "gpio1 !! 2838 pins = "gpio0", "gpio1",
2923 function = "q !! 2839 "gpio2", "gpio3";
>> 2840 drive-strength = <6>;
>> 2841 bias-disable;
>> 2842 };
2924 }; 2843 };
2925 2844
2926 qup_spi2_default: qup !! 2845 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2846 pinmux {
2928 function = "q !! 2847 pins = "gpio17", "gpio18",
>> 2848 "gpio19", "gpio20";
>> 2849 function = "qup1";
>> 2850 };
2929 }; 2851 };
2930 2852
2931 qup_spi3_default: qup !! 2853 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2854 pinmux {
2933 function = "q !! 2855 pins = "gpio27", "gpio28",
>> 2856 "gpio29", "gpio30";
>> 2857 function = "qup2";
>> 2858 };
2934 }; 2859 };
2935 2860
2936 qup_spi4_default: qup !! 2861 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2862 pinmux {
2938 function = "q !! 2863 pins = "gpio41", "gpio42",
>> 2864 "gpio43", "gpio44";
>> 2865 function = "qup3";
>> 2866 };
2939 }; 2867 };
2940 2868
2941 qup_spi5_default: qup !! 2869 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2870 pinmux {
2943 function = "q !! 2871 pins = "gpio89", "gpio90",
>> 2872 "gpio91", "gpio92";
>> 2873 function = "qup4";
>> 2874 };
2944 }; 2875 };
2945 2876
2946 qup_spi6_default: qup !! 2877 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2878 pinmux {
2948 function = "q !! 2879 pins = "gpio85", "gpio86",
>> 2880 "gpio87", "gpio88";
>> 2881 function = "qup5";
>> 2882 };
2949 }; 2883 };
2950 2884
2951 qup_spi7_default: qup !! 2885 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2886 pinmux {
2953 function = "q !! 2887 pins = "gpio45", "gpio46",
>> 2888 "gpio47", "gpio48";
>> 2889 function = "qup6";
>> 2890 };
2954 }; 2891 };
2955 2892
2956 qup_spi8_default: qup !! 2893 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2894 pinmux {
2958 function = "q !! 2895 pins = "gpio93", "gpio94",
>> 2896 "gpio95", "gpio96";
>> 2897 function = "qup7";
>> 2898 };
2959 }; 2899 };
2960 2900
2961 qup_spi9_default: qup !! 2901 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2902 pinmux {
2963 function = "q !! 2903 pins = "gpio65", "gpio66",
>> 2904 "gpio67", "gpio68";
>> 2905 function = "qup8";
>> 2906 };
2964 }; 2907 };
2965 2908
2966 qup_spi10_default: qu !! 2909 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2910 pinmux {
2968 function = "q !! 2911 pins = "gpio6", "gpio7",
>> 2912 "gpio4", "gpio5";
>> 2913 function = "qup9";
>> 2914 };
2969 }; 2915 };
2970 2916
2971 qup_spi11_default: qu !! 2917 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2918 pinmux {
2973 function = "q !! 2919 pins = "gpio55", "gpio56",
>> 2920 "gpio53", "gpio54";
>> 2921 function = "qup10";
>> 2922 };
2974 }; 2923 };
2975 2924
2976 qup_spi12_default: qu !! 2925 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2926 pinmux {
2978 function = "q !! 2927 pins = "gpio31", "gpio32",
>> 2928 "gpio33", "gpio34";
>> 2929 function = "qup11";
>> 2930 };
2979 }; 2931 };
2980 2932
2981 qup_spi13_default: qu !! 2933 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2934 pinmux {
2983 function = "q !! 2935 pins = "gpio49", "gpio50",
>> 2936 "gpio51", "gpio52";
>> 2937 function = "qup12";
>> 2938 };
2984 }; 2939 };
2985 2940
2986 qup_spi14_default: qu !! 2941 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2942 pinmux {
2988 function = "q !! 2943 pins = "gpio105", "gpio106",
>> 2944 "gpio107", "gpio108";
>> 2945 function = "qup13";
>> 2946 };
2989 }; 2947 };
2990 2948
2991 qup_spi15_default: qu !! 2949 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2950 pinmux {
2993 function = "q !! 2951 pins = "gpio33", "gpio34",
>> 2952 "gpio31", "gpio32";
>> 2953 function = "qup14";
>> 2954 };
2994 }; 2955 };
2995 2956
2996 qup_uart0_default: qu !! 2957 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2958 pinmux {
2998 pins !! 2959 pins = "gpio81", "gpio82",
2999 funct !! 2960 "gpio83", "gpio84";
>> 2961 function = "qup15";
3000 }; 2962 };
>> 2963 };
3001 2964
3002 qup_uart0_rx: !! 2965 qup_uart0_default: qup-uart0-default {
3003 pins !! 2966 pinmux {
>> 2967 pins = "gpio2", "gpio3";
3004 funct 2968 function = "qup0";
3005 }; 2969 };
3006 }; 2970 };
3007 2971
3008 qup_uart1_default: qu !! 2972 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2973 pinmux {
3010 pins !! 2974 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2975 function = "qup1";
3017 }; 2976 };
3018 }; 2977 };
3019 2978
3020 qup_uart2_default: qu !! 2979 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2980 pinmux {
3022 pins !! 2981 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2982 function = "qup2";
3029 }; 2983 };
3030 }; 2984 };
3031 2985
3032 qup_uart3_default: qu !! 2986 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2987 pinmux {
3034 pins !! 2988 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct 2989 function = "qup3";
3041 }; 2990 };
3042 }; 2991 };
3043 2992
3044 qup_uart3_4pin: qup-u !! 2993 qup_uart4_default: qup-uart4-default {
3045 qup_uart3_4pi !! 2994 pinmux {
3046 pins !! 2995 pins = "gpio91", "gpio92";
3047 funct !! 2996 function = "qup4";
3048 }; 2997 };
>> 2998 };
3049 2999
3050 qup_uart3_4pi !! 3000 qup_uart5_default: qup-uart5-default {
3051 pins !! 3001 pinmux {
3052 funct !! 3002 pins = "gpio87", "gpio88";
>> 3003 function = "qup5";
3053 }; 3004 };
>> 3005 };
3054 3006
3055 qup_uart3_4pi !! 3007 qup_uart6_default: qup-uart6-default {
3056 pins !! 3008 pinmux {
3057 funct !! 3009 pins = "gpio47", "gpio48";
>> 3010 function = "qup6";
3058 }; 3011 };
3059 }; 3012 };
3060 3013
3061 qup_uart4_default: qu !! 3014 qup_uart7_default: qup-uart7-default {
3062 qup_uart4_tx: !! 3015 pinmux {
3063 pins !! 3016 pins = "gpio95", "gpio96";
3064 funct !! 3017 function = "qup7";
3065 }; 3018 };
>> 3019 };
3066 3020
3067 qup_uart4_rx: !! 3021 qup_uart8_default: qup-uart8-default {
3068 pins !! 3022 pinmux {
3069 funct !! 3023 pins = "gpio67", "gpio68";
>> 3024 function = "qup8";
3070 }; 3025 };
3071 }; 3026 };
3072 3027
3073 qup_uart5_default: qu !! 3028 qup_uart9_default: qup-uart9-default {
3074 qup_uart5_tx: !! 3029 pinmux {
3075 pins !! 3030 pins = "gpio4", "gpio5";
3076 funct !! 3031 function = "qup9";
3077 }; 3032 };
>> 3033 };
3078 3034
3079 qup_uart5_rx: !! 3035 qup_uart10_default: qup-uart10-default {
3080 pins !! 3036 pinmux {
3081 funct !! 3037 pins = "gpio53", "gpio54";
>> 3038 function = "qup10";
3082 }; 3039 };
3083 }; 3040 };
3084 3041
3085 qup_uart6_default: qu !! 3042 qup_uart11_default: qup-uart11-default {
3086 qup_uart6_tx: !! 3043 pinmux {
3087 pins !! 3044 pins = "gpio33", "gpio34";
3088 funct !! 3045 function = "qup11";
3089 }; 3046 };
>> 3047 };
3090 3048
3091 qup_uart6_rx: !! 3049 qup_uart12_default: qup-uart12-default {
3092 pins !! 3050 pinmux {
3093 funct !! 3051 pins = "gpio51", "gpio52";
>> 3052 function = "qup12";
3094 }; 3053 };
3095 }; 3054 };
3096 3055
3097 qup_uart6_4pin: qup-u !! 3056 qup_uart13_default: qup-uart13-default {
3098 qup_uart6_4pi !! 3057 pinmux {
3099 pins !! 3058 pins = "gpio107", "gpio108";
3100 funct !! 3059 function = "qup13";
3101 bias- <<
3102 }; 3060 };
>> 3061 };
3103 3062
3104 qup_uart6_4pi !! 3063 qup_uart14_default: qup-uart14-default {
3105 pins !! 3064 pinmux {
3106 funct !! 3065 pins = "gpio31", "gpio32";
3107 drive !! 3066 function = "qup14";
3108 bias- <<
3109 }; 3067 };
>> 3068 };
3110 3069
3111 qup_uart6_4pi !! 3070 qup_uart15_default: qup-uart15-default {
3112 pins !! 3071 pinmux {
3113 funct !! 3072 pins = "gpio83", "gpio84";
3114 bias- !! 3073 function = "qup15";
3115 }; 3074 };
3116 }; 3075 };
3117 3076
3118 qup_uart7_default: qu !! 3077 quat_mi2s_sleep: quat_mi2s_sleep {
3119 qup_uart7_tx: !! 3078 mux {
3120 pins !! 3079 pins = "gpio58", "gpio59";
3121 funct !! 3080 function = "gpio";
3122 }; 3081 };
3123 3082
3124 qup_uart7_rx: !! 3083 config {
3125 pins !! 3084 pins = "gpio58", "gpio59";
3126 funct !! 3085 drive-strength = <2>;
>> 3086 bias-pull-down;
>> 3087 input-enable;
3127 }; 3088 };
3128 }; 3089 };
3129 3090
3130 qup_uart8_default: qu !! 3091 quat_mi2s_active: quat_mi2s_active {
3131 qup_uart8_tx: !! 3092 mux {
3132 pins !! 3093 pins = "gpio58", "gpio59";
3133 funct !! 3094 function = "qua_mi2s";
3134 }; 3095 };
3135 3096
3136 qup_uart8_rx: !! 3097 config {
3137 pins !! 3098 pins = "gpio58", "gpio59";
3138 funct !! 3099 drive-strength = <8>;
>> 3100 bias-disable;
>> 3101 output-high;
3139 }; 3102 };
3140 }; 3103 };
3141 3104
3142 qup_uart9_default: qu !! 3105 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3143 qup_uart9_tx: !! 3106 mux {
3144 pins !! 3107 pins = "gpio60";
3145 funct !! 3108 function = "gpio";
3146 }; 3109 };
3147 3110
3148 qup_uart9_rx: !! 3111 config {
3149 pins !! 3112 pins = "gpio60";
3150 funct !! 3113 drive-strength = <2>;
>> 3114 bias-pull-down;
>> 3115 input-enable;
3151 }; 3116 };
3152 }; 3117 };
3153 3118
3154 qup_uart10_default: q !! 3119 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3155 qup_uart10_tx !! 3120 mux {
3156 pins !! 3121 pins = "gpio60";
3157 funct !! 3122 function = "qua_mi2s";
3158 }; 3123 };
3159 3124
3160 qup_uart10_rx !! 3125 config {
3161 pins !! 3126 pins = "gpio60";
3162 funct !! 3127 drive-strength = <8>;
>> 3128 bias-disable;
3163 }; 3129 };
3164 }; 3130 };
3165 3131
3166 qup_uart11_default: q !! 3132 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3167 qup_uart11_tx !! 3133 mux {
3168 pins !! 3134 pins = "gpio61";
3169 funct !! 3135 function = "gpio";
3170 }; 3136 };
3171 3137
3172 qup_uart11_rx !! 3138 config {
3173 pins !! 3139 pins = "gpio61";
3174 funct !! 3140 drive-strength = <2>;
>> 3141 bias-pull-down;
>> 3142 input-enable;
3175 }; 3143 };
3176 }; 3144 };
3177 3145
3178 qup_uart12_default: q !! 3146 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3179 qup_uart12_tx !! 3147 mux {
3180 pins !! 3148 pins = "gpio61";
3181 funct !! 3149 function = "qua_mi2s";
3182 }; 3150 };
3183 3151
3184 qup_uart12_rx !! 3152 config {
3185 pins !! 3153 pins = "gpio61";
3186 funct !! 3154 drive-strength = <8>;
>> 3155 bias-disable;
3187 }; 3156 };
3188 }; 3157 };
3189 3158
3190 qup_uart13_default: q !! 3159 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3191 qup_uart13_tx !! 3160 mux {
3192 pins !! 3161 pins = "gpio62";
3193 funct !! 3162 function = "gpio";
3194 }; 3163 };
3195 3164
3196 qup_uart13_rx !! 3165 config {
3197 pins !! 3166 pins = "gpio62";
3198 funct !! 3167 drive-strength = <2>;
>> 3168 bias-pull-down;
>> 3169 input-enable;
3199 }; 3170 };
3200 }; 3171 };
3201 3172
3202 qup_uart14_default: q !! 3173 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3203 qup_uart14_tx !! 3174 mux {
3204 pins !! 3175 pins = "gpio62";
3205 funct !! 3176 function = "qua_mi2s";
3206 }; 3177 };
3207 3178
3208 qup_uart14_rx !! 3179 config {
3209 pins !! 3180 pins = "gpio62";
3210 funct !! 3181 drive-strength = <8>;
>> 3182 bias-disable;
3211 }; 3183 };
3212 }; 3184 };
3213 3185
3214 qup_uart15_default: q !! 3186 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3215 qup_uart15_tx !! 3187 mux {
3216 pins !! 3188 pins = "gpio63";
3217 funct !! 3189 function = "gpio";
3218 }; 3190 };
3219 3191
3220 qup_uart15_rx !! 3192 config {
3221 pins !! 3193 pins = "gpio63";
3222 funct !! 3194 drive-strength = <2>;
>> 3195 bias-pull-down;
>> 3196 input-enable;
3223 }; 3197 };
3224 }; 3198 };
3225 3199
3226 quat_mi2s_sleep: quat !! 3200 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3227 pins = "gpio5 !! 3201 mux {
3228 function = "g !! 3202 pins = "gpio63";
3229 drive-strengt !! 3203 function = "qua_mi2s";
3230 bias-pull-dow !! 3204 };
3231 }; <<
3232 <<
3233 quat_mi2s_active: qua <<
3234 pins = "gpio5 <<
3235 function = "q <<
3236 drive-strengt <<
3237 bias-disable; <<
3238 output-high; <<
3239 }; <<
3240 <<
3241 quat_mi2s_sd0_sleep: <<
3242 pins = "gpio6 <<
3243 function = "g <<
3244 drive-strengt <<
3245 bias-pull-dow <<
3246 }; <<
3247 <<
3248 quat_mi2s_sd0_active: <<
3249 pins = "gpio6 <<
3250 function = "q <<
3251 drive-strengt <<
3252 bias-disable; <<
3253 }; <<
3254 <<
3255 quat_mi2s_sd1_sleep: <<
3256 pins = "gpio6 <<
3257 function = "g <<
3258 drive-strengt <<
3259 bias-pull-dow <<
3260 }; <<
3261 <<
3262 quat_mi2s_sd1_active: <<
3263 pins = "gpio6 <<
3264 function = "q <<
3265 drive-strengt <<
3266 bias-disable; <<
3267 }; <<
3268 <<
3269 quat_mi2s_sd2_sleep: <<
3270 pins = "gpio6 <<
3271 function = "g <<
3272 drive-strengt <<
3273 bias-pull-dow <<
3274 }; <<
3275 <<
3276 quat_mi2s_sd2_active: <<
3277 pins = "gpio6 <<
3278 function = "q <<
3279 drive-strengt <<
3280 bias-disable; <<
3281 }; <<
3282 <<
3283 quat_mi2s_sd3_sleep: <<
3284 pins = "gpio6 <<
3285 function = "g <<
3286 drive-strengt <<
3287 bias-pull-dow <<
3288 }; <<
3289 3205
3290 quat_mi2s_sd3_active: !! 3206 config {
3291 pins = "gpio6 !! 3207 pins = "gpio63";
3292 function = "q !! 3208 drive-strength = <8>;
3293 drive-strengt !! 3209 bias-disable;
3294 bias-disable; !! 3210 };
3295 }; 3211 };
3296 }; 3212 };
3297 3213
3298 mss_pil: remoteproc@4080000 { 3214 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 3215 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 3216 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 3217 reg-names = "qdsp6", "rmb";
3302 3218
3303 interrupts-extended = 3219 interrupts-extended =
3304 <&intc GIC_SP 3220 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 3221 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 3222 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 3223 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 3224 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 3225 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 3226 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 3227 "handover", "stop-ack",
3312 "sh 3228 "shutdown-ack";
3313 3229
3314 clocks = <&gcc GCC_MS 3230 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 3231 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 3232 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 3233 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 3234 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 3235 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 3236 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 3237 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 3238 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 3239 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 3240
3325 qcom,qmp = <&aoss_qmp 3241 qcom,qmp = <&aoss_qmp>;
3326 3242
3327 qcom,smem-states = <& 3243 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 3244 qcom,smem-state-names = "stop";
3329 3245
3330 resets = <&aoss_reset 3246 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 3247 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 3248 reset-names = "mss_restart", "pdc_reset";
3333 3249
3334 qcom,halt-regs = <&tc 3250 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3335 3251
3336 power-domains = <&rpm 3252 power-domains = <&rpmhpd SDM845_CX>,
3337 <&rpm 3253 <&rpmhpd SDM845_MX>,
3338 <&rpm 3254 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = 3255 power-domain-names = "cx", "mx", "mss";
3340 3256
3341 status = "disabled"; 3257 status = "disabled";
3342 3258
3343 mba { 3259 mba {
3344 memory-region 3260 memory-region = <&mba_region>;
3345 }; 3261 };
3346 3262
3347 mpss { 3263 mpss {
3348 memory-region 3264 memory-region = <&mpss_region>;
3349 }; 3265 };
3350 3266
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 3267 glink-edge {
3356 interrupts = 3268 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3269 label = "modem";
3358 qcom,remote-p 3270 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3271 mboxes = <&apss_shared 12>;
3360 }; 3272 };
3361 }; 3273 };
3362 3274
3363 gpucc: clock-controller@50900 3275 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3276 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3277 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3278 #clock-cells = <1>;
3367 #reset-cells = <1>; 3279 #reset-cells = <1>;
3368 #power-domain-cells = 3280 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3281 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3282 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3283 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3284 clock-names = "bi_tcxo",
3373 "gcc_gp 3285 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3286 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3287 };
3376 3288
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 3289 stm@6002000 {
3431 compatible = "arm,cor 3290 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3291 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3292 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3293 reg-names = "stm-base", "stm-stimulus-base";
3435 3294
3436 clocks = <&aoss_qmp>; 3295 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3296 clock-names = "apb_pclk";
3438 3297
3439 out-ports { 3298 out-ports {
3440 port { 3299 port {
3441 stm_o 3300 stm_out: endpoint {
3442 3301 remote-endpoint =
3443 3302 <&funnel0_in7>;
3444 }; 3303 };
3445 }; 3304 };
3446 }; 3305 };
3447 }; 3306 };
3448 3307
3449 funnel@6041000 { 3308 funnel@6041000 {
3450 compatible = "arm,cor 3309 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3310 reg = <0 0x06041000 0 0x1000>;
3452 3311
3453 clocks = <&aoss_qmp>; 3312 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3313 clock-names = "apb_pclk";
3455 3314
3456 out-ports { 3315 out-ports {
3457 port { 3316 port {
3458 funne 3317 funnel0_out: endpoint {
3459 3318 remote-endpoint =
3460 3319 <&merge_funnel_in0>;
3461 }; 3320 };
3462 }; 3321 };
3463 }; 3322 };
3464 3323
3465 in-ports { 3324 in-ports {
3466 #address-cell 3325 #address-cells = <1>;
3467 #size-cells = 3326 #size-cells = <0>;
3468 3327
3469 port@7 { 3328 port@7 {
3470 reg = 3329 reg = <7>;
3471 funne 3330 funnel0_in7: endpoint {
3472 3331 remote-endpoint = <&stm_out>;
3473 }; 3332 };
3474 }; 3333 };
3475 }; 3334 };
3476 }; 3335 };
3477 3336
3478 funnel@6043000 { 3337 funnel@6043000 {
3479 compatible = "arm,cor 3338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3339 reg = <0 0x06043000 0 0x1000>;
3481 3340
3482 clocks = <&aoss_qmp>; 3341 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3342 clock-names = "apb_pclk";
3484 3343
3485 out-ports { 3344 out-ports {
3486 port { 3345 port {
3487 funne 3346 funnel2_out: endpoint {
3488 3347 remote-endpoint =
3489 3348 <&merge_funnel_in2>;
3490 }; 3349 };
3491 }; 3350 };
3492 }; 3351 };
3493 3352
3494 in-ports { 3353 in-ports {
3495 #address-cell 3354 #address-cells = <1>;
3496 #size-cells = 3355 #size-cells = <0>;
3497 3356
3498 port@5 { 3357 port@5 {
3499 reg = 3358 reg = <5>;
3500 funne 3359 funnel2_in5: endpoint {
3501 3360 remote-endpoint =
3502 3361 <&apss_merge_funnel_out>;
3503 }; 3362 };
3504 }; 3363 };
3505 }; 3364 };
3506 }; 3365 };
3507 3366
3508 funnel@6045000 { 3367 funnel@6045000 {
3509 compatible = "arm,cor 3368 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3369 reg = <0 0x06045000 0 0x1000>;
3511 3370
3512 clocks = <&aoss_qmp>; 3371 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3372 clock-names = "apb_pclk";
3514 3373
3515 out-ports { 3374 out-ports {
3516 port { 3375 port {
3517 merge 3376 merge_funnel_out: endpoint {
3518 3377 remote-endpoint = <&etf_in>;
3519 }; 3378 };
3520 }; 3379 };
3521 }; 3380 };
3522 3381
3523 in-ports { 3382 in-ports {
3524 #address-cell 3383 #address-cells = <1>;
3525 #size-cells = 3384 #size-cells = <0>;
3526 3385
3527 port@0 { 3386 port@0 {
3528 reg = 3387 reg = <0>;
3529 merge 3388 merge_funnel_in0: endpoint {
3530 3389 remote-endpoint =
3531 3390 <&funnel0_out>;
3532 }; 3391 };
3533 }; 3392 };
3534 3393
3535 port@2 { 3394 port@2 {
3536 reg = 3395 reg = <2>;
3537 merge 3396 merge_funnel_in2: endpoint {
3538 3397 remote-endpoint =
3539 3398 <&funnel2_out>;
3540 }; 3399 };
3541 }; 3400 };
3542 }; 3401 };
3543 }; 3402 };
3544 3403
3545 replicator@6046000 { 3404 replicator@6046000 {
3546 compatible = "arm,cor 3405 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3406 reg = <0 0x06046000 0 0x1000>;
3548 3407
3549 clocks = <&aoss_qmp>; 3408 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3409 clock-names = "apb_pclk";
3551 3410
3552 out-ports { 3411 out-ports {
3553 port { 3412 port {
3554 repli 3413 replicator_out: endpoint {
3555 3414 remote-endpoint = <&etr_in>;
3556 }; 3415 };
3557 }; 3416 };
3558 }; 3417 };
3559 3418
3560 in-ports { 3419 in-ports {
3561 port { 3420 port {
3562 repli 3421 replicator_in: endpoint {
3563 3422 remote-endpoint = <&etf_out>;
3564 }; 3423 };
3565 }; 3424 };
3566 }; 3425 };
3567 }; 3426 };
3568 3427
3569 etf@6047000 { 3428 etf@6047000 {
3570 compatible = "arm,cor 3429 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3430 reg = <0 0x06047000 0 0x1000>;
3572 3431
3573 clocks = <&aoss_qmp>; 3432 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3433 clock-names = "apb_pclk";
3575 3434
3576 out-ports { 3435 out-ports {
3577 port { 3436 port {
3578 etf_o 3437 etf_out: endpoint {
3579 3438 remote-endpoint =
3580 3439 <&replicator_in>;
3581 }; 3440 };
3582 }; 3441 };
3583 }; 3442 };
3584 3443
3585 in-ports { 3444 in-ports {
>> 3445 #address-cells = <1>;
>> 3446 #size-cells = <0>;
3586 3447
3587 port { !! 3448 port@1 {
>> 3449 reg = <1>;
3588 etf_i 3450 etf_in: endpoint {
3589 3451 remote-endpoint =
3590 3452 <&merge_funnel_out>;
3591 }; 3453 };
3592 }; 3454 };
3593 }; 3455 };
3594 }; 3456 };
3595 3457
3596 etr@6048000 { 3458 etr@6048000 {
3597 compatible = "arm,cor 3459 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3460 reg = <0 0x06048000 0 0x1000>;
3599 3461
3600 clocks = <&aoss_qmp>; 3462 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3463 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3464 arm,scatter-gather;
3603 3465
3604 in-ports { 3466 in-ports {
3605 port { 3467 port {
3606 etr_i 3468 etr_in: endpoint {
3607 3469 remote-endpoint =
3608 3470 <&replicator_out>;
3609 }; 3471 };
3610 }; 3472 };
3611 }; 3473 };
3612 }; 3474 };
3613 3475
3614 etm@7040000 { 3476 etm@7040000 {
3615 compatible = "arm,cor 3477 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3478 reg = <0 0x07040000 0 0x1000>;
3617 3479
3618 cpu = <&CPU0>; 3480 cpu = <&CPU0>;
3619 3481
3620 clocks = <&aoss_qmp>; 3482 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3483 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3484 arm,coresight-loses-context-with-cpu;
3623 3485
3624 out-ports { 3486 out-ports {
3625 port { 3487 port {
3626 etm0_ 3488 etm0_out: endpoint {
3627 3489 remote-endpoint =
3628 3490 <&apss_funnel_in0>;
3629 }; 3491 };
3630 }; 3492 };
3631 }; 3493 };
3632 }; 3494 };
3633 3495
3634 etm@7140000 { 3496 etm@7140000 {
3635 compatible = "arm,cor 3497 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3498 reg = <0 0x07140000 0 0x1000>;
3637 3499
3638 cpu = <&CPU1>; 3500 cpu = <&CPU1>;
3639 3501
3640 clocks = <&aoss_qmp>; 3502 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3503 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3504 arm,coresight-loses-context-with-cpu;
3643 3505
3644 out-ports { 3506 out-ports {
3645 port { 3507 port {
3646 etm1_ 3508 etm1_out: endpoint {
3647 3509 remote-endpoint =
3648 3510 <&apss_funnel_in1>;
3649 }; 3511 };
3650 }; 3512 };
3651 }; 3513 };
3652 }; 3514 };
3653 3515
3654 etm@7240000 { 3516 etm@7240000 {
3655 compatible = "arm,cor 3517 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3518 reg = <0 0x07240000 0 0x1000>;
3657 3519
3658 cpu = <&CPU2>; 3520 cpu = <&CPU2>;
3659 3521
3660 clocks = <&aoss_qmp>; 3522 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3523 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3524 arm,coresight-loses-context-with-cpu;
3663 3525
3664 out-ports { 3526 out-ports {
3665 port { 3527 port {
3666 etm2_ 3528 etm2_out: endpoint {
3667 3529 remote-endpoint =
3668 3530 <&apss_funnel_in2>;
3669 }; 3531 };
3670 }; 3532 };
3671 }; 3533 };
3672 }; 3534 };
3673 3535
3674 etm@7340000 { 3536 etm@7340000 {
3675 compatible = "arm,cor 3537 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3538 reg = <0 0x07340000 0 0x1000>;
3677 3539
3678 cpu = <&CPU3>; 3540 cpu = <&CPU3>;
3679 3541
3680 clocks = <&aoss_qmp>; 3542 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3543 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3544 arm,coresight-loses-context-with-cpu;
3683 3545
3684 out-ports { 3546 out-ports {
3685 port { 3547 port {
3686 etm3_ 3548 etm3_out: endpoint {
3687 3549 remote-endpoint =
3688 3550 <&apss_funnel_in3>;
3689 }; 3551 };
3690 }; 3552 };
3691 }; 3553 };
3692 }; 3554 };
3693 3555
3694 etm@7440000 { 3556 etm@7440000 {
3695 compatible = "arm,cor 3557 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3558 reg = <0 0x07440000 0 0x1000>;
3697 3559
3698 cpu = <&CPU4>; 3560 cpu = <&CPU4>;
3699 3561
3700 clocks = <&aoss_qmp>; 3562 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3563 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3564 arm,coresight-loses-context-with-cpu;
3703 3565
3704 out-ports { 3566 out-ports {
3705 port { 3567 port {
3706 etm4_ 3568 etm4_out: endpoint {
3707 3569 remote-endpoint =
3708 3570 <&apss_funnel_in4>;
3709 }; 3571 };
3710 }; 3572 };
3711 }; 3573 };
3712 }; 3574 };
3713 3575
3714 etm@7540000 { 3576 etm@7540000 {
3715 compatible = "arm,cor 3577 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3578 reg = <0 0x07540000 0 0x1000>;
3717 3579
3718 cpu = <&CPU5>; 3580 cpu = <&CPU5>;
3719 3581
3720 clocks = <&aoss_qmp>; 3582 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3583 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3584 arm,coresight-loses-context-with-cpu;
3723 3585
3724 out-ports { 3586 out-ports {
3725 port { 3587 port {
3726 etm5_ 3588 etm5_out: endpoint {
3727 3589 remote-endpoint =
3728 3590 <&apss_funnel_in5>;
3729 }; 3591 };
3730 }; 3592 };
3731 }; 3593 };
3732 }; 3594 };
3733 3595
3734 etm@7640000 { 3596 etm@7640000 {
3735 compatible = "arm,cor 3597 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3598 reg = <0 0x07640000 0 0x1000>;
3737 3599
3738 cpu = <&CPU6>; 3600 cpu = <&CPU6>;
3739 3601
3740 clocks = <&aoss_qmp>; 3602 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3603 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3604 arm,coresight-loses-context-with-cpu;
3743 3605
3744 out-ports { 3606 out-ports {
3745 port { 3607 port {
3746 etm6_ 3608 etm6_out: endpoint {
3747 3609 remote-endpoint =
3748 3610 <&apss_funnel_in6>;
3749 }; 3611 };
3750 }; 3612 };
3751 }; 3613 };
3752 }; 3614 };
3753 3615
3754 etm@7740000 { 3616 etm@7740000 {
3755 compatible = "arm,cor 3617 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3618 reg = <0 0x07740000 0 0x1000>;
3757 3619
3758 cpu = <&CPU7>; 3620 cpu = <&CPU7>;
3759 3621
3760 clocks = <&aoss_qmp>; 3622 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3623 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3624 arm,coresight-loses-context-with-cpu;
3763 3625
3764 out-ports { 3626 out-ports {
3765 port { 3627 port {
3766 etm7_ 3628 etm7_out: endpoint {
3767 3629 remote-endpoint =
3768 3630 <&apss_funnel_in7>;
3769 }; 3631 };
3770 }; 3632 };
3771 }; 3633 };
3772 }; 3634 };
3773 3635
3774 funnel@7800000 { /* APSS Funn 3636 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3637 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3638 reg = <0 0x07800000 0 0x1000>;
3777 3639
3778 clocks = <&aoss_qmp>; 3640 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3641 clock-names = "apb_pclk";
3780 3642
3781 out-ports { 3643 out-ports {
3782 port { 3644 port {
3783 apss_ 3645 apss_funnel_out: endpoint {
3784 3646 remote-endpoint =
3785 3647 <&apss_merge_funnel_in>;
3786 }; 3648 };
3787 }; 3649 };
3788 }; 3650 };
3789 3651
3790 in-ports { 3652 in-ports {
3791 #address-cell 3653 #address-cells = <1>;
3792 #size-cells = 3654 #size-cells = <0>;
3793 3655
3794 port@0 { 3656 port@0 {
3795 reg = 3657 reg = <0>;
3796 apss_ 3658 apss_funnel_in0: endpoint {
3797 3659 remote-endpoint =
3798 3660 <&etm0_out>;
3799 }; 3661 };
3800 }; 3662 };
3801 3663
3802 port@1 { 3664 port@1 {
3803 reg = 3665 reg = <1>;
3804 apss_ 3666 apss_funnel_in1: endpoint {
3805 3667 remote-endpoint =
3806 3668 <&etm1_out>;
3807 }; 3669 };
3808 }; 3670 };
3809 3671
3810 port@2 { 3672 port@2 {
3811 reg = 3673 reg = <2>;
3812 apss_ 3674 apss_funnel_in2: endpoint {
3813 3675 remote-endpoint =
3814 3676 <&etm2_out>;
3815 }; 3677 };
3816 }; 3678 };
3817 3679
3818 port@3 { 3680 port@3 {
3819 reg = 3681 reg = <3>;
3820 apss_ 3682 apss_funnel_in3: endpoint {
3821 3683 remote-endpoint =
3822 3684 <&etm3_out>;
3823 }; 3685 };
3824 }; 3686 };
3825 3687
3826 port@4 { 3688 port@4 {
3827 reg = 3689 reg = <4>;
3828 apss_ 3690 apss_funnel_in4: endpoint {
3829 3691 remote-endpoint =
3830 3692 <&etm4_out>;
3831 }; 3693 };
3832 }; 3694 };
3833 3695
3834 port@5 { 3696 port@5 {
3835 reg = 3697 reg = <5>;
3836 apss_ 3698 apss_funnel_in5: endpoint {
3837 3699 remote-endpoint =
3838 3700 <&etm5_out>;
3839 }; 3701 };
3840 }; 3702 };
3841 3703
3842 port@6 { 3704 port@6 {
3843 reg = 3705 reg = <6>;
3844 apss_ 3706 apss_funnel_in6: endpoint {
3845 3707 remote-endpoint =
3846 3708 <&etm6_out>;
3847 }; 3709 };
3848 }; 3710 };
3849 3711
3850 port@7 { 3712 port@7 {
3851 reg = 3713 reg = <7>;
3852 apss_ 3714 apss_funnel_in7: endpoint {
3853 3715 remote-endpoint =
3854 3716 <&etm7_out>;
3855 }; 3717 };
3856 }; 3718 };
3857 }; 3719 };
3858 }; 3720 };
3859 3721
3860 funnel@7810000 { 3722 funnel@7810000 {
3861 compatible = "arm,cor 3723 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3724 reg = <0 0x07810000 0 0x1000>;
3863 3725
3864 clocks = <&aoss_qmp>; 3726 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3727 clock-names = "apb_pclk";
3866 3728
3867 out-ports { 3729 out-ports {
3868 port { 3730 port {
3869 apss_ 3731 apss_merge_funnel_out: endpoint {
3870 3732 remote-endpoint =
3871 3733 <&funnel2_in5>;
3872 }; 3734 };
3873 }; 3735 };
3874 }; 3736 };
3875 3737
3876 in-ports { 3738 in-ports {
3877 port { 3739 port {
3878 apss_ 3740 apss_merge_funnel_in: endpoint {
3879 3741 remote-endpoint =
3880 3742 <&apss_funnel_out>;
3881 }; 3743 };
3882 }; 3744 };
3883 }; 3745 };
3884 }; 3746 };
3885 3747
3886 sdhc_2: mmc@8804000 { 3748 sdhc_2: mmc@8804000 {
3887 compatible = "qcom,sd 3749 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3750 reg = <0 0x08804000 0 0x1000>;
3889 3751
3890 interrupts = <GIC_SPI 3752 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3753 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3754 interrupt-names = "hc_irq", "pwr_irq";
3893 3755
3894 clocks = <&gcc GCC_SD 3756 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD 3757 <&gcc GCC_SDCC2_APPS_CLK>,
3896 <&rpmhcc RPM 3758 <&rpmhcc RPMH_CXO_CLK>;
3897 clock-names = "iface" 3759 clock-names = "iface", "core", "xo";
3898 iommus = <&apps_smmu 3760 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3761 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3762 operating-points-v2 = <&sdhc2_opp_table>;
3901 3763
3902 status = "disabled"; 3764 status = "disabled";
3903 3765
3904 sdhc2_opp_table: opp- 3766 sdhc2_opp_table: opp-table {
3905 compatible = 3767 compatible = "operating-points-v2";
3906 3768
3907 opp-9600000 { 3769 opp-9600000 {
3908 opp-h 3770 opp-hz = /bits/ 64 <9600000>;
3909 requi 3771 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3772 };
3911 3773
3912 opp-19200000 3774 opp-19200000 {
3913 opp-h 3775 opp-hz = /bits/ 64 <19200000>;
3914 requi 3776 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3777 };
3916 3778
3917 opp-100000000 3779 opp-100000000 {
3918 opp-h 3780 opp-hz = /bits/ 64 <100000000>;
3919 requi 3781 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3782 };
3921 3783
3922 opp-201500000 3784 opp-201500000 {
3923 opp-h 3785 opp-hz = /bits/ 64 <201500000>;
3924 requi 3786 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3787 };
3926 }; 3788 };
3927 }; 3789 };
3928 3790
>> 3791 qspi_opp_table: opp-table-qspi {
>> 3792 compatible = "operating-points-v2";
>> 3793
>> 3794 opp-19200000 {
>> 3795 opp-hz = /bits/ 64 <19200000>;
>> 3796 required-opps = <&rpmhpd_opp_min_svs>;
>> 3797 };
>> 3798
>> 3799 opp-100000000 {
>> 3800 opp-hz = /bits/ 64 <100000000>;
>> 3801 required-opps = <&rpmhpd_opp_low_svs>;
>> 3802 };
>> 3803
>> 3804 opp-150000000 {
>> 3805 opp-hz = /bits/ 64 <150000000>;
>> 3806 required-opps = <&rpmhpd_opp_svs>;
>> 3807 };
>> 3808
>> 3809 opp-300000000 {
>> 3810 opp-hz = /bits/ 64 <300000000>;
>> 3811 required-opps = <&rpmhpd_opp_nom>;
>> 3812 };
>> 3813 };
>> 3814
3929 qspi: spi@88df000 { 3815 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3816 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3817 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3818 #address-cells = <1>;
3934 #size-cells = <0>; 3819 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3820 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3821 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3822 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3823 clock-names = "iface", "core";
3939 power-domains = <&rpm 3824 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3825 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3826 status = "disabled";
3942 }; 3827 };
3943 3828
3944 slim: slim-ngd@171c0000 { !! 3829 slim: slim@171c0000 {
3945 compatible = "qcom,sl 3830 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3831 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3832 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3833
3949 dmas = <&slimbam 3>, !! 3834 qcom,apps-ch-pipes = <0x780000>;
3950 dma-names = "rx", "tx !! 3835 qcom,ea-pc = <0x270>;
>> 3836 status = "okay";
>> 3837 dmas = <&slimbam 3>, <&slimbam 4>,
>> 3838 <&slimbam 5>, <&slimbam 6>;
>> 3839 dma-names = "rx", "tx", "tx2", "rx2";
3951 3840
3952 iommus = <&apps_smmu 3841 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3842 #address-cells = <1>;
3954 #size-cells = <0>; 3843 #size-cells = <0>;
3955 status = "disabled"; !! 3844
>> 3845 ngd@1 {
>> 3846 reg = <1>;
>> 3847 #address-cells = <2>;
>> 3848 #size-cells = <0>;
>> 3849
>> 3850 wcd9340_ifd: ifd@0{
>> 3851 compatible = "slim217,250";
>> 3852 reg = <0 0>;
>> 3853 };
>> 3854
>> 3855 wcd9340: codec@1{
>> 3856 compatible = "slim217,250";
>> 3857 reg = <1 0>;
>> 3858 slim-ifc-dev = <&wcd9340_ifd>;
>> 3859
>> 3860 #sound-dai-cells = <1>;
>> 3861
>> 3862 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3863 interrupt-controller;
>> 3864 #interrupt-cells = <1>;
>> 3865
>> 3866 #clock-cells = <0>;
>> 3867 clock-frequency = <9600000>;
>> 3868 clock-output-names = "mclk";
>> 3869 qcom,micbias1-microvolt = <1800000>;
>> 3870 qcom,micbias2-microvolt = <1800000>;
>> 3871 qcom,micbias3-microvolt = <1800000>;
>> 3872 qcom,micbias4-microvolt = <1800000>;
>> 3873
>> 3874 #address-cells = <1>;
>> 3875 #size-cells = <1>;
>> 3876
>> 3877 wcdgpio: gpio-controller@42 {
>> 3878 compatible = "qcom,wcd9340-gpio";
>> 3879 gpio-controller;
>> 3880 #gpio-cells = <2>;
>> 3881 reg = <0x42 0x2>;
>> 3882 };
>> 3883
>> 3884 swm: swm@c85 {
>> 3885 compatible = "qcom,soundwire-v1.3.0";
>> 3886 reg = <0xc85 0x40>;
>> 3887 interrupts-extended = <&wcd9340 20>;
>> 3888
>> 3889 qcom,dout-ports = <6>;
>> 3890 qcom,din-ports = <2>;
>> 3891 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3892 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3893 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3894
>> 3895 #sound-dai-cells = <1>;
>> 3896 clocks = <&wcd9340>;
>> 3897 clock-names = "iface";
>> 3898 #address-cells = <2>;
>> 3899 #size-cells = <0>;
>> 3900
>> 3901
>> 3902 };
>> 3903 };
>> 3904 };
3956 }; 3905 };
3957 3906
3958 lmh_cluster1: lmh@17d70800 { 3907 lmh_cluster1: lmh@17d70800 {
3959 compatible = "qcom,sd 3908 compatible = "qcom,sdm845-lmh";
3960 reg = <0 0x17d70800 0 3909 reg = <0 0x17d70800 0 0x400>;
3961 interrupts = <GIC_SPI 3910 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962 cpus = <&CPU4>; 3911 cpus = <&CPU4>;
3963 qcom,lmh-temp-arm-mil 3912 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-mil 3913 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-mi 3914 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller; 3915 interrupt-controller;
3967 #interrupt-cells = <1 3916 #interrupt-cells = <1>;
3968 }; 3917 };
3969 3918
3970 lmh_cluster0: lmh@17d78800 { 3919 lmh_cluster0: lmh@17d78800 {
3971 compatible = "qcom,sd 3920 compatible = "qcom,sdm845-lmh";
3972 reg = <0 0x17d78800 0 3921 reg = <0 0x17d78800 0 0x400>;
3973 interrupts = <GIC_SPI 3922 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974 cpus = <&CPU0>; 3923 cpus = <&CPU0>;
3975 qcom,lmh-temp-arm-mil 3924 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-mil 3925 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-mi 3926 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller; 3927 interrupt-controller;
3979 #interrupt-cells = <1 3928 #interrupt-cells = <1>;
3980 }; 3929 };
3981 3930
>> 3931 sound: sound {
>> 3932 };
>> 3933
3982 usb_1_hsphy: phy@88e2000 { 3934 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3935 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3936 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3937 status = "disabled";
3986 #phy-cells = <0>; 3938 #phy-cells = <0>;
3987 3939
3988 clocks = <&gcc GCC_US 3940 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3941 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3942 clock-names = "cfg_ahb", "ref";
3991 3943
3992 resets = <&gcc GCC_QU 3944 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3945
3994 nvmem-cells = <&qusb2 3946 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3947 };
3996 3948
3997 usb_2_hsphy: phy@88e3000 { 3949 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3950 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3951 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3952 status = "disabled";
4001 #phy-cells = <0>; 3953 #phy-cells = <0>;
4002 3954
4003 clocks = <&gcc GCC_US 3955 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3956 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3957 clock-names = "cfg_ahb", "ref";
4006 3958
4007 resets = <&gcc GCC_QU 3959 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3960
4009 nvmem-cells = <&qusb2 3961 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3962 };
4011 3963
4012 usb_1_qmpphy: phy@88e8000 { !! 3964 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd !! 3965 compatible = "qcom,sdm845-qmp-usb3-phy";
4014 reg = <0 0x088e8000 0 !! 3966 reg = <0 0x088e9000 0 0x18c>,
>> 3967 <0 0x088e8000 0 0x10>;
4015 status = "disabled"; 3968 status = "disabled";
>> 3969 #address-cells = <2>;
>> 3970 #size-cells = <2>;
>> 3971 ranges;
4016 3972
4017 clocks = <&gcc GCC_US 3973 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3974 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3975 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3976 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3977 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3978
4028 resets = <&gcc GCC_US !! 3979 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
4029 <&gcc GCC_US !! 3980 <&gcc GCC_USB3_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3981 reset-names = "phy", "common";
4031 3982
4032 #clock-cells = <1>; !! 3983 usb_1_ssphy: phy@88e9200 {
4033 #phy-cells = <1>; !! 3984 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 3985 <0 0x088e9400 0 0x200>,
4035 !! 3986 <0 0x088e9c00 0 0x218>,
4036 ports { !! 3987 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 3988 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 3989 <0 0x088e9a00 0 0x100>;
4039 !! 3990 #clock-cells = <0>;
4040 port@0 { !! 3991 #phy-cells = <0>;
4041 reg = !! 3992 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042 !! 3993 clock-names = "pipe0";
4043 usb_1 !! 3994 clock-output-names = "usb3_phy_pipe_clk_src";
4044 }; <<
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 <<
4058 usb_1 <<
4059 <<
4060 }; <<
4061 }; <<
4062 }; 3995 };
4063 }; 3996 };
4064 3997
4065 usb_2_qmpphy: phy@88eb000 { 3998 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 3999 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 4000 reg = <0 0x088eb000 0 0x18c>;
>> 4001 status = "disabled";
>> 4002 #address-cells = <2>;
>> 4003 #size-cells = <2>;
>> 4004 ranges;
4068 4005
4069 clocks = <&gcc GCC_US 4006 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 4007 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 4008 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 4009 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 4010 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 4011
4083 resets = <&gcc GCC_US !! 4012 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 4013 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 4014 reset-names = "phy", "common";
4086 "phy_ph <<
4087 4015
4088 status = "disabled"; !! 4016 usb_2_ssphy: phy@88eb200 {
>> 4017 reg = <0 0x088eb200 0 0x128>,
>> 4018 <0 0x088eb400 0 0x1fc>,
>> 4019 <0 0x088eb800 0 0x218>,
>> 4020 <0 0x088eb600 0 0x70>;
>> 4021 #clock-cells = <0>;
>> 4022 #phy-cells = <0>;
>> 4023 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 4024 clock-names = "pipe0";
>> 4025 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 4026 };
4089 }; 4027 };
4090 4028
4091 usb_1: usb@a6f8800 { 4029 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 4030 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 4031 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 4032 status = "disabled";
4095 #address-cells = <2>; 4033 #address-cells = <2>;
4096 #size-cells = <2>; 4034 #size-cells = <2>;
4097 ranges; 4035 ranges;
4098 dma-ranges; 4036 dma-ranges;
4099 4037
4100 clocks = <&gcc GCC_CF 4038 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 4039 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 4040 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US 4041 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4104 <&gcc GCC_US 4042 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4105 clock-names = "cfg_no 4043 clock-names = "cfg_noc",
4106 "core", 4044 "core",
4107 "iface" 4045 "iface",
4108 "sleep" 4046 "sleep",
4109 "mock_u 4047 "mock_utmi";
4110 4048
4111 assigned-clocks = <&g 4049 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 4050 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 4051 assigned-clock-rates = <19200000>, <150000000>;
4114 4052
4115 interrupts-extended = !! 4053 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 4054 <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>,
4117 <<
4118 4055 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
4119 !! 4056 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>;
4120 interrupt-names = "pw !! 4057 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4121 "hs !! 4058 "dm_hs_phy_irq", "dp_hs_phy_irq";
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 4059
4126 power-domains = <&gcc 4060 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 4061
4128 resets = <&gcc GCC_US 4062 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 4063
4130 interconnects = <&agg 4064 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 4065 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 4066 interconnect-names = "usb-ddr", "apps-usb";
4133 4067
4134 usb_1_dwc3: usb@a6000 4068 usb_1_dwc3: usb@a600000 {
4135 compatible = 4069 compatible = "snps,dwc3";
4136 reg = <0 0x0a 4070 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 4071 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 4072 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 4073 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 4074 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 4075 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 4076 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 4077 };
4165 }; 4078 };
4166 4079
4167 usb_2: usb@a8f8800 { 4080 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 4081 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 4082 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 4083 status = "disabled";
4171 #address-cells = <2>; 4084 #address-cells = <2>;
4172 #size-cells = <2>; 4085 #size-cells = <2>;
4173 ranges; 4086 ranges;
4174 dma-ranges; 4087 dma-ranges;
4175 4088
4176 clocks = <&gcc GCC_CF 4089 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 4090 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 4091 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US 4092 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4180 <&gcc GCC_US 4093 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4181 clock-names = "cfg_no 4094 clock-names = "cfg_noc",
4182 "core", 4095 "core",
4183 "iface" 4096 "iface",
4184 "sleep" 4097 "sleep",
4185 "mock_u 4098 "mock_utmi";
4186 4099
4187 assigned-clocks = <&g 4100 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 4101 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 4102 assigned-clock-rates = <19200000>, <150000000>;
4190 4103
4191 interrupts-extended = !! 4104 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 4105 <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>,
4193 <<
4194 4106 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
4195 !! 4107 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>;
4196 interrupt-names = "pw !! 4108 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4197 "hs !! 4109 "dm_hs_phy_irq", "dp_hs_phy_irq";
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 4110
4202 power-domains = <&gcc 4111 power-domains = <&gcc USB30_SEC_GDSC>;
4203 4112
4204 resets = <&gcc GCC_US 4113 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 4114
4206 interconnects = <&agg 4115 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 4116 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 4117 interconnect-names = "usb-ddr", "apps-usb";
4209 4118
4210 usb_2_dwc3: usb@a8000 4119 usb_2_dwc3: usb@a800000 {
4211 compatible = 4120 compatible = "snps,dwc3";
4212 reg = <0 0x0a 4121 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 4122 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 4123 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 4124 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 4125 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 4126 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 4127 phy-names = "usb2-phy", "usb3-phy";
4220 }; 4128 };
4221 }; 4129 };
4222 4130
4223 venus: video-codec@aa00000 { 4131 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 4132 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 4133 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 4134 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 4135 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 4136 <&videocc VCODEC0_GDSC>,
4229 <&vid 4137 <&videocc VCODEC1_GDSC>,
4230 <&rpm 4138 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 4139 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 4140 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 4141 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 4142 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 4143 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 4144 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 4145 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 4146 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 4147 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 4148 clock-names = "core", "iface", "bus",
4241 "vcodec 4149 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 4150 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 4151 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 4152 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 4153 memory-region = <&venus_mem>;
4246 interconnects = <&mms 4154 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 4155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 4156 interconnect-names = "video-mem", "cpu-cfg";
4249 4157
4250 status = "disabled"; 4158 status = "disabled";
4251 4159
4252 video-core0 { 4160 video-core0 {
4253 compatible = 4161 compatible = "venus-decoder";
4254 }; 4162 };
4255 4163
4256 video-core1 { 4164 video-core1 {
4257 compatible = 4165 compatible = "venus-encoder";
4258 }; 4166 };
4259 4167
4260 venus_opp_table: opp- 4168 venus_opp_table: opp-table {
4261 compatible = 4169 compatible = "operating-points-v2";
4262 4170
4263 opp-100000000 4171 opp-100000000 {
4264 opp-h 4172 opp-hz = /bits/ 64 <100000000>;
4265 requi 4173 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 4174 };
4267 4175
4268 opp-200000000 4176 opp-200000000 {
4269 opp-h 4177 opp-hz = /bits/ 64 <200000000>;
4270 requi 4178 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 4179 };
4272 4180
4273 opp-320000000 4181 opp-320000000 {
4274 opp-h 4182 opp-hz = /bits/ 64 <320000000>;
4275 requi 4183 required-opps = <&rpmhpd_opp_svs>;
4276 }; 4184 };
4277 4185
4278 opp-380000000 4186 opp-380000000 {
4279 opp-h 4187 opp-hz = /bits/ 64 <380000000>;
4280 requi 4188 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 4189 };
4282 4190
4283 opp-444000000 4191 opp-444000000 {
4284 opp-h 4192 opp-hz = /bits/ 64 <444000000>;
4285 requi 4193 required-opps = <&rpmhpd_opp_nom>;
4286 }; 4194 };
4287 4195
4288 opp-533000097 4196 opp-533000097 {
4289 opp-h 4197 opp-hz = /bits/ 64 <533000097>;
4290 requi 4198 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 4199 };
4292 }; 4200 };
4293 }; 4201 };
4294 4202
4295 videocc: clock-controller@ab0 4203 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 4204 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 4205 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 4206 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 4207 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 4208 #clock-cells = <1>;
4301 #power-domain-cells = 4209 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 4210 #reset-cells = <1>;
4303 }; 4211 };
4304 4212
4305 camss: camss@acb3000 { 4213 camss: camss@acb3000 {
4306 compatible = "qcom,sd 4214 compatible = "qcom,sdm845-camss";
4307 4215
4308 reg = <0 0x0acb3000 0 !! 4216 reg = <0 0xacb3000 0 0x1000>,
4309 <0 0x0acba000 !! 4217 <0 0xacba000 0 0x1000>,
4310 <0 0x0acc8000 !! 4218 <0 0xacc8000 0 0x1000>,
4311 <0 0x0ac65000 !! 4219 <0 0xac65000 0 0x1000>,
4312 <0 0x0ac66000 !! 4220 <0 0xac66000 0 0x1000>,
4313 <0 0x0ac67000 !! 4221 <0 0xac67000 0 0x1000>,
4314 <0 0x0ac68000 !! 4222 <0 0xac68000 0 0x1000>,
4315 <0 0x0acaf000 !! 4223 <0 0xacaf000 0 0x4000>,
4316 <0 0x0acb6000 !! 4224 <0 0xacb6000 0 0x4000>,
4317 <0 0x0acc4000 !! 4225 <0 0xacc4000 0 0x4000>;
4318 reg-names = "csid0", 4226 reg-names = "csid0",
4319 "csid1", 4227 "csid1",
4320 "csid2", 4228 "csid2",
4321 "csiphy0", 4229 "csiphy0",
4322 "csiphy1", 4230 "csiphy1",
4323 "csiphy2", 4231 "csiphy2",
4324 "csiphy3", 4232 "csiphy3",
4325 "vfe0", 4233 "vfe0",
4326 "vfe1", 4234 "vfe1",
4327 "vfe_lite"; 4235 "vfe_lite";
4328 4236
4329 interrupts = <GIC_SPI 4237 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 4238 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 4239 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 4240 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 4241 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 4242 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 4243 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 4244 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 4245 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 4246 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 4247 interrupt-names = "csid0",
4340 "csid1", 4248 "csid1",
4341 "csid2", 4249 "csid2",
4342 "csiphy0", 4250 "csiphy0",
4343 "csiphy1", 4251 "csiphy1",
4344 "csiphy2", 4252 "csiphy2",
4345 "csiphy3", 4253 "csiphy3",
4346 "vfe0", 4254 "vfe0",
4347 "vfe1", 4255 "vfe1",
4348 "vfe_lite"; 4256 "vfe_lite";
4349 4257
4350 power-domains = <&clo 4258 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 4259 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 4260 <&clock_camcc TITAN_TOP_GDSC>;
4353 4261
4354 clocks = <&clock_camc 4262 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 4263 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 4264 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 4265 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 4266 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 4267 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 4268 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 4269 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 4270 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 4271 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 4272 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 4273 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 4274 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 4275 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 4276 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 4277 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 4278 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 4279 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 4280 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 4281 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 4282 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 4283 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 4284 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 4285 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 4286 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 4287 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 4288 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4289 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4290 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4291 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4292 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4293 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4294 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4295 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4296 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4297 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4298 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4299 "cpas_ahb",
4392 "cphy_rx_src" 4300 "cphy_rx_src",
4393 "csi0", 4301 "csi0",
4394 "csi0_src", 4302 "csi0_src",
4395 "csi1", 4303 "csi1",
4396 "csi1_src", 4304 "csi1_src",
4397 "csi2", 4305 "csi2",
4398 "csi2_src", 4306 "csi2_src",
4399 "csiphy0", 4307 "csiphy0",
4400 "csiphy0_time 4308 "csiphy0_timer",
4401 "csiphy0_time 4309 "csiphy0_timer_src",
4402 "csiphy1", 4310 "csiphy1",
4403 "csiphy1_time 4311 "csiphy1_timer",
4404 "csiphy1_time 4312 "csiphy1_timer_src",
4405 "csiphy2", 4313 "csiphy2",
4406 "csiphy2_time 4314 "csiphy2_timer",
4407 "csiphy2_time 4315 "csiphy2_timer_src",
4408 "csiphy3", 4316 "csiphy3",
4409 "csiphy3_time 4317 "csiphy3_timer",
4410 "csiphy3_time 4318 "csiphy3_timer_src",
4411 "gcc_camera_a 4319 "gcc_camera_ahb",
4412 "gcc_camera_a 4320 "gcc_camera_axi",
4413 "slow_ahb_src 4321 "slow_ahb_src",
4414 "soc_ahb", 4322 "soc_ahb",
4415 "vfe0_axi", 4323 "vfe0_axi",
4416 "vfe0", 4324 "vfe0",
4417 "vfe0_cphy_rx 4325 "vfe0_cphy_rx",
4418 "vfe0_src", 4326 "vfe0_src",
4419 "vfe1_axi", 4327 "vfe1_axi",
4420 "vfe1", 4328 "vfe1",
4421 "vfe1_cphy_rx 4329 "vfe1_cphy_rx",
4422 "vfe1_src", 4330 "vfe1_src",
4423 "vfe_lite", 4331 "vfe_lite",
4424 "vfe_lite_cph 4332 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4333 "vfe_lite_src";
4426 4334
4427 iommus = <&apps_smmu 4335 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4336 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4337 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4338 <&apps_smmu 0x0c10 0x8>;
4431 4339
4432 status = "disabled"; 4340 status = "disabled";
4433 4341
4434 ports { 4342 ports {
4435 #address-cell 4343 #address-cells = <1>;
4436 #size-cells = 4344 #size-cells = <0>;
4437 <<
4438 port@0 { <<
4439 reg = <<
4440 }; <<
4441 <<
4442 port@1 { <<
4443 reg = <<
4444 }; <<
4445 <<
4446 port@2 { <<
4447 reg = <<
4448 }; <<
4449 <<
4450 port@3 { <<
4451 reg = <<
4452 }; <<
4453 }; 4345 };
4454 }; 4346 };
4455 4347
4456 cci: cci@ac4a000 { 4348 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 4349 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 4350 #address-cells = <1>;
4459 #size-cells = <0>; 4351 #size-cells = <0>;
4460 4352
4461 reg = <0 0x0ac4a000 0 4353 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4354 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4355 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4356
4465 clocks = <&clock_camc 4357 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4358 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4359 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4360 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4361 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4362 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4363 clock-names = "camnoc_axi",
4472 "soc_ahb", 4364 "soc_ahb",
4473 "slow_ahb_src 4365 "slow_ahb_src",
4474 "cpas_ahb", 4366 "cpas_ahb",
4475 "cci", 4367 "cci",
4476 "cci_src"; 4368 "cci_src";
4477 4369
4478 assigned-clocks = <&c 4370 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4371 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4372 assigned-clock-rates = <80000000>, <37500000>;
4481 4373
4482 pinctrl-names = "defa 4374 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4375 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4376 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4377
4486 status = "disabled"; 4378 status = "disabled";
4487 4379
4488 cci_i2c0: i2c-bus@0 { 4380 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4381 reg = <0>;
4490 clock-frequen 4382 clock-frequency = <1000000>;
4491 #address-cell 4383 #address-cells = <1>;
4492 #size-cells = 4384 #size-cells = <0>;
4493 }; 4385 };
4494 4386
4495 cci_i2c1: i2c-bus@1 { 4387 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4388 reg = <1>;
4497 clock-frequen 4389 clock-frequency = <1000000>;
4498 #address-cell 4390 #address-cells = <1>;
4499 #size-cells = 4391 #size-cells = <0>;
4500 }; 4392 };
4501 }; 4393 };
4502 4394
4503 clock_camcc: clock-controller 4395 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4396 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4397 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4398 #clock-cells = <1>;
4507 #reset-cells = <1>; 4399 #reset-cells = <1>;
4508 #power-domain-cells = 4400 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM 4401 clocks = <&rpmhcc RPMH_CXO_CLK>;
4510 clock-names = "bi_tcx 4402 clock-names = "bi_tcxo";
4511 }; 4403 };
4512 4404
4513 mdss: display-subsystem@ae000 !! 4405 dsi_opp_table: opp-table-dsi {
>> 4406 compatible = "operating-points-v2";
>> 4407
>> 4408 opp-19200000 {
>> 4409 opp-hz = /bits/ 64 <19200000>;
>> 4410 required-opps = <&rpmhpd_opp_min_svs>;
>> 4411 };
>> 4412
>> 4413 opp-180000000 {
>> 4414 opp-hz = /bits/ 64 <180000000>;
>> 4415 required-opps = <&rpmhpd_opp_low_svs>;
>> 4416 };
>> 4417
>> 4418 opp-275000000 {
>> 4419 opp-hz = /bits/ 64 <275000000>;
>> 4420 required-opps = <&rpmhpd_opp_svs>;
>> 4421 };
>> 4422
>> 4423 opp-328580000 {
>> 4424 opp-hz = /bits/ 64 <328580000>;
>> 4425 required-opps = <&rpmhpd_opp_svs_l1>;
>> 4426 };
>> 4427
>> 4428 opp-358000000 {
>> 4429 opp-hz = /bits/ 64 <358000000>;
>> 4430 required-opps = <&rpmhpd_opp_nom>;
>> 4431 };
>> 4432 };
>> 4433
>> 4434 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 4435 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4436 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4437 reg-names = "mdss";
4517 4438
4518 power-domains = <&dis 4439 power-domains = <&dispcc MDSS_GDSC>;
4519 4440
4520 clocks = <&dispcc DIS 4441 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521 <&dispcc DIS 4442 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" 4443 clock-names = "iface", "core";
4523 4444
4524 interrupts = <GIC_SPI 4445 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4446 interrupt-controller;
4526 #interrupt-cells = <1 4447 #interrupt-cells = <1>;
4527 4448
4528 interconnects = <&mms 4449 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4450 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4451 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4452
4532 iommus = <&apps_smmu 4453 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4454 <&apps_smmu 0xc80 0x8>;
4534 4455
4535 status = "disabled"; 4456 status = "disabled";
4536 4457
4537 #address-cells = <2>; 4458 #address-cells = <2>;
4538 #size-cells = <2>; 4459 #size-cells = <2>;
4539 ranges; 4460 ranges;
4540 4461
4541 mdss_mdp: display-con 4462 mdss_mdp: display-controller@ae01000 {
4542 compatible = 4463 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4464 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4465 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4466 reg-names = "mdp", "vbif";
4546 4467
4547 clocks = <&gc 4468 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548 <&di 4469 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549 <&di 4470 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4471 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4472 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = 4473 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553 4474
4554 assigned-cloc 4475 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555 assigned-cloc 4476 assigned-clock-rates = <19200000>;
4556 operating-poi 4477 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4478 power-domains = <&rpmhpd SDM845_CX>;
4558 4479
4559 interrupt-par 4480 interrupt-parent = <&mdss>;
4560 interrupts = 4481 interrupts = <0>;
4561 4482
4562 ports { 4483 ports {
4563 #addr 4484 #address-cells = <1>;
4564 #size 4485 #size-cells = <0>;
4565 4486
4566 port@ 4487 port@0 {
4567 4488 reg = <0>;
4568 !! 4489 dpu_intf1_out: endpoint {
4569 !! 4490 remote-endpoint = <&dsi0_in>;
4570 4491 };
4571 }; 4492 };
4572 4493
4573 port@ 4494 port@1 {
4574 4495 reg = <1>;
4575 <<
4576 <<
4577 <<
4578 }; <<
4579 <<
4580 port@ <<
4581 <<
4582 4496 dpu_intf2_out: endpoint {
4583 !! 4497 remote-endpoint = <&dsi1_in>;
4584 4498 };
4585 }; 4499 };
4586 }; 4500 };
4587 4501
4588 mdp_opp_table 4502 mdp_opp_table: opp-table {
4589 compa 4503 compatible = "operating-points-v2";
4590 4504
4591 opp-1 4505 opp-19200000 {
4592 4506 opp-hz = /bits/ 64 <19200000>;
4593 4507 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4508 };
4595 4509
4596 opp-1 4510 opp-171428571 {
4597 4511 opp-hz = /bits/ 64 <171428571>;
4598 4512 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4513 };
4600 4514
4601 opp-3 4515 opp-344000000 {
4602 4516 opp-hz = /bits/ 64 <344000000>;
4603 4517 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4518 };
4605 4519
4606 opp-4 4520 opp-430000000 {
4607 4521 opp-hz = /bits/ 64 <430000000>;
4608 4522 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4523 };
4610 }; 4524 };
4611 }; 4525 };
4612 4526
4613 mdss_dp: displayport- !! 4527 dsi0: dsi@ae94000 {
4614 status = "dis !! 4528 compatible = "qcom,mdss-dsi-ctrl";
4615 compatible = <<
4616 <<
4617 reg = <0 0x0a <<
4618 <0 0x0a <<
4619 <0 0x0a <<
4620 <0 0x0a <<
4621 <0 0x0a <<
4622 <<
4623 interrupt-par <<
4624 interrupts = <<
4625 <<
4626 clocks = <&di <<
4627 <&di <<
4628 <&di <<
4629 <&di <<
4630 <&di <<
4631 clock-names = <<
4632 <<
4633 assigned-cloc <<
4634 <<
4635 assigned-cloc <<
4636 <<
4637 phys = <&usb_ <<
4638 phy-names = " <<
4639 <<
4640 operating-poi <<
4641 power-domains <<
4642 <<
4643 ports { <<
4644 #addr <<
4645 #size <<
4646 port@ <<
4647 <<
4648 <<
4649 <<
4650 <<
4651 }; <<
4652 <<
4653 port@ <<
4654 <<
4655 <<
4656 <<
4657 <<
4658 }; <<
4659 }; <<
4660 <<
4661 dp_opp_table: <<
4662 compa <<
4663 <<
4664 opp-1 <<
4665 <<
4666 <<
4667 }; <<
4668 <<
4669 opp-2 <<
4670 <<
4671 <<
4672 }; <<
4673 <<
4674 opp-5 <<
4675 <<
4676 <<
4677 }; <<
4678 <<
4679 opp-8 <<
4680 <<
4681 <<
4682 }; <<
4683 }; <<
4684 }; <<
4685 <<
4686 mdss_dsi0: dsi@ae9400 <<
4687 compatible = <<
4688 <<
4689 reg = <0 0x0a 4529 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4530 reg-names = "dsi_ctrl";
4691 4531
4692 interrupt-par 4532 interrupt-parent = <&mdss>;
4693 interrupts = 4533 interrupts = <4>;
4694 4534
4695 clocks = <&di 4535 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4536 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4537 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4538 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4539 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4540 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4541 clock-names = "byte",
4702 4542 "byte_intf",
4703 4543 "pixel",
4704 4544 "core",
4705 4545 "iface",
4706 4546 "bus";
4707 assigned-cloc 4547 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-cloc !! 4548 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4709 4549
4710 operating-poi 4550 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4551 power-domains = <&rpmhpd SDM845_CX>;
4712 4552
4713 phys = <&mdss !! 4553 phys = <&dsi0_phy>;
>> 4554 phy-names = "dsi";
4714 4555
4715 status = "dis 4556 status = "disabled";
4716 4557
4717 #address-cell 4558 #address-cells = <1>;
4718 #size-cells = 4559 #size-cells = <0>;
4719 4560
4720 ports { 4561 ports {
4721 #addr 4562 #address-cells = <1>;
4722 #size 4563 #size-cells = <0>;
4723 4564
4724 port@ 4565 port@0 {
4725 4566 reg = <0>;
4726 !! 4567 dsi0_in: endpoint {
4727 4568 remote-endpoint = <&dpu_intf1_out>;
4728 4569 };
4729 }; 4570 };
4730 4571
4731 port@ 4572 port@1 {
4732 4573 reg = <1>;
4733 !! 4574 dsi0_out: endpoint {
4734 4575 };
4735 }; 4576 };
4736 }; 4577 };
4737 }; 4578 };
4738 4579
4739 mdss_dsi0_phy: phy@ae !! 4580 dsi0_phy: dsi-phy@ae94400 {
4740 compatible = 4581 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4582 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4583 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4584 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4585 reg-names = "dsi_phy",
4745 " 4586 "dsi_phy_lane",
4746 " 4587 "dsi_pll";
4747 4588
4748 #clock-cells 4589 #clock-cells = <1>;
4749 #phy-cells = 4590 #phy-cells = <0>;
4750 4591
4751 clocks = <&di 4592 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4593 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4594 clock-names = "iface", "ref";
4754 4595
4755 status = "dis 4596 status = "disabled";
4756 }; 4597 };
4757 4598
4758 mdss_dsi1: dsi@ae9600 !! 4599 dsi1: dsi@ae96000 {
4759 compatible = !! 4600 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 4601 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4602 reg-names = "dsi_ctrl";
4763 4603
4764 interrupt-par 4604 interrupt-parent = <&mdss>;
4765 interrupts = 4605 interrupts = <5>;
4766 4606
4767 clocks = <&di 4607 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4608 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4609 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4610 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4611 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4612 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4613 clock-names = "byte",
4774 4614 "byte_intf",
4775 4615 "pixel",
4776 4616 "core",
4777 4617 "iface",
4778 4618 "bus";
4779 assigned-cloc 4619 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-cloc !! 4620 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4781 4621
4782 operating-poi 4622 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4623 power-domains = <&rpmhpd SDM845_CX>;
4784 4624
4785 phys = <&mdss !! 4625 phys = <&dsi1_phy>;
>> 4626 phy-names = "dsi";
4786 4627
4787 status = "dis 4628 status = "disabled";
4788 4629
4789 #address-cell 4630 #address-cells = <1>;
4790 #size-cells = 4631 #size-cells = <0>;
4791 4632
4792 ports { 4633 ports {
4793 #addr 4634 #address-cells = <1>;
4794 #size 4635 #size-cells = <0>;
4795 4636
4796 port@ 4637 port@0 {
4797 4638 reg = <0>;
4798 !! 4639 dsi1_in: endpoint {
4799 4640 remote-endpoint = <&dpu_intf2_out>;
4800 4641 };
4801 }; 4642 };
4802 4643
4803 port@ 4644 port@1 {
4804 4645 reg = <1>;
4805 !! 4646 dsi1_out: endpoint {
4806 4647 };
4807 }; 4648 };
4808 }; 4649 };
4809 }; 4650 };
4810 4651
4811 mdss_dsi1_phy: phy@ae !! 4652 dsi1_phy: dsi-phy@ae96400 {
4812 compatible = 4653 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4654 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4655 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4656 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4657 reg-names = "dsi_phy",
4817 " 4658 "dsi_phy_lane",
4818 " 4659 "dsi_pll";
4819 4660
4820 #clock-cells 4661 #clock-cells = <1>;
4821 #phy-cells = 4662 #phy-cells = <0>;
4822 4663
4823 clocks = <&di 4664 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4665 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4666 clock-names = "iface", "ref";
4826 4667
4827 status = "dis 4668 status = "disabled";
4828 }; 4669 };
4829 }; 4670 };
4830 4671
4831 gpu: gpu@5000000 { 4672 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4673 compatible = "qcom,adreno-630.2", "qcom,adreno";
4833 4674
4834 reg = <0 0x05000000 0 !! 4675 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4676 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4677
4837 /* 4678 /*
4838 * Look ma, no clocks 4679 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4680 * controlled entirely by the GMU
4840 */ 4681 */
4841 4682
4842 interrupts = <GIC_SPI 4683 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4684
4844 iommus = <&adreno_smm 4685 iommus = <&adreno_smmu 0>;
4845 4686
4846 operating-points-v2 = 4687 operating-points-v2 = <&gpu_opp_table>;
4847 4688
4848 qcom,gmu = <&gmu>; 4689 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4690
4851 interconnects = <&mem 4691 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4692 interconnect-names = "gfx-mem";
4853 4693
4854 status = "disabled"; 4694 status = "disabled";
4855 4695
4856 gpu_opp_table: opp-ta 4696 gpu_opp_table: opp-table {
4857 compatible = 4697 compatible = "operating-points-v2";
4858 4698
4859 opp-710000000 4699 opp-710000000 {
4860 opp-h 4700 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4701 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4702 opp-peak-kBps = <7216000>;
4863 }; 4703 };
4864 4704
4865 opp-675000000 4705 opp-675000000 {
4866 opp-h 4706 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4707 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4708 opp-peak-kBps = <7216000>;
4869 }; 4709 };
4870 4710
4871 opp-596000000 4711 opp-596000000 {
4872 opp-h 4712 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4713 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4714 opp-peak-kBps = <6220000>;
4875 }; 4715 };
4876 4716
4877 opp-520000000 4717 opp-520000000 {
4878 opp-h 4718 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4719 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4720 opp-peak-kBps = <6220000>;
4881 }; 4721 };
4882 4722
4883 opp-414000000 4723 opp-414000000 {
4884 opp-h 4724 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4725 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4726 opp-peak-kBps = <4068000>;
4887 }; 4727 };
4888 4728
4889 opp-342000000 4729 opp-342000000 {
4890 opp-h 4730 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4731 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4732 opp-peak-kBps = <2724000>;
4893 }; 4733 };
4894 4734
4895 opp-257000000 4735 opp-257000000 {
4896 opp-h 4736 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4737 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4738 opp-peak-kBps = <1648000>;
4899 }; 4739 };
4900 }; 4740 };
4901 }; 4741 };
4902 4742
4903 adreno_smmu: iommu@5040000 { 4743 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4744 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4745 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4746 #iommu-cells = <1>;
4907 #global-interrupts = 4747 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4748 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4749 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4750 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4751 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4752 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4753 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4754 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4755 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4756 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4757 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4758 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4759 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4760 clock-names = "bus", "iface";
4921 4761
4922 power-domains = <&gpu 4762 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4763 };
4924 4764
4925 gmu: gmu@506a000 { 4765 gmu: gmu@506a000 {
4926 compatible = "qcom,ad 4766 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4767
4928 reg = <0 0x0506a000 0 !! 4768 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4769 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4770 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4771 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4772
4933 interrupts = <GIC_SPI 4773 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4774 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4775 interrupt-names = "hfi", "gmu";
4936 4776
4937 clocks = <&gpucc GPU_ 4777 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4778 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4779 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4780 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4781 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4782
4943 power-domains = <&gpu 4783 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4784 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4785 power-domain-names = "cx", "gx";
4946 4786
4947 iommus = <&adreno_smm 4787 iommus = <&adreno_smmu 5>;
4948 4788
4949 operating-points-v2 = 4789 operating-points-v2 = <&gmu_opp_table>;
4950 4790
4951 status = "disabled"; 4791 status = "disabled";
4952 4792
4953 gmu_opp_table: opp-ta 4793 gmu_opp_table: opp-table {
4954 compatible = 4794 compatible = "operating-points-v2";
4955 4795
4956 opp-400000000 4796 opp-400000000 {
4957 opp-h 4797 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4798 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4799 };
4960 4800
4961 opp-200000000 4801 opp-200000000 {
4962 opp-h 4802 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4803 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4804 };
4965 }; 4805 };
4966 }; 4806 };
4967 4807
4968 dispcc: clock-controller@af00 4808 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4809 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4810 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4811 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4812 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4813 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4814 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4815 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4816 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4817 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4818 <0>,
4979 <&usb_1_qmpp !! 4819 <0>;
4980 clock-names = "bi_tcx 4820 clock-names = "bi_tcxo",
4981 "gcc_di 4821 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4822 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4823 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4824 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4825 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4826 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4827 "dp_link_clk_divsel_ten",
4988 "dp_vco 4828 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4829 #clock-cells = <1>;
4990 #reset-cells = <1>; 4830 #reset-cells = <1>;
4991 #power-domain-cells = 4831 #power-domain-cells = <1>;
4992 }; 4832 };
4993 4833
4994 pdc_intc: interrupt-controlle 4834 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4835 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4836 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4837 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4838 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4839 interrupt-parent = <&intc>;
5000 interrupt-controller; 4840 interrupt-controller;
5001 }; 4841 };
5002 4842
5003 pdc_reset: reset-controller@b 4843 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4844 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4845 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4846 #reset-cells = <1>;
5007 }; 4847 };
5008 4848
5009 tsens0: thermal-sensor@c26300 4849 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4850 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4851 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4852 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4853 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4854 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4855 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4856 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4857 #thermal-sensor-cells = <1>;
5018 }; 4858 };
5019 4859
5020 tsens1: thermal-sensor@c26500 4860 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4861 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4862 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4863 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4864 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4865 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4866 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4867 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4868 #thermal-sensor-cells = <1>;
5029 }; 4869 };
5030 4870
5031 aoss_reset: reset-controller@ 4871 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4872 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4873 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4874 #reset-cells = <1>;
5035 }; 4875 };
5036 4876
5037 aoss_qmp: power-management@c3 !! 4877 aoss_qmp: power-controller@c300000 {
5038 compatible = "qcom,sd 4878 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039 reg = <0 0x0c300000 0 4879 reg = <0 0x0c300000 0 0x400>;
5040 interrupts = <GIC_SPI 4880 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4881 mboxes = <&apss_shared 0>;
5042 4882
5043 #clock-cells = <0>; 4883 #clock-cells = <0>;
5044 4884
5045 cx_cdev: cx { 4885 cx_cdev: cx {
5046 #cooling-cell 4886 #cooling-cells = <2>;
5047 }; 4887 };
5048 4888
5049 ebi_cdev: ebi { 4889 ebi_cdev: ebi {
5050 #cooling-cell 4890 #cooling-cells = <2>;
5051 }; 4891 };
5052 }; 4892 };
5053 4893
5054 sram@c3f0000 { 4894 sram@c3f0000 {
5055 compatible = "qcom,sd 4895 compatible = "qcom,sdm845-rpmh-stats";
5056 reg = <0 0x0c3f0000 0 4896 reg = <0 0x0c3f0000 0 0x400>;
5057 }; 4897 };
5058 4898
5059 spmi_bus: spmi@c440000 { 4899 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4900 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4901 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4902 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4903 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4904 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4905 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 4906 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 4907 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 4908 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 4909 qcom,ee = <0>;
5070 qcom,channel = <0>; 4910 qcom,channel = <0>;
5071 #address-cells = <2>; 4911 #address-cells = <2>;
5072 #size-cells = <0>; 4912 #size-cells = <0>;
5073 interrupt-controller; 4913 interrupt-controller;
5074 #interrupt-cells = <4 4914 #interrupt-cells = <4>;
>> 4915 cell-index = <0>;
5075 }; 4916 };
5076 4917
5077 sram@146bf000 { 4918 sram@146bf000 {
5078 compatible = "qcom,sd 4919 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5079 reg = <0 0x146bf000 0 4920 reg = <0 0x146bf000 0 0x1000>;
5080 4921
5081 #address-cells = <1>; 4922 #address-cells = <1>;
5082 #size-cells = <1>; 4923 #size-cells = <1>;
5083 4924
5084 ranges = <0 0 0x146bf 4925 ranges = <0 0 0x146bf000 0x1000>;
5085 4926
5086 pil-reloc@94c { 4927 pil-reloc@94c {
5087 compatible = 4928 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 4929 reg = <0x94c 0xc8>;
5089 }; 4930 };
5090 }; 4931 };
5091 4932
5092 apps_smmu: iommu@15000000 { 4933 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 4934 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 4935 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 4936 #iommu-cells = <2>;
5096 #global-interrupts = 4937 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 4938 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 4939 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 4940 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 4941 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 4942 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 4943 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 4944 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 4945 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 4946 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 4947 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 4948 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 4949 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 4950 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 4951 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 4952 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 4953 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 4954 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 4955 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 4956 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 4957 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 4958 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 4959 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 4960 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 4961 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 4962 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 4963 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 4964 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 4965 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 4966 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 4967 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 4968 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 4969 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 4970 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 4971 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 4972 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 4973 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 4974 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 4975 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 4976 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 4977 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 4978 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 4979 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 4980 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 4981 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 4982 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 4983 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 4984 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 4985 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 4986 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 4987 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 4988 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 4989 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 4990 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 4991 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 4992 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 4993 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 4994 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 4995 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 4996 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 4997 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 4998 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 4999 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 5000 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 5001 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 5002 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 5003 };
5163 5004
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 5005 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 5006 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 5007 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 5008 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 5009 #clock-cells = <1>;
5241 status = "disabled"; 5010 status = "disabled";
5242 }; 5011 };
5243 5012
5244 gladiator_noc: interconnect@1 5013 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 5014 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 5015 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 5016 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 5017 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 5018 };
5250 5019
5251 watchdog@17980000 { 5020 watchdog@17980000 {
5252 compatible = "qcom,ap 5021 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 5022 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 5023 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI 5024 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5256 }; 5025 };
5257 5026
5258 apss_shared: mailbox@17990000 5027 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 5028 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 5029 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 5030 #mbox-cells = <1>;
5262 }; 5031 };
5263 5032
5264 apps_rsc: rsc@179c0000 { 5033 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 5034 label = "apps_rsc";
5266 compatible = "qcom,rp 5035 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 5036 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 5037 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 5038 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 5039 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 5040 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 5041 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 5042 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 5043 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 5044 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 5045 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 5046 <SLEEP_TCS 3>,
5278 <WA 5047 <WAKE_TCS 3>,
5279 <CO 5048 <CONTROL_TCS 1>;
5280 power-domains = <&CLU 5049 power-domains = <&CLUSTER_PD>;
5281 5050
5282 apps_bcm_voter: bcm-v 5051 apps_bcm_voter: bcm-voter {
5283 compatible = 5052 compatible = "qcom,bcm-voter";
5284 }; 5053 };
5285 5054
5286 rpmhcc: clock-control 5055 rpmhcc: clock-controller {
5287 compatible = 5056 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 5057 #clock-cells = <1>;
5289 clock-names = 5058 clock-names = "xo";
5290 clocks = <&xo 5059 clocks = <&xo_board>;
5291 }; 5060 };
5292 5061
5293 rpmhpd: power-control 5062 rpmhpd: power-controller {
5294 compatible = 5063 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 5064 #power-domain-cells = <1>;
5296 operating-poi 5065 operating-points-v2 = <&rpmhpd_opp_table>;
5297 5066
5298 rpmhpd_opp_ta 5067 rpmhpd_opp_table: opp-table {
5299 compa 5068 compatible = "operating-points-v2";
5300 5069
5301 rpmhp 5070 rpmhpd_opp_ret: opp1 {
5302 5071 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 5072 };
5304 5073
5305 rpmhp 5074 rpmhpd_opp_min_svs: opp2 {
5306 5075 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 5076 };
5308 5077
5309 rpmhp 5078 rpmhpd_opp_low_svs: opp3 {
5310 5079 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 5080 };
5312 5081
5313 rpmhp 5082 rpmhpd_opp_svs: opp4 {
5314 5083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 5084 };
5316 5085
5317 rpmhp 5086 rpmhpd_opp_svs_l1: opp5 {
5318 5087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 5088 };
5320 5089
5321 rpmhp 5090 rpmhpd_opp_nom: opp6 {
5322 5091 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 5092 };
5324 5093
5325 rpmhp 5094 rpmhpd_opp_nom_l1: opp7 {
5326 5095 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 5096 };
5328 5097
5329 rpmhp 5098 rpmhpd_opp_nom_l2: opp8 {
5330 5099 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 5100 };
5332 5101
5333 rpmhp 5102 rpmhpd_opp_turbo: opp9 {
5334 5103 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 5104 };
5336 5105
5337 rpmhp 5106 rpmhpd_opp_turbo_l1: opp10 {
5338 5107 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 5108 };
5340 }; 5109 };
5341 }; 5110 };
5342 }; 5111 };
5343 5112
5344 intc: interrupt-controller@17 5113 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 5114 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 5115 #address-cells = <2>;
5347 #size-cells = <2>; 5116 #size-cells = <2>;
5348 ranges; 5117 ranges;
5349 #interrupt-cells = <3 5118 #interrupt-cells = <3>;
5350 interrupt-controller; 5119 interrupt-controller;
5351 reg = <0 0x17a00000 0 5120 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 5121 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 5122 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 5123
5355 msi-controller@17a400 5124 msi-controller@17a40000 {
5356 compatible = 5125 compatible = "arm,gic-v3-its";
5357 msi-controlle 5126 msi-controller;
5358 #msi-cells = 5127 #msi-cells = <1>;
5359 reg = <0 0x17 5128 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 5129 status = "disabled";
5361 }; 5130 };
5362 }; 5131 };
5363 5132
5364 slimbam: dma-controller@17184 5133 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba !! 5134 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 5135 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 5136 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; 5137 num-channels = <31>;
5369 interrupts = <GIC_SPI 5138 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 5139 #dma-cells = <1>;
5371 qcom,ee = <1>; 5140 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 5141 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 5142 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 5143 };
5375 5144
5376 timer@17c90000 { 5145 timer@17c90000 {
5377 #address-cells = <1>; 5146 #address-cells = <1>;
5378 #size-cells = <1>; 5147 #size-cells = <1>;
5379 ranges = <0 0 0 0x200 5148 ranges = <0 0 0 0x20000000>;
5380 compatible = "arm,arm 5149 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 5150 reg = <0 0x17c90000 0 0x1000>;
5382 5151
5383 frame@17ca0000 { 5152 frame@17ca0000 {
5384 frame-number 5153 frame-number = <0>;
5385 interrupts = 5154 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 5155 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca 5156 reg = <0x17ca0000 0x1000>,
5388 <0x17cb 5157 <0x17cb0000 0x1000>;
5389 }; 5158 };
5390 5159
5391 frame@17cc0000 { 5160 frame@17cc0000 {
5392 frame-number 5161 frame-number = <1>;
5393 interrupts = 5162 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc 5163 reg = <0x17cc0000 0x1000>;
5395 status = "dis 5164 status = "disabled";
5396 }; 5165 };
5397 5166
5398 frame@17cd0000 { 5167 frame@17cd0000 {
5399 frame-number 5168 frame-number = <2>;
5400 interrupts = 5169 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd 5170 reg = <0x17cd0000 0x1000>;
5402 status = "dis 5171 status = "disabled";
5403 }; 5172 };
5404 5173
5405 frame@17ce0000 { 5174 frame@17ce0000 {
5406 frame-number 5175 frame-number = <3>;
5407 interrupts = 5176 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce 5177 reg = <0x17ce0000 0x1000>;
5409 status = "dis 5178 status = "disabled";
5410 }; 5179 };
5411 5180
5412 frame@17cf0000 { 5181 frame@17cf0000 {
5413 frame-number 5182 frame-number = <4>;
5414 interrupts = 5183 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf 5184 reg = <0x17cf0000 0x1000>;
5416 status = "dis 5185 status = "disabled";
5417 }; 5186 };
5418 5187
5419 frame@17d00000 { 5188 frame@17d00000 {
5420 frame-number 5189 frame-number = <5>;
5421 interrupts = 5190 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 5191 reg = <0x17d00000 0x1000>;
5423 status = "dis 5192 status = "disabled";
5424 }; 5193 };
5425 5194
5426 frame@17d10000 { 5195 frame@17d10000 {
5427 frame-number 5196 frame-number = <6>;
5428 interrupts = 5197 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 5198 reg = <0x17d10000 0x1000>;
5430 status = "dis 5199 status = "disabled";
5431 }; 5200 };
5432 }; 5201 };
5433 5202
5434 osm_l3: interconnect@17d41000 5203 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd !! 5204 compatible = "qcom,sdm845-osm-l3";
5436 reg = <0 0x17d41000 0 5205 reg = <0 0x17d41000 0 0x1400>;
5437 5206
5438 clocks = <&rpmhcc RPM 5207 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 5208 clock-names = "xo", "alternate";
5440 5209
5441 #interconnect-cells = 5210 #interconnect-cells = <1>;
5442 }; 5211 };
5443 5212
5444 cpufreq_hw: cpufreq@17d43000 5213 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 5214 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 5215 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 5216 reg-names = "freq-domain0", "freq-domain1";
5448 5217
5449 interrupts-extended = 5218 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450 5219
5451 clocks = <&rpmhcc RPM 5220 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 5221 clock-names = "xo", "alternate";
5453 5222
5454 #freq-domain-cells = 5223 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 5224 };
5457 5225
5458 wifi: wifi@18800000 { 5226 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 5227 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 5228 status = "disabled";
5461 reg = <0 0x18800000 0 5229 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 5230 reg-names = "membase";
5463 memory-region = <&wla 5231 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 5232 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 5233 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 5234 interrupts =
5467 <GIC_SPI 414 5235 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 5236 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 5237 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 5238 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 5239 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 5240 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 5241 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 5242 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 5243 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 5244 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 5245 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 5246 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 5247 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 5248 };
5481 }; 5249 };
5482 5250
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 5251 thermal-zones {
5487 cpu0-thermal { 5252 cpu0-thermal {
5488 polling-delay-passive 5253 polling-delay-passive = <250>;
>> 5254 polling-delay = <1000>;
5489 5255
5490 thermal-sensors = <&t 5256 thermal-sensors = <&tsens0 1>;
5491 5257
5492 trips { 5258 trips {
5493 cpu0_alert0: 5259 cpu0_alert0: trip-point0 {
5494 tempe 5260 temperature = <90000>;
5495 hyste 5261 hysteresis = <2000>;
5496 type 5262 type = "passive";
5497 }; 5263 };
5498 5264
5499 cpu0_alert1: 5265 cpu0_alert1: trip-point1 {
5500 tempe 5266 temperature = <95000>;
5501 hyste 5267 hysteresis = <2000>;
5502 type 5268 type = "passive";
5503 }; 5269 };
5504 5270
5505 cpu0_crit: cp !! 5271 cpu0_crit: cpu_crit {
5506 tempe 5272 temperature = <110000>;
5507 hyste 5273 hysteresis = <1000>;
5508 type 5274 type = "critical";
5509 }; 5275 };
5510 }; 5276 };
5511 }; 5277 };
5512 5278
5513 cpu1-thermal { 5279 cpu1-thermal {
5514 polling-delay-passive 5280 polling-delay-passive = <250>;
>> 5281 polling-delay = <1000>;
5515 5282
5516 thermal-sensors = <&t 5283 thermal-sensors = <&tsens0 2>;
5517 5284
5518 trips { 5285 trips {
5519 cpu1_alert0: 5286 cpu1_alert0: trip-point0 {
5520 tempe 5287 temperature = <90000>;
5521 hyste 5288 hysteresis = <2000>;
5522 type 5289 type = "passive";
5523 }; 5290 };
5524 5291
5525 cpu1_alert1: 5292 cpu1_alert1: trip-point1 {
5526 tempe 5293 temperature = <95000>;
5527 hyste 5294 hysteresis = <2000>;
5528 type 5295 type = "passive";
5529 }; 5296 };
5530 5297
5531 cpu1_crit: cp !! 5298 cpu1_crit: cpu_crit {
5532 tempe 5299 temperature = <110000>;
5533 hyste 5300 hysteresis = <1000>;
5534 type 5301 type = "critical";
5535 }; 5302 };
5536 }; 5303 };
5537 }; 5304 };
5538 5305
5539 cpu2-thermal { 5306 cpu2-thermal {
5540 polling-delay-passive 5307 polling-delay-passive = <250>;
>> 5308 polling-delay = <1000>;
5541 5309
5542 thermal-sensors = <&t 5310 thermal-sensors = <&tsens0 3>;
5543 5311
5544 trips { 5312 trips {
5545 cpu2_alert0: 5313 cpu2_alert0: trip-point0 {
5546 tempe 5314 temperature = <90000>;
5547 hyste 5315 hysteresis = <2000>;
5548 type 5316 type = "passive";
5549 }; 5317 };
5550 5318
5551 cpu2_alert1: 5319 cpu2_alert1: trip-point1 {
5552 tempe 5320 temperature = <95000>;
5553 hyste 5321 hysteresis = <2000>;
5554 type 5322 type = "passive";
5555 }; 5323 };
5556 5324
5557 cpu2_crit: cp !! 5325 cpu2_crit: cpu_crit {
5558 tempe 5326 temperature = <110000>;
5559 hyste 5327 hysteresis = <1000>;
5560 type 5328 type = "critical";
5561 }; 5329 };
5562 }; 5330 };
5563 }; 5331 };
5564 5332
5565 cpu3-thermal { 5333 cpu3-thermal {
5566 polling-delay-passive 5334 polling-delay-passive = <250>;
>> 5335 polling-delay = <1000>;
5567 5336
5568 thermal-sensors = <&t 5337 thermal-sensors = <&tsens0 4>;
5569 5338
5570 trips { 5339 trips {
5571 cpu3_alert0: 5340 cpu3_alert0: trip-point0 {
5572 tempe 5341 temperature = <90000>;
5573 hyste 5342 hysteresis = <2000>;
5574 type 5343 type = "passive";
5575 }; 5344 };
5576 5345
5577 cpu3_alert1: 5346 cpu3_alert1: trip-point1 {
5578 tempe 5347 temperature = <95000>;
5579 hyste 5348 hysteresis = <2000>;
5580 type 5349 type = "passive";
5581 }; 5350 };
5582 5351
5583 cpu3_crit: cp !! 5352 cpu3_crit: cpu_crit {
5584 tempe 5353 temperature = <110000>;
5585 hyste 5354 hysteresis = <1000>;
5586 type 5355 type = "critical";
5587 }; 5356 };
5588 }; 5357 };
5589 }; 5358 };
5590 5359
5591 cpu4-thermal { 5360 cpu4-thermal {
5592 polling-delay-passive 5361 polling-delay-passive = <250>;
>> 5362 polling-delay = <1000>;
5593 5363
5594 thermal-sensors = <&t 5364 thermal-sensors = <&tsens0 7>;
5595 5365
5596 trips { 5366 trips {
5597 cpu4_alert0: 5367 cpu4_alert0: trip-point0 {
5598 tempe 5368 temperature = <90000>;
5599 hyste 5369 hysteresis = <2000>;
5600 type 5370 type = "passive";
5601 }; 5371 };
5602 5372
5603 cpu4_alert1: 5373 cpu4_alert1: trip-point1 {
5604 tempe 5374 temperature = <95000>;
5605 hyste 5375 hysteresis = <2000>;
5606 type 5376 type = "passive";
5607 }; 5377 };
5608 5378
5609 cpu4_crit: cp !! 5379 cpu4_crit: cpu_crit {
5610 tempe 5380 temperature = <110000>;
5611 hyste 5381 hysteresis = <1000>;
5612 type 5382 type = "critical";
5613 }; 5383 };
5614 }; 5384 };
5615 }; 5385 };
5616 5386
5617 cpu5-thermal { 5387 cpu5-thermal {
5618 polling-delay-passive 5388 polling-delay-passive = <250>;
>> 5389 polling-delay = <1000>;
5619 5390
5620 thermal-sensors = <&t 5391 thermal-sensors = <&tsens0 8>;
5621 5392
5622 trips { 5393 trips {
5623 cpu5_alert0: 5394 cpu5_alert0: trip-point0 {
5624 tempe 5395 temperature = <90000>;
5625 hyste 5396 hysteresis = <2000>;
5626 type 5397 type = "passive";
5627 }; 5398 };
5628 5399
5629 cpu5_alert1: 5400 cpu5_alert1: trip-point1 {
5630 tempe 5401 temperature = <95000>;
5631 hyste 5402 hysteresis = <2000>;
5632 type 5403 type = "passive";
5633 }; 5404 };
5634 5405
5635 cpu5_crit: cp !! 5406 cpu5_crit: cpu_crit {
5636 tempe 5407 temperature = <110000>;
5637 hyste 5408 hysteresis = <1000>;
5638 type 5409 type = "critical";
5639 }; 5410 };
5640 }; 5411 };
5641 }; 5412 };
5642 5413
5643 cpu6-thermal { 5414 cpu6-thermal {
5644 polling-delay-passive 5415 polling-delay-passive = <250>;
>> 5416 polling-delay = <1000>;
5645 5417
5646 thermal-sensors = <&t 5418 thermal-sensors = <&tsens0 9>;
5647 5419
5648 trips { 5420 trips {
5649 cpu6_alert0: 5421 cpu6_alert0: trip-point0 {
5650 tempe 5422 temperature = <90000>;
5651 hyste 5423 hysteresis = <2000>;
5652 type 5424 type = "passive";
5653 }; 5425 };
5654 5426
5655 cpu6_alert1: 5427 cpu6_alert1: trip-point1 {
5656 tempe 5428 temperature = <95000>;
5657 hyste 5429 hysteresis = <2000>;
5658 type 5430 type = "passive";
5659 }; 5431 };
5660 5432
5661 cpu6_crit: cp !! 5433 cpu6_crit: cpu_crit {
5662 tempe 5434 temperature = <110000>;
5663 hyste 5435 hysteresis = <1000>;
5664 type 5436 type = "critical";
5665 }; 5437 };
5666 }; 5438 };
5667 }; 5439 };
5668 5440
5669 cpu7-thermal { 5441 cpu7-thermal {
5670 polling-delay-passive 5442 polling-delay-passive = <250>;
>> 5443 polling-delay = <1000>;
5671 5444
5672 thermal-sensors = <&t 5445 thermal-sensors = <&tsens0 10>;
5673 5446
5674 trips { 5447 trips {
5675 cpu7_alert0: 5448 cpu7_alert0: trip-point0 {
5676 tempe 5449 temperature = <90000>;
5677 hyste 5450 hysteresis = <2000>;
5678 type 5451 type = "passive";
5679 }; 5452 };
5680 5453
5681 cpu7_alert1: 5454 cpu7_alert1: trip-point1 {
5682 tempe 5455 temperature = <95000>;
5683 hyste 5456 hysteresis = <2000>;
5684 type 5457 type = "passive";
5685 }; 5458 };
5686 5459
5687 cpu7_crit: cp !! 5460 cpu7_crit: cpu_crit {
5688 tempe 5461 temperature = <110000>;
5689 hyste 5462 hysteresis = <1000>;
5690 type 5463 type = "critical";
5691 }; 5464 };
5692 }; 5465 };
5693 }; 5466 };
5694 5467
5695 aoss0-thermal { 5468 aoss0-thermal {
5696 polling-delay-passive 5469 polling-delay-passive = <250>;
>> 5470 polling-delay = <1000>;
5697 5471
5698 thermal-sensors = <&t 5472 thermal-sensors = <&tsens0 0>;
5699 5473
5700 trips { 5474 trips {
5701 aoss0_alert0: 5475 aoss0_alert0: trip-point0 {
5702 tempe 5476 temperature = <90000>;
5703 hyste 5477 hysteresis = <2000>;
5704 type 5478 type = "hot";
5705 }; 5479 };
5706 }; 5480 };
5707 }; 5481 };
5708 5482
5709 cluster0-thermal { 5483 cluster0-thermal {
5710 polling-delay-passive 5484 polling-delay-passive = <250>;
>> 5485 polling-delay = <1000>;
5711 5486
5712 thermal-sensors = <&t 5487 thermal-sensors = <&tsens0 5>;
5713 5488
5714 trips { 5489 trips {
5715 cluster0_aler 5490 cluster0_alert0: trip-point0 {
5716 tempe 5491 temperature = <90000>;
5717 hyste 5492 hysteresis = <2000>;
5718 type 5493 type = "hot";
5719 }; 5494 };
5720 cluster0_crit !! 5495 cluster0_crit: cluster0_crit {
5721 tempe 5496 temperature = <110000>;
5722 hyste 5497 hysteresis = <2000>;
5723 type 5498 type = "critical";
5724 }; 5499 };
5725 }; 5500 };
5726 }; 5501 };
5727 5502
5728 cluster1-thermal { 5503 cluster1-thermal {
5729 polling-delay-passive 5504 polling-delay-passive = <250>;
>> 5505 polling-delay = <1000>;
5730 5506
5731 thermal-sensors = <&t 5507 thermal-sensors = <&tsens0 6>;
5732 5508
5733 trips { 5509 trips {
5734 cluster1_aler 5510 cluster1_alert0: trip-point0 {
5735 tempe 5511 temperature = <90000>;
5736 hyste 5512 hysteresis = <2000>;
5737 type 5513 type = "hot";
5738 }; 5514 };
5739 cluster1_crit !! 5515 cluster1_crit: cluster1_crit {
5740 tempe 5516 temperature = <110000>;
5741 hyste 5517 hysteresis = <2000>;
5742 type 5518 type = "critical";
5743 }; 5519 };
5744 }; 5520 };
5745 }; 5521 };
5746 5522
5747 gpu-top-thermal { 5523 gpu-top-thermal {
5748 polling-delay-passive 5524 polling-delay-passive = <250>;
>> 5525 polling-delay = <1000>;
5749 5526
5750 thermal-sensors = <&t 5527 thermal-sensors = <&tsens0 11>;
5751 5528
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5529 trips {
5760 gpu_top_alert !! 5530 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5531 temperature = <90000>;
5768 hyste !! 5532 hysteresis = <2000>;
5769 type 5533 type = "hot";
5770 }; 5534 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5535 };
5778 }; 5536 };
5779 5537
5780 gpu-bottom-thermal { 5538 gpu-bottom-thermal {
5781 polling-delay-passive 5539 polling-delay-passive = <250>;
>> 5540 polling-delay = <1000>;
5782 5541
5783 thermal-sensors = <&t 5542 thermal-sensors = <&tsens0 12>;
5784 5543
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5544 trips {
5793 gpu_bottom_al !! 5545 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5546 temperature = <90000>;
5801 hyste !! 5547 hysteresis = <2000>;
5802 type 5548 type = "hot";
5803 }; 5549 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5550 };
5811 }; 5551 };
5812 5552
5813 aoss1-thermal { 5553 aoss1-thermal {
5814 polling-delay-passive 5554 polling-delay-passive = <250>;
>> 5555 polling-delay = <1000>;
5815 5556
5816 thermal-sensors = <&t 5557 thermal-sensors = <&tsens1 0>;
5817 5558
5818 trips { 5559 trips {
5819 aoss1_alert0: 5560 aoss1_alert0: trip-point0 {
5820 tempe 5561 temperature = <90000>;
5821 hyste 5562 hysteresis = <2000>;
5822 type 5563 type = "hot";
5823 }; 5564 };
5824 }; 5565 };
5825 }; 5566 };
5826 5567
5827 q6-modem-thermal { 5568 q6-modem-thermal {
5828 polling-delay-passive 5569 polling-delay-passive = <250>;
>> 5570 polling-delay = <1000>;
5829 5571
5830 thermal-sensors = <&t 5572 thermal-sensors = <&tsens1 1>;
5831 5573
5832 trips { 5574 trips {
5833 q6_modem_aler 5575 q6_modem_alert0: trip-point0 {
5834 tempe 5576 temperature = <90000>;
5835 hyste 5577 hysteresis = <2000>;
5836 type 5578 type = "hot";
5837 }; 5579 };
5838 }; 5580 };
5839 }; 5581 };
5840 5582
5841 mem-thermal { 5583 mem-thermal {
5842 polling-delay-passive 5584 polling-delay-passive = <250>;
>> 5585 polling-delay = <1000>;
5843 5586
5844 thermal-sensors = <&t 5587 thermal-sensors = <&tsens1 2>;
5845 5588
5846 trips { 5589 trips {
5847 mem_alert0: t 5590 mem_alert0: trip-point0 {
5848 tempe 5591 temperature = <90000>;
5849 hyste 5592 hysteresis = <2000>;
5850 type 5593 type = "hot";
5851 }; 5594 };
5852 }; 5595 };
5853 }; 5596 };
5854 5597
5855 wlan-thermal { 5598 wlan-thermal {
5856 polling-delay-passive 5599 polling-delay-passive = <250>;
>> 5600 polling-delay = <1000>;
5857 5601
5858 thermal-sensors = <&t 5602 thermal-sensors = <&tsens1 3>;
5859 5603
5860 trips { 5604 trips {
5861 wlan_alert0: 5605 wlan_alert0: trip-point0 {
5862 tempe 5606 temperature = <90000>;
5863 hyste 5607 hysteresis = <2000>;
5864 type 5608 type = "hot";
5865 }; 5609 };
5866 }; 5610 };
5867 }; 5611 };
5868 5612
5869 q6-hvx-thermal { 5613 q6-hvx-thermal {
5870 polling-delay-passive 5614 polling-delay-passive = <250>;
>> 5615 polling-delay = <1000>;
5871 5616
5872 thermal-sensors = <&t 5617 thermal-sensors = <&tsens1 4>;
5873 5618
5874 trips { 5619 trips {
5875 q6_hvx_alert0 5620 q6_hvx_alert0: trip-point0 {
5876 tempe 5621 temperature = <90000>;
5877 hyste 5622 hysteresis = <2000>;
5878 type 5623 type = "hot";
5879 }; 5624 };
5880 }; 5625 };
5881 }; 5626 };
5882 5627
5883 camera-thermal { 5628 camera-thermal {
5884 polling-delay-passive 5629 polling-delay-passive = <250>;
>> 5630 polling-delay = <1000>;
5885 5631
5886 thermal-sensors = <&t 5632 thermal-sensors = <&tsens1 5>;
5887 5633
5888 trips { 5634 trips {
5889 camera_alert0 5635 camera_alert0: trip-point0 {
5890 tempe 5636 temperature = <90000>;
5891 hyste 5637 hysteresis = <2000>;
5892 type 5638 type = "hot";
5893 }; 5639 };
5894 }; 5640 };
5895 }; 5641 };
5896 5642
5897 video-thermal { 5643 video-thermal {
5898 polling-delay-passive 5644 polling-delay-passive = <250>;
>> 5645 polling-delay = <1000>;
5899 5646
5900 thermal-sensors = <&t 5647 thermal-sensors = <&tsens1 6>;
5901 5648
5902 trips { 5649 trips {
5903 video_alert0: 5650 video_alert0: trip-point0 {
5904 tempe 5651 temperature = <90000>;
5905 hyste 5652 hysteresis = <2000>;
5906 type 5653 type = "hot";
5907 }; 5654 };
5908 }; 5655 };
5909 }; 5656 };
5910 5657
5911 modem-thermal { 5658 modem-thermal {
5912 polling-delay-passive 5659 polling-delay-passive = <250>;
>> 5660 polling-delay = <1000>;
5913 5661
5914 thermal-sensors = <&t 5662 thermal-sensors = <&tsens1 7>;
5915 5663
5916 trips { 5664 trips {
5917 modem_alert0: 5665 modem_alert0: trip-point0 {
5918 tempe 5666 temperature = <90000>;
5919 hyste 5667 hysteresis = <2000>;
5920 type 5668 type = "hot";
5921 }; 5669 };
5922 }; 5670 };
5923 }; 5671 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5672 };
5933 }; 5673 };
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