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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/qcom/sdm845.dtsi (Version linux-6.10.14)


  1 // SPDX-License-Identifier: GPL-2.0                 1 // SPDX-License-Identifier: GPL-2.0
  2 /*                                                  2 /*
  3  * SDM845 SoC device tree source                    3  * SDM845 SoC device tree source
  4  *                                                  4  *
  5  * Copyright (c) 2018, The Linux Foundation. A      5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  6  */                                                 6  */
  7                                                     7 
  8 #include <dt-bindings/clock/qcom,camcc-sdm845.      8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
  9 #include <dt-bindings/clock/qcom,dispcc-sdm845      9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>     10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.     11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
 12 #include <dt-bindings/clock/qcom,lpass-sdm845.     12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
 13 #include <dt-bindings/clock/qcom,rpmh.h>           13 #include <dt-bindings/clock/qcom,rpmh.h>
 14 #include <dt-bindings/clock/qcom,videocc-sdm84     14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
 15 #include <dt-bindings/dma/qcom-gpi.h>              15 #include <dt-bindings/dma/qcom-gpi.h>
 16 #include <dt-bindings/firmware/qcom,scm.h>         16 #include <dt-bindings/firmware/qcom,scm.h>
 17 #include <dt-bindings/gpio/gpio.h>                 17 #include <dt-bindings/gpio/gpio.h>
 18 #include <dt-bindings/interconnect/qcom,icc.h> << 
 19 #include <dt-bindings/interconnect/qcom,osm-l3     18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 20 #include <dt-bindings/interconnect/qcom,sdm845     19 #include <dt-bindings/interconnect/qcom,sdm845.h>
 21 #include <dt-bindings/interrupt-controller/arm     20 #include <dt-bindings/interrupt-controller/arm-gic.h>
 22 #include <dt-bindings/phy/phy-qcom-qmp.h>          21 #include <dt-bindings/phy/phy-qcom-qmp.h>
 23 #include <dt-bindings/phy/phy-qcom-qusb2.h>        22 #include <dt-bindings/phy/phy-qcom-qusb2.h>
 24 #include <dt-bindings/power/qcom-rpmpd.h>          23 #include <dt-bindings/power/qcom-rpmpd.h>
 25 #include <dt-bindings/reset/qcom,sdm845-aoss.h     24 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
 26 #include <dt-bindings/reset/qcom,sdm845-pdc.h>     25 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
 27 #include <dt-bindings/soc/qcom,apr.h>              26 #include <dt-bindings/soc/qcom,apr.h>
 28 #include <dt-bindings/soc/qcom,rpmh-rsc.h>         27 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 29 #include <dt-bindings/clock/qcom,gcc-sdm845.h>     28 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 30 #include <dt-bindings/thermal/thermal.h>           29 #include <dt-bindings/thermal/thermal.h>
 31                                                    30 
 32 / {                                                31 / {
 33         interrupt-parent = <&intc>;                32         interrupt-parent = <&intc>;
 34                                                    33 
 35         #address-cells = <2>;                      34         #address-cells = <2>;
 36         #size-cells = <2>;                         35         #size-cells = <2>;
 37                                                    36 
 38         aliases {                                  37         aliases {
 39                 i2c0 = &i2c0;                      38                 i2c0 = &i2c0;
 40                 i2c1 = &i2c1;                      39                 i2c1 = &i2c1;
 41                 i2c2 = &i2c2;                      40                 i2c2 = &i2c2;
 42                 i2c3 = &i2c3;                      41                 i2c3 = &i2c3;
 43                 i2c4 = &i2c4;                      42                 i2c4 = &i2c4;
 44                 i2c5 = &i2c5;                      43                 i2c5 = &i2c5;
 45                 i2c6 = &i2c6;                      44                 i2c6 = &i2c6;
 46                 i2c7 = &i2c7;                      45                 i2c7 = &i2c7;
 47                 i2c8 = &i2c8;                      46                 i2c8 = &i2c8;
 48                 i2c9 = &i2c9;                      47                 i2c9 = &i2c9;
 49                 i2c10 = &i2c10;                    48                 i2c10 = &i2c10;
 50                 i2c11 = &i2c11;                    49                 i2c11 = &i2c11;
 51                 i2c12 = &i2c12;                    50                 i2c12 = &i2c12;
 52                 i2c13 = &i2c13;                    51                 i2c13 = &i2c13;
 53                 i2c14 = &i2c14;                    52                 i2c14 = &i2c14;
 54                 i2c15 = &i2c15;                    53                 i2c15 = &i2c15;
 55                 spi0 = &spi0;                      54                 spi0 = &spi0;
 56                 spi1 = &spi1;                      55                 spi1 = &spi1;
 57                 spi2 = &spi2;                      56                 spi2 = &spi2;
 58                 spi3 = &spi3;                      57                 spi3 = &spi3;
 59                 spi4 = &spi4;                      58                 spi4 = &spi4;
 60                 spi5 = &spi5;                      59                 spi5 = &spi5;
 61                 spi6 = &spi6;                      60                 spi6 = &spi6;
 62                 spi7 = &spi7;                      61                 spi7 = &spi7;
 63                 spi8 = &spi8;                      62                 spi8 = &spi8;
 64                 spi9 = &spi9;                      63                 spi9 = &spi9;
 65                 spi10 = &spi10;                    64                 spi10 = &spi10;
 66                 spi11 = &spi11;                    65                 spi11 = &spi11;
 67                 spi12 = &spi12;                    66                 spi12 = &spi12;
 68                 spi13 = &spi13;                    67                 spi13 = &spi13;
 69                 spi14 = &spi14;                    68                 spi14 = &spi14;
 70                 spi15 = &spi15;                    69                 spi15 = &spi15;
 71         };                                         70         };
 72                                                    71 
 73         chosen { };                                72         chosen { };
 74                                                    73 
 75         clocks {                                   74         clocks {
 76                 xo_board: xo-board {               75                 xo_board: xo-board {
 77                         compatible = "fixed-cl     76                         compatible = "fixed-clock";
 78                         #clock-cells = <0>;        77                         #clock-cells = <0>;
 79                         clock-frequency = <384     78                         clock-frequency = <38400000>;
 80                         clock-output-names = "     79                         clock-output-names = "xo_board";
 81                 };                                 80                 };
 82                                                    81 
 83                 sleep_clk: sleep-clk {             82                 sleep_clk: sleep-clk {
 84                         compatible = "fixed-cl     83                         compatible = "fixed-clock";
 85                         #clock-cells = <0>;        84                         #clock-cells = <0>;
 86                         clock-frequency = <327     85                         clock-frequency = <32764>;
 87                 };                                 86                 };
 88         };                                         87         };
 89                                                    88 
 90         cpus: cpus {                               89         cpus: cpus {
 91                 #address-cells = <2>;              90                 #address-cells = <2>;
 92                 #size-cells = <0>;                 91                 #size-cells = <0>;
 93                                                    92 
 94                 CPU0: cpu@0 {                      93                 CPU0: cpu@0 {
 95                         device_type = "cpu";       94                         device_type = "cpu";
 96                         compatible = "qcom,kry     95                         compatible = "qcom,kryo385";
 97                         reg = <0x0 0x0>;           96                         reg = <0x0 0x0>;
 98                         clocks = <&cpufreq_hw      97                         clocks = <&cpufreq_hw 0>;
 99                         enable-method = "psci"     98                         enable-method = "psci";
100                         capacity-dmips-mhz = <     99                         capacity-dmips-mhz = <611>;
101                         dynamic-power-coeffici    100                         dynamic-power-coefficient = <154>;
102                         qcom,freq-domain = <&c    101                         qcom,freq-domain = <&cpufreq_hw 0>;
103                         operating-points-v2 =     102                         operating-points-v2 = <&cpu0_opp_table>;
104                         interconnects = <&glad    103                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105                                         <&osm_    104                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106                         power-domains = <&CPU_    105                         power-domains = <&CPU_PD0>;
107                         power-domain-names = "    106                         power-domain-names = "psci";
108                         #cooling-cells = <2>;     107                         #cooling-cells = <2>;
109                         next-level-cache = <&L    108                         next-level-cache = <&L2_0>;
110                         L2_0: l2-cache {          109                         L2_0: l2-cache {
111                                 compatible = "    110                                 compatible = "cache";
112                                 cache-level =     111                                 cache-level = <2>;
113                                 cache-unified;    112                                 cache-unified;
114                                 next-level-cac    113                                 next-level-cache = <&L3_0>;
115                                 L3_0: l3-cache    114                                 L3_0: l3-cache {
116                                         compat    115                                         compatible = "cache";
117                                         cache-    116                                         cache-level = <3>;
118                                         cache-    117                                         cache-unified;
119                                 };                118                                 };
120                         };                        119                         };
121                 };                                120                 };
122                                                   121 
123                 CPU1: cpu@100 {                   122                 CPU1: cpu@100 {
124                         device_type = "cpu";      123                         device_type = "cpu";
125                         compatible = "qcom,kry    124                         compatible = "qcom,kryo385";
126                         reg = <0x0 0x100>;        125                         reg = <0x0 0x100>;
127                         clocks = <&cpufreq_hw     126                         clocks = <&cpufreq_hw 0>;
128                         enable-method = "psci"    127                         enable-method = "psci";
129                         capacity-dmips-mhz = <    128                         capacity-dmips-mhz = <611>;
130                         dynamic-power-coeffici    129                         dynamic-power-coefficient = <154>;
131                         qcom,freq-domain = <&c    130                         qcom,freq-domain = <&cpufreq_hw 0>;
132                         operating-points-v2 =     131                         operating-points-v2 = <&cpu0_opp_table>;
133                         interconnects = <&glad    132                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134                                         <&osm_    133                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135                         power-domains = <&CPU_    134                         power-domains = <&CPU_PD1>;
136                         power-domain-names = "    135                         power-domain-names = "psci";
137                         #cooling-cells = <2>;     136                         #cooling-cells = <2>;
138                         next-level-cache = <&L    137                         next-level-cache = <&L2_100>;
139                         L2_100: l2-cache {        138                         L2_100: l2-cache {
140                                 compatible = "    139                                 compatible = "cache";
141                                 cache-level =     140                                 cache-level = <2>;
142                                 cache-unified;    141                                 cache-unified;
143                                 next-level-cac    142                                 next-level-cache = <&L3_0>;
144                         };                        143                         };
145                 };                                144                 };
146                                                   145 
147                 CPU2: cpu@200 {                   146                 CPU2: cpu@200 {
148                         device_type = "cpu";      147                         device_type = "cpu";
149                         compatible = "qcom,kry    148                         compatible = "qcom,kryo385";
150                         reg = <0x0 0x200>;        149                         reg = <0x0 0x200>;
151                         clocks = <&cpufreq_hw     150                         clocks = <&cpufreq_hw 0>;
152                         enable-method = "psci"    151                         enable-method = "psci";
153                         capacity-dmips-mhz = <    152                         capacity-dmips-mhz = <611>;
154                         dynamic-power-coeffici    153                         dynamic-power-coefficient = <154>;
155                         qcom,freq-domain = <&c    154                         qcom,freq-domain = <&cpufreq_hw 0>;
156                         operating-points-v2 =     155                         operating-points-v2 = <&cpu0_opp_table>;
157                         interconnects = <&glad    156                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158                                         <&osm_    157                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159                         power-domains = <&CPU_    158                         power-domains = <&CPU_PD2>;
160                         power-domain-names = "    159                         power-domain-names = "psci";
161                         #cooling-cells = <2>;     160                         #cooling-cells = <2>;
162                         next-level-cache = <&L    161                         next-level-cache = <&L2_200>;
163                         L2_200: l2-cache {        162                         L2_200: l2-cache {
164                                 compatible = "    163                                 compatible = "cache";
165                                 cache-level =     164                                 cache-level = <2>;
166                                 cache-unified;    165                                 cache-unified;
167                                 next-level-cac    166                                 next-level-cache = <&L3_0>;
168                         };                        167                         };
169                 };                                168                 };
170                                                   169 
171                 CPU3: cpu@300 {                   170                 CPU3: cpu@300 {
172                         device_type = "cpu";      171                         device_type = "cpu";
173                         compatible = "qcom,kry    172                         compatible = "qcom,kryo385";
174                         reg = <0x0 0x300>;        173                         reg = <0x0 0x300>;
175                         clocks = <&cpufreq_hw     174                         clocks = <&cpufreq_hw 0>;
176                         enable-method = "psci"    175                         enable-method = "psci";
177                         capacity-dmips-mhz = <    176                         capacity-dmips-mhz = <611>;
178                         dynamic-power-coeffici    177                         dynamic-power-coefficient = <154>;
179                         qcom,freq-domain = <&c    178                         qcom,freq-domain = <&cpufreq_hw 0>;
180                         operating-points-v2 =     179                         operating-points-v2 = <&cpu0_opp_table>;
181                         interconnects = <&glad    180                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182                                         <&osm_    181                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183                         #cooling-cells = <2>;     182                         #cooling-cells = <2>;
184                         power-domains = <&CPU_    183                         power-domains = <&CPU_PD3>;
185                         power-domain-names = "    184                         power-domain-names = "psci";
186                         next-level-cache = <&L    185                         next-level-cache = <&L2_300>;
187                         L2_300: l2-cache {        186                         L2_300: l2-cache {
188                                 compatible = "    187                                 compatible = "cache";
189                                 cache-level =     188                                 cache-level = <2>;
190                                 cache-unified;    189                                 cache-unified;
191                                 next-level-cac    190                                 next-level-cache = <&L3_0>;
192                         };                        191                         };
193                 };                                192                 };
194                                                   193 
195                 CPU4: cpu@400 {                   194                 CPU4: cpu@400 {
196                         device_type = "cpu";      195                         device_type = "cpu";
197                         compatible = "qcom,kry    196                         compatible = "qcom,kryo385";
198                         reg = <0x0 0x400>;        197                         reg = <0x0 0x400>;
199                         clocks = <&cpufreq_hw     198                         clocks = <&cpufreq_hw 1>;
200                         enable-method = "psci"    199                         enable-method = "psci";
201                         capacity-dmips-mhz = <    200                         capacity-dmips-mhz = <1024>;
202                         dynamic-power-coeffici    201                         dynamic-power-coefficient = <442>;
203                         qcom,freq-domain = <&c    202                         qcom,freq-domain = <&cpufreq_hw 1>;
204                         operating-points-v2 =     203                         operating-points-v2 = <&cpu4_opp_table>;
205                         interconnects = <&glad    204                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206                                         <&osm_    205                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207                         power-domains = <&CPU_    206                         power-domains = <&CPU_PD4>;
208                         power-domain-names = "    207                         power-domain-names = "psci";
209                         #cooling-cells = <2>;     208                         #cooling-cells = <2>;
210                         next-level-cache = <&L    209                         next-level-cache = <&L2_400>;
211                         L2_400: l2-cache {        210                         L2_400: l2-cache {
212                                 compatible = "    211                                 compatible = "cache";
213                                 cache-level =     212                                 cache-level = <2>;
214                                 cache-unified;    213                                 cache-unified;
215                                 next-level-cac    214                                 next-level-cache = <&L3_0>;
216                         };                        215                         };
217                 };                                216                 };
218                                                   217 
219                 CPU5: cpu@500 {                   218                 CPU5: cpu@500 {
220                         device_type = "cpu";      219                         device_type = "cpu";
221                         compatible = "qcom,kry    220                         compatible = "qcom,kryo385";
222                         reg = <0x0 0x500>;        221                         reg = <0x0 0x500>;
223                         clocks = <&cpufreq_hw     222                         clocks = <&cpufreq_hw 1>;
224                         enable-method = "psci"    223                         enable-method = "psci";
225                         capacity-dmips-mhz = <    224                         capacity-dmips-mhz = <1024>;
226                         dynamic-power-coeffici    225                         dynamic-power-coefficient = <442>;
227                         qcom,freq-domain = <&c    226                         qcom,freq-domain = <&cpufreq_hw 1>;
228                         operating-points-v2 =     227                         operating-points-v2 = <&cpu4_opp_table>;
229                         interconnects = <&glad    228                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230                                         <&osm_    229                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231                         power-domains = <&CPU_    230                         power-domains = <&CPU_PD5>;
232                         power-domain-names = "    231                         power-domain-names = "psci";
233                         #cooling-cells = <2>;     232                         #cooling-cells = <2>;
234                         next-level-cache = <&L    233                         next-level-cache = <&L2_500>;
235                         L2_500: l2-cache {        234                         L2_500: l2-cache {
236                                 compatible = "    235                                 compatible = "cache";
237                                 cache-level =     236                                 cache-level = <2>;
238                                 cache-unified;    237                                 cache-unified;
239                                 next-level-cac    238                                 next-level-cache = <&L3_0>;
240                         };                        239                         };
241                 };                                240                 };
242                                                   241 
243                 CPU6: cpu@600 {                   242                 CPU6: cpu@600 {
244                         device_type = "cpu";      243                         device_type = "cpu";
245                         compatible = "qcom,kry    244                         compatible = "qcom,kryo385";
246                         reg = <0x0 0x600>;        245                         reg = <0x0 0x600>;
247                         clocks = <&cpufreq_hw     246                         clocks = <&cpufreq_hw 1>;
248                         enable-method = "psci"    247                         enable-method = "psci";
249                         capacity-dmips-mhz = <    248                         capacity-dmips-mhz = <1024>;
250                         dynamic-power-coeffici    249                         dynamic-power-coefficient = <442>;
251                         qcom,freq-domain = <&c    250                         qcom,freq-domain = <&cpufreq_hw 1>;
252                         operating-points-v2 =     251                         operating-points-v2 = <&cpu4_opp_table>;
253                         interconnects = <&glad    252                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254                                         <&osm_    253                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255                         power-domains = <&CPU_    254                         power-domains = <&CPU_PD6>;
256                         power-domain-names = "    255                         power-domain-names = "psci";
257                         #cooling-cells = <2>;     256                         #cooling-cells = <2>;
258                         next-level-cache = <&L    257                         next-level-cache = <&L2_600>;
259                         L2_600: l2-cache {        258                         L2_600: l2-cache {
260                                 compatible = "    259                                 compatible = "cache";
261                                 cache-level =     260                                 cache-level = <2>;
262                                 cache-unified;    261                                 cache-unified;
263                                 next-level-cac    262                                 next-level-cache = <&L3_0>;
264                         };                        263                         };
265                 };                                264                 };
266                                                   265 
267                 CPU7: cpu@700 {                   266                 CPU7: cpu@700 {
268                         device_type = "cpu";      267                         device_type = "cpu";
269                         compatible = "qcom,kry    268                         compatible = "qcom,kryo385";
270                         reg = <0x0 0x700>;        269                         reg = <0x0 0x700>;
271                         clocks = <&cpufreq_hw     270                         clocks = <&cpufreq_hw 1>;
272                         enable-method = "psci"    271                         enable-method = "psci";
273                         capacity-dmips-mhz = <    272                         capacity-dmips-mhz = <1024>;
274                         dynamic-power-coeffici    273                         dynamic-power-coefficient = <442>;
275                         qcom,freq-domain = <&c    274                         qcom,freq-domain = <&cpufreq_hw 1>;
276                         operating-points-v2 =     275                         operating-points-v2 = <&cpu4_opp_table>;
277                         interconnects = <&glad    276                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278                                         <&osm_    277                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279                         power-domains = <&CPU_    278                         power-domains = <&CPU_PD7>;
280                         power-domain-names = "    279                         power-domain-names = "psci";
281                         #cooling-cells = <2>;     280                         #cooling-cells = <2>;
282                         next-level-cache = <&L    281                         next-level-cache = <&L2_700>;
283                         L2_700: l2-cache {        282                         L2_700: l2-cache {
284                                 compatible = "    283                                 compatible = "cache";
285                                 cache-level =     284                                 cache-level = <2>;
286                                 cache-unified;    285                                 cache-unified;
287                                 next-level-cac    286                                 next-level-cache = <&L3_0>;
288                         };                        287                         };
289                 };                                288                 };
290                                                   289 
291                 cpu-map {                         290                 cpu-map {
292                         cluster0 {                291                         cluster0 {
293                                 core0 {           292                                 core0 {
294                                         cpu =     293                                         cpu = <&CPU0>;
295                                 };                294                                 };
296                                                   295 
297                                 core1 {           296                                 core1 {
298                                         cpu =     297                                         cpu = <&CPU1>;
299                                 };                298                                 };
300                                                   299 
301                                 core2 {           300                                 core2 {
302                                         cpu =     301                                         cpu = <&CPU2>;
303                                 };                302                                 };
304                                                   303 
305                                 core3 {           304                                 core3 {
306                                         cpu =     305                                         cpu = <&CPU3>;
307                                 };                306                                 };
308                                                   307 
309                                 core4 {           308                                 core4 {
310                                         cpu =     309                                         cpu = <&CPU4>;
311                                 };                310                                 };
312                                                   311 
313                                 core5 {           312                                 core5 {
314                                         cpu =     313                                         cpu = <&CPU5>;
315                                 };                314                                 };
316                                                   315 
317                                 core6 {           316                                 core6 {
318                                         cpu =     317                                         cpu = <&CPU6>;
319                                 };                318                                 };
320                                                   319 
321                                 core7 {           320                                 core7 {
322                                         cpu =     321                                         cpu = <&CPU7>;
323                                 };                322                                 };
324                         };                        323                         };
325                 };                                324                 };
326                                                   325 
327                 cpu_idle_states: idle-states {    326                 cpu_idle_states: idle-states {
328                         entry-method = "psci";    327                         entry-method = "psci";
329                                                   328 
330                         LITTLE_CPU_SLEEP_0: cp    329                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331                                 compatible = "    330                                 compatible = "arm,idle-state";
332                                 idle-state-nam    331                                 idle-state-name = "little-rail-power-collapse";
333                                 arm,psci-suspe    332                                 arm,psci-suspend-param = <0x40000004>;
334                                 entry-latency-    333                                 entry-latency-us = <350>;
335                                 exit-latency-u    334                                 exit-latency-us = <461>;
336                                 min-residency-    335                                 min-residency-us = <1890>;
337                                 local-timer-st    336                                 local-timer-stop;
338                         };                        337                         };
339                                                   338 
340                         BIG_CPU_SLEEP_0: cpu-s    339                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341                                 compatible = "    340                                 compatible = "arm,idle-state";
342                                 idle-state-nam    341                                 idle-state-name = "big-rail-power-collapse";
343                                 arm,psci-suspe    342                                 arm,psci-suspend-param = <0x40000004>;
344                                 entry-latency-    343                                 entry-latency-us = <264>;
345                                 exit-latency-u    344                                 exit-latency-us = <621>;
346                                 min-residency-    345                                 min-residency-us = <952>;
347                                 local-timer-st    346                                 local-timer-stop;
348                         };                        347                         };
349                 };                                348                 };
350                                                   349 
351                 domain-idle-states {              350                 domain-idle-states {
352                         CLUSTER_SLEEP_0: clust    351                         CLUSTER_SLEEP_0: cluster-sleep-0 {
353                                 compatible = "    352                                 compatible = "domain-idle-state";
354                                 arm,psci-suspe    353                                 arm,psci-suspend-param = <0x4100c244>;
355                                 entry-latency-    354                                 entry-latency-us = <3263>;
356                                 exit-latency-u    355                                 exit-latency-us = <6562>;
357                                 min-residency-    356                                 min-residency-us = <9987>;
358                         };                        357                         };
359                 };                                358                 };
360         };                                        359         };
361                                                   360 
362         firmware {                                361         firmware {
363                 scm {                             362                 scm {
364                         compatible = "qcom,scm    363                         compatible = "qcom,scm-sdm845", "qcom,scm";
365                 };                                364                 };
366         };                                        365         };
367                                                   366 
368         memory@80000000 {                         367         memory@80000000 {
369                 device_type = "memory";           368                 device_type = "memory";
370                 /* We expect the bootloader to    369                 /* We expect the bootloader to fill in the size */
371                 reg = <0 0x80000000 0 0>;         370                 reg = <0 0x80000000 0 0>;
372         };                                        371         };
373                                                   372 
374         cpu0_opp_table: opp-table-cpu0 {          373         cpu0_opp_table: opp-table-cpu0 {
375                 compatible = "operating-points    374                 compatible = "operating-points-v2";
376                 opp-shared;                       375                 opp-shared;
377                                                   376 
378                 cpu0_opp1: opp-300000000 {        377                 cpu0_opp1: opp-300000000 {
379                         opp-hz = /bits/ 64 <30    378                         opp-hz = /bits/ 64 <300000000>;
380                         opp-peak-kBps = <80000    379                         opp-peak-kBps = <800000 4800000>;
381                 };                                380                 };
382                                                   381 
383                 cpu0_opp2: opp-403200000 {        382                 cpu0_opp2: opp-403200000 {
384                         opp-hz = /bits/ 64 <40    383                         opp-hz = /bits/ 64 <403200000>;
385                         opp-peak-kBps = <80000    384                         opp-peak-kBps = <800000 4800000>;
386                 };                                385                 };
387                                                   386 
388                 cpu0_opp3: opp-480000000 {        387                 cpu0_opp3: opp-480000000 {
389                         opp-hz = /bits/ 64 <48    388                         opp-hz = /bits/ 64 <480000000>;
390                         opp-peak-kBps = <80000    389                         opp-peak-kBps = <800000 6451200>;
391                 };                                390                 };
392                                                   391 
393                 cpu0_opp4: opp-576000000 {        392                 cpu0_opp4: opp-576000000 {
394                         opp-hz = /bits/ 64 <57    393                         opp-hz = /bits/ 64 <576000000>;
395                         opp-peak-kBps = <80000    394                         opp-peak-kBps = <800000 6451200>;
396                 };                                395                 };
397                                                   396 
398                 cpu0_opp5: opp-652800000 {        397                 cpu0_opp5: opp-652800000 {
399                         opp-hz = /bits/ 64 <65    398                         opp-hz = /bits/ 64 <652800000>;
400                         opp-peak-kBps = <80000    399                         opp-peak-kBps = <800000 7680000>;
401                 };                                400                 };
402                                                   401 
403                 cpu0_opp6: opp-748800000 {        402                 cpu0_opp6: opp-748800000 {
404                         opp-hz = /bits/ 64 <74    403                         opp-hz = /bits/ 64 <748800000>;
405                         opp-peak-kBps = <18040    404                         opp-peak-kBps = <1804000 9216000>;
406                 };                                405                 };
407                                                   406 
408                 cpu0_opp7: opp-825600000 {        407                 cpu0_opp7: opp-825600000 {
409                         opp-hz = /bits/ 64 <82    408                         opp-hz = /bits/ 64 <825600000>;
410                         opp-peak-kBps = <18040    409                         opp-peak-kBps = <1804000 9216000>;
411                 };                                410                 };
412                                                   411 
413                 cpu0_opp8: opp-902400000 {        412                 cpu0_opp8: opp-902400000 {
414                         opp-hz = /bits/ 64 <90    413                         opp-hz = /bits/ 64 <902400000>;
415                         opp-peak-kBps = <18040    414                         opp-peak-kBps = <1804000 10444800>;
416                 };                                415                 };
417                                                   416 
418                 cpu0_opp9: opp-979200000 {        417                 cpu0_opp9: opp-979200000 {
419                         opp-hz = /bits/ 64 <97    418                         opp-hz = /bits/ 64 <979200000>;
420                         opp-peak-kBps = <18040    419                         opp-peak-kBps = <1804000 11980800>;
421                 };                                420                 };
422                                                   421 
423                 cpu0_opp10: opp-1056000000 {      422                 cpu0_opp10: opp-1056000000 {
424                         opp-hz = /bits/ 64 <10    423                         opp-hz = /bits/ 64 <1056000000>;
425                         opp-peak-kBps = <18040    424                         opp-peak-kBps = <1804000 11980800>;
426                 };                                425                 };
427                                                   426 
428                 cpu0_opp11: opp-1132800000 {      427                 cpu0_opp11: opp-1132800000 {
429                         opp-hz = /bits/ 64 <11    428                         opp-hz = /bits/ 64 <1132800000>;
430                         opp-peak-kBps = <21880    429                         opp-peak-kBps = <2188000 13516800>;
431                 };                                430                 };
432                                                   431 
433                 cpu0_opp12: opp-1228800000 {      432                 cpu0_opp12: opp-1228800000 {
434                         opp-hz = /bits/ 64 <12    433                         opp-hz = /bits/ 64 <1228800000>;
435                         opp-peak-kBps = <21880    434                         opp-peak-kBps = <2188000 15052800>;
436                 };                                435                 };
437                                                   436 
438                 cpu0_opp13: opp-1324800000 {      437                 cpu0_opp13: opp-1324800000 {
439                         opp-hz = /bits/ 64 <13    438                         opp-hz = /bits/ 64 <1324800000>;
440                         opp-peak-kBps = <21880    439                         opp-peak-kBps = <2188000 16588800>;
441                 };                                440                 };
442                                                   441 
443                 cpu0_opp14: opp-1420800000 {      442                 cpu0_opp14: opp-1420800000 {
444                         opp-hz = /bits/ 64 <14    443                         opp-hz = /bits/ 64 <1420800000>;
445                         opp-peak-kBps = <30720    444                         opp-peak-kBps = <3072000 18124800>;
446                 };                                445                 };
447                                                   446 
448                 cpu0_opp15: opp-1516800000 {      447                 cpu0_opp15: opp-1516800000 {
449                         opp-hz = /bits/ 64 <15    448                         opp-hz = /bits/ 64 <1516800000>;
450                         opp-peak-kBps = <30720    449                         opp-peak-kBps = <3072000 19353600>;
451                 };                                450                 };
452                                                   451 
453                 cpu0_opp16: opp-1612800000 {      452                 cpu0_opp16: opp-1612800000 {
454                         opp-hz = /bits/ 64 <16    453                         opp-hz = /bits/ 64 <1612800000>;
455                         opp-peak-kBps = <40680    454                         opp-peak-kBps = <4068000 19353600>;
456                 };                                455                 };
457                                                   456 
458                 cpu0_opp17: opp-1689600000 {      457                 cpu0_opp17: opp-1689600000 {
459                         opp-hz = /bits/ 64 <16    458                         opp-hz = /bits/ 64 <1689600000>;
460                         opp-peak-kBps = <40680    459                         opp-peak-kBps = <4068000 20889600>;
461                 };                                460                 };
462                                                   461 
463                 cpu0_opp18: opp-1766400000 {      462                 cpu0_opp18: opp-1766400000 {
464                         opp-hz = /bits/ 64 <17    463                         opp-hz = /bits/ 64 <1766400000>;
465                         opp-peak-kBps = <40680    464                         opp-peak-kBps = <4068000 22425600>;
466                 };                                465                 };
467         };                                        466         };
468                                                   467 
469         cpu4_opp_table: opp-table-cpu4 {          468         cpu4_opp_table: opp-table-cpu4 {
470                 compatible = "operating-points    469                 compatible = "operating-points-v2";
471                 opp-shared;                       470                 opp-shared;
472                                                   471 
473                 cpu4_opp1: opp-300000000 {        472                 cpu4_opp1: opp-300000000 {
474                         opp-hz = /bits/ 64 <30    473                         opp-hz = /bits/ 64 <300000000>;
475                         opp-peak-kBps = <80000    474                         opp-peak-kBps = <800000 4800000>;
476                 };                                475                 };
477                                                   476 
478                 cpu4_opp2: opp-403200000 {        477                 cpu4_opp2: opp-403200000 {
479                         opp-hz = /bits/ 64 <40    478                         opp-hz = /bits/ 64 <403200000>;
480                         opp-peak-kBps = <80000    479                         opp-peak-kBps = <800000 4800000>;
481                 };                                480                 };
482                                                   481 
483                 cpu4_opp3: opp-480000000 {        482                 cpu4_opp3: opp-480000000 {
484                         opp-hz = /bits/ 64 <48    483                         opp-hz = /bits/ 64 <480000000>;
485                         opp-peak-kBps = <18040    484                         opp-peak-kBps = <1804000 4800000>;
486                 };                                485                 };
487                                                   486 
488                 cpu4_opp4: opp-576000000 {        487                 cpu4_opp4: opp-576000000 {
489                         opp-hz = /bits/ 64 <57    488                         opp-hz = /bits/ 64 <576000000>;
490                         opp-peak-kBps = <18040    489                         opp-peak-kBps = <1804000 4800000>;
491                 };                                490                 };
492                                                   491 
493                 cpu4_opp5: opp-652800000 {        492                 cpu4_opp5: opp-652800000 {
494                         opp-hz = /bits/ 64 <65    493                         opp-hz = /bits/ 64 <652800000>;
495                         opp-peak-kBps = <18040    494                         opp-peak-kBps = <1804000 4800000>;
496                 };                                495                 };
497                                                   496 
498                 cpu4_opp6: opp-748800000 {        497                 cpu4_opp6: opp-748800000 {
499                         opp-hz = /bits/ 64 <74    498                         opp-hz = /bits/ 64 <748800000>;
500                         opp-peak-kBps = <18040    499                         opp-peak-kBps = <1804000 4800000>;
501                 };                                500                 };
502                                                   501 
503                 cpu4_opp7: opp-825600000 {        502                 cpu4_opp7: opp-825600000 {
504                         opp-hz = /bits/ 64 <82    503                         opp-hz = /bits/ 64 <825600000>;
505                         opp-peak-kBps = <21880    504                         opp-peak-kBps = <2188000 9216000>;
506                 };                                505                 };
507                                                   506 
508                 cpu4_opp8: opp-902400000 {        507                 cpu4_opp8: opp-902400000 {
509                         opp-hz = /bits/ 64 <90    508                         opp-hz = /bits/ 64 <902400000>;
510                         opp-peak-kBps = <21880    509                         opp-peak-kBps = <2188000 9216000>;
511                 };                                510                 };
512                                                   511 
513                 cpu4_opp9: opp-979200000 {        512                 cpu4_opp9: opp-979200000 {
514                         opp-hz = /bits/ 64 <97    513                         opp-hz = /bits/ 64 <979200000>;
515                         opp-peak-kBps = <21880    514                         opp-peak-kBps = <2188000 9216000>;
516                 };                                515                 };
517                                                   516 
518                 cpu4_opp10: opp-1056000000 {      517                 cpu4_opp10: opp-1056000000 {
519                         opp-hz = /bits/ 64 <10    518                         opp-hz = /bits/ 64 <1056000000>;
520                         opp-peak-kBps = <30720    519                         opp-peak-kBps = <3072000 9216000>;
521                 };                                520                 };
522                                                   521 
523                 cpu4_opp11: opp-1132800000 {      522                 cpu4_opp11: opp-1132800000 {
524                         opp-hz = /bits/ 64 <11    523                         opp-hz = /bits/ 64 <1132800000>;
525                         opp-peak-kBps = <30720    524                         opp-peak-kBps = <3072000 11980800>;
526                 };                                525                 };
527                                                   526 
528                 cpu4_opp12: opp-1209600000 {      527                 cpu4_opp12: opp-1209600000 {
529                         opp-hz = /bits/ 64 <12    528                         opp-hz = /bits/ 64 <1209600000>;
530                         opp-peak-kBps = <40680    529                         opp-peak-kBps = <4068000 11980800>;
531                 };                                530                 };
532                                                   531 
533                 cpu4_opp13: opp-1286400000 {      532                 cpu4_opp13: opp-1286400000 {
534                         opp-hz = /bits/ 64 <12    533                         opp-hz = /bits/ 64 <1286400000>;
535                         opp-peak-kBps = <40680    534                         opp-peak-kBps = <4068000 11980800>;
536                 };                                535                 };
537                                                   536 
538                 cpu4_opp14: opp-1363200000 {      537                 cpu4_opp14: opp-1363200000 {
539                         opp-hz = /bits/ 64 <13    538                         opp-hz = /bits/ 64 <1363200000>;
540                         opp-peak-kBps = <40680    539                         opp-peak-kBps = <4068000 15052800>;
541                 };                                540                 };
542                                                   541 
543                 cpu4_opp15: opp-1459200000 {      542                 cpu4_opp15: opp-1459200000 {
544                         opp-hz = /bits/ 64 <14    543                         opp-hz = /bits/ 64 <1459200000>;
545                         opp-peak-kBps = <40680    544                         opp-peak-kBps = <4068000 15052800>;
546                 };                                545                 };
547                                                   546 
548                 cpu4_opp16: opp-1536000000 {      547                 cpu4_opp16: opp-1536000000 {
549                         opp-hz = /bits/ 64 <15    548                         opp-hz = /bits/ 64 <1536000000>;
550                         opp-peak-kBps = <54120    549                         opp-peak-kBps = <5412000 15052800>;
551                 };                                550                 };
552                                                   551 
553                 cpu4_opp17: opp-1612800000 {      552                 cpu4_opp17: opp-1612800000 {
554                         opp-hz = /bits/ 64 <16    553                         opp-hz = /bits/ 64 <1612800000>;
555                         opp-peak-kBps = <54120    554                         opp-peak-kBps = <5412000 15052800>;
556                 };                                555                 };
557                                                   556 
558                 cpu4_opp18: opp-1689600000 {      557                 cpu4_opp18: opp-1689600000 {
559                         opp-hz = /bits/ 64 <16    558                         opp-hz = /bits/ 64 <1689600000>;
560                         opp-peak-kBps = <54120    559                         opp-peak-kBps = <5412000 19353600>;
561                 };                                560                 };
562                                                   561 
563                 cpu4_opp19: opp-1766400000 {      562                 cpu4_opp19: opp-1766400000 {
564                         opp-hz = /bits/ 64 <17    563                         opp-hz = /bits/ 64 <1766400000>;
565                         opp-peak-kBps = <62200    564                         opp-peak-kBps = <6220000 19353600>;
566                 };                                565                 };
567                                                   566 
568                 cpu4_opp20: opp-1843200000 {      567                 cpu4_opp20: opp-1843200000 {
569                         opp-hz = /bits/ 64 <18    568                         opp-hz = /bits/ 64 <1843200000>;
570                         opp-peak-kBps = <62200    569                         opp-peak-kBps = <6220000 19353600>;
571                 };                                570                 };
572                                                   571 
573                 cpu4_opp21: opp-1920000000 {      572                 cpu4_opp21: opp-1920000000 {
574                         opp-hz = /bits/ 64 <19    573                         opp-hz = /bits/ 64 <1920000000>;
575                         opp-peak-kBps = <72160    574                         opp-peak-kBps = <7216000 19353600>;
576                 };                                575                 };
577                                                   576 
578                 cpu4_opp22: opp-1996800000 {      577                 cpu4_opp22: opp-1996800000 {
579                         opp-hz = /bits/ 64 <19    578                         opp-hz = /bits/ 64 <1996800000>;
580                         opp-peak-kBps = <72160    579                         opp-peak-kBps = <7216000 20889600>;
581                 };                                580                 };
582                                                   581 
583                 cpu4_opp23: opp-2092800000 {      582                 cpu4_opp23: opp-2092800000 {
584                         opp-hz = /bits/ 64 <20    583                         opp-hz = /bits/ 64 <2092800000>;
585                         opp-peak-kBps = <72160    584                         opp-peak-kBps = <7216000 20889600>;
586                 };                                585                 };
587                                                   586 
588                 cpu4_opp24: opp-2169600000 {      587                 cpu4_opp24: opp-2169600000 {
589                         opp-hz = /bits/ 64 <21    588                         opp-hz = /bits/ 64 <2169600000>;
590                         opp-peak-kBps = <72160    589                         opp-peak-kBps = <7216000 20889600>;
591                 };                                590                 };
592                                                   591 
593                 cpu4_opp25: opp-2246400000 {      592                 cpu4_opp25: opp-2246400000 {
594                         opp-hz = /bits/ 64 <22    593                         opp-hz = /bits/ 64 <2246400000>;
595                         opp-peak-kBps = <72160    594                         opp-peak-kBps = <7216000 20889600>;
596                 };                                595                 };
597                                                   596 
598                 cpu4_opp26: opp-2323200000 {      597                 cpu4_opp26: opp-2323200000 {
599                         opp-hz = /bits/ 64 <23    598                         opp-hz = /bits/ 64 <2323200000>;
600                         opp-peak-kBps = <72160    599                         opp-peak-kBps = <7216000 20889600>;
601                 };                                600                 };
602                                                   601 
603                 cpu4_opp27: opp-2400000000 {      602                 cpu4_opp27: opp-2400000000 {
604                         opp-hz = /bits/ 64 <24    603                         opp-hz = /bits/ 64 <2400000000>;
605                         opp-peak-kBps = <72160    604                         opp-peak-kBps = <7216000 22425600>;
606                 };                                605                 };
607                                                   606 
608                 cpu4_opp28: opp-2476800000 {      607                 cpu4_opp28: opp-2476800000 {
609                         opp-hz = /bits/ 64 <24    608                         opp-hz = /bits/ 64 <2476800000>;
610                         opp-peak-kBps = <72160    609                         opp-peak-kBps = <7216000 22425600>;
611                 };                                610                 };
612                                                   611 
613                 cpu4_opp29: opp-2553600000 {      612                 cpu4_opp29: opp-2553600000 {
614                         opp-hz = /bits/ 64 <25    613                         opp-hz = /bits/ 64 <2553600000>;
615                         opp-peak-kBps = <72160    614                         opp-peak-kBps = <7216000 22425600>;
616                 };                                615                 };
617                                                   616 
618                 cpu4_opp30: opp-2649600000 {      617                 cpu4_opp30: opp-2649600000 {
619                         opp-hz = /bits/ 64 <26    618                         opp-hz = /bits/ 64 <2649600000>;
620                         opp-peak-kBps = <72160    619                         opp-peak-kBps = <7216000 22425600>;
621                 };                                620                 };
622                                                   621 
623                 cpu4_opp31: opp-2745600000 {      622                 cpu4_opp31: opp-2745600000 {
624                         opp-hz = /bits/ 64 <27    623                         opp-hz = /bits/ 64 <2745600000>;
625                         opp-peak-kBps = <72160    624                         opp-peak-kBps = <7216000 25497600>;
626                 };                                625                 };
627                                                   626 
628                 cpu4_opp32: opp-2803200000 {      627                 cpu4_opp32: opp-2803200000 {
629                         opp-hz = /bits/ 64 <28    628                         opp-hz = /bits/ 64 <2803200000>;
630                         opp-peak-kBps = <72160    629                         opp-peak-kBps = <7216000 25497600>;
631                 };                                630                 };
632         };                                        631         };
633                                                   632 
634         dsi_opp_table: opp-table-dsi {            633         dsi_opp_table: opp-table-dsi {
635                 compatible = "operating-points    634                 compatible = "operating-points-v2";
636                                                   635 
637                 opp-19200000 {                    636                 opp-19200000 {
638                         opp-hz = /bits/ 64 <19    637                         opp-hz = /bits/ 64 <19200000>;
639                         required-opps = <&rpmh    638                         required-opps = <&rpmhpd_opp_min_svs>;
640                 };                                639                 };
641                                                   640 
642                 opp-180000000 {                   641                 opp-180000000 {
643                         opp-hz = /bits/ 64 <18    642                         opp-hz = /bits/ 64 <180000000>;
644                         required-opps = <&rpmh    643                         required-opps = <&rpmhpd_opp_low_svs>;
645                 };                                644                 };
646                                                   645 
647                 opp-275000000 {                   646                 opp-275000000 {
648                         opp-hz = /bits/ 64 <27    647                         opp-hz = /bits/ 64 <275000000>;
649                         required-opps = <&rpmh    648                         required-opps = <&rpmhpd_opp_svs>;
650                 };                                649                 };
651                                                   650 
652                 opp-328580000 {                   651                 opp-328580000 {
653                         opp-hz = /bits/ 64 <32    652                         opp-hz = /bits/ 64 <328580000>;
654                         required-opps = <&rpmh    653                         required-opps = <&rpmhpd_opp_svs_l1>;
655                 };                                654                 };
656                                                   655 
657                 opp-358000000 {                   656                 opp-358000000 {
658                         opp-hz = /bits/ 64 <35    657                         opp-hz = /bits/ 64 <358000000>;
659                         required-opps = <&rpmh    658                         required-opps = <&rpmhpd_opp_nom>;
660                 };                                659                 };
661         };                                        660         };
662                                                   661 
663         qspi_opp_table: opp-table-qspi {          662         qspi_opp_table: opp-table-qspi {
664                 compatible = "operating-points    663                 compatible = "operating-points-v2";
665                                                   664 
666                 opp-19200000 {                    665                 opp-19200000 {
667                         opp-hz = /bits/ 64 <19    666                         opp-hz = /bits/ 64 <19200000>;
668                         required-opps = <&rpmh    667                         required-opps = <&rpmhpd_opp_min_svs>;
669                 };                                668                 };
670                                                   669 
671                 opp-100000000 {                   670                 opp-100000000 {
672                         opp-hz = /bits/ 64 <10    671                         opp-hz = /bits/ 64 <100000000>;
673                         required-opps = <&rpmh    672                         required-opps = <&rpmhpd_opp_low_svs>;
674                 };                                673                 };
675                                                   674 
676                 opp-150000000 {                   675                 opp-150000000 {
677                         opp-hz = /bits/ 64 <15    676                         opp-hz = /bits/ 64 <150000000>;
678                         required-opps = <&rpmh    677                         required-opps = <&rpmhpd_opp_svs>;
679                 };                                678                 };
680                                                   679 
681                 opp-300000000 {                   680                 opp-300000000 {
682                         opp-hz = /bits/ 64 <30    681                         opp-hz = /bits/ 64 <300000000>;
683                         required-opps = <&rpmh    682                         required-opps = <&rpmhpd_opp_nom>;
684                 };                                683                 };
685         };                                        684         };
686                                                   685 
687         qup_opp_table: opp-table-qup {            686         qup_opp_table: opp-table-qup {
688                 compatible = "operating-points    687                 compatible = "operating-points-v2";
689                                                   688 
690                 opp-50000000 {                    689                 opp-50000000 {
691                         opp-hz = /bits/ 64 <50    690                         opp-hz = /bits/ 64 <50000000>;
692                         required-opps = <&rpmh    691                         required-opps = <&rpmhpd_opp_min_svs>;
693                 };                                692                 };
694                                                   693 
695                 opp-75000000 {                    694                 opp-75000000 {
696                         opp-hz = /bits/ 64 <75    695                         opp-hz = /bits/ 64 <75000000>;
697                         required-opps = <&rpmh    696                         required-opps = <&rpmhpd_opp_low_svs>;
698                 };                                697                 };
699                                                   698 
700                 opp-100000000 {                   699                 opp-100000000 {
701                         opp-hz = /bits/ 64 <10    700                         opp-hz = /bits/ 64 <100000000>;
702                         required-opps = <&rpmh    701                         required-opps = <&rpmhpd_opp_svs>;
703                 };                                702                 };
704                                                   703 
705                 opp-128000000 {                   704                 opp-128000000 {
706                         opp-hz = /bits/ 64 <12    705                         opp-hz = /bits/ 64 <128000000>;
707                         required-opps = <&rpmh    706                         required-opps = <&rpmhpd_opp_nom>;
708                 };                                707                 };
709         };                                        708         };
710                                                   709 
711         pmu {                                     710         pmu {
712                 compatible = "arm,armv8-pmuv3"    711                 compatible = "arm,armv8-pmuv3";
713                 interrupts = <GIC_PPI 5 IRQ_TY    712                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714         };                                        713         };
715                                                   714 
716         psci: psci {                              715         psci: psci {
717                 compatible = "arm,psci-1.0";      716                 compatible = "arm,psci-1.0";
718                 method = "smc";                   717                 method = "smc";
719                                                   718 
720                 CPU_PD0: power-domain-cpu0 {      719                 CPU_PD0: power-domain-cpu0 {
721                         #power-domain-cells =     720                         #power-domain-cells = <0>;
722                         power-domains = <&CLUS    721                         power-domains = <&CLUSTER_PD>;
723                         domain-idle-states = <    722                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
724                 };                                723                 };
725                                                   724 
726                 CPU_PD1: power-domain-cpu1 {      725                 CPU_PD1: power-domain-cpu1 {
727                         #power-domain-cells =     726                         #power-domain-cells = <0>;
728                         power-domains = <&CLUS    727                         power-domains = <&CLUSTER_PD>;
729                         domain-idle-states = <    728                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
730                 };                                729                 };
731                                                   730 
732                 CPU_PD2: power-domain-cpu2 {      731                 CPU_PD2: power-domain-cpu2 {
733                         #power-domain-cells =     732                         #power-domain-cells = <0>;
734                         power-domains = <&CLUS    733                         power-domains = <&CLUSTER_PD>;
735                         domain-idle-states = <    734                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
736                 };                                735                 };
737                                                   736 
738                 CPU_PD3: power-domain-cpu3 {      737                 CPU_PD3: power-domain-cpu3 {
739                         #power-domain-cells =     738                         #power-domain-cells = <0>;
740                         power-domains = <&CLUS    739                         power-domains = <&CLUSTER_PD>;
741                         domain-idle-states = <    740                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
742                 };                                741                 };
743                                                   742 
744                 CPU_PD4: power-domain-cpu4 {      743                 CPU_PD4: power-domain-cpu4 {
745                         #power-domain-cells =     744                         #power-domain-cells = <0>;
746                         power-domains = <&CLUS    745                         power-domains = <&CLUSTER_PD>;
747                         domain-idle-states = <    746                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
748                 };                                747                 };
749                                                   748 
750                 CPU_PD5: power-domain-cpu5 {      749                 CPU_PD5: power-domain-cpu5 {
751                         #power-domain-cells =     750                         #power-domain-cells = <0>;
752                         power-domains = <&CLUS    751                         power-domains = <&CLUSTER_PD>;
753                         domain-idle-states = <    752                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
754                 };                                753                 };
755                                                   754 
756                 CPU_PD6: power-domain-cpu6 {      755                 CPU_PD6: power-domain-cpu6 {
757                         #power-domain-cells =     756                         #power-domain-cells = <0>;
758                         power-domains = <&CLUS    757                         power-domains = <&CLUSTER_PD>;
759                         domain-idle-states = <    758                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
760                 };                                759                 };
761                                                   760 
762                 CPU_PD7: power-domain-cpu7 {      761                 CPU_PD7: power-domain-cpu7 {
763                         #power-domain-cells =     762                         #power-domain-cells = <0>;
764                         power-domains = <&CLUS    763                         power-domains = <&CLUSTER_PD>;
765                         domain-idle-states = <    764                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
766                 };                                765                 };
767                                                   766 
768                 CLUSTER_PD: power-domain-clust    767                 CLUSTER_PD: power-domain-cluster {
769                         #power-domain-cells =     768                         #power-domain-cells = <0>;
770                         domain-idle-states = <    769                         domain-idle-states = <&CLUSTER_SLEEP_0>;
771                 };                                770                 };
772         };                                        771         };
773                                                   772 
774         reserved-memory {                         773         reserved-memory {
775                 #address-cells = <2>;             774                 #address-cells = <2>;
776                 #size-cells = <2>;                775                 #size-cells = <2>;
777                 ranges;                           776                 ranges;
778                                                   777 
779                 hyp_mem: hyp-mem@85700000 {       778                 hyp_mem: hyp-mem@85700000 {
780                         reg = <0 0x85700000 0     779                         reg = <0 0x85700000 0 0x600000>;
781                         no-map;                   780                         no-map;
782                 };                                781                 };
783                                                   782 
784                 xbl_mem: xbl-mem@85e00000 {       783                 xbl_mem: xbl-mem@85e00000 {
785                         reg = <0 0x85e00000 0     784                         reg = <0 0x85e00000 0 0x100000>;
786                         no-map;                   785                         no-map;
787                 };                                786                 };
788                                                   787 
789                 aop_mem: aop-mem@85fc0000 {       788                 aop_mem: aop-mem@85fc0000 {
790                         reg = <0 0x85fc0000 0     789                         reg = <0 0x85fc0000 0 0x20000>;
791                         no-map;                   790                         no-map;
792                 };                                791                 };
793                                                   792 
794                 aop_cmd_db_mem: aop-cmd-db-mem    793                 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
795                         compatible = "qcom,cmd    794                         compatible = "qcom,cmd-db";
796                         reg = <0x0 0x85fe0000     795                         reg = <0x0 0x85fe0000 0 0x20000>;
797                         no-map;                   796                         no-map;
798                 };                                797                 };
799                                                   798 
800                 smem@86000000 {                   799                 smem@86000000 {
801                         compatible = "qcom,sme    800                         compatible = "qcom,smem";
802                         reg = <0x0 0x86000000     801                         reg = <0x0 0x86000000 0 0x200000>;
803                         no-map;                   802                         no-map;
804                         hwlocks = <&tcsr_mutex    803                         hwlocks = <&tcsr_mutex 3>;
805                 };                                804                 };
806                                                   805 
807                 tz_mem: tz@86200000 {             806                 tz_mem: tz@86200000 {
808                         reg = <0 0x86200000 0     807                         reg = <0 0x86200000 0 0x2d00000>;
809                         no-map;                   808                         no-map;
810                 };                                809                 };
811                                                   810 
812                 rmtfs_mem: rmtfs@88f00000 {       811                 rmtfs_mem: rmtfs@88f00000 {
813                         compatible = "qcom,rmt    812                         compatible = "qcom,rmtfs-mem";
814                         reg = <0 0x88f00000 0     813                         reg = <0 0x88f00000 0 0x200000>;
815                         no-map;                   814                         no-map;
816                                                   815 
817                         qcom,client-id = <1>;     816                         qcom,client-id = <1>;
818                         qcom,vmid = <QCOM_SCM_    817                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
819                 };                                818                 };
820                                                   819 
821                 qseecom_mem: qseecom@8ab00000     820                 qseecom_mem: qseecom@8ab00000 {
822                         reg = <0 0x8ab00000 0     821                         reg = <0 0x8ab00000 0 0x1400000>;
823                         no-map;                   822                         no-map;
824                 };                                823                 };
825                                                   824 
826                 camera_mem: camera-mem@8bf0000    825                 camera_mem: camera-mem@8bf00000 {
827                         reg = <0 0x8bf00000 0     826                         reg = <0 0x8bf00000 0 0x500000>;
828                         no-map;                   827                         no-map;
829                 };                                828                 };
830                                                   829 
831                 ipa_fw_mem: ipa-fw@8c400000 {     830                 ipa_fw_mem: ipa-fw@8c400000 {
832                         reg = <0 0x8c400000 0     831                         reg = <0 0x8c400000 0 0x10000>;
833                         no-map;                   832                         no-map;
834                 };                                833                 };
835                                                   834 
836                 ipa_gsi_mem: ipa-gsi@8c410000     835                 ipa_gsi_mem: ipa-gsi@8c410000 {
837                         reg = <0 0x8c410000 0     836                         reg = <0 0x8c410000 0 0x5000>;
838                         no-map;                   837                         no-map;
839                 };                                838                 };
840                                                   839 
841                 gpu_mem: gpu@8c415000 {           840                 gpu_mem: gpu@8c415000 {
842                         reg = <0 0x8c415000 0     841                         reg = <0 0x8c415000 0 0x2000>;
843                         no-map;                   842                         no-map;
844                 };                                843                 };
845                                                   844 
846                 adsp_mem: adsp@8c500000 {         845                 adsp_mem: adsp@8c500000 {
847                         reg = <0 0x8c500000 0     846                         reg = <0 0x8c500000 0 0x1a00000>;
848                         no-map;                   847                         no-map;
849                 };                                848                 };
850                                                   849 
851                 wlan_msa_mem: wlan-msa@8df0000    850                 wlan_msa_mem: wlan-msa@8df00000 {
852                         reg = <0 0x8df00000 0     851                         reg = <0 0x8df00000 0 0x100000>;
853                         no-map;                   852                         no-map;
854                 };                                853                 };
855                                                   854 
856                 mpss_region: mpss@8e000000 {      855                 mpss_region: mpss@8e000000 {
857                         reg = <0 0x8e000000 0     856                         reg = <0 0x8e000000 0 0x7800000>;
858                         no-map;                   857                         no-map;
859                 };                                858                 };
860                                                   859 
861                 venus_mem: venus@95800000 {       860                 venus_mem: venus@95800000 {
862                         reg = <0 0x95800000 0     861                         reg = <0 0x95800000 0 0x500000>;
863                         no-map;                   862                         no-map;
864                 };                                863                 };
865                                                   864 
866                 cdsp_mem: cdsp@95d00000 {         865                 cdsp_mem: cdsp@95d00000 {
867                         reg = <0 0x95d00000 0     866                         reg = <0 0x95d00000 0 0x800000>;
868                         no-map;                   867                         no-map;
869                 };                                868                 };
870                                                   869 
871                 mba_region: mba@96500000 {        870                 mba_region: mba@96500000 {
872                         reg = <0 0x96500000 0     871                         reg = <0 0x96500000 0 0x200000>;
873                         no-map;                   872                         no-map;
874                 };                                873                 };
875                                                   874 
876                 slpi_mem: slpi@96700000 {         875                 slpi_mem: slpi@96700000 {
877                         reg = <0 0x96700000 0     876                         reg = <0 0x96700000 0 0x1400000>;
878                         no-map;                   877                         no-map;
879                 };                                878                 };
880                                                   879 
881                 spss_mem: spss@97b00000 {         880                 spss_mem: spss@97b00000 {
882                         reg = <0 0x97b00000 0     881                         reg = <0 0x97b00000 0 0x100000>;
883                         no-map;                   882                         no-map;
884                 };                                883                 };
885                                                   884 
886                 mdata_mem: mpss-metadata {        885                 mdata_mem: mpss-metadata {
887                         alloc-ranges = <0 0xa0    886                         alloc-ranges = <0 0xa0000000 0 0x20000000>;
888                         size = <0 0x4000>;        887                         size = <0 0x4000>;
889                         no-map;                   888                         no-map;
890                 };                                889                 };
891                                                   890 
892                 fastrpc_mem: fastrpc {            891                 fastrpc_mem: fastrpc {
893                         compatible = "shared-d    892                         compatible = "shared-dma-pool";
894                         alloc-ranges = <0x0 0x    893                         alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
895                         alignment = <0x0 0x400    894                         alignment = <0x0 0x400000>;
896                         size = <0x0 0x1000000>    895                         size = <0x0 0x1000000>;
897                         reusable;                 896                         reusable;
898                 };                                897                 };
899         };                                        898         };
900                                                   899 
901         adsp_pas: remoteproc-adsp {               900         adsp_pas: remoteproc-adsp {
902                 compatible = "qcom,sdm845-adsp    901                 compatible = "qcom,sdm845-adsp-pas";
903                                                   902 
904                 interrupts-extended = <&intc G    903                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905                                       <&adsp_s    904                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906                                       <&adsp_s    905                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907                                       <&adsp_s    906                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908                                       <&adsp_s    907                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909                 interrupt-names = "wdog", "fat    908                 interrupt-names = "wdog", "fatal", "ready",
910                                   "handover",     909                                   "handover", "stop-ack";
911                                                   910 
912                 clocks = <&rpmhcc RPMH_CXO_CLK    911                 clocks = <&rpmhcc RPMH_CXO_CLK>;
913                 clock-names = "xo";               912                 clock-names = "xo";
914                                                   913 
915                 memory-region = <&adsp_mem>;      914                 memory-region = <&adsp_mem>;
916                                                   915 
917                 qcom,qmp = <&aoss_qmp>;           916                 qcom,qmp = <&aoss_qmp>;
918                                                   917 
919                 qcom,smem-states = <&adsp_smp2    918                 qcom,smem-states = <&adsp_smp2p_out 0>;
920                 qcom,smem-state-names = "stop"    919                 qcom,smem-state-names = "stop";
921                                                   920 
922                 status = "disabled";              921                 status = "disabled";
923                                                   922 
924                 glink-edge {                      923                 glink-edge {
925                         interrupts = <GIC_SPI     924                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926                         label = "lpass";          925                         label = "lpass";
927                         qcom,remote-pid = <2>;    926                         qcom,remote-pid = <2>;
928                         mboxes = <&apss_shared    927                         mboxes = <&apss_shared 8>;
929                                                   928 
930                         apr {                     929                         apr {
931                                 compatible = "    930                                 compatible = "qcom,apr-v2";
932                                 qcom,glink-cha    931                                 qcom,glink-channels = "apr_audio_svc";
933                                 qcom,domain =     932                                 qcom,domain = <APR_DOMAIN_ADSP>;
934                                 #address-cells    933                                 #address-cells = <1>;
935                                 #size-cells =     934                                 #size-cells = <0>;
936                                 qcom,intents =    935                                 qcom,intents = <512 20>;
937                                                   936 
938                                 service@3 {       937                                 service@3 {
939                                         reg =     938                                         reg = <APR_SVC_ADSP_CORE>;
940                                         compat    939                                         compatible = "qcom,q6core";
941                                         qcom,p    940                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942                                 };                941                                 };
943                                                   942 
944                                 q6afe: service    943                                 q6afe: service@4 {
945                                         compat    944                                         compatible = "qcom,q6afe";
946                                         reg =     945                                         reg = <APR_SVC_AFE>;
947                                         qcom,p    946                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948                                         q6afed    947                                         q6afedai: dais {
949                                                   948                                                 compatible = "qcom,q6afe-dais";
950                                                   949                                                 #address-cells = <1>;
951                                                   950                                                 #size-cells = <0>;
952                                                   951                                                 #sound-dai-cells = <1>;
953                                         };        952                                         };
954                                 };                953                                 };
955                                                   954 
956                                 q6asm: service    955                                 q6asm: service@7 {
957                                         compat    956                                         compatible = "qcom,q6asm";
958                                         reg =     957                                         reg = <APR_SVC_ASM>;
959                                         qcom,p    958                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960                                         q6asmd    959                                         q6asmdai: dais {
961                                                   960                                                 compatible = "qcom,q6asm-dais";
962                                                   961                                                 #address-cells = <1>;
963                                                   962                                                 #size-cells = <0>;
964                                                   963                                                 #sound-dai-cells = <1>;
965                                                   964                                                 iommus = <&apps_smmu 0x1821 0x0>;
966                                         };        965                                         };
967                                 };                966                                 };
968                                                   967 
969                                 q6adm: service    968                                 q6adm: service@8 {
970                                         compat    969                                         compatible = "qcom,q6adm";
971                                         reg =     970                                         reg = <APR_SVC_ADM>;
972                                         qcom,p    971                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973                                         q6rout    972                                         q6routing: routing {
974                                                   973                                                 compatible = "qcom,q6adm-routing";
975                                                   974                                                 #sound-dai-cells = <0>;
976                                         };        975                                         };
977                                 };                976                                 };
978                         };                        977                         };
979                                                   978 
980                         fastrpc {                 979                         fastrpc {
981                                 compatible = "    980                                 compatible = "qcom,fastrpc";
982                                 qcom,glink-cha    981                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
983                                 label = "adsp"    982                                 label = "adsp";
984                                 qcom,non-secur    983                                 qcom,non-secure-domain;
985                                 #address-cells    984                                 #address-cells = <1>;
986                                 #size-cells =     985                                 #size-cells = <0>;
987                                                   986 
988                                 compute-cb@3 {    987                                 compute-cb@3 {
989                                         compat    988                                         compatible = "qcom,fastrpc-compute-cb";
990                                         reg =     989                                         reg = <3>;
991                                         iommus    990                                         iommus = <&apps_smmu 0x1823 0x0>;
992                                 };                991                                 };
993                                                   992 
994                                 compute-cb@4 {    993                                 compute-cb@4 {
995                                         compat    994                                         compatible = "qcom,fastrpc-compute-cb";
996                                         reg =     995                                         reg = <4>;
997                                         iommus    996                                         iommus = <&apps_smmu 0x1824 0x0>;
998                                 };                997                                 };
999                         };                        998                         };
1000                 };                               999                 };
1001         };                                       1000         };
1002                                                  1001 
1003         cdsp_pas: remoteproc-cdsp {              1002         cdsp_pas: remoteproc-cdsp {
1004                 compatible = "qcom,sdm845-cds    1003                 compatible = "qcom,sdm845-cdsp-pas";
1005                                                  1004 
1006                 interrupts-extended = <&intc     1005                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007                                       <&cdsp_    1006                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008                                       <&cdsp_    1007                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009                                       <&cdsp_    1008                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010                                       <&cdsp_    1009                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011                 interrupt-names = "wdog", "fa    1010                 interrupt-names = "wdog", "fatal", "ready",
1012                                   "handover",    1011                                   "handover", "stop-ack";
1013                                                  1012 
1014                 clocks = <&rpmhcc RPMH_CXO_CL    1013                 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015                 clock-names = "xo";              1014                 clock-names = "xo";
1016                                                  1015 
1017                 memory-region = <&cdsp_mem>;     1016                 memory-region = <&cdsp_mem>;
1018                                                  1017 
1019                 qcom,qmp = <&aoss_qmp>;          1018                 qcom,qmp = <&aoss_qmp>;
1020                                                  1019 
1021                 qcom,smem-states = <&cdsp_smp    1020                 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022                 qcom,smem-state-names = "stop    1021                 qcom,smem-state-names = "stop";
1023                                                  1022 
1024                 status = "disabled";             1023                 status = "disabled";
1025                                                  1024 
1026                 glink-edge {                     1025                 glink-edge {
1027                         interrupts = <GIC_SPI    1026                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028                         label = "turing";        1027                         label = "turing";
1029                         qcom,remote-pid = <5>    1028                         qcom,remote-pid = <5>;
1030                         mboxes = <&apss_share    1029                         mboxes = <&apss_shared 4>;
1031                         fastrpc {                1030                         fastrpc {
1032                                 compatible =     1031                                 compatible = "qcom,fastrpc";
1033                                 qcom,glink-ch    1032                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034                                 label = "cdsp    1033                                 label = "cdsp";
1035                                 qcom,non-secu    1034                                 qcom,non-secure-domain;
1036                                 #address-cell    1035                                 #address-cells = <1>;
1037                                 #size-cells =    1036                                 #size-cells = <0>;
1038                                                  1037 
1039                                 compute-cb@1     1038                                 compute-cb@1 {
1040                                         compa    1039                                         compatible = "qcom,fastrpc-compute-cb";
1041                                         reg =    1040                                         reg = <1>;
1042                                         iommu    1041                                         iommus = <&apps_smmu 0x1401 0x30>;
1043                                 };               1042                                 };
1044                                                  1043 
1045                                 compute-cb@2     1044                                 compute-cb@2 {
1046                                         compa    1045                                         compatible = "qcom,fastrpc-compute-cb";
1047                                         reg =    1046                                         reg = <2>;
1048                                         iommu    1047                                         iommus = <&apps_smmu 0x1402 0x30>;
1049                                 };               1048                                 };
1050                                                  1049 
1051                                 compute-cb@3     1050                                 compute-cb@3 {
1052                                         compa    1051                                         compatible = "qcom,fastrpc-compute-cb";
1053                                         reg =    1052                                         reg = <3>;
1054                                         iommu    1053                                         iommus = <&apps_smmu 0x1403 0x30>;
1055                                 };               1054                                 };
1056                                                  1055 
1057                                 compute-cb@4     1056                                 compute-cb@4 {
1058                                         compa    1057                                         compatible = "qcom,fastrpc-compute-cb";
1059                                         reg =    1058                                         reg = <4>;
1060                                         iommu    1059                                         iommus = <&apps_smmu 0x1404 0x30>;
1061                                 };               1060                                 };
1062                                                  1061 
1063                                 compute-cb@5     1062                                 compute-cb@5 {
1064                                         compa    1063                                         compatible = "qcom,fastrpc-compute-cb";
1065                                         reg =    1064                                         reg = <5>;
1066                                         iommu    1065                                         iommus = <&apps_smmu 0x1405 0x30>;
1067                                 };               1066                                 };
1068                                                  1067 
1069                                 compute-cb@6     1068                                 compute-cb@6 {
1070                                         compa    1069                                         compatible = "qcom,fastrpc-compute-cb";
1071                                         reg =    1070                                         reg = <6>;
1072                                         iommu    1071                                         iommus = <&apps_smmu 0x1406 0x30>;
1073                                 };               1072                                 };
1074                                                  1073 
1075                                 compute-cb@7     1074                                 compute-cb@7 {
1076                                         compa    1075                                         compatible = "qcom,fastrpc-compute-cb";
1077                                         reg =    1076                                         reg = <7>;
1078                                         iommu    1077                                         iommus = <&apps_smmu 0x1407 0x30>;
1079                                 };               1078                                 };
1080                                                  1079 
1081                                 compute-cb@8     1080                                 compute-cb@8 {
1082                                         compa    1081                                         compatible = "qcom,fastrpc-compute-cb";
1083                                         reg =    1082                                         reg = <8>;
1084                                         iommu    1083                                         iommus = <&apps_smmu 0x1408 0x30>;
1085                                 };               1084                                 };
1086                         };                       1085                         };
1087                 };                               1086                 };
1088         };                                       1087         };
1089                                                  1088 
1090         smp2p-cdsp {                             1089         smp2p-cdsp {
1091                 compatible = "qcom,smp2p";       1090                 compatible = "qcom,smp2p";
1092                 qcom,smem = <94>, <432>;         1091                 qcom,smem = <94>, <432>;
1093                                                  1092 
1094                 interrupts = <GIC_SPI 576 IRQ    1093                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095                                                  1094 
1096                 mboxes = <&apss_shared 6>;       1095                 mboxes = <&apss_shared 6>;
1097                                                  1096 
1098                 qcom,local-pid = <0>;            1097                 qcom,local-pid = <0>;
1099                 qcom,remote-pid = <5>;           1098                 qcom,remote-pid = <5>;
1100                                                  1099 
1101                 cdsp_smp2p_out: master-kernel    1100                 cdsp_smp2p_out: master-kernel {
1102                         qcom,entry-name = "ma    1101                         qcom,entry-name = "master-kernel";
1103                         #qcom,smem-state-cell    1102                         #qcom,smem-state-cells = <1>;
1104                 };                               1103                 };
1105                                                  1104 
1106                 cdsp_smp2p_in: slave-kernel {    1105                 cdsp_smp2p_in: slave-kernel {
1107                         qcom,entry-name = "sl    1106                         qcom,entry-name = "slave-kernel";
1108                                                  1107 
1109                         interrupt-controller;    1108                         interrupt-controller;
1110                         #interrupt-cells = <2    1109                         #interrupt-cells = <2>;
1111                 };                               1110                 };
1112         };                                       1111         };
1113                                                  1112 
1114         smp2p-lpass {                            1113         smp2p-lpass {
1115                 compatible = "qcom,smp2p";       1114                 compatible = "qcom,smp2p";
1116                 qcom,smem = <443>, <429>;        1115                 qcom,smem = <443>, <429>;
1117                                                  1116 
1118                 interrupts = <GIC_SPI 158 IRQ    1117                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119                                                  1118 
1120                 mboxes = <&apss_shared 10>;      1119                 mboxes = <&apss_shared 10>;
1121                                                  1120 
1122                 qcom,local-pid = <0>;            1121                 qcom,local-pid = <0>;
1123                 qcom,remote-pid = <2>;           1122                 qcom,remote-pid = <2>;
1124                                                  1123 
1125                 adsp_smp2p_out: master-kernel    1124                 adsp_smp2p_out: master-kernel {
1126                         qcom,entry-name = "ma    1125                         qcom,entry-name = "master-kernel";
1127                         #qcom,smem-state-cell    1126                         #qcom,smem-state-cells = <1>;
1128                 };                               1127                 };
1129                                                  1128 
1130                 adsp_smp2p_in: slave-kernel {    1129                 adsp_smp2p_in: slave-kernel {
1131                         qcom,entry-name = "sl    1130                         qcom,entry-name = "slave-kernel";
1132                                                  1131 
1133                         interrupt-controller;    1132                         interrupt-controller;
1134                         #interrupt-cells = <2    1133                         #interrupt-cells = <2>;
1135                 };                               1134                 };
1136         };                                       1135         };
1137                                                  1136 
1138         smp2p-mpss {                             1137         smp2p-mpss {
1139                 compatible = "qcom,smp2p";       1138                 compatible = "qcom,smp2p";
1140                 qcom,smem = <435>, <428>;        1139                 qcom,smem = <435>, <428>;
1141                 interrupts = <GIC_SPI 451 IRQ    1140                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142                 mboxes = <&apss_shared 14>;      1141                 mboxes = <&apss_shared 14>;
1143                 qcom,local-pid = <0>;            1142                 qcom,local-pid = <0>;
1144                 qcom,remote-pid = <1>;           1143                 qcom,remote-pid = <1>;
1145                                                  1144 
1146                 modem_smp2p_out: master-kerne    1145                 modem_smp2p_out: master-kernel {
1147                         qcom,entry-name = "ma    1146                         qcom,entry-name = "master-kernel";
1148                         #qcom,smem-state-cell    1147                         #qcom,smem-state-cells = <1>;
1149                 };                               1148                 };
1150                                                  1149 
1151                 modem_smp2p_in: slave-kernel     1150                 modem_smp2p_in: slave-kernel {
1152                         qcom,entry-name = "sl    1151                         qcom,entry-name = "slave-kernel";
1153                         interrupt-controller;    1152                         interrupt-controller;
1154                         #interrupt-cells = <2    1153                         #interrupt-cells = <2>;
1155                 };                               1154                 };
1156                                                  1155 
1157                 ipa_smp2p_out: ipa-ap-to-mode    1156                 ipa_smp2p_out: ipa-ap-to-modem {
1158                         qcom,entry-name = "ip    1157                         qcom,entry-name = "ipa";
1159                         #qcom,smem-state-cell    1158                         #qcom,smem-state-cells = <1>;
1160                 };                               1159                 };
1161                                                  1160 
1162                 ipa_smp2p_in: ipa-modem-to-ap    1161                 ipa_smp2p_in: ipa-modem-to-ap {
1163                         qcom,entry-name = "ip    1162                         qcom,entry-name = "ipa";
1164                         interrupt-controller;    1163                         interrupt-controller;
1165                         #interrupt-cells = <2    1164                         #interrupt-cells = <2>;
1166                 };                               1165                 };
1167         };                                       1166         };
1168                                                  1167 
1169         smp2p-slpi {                             1168         smp2p-slpi {
1170                 compatible = "qcom,smp2p";       1169                 compatible = "qcom,smp2p";
1171                 qcom,smem = <481>, <430>;        1170                 qcom,smem = <481>, <430>;
1172                 interrupts = <GIC_SPI 172 IRQ    1171                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173                 mboxes = <&apss_shared 26>;      1172                 mboxes = <&apss_shared 26>;
1174                 qcom,local-pid = <0>;            1173                 qcom,local-pid = <0>;
1175                 qcom,remote-pid = <3>;           1174                 qcom,remote-pid = <3>;
1176                                                  1175 
1177                 slpi_smp2p_out: master-kernel    1176                 slpi_smp2p_out: master-kernel {
1178                         qcom,entry-name = "ma    1177                         qcom,entry-name = "master-kernel";
1179                         #qcom,smem-state-cell    1178                         #qcom,smem-state-cells = <1>;
1180                 };                               1179                 };
1181                                                  1180 
1182                 slpi_smp2p_in: slave-kernel {    1181                 slpi_smp2p_in: slave-kernel {
1183                         qcom,entry-name = "sl    1182                         qcom,entry-name = "slave-kernel";
1184                         interrupt-controller;    1183                         interrupt-controller;
1185                         #interrupt-cells = <2    1184                         #interrupt-cells = <2>;
1186                 };                               1185                 };
1187         };                                       1186         };
1188                                                  1187 
1189         soc: soc@0 {                             1188         soc: soc@0 {
1190                 #address-cells = <2>;            1189                 #address-cells = <2>;
1191                 #size-cells = <2>;               1190                 #size-cells = <2>;
1192                 ranges = <0 0 0 0 0x10 0>;       1191                 ranges = <0 0 0 0 0x10 0>;
1193                 dma-ranges = <0 0 0 0 0x10 0>    1192                 dma-ranges = <0 0 0 0 0x10 0>;
1194                 compatible = "simple-bus";       1193                 compatible = "simple-bus";
1195                                                  1194 
1196                 gcc: clock-controller@100000     1195                 gcc: clock-controller@100000 {
1197                         compatible = "qcom,gc    1196                         compatible = "qcom,gcc-sdm845";
1198                         reg = <0 0x00100000 0    1197                         reg = <0 0x00100000 0 0x1f0000>;
1199                         clocks = <&rpmhcc RPM    1198                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1200                                  <&rpmhcc RPM    1199                                  <&rpmhcc RPMH_CXO_CLK_A>,
1201                                  <&sleep_clk>    1200                                  <&sleep_clk>,
1202                                  <&pcie0_phy>    1201                                  <&pcie0_phy>,
1203                                  <&pcie1_phy>    1202                                  <&pcie1_phy>;
1204                         clock-names = "bi_tcx    1203                         clock-names = "bi_tcxo",
1205                                       "bi_tcx    1204                                       "bi_tcxo_ao",
1206                                       "sleep_    1205                                       "sleep_clk",
1207                                       "pcie_0    1206                                       "pcie_0_pipe_clk",
1208                                       "pcie_1    1207                                       "pcie_1_pipe_clk";
1209                         #clock-cells = <1>;      1208                         #clock-cells = <1>;
1210                         #reset-cells = <1>;      1209                         #reset-cells = <1>;
1211                         #power-domain-cells =    1210                         #power-domain-cells = <1>;
1212                         power-domains = <&rpm    1211                         power-domains = <&rpmhpd SDM845_CX>;
1213                 };                               1212                 };
1214                                                  1213 
1215                 qfprom@784000 {                  1214                 qfprom@784000 {
1216                         compatible = "qcom,sd    1215                         compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217                         reg = <0 0x00784000 0    1216                         reg = <0 0x00784000 0 0x8ff>;
1218                         #address-cells = <1>;    1217                         #address-cells = <1>;
1219                         #size-cells = <1>;       1218                         #size-cells = <1>;
1220                                                  1219 
1221                         qusb2p_hstx_trim: hst    1220                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222                                 reg = <0x1eb     1221                                 reg = <0x1eb 0x1>;
1223                                 bits = <1 4>;    1222                                 bits = <1 4>;
1224                         };                       1223                         };
1225                                                  1224 
1226                         qusb2s_hstx_trim: hst    1225                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227                                 reg = <0x1eb     1226                                 reg = <0x1eb 0x2>;
1228                                 bits = <6 4>;    1227                                 bits = <6 4>;
1229                         };                       1228                         };
1230                 };                               1229                 };
1231                                                  1230 
1232                 rng: rng@793000 {                1231                 rng: rng@793000 {
1233                         compatible = "qcom,pr    1232                         compatible = "qcom,prng-ee";
1234                         reg = <0 0x00793000 0    1233                         reg = <0 0x00793000 0 0x1000>;
1235                         clocks = <&gcc GCC_PR    1234                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236                         clock-names = "core";    1235                         clock-names = "core";
1237                 };                               1236                 };
1238                                                  1237 
1239                 gpi_dma0: dma-controller@8000    1238                 gpi_dma0: dma-controller@800000 {
1240                         #dma-cells = <3>;        1239                         #dma-cells = <3>;
1241                         compatible = "qcom,sd    1240                         compatible = "qcom,sdm845-gpi-dma";
1242                         reg = <0 0x00800000 0    1241                         reg = <0 0x00800000 0 0x60000>;
1243                         interrupts = <GIC_SPI    1242                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244                                      <GIC_SPI    1243                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245                                      <GIC_SPI    1244                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246                                      <GIC_SPI    1245                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247                                      <GIC_SPI    1246                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248                                      <GIC_SPI    1247                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249                                      <GIC_SPI    1248                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250                                      <GIC_SPI    1249                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251                                      <GIC_SPI    1250                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252                                      <GIC_SPI    1251                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253                                      <GIC_SPI    1252                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254                                      <GIC_SPI    1253                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255                                      <GIC_SPI    1254                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256                         dma-channels = <13>;     1255                         dma-channels = <13>;
1257                         dma-channel-mask = <0    1256                         dma-channel-mask = <0xfa>;
1258                         iommus = <&apps_smmu     1257                         iommus = <&apps_smmu 0x0016 0x0>;
1259                         status = "disabled";     1258                         status = "disabled";
1260                 };                               1259                 };
1261                                                  1260 
1262                 qupv3_id_0: geniqup@8c0000 {     1261                 qupv3_id_0: geniqup@8c0000 {
1263                         compatible = "qcom,ge    1262                         compatible = "qcom,geni-se-qup";
1264                         reg = <0 0x008c0000 0    1263                         reg = <0 0x008c0000 0 0x6000>;
1265                         clock-names = "m-ahb"    1264                         clock-names = "m-ahb", "s-ahb";
1266                         clocks = <&gcc GCC_QU    1265                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267                                  <&gcc GCC_QU    1266                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268                         iommus = <&apps_smmu     1267                         iommus = <&apps_smmu 0x3 0x0>;
1269                         #address-cells = <2>;    1268                         #address-cells = <2>;
1270                         #size-cells = <2>;       1269                         #size-cells = <2>;
1271                         ranges;                  1270                         ranges;
1272                         interconnects = <&agg    1271                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273                         interconnect-names =     1272                         interconnect-names = "qup-core";
1274                         status = "disabled";     1273                         status = "disabled";
1275                                                  1274 
1276                         i2c0: i2c@880000 {       1275                         i2c0: i2c@880000 {
1277                                 compatible =     1276                                 compatible = "qcom,geni-i2c";
1278                                 reg = <0 0x00    1277                                 reg = <0 0x00880000 0 0x4000>;
1279                                 clock-names =    1278                                 clock-names = "se";
1280                                 clocks = <&gc    1279                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281                                 pinctrl-names    1280                                 pinctrl-names = "default";
1282                                 pinctrl-0 = <    1281                                 pinctrl-0 = <&qup_i2c0_default>;
1283                                 interrupts =     1282                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284                                 #address-cell    1283                                 #address-cells = <1>;
1285                                 #size-cells =    1284                                 #size-cells = <0>;
1286                                 power-domains    1285                                 power-domains = <&rpmhpd SDM845_CX>;
1287                                 operating-poi    1286                                 operating-points-v2 = <&qup_opp_table>;
1288                                 interconnects    1287                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289                                                  1288                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290                                                  1289                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291                                 interconnect-    1290                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292                                 dmas = <&gpi_    1291                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293                                        <&gpi_    1292                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1294                                 dma-names = "    1293                                 dma-names = "tx", "rx";
1295                                 status = "dis    1294                                 status = "disabled";
1296                         };                       1295                         };
1297                                                  1296 
1298                         spi0: spi@880000 {       1297                         spi0: spi@880000 {
1299                                 compatible =     1298                                 compatible = "qcom,geni-spi";
1300                                 reg = <0 0x00    1299                                 reg = <0 0x00880000 0 0x4000>;
1301                                 clock-names =    1300                                 clock-names = "se";
1302                                 clocks = <&gc    1301                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303                                 pinctrl-names    1302                                 pinctrl-names = "default";
1304                                 pinctrl-0 = <    1303                                 pinctrl-0 = <&qup_spi0_default>;
1305                                 interrupts =     1304                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306                                 #address-cell    1305                                 #address-cells = <1>;
1307                                 #size-cells =    1306                                 #size-cells = <0>;
1308                                 interconnects    1307                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309                                                  1308                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310                                 interconnect-    1309                                 interconnect-names = "qup-core", "qup-config";
1311                                 dmas = <&gpi_    1310                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312                                        <&gpi_    1311                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313                                 dma-names = "    1312                                 dma-names = "tx", "rx";
1314                                 status = "dis    1313                                 status = "disabled";
1315                         };                       1314                         };
1316                                                  1315 
1317                         uart0: serial@880000     1316                         uart0: serial@880000 {
1318                                 compatible =     1317                                 compatible = "qcom,geni-uart";
1319                                 reg = <0 0x00    1318                                 reg = <0 0x00880000 0 0x4000>;
1320                                 clock-names =    1319                                 clock-names = "se";
1321                                 clocks = <&gc    1320                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322                                 pinctrl-names    1321                                 pinctrl-names = "default";
1323                                 pinctrl-0 = <    1322                                 pinctrl-0 = <&qup_uart0_default>;
1324                                 interrupts =     1323                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325                                 power-domains    1324                                 power-domains = <&rpmhpd SDM845_CX>;
1326                                 operating-poi    1325                                 operating-points-v2 = <&qup_opp_table>;
1327                                 interconnects    1326                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328                                                  1327                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329                                 interconnect-    1328                                 interconnect-names = "qup-core", "qup-config";
1330                                 status = "dis    1329                                 status = "disabled";
1331                         };                       1330                         };
1332                                                  1331 
1333                         i2c1: i2c@884000 {       1332                         i2c1: i2c@884000 {
1334                                 compatible =     1333                                 compatible = "qcom,geni-i2c";
1335                                 reg = <0 0x00    1334                                 reg = <0 0x00884000 0 0x4000>;
1336                                 clock-names =    1335                                 clock-names = "se";
1337                                 clocks = <&gc    1336                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338                                 pinctrl-names    1337                                 pinctrl-names = "default";
1339                                 pinctrl-0 = <    1338                                 pinctrl-0 = <&qup_i2c1_default>;
1340                                 interrupts =     1339                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341                                 #address-cell    1340                                 #address-cells = <1>;
1342                                 #size-cells =    1341                                 #size-cells = <0>;
1343                                 power-domains    1342                                 power-domains = <&rpmhpd SDM845_CX>;
1344                                 operating-poi    1343                                 operating-points-v2 = <&qup_opp_table>;
1345                                 interconnects    1344                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346                                                  1345                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347                                                  1346                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348                                 interconnect-    1347                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349                                 dmas = <&gpi_    1348                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1350                                        <&gpi_    1349                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1351                                 dma-names = "    1350                                 dma-names = "tx", "rx";
1352                                 status = "dis    1351                                 status = "disabled";
1353                         };                       1352                         };
1354                                                  1353 
1355                         spi1: spi@884000 {       1354                         spi1: spi@884000 {
1356                                 compatible =     1355                                 compatible = "qcom,geni-spi";
1357                                 reg = <0 0x00    1356                                 reg = <0 0x00884000 0 0x4000>;
1358                                 clock-names =    1357                                 clock-names = "se";
1359                                 clocks = <&gc    1358                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360                                 pinctrl-names    1359                                 pinctrl-names = "default";
1361                                 pinctrl-0 = <    1360                                 pinctrl-0 = <&qup_spi1_default>;
1362                                 interrupts =     1361                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363                                 #address-cell    1362                                 #address-cells = <1>;
1364                                 #size-cells =    1363                                 #size-cells = <0>;
1365                                 interconnects    1364                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366                                                  1365                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367                                 interconnect-    1366                                 interconnect-names = "qup-core", "qup-config";
1368                                 dmas = <&gpi_    1367                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1369                                        <&gpi_    1368                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1370                                 dma-names = "    1369                                 dma-names = "tx", "rx";
1371                                 status = "dis    1370                                 status = "disabled";
1372                         };                       1371                         };
1373                                                  1372 
1374                         uart1: serial@884000     1373                         uart1: serial@884000 {
1375                                 compatible =     1374                                 compatible = "qcom,geni-uart";
1376                                 reg = <0 0x00    1375                                 reg = <0 0x00884000 0 0x4000>;
1377                                 clock-names =    1376                                 clock-names = "se";
1378                                 clocks = <&gc    1377                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379                                 pinctrl-names    1378                                 pinctrl-names = "default";
1380                                 pinctrl-0 = <    1379                                 pinctrl-0 = <&qup_uart1_default>;
1381                                 interrupts =     1380                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382                                 power-domains    1381                                 power-domains = <&rpmhpd SDM845_CX>;
1383                                 operating-poi    1382                                 operating-points-v2 = <&qup_opp_table>;
1384                                 interconnects    1383                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385                                                  1384                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386                                 interconnect-    1385                                 interconnect-names = "qup-core", "qup-config";
1387                                 status = "dis    1386                                 status = "disabled";
1388                         };                       1387                         };
1389                                                  1388 
1390                         i2c2: i2c@888000 {       1389                         i2c2: i2c@888000 {
1391                                 compatible =     1390                                 compatible = "qcom,geni-i2c";
1392                                 reg = <0 0x00    1391                                 reg = <0 0x00888000 0 0x4000>;
1393                                 clock-names =    1392                                 clock-names = "se";
1394                                 clocks = <&gc    1393                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395                                 pinctrl-names    1394                                 pinctrl-names = "default";
1396                                 pinctrl-0 = <    1395                                 pinctrl-0 = <&qup_i2c2_default>;
1397                                 interrupts =     1396                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398                                 #address-cell    1397                                 #address-cells = <1>;
1399                                 #size-cells =    1398                                 #size-cells = <0>;
1400                                 power-domains    1399                                 power-domains = <&rpmhpd SDM845_CX>;
1401                                 operating-poi    1400                                 operating-points-v2 = <&qup_opp_table>;
1402                                 interconnects    1401                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403                                                  1402                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404                                                  1403                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405                                 interconnect-    1404                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406                                 dmas = <&gpi_    1405                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1407                                        <&gpi_    1406                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1408                                 dma-names = "    1407                                 dma-names = "tx", "rx";
1409                                 status = "dis    1408                                 status = "disabled";
1410                         };                       1409                         };
1411                                                  1410 
1412                         spi2: spi@888000 {       1411                         spi2: spi@888000 {
1413                                 compatible =     1412                                 compatible = "qcom,geni-spi";
1414                                 reg = <0 0x00    1413                                 reg = <0 0x00888000 0 0x4000>;
1415                                 clock-names =    1414                                 clock-names = "se";
1416                                 clocks = <&gc    1415                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417                                 pinctrl-names    1416                                 pinctrl-names = "default";
1418                                 pinctrl-0 = <    1417                                 pinctrl-0 = <&qup_spi2_default>;
1419                                 interrupts =     1418                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420                                 #address-cell    1419                                 #address-cells = <1>;
1421                                 #size-cells =    1420                                 #size-cells = <0>;
1422                                 interconnects    1421                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423                                                  1422                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424                                 interconnect-    1423                                 interconnect-names = "qup-core", "qup-config";
1425                                 dmas = <&gpi_    1424                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1426                                        <&gpi_    1425                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1427                                 dma-names = "    1426                                 dma-names = "tx", "rx";
1428                                 status = "dis    1427                                 status = "disabled";
1429                         };                       1428                         };
1430                                                  1429 
1431                         uart2: serial@888000     1430                         uart2: serial@888000 {
1432                                 compatible =     1431                                 compatible = "qcom,geni-uart";
1433                                 reg = <0 0x00    1432                                 reg = <0 0x00888000 0 0x4000>;
1434                                 clock-names =    1433                                 clock-names = "se";
1435                                 clocks = <&gc    1434                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436                                 pinctrl-names    1435                                 pinctrl-names = "default";
1437                                 pinctrl-0 = <    1436                                 pinctrl-0 = <&qup_uart2_default>;
1438                                 interrupts =     1437                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439                                 power-domains    1438                                 power-domains = <&rpmhpd SDM845_CX>;
1440                                 operating-poi    1439                                 operating-points-v2 = <&qup_opp_table>;
1441                                 interconnects    1440                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442                                                  1441                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443                                 interconnect-    1442                                 interconnect-names = "qup-core", "qup-config";
1444                                 status = "dis    1443                                 status = "disabled";
1445                         };                       1444                         };
1446                                                  1445 
1447                         i2c3: i2c@88c000 {       1446                         i2c3: i2c@88c000 {
1448                                 compatible =     1447                                 compatible = "qcom,geni-i2c";
1449                                 reg = <0 0x00    1448                                 reg = <0 0x0088c000 0 0x4000>;
1450                                 clock-names =    1449                                 clock-names = "se";
1451                                 clocks = <&gc    1450                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452                                 pinctrl-names    1451                                 pinctrl-names = "default";
1453                                 pinctrl-0 = <    1452                                 pinctrl-0 = <&qup_i2c3_default>;
1454                                 interrupts =     1453                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455                                 #address-cell    1454                                 #address-cells = <1>;
1456                                 #size-cells =    1455                                 #size-cells = <0>;
1457                                 power-domains    1456                                 power-domains = <&rpmhpd SDM845_CX>;
1458                                 operating-poi    1457                                 operating-points-v2 = <&qup_opp_table>;
1459                                 interconnects    1458                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460                                                  1459                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461                                                  1460                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462                                 interconnect-    1461                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463                                 dmas = <&gpi_    1462                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1464                                        <&gpi_    1463                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1465                                 dma-names = "    1464                                 dma-names = "tx", "rx";
1466                                 status = "dis    1465                                 status = "disabled";
1467                         };                       1466                         };
1468                                                  1467 
1469                         spi3: spi@88c000 {       1468                         spi3: spi@88c000 {
1470                                 compatible =     1469                                 compatible = "qcom,geni-spi";
1471                                 reg = <0 0x00    1470                                 reg = <0 0x0088c000 0 0x4000>;
1472                                 clock-names =    1471                                 clock-names = "se";
1473                                 clocks = <&gc    1472                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474                                 pinctrl-names    1473                                 pinctrl-names = "default";
1475                                 pinctrl-0 = <    1474                                 pinctrl-0 = <&qup_spi3_default>;
1476                                 interrupts =     1475                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477                                 #address-cell    1476                                 #address-cells = <1>;
1478                                 #size-cells =    1477                                 #size-cells = <0>;
1479                                 interconnects    1478                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480                                                  1479                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481                                 interconnect-    1480                                 interconnect-names = "qup-core", "qup-config";
1482                                 dmas = <&gpi_    1481                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1483                                        <&gpi_    1482                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1484                                 dma-names = "    1483                                 dma-names = "tx", "rx";
1485                                 status = "dis    1484                                 status = "disabled";
1486                         };                       1485                         };
1487                                                  1486 
1488                         uart3: serial@88c000     1487                         uart3: serial@88c000 {
1489                                 compatible =     1488                                 compatible = "qcom,geni-uart";
1490                                 reg = <0 0x00    1489                                 reg = <0 0x0088c000 0 0x4000>;
1491                                 clock-names =    1490                                 clock-names = "se";
1492                                 clocks = <&gc    1491                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493                                 pinctrl-names    1492                                 pinctrl-names = "default";
1494                                 pinctrl-0 = <    1493                                 pinctrl-0 = <&qup_uart3_default>;
1495                                 interrupts =     1494                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496                                 power-domains    1495                                 power-domains = <&rpmhpd SDM845_CX>;
1497                                 operating-poi    1496                                 operating-points-v2 = <&qup_opp_table>;
1498                                 interconnects    1497                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499                                                  1498                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500                                 interconnect-    1499                                 interconnect-names = "qup-core", "qup-config";
1501                                 status = "dis    1500                                 status = "disabled";
1502                         };                       1501                         };
1503                                                  1502 
1504                         i2c4: i2c@890000 {       1503                         i2c4: i2c@890000 {
1505                                 compatible =     1504                                 compatible = "qcom,geni-i2c";
1506                                 reg = <0 0x00    1505                                 reg = <0 0x00890000 0 0x4000>;
1507                                 clock-names =    1506                                 clock-names = "se";
1508                                 clocks = <&gc    1507                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509                                 pinctrl-names    1508                                 pinctrl-names = "default";
1510                                 pinctrl-0 = <    1509                                 pinctrl-0 = <&qup_i2c4_default>;
1511                                 interrupts =     1510                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512                                 #address-cell    1511                                 #address-cells = <1>;
1513                                 #size-cells =    1512                                 #size-cells = <0>;
1514                                 power-domains    1513                                 power-domains = <&rpmhpd SDM845_CX>;
1515                                 operating-poi    1514                                 operating-points-v2 = <&qup_opp_table>;
1516                                 interconnects    1515                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517                                                  1516                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518                                                  1517                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519                                 interconnect-    1518                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520                                 dmas = <&gpi_    1519                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521                                        <&gpi_    1520                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522                                 dma-names = "    1521                                 dma-names = "tx", "rx";
1523                                 status = "dis    1522                                 status = "disabled";
1524                         };                       1523                         };
1525                                                  1524 
1526                         spi4: spi@890000 {       1525                         spi4: spi@890000 {
1527                                 compatible =     1526                                 compatible = "qcom,geni-spi";
1528                                 reg = <0 0x00    1527                                 reg = <0 0x00890000 0 0x4000>;
1529                                 clock-names =    1528                                 clock-names = "se";
1530                                 clocks = <&gc    1529                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531                                 pinctrl-names    1530                                 pinctrl-names = "default";
1532                                 pinctrl-0 = <    1531                                 pinctrl-0 = <&qup_spi4_default>;
1533                                 interrupts =     1532                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534                                 #address-cell    1533                                 #address-cells = <1>;
1535                                 #size-cells =    1534                                 #size-cells = <0>;
1536                                 interconnects    1535                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537                                                  1536                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538                                 interconnect-    1537                                 interconnect-names = "qup-core", "qup-config";
1539                                 dmas = <&gpi_    1538                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1540                                        <&gpi_    1539                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1541                                 dma-names = "    1540                                 dma-names = "tx", "rx";
1542                                 status = "dis    1541                                 status = "disabled";
1543                         };                       1542                         };
1544                                                  1543 
1545                         uart4: serial@890000     1544                         uart4: serial@890000 {
1546                                 compatible =     1545                                 compatible = "qcom,geni-uart";
1547                                 reg = <0 0x00    1546                                 reg = <0 0x00890000 0 0x4000>;
1548                                 clock-names =    1547                                 clock-names = "se";
1549                                 clocks = <&gc    1548                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550                                 pinctrl-names    1549                                 pinctrl-names = "default";
1551                                 pinctrl-0 = <    1550                                 pinctrl-0 = <&qup_uart4_default>;
1552                                 interrupts =     1551                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553                                 power-domains    1552                                 power-domains = <&rpmhpd SDM845_CX>;
1554                                 operating-poi    1553                                 operating-points-v2 = <&qup_opp_table>;
1555                                 interconnects    1554                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556                                                  1555                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557                                 interconnect-    1556                                 interconnect-names = "qup-core", "qup-config";
1558                                 status = "dis    1557                                 status = "disabled";
1559                         };                       1558                         };
1560                                                  1559 
1561                         i2c5: i2c@894000 {       1560                         i2c5: i2c@894000 {
1562                                 compatible =     1561                                 compatible = "qcom,geni-i2c";
1563                                 reg = <0 0x00    1562                                 reg = <0 0x00894000 0 0x4000>;
1564                                 clock-names =    1563                                 clock-names = "se";
1565                                 clocks = <&gc    1564                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566                                 pinctrl-names    1565                                 pinctrl-names = "default";
1567                                 pinctrl-0 = <    1566                                 pinctrl-0 = <&qup_i2c5_default>;
1568                                 interrupts =     1567                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569                                 #address-cell    1568                                 #address-cells = <1>;
1570                                 #size-cells =    1569                                 #size-cells = <0>;
1571                                 power-domains    1570                                 power-domains = <&rpmhpd SDM845_CX>;
1572                                 operating-poi    1571                                 operating-points-v2 = <&qup_opp_table>;
1573                                 interconnects    1572                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574                                                  1573                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575                                                  1574                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576                                 interconnect-    1575                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577                                 dmas = <&gpi_    1576                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1578                                        <&gpi_    1577                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1579                                 dma-names = "    1578                                 dma-names = "tx", "rx";
1580                                 status = "dis    1579                                 status = "disabled";
1581                         };                       1580                         };
1582                                                  1581 
1583                         spi5: spi@894000 {       1582                         spi5: spi@894000 {
1584                                 compatible =     1583                                 compatible = "qcom,geni-spi";
1585                                 reg = <0 0x00    1584                                 reg = <0 0x00894000 0 0x4000>;
1586                                 clock-names =    1585                                 clock-names = "se";
1587                                 clocks = <&gc    1586                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588                                 pinctrl-names    1587                                 pinctrl-names = "default";
1589                                 pinctrl-0 = <    1588                                 pinctrl-0 = <&qup_spi5_default>;
1590                                 interrupts =     1589                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591                                 #address-cell    1590                                 #address-cells = <1>;
1592                                 #size-cells =    1591                                 #size-cells = <0>;
1593                                 interconnects    1592                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594                                                  1593                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595                                 interconnect-    1594                                 interconnect-names = "qup-core", "qup-config";
1596                                 dmas = <&gpi_    1595                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1597                                        <&gpi_    1596                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1598                                 dma-names = "    1597                                 dma-names = "tx", "rx";
1599                                 status = "dis    1598                                 status = "disabled";
1600                         };                       1599                         };
1601                                                  1600 
1602                         uart5: serial@894000     1601                         uart5: serial@894000 {
1603                                 compatible =     1602                                 compatible = "qcom,geni-uart";
1604                                 reg = <0 0x00    1603                                 reg = <0 0x00894000 0 0x4000>;
1605                                 clock-names =    1604                                 clock-names = "se";
1606                                 clocks = <&gc    1605                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607                                 pinctrl-names    1606                                 pinctrl-names = "default";
1608                                 pinctrl-0 = <    1607                                 pinctrl-0 = <&qup_uart5_default>;
1609                                 interrupts =     1608                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610                                 power-domains    1609                                 power-domains = <&rpmhpd SDM845_CX>;
1611                                 operating-poi    1610                                 operating-points-v2 = <&qup_opp_table>;
1612                                 interconnects    1611                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613                                                  1612                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614                                 interconnect-    1613                                 interconnect-names = "qup-core", "qup-config";
1615                                 status = "dis    1614                                 status = "disabled";
1616                         };                       1615                         };
1617                                                  1616 
1618                         i2c6: i2c@898000 {       1617                         i2c6: i2c@898000 {
1619                                 compatible =     1618                                 compatible = "qcom,geni-i2c";
1620                                 reg = <0 0x00    1619                                 reg = <0 0x00898000 0 0x4000>;
1621                                 clock-names =    1620                                 clock-names = "se";
1622                                 clocks = <&gc    1621                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623                                 pinctrl-names    1622                                 pinctrl-names = "default";
1624                                 pinctrl-0 = <    1623                                 pinctrl-0 = <&qup_i2c6_default>;
1625                                 interrupts =     1624                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626                                 #address-cell    1625                                 #address-cells = <1>;
1627                                 #size-cells =    1626                                 #size-cells = <0>;
1628                                 power-domains    1627                                 power-domains = <&rpmhpd SDM845_CX>;
1629                                 operating-poi    1628                                 operating-points-v2 = <&qup_opp_table>;
1630                                 interconnects    1629                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631                                                  1630                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632                                                  1631                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633                                 interconnect-    1632                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634                                 dmas = <&gpi_    1633                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1635                                        <&gpi_    1634                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1636                                 dma-names = "    1635                                 dma-names = "tx", "rx";
1637                                 status = "dis    1636                                 status = "disabled";
1638                         };                       1637                         };
1639                                                  1638 
1640                         spi6: spi@898000 {       1639                         spi6: spi@898000 {
1641                                 compatible =     1640                                 compatible = "qcom,geni-spi";
1642                                 reg = <0 0x00    1641                                 reg = <0 0x00898000 0 0x4000>;
1643                                 clock-names =    1642                                 clock-names = "se";
1644                                 clocks = <&gc    1643                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645                                 pinctrl-names    1644                                 pinctrl-names = "default";
1646                                 pinctrl-0 = <    1645                                 pinctrl-0 = <&qup_spi6_default>;
1647                                 interrupts =     1646                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648                                 #address-cell    1647                                 #address-cells = <1>;
1649                                 #size-cells =    1648                                 #size-cells = <0>;
1650                                 interconnects    1649                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651                                                  1650                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652                                 interconnect-    1651                                 interconnect-names = "qup-core", "qup-config";
1653                                 dmas = <&gpi_    1652                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1654                                        <&gpi_    1653                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1655                                 dma-names = "    1654                                 dma-names = "tx", "rx";
1656                                 status = "dis    1655                                 status = "disabled";
1657                         };                       1656                         };
1658                                                  1657 
1659                         uart6: serial@898000     1658                         uart6: serial@898000 {
1660                                 compatible =     1659                                 compatible = "qcom,geni-uart";
1661                                 reg = <0 0x00    1660                                 reg = <0 0x00898000 0 0x4000>;
1662                                 clock-names =    1661                                 clock-names = "se";
1663                                 clocks = <&gc    1662                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664                                 pinctrl-names    1663                                 pinctrl-names = "default";
1665                                 pinctrl-0 = <    1664                                 pinctrl-0 = <&qup_uart6_default>;
1666                                 interrupts =     1665                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667                                 power-domains    1666                                 power-domains = <&rpmhpd SDM845_CX>;
1668                                 operating-poi    1667                                 operating-points-v2 = <&qup_opp_table>;
1669                                 interconnects    1668                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670                                                  1669                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671                                 interconnect-    1670                                 interconnect-names = "qup-core", "qup-config";
1672                                 status = "dis    1671                                 status = "disabled";
1673                         };                       1672                         };
1674                                                  1673 
1675                         i2c7: i2c@89c000 {       1674                         i2c7: i2c@89c000 {
1676                                 compatible =     1675                                 compatible = "qcom,geni-i2c";
1677                                 reg = <0 0x00    1676                                 reg = <0 0x0089c000 0 0x4000>;
1678                                 clock-names =    1677                                 clock-names = "se";
1679                                 clocks = <&gc    1678                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680                                 pinctrl-names    1679                                 pinctrl-names = "default";
1681                                 pinctrl-0 = <    1680                                 pinctrl-0 = <&qup_i2c7_default>;
1682                                 interrupts =     1681                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683                                 #address-cell    1682                                 #address-cells = <1>;
1684                                 #size-cells =    1683                                 #size-cells = <0>;
1685                                 power-domains    1684                                 power-domains = <&rpmhpd SDM845_CX>;
1686                                 operating-poi    1685                                 operating-points-v2 = <&qup_opp_table>;
1687                                 status = "dis    1686                                 status = "disabled";
1688                         };                       1687                         };
1689                                                  1688 
1690                         spi7: spi@89c000 {       1689                         spi7: spi@89c000 {
1691                                 compatible =     1690                                 compatible = "qcom,geni-spi";
1692                                 reg = <0 0x00    1691                                 reg = <0 0x0089c000 0 0x4000>;
1693                                 clock-names =    1692                                 clock-names = "se";
1694                                 clocks = <&gc    1693                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695                                 pinctrl-names    1694                                 pinctrl-names = "default";
1696                                 pinctrl-0 = <    1695                                 pinctrl-0 = <&qup_spi7_default>;
1697                                 interrupts =     1696                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698                                 #address-cell    1697                                 #address-cells = <1>;
1699                                 #size-cells =    1698                                 #size-cells = <0>;
1700                                 interconnects    1699                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701                                                  1700                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702                                 interconnect-    1701                                 interconnect-names = "qup-core", "qup-config";
1703                                 dmas = <&gpi_    1702                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1704                                        <&gpi_    1703                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1705                                 dma-names = "    1704                                 dma-names = "tx", "rx";
1706                                 status = "dis    1705                                 status = "disabled";
1707                         };                       1706                         };
1708                                                  1707 
1709                         uart7: serial@89c000     1708                         uart7: serial@89c000 {
1710                                 compatible =     1709                                 compatible = "qcom,geni-uart";
1711                                 reg = <0 0x00    1710                                 reg = <0 0x0089c000 0 0x4000>;
1712                                 clock-names =    1711                                 clock-names = "se";
1713                                 clocks = <&gc    1712                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714                                 pinctrl-names    1713                                 pinctrl-names = "default";
1715                                 pinctrl-0 = <    1714                                 pinctrl-0 = <&qup_uart7_default>;
1716                                 interrupts =     1715                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717                                 power-domains    1716                                 power-domains = <&rpmhpd SDM845_CX>;
1718                                 operating-poi    1717                                 operating-points-v2 = <&qup_opp_table>;
1719                                 interconnects    1718                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720                                                  1719                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721                                 interconnect-    1720                                 interconnect-names = "qup-core", "qup-config";
1722                                 status = "dis    1721                                 status = "disabled";
1723                         };                       1722                         };
1724                 };                               1723                 };
1725                                                  1724 
1726                 gpi_dma1: dma-controller@a000    1725                 gpi_dma1: dma-controller@a00000 {
1727                         #dma-cells = <3>;        1726                         #dma-cells = <3>;
1728                         compatible = "qcom,sd    1727                         compatible = "qcom,sdm845-gpi-dma";
1729                         reg = <0 0x00a00000 0    1728                         reg = <0 0x00a00000 0 0x60000>;
1730                         interrupts = <GIC_SPI    1729                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731                                      <GIC_SPI    1730                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732                                      <GIC_SPI    1731                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733                                      <GIC_SPI    1732                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734                                      <GIC_SPI    1733                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI    1734                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736                                      <GIC_SPI    1735                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI    1736                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738                                      <GIC_SPI    1737                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI    1738                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740                                      <GIC_SPI    1739                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741                                      <GIC_SPI    1740                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742                                      <GIC_SPI    1741                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743                         dma-channels = <13>;     1742                         dma-channels = <13>;
1744                         dma-channel-mask = <0    1743                         dma-channel-mask = <0xfa>;
1745                         iommus = <&apps_smmu     1744                         iommus = <&apps_smmu 0x06d6 0x0>;
1746                         status = "disabled";     1745                         status = "disabled";
1747                 };                               1746                 };
1748                                                  1747 
1749                 qupv3_id_1: geniqup@ac0000 {     1748                 qupv3_id_1: geniqup@ac0000 {
1750                         compatible = "qcom,ge    1749                         compatible = "qcom,geni-se-qup";
1751                         reg = <0 0x00ac0000 0    1750                         reg = <0 0x00ac0000 0 0x6000>;
1752                         clock-names = "m-ahb"    1751                         clock-names = "m-ahb", "s-ahb";
1753                         clocks = <&gcc GCC_QU    1752                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754                                  <&gcc GCC_QU    1753                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755                         iommus = <&apps_smmu     1754                         iommus = <&apps_smmu 0x6c3 0x0>;
1756                         #address-cells = <2>;    1755                         #address-cells = <2>;
1757                         #size-cells = <2>;       1756                         #size-cells = <2>;
1758                         ranges;                  1757                         ranges;
1759                         interconnects = <&agg    1758                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760                         interconnect-names =     1759                         interconnect-names = "qup-core";
1761                         status = "disabled";     1760                         status = "disabled";
1762                                                  1761 
1763                         i2c8: i2c@a80000 {       1762                         i2c8: i2c@a80000 {
1764                                 compatible =     1763                                 compatible = "qcom,geni-i2c";
1765                                 reg = <0 0x00    1764                                 reg = <0 0x00a80000 0 0x4000>;
1766                                 clock-names =    1765                                 clock-names = "se";
1767                                 clocks = <&gc    1766                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768                                 pinctrl-names    1767                                 pinctrl-names = "default";
1769                                 pinctrl-0 = <    1768                                 pinctrl-0 = <&qup_i2c8_default>;
1770                                 interrupts =     1769                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771                                 #address-cell    1770                                 #address-cells = <1>;
1772                                 #size-cells =    1771                                 #size-cells = <0>;
1773                                 power-domains    1772                                 power-domains = <&rpmhpd SDM845_CX>;
1774                                 operating-poi    1773                                 operating-points-v2 = <&qup_opp_table>;
1775                                 interconnects    1774                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776                                                  1775                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777                                                  1776                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778                                 interconnect-    1777                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779                                 dmas = <&gpi_    1778                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780                                        <&gpi_    1779                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1781                                 dma-names = "    1780                                 dma-names = "tx", "rx";
1782                                 status = "dis    1781                                 status = "disabled";
1783                         };                       1782                         };
1784                                                  1783 
1785                         spi8: spi@a80000 {       1784                         spi8: spi@a80000 {
1786                                 compatible =     1785                                 compatible = "qcom,geni-spi";
1787                                 reg = <0 0x00    1786                                 reg = <0 0x00a80000 0 0x4000>;
1788                                 clock-names =    1787                                 clock-names = "se";
1789                                 clocks = <&gc    1788                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790                                 pinctrl-names    1789                                 pinctrl-names = "default";
1791                                 pinctrl-0 = <    1790                                 pinctrl-0 = <&qup_spi8_default>;
1792                                 interrupts =     1791                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793                                 #address-cell    1792                                 #address-cells = <1>;
1794                                 #size-cells =    1793                                 #size-cells = <0>;
1795                                 interconnects    1794                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796                                                  1795                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797                                 interconnect-    1796                                 interconnect-names = "qup-core", "qup-config";
1798                                 dmas = <&gpi_    1797                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799                                        <&gpi_    1798                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1800                                 dma-names = "    1799                                 dma-names = "tx", "rx";
1801                                 status = "dis    1800                                 status = "disabled";
1802                         };                       1801                         };
1803                                                  1802 
1804                         uart8: serial@a80000     1803                         uart8: serial@a80000 {
1805                                 compatible =     1804                                 compatible = "qcom,geni-uart";
1806                                 reg = <0 0x00    1805                                 reg = <0 0x00a80000 0 0x4000>;
1807                                 clock-names =    1806                                 clock-names = "se";
1808                                 clocks = <&gc    1807                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809                                 pinctrl-names    1808                                 pinctrl-names = "default";
1810                                 pinctrl-0 = <    1809                                 pinctrl-0 = <&qup_uart8_default>;
1811                                 interrupts =     1810                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812                                 power-domains    1811                                 power-domains = <&rpmhpd SDM845_CX>;
1813                                 operating-poi    1812                                 operating-points-v2 = <&qup_opp_table>;
1814                                 interconnects    1813                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815                                                  1814                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816                                 interconnect-    1815                                 interconnect-names = "qup-core", "qup-config";
1817                                 status = "dis    1816                                 status = "disabled";
1818                         };                       1817                         };
1819                                                  1818 
1820                         i2c9: i2c@a84000 {       1819                         i2c9: i2c@a84000 {
1821                                 compatible =     1820                                 compatible = "qcom,geni-i2c";
1822                                 reg = <0 0x00    1821                                 reg = <0 0x00a84000 0 0x4000>;
1823                                 clock-names =    1822                                 clock-names = "se";
1824                                 clocks = <&gc    1823                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825                                 pinctrl-names    1824                                 pinctrl-names = "default";
1826                                 pinctrl-0 = <    1825                                 pinctrl-0 = <&qup_i2c9_default>;
1827                                 interrupts =     1826                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828                                 #address-cell    1827                                 #address-cells = <1>;
1829                                 #size-cells =    1828                                 #size-cells = <0>;
1830                                 power-domains    1829                                 power-domains = <&rpmhpd SDM845_CX>;
1831                                 operating-poi    1830                                 operating-points-v2 = <&qup_opp_table>;
1832                                 interconnects    1831                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833                                                  1832                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834                                                  1833                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835                                 interconnect-    1834                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836                                 dmas = <&gpi_    1835                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1837                                        <&gpi_    1836                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1838                                 dma-names = "    1837                                 dma-names = "tx", "rx";
1839                                 status = "dis    1838                                 status = "disabled";
1840                         };                       1839                         };
1841                                                  1840 
1842                         spi9: spi@a84000 {       1841                         spi9: spi@a84000 {
1843                                 compatible =     1842                                 compatible = "qcom,geni-spi";
1844                                 reg = <0 0x00    1843                                 reg = <0 0x00a84000 0 0x4000>;
1845                                 clock-names =    1844                                 clock-names = "se";
1846                                 clocks = <&gc    1845                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847                                 pinctrl-names    1846                                 pinctrl-names = "default";
1848                                 pinctrl-0 = <    1847                                 pinctrl-0 = <&qup_spi9_default>;
1849                                 interrupts =     1848                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850                                 #address-cell    1849                                 #address-cells = <1>;
1851                                 #size-cells =    1850                                 #size-cells = <0>;
1852                                 interconnects    1851                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853                                                  1852                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854                                 interconnect-    1853                                 interconnect-names = "qup-core", "qup-config";
1855                                 dmas = <&gpi_    1854                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1856                                        <&gpi_    1855                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1857                                 dma-names = "    1856                                 dma-names = "tx", "rx";
1858                                 status = "dis    1857                                 status = "disabled";
1859                         };                       1858                         };
1860                                                  1859 
1861                         uart9: serial@a84000     1860                         uart9: serial@a84000 {
1862                                 compatible =     1861                                 compatible = "qcom,geni-debug-uart";
1863                                 reg = <0 0x00    1862                                 reg = <0 0x00a84000 0 0x4000>;
1864                                 clock-names =    1863                                 clock-names = "se";
1865                                 clocks = <&gc    1864                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866                                 pinctrl-names    1865                                 pinctrl-names = "default";
1867                                 pinctrl-0 = <    1866                                 pinctrl-0 = <&qup_uart9_default>;
1868                                 interrupts =     1867                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869                                 power-domains    1868                                 power-domains = <&rpmhpd SDM845_CX>;
1870                                 operating-poi    1869                                 operating-points-v2 = <&qup_opp_table>;
1871                                 interconnects    1870                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872                                                  1871                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873                                 interconnect-    1872                                 interconnect-names = "qup-core", "qup-config";
1874                                 status = "dis    1873                                 status = "disabled";
1875                         };                       1874                         };
1876                                                  1875 
1877                         i2c10: i2c@a88000 {      1876                         i2c10: i2c@a88000 {
1878                                 compatible =     1877                                 compatible = "qcom,geni-i2c";
1879                                 reg = <0 0x00    1878                                 reg = <0 0x00a88000 0 0x4000>;
1880                                 clock-names =    1879                                 clock-names = "se";
1881                                 clocks = <&gc    1880                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882                                 pinctrl-names    1881                                 pinctrl-names = "default";
1883                                 pinctrl-0 = <    1882                                 pinctrl-0 = <&qup_i2c10_default>;
1884                                 interrupts =     1883                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885                                 #address-cell    1884                                 #address-cells = <1>;
1886                                 #size-cells =    1885                                 #size-cells = <0>;
1887                                 power-domains    1886                                 power-domains = <&rpmhpd SDM845_CX>;
1888                                 operating-poi    1887                                 operating-points-v2 = <&qup_opp_table>;
1889                                 interconnects    1888                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890                                                  1889                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891                                                  1890                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892                                 interconnect-    1891                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893                                 dmas = <&gpi_    1892                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1894                                        <&gpi_    1893                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1895                                 dma-names = "    1894                                 dma-names = "tx", "rx";
1896                                 status = "dis    1895                                 status = "disabled";
1897                         };                       1896                         };
1898                                                  1897 
1899                         spi10: spi@a88000 {      1898                         spi10: spi@a88000 {
1900                                 compatible =     1899                                 compatible = "qcom,geni-spi";
1901                                 reg = <0 0x00    1900                                 reg = <0 0x00a88000 0 0x4000>;
1902                                 clock-names =    1901                                 clock-names = "se";
1903                                 clocks = <&gc    1902                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904                                 pinctrl-names    1903                                 pinctrl-names = "default";
1905                                 pinctrl-0 = <    1904                                 pinctrl-0 = <&qup_spi10_default>;
1906                                 interrupts =     1905                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907                                 #address-cell    1906                                 #address-cells = <1>;
1908                                 #size-cells =    1907                                 #size-cells = <0>;
1909                                 interconnects    1908                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910                                                  1909                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911                                 interconnect-    1910                                 interconnect-names = "qup-core", "qup-config";
1912                                 dmas = <&gpi_    1911                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913                                        <&gpi_    1912                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1914                                 dma-names = "    1913                                 dma-names = "tx", "rx";
1915                                 status = "dis    1914                                 status = "disabled";
1916                         };                       1915                         };
1917                                                  1916 
1918                         uart10: serial@a88000    1917                         uart10: serial@a88000 {
1919                                 compatible =     1918                                 compatible = "qcom,geni-uart";
1920                                 reg = <0 0x00    1919                                 reg = <0 0x00a88000 0 0x4000>;
1921                                 clock-names =    1920                                 clock-names = "se";
1922                                 clocks = <&gc    1921                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923                                 pinctrl-names    1922                                 pinctrl-names = "default";
1924                                 pinctrl-0 = <    1923                                 pinctrl-0 = <&qup_uart10_default>;
1925                                 interrupts =     1924                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926                                 power-domains    1925                                 power-domains = <&rpmhpd SDM845_CX>;
1927                                 operating-poi    1926                                 operating-points-v2 = <&qup_opp_table>;
1928                                 interconnects    1927                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929                                                  1928                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930                                 interconnect-    1929                                 interconnect-names = "qup-core", "qup-config";
1931                                 status = "dis    1930                                 status = "disabled";
1932                         };                       1931                         };
1933                                                  1932 
1934                         i2c11: i2c@a8c000 {      1933                         i2c11: i2c@a8c000 {
1935                                 compatible =     1934                                 compatible = "qcom,geni-i2c";
1936                                 reg = <0 0x00    1935                                 reg = <0 0x00a8c000 0 0x4000>;
1937                                 clock-names =    1936                                 clock-names = "se";
1938                                 clocks = <&gc    1937                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939                                 pinctrl-names    1938                                 pinctrl-names = "default";
1940                                 pinctrl-0 = <    1939                                 pinctrl-0 = <&qup_i2c11_default>;
1941                                 interrupts =     1940                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942                                 #address-cell    1941                                 #address-cells = <1>;
1943                                 #size-cells =    1942                                 #size-cells = <0>;
1944                                 power-domains    1943                                 power-domains = <&rpmhpd SDM845_CX>;
1945                                 operating-poi    1944                                 operating-points-v2 = <&qup_opp_table>;
1946                                 interconnects    1945                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947                                                  1946                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948                                                  1947                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949                                 interconnect-    1948                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950                                 dmas = <&gpi_    1949                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1951                                        <&gpi_    1950                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1952                                 dma-names = "    1951                                 dma-names = "tx", "rx";
1953                                 status = "dis    1952                                 status = "disabled";
1954                         };                       1953                         };
1955                                                  1954 
1956                         spi11: spi@a8c000 {      1955                         spi11: spi@a8c000 {
1957                                 compatible =     1956                                 compatible = "qcom,geni-spi";
1958                                 reg = <0 0x00    1957                                 reg = <0 0x00a8c000 0 0x4000>;
1959                                 clock-names =    1958                                 clock-names = "se";
1960                                 clocks = <&gc    1959                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961                                 pinctrl-names    1960                                 pinctrl-names = "default";
1962                                 pinctrl-0 = <    1961                                 pinctrl-0 = <&qup_spi11_default>;
1963                                 interrupts =     1962                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964                                 #address-cell    1963                                 #address-cells = <1>;
1965                                 #size-cells =    1964                                 #size-cells = <0>;
1966                                 interconnects    1965                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967                                                  1966                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968                                 interconnect-    1967                                 interconnect-names = "qup-core", "qup-config";
1969                                 dmas = <&gpi_    1968                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1970                                        <&gpi_    1969                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1971                                 dma-names = "    1970                                 dma-names = "tx", "rx";
1972                                 status = "dis    1971                                 status = "disabled";
1973                         };                       1972                         };
1974                                                  1973 
1975                         uart11: serial@a8c000    1974                         uart11: serial@a8c000 {
1976                                 compatible =     1975                                 compatible = "qcom,geni-uart";
1977                                 reg = <0 0x00    1976                                 reg = <0 0x00a8c000 0 0x4000>;
1978                                 clock-names =    1977                                 clock-names = "se";
1979                                 clocks = <&gc    1978                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980                                 pinctrl-names    1979                                 pinctrl-names = "default";
1981                                 pinctrl-0 = <    1980                                 pinctrl-0 = <&qup_uart11_default>;
1982                                 interrupts =     1981                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983                                 power-domains    1982                                 power-domains = <&rpmhpd SDM845_CX>;
1984                                 operating-poi    1983                                 operating-points-v2 = <&qup_opp_table>;
1985                                 interconnects    1984                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986                                                  1985                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987                                 interconnect-    1986                                 interconnect-names = "qup-core", "qup-config";
1988                                 status = "dis    1987                                 status = "disabled";
1989                         };                       1988                         };
1990                                                  1989 
1991                         i2c12: i2c@a90000 {      1990                         i2c12: i2c@a90000 {
1992                                 compatible =     1991                                 compatible = "qcom,geni-i2c";
1993                                 reg = <0 0x00    1992                                 reg = <0 0x00a90000 0 0x4000>;
1994                                 clock-names =    1993                                 clock-names = "se";
1995                                 clocks = <&gc    1994                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996                                 pinctrl-names    1995                                 pinctrl-names = "default";
1997                                 pinctrl-0 = <    1996                                 pinctrl-0 = <&qup_i2c12_default>;
1998                                 interrupts =     1997                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999                                 #address-cell    1998                                 #address-cells = <1>;
2000                                 #size-cells =    1999                                 #size-cells = <0>;
2001                                 power-domains    2000                                 power-domains = <&rpmhpd SDM845_CX>;
2002                                 operating-poi    2001                                 operating-points-v2 = <&qup_opp_table>;
2003                                 interconnects    2002                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004                                                  2003                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005                                                  2004                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006                                 interconnect-    2005                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007                                 dmas = <&gpi_    2006                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2008                                        <&gpi_    2007                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2009                                 dma-names = "    2008                                 dma-names = "tx", "rx";
2010                                 status = "dis    2009                                 status = "disabled";
2011                         };                       2010                         };
2012                                                  2011 
2013                         spi12: spi@a90000 {      2012                         spi12: spi@a90000 {
2014                                 compatible =     2013                                 compatible = "qcom,geni-spi";
2015                                 reg = <0 0x00    2014                                 reg = <0 0x00a90000 0 0x4000>;
2016                                 clock-names =    2015                                 clock-names = "se";
2017                                 clocks = <&gc    2016                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018                                 pinctrl-names    2017                                 pinctrl-names = "default";
2019                                 pinctrl-0 = <    2018                                 pinctrl-0 = <&qup_spi12_default>;
2020                                 interrupts =     2019                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021                                 #address-cell    2020                                 #address-cells = <1>;
2022                                 #size-cells =    2021                                 #size-cells = <0>;
2023                                 interconnects    2022                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024                                                  2023                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025                                 interconnect-    2024                                 interconnect-names = "qup-core", "qup-config";
2026                                 dmas = <&gpi_    2025                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2027                                        <&gpi_    2026                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2028                                 dma-names = "    2027                                 dma-names = "tx", "rx";
2029                                 status = "dis    2028                                 status = "disabled";
2030                         };                       2029                         };
2031                                                  2030 
2032                         uart12: serial@a90000    2031                         uart12: serial@a90000 {
2033                                 compatible =     2032                                 compatible = "qcom,geni-uart";
2034                                 reg = <0 0x00    2033                                 reg = <0 0x00a90000 0 0x4000>;
2035                                 clock-names =    2034                                 clock-names = "se";
2036                                 clocks = <&gc    2035                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037                                 pinctrl-names    2036                                 pinctrl-names = "default";
2038                                 pinctrl-0 = <    2037                                 pinctrl-0 = <&qup_uart12_default>;
2039                                 interrupts =     2038                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040                                 power-domains    2039                                 power-domains = <&rpmhpd SDM845_CX>;
2041                                 operating-poi    2040                                 operating-points-v2 = <&qup_opp_table>;
2042                                 interconnects    2041                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043                                                  2042                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044                                 interconnect-    2043                                 interconnect-names = "qup-core", "qup-config";
2045                                 status = "dis    2044                                 status = "disabled";
2046                         };                       2045                         };
2047                                                  2046 
2048                         i2c13: i2c@a94000 {      2047                         i2c13: i2c@a94000 {
2049                                 compatible =     2048                                 compatible = "qcom,geni-i2c";
2050                                 reg = <0 0x00    2049                                 reg = <0 0x00a94000 0 0x4000>;
2051                                 clock-names =    2050                                 clock-names = "se";
2052                                 clocks = <&gc    2051                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053                                 pinctrl-names    2052                                 pinctrl-names = "default";
2054                                 pinctrl-0 = <    2053                                 pinctrl-0 = <&qup_i2c13_default>;
2055                                 interrupts =     2054                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056                                 #address-cell    2055                                 #address-cells = <1>;
2057                                 #size-cells =    2056                                 #size-cells = <0>;
2058                                 power-domains    2057                                 power-domains = <&rpmhpd SDM845_CX>;
2059                                 operating-poi    2058                                 operating-points-v2 = <&qup_opp_table>;
2060                                 interconnects    2059                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061                                                  2060                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062                                                  2061                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063                                 interconnect-    2062                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064                                 dmas = <&gpi_    2063                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2065                                        <&gpi_    2064                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2066                                 dma-names = "    2065                                 dma-names = "tx", "rx";
2067                                 status = "dis    2066                                 status = "disabled";
2068                         };                       2067                         };
2069                                                  2068 
2070                         spi13: spi@a94000 {      2069                         spi13: spi@a94000 {
2071                                 compatible =     2070                                 compatible = "qcom,geni-spi";
2072                                 reg = <0 0x00    2071                                 reg = <0 0x00a94000 0 0x4000>;
2073                                 clock-names =    2072                                 clock-names = "se";
2074                                 clocks = <&gc    2073                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075                                 pinctrl-names    2074                                 pinctrl-names = "default";
2076                                 pinctrl-0 = <    2075                                 pinctrl-0 = <&qup_spi13_default>;
2077                                 interrupts =     2076                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078                                 #address-cell    2077                                 #address-cells = <1>;
2079                                 #size-cells =    2078                                 #size-cells = <0>;
2080                                 interconnects    2079                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081                                                  2080                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082                                 interconnect-    2081                                 interconnect-names = "qup-core", "qup-config";
2083                                 dmas = <&gpi_    2082                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2084                                        <&gpi_    2083                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2085                                 dma-names = "    2084                                 dma-names = "tx", "rx";
2086                                 status = "dis    2085                                 status = "disabled";
2087                         };                       2086                         };
2088                                                  2087 
2089                         uart13: serial@a94000    2088                         uart13: serial@a94000 {
2090                                 compatible =     2089                                 compatible = "qcom,geni-uart";
2091                                 reg = <0 0x00    2090                                 reg = <0 0x00a94000 0 0x4000>;
2092                                 clock-names =    2091                                 clock-names = "se";
2093                                 clocks = <&gc    2092                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094                                 pinctrl-names    2093                                 pinctrl-names = "default";
2095                                 pinctrl-0 = <    2094                                 pinctrl-0 = <&qup_uart13_default>;
2096                                 interrupts =     2095                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097                                 power-domains    2096                                 power-domains = <&rpmhpd SDM845_CX>;
2098                                 operating-poi    2097                                 operating-points-v2 = <&qup_opp_table>;
2099                                 interconnects    2098                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100                                                  2099                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101                                 interconnect-    2100                                 interconnect-names = "qup-core", "qup-config";
2102                                 status = "dis    2101                                 status = "disabled";
2103                         };                       2102                         };
2104                                                  2103 
2105                         i2c14: i2c@a98000 {      2104                         i2c14: i2c@a98000 {
2106                                 compatible =     2105                                 compatible = "qcom,geni-i2c";
2107                                 reg = <0 0x00    2106                                 reg = <0 0x00a98000 0 0x4000>;
2108                                 clock-names =    2107                                 clock-names = "se";
2109                                 clocks = <&gc    2108                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110                                 pinctrl-names    2109                                 pinctrl-names = "default";
2111                                 pinctrl-0 = <    2110                                 pinctrl-0 = <&qup_i2c14_default>;
2112                                 interrupts =     2111                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113                                 #address-cell    2112                                 #address-cells = <1>;
2114                                 #size-cells =    2113                                 #size-cells = <0>;
2115                                 power-domains    2114                                 power-domains = <&rpmhpd SDM845_CX>;
2116                                 operating-poi    2115                                 operating-points-v2 = <&qup_opp_table>;
2117                                 interconnects    2116                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118                                                  2117                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119                                                  2118                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120                                 interconnect-    2119                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121                                 dmas = <&gpi_    2120                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2122                                        <&gpi_    2121                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2123                                 dma-names = "    2122                                 dma-names = "tx", "rx";
2124                                 status = "dis    2123                                 status = "disabled";
2125                         };                       2124                         };
2126                                                  2125 
2127                         spi14: spi@a98000 {      2126                         spi14: spi@a98000 {
2128                                 compatible =     2127                                 compatible = "qcom,geni-spi";
2129                                 reg = <0 0x00    2128                                 reg = <0 0x00a98000 0 0x4000>;
2130                                 clock-names =    2129                                 clock-names = "se";
2131                                 clocks = <&gc    2130                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132                                 pinctrl-names    2131                                 pinctrl-names = "default";
2133                                 pinctrl-0 = <    2132                                 pinctrl-0 = <&qup_spi14_default>;
2134                                 interrupts =     2133                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135                                 #address-cell    2134                                 #address-cells = <1>;
2136                                 #size-cells =    2135                                 #size-cells = <0>;
2137                                 interconnects    2136                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138                                                  2137                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139                                 interconnect-    2138                                 interconnect-names = "qup-core", "qup-config";
2140                                 dmas = <&gpi_    2139                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2141                                        <&gpi_    2140                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2142                                 dma-names = "    2141                                 dma-names = "tx", "rx";
2143                                 status = "dis    2142                                 status = "disabled";
2144                         };                       2143                         };
2145                                                  2144 
2146                         uart14: serial@a98000    2145                         uart14: serial@a98000 {
2147                                 compatible =     2146                                 compatible = "qcom,geni-uart";
2148                                 reg = <0 0x00    2147                                 reg = <0 0x00a98000 0 0x4000>;
2149                                 clock-names =    2148                                 clock-names = "se";
2150                                 clocks = <&gc    2149                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151                                 pinctrl-names    2150                                 pinctrl-names = "default";
2152                                 pinctrl-0 = <    2151                                 pinctrl-0 = <&qup_uart14_default>;
2153                                 interrupts =     2152                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154                                 power-domains    2153                                 power-domains = <&rpmhpd SDM845_CX>;
2155                                 operating-poi    2154                                 operating-points-v2 = <&qup_opp_table>;
2156                                 interconnects    2155                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157                                                  2156                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158                                 interconnect-    2157                                 interconnect-names = "qup-core", "qup-config";
2159                                 status = "dis    2158                                 status = "disabled";
2160                         };                       2159                         };
2161                                                  2160 
2162                         i2c15: i2c@a9c000 {      2161                         i2c15: i2c@a9c000 {
2163                                 compatible =     2162                                 compatible = "qcom,geni-i2c";
2164                                 reg = <0 0x00    2163                                 reg = <0 0x00a9c000 0 0x4000>;
2165                                 clock-names =    2164                                 clock-names = "se";
2166                                 clocks = <&gc    2165                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167                                 pinctrl-names    2166                                 pinctrl-names = "default";
2168                                 pinctrl-0 = <    2167                                 pinctrl-0 = <&qup_i2c15_default>;
2169                                 interrupts =     2168                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170                                 #address-cell    2169                                 #address-cells = <1>;
2171                                 #size-cells =    2170                                 #size-cells = <0>;
2172                                 power-domains    2171                                 power-domains = <&rpmhpd SDM845_CX>;
2173                                 operating-poi    2172                                 operating-points-v2 = <&qup_opp_table>;
2174                                 status = "dis    2173                                 status = "disabled";
2175                                 interconnects    2174                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176                                                  2175                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177                                                  2176                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178                                 interconnect-    2177                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179                                 dmas = <&gpi_    2178                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2180                                        <&gpi_    2179                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2181                                 dma-names = "    2180                                 dma-names = "tx", "rx";
2182                         };                       2181                         };
2183                                                  2182 
2184                         spi15: spi@a9c000 {      2183                         spi15: spi@a9c000 {
2185                                 compatible =     2184                                 compatible = "qcom,geni-spi";
2186                                 reg = <0 0x00    2185                                 reg = <0 0x00a9c000 0 0x4000>;
2187                                 clock-names =    2186                                 clock-names = "se";
2188                                 clocks = <&gc    2187                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189                                 pinctrl-names    2188                                 pinctrl-names = "default";
2190                                 pinctrl-0 = <    2189                                 pinctrl-0 = <&qup_spi15_default>;
2191                                 interrupts =     2190                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192                                 #address-cell    2191                                 #address-cells = <1>;
2193                                 #size-cells =    2192                                 #size-cells = <0>;
2194                                 interconnects    2193                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195                                                  2194                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196                                 interconnect-    2195                                 interconnect-names = "qup-core", "qup-config";
2197                                 dmas = <&gpi_    2196                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2198                                        <&gpi_    2197                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2199                                 dma-names = "    2198                                 dma-names = "tx", "rx";
2200                                 status = "dis    2199                                 status = "disabled";
2201                         };                       2200                         };
2202                                                  2201 
2203                         uart15: serial@a9c000    2202                         uart15: serial@a9c000 {
2204                                 compatible =     2203                                 compatible = "qcom,geni-uart";
2205                                 reg = <0 0x00    2204                                 reg = <0 0x00a9c000 0 0x4000>;
2206                                 clock-names =    2205                                 clock-names = "se";
2207                                 clocks = <&gc    2206                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208                                 pinctrl-names    2207                                 pinctrl-names = "default";
2209                                 pinctrl-0 = <    2208                                 pinctrl-0 = <&qup_uart15_default>;
2210                                 interrupts =     2209                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211                                 power-domains    2210                                 power-domains = <&rpmhpd SDM845_CX>;
2212                                 operating-poi    2211                                 operating-points-v2 = <&qup_opp_table>;
2213                                 interconnects    2212                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214                                                  2213                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215                                 interconnect-    2214                                 interconnect-names = "qup-core", "qup-config";
2216                                 status = "dis    2215                                 status = "disabled";
2217                         };                       2216                         };
2218                 };                               2217                 };
2219                                                  2218 
2220                 llcc: system-cache-controller    2219                 llcc: system-cache-controller@1100000 {
2221                         compatible = "qcom,sd    2220                         compatible = "qcom,sdm845-llcc";
2222                         reg = <0 0x01100000 0    2221                         reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2223                               <0 0x01200000 0    2222                               <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2224                               <0 0x01300000 0    2223                               <0 0x01300000 0 0x50000>;
2225                         reg-names = "llcc0_ba    2224                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2226                                     "llcc3_ba    2225                                     "llcc3_base", "llcc_broadcast_base";
2227                         interrupts = <GIC_SPI    2226                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228                 };                               2227                 };
2229                                                  2228 
2230                 dma@10a2000 {                    2229                 dma@10a2000 {
2231                         compatible = "qcom,sd    2230                         compatible = "qcom,sdm845-dcc", "qcom,dcc";
2232                         reg = <0x0 0x010a2000    2231                         reg = <0x0 0x010a2000 0x0 0x1000>,
2233                               <0x0 0x010ae000    2232                               <0x0 0x010ae000 0x0 0x2000>;
2234                 };                               2233                 };
2235                                                  2234 
2236                 pmu@114a000 {                    2235                 pmu@114a000 {
2237                         compatible = "qcom,sd    2236                         compatible = "qcom,sdm845-llcc-bwmon";
2238                         reg = <0 0x0114a000 0    2237                         reg = <0 0x0114a000 0 0x1000>;
2239                         interrupts = <GIC_SPI    2238                         interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2240                         interconnects = <&mem    2239                         interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2241                                                  2240 
2242                         operating-points-v2 =    2241                         operating-points-v2 = <&llcc_bwmon_opp_table>;
2243                                                  2242 
2244                         llcc_bwmon_opp_table:    2243                         llcc_bwmon_opp_table: opp-table {
2245                                 compatible =     2244                                 compatible = "operating-points-v2";
2246                                                  2245 
2247                                 /*               2246                                 /*
2248                                  * The interc    2247                                  * The interconnect path bandwidth taken from
2249                                  * cpu4_opp_t    2248                                  * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2250                                  * interconne    2249                                  * interconnect.  This also matches the
2251                                  * bandwidth     2250                                  * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2252                                  * bus width:    2251                                  * bus width: 4 bytes) from msm-4.9 downstream
2253                                  * kernel.       2252                                  * kernel.
2254                                  */              2253                                  */
2255                                 opp-0 {          2254                                 opp-0 {
2256                                         opp-p    2255                                         opp-peak-kBps = <800000>;
2257                                 };               2256                                 };
2258                                 opp-1 {          2257                                 opp-1 {
2259                                         opp-p    2258                                         opp-peak-kBps = <1804000>;
2260                                 };               2259                                 };
2261                                 opp-2 {          2260                                 opp-2 {
2262                                         opp-p    2261                                         opp-peak-kBps = <3072000>;
2263                                 };               2262                                 };
2264                                 opp-3 {          2263                                 opp-3 {
2265                                         opp-p    2264                                         opp-peak-kBps = <5412000>;
2266                                 };               2265                                 };
2267                                 opp-4 {          2266                                 opp-4 {
2268                                         opp-p    2267                                         opp-peak-kBps = <7216000>;
2269                                 };               2268                                 };
2270                         };                       2269                         };
2271                 };                               2270                 };
2272                                                  2271 
2273                 pmu@1436400 {                    2272                 pmu@1436400 {
2274                         compatible = "qcom,sd    2273                         compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2275                         reg = <0 0x01436400 0    2274                         reg = <0 0x01436400 0 0x600>;
2276                         interrupts = <GIC_SPI    2275                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2277                         interconnects = <&gla    2276                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278                                                  2277 
2279                         operating-points-v2 =    2278                         operating-points-v2 = <&cpu_bwmon_opp_table>;
2280                                                  2279 
2281                         cpu_bwmon_opp_table:     2280                         cpu_bwmon_opp_table: opp-table {
2282                                 compatible =     2281                                 compatible = "operating-points-v2";
2283                                                  2282 
2284                                 /*               2283                                 /*
2285                                  * The interc    2284                                  * The interconnect path bandwidth taken from
2286                                  * cpu4_opp_t    2285                                  * cpu4_opp_table bandwidth for OSM L3
2287                                  * interconne    2286                                  * interconnect.  This also matches the OSM L3
2288                                  * from bandw    2287                                  * from bandwidth table of qcom,cpu4-l3lat-mon
2289                                  * (qcom,core    2288                                  * (qcom,core-dev-table, bus width: 16 bytes)
2290                                  * from msm-4    2289                                  * from msm-4.9 downstream kernel.
2291                                  */              2290                                  */
2292                                 opp-0 {          2291                                 opp-0 {
2293                                         opp-p    2292                                         opp-peak-kBps = <4800000>;
2294                                 };               2293                                 };
2295                                 opp-1 {          2294                                 opp-1 {
2296                                         opp-p    2295                                         opp-peak-kBps = <9216000>;
2297                                 };               2296                                 };
2298                                 opp-2 {          2297                                 opp-2 {
2299                                         opp-p    2298                                         opp-peak-kBps = <15052800>;
2300                                 };               2299                                 };
2301                                 opp-3 {          2300                                 opp-3 {
2302                                         opp-p    2301                                         opp-peak-kBps = <20889600>;
2303                                 };               2302                                 };
2304                                 opp-4 {          2303                                 opp-4 {
2305                                         opp-p    2304                                         opp-peak-kBps = <25497600>;
2306                                 };               2305                                 };
2307                         };                       2306                         };
2308                 };                               2307                 };
2309                                                  2308 
2310                 pcie0: pcie@1c00000 {            2309                 pcie0: pcie@1c00000 {
2311                         compatible = "qcom,pc    2310                         compatible = "qcom,pcie-sdm845";
2312                         reg = <0 0x01c00000 0    2311                         reg = <0 0x01c00000 0 0x2000>,
2313                               <0 0x60000000 0    2312                               <0 0x60000000 0 0xf1d>,
2314                               <0 0x60000f20 0    2313                               <0 0x60000f20 0 0xa8>,
2315                               <0 0x60100000 0    2314                               <0 0x60100000 0 0x100000>,
2316                               <0 0x01c07000 0    2315                               <0 0x01c07000 0 0x1000>;
2317                         reg-names = "parf", "    2316                         reg-names = "parf", "dbi", "elbi", "config", "mhi";
2318                         device_type = "pci";     2317                         device_type = "pci";
2319                         linux,pci-domain = <0    2318                         linux,pci-domain = <0>;
2320                         bus-range = <0x00 0xf    2319                         bus-range = <0x00 0xff>;
2321                         num-lanes = <1>;         2320                         num-lanes = <1>;
2322                                                  2321 
2323                         #address-cells = <3>;    2322                         #address-cells = <3>;
2324                         #size-cells = <2>;       2323                         #size-cells = <2>;
2325                                                  2324 
2326                         ranges = <0x01000000     2325                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2327                                  <0x02000000     2326                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2328                                                  2327 
2329                         interrupts = <GIC_SPI    2328                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330                         interrupt-names = "ms    2329                         interrupt-names = "msi";
2331                         #interrupt-cells = <1    2330                         #interrupt-cells = <1>;
2332                         interrupt-map-mask =     2331                         interrupt-map-mask = <0 0 0 0x7>;
2333                         interrupt-map = <0 0     2332                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334                                         <0 0     2333                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335                                         <0 0     2334                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336                                         <0 0     2335                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337                                                  2336 
2338                         clocks = <&gcc GCC_PC    2337                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339                                  <&gcc GCC_PC    2338                                  <&gcc GCC_PCIE_0_AUX_CLK>,
2340                                  <&gcc GCC_PC    2339                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341                                  <&gcc GCC_PC    2340                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342                                  <&gcc GCC_PC    2341                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343                                  <&gcc GCC_PC    2342                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344                                  <&gcc GCC_AG    2343                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345                         clock-names = "pipe",    2344                         clock-names = "pipe",
2346                                       "aux",     2345                                       "aux",
2347                                       "cfg",     2346                                       "cfg",
2348                                       "bus_ma    2347                                       "bus_master",
2349                                       "bus_sl    2348                                       "bus_slave",
2350                                       "slave_    2349                                       "slave_q2a",
2351                                       "tbu";     2350                                       "tbu";
2352                                                  2351 
2353                         iommu-map = <0x0   &a    2352                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
2354                                     <0x100 &a    2353                                     <0x100 &apps_smmu 0x1c11 0x1>,
2355                                     <0x200 &a    2354                                     <0x200 &apps_smmu 0x1c12 0x1>,
2356                                     <0x300 &a    2355                                     <0x300 &apps_smmu 0x1c13 0x1>,
2357                                     <0x400 &a    2356                                     <0x400 &apps_smmu 0x1c14 0x1>,
2358                                     <0x500 &a    2357                                     <0x500 &apps_smmu 0x1c15 0x1>,
2359                                     <0x600 &a    2358                                     <0x600 &apps_smmu 0x1c16 0x1>,
2360                                     <0x700 &a    2359                                     <0x700 &apps_smmu 0x1c17 0x1>,
2361                                     <0x800 &a    2360                                     <0x800 &apps_smmu 0x1c18 0x1>,
2362                                     <0x900 &a    2361                                     <0x900 &apps_smmu 0x1c19 0x1>,
2363                                     <0xa00 &a    2362                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
2364                                     <0xb00 &a    2363                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
2365                                     <0xc00 &a    2364                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
2366                                     <0xd00 &a    2365                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
2367                                     <0xe00 &a    2366                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
2368                                     <0xf00 &a    2367                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
2369                                                  2368 
2370                         resets = <&gcc GCC_PC    2369                         resets = <&gcc GCC_PCIE_0_BCR>;
2371                         reset-names = "pci";     2370                         reset-names = "pci";
2372                                                  2371 
2373                         power-domains = <&gcc    2372                         power-domains = <&gcc PCIE_0_GDSC>;
2374                                                  2373 
2375                         phys = <&pcie0_phy>;     2374                         phys = <&pcie0_phy>;
2376                         phy-names = "pciephy"    2375                         phy-names = "pciephy";
2377                                                  2376 
2378                         status = "disabled";     2377                         status = "disabled";
2379                                                  2378 
2380                         pcie@0 {                 2379                         pcie@0 {
2381                                 device_type =    2380                                 device_type = "pci";
2382                                 reg = <0x0 0x    2381                                 reg = <0x0 0x0 0x0 0x0 0x0>;
2383                                 bus-range = <    2382                                 bus-range = <0x01 0xff>;
2384                                                  2383 
2385                                 #address-cell    2384                                 #address-cells = <3>;
2386                                 #size-cells =    2385                                 #size-cells = <2>;
2387                                 ranges;          2386                                 ranges;
2388                         };                       2387                         };
2389                 };                               2388                 };
2390                                                  2389 
2391                 pcie0_phy: phy@1c06000 {         2390                 pcie0_phy: phy@1c06000 {
2392                         compatible = "qcom,sd    2391                         compatible = "qcom,sdm845-qmp-pcie-phy";
2393                         reg = <0 0x01c06000 0    2392                         reg = <0 0x01c06000 0 0x1000>;
2394                         clocks = <&gcc GCC_PC    2393                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395                                  <&gcc GCC_PC    2394                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396                                  <&gcc GCC_PC    2395                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397                                  <&gcc GCC_PC    2396                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2398                                  <&gcc GCC_PC    2397                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
2399                         clock-names = "aux",     2398                         clock-names = "aux",
2400                                       "cfg_ah    2399                                       "cfg_ahb",
2401                                       "ref",     2400                                       "ref",
2402                                       "refgen    2401                                       "refgen",
2403                                       "pipe";    2402                                       "pipe";
2404                                                  2403 
2405                         clock-output-names =     2404                         clock-output-names = "pcie_0_pipe_clk";
2406                         #clock-cells = <0>;      2405                         #clock-cells = <0>;
2407                                                  2406 
2408                         #phy-cells = <0>;        2407                         #phy-cells = <0>;
2409                                                  2408 
2410                         resets = <&gcc GCC_PC    2409                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411                         reset-names = "phy";     2410                         reset-names = "phy";
2412                                                  2411 
2413                         assigned-clocks = <&g    2412                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414                         assigned-clock-rates     2413                         assigned-clock-rates = <100000000>;
2415                                                  2414 
2416                         status = "disabled";     2415                         status = "disabled";
2417                 };                               2416                 };
2418                                                  2417 
2419                 pcie1: pcie@1c08000 {            2418                 pcie1: pcie@1c08000 {
2420                         compatible = "qcom,pc    2419                         compatible = "qcom,pcie-sdm845";
2421                         reg = <0 0x01c08000 0    2420                         reg = <0 0x01c08000 0 0x2000>,
2422                               <0 0x40000000 0    2421                               <0 0x40000000 0 0xf1d>,
2423                               <0 0x40000f20 0    2422                               <0 0x40000f20 0 0xa8>,
2424                               <0 0x40100000 0    2423                               <0 0x40100000 0 0x100000>,
2425                               <0 0x01c0c000 0    2424                               <0 0x01c0c000 0 0x1000>;
2426                         reg-names = "parf", "    2425                         reg-names = "parf", "dbi", "elbi", "config", "mhi";
2427                         device_type = "pci";     2426                         device_type = "pci";
2428                         linux,pci-domain = <1    2427                         linux,pci-domain = <1>;
2429                         bus-range = <0x00 0xf    2428                         bus-range = <0x00 0xff>;
2430                         num-lanes = <1>;         2429                         num-lanes = <1>;
2431                                                  2430 
2432                         #address-cells = <3>;    2431                         #address-cells = <3>;
2433                         #size-cells = <2>;       2432                         #size-cells = <2>;
2434                                                  2433 
2435                         ranges = <0x01000000     2434                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2436                                  <0x02000000     2435                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437                                                  2436 
2438                         interrupts = <GIC_SPI    2437                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439                         interrupt-names = "ms    2438                         interrupt-names = "msi";
2440                         #interrupt-cells = <1    2439                         #interrupt-cells = <1>;
2441                         interrupt-map-mask =     2440                         interrupt-map-mask = <0 0 0 0x7>;
2442                         interrupt-map = <0 0     2441                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443                                         <0 0     2442                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444                                         <0 0     2443                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445                                         <0 0     2444                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446                                                  2445 
2447                         clocks = <&gcc GCC_PC    2446                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448                                  <&gcc GCC_PC    2447                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2449                                  <&gcc GCC_PC    2448                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450                                  <&gcc GCC_PC    2449                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451                                  <&gcc GCC_PC    2450                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452                                  <&gcc GCC_PC    2451                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453                                  <&gcc GCC_PC    2452                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454                                  <&gcc GCC_AG    2453                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455                         clock-names = "pipe",    2454                         clock-names = "pipe",
2456                                       "aux",     2455                                       "aux",
2457                                       "cfg",     2456                                       "cfg",
2458                                       "bus_ma    2457                                       "bus_master",
2459                                       "bus_sl    2458                                       "bus_slave",
2460                                       "slave_    2459                                       "slave_q2a",
2461                                       "ref",     2460                                       "ref",
2462                                       "tbu";     2461                                       "tbu";
2463                                                  2462 
2464                         assigned-clocks = <&g    2463                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465                         assigned-clock-rates     2464                         assigned-clock-rates = <19200000>;
2466                                                  2465 
2467                         iommu-map = <0x0   &a    2466                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
2468                                     <0x100 &a    2467                                     <0x100 &apps_smmu 0x1c01 0x1>,
2469                                     <0x200 &a    2468                                     <0x200 &apps_smmu 0x1c02 0x1>,
2470                                     <0x300 &a    2469                                     <0x300 &apps_smmu 0x1c03 0x1>,
2471                                     <0x400 &a    2470                                     <0x400 &apps_smmu 0x1c04 0x1>,
2472                                     <0x500 &a    2471                                     <0x500 &apps_smmu 0x1c05 0x1>,
2473                                     <0x600 &a    2472                                     <0x600 &apps_smmu 0x1c06 0x1>,
2474                                     <0x700 &a    2473                                     <0x700 &apps_smmu 0x1c07 0x1>,
2475                                     <0x800 &a    2474                                     <0x800 &apps_smmu 0x1c08 0x1>,
2476                                     <0x900 &a    2475                                     <0x900 &apps_smmu 0x1c09 0x1>,
2477                                     <0xa00 &a    2476                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
2478                                     <0xb00 &a    2477                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
2479                                     <0xc00 &a    2478                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
2480                                     <0xd00 &a    2479                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
2481                                     <0xe00 &a    2480                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
2482                                     <0xf00 &a    2481                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
2483                                                  2482 
2484                         resets = <&gcc GCC_PC    2483                         resets = <&gcc GCC_PCIE_1_BCR>;
2485                         reset-names = "pci";     2484                         reset-names = "pci";
2486                                                  2485 
2487                         power-domains = <&gcc    2486                         power-domains = <&gcc PCIE_1_GDSC>;
2488                                                  2487 
2489                         phys = <&pcie1_phy>;     2488                         phys = <&pcie1_phy>;
2490                         phy-names = "pciephy"    2489                         phy-names = "pciephy";
2491                                                  2490 
2492                         status = "disabled";     2491                         status = "disabled";
2493                                                  2492 
2494                         pcie@0 {                 2493                         pcie@0 {
2495                                 device_type =    2494                                 device_type = "pci";
2496                                 reg = <0x0 0x    2495                                 reg = <0x0 0x0 0x0 0x0 0x0>;
2497                                 bus-range = <    2496                                 bus-range = <0x01 0xff>;
2498                                                  2497 
2499                                 #address-cell    2498                                 #address-cells = <3>;
2500                                 #size-cells =    2499                                 #size-cells = <2>;
2501                                 ranges;          2500                                 ranges;
2502                         };                       2501                         };
2503                 };                               2502                 };
2504                                                  2503 
2505                 pcie1_phy: phy@1c0a000 {         2504                 pcie1_phy: phy@1c0a000 {
2506                         compatible = "qcom,sd    2505                         compatible = "qcom,sdm845-qhp-pcie-phy";
2507                         reg = <0 0x01c0a000 0    2506                         reg = <0 0x01c0a000 0 0x2000>;
2508                         clocks = <&gcc GCC_PC    2507                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509                                  <&gcc GCC_PC    2508                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510                                  <&gcc GCC_PC    2509                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511                                  <&gcc GCC_PC    2510                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>,
2512                                  <&gcc GCC_PC    2511                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
2513                         clock-names = "aux",     2512                         clock-names = "aux",
2514                                       "cfg_ah    2513                                       "cfg_ahb",
2515                                       "ref",     2514                                       "ref",
2516                                       "refgen    2515                                       "refgen",
2517                                       "pipe";    2516                                       "pipe";
2518                                                  2517 
2519                         clock-output-names =     2518                         clock-output-names = "pcie_1_pipe_clk";
2520                         #clock-cells = <0>;      2519                         #clock-cells = <0>;
2521                                                  2520 
2522                         #phy-cells = <0>;        2521                         #phy-cells = <0>;
2523                                                  2522 
2524                         resets = <&gcc GCC_PC    2523                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525                         reset-names = "phy";     2524                         reset-names = "phy";
2526                                                  2525 
2527                         assigned-clocks = <&g    2526                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528                         assigned-clock-rates     2527                         assigned-clock-rates = <100000000>;
2529                                                  2528 
2530                         status = "disabled";     2529                         status = "disabled";
2531                 };                               2530                 };
2532                                                  2531 
2533                 mem_noc: interconnect@1380000    2532                 mem_noc: interconnect@1380000 {
2534                         compatible = "qcom,sd    2533                         compatible = "qcom,sdm845-mem-noc";
2535                         reg = <0 0x01380000 0    2534                         reg = <0 0x01380000 0 0x27200>;
2536                         #interconnect-cells =    2535                         #interconnect-cells = <2>;
2537                         qcom,bcm-voters = <&a    2536                         qcom,bcm-voters = <&apps_bcm_voter>;
2538                 };                               2537                 };
2539                                                  2538 
2540                 dc_noc: interconnect@14e0000     2539                 dc_noc: interconnect@14e0000 {
2541                         compatible = "qcom,sd    2540                         compatible = "qcom,sdm845-dc-noc";
2542                         reg = <0 0x014e0000 0    2541                         reg = <0 0x014e0000 0 0x400>;
2543                         #interconnect-cells =    2542                         #interconnect-cells = <2>;
2544                         qcom,bcm-voters = <&a    2543                         qcom,bcm-voters = <&apps_bcm_voter>;
2545                 };                               2544                 };
2546                                                  2545 
2547                 config_noc: interconnect@1500    2546                 config_noc: interconnect@1500000 {
2548                         compatible = "qcom,sd    2547                         compatible = "qcom,sdm845-config-noc";
2549                         reg = <0 0x01500000 0    2548                         reg = <0 0x01500000 0 0x5080>;
2550                         #interconnect-cells =    2549                         #interconnect-cells = <2>;
2551                         qcom,bcm-voters = <&a    2550                         qcom,bcm-voters = <&apps_bcm_voter>;
2552                 };                               2551                 };
2553                                                  2552 
2554                 system_noc: interconnect@1620    2553                 system_noc: interconnect@1620000 {
2555                         compatible = "qcom,sd    2554                         compatible = "qcom,sdm845-system-noc";
2556                         reg = <0 0x01620000 0    2555                         reg = <0 0x01620000 0 0x18080>;
2557                         #interconnect-cells =    2556                         #interconnect-cells = <2>;
2558                         qcom,bcm-voters = <&a    2557                         qcom,bcm-voters = <&apps_bcm_voter>;
2559                 };                               2558                 };
2560                                                  2559 
2561                 aggre1_noc: interconnect@16e0    2560                 aggre1_noc: interconnect@16e0000 {
2562                         compatible = "qcom,sd    2561                         compatible = "qcom,sdm845-aggre1-noc";
2563                         reg = <0 0x016e0000 0    2562                         reg = <0 0x016e0000 0 0x15080>;
2564                         #interconnect-cells =    2563                         #interconnect-cells = <2>;
2565                         qcom,bcm-voters = <&a    2564                         qcom,bcm-voters = <&apps_bcm_voter>;
2566                 };                               2565                 };
2567                                                  2566 
2568                 aggre2_noc: interconnect@1700    2567                 aggre2_noc: interconnect@1700000 {
2569                         compatible = "qcom,sd    2568                         compatible = "qcom,sdm845-aggre2-noc";
2570                         reg = <0 0x01700000 0    2569                         reg = <0 0x01700000 0 0x1f300>;
2571                         #interconnect-cells =    2570                         #interconnect-cells = <2>;
2572                         qcom,bcm-voters = <&a    2571                         qcom,bcm-voters = <&apps_bcm_voter>;
2573                 };                               2572                 };
2574                                                  2573 
2575                 mmss_noc: interconnect@174000    2574                 mmss_noc: interconnect@1740000 {
2576                         compatible = "qcom,sd    2575                         compatible = "qcom,sdm845-mmss-noc";
2577                         reg = <0 0x01740000 0    2576                         reg = <0 0x01740000 0 0x1c100>;
2578                         #interconnect-cells =    2577                         #interconnect-cells = <2>;
2579                         qcom,bcm-voters = <&a    2578                         qcom,bcm-voters = <&apps_bcm_voter>;
2580                 };                               2579                 };
2581                                                  2580 
2582                 ufs_mem_hc: ufshc@1d84000 {      2581                 ufs_mem_hc: ufshc@1d84000 {
2583                         compatible = "qcom,sd    2582                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584                                      "jedec,u    2583                                      "jedec,ufs-2.0";
2585                         reg = <0 0x01d84000 0    2584                         reg = <0 0x01d84000 0 0x2500>,
2586                               <0 0x01d90000 0    2585                               <0 0x01d90000 0 0x8000>;
2587                         reg-names = "std", "i    2586                         reg-names = "std", "ice";
2588                         interrupts = <GIC_SPI    2587                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589                         phys = <&ufs_mem_phy>    2588                         phys = <&ufs_mem_phy>;
2590                         phy-names = "ufsphy";    2589                         phy-names = "ufsphy";
2591                         lanes-per-direction =    2590                         lanes-per-direction = <2>;
2592                         power-domains = <&gcc    2591                         power-domains = <&gcc UFS_PHY_GDSC>;
2593                         #reset-cells = <1>;      2592                         #reset-cells = <1>;
2594                         resets = <&gcc GCC_UF    2593                         resets = <&gcc GCC_UFS_PHY_BCR>;
2595                         reset-names = "rst";     2594                         reset-names = "rst";
2596                                                  2595 
2597                         iommus = <&apps_smmu     2596                         iommus = <&apps_smmu 0x100 0xf>;
2598                                                  2597 
2599                         clock-names =            2598                         clock-names =
2600                                 "core_clk",      2599                                 "core_clk",
2601                                 "bus_aggr_clk    2600                                 "bus_aggr_clk",
2602                                 "iface_clk",     2601                                 "iface_clk",
2603                                 "core_clk_uni    2602                                 "core_clk_unipro",
2604                                 "ref_clk",       2603                                 "ref_clk",
2605                                 "tx_lane0_syn    2604                                 "tx_lane0_sync_clk",
2606                                 "rx_lane0_syn    2605                                 "rx_lane0_sync_clk",
2607                                 "rx_lane1_syn    2606                                 "rx_lane1_sync_clk",
2608                                 "ice_core_clk    2607                                 "ice_core_clk";
2609                         clocks =                 2608                         clocks =
2610                                 <&gcc GCC_UFS    2609                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611                                 <&gcc GCC_AGG    2610                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612                                 <&gcc GCC_UFS    2611                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613                                 <&gcc GCC_UFS    2612                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614                                 <&rpmhcc RPMH    2613                                 <&rpmhcc RPMH_CXO_CLK>,
2615                                 <&gcc GCC_UFS    2614                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616                                 <&gcc GCC_UFS    2615                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617                                 <&gcc GCC_UFS    2616                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618                                 <&gcc GCC_UFS    2617                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619                                                  2618 
2620                         operating-points-v2 =    2619                         operating-points-v2 = <&ufs_opp_table>;
2621                                                  2620 
2622                         interconnects = <&agg    2621                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2623                                         <&gla    2622                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2624                         interconnect-names =     2623                         interconnect-names = "ufs-ddr", "cpu-ufs";
2625                                                  2624 
2626                         status = "disabled";     2625                         status = "disabled";
2627                                                  2626 
2628                         ufs_opp_table: opp-ta    2627                         ufs_opp_table: opp-table {
2629                                 compatible =     2628                                 compatible = "operating-points-v2";
2630                                                  2629 
2631                                 opp-50000000     2630                                 opp-50000000 {
2632                                         opp-h    2631                                         opp-hz = /bits/ 64 <50000000>,
2633                                                  2632                                                  /bits/ 64 <0>,
2634                                                  2633                                                  /bits/ 64 <0>,
2635                                                  2634                                                  /bits/ 64 <37500000>,
2636                                                  2635                                                  /bits/ 64 <0>,
2637                                                  2636                                                  /bits/ 64 <0>,
2638                                                  2637                                                  /bits/ 64 <0>,
2639                                                  2638                                                  /bits/ 64 <0>,
2640                                                  2639                                                  /bits/ 64 <75000000>;
2641                                         requi    2640                                         required-opps = <&rpmhpd_opp_low_svs>;
2642                                 };               2641                                 };
2643                                                  2642 
2644                                 opp-200000000    2643                                 opp-200000000 {
2645                                         opp-h    2644                                         opp-hz = /bits/ 64 <200000000>,
2646                                                  2645                                                  /bits/ 64 <0>,
2647                                                  2646                                                  /bits/ 64 <0>,
2648                                                  2647                                                  /bits/ 64 <150000000>,
2649                                                  2648                                                  /bits/ 64 <0>,
2650                                                  2649                                                  /bits/ 64 <0>,
2651                                                  2650                                                  /bits/ 64 <0>,
2652                                                  2651                                                  /bits/ 64 <0>,
2653                                                  2652                                                  /bits/ 64 <300000000>;
2654                                         requi    2653                                         required-opps = <&rpmhpd_opp_nom>;
2655                                 };               2654                                 };
2656                         };                       2655                         };
2657                 };                               2656                 };
2658                                                  2657 
2659                 ufs_mem_phy: phy@1d87000 {       2658                 ufs_mem_phy: phy@1d87000 {
2660                         compatible = "qcom,sd    2659                         compatible = "qcom,sdm845-qmp-ufs-phy";
2661                         reg = <0 0x01d87000 0    2660                         reg = <0 0x01d87000 0 0x1000>;
2662                                                  2661 
2663                         clocks = <&rpmhcc RPM    2662                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2664                                  <&gcc GCC_UF    2663                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2665                                  <&gcc GCC_UF    2664                                  <&gcc GCC_UFS_MEM_CLKREF_CLK>;
2666                         clock-names = "ref",     2665                         clock-names = "ref",
2667                                       "ref_au    2666                                       "ref_aux",
2668                                       "qref";    2667                                       "qref";
2669                                                  2668 
2670                         power-domains = <&gcc    2669                         power-domains = <&gcc UFS_PHY_GDSC>;
2671                                                  2670 
2672                         resets = <&ufs_mem_hc    2671                         resets = <&ufs_mem_hc 0>;
2673                         reset-names = "ufsphy    2672                         reset-names = "ufsphy";
2674                                                  2673 
2675                         #phy-cells = <0>;        2674                         #phy-cells = <0>;
2676                         status = "disabled";     2675                         status = "disabled";
2677                 };                               2676                 };
2678                                                  2677 
2679                 cryptobam: dma-controller@1dc    2678                 cryptobam: dma-controller@1dc4000 {
2680                         compatible = "qcom,ba    2679                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2681                         reg = <0 0x01dc4000 0    2680                         reg = <0 0x01dc4000 0 0x24000>;
2682                         interrupts = <GIC_SPI    2681                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683                         clocks = <&rpmhcc RPM    2682                         clocks = <&rpmhcc RPMH_CE_CLK>;
2684                         clock-names = "bam_cl    2683                         clock-names = "bam_clk";
2685                         #dma-cells = <1>;        2684                         #dma-cells = <1>;
2686                         qcom,ee = <0>;           2685                         qcom,ee = <0>;
2687                         qcom,controlled-remot    2686                         qcom,controlled-remotely;
2688                         iommus = <&apps_smmu     2687                         iommus = <&apps_smmu 0x704 0x1>,
2689                                  <&apps_smmu     2688                                  <&apps_smmu 0x706 0x1>,
2690                                  <&apps_smmu     2689                                  <&apps_smmu 0x714 0x1>,
2691                                  <&apps_smmu     2690                                  <&apps_smmu 0x716 0x1>;
2692                 };                               2691                 };
2693                                                  2692 
2694                 crypto: crypto@1dfa000 {         2693                 crypto: crypto@1dfa000 {
2695                         compatible = "qcom,cr    2694                         compatible = "qcom,crypto-v5.4";
2696                         reg = <0 0x01dfa000 0    2695                         reg = <0 0x01dfa000 0 0x6000>;
2697                         clocks = <&gcc GCC_CE    2696                         clocks = <&gcc GCC_CE1_AHB_CLK>,
2698                                  <&gcc GCC_CE    2697                                  <&gcc GCC_CE1_AXI_CLK>,
2699                                  <&rpmhcc RPM    2698                                  <&rpmhcc RPMH_CE_CLK>;
2700                         clock-names = "iface"    2699                         clock-names = "iface", "bus", "core";
2701                         dmas = <&cryptobam 6>    2700                         dmas = <&cryptobam 6>, <&cryptobam 7>;
2702                         dma-names = "rx", "tx    2701                         dma-names = "rx", "tx";
2703                         iommus = <&apps_smmu     2702                         iommus = <&apps_smmu 0x704 0x1>,
2704                                  <&apps_smmu     2703                                  <&apps_smmu 0x706 0x1>,
2705                                  <&apps_smmu     2704                                  <&apps_smmu 0x714 0x1>,
2706                                  <&apps_smmu     2705                                  <&apps_smmu 0x716 0x1>;
2707                 };                               2706                 };
2708                                                  2707 
2709                 ipa: ipa@1e40000 {               2708                 ipa: ipa@1e40000 {
2710                         compatible = "qcom,sd    2709                         compatible = "qcom,sdm845-ipa";
2711                                                  2710 
2712                         iommus = <&apps_smmu     2711                         iommus = <&apps_smmu 0x720 0x0>,
2713                                  <&apps_smmu     2712                                  <&apps_smmu 0x722 0x0>;
2714                         reg = <0 0x01e40000 0    2713                         reg = <0 0x01e40000 0 0x7000>,
2715                               <0 0x01e47000 0    2714                               <0 0x01e47000 0 0x2000>,
2716                               <0 0x01e04000 0    2715                               <0 0x01e04000 0 0x2c000>;
2717                         reg-names = "ipa-reg"    2716                         reg-names = "ipa-reg",
2718                                     "ipa-shar    2717                                     "ipa-shared",
2719                                     "gsi";       2718                                     "gsi";
2720                                                  2719 
2721                         interrupts-extended =    2720                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722                                                  2721                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723                                                  2722                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724                                                  2723                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725                         interrupt-names = "ip    2724                         interrupt-names = "ipa",
2726                                           "gs    2725                                           "gsi",
2727                                           "ip    2726                                           "ipa-clock-query",
2728                                           "ip    2727                                           "ipa-setup-ready";
2729                                                  2728 
2730                         clocks = <&rpmhcc RPM    2729                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2731                         clock-names = "core";    2730                         clock-names = "core";
2732                                                  2731 
2733                         interconnects = <&agg    2732                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734                                         <&agg    2733                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735                                         <&gla    2734                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736                         interconnect-names =     2735                         interconnect-names = "memory",
2737                                                  2736                                              "imem",
2738                                                  2737                                              "config";
2739                                                  2738 
2740                         qcom,smem-states = <&    2739                         qcom,smem-states = <&ipa_smp2p_out 0>,
2741                                            <&    2740                                            <&ipa_smp2p_out 1>;
2742                         qcom,smem-state-names    2741                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2743                                                  2742                                                 "ipa-clock-enabled";
2744                                                  2743 
2745                         status = "disabled";     2744                         status = "disabled";
2746                 };                               2745                 };
2747                                                  2746 
2748                 tcsr_mutex: hwlock@1f40000 {     2747                 tcsr_mutex: hwlock@1f40000 {
2749                         compatible = "qcom,tc    2748                         compatible = "qcom,tcsr-mutex";
2750                         reg = <0 0x01f40000 0    2749                         reg = <0 0x01f40000 0 0x20000>;
2751                         #hwlock-cells = <1>;     2750                         #hwlock-cells = <1>;
2752                 };                               2751                 };
2753                                                  2752 
2754                 tcsr_regs_1: syscon@1f60000 {    2753                 tcsr_regs_1: syscon@1f60000 {
2755                         compatible = "qcom,sd    2754                         compatible = "qcom,sdm845-tcsr", "syscon";
2756                         reg = <0 0x01f60000 0    2755                         reg = <0 0x01f60000 0 0x20000>;
2757                 };                               2756                 };
2758                                                  2757 
2759                 tlmm: pinctrl@3400000 {          2758                 tlmm: pinctrl@3400000 {
2760                         compatible = "qcom,sd    2759                         compatible = "qcom,sdm845-pinctrl";
2761                         reg = <0 0x03400000 0    2760                         reg = <0 0x03400000 0 0xc00000>;
2762                         interrupts = <GIC_SPI    2761                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763                         gpio-controller;         2762                         gpio-controller;
2764                         #gpio-cells = <2>;       2763                         #gpio-cells = <2>;
2765                         interrupt-controller;    2764                         interrupt-controller;
2766                         #interrupt-cells = <2    2765                         #interrupt-cells = <2>;
2767                         gpio-ranges = <&tlmm     2766                         gpio-ranges = <&tlmm 0 0 151>;
2768                         wakeup-parent = <&pdc    2767                         wakeup-parent = <&pdc_intc>;
2769                                                  2768 
2770                         cci0_default: cci0-de    2769                         cci0_default: cci0-default-state {
2771                                 /* SDA, SCL *    2770                                 /* SDA, SCL */
2772                                 pins = "gpio1    2771                                 pins = "gpio17", "gpio18";
2773                                 function = "c    2772                                 function = "cci_i2c";
2774                                                  2773 
2775                                 bias-pull-up;    2774                                 bias-pull-up;
2776                                 drive-strengt    2775                                 drive-strength = <2>; /* 2 mA */
2777                         };                       2776                         };
2778                                                  2777 
2779                         cci0_sleep: cci0-slee    2778                         cci0_sleep: cci0-sleep-state {
2780                                 /* SDA, SCL *    2779                                 /* SDA, SCL */
2781                                 pins = "gpio1    2780                                 pins = "gpio17", "gpio18";
2782                                 function = "c    2781                                 function = "cci_i2c";
2783                                                  2782 
2784                                 drive-strengt    2783                                 drive-strength = <2>; /* 2 mA */
2785                                 bias-pull-dow    2784                                 bias-pull-down;
2786                         };                       2785                         };
2787                                                  2786 
2788                         cci1_default: cci1-de    2787                         cci1_default: cci1-default-state {
2789                                 /* SDA, SCL *    2788                                 /* SDA, SCL */
2790                                 pins = "gpio1    2789                                 pins = "gpio19", "gpio20";
2791                                 function = "c    2790                                 function = "cci_i2c";
2792                                                  2791 
2793                                 bias-pull-up;    2792                                 bias-pull-up;
2794                                 drive-strengt    2793                                 drive-strength = <2>; /* 2 mA */
2795                         };                       2794                         };
2796                                                  2795 
2797                         cci1_sleep: cci1-slee    2796                         cci1_sleep: cci1-sleep-state {
2798                                 /* SDA, SCL *    2797                                 /* SDA, SCL */
2799                                 pins = "gpio1    2798                                 pins = "gpio19", "gpio20";
2800                                 function = "c    2799                                 function = "cci_i2c";
2801                                                  2800 
2802                                 drive-strengt    2801                                 drive-strength = <2>; /* 2 mA */
2803                                 bias-pull-dow    2802                                 bias-pull-down;
2804                         };                       2803                         };
2805                                                  2804 
2806                         qspi_clk: qspi-clk-st    2805                         qspi_clk: qspi-clk-state {
2807                                 pins = "gpio9    2806                                 pins = "gpio95";
2808                                 function = "q    2807                                 function = "qspi_clk";
2809                         };                       2808                         };
2810                                                  2809 
2811                         qspi_cs0: qspi-cs0-st    2810                         qspi_cs0: qspi-cs0-state {
2812                                 pins = "gpio9    2811                                 pins = "gpio90";
2813                                 function = "q    2812                                 function = "qspi_cs";
2814                         };                       2813                         };
2815                                                  2814 
2816                         qspi_cs1: qspi-cs1-st    2815                         qspi_cs1: qspi-cs1-state {
2817                                 pins = "gpio8    2816                                 pins = "gpio89";
2818                                 function = "q    2817                                 function = "qspi_cs";
2819                         };                       2818                         };
2820                                                  2819 
2821                         qspi_data0: qspi-data    2820                         qspi_data0: qspi-data0-state {
2822                                 pins = "gpio9    2821                                 pins = "gpio91";
2823                                 function = "q    2822                                 function = "qspi_data";
2824                         };                       2823                         };
2825                                                  2824 
2826                         qspi_data1: qspi-data    2825                         qspi_data1: qspi-data1-state {
2827                                 pins = "gpio9    2826                                 pins = "gpio92";
2828                                 function = "q    2827                                 function = "qspi_data";
2829                         };                       2828                         };
2830                                                  2829 
2831                         qspi_data23: qspi-dat    2830                         qspi_data23: qspi-data23-state {
2832                                 pins = "gpio9    2831                                 pins = "gpio93", "gpio94";
2833                                 function = "q    2832                                 function = "qspi_data";
2834                         };                       2833                         };
2835                                                  2834 
2836                         qup_i2c0_default: qup    2835                         qup_i2c0_default: qup-i2c0-default-state {
2837                                 pins = "gpio0    2836                                 pins = "gpio0", "gpio1";
2838                                 function = "q    2837                                 function = "qup0";
2839                         };                       2838                         };
2840                                                  2839 
2841                         qup_i2c1_default: qup    2840                         qup_i2c1_default: qup-i2c1-default-state {
2842                                 pins = "gpio1    2841                                 pins = "gpio17", "gpio18";
2843                                 function = "q    2842                                 function = "qup1";
2844                         };                       2843                         };
2845                                                  2844 
2846                         qup_i2c2_default: qup    2845                         qup_i2c2_default: qup-i2c2-default-state {
2847                                 pins = "gpio2    2846                                 pins = "gpio27", "gpio28";
2848                                 function = "q    2847                                 function = "qup2";
2849                         };                       2848                         };
2850                                                  2849 
2851                         qup_i2c3_default: qup    2850                         qup_i2c3_default: qup-i2c3-default-state {
2852                                 pins = "gpio4    2851                                 pins = "gpio41", "gpio42";
2853                                 function = "q    2852                                 function = "qup3";
2854                         };                       2853                         };
2855                                                  2854 
2856                         qup_i2c4_default: qup    2855                         qup_i2c4_default: qup-i2c4-default-state {
2857                                 pins = "gpio8    2856                                 pins = "gpio89", "gpio90";
2858                                 function = "q    2857                                 function = "qup4";
2859                         };                       2858                         };
2860                                                  2859 
2861                         qup_i2c5_default: qup    2860                         qup_i2c5_default: qup-i2c5-default-state {
2862                                 pins = "gpio8    2861                                 pins = "gpio85", "gpio86";
2863                                 function = "q    2862                                 function = "qup5";
2864                         };                       2863                         };
2865                                                  2864 
2866                         qup_i2c6_default: qup    2865                         qup_i2c6_default: qup-i2c6-default-state {
2867                                 pins = "gpio4    2866                                 pins = "gpio45", "gpio46";
2868                                 function = "q    2867                                 function = "qup6";
2869                         };                       2868                         };
2870                                                  2869 
2871                         qup_i2c7_default: qup    2870                         qup_i2c7_default: qup-i2c7-default-state {
2872                                 pins = "gpio9    2871                                 pins = "gpio93", "gpio94";
2873                                 function = "q    2872                                 function = "qup7";
2874                         };                       2873                         };
2875                                                  2874 
2876                         qup_i2c8_default: qup    2875                         qup_i2c8_default: qup-i2c8-default-state {
2877                                 pins = "gpio6    2876                                 pins = "gpio65", "gpio66";
2878                                 function = "q    2877                                 function = "qup8";
2879                         };                       2878                         };
2880                                                  2879 
2881                         qup_i2c9_default: qup    2880                         qup_i2c9_default: qup-i2c9-default-state {
2882                                 pins = "gpio6    2881                                 pins = "gpio6", "gpio7";
2883                                 function = "q    2882                                 function = "qup9";
2884                         };                       2883                         };
2885                                                  2884 
2886                         qup_i2c10_default: qu    2885                         qup_i2c10_default: qup-i2c10-default-state {
2887                                 pins = "gpio5    2886                                 pins = "gpio55", "gpio56";
2888                                 function = "q    2887                                 function = "qup10";
2889                         };                       2888                         };
2890                                                  2889 
2891                         qup_i2c11_default: qu    2890                         qup_i2c11_default: qup-i2c11-default-state {
2892                                 pins = "gpio3    2891                                 pins = "gpio31", "gpio32";
2893                                 function = "q    2892                                 function = "qup11";
2894                         };                       2893                         };
2895                                                  2894 
2896                         qup_i2c12_default: qu    2895                         qup_i2c12_default: qup-i2c12-default-state {
2897                                 pins = "gpio4    2896                                 pins = "gpio49", "gpio50";
2898                                 function = "q    2897                                 function = "qup12";
2899                         };                       2898                         };
2900                                                  2899 
2901                         qup_i2c13_default: qu    2900                         qup_i2c13_default: qup-i2c13-default-state {
2902                                 pins = "gpio1    2901                                 pins = "gpio105", "gpio106";
2903                                 function = "q    2902                                 function = "qup13";
2904                         };                       2903                         };
2905                                                  2904 
2906                         qup_i2c14_default: qu    2905                         qup_i2c14_default: qup-i2c14-default-state {
2907                                 pins = "gpio3    2906                                 pins = "gpio33", "gpio34";
2908                                 function = "q    2907                                 function = "qup14";
2909                         };                       2908                         };
2910                                                  2909 
2911                         qup_i2c15_default: qu    2910                         qup_i2c15_default: qup-i2c15-default-state {
2912                                 pins = "gpio8    2911                                 pins = "gpio81", "gpio82";
2913                                 function = "q    2912                                 function = "qup15";
2914                         };                       2913                         };
2915                                                  2914 
2916                         qup_spi0_default: qup    2915                         qup_spi0_default: qup-spi0-default-state {
2917                                 pins = "gpio0    2916                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2918                                 function = "q    2917                                 function = "qup0";
2919                         };                       2918                         };
2920                                                  2919 
2921                         qup_spi1_default: qup    2920                         qup_spi1_default: qup-spi1-default-state {
2922                                 pins = "gpio1    2921                                 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2923                                 function = "q    2922                                 function = "qup1";
2924                         };                       2923                         };
2925                                                  2924 
2926                         qup_spi2_default: qup    2925                         qup_spi2_default: qup-spi2-default-state {
2927                                 pins = "gpio2    2926                                 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2928                                 function = "q    2927                                 function = "qup2";
2929                         };                       2928                         };
2930                                                  2929 
2931                         qup_spi3_default: qup    2930                         qup_spi3_default: qup-spi3-default-state {
2932                                 pins = "gpio4    2931                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2933                                 function = "q    2932                                 function = "qup3";
2934                         };                       2933                         };
2935                                                  2934 
2936                         qup_spi4_default: qup    2935                         qup_spi4_default: qup-spi4-default-state {
2937                                 pins = "gpio8    2936                                 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2938                                 function = "q    2937                                 function = "qup4";
2939                         };                       2938                         };
2940                                                  2939 
2941                         qup_spi5_default: qup    2940                         qup_spi5_default: qup-spi5-default-state {
2942                                 pins = "gpio8    2941                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2943                                 function = "q    2942                                 function = "qup5";
2944                         };                       2943                         };
2945                                                  2944 
2946                         qup_spi6_default: qup    2945                         qup_spi6_default: qup-spi6-default-state {
2947                                 pins = "gpio4    2946                                 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2948                                 function = "q    2947                                 function = "qup6";
2949                         };                       2948                         };
2950                                                  2949 
2951                         qup_spi7_default: qup    2950                         qup_spi7_default: qup-spi7-default-state {
2952                                 pins = "gpio9    2951                                 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2953                                 function = "q    2952                                 function = "qup7";
2954                         };                       2953                         };
2955                                                  2954 
2956                         qup_spi8_default: qup    2955                         qup_spi8_default: qup-spi8-default-state {
2957                                 pins = "gpio6    2956                                 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2958                                 function = "q    2957                                 function = "qup8";
2959                         };                       2958                         };
2960                                                  2959 
2961                         qup_spi9_default: qup    2960                         qup_spi9_default: qup-spi9-default-state {
2962                                 pins = "gpio6    2961                                 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2963                                 function = "q    2962                                 function = "qup9";
2964                         };                       2963                         };
2965                                                  2964 
2966                         qup_spi10_default: qu    2965                         qup_spi10_default: qup-spi10-default-state {
2967                                 pins = "gpio5    2966                                 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2968                                 function = "q    2967                                 function = "qup10";
2969                         };                       2968                         };
2970                                                  2969 
2971                         qup_spi11_default: qu    2970                         qup_spi11_default: qup-spi11-default-state {
2972                                 pins = "gpio3    2971                                 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2973                                 function = "q    2972                                 function = "qup11";
2974                         };                       2973                         };
2975                                                  2974 
2976                         qup_spi12_default: qu    2975                         qup_spi12_default: qup-spi12-default-state {
2977                                 pins = "gpio4    2976                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2978                                 function = "q    2977                                 function = "qup12";
2979                         };                       2978                         };
2980                                                  2979 
2981                         qup_spi13_default: qu    2980                         qup_spi13_default: qup-spi13-default-state {
2982                                 pins = "gpio1    2981                                 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2983                                 function = "q    2982                                 function = "qup13";
2984                         };                       2983                         };
2985                                                  2984 
2986                         qup_spi14_default: qu    2985                         qup_spi14_default: qup-spi14-default-state {
2987                                 pins = "gpio3    2986                                 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2988                                 function = "q    2987                                 function = "qup14";
2989                         };                       2988                         };
2990                                                  2989 
2991                         qup_spi15_default: qu    2990                         qup_spi15_default: qup-spi15-default-state {
2992                                 pins = "gpio8    2991                                 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2993                                 function = "q    2992                                 function = "qup15";
2994                         };                       2993                         };
2995                                                  2994 
2996                         qup_uart0_default: qu    2995                         qup_uart0_default: qup-uart0-default-state {
2997                                 qup_uart0_tx:    2996                                 qup_uart0_tx: tx-pins {
2998                                         pins     2997                                         pins = "gpio2";
2999                                         funct    2998                                         function = "qup0";
3000                                 };               2999                                 };
3001                                                  3000 
3002                                 qup_uart0_rx:    3001                                 qup_uart0_rx: rx-pins {
3003                                         pins     3002                                         pins = "gpio3";
3004                                         funct    3003                                         function = "qup0";
3005                                 };               3004                                 };
3006                         };                       3005                         };
3007                                                  3006 
3008                         qup_uart1_default: qu    3007                         qup_uart1_default: qup-uart1-default-state {
3009                                 qup_uart1_tx:    3008                                 qup_uart1_tx: tx-pins {
3010                                         pins     3009                                         pins = "gpio19";
3011                                         funct    3010                                         function = "qup1";
3012                                 };               3011                                 };
3013                                                  3012 
3014                                 qup_uart1_rx:    3013                                 qup_uart1_rx: rx-pins {
3015                                         pins     3014                                         pins = "gpio20";
3016                                         funct    3015                                         function = "qup1";
3017                                 };               3016                                 };
3018                         };                       3017                         };
3019                                                  3018 
3020                         qup_uart2_default: qu    3019                         qup_uart2_default: qup-uart2-default-state {
3021                                 qup_uart2_tx:    3020                                 qup_uart2_tx: tx-pins {
3022                                         pins     3021                                         pins = "gpio29";
3023                                         funct    3022                                         function = "qup2";
3024                                 };               3023                                 };
3025                                                  3024 
3026                                 qup_uart2_rx:    3025                                 qup_uart2_rx: rx-pins {
3027                                         pins     3026                                         pins = "gpio30";
3028                                         funct    3027                                         function = "qup2";
3029                                 };               3028                                 };
3030                         };                       3029                         };
3031                                                  3030 
3032                         qup_uart3_default: qu    3031                         qup_uart3_default: qup-uart3-default-state {
3033                                 qup_uart3_tx:    3032                                 qup_uart3_tx: tx-pins {
3034                                         pins     3033                                         pins = "gpio43";
3035                                         funct    3034                                         function = "qup3";
3036                                 };               3035                                 };
3037                                                  3036 
3038                                 qup_uart3_rx:    3037                                 qup_uart3_rx: rx-pins {
3039                                         pins     3038                                         pins = "gpio44";
3040                                         funct    3039                                         function = "qup3";
3041                                 };               3040                                 };
3042                         };                       3041                         };
3043                                                  3042 
3044                         qup_uart3_4pin: qup-u    3043                         qup_uart3_4pin: qup-uart3-4pin-state {
3045                                 qup_uart3_4pi    3044                                 qup_uart3_4pin_cts: cts-pins {
3046                                         pins     3045                                         pins = "gpio41";
3047                                         funct    3046                                         function = "qup3";
3048                                 };               3047                                 };
3049                                                  3048 
3050                                 qup_uart3_4pi    3049                                 qup_uart3_4pin_rts_tx: rts-tx-pins {
3051                                         pins     3050                                         pins = "gpio42", "gpio43";
3052                                         funct    3051                                         function = "qup3";
3053                                 };               3052                                 };
3054                                                  3053 
3055                                 qup_uart3_4pi    3054                                 qup_uart3_4pin_rx: rx-pins {
3056                                         pins     3055                                         pins = "gpio44";
3057                                         funct    3056                                         function = "qup3";
3058                                 };               3057                                 };
3059                         };                       3058                         };
3060                                                  3059 
3061                         qup_uart4_default: qu    3060                         qup_uart4_default: qup-uart4-default-state {
3062                                 qup_uart4_tx:    3061                                 qup_uart4_tx: tx-pins {
3063                                         pins     3062                                         pins = "gpio91";
3064                                         funct    3063                                         function = "qup4";
3065                                 };               3064                                 };
3066                                                  3065 
3067                                 qup_uart4_rx:    3066                                 qup_uart4_rx: rx-pins {
3068                                         pins     3067                                         pins = "gpio92";
3069                                         funct    3068                                         function = "qup4";
3070                                 };               3069                                 };
3071                         };                       3070                         };
3072                                                  3071 
3073                         qup_uart5_default: qu    3072                         qup_uart5_default: qup-uart5-default-state {
3074                                 qup_uart5_tx:    3073                                 qup_uart5_tx: tx-pins {
3075                                         pins     3074                                         pins = "gpio87";
3076                                         funct    3075                                         function = "qup5";
3077                                 };               3076                                 };
3078                                                  3077 
3079                                 qup_uart5_rx:    3078                                 qup_uart5_rx: rx-pins {
3080                                         pins     3079                                         pins = "gpio88";
3081                                         funct    3080                                         function = "qup5";
3082                                 };               3081                                 };
3083                         };                       3082                         };
3084                                                  3083 
3085                         qup_uart6_default: qu    3084                         qup_uart6_default: qup-uart6-default-state {
3086                                 qup_uart6_tx:    3085                                 qup_uart6_tx: tx-pins {
3087                                         pins     3086                                         pins = "gpio47";
3088                                         funct    3087                                         function = "qup6";
3089                                 };               3088                                 };
3090                                                  3089 
3091                                 qup_uart6_rx:    3090                                 qup_uart6_rx: rx-pins {
3092                                         pins     3091                                         pins = "gpio48";
3093                                         funct    3092                                         function = "qup6";
3094                                 };               3093                                 };
3095                         };                       3094                         };
3096                                                  3095 
3097                         qup_uart6_4pin: qup-u    3096                         qup_uart6_4pin: qup-uart6-4pin-state {
3098                                 qup_uart6_4pi    3097                                 qup_uart6_4pin_cts: cts-pins {
3099                                         pins     3098                                         pins = "gpio45";
3100                                         funct    3099                                         function = "qup6";
3101                                         bias-    3100                                         bias-pull-down;
3102                                 };               3101                                 };
3103                                                  3102 
3104                                 qup_uart6_4pi    3103                                 qup_uart6_4pin_rts_tx: rts-tx-pins {
3105                                         pins     3104                                         pins = "gpio46", "gpio47";
3106                                         funct    3105                                         function = "qup6";
3107                                         drive    3106                                         drive-strength = <2>;
3108                                         bias-    3107                                         bias-disable;
3109                                 };               3108                                 };
3110                                                  3109 
3111                                 qup_uart6_4pi    3110                                 qup_uart6_4pin_rx: rx-pins {
3112                                         pins     3111                                         pins = "gpio48";
3113                                         funct    3112                                         function = "qup6";
3114                                         bias-    3113                                         bias-pull-up;
3115                                 };               3114                                 };
3116                         };                       3115                         };
3117                                                  3116 
3118                         qup_uart7_default: qu    3117                         qup_uart7_default: qup-uart7-default-state {
3119                                 qup_uart7_tx:    3118                                 qup_uart7_tx: tx-pins {
3120                                         pins     3119                                         pins = "gpio95";
3121                                         funct    3120                                         function = "qup7";
3122                                 };               3121                                 };
3123                                                  3122 
3124                                 qup_uart7_rx:    3123                                 qup_uart7_rx: rx-pins {
3125                                         pins     3124                                         pins = "gpio96";
3126                                         funct    3125                                         function = "qup7";
3127                                 };               3126                                 };
3128                         };                       3127                         };
3129                                                  3128 
3130                         qup_uart8_default: qu    3129                         qup_uart8_default: qup-uart8-default-state {
3131                                 qup_uart8_tx:    3130                                 qup_uart8_tx: tx-pins {
3132                                         pins     3131                                         pins = "gpio67";
3133                                         funct    3132                                         function = "qup8";
3134                                 };               3133                                 };
3135                                                  3134 
3136                                 qup_uart8_rx:    3135                                 qup_uart8_rx: rx-pins {
3137                                         pins     3136                                         pins = "gpio68";
3138                                         funct    3137                                         function = "qup8";
3139                                 };               3138                                 };
3140                         };                       3139                         };
3141                                                  3140 
3142                         qup_uart9_default: qu    3141                         qup_uart9_default: qup-uart9-default-state {
3143                                 qup_uart9_tx:    3142                                 qup_uart9_tx: tx-pins {
3144                                         pins     3143                                         pins = "gpio4";
3145                                         funct    3144                                         function = "qup9";
3146                                 };               3145                                 };
3147                                                  3146 
3148                                 qup_uart9_rx:    3147                                 qup_uart9_rx: rx-pins {
3149                                         pins     3148                                         pins = "gpio5";
3150                                         funct    3149                                         function = "qup9";
3151                                 };               3150                                 };
3152                         };                       3151                         };
3153                                                  3152 
3154                         qup_uart10_default: q    3153                         qup_uart10_default: qup-uart10-default-state {
3155                                 qup_uart10_tx    3154                                 qup_uart10_tx: tx-pins {
3156                                         pins     3155                                         pins = "gpio53";
3157                                         funct    3156                                         function = "qup10";
3158                                 };               3157                                 };
3159                                                  3158 
3160                                 qup_uart10_rx    3159                                 qup_uart10_rx: rx-pins {
3161                                         pins     3160                                         pins = "gpio54";
3162                                         funct    3161                                         function = "qup10";
3163                                 };               3162                                 };
3164                         };                       3163                         };
3165                                                  3164 
3166                         qup_uart11_default: q    3165                         qup_uart11_default: qup-uart11-default-state {
3167                                 qup_uart11_tx    3166                                 qup_uart11_tx: tx-pins {
3168                                         pins     3167                                         pins = "gpio33";
3169                                         funct    3168                                         function = "qup11";
3170                                 };               3169                                 };
3171                                                  3170 
3172                                 qup_uart11_rx    3171                                 qup_uart11_rx: rx-pins {
3173                                         pins     3172                                         pins = "gpio34";
3174                                         funct    3173                                         function = "qup11";
3175                                 };               3174                                 };
3176                         };                       3175                         };
3177                                                  3176 
3178                         qup_uart12_default: q    3177                         qup_uart12_default: qup-uart12-default-state {
3179                                 qup_uart12_tx    3178                                 qup_uart12_tx: tx-pins {
3180                                         pins     3179                                         pins = "gpio51";
3181                                         funct    3180                                         function = "qup0";
3182                                 };               3181                                 };
3183                                                  3182 
3184                                 qup_uart12_rx    3183                                 qup_uart12_rx: rx-pins {
3185                                         pins     3184                                         pins = "gpio52";
3186                                         funct    3185                                         function = "qup0";
3187                                 };               3186                                 };
3188                         };                       3187                         };
3189                                                  3188 
3190                         qup_uart13_default: q    3189                         qup_uart13_default: qup-uart13-default-state {
3191                                 qup_uart13_tx    3190                                 qup_uart13_tx: tx-pins {
3192                                         pins     3191                                         pins = "gpio107";
3193                                         funct    3192                                         function = "qup13";
3194                                 };               3193                                 };
3195                                                  3194 
3196                                 qup_uart13_rx    3195                                 qup_uart13_rx: rx-pins {
3197                                         pins     3196                                         pins = "gpio108";
3198                                         funct    3197                                         function = "qup13";
3199                                 };               3198                                 };
3200                         };                       3199                         };
3201                                                  3200 
3202                         qup_uart14_default: q    3201                         qup_uart14_default: qup-uart14-default-state {
3203                                 qup_uart14_tx    3202                                 qup_uart14_tx: tx-pins {
3204                                         pins     3203                                         pins = "gpio31";
3205                                         funct    3204                                         function = "qup14";
3206                                 };               3205                                 };
3207                                                  3206 
3208                                 qup_uart14_rx    3207                                 qup_uart14_rx: rx-pins {
3209                                         pins     3208                                         pins = "gpio32";
3210                                         funct    3209                                         function = "qup14";
3211                                 };               3210                                 };
3212                         };                       3211                         };
3213                                                  3212 
3214                         qup_uart15_default: q    3213                         qup_uart15_default: qup-uart15-default-state {
3215                                 qup_uart15_tx    3214                                 qup_uart15_tx: tx-pins {
3216                                         pins     3215                                         pins = "gpio83";
3217                                         funct    3216                                         function = "qup15";
3218                                 };               3217                                 };
3219                                                  3218 
3220                                 qup_uart15_rx    3219                                 qup_uart15_rx: rx-pins {
3221                                         pins     3220                                         pins = "gpio84";
3222                                         funct    3221                                         function = "qup15";
3223                                 };               3222                                 };
3224                         };                       3223                         };
3225                                                  3224 
3226                         quat_mi2s_sleep: quat    3225                         quat_mi2s_sleep: quat-mi2s-sleep-state {
3227                                 pins = "gpio5    3226                                 pins = "gpio58", "gpio59";
3228                                 function = "g    3227                                 function = "gpio";
3229                                 drive-strengt    3228                                 drive-strength = <2>;
3230                                 bias-pull-dow    3229                                 bias-pull-down;
3231                         };                       3230                         };
3232                                                  3231 
3233                         quat_mi2s_active: qua    3232                         quat_mi2s_active: quat-mi2s-active-state {
3234                                 pins = "gpio5    3233                                 pins = "gpio58", "gpio59";
3235                                 function = "q    3234                                 function = "qua_mi2s";
3236                                 drive-strengt    3235                                 drive-strength = <8>;
3237                                 bias-disable;    3236                                 bias-disable;
3238                                 output-high;     3237                                 output-high;
3239                         };                       3238                         };
3240                                                  3239 
3241                         quat_mi2s_sd0_sleep:     3240                         quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3242                                 pins = "gpio6    3241                                 pins = "gpio60";
3243                                 function = "g    3242                                 function = "gpio";
3244                                 drive-strengt    3243                                 drive-strength = <2>;
3245                                 bias-pull-dow    3244                                 bias-pull-down;
3246                         };                       3245                         };
3247                                                  3246 
3248                         quat_mi2s_sd0_active:    3247                         quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3249                                 pins = "gpio6    3248                                 pins = "gpio60";
3250                                 function = "q    3249                                 function = "qua_mi2s";
3251                                 drive-strengt    3250                                 drive-strength = <8>;
3252                                 bias-disable;    3251                                 bias-disable;
3253                         };                       3252                         };
3254                                                  3253 
3255                         quat_mi2s_sd1_sleep:     3254                         quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3256                                 pins = "gpio6    3255                                 pins = "gpio61";
3257                                 function = "g    3256                                 function = "gpio";
3258                                 drive-strengt    3257                                 drive-strength = <2>;
3259                                 bias-pull-dow    3258                                 bias-pull-down;
3260                         };                       3259                         };
3261                                                  3260 
3262                         quat_mi2s_sd1_active:    3261                         quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3263                                 pins = "gpio6    3262                                 pins = "gpio61";
3264                                 function = "q    3263                                 function = "qua_mi2s";
3265                                 drive-strengt    3264                                 drive-strength = <8>;
3266                                 bias-disable;    3265                                 bias-disable;
3267                         };                       3266                         };
3268                                                  3267 
3269                         quat_mi2s_sd2_sleep:     3268                         quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3270                                 pins = "gpio6    3269                                 pins = "gpio62";
3271                                 function = "g    3270                                 function = "gpio";
3272                                 drive-strengt    3271                                 drive-strength = <2>;
3273                                 bias-pull-dow    3272                                 bias-pull-down;
3274                         };                       3273                         };
3275                                                  3274 
3276                         quat_mi2s_sd2_active:    3275                         quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3277                                 pins = "gpio6    3276                                 pins = "gpio62";
3278                                 function = "q    3277                                 function = "qua_mi2s";
3279                                 drive-strengt    3278                                 drive-strength = <8>;
3280                                 bias-disable;    3279                                 bias-disable;
3281                         };                       3280                         };
3282                                                  3281 
3283                         quat_mi2s_sd3_sleep:     3282                         quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3284                                 pins = "gpio6    3283                                 pins = "gpio63";
3285                                 function = "g    3284                                 function = "gpio";
3286                                 drive-strengt    3285                                 drive-strength = <2>;
3287                                 bias-pull-dow    3286                                 bias-pull-down;
3288                         };                       3287                         };
3289                                                  3288 
3290                         quat_mi2s_sd3_active:    3289                         quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3291                                 pins = "gpio6    3290                                 pins = "gpio63";
3292                                 function = "q    3291                                 function = "qua_mi2s";
3293                                 drive-strengt    3292                                 drive-strength = <8>;
3294                                 bias-disable;    3293                                 bias-disable;
3295                         };                       3294                         };
3296                 };                               3295                 };
3297                                                  3296 
3298                 mss_pil: remoteproc@4080000 {    3297                 mss_pil: remoteproc@4080000 {
3299                         compatible = "qcom,sd    3298                         compatible = "qcom,sdm845-mss-pil";
3300                         reg = <0 0x04080000 0    3299                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301                         reg-names = "qdsp6",     3300                         reg-names = "qdsp6", "rmb";
3302                                                  3301 
3303                         interrupts-extended =    3302                         interrupts-extended =
3304                                 <&intc GIC_SP    3303                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305                                 <&modem_smp2p    3304                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306                                 <&modem_smp2p    3305                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307                                 <&modem_smp2p    3306                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308                                 <&modem_smp2p    3307                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309                                 <&modem_smp2p    3308                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310                         interrupt-names = "wd    3309                         interrupt-names = "wdog", "fatal", "ready",
3311                                           "ha    3310                                           "handover", "stop-ack",
3312                                           "sh    3311                                           "shutdown-ack";
3313                                                  3312 
3314                         clocks = <&gcc GCC_MS    3313                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315                                  <&gcc GCC_MS    3314                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316                                  <&gcc GCC_BO    3315                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317                                  <&gcc GCC_MS    3316                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318                                  <&gcc GCC_MS    3317                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319                                  <&gcc GCC_MS    3318                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320                                  <&gcc GCC_PR    3319                                  <&gcc GCC_PRNG_AHB_CLK>,
3321                                  <&rpmhcc RPM    3320                                  <&rpmhcc RPMH_CXO_CLK>;
3322                         clock-names = "iface"    3321                         clock-names = "iface", "bus", "mem", "gpll0_mss",
3323                                       "snoc_a    3322                                       "snoc_axi", "mnoc_axi", "prng", "xo";
3324                                                  3323 
3325                         qcom,qmp = <&aoss_qmp    3324                         qcom,qmp = <&aoss_qmp>;
3326                                                  3325 
3327                         qcom,smem-states = <&    3326                         qcom,smem-states = <&modem_smp2p_out 0>;
3328                         qcom,smem-state-names    3327                         qcom,smem-state-names = "stop";
3329                                                  3328 
3330                         resets = <&aoss_reset    3329                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331                                  <&pdc_reset     3330                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332                         reset-names = "mss_re    3331                         reset-names = "mss_restart", "pdc_reset";
3333                                                  3332 
3334                         qcom,halt-regs = <&tc    3333                         qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3335                                                  3334 
3336                         power-domains = <&rpm    3335                         power-domains = <&rpmhpd SDM845_CX>,
3337                                         <&rpm    3336                                         <&rpmhpd SDM845_MX>,
3338                                         <&rpm    3337                                         <&rpmhpd SDM845_MSS>;
3339                         power-domain-names =     3338                         power-domain-names = "cx", "mx", "mss";
3340                                                  3339 
3341                         status = "disabled";     3340                         status = "disabled";
3342                                                  3341 
3343                         mba {                    3342                         mba {
3344                                 memory-region    3343                                 memory-region = <&mba_region>;
3345                         };                       3344                         };
3346                                                  3345 
3347                         mpss {                   3346                         mpss {
3348                                 memory-region    3347                                 memory-region = <&mpss_region>;
3349                         };                       3348                         };
3350                                                  3349 
3351                         metadata {               3350                         metadata {
3352                                 memory-region    3351                                 memory-region = <&mdata_mem>;
3353                         };                       3352                         };
3354                                                  3353 
3355                         glink-edge {             3354                         glink-edge {
3356                                 interrupts =     3355                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357                                 label = "mode    3356                                 label = "modem";
3358                                 qcom,remote-p    3357                                 qcom,remote-pid = <1>;
3359                                 mboxes = <&ap    3358                                 mboxes = <&apss_shared 12>;
3360                         };                       3359                         };
3361                 };                               3360                 };
3362                                                  3361 
3363                 gpucc: clock-controller@50900    3362                 gpucc: clock-controller@5090000 {
3364                         compatible = "qcom,sd    3363                         compatible = "qcom,sdm845-gpucc";
3365                         reg = <0 0x05090000 0    3364                         reg = <0 0x05090000 0 0x9000>;
3366                         #clock-cells = <1>;      3365                         #clock-cells = <1>;
3367                         #reset-cells = <1>;      3366                         #reset-cells = <1>;
3368                         #power-domain-cells =    3367                         #power-domain-cells = <1>;
3369                         clocks = <&rpmhcc RPM    3368                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3370                                  <&gcc GCC_GP    3369                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371                                  <&gcc GCC_GP    3370                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372                         clock-names = "bi_tcx    3371                         clock-names = "bi_tcxo",
3373                                       "gcc_gp    3372                                       "gcc_gpu_gpll0_clk_src",
3374                                       "gcc_gp    3373                                       "gcc_gpu_gpll0_div_clk_src";
3375                 };                               3374                 };
3376                                                  3375 
3377                 slpi_pas: remoteproc@5c00000     3376                 slpi_pas: remoteproc@5c00000 {
3378                         compatible = "qcom,sd    3377                         compatible = "qcom,sdm845-slpi-pas";
3379                         reg = <0 0x5c00000 0     3378                         reg = <0 0x5c00000 0 0x4000>;
3380                                                  3379 
3381                         interrupts-extended =    3380                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3382                                                  3381                                                 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3383                                                  3382                                                 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3384                                                  3383                                                 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3385                                                  3384                                                 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3386                         interrupt-names = "wd    3385                         interrupt-names = "wdog", "fatal", "ready",
3387                                                  3386                                                 "handover", "stop-ack";
3388                                                  3387 
3389                         clocks = <&rpmhcc RPM    3388                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3390                         clock-names = "xo";      3389                         clock-names = "xo";
3391                                                  3390 
3392                         qcom,qmp = <&aoss_qmp    3391                         qcom,qmp = <&aoss_qmp>;
3393                                                  3392 
3394                         power-domains = <&rpm    3393                         power-domains = <&rpmhpd SDM845_LCX>,
3395                                         <&rpm    3394                                         <&rpmhpd SDM845_LMX>;
3396                         power-domain-names =     3395                         power-domain-names = "lcx", "lmx";
3397                                                  3396 
3398                         memory-region = <&slp    3397                         memory-region = <&slpi_mem>;
3399                                                  3398 
3400                         qcom,smem-states = <&    3399                         qcom,smem-states = <&slpi_smp2p_out 0>;
3401                         qcom,smem-state-names    3400                         qcom,smem-state-names = "stop";
3402                                                  3401 
3403                         status = "disabled";     3402                         status = "disabled";
3404                                                  3403 
3405                         glink-edge {             3404                         glink-edge {
3406                                 interrupts =     3405                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3407                                 label = "dsps    3406                                 label = "dsps";
3408                                 qcom,remote-p    3407                                 qcom,remote-pid = <3>;
3409                                 mboxes = <&ap    3408                                 mboxes = <&apss_shared 24>;
3410                                                  3409 
3411                                 fastrpc {        3410                                 fastrpc {
3412                                         compa    3411                                         compatible = "qcom,fastrpc";
3413                                         qcom,    3412                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3414                                         label    3413                                         label = "sdsp";
3415                                         qcom,    3414                                         qcom,non-secure-domain;
3416                                         qcom,    3415                                         qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3417                                                  3416                                                       QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3418                                         memor    3417                                         memory-region = <&fastrpc_mem>;
3419                                         #addr    3418                                         #address-cells = <1>;
3420                                         #size    3419                                         #size-cells = <0>;
3421                                                  3420 
3422                                         compu    3421                                         compute-cb@0 {
3423                                                  3422                                                 compatible = "qcom,fastrpc-compute-cb";
3424                                                  3423                                                 reg = <0>;
3425                                         };       3424                                         };
3426                                 };               3425                                 };
3427                         };                       3426                         };
3428                 };                               3427                 };
3429                                                  3428 
3430                 stm@6002000 {                    3429                 stm@6002000 {
3431                         compatible = "arm,cor    3430                         compatible = "arm,coresight-stm", "arm,primecell";
3432                         reg = <0 0x06002000 0    3431                         reg = <0 0x06002000 0 0x1000>,
3433                               <0 0x16280000 0    3432                               <0 0x16280000 0 0x180000>;
3434                         reg-names = "stm-base    3433                         reg-names = "stm-base", "stm-stimulus-base";
3435                                                  3434 
3436                         clocks = <&aoss_qmp>;    3435                         clocks = <&aoss_qmp>;
3437                         clock-names = "apb_pc    3436                         clock-names = "apb_pclk";
3438                                                  3437 
3439                         out-ports {              3438                         out-ports {
3440                                 port {           3439                                 port {
3441                                         stm_o    3440                                         stm_out: endpoint {
3442                                                  3441                                                 remote-endpoint =
3443                                                  3442                                                   <&funnel0_in7>;
3444                                         };       3443                                         };
3445                                 };               3444                                 };
3446                         };                       3445                         };
3447                 };                               3446                 };
3448                                                  3447 
3449                 funnel@6041000 {                 3448                 funnel@6041000 {
3450                         compatible = "arm,cor    3449                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451                         reg = <0 0x06041000 0    3450                         reg = <0 0x06041000 0 0x1000>;
3452                                                  3451 
3453                         clocks = <&aoss_qmp>;    3452                         clocks = <&aoss_qmp>;
3454                         clock-names = "apb_pc    3453                         clock-names = "apb_pclk";
3455                                                  3454 
3456                         out-ports {              3455                         out-ports {
3457                                 port {           3456                                 port {
3458                                         funne    3457                                         funnel0_out: endpoint {
3459                                                  3458                                                 remote-endpoint =
3460                                                  3459                                                   <&merge_funnel_in0>;
3461                                         };       3460                                         };
3462                                 };               3461                                 };
3463                         };                       3462                         };
3464                                                  3463 
3465                         in-ports {               3464                         in-ports {
3466                                 #address-cell    3465                                 #address-cells = <1>;
3467                                 #size-cells =    3466                                 #size-cells = <0>;
3468                                                  3467 
3469                                 port@7 {         3468                                 port@7 {
3470                                         reg =    3469                                         reg = <7>;
3471                                         funne    3470                                         funnel0_in7: endpoint {
3472                                                  3471                                                 remote-endpoint = <&stm_out>;
3473                                         };       3472                                         };
3474                                 };               3473                                 };
3475                         };                       3474                         };
3476                 };                               3475                 };
3477                                                  3476 
3478                 funnel@6043000 {                 3477                 funnel@6043000 {
3479                         compatible = "arm,cor    3478                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480                         reg = <0 0x06043000 0    3479                         reg = <0 0x06043000 0 0x1000>;
3481                                                  3480 
3482                         clocks = <&aoss_qmp>;    3481                         clocks = <&aoss_qmp>;
3483                         clock-names = "apb_pc    3482                         clock-names = "apb_pclk";
3484                                                  3483 
3485                         out-ports {              3484                         out-ports {
3486                                 port {           3485                                 port {
3487                                         funne    3486                                         funnel2_out: endpoint {
3488                                                  3487                                                 remote-endpoint =
3489                                                  3488                                                   <&merge_funnel_in2>;
3490                                         };       3489                                         };
3491                                 };               3490                                 };
3492                         };                       3491                         };
3493                                                  3492 
3494                         in-ports {               3493                         in-ports {
3495                                 #address-cell    3494                                 #address-cells = <1>;
3496                                 #size-cells =    3495                                 #size-cells = <0>;
3497                                                  3496 
3498                                 port@5 {         3497                                 port@5 {
3499                                         reg =    3498                                         reg = <5>;
3500                                         funne    3499                                         funnel2_in5: endpoint {
3501                                                  3500                                                 remote-endpoint =
3502                                                  3501                                                   <&apss_merge_funnel_out>;
3503                                         };       3502                                         };
3504                                 };               3503                                 };
3505                         };                       3504                         };
3506                 };                               3505                 };
3507                                                  3506 
3508                 funnel@6045000 {                 3507                 funnel@6045000 {
3509                         compatible = "arm,cor    3508                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510                         reg = <0 0x06045000 0    3509                         reg = <0 0x06045000 0 0x1000>;
3511                                                  3510 
3512                         clocks = <&aoss_qmp>;    3511                         clocks = <&aoss_qmp>;
3513                         clock-names = "apb_pc    3512                         clock-names = "apb_pclk";
3514                                                  3513 
3515                         out-ports {              3514                         out-ports {
3516                                 port {           3515                                 port {
3517                                         merge    3516                                         merge_funnel_out: endpoint {
3518                                                  3517                                                 remote-endpoint = <&etf_in>;
3519                                         };       3518                                         };
3520                                 };               3519                                 };
3521                         };                       3520                         };
3522                                                  3521 
3523                         in-ports {               3522                         in-ports {
3524                                 #address-cell    3523                                 #address-cells = <1>;
3525                                 #size-cells =    3524                                 #size-cells = <0>;
3526                                                  3525 
3527                                 port@0 {         3526                                 port@0 {
3528                                         reg =    3527                                         reg = <0>;
3529                                         merge    3528                                         merge_funnel_in0: endpoint {
3530                                                  3529                                                 remote-endpoint =
3531                                                  3530                                                   <&funnel0_out>;
3532                                         };       3531                                         };
3533                                 };               3532                                 };
3534                                                  3533 
3535                                 port@2 {         3534                                 port@2 {
3536                                         reg =    3535                                         reg = <2>;
3537                                         merge    3536                                         merge_funnel_in2: endpoint {
3538                                                  3537                                                 remote-endpoint =
3539                                                  3538                                                   <&funnel2_out>;
3540                                         };       3539                                         };
3541                                 };               3540                                 };
3542                         };                       3541                         };
3543                 };                               3542                 };
3544                                                  3543 
3545                 replicator@6046000 {             3544                 replicator@6046000 {
3546                         compatible = "arm,cor    3545                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547                         reg = <0 0x06046000 0    3546                         reg = <0 0x06046000 0 0x1000>;
3548                                                  3547 
3549                         clocks = <&aoss_qmp>;    3548                         clocks = <&aoss_qmp>;
3550                         clock-names = "apb_pc    3549                         clock-names = "apb_pclk";
3551                                                  3550 
3552                         out-ports {              3551                         out-ports {
3553                                 port {           3552                                 port {
3554                                         repli    3553                                         replicator_out: endpoint {
3555                                                  3554                                                 remote-endpoint = <&etr_in>;
3556                                         };       3555                                         };
3557                                 };               3556                                 };
3558                         };                       3557                         };
3559                                                  3558 
3560                         in-ports {               3559                         in-ports {
3561                                 port {           3560                                 port {
3562                                         repli    3561                                         replicator_in: endpoint {
3563                                                  3562                                                 remote-endpoint = <&etf_out>;
3564                                         };       3563                                         };
3565                                 };               3564                                 };
3566                         };                       3565                         };
3567                 };                               3566                 };
3568                                                  3567 
3569                 etf@6047000 {                    3568                 etf@6047000 {
3570                         compatible = "arm,cor    3569                         compatible = "arm,coresight-tmc", "arm,primecell";
3571                         reg = <0 0x06047000 0    3570                         reg = <0 0x06047000 0 0x1000>;
3572                                                  3571 
3573                         clocks = <&aoss_qmp>;    3572                         clocks = <&aoss_qmp>;
3574                         clock-names = "apb_pc    3573                         clock-names = "apb_pclk";
3575                                                  3574 
3576                         out-ports {              3575                         out-ports {
3577                                 port {           3576                                 port {
3578                                         etf_o    3577                                         etf_out: endpoint {
3579                                                  3578                                                 remote-endpoint =
3580                                                  3579                                                   <&replicator_in>;
3581                                         };       3580                                         };
3582                                 };               3581                                 };
3583                         };                       3582                         };
3584                                                  3583 
3585                         in-ports {               3584                         in-ports {
3586                                                  3585 
3587                                 port {           3586                                 port {
3588                                         etf_i    3587                                         etf_in: endpoint {
3589                                                  3588                                                 remote-endpoint =
3590                                                  3589                                                   <&merge_funnel_out>;
3591                                         };       3590                                         };
3592                                 };               3591                                 };
3593                         };                       3592                         };
3594                 };                               3593                 };
3595                                                  3594 
3596                 etr@6048000 {                    3595                 etr@6048000 {
3597                         compatible = "arm,cor    3596                         compatible = "arm,coresight-tmc", "arm,primecell";
3598                         reg = <0 0x06048000 0    3597                         reg = <0 0x06048000 0 0x1000>;
3599                                                  3598 
3600                         clocks = <&aoss_qmp>;    3599                         clocks = <&aoss_qmp>;
3601                         clock-names = "apb_pc    3600                         clock-names = "apb_pclk";
3602                         arm,scatter-gather;      3601                         arm,scatter-gather;
3603                                                  3602 
3604                         in-ports {               3603                         in-ports {
3605                                 port {           3604                                 port {
3606                                         etr_i    3605                                         etr_in: endpoint {
3607                                                  3606                                                 remote-endpoint =
3608                                                  3607                                                   <&replicator_out>;
3609                                         };       3608                                         };
3610                                 };               3609                                 };
3611                         };                       3610                         };
3612                 };                               3611                 };
3613                                                  3612 
3614                 etm@7040000 {                    3613                 etm@7040000 {
3615                         compatible = "arm,cor    3614                         compatible = "arm,coresight-etm4x", "arm,primecell";
3616                         reg = <0 0x07040000 0    3615                         reg = <0 0x07040000 0 0x1000>;
3617                                                  3616 
3618                         cpu = <&CPU0>;           3617                         cpu = <&CPU0>;
3619                                                  3618 
3620                         clocks = <&aoss_qmp>;    3619                         clocks = <&aoss_qmp>;
3621                         clock-names = "apb_pc    3620                         clock-names = "apb_pclk";
3622                         arm,coresight-loses-c    3621                         arm,coresight-loses-context-with-cpu;
3623                                                  3622 
3624                         out-ports {              3623                         out-ports {
3625                                 port {           3624                                 port {
3626                                         etm0_    3625                                         etm0_out: endpoint {
3627                                                  3626                                                 remote-endpoint =
3628                                                  3627                                                   <&apss_funnel_in0>;
3629                                         };       3628                                         };
3630                                 };               3629                                 };
3631                         };                       3630                         };
3632                 };                               3631                 };
3633                                                  3632 
3634                 etm@7140000 {                    3633                 etm@7140000 {
3635                         compatible = "arm,cor    3634                         compatible = "arm,coresight-etm4x", "arm,primecell";
3636                         reg = <0 0x07140000 0    3635                         reg = <0 0x07140000 0 0x1000>;
3637                                                  3636 
3638                         cpu = <&CPU1>;           3637                         cpu = <&CPU1>;
3639                                                  3638 
3640                         clocks = <&aoss_qmp>;    3639                         clocks = <&aoss_qmp>;
3641                         clock-names = "apb_pc    3640                         clock-names = "apb_pclk";
3642                         arm,coresight-loses-c    3641                         arm,coresight-loses-context-with-cpu;
3643                                                  3642 
3644                         out-ports {              3643                         out-ports {
3645                                 port {           3644                                 port {
3646                                         etm1_    3645                                         etm1_out: endpoint {
3647                                                  3646                                                 remote-endpoint =
3648                                                  3647                                                   <&apss_funnel_in1>;
3649                                         };       3648                                         };
3650                                 };               3649                                 };
3651                         };                       3650                         };
3652                 };                               3651                 };
3653                                                  3652 
3654                 etm@7240000 {                    3653                 etm@7240000 {
3655                         compatible = "arm,cor    3654                         compatible = "arm,coresight-etm4x", "arm,primecell";
3656                         reg = <0 0x07240000 0    3655                         reg = <0 0x07240000 0 0x1000>;
3657                                                  3656 
3658                         cpu = <&CPU2>;           3657                         cpu = <&CPU2>;
3659                                                  3658 
3660                         clocks = <&aoss_qmp>;    3659                         clocks = <&aoss_qmp>;
3661                         clock-names = "apb_pc    3660                         clock-names = "apb_pclk";
3662                         arm,coresight-loses-c    3661                         arm,coresight-loses-context-with-cpu;
3663                                                  3662 
3664                         out-ports {              3663                         out-ports {
3665                                 port {           3664                                 port {
3666                                         etm2_    3665                                         etm2_out: endpoint {
3667                                                  3666                                                 remote-endpoint =
3668                                                  3667                                                   <&apss_funnel_in2>;
3669                                         };       3668                                         };
3670                                 };               3669                                 };
3671                         };                       3670                         };
3672                 };                               3671                 };
3673                                                  3672 
3674                 etm@7340000 {                    3673                 etm@7340000 {
3675                         compatible = "arm,cor    3674                         compatible = "arm,coresight-etm4x", "arm,primecell";
3676                         reg = <0 0x07340000 0    3675                         reg = <0 0x07340000 0 0x1000>;
3677                                                  3676 
3678                         cpu = <&CPU3>;           3677                         cpu = <&CPU3>;
3679                                                  3678 
3680                         clocks = <&aoss_qmp>;    3679                         clocks = <&aoss_qmp>;
3681                         clock-names = "apb_pc    3680                         clock-names = "apb_pclk";
3682                         arm,coresight-loses-c    3681                         arm,coresight-loses-context-with-cpu;
3683                                                  3682 
3684                         out-ports {              3683                         out-ports {
3685                                 port {           3684                                 port {
3686                                         etm3_    3685                                         etm3_out: endpoint {
3687                                                  3686                                                 remote-endpoint =
3688                                                  3687                                                   <&apss_funnel_in3>;
3689                                         };       3688                                         };
3690                                 };               3689                                 };
3691                         };                       3690                         };
3692                 };                               3691                 };
3693                                                  3692 
3694                 etm@7440000 {                    3693                 etm@7440000 {
3695                         compatible = "arm,cor    3694                         compatible = "arm,coresight-etm4x", "arm,primecell";
3696                         reg = <0 0x07440000 0    3695                         reg = <0 0x07440000 0 0x1000>;
3697                                                  3696 
3698                         cpu = <&CPU4>;           3697                         cpu = <&CPU4>;
3699                                                  3698 
3700                         clocks = <&aoss_qmp>;    3699                         clocks = <&aoss_qmp>;
3701                         clock-names = "apb_pc    3700                         clock-names = "apb_pclk";
3702                         arm,coresight-loses-c    3701                         arm,coresight-loses-context-with-cpu;
3703                                                  3702 
3704                         out-ports {              3703                         out-ports {
3705                                 port {           3704                                 port {
3706                                         etm4_    3705                                         etm4_out: endpoint {
3707                                                  3706                                                 remote-endpoint =
3708                                                  3707                                                   <&apss_funnel_in4>;
3709                                         };       3708                                         };
3710                                 };               3709                                 };
3711                         };                       3710                         };
3712                 };                               3711                 };
3713                                                  3712 
3714                 etm@7540000 {                    3713                 etm@7540000 {
3715                         compatible = "arm,cor    3714                         compatible = "arm,coresight-etm4x", "arm,primecell";
3716                         reg = <0 0x07540000 0    3715                         reg = <0 0x07540000 0 0x1000>;
3717                                                  3716 
3718                         cpu = <&CPU5>;           3717                         cpu = <&CPU5>;
3719                                                  3718 
3720                         clocks = <&aoss_qmp>;    3719                         clocks = <&aoss_qmp>;
3721                         clock-names = "apb_pc    3720                         clock-names = "apb_pclk";
3722                         arm,coresight-loses-c    3721                         arm,coresight-loses-context-with-cpu;
3723                                                  3722 
3724                         out-ports {              3723                         out-ports {
3725                                 port {           3724                                 port {
3726                                         etm5_    3725                                         etm5_out: endpoint {
3727                                                  3726                                                 remote-endpoint =
3728                                                  3727                                                   <&apss_funnel_in5>;
3729                                         };       3728                                         };
3730                                 };               3729                                 };
3731                         };                       3730                         };
3732                 };                               3731                 };
3733                                                  3732 
3734                 etm@7640000 {                    3733                 etm@7640000 {
3735                         compatible = "arm,cor    3734                         compatible = "arm,coresight-etm4x", "arm,primecell";
3736                         reg = <0 0x07640000 0    3735                         reg = <0 0x07640000 0 0x1000>;
3737                                                  3736 
3738                         cpu = <&CPU6>;           3737                         cpu = <&CPU6>;
3739                                                  3738 
3740                         clocks = <&aoss_qmp>;    3739                         clocks = <&aoss_qmp>;
3741                         clock-names = "apb_pc    3740                         clock-names = "apb_pclk";
3742                         arm,coresight-loses-c    3741                         arm,coresight-loses-context-with-cpu;
3743                                                  3742 
3744                         out-ports {              3743                         out-ports {
3745                                 port {           3744                                 port {
3746                                         etm6_    3745                                         etm6_out: endpoint {
3747                                                  3746                                                 remote-endpoint =
3748                                                  3747                                                   <&apss_funnel_in6>;
3749                                         };       3748                                         };
3750                                 };               3749                                 };
3751                         };                       3750                         };
3752                 };                               3751                 };
3753                                                  3752 
3754                 etm@7740000 {                    3753                 etm@7740000 {
3755                         compatible = "arm,cor    3754                         compatible = "arm,coresight-etm4x", "arm,primecell";
3756                         reg = <0 0x07740000 0    3755                         reg = <0 0x07740000 0 0x1000>;
3757                                                  3756 
3758                         cpu = <&CPU7>;           3757                         cpu = <&CPU7>;
3759                                                  3758 
3760                         clocks = <&aoss_qmp>;    3759                         clocks = <&aoss_qmp>;
3761                         clock-names = "apb_pc    3760                         clock-names = "apb_pclk";
3762                         arm,coresight-loses-c    3761                         arm,coresight-loses-context-with-cpu;
3763                                                  3762 
3764                         out-ports {              3763                         out-ports {
3765                                 port {           3764                                 port {
3766                                         etm7_    3765                                         etm7_out: endpoint {
3767                                                  3766                                                 remote-endpoint =
3768                                                  3767                                                   <&apss_funnel_in7>;
3769                                         };       3768                                         };
3770                                 };               3769                                 };
3771                         };                       3770                         };
3772                 };                               3771                 };
3773                                                  3772 
3774                 funnel@7800000 { /* APSS Funn    3773                 funnel@7800000 { /* APSS Funnel */
3775                         compatible = "arm,cor    3774                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776                         reg = <0 0x07800000 0    3775                         reg = <0 0x07800000 0 0x1000>;
3777                                                  3776 
3778                         clocks = <&aoss_qmp>;    3777                         clocks = <&aoss_qmp>;
3779                         clock-names = "apb_pc    3778                         clock-names = "apb_pclk";
3780                                                  3779 
3781                         out-ports {              3780                         out-ports {
3782                                 port {           3781                                 port {
3783                                         apss_    3782                                         apss_funnel_out: endpoint {
3784                                                  3783                                                 remote-endpoint =
3785                                                  3784                                                   <&apss_merge_funnel_in>;
3786                                         };       3785                                         };
3787                                 };               3786                                 };
3788                         };                       3787                         };
3789                                                  3788 
3790                         in-ports {               3789                         in-ports {
3791                                 #address-cell    3790                                 #address-cells = <1>;
3792                                 #size-cells =    3791                                 #size-cells = <0>;
3793                                                  3792 
3794                                 port@0 {         3793                                 port@0 {
3795                                         reg =    3794                                         reg = <0>;
3796                                         apss_    3795                                         apss_funnel_in0: endpoint {
3797                                                  3796                                                 remote-endpoint =
3798                                                  3797                                                   <&etm0_out>;
3799                                         };       3798                                         };
3800                                 };               3799                                 };
3801                                                  3800 
3802                                 port@1 {         3801                                 port@1 {
3803                                         reg =    3802                                         reg = <1>;
3804                                         apss_    3803                                         apss_funnel_in1: endpoint {
3805                                                  3804                                                 remote-endpoint =
3806                                                  3805                                                   <&etm1_out>;
3807                                         };       3806                                         };
3808                                 };               3807                                 };
3809                                                  3808 
3810                                 port@2 {         3809                                 port@2 {
3811                                         reg =    3810                                         reg = <2>;
3812                                         apss_    3811                                         apss_funnel_in2: endpoint {
3813                                                  3812                                                 remote-endpoint =
3814                                                  3813                                                   <&etm2_out>;
3815                                         };       3814                                         };
3816                                 };               3815                                 };
3817                                                  3816 
3818                                 port@3 {         3817                                 port@3 {
3819                                         reg =    3818                                         reg = <3>;
3820                                         apss_    3819                                         apss_funnel_in3: endpoint {
3821                                                  3820                                                 remote-endpoint =
3822                                                  3821                                                   <&etm3_out>;
3823                                         };       3822                                         };
3824                                 };               3823                                 };
3825                                                  3824 
3826                                 port@4 {         3825                                 port@4 {
3827                                         reg =    3826                                         reg = <4>;
3828                                         apss_    3827                                         apss_funnel_in4: endpoint {
3829                                                  3828                                                 remote-endpoint =
3830                                                  3829                                                   <&etm4_out>;
3831                                         };       3830                                         };
3832                                 };               3831                                 };
3833                                                  3832 
3834                                 port@5 {         3833                                 port@5 {
3835                                         reg =    3834                                         reg = <5>;
3836                                         apss_    3835                                         apss_funnel_in5: endpoint {
3837                                                  3836                                                 remote-endpoint =
3838                                                  3837                                                   <&etm5_out>;
3839                                         };       3838                                         };
3840                                 };               3839                                 };
3841                                                  3840 
3842                                 port@6 {         3841                                 port@6 {
3843                                         reg =    3842                                         reg = <6>;
3844                                         apss_    3843                                         apss_funnel_in6: endpoint {
3845                                                  3844                                                 remote-endpoint =
3846                                                  3845                                                   <&etm6_out>;
3847                                         };       3846                                         };
3848                                 };               3847                                 };
3849                                                  3848 
3850                                 port@7 {         3849                                 port@7 {
3851                                         reg =    3850                                         reg = <7>;
3852                                         apss_    3851                                         apss_funnel_in7: endpoint {
3853                                                  3852                                                 remote-endpoint =
3854                                                  3853                                                   <&etm7_out>;
3855                                         };       3854                                         };
3856                                 };               3855                                 };
3857                         };                       3856                         };
3858                 };                               3857                 };
3859                                                  3858 
3860                 funnel@7810000 {                 3859                 funnel@7810000 {
3861                         compatible = "arm,cor    3860                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862                         reg = <0 0x07810000 0    3861                         reg = <0 0x07810000 0 0x1000>;
3863                                                  3862 
3864                         clocks = <&aoss_qmp>;    3863                         clocks = <&aoss_qmp>;
3865                         clock-names = "apb_pc    3864                         clock-names = "apb_pclk";
3866                                                  3865 
3867                         out-ports {              3866                         out-ports {
3868                                 port {           3867                                 port {
3869                                         apss_    3868                                         apss_merge_funnel_out: endpoint {
3870                                                  3869                                                 remote-endpoint =
3871                                                  3870                                                   <&funnel2_in5>;
3872                                         };       3871                                         };
3873                                 };               3872                                 };
3874                         };                       3873                         };
3875                                                  3874 
3876                         in-ports {               3875                         in-ports {
3877                                 port {           3876                                 port {
3878                                         apss_    3877                                         apss_merge_funnel_in: endpoint {
3879                                                  3878                                                 remote-endpoint =
3880                                                  3879                                                   <&apss_funnel_out>;
3881                                         };       3880                                         };
3882                                 };               3881                                 };
3883                         };                       3882                         };
3884                 };                               3883                 };
3885                                                  3884 
3886                 sdhc_2: mmc@8804000 {            3885                 sdhc_2: mmc@8804000 {
3887                         compatible = "qcom,sd    3886                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888                         reg = <0 0x08804000 0    3887                         reg = <0 0x08804000 0 0x1000>;
3889                                                  3888 
3890                         interrupts = <GIC_SPI    3889                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI    3890                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892                         interrupt-names = "hc    3891                         interrupt-names = "hc_irq", "pwr_irq";
3893                                                  3892 
3894                         clocks = <&gcc GCC_SD    3893                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895                                  <&gcc GCC_SD    3894                                  <&gcc GCC_SDCC2_APPS_CLK>,
3896                                  <&rpmhcc RPM    3895                                  <&rpmhcc RPMH_CXO_CLK>;
3897                         clock-names = "iface"    3896                         clock-names = "iface", "core", "xo";
3898                         iommus = <&apps_smmu     3897                         iommus = <&apps_smmu 0xa0 0xf>;
3899                         power-domains = <&rpm    3898                         power-domains = <&rpmhpd SDM845_CX>;
3900                         operating-points-v2 =    3899                         operating-points-v2 = <&sdhc2_opp_table>;
3901                                                  3900 
3902                         status = "disabled";     3901                         status = "disabled";
3903                                                  3902 
3904                         sdhc2_opp_table: opp-    3903                         sdhc2_opp_table: opp-table {
3905                                 compatible =     3904                                 compatible = "operating-points-v2";
3906                                                  3905 
3907                                 opp-9600000 {    3906                                 opp-9600000 {
3908                                         opp-h    3907                                         opp-hz = /bits/ 64 <9600000>;
3909                                         requi    3908                                         required-opps = <&rpmhpd_opp_min_svs>;
3910                                 };               3909                                 };
3911                                                  3910 
3912                                 opp-19200000     3911                                 opp-19200000 {
3913                                         opp-h    3912                                         opp-hz = /bits/ 64 <19200000>;
3914                                         requi    3913                                         required-opps = <&rpmhpd_opp_low_svs>;
3915                                 };               3914                                 };
3916                                                  3915 
3917                                 opp-100000000    3916                                 opp-100000000 {
3918                                         opp-h    3917                                         opp-hz = /bits/ 64 <100000000>;
3919                                         requi    3918                                         required-opps = <&rpmhpd_opp_svs>;
3920                                 };               3919                                 };
3921                                                  3920 
3922                                 opp-201500000    3921                                 opp-201500000 {
3923                                         opp-h    3922                                         opp-hz = /bits/ 64 <201500000>;
3924                                         requi    3923                                         required-opps = <&rpmhpd_opp_svs_l1>;
3925                                 };               3924                                 };
3926                         };                       3925                         };
3927                 };                               3926                 };
3928                                                  3927 
3929                 qspi: spi@88df000 {              3928                 qspi: spi@88df000 {
3930                         compatible = "qcom,sd    3929                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931                         reg = <0 0x088df000 0    3930                         reg = <0 0x088df000 0 0x600>;
3932                         iommus = <&apps_smmu     3931                         iommus = <&apps_smmu 0x160 0x0>;
3933                         #address-cells = <1>;    3932                         #address-cells = <1>;
3934                         #size-cells = <0>;       3933                         #size-cells = <0>;
3935                         interrupts = <GIC_SPI    3934                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936                         clocks = <&gcc GCC_QS    3935                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937                                  <&gcc GCC_QS    3936                                  <&gcc GCC_QSPI_CORE_CLK>;
3938                         clock-names = "iface"    3937                         clock-names = "iface", "core";
3939                         power-domains = <&rpm    3938                         power-domains = <&rpmhpd SDM845_CX>;
3940                         operating-points-v2 =    3939                         operating-points-v2 = <&qspi_opp_table>;
3941                         status = "disabled";     3940                         status = "disabled";
3942                 };                               3941                 };
3943                                                  3942 
3944                 slim: slim-ngd@171c0000 {        3943                 slim: slim-ngd@171c0000 {
3945                         compatible = "qcom,sl    3944                         compatible = "qcom,slim-ngd-v2.1.0";
3946                         reg = <0 0x171c0000 0    3945                         reg = <0 0x171c0000 0 0x2c000>;
3947                         interrupts = <GIC_SPI    3946                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948                                                  3947 
3949                         dmas = <&slimbam 3>,     3948                         dmas = <&slimbam 3>, <&slimbam 4>;
3950                         dma-names = "rx", "tx    3949                         dma-names = "rx", "tx";
3951                                                  3950 
3952                         iommus = <&apps_smmu     3951                         iommus = <&apps_smmu 0x1806 0x0>;
3953                         #address-cells = <1>;    3952                         #address-cells = <1>;
3954                         #size-cells = <0>;       3953                         #size-cells = <0>;
3955                         status = "disabled";     3954                         status = "disabled";
3956                 };                               3955                 };
3957                                                  3956 
3958                 lmh_cluster1: lmh@17d70800 {     3957                 lmh_cluster1: lmh@17d70800 {
3959                         compatible = "qcom,sd    3958                         compatible = "qcom,sdm845-lmh";
3960                         reg = <0 0x17d70800 0    3959                         reg = <0 0x17d70800 0 0x400>;
3961                         interrupts = <GIC_SPI    3960                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962                         cpus = <&CPU4>;          3961                         cpus = <&CPU4>;
3963                         qcom,lmh-temp-arm-mil    3962                         qcom,lmh-temp-arm-millicelsius = <65000>;
3964                         qcom,lmh-temp-low-mil    3963                         qcom,lmh-temp-low-millicelsius = <94500>;
3965                         qcom,lmh-temp-high-mi    3964                         qcom,lmh-temp-high-millicelsius = <95000>;
3966                         interrupt-controller;    3965                         interrupt-controller;
3967                         #interrupt-cells = <1    3966                         #interrupt-cells = <1>;
3968                 };                               3967                 };
3969                                                  3968 
3970                 lmh_cluster0: lmh@17d78800 {     3969                 lmh_cluster0: lmh@17d78800 {
3971                         compatible = "qcom,sd    3970                         compatible = "qcom,sdm845-lmh";
3972                         reg = <0 0x17d78800 0    3971                         reg = <0 0x17d78800 0 0x400>;
3973                         interrupts = <GIC_SPI    3972                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974                         cpus = <&CPU0>;          3973                         cpus = <&CPU0>;
3975                         qcom,lmh-temp-arm-mil    3974                         qcom,lmh-temp-arm-millicelsius = <65000>;
3976                         qcom,lmh-temp-low-mil    3975                         qcom,lmh-temp-low-millicelsius = <94500>;
3977                         qcom,lmh-temp-high-mi    3976                         qcom,lmh-temp-high-millicelsius = <95000>;
3978                         interrupt-controller;    3977                         interrupt-controller;
3979                         #interrupt-cells = <1    3978                         #interrupt-cells = <1>;
3980                 };                               3979                 };
3981                                                  3980 
3982                 usb_1_hsphy: phy@88e2000 {       3981                 usb_1_hsphy: phy@88e2000 {
3983                         compatible = "qcom,sd    3982                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984                         reg = <0 0x088e2000 0    3983                         reg = <0 0x088e2000 0 0x400>;
3985                         status = "disabled";     3984                         status = "disabled";
3986                         #phy-cells = <0>;        3985                         #phy-cells = <0>;
3987                                                  3986 
3988                         clocks = <&gcc GCC_US    3987                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989                                  <&rpmhcc RPM    3988                                  <&rpmhcc RPMH_CXO_CLK>;
3990                         clock-names = "cfg_ah    3989                         clock-names = "cfg_ahb", "ref";
3991                                                  3990 
3992                         resets = <&gcc GCC_QU    3991                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993                                                  3992 
3994                         nvmem-cells = <&qusb2    3993                         nvmem-cells = <&qusb2p_hstx_trim>;
3995                 };                               3994                 };
3996                                                  3995 
3997                 usb_2_hsphy: phy@88e3000 {       3996                 usb_2_hsphy: phy@88e3000 {
3998                         compatible = "qcom,sd    3997                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999                         reg = <0 0x088e3000 0    3998                         reg = <0 0x088e3000 0 0x400>;
4000                         status = "disabled";     3999                         status = "disabled";
4001                         #phy-cells = <0>;        4000                         #phy-cells = <0>;
4002                                                  4001 
4003                         clocks = <&gcc GCC_US    4002                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004                                  <&rpmhcc RPM    4003                                  <&rpmhcc RPMH_CXO_CLK>;
4005                         clock-names = "cfg_ah    4004                         clock-names = "cfg_ahb", "ref";
4006                                                  4005 
4007                         resets = <&gcc GCC_QU    4006                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008                                                  4007 
4009                         nvmem-cells = <&qusb2    4008                         nvmem-cells = <&qusb2s_hstx_trim>;
4010                 };                               4009                 };
4011                                                  4010 
4012                 usb_1_qmpphy: phy@88e8000 {      4011                 usb_1_qmpphy: phy@88e8000 {
4013                         compatible = "qcom,sd    4012                         compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4014                         reg = <0 0x088e8000 0    4013                         reg = <0 0x088e8000 0 0x3000>;
4015                         status = "disabled";     4014                         status = "disabled";
4016                                                  4015 
4017                         clocks = <&gcc GCC_US    4016                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
4018                                  <&gcc GCC_US    4017                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019                                  <&gcc GCC_US    4018                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
4020                                  <&gcc GCC_US    4019                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
4021                                  <&gcc GCC_US    4020                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
4022                         clock-names = "aux",     4021                         clock-names = "aux",
4023                                       "ref",     4022                                       "ref",
4024                                       "com_au    4023                                       "com_aux",
4025                                       "usb3_p    4024                                       "usb3_pipe",
4026                                       "cfg_ah    4025                                       "cfg_ahb";
4027                                                  4026 
4028                         resets = <&gcc GCC_US    4027                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4029                                  <&gcc GCC_US    4028                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4030                         reset-names = "phy",     4029                         reset-names = "phy", "common";
4031                                                  4030 
4032                         #clock-cells = <1>;      4031                         #clock-cells = <1>;
4033                         #phy-cells = <1>;        4032                         #phy-cells = <1>;
4034                         orientation-switch;   << 
4035                                               << 
4036                         ports {               << 
4037                                 #address-cell << 
4038                                 #size-cells = << 
4039                                               << 
4040                                 port@0 {      << 
4041                                         reg = << 
4042                                               << 
4043                                         usb_1 << 
4044                                         };    << 
4045                                 };            << 
4046                                               << 
4047                                 port@1 {      << 
4048                                         reg = << 
4049                                               << 
4050                                         usb_1 << 
4051                                               << 
4052                                         };    << 
4053                                 };            << 
4054                                               << 
4055                                 port@2 {      << 
4056                                         reg = << 
4057                                               << 
4058                                         usb_1 << 
4059                                               << 
4060                                         };    << 
4061                                 };            << 
4062                         };                    << 
4063                 };                               4033                 };
4064                                                  4034 
4065                 usb_2_qmpphy: phy@88eb000 {      4035                 usb_2_qmpphy: phy@88eb000 {
4066                         compatible = "qcom,sd    4036                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067                         reg = <0 0x088eb000 0    4037                         reg = <0 0x088eb000 0 0x1000>;
4068                                                  4038 
4069                         clocks = <&gcc GCC_US    4039                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070                                  <&gcc GCC_US    4040                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071                                  <&gcc GCC_US    4041                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072                                  <&gcc GCC_US    4042                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
4073                                  <&gcc GCC_US    4043                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
4074                         clock-names = "aux",     4044                         clock-names = "aux",
4075                                       "cfg_ah    4045                                       "cfg_ahb",
4076                                       "ref",     4046                                       "ref",
4077                                       "com_au    4047                                       "com_aux",
4078                                       "pipe";    4048                                       "pipe";
4079                         clock-output-names =     4049                         clock-output-names = "usb3_uni_phy_pipe_clk_src";
4080                         #clock-cells = <0>;      4050                         #clock-cells = <0>;
4081                         #phy-cells = <0>;        4051                         #phy-cells = <0>;
4082                                                  4052 
4083                         resets = <&gcc GCC_US    4053                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
4084                                  <&gcc GCC_US    4054                                  <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
4085                         reset-names = "phy",     4055                         reset-names = "phy",
4086                                       "phy_ph    4056                                       "phy_phy";
4087                                                  4057 
4088                         status = "disabled";     4058                         status = "disabled";
4089                 };                               4059                 };
4090                                                  4060 
4091                 usb_1: usb@a6f8800 {             4061                 usb_1: usb@a6f8800 {
4092                         compatible = "qcom,sd    4062                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093                         reg = <0 0x0a6f8800 0    4063                         reg = <0 0x0a6f8800 0 0x400>;
4094                         status = "disabled";     4064                         status = "disabled";
4095                         #address-cells = <2>;    4065                         #address-cells = <2>;
4096                         #size-cells = <2>;       4066                         #size-cells = <2>;
4097                         ranges;                  4067                         ranges;
4098                         dma-ranges;              4068                         dma-ranges;
4099                                                  4069 
4100                         clocks = <&gcc GCC_CF    4070                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101                                  <&gcc GCC_US    4071                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102                                  <&gcc GCC_AG    4072                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103                                  <&gcc GCC_US    4073                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4104                                  <&gcc GCC_US    4074                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4105                         clock-names = "cfg_no    4075                         clock-names = "cfg_noc",
4106                                       "core",    4076                                       "core",
4107                                       "iface"    4077                                       "iface",
4108                                       "sleep"    4078                                       "sleep",
4109                                       "mock_u    4079                                       "mock_utmi";
4110                                                  4080 
4111                         assigned-clocks = <&g    4081                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112                                           <&g    4082                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113                         assigned-clock-rates     4083                         assigned-clock-rates = <19200000>, <150000000>;
4114                                                  4084 
4115                         interrupts-extended =    4085                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4116                                                  4086                                               <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4117                                                  4087                                               <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>,
4118                                                  4088                                               <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>,
4119                                                  4089                                               <&pdc_intc 6 IRQ_TYPE_LEVEL_HIGH>;
4120                         interrupt-names = "pw    4090                         interrupt-names = "pwr_event",
4121                                           "hs    4091                                           "hs_phy_irq",
4122                                           "dp    4092                                           "dp_hs_phy_irq",
4123                                           "dm    4093                                           "dm_hs_phy_irq",
4124                                           "ss    4094                                           "ss_phy_irq";
4125                                                  4095 
4126                         power-domains = <&gcc    4096                         power-domains = <&gcc USB30_PRIM_GDSC>;
4127                                                  4097 
4128                         resets = <&gcc GCC_US    4098                         resets = <&gcc GCC_USB30_PRIM_BCR>;
4129                                                  4099 
4130                         interconnects = <&agg    4100                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131                                         <&gla    4101                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132                         interconnect-names =     4102                         interconnect-names = "usb-ddr", "apps-usb";
4133                                                  4103 
4134                         usb_1_dwc3: usb@a6000    4104                         usb_1_dwc3: usb@a600000 {
4135                                 compatible =     4105                                 compatible = "snps,dwc3";
4136                                 reg = <0 0x0a    4106                                 reg = <0 0x0a600000 0 0xcd00>;
4137                                 interrupts =     4107                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138                                 iommus = <&ap    4108                                 iommus = <&apps_smmu 0x740 0>;
4139                                 snps,dis_u2_s    4109                                 snps,dis_u2_susphy_quirk;
4140                                 snps,dis_enbl    4110                                 snps,dis_enblslpm_quirk;
4141                                 snps,parkmode    4111                                 snps,parkmode-disable-ss-quirk;
4142                                 phys = <&usb_    4112                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
4143                                 phy-names = "    4113                                 phy-names = "usb2-phy", "usb3-phy";
4144                                               << 
4145                                 ports {       << 
4146                                         #addr << 
4147                                         #size << 
4148                                               << 
4149                                         port@ << 
4150                                               << 
4151                                               << 
4152                                               << 
4153                                               << 
4154                                         };    << 
4155                                               << 
4156                                         port@ << 
4157                                               << 
4158                                               << 
4159                                               << 
4160                                               << 
4161                                               << 
4162                                         };    << 
4163                                 };            << 
4164                         };                       4114                         };
4165                 };                               4115                 };
4166                                                  4116 
4167                 usb_2: usb@a8f8800 {             4117                 usb_2: usb@a8f8800 {
4168                         compatible = "qcom,sd    4118                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169                         reg = <0 0x0a8f8800 0    4119                         reg = <0 0x0a8f8800 0 0x400>;
4170                         status = "disabled";     4120                         status = "disabled";
4171                         #address-cells = <2>;    4121                         #address-cells = <2>;
4172                         #size-cells = <2>;       4122                         #size-cells = <2>;
4173                         ranges;                  4123                         ranges;
4174                         dma-ranges;              4124                         dma-ranges;
4175                                                  4125 
4176                         clocks = <&gcc GCC_CF    4126                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177                                  <&gcc GCC_US    4127                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178                                  <&gcc GCC_AG    4128                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179                                  <&gcc GCC_US    4129                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4180                                  <&gcc GCC_US    4130                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4181                         clock-names = "cfg_no    4131                         clock-names = "cfg_noc",
4182                                       "core",    4132                                       "core",
4183                                       "iface"    4133                                       "iface",
4184                                       "sleep"    4134                                       "sleep",
4185                                       "mock_u    4135                                       "mock_utmi";
4186                                                  4136 
4187                         assigned-clocks = <&g    4137                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188                                           <&g    4138                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189                         assigned-clock-rates     4139                         assigned-clock-rates = <19200000>, <150000000>;
4190                                                  4140 
4191                         interrupts-extended =    4141                         interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
4192                                                  4142                                               <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4193                                                  4143                                               <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>,
4194                                                  4144                                               <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>,
4195                                                  4145                                               <&pdc_intc 7 IRQ_TYPE_LEVEL_HIGH>;
4196                         interrupt-names = "pw    4146                         interrupt-names = "pwr_event",
4197                                           "hs    4147                                           "hs_phy_irq",
4198                                           "dp    4148                                           "dp_hs_phy_irq",
4199                                           "dm    4149                                           "dm_hs_phy_irq",
4200                                           "ss    4150                                           "ss_phy_irq";
4201                                                  4151 
4202                         power-domains = <&gcc    4152                         power-domains = <&gcc USB30_SEC_GDSC>;
4203                                                  4153 
4204                         resets = <&gcc GCC_US    4154                         resets = <&gcc GCC_USB30_SEC_BCR>;
4205                                                  4155 
4206                         interconnects = <&agg    4156                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207                                         <&gla    4157                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208                         interconnect-names =     4158                         interconnect-names = "usb-ddr", "apps-usb";
4209                                                  4159 
4210                         usb_2_dwc3: usb@a8000    4160                         usb_2_dwc3: usb@a800000 {
4211                                 compatible =     4161                                 compatible = "snps,dwc3";
4212                                 reg = <0 0x0a    4162                                 reg = <0 0x0a800000 0 0xcd00>;
4213                                 interrupts =     4163                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214                                 iommus = <&ap    4164                                 iommus = <&apps_smmu 0x760 0>;
4215                                 snps,dis_u2_s    4165                                 snps,dis_u2_susphy_quirk;
4216                                 snps,dis_enbl    4166                                 snps,dis_enblslpm_quirk;
4217                                 snps,parkmode    4167                                 snps,parkmode-disable-ss-quirk;
4218                                 phys = <&usb_    4168                                 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
4219                                 phy-names = "    4169                                 phy-names = "usb2-phy", "usb3-phy";
4220                         };                       4170                         };
4221                 };                               4171                 };
4222                                                  4172 
4223                 venus: video-codec@aa00000 {     4173                 venus: video-codec@aa00000 {
4224                         compatible = "qcom,sd    4174                         compatible = "qcom,sdm845-venus-v2";
4225                         reg = <0 0x0aa00000 0    4175                         reg = <0 0x0aa00000 0 0xff000>;
4226                         interrupts = <GIC_SPI    4176                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227                         power-domains = <&vid    4177                         power-domains = <&videocc VENUS_GDSC>,
4228                                         <&vid    4178                                         <&videocc VCODEC0_GDSC>,
4229                                         <&vid    4179                                         <&videocc VCODEC1_GDSC>,
4230                                         <&rpm    4180                                         <&rpmhpd SDM845_CX>;
4231                         power-domain-names =     4181                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232                         operating-points-v2 =    4182                         operating-points-v2 = <&venus_opp_table>;
4233                         clocks = <&videocc VI    4183                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234                                  <&videocc VI    4184                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235                                  <&videocc VI    4185                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236                                  <&videocc VI    4186                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237                                  <&videocc VI    4187                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238                                  <&videocc VI    4188                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239                                  <&videocc VI    4189                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240                         clock-names = "core",    4190                         clock-names = "core", "iface", "bus",
4241                                       "vcodec    4191                                       "vcodec0_core", "vcodec0_bus",
4242                                       "vcodec    4192                                       "vcodec1_core", "vcodec1_bus";
4243                         iommus = <&apps_smmu     4193                         iommus = <&apps_smmu 0x10a0 0x8>,
4244                                  <&apps_smmu     4194                                  <&apps_smmu 0x10b0 0x0>;
4245                         memory-region = <&ven    4195                         memory-region = <&venus_mem>;
4246                         interconnects = <&mms    4196                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247                                         <&gla    4197                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248                         interconnect-names =     4198                         interconnect-names = "video-mem", "cpu-cfg";
4249                                                  4199 
4250                         status = "disabled";     4200                         status = "disabled";
4251                                                  4201 
4252                         video-core0 {            4202                         video-core0 {
4253                                 compatible =     4203                                 compatible = "venus-decoder";
4254                         };                       4204                         };
4255                                                  4205 
4256                         video-core1 {            4206                         video-core1 {
4257                                 compatible =     4207                                 compatible = "venus-encoder";
4258                         };                       4208                         };
4259                                                  4209 
4260                         venus_opp_table: opp-    4210                         venus_opp_table: opp-table {
4261                                 compatible =     4211                                 compatible = "operating-points-v2";
4262                                                  4212 
4263                                 opp-100000000    4213                                 opp-100000000 {
4264                                         opp-h    4214                                         opp-hz = /bits/ 64 <100000000>;
4265                                         requi    4215                                         required-opps = <&rpmhpd_opp_min_svs>;
4266                                 };               4216                                 };
4267                                                  4217 
4268                                 opp-200000000    4218                                 opp-200000000 {
4269                                         opp-h    4219                                         opp-hz = /bits/ 64 <200000000>;
4270                                         requi    4220                                         required-opps = <&rpmhpd_opp_low_svs>;
4271                                 };               4221                                 };
4272                                                  4222 
4273                                 opp-320000000    4223                                 opp-320000000 {
4274                                         opp-h    4224                                         opp-hz = /bits/ 64 <320000000>;
4275                                         requi    4225                                         required-opps = <&rpmhpd_opp_svs>;
4276                                 };               4226                                 };
4277                                                  4227 
4278                                 opp-380000000    4228                                 opp-380000000 {
4279                                         opp-h    4229                                         opp-hz = /bits/ 64 <380000000>;
4280                                         requi    4230                                         required-opps = <&rpmhpd_opp_svs_l1>;
4281                                 };               4231                                 };
4282                                                  4232 
4283                                 opp-444000000    4233                                 opp-444000000 {
4284                                         opp-h    4234                                         opp-hz = /bits/ 64 <444000000>;
4285                                         requi    4235                                         required-opps = <&rpmhpd_opp_nom>;
4286                                 };               4236                                 };
4287                                                  4237 
4288                                 opp-533000097    4238                                 opp-533000097 {
4289                                         opp-h    4239                                         opp-hz = /bits/ 64 <533000097>;
4290                                         requi    4240                                         required-opps = <&rpmhpd_opp_turbo>;
4291                                 };               4241                                 };
4292                         };                       4242                         };
4293                 };                               4243                 };
4294                                                  4244 
4295                 videocc: clock-controller@ab0    4245                 videocc: clock-controller@ab00000 {
4296                         compatible = "qcom,sd    4246                         compatible = "qcom,sdm845-videocc";
4297                         reg = <0 0x0ab00000 0    4247                         reg = <0 0x0ab00000 0 0x10000>;
4298                         clocks = <&rpmhcc RPM    4248                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4299                         clock-names = "bi_tcx    4249                         clock-names = "bi_tcxo";
4300                         #clock-cells = <1>;      4250                         #clock-cells = <1>;
4301                         #power-domain-cells =    4251                         #power-domain-cells = <1>;
4302                         #reset-cells = <1>;      4252                         #reset-cells = <1>;
4303                 };                               4253                 };
4304                                                  4254 
4305                 camss: camss@acb3000 {           4255                 camss: camss@acb3000 {
4306                         compatible = "qcom,sd    4256                         compatible = "qcom,sdm845-camss";
4307                                                  4257 
4308                         reg = <0 0x0acb3000 0    4258                         reg = <0 0x0acb3000 0 0x1000>,
4309                                 <0 0x0acba000    4259                                 <0 0x0acba000 0 0x1000>,
4310                                 <0 0x0acc8000    4260                                 <0 0x0acc8000 0 0x1000>,
4311                                 <0 0x0ac65000    4261                                 <0 0x0ac65000 0 0x1000>,
4312                                 <0 0x0ac66000    4262                                 <0 0x0ac66000 0 0x1000>,
4313                                 <0 0x0ac67000    4263                                 <0 0x0ac67000 0 0x1000>,
4314                                 <0 0x0ac68000    4264                                 <0 0x0ac68000 0 0x1000>,
4315                                 <0 0x0acaf000    4265                                 <0 0x0acaf000 0 0x4000>,
4316                                 <0 0x0acb6000    4266                                 <0 0x0acb6000 0 0x4000>,
4317                                 <0 0x0acc4000    4267                                 <0 0x0acc4000 0 0x4000>;
4318                         reg-names = "csid0",     4268                         reg-names = "csid0",
4319                                 "csid1",         4269                                 "csid1",
4320                                 "csid2",         4270                                 "csid2",
4321                                 "csiphy0",       4271                                 "csiphy0",
4322                                 "csiphy1",       4272                                 "csiphy1",
4323                                 "csiphy2",       4273                                 "csiphy2",
4324                                 "csiphy3",       4274                                 "csiphy3",
4325                                 "vfe0",          4275                                 "vfe0",
4326                                 "vfe1",          4276                                 "vfe1",
4327                                 "vfe_lite";      4277                                 "vfe_lite";
4328                                                  4278 
4329                         interrupts = <GIC_SPI    4279                         interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330                                 <GIC_SPI 466     4280                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331                                 <GIC_SPI 468     4281                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332                                 <GIC_SPI 477     4282                                 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333                                 <GIC_SPI 478     4283                                 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334                                 <GIC_SPI 479     4284                                 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335                                 <GIC_SPI 448     4285                                 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336                                 <GIC_SPI 465     4286                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337                                 <GIC_SPI 467     4287                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338                                 <GIC_SPI 469     4288                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339                         interrupt-names = "cs    4289                         interrupt-names = "csid0",
4340                                 "csid1",         4290                                 "csid1",
4341                                 "csid2",         4291                                 "csid2",
4342                                 "csiphy0",       4292                                 "csiphy0",
4343                                 "csiphy1",       4293                                 "csiphy1",
4344                                 "csiphy2",       4294                                 "csiphy2",
4345                                 "csiphy3",       4295                                 "csiphy3",
4346                                 "vfe0",          4296                                 "vfe0",
4347                                 "vfe1",          4297                                 "vfe1",
4348                                 "vfe_lite";      4298                                 "vfe_lite";
4349                                                  4299 
4350                         power-domains = <&clo    4300                         power-domains = <&clock_camcc IFE_0_GDSC>,
4351                                 <&clock_camcc    4301                                 <&clock_camcc IFE_1_GDSC>,
4352                                 <&clock_camcc    4302                                 <&clock_camcc TITAN_TOP_GDSC>;
4353                                                  4303 
4354                         clocks = <&clock_camc    4304                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355                                 <&clock_camcc    4305                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356                                 <&clock_camcc    4306                                 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357                                 <&clock_camcc    4307                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358                                 <&clock_camcc    4308                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359                                 <&clock_camcc    4309                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360                                 <&clock_camcc    4310                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361                                 <&clock_camcc    4311                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362                                 <&clock_camcc    4312                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363                                 <&clock_camcc    4313                                 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364                                 <&clock_camcc    4314                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365                                 <&clock_camcc    4315                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366                                 <&clock_camcc    4316                                 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367                                 <&clock_camcc    4317                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368                                 <&clock_camcc    4318                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369                                 <&clock_camcc    4319                                 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370                                 <&clock_camcc    4320                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371                                 <&clock_camcc    4321                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372                                 <&clock_camcc    4322                                 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373                                 <&clock_camcc    4323                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374                                 <&clock_camcc    4324                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375                                 <&gcc GCC_CAM    4325                                 <&gcc GCC_CAMERA_AHB_CLK>,
4376                                 <&gcc GCC_CAM    4326                                 <&gcc GCC_CAMERA_AXI_CLK>,
4377                                 <&clock_camcc    4327                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378                                 <&clock_camcc    4328                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379                                 <&clock_camcc    4329                                 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380                                 <&clock_camcc    4330                                 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381                                 <&clock_camcc    4331                                 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382                                 <&clock_camcc    4332                                 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383                                 <&clock_camcc    4333                                 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384                                 <&clock_camcc    4334                                 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385                                 <&clock_camcc    4335                                 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386                                 <&clock_camcc    4336                                 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387                                 <&clock_camcc    4337                                 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388                                 <&clock_camcc    4338                                 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389                                 <&clock_camcc    4339                                 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390                         clock-names = "camnoc    4340                         clock-names = "camnoc_axi",
4391                                 "cpas_ahb",      4341                                 "cpas_ahb",
4392                                 "cphy_rx_src"    4342                                 "cphy_rx_src",
4393                                 "csi0",          4343                                 "csi0",
4394                                 "csi0_src",      4344                                 "csi0_src",
4395                                 "csi1",          4345                                 "csi1",
4396                                 "csi1_src",      4346                                 "csi1_src",
4397                                 "csi2",          4347                                 "csi2",
4398                                 "csi2_src",      4348                                 "csi2_src",
4399                                 "csiphy0",       4349                                 "csiphy0",
4400                                 "csiphy0_time    4350                                 "csiphy0_timer",
4401                                 "csiphy0_time    4351                                 "csiphy0_timer_src",
4402                                 "csiphy1",       4352                                 "csiphy1",
4403                                 "csiphy1_time    4353                                 "csiphy1_timer",
4404                                 "csiphy1_time    4354                                 "csiphy1_timer_src",
4405                                 "csiphy2",       4355                                 "csiphy2",
4406                                 "csiphy2_time    4356                                 "csiphy2_timer",
4407                                 "csiphy2_time    4357                                 "csiphy2_timer_src",
4408                                 "csiphy3",       4358                                 "csiphy3",
4409                                 "csiphy3_time    4359                                 "csiphy3_timer",
4410                                 "csiphy3_time    4360                                 "csiphy3_timer_src",
4411                                 "gcc_camera_a    4361                                 "gcc_camera_ahb",
4412                                 "gcc_camera_a    4362                                 "gcc_camera_axi",
4413                                 "slow_ahb_src    4363                                 "slow_ahb_src",
4414                                 "soc_ahb",       4364                                 "soc_ahb",
4415                                 "vfe0_axi",      4365                                 "vfe0_axi",
4416                                 "vfe0",          4366                                 "vfe0",
4417                                 "vfe0_cphy_rx    4367                                 "vfe0_cphy_rx",
4418                                 "vfe0_src",      4368                                 "vfe0_src",
4419                                 "vfe1_axi",      4369                                 "vfe1_axi",
4420                                 "vfe1",          4370                                 "vfe1",
4421                                 "vfe1_cphy_rx    4371                                 "vfe1_cphy_rx",
4422                                 "vfe1_src",      4372                                 "vfe1_src",
4423                                 "vfe_lite",      4373                                 "vfe_lite",
4424                                 "vfe_lite_cph    4374                                 "vfe_lite_cphy_rx",
4425                                 "vfe_lite_src    4375                                 "vfe_lite_src";
4426                                                  4376 
4427                         iommus = <&apps_smmu     4377                         iommus = <&apps_smmu 0x0808 0x0>,
4428                                  <&apps_smmu     4378                                  <&apps_smmu 0x0810 0x8>,
4429                                  <&apps_smmu     4379                                  <&apps_smmu 0x0c08 0x0>,
4430                                  <&apps_smmu     4380                                  <&apps_smmu 0x0c10 0x8>;
4431                                                  4381 
4432                         status = "disabled";     4382                         status = "disabled";
4433                                                  4383 
4434                         ports {                  4384                         ports {
4435                                 #address-cell    4385                                 #address-cells = <1>;
4436                                 #size-cells =    4386                                 #size-cells = <0>;
4437                                                  4387 
4438                                 port@0 {         4388                                 port@0 {
4439                                         reg =    4389                                         reg = <0>;
4440                                 };               4390                                 };
4441                                                  4391 
4442                                 port@1 {         4392                                 port@1 {
4443                                         reg =    4393                                         reg = <1>;
4444                                 };               4394                                 };
4445                                                  4395 
4446                                 port@2 {         4396                                 port@2 {
4447                                         reg =    4397                                         reg = <2>;
4448                                 };               4398                                 };
4449                                                  4399 
4450                                 port@3 {         4400                                 port@3 {
4451                                         reg =    4401                                         reg = <3>;
4452                                 };               4402                                 };
4453                         };                       4403                         };
4454                 };                               4404                 };
4455                                                  4405 
4456                 cci: cci@ac4a000 {               4406                 cci: cci@ac4a000 {
4457                         compatible = "qcom,sd    4407                         compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4458                         #address-cells = <1>;    4408                         #address-cells = <1>;
4459                         #size-cells = <0>;       4409                         #size-cells = <0>;
4460                                                  4410 
4461                         reg = <0 0x0ac4a000 0    4411                         reg = <0 0x0ac4a000 0 0x4000>;
4462                         interrupts = <GIC_SPI    4412                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463                         power-domains = <&clo    4413                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464                                                  4414 
4465                         clocks = <&clock_camc    4415                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466                                 <&clock_camcc    4416                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467                                 <&clock_camcc    4417                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468                                 <&clock_camcc    4418                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469                                 <&clock_camcc    4419                                 <&clock_camcc CAM_CC_CCI_CLK>,
4470                                 <&clock_camcc    4420                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471                         clock-names = "camnoc    4421                         clock-names = "camnoc_axi",
4472                                 "soc_ahb",       4422                                 "soc_ahb",
4473                                 "slow_ahb_src    4423                                 "slow_ahb_src",
4474                                 "cpas_ahb",      4424                                 "cpas_ahb",
4475                                 "cci",           4425                                 "cci",
4476                                 "cci_src";       4426                                 "cci_src";
4477                                                  4427 
4478                         assigned-clocks = <&c    4428                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479                                 <&clock_camcc    4429                                 <&clock_camcc CAM_CC_CCI_CLK>;
4480                         assigned-clock-rates     4430                         assigned-clock-rates = <80000000>, <37500000>;
4481                                                  4431 
4482                         pinctrl-names = "defa    4432                         pinctrl-names = "default", "sleep";
4483                         pinctrl-0 = <&cci0_de    4433                         pinctrl-0 = <&cci0_default &cci1_default>;
4484                         pinctrl-1 = <&cci0_sl    4434                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485                                                  4435 
4486                         status = "disabled";     4436                         status = "disabled";
4487                                                  4437 
4488                         cci_i2c0: i2c-bus@0 {    4438                         cci_i2c0: i2c-bus@0 {
4489                                 reg = <0>;       4439                                 reg = <0>;
4490                                 clock-frequen    4440                                 clock-frequency = <1000000>;
4491                                 #address-cell    4441                                 #address-cells = <1>;
4492                                 #size-cells =    4442                                 #size-cells = <0>;
4493                         };                       4443                         };
4494                                                  4444 
4495                         cci_i2c1: i2c-bus@1 {    4445                         cci_i2c1: i2c-bus@1 {
4496                                 reg = <1>;       4446                                 reg = <1>;
4497                                 clock-frequen    4447                                 clock-frequency = <1000000>;
4498                                 #address-cell    4448                                 #address-cells = <1>;
4499                                 #size-cells =    4449                                 #size-cells = <0>;
4500                         };                       4450                         };
4501                 };                               4451                 };
4502                                                  4452 
4503                 clock_camcc: clock-controller    4453                 clock_camcc: clock-controller@ad00000 {
4504                         compatible = "qcom,sd    4454                         compatible = "qcom,sdm845-camcc";
4505                         reg = <0 0x0ad00000 0    4455                         reg = <0 0x0ad00000 0 0x10000>;
4506                         #clock-cells = <1>;      4456                         #clock-cells = <1>;
4507                         #reset-cells = <1>;      4457                         #reset-cells = <1>;
4508                         #power-domain-cells =    4458                         #power-domain-cells = <1>;
4509                         clocks = <&rpmhcc RPM    4459                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4510                         clock-names = "bi_tcx    4460                         clock-names = "bi_tcxo";
4511                 };                               4461                 };
4512                                                  4462 
4513                 mdss: display-subsystem@ae000    4463                 mdss: display-subsystem@ae00000 {
4514                         compatible = "qcom,sd    4464                         compatible = "qcom,sdm845-mdss";
4515                         reg = <0 0x0ae00000 0    4465                         reg = <0 0x0ae00000 0 0x1000>;
4516                         reg-names = "mdss";      4466                         reg-names = "mdss";
4517                                                  4467 
4518                         power-domains = <&dis    4468                         power-domains = <&dispcc MDSS_GDSC>;
4519                                                  4469 
4520                         clocks = <&dispcc DIS    4470                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521                                  <&dispcc DIS    4471                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522                         clock-names = "iface"    4472                         clock-names = "iface", "core";
4523                                                  4473 
4524                         interrupts = <GIC_SPI    4474                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525                         interrupt-controller;    4475                         interrupt-controller;
4526                         #interrupt-cells = <1    4476                         #interrupt-cells = <1>;
4527                                                  4477 
4528                         interconnects = <&mms    4478                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529                                         <&mms    4479                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530                         interconnect-names =     4480                         interconnect-names = "mdp0-mem", "mdp1-mem";
4531                                                  4481 
4532                         iommus = <&apps_smmu     4482                         iommus = <&apps_smmu 0x880 0x8>,
4533                                  <&apps_smmu     4483                                  <&apps_smmu 0xc80 0x8>;
4534                                                  4484 
4535                         status = "disabled";     4485                         status = "disabled";
4536                                                  4486 
4537                         #address-cells = <2>;    4487                         #address-cells = <2>;
4538                         #size-cells = <2>;       4488                         #size-cells = <2>;
4539                         ranges;                  4489                         ranges;
4540                                                  4490 
4541                         mdss_mdp: display-con    4491                         mdss_mdp: display-controller@ae01000 {
4542                                 compatible =     4492                                 compatible = "qcom,sdm845-dpu";
4543                                 reg = <0 0x0a    4493                                 reg = <0 0x0ae01000 0 0x8f000>,
4544                                       <0 0x0a    4494                                       <0 0x0aeb0000 0 0x2008>;
4545                                 reg-names = "    4495                                 reg-names = "mdp", "vbif";
4546                                                  4496 
4547                                 clocks = <&gc    4497                                 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548                                          <&di    4498                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549                                          <&di    4499                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550                                          <&di    4500                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551                                          <&di    4501                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552                                 clock-names =    4502                                 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553                                                  4503 
4554                                 assigned-cloc    4504                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555                                 assigned-cloc    4505                                 assigned-clock-rates = <19200000>;
4556                                 operating-poi    4506                                 operating-points-v2 = <&mdp_opp_table>;
4557                                 power-domains    4507                                 power-domains = <&rpmhpd SDM845_CX>;
4558                                                  4508 
4559                                 interrupt-par    4509                                 interrupt-parent = <&mdss>;
4560                                 interrupts =     4510                                 interrupts = <0>;
4561                                                  4511 
4562                                 ports {          4512                                 ports {
4563                                         #addr    4513                                         #address-cells = <1>;
4564                                         #size    4514                                         #size-cells = <0>;
4565                                                  4515 
4566                                         port@    4516                                         port@0 {
4567                                                  4517                                                 reg = <0>;
4568                                                  4518                                                 dpu_intf0_out: endpoint {
4569                                                  4519                                                         remote-endpoint = <&dp_in>;
4570                                                  4520                                                 };
4571                                         };       4521                                         };
4572                                                  4522 
4573                                         port@    4523                                         port@1 {
4574                                                  4524                                                 reg = <1>;
4575                                                  4525                                                 dpu_intf1_out: endpoint {
4576                                                  4526                                                         remote-endpoint = <&mdss_dsi0_in>;
4577                                                  4527                                                 };
4578                                         };       4528                                         };
4579                                                  4529 
4580                                         port@    4530                                         port@2 {
4581                                                  4531                                                 reg = <2>;
4582                                                  4532                                                 dpu_intf2_out: endpoint {
4583                                                  4533                                                         remote-endpoint = <&mdss_dsi1_in>;
4584                                                  4534                                                 };
4585                                         };       4535                                         };
4586                                 };               4536                                 };
4587                                                  4537 
4588                                 mdp_opp_table    4538                                 mdp_opp_table: opp-table {
4589                                         compa    4539                                         compatible = "operating-points-v2";
4590                                                  4540 
4591                                         opp-1    4541                                         opp-19200000 {
4592                                                  4542                                                 opp-hz = /bits/ 64 <19200000>;
4593                                                  4543                                                 required-opps = <&rpmhpd_opp_min_svs>;
4594                                         };       4544                                         };
4595                                                  4545 
4596                                         opp-1    4546                                         opp-171428571 {
4597                                                  4547                                                 opp-hz = /bits/ 64 <171428571>;
4598                                                  4548                                                 required-opps = <&rpmhpd_opp_low_svs>;
4599                                         };       4549                                         };
4600                                                  4550 
4601                                         opp-3    4551                                         opp-344000000 {
4602                                                  4552                                                 opp-hz = /bits/ 64 <344000000>;
4603                                                  4553                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4604                                         };       4554                                         };
4605                                                  4555 
4606                                         opp-4    4556                                         opp-430000000 {
4607                                                  4557                                                 opp-hz = /bits/ 64 <430000000>;
4608                                                  4558                                                 required-opps = <&rpmhpd_opp_nom>;
4609                                         };       4559                                         };
4610                                 };               4560                                 };
4611                         };                       4561                         };
4612                                                  4562 
4613                         mdss_dp: displayport-    4563                         mdss_dp: displayport-controller@ae90000 {
4614                                 status = "dis    4564                                 status = "disabled";
4615                                 compatible =     4565                                 compatible = "qcom,sdm845-dp";
4616                                                  4566 
4617                                 reg = <0 0x0a    4567                                 reg = <0 0x0ae90000 0 0x200>,
4618                                       <0 0x0a    4568                                       <0 0x0ae90200 0 0x200>,
4619                                       <0 0x0a    4569                                       <0 0x0ae90400 0 0x600>,
4620                                       <0 0x0a    4570                                       <0 0x0ae90a00 0 0x600>,
4621                                       <0 0x0a    4571                                       <0 0x0ae91000 0 0x600>;
4622                                                  4572 
4623                                 interrupt-par    4573                                 interrupt-parent = <&mdss>;
4624                                 interrupts =     4574                                 interrupts = <12>;
4625                                                  4575 
4626                                 clocks = <&di    4576                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4627                                          <&di    4577                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4628                                          <&di    4578                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4629                                          <&di    4579                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4630                                          <&di    4580                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4631                                 clock-names =    4581                                 clock-names = "core_iface", "core_aux", "ctrl_link",
4632                                                  4582                                               "ctrl_link_iface", "stream_pixel";
4633                                 assigned-cloc    4583                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4634                                                  4584                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4635                                 assigned-cloc    4585                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4636                                                  4586                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4637                                 phys = <&usb_    4587                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4638                                 phy-names = "    4588                                 phy-names = "dp";
4639                                                  4589 
4640                                 operating-poi    4590                                 operating-points-v2 = <&dp_opp_table>;
4641                                 power-domains    4591                                 power-domains = <&rpmhpd SDM845_CX>;
4642                                                  4592 
4643                                 ports {          4593                                 ports {
4644                                         #addr    4594                                         #address-cells = <1>;
4645                                         #size    4595                                         #size-cells = <0>;
4646                                         port@    4596                                         port@0 {
4647                                                  4597                                                 reg = <0>;
4648                                                  4598                                                 dp_in: endpoint {
4649                                                  4599                                                         remote-endpoint = <&dpu_intf0_out>;
4650                                                  4600                                                 };
4651                                         };       4601                                         };
4652                                                  4602 
4653                                         port@    4603                                         port@1 {
4654                                                  4604                                                 reg = <1>;
4655                                               !! 4605                                                 dp_out: endpoint { };
4656                                               << 
4657                                               << 
4658                                         };       4606                                         };
4659                                 };               4607                                 };
4660                                                  4608 
4661                                 dp_opp_table:    4609                                 dp_opp_table: opp-table {
4662                                         compa    4610                                         compatible = "operating-points-v2";
4663                                                  4611 
4664                                         opp-1    4612                                         opp-162000000 {
4665                                                  4613                                                 opp-hz = /bits/ 64 <162000000>;
4666                                                  4614                                                 required-opps = <&rpmhpd_opp_low_svs>;
4667                                         };       4615                                         };
4668                                                  4616 
4669                                         opp-2    4617                                         opp-270000000 {
4670                                                  4618                                                 opp-hz = /bits/ 64 <270000000>;
4671                                                  4619                                                 required-opps = <&rpmhpd_opp_svs>;
4672                                         };       4620                                         };
4673                                                  4621 
4674                                         opp-5    4622                                         opp-540000000 {
4675                                                  4623                                                 opp-hz = /bits/ 64 <540000000>;
4676                                                  4624                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4677                                         };       4625                                         };
4678                                                  4626 
4679                                         opp-8    4627                                         opp-810000000 {
4680                                                  4628                                                 opp-hz = /bits/ 64 <810000000>;
4681                                                  4629                                                 required-opps = <&rpmhpd_opp_nom>;
4682                                         };       4630                                         };
4683                                 };               4631                                 };
4684                         };                       4632                         };
4685                                                  4633 
4686                         mdss_dsi0: dsi@ae9400    4634                         mdss_dsi0: dsi@ae94000 {
4687                                 compatible =     4635                                 compatible = "qcom,sdm845-dsi-ctrl",
4688                                                  4636                                              "qcom,mdss-dsi-ctrl";
4689                                 reg = <0 0x0a    4637                                 reg = <0 0x0ae94000 0 0x400>;
4690                                 reg-names = "    4638                                 reg-names = "dsi_ctrl";
4691                                                  4639 
4692                                 interrupt-par    4640                                 interrupt-parent = <&mdss>;
4693                                 interrupts =     4641                                 interrupts = <4>;
4694                                                  4642 
4695                                 clocks = <&di    4643                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696                                          <&di    4644                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697                                          <&di    4645                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698                                          <&di    4646                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699                                          <&di    4647                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700                                          <&di    4648                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701                                 clock-names =    4649                                 clock-names = "byte",
4702                                                  4650                                               "byte_intf",
4703                                                  4651                                               "pixel",
4704                                                  4652                                               "core",
4705                                                  4653                                               "iface",
4706                                                  4654                                               "bus";
4707                                 assigned-cloc    4655                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708                                 assigned-cloc    4656                                 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4709                                                  4657 
4710                                 operating-poi    4658                                 operating-points-v2 = <&dsi_opp_table>;
4711                                 power-domains    4659                                 power-domains = <&rpmhpd SDM845_CX>;
4712                                                  4660 
4713                                 phys = <&mdss    4661                                 phys = <&mdss_dsi0_phy>;
4714                                                  4662 
4715                                 status = "dis    4663                                 status = "disabled";
4716                                                  4664 
4717                                 #address-cell    4665                                 #address-cells = <1>;
4718                                 #size-cells =    4666                                 #size-cells = <0>;
4719                                                  4667 
4720                                 ports {          4668                                 ports {
4721                                         #addr    4669                                         #address-cells = <1>;
4722                                         #size    4670                                         #size-cells = <0>;
4723                                                  4671 
4724                                         port@    4672                                         port@0 {
4725                                                  4673                                                 reg = <0>;
4726                                                  4674                                                 mdss_dsi0_in: endpoint {
4727                                                  4675                                                         remote-endpoint = <&dpu_intf1_out>;
4728                                                  4676                                                 };
4729                                         };       4677                                         };
4730                                                  4678 
4731                                         port@    4679                                         port@1 {
4732                                                  4680                                                 reg = <1>;
4733                                                  4681                                                 mdss_dsi0_out: endpoint {
4734                                                  4682                                                 };
4735                                         };       4683                                         };
4736                                 };               4684                                 };
4737                         };                       4685                         };
4738                                                  4686 
4739                         mdss_dsi0_phy: phy@ae    4687                         mdss_dsi0_phy: phy@ae94400 {
4740                                 compatible =     4688                                 compatible = "qcom,dsi-phy-10nm";
4741                                 reg = <0 0x0a    4689                                 reg = <0 0x0ae94400 0 0x200>,
4742                                       <0 0x0a    4690                                       <0 0x0ae94600 0 0x280>,
4743                                       <0 0x0a    4691                                       <0 0x0ae94a00 0 0x1e0>;
4744                                 reg-names = "    4692                                 reg-names = "dsi_phy",
4745                                             "    4693                                             "dsi_phy_lane",
4746                                             "    4694                                             "dsi_pll";
4747                                                  4695 
4748                                 #clock-cells     4696                                 #clock-cells = <1>;
4749                                 #phy-cells =     4697                                 #phy-cells = <0>;
4750                                                  4698 
4751                                 clocks = <&di    4699                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752                                          <&rp    4700                                          <&rpmhcc RPMH_CXO_CLK>;
4753                                 clock-names =    4701                                 clock-names = "iface", "ref";
4754                                                  4702 
4755                                 status = "dis    4703                                 status = "disabled";
4756                         };                       4704                         };
4757                                                  4705 
4758                         mdss_dsi1: dsi@ae9600    4706                         mdss_dsi1: dsi@ae96000 {
4759                                 compatible =     4707                                 compatible = "qcom,sdm845-dsi-ctrl",
4760                                                  4708                                              "qcom,mdss-dsi-ctrl";
4761                                 reg = <0 0x0a    4709                                 reg = <0 0x0ae96000 0 0x400>;
4762                                 reg-names = "    4710                                 reg-names = "dsi_ctrl";
4763                                                  4711 
4764                                 interrupt-par    4712                                 interrupt-parent = <&mdss>;
4765                                 interrupts =     4713                                 interrupts = <5>;
4766                                                  4714 
4767                                 clocks = <&di    4715                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768                                          <&di    4716                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769                                          <&di    4717                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770                                          <&di    4718                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771                                          <&di    4719                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772                                          <&di    4720                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773                                 clock-names =    4721                                 clock-names = "byte",
4774                                                  4722                                               "byte_intf",
4775                                                  4723                                               "pixel",
4776                                                  4724                                               "core",
4777                                                  4725                                               "iface",
4778                                                  4726                                               "bus";
4779                                 assigned-cloc    4727                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780                                 assigned-cloc    4728                                 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4781                                                  4729 
4782                                 operating-poi    4730                                 operating-points-v2 = <&dsi_opp_table>;
4783                                 power-domains    4731                                 power-domains = <&rpmhpd SDM845_CX>;
4784                                                  4732 
4785                                 phys = <&mdss    4733                                 phys = <&mdss_dsi1_phy>;
4786                                                  4734 
4787                                 status = "dis    4735                                 status = "disabled";
4788                                                  4736 
4789                                 #address-cell    4737                                 #address-cells = <1>;
4790                                 #size-cells =    4738                                 #size-cells = <0>;
4791                                                  4739 
4792                                 ports {          4740                                 ports {
4793                                         #addr    4741                                         #address-cells = <1>;
4794                                         #size    4742                                         #size-cells = <0>;
4795                                                  4743 
4796                                         port@    4744                                         port@0 {
4797                                                  4745                                                 reg = <0>;
4798                                                  4746                                                 mdss_dsi1_in: endpoint {
4799                                                  4747                                                         remote-endpoint = <&dpu_intf2_out>;
4800                                                  4748                                                 };
4801                                         };       4749                                         };
4802                                                  4750 
4803                                         port@    4751                                         port@1 {
4804                                                  4752                                                 reg = <1>;
4805                                                  4753                                                 mdss_dsi1_out: endpoint {
4806                                                  4754                                                 };
4807                                         };       4755                                         };
4808                                 };               4756                                 };
4809                         };                       4757                         };
4810                                                  4758 
4811                         mdss_dsi1_phy: phy@ae    4759                         mdss_dsi1_phy: phy@ae96400 {
4812                                 compatible =     4760                                 compatible = "qcom,dsi-phy-10nm";
4813                                 reg = <0 0x0a    4761                                 reg = <0 0x0ae96400 0 0x200>,
4814                                       <0 0x0a    4762                                       <0 0x0ae96600 0 0x280>,
4815                                       <0 0x0a    4763                                       <0 0x0ae96a00 0 0x10e>;
4816                                 reg-names = "    4764                                 reg-names = "dsi_phy",
4817                                             "    4765                                             "dsi_phy_lane",
4818                                             "    4766                                             "dsi_pll";
4819                                                  4767 
4820                                 #clock-cells     4768                                 #clock-cells = <1>;
4821                                 #phy-cells =     4769                                 #phy-cells = <0>;
4822                                                  4770 
4823                                 clocks = <&di    4771                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824                                          <&rp    4772                                          <&rpmhcc RPMH_CXO_CLK>;
4825                                 clock-names =    4773                                 clock-names = "iface", "ref";
4826                                                  4774 
4827                                 status = "dis    4775                                 status = "disabled";
4828                         };                       4776                         };
4829                 };                               4777                 };
4830                                                  4778 
4831                 gpu: gpu@5000000 {               4779                 gpu: gpu@5000000 {
4832                         compatible = "qcom,ad    4780                         compatible = "qcom,adreno-630.2", "qcom,adreno";
4833                                                  4781 
4834                         reg = <0 0x05000000 0    4782                         reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835                         reg-names = "kgsl_3d0    4783                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836                                                  4784 
4837                         /*                       4785                         /*
4838                          * Look ma, no clocks    4786                          * Look ma, no clocks! The GPU clocks and power are
4839                          * controlled entirel    4787                          * controlled entirely by the GMU
4840                          */                      4788                          */
4841                                                  4789 
4842                         interrupts = <GIC_SPI    4790                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843                                                  4791 
4844                         iommus = <&adreno_smm    4792                         iommus = <&adreno_smmu 0>;
4845                                                  4793 
4846                         operating-points-v2 =    4794                         operating-points-v2 = <&gpu_opp_table>;
4847                                                  4795 
4848                         qcom,gmu = <&gmu>;       4796                         qcom,gmu = <&gmu>;
4849                         #cooling-cells = <2>;    4797                         #cooling-cells = <2>;
4850                                                  4798 
4851                         interconnects = <&mem    4799                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852                         interconnect-names =     4800                         interconnect-names = "gfx-mem";
4853                                                  4801 
4854                         status = "disabled";     4802                         status = "disabled";
4855                                                  4803 
4856                         gpu_opp_table: opp-ta    4804                         gpu_opp_table: opp-table {
4857                                 compatible =     4805                                 compatible = "operating-points-v2";
4858                                                  4806 
4859                                 opp-710000000    4807                                 opp-710000000 {
4860                                         opp-h    4808                                         opp-hz = /bits/ 64 <710000000>;
4861                                         opp-l    4809                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862                                         opp-p    4810                                         opp-peak-kBps = <7216000>;
4863                                 };               4811                                 };
4864                                                  4812 
4865                                 opp-675000000    4813                                 opp-675000000 {
4866                                         opp-h    4814                                         opp-hz = /bits/ 64 <675000000>;
4867                                         opp-l    4815                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868                                         opp-p    4816                                         opp-peak-kBps = <7216000>;
4869                                 };               4817                                 };
4870                                                  4818 
4871                                 opp-596000000    4819                                 opp-596000000 {
4872                                         opp-h    4820                                         opp-hz = /bits/ 64 <596000000>;
4873                                         opp-l    4821                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874                                         opp-p    4822                                         opp-peak-kBps = <6220000>;
4875                                 };               4823                                 };
4876                                                  4824 
4877                                 opp-520000000    4825                                 opp-520000000 {
4878                                         opp-h    4826                                         opp-hz = /bits/ 64 <520000000>;
4879                                         opp-l    4827                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880                                         opp-p    4828                                         opp-peak-kBps = <6220000>;
4881                                 };               4829                                 };
4882                                                  4830 
4883                                 opp-414000000    4831                                 opp-414000000 {
4884                                         opp-h    4832                                         opp-hz = /bits/ 64 <414000000>;
4885                                         opp-l    4833                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886                                         opp-p    4834                                         opp-peak-kBps = <4068000>;
4887                                 };               4835                                 };
4888                                                  4836 
4889                                 opp-342000000    4837                                 opp-342000000 {
4890                                         opp-h    4838                                         opp-hz = /bits/ 64 <342000000>;
4891                                         opp-l    4839                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892                                         opp-p    4840                                         opp-peak-kBps = <2724000>;
4893                                 };               4841                                 };
4894                                                  4842 
4895                                 opp-257000000    4843                                 opp-257000000 {
4896                                         opp-h    4844                                         opp-hz = /bits/ 64 <257000000>;
4897                                         opp-l    4845                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898                                         opp-p    4846                                         opp-peak-kBps = <1648000>;
4899                                 };               4847                                 };
4900                         };                       4848                         };
4901                 };                               4849                 };
4902                                                  4850 
4903                 adreno_smmu: iommu@5040000 {     4851                 adreno_smmu: iommu@5040000 {
4904                         compatible = "qcom,sd    4852                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905                         reg = <0 0x05040000 0    4853                         reg = <0 0x05040000 0 0x10000>;
4906                         #iommu-cells = <1>;      4854                         #iommu-cells = <1>;
4907                         #global-interrupts =     4855                         #global-interrupts = <2>;
4908                         interrupts = <GIC_SPI    4856                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909                                      <GIC_SPI    4857                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910                                      <GIC_SPI    4858                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911                                      <GIC_SPI    4859                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912                                      <GIC_SPI    4860                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913                                      <GIC_SPI    4861                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914                                      <GIC_SPI    4862                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915                                      <GIC_SPI    4863                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916                                      <GIC_SPI    4864                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917                                      <GIC_SPI    4865                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918                         clocks = <&gcc GCC_GP    4866                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919                                  <&gcc GCC_GP    4867                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
4920                         clock-names = "bus",     4868                         clock-names = "bus", "iface";
4921                                                  4869 
4922                         power-domains = <&gpu    4870                         power-domains = <&gpucc GPU_CX_GDSC>;
4923                 };                               4871                 };
4924                                                  4872 
4925                 gmu: gmu@506a000 {               4873                 gmu: gmu@506a000 {
4926                         compatible = "qcom,ad    4874                         compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927                                                  4875 
4928                         reg = <0 0x0506a000 0    4876                         reg = <0 0x0506a000 0 0x30000>,
4929                               <0 0x0b280000 0    4877                               <0 0x0b280000 0 0x10000>,
4930                               <0 0x0b480000 0    4878                               <0 0x0b480000 0 0x10000>;
4931                         reg-names = "gmu", "g    4879                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932                                                  4880 
4933                         interrupts = <GIC_SPI    4881                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934                                      <GIC_SPI    4882                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935                         interrupt-names = "hf    4883                         interrupt-names = "hfi", "gmu";
4936                                                  4884 
4937                         clocks = <&gpucc GPU_    4885                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938                                  <&gpucc GPU_    4886                                  <&gpucc GPU_CC_CXO_CLK>,
4939                                  <&gcc GCC_DD    4887                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940                                  <&gcc GCC_GP    4888                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941                         clock-names = "gmu",     4889                         clock-names = "gmu", "cxo", "axi", "memnoc";
4942                                                  4890 
4943                         power-domains = <&gpu    4891                         power-domains = <&gpucc GPU_CX_GDSC>,
4944                                         <&gpu    4892                                         <&gpucc GPU_GX_GDSC>;
4945                         power-domain-names =     4893                         power-domain-names = "cx", "gx";
4946                                                  4894 
4947                         iommus = <&adreno_smm    4895                         iommus = <&adreno_smmu 5>;
4948                                                  4896 
4949                         operating-points-v2 =    4897                         operating-points-v2 = <&gmu_opp_table>;
4950                                                  4898 
4951                         status = "disabled";     4899                         status = "disabled";
4952                                                  4900 
4953                         gmu_opp_table: opp-ta    4901                         gmu_opp_table: opp-table {
4954                                 compatible =     4902                                 compatible = "operating-points-v2";
4955                                                  4903 
4956                                 opp-400000000    4904                                 opp-400000000 {
4957                                         opp-h    4905                                         opp-hz = /bits/ 64 <400000000>;
4958                                         opp-l    4906                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959                                 };               4907                                 };
4960                                                  4908 
4961                                 opp-200000000    4909                                 opp-200000000 {
4962                                         opp-h    4910                                         opp-hz = /bits/ 64 <200000000>;
4963                                         opp-l    4911                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964                                 };               4912                                 };
4965                         };                       4913                         };
4966                 };                               4914                 };
4967                                                  4915 
4968                 dispcc: clock-controller@af00    4916                 dispcc: clock-controller@af00000 {
4969                         compatible = "qcom,sd    4917                         compatible = "qcom,sdm845-dispcc";
4970                         reg = <0 0x0af00000 0    4918                         reg = <0 0x0af00000 0 0x10000>;
4971                         clocks = <&rpmhcc RPM    4919                         clocks = <&rpmhcc RPMH_CXO_CLK>,
4972                                  <&gcc GCC_DI    4920                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973                                  <&gcc GCC_DI    4921                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974                                  <&mdss_dsi0_    4922                                  <&mdss_dsi0_phy 0>,
4975                                  <&mdss_dsi0_    4923                                  <&mdss_dsi0_phy 1>,
4976                                  <&mdss_dsi1_    4924                                  <&mdss_dsi1_phy 0>,
4977                                  <&mdss_dsi1_    4925                                  <&mdss_dsi1_phy 1>,
4978                                  <&usb_1_qmpp    4926                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4979                                  <&usb_1_qmpp    4927                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4980                         clock-names = "bi_tcx    4928                         clock-names = "bi_tcxo",
4981                                       "gcc_di    4929                                       "gcc_disp_gpll0_clk_src",
4982                                       "gcc_di    4930                                       "gcc_disp_gpll0_div_clk_src",
4983                                       "dsi0_p    4931                                       "dsi0_phy_pll_out_byteclk",
4984                                       "dsi0_p    4932                                       "dsi0_phy_pll_out_dsiclk",
4985                                       "dsi1_p    4933                                       "dsi1_phy_pll_out_byteclk",
4986                                       "dsi1_p    4934                                       "dsi1_phy_pll_out_dsiclk",
4987                                       "dp_lin    4935                                       "dp_link_clk_divsel_ten",
4988                                       "dp_vco    4936                                       "dp_vco_divided_clk_src_mux";
4989                         #clock-cells = <1>;      4937                         #clock-cells = <1>;
4990                         #reset-cells = <1>;      4938                         #reset-cells = <1>;
4991                         #power-domain-cells =    4939                         #power-domain-cells = <1>;
4992                 };                               4940                 };
4993                                                  4941 
4994                 pdc_intc: interrupt-controlle    4942                 pdc_intc: interrupt-controller@b220000 {
4995                         compatible = "qcom,sd    4943                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996                         reg = <0 0x0b220000 0    4944                         reg = <0 0x0b220000 0 0x30000>;
4997                         qcom,pdc-ranges = <0     4945                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998                         #interrupt-cells = <2    4946                         #interrupt-cells = <2>;
4999                         interrupt-parent = <&    4947                         interrupt-parent = <&intc>;
5000                         interrupt-controller;    4948                         interrupt-controller;
5001                 };                               4949                 };
5002                                                  4950 
5003                 pdc_reset: reset-controller@b    4951                 pdc_reset: reset-controller@b2e0000 {
5004                         compatible = "qcom,sd    4952                         compatible = "qcom,sdm845-pdc-global";
5005                         reg = <0 0x0b2e0000 0    4953                         reg = <0 0x0b2e0000 0 0x20000>;
5006                         #reset-cells = <1>;      4954                         #reset-cells = <1>;
5007                 };                               4955                 };
5008                                                  4956 
5009                 tsens0: thermal-sensor@c26300    4957                 tsens0: thermal-sensor@c263000 {
5010                         compatible = "qcom,sd    4958                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011                         reg = <0 0x0c263000 0    4959                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012                               <0 0x0c222000 0    4960                               <0 0x0c222000 0 0x1ff>; /* SROT */
5013                         #qcom,sensors = <13>;    4961                         #qcom,sensors = <13>;
5014                         interrupts = <GIC_SPI    4962                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015                                      <GIC_SPI    4963                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016                         interrupt-names = "up    4964                         interrupt-names = "uplow", "critical";
5017                         #thermal-sensor-cells    4965                         #thermal-sensor-cells = <1>;
5018                 };                               4966                 };
5019                                                  4967 
5020                 tsens1: thermal-sensor@c26500    4968                 tsens1: thermal-sensor@c265000 {
5021                         compatible = "qcom,sd    4969                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022                         reg = <0 0x0c265000 0    4970                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023                               <0 0x0c223000 0    4971                               <0 0x0c223000 0 0x1ff>; /* SROT */
5024                         #qcom,sensors = <8>;     4972                         #qcom,sensors = <8>;
5025                         interrupts = <GIC_SPI    4973                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026                                      <GIC_SPI    4974                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027                         interrupt-names = "up    4975                         interrupt-names = "uplow", "critical";
5028                         #thermal-sensor-cells    4976                         #thermal-sensor-cells = <1>;
5029                 };                               4977                 };
5030                                                  4978 
5031                 aoss_reset: reset-controller@    4979                 aoss_reset: reset-controller@c2a0000 {
5032                         compatible = "qcom,sd    4980                         compatible = "qcom,sdm845-aoss-cc";
5033                         reg = <0 0x0c2a0000 0    4981                         reg = <0 0x0c2a0000 0 0x31000>;
5034                         #reset-cells = <1>;      4982                         #reset-cells = <1>;
5035                 };                               4983                 };
5036                                                  4984 
5037                 aoss_qmp: power-management@c3    4985                 aoss_qmp: power-management@c300000 {
5038                         compatible = "qcom,sd    4986                         compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039                         reg = <0 0x0c300000 0    4987                         reg = <0 0x0c300000 0 0x400>;
5040                         interrupts = <GIC_SPI    4988                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041                         mboxes = <&apss_share    4989                         mboxes = <&apss_shared 0>;
5042                                                  4990 
5043                         #clock-cells = <0>;      4991                         #clock-cells = <0>;
5044                                                  4992 
5045                         cx_cdev: cx {            4993                         cx_cdev: cx {
5046                                 #cooling-cell    4994                                 #cooling-cells = <2>;
5047                         };                       4995                         };
5048                                                  4996 
5049                         ebi_cdev: ebi {          4997                         ebi_cdev: ebi {
5050                                 #cooling-cell    4998                                 #cooling-cells = <2>;
5051                         };                       4999                         };
5052                 };                               5000                 };
5053                                                  5001 
5054                 sram@c3f0000 {                   5002                 sram@c3f0000 {
5055                         compatible = "qcom,sd    5003                         compatible = "qcom,sdm845-rpmh-stats";
5056                         reg = <0 0x0c3f0000 0    5004                         reg = <0 0x0c3f0000 0 0x400>;
5057                 };                               5005                 };
5058                                                  5006 
5059                 spmi_bus: spmi@c440000 {         5007                 spmi_bus: spmi@c440000 {
5060                         compatible = "qcom,sp    5008                         compatible = "qcom,spmi-pmic-arb";
5061                         reg = <0 0x0c440000 0    5009                         reg = <0 0x0c440000 0 0x1100>,
5062                               <0 0x0c600000 0    5010                               <0 0x0c600000 0 0x2000000>,
5063                               <0 0x0e600000 0    5011                               <0 0x0e600000 0 0x100000>,
5064                               <0 0x0e700000 0    5012                               <0 0x0e700000 0 0xa0000>,
5065                               <0 0x0c40a000 0    5013                               <0 0x0c40a000 0 0x26000>;
5066                         reg-names = "core", "    5014                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067                         interrupt-names = "pe    5015                         interrupt-names = "periph_irq";
5068                         interrupts = <GIC_SPI    5016                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069                         qcom,ee = <0>;           5017                         qcom,ee = <0>;
5070                         qcom,channel = <0>;      5018                         qcom,channel = <0>;
5071                         #address-cells = <2>;    5019                         #address-cells = <2>;
5072                         #size-cells = <0>;       5020                         #size-cells = <0>;
5073                         interrupt-controller;    5021                         interrupt-controller;
5074                         #interrupt-cells = <4    5022                         #interrupt-cells = <4>;
5075                 };                               5023                 };
5076                                                  5024 
5077                 sram@146bf000 {                  5025                 sram@146bf000 {
5078                         compatible = "qcom,sd    5026                         compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5079                         reg = <0 0x146bf000 0    5027                         reg = <0 0x146bf000 0 0x1000>;
5080                                                  5028 
5081                         #address-cells = <1>;    5029                         #address-cells = <1>;
5082                         #size-cells = <1>;       5030                         #size-cells = <1>;
5083                                                  5031 
5084                         ranges = <0 0 0x146bf    5032                         ranges = <0 0 0x146bf000 0x1000>;
5085                                                  5033 
5086                         pil-reloc@94c {          5034                         pil-reloc@94c {
5087                                 compatible =     5035                                 compatible = "qcom,pil-reloc-info";
5088                                 reg = <0x94c     5036                                 reg = <0x94c 0xc8>;
5089                         };                       5037                         };
5090                 };                               5038                 };
5091                                                  5039 
5092                 apps_smmu: iommu@15000000 {      5040                 apps_smmu: iommu@15000000 {
5093                         compatible = "qcom,sd    5041                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094                         reg = <0 0x15000000 0    5042                         reg = <0 0x15000000 0 0x80000>;
5095                         #iommu-cells = <2>;      5043                         #iommu-cells = <2>;
5096                         #global-interrupts =     5044                         #global-interrupts = <1>;
5097                         interrupts = <GIC_SPI    5045                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098                                      <GIC_SPI    5046                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099                                      <GIC_SPI    5047                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100                                      <GIC_SPI    5048                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101                                      <GIC_SPI    5049                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102                                      <GIC_SPI    5050                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103                                      <GIC_SPI    5051                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104                                      <GIC_SPI    5052                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105                                      <GIC_SPI    5053                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106                                      <GIC_SPI    5054                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107                                      <GIC_SPI    5055                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108                                      <GIC_SPI    5056                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109                                      <GIC_SPI    5057                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110                                      <GIC_SPI    5058                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111                                      <GIC_SPI    5059                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112                                      <GIC_SPI    5060                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113                                      <GIC_SPI    5061                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114                                      <GIC_SPI    5062                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115                                      <GIC_SPI    5063                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116                                      <GIC_SPI    5064                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117                                      <GIC_SPI    5065                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118                                      <GIC_SPI    5066                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119                                      <GIC_SPI    5067                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120                                      <GIC_SPI    5068                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121                                      <GIC_SPI    5069                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122                                      <GIC_SPI    5070                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123                                      <GIC_SPI    5071                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124                                      <GIC_SPI    5072                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125                                      <GIC_SPI    5073                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126                                      <GIC_SPI    5074                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127                                      <GIC_SPI    5075                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128                                      <GIC_SPI    5076                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129                                      <GIC_SPI    5077                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130                                      <GIC_SPI    5078                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131                                      <GIC_SPI    5079                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132                                      <GIC_SPI    5080                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133                                      <GIC_SPI    5081                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134                                      <GIC_SPI    5082                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135                                      <GIC_SPI    5083                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136                                      <GIC_SPI    5084                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137                                      <GIC_SPI    5085                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138                                      <GIC_SPI    5086                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139                                      <GIC_SPI    5087                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140                                      <GIC_SPI    5088                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141                                      <GIC_SPI    5089                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142                                      <GIC_SPI    5090                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143                                      <GIC_SPI    5091                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144                                      <GIC_SPI    5092                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145                                      <GIC_SPI    5093                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146                                      <GIC_SPI    5094                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147                                      <GIC_SPI    5095                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148                                      <GIC_SPI    5096                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149                                      <GIC_SPI    5097                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150                                      <GIC_SPI    5098                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151                                      <GIC_SPI    5099                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152                                      <GIC_SPI    5100                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153                                      <GIC_SPI    5101                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154                                      <GIC_SPI    5102                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155                                      <GIC_SPI    5103                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156                                      <GIC_SPI    5104                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157                                      <GIC_SPI    5105                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158                                      <GIC_SPI    5106                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159                                      <GIC_SPI    5107                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160                                      <GIC_SPI    5108                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161                                      <GIC_SPI    5109                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162                 };                               5110                 };
5163                                                  5111 
5164                 anoc_1_tbu: tbu@150c5000 {    << 
5165                         compatible = "qcom,sd << 
5166                         reg = <0x0 0x150c5000 << 
5167                         interconnects = <&sys << 
5168                                          &con << 
5169                         power-domains = <&gcc << 
5170                         qcom,stream-id-range  << 
5171                 };                            << 
5172                                               << 
5173                 anoc_2_tbu: tbu@150c9000 {    << 
5174                         compatible = "qcom,sd << 
5175                         reg = <0x0 0x150c9000 << 
5176                         interconnects = <&sys << 
5177                                          &con << 
5178                         power-domains = <&gcc << 
5179                         qcom,stream-id-range  << 
5180                 };                            << 
5181                                               << 
5182                 mnoc_hf_0_tbu: tbu@150cd000 { << 
5183                         compatible = "qcom,sd << 
5184                         reg = <0x0 0x150cd000 << 
5185                         interconnects = <&mms << 
5186                                          &mms << 
5187                         power-domains = <&gcc << 
5188                         qcom,stream-id-range  << 
5189                 };                            << 
5190                                               << 
5191                 mnoc_hf_1_tbu: tbu@150d1000 { << 
5192                         compatible = "qcom,sd << 
5193                         reg = <0x0 0x150d1000 << 
5194                         interconnects = <&mms << 
5195                                          &mms << 
5196                         power-domains = <&gcc << 
5197                         qcom,stream-id-range  << 
5198                 };                            << 
5199                                               << 
5200                 mnoc_sf_0_tbu: tbu@150d5000 { << 
5201                         compatible = "qcom,sd << 
5202                         reg = <0x0 0x150d5000 << 
5203                         interconnects = <&mms << 
5204                                          &mms << 
5205                         power-domains = <&gcc << 
5206                         qcom,stream-id-range  << 
5207                 };                            << 
5208                                               << 
5209                 compute_dsp_tbu: tbu@150d9000 << 
5210                         compatible = "qcom,sd << 
5211                         reg = <0x0 0x150d9000 << 
5212                         interconnects = <&sys << 
5213                                          &con << 
5214                         qcom,stream-id-range  << 
5215                 };                            << 
5216                                               << 
5217                 adsp_tbu: tbu@150dd000 {      << 
5218                         compatible = "qcom,sd << 
5219                         reg = <0x0 0x150dd000 << 
5220                         interconnects = <&sys << 
5221                                          &con << 
5222                         power-domains = <&gcc << 
5223                         qcom,stream-id-range  << 
5224                 };                            << 
5225                                               << 
5226                 anoc_1_pcie_tbu: tbu@150e1000 << 
5227                         compatible = "qcom,sd << 
5228                         reg = <0x0 0x150e1000 << 
5229                         clocks = <&gcc GCC_AG << 
5230                         interconnects = <&sys << 
5231                                          &con << 
5232                         power-domains = <&gcc << 
5233                         qcom,stream-id-range  << 
5234                 };                            << 
5235                                               << 
5236                 lpasscc: clock-controller@170    5112                 lpasscc: clock-controller@17014000 {
5237                         compatible = "qcom,sd    5113                         compatible = "qcom,sdm845-lpasscc";
5238                         reg = <0 0x17014000 0    5114                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239                         reg-names = "cc", "qd    5115                         reg-names = "cc", "qdsp6ss";
5240                         #clock-cells = <1>;      5116                         #clock-cells = <1>;
5241                         status = "disabled";     5117                         status = "disabled";
5242                 };                               5118                 };
5243                                                  5119 
5244                 gladiator_noc: interconnect@1    5120                 gladiator_noc: interconnect@17900000 {
5245                         compatible = "qcom,sd    5121                         compatible = "qcom,sdm845-gladiator-noc";
5246                         reg = <0 0x17900000 0    5122                         reg = <0 0x17900000 0 0xd080>;
5247                         #interconnect-cells =    5123                         #interconnect-cells = <2>;
5248                         qcom,bcm-voters = <&a    5124                         qcom,bcm-voters = <&apps_bcm_voter>;
5249                 };                               5125                 };
5250                                                  5126 
5251                 watchdog@17980000 {              5127                 watchdog@17980000 {
5252                         compatible = "qcom,ap    5128                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253                         reg = <0 0x17980000 0    5129                         reg = <0 0x17980000 0 0x1000>;
5254                         clocks = <&sleep_clk>    5130                         clocks = <&sleep_clk>;
5255                         interrupts = <GIC_SPI    5131                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5256                 };                               5132                 };
5257                                                  5133 
5258                 apss_shared: mailbox@17990000    5134                 apss_shared: mailbox@17990000 {
5259                         compatible = "qcom,sd    5135                         compatible = "qcom,sdm845-apss-shared";
5260                         reg = <0 0x17990000 0    5136                         reg = <0 0x17990000 0 0x1000>;
5261                         #mbox-cells = <1>;       5137                         #mbox-cells = <1>;
5262                 };                               5138                 };
5263                                                  5139 
5264                 apps_rsc: rsc@179c0000 {         5140                 apps_rsc: rsc@179c0000 {
5265                         label = "apps_rsc";      5141                         label = "apps_rsc";
5266                         compatible = "qcom,rp    5142                         compatible = "qcom,rpmh-rsc";
5267                         reg = <0 0x179c0000 0    5143                         reg = <0 0x179c0000 0 0x10000>,
5268                               <0 0x179d0000 0    5144                               <0 0x179d0000 0 0x10000>,
5269                               <0 0x179e0000 0    5145                               <0 0x179e0000 0 0x10000>;
5270                         reg-names = "drv-0",     5146                         reg-names = "drv-0", "drv-1", "drv-2";
5271                         interrupts = <GIC_SPI    5147                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272                                      <GIC_SPI    5148                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273                                      <GIC_SPI    5149                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274                         qcom,tcs-offset = <0x    5150                         qcom,tcs-offset = <0xd00>;
5275                         qcom,drv-id = <2>;       5151                         qcom,drv-id = <2>;
5276                         qcom,tcs-config = <AC    5152                         qcom,tcs-config = <ACTIVE_TCS  2>,
5277                                           <SL    5153                                           <SLEEP_TCS   3>,
5278                                           <WA    5154                                           <WAKE_TCS    3>,
5279                                           <CO    5155                                           <CONTROL_TCS 1>;
5280                         power-domains = <&CLU    5156                         power-domains = <&CLUSTER_PD>;
5281                                                  5157 
5282                         apps_bcm_voter: bcm-v    5158                         apps_bcm_voter: bcm-voter {
5283                                 compatible =     5159                                 compatible = "qcom,bcm-voter";
5284                         };                       5160                         };
5285                                                  5161 
5286                         rpmhcc: clock-control    5162                         rpmhcc: clock-controller {
5287                                 compatible =     5163                                 compatible = "qcom,sdm845-rpmh-clk";
5288                                 #clock-cells     5164                                 #clock-cells = <1>;
5289                                 clock-names =    5165                                 clock-names = "xo";
5290                                 clocks = <&xo    5166                                 clocks = <&xo_board>;
5291                         };                       5167                         };
5292                                                  5168 
5293                         rpmhpd: power-control    5169                         rpmhpd: power-controller {
5294                                 compatible =     5170                                 compatible = "qcom,sdm845-rpmhpd";
5295                                 #power-domain    5171                                 #power-domain-cells = <1>;
5296                                 operating-poi    5172                                 operating-points-v2 = <&rpmhpd_opp_table>;
5297                                                  5173 
5298                                 rpmhpd_opp_ta    5174                                 rpmhpd_opp_table: opp-table {
5299                                         compa    5175                                         compatible = "operating-points-v2";
5300                                                  5176 
5301                                         rpmhp    5177                                         rpmhpd_opp_ret: opp1 {
5302                                                  5178                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303                                         };       5179                                         };
5304                                                  5180 
5305                                         rpmhp    5181                                         rpmhpd_opp_min_svs: opp2 {
5306                                                  5182                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307                                         };       5183                                         };
5308                                                  5184 
5309                                         rpmhp    5185                                         rpmhpd_opp_low_svs: opp3 {
5310                                                  5186                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311                                         };       5187                                         };
5312                                                  5188 
5313                                         rpmhp    5189                                         rpmhpd_opp_svs: opp4 {
5314                                                  5190                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315                                         };       5191                                         };
5316                                                  5192 
5317                                         rpmhp    5193                                         rpmhpd_opp_svs_l1: opp5 {
5318                                                  5194                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319                                         };       5195                                         };
5320                                                  5196 
5321                                         rpmhp    5197                                         rpmhpd_opp_nom: opp6 {
5322                                                  5198                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323                                         };       5199                                         };
5324                                                  5200 
5325                                         rpmhp    5201                                         rpmhpd_opp_nom_l1: opp7 {
5326                                                  5202                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327                                         };       5203                                         };
5328                                                  5204 
5329                                         rpmhp    5205                                         rpmhpd_opp_nom_l2: opp8 {
5330                                                  5206                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331                                         };       5207                                         };
5332                                                  5208 
5333                                         rpmhp    5209                                         rpmhpd_opp_turbo: opp9 {
5334                                                  5210                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335                                         };       5211                                         };
5336                                                  5212 
5337                                         rpmhp    5213                                         rpmhpd_opp_turbo_l1: opp10 {
5338                                                  5214                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339                                         };       5215                                         };
5340                                 };               5216                                 };
5341                         };                       5217                         };
5342                 };                               5218                 };
5343                                                  5219 
5344                 intc: interrupt-controller@17    5220                 intc: interrupt-controller@17a00000 {
5345                         compatible = "arm,gic    5221                         compatible = "arm,gic-v3";
5346                         #address-cells = <2>;    5222                         #address-cells = <2>;
5347                         #size-cells = <2>;       5223                         #size-cells = <2>;
5348                         ranges;                  5224                         ranges;
5349                         #interrupt-cells = <3    5225                         #interrupt-cells = <3>;
5350                         interrupt-controller;    5226                         interrupt-controller;
5351                         reg = <0 0x17a00000 0    5227                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
5352                               <0 0x17a60000 0    5228                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
5353                         interrupts = <GIC_PPI    5229                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354                                                  5230 
5355                         msi-controller@17a400    5231                         msi-controller@17a40000 {
5356                                 compatible =     5232                                 compatible = "arm,gic-v3-its";
5357                                 msi-controlle    5233                                 msi-controller;
5358                                 #msi-cells =     5234                                 #msi-cells = <1>;
5359                                 reg = <0 0x17    5235                                 reg = <0 0x17a40000 0 0x20000>;
5360                                 status = "dis    5236                                 status = "disabled";
5361                         };                       5237                         };
5362                 };                               5238                 };
5363                                                  5239 
5364                 slimbam: dma-controller@17184    5240                 slimbam: dma-controller@17184000 {
5365                         compatible = "qcom,ba    5241                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5366                         qcom,controlled-remot    5242                         qcom,controlled-remotely;
5367                         reg = <0 0x17184000 0    5243                         reg = <0 0x17184000 0 0x2a000>;
5368                         num-channels = <31>;     5244                         num-channels = <31>;
5369                         interrupts = <GIC_SPI    5245                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370                         #dma-cells = <1>;        5246                         #dma-cells = <1>;
5371                         qcom,ee = <1>;           5247                         qcom,ee = <1>;
5372                         qcom,num-ees = <2>;      5248                         qcom,num-ees = <2>;
5373                         iommus = <&apps_smmu     5249                         iommus = <&apps_smmu 0x1806 0x0>;
5374                 };                               5250                 };
5375                                                  5251 
5376                 timer@17c90000 {                 5252                 timer@17c90000 {
5377                         #address-cells = <1>;    5253                         #address-cells = <1>;
5378                         #size-cells = <1>;       5254                         #size-cells = <1>;
5379                         ranges = <0 0 0 0x200    5255                         ranges = <0 0 0 0x20000000>;
5380                         compatible = "arm,arm    5256                         compatible = "arm,armv7-timer-mem";
5381                         reg = <0 0x17c90000 0    5257                         reg = <0 0x17c90000 0 0x1000>;
5382                                                  5258 
5383                         frame@17ca0000 {         5259                         frame@17ca0000 {
5384                                 frame-number     5260                                 frame-number = <0>;
5385                                 interrupts =     5261                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386                                                  5262                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387                                 reg = <0x17ca    5263                                 reg = <0x17ca0000 0x1000>,
5388                                       <0x17cb    5264                                       <0x17cb0000 0x1000>;
5389                         };                       5265                         };
5390                                                  5266 
5391                         frame@17cc0000 {         5267                         frame@17cc0000 {
5392                                 frame-number     5268                                 frame-number = <1>;
5393                                 interrupts =     5269                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394                                 reg = <0x17cc    5270                                 reg = <0x17cc0000 0x1000>;
5395                                 status = "dis    5271                                 status = "disabled";
5396                         };                       5272                         };
5397                                                  5273 
5398                         frame@17cd0000 {         5274                         frame@17cd0000 {
5399                                 frame-number     5275                                 frame-number = <2>;
5400                                 interrupts =     5276                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401                                 reg = <0x17cd    5277                                 reg = <0x17cd0000 0x1000>;
5402                                 status = "dis    5278                                 status = "disabled";
5403                         };                       5279                         };
5404                                                  5280 
5405                         frame@17ce0000 {         5281                         frame@17ce0000 {
5406                                 frame-number     5282                                 frame-number = <3>;
5407                                 interrupts =     5283                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408                                 reg = <0x17ce    5284                                 reg = <0x17ce0000 0x1000>;
5409                                 status = "dis    5285                                 status = "disabled";
5410                         };                       5286                         };
5411                                                  5287 
5412                         frame@17cf0000 {         5288                         frame@17cf0000 {
5413                                 frame-number     5289                                 frame-number = <4>;
5414                                 interrupts =     5290                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415                                 reg = <0x17cf    5291                                 reg = <0x17cf0000 0x1000>;
5416                                 status = "dis    5292                                 status = "disabled";
5417                         };                       5293                         };
5418                                                  5294 
5419                         frame@17d00000 {         5295                         frame@17d00000 {
5420                                 frame-number     5296                                 frame-number = <5>;
5421                                 interrupts =     5297                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422                                 reg = <0x17d0    5298                                 reg = <0x17d00000 0x1000>;
5423                                 status = "dis    5299                                 status = "disabled";
5424                         };                       5300                         };
5425                                                  5301 
5426                         frame@17d10000 {         5302                         frame@17d10000 {
5427                                 frame-number     5303                                 frame-number = <6>;
5428                                 interrupts =     5304                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429                                 reg = <0x17d1    5305                                 reg = <0x17d10000 0x1000>;
5430                                 status = "dis    5306                                 status = "disabled";
5431                         };                       5307                         };
5432                 };                               5308                 };
5433                                                  5309 
5434                 osm_l3: interconnect@17d41000    5310                 osm_l3: interconnect@17d41000 {
5435                         compatible = "qcom,sd    5311                         compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5436                         reg = <0 0x17d41000 0    5312                         reg = <0 0x17d41000 0 0x1400>;
5437                                                  5313 
5438                         clocks = <&rpmhcc RPM    5314                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439                         clock-names = "xo", "    5315                         clock-names = "xo", "alternate";
5440                                                  5316 
5441                         #interconnect-cells =    5317                         #interconnect-cells = <1>;
5442                 };                               5318                 };
5443                                                  5319 
5444                 cpufreq_hw: cpufreq@17d43000     5320                 cpufreq_hw: cpufreq@17d43000 {
5445                         compatible = "qcom,sd    5321                         compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5446                         reg = <0 0x17d43000 0    5322                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447                         reg-names = "freq-dom    5323                         reg-names = "freq-domain0", "freq-domain1";
5448                                                  5324 
5449                         interrupts-extended =    5325                         interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450                                                  5326 
5451                         clocks = <&rpmhcc RPM    5327                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452                         clock-names = "xo", "    5328                         clock-names = "xo", "alternate";
5453                                                  5329 
5454                         #freq-domain-cells =     5330                         #freq-domain-cells = <1>;
5455                         #clock-cells = <1>;      5331                         #clock-cells = <1>;
5456                 };                               5332                 };
5457                                                  5333 
5458                 wifi: wifi@18800000 {            5334                 wifi: wifi@18800000 {
5459                         compatible = "qcom,wc    5335                         compatible = "qcom,wcn3990-wifi";
5460                         status = "disabled";     5336                         status = "disabled";
5461                         reg = <0 0x18800000 0    5337                         reg = <0 0x18800000 0 0x800000>;
5462                         reg-names = "membase"    5338                         reg-names = "membase";
5463                         memory-region = <&wla    5339                         memory-region = <&wlan_msa_mem>;
5464                         clock-names = "cxo_re    5340                         clock-names = "cxo_ref_clk_pin";
5465                         clocks = <&rpmhcc RPM    5341                         clocks = <&rpmhcc RPMH_RF_CLK2>;
5466                         interrupts =             5342                         interrupts =
5467                                 <GIC_SPI 414     5343                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468                                 <GIC_SPI 415     5344                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469                                 <GIC_SPI 416     5345                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470                                 <GIC_SPI 417     5346                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471                                 <GIC_SPI 418     5347                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472                                 <GIC_SPI 419     5348                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473                                 <GIC_SPI 420     5349                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474                                 <GIC_SPI 421     5350                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475                                 <GIC_SPI 422     5351                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476                                 <GIC_SPI 423     5352                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477                                 <GIC_SPI 424     5353                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478                                 <GIC_SPI 425     5354                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479                         iommus = <&apps_smmu     5355                         iommus = <&apps_smmu 0x0040 0x1>;
5480                 };                               5356                 };
5481         };                                       5357         };
5482                                                  5358 
5483         sound: sound {                           5359         sound: sound {
5484         };                                       5360         };
5485                                                  5361 
5486         thermal-zones {                          5362         thermal-zones {
5487                 cpu0-thermal {                   5363                 cpu0-thermal {
5488                         polling-delay-passive    5364                         polling-delay-passive = <250>;
                                                   >> 5365                         polling-delay = <1000>;
5489                                                  5366 
5490                         thermal-sensors = <&t    5367                         thermal-sensors = <&tsens0 1>;
5491                                                  5368 
5492                         trips {                  5369                         trips {
5493                                 cpu0_alert0:     5370                                 cpu0_alert0: trip-point0 {
5494                                         tempe    5371                                         temperature = <90000>;
5495                                         hyste    5372                                         hysteresis = <2000>;
5496                                         type     5373                                         type = "passive";
5497                                 };               5374                                 };
5498                                                  5375 
5499                                 cpu0_alert1:     5376                                 cpu0_alert1: trip-point1 {
5500                                         tempe    5377                                         temperature = <95000>;
5501                                         hyste    5378                                         hysteresis = <2000>;
5502                                         type     5379                                         type = "passive";
5503                                 };               5380                                 };
5504                                                  5381 
5505                                 cpu0_crit: cp    5382                                 cpu0_crit: cpu-crit {
5506                                         tempe    5383                                         temperature = <110000>;
5507                                         hyste    5384                                         hysteresis = <1000>;
5508                                         type     5385                                         type = "critical";
5509                                 };               5386                                 };
5510                         };                       5387                         };
5511                 };                               5388                 };
5512                                                  5389 
5513                 cpu1-thermal {                   5390                 cpu1-thermal {
5514                         polling-delay-passive    5391                         polling-delay-passive = <250>;
                                                   >> 5392                         polling-delay = <1000>;
5515                                                  5393 
5516                         thermal-sensors = <&t    5394                         thermal-sensors = <&tsens0 2>;
5517                                                  5395 
5518                         trips {                  5396                         trips {
5519                                 cpu1_alert0:     5397                                 cpu1_alert0: trip-point0 {
5520                                         tempe    5398                                         temperature = <90000>;
5521                                         hyste    5399                                         hysteresis = <2000>;
5522                                         type     5400                                         type = "passive";
5523                                 };               5401                                 };
5524                                                  5402 
5525                                 cpu1_alert1:     5403                                 cpu1_alert1: trip-point1 {
5526                                         tempe    5404                                         temperature = <95000>;
5527                                         hyste    5405                                         hysteresis = <2000>;
5528                                         type     5406                                         type = "passive";
5529                                 };               5407                                 };
5530                                                  5408 
5531                                 cpu1_crit: cp    5409                                 cpu1_crit: cpu-crit {
5532                                         tempe    5410                                         temperature = <110000>;
5533                                         hyste    5411                                         hysteresis = <1000>;
5534                                         type     5412                                         type = "critical";
5535                                 };               5413                                 };
5536                         };                       5414                         };
5537                 };                               5415                 };
5538                                                  5416 
5539                 cpu2-thermal {                   5417                 cpu2-thermal {
5540                         polling-delay-passive    5418                         polling-delay-passive = <250>;
                                                   >> 5419                         polling-delay = <1000>;
5541                                                  5420 
5542                         thermal-sensors = <&t    5421                         thermal-sensors = <&tsens0 3>;
5543                                                  5422 
5544                         trips {                  5423                         trips {
5545                                 cpu2_alert0:     5424                                 cpu2_alert0: trip-point0 {
5546                                         tempe    5425                                         temperature = <90000>;
5547                                         hyste    5426                                         hysteresis = <2000>;
5548                                         type     5427                                         type = "passive";
5549                                 };               5428                                 };
5550                                                  5429 
5551                                 cpu2_alert1:     5430                                 cpu2_alert1: trip-point1 {
5552                                         tempe    5431                                         temperature = <95000>;
5553                                         hyste    5432                                         hysteresis = <2000>;
5554                                         type     5433                                         type = "passive";
5555                                 };               5434                                 };
5556                                                  5435 
5557                                 cpu2_crit: cp    5436                                 cpu2_crit: cpu-crit {
5558                                         tempe    5437                                         temperature = <110000>;
5559                                         hyste    5438                                         hysteresis = <1000>;
5560                                         type     5439                                         type = "critical";
5561                                 };               5440                                 };
5562                         };                       5441                         };
5563                 };                               5442                 };
5564                                                  5443 
5565                 cpu3-thermal {                   5444                 cpu3-thermal {
5566                         polling-delay-passive    5445                         polling-delay-passive = <250>;
                                                   >> 5446                         polling-delay = <1000>;
5567                                                  5447 
5568                         thermal-sensors = <&t    5448                         thermal-sensors = <&tsens0 4>;
5569                                                  5449 
5570                         trips {                  5450                         trips {
5571                                 cpu3_alert0:     5451                                 cpu3_alert0: trip-point0 {
5572                                         tempe    5452                                         temperature = <90000>;
5573                                         hyste    5453                                         hysteresis = <2000>;
5574                                         type     5454                                         type = "passive";
5575                                 };               5455                                 };
5576                                                  5456 
5577                                 cpu3_alert1:     5457                                 cpu3_alert1: trip-point1 {
5578                                         tempe    5458                                         temperature = <95000>;
5579                                         hyste    5459                                         hysteresis = <2000>;
5580                                         type     5460                                         type = "passive";
5581                                 };               5461                                 };
5582                                                  5462 
5583                                 cpu3_crit: cp    5463                                 cpu3_crit: cpu-crit {
5584                                         tempe    5464                                         temperature = <110000>;
5585                                         hyste    5465                                         hysteresis = <1000>;
5586                                         type     5466                                         type = "critical";
5587                                 };               5467                                 };
5588                         };                       5468                         };
5589                 };                               5469                 };
5590                                                  5470 
5591                 cpu4-thermal {                   5471                 cpu4-thermal {
5592                         polling-delay-passive    5472                         polling-delay-passive = <250>;
                                                   >> 5473                         polling-delay = <1000>;
5593                                                  5474 
5594                         thermal-sensors = <&t    5475                         thermal-sensors = <&tsens0 7>;
5595                                                  5476 
5596                         trips {                  5477                         trips {
5597                                 cpu4_alert0:     5478                                 cpu4_alert0: trip-point0 {
5598                                         tempe    5479                                         temperature = <90000>;
5599                                         hyste    5480                                         hysteresis = <2000>;
5600                                         type     5481                                         type = "passive";
5601                                 };               5482                                 };
5602                                                  5483 
5603                                 cpu4_alert1:     5484                                 cpu4_alert1: trip-point1 {
5604                                         tempe    5485                                         temperature = <95000>;
5605                                         hyste    5486                                         hysteresis = <2000>;
5606                                         type     5487                                         type = "passive";
5607                                 };               5488                                 };
5608                                                  5489 
5609                                 cpu4_crit: cp    5490                                 cpu4_crit: cpu-crit {
5610                                         tempe    5491                                         temperature = <110000>;
5611                                         hyste    5492                                         hysteresis = <1000>;
5612                                         type     5493                                         type = "critical";
5613                                 };               5494                                 };
5614                         };                       5495                         };
5615                 };                               5496                 };
5616                                                  5497 
5617                 cpu5-thermal {                   5498                 cpu5-thermal {
5618                         polling-delay-passive    5499                         polling-delay-passive = <250>;
                                                   >> 5500                         polling-delay = <1000>;
5619                                                  5501 
5620                         thermal-sensors = <&t    5502                         thermal-sensors = <&tsens0 8>;
5621                                                  5503 
5622                         trips {                  5504                         trips {
5623                                 cpu5_alert0:     5505                                 cpu5_alert0: trip-point0 {
5624                                         tempe    5506                                         temperature = <90000>;
5625                                         hyste    5507                                         hysteresis = <2000>;
5626                                         type     5508                                         type = "passive";
5627                                 };               5509                                 };
5628                                                  5510 
5629                                 cpu5_alert1:     5511                                 cpu5_alert1: trip-point1 {
5630                                         tempe    5512                                         temperature = <95000>;
5631                                         hyste    5513                                         hysteresis = <2000>;
5632                                         type     5514                                         type = "passive";
5633                                 };               5515                                 };
5634                                                  5516 
5635                                 cpu5_crit: cp    5517                                 cpu5_crit: cpu-crit {
5636                                         tempe    5518                                         temperature = <110000>;
5637                                         hyste    5519                                         hysteresis = <1000>;
5638                                         type     5520                                         type = "critical";
5639                                 };               5521                                 };
5640                         };                       5522                         };
5641                 };                               5523                 };
5642                                                  5524 
5643                 cpu6-thermal {                   5525                 cpu6-thermal {
5644                         polling-delay-passive    5526                         polling-delay-passive = <250>;
                                                   >> 5527                         polling-delay = <1000>;
5645                                                  5528 
5646                         thermal-sensors = <&t    5529                         thermal-sensors = <&tsens0 9>;
5647                                                  5530 
5648                         trips {                  5531                         trips {
5649                                 cpu6_alert0:     5532                                 cpu6_alert0: trip-point0 {
5650                                         tempe    5533                                         temperature = <90000>;
5651                                         hyste    5534                                         hysteresis = <2000>;
5652                                         type     5535                                         type = "passive";
5653                                 };               5536                                 };
5654                                                  5537 
5655                                 cpu6_alert1:     5538                                 cpu6_alert1: trip-point1 {
5656                                         tempe    5539                                         temperature = <95000>;
5657                                         hyste    5540                                         hysteresis = <2000>;
5658                                         type     5541                                         type = "passive";
5659                                 };               5542                                 };
5660                                                  5543 
5661                                 cpu6_crit: cp    5544                                 cpu6_crit: cpu-crit {
5662                                         tempe    5545                                         temperature = <110000>;
5663                                         hyste    5546                                         hysteresis = <1000>;
5664                                         type     5547                                         type = "critical";
5665                                 };               5548                                 };
5666                         };                       5549                         };
5667                 };                               5550                 };
5668                                                  5551 
5669                 cpu7-thermal {                   5552                 cpu7-thermal {
5670                         polling-delay-passive    5553                         polling-delay-passive = <250>;
                                                   >> 5554                         polling-delay = <1000>;
5671                                                  5555 
5672                         thermal-sensors = <&t    5556                         thermal-sensors = <&tsens0 10>;
5673                                                  5557 
5674                         trips {                  5558                         trips {
5675                                 cpu7_alert0:     5559                                 cpu7_alert0: trip-point0 {
5676                                         tempe    5560                                         temperature = <90000>;
5677                                         hyste    5561                                         hysteresis = <2000>;
5678                                         type     5562                                         type = "passive";
5679                                 };               5563                                 };
5680                                                  5564 
5681                                 cpu7_alert1:     5565                                 cpu7_alert1: trip-point1 {
5682                                         tempe    5566                                         temperature = <95000>;
5683                                         hyste    5567                                         hysteresis = <2000>;
5684                                         type     5568                                         type = "passive";
5685                                 };               5569                                 };
5686                                                  5570 
5687                                 cpu7_crit: cp    5571                                 cpu7_crit: cpu-crit {
5688                                         tempe    5572                                         temperature = <110000>;
5689                                         hyste    5573                                         hysteresis = <1000>;
5690                                         type     5574                                         type = "critical";
5691                                 };               5575                                 };
5692                         };                       5576                         };
5693                 };                               5577                 };
5694                                                  5578 
5695                 aoss0-thermal {                  5579                 aoss0-thermal {
5696                         polling-delay-passive    5580                         polling-delay-passive = <250>;
                                                   >> 5581                         polling-delay = <1000>;
5697                                                  5582 
5698                         thermal-sensors = <&t    5583                         thermal-sensors = <&tsens0 0>;
5699                                                  5584 
5700                         trips {                  5585                         trips {
5701                                 aoss0_alert0:    5586                                 aoss0_alert0: trip-point0 {
5702                                         tempe    5587                                         temperature = <90000>;
5703                                         hyste    5588                                         hysteresis = <2000>;
5704                                         type     5589                                         type = "hot";
5705                                 };               5590                                 };
5706                         };                       5591                         };
5707                 };                               5592                 };
5708                                                  5593 
5709                 cluster0-thermal {               5594                 cluster0-thermal {
5710                         polling-delay-passive    5595                         polling-delay-passive = <250>;
                                                   >> 5596                         polling-delay = <1000>;
5711                                                  5597 
5712                         thermal-sensors = <&t    5598                         thermal-sensors = <&tsens0 5>;
5713                                                  5599 
5714                         trips {                  5600                         trips {
5715                                 cluster0_aler    5601                                 cluster0_alert0: trip-point0 {
5716                                         tempe    5602                                         temperature = <90000>;
5717                                         hyste    5603                                         hysteresis = <2000>;
5718                                         type     5604                                         type = "hot";
5719                                 };               5605                                 };
5720                                 cluster0_crit    5606                                 cluster0_crit: cluster0-crit {
5721                                         tempe    5607                                         temperature = <110000>;
5722                                         hyste    5608                                         hysteresis = <2000>;
5723                                         type     5609                                         type = "critical";
5724                                 };               5610                                 };
5725                         };                       5611                         };
5726                 };                               5612                 };
5727                                                  5613 
5728                 cluster1-thermal {               5614                 cluster1-thermal {
5729                         polling-delay-passive    5615                         polling-delay-passive = <250>;
                                                   >> 5616                         polling-delay = <1000>;
5730                                                  5617 
5731                         thermal-sensors = <&t    5618                         thermal-sensors = <&tsens0 6>;
5732                                                  5619 
5733                         trips {                  5620                         trips {
5734                                 cluster1_aler    5621                                 cluster1_alert0: trip-point0 {
5735                                         tempe    5622                                         temperature = <90000>;
5736                                         hyste    5623                                         hysteresis = <2000>;
5737                                         type     5624                                         type = "hot";
5738                                 };               5625                                 };
5739                                 cluster1_crit    5626                                 cluster1_crit: cluster1-crit {
5740                                         tempe    5627                                         temperature = <110000>;
5741                                         hyste    5628                                         hysteresis = <2000>;
5742                                         type     5629                                         type = "critical";
5743                                 };               5630                                 };
5744                         };                       5631                         };
5745                 };                               5632                 };
5746                                                  5633 
5747                 gpu-top-thermal {                5634                 gpu-top-thermal {
5748                         polling-delay-passive    5635                         polling-delay-passive = <250>;
                                                   >> 5636                         polling-delay = <1000>;
5749                                                  5637 
5750                         thermal-sensors = <&t    5638                         thermal-sensors = <&tsens0 11>;
5751                                                  5639 
5752                         cooling-maps {           5640                         cooling-maps {
5753                                 map0 {           5641                                 map0 {
5754                                         trip     5642                                         trip = <&gpu_top_alert0>;
5755                                         cooli    5643                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5756                                 };               5644                                 };
5757                         };                       5645                         };
5758                                                  5646 
5759                         trips {                  5647                         trips {
5760                                 gpu_top_alert    5648                                 gpu_top_alert0: trip-point0 {
5761                                         tempe << 
5762                                         hyste << 
5763                                         type  << 
5764                                 };            << 
5765                                               << 
5766                                 trip-point1 { << 
5767                                         tempe    5649                                         temperature = <90000>;
5768                                         hyste !! 5650                                         hysteresis = <2000>;
5769                                         type     5651                                         type = "hot";
5770                                 };               5652                                 };
5771                                               << 
5772                                 trip-point2 { << 
5773                                         tempe << 
5774                                         hyste << 
5775                                         type  << 
5776                                 };            << 
5777                         };                       5653                         };
5778                 };                               5654                 };
5779                                                  5655 
5780                 gpu-bottom-thermal {             5656                 gpu-bottom-thermal {
5781                         polling-delay-passive    5657                         polling-delay-passive = <250>;
                                                   >> 5658                         polling-delay = <1000>;
5782                                                  5659 
5783                         thermal-sensors = <&t    5660                         thermal-sensors = <&tsens0 12>;
5784                                                  5661 
5785                         cooling-maps {           5662                         cooling-maps {
5786                                 map0 {           5663                                 map0 {
5787                                         trip     5664                                         trip = <&gpu_bottom_alert0>;
5788                                         cooli    5665                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5789                                 };               5666                                 };
5790                         };                       5667                         };
5791                                                  5668 
5792                         trips {                  5669                         trips {
5793                                 gpu_bottom_al    5670                                 gpu_bottom_alert0: trip-point0 {
5794                                         tempe << 
5795                                         hyste << 
5796                                         type  << 
5797                                 };            << 
5798                                               << 
5799                                 trip-point1 { << 
5800                                         tempe    5671                                         temperature = <90000>;
5801                                         hyste !! 5672                                         hysteresis = <2000>;
5802                                         type     5673                                         type = "hot";
5803                                 };               5674                                 };
5804                                               << 
5805                                 trip-point2 { << 
5806                                         tempe << 
5807                                         hyste << 
5808                                         type  << 
5809                                 };            << 
5810                         };                       5675                         };
5811                 };                               5676                 };
5812                                                  5677 
5813                 aoss1-thermal {                  5678                 aoss1-thermal {
5814                         polling-delay-passive    5679                         polling-delay-passive = <250>;
                                                   >> 5680                         polling-delay = <1000>;
5815                                                  5681 
5816                         thermal-sensors = <&t    5682                         thermal-sensors = <&tsens1 0>;
5817                                                  5683 
5818                         trips {                  5684                         trips {
5819                                 aoss1_alert0:    5685                                 aoss1_alert0: trip-point0 {
5820                                         tempe    5686                                         temperature = <90000>;
5821                                         hyste    5687                                         hysteresis = <2000>;
5822                                         type     5688                                         type = "hot";
5823                                 };               5689                                 };
5824                         };                       5690                         };
5825                 };                               5691                 };
5826                                                  5692 
5827                 q6-modem-thermal {               5693                 q6-modem-thermal {
5828                         polling-delay-passive    5694                         polling-delay-passive = <250>;
                                                   >> 5695                         polling-delay = <1000>;
5829                                                  5696 
5830                         thermal-sensors = <&t    5697                         thermal-sensors = <&tsens1 1>;
5831                                                  5698 
5832                         trips {                  5699                         trips {
5833                                 q6_modem_aler    5700                                 q6_modem_alert0: trip-point0 {
5834                                         tempe    5701                                         temperature = <90000>;
5835                                         hyste    5702                                         hysteresis = <2000>;
5836                                         type     5703                                         type = "hot";
5837                                 };               5704                                 };
5838                         };                       5705                         };
5839                 };                               5706                 };
5840                                                  5707 
5841                 mem-thermal {                    5708                 mem-thermal {
5842                         polling-delay-passive    5709                         polling-delay-passive = <250>;
                                                   >> 5710                         polling-delay = <1000>;
5843                                                  5711 
5844                         thermal-sensors = <&t    5712                         thermal-sensors = <&tsens1 2>;
5845                                                  5713 
5846                         trips {                  5714                         trips {
5847                                 mem_alert0: t    5715                                 mem_alert0: trip-point0 {
5848                                         tempe    5716                                         temperature = <90000>;
5849                                         hyste    5717                                         hysteresis = <2000>;
5850                                         type     5718                                         type = "hot";
5851                                 };               5719                                 };
5852                         };                       5720                         };
5853                 };                               5721                 };
5854                                                  5722 
5855                 wlan-thermal {                   5723                 wlan-thermal {
5856                         polling-delay-passive    5724                         polling-delay-passive = <250>;
                                                   >> 5725                         polling-delay = <1000>;
5857                                                  5726 
5858                         thermal-sensors = <&t    5727                         thermal-sensors = <&tsens1 3>;
5859                                                  5728 
5860                         trips {                  5729                         trips {
5861                                 wlan_alert0:     5730                                 wlan_alert0: trip-point0 {
5862                                         tempe    5731                                         temperature = <90000>;
5863                                         hyste    5732                                         hysteresis = <2000>;
5864                                         type     5733                                         type = "hot";
5865                                 };               5734                                 };
5866                         };                       5735                         };
5867                 };                               5736                 };
5868                                                  5737 
5869                 q6-hvx-thermal {                 5738                 q6-hvx-thermal {
5870                         polling-delay-passive    5739                         polling-delay-passive = <250>;
                                                   >> 5740                         polling-delay = <1000>;
5871                                                  5741 
5872                         thermal-sensors = <&t    5742                         thermal-sensors = <&tsens1 4>;
5873                                                  5743 
5874                         trips {                  5744                         trips {
5875                                 q6_hvx_alert0    5745                                 q6_hvx_alert0: trip-point0 {
5876                                         tempe    5746                                         temperature = <90000>;
5877                                         hyste    5747                                         hysteresis = <2000>;
5878                                         type     5748                                         type = "hot";
5879                                 };               5749                                 };
5880                         };                       5750                         };
5881                 };                               5751                 };
5882                                                  5752 
5883                 camera-thermal {                 5753                 camera-thermal {
5884                         polling-delay-passive    5754                         polling-delay-passive = <250>;
                                                   >> 5755                         polling-delay = <1000>;
5885                                                  5756 
5886                         thermal-sensors = <&t    5757                         thermal-sensors = <&tsens1 5>;
5887                                                  5758 
5888                         trips {                  5759                         trips {
5889                                 camera_alert0    5760                                 camera_alert0: trip-point0 {
5890                                         tempe    5761                                         temperature = <90000>;
5891                                         hyste    5762                                         hysteresis = <2000>;
5892                                         type     5763                                         type = "hot";
5893                                 };               5764                                 };
5894                         };                       5765                         };
5895                 };                               5766                 };
5896                                                  5767 
5897                 video-thermal {                  5768                 video-thermal {
5898                         polling-delay-passive    5769                         polling-delay-passive = <250>;
                                                   >> 5770                         polling-delay = <1000>;
5899                                                  5771 
5900                         thermal-sensors = <&t    5772                         thermal-sensors = <&tsens1 6>;
5901                                                  5773 
5902                         trips {                  5774                         trips {
5903                                 video_alert0:    5775                                 video_alert0: trip-point0 {
5904                                         tempe    5776                                         temperature = <90000>;
5905                                         hyste    5777                                         hysteresis = <2000>;
5906                                         type     5778                                         type = "hot";
5907                                 };               5779                                 };
5908                         };                       5780                         };
5909                 };                               5781                 };
5910                                                  5782 
5911                 modem-thermal {                  5783                 modem-thermal {
5912                         polling-delay-passive    5784                         polling-delay-passive = <250>;
                                                   >> 5785                         polling-delay = <1000>;
5913                                                  5786 
5914                         thermal-sensors = <&t    5787                         thermal-sensors = <&tsens1 7>;
5915                                                  5788 
5916                         trips {                  5789                         trips {
5917                                 modem_alert0:    5790                                 modem_alert0: trip-point0 {
5918                                         tempe    5791                                         temperature = <90000>;
5919                                         hyste    5792                                         hysteresis = <2000>;
5920                                         type     5793                                         type = "hot";
5921                                 };               5794                                 };
5922                         };                       5795                         };
5923                 };                               5796                 };
5924         };                                       5797         };
5925                                                  5798 
5926         timer {                                  5799         timer {
5927                 compatible = "arm,armv8-timer    5800                 compatible = "arm,armv8-timer";
5928                 interrupts = <GIC_PPI 1 IRQ_T    5801                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5929                              <GIC_PPI 2 IRQ_T    5802                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5930                              <GIC_PPI 3 IRQ_T    5803                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5931                              <GIC_PPI 0 IRQ_T    5804                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5932         };                                       5805         };
5933 };                                               5806 };
                                                      

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