1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> 15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h> <<
17 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 18 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 19 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 21 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 24 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 27 #include <dt-bindings/thermal/thermal.h>
31 28
32 / { 29 / {
33 interrupt-parent = <&intc>; 30 interrupt-parent = <&intc>;
34 31
35 #address-cells = <2>; 32 #address-cells = <2>;
36 #size-cells = <2>; 33 #size-cells = <2>;
37 34
38 aliases { 35 aliases {
39 i2c0 = &i2c0; 36 i2c0 = &i2c0;
40 i2c1 = &i2c1; 37 i2c1 = &i2c1;
41 i2c2 = &i2c2; 38 i2c2 = &i2c2;
42 i2c3 = &i2c3; 39 i2c3 = &i2c3;
43 i2c4 = &i2c4; 40 i2c4 = &i2c4;
44 i2c5 = &i2c5; 41 i2c5 = &i2c5;
45 i2c6 = &i2c6; 42 i2c6 = &i2c6;
46 i2c7 = &i2c7; 43 i2c7 = &i2c7;
47 i2c8 = &i2c8; 44 i2c8 = &i2c8;
48 i2c9 = &i2c9; 45 i2c9 = &i2c9;
49 i2c10 = &i2c10; 46 i2c10 = &i2c10;
50 i2c11 = &i2c11; 47 i2c11 = &i2c11;
51 i2c12 = &i2c12; 48 i2c12 = &i2c12;
52 i2c13 = &i2c13; 49 i2c13 = &i2c13;
53 i2c14 = &i2c14; 50 i2c14 = &i2c14;
54 i2c15 = &i2c15; 51 i2c15 = &i2c15;
55 spi0 = &spi0; 52 spi0 = &spi0;
56 spi1 = &spi1; 53 spi1 = &spi1;
57 spi2 = &spi2; 54 spi2 = &spi2;
58 spi3 = &spi3; 55 spi3 = &spi3;
59 spi4 = &spi4; 56 spi4 = &spi4;
60 spi5 = &spi5; 57 spi5 = &spi5;
61 spi6 = &spi6; 58 spi6 = &spi6;
62 spi7 = &spi7; 59 spi7 = &spi7;
63 spi8 = &spi8; 60 spi8 = &spi8;
64 spi9 = &spi9; 61 spi9 = &spi9;
65 spi10 = &spi10; 62 spi10 = &spi10;
66 spi11 = &spi11; 63 spi11 = &spi11;
67 spi12 = &spi12; 64 spi12 = &spi12;
68 spi13 = &spi13; 65 spi13 = &spi13;
69 spi14 = &spi14; 66 spi14 = &spi14;
70 spi15 = &spi15; 67 spi15 = &spi15;
71 }; 68 };
72 69
73 chosen { }; 70 chosen { };
74 71
75 clocks { !! 72 memory@80000000 {
76 xo_board: xo-board { !! 73 device_type = "memory";
77 compatible = "fixed-cl !! 74 /* We expect the bootloader to fill in the size */
78 #clock-cells = <0>; !! 75 reg = <0 0x80000000 0 0>;
79 clock-frequency = <384 !! 76 };
80 clock-output-names = " !! 77
>> 78 reserved-memory {
>> 79 #address-cells = <2>;
>> 80 #size-cells = <2>;
>> 81 ranges;
>> 82
>> 83 hyp_mem: hyp-mem@85700000 {
>> 84 reg = <0 0x85700000 0 0x600000>;
>> 85 no-map;
81 }; 86 };
82 87
83 sleep_clk: sleep-clk { !! 88 xbl_mem: xbl-mem@85e00000 {
84 compatible = "fixed-cl !! 89 reg = <0 0x85e00000 0 0x100000>;
85 #clock-cells = <0>; !! 90 no-map;
86 clock-frequency = <327 !! 91 };
>> 92
>> 93 aop_mem: aop-mem@85fc0000 {
>> 94 reg = <0 0x85fc0000 0 0x20000>;
>> 95 no-map;
>> 96 };
>> 97
>> 98 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
>> 99 compatible = "qcom,cmd-db";
>> 100 reg = <0x0 0x85fe0000 0 0x20000>;
>> 101 no-map;
>> 102 };
>> 103
>> 104 smem@86000000 {
>> 105 compatible = "qcom,smem";
>> 106 reg = <0x0 0x86000000 0 0x200000>;
>> 107 no-map;
>> 108 hwlocks = <&tcsr_mutex 3>;
>> 109 };
>> 110
>> 111 tz_mem: tz@86200000 {
>> 112 reg = <0 0x86200000 0 0x2d00000>;
>> 113 no-map;
>> 114 };
>> 115
>> 116 rmtfs_mem: rmtfs@88f00000 {
>> 117 compatible = "qcom,rmtfs-mem";
>> 118 reg = <0 0x88f00000 0 0x200000>;
>> 119 no-map;
>> 120
>> 121 qcom,client-id = <1>;
>> 122 qcom,vmid = <15>;
>> 123 };
>> 124
>> 125 qseecom_mem: qseecom@8ab00000 {
>> 126 reg = <0 0x8ab00000 0 0x1400000>;
>> 127 no-map;
>> 128 };
>> 129
>> 130 camera_mem: camera-mem@8bf00000 {
>> 131 reg = <0 0x8bf00000 0 0x500000>;
>> 132 no-map;
>> 133 };
>> 134
>> 135 ipa_fw_mem: ipa-fw@8c400000 {
>> 136 reg = <0 0x8c400000 0 0x10000>;
>> 137 no-map;
>> 138 };
>> 139
>> 140 ipa_gsi_mem: ipa-gsi@8c410000 {
>> 141 reg = <0 0x8c410000 0 0x5000>;
>> 142 no-map;
>> 143 };
>> 144
>> 145 gpu_mem: gpu@8c415000 {
>> 146 reg = <0 0x8c415000 0 0x2000>;
>> 147 no-map;
>> 148 };
>> 149
>> 150 adsp_mem: adsp@8c500000 {
>> 151 reg = <0 0x8c500000 0 0x1a00000>;
>> 152 no-map;
>> 153 };
>> 154
>> 155 wlan_msa_mem: wlan-msa@8df00000 {
>> 156 reg = <0 0x8df00000 0 0x100000>;
>> 157 no-map;
>> 158 };
>> 159
>> 160 mpss_region: mpss@8e000000 {
>> 161 reg = <0 0x8e000000 0 0x7800000>;
>> 162 no-map;
>> 163 };
>> 164
>> 165 venus_mem: venus@95800000 {
>> 166 reg = <0 0x95800000 0 0x500000>;
>> 167 no-map;
>> 168 };
>> 169
>> 170 cdsp_mem: cdsp@95d00000 {
>> 171 reg = <0 0x95d00000 0 0x800000>;
>> 172 no-map;
>> 173 };
>> 174
>> 175 mba_region: mba@96500000 {
>> 176 reg = <0 0x96500000 0 0x200000>;
>> 177 no-map;
>> 178 };
>> 179
>> 180 slpi_mem: slpi@96700000 {
>> 181 reg = <0 0x96700000 0 0x1400000>;
>> 182 no-map;
>> 183 };
>> 184
>> 185 spss_mem: spss@97b00000 {
>> 186 reg = <0 0x97b00000 0 0x100000>;
>> 187 no-map;
87 }; 188 };
88 }; 189 };
89 190
90 cpus: cpus { 191 cpus: cpus {
91 #address-cells = <2>; 192 #address-cells = <2>;
92 #size-cells = <0>; 193 #size-cells = <0>;
93 194
94 CPU0: cpu@0 { 195 CPU0: cpu@0 {
95 device_type = "cpu"; 196 device_type = "cpu";
96 compatible = "qcom,kry 197 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 198 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw <<
99 enable-method = "psci" 199 enable-method = "psci";
100 capacity-dmips-mhz = < 200 capacity-dmips-mhz = <611>;
101 dynamic-power-coeffici 201 dynamic-power-coefficient = <154>;
102 qcom,freq-domain = <&c 202 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 203 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 204 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ 206 power-domains = <&CPU_PD0>;
107 power-domain-names = " 207 power-domain-names = "psci";
108 #cooling-cells = <2>; 208 #cooling-cells = <2>;
109 next-level-cache = <&L 209 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 210 L2_0: l2-cache {
111 compatible = " 211 compatible = "cache";
112 cache-level = <<
113 cache-unified; <<
114 next-level-cac 212 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 213 L3_0: l3-cache {
116 compat !! 214 compatible = "cache";
117 cache- <<
118 cache- <<
119 }; 215 };
120 }; 216 };
121 }; 217 };
122 218
123 CPU1: cpu@100 { 219 CPU1: cpu@100 {
124 device_type = "cpu"; 220 device_type = "cpu";
125 compatible = "qcom,kry 221 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 222 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw <<
128 enable-method = "psci" 223 enable-method = "psci";
129 capacity-dmips-mhz = < 224 capacity-dmips-mhz = <611>;
130 dynamic-power-coeffici 225 dynamic-power-coefficient = <154>;
131 qcom,freq-domain = <&c 226 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 227 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 228 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ 230 power-domains = <&CPU_PD1>;
136 power-domain-names = " 231 power-domain-names = "psci";
137 #cooling-cells = <2>; 232 #cooling-cells = <2>;
138 next-level-cache = <&L 233 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 234 L2_100: l2-cache {
140 compatible = " 235 compatible = "cache";
141 cache-level = <<
142 cache-unified; <<
143 next-level-cac 236 next-level-cache = <&L3_0>;
144 }; 237 };
145 }; 238 };
146 239
147 CPU2: cpu@200 { 240 CPU2: cpu@200 {
148 device_type = "cpu"; 241 device_type = "cpu";
149 compatible = "qcom,kry 242 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 243 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw <<
152 enable-method = "psci" 244 enable-method = "psci";
153 capacity-dmips-mhz = < 245 capacity-dmips-mhz = <611>;
154 dynamic-power-coeffici 246 dynamic-power-coefficient = <154>;
155 qcom,freq-domain = <&c 247 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 248 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 249 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 250 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ 251 power-domains = <&CPU_PD2>;
160 power-domain-names = " 252 power-domain-names = "psci";
161 #cooling-cells = <2>; 253 #cooling-cells = <2>;
162 next-level-cache = <&L 254 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 255 L2_200: l2-cache {
164 compatible = " 256 compatible = "cache";
165 cache-level = <<
166 cache-unified; <<
167 next-level-cac 257 next-level-cache = <&L3_0>;
168 }; 258 };
169 }; 259 };
170 260
171 CPU3: cpu@300 { 261 CPU3: cpu@300 {
172 device_type = "cpu"; 262 device_type = "cpu";
173 compatible = "qcom,kry 263 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 264 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw <<
176 enable-method = "psci" 265 enable-method = "psci";
177 capacity-dmips-mhz = < 266 capacity-dmips-mhz = <611>;
178 dynamic-power-coeffici 267 dynamic-power-coefficient = <154>;
179 qcom,freq-domain = <&c 268 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 269 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 270 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 271 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 272 #cooling-cells = <2>;
184 power-domains = <&CPU_ 273 power-domains = <&CPU_PD3>;
185 power-domain-names = " 274 power-domain-names = "psci";
186 next-level-cache = <&L 275 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 276 L2_300: l2-cache {
188 compatible = " 277 compatible = "cache";
189 cache-level = <<
190 cache-unified; <<
191 next-level-cac 278 next-level-cache = <&L3_0>;
192 }; 279 };
193 }; 280 };
194 281
195 CPU4: cpu@400 { 282 CPU4: cpu@400 {
196 device_type = "cpu"; 283 device_type = "cpu";
197 compatible = "qcom,kry 284 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 285 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw <<
200 enable-method = "psci" 286 enable-method = "psci";
201 capacity-dmips-mhz = < 287 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici 288 dynamic-power-coefficient = <442>;
203 qcom,freq-domain = <&c 289 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 290 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 291 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 292 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ 293 power-domains = <&CPU_PD4>;
208 power-domain-names = " 294 power-domain-names = "psci";
209 #cooling-cells = <2>; 295 #cooling-cells = <2>;
210 next-level-cache = <&L 296 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 297 L2_400: l2-cache {
212 compatible = " 298 compatible = "cache";
213 cache-level = <<
214 cache-unified; <<
215 next-level-cac 299 next-level-cache = <&L3_0>;
216 }; 300 };
217 }; 301 };
218 302
219 CPU5: cpu@500 { 303 CPU5: cpu@500 {
220 device_type = "cpu"; 304 device_type = "cpu";
221 compatible = "qcom,kry 305 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 306 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw <<
224 enable-method = "psci" 307 enable-method = "psci";
225 capacity-dmips-mhz = < 308 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici 309 dynamic-power-coefficient = <442>;
227 qcom,freq-domain = <&c 310 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 311 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 312 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 313 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ 314 power-domains = <&CPU_PD5>;
232 power-domain-names = " 315 power-domain-names = "psci";
233 #cooling-cells = <2>; 316 #cooling-cells = <2>;
234 next-level-cache = <&L 317 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 318 L2_500: l2-cache {
236 compatible = " 319 compatible = "cache";
237 cache-level = <<
238 cache-unified; <<
239 next-level-cac 320 next-level-cache = <&L3_0>;
240 }; 321 };
241 }; 322 };
242 323
243 CPU6: cpu@600 { 324 CPU6: cpu@600 {
244 device_type = "cpu"; 325 device_type = "cpu";
245 compatible = "qcom,kry 326 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 327 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw <<
248 enable-method = "psci" 328 enable-method = "psci";
249 capacity-dmips-mhz = < 329 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici 330 dynamic-power-coefficient = <442>;
251 qcom,freq-domain = <&c 331 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 332 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 333 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 334 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ 335 power-domains = <&CPU_PD6>;
256 power-domain-names = " 336 power-domain-names = "psci";
257 #cooling-cells = <2>; 337 #cooling-cells = <2>;
258 next-level-cache = <&L 338 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 339 L2_600: l2-cache {
260 compatible = " 340 compatible = "cache";
261 cache-level = <<
262 cache-unified; <<
263 next-level-cac 341 next-level-cache = <&L3_0>;
264 }; 342 };
265 }; 343 };
266 344
267 CPU7: cpu@700 { 345 CPU7: cpu@700 {
268 device_type = "cpu"; 346 device_type = "cpu";
269 compatible = "qcom,kry 347 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 348 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw <<
272 enable-method = "psci" 349 enable-method = "psci";
273 capacity-dmips-mhz = < 350 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici 351 dynamic-power-coefficient = <442>;
275 qcom,freq-domain = <&c 352 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 353 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 354 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 355 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ 356 power-domains = <&CPU_PD7>;
280 power-domain-names = " 357 power-domain-names = "psci";
281 #cooling-cells = <2>; 358 #cooling-cells = <2>;
282 next-level-cache = <&L 359 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 360 L2_700: l2-cache {
284 compatible = " 361 compatible = "cache";
285 cache-level = <<
286 cache-unified; <<
287 next-level-cac 362 next-level-cache = <&L3_0>;
288 }; 363 };
289 }; 364 };
290 365
291 cpu-map { 366 cpu-map {
292 cluster0 { 367 cluster0 {
293 core0 { 368 core0 {
294 cpu = 369 cpu = <&CPU0>;
295 }; 370 };
296 371
297 core1 { 372 core1 {
298 cpu = 373 cpu = <&CPU1>;
299 }; 374 };
300 375
301 core2 { 376 core2 {
302 cpu = 377 cpu = <&CPU2>;
303 }; 378 };
304 379
305 core3 { 380 core3 {
306 cpu = 381 cpu = <&CPU3>;
307 }; 382 };
308 383
309 core4 { 384 core4 {
310 cpu = 385 cpu = <&CPU4>;
311 }; 386 };
312 387
313 core5 { 388 core5 {
314 cpu = 389 cpu = <&CPU5>;
315 }; 390 };
316 391
317 core6 { 392 core6 {
318 cpu = 393 cpu = <&CPU6>;
319 }; 394 };
320 395
321 core7 { 396 core7 {
322 cpu = 397 cpu = <&CPU7>;
323 }; 398 };
324 }; 399 };
325 }; 400 };
326 401
327 cpu_idle_states: idle-states { 402 cpu_idle_states: idle-states {
328 entry-method = "psci"; 403 entry-method = "psci";
329 404
330 LITTLE_CPU_SLEEP_0: cp 405 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 406 compatible = "arm,idle-state";
332 idle-state-nam 407 idle-state-name = "little-rail-power-collapse";
333 arm,psci-suspe 408 arm,psci-suspend-param = <0x40000004>;
334 entry-latency- 409 entry-latency-us = <350>;
335 exit-latency-u 410 exit-latency-us = <461>;
336 min-residency- 411 min-residency-us = <1890>;
337 local-timer-st 412 local-timer-stop;
338 }; 413 };
339 414
340 BIG_CPU_SLEEP_0: cpu-s 415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 compatible = " 416 compatible = "arm,idle-state";
342 idle-state-nam 417 idle-state-name = "big-rail-power-collapse";
343 arm,psci-suspe 418 arm,psci-suspend-param = <0x40000004>;
344 entry-latency- 419 entry-latency-us = <264>;
345 exit-latency-u 420 exit-latency-us = <621>;
346 min-residency- 421 min-residency-us = <952>;
347 local-timer-st 422 local-timer-stop;
348 }; 423 };
349 }; 424 };
350 425
351 domain-idle-states { 426 domain-idle-states {
352 CLUSTER_SLEEP_0: clust 427 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " 428 compatible = "domain-idle-state";
>> 429 idle-state-name = "cluster-power-collapse";
354 arm,psci-suspe 430 arm,psci-suspend-param = <0x4100c244>;
355 entry-latency- 431 entry-latency-us = <3263>;
356 exit-latency-u 432 exit-latency-us = <6562>;
357 min-residency- 433 min-residency-us = <9987>;
>> 434 local-timer-stop;
358 }; 435 };
359 }; 436 };
360 }; 437 };
361 438
362 firmware { <<
363 scm { <<
364 compatible = "qcom,scm <<
365 }; <<
366 }; <<
367 <<
368 memory@80000000 { <<
369 device_type = "memory"; <<
370 /* We expect the bootloader to <<
371 reg = <0 0x80000000 0 0>; <<
372 }; <<
373 <<
374 cpu0_opp_table: opp-table-cpu0 { 439 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points 440 compatible = "operating-points-v2";
376 opp-shared; 441 opp-shared;
377 442
378 cpu0_opp1: opp-300000000 { 443 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 444 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 445 opp-peak-kBps = <800000 4800000>;
381 }; 446 };
382 447
383 cpu0_opp2: opp-403200000 { 448 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 449 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 450 opp-peak-kBps = <800000 4800000>;
386 }; 451 };
387 452
388 cpu0_opp3: opp-480000000 { 453 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 454 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 455 opp-peak-kBps = <800000 6451200>;
391 }; 456 };
392 457
393 cpu0_opp4: opp-576000000 { 458 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 459 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 460 opp-peak-kBps = <800000 6451200>;
396 }; 461 };
397 462
398 cpu0_opp5: opp-652800000 { 463 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 464 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 465 opp-peak-kBps = <800000 7680000>;
401 }; 466 };
402 467
403 cpu0_opp6: opp-748800000 { 468 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 469 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 470 opp-peak-kBps = <1804000 9216000>;
406 }; 471 };
407 472
408 cpu0_opp7: opp-825600000 { 473 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 474 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 475 opp-peak-kBps = <1804000 9216000>;
411 }; 476 };
412 477
413 cpu0_opp8: opp-902400000 { 478 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 479 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 480 opp-peak-kBps = <1804000 10444800>;
416 }; 481 };
417 482
418 cpu0_opp9: opp-979200000 { 483 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 484 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 485 opp-peak-kBps = <1804000 11980800>;
421 }; 486 };
422 487
423 cpu0_opp10: opp-1056000000 { 488 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 489 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 490 opp-peak-kBps = <1804000 11980800>;
426 }; 491 };
427 492
428 cpu0_opp11: opp-1132800000 { 493 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 494 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 495 opp-peak-kBps = <2188000 13516800>;
431 }; 496 };
432 497
433 cpu0_opp12: opp-1228800000 { 498 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 499 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 500 opp-peak-kBps = <2188000 15052800>;
436 }; 501 };
437 502
438 cpu0_opp13: opp-1324800000 { 503 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 504 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 505 opp-peak-kBps = <2188000 16588800>;
441 }; 506 };
442 507
443 cpu0_opp14: opp-1420800000 { 508 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 509 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 510 opp-peak-kBps = <3072000 18124800>;
446 }; 511 };
447 512
448 cpu0_opp15: opp-1516800000 { 513 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 514 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 515 opp-peak-kBps = <3072000 19353600>;
451 }; 516 };
452 517
453 cpu0_opp16: opp-1612800000 { 518 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 519 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 520 opp-peak-kBps = <4068000 19353600>;
456 }; 521 };
457 522
458 cpu0_opp17: opp-1689600000 { 523 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 524 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 525 opp-peak-kBps = <4068000 20889600>;
461 }; 526 };
462 527
463 cpu0_opp18: opp-1766400000 { 528 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 529 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 530 opp-peak-kBps = <4068000 22425600>;
466 }; 531 };
467 }; 532 };
468 533
469 cpu4_opp_table: opp-table-cpu4 { 534 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 535 compatible = "operating-points-v2";
471 opp-shared; 536 opp-shared;
472 537
473 cpu4_opp1: opp-300000000 { 538 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 539 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 540 opp-peak-kBps = <800000 4800000>;
476 }; 541 };
477 542
478 cpu4_opp2: opp-403200000 { 543 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 544 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 545 opp-peak-kBps = <800000 4800000>;
481 }; 546 };
482 547
483 cpu4_opp3: opp-480000000 { 548 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 549 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 550 opp-peak-kBps = <1804000 4800000>;
486 }; 551 };
487 552
488 cpu4_opp4: opp-576000000 { 553 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 554 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 555 opp-peak-kBps = <1804000 4800000>;
491 }; 556 };
492 557
493 cpu4_opp5: opp-652800000 { 558 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 559 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 560 opp-peak-kBps = <1804000 4800000>;
496 }; 561 };
497 562
498 cpu4_opp6: opp-748800000 { 563 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 564 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 565 opp-peak-kBps = <1804000 4800000>;
501 }; 566 };
502 567
503 cpu4_opp7: opp-825600000 { 568 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 569 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 570 opp-peak-kBps = <2188000 9216000>;
506 }; 571 };
507 572
508 cpu4_opp8: opp-902400000 { 573 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 574 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 575 opp-peak-kBps = <2188000 9216000>;
511 }; 576 };
512 577
513 cpu4_opp9: opp-979200000 { 578 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 579 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 580 opp-peak-kBps = <2188000 9216000>;
516 }; 581 };
517 582
518 cpu4_opp10: opp-1056000000 { 583 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 584 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 585 opp-peak-kBps = <3072000 9216000>;
521 }; 586 };
522 587
523 cpu4_opp11: opp-1132800000 { 588 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 589 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 590 opp-peak-kBps = <3072000 11980800>;
526 }; 591 };
527 592
528 cpu4_opp12: opp-1209600000 { 593 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 594 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 595 opp-peak-kBps = <4068000 11980800>;
531 }; 596 };
532 597
533 cpu4_opp13: opp-1286400000 { 598 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 599 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 600 opp-peak-kBps = <4068000 11980800>;
536 }; 601 };
537 602
538 cpu4_opp14: opp-1363200000 { 603 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 604 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 605 opp-peak-kBps = <4068000 15052800>;
541 }; 606 };
542 607
543 cpu4_opp15: opp-1459200000 { 608 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 609 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 610 opp-peak-kBps = <4068000 15052800>;
546 }; 611 };
547 612
548 cpu4_opp16: opp-1536000000 { 613 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 614 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 615 opp-peak-kBps = <5412000 15052800>;
551 }; 616 };
552 617
553 cpu4_opp17: opp-1612800000 { 618 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 619 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 620 opp-peak-kBps = <5412000 15052800>;
556 }; 621 };
557 622
558 cpu4_opp18: opp-1689600000 { 623 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 624 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 625 opp-peak-kBps = <5412000 19353600>;
561 }; 626 };
562 627
563 cpu4_opp19: opp-1766400000 { 628 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 629 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 630 opp-peak-kBps = <6220000 19353600>;
566 }; 631 };
567 632
568 cpu4_opp20: opp-1843200000 { 633 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 634 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 635 opp-peak-kBps = <6220000 19353600>;
571 }; 636 };
572 637
573 cpu4_opp21: opp-1920000000 { 638 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 639 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 640 opp-peak-kBps = <7216000 19353600>;
576 }; 641 };
577 642
578 cpu4_opp22: opp-1996800000 { 643 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 644 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 645 opp-peak-kBps = <7216000 20889600>;
581 }; 646 };
582 647
583 cpu4_opp23: opp-2092800000 { 648 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 649 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 650 opp-peak-kBps = <7216000 20889600>;
586 }; 651 };
587 652
588 cpu4_opp24: opp-2169600000 { 653 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 654 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 655 opp-peak-kBps = <7216000 20889600>;
591 }; 656 };
592 657
593 cpu4_opp25: opp-2246400000 { 658 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 659 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 660 opp-peak-kBps = <7216000 20889600>;
596 }; 661 };
597 662
598 cpu4_opp26: opp-2323200000 { 663 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 664 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 665 opp-peak-kBps = <7216000 20889600>;
601 }; 666 };
602 667
603 cpu4_opp27: opp-2400000000 { 668 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 669 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 670 opp-peak-kBps = <7216000 22425600>;
606 }; 671 };
607 672
608 cpu4_opp28: opp-2476800000 { 673 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 674 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 675 opp-peak-kBps = <7216000 22425600>;
611 }; 676 };
612 677
613 cpu4_opp29: opp-2553600000 { 678 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 679 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 680 opp-peak-kBps = <7216000 22425600>;
616 }; 681 };
617 682
618 cpu4_opp30: opp-2649600000 { 683 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 684 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 685 opp-peak-kBps = <7216000 22425600>;
621 }; 686 };
622 687
623 cpu4_opp31: opp-2745600000 { 688 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 689 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 690 opp-peak-kBps = <7216000 25497600>;
626 }; 691 };
627 692
628 cpu4_opp32: opp-2803200000 { 693 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 694 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 695 opp-peak-kBps = <7216000 25497600>;
631 }; 696 };
632 }; 697 };
633 698
634 dsi_opp_table: opp-table-dsi { <<
635 compatible = "operating-points <<
636 <<
637 opp-19200000 { <<
638 opp-hz = /bits/ 64 <19 <<
639 required-opps = <&rpmh <<
640 }; <<
641 <<
642 opp-180000000 { <<
643 opp-hz = /bits/ 64 <18 <<
644 required-opps = <&rpmh <<
645 }; <<
646 <<
647 opp-275000000 { <<
648 opp-hz = /bits/ 64 <27 <<
649 required-opps = <&rpmh <<
650 }; <<
651 <<
652 opp-328580000 { <<
653 opp-hz = /bits/ 64 <32 <<
654 required-opps = <&rpmh <<
655 }; <<
656 <<
657 opp-358000000 { <<
658 opp-hz = /bits/ 64 <35 <<
659 required-opps = <&rpmh <<
660 }; <<
661 }; <<
662 <<
663 qspi_opp_table: opp-table-qspi { <<
664 compatible = "operating-points <<
665 <<
666 opp-19200000 { <<
667 opp-hz = /bits/ 64 <19 <<
668 required-opps = <&rpmh <<
669 }; <<
670 <<
671 opp-100000000 { <<
672 opp-hz = /bits/ 64 <10 <<
673 required-opps = <&rpmh <<
674 }; <<
675 <<
676 opp-150000000 { <<
677 opp-hz = /bits/ 64 <15 <<
678 required-opps = <&rpmh <<
679 }; <<
680 <<
681 opp-300000000 { <<
682 opp-hz = /bits/ 64 <30 <<
683 required-opps = <&rpmh <<
684 }; <<
685 }; <<
686 <<
687 qup_opp_table: opp-table-qup { <<
688 compatible = "operating-points <<
689 <<
690 opp-50000000 { <<
691 opp-hz = /bits/ 64 <50 <<
692 required-opps = <&rpmh <<
693 }; <<
694 <<
695 opp-75000000 { <<
696 opp-hz = /bits/ 64 <75 <<
697 required-opps = <&rpmh <<
698 }; <<
699 <<
700 opp-100000000 { <<
701 opp-hz = /bits/ 64 <10 <<
702 required-opps = <&rpmh <<
703 }; <<
704 <<
705 opp-128000000 { <<
706 opp-hz = /bits/ 64 <12 <<
707 required-opps = <&rpmh <<
708 }; <<
709 }; <<
710 <<
711 pmu { 699 pmu {
712 compatible = "arm,armv8-pmuv3" 700 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 701 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 702 };
715 703
716 psci: psci { !! 704 timer {
717 compatible = "arm,psci-1.0"; !! 705 compatible = "arm,armv8-timer";
718 method = "smc"; !! 706 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
719 !! 707 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
720 CPU_PD0: power-domain-cpu0 { !! 708 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
721 #power-domain-cells = !! 709 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
722 power-domains = <&CLUS <<
723 domain-idle-states = < <<
724 }; <<
725 <<
726 CPU_PD1: power-domain-cpu1 { <<
727 #power-domain-cells = <<
728 power-domains = <&CLUS <<
729 domain-idle-states = < <<
730 }; <<
731 <<
732 CPU_PD2: power-domain-cpu2 { <<
733 #power-domain-cells = <<
734 power-domains = <&CLUS <<
735 domain-idle-states = < <<
736 }; <<
737 <<
738 CPU_PD3: power-domain-cpu3 { <<
739 #power-domain-cells = <<
740 power-domains = <&CLUS <<
741 domain-idle-states = < <<
742 }; <<
743 <<
744 CPU_PD4: power-domain-cpu4 { <<
745 #power-domain-cells = <<
746 power-domains = <&CLUS <<
747 domain-idle-states = < <<
748 }; <<
749 <<
750 CPU_PD5: power-domain-cpu5 { <<
751 #power-domain-cells = <<
752 power-domains = <&CLUS <<
753 domain-idle-states = < <<
754 }; <<
755 <<
756 CPU_PD6: power-domain-cpu6 { <<
757 #power-domain-cells = <<
758 power-domains = <&CLUS <<
759 domain-idle-states = < <<
760 }; <<
761 <<
762 CPU_PD7: power-domain-cpu7 { <<
763 #power-domain-cells = <<
764 power-domains = <&CLUS <<
765 domain-idle-states = < <<
766 }; <<
767 <<
768 CLUSTER_PD: power-domain-clust <<
769 #power-domain-cells = <<
770 domain-idle-states = < <<
771 }; <<
772 }; 710 };
773 711
774 reserved-memory { !! 712 clocks {
775 #address-cells = <2>; !! 713 xo_board: xo-board {
776 #size-cells = <2>; !! 714 compatible = "fixed-clock";
777 ranges; !! 715 #clock-cells = <0>;
778 !! 716 clock-frequency = <38400000>;
779 hyp_mem: hyp-mem@85700000 { !! 717 clock-output-names = "xo_board";
780 reg = <0 0x85700000 0 <<
781 no-map; <<
782 }; <<
783 <<
784 xbl_mem: xbl-mem@85e00000 { <<
785 reg = <0 0x85e00000 0 <<
786 no-map; <<
787 }; <<
788 <<
789 aop_mem: aop-mem@85fc0000 { <<
790 reg = <0 0x85fc0000 0 <<
791 no-map; <<
792 }; <<
793 <<
794 aop_cmd_db_mem: aop-cmd-db-mem <<
795 compatible = "qcom,cmd <<
796 reg = <0x0 0x85fe0000 <<
797 no-map; <<
798 }; <<
799 <<
800 smem@86000000 { <<
801 compatible = "qcom,sme <<
802 reg = <0x0 0x86000000 <<
803 no-map; <<
804 hwlocks = <&tcsr_mutex <<
805 }; <<
806 <<
807 tz_mem: tz@86200000 { <<
808 reg = <0 0x86200000 0 <<
809 no-map; <<
810 }; <<
811 <<
812 rmtfs_mem: rmtfs@88f00000 { <<
813 compatible = "qcom,rmt <<
814 reg = <0 0x88f00000 0 <<
815 no-map; <<
816 <<
817 qcom,client-id = <1>; <<
818 qcom,vmid = <QCOM_SCM_ <<
819 }; <<
820 <<
821 qseecom_mem: qseecom@8ab00000 <<
822 reg = <0 0x8ab00000 0 <<
823 no-map; <<
824 }; <<
825 <<
826 camera_mem: camera-mem@8bf0000 <<
827 reg = <0 0x8bf00000 0 <<
828 no-map; <<
829 }; <<
830 <<
831 ipa_fw_mem: ipa-fw@8c400000 { <<
832 reg = <0 0x8c400000 0 <<
833 no-map; <<
834 }; <<
835 <<
836 ipa_gsi_mem: ipa-gsi@8c410000 <<
837 reg = <0 0x8c410000 0 <<
838 no-map; <<
839 }; <<
840 <<
841 gpu_mem: gpu@8c415000 { <<
842 reg = <0 0x8c415000 0 <<
843 no-map; <<
844 }; <<
845 <<
846 adsp_mem: adsp@8c500000 { <<
847 reg = <0 0x8c500000 0 <<
848 no-map; <<
849 }; <<
850 <<
851 wlan_msa_mem: wlan-msa@8df0000 <<
852 reg = <0 0x8df00000 0 <<
853 no-map; <<
854 }; <<
855 <<
856 mpss_region: mpss@8e000000 { <<
857 reg = <0 0x8e000000 0 <<
858 no-map; <<
859 }; <<
860 <<
861 venus_mem: venus@95800000 { <<
862 reg = <0 0x95800000 0 <<
863 no-map; <<
864 }; <<
865 <<
866 cdsp_mem: cdsp@95d00000 { <<
867 reg = <0 0x95d00000 0 <<
868 no-map; <<
869 }; <<
870 <<
871 mba_region: mba@96500000 { <<
872 reg = <0 0x96500000 0 <<
873 no-map; <<
874 }; <<
875 <<
876 slpi_mem: slpi@96700000 { <<
877 reg = <0 0x96700000 0 <<
878 no-map; <<
879 }; <<
880 <<
881 spss_mem: spss@97b00000 { <<
882 reg = <0 0x97b00000 0 <<
883 no-map; <<
884 }; 718 };
885 719
886 mdata_mem: mpss-metadata { !! 720 sleep_clk: sleep-clk {
887 alloc-ranges = <0 0xa0 !! 721 compatible = "fixed-clock";
888 size = <0 0x4000>; !! 722 #clock-cells = <0>;
889 no-map; !! 723 clock-frequency = <32764>;
890 }; 724 };
>> 725 };
891 726
892 fastrpc_mem: fastrpc { !! 727 firmware {
893 compatible = "shared-d !! 728 scm {
894 alloc-ranges = <0x0 0x !! 729 compatible = "qcom,scm-sdm845", "qcom,scm";
895 alignment = <0x0 0x400 <<
896 size = <0x0 0x1000000> <<
897 reusable; <<
898 }; 730 };
899 }; 731 };
900 732
901 adsp_pas: remoteproc-adsp { 733 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 734 compatible = "qcom,sdm845-adsp-pas";
903 735
904 interrupts-extended = <&intc G 736 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 737 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 738 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 739 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 740 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 741 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 742 "handover", "stop-ack";
911 743
912 clocks = <&rpmhcc RPMH_CXO_CLK 744 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 745 clock-names = "xo";
914 746
915 memory-region = <&adsp_mem>; 747 memory-region = <&adsp_mem>;
916 748
917 qcom,qmp = <&aoss_qmp>; 749 qcom,qmp = <&aoss_qmp>;
918 750
919 qcom,smem-states = <&adsp_smp2 751 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 752 qcom,smem-state-names = "stop";
921 753
922 status = "disabled"; 754 status = "disabled";
923 755
924 glink-edge { 756 glink-edge {
925 interrupts = <GIC_SPI 757 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 758 label = "lpass";
927 qcom,remote-pid = <2>; 759 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 760 mboxes = <&apss_shared 8>;
929 761
930 apr { 762 apr {
931 compatible = " 763 compatible = "qcom,apr-v2";
932 qcom,glink-cha 764 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = 765 qcom,domain = <APR_DOMAIN_ADSP>;
934 #address-cells 766 #address-cells = <1>;
935 #size-cells = 767 #size-cells = <0>;
936 qcom,intents = 768 qcom,intents = <512 20>;
937 769
938 service@3 { 770 service@3 {
939 reg = 771 reg = <APR_SVC_ADSP_CORE>;
940 compat 772 compatible = "qcom,q6core";
941 qcom,p 773 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 774 };
943 775
944 q6afe: service 776 q6afe: service@4 {
945 compat 777 compatible = "qcom,q6afe";
946 reg = 778 reg = <APR_SVC_AFE>;
947 qcom,p 779 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 780 q6afedai: dais {
949 781 compatible = "qcom,q6afe-dais";
950 782 #address-cells = <1>;
951 783 #size-cells = <0>;
952 784 #sound-dai-cells = <1>;
953 }; 785 };
954 }; 786 };
955 787
956 q6asm: service 788 q6asm: service@7 {
957 compat 789 compatible = "qcom,q6asm";
958 reg = 790 reg = <APR_SVC_ASM>;
959 qcom,p 791 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 792 q6asmdai: dais {
961 793 compatible = "qcom,q6asm-dais";
962 794 #address-cells = <1>;
963 795 #size-cells = <0>;
964 796 #sound-dai-cells = <1>;
965 797 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 798 };
967 }; 799 };
968 800
969 q6adm: service 801 q6adm: service@8 {
970 compat 802 compatible = "qcom,q6adm";
971 reg = 803 reg = <APR_SVC_ADM>;
972 qcom,p 804 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 805 q6routing: routing {
974 806 compatible = "qcom,q6adm-routing";
975 807 #sound-dai-cells = <0>;
976 }; 808 };
977 }; 809 };
978 }; 810 };
979 811
980 fastrpc { 812 fastrpc {
981 compatible = " 813 compatible = "qcom,fastrpc";
982 qcom,glink-cha 814 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 815 label = "adsp";
984 qcom,non-secur 816 qcom,non-secure-domain;
985 #address-cells 817 #address-cells = <1>;
986 #size-cells = 818 #size-cells = <0>;
987 819
988 compute-cb@3 { 820 compute-cb@3 {
989 compat 821 compatible = "qcom,fastrpc-compute-cb";
990 reg = 822 reg = <3>;
991 iommus 823 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 824 };
993 825
994 compute-cb@4 { 826 compute-cb@4 {
995 compat 827 compatible = "qcom,fastrpc-compute-cb";
996 reg = 828 reg = <4>;
997 iommus 829 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 830 };
999 }; 831 };
1000 }; 832 };
1001 }; 833 };
1002 834
1003 cdsp_pas: remoteproc-cdsp { 835 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 836 compatible = "qcom,sdm845-cdsp-pas";
1005 837
1006 interrupts-extended = <&intc 838 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 839 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 840 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 841 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 842 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 843 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 844 "handover", "stop-ack";
1013 845
1014 clocks = <&rpmhcc RPMH_CXO_CL 846 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 847 clock-names = "xo";
1016 848
1017 memory-region = <&cdsp_mem>; 849 memory-region = <&cdsp_mem>;
1018 850
1019 qcom,qmp = <&aoss_qmp>; 851 qcom,qmp = <&aoss_qmp>;
1020 852
1021 qcom,smem-states = <&cdsp_smp 853 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 854 qcom,smem-state-names = "stop";
1023 855
1024 status = "disabled"; 856 status = "disabled";
1025 857
1026 glink-edge { 858 glink-edge {
1027 interrupts = <GIC_SPI 859 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 860 label = "turing";
1029 qcom,remote-pid = <5> 861 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 862 mboxes = <&apss_shared 4>;
1031 fastrpc { 863 fastrpc {
1032 compatible = 864 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 865 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 866 label = "cdsp";
1035 qcom,non-secu 867 qcom,non-secure-domain;
1036 #address-cell 868 #address-cells = <1>;
1037 #size-cells = 869 #size-cells = <0>;
1038 870
1039 compute-cb@1 871 compute-cb@1 {
1040 compa 872 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 873 reg = <1>;
1042 iommu 874 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 875 };
1044 876
1045 compute-cb@2 877 compute-cb@2 {
1046 compa 878 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 879 reg = <2>;
1048 iommu 880 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 881 };
1050 882
1051 compute-cb@3 883 compute-cb@3 {
1052 compa 884 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 885 reg = <3>;
1054 iommu 886 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 887 };
1056 888
1057 compute-cb@4 889 compute-cb@4 {
1058 compa 890 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 891 reg = <4>;
1060 iommu 892 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 893 };
1062 894
1063 compute-cb@5 895 compute-cb@5 {
1064 compa 896 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 897 reg = <5>;
1066 iommu 898 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 899 };
1068 900
1069 compute-cb@6 901 compute-cb@6 {
1070 compa 902 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 903 reg = <6>;
1072 iommu 904 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 905 };
1074 906
1075 compute-cb@7 907 compute-cb@7 {
1076 compa 908 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 909 reg = <7>;
1078 iommu 910 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 911 };
1080 912
1081 compute-cb@8 913 compute-cb@8 {
1082 compa 914 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 915 reg = <8>;
1084 iommu 916 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 917 };
1086 }; 918 };
1087 }; 919 };
1088 }; 920 };
1089 921
1090 smp2p-cdsp { 922 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 923 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 924 qcom,smem = <94>, <432>;
1093 925
1094 interrupts = <GIC_SPI 576 IRQ 926 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 927
1096 mboxes = <&apss_shared 6>; 928 mboxes = <&apss_shared 6>;
1097 929
1098 qcom,local-pid = <0>; 930 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 931 qcom,remote-pid = <5>;
1100 932
1101 cdsp_smp2p_out: master-kernel 933 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 934 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 935 #qcom,smem-state-cells = <1>;
1104 }; 936 };
1105 937
1106 cdsp_smp2p_in: slave-kernel { 938 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 939 qcom,entry-name = "slave-kernel";
1108 940
1109 interrupt-controller; 941 interrupt-controller;
1110 #interrupt-cells = <2 942 #interrupt-cells = <2>;
1111 }; 943 };
1112 }; 944 };
1113 945
1114 smp2p-lpass { 946 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 947 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 948 qcom,smem = <443>, <429>;
1117 949
1118 interrupts = <GIC_SPI 158 IRQ 950 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 951
1120 mboxes = <&apss_shared 10>; 952 mboxes = <&apss_shared 10>;
1121 953
1122 qcom,local-pid = <0>; 954 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 955 qcom,remote-pid = <2>;
1124 956
1125 adsp_smp2p_out: master-kernel 957 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 958 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 959 #qcom,smem-state-cells = <1>;
1128 }; 960 };
1129 961
1130 adsp_smp2p_in: slave-kernel { 962 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 963 qcom,entry-name = "slave-kernel";
1132 964
1133 interrupt-controller; 965 interrupt-controller;
1134 #interrupt-cells = <2 966 #interrupt-cells = <2>;
1135 }; 967 };
1136 }; 968 };
1137 969
1138 smp2p-mpss { 970 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 971 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 972 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 973 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 974 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 975 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 976 qcom,remote-pid = <1>;
1145 977
1146 modem_smp2p_out: master-kerne 978 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 979 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 980 #qcom,smem-state-cells = <1>;
1149 }; 981 };
1150 982
1151 modem_smp2p_in: slave-kernel 983 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 984 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 985 interrupt-controller;
1154 #interrupt-cells = <2 986 #interrupt-cells = <2>;
1155 }; 987 };
1156 988
1157 ipa_smp2p_out: ipa-ap-to-mode 989 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 990 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 991 #qcom,smem-state-cells = <1>;
1160 }; 992 };
1161 993
1162 ipa_smp2p_in: ipa-modem-to-ap 994 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 995 qcom,entry-name = "ipa";
1164 interrupt-controller; 996 interrupt-controller;
1165 #interrupt-cells = <2 997 #interrupt-cells = <2>;
1166 }; 998 };
1167 }; 999 };
1168 1000
1169 smp2p-slpi { 1001 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1002 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1003 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1004 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1005 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1006 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1007 qcom,remote-pid = <3>;
1176 1008
1177 slpi_smp2p_out: master-kernel 1009 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1010 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1011 #qcom,smem-state-cells = <1>;
1180 }; 1012 };
1181 1013
1182 slpi_smp2p_in: slave-kernel { 1014 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1015 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1016 interrupt-controller;
1185 #interrupt-cells = <2 1017 #interrupt-cells = <2>;
1186 }; 1018 };
1187 }; 1019 };
1188 1020
>> 1021 psci: psci {
>> 1022 compatible = "arm,psci-1.0";
>> 1023 method = "smc";
>> 1024
>> 1025 CPU_PD0: power-domain-cpu0 {
>> 1026 #power-domain-cells = <0>;
>> 1027 power-domains = <&CLUSTER_PD>;
>> 1028 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1029 };
>> 1030
>> 1031 CPU_PD1: power-domain-cpu1 {
>> 1032 #power-domain-cells = <0>;
>> 1033 power-domains = <&CLUSTER_PD>;
>> 1034 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1035 };
>> 1036
>> 1037 CPU_PD2: power-domain-cpu2 {
>> 1038 #power-domain-cells = <0>;
>> 1039 power-domains = <&CLUSTER_PD>;
>> 1040 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1041 };
>> 1042
>> 1043 CPU_PD3: power-domain-cpu3 {
>> 1044 #power-domain-cells = <0>;
>> 1045 power-domains = <&CLUSTER_PD>;
>> 1046 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
>> 1047 };
>> 1048
>> 1049 CPU_PD4: power-domain-cpu4 {
>> 1050 #power-domain-cells = <0>;
>> 1051 power-domains = <&CLUSTER_PD>;
>> 1052 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1053 };
>> 1054
>> 1055 CPU_PD5: power-domain-cpu5 {
>> 1056 #power-domain-cells = <0>;
>> 1057 power-domains = <&CLUSTER_PD>;
>> 1058 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1059 };
>> 1060
>> 1061 CPU_PD6: power-domain-cpu6 {
>> 1062 #power-domain-cells = <0>;
>> 1063 power-domains = <&CLUSTER_PD>;
>> 1064 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1065 };
>> 1066
>> 1067 CPU_PD7: power-domain-cpu7 {
>> 1068 #power-domain-cells = <0>;
>> 1069 power-domains = <&CLUSTER_PD>;
>> 1070 domain-idle-states = <&BIG_CPU_SLEEP_0>;
>> 1071 };
>> 1072
>> 1073 CLUSTER_PD: power-domain-cluster {
>> 1074 #power-domain-cells = <0>;
>> 1075 domain-idle-states = <&CLUSTER_SLEEP_0>;
>> 1076 };
>> 1077 };
>> 1078
1189 soc: soc@0 { 1079 soc: soc@0 {
1190 #address-cells = <2>; 1080 #address-cells = <2>;
1191 #size-cells = <2>; 1081 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1082 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1083 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1084 compatible = "simple-bus";
1195 1085
1196 gcc: clock-controller@100000 1086 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1087 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1088 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1089 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1090 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1091 <&sleep_clk>,
1202 <&pcie0_phy> !! 1092 <&pcie0_lane>,
1203 <&pcie1_phy> !! 1093 <&pcie1_lane>;
1204 clock-names = "bi_tcx 1094 clock-names = "bi_tcxo",
1205 "bi_tcx 1095 "bi_tcxo_ao",
1206 "sleep_ 1096 "sleep_clk",
1207 "pcie_0 1097 "pcie_0_pipe_clk",
1208 "pcie_1 1098 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1099 #clock-cells = <1>;
1210 #reset-cells = <1>; 1100 #reset-cells = <1>;
1211 #power-domain-cells = 1101 #power-domain-cells = <1>;
1212 power-domains = <&rpm <<
1213 }; 1102 };
1214 1103
1215 qfprom@784000 { 1104 qfprom@784000 {
1216 compatible = "qcom,sd 1105 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 reg = <0 0x00784000 0 1106 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1107 #address-cells = <1>;
1219 #size-cells = <1>; 1108 #size-cells = <1>;
1220 1109
1221 qusb2p_hstx_trim: hst 1110 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1111 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1112 bits = <1 4>;
1224 }; 1113 };
1225 1114
1226 qusb2s_hstx_trim: hst 1115 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1116 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1117 bits = <6 4>;
1229 }; 1118 };
1230 }; 1119 };
1231 1120
1232 rng: rng@793000 { 1121 rng: rng@793000 {
1233 compatible = "qcom,pr 1122 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1123 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1124 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1125 clock-names = "core";
1237 }; 1126 };
1238 1127
>> 1128 qup_opp_table: opp-table-qup {
>> 1129 compatible = "operating-points-v2";
>> 1130
>> 1131 opp-50000000 {
>> 1132 opp-hz = /bits/ 64 <50000000>;
>> 1133 required-opps = <&rpmhpd_opp_min_svs>;
>> 1134 };
>> 1135
>> 1136 opp-75000000 {
>> 1137 opp-hz = /bits/ 64 <75000000>;
>> 1138 required-opps = <&rpmhpd_opp_low_svs>;
>> 1139 };
>> 1140
>> 1141 opp-100000000 {
>> 1142 opp-hz = /bits/ 64 <100000000>;
>> 1143 required-opps = <&rpmhpd_opp_svs>;
>> 1144 };
>> 1145
>> 1146 opp-128000000 {
>> 1147 opp-hz = /bits/ 64 <128000000>;
>> 1148 required-opps = <&rpmhpd_opp_nom>;
>> 1149 };
>> 1150 };
>> 1151
1239 gpi_dma0: dma-controller@8000 1152 gpi_dma0: dma-controller@800000 {
1240 #dma-cells = <3>; 1153 #dma-cells = <3>;
1241 compatible = "qcom,sd 1154 compatible = "qcom,sdm845-gpi-dma";
1242 reg = <0 0x00800000 0 1155 reg = <0 0x00800000 0 0x60000>;
1243 interrupts = <GIC_SPI 1156 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 1157 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 1158 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 1159 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 1160 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 1161 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 1162 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 1163 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 1164 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 1165 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 1166 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 1167 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 1168 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256 dma-channels = <13>; 1169 dma-channels = <13>;
1257 dma-channel-mask = <0 1170 dma-channel-mask = <0xfa>;
1258 iommus = <&apps_smmu 1171 iommus = <&apps_smmu 0x0016 0x0>;
1259 status = "disabled"; 1172 status = "disabled";
1260 }; 1173 };
1261 1174
1262 qupv3_id_0: geniqup@8c0000 { 1175 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1176 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1177 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1178 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1179 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1180 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1181 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1182 #address-cells = <2>;
1270 #size-cells = <2>; 1183 #size-cells = <2>;
1271 ranges; 1184 ranges;
1272 interconnects = <&agg 1185 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1186 interconnect-names = "qup-core";
1274 status = "disabled"; 1187 status = "disabled";
1275 1188
1276 i2c0: i2c@880000 { 1189 i2c0: i2c@880000 {
1277 compatible = 1190 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1191 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1192 clock-names = "se";
1280 clocks = <&gc 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1194 pinctrl-names = "default";
1282 pinctrl-0 = < 1195 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1196 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1197 #address-cells = <1>;
1285 #size-cells = 1198 #size-cells = <0>;
1286 power-domains 1199 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1200 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1201 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1202 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1203 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1204 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ 1205 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293 <&gpi_ 1206 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1294 dma-names = " 1207 dma-names = "tx", "rx";
1295 status = "dis 1208 status = "disabled";
1296 }; 1209 };
1297 1210
1298 spi0: spi@880000 { 1211 spi0: spi@880000 {
1299 compatible = 1212 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1213 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1214 clock-names = "se";
1302 clocks = <&gc 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1216 pinctrl-names = "default";
1304 pinctrl-0 = < 1217 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1218 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1219 #address-cells = <1>;
1307 #size-cells = 1220 #size-cells = <0>;
1308 interconnects 1221 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1222 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1223 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ 1224 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_ 1225 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313 dma-names = " 1226 dma-names = "tx", "rx";
1314 status = "dis 1227 status = "disabled";
1315 }; 1228 };
1316 1229
1317 uart0: serial@880000 1230 uart0: serial@880000 {
1318 compatible = 1231 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1232 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1233 clock-names = "se";
1321 clocks = <&gc 1234 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1235 pinctrl-names = "default";
1323 pinctrl-0 = < 1236 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1237 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1238 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1239 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1240 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1241 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1242 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1243 status = "disabled";
1331 }; 1244 };
1332 1245
1333 i2c1: i2c@884000 { 1246 i2c1: i2c@884000 {
1334 compatible = 1247 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1248 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1249 clock-names = "se";
1337 clocks = <&gc 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1251 pinctrl-names = "default";
1339 pinctrl-0 = < 1252 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1253 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1254 #address-cells = <1>;
1342 #size-cells = 1255 #size-cells = <0>;
1343 power-domains 1256 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1257 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1258 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1259 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1260 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1261 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ 1262 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1350 <&gpi_ 1263 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1351 dma-names = " 1264 dma-names = "tx", "rx";
1352 status = "dis 1265 status = "disabled";
1353 }; 1266 };
1354 1267
1355 spi1: spi@884000 { 1268 spi1: spi@884000 {
1356 compatible = 1269 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1270 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1271 clock-names = "se";
1359 clocks = <&gc 1272 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1273 pinctrl-names = "default";
1361 pinctrl-0 = < 1274 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1275 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1276 #address-cells = <1>;
1364 #size-cells = 1277 #size-cells = <0>;
1365 interconnects 1278 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1279 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1280 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ 1281 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1369 <&gpi_ 1282 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1370 dma-names = " 1283 dma-names = "tx", "rx";
1371 status = "dis 1284 status = "disabled";
1372 }; 1285 };
1373 1286
1374 uart1: serial@884000 1287 uart1: serial@884000 {
1375 compatible = 1288 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1289 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1290 clock-names = "se";
1378 clocks = <&gc 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1292 pinctrl-names = "default";
1380 pinctrl-0 = < 1293 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1294 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1295 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1296 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1297 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1298 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1299 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1300 status = "disabled";
1388 }; 1301 };
1389 1302
1390 i2c2: i2c@888000 { 1303 i2c2: i2c@888000 {
1391 compatible = 1304 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1305 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1306 clock-names = "se";
1394 clocks = <&gc 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1308 pinctrl-names = "default";
1396 pinctrl-0 = < 1309 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1310 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1311 #address-cells = <1>;
1399 #size-cells = 1312 #size-cells = <0>;
1400 power-domains 1313 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1314 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1315 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1316 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1317 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1318 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ 1319 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1407 <&gpi_ 1320 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1408 dma-names = " 1321 dma-names = "tx", "rx";
1409 status = "dis 1322 status = "disabled";
1410 }; 1323 };
1411 1324
1412 spi2: spi@888000 { 1325 spi2: spi@888000 {
1413 compatible = 1326 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1327 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1328 clock-names = "se";
1416 clocks = <&gc 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1330 pinctrl-names = "default";
1418 pinctrl-0 = < 1331 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1332 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1333 #address-cells = <1>;
1421 #size-cells = 1334 #size-cells = <0>;
1422 interconnects 1335 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1336 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1337 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ 1338 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1426 <&gpi_ 1339 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1427 dma-names = " 1340 dma-names = "tx", "rx";
1428 status = "dis 1341 status = "disabled";
1429 }; 1342 };
1430 1343
1431 uart2: serial@888000 1344 uart2: serial@888000 {
1432 compatible = 1345 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1346 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1347 clock-names = "se";
1435 clocks = <&gc 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1349 pinctrl-names = "default";
1437 pinctrl-0 = < 1350 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1351 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1352 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1353 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1354 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1355 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1356 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1357 status = "disabled";
1445 }; 1358 };
1446 1359
1447 i2c3: i2c@88c000 { 1360 i2c3: i2c@88c000 {
1448 compatible = 1361 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1362 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1363 clock-names = "se";
1451 clocks = <&gc 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1365 pinctrl-names = "default";
1453 pinctrl-0 = < 1366 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1367 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1368 #address-cells = <1>;
1456 #size-cells = 1369 #size-cells = <0>;
1457 power-domains 1370 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1371 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1372 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1373 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1374 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1375 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ 1376 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1464 <&gpi_ 1377 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1465 dma-names = " 1378 dma-names = "tx", "rx";
1466 status = "dis 1379 status = "disabled";
1467 }; 1380 };
1468 1381
1469 spi3: spi@88c000 { 1382 spi3: spi@88c000 {
1470 compatible = 1383 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1384 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1385 clock-names = "se";
1473 clocks = <&gc 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1387 pinctrl-names = "default";
1475 pinctrl-0 = < 1388 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1389 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1390 #address-cells = <1>;
1478 #size-cells = 1391 #size-cells = <0>;
1479 interconnects 1392 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1393 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1394 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ 1395 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1483 <&gpi_ 1396 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1484 dma-names = " 1397 dma-names = "tx", "rx";
1485 status = "dis 1398 status = "disabled";
1486 }; 1399 };
1487 1400
1488 uart3: serial@88c000 1401 uart3: serial@88c000 {
1489 compatible = 1402 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1403 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1404 clock-names = "se";
1492 clocks = <&gc 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1406 pinctrl-names = "default";
1494 pinctrl-0 = < 1407 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1408 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1409 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1410 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1411 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1412 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1413 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1414 status = "disabled";
1502 }; 1415 };
1503 1416
1504 i2c4: i2c@890000 { 1417 i2c4: i2c@890000 {
1505 compatible = 1418 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1419 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1420 clock-names = "se";
1508 clocks = <&gc 1421 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1422 pinctrl-names = "default";
1510 pinctrl-0 = < 1423 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1424 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1425 #address-cells = <1>;
1513 #size-cells = 1426 #size-cells = <0>;
1514 power-domains 1427 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1428 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1429 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1430 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1431 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1432 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ 1433 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521 <&gpi_ 1434 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522 dma-names = " 1435 dma-names = "tx", "rx";
1523 status = "dis 1436 status = "disabled";
1524 }; 1437 };
1525 1438
1526 spi4: spi@890000 { 1439 spi4: spi@890000 {
1527 compatible = 1440 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1441 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1442 clock-names = "se";
1530 clocks = <&gc 1443 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1444 pinctrl-names = "default";
1532 pinctrl-0 = < 1445 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1446 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1447 #address-cells = <1>;
1535 #size-cells = 1448 #size-cells = <0>;
1536 interconnects 1449 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1450 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1451 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ 1452 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1540 <&gpi_ 1453 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1541 dma-names = " 1454 dma-names = "tx", "rx";
1542 status = "dis 1455 status = "disabled";
1543 }; 1456 };
1544 1457
1545 uart4: serial@890000 1458 uart4: serial@890000 {
1546 compatible = 1459 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1460 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1461 clock-names = "se";
1549 clocks = <&gc 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1463 pinctrl-names = "default";
1551 pinctrl-0 = < 1464 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1465 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1466 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1467 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1468 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1469 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1470 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1471 status = "disabled";
1559 }; 1472 };
1560 1473
1561 i2c5: i2c@894000 { 1474 i2c5: i2c@894000 {
1562 compatible = 1475 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1476 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1477 clock-names = "se";
1565 clocks = <&gc 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1479 pinctrl-names = "default";
1567 pinctrl-0 = < 1480 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1481 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1482 #address-cells = <1>;
1570 #size-cells = 1483 #size-cells = <0>;
1571 power-domains 1484 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1485 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1486 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1487 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1488 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ 1490 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1578 <&gpi_ 1491 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1579 dma-names = " 1492 dma-names = "tx", "rx";
1580 status = "dis 1493 status = "disabled";
1581 }; 1494 };
1582 1495
1583 spi5: spi@894000 { 1496 spi5: spi@894000 {
1584 compatible = 1497 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1498 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1499 clock-names = "se";
1587 clocks = <&gc 1500 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1501 pinctrl-names = "default";
1589 pinctrl-0 = < 1502 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1503 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1504 #address-cells = <1>;
1592 #size-cells = 1505 #size-cells = <0>;
1593 interconnects 1506 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1507 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1508 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ 1509 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1597 <&gpi_ 1510 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1598 dma-names = " 1511 dma-names = "tx", "rx";
1599 status = "dis 1512 status = "disabled";
1600 }; 1513 };
1601 1514
1602 uart5: serial@894000 1515 uart5: serial@894000 {
1603 compatible = 1516 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1517 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1518 clock-names = "se";
1606 clocks = <&gc 1519 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1520 pinctrl-names = "default";
1608 pinctrl-0 = < 1521 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1522 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1523 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1524 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1525 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1526 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1527 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1528 status = "disabled";
1616 }; 1529 };
1617 1530
1618 i2c6: i2c@898000 { 1531 i2c6: i2c@898000 {
1619 compatible = 1532 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1533 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1534 clock-names = "se";
1622 clocks = <&gc 1535 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1536 pinctrl-names = "default";
1624 pinctrl-0 = < 1537 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1538 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1539 #address-cells = <1>;
1627 #size-cells = 1540 #size-cells = <0>;
1628 power-domains 1541 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1542 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1543 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1544 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1545 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ 1547 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1635 <&gpi_ 1548 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1636 dma-names = " 1549 dma-names = "tx", "rx";
1637 status = "dis 1550 status = "disabled";
1638 }; 1551 };
1639 1552
1640 spi6: spi@898000 { 1553 spi6: spi@898000 {
1641 compatible = 1554 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1555 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1556 clock-names = "se";
1644 clocks = <&gc 1557 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1558 pinctrl-names = "default";
1646 pinctrl-0 = < 1559 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1560 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1561 #address-cells = <1>;
1649 #size-cells = 1562 #size-cells = <0>;
1650 interconnects 1563 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1564 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1565 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ 1566 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1654 <&gpi_ 1567 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1655 dma-names = " 1568 dma-names = "tx", "rx";
1656 status = "dis 1569 status = "disabled";
1657 }; 1570 };
1658 1571
1659 uart6: serial@898000 1572 uart6: serial@898000 {
1660 compatible = 1573 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1574 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1575 clock-names = "se";
1663 clocks = <&gc 1576 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1577 pinctrl-names = "default";
1665 pinctrl-0 = < 1578 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1579 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1580 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1581 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1582 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1583 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1584 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1585 status = "disabled";
1673 }; 1586 };
1674 1587
1675 i2c7: i2c@89c000 { 1588 i2c7: i2c@89c000 {
1676 compatible = 1589 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1590 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1591 clock-names = "se";
1679 clocks = <&gc 1592 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1593 pinctrl-names = "default";
1681 pinctrl-0 = < 1594 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1595 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1596 #address-cells = <1>;
1684 #size-cells = 1597 #size-cells = <0>;
1685 power-domains 1598 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1599 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1600 status = "disabled";
1688 }; 1601 };
1689 1602
1690 spi7: spi@89c000 { 1603 spi7: spi@89c000 {
1691 compatible = 1604 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1605 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1606 clock-names = "se";
1694 clocks = <&gc 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1608 pinctrl-names = "default";
1696 pinctrl-0 = < 1609 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1610 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1611 #address-cells = <1>;
1699 #size-cells = 1612 #size-cells = <0>;
1700 interconnects 1613 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1614 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1615 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ 1616 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1704 <&gpi_ 1617 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1705 dma-names = " 1618 dma-names = "tx", "rx";
1706 status = "dis 1619 status = "disabled";
1707 }; 1620 };
1708 1621
1709 uart7: serial@89c000 1622 uart7: serial@89c000 {
1710 compatible = 1623 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1624 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1625 clock-names = "se";
1713 clocks = <&gc 1626 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1627 pinctrl-names = "default";
1715 pinctrl-0 = < 1628 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1629 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1630 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1631 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1632 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1633 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1634 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1635 status = "disabled";
1723 }; 1636 };
1724 }; 1637 };
1725 1638
1726 gpi_dma1: dma-controller@a000 !! 1639 gpi_dma1: dma-controller@0xa00000 {
1727 #dma-cells = <3>; 1640 #dma-cells = <3>;
1728 compatible = "qcom,sd 1641 compatible = "qcom,sdm845-gpi-dma";
1729 reg = <0 0x00a00000 0 1642 reg = <0 0x00a00000 0 0x60000>;
1730 interrupts = <GIC_SPI 1643 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1644 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 1645 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 1646 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 1647 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 1648 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 1649 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1650 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1651 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1652 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1653 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1654 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1655 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743 dma-channels = <13>; 1656 dma-channels = <13>;
1744 dma-channel-mask = <0 1657 dma-channel-mask = <0xfa>;
1745 iommus = <&apps_smmu 1658 iommus = <&apps_smmu 0x06d6 0x0>;
1746 status = "disabled"; 1659 status = "disabled";
1747 }; 1660 };
1748 1661
1749 qupv3_id_1: geniqup@ac0000 { 1662 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1663 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1664 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1665 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1666 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1667 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1668 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1669 #address-cells = <2>;
1757 #size-cells = <2>; 1670 #size-cells = <2>;
1758 ranges; 1671 ranges;
1759 interconnects = <&agg 1672 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1673 interconnect-names = "qup-core";
1761 status = "disabled"; 1674 status = "disabled";
1762 1675
1763 i2c8: i2c@a80000 { 1676 i2c8: i2c@a80000 {
1764 compatible = 1677 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1678 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1679 clock-names = "se";
1767 clocks = <&gc 1680 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1681 pinctrl-names = "default";
1769 pinctrl-0 = < 1682 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1683 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1684 #address-cells = <1>;
1772 #size-cells = 1685 #size-cells = <0>;
1773 power-domains 1686 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1687 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1688 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1689 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1690 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1691 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ 1692 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780 <&gpi_ 1693 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1781 dma-names = " 1694 dma-names = "tx", "rx";
1782 status = "dis 1695 status = "disabled";
1783 }; 1696 };
1784 1697
1785 spi8: spi@a80000 { 1698 spi8: spi@a80000 {
1786 compatible = 1699 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1700 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1701 clock-names = "se";
1789 clocks = <&gc 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1703 pinctrl-names = "default";
1791 pinctrl-0 = < 1704 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1705 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1706 #address-cells = <1>;
1794 #size-cells = 1707 #size-cells = <0>;
1795 interconnects 1708 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1709 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1710 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ 1711 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799 <&gpi_ 1712 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1800 dma-names = " 1713 dma-names = "tx", "rx";
1801 status = "dis 1714 status = "disabled";
1802 }; 1715 };
1803 1716
1804 uart8: serial@a80000 1717 uart8: serial@a80000 {
1805 compatible = 1718 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1719 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1720 clock-names = "se";
1808 clocks = <&gc 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1722 pinctrl-names = "default";
1810 pinctrl-0 = < 1723 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1724 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1725 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1726 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1727 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1728 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1729 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1730 status = "disabled";
1818 }; 1731 };
1819 1732
1820 i2c9: i2c@a84000 { 1733 i2c9: i2c@a84000 {
1821 compatible = 1734 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1735 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1736 clock-names = "se";
1824 clocks = <&gc 1737 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1738 pinctrl-names = "default";
1826 pinctrl-0 = < 1739 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1740 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1741 #address-cells = <1>;
1829 #size-cells = 1742 #size-cells = <0>;
1830 power-domains 1743 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1744 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1745 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1746 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1747 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1748 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ 1749 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1837 <&gpi_ 1750 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1838 dma-names = " 1751 dma-names = "tx", "rx";
1839 status = "dis 1752 status = "disabled";
1840 }; 1753 };
1841 1754
1842 spi9: spi@a84000 { 1755 spi9: spi@a84000 {
1843 compatible = 1756 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1757 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1758 clock-names = "se";
1846 clocks = <&gc 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1760 pinctrl-names = "default";
1848 pinctrl-0 = < 1761 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1762 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1763 #address-cells = <1>;
1851 #size-cells = 1764 #size-cells = <0>;
1852 interconnects 1765 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1766 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1767 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ 1768 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1856 <&gpi_ 1769 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1857 dma-names = " 1770 dma-names = "tx", "rx";
1858 status = "dis 1771 status = "disabled";
1859 }; 1772 };
1860 1773
1861 uart9: serial@a84000 1774 uart9: serial@a84000 {
1862 compatible = 1775 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1776 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1777 clock-names = "se";
1865 clocks = <&gc 1778 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1779 pinctrl-names = "default";
1867 pinctrl-0 = < 1780 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1781 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1782 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1783 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1784 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1785 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1786 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1787 status = "disabled";
1875 }; 1788 };
1876 1789
1877 i2c10: i2c@a88000 { 1790 i2c10: i2c@a88000 {
1878 compatible = 1791 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1792 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1793 clock-names = "se";
1881 clocks = <&gc 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1795 pinctrl-names = "default";
1883 pinctrl-0 = < 1796 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1797 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1798 #address-cells = <1>;
1886 #size-cells = 1799 #size-cells = <0>;
1887 power-domains 1800 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1801 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1802 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1803 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1804 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1805 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ 1806 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1894 <&gpi_ 1807 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1895 dma-names = " 1808 dma-names = "tx", "rx";
1896 status = "dis 1809 status = "disabled";
1897 }; 1810 };
1898 1811
1899 spi10: spi@a88000 { 1812 spi10: spi@a88000 {
1900 compatible = 1813 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1814 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1815 clock-names = "se";
1903 clocks = <&gc 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1817 pinctrl-names = "default";
1905 pinctrl-0 = < 1818 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1819 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1820 #address-cells = <1>;
1908 #size-cells = 1821 #size-cells = <0>;
1909 interconnects 1822 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1823 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1824 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ 1825 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913 <&gpi_ 1826 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1914 dma-names = " 1827 dma-names = "tx", "rx";
1915 status = "dis 1828 status = "disabled";
1916 }; 1829 };
1917 1830
1918 uart10: serial@a88000 1831 uart10: serial@a88000 {
1919 compatible = 1832 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1833 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1834 clock-names = "se";
1922 clocks = <&gc 1835 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1836 pinctrl-names = "default";
1924 pinctrl-0 = < 1837 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1838 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1839 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1840 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1841 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1842 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1843 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1844 status = "disabled";
1932 }; 1845 };
1933 1846
1934 i2c11: i2c@a8c000 { 1847 i2c11: i2c@a8c000 {
1935 compatible = 1848 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1849 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1850 clock-names = "se";
1938 clocks = <&gc 1851 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1852 pinctrl-names = "default";
1940 pinctrl-0 = < 1853 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1854 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1855 #address-cells = <1>;
1943 #size-cells = 1856 #size-cells = <0>;
1944 power-domains 1857 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1858 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1859 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1860 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1861 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1862 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ 1863 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1951 <&gpi_ 1864 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1952 dma-names = " 1865 dma-names = "tx", "rx";
1953 status = "dis 1866 status = "disabled";
1954 }; 1867 };
1955 1868
1956 spi11: spi@a8c000 { 1869 spi11: spi@a8c000 {
1957 compatible = 1870 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1871 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1872 clock-names = "se";
1960 clocks = <&gc 1873 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1874 pinctrl-names = "default";
1962 pinctrl-0 = < 1875 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1876 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1877 #address-cells = <1>;
1965 #size-cells = 1878 #size-cells = <0>;
1966 interconnects 1879 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1880 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1881 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ 1882 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1970 <&gpi_ 1883 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1971 dma-names = " 1884 dma-names = "tx", "rx";
1972 status = "dis 1885 status = "disabled";
1973 }; 1886 };
1974 1887
1975 uart11: serial@a8c000 1888 uart11: serial@a8c000 {
1976 compatible = 1889 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1890 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1891 clock-names = "se";
1979 clocks = <&gc 1892 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1893 pinctrl-names = "default";
1981 pinctrl-0 = < 1894 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1895 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1896 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1897 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1898 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1899 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1900 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1901 status = "disabled";
1989 }; 1902 };
1990 1903
1991 i2c12: i2c@a90000 { 1904 i2c12: i2c@a90000 {
1992 compatible = 1905 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1906 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1907 clock-names = "se";
1995 clocks = <&gc 1908 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1909 pinctrl-names = "default";
1997 pinctrl-0 = < 1910 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1911 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1912 #address-cells = <1>;
2000 #size-cells = 1913 #size-cells = <0>;
2001 power-domains 1914 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 1915 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 1916 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 1917 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 1918 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 1919 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ 1920 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2008 <&gpi_ 1921 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2009 dma-names = " 1922 dma-names = "tx", "rx";
2010 status = "dis 1923 status = "disabled";
2011 }; 1924 };
2012 1925
2013 spi12: spi@a90000 { 1926 spi12: spi@a90000 {
2014 compatible = 1927 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 1928 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 1929 clock-names = "se";
2017 clocks = <&gc 1930 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1931 pinctrl-names = "default";
2019 pinctrl-0 = < 1932 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 1933 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 1934 #address-cells = <1>;
2022 #size-cells = 1935 #size-cells = <0>;
2023 interconnects 1936 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 1937 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 1938 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ 1939 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2027 <&gpi_ 1940 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2028 dma-names = " 1941 dma-names = "tx", "rx";
2029 status = "dis 1942 status = "disabled";
2030 }; 1943 };
2031 1944
2032 uart12: serial@a90000 1945 uart12: serial@a90000 {
2033 compatible = 1946 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 1947 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 1948 clock-names = "se";
2036 clocks = <&gc 1949 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 1950 pinctrl-names = "default";
2038 pinctrl-0 = < 1951 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 1952 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 1953 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 1954 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 1955 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 1956 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 1957 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 1958 status = "disabled";
2046 }; 1959 };
2047 1960
2048 i2c13: i2c@a94000 { 1961 i2c13: i2c@a94000 {
2049 compatible = 1962 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 1963 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 1964 clock-names = "se";
2052 clocks = <&gc 1965 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 1966 pinctrl-names = "default";
2054 pinctrl-0 = < 1967 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 1968 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 1969 #address-cells = <1>;
2057 #size-cells = 1970 #size-cells = <0>;
2058 power-domains 1971 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 1972 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 1973 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 1974 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 1975 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 1976 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ 1977 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2065 <&gpi_ 1978 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2066 dma-names = " 1979 dma-names = "tx", "rx";
2067 status = "dis 1980 status = "disabled";
2068 }; 1981 };
2069 1982
2070 spi13: spi@a94000 { 1983 spi13: spi@a94000 {
2071 compatible = 1984 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 1985 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 1986 clock-names = "se";
2074 clocks = <&gc 1987 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 1988 pinctrl-names = "default";
2076 pinctrl-0 = < 1989 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 1990 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 1991 #address-cells = <1>;
2079 #size-cells = 1992 #size-cells = <0>;
2080 interconnects 1993 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 1994 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 1995 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ 1996 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2084 <&gpi_ 1997 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2085 dma-names = " 1998 dma-names = "tx", "rx";
2086 status = "dis 1999 status = "disabled";
2087 }; 2000 };
2088 2001
2089 uart13: serial@a94000 2002 uart13: serial@a94000 {
2090 compatible = 2003 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 2004 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 2005 clock-names = "se";
2093 clocks = <&gc 2006 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 2007 pinctrl-names = "default";
2095 pinctrl-0 = < 2008 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 2009 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 2010 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 2011 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 2012 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 2013 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 2014 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 2015 status = "disabled";
2103 }; 2016 };
2104 2017
2105 i2c14: i2c@a98000 { 2018 i2c14: i2c@a98000 {
2106 compatible = 2019 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 2020 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 2021 clock-names = "se";
2109 clocks = <&gc 2022 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 2023 pinctrl-names = "default";
2111 pinctrl-0 = < 2024 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 2025 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 2026 #address-cells = <1>;
2114 #size-cells = 2027 #size-cells = <0>;
2115 power-domains 2028 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 2029 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 2030 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 2031 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 2032 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 2033 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ 2034 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2122 <&gpi_ 2035 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2123 dma-names = " 2036 dma-names = "tx", "rx";
2124 status = "dis 2037 status = "disabled";
2125 }; 2038 };
2126 2039
2127 spi14: spi@a98000 { 2040 spi14: spi@a98000 {
2128 compatible = 2041 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 2042 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 2043 clock-names = "se";
2131 clocks = <&gc 2044 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 2045 pinctrl-names = "default";
2133 pinctrl-0 = < 2046 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 2047 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 2048 #address-cells = <1>;
2136 #size-cells = 2049 #size-cells = <0>;
2137 interconnects 2050 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 2051 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 2052 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ 2053 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2141 <&gpi_ 2054 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2142 dma-names = " 2055 dma-names = "tx", "rx";
2143 status = "dis 2056 status = "disabled";
2144 }; 2057 };
2145 2058
2146 uart14: serial@a98000 2059 uart14: serial@a98000 {
2147 compatible = 2060 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 2061 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 2062 clock-names = "se";
2150 clocks = <&gc 2063 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 2064 pinctrl-names = "default";
2152 pinctrl-0 = < 2065 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 2066 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 2067 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 2068 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 2069 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 2070 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 2071 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 2072 status = "disabled";
2160 }; 2073 };
2161 2074
2162 i2c15: i2c@a9c000 { 2075 i2c15: i2c@a9c000 {
2163 compatible = 2076 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 2077 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 2078 clock-names = "se";
2166 clocks = <&gc 2079 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 2080 pinctrl-names = "default";
2168 pinctrl-0 = < 2081 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 2082 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 2083 #address-cells = <1>;
2171 #size-cells = 2084 #size-cells = <0>;
2172 power-domains 2085 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 2086 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 2087 status = "disabled";
2175 interconnects 2088 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 2089 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 2090 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 2091 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ 2092 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2180 <&gpi_ 2093 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2181 dma-names = " 2094 dma-names = "tx", "rx";
2182 }; 2095 };
2183 2096
2184 spi15: spi@a9c000 { 2097 spi15: spi@a9c000 {
2185 compatible = 2098 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 2099 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 2100 clock-names = "se";
2188 clocks = <&gc 2101 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 2102 pinctrl-names = "default";
2190 pinctrl-0 = < 2103 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 2104 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 2105 #address-cells = <1>;
2193 #size-cells = 2106 #size-cells = <0>;
2194 interconnects 2107 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 2108 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 2109 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ 2110 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2198 <&gpi_ 2111 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2199 dma-names = " 2112 dma-names = "tx", "rx";
2200 status = "dis 2113 status = "disabled";
2201 }; 2114 };
2202 2115
2203 uart15: serial@a9c000 2116 uart15: serial@a9c000 {
2204 compatible = 2117 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 2118 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 2119 clock-names = "se";
2207 clocks = <&gc 2120 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 2121 pinctrl-names = "default";
2209 pinctrl-0 = < 2122 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 2123 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 2124 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 2125 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 2126 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 2127 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 2128 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 2129 status = "disabled";
2217 }; 2130 };
2218 }; 2131 };
2219 2132
2220 llcc: system-cache-controller 2133 llcc: system-cache-controller@1100000 {
2221 compatible = "qcom,sd 2134 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 !! 2135 reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>;
2223 <0 0x01200000 0 !! 2136 reg-names = "llcc_base", "llcc_broadcast_base";
2224 <0 0x01300000 0 <<
2225 reg-names = "llcc0_ba <<
2226 "llcc3_ba <<
2227 interrupts = <GIC_SPI 2137 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 2138 };
2229 2139
2230 dma@10a2000 { <<
2231 compatible = "qcom,sd <<
2232 reg = <0x0 0x010a2000 <<
2233 <0x0 0x010ae000 <<
2234 }; <<
2235 <<
2236 pmu@114a000 { 2140 pmu@114a000 {
2237 compatible = "qcom,sd 2141 compatible = "qcom,sdm845-llcc-bwmon";
2238 reg = <0 0x0114a000 0 2142 reg = <0 0x0114a000 0 0x1000>;
2239 interrupts = <GIC_SPI 2143 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2240 interconnects = <&mem 2144 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2241 2145
2242 operating-points-v2 = 2146 operating-points-v2 = <&llcc_bwmon_opp_table>;
2243 2147
2244 llcc_bwmon_opp_table: 2148 llcc_bwmon_opp_table: opp-table {
2245 compatible = 2149 compatible = "operating-points-v2";
2246 2150
2247 /* 2151 /*
2248 * The interc 2152 * The interconnect path bandwidth taken from
2249 * cpu4_opp_t 2153 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2250 * interconne 2154 * interconnect. This also matches the
2251 * bandwidth 2155 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2252 * bus width: 2156 * bus width: 4 bytes) from msm-4.9 downstream
2253 * kernel. 2157 * kernel.
2254 */ 2158 */
2255 opp-0 { 2159 opp-0 {
2256 opp-p 2160 opp-peak-kBps = <800000>;
2257 }; 2161 };
2258 opp-1 { 2162 opp-1 {
2259 opp-p 2163 opp-peak-kBps = <1804000>;
2260 }; 2164 };
2261 opp-2 { 2165 opp-2 {
2262 opp-p 2166 opp-peak-kBps = <3072000>;
2263 }; 2167 };
2264 opp-3 { 2168 opp-3 {
2265 opp-p 2169 opp-peak-kBps = <5412000>;
2266 }; 2170 };
2267 opp-4 { 2171 opp-4 {
2268 opp-p 2172 opp-peak-kBps = <7216000>;
2269 }; 2173 };
2270 }; 2174 };
2271 }; 2175 };
2272 2176
2273 pmu@1436400 { 2177 pmu@1436400 {
2274 compatible = "qcom,sd !! 2178 compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
2275 reg = <0 0x01436400 0 2179 reg = <0 0x01436400 0 0x600>;
2276 interrupts = <GIC_SPI 2180 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2277 interconnects = <&gla 2181 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278 2182
2279 operating-points-v2 = 2183 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 2184
2281 cpu_bwmon_opp_table: 2185 cpu_bwmon_opp_table: opp-table {
2282 compatible = 2186 compatible = "operating-points-v2";
2283 2187
2284 /* 2188 /*
2285 * The interc 2189 * The interconnect path bandwidth taken from
2286 * cpu4_opp_t 2190 * cpu4_opp_table bandwidth for OSM L3
2287 * interconne 2191 * interconnect. This also matches the OSM L3
2288 * from bandw 2192 * from bandwidth table of qcom,cpu4-l3lat-mon
2289 * (qcom,core 2193 * (qcom,core-dev-table, bus width: 16 bytes)
2290 * from msm-4 2194 * from msm-4.9 downstream kernel.
2291 */ 2195 */
2292 opp-0 { 2196 opp-0 {
2293 opp-p 2197 opp-peak-kBps = <4800000>;
2294 }; 2198 };
2295 opp-1 { 2199 opp-1 {
2296 opp-p 2200 opp-peak-kBps = <9216000>;
2297 }; 2201 };
2298 opp-2 { 2202 opp-2 {
2299 opp-p 2203 opp-peak-kBps = <15052800>;
2300 }; 2204 };
2301 opp-3 { 2205 opp-3 {
2302 opp-p 2206 opp-peak-kBps = <20889600>;
2303 }; 2207 };
2304 opp-4 { 2208 opp-4 {
2305 opp-p 2209 opp-peak-kBps = <25497600>;
2306 }; 2210 };
2307 }; 2211 };
2308 }; 2212 };
2309 2213
2310 pcie0: pcie@1c00000 { !! 2214 pcie0: pci@1c00000 {
2311 compatible = "qcom,pc 2215 compatible = "qcom,pcie-sdm845";
2312 reg = <0 0x01c00000 0 2216 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 2217 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 2218 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 !! 2219 <0 0x60100000 0 0x100000>;
2316 <0 0x01c07000 0 !! 2220 reg-names = "parf", "dbi", "elbi", "config";
2317 reg-names = "parf", " <<
2318 device_type = "pci"; 2221 device_type = "pci";
2319 linux,pci-domain = <0 2222 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 2223 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 2224 num-lanes = <1>;
2322 2225
2323 #address-cells = <3>; 2226 #address-cells = <3>;
2324 #size-cells = <2>; 2227 #size-cells = <2>;
2325 2228
2326 ranges = <0x01000000 2229 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2327 <0x02000000 2230 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2328 2231
2329 interrupts = <GIC_SPI 2232 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 2233 interrupt-names = "msi";
2331 #interrupt-cells = <1 2234 #interrupt-cells = <1>;
2332 interrupt-map-mask = 2235 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 2236 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 2237 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 2238 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 2239 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2240
2338 clocks = <&gcc GCC_PC 2241 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2242 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2243 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2244 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2245 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2246 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2247 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2248 clock-names = "pipe",
2346 "aux", 2249 "aux",
2347 "cfg", 2250 "cfg",
2348 "bus_ma 2251 "bus_master",
2349 "bus_sl 2252 "bus_slave",
2350 "slave_ 2253 "slave_q2a",
2351 "tbu"; 2254 "tbu";
2352 2255
>> 2256 iommus = <&apps_smmu 0x1c10 0xf>;
2353 iommu-map = <0x0 &a 2257 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2258 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2259 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2260 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2261 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2262 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2263 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2264 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2265 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2266 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2267 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2268 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2269 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2270 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2271 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2272 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2273
2370 resets = <&gcc GCC_PC 2274 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2275 reset-names = "pci";
2372 2276
2373 power-domains = <&gcc 2277 power-domains = <&gcc PCIE_0_GDSC>;
2374 2278
2375 phys = <&pcie0_phy>; !! 2279 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2280 phy-names = "pciephy";
2377 2281
2378 status = "disabled"; 2282 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2283 };
2390 2284
2391 pcie0_phy: phy@1c06000 { 2285 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2286 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2287 reg = <0 0x01c06000 0 0x18c>;
>> 2288 #address-cells = <2>;
>> 2289 #size-cells = <2>;
>> 2290 ranges;
2394 clocks = <&gcc GCC_PC 2291 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2292 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2293 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2294 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2295 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2296
2410 resets = <&gcc GCC_PC 2297 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2298 reset-names = "phy";
2412 2299
2413 assigned-clocks = <&g 2300 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2301 assigned-clock-rates = <100000000>;
2415 2302
2416 status = "disabled"; 2303 status = "disabled";
>> 2304
>> 2305 pcie0_lane: phy@1c06200 {
>> 2306 reg = <0 0x01c06200 0 0x128>,
>> 2307 <0 0x01c06400 0 0x1fc>,
>> 2308 <0 0x01c06800 0 0x218>,
>> 2309 <0 0x01c06600 0 0x70>;
>> 2310 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2311 clock-names = "pipe0";
>> 2312
>> 2313 #clock-cells = <0>;
>> 2314 #phy-cells = <0>;
>> 2315 clock-output-names = "pcie_0_pipe_clk";
>> 2316 };
2417 }; 2317 };
2418 2318
2419 pcie1: pcie@1c08000 { !! 2319 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc 2320 compatible = "qcom,pcie-sdm845";
2421 reg = <0 0x01c08000 0 2321 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2322 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2323 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 !! 2324 <0 0x40100000 0 0x100000>;
2425 <0 0x01c0c000 0 !! 2325 reg-names = "parf", "dbi", "elbi", "config";
2426 reg-names = "parf", " <<
2427 device_type = "pci"; 2326 device_type = "pci";
2428 linux,pci-domain = <1 2327 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2328 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2329 num-lanes = <1>;
2431 2330
2432 #address-cells = <3>; 2331 #address-cells = <3>;
2433 #size-cells = <2>; 2332 #size-cells = <2>;
2434 2333
2435 ranges = <0x01000000 2334 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2335 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2336
2438 interrupts = <GIC_SPI 2337 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2338 interrupt-names = "msi";
2440 #interrupt-cells = <1 2339 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2340 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 2341 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 2342 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 2343 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 2344 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2345
2447 clocks = <&gcc GCC_PC 2346 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2347 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2348 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2349 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2350 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2351 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2352 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2353 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2354 clock-names = "pipe",
2456 "aux", 2355 "aux",
2457 "cfg", 2356 "cfg",
2458 "bus_ma 2357 "bus_master",
2459 "bus_sl 2358 "bus_slave",
2460 "slave_ 2359 "slave_q2a",
2461 "ref", 2360 "ref",
2462 "tbu"; 2361 "tbu";
2463 2362
2464 assigned-clocks = <&g 2363 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2364 assigned-clock-rates = <19200000>;
2466 2365
>> 2366 iommus = <&apps_smmu 0x1c00 0xf>;
2467 iommu-map = <0x0 &a 2367 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2368 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2369 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2370 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2371 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2372 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2373 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2374 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2375 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2376 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2377 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2378 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2379 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2380 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2381 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2382 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2383
2484 resets = <&gcc GCC_PC 2384 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2385 reset-names = "pci";
2486 2386
2487 power-domains = <&gcc 2387 power-domains = <&gcc PCIE_1_GDSC>;
2488 2388
2489 phys = <&pcie1_phy>; !! 2389 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2390 phy-names = "pciephy";
2491 2391
2492 status = "disabled"; 2392 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2393 };
2504 2394
2505 pcie1_phy: phy@1c0a000 { 2395 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2396 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2397 reg = <0 0x01c0a000 0 0x800>;
>> 2398 #address-cells = <2>;
>> 2399 #size-cells = <2>;
>> 2400 ranges;
2508 clocks = <&gcc GCC_PC 2401 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2402 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2403 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2404 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2405 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2406
2524 resets = <&gcc GCC_PC 2407 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2408 reset-names = "phy";
2526 2409
2527 assigned-clocks = <&g 2410 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2411 assigned-clock-rates = <100000000>;
2529 2412
2530 status = "disabled"; 2413 status = "disabled";
>> 2414
>> 2415 pcie1_lane: phy@1c06200 {
>> 2416 reg = <0 0x01c0a800 0 0x800>,
>> 2417 <0 0x01c0a800 0 0x800>,
>> 2418 <0 0x01c0b800 0 0x400>;
>> 2419 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2420 clock-names = "pipe0";
>> 2421
>> 2422 #clock-cells = <0>;
>> 2423 #phy-cells = <0>;
>> 2424 clock-output-names = "pcie_1_pipe_clk";
>> 2425 };
2531 }; 2426 };
2532 2427
2533 mem_noc: interconnect@1380000 2428 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2429 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2430 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2431 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2432 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2433 };
2539 2434
2540 dc_noc: interconnect@14e0000 2435 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2436 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2437 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2438 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2439 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2440 };
2546 2441
2547 config_noc: interconnect@1500 2442 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2443 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2444 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2445 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2446 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2447 };
2553 2448
2554 system_noc: interconnect@1620 2449 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2450 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2451 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2452 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2453 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2454 };
2560 2455
2561 aggre1_noc: interconnect@16e0 2456 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2457 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2458 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2459 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2460 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2461 };
2567 2462
2568 aggre2_noc: interconnect@1700 2463 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2464 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2465 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2466 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2467 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2468 };
2574 2469
2575 mmss_noc: interconnect@174000 2470 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2471 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2472 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2473 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2474 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2475 };
2581 2476
2582 ufs_mem_hc: ufshc@1d84000 { 2477 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2478 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2479 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2480 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2481 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2482 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2483 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2484 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2485 phy-names = "ufsphy";
2591 lanes-per-direction = 2486 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2487 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2488 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2489 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2490 reset-names = "rst";
2596 2491
2597 iommus = <&apps_smmu 2492 iommus = <&apps_smmu 0x100 0xf>;
2598 2493
2599 clock-names = 2494 clock-names =
2600 "core_clk", 2495 "core_clk",
2601 "bus_aggr_clk 2496 "bus_aggr_clk",
2602 "iface_clk", 2497 "iface_clk",
2603 "core_clk_uni 2498 "core_clk_unipro",
2604 "ref_clk", 2499 "ref_clk",
2605 "tx_lane0_syn 2500 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2501 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2502 "rx_lane1_sync_clk",
2608 "ice_core_clk 2503 "ice_core_clk";
2609 clocks = 2504 clocks =
2610 <&gcc GCC_UFS 2505 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2506 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2507 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2508 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2509 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2510 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2511 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2512 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2513 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2514 freq-table-hz =
2620 operating-points-v2 = !! 2515 <50000000 200000000>,
2621 !! 2516 <0 0>,
2622 interconnects = <&agg !! 2517 <0 0>,
2623 <&gla !! 2518 <37500000 150000000>,
2624 interconnect-names = !! 2519 <0 0>,
>> 2520 <0 0>,
>> 2521 <0 0>,
>> 2522 <0 0>,
>> 2523 <0 300000000>;
2625 2524
2626 status = "disabled"; 2525 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2526 };
2658 2527
2659 ufs_mem_phy: phy@1d87000 { 2528 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2529 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2530 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2531 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2532 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2533 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2534 clock-names = "ref",
2667 "ref_au !! 2535 "ref_aux";
2668 "qref"; !! 2536 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2537 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2538
2672 resets = <&ufs_mem_hc 2539 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2540 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2541 status = "disabled";
>> 2542
>> 2543 ufs_mem_phy_lanes: phy@1d87400 {
>> 2544 reg = <0 0x01d87400 0 0x108>,
>> 2545 <0 0x01d87600 0 0x1e0>,
>> 2546 <0 0x01d87c00 0 0x1dc>,
>> 2547 <0 0x01d87800 0 0x108>,
>> 2548 <0 0x01d87a00 0 0x1e0>;
>> 2549 #phy-cells = <0>;
>> 2550 };
2677 }; 2551 };
2678 2552
2679 cryptobam: dma-controller@1dc 2553 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,ba !! 2554 compatible = "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2555 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2556 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2557 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2558 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2559 #dma-cells = <1>;
2686 qcom,ee = <0>; 2560 qcom,ee = <0>;
2687 qcom,controlled-remot 2561 qcom,controlled-remotely;
2688 iommus = <&apps_smmu 2562 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2563 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2564 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2565 <&apps_smmu 0x716 0x1>;
2692 }; 2566 };
2693 2567
2694 crypto: crypto@1dfa000 { 2568 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2569 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2570 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2571 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2572 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2573 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2574 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2575 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2576 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2577 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2578 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2579 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2580 <&apps_smmu 0x716 0x1>;
2707 }; 2581 };
2708 2582
2709 ipa: ipa@1e40000 { 2583 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2584 compatible = "qcom,sdm845-ipa";
2711 2585
2712 iommus = <&apps_smmu 2586 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2587 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 !! 2588 reg = <0 0x1e40000 0 0x7000>,
2715 <0 0x01e47000 0 !! 2589 <0 0x1e47000 0 0x2000>,
2716 <0 0x01e04000 0 !! 2590 <0 0x1e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2591 reg-names = "ipa-reg",
2718 "ipa-shar 2592 "ipa-shared",
2719 "gsi"; 2593 "gsi";
2720 2594
2721 interrupts-extended = 2595 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2596 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2597 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2598 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2599 interrupt-names = "ipa",
2726 "gs 2600 "gsi",
2727 "ip 2601 "ipa-clock-query",
2728 "ip 2602 "ipa-setup-ready";
2729 2603
2730 clocks = <&rpmhcc RPM 2604 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2605 clock-names = "core";
2732 2606
2733 interconnects = <&agg 2607 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2608 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2609 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2610 interconnect-names = "memory",
2737 2611 "imem",
2738 2612 "config";
2739 2613
2740 qcom,smem-states = <& 2614 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2615 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2616 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2617 "ipa-clock-enabled";
2744 2618
2745 status = "disabled"; 2619 status = "disabled";
2746 }; 2620 };
2747 2621
2748 tcsr_mutex: hwlock@1f40000 { 2622 tcsr_mutex: hwlock@1f40000 {
2749 compatible = "qcom,tc 2623 compatible = "qcom,tcsr-mutex";
2750 reg = <0 0x01f40000 0 2624 reg = <0 0x01f40000 0 0x20000>;
2751 #hwlock-cells = <1>; 2625 #hwlock-cells = <1>;
2752 }; 2626 };
2753 2627
2754 tcsr_regs_1: syscon@1f60000 { 2628 tcsr_regs_1: syscon@1f60000 {
2755 compatible = "qcom,sd 2629 compatible = "qcom,sdm845-tcsr", "syscon";
2756 reg = <0 0x01f60000 0 2630 reg = <0 0x01f60000 0 0x20000>;
2757 }; 2631 };
2758 2632
2759 tlmm: pinctrl@3400000 { 2633 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2634 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2635 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2636 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2637 gpio-controller;
2764 #gpio-cells = <2>; 2638 #gpio-cells = <2>;
2765 interrupt-controller; 2639 interrupt-controller;
2766 #interrupt-cells = <2 2640 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2641 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2642 wakeup-parent = <&pdc_intc>;
2769 2643
2770 cci0_default: cci0-de !! 2644 cci0_default: cci0-default {
2771 /* SDA, SCL * 2645 /* SDA, SCL */
2772 pins = "gpio1 2646 pins = "gpio17", "gpio18";
2773 function = "c 2647 function = "cci_i2c";
2774 2648
2775 bias-pull-up; 2649 bias-pull-up;
2776 drive-strengt 2650 drive-strength = <2>; /* 2 mA */
2777 }; 2651 };
2778 2652
2779 cci0_sleep: cci0-slee !! 2653 cci0_sleep: cci0-sleep {
2780 /* SDA, SCL * 2654 /* SDA, SCL */
2781 pins = "gpio1 2655 pins = "gpio17", "gpio18";
2782 function = "c 2656 function = "cci_i2c";
2783 2657
2784 drive-strengt 2658 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2659 bias-pull-down;
2786 }; 2660 };
2787 2661
2788 cci1_default: cci1-de !! 2662 cci1_default: cci1-default {
2789 /* SDA, SCL * 2663 /* SDA, SCL */
2790 pins = "gpio1 2664 pins = "gpio19", "gpio20";
2791 function = "c 2665 function = "cci_i2c";
2792 2666
2793 bias-pull-up; 2667 bias-pull-up;
2794 drive-strengt 2668 drive-strength = <2>; /* 2 mA */
2795 }; 2669 };
2796 2670
2797 cci1_sleep: cci1-slee !! 2671 cci1_sleep: cci1-sleep {
2798 /* SDA, SCL * 2672 /* SDA, SCL */
2799 pins = "gpio1 2673 pins = "gpio19", "gpio20";
2800 function = "c 2674 function = "cci_i2c";
2801 2675
2802 drive-strengt 2676 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2677 bias-pull-down;
2804 }; 2678 };
2805 2679
2806 qspi_clk: qspi-clk-st !! 2680 qspi_clk: qspi-clk {
2807 pins = "gpio9 !! 2681 pinmux {
2808 function = "q !! 2682 pins = "gpio95";
2809 }; !! 2683 function = "qspi_clk";
2810 !! 2684 };
2811 qspi_cs0: qspi-cs0-st <<
2812 pins = "gpio9 <<
2813 function = "q <<
2814 }; 2685 };
2815 2686
2816 qspi_cs1: qspi-cs1-st !! 2687 qspi_cs0: qspi-cs0 {
2817 pins = "gpio8 !! 2688 pinmux {
2818 function = "q !! 2689 pins = "gpio90";
>> 2690 function = "qspi_cs";
>> 2691 };
2819 }; 2692 };
2820 2693
2821 qspi_data0: qspi-data !! 2694 qspi_cs1: qspi-cs1 {
2822 pins = "gpio9 !! 2695 pinmux {
2823 function = "q !! 2696 pins = "gpio89";
>> 2697 function = "qspi_cs";
>> 2698 };
2824 }; 2699 };
2825 2700
2826 qspi_data1: qspi-data !! 2701 qspi_data01: qspi-data01 {
2827 pins = "gpio9 !! 2702 pinmux-data {
2828 function = "q !! 2703 pins = "gpio91", "gpio92";
>> 2704 function = "qspi_data";
>> 2705 };
2829 }; 2706 };
2830 2707
2831 qspi_data23: qspi-dat !! 2708 qspi_data23: qspi-data23 {
2832 pins = "gpio9 !! 2709 pinmux-data {
2833 function = "q !! 2710 pins = "gpio93", "gpio94";
>> 2711 function = "qspi_data";
>> 2712 };
2834 }; 2713 };
2835 2714
2836 qup_i2c0_default: qup !! 2715 qup_i2c0_default: qup-i2c0-default {
2837 pins = "gpio0 !! 2716 pinmux {
2838 function = "q !! 2717 pins = "gpio0", "gpio1";
>> 2718 function = "qup0";
>> 2719 };
2839 }; 2720 };
2840 2721
2841 qup_i2c1_default: qup !! 2722 qup_i2c1_default: qup-i2c1-default {
2842 pins = "gpio1 !! 2723 pinmux {
2843 function = "q !! 2724 pins = "gpio17", "gpio18";
>> 2725 function = "qup1";
>> 2726 };
2844 }; 2727 };
2845 2728
2846 qup_i2c2_default: qup !! 2729 qup_i2c2_default: qup-i2c2-default {
2847 pins = "gpio2 !! 2730 pinmux {
2848 function = "q !! 2731 pins = "gpio27", "gpio28";
>> 2732 function = "qup2";
>> 2733 };
2849 }; 2734 };
2850 2735
2851 qup_i2c3_default: qup !! 2736 qup_i2c3_default: qup-i2c3-default {
2852 pins = "gpio4 !! 2737 pinmux {
2853 function = "q !! 2738 pins = "gpio41", "gpio42";
>> 2739 function = "qup3";
>> 2740 };
2854 }; 2741 };
2855 2742
2856 qup_i2c4_default: qup !! 2743 qup_i2c4_default: qup-i2c4-default {
2857 pins = "gpio8 !! 2744 pinmux {
2858 function = "q !! 2745 pins = "gpio89", "gpio90";
>> 2746 function = "qup4";
>> 2747 };
2859 }; 2748 };
2860 2749
2861 qup_i2c5_default: qup !! 2750 qup_i2c5_default: qup-i2c5-default {
2862 pins = "gpio8 !! 2751 pinmux {
2863 function = "q !! 2752 pins = "gpio85", "gpio86";
>> 2753 function = "qup5";
>> 2754 };
2864 }; 2755 };
2865 2756
2866 qup_i2c6_default: qup !! 2757 qup_i2c6_default: qup-i2c6-default {
2867 pins = "gpio4 !! 2758 pinmux {
2868 function = "q !! 2759 pins = "gpio45", "gpio46";
>> 2760 function = "qup6";
>> 2761 };
2869 }; 2762 };
2870 2763
2871 qup_i2c7_default: qup !! 2764 qup_i2c7_default: qup-i2c7-default {
2872 pins = "gpio9 !! 2765 pinmux {
2873 function = "q !! 2766 pins = "gpio93", "gpio94";
>> 2767 function = "qup7";
>> 2768 };
2874 }; 2769 };
2875 2770
2876 qup_i2c8_default: qup !! 2771 qup_i2c8_default: qup-i2c8-default {
2877 pins = "gpio6 !! 2772 pinmux {
2878 function = "q !! 2773 pins = "gpio65", "gpio66";
>> 2774 function = "qup8";
>> 2775 };
2879 }; 2776 };
2880 2777
2881 qup_i2c9_default: qup !! 2778 qup_i2c9_default: qup-i2c9-default {
2882 pins = "gpio6 !! 2779 pinmux {
2883 function = "q !! 2780 pins = "gpio6", "gpio7";
>> 2781 function = "qup9";
>> 2782 };
2884 }; 2783 };
2885 2784
2886 qup_i2c10_default: qu !! 2785 qup_i2c10_default: qup-i2c10-default {
2887 pins = "gpio5 !! 2786 pinmux {
2888 function = "q !! 2787 pins = "gpio55", "gpio56";
>> 2788 function = "qup10";
>> 2789 };
2889 }; 2790 };
2890 2791
2891 qup_i2c11_default: qu !! 2792 qup_i2c11_default: qup-i2c11-default {
2892 pins = "gpio3 !! 2793 pinmux {
2893 function = "q !! 2794 pins = "gpio31", "gpio32";
>> 2795 function = "qup11";
>> 2796 };
2894 }; 2797 };
2895 2798
2896 qup_i2c12_default: qu !! 2799 qup_i2c12_default: qup-i2c12-default {
2897 pins = "gpio4 !! 2800 pinmux {
2898 function = "q !! 2801 pins = "gpio49", "gpio50";
>> 2802 function = "qup12";
>> 2803 };
2899 }; 2804 };
2900 2805
2901 qup_i2c13_default: qu !! 2806 qup_i2c13_default: qup-i2c13-default {
2902 pins = "gpio1 !! 2807 pinmux {
2903 function = "q !! 2808 pins = "gpio105", "gpio106";
>> 2809 function = "qup13";
>> 2810 };
2904 }; 2811 };
2905 2812
2906 qup_i2c14_default: qu !! 2813 qup_i2c14_default: qup-i2c14-default {
2907 pins = "gpio3 !! 2814 pinmux {
2908 function = "q !! 2815 pins = "gpio33", "gpio34";
>> 2816 function = "qup14";
>> 2817 };
2909 }; 2818 };
2910 2819
2911 qup_i2c15_default: qu !! 2820 qup_i2c15_default: qup-i2c15-default {
2912 pins = "gpio8 !! 2821 pinmux {
2913 function = "q !! 2822 pins = "gpio81", "gpio82";
>> 2823 function = "qup15";
>> 2824 };
2914 }; 2825 };
2915 2826
2916 qup_spi0_default: qup !! 2827 qup_spi0_default: qup-spi0-default {
2917 pins = "gpio0 !! 2828 pinmux {
2918 function = "q !! 2829 pins = "gpio0", "gpio1",
2919 }; !! 2830 "gpio2", "gpio3";
>> 2831 function = "qup0";
>> 2832 };
2920 2833
2921 qup_spi1_default: qup !! 2834 config {
2922 pins = "gpio1 !! 2835 pins = "gpio0", "gpio1",
2923 function = "q !! 2836 "gpio2", "gpio3";
>> 2837 drive-strength = <6>;
>> 2838 bias-disable;
>> 2839 };
2924 }; 2840 };
2925 2841
2926 qup_spi2_default: qup !! 2842 qup_spi1_default: qup-spi1-default {
2927 pins = "gpio2 !! 2843 pinmux {
2928 function = "q !! 2844 pins = "gpio17", "gpio18",
>> 2845 "gpio19", "gpio20";
>> 2846 function = "qup1";
>> 2847 };
2929 }; 2848 };
2930 2849
2931 qup_spi3_default: qup !! 2850 qup_spi2_default: qup-spi2-default {
2932 pins = "gpio4 !! 2851 pinmux {
2933 function = "q !! 2852 pins = "gpio27", "gpio28",
>> 2853 "gpio29", "gpio30";
>> 2854 function = "qup2";
>> 2855 };
2934 }; 2856 };
2935 2857
2936 qup_spi4_default: qup !! 2858 qup_spi3_default: qup-spi3-default {
2937 pins = "gpio8 !! 2859 pinmux {
2938 function = "q !! 2860 pins = "gpio41", "gpio42",
>> 2861 "gpio43", "gpio44";
>> 2862 function = "qup3";
>> 2863 };
2939 }; 2864 };
2940 2865
2941 qup_spi5_default: qup !! 2866 qup_spi4_default: qup-spi4-default {
2942 pins = "gpio8 !! 2867 pinmux {
2943 function = "q !! 2868 pins = "gpio89", "gpio90",
>> 2869 "gpio91", "gpio92";
>> 2870 function = "qup4";
>> 2871 };
2944 }; 2872 };
2945 2873
2946 qup_spi6_default: qup !! 2874 qup_spi5_default: qup-spi5-default {
2947 pins = "gpio4 !! 2875 pinmux {
2948 function = "q !! 2876 pins = "gpio85", "gpio86",
>> 2877 "gpio87", "gpio88";
>> 2878 function = "qup5";
>> 2879 };
2949 }; 2880 };
2950 2881
2951 qup_spi7_default: qup !! 2882 qup_spi6_default: qup-spi6-default {
2952 pins = "gpio9 !! 2883 pinmux {
2953 function = "q !! 2884 pins = "gpio45", "gpio46",
>> 2885 "gpio47", "gpio48";
>> 2886 function = "qup6";
>> 2887 };
2954 }; 2888 };
2955 2889
2956 qup_spi8_default: qup !! 2890 qup_spi7_default: qup-spi7-default {
2957 pins = "gpio6 !! 2891 pinmux {
2958 function = "q !! 2892 pins = "gpio93", "gpio94",
>> 2893 "gpio95", "gpio96";
>> 2894 function = "qup7";
>> 2895 };
2959 }; 2896 };
2960 2897
2961 qup_spi9_default: qup !! 2898 qup_spi8_default: qup-spi8-default {
2962 pins = "gpio6 !! 2899 pinmux {
2963 function = "q !! 2900 pins = "gpio65", "gpio66",
>> 2901 "gpio67", "gpio68";
>> 2902 function = "qup8";
>> 2903 };
2964 }; 2904 };
2965 2905
2966 qup_spi10_default: qu !! 2906 qup_spi9_default: qup-spi9-default {
2967 pins = "gpio5 !! 2907 pinmux {
2968 function = "q !! 2908 pins = "gpio6", "gpio7",
>> 2909 "gpio4", "gpio5";
>> 2910 function = "qup9";
>> 2911 };
2969 }; 2912 };
2970 2913
2971 qup_spi11_default: qu !! 2914 qup_spi10_default: qup-spi10-default {
2972 pins = "gpio3 !! 2915 pinmux {
2973 function = "q !! 2916 pins = "gpio55", "gpio56",
>> 2917 "gpio53", "gpio54";
>> 2918 function = "qup10";
>> 2919 };
2974 }; 2920 };
2975 2921
2976 qup_spi12_default: qu !! 2922 qup_spi11_default: qup-spi11-default {
2977 pins = "gpio4 !! 2923 pinmux {
2978 function = "q !! 2924 pins = "gpio31", "gpio32",
>> 2925 "gpio33", "gpio34";
>> 2926 function = "qup11";
>> 2927 };
2979 }; 2928 };
2980 2929
2981 qup_spi13_default: qu !! 2930 qup_spi12_default: qup-spi12-default {
2982 pins = "gpio1 !! 2931 pinmux {
2983 function = "q !! 2932 pins = "gpio49", "gpio50",
>> 2933 "gpio51", "gpio52";
>> 2934 function = "qup12";
>> 2935 };
2984 }; 2936 };
2985 2937
2986 qup_spi14_default: qu !! 2938 qup_spi13_default: qup-spi13-default {
2987 pins = "gpio3 !! 2939 pinmux {
2988 function = "q !! 2940 pins = "gpio105", "gpio106",
>> 2941 "gpio107", "gpio108";
>> 2942 function = "qup13";
>> 2943 };
2989 }; 2944 };
2990 2945
2991 qup_spi15_default: qu !! 2946 qup_spi14_default: qup-spi14-default {
2992 pins = "gpio8 !! 2947 pinmux {
2993 function = "q !! 2948 pins = "gpio33", "gpio34",
>> 2949 "gpio31", "gpio32";
>> 2950 function = "qup14";
>> 2951 };
2994 }; 2952 };
2995 2953
2996 qup_uart0_default: qu !! 2954 qup_spi15_default: qup-spi15-default {
2997 qup_uart0_tx: !! 2955 pinmux {
2998 pins !! 2956 pins = "gpio81", "gpio82",
2999 funct !! 2957 "gpio83", "gpio84";
>> 2958 function = "qup15";
3000 }; 2959 };
>> 2960 };
3001 2961
3002 qup_uart0_rx: !! 2962 qup_uart0_default: qup-uart0-default {
3003 pins !! 2963 pinmux {
>> 2964 pins = "gpio2", "gpio3";
3004 funct 2965 function = "qup0";
3005 }; 2966 };
3006 }; 2967 };
3007 2968
3008 qup_uart1_default: qu !! 2969 qup_uart1_default: qup-uart1-default {
3009 qup_uart1_tx: !! 2970 pinmux {
3010 pins !! 2971 pins = "gpio19", "gpio20";
3011 funct <<
3012 }; <<
3013 <<
3014 qup_uart1_rx: <<
3015 pins <<
3016 funct 2972 function = "qup1";
3017 }; 2973 };
3018 }; 2974 };
3019 2975
3020 qup_uart2_default: qu !! 2976 qup_uart2_default: qup-uart2-default {
3021 qup_uart2_tx: !! 2977 pinmux {
3022 pins !! 2978 pins = "gpio29", "gpio30";
3023 funct <<
3024 }; <<
3025 <<
3026 qup_uart2_rx: <<
3027 pins <<
3028 funct 2979 function = "qup2";
3029 }; 2980 };
3030 }; 2981 };
3031 2982
3032 qup_uart3_default: qu !! 2983 qup_uart3_default: qup-uart3-default {
3033 qup_uart3_tx: !! 2984 pinmux {
3034 pins !! 2985 pins = "gpio43", "gpio44";
3035 funct <<
3036 }; <<
3037 <<
3038 qup_uart3_rx: <<
3039 pins <<
3040 funct <<
3041 }; <<
3042 }; <<
3043 <<
3044 qup_uart3_4pin: qup-u <<
3045 qup_uart3_4pi <<
3046 pins <<
3047 funct <<
3048 }; <<
3049 <<
3050 qup_uart3_4pi <<
3051 pins <<
3052 funct <<
3053 }; <<
3054 <<
3055 qup_uart3_4pi <<
3056 pins <<
3057 funct 2986 function = "qup3";
3058 }; 2987 };
3059 }; 2988 };
3060 2989
3061 qup_uart4_default: qu !! 2990 qup_uart4_default: qup-uart4-default {
3062 qup_uart4_tx: !! 2991 pinmux {
3063 pins !! 2992 pins = "gpio91", "gpio92";
3064 funct <<
3065 }; <<
3066 <<
3067 qup_uart4_rx: <<
3068 pins <<
3069 funct 2993 function = "qup4";
3070 }; 2994 };
3071 }; 2995 };
3072 2996
3073 qup_uart5_default: qu !! 2997 qup_uart5_default: qup-uart5-default {
3074 qup_uart5_tx: !! 2998 pinmux {
3075 pins !! 2999 pins = "gpio87", "gpio88";
3076 funct <<
3077 }; <<
3078 <<
3079 qup_uart5_rx: <<
3080 pins <<
3081 funct 3000 function = "qup5";
3082 }; 3001 };
3083 }; 3002 };
3084 3003
3085 qup_uart6_default: qu !! 3004 qup_uart6_default: qup-uart6-default {
3086 qup_uart6_tx: !! 3005 pinmux {
3087 pins !! 3006 pins = "gpio47", "gpio48";
3088 funct <<
3089 }; <<
3090 <<
3091 qup_uart6_rx: <<
3092 pins <<
3093 funct 3007 function = "qup6";
3094 }; 3008 };
3095 }; 3009 };
3096 3010
3097 qup_uart6_4pin: qup-u 3011 qup_uart6_4pin: qup-uart6-4pin-state {
3098 qup_uart6_4pi !! 3012
>> 3013 cts-pins {
3099 pins 3014 pins = "gpio45";
3100 funct 3015 function = "qup6";
3101 bias- 3016 bias-pull-down;
3102 }; 3017 };
3103 3018
3104 qup_uart6_4pi !! 3019 rts-tx-pins {
3105 pins 3020 pins = "gpio46", "gpio47";
3106 funct 3021 function = "qup6";
3107 drive 3022 drive-strength = <2>;
3108 bias- 3023 bias-disable;
3109 }; 3024 };
3110 3025
3111 qup_uart6_4pi !! 3026 rx-pins {
3112 pins 3027 pins = "gpio48";
3113 funct 3028 function = "qup6";
3114 bias- 3029 bias-pull-up;
3115 }; 3030 };
3116 }; 3031 };
3117 3032
3118 qup_uart7_default: qu !! 3033 qup_uart7_default: qup-uart7-default {
3119 qup_uart7_tx: !! 3034 pinmux {
3120 pins !! 3035 pins = "gpio95", "gpio96";
3121 funct <<
3122 }; <<
3123 <<
3124 qup_uart7_rx: <<
3125 pins <<
3126 funct 3036 function = "qup7";
3127 }; 3037 };
3128 }; 3038 };
3129 3039
3130 qup_uart8_default: qu !! 3040 qup_uart8_default: qup-uart8-default {
3131 qup_uart8_tx: !! 3041 pinmux {
3132 pins !! 3042 pins = "gpio67", "gpio68";
3133 funct 3043 function = "qup8";
3134 }; 3044 };
>> 3045 };
3135 3046
3136 qup_uart8_rx: !! 3047 qup_uart9_default: qup-uart9-default {
3137 pins !! 3048 pinmux {
3138 funct !! 3049 pins = "gpio4", "gpio5";
>> 3050 function = "qup9";
3139 }; 3051 };
3140 }; 3052 };
3141 3053
3142 qup_uart9_default: qu !! 3054 qup_uart10_default: qup-uart10-default {
3143 qup_uart9_tx: !! 3055 pinmux {
3144 pins !! 3056 pins = "gpio53", "gpio54";
3145 funct !! 3057 function = "qup10";
3146 }; 3058 };
>> 3059 };
3147 3060
3148 qup_uart9_rx: !! 3061 qup_uart11_default: qup-uart11-default {
3149 pins !! 3062 pinmux {
3150 funct !! 3063 pins = "gpio33", "gpio34";
>> 3064 function = "qup11";
3151 }; 3065 };
3152 }; 3066 };
3153 3067
3154 qup_uart10_default: q !! 3068 qup_uart12_default: qup-uart12-default {
3155 qup_uart10_tx !! 3069 pinmux {
3156 pins !! 3070 pins = "gpio51", "gpio52";
3157 funct !! 3071 function = "qup12";
3158 }; 3072 };
>> 3073 };
3159 3074
3160 qup_uart10_rx !! 3075 qup_uart13_default: qup-uart13-default {
3161 pins !! 3076 pinmux {
3162 funct !! 3077 pins = "gpio107", "gpio108";
>> 3078 function = "qup13";
3163 }; 3079 };
3164 }; 3080 };
3165 3081
3166 qup_uart11_default: q !! 3082 qup_uart14_default: qup-uart14-default {
3167 qup_uart11_tx !! 3083 pinmux {
3168 pins !! 3084 pins = "gpio31", "gpio32";
3169 funct !! 3085 function = "qup14";
3170 }; 3086 };
>> 3087 };
3171 3088
3172 qup_uart11_rx !! 3089 qup_uart15_default: qup-uart15-default {
3173 pins !! 3090 pinmux {
3174 funct !! 3091 pins = "gpio83", "gpio84";
>> 3092 function = "qup15";
3175 }; 3093 };
3176 }; 3094 };
3177 3095
3178 qup_uart12_default: q !! 3096 quat_mi2s_sleep: quat_mi2s_sleep {
3179 qup_uart12_tx !! 3097 mux {
3180 pins !! 3098 pins = "gpio58", "gpio59";
3181 funct !! 3099 function = "gpio";
3182 }; 3100 };
3183 3101
3184 qup_uart12_rx !! 3102 config {
3185 pins !! 3103 pins = "gpio58", "gpio59";
3186 funct !! 3104 drive-strength = <2>;
>> 3105 bias-pull-down;
>> 3106 input-enable;
3187 }; 3107 };
3188 }; 3108 };
3189 3109
3190 qup_uart13_default: q !! 3110 quat_mi2s_active: quat_mi2s_active {
3191 qup_uart13_tx !! 3111 mux {
3192 pins !! 3112 pins = "gpio58", "gpio59";
3193 funct !! 3113 function = "qua_mi2s";
3194 }; 3114 };
3195 3115
3196 qup_uart13_rx !! 3116 config {
3197 pins !! 3117 pins = "gpio58", "gpio59";
3198 funct !! 3118 drive-strength = <8>;
>> 3119 bias-disable;
>> 3120 output-high;
3199 }; 3121 };
3200 }; 3122 };
3201 3123
3202 qup_uart14_default: q !! 3124 quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
3203 qup_uart14_tx !! 3125 mux {
3204 pins !! 3126 pins = "gpio60";
3205 funct !! 3127 function = "gpio";
3206 }; 3128 };
3207 3129
3208 qup_uart14_rx !! 3130 config {
3209 pins !! 3131 pins = "gpio60";
3210 funct !! 3132 drive-strength = <2>;
>> 3133 bias-pull-down;
>> 3134 input-enable;
3211 }; 3135 };
3212 }; 3136 };
3213 3137
3214 qup_uart15_default: q !! 3138 quat_mi2s_sd0_active: quat_mi2s_sd0_active {
3215 qup_uart15_tx !! 3139 mux {
3216 pins !! 3140 pins = "gpio60";
3217 funct !! 3141 function = "qua_mi2s";
3218 }; 3142 };
3219 3143
3220 qup_uart15_rx !! 3144 config {
3221 pins !! 3145 pins = "gpio60";
3222 funct !! 3146 drive-strength = <8>;
>> 3147 bias-disable;
3223 }; 3148 };
3224 }; 3149 };
3225 3150
3226 quat_mi2s_sleep: quat !! 3151 quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
3227 pins = "gpio5 !! 3152 mux {
3228 function = "g !! 3153 pins = "gpio61";
3229 drive-strengt !! 3154 function = "gpio";
3230 bias-pull-dow !! 3155 };
3231 }; <<
3232 3156
3233 quat_mi2s_active: qua !! 3157 config {
3234 pins = "gpio5 !! 3158 pins = "gpio61";
3235 function = "q !! 3159 drive-strength = <2>;
3236 drive-strengt !! 3160 bias-pull-down;
3237 bias-disable; !! 3161 input-enable;
3238 output-high; !! 3162 };
3239 }; 3163 };
3240 3164
3241 quat_mi2s_sd0_sleep: !! 3165 quat_mi2s_sd1_active: quat_mi2s_sd1_active {
3242 pins = "gpio6 !! 3166 mux {
3243 function = "g !! 3167 pins = "gpio61";
3244 drive-strengt !! 3168 function = "qua_mi2s";
3245 bias-pull-dow !! 3169 };
3246 }; <<
3247 3170
3248 quat_mi2s_sd0_active: !! 3171 config {
3249 pins = "gpio6 !! 3172 pins = "gpio61";
3250 function = "q !! 3173 drive-strength = <8>;
3251 drive-strengt !! 3174 bias-disable;
3252 bias-disable; !! 3175 };
3253 }; 3176 };
3254 3177
3255 quat_mi2s_sd1_sleep: !! 3178 quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
3256 pins = "gpio6 !! 3179 mux {
3257 function = "g !! 3180 pins = "gpio62";
3258 drive-strengt !! 3181 function = "gpio";
3259 bias-pull-dow !! 3182 };
3260 }; <<
3261 3183
3262 quat_mi2s_sd1_active: !! 3184 config {
3263 pins = "gpio6 !! 3185 pins = "gpio62";
3264 function = "q !! 3186 drive-strength = <2>;
3265 drive-strengt !! 3187 bias-pull-down;
3266 bias-disable; !! 3188 input-enable;
>> 3189 };
3267 }; 3190 };
3268 3191
3269 quat_mi2s_sd2_sleep: !! 3192 quat_mi2s_sd2_active: quat_mi2s_sd2_active {
3270 pins = "gpio6 !! 3193 mux {
3271 function = "g !! 3194 pins = "gpio62";
3272 drive-strengt !! 3195 function = "qua_mi2s";
3273 bias-pull-dow !! 3196 };
3274 }; <<
3275 3197
3276 quat_mi2s_sd2_active: !! 3198 config {
3277 pins = "gpio6 !! 3199 pins = "gpio62";
3278 function = "q !! 3200 drive-strength = <8>;
3279 drive-strengt !! 3201 bias-disable;
3280 bias-disable; !! 3202 };
3281 }; 3203 };
3282 3204
3283 quat_mi2s_sd3_sleep: !! 3205 quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
3284 pins = "gpio6 !! 3206 mux {
3285 function = "g !! 3207 pins = "gpio63";
3286 drive-strengt !! 3208 function = "gpio";
3287 bias-pull-dow !! 3209 };
>> 3210
>> 3211 config {
>> 3212 pins = "gpio63";
>> 3213 drive-strength = <2>;
>> 3214 bias-pull-down;
>> 3215 input-enable;
>> 3216 };
3288 }; 3217 };
3289 3218
3290 quat_mi2s_sd3_active: !! 3219 quat_mi2s_sd3_active: quat_mi2s_sd3_active {
3291 pins = "gpio6 !! 3220 mux {
3292 function = "q !! 3221 pins = "gpio63";
3293 drive-strengt !! 3222 function = "qua_mi2s";
3294 bias-disable; !! 3223 };
>> 3224
>> 3225 config {
>> 3226 pins = "gpio63";
>> 3227 drive-strength = <8>;
>> 3228 bias-disable;
>> 3229 };
3295 }; 3230 };
3296 }; 3231 };
3297 3232
3298 mss_pil: remoteproc@4080000 { 3233 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 3234 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 3235 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 3236 reg-names = "qdsp6", "rmb";
3302 3237
3303 interrupts-extended = 3238 interrupts-extended =
3304 <&intc GIC_SP 3239 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 3240 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 3241 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 3242 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 3243 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 3244 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 3245 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 3246 "handover", "stop-ack",
3312 "sh 3247 "shutdown-ack";
3313 3248
3314 clocks = <&gcc GCC_MS 3249 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 3250 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 3251 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 3252 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 3253 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 3254 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 3255 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 3256 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 3257 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 3258 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 3259
3325 qcom,qmp = <&aoss_qmp 3260 qcom,qmp = <&aoss_qmp>;
3326 3261
3327 qcom,smem-states = <& 3262 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 3263 qcom,smem-state-names = "stop";
3329 3264
3330 resets = <&aoss_reset 3265 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 3266 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 3267 reset-names = "mss_restart", "pdc_reset";
3333 3268
3334 qcom,halt-regs = <&tc 3269 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3335 3270
3336 power-domains = <&rpm 3271 power-domains = <&rpmhpd SDM845_CX>,
3337 <&rpm 3272 <&rpmhpd SDM845_MX>,
3338 <&rpm 3273 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = 3274 power-domain-names = "cx", "mx", "mss";
3340 3275
3341 status = "disabled"; 3276 status = "disabled";
3342 3277
3343 mba { 3278 mba {
3344 memory-region 3279 memory-region = <&mba_region>;
3345 }; 3280 };
3346 3281
3347 mpss { 3282 mpss {
3348 memory-region 3283 memory-region = <&mpss_region>;
3349 }; 3284 };
3350 3285
3351 metadata { <<
3352 memory-region <<
3353 }; <<
3354 <<
3355 glink-edge { 3286 glink-edge {
3356 interrupts = 3287 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3288 label = "modem";
3358 qcom,remote-p 3289 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3290 mboxes = <&apss_shared 12>;
3360 }; 3291 };
3361 }; 3292 };
3362 3293
3363 gpucc: clock-controller@50900 3294 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3295 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3296 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3297 #clock-cells = <1>;
3367 #reset-cells = <1>; 3298 #reset-cells = <1>;
3368 #power-domain-cells = 3299 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3300 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3301 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3302 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3303 clock-names = "bi_tcxo",
3373 "gcc_gp 3304 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3305 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3306 };
3376 3307
3377 slpi_pas: remoteproc@5c00000 <<
3378 compatible = "qcom,sd <<
3379 reg = <0 0x5c00000 0 <<
3380 <<
3381 interrupts-extended = <<
3382 <<
3383 <<
3384 <<
3385 <<
3386 interrupt-names = "wd <<
3387 <<
3388 <<
3389 clocks = <&rpmhcc RPM <<
3390 clock-names = "xo"; <<
3391 <<
3392 qcom,qmp = <&aoss_qmp <<
3393 <<
3394 power-domains = <&rpm <<
3395 <&rpm <<
3396 power-domain-names = <<
3397 <<
3398 memory-region = <&slp <<
3399 <<
3400 qcom,smem-states = <& <<
3401 qcom,smem-state-names <<
3402 <<
3403 status = "disabled"; <<
3404 <<
3405 glink-edge { <<
3406 interrupts = <<
3407 label = "dsps <<
3408 qcom,remote-p <<
3409 mboxes = <&ap <<
3410 <<
3411 fastrpc { <<
3412 compa <<
3413 qcom, <<
3414 label <<
3415 qcom, <<
3416 qcom, <<
3417 <<
3418 memor <<
3419 #addr <<
3420 #size <<
3421 <<
3422 compu <<
3423 <<
3424 <<
3425 }; <<
3426 }; <<
3427 }; <<
3428 }; <<
3429 <<
3430 stm@6002000 { 3308 stm@6002000 {
3431 compatible = "arm,cor 3309 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3310 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3311 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3312 reg-names = "stm-base", "stm-stimulus-base";
3435 3313
3436 clocks = <&aoss_qmp>; 3314 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3315 clock-names = "apb_pclk";
3438 3316
3439 out-ports { 3317 out-ports {
3440 port { 3318 port {
3441 stm_o 3319 stm_out: endpoint {
3442 3320 remote-endpoint =
3443 3321 <&funnel0_in7>;
3444 }; 3322 };
3445 }; 3323 };
3446 }; 3324 };
3447 }; 3325 };
3448 3326
3449 funnel@6041000 { 3327 funnel@6041000 {
3450 compatible = "arm,cor 3328 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3329 reg = <0 0x06041000 0 0x1000>;
3452 3330
3453 clocks = <&aoss_qmp>; 3331 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3332 clock-names = "apb_pclk";
3455 3333
3456 out-ports { 3334 out-ports {
3457 port { 3335 port {
3458 funne 3336 funnel0_out: endpoint {
3459 3337 remote-endpoint =
3460 3338 <&merge_funnel_in0>;
3461 }; 3339 };
3462 }; 3340 };
3463 }; 3341 };
3464 3342
3465 in-ports { 3343 in-ports {
3466 #address-cell 3344 #address-cells = <1>;
3467 #size-cells = 3345 #size-cells = <0>;
3468 3346
3469 port@7 { 3347 port@7 {
3470 reg = 3348 reg = <7>;
3471 funne 3349 funnel0_in7: endpoint {
3472 3350 remote-endpoint = <&stm_out>;
3473 }; 3351 };
3474 }; 3352 };
3475 }; 3353 };
3476 }; 3354 };
3477 3355
3478 funnel@6043000 { 3356 funnel@6043000 {
3479 compatible = "arm,cor 3357 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3358 reg = <0 0x06043000 0 0x1000>;
3481 3359
3482 clocks = <&aoss_qmp>; 3360 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3361 clock-names = "apb_pclk";
3484 3362
3485 out-ports { 3363 out-ports {
3486 port { 3364 port {
3487 funne 3365 funnel2_out: endpoint {
3488 3366 remote-endpoint =
3489 3367 <&merge_funnel_in2>;
3490 }; 3368 };
3491 }; 3369 };
3492 }; 3370 };
3493 3371
3494 in-ports { 3372 in-ports {
3495 #address-cell 3373 #address-cells = <1>;
3496 #size-cells = 3374 #size-cells = <0>;
3497 3375
3498 port@5 { 3376 port@5 {
3499 reg = 3377 reg = <5>;
3500 funne 3378 funnel2_in5: endpoint {
3501 3379 remote-endpoint =
3502 3380 <&apss_merge_funnel_out>;
3503 }; 3381 };
3504 }; 3382 };
3505 }; 3383 };
3506 }; 3384 };
3507 3385
3508 funnel@6045000 { 3386 funnel@6045000 {
3509 compatible = "arm,cor 3387 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3388 reg = <0 0x06045000 0 0x1000>;
3511 3389
3512 clocks = <&aoss_qmp>; 3390 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3391 clock-names = "apb_pclk";
3514 3392
3515 out-ports { 3393 out-ports {
3516 port { 3394 port {
3517 merge 3395 merge_funnel_out: endpoint {
3518 3396 remote-endpoint = <&etf_in>;
3519 }; 3397 };
3520 }; 3398 };
3521 }; 3399 };
3522 3400
3523 in-ports { 3401 in-ports {
3524 #address-cell 3402 #address-cells = <1>;
3525 #size-cells = 3403 #size-cells = <0>;
3526 3404
3527 port@0 { 3405 port@0 {
3528 reg = 3406 reg = <0>;
3529 merge 3407 merge_funnel_in0: endpoint {
3530 3408 remote-endpoint =
3531 3409 <&funnel0_out>;
3532 }; 3410 };
3533 }; 3411 };
3534 3412
3535 port@2 { 3413 port@2 {
3536 reg = 3414 reg = <2>;
3537 merge 3415 merge_funnel_in2: endpoint {
3538 3416 remote-endpoint =
3539 3417 <&funnel2_out>;
3540 }; 3418 };
3541 }; 3419 };
3542 }; 3420 };
3543 }; 3421 };
3544 3422
3545 replicator@6046000 { 3423 replicator@6046000 {
3546 compatible = "arm,cor 3424 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3425 reg = <0 0x06046000 0 0x1000>;
3548 3426
3549 clocks = <&aoss_qmp>; 3427 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3428 clock-names = "apb_pclk";
3551 3429
3552 out-ports { 3430 out-ports {
3553 port { 3431 port {
3554 repli 3432 replicator_out: endpoint {
3555 3433 remote-endpoint = <&etr_in>;
3556 }; 3434 };
3557 }; 3435 };
3558 }; 3436 };
3559 3437
3560 in-ports { 3438 in-ports {
3561 port { 3439 port {
3562 repli 3440 replicator_in: endpoint {
3563 3441 remote-endpoint = <&etf_out>;
3564 }; 3442 };
3565 }; 3443 };
3566 }; 3444 };
3567 }; 3445 };
3568 3446
3569 etf@6047000 { 3447 etf@6047000 {
3570 compatible = "arm,cor 3448 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3449 reg = <0 0x06047000 0 0x1000>;
3572 3450
3573 clocks = <&aoss_qmp>; 3451 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3452 clock-names = "apb_pclk";
3575 3453
3576 out-ports { 3454 out-ports {
3577 port { 3455 port {
3578 etf_o 3456 etf_out: endpoint {
3579 3457 remote-endpoint =
3580 3458 <&replicator_in>;
3581 }; 3459 };
3582 }; 3460 };
3583 }; 3461 };
3584 3462
3585 in-ports { 3463 in-ports {
>> 3464 #address-cells = <1>;
>> 3465 #size-cells = <0>;
3586 3466
3587 port { !! 3467 port@1 {
>> 3468 reg = <1>;
3588 etf_i 3469 etf_in: endpoint {
3589 3470 remote-endpoint =
3590 3471 <&merge_funnel_out>;
3591 }; 3472 };
3592 }; 3473 };
3593 }; 3474 };
3594 }; 3475 };
3595 3476
3596 etr@6048000 { 3477 etr@6048000 {
3597 compatible = "arm,cor 3478 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3479 reg = <0 0x06048000 0 0x1000>;
3599 3480
3600 clocks = <&aoss_qmp>; 3481 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3482 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3483 arm,scatter-gather;
3603 3484
3604 in-ports { 3485 in-ports {
3605 port { 3486 port {
3606 etr_i 3487 etr_in: endpoint {
3607 3488 remote-endpoint =
3608 3489 <&replicator_out>;
3609 }; 3490 };
3610 }; 3491 };
3611 }; 3492 };
3612 }; 3493 };
3613 3494
3614 etm@7040000 { 3495 etm@7040000 {
3615 compatible = "arm,cor 3496 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3497 reg = <0 0x07040000 0 0x1000>;
3617 3498
3618 cpu = <&CPU0>; 3499 cpu = <&CPU0>;
3619 3500
3620 clocks = <&aoss_qmp>; 3501 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3502 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3503 arm,coresight-loses-context-with-cpu;
3623 3504
3624 out-ports { 3505 out-ports {
3625 port { 3506 port {
3626 etm0_ 3507 etm0_out: endpoint {
3627 3508 remote-endpoint =
3628 3509 <&apss_funnel_in0>;
3629 }; 3510 };
3630 }; 3511 };
3631 }; 3512 };
3632 }; 3513 };
3633 3514
3634 etm@7140000 { 3515 etm@7140000 {
3635 compatible = "arm,cor 3516 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3517 reg = <0 0x07140000 0 0x1000>;
3637 3518
3638 cpu = <&CPU1>; 3519 cpu = <&CPU1>;
3639 3520
3640 clocks = <&aoss_qmp>; 3521 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3522 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3523 arm,coresight-loses-context-with-cpu;
3643 3524
3644 out-ports { 3525 out-ports {
3645 port { 3526 port {
3646 etm1_ 3527 etm1_out: endpoint {
3647 3528 remote-endpoint =
3648 3529 <&apss_funnel_in1>;
3649 }; 3530 };
3650 }; 3531 };
3651 }; 3532 };
3652 }; 3533 };
3653 3534
3654 etm@7240000 { 3535 etm@7240000 {
3655 compatible = "arm,cor 3536 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3537 reg = <0 0x07240000 0 0x1000>;
3657 3538
3658 cpu = <&CPU2>; 3539 cpu = <&CPU2>;
3659 3540
3660 clocks = <&aoss_qmp>; 3541 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3542 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3543 arm,coresight-loses-context-with-cpu;
3663 3544
3664 out-ports { 3545 out-ports {
3665 port { 3546 port {
3666 etm2_ 3547 etm2_out: endpoint {
3667 3548 remote-endpoint =
3668 3549 <&apss_funnel_in2>;
3669 }; 3550 };
3670 }; 3551 };
3671 }; 3552 };
3672 }; 3553 };
3673 3554
3674 etm@7340000 { 3555 etm@7340000 {
3675 compatible = "arm,cor 3556 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3557 reg = <0 0x07340000 0 0x1000>;
3677 3558
3678 cpu = <&CPU3>; 3559 cpu = <&CPU3>;
3679 3560
3680 clocks = <&aoss_qmp>; 3561 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3562 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3563 arm,coresight-loses-context-with-cpu;
3683 3564
3684 out-ports { 3565 out-ports {
3685 port { 3566 port {
3686 etm3_ 3567 etm3_out: endpoint {
3687 3568 remote-endpoint =
3688 3569 <&apss_funnel_in3>;
3689 }; 3570 };
3690 }; 3571 };
3691 }; 3572 };
3692 }; 3573 };
3693 3574
3694 etm@7440000 { 3575 etm@7440000 {
3695 compatible = "arm,cor 3576 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3577 reg = <0 0x07440000 0 0x1000>;
3697 3578
3698 cpu = <&CPU4>; 3579 cpu = <&CPU4>;
3699 3580
3700 clocks = <&aoss_qmp>; 3581 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3582 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3583 arm,coresight-loses-context-with-cpu;
3703 3584
3704 out-ports { 3585 out-ports {
3705 port { 3586 port {
3706 etm4_ 3587 etm4_out: endpoint {
3707 3588 remote-endpoint =
3708 3589 <&apss_funnel_in4>;
3709 }; 3590 };
3710 }; 3591 };
3711 }; 3592 };
3712 }; 3593 };
3713 3594
3714 etm@7540000 { 3595 etm@7540000 {
3715 compatible = "arm,cor 3596 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3597 reg = <0 0x07540000 0 0x1000>;
3717 3598
3718 cpu = <&CPU5>; 3599 cpu = <&CPU5>;
3719 3600
3720 clocks = <&aoss_qmp>; 3601 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3602 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3603 arm,coresight-loses-context-with-cpu;
3723 3604
3724 out-ports { 3605 out-ports {
3725 port { 3606 port {
3726 etm5_ 3607 etm5_out: endpoint {
3727 3608 remote-endpoint =
3728 3609 <&apss_funnel_in5>;
3729 }; 3610 };
3730 }; 3611 };
3731 }; 3612 };
3732 }; 3613 };
3733 3614
3734 etm@7640000 { 3615 etm@7640000 {
3735 compatible = "arm,cor 3616 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3617 reg = <0 0x07640000 0 0x1000>;
3737 3618
3738 cpu = <&CPU6>; 3619 cpu = <&CPU6>;
3739 3620
3740 clocks = <&aoss_qmp>; 3621 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3622 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3623 arm,coresight-loses-context-with-cpu;
3743 3624
3744 out-ports { 3625 out-ports {
3745 port { 3626 port {
3746 etm6_ 3627 etm6_out: endpoint {
3747 3628 remote-endpoint =
3748 3629 <&apss_funnel_in6>;
3749 }; 3630 };
3750 }; 3631 };
3751 }; 3632 };
3752 }; 3633 };
3753 3634
3754 etm@7740000 { 3635 etm@7740000 {
3755 compatible = "arm,cor 3636 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3637 reg = <0 0x07740000 0 0x1000>;
3757 3638
3758 cpu = <&CPU7>; 3639 cpu = <&CPU7>;
3759 3640
3760 clocks = <&aoss_qmp>; 3641 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3642 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3643 arm,coresight-loses-context-with-cpu;
3763 3644
3764 out-ports { 3645 out-ports {
3765 port { 3646 port {
3766 etm7_ 3647 etm7_out: endpoint {
3767 3648 remote-endpoint =
3768 3649 <&apss_funnel_in7>;
3769 }; 3650 };
3770 }; 3651 };
3771 }; 3652 };
3772 }; 3653 };
3773 3654
3774 funnel@7800000 { /* APSS Funn 3655 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3656 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3657 reg = <0 0x07800000 0 0x1000>;
3777 3658
3778 clocks = <&aoss_qmp>; 3659 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3660 clock-names = "apb_pclk";
3780 3661
3781 out-ports { 3662 out-ports {
3782 port { 3663 port {
3783 apss_ 3664 apss_funnel_out: endpoint {
3784 3665 remote-endpoint =
3785 3666 <&apss_merge_funnel_in>;
3786 }; 3667 };
3787 }; 3668 };
3788 }; 3669 };
3789 3670
3790 in-ports { 3671 in-ports {
3791 #address-cell 3672 #address-cells = <1>;
3792 #size-cells = 3673 #size-cells = <0>;
3793 3674
3794 port@0 { 3675 port@0 {
3795 reg = 3676 reg = <0>;
3796 apss_ 3677 apss_funnel_in0: endpoint {
3797 3678 remote-endpoint =
3798 3679 <&etm0_out>;
3799 }; 3680 };
3800 }; 3681 };
3801 3682
3802 port@1 { 3683 port@1 {
3803 reg = 3684 reg = <1>;
3804 apss_ 3685 apss_funnel_in1: endpoint {
3805 3686 remote-endpoint =
3806 3687 <&etm1_out>;
3807 }; 3688 };
3808 }; 3689 };
3809 3690
3810 port@2 { 3691 port@2 {
3811 reg = 3692 reg = <2>;
3812 apss_ 3693 apss_funnel_in2: endpoint {
3813 3694 remote-endpoint =
3814 3695 <&etm2_out>;
3815 }; 3696 };
3816 }; 3697 };
3817 3698
3818 port@3 { 3699 port@3 {
3819 reg = 3700 reg = <3>;
3820 apss_ 3701 apss_funnel_in3: endpoint {
3821 3702 remote-endpoint =
3822 3703 <&etm3_out>;
3823 }; 3704 };
3824 }; 3705 };
3825 3706
3826 port@4 { 3707 port@4 {
3827 reg = 3708 reg = <4>;
3828 apss_ 3709 apss_funnel_in4: endpoint {
3829 3710 remote-endpoint =
3830 3711 <&etm4_out>;
3831 }; 3712 };
3832 }; 3713 };
3833 3714
3834 port@5 { 3715 port@5 {
3835 reg = 3716 reg = <5>;
3836 apss_ 3717 apss_funnel_in5: endpoint {
3837 3718 remote-endpoint =
3838 3719 <&etm5_out>;
3839 }; 3720 };
3840 }; 3721 };
3841 3722
3842 port@6 { 3723 port@6 {
3843 reg = 3724 reg = <6>;
3844 apss_ 3725 apss_funnel_in6: endpoint {
3845 3726 remote-endpoint =
3846 3727 <&etm6_out>;
3847 }; 3728 };
3848 }; 3729 };
3849 3730
3850 port@7 { 3731 port@7 {
3851 reg = 3732 reg = <7>;
3852 apss_ 3733 apss_funnel_in7: endpoint {
3853 3734 remote-endpoint =
3854 3735 <&etm7_out>;
3855 }; 3736 };
3856 }; 3737 };
3857 }; 3738 };
3858 }; 3739 };
3859 3740
3860 funnel@7810000 { 3741 funnel@7810000 {
3861 compatible = "arm,cor 3742 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3743 reg = <0 0x07810000 0 0x1000>;
3863 3744
3864 clocks = <&aoss_qmp>; 3745 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3746 clock-names = "apb_pclk";
3866 3747
3867 out-ports { 3748 out-ports {
3868 port { 3749 port {
3869 apss_ 3750 apss_merge_funnel_out: endpoint {
3870 3751 remote-endpoint =
3871 3752 <&funnel2_in5>;
3872 }; 3753 };
3873 }; 3754 };
3874 }; 3755 };
3875 3756
3876 in-ports { 3757 in-ports {
3877 port { 3758 port {
3878 apss_ 3759 apss_merge_funnel_in: endpoint {
3879 3760 remote-endpoint =
3880 3761 <&apss_funnel_out>;
3881 }; 3762 };
3882 }; 3763 };
3883 }; 3764 };
3884 }; 3765 };
3885 3766
3886 sdhc_2: mmc@8804000 { 3767 sdhc_2: mmc@8804000 {
3887 compatible = "qcom,sd 3768 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3769 reg = <0 0x08804000 0 0x1000>;
3889 3770
3890 interrupts = <GIC_SPI 3771 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3772 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3773 interrupt-names = "hc_irq", "pwr_irq";
3893 3774
3894 clocks = <&gcc GCC_SD 3775 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD 3776 <&gcc GCC_SDCC2_APPS_CLK>,
3896 <&rpmhcc RPM 3777 <&rpmhcc RPMH_CXO_CLK>;
3897 clock-names = "iface" 3778 clock-names = "iface", "core", "xo";
3898 iommus = <&apps_smmu 3779 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3780 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3781 operating-points-v2 = <&sdhc2_opp_table>;
3901 3782
3902 status = "disabled"; 3783 status = "disabled";
3903 3784
3904 sdhc2_opp_table: opp- 3785 sdhc2_opp_table: opp-table {
3905 compatible = 3786 compatible = "operating-points-v2";
3906 3787
3907 opp-9600000 { 3788 opp-9600000 {
3908 opp-h 3789 opp-hz = /bits/ 64 <9600000>;
3909 requi 3790 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3791 };
3911 3792
3912 opp-19200000 3793 opp-19200000 {
3913 opp-h 3794 opp-hz = /bits/ 64 <19200000>;
3914 requi 3795 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3796 };
3916 3797
3917 opp-100000000 3798 opp-100000000 {
3918 opp-h 3799 opp-hz = /bits/ 64 <100000000>;
3919 requi 3800 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3801 };
3921 3802
3922 opp-201500000 3803 opp-201500000 {
3923 opp-h 3804 opp-hz = /bits/ 64 <201500000>;
3924 requi 3805 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3806 };
3926 }; 3807 };
3927 }; 3808 };
3928 3809
>> 3810 qspi_opp_table: opp-table-qspi {
>> 3811 compatible = "operating-points-v2";
>> 3812
>> 3813 opp-19200000 {
>> 3814 opp-hz = /bits/ 64 <19200000>;
>> 3815 required-opps = <&rpmhpd_opp_min_svs>;
>> 3816 };
>> 3817
>> 3818 opp-100000000 {
>> 3819 opp-hz = /bits/ 64 <100000000>;
>> 3820 required-opps = <&rpmhpd_opp_low_svs>;
>> 3821 };
>> 3822
>> 3823 opp-150000000 {
>> 3824 opp-hz = /bits/ 64 <150000000>;
>> 3825 required-opps = <&rpmhpd_opp_svs>;
>> 3826 };
>> 3827
>> 3828 opp-300000000 {
>> 3829 opp-hz = /bits/ 64 <300000000>;
>> 3830 required-opps = <&rpmhpd_opp_nom>;
>> 3831 };
>> 3832 };
>> 3833
3929 qspi: spi@88df000 { 3834 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3835 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3836 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu <<
3933 #address-cells = <1>; 3837 #address-cells = <1>;
3934 #size-cells = <0>; 3838 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3839 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3840 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3841 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3842 clock-names = "iface", "core";
3939 power-domains = <&rpm 3843 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3844 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3845 status = "disabled";
3942 }; 3846 };
3943 3847
3944 slim: slim-ngd@171c0000 { 3848 slim: slim-ngd@171c0000 {
3945 compatible = "qcom,sl 3849 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3850 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3851 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3852
3949 dmas = <&slimbam 3>, 3853 dmas = <&slimbam 3>, <&slimbam 4>;
3950 dma-names = "rx", "tx 3854 dma-names = "rx", "tx";
3951 3855
3952 iommus = <&apps_smmu 3856 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3857 #address-cells = <1>;
3954 #size-cells = <0>; 3858 #size-cells = <0>;
3955 status = "disabled"; !! 3859
>> 3860 slim@1 {
>> 3861 reg = <1>;
>> 3862 #address-cells = <2>;
>> 3863 #size-cells = <0>;
>> 3864
>> 3865 wcd9340_ifd: ifd@0,0 {
>> 3866 compatible = "slim217,250";
>> 3867 reg = <0 0>;
>> 3868 };
>> 3869
>> 3870 wcd9340: codec@1,0 {
>> 3871 compatible = "slim217,250";
>> 3872 reg = <1 0>;
>> 3873 slim-ifc-dev = <&wcd9340_ifd>;
>> 3874
>> 3875 #sound-dai-cells = <1>;
>> 3876
>> 3877 interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
>> 3878 interrupt-controller;
>> 3879 #interrupt-cells = <1>;
>> 3880
>> 3881 #clock-cells = <0>;
>> 3882 clock-frequency = <9600000>;
>> 3883 clock-output-names = "mclk";
>> 3884 qcom,micbias1-microvolt = <1800000>;
>> 3885 qcom,micbias2-microvolt = <1800000>;
>> 3886 qcom,micbias3-microvolt = <1800000>;
>> 3887 qcom,micbias4-microvolt = <1800000>;
>> 3888
>> 3889 #address-cells = <1>;
>> 3890 #size-cells = <1>;
>> 3891
>> 3892 wcdgpio: gpio-controller@42 {
>> 3893 compatible = "qcom,wcd9340-gpio";
>> 3894 gpio-controller;
>> 3895 #gpio-cells = <2>;
>> 3896 reg = <0x42 0x2>;
>> 3897 };
>> 3898
>> 3899 swm: swm@c85 {
>> 3900 compatible = "qcom,soundwire-v1.3.0";
>> 3901 reg = <0xc85 0x40>;
>> 3902 interrupts-extended = <&wcd9340 20>;
>> 3903
>> 3904 qcom,dout-ports = <6>;
>> 3905 qcom,din-ports = <2>;
>> 3906 qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
>> 3907 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
>> 3908 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
>> 3909
>> 3910 #sound-dai-cells = <1>;
>> 3911 clocks = <&wcd9340>;
>> 3912 clock-names = "iface";
>> 3913 #address-cells = <2>;
>> 3914 #size-cells = <0>;
>> 3915
>> 3916
>> 3917 };
>> 3918 };
>> 3919 };
3956 }; 3920 };
3957 3921
3958 lmh_cluster1: lmh@17d70800 { 3922 lmh_cluster1: lmh@17d70800 {
3959 compatible = "qcom,sd 3923 compatible = "qcom,sdm845-lmh";
3960 reg = <0 0x17d70800 0 3924 reg = <0 0x17d70800 0 0x400>;
3961 interrupts = <GIC_SPI 3925 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962 cpus = <&CPU4>; 3926 cpus = <&CPU4>;
3963 qcom,lmh-temp-arm-mil 3927 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-mil 3928 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-mi 3929 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller; 3930 interrupt-controller;
3967 #interrupt-cells = <1 3931 #interrupt-cells = <1>;
3968 }; 3932 };
3969 3933
3970 lmh_cluster0: lmh@17d78800 { 3934 lmh_cluster0: lmh@17d78800 {
3971 compatible = "qcom,sd 3935 compatible = "qcom,sdm845-lmh";
3972 reg = <0 0x17d78800 0 3936 reg = <0 0x17d78800 0 0x400>;
3973 interrupts = <GIC_SPI 3937 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974 cpus = <&CPU0>; 3938 cpus = <&CPU0>;
3975 qcom,lmh-temp-arm-mil 3939 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-mil 3940 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-mi 3941 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller; 3942 interrupt-controller;
3979 #interrupt-cells = <1 3943 #interrupt-cells = <1>;
3980 }; 3944 };
3981 3945
>> 3946 sound: sound {
>> 3947 };
>> 3948
3982 usb_1_hsphy: phy@88e2000 { 3949 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3950 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3951 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3952 status = "disabled";
3986 #phy-cells = <0>; 3953 #phy-cells = <0>;
3987 3954
3988 clocks = <&gcc GCC_US 3955 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3956 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3957 clock-names = "cfg_ahb", "ref";
3991 3958
3992 resets = <&gcc GCC_QU 3959 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3960
3994 nvmem-cells = <&qusb2 3961 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3962 };
3996 3963
3997 usb_2_hsphy: phy@88e3000 { 3964 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3965 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3966 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3967 status = "disabled";
4001 #phy-cells = <0>; 3968 #phy-cells = <0>;
4002 3969
4003 clocks = <&gcc GCC_US 3970 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3971 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3972 clock-names = "cfg_ahb", "ref";
4006 3973
4007 resets = <&gcc GCC_QU 3974 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3975
4009 nvmem-cells = <&qusb2 3976 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3977 };
4011 3978
4012 usb_1_qmpphy: phy@88e8000 { !! 3979 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd 3980 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4014 reg = <0 0x088e8000 0 !! 3981 reg = <0 0x088e9000 0 0x18c>,
>> 3982 <0 0x088e8000 0 0x38>,
>> 3983 <0 0x088ea000 0 0x40>;
4015 status = "disabled"; 3984 status = "disabled";
>> 3985 #address-cells = <2>;
>> 3986 #size-cells = <2>;
>> 3987 ranges;
4016 3988
4017 clocks = <&gcc GCC_US 3989 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3990 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3991 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3992 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3993 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3994
4028 resets = <&gcc GCC_US 3995 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4029 <&gcc GCC_US 3996 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4030 reset-names = "phy", 3997 reset-names = "phy", "common";
4031 3998
4032 #clock-cells = <1>; !! 3999 usb_1_ssphy: usb3-phy@88e9200 {
4033 #phy-cells = <1>; !! 4000 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 4001 <0 0x088e9400 0 0x200>,
4035 !! 4002 <0 0x088e9c00 0 0x218>,
4036 ports { !! 4003 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 4004 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 4005 <0 0x088e9a00 0 0x100>;
4039 !! 4006 #clock-cells = <0>;
4040 port@0 { !! 4007 #phy-cells = <0>;
4041 reg = !! 4008 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042 !! 4009 clock-names = "pipe0";
4043 usb_1 !! 4010 clock-output-names = "usb3_phy_pipe_clk_src";
4044 }; !! 4011 };
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 4012
4058 usb_1 !! 4013 dp_phy: dp-phy@88ea200 {
4059 !! 4014 reg = <0 0x088ea200 0 0x200>,
4060 }; !! 4015 <0 0x088ea400 0 0x200>,
4061 }; !! 4016 <0 0x088eaa00 0 0x200>,
>> 4017 <0 0x088ea600 0 0x200>,
>> 4018 <0 0x088ea800 0 0x200>;
>> 4019 #clock-cells = <1>;
>> 4020 #phy-cells = <0>;
4062 }; 4021 };
4063 }; 4022 };
4064 4023
4065 usb_2_qmpphy: phy@88eb000 { 4024 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 4025 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 4026 reg = <0 0x088eb000 0 0x18c>;
>> 4027 status = "disabled";
>> 4028 #address-cells = <2>;
>> 4029 #size-cells = <2>;
>> 4030 ranges;
4068 4031
4069 clocks = <&gcc GCC_US 4032 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 4033 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 4034 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 4035 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 4036 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 4037
4083 resets = <&gcc GCC_US !! 4038 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 4039 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 4040 reset-names = "phy", "common";
4086 "phy_ph <<
4087 4041
4088 status = "disabled"; !! 4042 usb_2_ssphy: phy@88eb200 {
>> 4043 reg = <0 0x088eb200 0 0x128>,
>> 4044 <0 0x088eb400 0 0x1fc>,
>> 4045 <0 0x088eb800 0 0x218>,
>> 4046 <0 0x088eb600 0 0x70>;
>> 4047 #clock-cells = <0>;
>> 4048 #phy-cells = <0>;
>> 4049 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 4050 clock-names = "pipe0";
>> 4051 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 4052 };
4089 }; 4053 };
4090 4054
4091 usb_1: usb@a6f8800 { 4055 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 4056 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 4057 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 4058 status = "disabled";
4095 #address-cells = <2>; 4059 #address-cells = <2>;
4096 #size-cells = <2>; 4060 #size-cells = <2>;
4097 ranges; 4061 ranges;
4098 dma-ranges; 4062 dma-ranges;
4099 4063
4100 clocks = <&gcc GCC_CF 4064 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 4065 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 4066 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US 4067 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4104 <&gcc GCC_US 4068 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4105 clock-names = "cfg_no 4069 clock-names = "cfg_noc",
4106 "core", 4070 "core",
4107 "iface" 4071 "iface",
4108 "sleep" 4072 "sleep",
4109 "mock_u 4073 "mock_utmi";
4110 4074
4111 assigned-clocks = <&g 4075 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 4076 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 4077 assigned-clock-rates = <19200000>, <150000000>;
4114 4078
4115 interrupts-extended = !! 4079 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 4080 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 4081 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 4082 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 4083 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 4084 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 4085
4126 power-domains = <&gcc 4086 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 4087
4128 resets = <&gcc GCC_US 4088 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 4089
4130 interconnects = <&agg 4090 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 4091 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 4092 interconnect-names = "usb-ddr", "apps-usb";
4133 4093
4134 usb_1_dwc3: usb@a6000 4094 usb_1_dwc3: usb@a600000 {
4135 compatible = 4095 compatible = "snps,dwc3";
4136 reg = <0 0x0a 4096 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 4097 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 4098 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 4099 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 4100 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 4101 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 4102 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 4103 };
4165 }; 4104 };
4166 4105
4167 usb_2: usb@a8f8800 { 4106 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 4107 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 4108 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 4109 status = "disabled";
4171 #address-cells = <2>; 4110 #address-cells = <2>;
4172 #size-cells = <2>; 4111 #size-cells = <2>;
4173 ranges; 4112 ranges;
4174 dma-ranges; 4113 dma-ranges;
4175 4114
4176 clocks = <&gcc GCC_CF 4115 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 4116 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 4117 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US 4118 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4180 <&gcc GCC_US 4119 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4181 clock-names = "cfg_no 4120 clock-names = "cfg_noc",
4182 "core", 4121 "core",
4183 "iface" 4122 "iface",
4184 "sleep" 4123 "sleep",
4185 "mock_u 4124 "mock_utmi";
4186 4125
4187 assigned-clocks = <&g 4126 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 4127 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 4128 assigned-clock-rates = <19200000>, <150000000>;
4190 4129
4191 interrupts-extended = !! 4130 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 4131 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 4132 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 4133 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 4134 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 4135 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 4136
4202 power-domains = <&gcc 4137 power-domains = <&gcc USB30_SEC_GDSC>;
4203 4138
4204 resets = <&gcc GCC_US 4139 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 4140
4206 interconnects = <&agg 4141 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 4142 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 4143 interconnect-names = "usb-ddr", "apps-usb";
4209 4144
4210 usb_2_dwc3: usb@a8000 4145 usb_2_dwc3: usb@a800000 {
4211 compatible = 4146 compatible = "snps,dwc3";
4212 reg = <0 0x0a 4147 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 4148 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 4149 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 4150 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 4151 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 4152 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 4153 phy-names = "usb2-phy", "usb3-phy";
4220 }; 4154 };
4221 }; 4155 };
4222 4156
4223 venus: video-codec@aa00000 { 4157 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 4158 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 4159 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 4160 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 4161 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 4162 <&videocc VCODEC0_GDSC>,
4229 <&vid 4163 <&videocc VCODEC1_GDSC>,
4230 <&rpm 4164 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 4165 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 4166 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 4167 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 4168 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 4169 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 4170 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 4171 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 4172 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 4173 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 4174 clock-names = "core", "iface", "bus",
4241 "vcodec 4175 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 4176 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 4177 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 4178 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 4179 memory-region = <&venus_mem>;
4246 interconnects = <&mms 4180 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 4181 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 4182 interconnect-names = "video-mem", "cpu-cfg";
4249 4183
4250 status = "disabled"; 4184 status = "disabled";
4251 4185
4252 video-core0 { 4186 video-core0 {
4253 compatible = 4187 compatible = "venus-decoder";
4254 }; 4188 };
4255 4189
4256 video-core1 { 4190 video-core1 {
4257 compatible = 4191 compatible = "venus-encoder";
4258 }; 4192 };
4259 4193
4260 venus_opp_table: opp- 4194 venus_opp_table: opp-table {
4261 compatible = 4195 compatible = "operating-points-v2";
4262 4196
4263 opp-100000000 4197 opp-100000000 {
4264 opp-h 4198 opp-hz = /bits/ 64 <100000000>;
4265 requi 4199 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 4200 };
4267 4201
4268 opp-200000000 4202 opp-200000000 {
4269 opp-h 4203 opp-hz = /bits/ 64 <200000000>;
4270 requi 4204 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 4205 };
4272 4206
4273 opp-320000000 4207 opp-320000000 {
4274 opp-h 4208 opp-hz = /bits/ 64 <320000000>;
4275 requi 4209 required-opps = <&rpmhpd_opp_svs>;
4276 }; 4210 };
4277 4211
4278 opp-380000000 4212 opp-380000000 {
4279 opp-h 4213 opp-hz = /bits/ 64 <380000000>;
4280 requi 4214 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 4215 };
4282 4216
4283 opp-444000000 4217 opp-444000000 {
4284 opp-h 4218 opp-hz = /bits/ 64 <444000000>;
4285 requi 4219 required-opps = <&rpmhpd_opp_nom>;
4286 }; 4220 };
4287 4221
4288 opp-533000097 4222 opp-533000097 {
4289 opp-h 4223 opp-hz = /bits/ 64 <533000097>;
4290 requi 4224 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 4225 };
4292 }; 4226 };
4293 }; 4227 };
4294 4228
4295 videocc: clock-controller@ab0 4229 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 4230 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 4231 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 4232 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 4233 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 4234 #clock-cells = <1>;
4301 #power-domain-cells = 4235 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 4236 #reset-cells = <1>;
4303 }; 4237 };
4304 4238
4305 camss: camss@acb3000 { !! 4239 camss: camss@a00000 {
4306 compatible = "qcom,sd 4240 compatible = "qcom,sdm845-camss";
4307 4241
4308 reg = <0 0x0acb3000 0 !! 4242 reg = <0 0xacb3000 0 0x1000>,
4309 <0 0x0acba000 !! 4243 <0 0xacba000 0 0x1000>,
4310 <0 0x0acc8000 !! 4244 <0 0xacc8000 0 0x1000>,
4311 <0 0x0ac65000 !! 4245 <0 0xac65000 0 0x1000>,
4312 <0 0x0ac66000 !! 4246 <0 0xac66000 0 0x1000>,
4313 <0 0x0ac67000 !! 4247 <0 0xac67000 0 0x1000>,
4314 <0 0x0ac68000 !! 4248 <0 0xac68000 0 0x1000>,
4315 <0 0x0acaf000 !! 4249 <0 0xacaf000 0 0x4000>,
4316 <0 0x0acb6000 !! 4250 <0 0xacb6000 0 0x4000>,
4317 <0 0x0acc4000 !! 4251 <0 0xacc4000 0 0x4000>;
4318 reg-names = "csid0", 4252 reg-names = "csid0",
4319 "csid1", 4253 "csid1",
4320 "csid2", 4254 "csid2",
4321 "csiphy0", 4255 "csiphy0",
4322 "csiphy1", 4256 "csiphy1",
4323 "csiphy2", 4257 "csiphy2",
4324 "csiphy3", 4258 "csiphy3",
4325 "vfe0", 4259 "vfe0",
4326 "vfe1", 4260 "vfe1",
4327 "vfe_lite"; 4261 "vfe_lite";
4328 4262
4329 interrupts = <GIC_SPI 4263 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 4264 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 4265 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 4266 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 4267 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 4268 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 4269 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 4270 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 4271 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 4272 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 4273 interrupt-names = "csid0",
4340 "csid1", 4274 "csid1",
4341 "csid2", 4275 "csid2",
4342 "csiphy0", 4276 "csiphy0",
4343 "csiphy1", 4277 "csiphy1",
4344 "csiphy2", 4278 "csiphy2",
4345 "csiphy3", 4279 "csiphy3",
4346 "vfe0", 4280 "vfe0",
4347 "vfe1", 4281 "vfe1",
4348 "vfe_lite"; 4282 "vfe_lite";
4349 4283
4350 power-domains = <&clo 4284 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 4285 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 4286 <&clock_camcc TITAN_TOP_GDSC>;
4353 4287
4354 clocks = <&clock_camc 4288 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 4289 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 4290 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 4291 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 4292 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 4293 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 4294 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 4295 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 4296 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 4297 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 4298 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 4299 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 4300 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 4301 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 4302 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 4303 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 4304 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 4305 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 4306 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 4307 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 4308 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 4309 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 4310 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 4311 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 4312 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 4313 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 4314 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4315 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4316 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4317 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4318 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4319 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4320 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4321 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4322 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4323 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4324 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4325 "cpas_ahb",
4392 "cphy_rx_src" 4326 "cphy_rx_src",
4393 "csi0", 4327 "csi0",
4394 "csi0_src", 4328 "csi0_src",
4395 "csi1", 4329 "csi1",
4396 "csi1_src", 4330 "csi1_src",
4397 "csi2", 4331 "csi2",
4398 "csi2_src", 4332 "csi2_src",
4399 "csiphy0", 4333 "csiphy0",
4400 "csiphy0_time 4334 "csiphy0_timer",
4401 "csiphy0_time 4335 "csiphy0_timer_src",
4402 "csiphy1", 4336 "csiphy1",
4403 "csiphy1_time 4337 "csiphy1_timer",
4404 "csiphy1_time 4338 "csiphy1_timer_src",
4405 "csiphy2", 4339 "csiphy2",
4406 "csiphy2_time 4340 "csiphy2_timer",
4407 "csiphy2_time 4341 "csiphy2_timer_src",
4408 "csiphy3", 4342 "csiphy3",
4409 "csiphy3_time 4343 "csiphy3_timer",
4410 "csiphy3_time 4344 "csiphy3_timer_src",
4411 "gcc_camera_a 4345 "gcc_camera_ahb",
4412 "gcc_camera_a 4346 "gcc_camera_axi",
4413 "slow_ahb_src 4347 "slow_ahb_src",
4414 "soc_ahb", 4348 "soc_ahb",
4415 "vfe0_axi", 4349 "vfe0_axi",
4416 "vfe0", 4350 "vfe0",
4417 "vfe0_cphy_rx 4351 "vfe0_cphy_rx",
4418 "vfe0_src", 4352 "vfe0_src",
4419 "vfe1_axi", 4353 "vfe1_axi",
4420 "vfe1", 4354 "vfe1",
4421 "vfe1_cphy_rx 4355 "vfe1_cphy_rx",
4422 "vfe1_src", 4356 "vfe1_src",
4423 "vfe_lite", 4357 "vfe_lite",
4424 "vfe_lite_cph 4358 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4359 "vfe_lite_src";
4426 4360
4427 iommus = <&apps_smmu 4361 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4362 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4363 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4364 <&apps_smmu 0x0c10 0x8>;
4431 4365
4432 status = "disabled"; 4366 status = "disabled";
4433 4367
4434 ports { 4368 ports {
4435 #address-cell 4369 #address-cells = <1>;
4436 #size-cells = 4370 #size-cells = <0>;
4437 4371
4438 port@0 { 4372 port@0 {
4439 reg = 4373 reg = <0>;
4440 }; 4374 };
4441 4375
4442 port@1 { 4376 port@1 {
4443 reg = 4377 reg = <1>;
4444 }; 4378 };
4445 4379
4446 port@2 { 4380 port@2 {
4447 reg = 4381 reg = <2>;
4448 }; 4382 };
4449 4383
4450 port@3 { 4384 port@3 {
4451 reg = 4385 reg = <3>;
4452 }; 4386 };
4453 }; 4387 };
4454 }; 4388 };
4455 4389
4456 cci: cci@ac4a000 { 4390 cci: cci@ac4a000 {
4457 compatible = "qcom,sd !! 4391 compatible = "qcom,sdm845-cci";
4458 #address-cells = <1>; 4392 #address-cells = <1>;
4459 #size-cells = <0>; 4393 #size-cells = <0>;
4460 4394
4461 reg = <0 0x0ac4a000 0 4395 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4396 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4397 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4398
4465 clocks = <&clock_camc 4399 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4400 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4401 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4402 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4403 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4404 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4405 clock-names = "camnoc_axi",
4472 "soc_ahb", 4406 "soc_ahb",
4473 "slow_ahb_src 4407 "slow_ahb_src",
4474 "cpas_ahb", 4408 "cpas_ahb",
4475 "cci", 4409 "cci",
4476 "cci_src"; 4410 "cci_src";
4477 4411
4478 assigned-clocks = <&c 4412 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4413 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4414 assigned-clock-rates = <80000000>, <37500000>;
4481 4415
4482 pinctrl-names = "defa 4416 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4417 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4418 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4419
4486 status = "disabled"; 4420 status = "disabled";
4487 4421
4488 cci_i2c0: i2c-bus@0 { 4422 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4423 reg = <0>;
4490 clock-frequen 4424 clock-frequency = <1000000>;
4491 #address-cell 4425 #address-cells = <1>;
4492 #size-cells = 4426 #size-cells = <0>;
4493 }; 4427 };
4494 4428
4495 cci_i2c1: i2c-bus@1 { 4429 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4430 reg = <1>;
4497 clock-frequen 4431 clock-frequency = <1000000>;
4498 #address-cell 4432 #address-cells = <1>;
4499 #size-cells = 4433 #size-cells = <0>;
4500 }; 4434 };
4501 }; 4435 };
4502 4436
4503 clock_camcc: clock-controller 4437 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4438 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4439 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4440 #clock-cells = <1>;
4507 #reset-cells = <1>; 4441 #reset-cells = <1>;
4508 #power-domain-cells = 4442 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM 4443 clocks = <&rpmhcc RPMH_CXO_CLK>;
4510 clock-names = "bi_tcx 4444 clock-names = "bi_tcxo";
4511 }; 4445 };
4512 4446
4513 mdss: display-subsystem@ae000 !! 4447 dsi_opp_table: opp-table-dsi {
>> 4448 compatible = "operating-points-v2";
>> 4449
>> 4450 opp-19200000 {
>> 4451 opp-hz = /bits/ 64 <19200000>;
>> 4452 required-opps = <&rpmhpd_opp_min_svs>;
>> 4453 };
>> 4454
>> 4455 opp-180000000 {
>> 4456 opp-hz = /bits/ 64 <180000000>;
>> 4457 required-opps = <&rpmhpd_opp_low_svs>;
>> 4458 };
>> 4459
>> 4460 opp-275000000 {
>> 4461 opp-hz = /bits/ 64 <275000000>;
>> 4462 required-opps = <&rpmhpd_opp_svs>;
>> 4463 };
>> 4464
>> 4465 opp-328580000 {
>> 4466 opp-hz = /bits/ 64 <328580000>;
>> 4467 required-opps = <&rpmhpd_opp_svs_l1>;
>> 4468 };
>> 4469
>> 4470 opp-358000000 {
>> 4471 opp-hz = /bits/ 64 <358000000>;
>> 4472 required-opps = <&rpmhpd_opp_nom>;
>> 4473 };
>> 4474 };
>> 4475
>> 4476 mdss: mdss@ae00000 {
4514 compatible = "qcom,sd 4477 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4478 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4479 reg-names = "mdss";
4517 4480
4518 power-domains = <&dis 4481 power-domains = <&dispcc MDSS_GDSC>;
4519 4482
4520 clocks = <&dispcc DIS 4483 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521 <&dispcc DIS 4484 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" 4485 clock-names = "iface", "core";
4523 4486
4524 interrupts = <GIC_SPI 4487 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4488 interrupt-controller;
4526 #interrupt-cells = <1 4489 #interrupt-cells = <1>;
4527 4490
4528 interconnects = <&mms 4491 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4492 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4493 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4494
4532 iommus = <&apps_smmu 4495 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4496 <&apps_smmu 0xc80 0x8>;
4534 4497
4535 status = "disabled"; 4498 status = "disabled";
4536 4499
4537 #address-cells = <2>; 4500 #address-cells = <2>;
4538 #size-cells = <2>; 4501 #size-cells = <2>;
4539 ranges; 4502 ranges;
4540 4503
4541 mdss_mdp: display-con 4504 mdss_mdp: display-controller@ae01000 {
4542 compatible = 4505 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4506 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4507 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4508 reg-names = "mdp", "vbif";
4546 4509
4547 clocks = <&gc 4510 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548 <&di 4511 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549 <&di 4512 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4513 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4514 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = 4515 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553 4516
4554 assigned-cloc 4517 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555 assigned-cloc 4518 assigned-clock-rates = <19200000>;
4556 operating-poi 4519 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4520 power-domains = <&rpmhpd SDM845_CX>;
4558 4521
4559 interrupt-par 4522 interrupt-parent = <&mdss>;
4560 interrupts = 4523 interrupts = <0>;
4561 4524
4562 ports { 4525 ports {
4563 #addr 4526 #address-cells = <1>;
4564 #size 4527 #size-cells = <0>;
4565 4528
4566 port@ 4529 port@0 {
4567 4530 reg = <0>;
4568 4531 dpu_intf0_out: endpoint {
4569 4532 remote-endpoint = <&dp_in>;
4570 4533 };
4571 }; 4534 };
4572 4535
4573 port@ 4536 port@1 {
4574 4537 reg = <1>;
4575 4538 dpu_intf1_out: endpoint {
4576 !! 4539 remote-endpoint = <&dsi0_in>;
4577 4540 };
4578 }; 4541 };
4579 4542
4580 port@ 4543 port@2 {
4581 4544 reg = <2>;
4582 4545 dpu_intf2_out: endpoint {
4583 !! 4546 remote-endpoint = <&dsi1_in>;
4584 4547 };
4585 }; 4548 };
4586 }; 4549 };
4587 4550
4588 mdp_opp_table 4551 mdp_opp_table: opp-table {
4589 compa 4552 compatible = "operating-points-v2";
4590 4553
4591 opp-1 4554 opp-19200000 {
4592 4555 opp-hz = /bits/ 64 <19200000>;
4593 4556 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4557 };
4595 4558
4596 opp-1 4559 opp-171428571 {
4597 4560 opp-hz = /bits/ 64 <171428571>;
4598 4561 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4562 };
4600 4563
4601 opp-3 4564 opp-344000000 {
4602 4565 opp-hz = /bits/ 64 <344000000>;
4603 4566 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4567 };
4605 4568
4606 opp-4 4569 opp-430000000 {
4607 4570 opp-hz = /bits/ 64 <430000000>;
4608 4571 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4572 };
4610 }; 4573 };
4611 }; 4574 };
4612 4575
4613 mdss_dp: displayport- 4576 mdss_dp: displayport-controller@ae90000 {
4614 status = "dis 4577 status = "disabled";
4615 compatible = 4578 compatible = "qcom,sdm845-dp";
4616 4579
4617 reg = <0 0x0a !! 4580 reg = <0 0xae90000 0 0x200>,
4618 <0 0x0a !! 4581 <0 0xae90200 0 0x200>,
4619 <0 0x0a !! 4582 <0 0xae90400 0 0x600>,
4620 <0 0x0a !! 4583 <0 0xae90a00 0 0x600>,
4621 <0 0x0a !! 4584 <0 0xae91000 0 0x600>;
4622 4585
4623 interrupt-par 4586 interrupt-parent = <&mdss>;
4624 interrupts = 4587 interrupts = <12>;
4625 4588
4626 clocks = <&di 4589 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4627 <&di 4590 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4628 <&di 4591 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4629 <&di 4592 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4630 <&di 4593 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4631 clock-names = 4594 clock-names = "core_iface", "core_aux", "ctrl_link",
4632 4595 "ctrl_link_iface", "stream_pixel";
4633 assigned-cloc 4596 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4634 4597 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4635 assigned-cloc !! 4598 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4636 !! 4599 phys = <&dp_phy>;
4637 phys = <&usb_ <<
4638 phy-names = " 4600 phy-names = "dp";
4639 4601
4640 operating-poi 4602 operating-points-v2 = <&dp_opp_table>;
4641 power-domains 4603 power-domains = <&rpmhpd SDM845_CX>;
4642 4604
4643 ports { 4605 ports {
4644 #addr 4606 #address-cells = <1>;
4645 #size 4607 #size-cells = <0>;
4646 port@ 4608 port@0 {
4647 4609 reg = <0>;
4648 4610 dp_in: endpoint {
4649 4611 remote-endpoint = <&dpu_intf0_out>;
4650 4612 };
4651 }; 4613 };
4652 4614
4653 port@ 4615 port@1 {
4654 4616 reg = <1>;
4655 !! 4617 dp_out: endpoint { };
4656 <<
4657 <<
4658 }; 4618 };
4659 }; 4619 };
4660 4620
4661 dp_opp_table: !! 4621 dp_opp_table: dp-opp-table {
4662 compa 4622 compatible = "operating-points-v2";
4663 4623
4664 opp-1 4624 opp-162000000 {
4665 4625 opp-hz = /bits/ 64 <162000000>;
4666 4626 required-opps = <&rpmhpd_opp_low_svs>;
4667 }; 4627 };
4668 4628
4669 opp-2 4629 opp-270000000 {
4670 4630 opp-hz = /bits/ 64 <270000000>;
4671 4631 required-opps = <&rpmhpd_opp_svs>;
4672 }; 4632 };
4673 4633
4674 opp-5 4634 opp-540000000 {
4675 4635 opp-hz = /bits/ 64 <540000000>;
4676 4636 required-opps = <&rpmhpd_opp_svs_l1>;
4677 }; 4637 };
4678 4638
4679 opp-8 4639 opp-810000000 {
4680 4640 opp-hz = /bits/ 64 <810000000>;
4681 4641 required-opps = <&rpmhpd_opp_nom>;
4682 }; 4642 };
4683 }; 4643 };
4684 }; 4644 };
4685 4645
4686 mdss_dsi0: dsi@ae9400 !! 4646 dsi0: dsi@ae94000 {
4687 compatible = !! 4647 compatible = "qcom,mdss-dsi-ctrl";
4688 <<
4689 reg = <0 0x0a 4648 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4649 reg-names = "dsi_ctrl";
4691 4650
4692 interrupt-par 4651 interrupt-parent = <&mdss>;
4693 interrupts = 4652 interrupts = <4>;
4694 4653
4695 clocks = <&di 4654 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4655 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4656 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4657 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4658 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4659 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4660 clock-names = "byte",
4702 4661 "byte_intf",
4703 4662 "pixel",
4704 4663 "core",
4705 4664 "iface",
4706 4665 "bus";
4707 assigned-cloc 4666 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-cloc !! 4667 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4709 4668
4710 operating-poi 4669 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4670 power-domains = <&rpmhpd SDM845_CX>;
4712 4671
4713 phys = <&mdss !! 4672 phys = <&dsi0_phy>;
4714 4673
4715 status = "dis 4674 status = "disabled";
4716 4675
4717 #address-cell 4676 #address-cells = <1>;
4718 #size-cells = 4677 #size-cells = <0>;
4719 4678
4720 ports { 4679 ports {
4721 #addr 4680 #address-cells = <1>;
4722 #size 4681 #size-cells = <0>;
4723 4682
4724 port@ 4683 port@0 {
4725 4684 reg = <0>;
4726 !! 4685 dsi0_in: endpoint {
4727 4686 remote-endpoint = <&dpu_intf1_out>;
4728 4687 };
4729 }; 4688 };
4730 4689
4731 port@ 4690 port@1 {
4732 4691 reg = <1>;
4733 !! 4692 dsi0_out: endpoint {
4734 4693 };
4735 }; 4694 };
4736 }; 4695 };
4737 }; 4696 };
4738 4697
4739 mdss_dsi0_phy: phy@ae !! 4698 dsi0_phy: phy@ae94400 {
4740 compatible = 4699 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4700 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4701 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4702 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4703 reg-names = "dsi_phy",
4745 " 4704 "dsi_phy_lane",
4746 " 4705 "dsi_pll";
4747 4706
4748 #clock-cells 4707 #clock-cells = <1>;
4749 #phy-cells = 4708 #phy-cells = <0>;
4750 4709
4751 clocks = <&di 4710 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4711 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4712 clock-names = "iface", "ref";
4754 4713
4755 status = "dis 4714 status = "disabled";
4756 }; 4715 };
4757 4716
4758 mdss_dsi1: dsi@ae9600 !! 4717 dsi1: dsi@ae96000 {
4759 compatible = !! 4718 compatible = "qcom,mdss-dsi-ctrl";
4760 <<
4761 reg = <0 0x0a 4719 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4720 reg-names = "dsi_ctrl";
4763 4721
4764 interrupt-par 4722 interrupt-parent = <&mdss>;
4765 interrupts = 4723 interrupts = <5>;
4766 4724
4767 clocks = <&di 4725 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4726 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4727 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4728 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4729 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4730 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4731 clock-names = "byte",
4774 4732 "byte_intf",
4775 4733 "pixel",
4776 4734 "core",
4777 4735 "iface",
4778 4736 "bus";
4779 assigned-cloc 4737 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-cloc !! 4738 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4781 4739
4782 operating-poi 4740 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4741 power-domains = <&rpmhpd SDM845_CX>;
4784 4742
4785 phys = <&mdss !! 4743 phys = <&dsi1_phy>;
4786 4744
4787 status = "dis 4745 status = "disabled";
4788 4746
4789 #address-cell 4747 #address-cells = <1>;
4790 #size-cells = 4748 #size-cells = <0>;
4791 4749
4792 ports { 4750 ports {
4793 #addr 4751 #address-cells = <1>;
4794 #size 4752 #size-cells = <0>;
4795 4753
4796 port@ 4754 port@0 {
4797 4755 reg = <0>;
4798 !! 4756 dsi1_in: endpoint {
4799 4757 remote-endpoint = <&dpu_intf2_out>;
4800 4758 };
4801 }; 4759 };
4802 4760
4803 port@ 4761 port@1 {
4804 4762 reg = <1>;
4805 !! 4763 dsi1_out: endpoint {
4806 4764 };
4807 }; 4765 };
4808 }; 4766 };
4809 }; 4767 };
4810 4768
4811 mdss_dsi1_phy: phy@ae !! 4769 dsi1_phy: phy@ae96400 {
4812 compatible = 4770 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4771 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4772 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4773 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4774 reg-names = "dsi_phy",
4817 " 4775 "dsi_phy_lane",
4818 " 4776 "dsi_pll";
4819 4777
4820 #clock-cells 4778 #clock-cells = <1>;
4821 #phy-cells = 4779 #phy-cells = <0>;
4822 4780
4823 clocks = <&di 4781 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4782 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4783 clock-names = "iface", "ref";
4826 4784
4827 status = "dis 4785 status = "disabled";
4828 }; 4786 };
4829 }; 4787 };
4830 4788
4831 gpu: gpu@5000000 { 4789 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4790 compatible = "qcom,adreno-630.2", "qcom,adreno";
4833 4791
4834 reg = <0 0x05000000 0 !! 4792 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4793 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4794
4837 /* 4795 /*
4838 * Look ma, no clocks 4796 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4797 * controlled entirely by the GMU
4840 */ 4798 */
4841 4799
4842 interrupts = <GIC_SPI 4800 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4801
4844 iommus = <&adreno_smm 4802 iommus = <&adreno_smmu 0>;
4845 4803
4846 operating-points-v2 = 4804 operating-points-v2 = <&gpu_opp_table>;
4847 4805
4848 qcom,gmu = <&gmu>; 4806 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4807
4851 interconnects = <&mem 4808 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4809 interconnect-names = "gfx-mem";
4853 4810
4854 status = "disabled"; 4811 status = "disabled";
4855 4812
4856 gpu_opp_table: opp-ta 4813 gpu_opp_table: opp-table {
4857 compatible = 4814 compatible = "operating-points-v2";
4858 4815
4859 opp-710000000 4816 opp-710000000 {
4860 opp-h 4817 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4818 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4819 opp-peak-kBps = <7216000>;
4863 }; 4820 };
4864 4821
4865 opp-675000000 4822 opp-675000000 {
4866 opp-h 4823 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4824 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4825 opp-peak-kBps = <7216000>;
4869 }; 4826 };
4870 4827
4871 opp-596000000 4828 opp-596000000 {
4872 opp-h 4829 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4831 opp-peak-kBps = <6220000>;
4875 }; 4832 };
4876 4833
4877 opp-520000000 4834 opp-520000000 {
4878 opp-h 4835 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4836 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4837 opp-peak-kBps = <6220000>;
4881 }; 4838 };
4882 4839
4883 opp-414000000 4840 opp-414000000 {
4884 opp-h 4841 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4842 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4843 opp-peak-kBps = <4068000>;
4887 }; 4844 };
4888 4845
4889 opp-342000000 4846 opp-342000000 {
4890 opp-h 4847 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4848 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4849 opp-peak-kBps = <2724000>;
4893 }; 4850 };
4894 4851
4895 opp-257000000 4852 opp-257000000 {
4896 opp-h 4853 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4854 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4855 opp-peak-kBps = <1648000>;
4899 }; 4856 };
4900 }; 4857 };
4901 }; 4858 };
4902 4859
4903 adreno_smmu: iommu@5040000 { 4860 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4861 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 !! 4862 reg = <0 0x5040000 0 0x10000>;
4906 #iommu-cells = <1>; 4863 #iommu-cells = <1>;
4907 #global-interrupts = 4864 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4865 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4866 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4867 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4868 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4869 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4870 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4871 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4872 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4873 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4874 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4875 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4876 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4877 clock-names = "bus", "iface";
4921 4878
4922 power-domains = <&gpu 4879 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4880 };
4924 4881
4925 gmu: gmu@506a000 { 4882 gmu: gmu@506a000 {
4926 compatible = "qcom,ad 4883 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4884
4928 reg = <0 0x0506a000 0 !! 4885 reg = <0 0x506a000 0 0x30000>,
4929 <0 0x0b280000 0 !! 4886 <0 0xb280000 0 0x10000>,
4930 <0 0x0b480000 0 !! 4887 <0 0xb480000 0 0x10000>;
4931 reg-names = "gmu", "g 4888 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4889
4933 interrupts = <GIC_SPI 4890 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4891 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4892 interrupt-names = "hfi", "gmu";
4936 4893
4937 clocks = <&gpucc GPU_ 4894 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4895 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4896 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4897 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4898 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4899
4943 power-domains = <&gpu 4900 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4901 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4902 power-domain-names = "cx", "gx";
4946 4903
4947 iommus = <&adreno_smm 4904 iommus = <&adreno_smmu 5>;
4948 4905
4949 operating-points-v2 = 4906 operating-points-v2 = <&gmu_opp_table>;
4950 4907
4951 status = "disabled"; 4908 status = "disabled";
4952 4909
4953 gmu_opp_table: opp-ta 4910 gmu_opp_table: opp-table {
4954 compatible = 4911 compatible = "operating-points-v2";
4955 4912
4956 opp-400000000 4913 opp-400000000 {
4957 opp-h 4914 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4915 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4916 };
4960 4917
4961 opp-200000000 4918 opp-200000000 {
4962 opp-h 4919 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4920 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4921 };
4965 }; 4922 };
4966 }; 4923 };
4967 4924
4968 dispcc: clock-controller@af00 4925 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4926 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4927 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4928 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4929 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4930 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ !! 4931 <&dsi0_phy 0>,
4975 <&mdss_dsi0_ !! 4932 <&dsi0_phy 1>,
4976 <&mdss_dsi1_ !! 4933 <&dsi1_phy 0>,
4977 <&mdss_dsi1_ !! 4934 <&dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4935 <&dp_phy 0>,
4979 <&usb_1_qmpp !! 4936 <&dp_phy 1>;
4980 clock-names = "bi_tcx 4937 clock-names = "bi_tcxo",
4981 "gcc_di 4938 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4939 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4940 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4941 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4942 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4943 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4944 "dp_link_clk_divsel_ten",
4988 "dp_vco 4945 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4946 #clock-cells = <1>;
4990 #reset-cells = <1>; 4947 #reset-cells = <1>;
4991 #power-domain-cells = 4948 #power-domain-cells = <1>;
4992 }; 4949 };
4993 4950
4994 pdc_intc: interrupt-controlle 4951 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4952 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4953 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4954 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4955 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4956 interrupt-parent = <&intc>;
5000 interrupt-controller; 4957 interrupt-controller;
5001 }; 4958 };
5002 4959
5003 pdc_reset: reset-controller@b 4960 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4961 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4962 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4963 #reset-cells = <1>;
5007 }; 4964 };
5008 4965
5009 tsens0: thermal-sensor@c26300 4966 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4967 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4968 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4969 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4970 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4971 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4972 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4973 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4974 #thermal-sensor-cells = <1>;
5018 }; 4975 };
5019 4976
5020 tsens1: thermal-sensor@c26500 4977 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4978 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4979 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4980 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4981 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4982 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4983 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4984 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4985 #thermal-sensor-cells = <1>;
5029 }; 4986 };
5030 4987
5031 aoss_reset: reset-controller@ 4988 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4989 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4990 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4991 #reset-cells = <1>;
5035 }; 4992 };
5036 4993
5037 aoss_qmp: power-management@c3 !! 4994 aoss_qmp: power-controller@c300000 {
5038 compatible = "qcom,sd 4995 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039 reg = <0 0x0c300000 0 4996 reg = <0 0x0c300000 0 0x400>;
5040 interrupts = <GIC_SPI 4997 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4998 mboxes = <&apss_shared 0>;
5042 4999
5043 #clock-cells = <0>; 5000 #clock-cells = <0>;
5044 5001
5045 cx_cdev: cx { 5002 cx_cdev: cx {
5046 #cooling-cell 5003 #cooling-cells = <2>;
5047 }; 5004 };
5048 5005
5049 ebi_cdev: ebi { 5006 ebi_cdev: ebi {
5050 #cooling-cell 5007 #cooling-cells = <2>;
5051 }; 5008 };
5052 }; 5009 };
5053 5010
5054 sram@c3f0000 { 5011 sram@c3f0000 {
5055 compatible = "qcom,sd 5012 compatible = "qcom,sdm845-rpmh-stats";
5056 reg = <0 0x0c3f0000 0 5013 reg = <0 0x0c3f0000 0 0x400>;
5057 }; 5014 };
5058 5015
5059 spmi_bus: spmi@c440000 { 5016 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 5017 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 5018 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 5019 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 5020 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 5021 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 5022 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 5023 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 5024 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 5025 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 5026 qcom,ee = <0>;
5070 qcom,channel = <0>; 5027 qcom,channel = <0>;
5071 #address-cells = <2>; 5028 #address-cells = <2>;
5072 #size-cells = <0>; 5029 #size-cells = <0>;
5073 interrupt-controller; 5030 interrupt-controller;
5074 #interrupt-cells = <4 5031 #interrupt-cells = <4>;
>> 5032 cell-index = <0>;
5075 }; 5033 };
5076 5034
5077 sram@146bf000 { 5035 sram@146bf000 {
5078 compatible = "qcom,sd 5036 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5079 reg = <0 0x146bf000 0 5037 reg = <0 0x146bf000 0 0x1000>;
5080 5038
5081 #address-cells = <1>; 5039 #address-cells = <1>;
5082 #size-cells = <1>; 5040 #size-cells = <1>;
5083 5041
5084 ranges = <0 0 0x146bf 5042 ranges = <0 0 0x146bf000 0x1000>;
5085 5043
5086 pil-reloc@94c { 5044 pil-reloc@94c {
5087 compatible = 5045 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 5046 reg = <0x94c 0xc8>;
5089 }; 5047 };
5090 }; 5048 };
5091 5049
5092 apps_smmu: iommu@15000000 { 5050 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 5051 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 5052 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 5053 #iommu-cells = <2>;
5096 #global-interrupts = 5054 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 5055 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 5056 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 5057 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 5058 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 5059 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 5060 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 5061 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 5062 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 5063 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 5064 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 5065 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 5066 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 5067 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 5068 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 5069 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 5070 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 5071 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 5072 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 5073 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 5074 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 5075 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 5076 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 5077 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 5078 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 5079 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 5080 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 5081 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 5082 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 5083 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 5084 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 5085 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 5086 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 5087 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 5088 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 5089 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 5090 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 5091 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 5092 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 5093 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 5094 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 5095 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 5096 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 5097 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 5098 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 5099 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 5100 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 5101 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 5102 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 5103 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 5104 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 5105 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 5106 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 5107 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 5108 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 5109 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 5110 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 5111 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 5112 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 5113 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 5114 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 5115 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 5116 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 5117 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 5118 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 5119 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 5120 };
5163 5121
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 5122 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 5123 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 5124 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 5125 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 5126 #clock-cells = <1>;
5241 status = "disabled"; 5127 status = "disabled";
5242 }; 5128 };
5243 5129
5244 gladiator_noc: interconnect@1 5130 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 5131 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 5132 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 5133 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 5134 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 5135 };
5250 5136
5251 watchdog@17980000 { 5137 watchdog@17980000 {
5252 compatible = "qcom,ap 5138 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 5139 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 5140 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI !! 5141 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256 }; 5142 };
5257 5143
5258 apss_shared: mailbox@17990000 5144 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 5145 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 5146 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 5147 #mbox-cells = <1>;
5262 }; 5148 };
5263 5149
5264 apps_rsc: rsc@179c0000 { 5150 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 5151 label = "apps_rsc";
5266 compatible = "qcom,rp 5152 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 5153 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 5154 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 5155 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 5156 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 5157 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 5158 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 5159 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 5160 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 5161 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 5162 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 5163 <SLEEP_TCS 3>,
5278 <WA 5164 <WAKE_TCS 3>,
5279 <CO 5165 <CONTROL_TCS 1>;
5280 power-domains = <&CLU <<
5281 5166
5282 apps_bcm_voter: bcm-v 5167 apps_bcm_voter: bcm-voter {
5283 compatible = 5168 compatible = "qcom,bcm-voter";
5284 }; 5169 };
5285 5170
5286 rpmhcc: clock-control 5171 rpmhcc: clock-controller {
5287 compatible = 5172 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 5173 #clock-cells = <1>;
5289 clock-names = 5174 clock-names = "xo";
5290 clocks = <&xo 5175 clocks = <&xo_board>;
5291 }; 5176 };
5292 5177
5293 rpmhpd: power-control 5178 rpmhpd: power-controller {
5294 compatible = 5179 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 5180 #power-domain-cells = <1>;
5296 operating-poi 5181 operating-points-v2 = <&rpmhpd_opp_table>;
5297 5182
5298 rpmhpd_opp_ta 5183 rpmhpd_opp_table: opp-table {
5299 compa 5184 compatible = "operating-points-v2";
5300 5185
5301 rpmhp 5186 rpmhpd_opp_ret: opp1 {
5302 5187 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 5188 };
5304 5189
5305 rpmhp 5190 rpmhpd_opp_min_svs: opp2 {
5306 5191 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 5192 };
5308 5193
5309 rpmhp 5194 rpmhpd_opp_low_svs: opp3 {
5310 5195 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 5196 };
5312 5197
5313 rpmhp 5198 rpmhpd_opp_svs: opp4 {
5314 5199 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 5200 };
5316 5201
5317 rpmhp 5202 rpmhpd_opp_svs_l1: opp5 {
5318 5203 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 5204 };
5320 5205
5321 rpmhp 5206 rpmhpd_opp_nom: opp6 {
5322 5207 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 5208 };
5324 5209
5325 rpmhp 5210 rpmhpd_opp_nom_l1: opp7 {
5326 5211 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 5212 };
5328 5213
5329 rpmhp 5214 rpmhpd_opp_nom_l2: opp8 {
5330 5215 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 5216 };
5332 5217
5333 rpmhp 5218 rpmhpd_opp_turbo: opp9 {
5334 5219 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 5220 };
5336 5221
5337 rpmhp 5222 rpmhpd_opp_turbo_l1: opp10 {
5338 5223 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 5224 };
5340 }; 5225 };
5341 }; 5226 };
5342 }; 5227 };
5343 5228
5344 intc: interrupt-controller@17 5229 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 5230 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 5231 #address-cells = <2>;
5347 #size-cells = <2>; 5232 #size-cells = <2>;
5348 ranges; 5233 ranges;
5349 #interrupt-cells = <3 5234 #interrupt-cells = <3>;
5350 interrupt-controller; 5235 interrupt-controller;
5351 reg = <0 0x17a00000 0 5236 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 5237 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 5238 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 5239
5355 msi-controller@17a400 5240 msi-controller@17a40000 {
5356 compatible = 5241 compatible = "arm,gic-v3-its";
5357 msi-controlle 5242 msi-controller;
5358 #msi-cells = 5243 #msi-cells = <1>;
5359 reg = <0 0x17 5244 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 5245 status = "disabled";
5361 }; 5246 };
5362 }; 5247 };
5363 5248
5364 slimbam: dma-controller@17184 5249 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba !! 5250 compatible = "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 5251 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 5252 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; 5253 num-channels = <31>;
5369 interrupts = <GIC_SPI 5254 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 5255 #dma-cells = <1>;
5371 qcom,ee = <1>; 5256 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 5257 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 5258 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 5259 };
5375 5260
5376 timer@17c90000 { 5261 timer@17c90000 {
5377 #address-cells = <1>; 5262 #address-cells = <1>;
5378 #size-cells = <1>; 5263 #size-cells = <1>;
5379 ranges = <0 0 0 0x200 5264 ranges = <0 0 0 0x20000000>;
5380 compatible = "arm,arm 5265 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 5266 reg = <0 0x17c90000 0 0x1000>;
5382 5267
5383 frame@17ca0000 { 5268 frame@17ca0000 {
5384 frame-number 5269 frame-number = <0>;
5385 interrupts = 5270 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 5271 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca 5272 reg = <0x17ca0000 0x1000>,
5388 <0x17cb 5273 <0x17cb0000 0x1000>;
5389 }; 5274 };
5390 5275
5391 frame@17cc0000 { 5276 frame@17cc0000 {
5392 frame-number 5277 frame-number = <1>;
5393 interrupts = 5278 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc 5279 reg = <0x17cc0000 0x1000>;
5395 status = "dis 5280 status = "disabled";
5396 }; 5281 };
5397 5282
5398 frame@17cd0000 { 5283 frame@17cd0000 {
5399 frame-number 5284 frame-number = <2>;
5400 interrupts = 5285 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd 5286 reg = <0x17cd0000 0x1000>;
5402 status = "dis 5287 status = "disabled";
5403 }; 5288 };
5404 5289
5405 frame@17ce0000 { 5290 frame@17ce0000 {
5406 frame-number 5291 frame-number = <3>;
5407 interrupts = 5292 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce 5293 reg = <0x17ce0000 0x1000>;
5409 status = "dis 5294 status = "disabled";
5410 }; 5295 };
5411 5296
5412 frame@17cf0000 { 5297 frame@17cf0000 {
5413 frame-number 5298 frame-number = <4>;
5414 interrupts = 5299 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf 5300 reg = <0x17cf0000 0x1000>;
5416 status = "dis 5301 status = "disabled";
5417 }; 5302 };
5418 5303
5419 frame@17d00000 { 5304 frame@17d00000 {
5420 frame-number 5305 frame-number = <5>;
5421 interrupts = 5306 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 5307 reg = <0x17d00000 0x1000>;
5423 status = "dis 5308 status = "disabled";
5424 }; 5309 };
5425 5310
5426 frame@17d10000 { 5311 frame@17d10000 {
5427 frame-number 5312 frame-number = <6>;
5428 interrupts = 5313 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 5314 reg = <0x17d10000 0x1000>;
5430 status = "dis 5315 status = "disabled";
5431 }; 5316 };
5432 }; 5317 };
5433 5318
5434 osm_l3: interconnect@17d41000 5319 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd 5320 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5436 reg = <0 0x17d41000 0 5321 reg = <0 0x17d41000 0 0x1400>;
5437 5322
5438 clocks = <&rpmhcc RPM 5323 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 5324 clock-names = "xo", "alternate";
5440 5325
5441 #interconnect-cells = 5326 #interconnect-cells = <1>;
5442 }; 5327 };
5443 5328
5444 cpufreq_hw: cpufreq@17d43000 5329 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd !! 5330 compatible = "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 5331 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 5332 reg-names = "freq-domain0", "freq-domain1";
5448 5333
5449 interrupts-extended = 5334 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450 5335
5451 clocks = <&rpmhcc RPM 5336 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 5337 clock-names = "xo", "alternate";
5453 5338
5454 #freq-domain-cells = 5339 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; <<
5456 }; 5340 };
5457 5341
5458 wifi: wifi@18800000 { 5342 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 5343 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 5344 status = "disabled";
5461 reg = <0 0x18800000 0 5345 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 5346 reg-names = "membase";
5463 memory-region = <&wla 5347 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 5348 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 5349 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 5350 interrupts =
5467 <GIC_SPI 414 5351 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 5352 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 5353 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 5354 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 5355 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 5356 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 5357 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 5358 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 5359 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 5360 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 5361 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 5362 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 5363 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 5364 };
5481 }; 5365 };
5482 5366
5483 sound: sound { <<
5484 }; <<
5485 <<
5486 thermal-zones { 5367 thermal-zones {
5487 cpu0-thermal { 5368 cpu0-thermal {
5488 polling-delay-passive 5369 polling-delay-passive = <250>;
>> 5370 polling-delay = <1000>;
5489 5371
5490 thermal-sensors = <&t 5372 thermal-sensors = <&tsens0 1>;
5491 5373
5492 trips { 5374 trips {
5493 cpu0_alert0: 5375 cpu0_alert0: trip-point0 {
5494 tempe 5376 temperature = <90000>;
5495 hyste 5377 hysteresis = <2000>;
5496 type 5378 type = "passive";
5497 }; 5379 };
5498 5380
5499 cpu0_alert1: 5381 cpu0_alert1: trip-point1 {
5500 tempe 5382 temperature = <95000>;
5501 hyste 5383 hysteresis = <2000>;
5502 type 5384 type = "passive";
5503 }; 5385 };
5504 5386
5505 cpu0_crit: cp !! 5387 cpu0_crit: cpu_crit {
5506 tempe 5388 temperature = <110000>;
5507 hyste 5389 hysteresis = <1000>;
5508 type 5390 type = "critical";
5509 }; 5391 };
5510 }; 5392 };
5511 }; 5393 };
5512 5394
5513 cpu1-thermal { 5395 cpu1-thermal {
5514 polling-delay-passive 5396 polling-delay-passive = <250>;
>> 5397 polling-delay = <1000>;
5515 5398
5516 thermal-sensors = <&t 5399 thermal-sensors = <&tsens0 2>;
5517 5400
5518 trips { 5401 trips {
5519 cpu1_alert0: 5402 cpu1_alert0: trip-point0 {
5520 tempe 5403 temperature = <90000>;
5521 hyste 5404 hysteresis = <2000>;
5522 type 5405 type = "passive";
5523 }; 5406 };
5524 5407
5525 cpu1_alert1: 5408 cpu1_alert1: trip-point1 {
5526 tempe 5409 temperature = <95000>;
5527 hyste 5410 hysteresis = <2000>;
5528 type 5411 type = "passive";
5529 }; 5412 };
5530 5413
5531 cpu1_crit: cp !! 5414 cpu1_crit: cpu_crit {
5532 tempe 5415 temperature = <110000>;
5533 hyste 5416 hysteresis = <1000>;
5534 type 5417 type = "critical";
5535 }; 5418 };
5536 }; 5419 };
5537 }; 5420 };
5538 5421
5539 cpu2-thermal { 5422 cpu2-thermal {
5540 polling-delay-passive 5423 polling-delay-passive = <250>;
>> 5424 polling-delay = <1000>;
5541 5425
5542 thermal-sensors = <&t 5426 thermal-sensors = <&tsens0 3>;
5543 5427
5544 trips { 5428 trips {
5545 cpu2_alert0: 5429 cpu2_alert0: trip-point0 {
5546 tempe 5430 temperature = <90000>;
5547 hyste 5431 hysteresis = <2000>;
5548 type 5432 type = "passive";
5549 }; 5433 };
5550 5434
5551 cpu2_alert1: 5435 cpu2_alert1: trip-point1 {
5552 tempe 5436 temperature = <95000>;
5553 hyste 5437 hysteresis = <2000>;
5554 type 5438 type = "passive";
5555 }; 5439 };
5556 5440
5557 cpu2_crit: cp !! 5441 cpu2_crit: cpu_crit {
5558 tempe 5442 temperature = <110000>;
5559 hyste 5443 hysteresis = <1000>;
5560 type 5444 type = "critical";
5561 }; 5445 };
5562 }; 5446 };
5563 }; 5447 };
5564 5448
5565 cpu3-thermal { 5449 cpu3-thermal {
5566 polling-delay-passive 5450 polling-delay-passive = <250>;
>> 5451 polling-delay = <1000>;
5567 5452
5568 thermal-sensors = <&t 5453 thermal-sensors = <&tsens0 4>;
5569 5454
5570 trips { 5455 trips {
5571 cpu3_alert0: 5456 cpu3_alert0: trip-point0 {
5572 tempe 5457 temperature = <90000>;
5573 hyste 5458 hysteresis = <2000>;
5574 type 5459 type = "passive";
5575 }; 5460 };
5576 5461
5577 cpu3_alert1: 5462 cpu3_alert1: trip-point1 {
5578 tempe 5463 temperature = <95000>;
5579 hyste 5464 hysteresis = <2000>;
5580 type 5465 type = "passive";
5581 }; 5466 };
5582 5467
5583 cpu3_crit: cp !! 5468 cpu3_crit: cpu_crit {
5584 tempe 5469 temperature = <110000>;
5585 hyste 5470 hysteresis = <1000>;
5586 type 5471 type = "critical";
5587 }; 5472 };
5588 }; 5473 };
5589 }; 5474 };
5590 5475
5591 cpu4-thermal { 5476 cpu4-thermal {
5592 polling-delay-passive 5477 polling-delay-passive = <250>;
>> 5478 polling-delay = <1000>;
5593 5479
5594 thermal-sensors = <&t 5480 thermal-sensors = <&tsens0 7>;
5595 5481
5596 trips { 5482 trips {
5597 cpu4_alert0: 5483 cpu4_alert0: trip-point0 {
5598 tempe 5484 temperature = <90000>;
5599 hyste 5485 hysteresis = <2000>;
5600 type 5486 type = "passive";
5601 }; 5487 };
5602 5488
5603 cpu4_alert1: 5489 cpu4_alert1: trip-point1 {
5604 tempe 5490 temperature = <95000>;
5605 hyste 5491 hysteresis = <2000>;
5606 type 5492 type = "passive";
5607 }; 5493 };
5608 5494
5609 cpu4_crit: cp !! 5495 cpu4_crit: cpu_crit {
5610 tempe 5496 temperature = <110000>;
5611 hyste 5497 hysteresis = <1000>;
5612 type 5498 type = "critical";
5613 }; 5499 };
5614 }; 5500 };
5615 }; 5501 };
5616 5502
5617 cpu5-thermal { 5503 cpu5-thermal {
5618 polling-delay-passive 5504 polling-delay-passive = <250>;
>> 5505 polling-delay = <1000>;
5619 5506
5620 thermal-sensors = <&t 5507 thermal-sensors = <&tsens0 8>;
5621 5508
5622 trips { 5509 trips {
5623 cpu5_alert0: 5510 cpu5_alert0: trip-point0 {
5624 tempe 5511 temperature = <90000>;
5625 hyste 5512 hysteresis = <2000>;
5626 type 5513 type = "passive";
5627 }; 5514 };
5628 5515
5629 cpu5_alert1: 5516 cpu5_alert1: trip-point1 {
5630 tempe 5517 temperature = <95000>;
5631 hyste 5518 hysteresis = <2000>;
5632 type 5519 type = "passive";
5633 }; 5520 };
5634 5521
5635 cpu5_crit: cp !! 5522 cpu5_crit: cpu_crit {
5636 tempe 5523 temperature = <110000>;
5637 hyste 5524 hysteresis = <1000>;
5638 type 5525 type = "critical";
5639 }; 5526 };
5640 }; 5527 };
5641 }; 5528 };
5642 5529
5643 cpu6-thermal { 5530 cpu6-thermal {
5644 polling-delay-passive 5531 polling-delay-passive = <250>;
>> 5532 polling-delay = <1000>;
5645 5533
5646 thermal-sensors = <&t 5534 thermal-sensors = <&tsens0 9>;
5647 5535
5648 trips { 5536 trips {
5649 cpu6_alert0: 5537 cpu6_alert0: trip-point0 {
5650 tempe 5538 temperature = <90000>;
5651 hyste 5539 hysteresis = <2000>;
5652 type 5540 type = "passive";
5653 }; 5541 };
5654 5542
5655 cpu6_alert1: 5543 cpu6_alert1: trip-point1 {
5656 tempe 5544 temperature = <95000>;
5657 hyste 5545 hysteresis = <2000>;
5658 type 5546 type = "passive";
5659 }; 5547 };
5660 5548
5661 cpu6_crit: cp !! 5549 cpu6_crit: cpu_crit {
5662 tempe 5550 temperature = <110000>;
5663 hyste 5551 hysteresis = <1000>;
5664 type 5552 type = "critical";
5665 }; 5553 };
5666 }; 5554 };
5667 }; 5555 };
5668 5556
5669 cpu7-thermal { 5557 cpu7-thermal {
5670 polling-delay-passive 5558 polling-delay-passive = <250>;
>> 5559 polling-delay = <1000>;
5671 5560
5672 thermal-sensors = <&t 5561 thermal-sensors = <&tsens0 10>;
5673 5562
5674 trips { 5563 trips {
5675 cpu7_alert0: 5564 cpu7_alert0: trip-point0 {
5676 tempe 5565 temperature = <90000>;
5677 hyste 5566 hysteresis = <2000>;
5678 type 5567 type = "passive";
5679 }; 5568 };
5680 5569
5681 cpu7_alert1: 5570 cpu7_alert1: trip-point1 {
5682 tempe 5571 temperature = <95000>;
5683 hyste 5572 hysteresis = <2000>;
5684 type 5573 type = "passive";
5685 }; 5574 };
5686 5575
5687 cpu7_crit: cp !! 5576 cpu7_crit: cpu_crit {
5688 tempe 5577 temperature = <110000>;
5689 hyste 5578 hysteresis = <1000>;
5690 type 5579 type = "critical";
5691 }; 5580 };
5692 }; 5581 };
5693 }; 5582 };
5694 5583
5695 aoss0-thermal { 5584 aoss0-thermal {
5696 polling-delay-passive 5585 polling-delay-passive = <250>;
>> 5586 polling-delay = <1000>;
5697 5587
5698 thermal-sensors = <&t 5588 thermal-sensors = <&tsens0 0>;
5699 5589
5700 trips { 5590 trips {
5701 aoss0_alert0: 5591 aoss0_alert0: trip-point0 {
5702 tempe 5592 temperature = <90000>;
5703 hyste 5593 hysteresis = <2000>;
5704 type 5594 type = "hot";
5705 }; 5595 };
5706 }; 5596 };
5707 }; 5597 };
5708 5598
5709 cluster0-thermal { 5599 cluster0-thermal {
5710 polling-delay-passive 5600 polling-delay-passive = <250>;
>> 5601 polling-delay = <1000>;
5711 5602
5712 thermal-sensors = <&t 5603 thermal-sensors = <&tsens0 5>;
5713 5604
5714 trips { 5605 trips {
5715 cluster0_aler 5606 cluster0_alert0: trip-point0 {
5716 tempe 5607 temperature = <90000>;
5717 hyste 5608 hysteresis = <2000>;
5718 type 5609 type = "hot";
5719 }; 5610 };
5720 cluster0_crit !! 5611 cluster0_crit: cluster0_crit {
5721 tempe 5612 temperature = <110000>;
5722 hyste 5613 hysteresis = <2000>;
5723 type 5614 type = "critical";
5724 }; 5615 };
5725 }; 5616 };
5726 }; 5617 };
5727 5618
5728 cluster1-thermal { 5619 cluster1-thermal {
5729 polling-delay-passive 5620 polling-delay-passive = <250>;
>> 5621 polling-delay = <1000>;
5730 5622
5731 thermal-sensors = <&t 5623 thermal-sensors = <&tsens0 6>;
5732 5624
5733 trips { 5625 trips {
5734 cluster1_aler 5626 cluster1_alert0: trip-point0 {
5735 tempe 5627 temperature = <90000>;
5736 hyste 5628 hysteresis = <2000>;
5737 type 5629 type = "hot";
5738 }; 5630 };
5739 cluster1_crit !! 5631 cluster1_crit: cluster1_crit {
5740 tempe 5632 temperature = <110000>;
5741 hyste 5633 hysteresis = <2000>;
5742 type 5634 type = "critical";
5743 }; 5635 };
5744 }; 5636 };
5745 }; 5637 };
5746 5638
5747 gpu-top-thermal { 5639 gpu-top-thermal {
5748 polling-delay-passive 5640 polling-delay-passive = <250>;
>> 5641 polling-delay = <1000>;
5749 5642
5750 thermal-sensors = <&t 5643 thermal-sensors = <&tsens0 11>;
5751 5644
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5645 trips {
5760 gpu_top_alert !! 5646 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5647 temperature = <90000>;
5768 hyste !! 5648 hysteresis = <2000>;
5769 type 5649 type = "hot";
5770 }; 5650 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5651 };
5778 }; 5652 };
5779 5653
5780 gpu-bottom-thermal { 5654 gpu-bottom-thermal {
5781 polling-delay-passive 5655 polling-delay-passive = <250>;
>> 5656 polling-delay = <1000>;
5782 5657
5783 thermal-sensors = <&t 5658 thermal-sensors = <&tsens0 12>;
5784 5659
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5660 trips {
5793 gpu_bottom_al !! 5661 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5662 temperature = <90000>;
5801 hyste !! 5663 hysteresis = <2000>;
5802 type 5664 type = "hot";
5803 }; 5665 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5666 };
5811 }; 5667 };
5812 5668
5813 aoss1-thermal { 5669 aoss1-thermal {
5814 polling-delay-passive 5670 polling-delay-passive = <250>;
>> 5671 polling-delay = <1000>;
5815 5672
5816 thermal-sensors = <&t 5673 thermal-sensors = <&tsens1 0>;
5817 5674
5818 trips { 5675 trips {
5819 aoss1_alert0: 5676 aoss1_alert0: trip-point0 {
5820 tempe 5677 temperature = <90000>;
5821 hyste 5678 hysteresis = <2000>;
5822 type 5679 type = "hot";
5823 }; 5680 };
5824 }; 5681 };
5825 }; 5682 };
5826 5683
5827 q6-modem-thermal { 5684 q6-modem-thermal {
5828 polling-delay-passive 5685 polling-delay-passive = <250>;
>> 5686 polling-delay = <1000>;
5829 5687
5830 thermal-sensors = <&t 5688 thermal-sensors = <&tsens1 1>;
5831 5689
5832 trips { 5690 trips {
5833 q6_modem_aler 5691 q6_modem_alert0: trip-point0 {
5834 tempe 5692 temperature = <90000>;
5835 hyste 5693 hysteresis = <2000>;
5836 type 5694 type = "hot";
5837 }; 5695 };
5838 }; 5696 };
5839 }; 5697 };
5840 5698
5841 mem-thermal { 5699 mem-thermal {
5842 polling-delay-passive 5700 polling-delay-passive = <250>;
>> 5701 polling-delay = <1000>;
5843 5702
5844 thermal-sensors = <&t 5703 thermal-sensors = <&tsens1 2>;
5845 5704
5846 trips { 5705 trips {
5847 mem_alert0: t 5706 mem_alert0: trip-point0 {
5848 tempe 5707 temperature = <90000>;
5849 hyste 5708 hysteresis = <2000>;
5850 type 5709 type = "hot";
5851 }; 5710 };
5852 }; 5711 };
5853 }; 5712 };
5854 5713
5855 wlan-thermal { 5714 wlan-thermal {
5856 polling-delay-passive 5715 polling-delay-passive = <250>;
>> 5716 polling-delay = <1000>;
5857 5717
5858 thermal-sensors = <&t 5718 thermal-sensors = <&tsens1 3>;
5859 5719
5860 trips { 5720 trips {
5861 wlan_alert0: 5721 wlan_alert0: trip-point0 {
5862 tempe 5722 temperature = <90000>;
5863 hyste 5723 hysteresis = <2000>;
5864 type 5724 type = "hot";
5865 }; 5725 };
5866 }; 5726 };
5867 }; 5727 };
5868 5728
5869 q6-hvx-thermal { 5729 q6-hvx-thermal {
5870 polling-delay-passive 5730 polling-delay-passive = <250>;
>> 5731 polling-delay = <1000>;
5871 5732
5872 thermal-sensors = <&t 5733 thermal-sensors = <&tsens1 4>;
5873 5734
5874 trips { 5735 trips {
5875 q6_hvx_alert0 5736 q6_hvx_alert0: trip-point0 {
5876 tempe 5737 temperature = <90000>;
5877 hyste 5738 hysteresis = <2000>;
5878 type 5739 type = "hot";
5879 }; 5740 };
5880 }; 5741 };
5881 }; 5742 };
5882 5743
5883 camera-thermal { 5744 camera-thermal {
5884 polling-delay-passive 5745 polling-delay-passive = <250>;
>> 5746 polling-delay = <1000>;
5885 5747
5886 thermal-sensors = <&t 5748 thermal-sensors = <&tsens1 5>;
5887 5749
5888 trips { 5750 trips {
5889 camera_alert0 5751 camera_alert0: trip-point0 {
5890 tempe 5752 temperature = <90000>;
5891 hyste 5753 hysteresis = <2000>;
5892 type 5754 type = "hot";
5893 }; 5755 };
5894 }; 5756 };
5895 }; 5757 };
5896 5758
5897 video-thermal { 5759 video-thermal {
5898 polling-delay-passive 5760 polling-delay-passive = <250>;
>> 5761 polling-delay = <1000>;
5899 5762
5900 thermal-sensors = <&t 5763 thermal-sensors = <&tsens1 6>;
5901 5764
5902 trips { 5765 trips {
5903 video_alert0: 5766 video_alert0: trip-point0 {
5904 tempe 5767 temperature = <90000>;
5905 hyste 5768 hysteresis = <2000>;
5906 type 5769 type = "hot";
5907 }; 5770 };
5908 }; 5771 };
5909 }; 5772 };
5910 5773
5911 modem-thermal { 5774 modem-thermal {
5912 polling-delay-passive 5775 polling-delay-passive = <250>;
>> 5776 polling-delay = <1000>;
5913 5777
5914 thermal-sensors = <&t 5778 thermal-sensors = <&tsens1 7>;
5915 5779
5916 trips { 5780 trips {
5917 modem_alert0: 5781 modem_alert0: trip-point0 {
5918 tempe 5782 temperature = <90000>;
5919 hyste 5783 hysteresis = <2000>;
5920 type 5784 type = "hot";
5921 }; 5785 };
5922 }; 5786 };
5923 }; 5787 };
5924 }; <<
5925 <<
5926 timer { <<
5927 compatible = "arm,armv8-timer <<
5928 interrupts = <GIC_PPI 1 IRQ_T <<
5929 <GIC_PPI 2 IRQ_T <<
5930 <GIC_PPI 3 IRQ_T <<
5931 <GIC_PPI 0 IRQ_T <<
5932 }; 5788 };
5933 }; 5789 };
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