1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * SDM845 SoC device tree source 3 * SDM845 SoC device tree source
4 * 4 *
5 * Copyright (c) 2018, The Linux Foundation. A 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/qcom,camcc-sdm845. 8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845 9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845. 11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845. 12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm84 14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h> 15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h> 16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,icc.h> <<
19 #include <dt-bindings/interconnect/qcom,osm-l3 18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
20 #include <dt-bindings/interconnect/qcom,sdm845 19 #include <dt-bindings/interconnect/qcom,sdm845.h>
21 #include <dt-bindings/interrupt-controller/arm 20 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 21 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24 #include <dt-bindings/power/qcom-rpmpd.h> 22 #include <dt-bindings/power/qcom-rpmpd.h>
25 #include <dt-bindings/reset/qcom,sdm845-aoss.h 23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
26 #include <dt-bindings/reset/qcom,sdm845-pdc.h> 24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
27 #include <dt-bindings/soc/qcom,apr.h> 25 #include <dt-bindings/soc/qcom,apr.h>
28 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 26 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
29 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 27 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
30 #include <dt-bindings/thermal/thermal.h> 28 #include <dt-bindings/thermal/thermal.h>
31 29
32 / { 30 / {
33 interrupt-parent = <&intc>; 31 interrupt-parent = <&intc>;
34 32
35 #address-cells = <2>; 33 #address-cells = <2>;
36 #size-cells = <2>; 34 #size-cells = <2>;
37 35
38 aliases { 36 aliases {
39 i2c0 = &i2c0; 37 i2c0 = &i2c0;
40 i2c1 = &i2c1; 38 i2c1 = &i2c1;
41 i2c2 = &i2c2; 39 i2c2 = &i2c2;
42 i2c3 = &i2c3; 40 i2c3 = &i2c3;
43 i2c4 = &i2c4; 41 i2c4 = &i2c4;
44 i2c5 = &i2c5; 42 i2c5 = &i2c5;
45 i2c6 = &i2c6; 43 i2c6 = &i2c6;
46 i2c7 = &i2c7; 44 i2c7 = &i2c7;
47 i2c8 = &i2c8; 45 i2c8 = &i2c8;
48 i2c9 = &i2c9; 46 i2c9 = &i2c9;
49 i2c10 = &i2c10; 47 i2c10 = &i2c10;
50 i2c11 = &i2c11; 48 i2c11 = &i2c11;
51 i2c12 = &i2c12; 49 i2c12 = &i2c12;
52 i2c13 = &i2c13; 50 i2c13 = &i2c13;
53 i2c14 = &i2c14; 51 i2c14 = &i2c14;
54 i2c15 = &i2c15; 52 i2c15 = &i2c15;
55 spi0 = &spi0; 53 spi0 = &spi0;
56 spi1 = &spi1; 54 spi1 = &spi1;
57 spi2 = &spi2; 55 spi2 = &spi2;
58 spi3 = &spi3; 56 spi3 = &spi3;
59 spi4 = &spi4; 57 spi4 = &spi4;
60 spi5 = &spi5; 58 spi5 = &spi5;
61 spi6 = &spi6; 59 spi6 = &spi6;
62 spi7 = &spi7; 60 spi7 = &spi7;
63 spi8 = &spi8; 61 spi8 = &spi8;
64 spi9 = &spi9; 62 spi9 = &spi9;
65 spi10 = &spi10; 63 spi10 = &spi10;
66 spi11 = &spi11; 64 spi11 = &spi11;
67 spi12 = &spi12; 65 spi12 = &spi12;
68 spi13 = &spi13; 66 spi13 = &spi13;
69 spi14 = &spi14; 67 spi14 = &spi14;
70 spi15 = &spi15; 68 spi15 = &spi15;
71 }; 69 };
72 70
73 chosen { }; 71 chosen { };
74 72
75 clocks { 73 clocks {
76 xo_board: xo-board { 74 xo_board: xo-board {
77 compatible = "fixed-cl 75 compatible = "fixed-clock";
78 #clock-cells = <0>; 76 #clock-cells = <0>;
79 clock-frequency = <384 77 clock-frequency = <38400000>;
80 clock-output-names = " 78 clock-output-names = "xo_board";
81 }; 79 };
82 80
83 sleep_clk: sleep-clk { 81 sleep_clk: sleep-clk {
84 compatible = "fixed-cl 82 compatible = "fixed-clock";
85 #clock-cells = <0>; 83 #clock-cells = <0>;
86 clock-frequency = <327 84 clock-frequency = <32764>;
87 }; 85 };
88 }; 86 };
89 87
90 cpus: cpus { 88 cpus: cpus {
91 #address-cells = <2>; 89 #address-cells = <2>;
92 #size-cells = <0>; 90 #size-cells = <0>;
93 91
94 CPU0: cpu@0 { 92 CPU0: cpu@0 {
95 device_type = "cpu"; 93 device_type = "cpu";
96 compatible = "qcom,kry 94 compatible = "qcom,kryo385";
97 reg = <0x0 0x0>; 95 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 96 clocks = <&cpufreq_hw 0>;
99 enable-method = "psci" 97 enable-method = "psci";
100 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <611>;
101 dynamic-power-coeffici 99 dynamic-power-coefficient = <154>;
102 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
103 operating-points-v2 = 101 operating-points-v2 = <&cpu0_opp_table>;
104 interconnects = <&glad 102 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
105 <&osm_ 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
106 power-domains = <&CPU_ 104 power-domains = <&CPU_PD0>;
107 power-domain-names = " 105 power-domain-names = "psci";
108 #cooling-cells = <2>; 106 #cooling-cells = <2>;
109 next-level-cache = <&L 107 next-level-cache = <&L2_0>;
110 L2_0: l2-cache { 108 L2_0: l2-cache {
111 compatible = " 109 compatible = "cache";
112 cache-level = 110 cache-level = <2>;
113 cache-unified; 111 cache-unified;
114 next-level-cac 112 next-level-cache = <&L3_0>;
115 L3_0: l3-cache 113 L3_0: l3-cache {
116 compat 114 compatible = "cache";
117 cache- 115 cache-level = <3>;
118 cache- 116 cache-unified;
119 }; 117 };
120 }; 118 };
121 }; 119 };
122 120
123 CPU1: cpu@100 { 121 CPU1: cpu@100 {
124 device_type = "cpu"; 122 device_type = "cpu";
125 compatible = "qcom,kry 123 compatible = "qcom,kryo385";
126 reg = <0x0 0x100>; 124 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 125 clocks = <&cpufreq_hw 0>;
128 enable-method = "psci" 126 enable-method = "psci";
129 capacity-dmips-mhz = < 127 capacity-dmips-mhz = <611>;
130 dynamic-power-coeffici 128 dynamic-power-coefficient = <154>;
131 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = 130 operating-points-v2 = <&cpu0_opp_table>;
133 interconnects = <&glad 131 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
134 <&osm_ 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
135 power-domains = <&CPU_ 133 power-domains = <&CPU_PD1>;
136 power-domain-names = " 134 power-domain-names = "psci";
137 #cooling-cells = <2>; 135 #cooling-cells = <2>;
138 next-level-cache = <&L 136 next-level-cache = <&L2_100>;
139 L2_100: l2-cache { 137 L2_100: l2-cache {
140 compatible = " 138 compatible = "cache";
141 cache-level = 139 cache-level = <2>;
142 cache-unified; 140 cache-unified;
143 next-level-cac 141 next-level-cache = <&L3_0>;
144 }; 142 };
145 }; 143 };
146 144
147 CPU2: cpu@200 { 145 CPU2: cpu@200 {
148 device_type = "cpu"; 146 device_type = "cpu";
149 compatible = "qcom,kry 147 compatible = "qcom,kryo385";
150 reg = <0x0 0x200>; 148 reg = <0x0 0x200>;
151 clocks = <&cpufreq_hw 149 clocks = <&cpufreq_hw 0>;
152 enable-method = "psci" 150 enable-method = "psci";
153 capacity-dmips-mhz = < 151 capacity-dmips-mhz = <611>;
154 dynamic-power-coeffici 152 dynamic-power-coefficient = <154>;
155 qcom,freq-domain = <&c 153 qcom,freq-domain = <&cpufreq_hw 0>;
156 operating-points-v2 = 154 operating-points-v2 = <&cpu0_opp_table>;
157 interconnects = <&glad 155 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
158 <&osm_ 156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
159 power-domains = <&CPU_ 157 power-domains = <&CPU_PD2>;
160 power-domain-names = " 158 power-domain-names = "psci";
161 #cooling-cells = <2>; 159 #cooling-cells = <2>;
162 next-level-cache = <&L 160 next-level-cache = <&L2_200>;
163 L2_200: l2-cache { 161 L2_200: l2-cache {
164 compatible = " 162 compatible = "cache";
165 cache-level = 163 cache-level = <2>;
166 cache-unified; 164 cache-unified;
167 next-level-cac 165 next-level-cache = <&L3_0>;
168 }; 166 };
169 }; 167 };
170 168
171 CPU3: cpu@300 { 169 CPU3: cpu@300 {
172 device_type = "cpu"; 170 device_type = "cpu";
173 compatible = "qcom,kry 171 compatible = "qcom,kryo385";
174 reg = <0x0 0x300>; 172 reg = <0x0 0x300>;
175 clocks = <&cpufreq_hw 173 clocks = <&cpufreq_hw 0>;
176 enable-method = "psci" 174 enable-method = "psci";
177 capacity-dmips-mhz = < 175 capacity-dmips-mhz = <611>;
178 dynamic-power-coeffici 176 dynamic-power-coefficient = <154>;
179 qcom,freq-domain = <&c 177 qcom,freq-domain = <&cpufreq_hw 0>;
180 operating-points-v2 = 178 operating-points-v2 = <&cpu0_opp_table>;
181 interconnects = <&glad 179 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
182 <&osm_ 180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
183 #cooling-cells = <2>; 181 #cooling-cells = <2>;
184 power-domains = <&CPU_ 182 power-domains = <&CPU_PD3>;
185 power-domain-names = " 183 power-domain-names = "psci";
186 next-level-cache = <&L 184 next-level-cache = <&L2_300>;
187 L2_300: l2-cache { 185 L2_300: l2-cache {
188 compatible = " 186 compatible = "cache";
189 cache-level = 187 cache-level = <2>;
190 cache-unified; 188 cache-unified;
191 next-level-cac 189 next-level-cache = <&L3_0>;
192 }; 190 };
193 }; 191 };
194 192
195 CPU4: cpu@400 { 193 CPU4: cpu@400 {
196 device_type = "cpu"; 194 device_type = "cpu";
197 compatible = "qcom,kry 195 compatible = "qcom,kryo385";
198 reg = <0x0 0x400>; 196 reg = <0x0 0x400>;
199 clocks = <&cpufreq_hw 197 clocks = <&cpufreq_hw 1>;
200 enable-method = "psci" 198 enable-method = "psci";
201 capacity-dmips-mhz = < 199 capacity-dmips-mhz = <1024>;
202 dynamic-power-coeffici 200 dynamic-power-coefficient = <442>;
203 qcom,freq-domain = <&c 201 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = 202 operating-points-v2 = <&cpu4_opp_table>;
205 interconnects = <&glad 203 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
206 <&osm_ 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
207 power-domains = <&CPU_ 205 power-domains = <&CPU_PD4>;
208 power-domain-names = " 206 power-domain-names = "psci";
209 #cooling-cells = <2>; 207 #cooling-cells = <2>;
210 next-level-cache = <&L 208 next-level-cache = <&L2_400>;
211 L2_400: l2-cache { 209 L2_400: l2-cache {
212 compatible = " 210 compatible = "cache";
213 cache-level = 211 cache-level = <2>;
214 cache-unified; 212 cache-unified;
215 next-level-cac 213 next-level-cache = <&L3_0>;
216 }; 214 };
217 }; 215 };
218 216
219 CPU5: cpu@500 { 217 CPU5: cpu@500 {
220 device_type = "cpu"; 218 device_type = "cpu";
221 compatible = "qcom,kry 219 compatible = "qcom,kryo385";
222 reg = <0x0 0x500>; 220 reg = <0x0 0x500>;
223 clocks = <&cpufreq_hw 221 clocks = <&cpufreq_hw 1>;
224 enable-method = "psci" 222 enable-method = "psci";
225 capacity-dmips-mhz = < 223 capacity-dmips-mhz = <1024>;
226 dynamic-power-coeffici 224 dynamic-power-coefficient = <442>;
227 qcom,freq-domain = <&c 225 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = 226 operating-points-v2 = <&cpu4_opp_table>;
229 interconnects = <&glad 227 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
230 <&osm_ 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
231 power-domains = <&CPU_ 229 power-domains = <&CPU_PD5>;
232 power-domain-names = " 230 power-domain-names = "psci";
233 #cooling-cells = <2>; 231 #cooling-cells = <2>;
234 next-level-cache = <&L 232 next-level-cache = <&L2_500>;
235 L2_500: l2-cache { 233 L2_500: l2-cache {
236 compatible = " 234 compatible = "cache";
237 cache-level = 235 cache-level = <2>;
238 cache-unified; 236 cache-unified;
239 next-level-cac 237 next-level-cache = <&L3_0>;
240 }; 238 };
241 }; 239 };
242 240
243 CPU6: cpu@600 { 241 CPU6: cpu@600 {
244 device_type = "cpu"; 242 device_type = "cpu";
245 compatible = "qcom,kry 243 compatible = "qcom,kryo385";
246 reg = <0x0 0x600>; 244 reg = <0x0 0x600>;
247 clocks = <&cpufreq_hw 245 clocks = <&cpufreq_hw 1>;
248 enable-method = "psci" 246 enable-method = "psci";
249 capacity-dmips-mhz = < 247 capacity-dmips-mhz = <1024>;
250 dynamic-power-coeffici 248 dynamic-power-coefficient = <442>;
251 qcom,freq-domain = <&c 249 qcom,freq-domain = <&cpufreq_hw 1>;
252 operating-points-v2 = 250 operating-points-v2 = <&cpu4_opp_table>;
253 interconnects = <&glad 251 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
254 <&osm_ 252 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
255 power-domains = <&CPU_ 253 power-domains = <&CPU_PD6>;
256 power-domain-names = " 254 power-domain-names = "psci";
257 #cooling-cells = <2>; 255 #cooling-cells = <2>;
258 next-level-cache = <&L 256 next-level-cache = <&L2_600>;
259 L2_600: l2-cache { 257 L2_600: l2-cache {
260 compatible = " 258 compatible = "cache";
261 cache-level = 259 cache-level = <2>;
262 cache-unified; 260 cache-unified;
263 next-level-cac 261 next-level-cache = <&L3_0>;
264 }; 262 };
265 }; 263 };
266 264
267 CPU7: cpu@700 { 265 CPU7: cpu@700 {
268 device_type = "cpu"; 266 device_type = "cpu";
269 compatible = "qcom,kry 267 compatible = "qcom,kryo385";
270 reg = <0x0 0x700>; 268 reg = <0x0 0x700>;
271 clocks = <&cpufreq_hw 269 clocks = <&cpufreq_hw 1>;
272 enable-method = "psci" 270 enable-method = "psci";
273 capacity-dmips-mhz = < 271 capacity-dmips-mhz = <1024>;
274 dynamic-power-coeffici 272 dynamic-power-coefficient = <442>;
275 qcom,freq-domain = <&c 273 qcom,freq-domain = <&cpufreq_hw 1>;
276 operating-points-v2 = 274 operating-points-v2 = <&cpu4_opp_table>;
277 interconnects = <&glad 275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
278 <&osm_ 276 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
279 power-domains = <&CPU_ 277 power-domains = <&CPU_PD7>;
280 power-domain-names = " 278 power-domain-names = "psci";
281 #cooling-cells = <2>; 279 #cooling-cells = <2>;
282 next-level-cache = <&L 280 next-level-cache = <&L2_700>;
283 L2_700: l2-cache { 281 L2_700: l2-cache {
284 compatible = " 282 compatible = "cache";
285 cache-level = 283 cache-level = <2>;
286 cache-unified; 284 cache-unified;
287 next-level-cac 285 next-level-cache = <&L3_0>;
288 }; 286 };
289 }; 287 };
290 288
291 cpu-map { 289 cpu-map {
292 cluster0 { 290 cluster0 {
293 core0 { 291 core0 {
294 cpu = 292 cpu = <&CPU0>;
295 }; 293 };
296 294
297 core1 { 295 core1 {
298 cpu = 296 cpu = <&CPU1>;
299 }; 297 };
300 298
301 core2 { 299 core2 {
302 cpu = 300 cpu = <&CPU2>;
303 }; 301 };
304 302
305 core3 { 303 core3 {
306 cpu = 304 cpu = <&CPU3>;
307 }; 305 };
308 306
309 core4 { 307 core4 {
310 cpu = 308 cpu = <&CPU4>;
311 }; 309 };
312 310
313 core5 { 311 core5 {
314 cpu = 312 cpu = <&CPU5>;
315 }; 313 };
316 314
317 core6 { 315 core6 {
318 cpu = 316 cpu = <&CPU6>;
319 }; 317 };
320 318
321 core7 { 319 core7 {
322 cpu = 320 cpu = <&CPU7>;
323 }; 321 };
324 }; 322 };
325 }; 323 };
326 324
327 cpu_idle_states: idle-states { 325 cpu_idle_states: idle-states {
328 entry-method = "psci"; 326 entry-method = "psci";
329 327
330 LITTLE_CPU_SLEEP_0: cp 328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 compatible = " 329 compatible = "arm,idle-state";
332 idle-state-nam 330 idle-state-name = "little-rail-power-collapse";
333 arm,psci-suspe 331 arm,psci-suspend-param = <0x40000004>;
334 entry-latency- 332 entry-latency-us = <350>;
335 exit-latency-u 333 exit-latency-us = <461>;
336 min-residency- 334 min-residency-us = <1890>;
337 local-timer-st 335 local-timer-stop;
338 }; 336 };
339 337
340 BIG_CPU_SLEEP_0: cpu-s 338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 compatible = " 339 compatible = "arm,idle-state";
342 idle-state-nam 340 idle-state-name = "big-rail-power-collapse";
343 arm,psci-suspe 341 arm,psci-suspend-param = <0x40000004>;
344 entry-latency- 342 entry-latency-us = <264>;
345 exit-latency-u 343 exit-latency-us = <621>;
346 min-residency- 344 min-residency-us = <952>;
347 local-timer-st 345 local-timer-stop;
348 }; 346 };
349 }; 347 };
350 348
351 domain-idle-states { 349 domain-idle-states {
352 CLUSTER_SLEEP_0: clust 350 CLUSTER_SLEEP_0: cluster-sleep-0 {
353 compatible = " 351 compatible = "domain-idle-state";
354 arm,psci-suspe 352 arm,psci-suspend-param = <0x4100c244>;
355 entry-latency- 353 entry-latency-us = <3263>;
356 exit-latency-u 354 exit-latency-us = <6562>;
357 min-residency- 355 min-residency-us = <9987>;
358 }; 356 };
359 }; 357 };
360 }; 358 };
361 359
362 firmware { 360 firmware {
363 scm { 361 scm {
364 compatible = "qcom,scm 362 compatible = "qcom,scm-sdm845", "qcom,scm";
365 }; 363 };
366 }; 364 };
367 365
368 memory@80000000 { 366 memory@80000000 {
369 device_type = "memory"; 367 device_type = "memory";
370 /* We expect the bootloader to 368 /* We expect the bootloader to fill in the size */
371 reg = <0 0x80000000 0 0>; 369 reg = <0 0x80000000 0 0>;
372 }; 370 };
373 371
374 cpu0_opp_table: opp-table-cpu0 { 372 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points 373 compatible = "operating-points-v2";
376 opp-shared; 374 opp-shared;
377 375
378 cpu0_opp1: opp-300000000 { 376 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <30 377 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <80000 378 opp-peak-kBps = <800000 4800000>;
381 }; 379 };
382 380
383 cpu0_opp2: opp-403200000 { 381 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <40 382 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <80000 383 opp-peak-kBps = <800000 4800000>;
386 }; 384 };
387 385
388 cpu0_opp3: opp-480000000 { 386 cpu0_opp3: opp-480000000 {
389 opp-hz = /bits/ 64 <48 387 opp-hz = /bits/ 64 <480000000>;
390 opp-peak-kBps = <80000 388 opp-peak-kBps = <800000 6451200>;
391 }; 389 };
392 390
393 cpu0_opp4: opp-576000000 { 391 cpu0_opp4: opp-576000000 {
394 opp-hz = /bits/ 64 <57 392 opp-hz = /bits/ 64 <576000000>;
395 opp-peak-kBps = <80000 393 opp-peak-kBps = <800000 6451200>;
396 }; 394 };
397 395
398 cpu0_opp5: opp-652800000 { 396 cpu0_opp5: opp-652800000 {
399 opp-hz = /bits/ 64 <65 397 opp-hz = /bits/ 64 <652800000>;
400 opp-peak-kBps = <80000 398 opp-peak-kBps = <800000 7680000>;
401 }; 399 };
402 400
403 cpu0_opp6: opp-748800000 { 401 cpu0_opp6: opp-748800000 {
404 opp-hz = /bits/ 64 <74 402 opp-hz = /bits/ 64 <748800000>;
405 opp-peak-kBps = <18040 403 opp-peak-kBps = <1804000 9216000>;
406 }; 404 };
407 405
408 cpu0_opp7: opp-825600000 { 406 cpu0_opp7: opp-825600000 {
409 opp-hz = /bits/ 64 <82 407 opp-hz = /bits/ 64 <825600000>;
410 opp-peak-kBps = <18040 408 opp-peak-kBps = <1804000 9216000>;
411 }; 409 };
412 410
413 cpu0_opp8: opp-902400000 { 411 cpu0_opp8: opp-902400000 {
414 opp-hz = /bits/ 64 <90 412 opp-hz = /bits/ 64 <902400000>;
415 opp-peak-kBps = <18040 413 opp-peak-kBps = <1804000 10444800>;
416 }; 414 };
417 415
418 cpu0_opp9: opp-979200000 { 416 cpu0_opp9: opp-979200000 {
419 opp-hz = /bits/ 64 <97 417 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 418 opp-peak-kBps = <1804000 11980800>;
421 }; 419 };
422 420
423 cpu0_opp10: opp-1056000000 { 421 cpu0_opp10: opp-1056000000 {
424 opp-hz = /bits/ 64 <10 422 opp-hz = /bits/ 64 <1056000000>;
425 opp-peak-kBps = <18040 423 opp-peak-kBps = <1804000 11980800>;
426 }; 424 };
427 425
428 cpu0_opp11: opp-1132800000 { 426 cpu0_opp11: opp-1132800000 {
429 opp-hz = /bits/ 64 <11 427 opp-hz = /bits/ 64 <1132800000>;
430 opp-peak-kBps = <21880 428 opp-peak-kBps = <2188000 13516800>;
431 }; 429 };
432 430
433 cpu0_opp12: opp-1228800000 { 431 cpu0_opp12: opp-1228800000 {
434 opp-hz = /bits/ 64 <12 432 opp-hz = /bits/ 64 <1228800000>;
435 opp-peak-kBps = <21880 433 opp-peak-kBps = <2188000 15052800>;
436 }; 434 };
437 435
438 cpu0_opp13: opp-1324800000 { 436 cpu0_opp13: opp-1324800000 {
439 opp-hz = /bits/ 64 <13 437 opp-hz = /bits/ 64 <1324800000>;
440 opp-peak-kBps = <21880 438 opp-peak-kBps = <2188000 16588800>;
441 }; 439 };
442 440
443 cpu0_opp14: opp-1420800000 { 441 cpu0_opp14: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 442 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <30720 443 opp-peak-kBps = <3072000 18124800>;
446 }; 444 };
447 445
448 cpu0_opp15: opp-1516800000 { 446 cpu0_opp15: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 447 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 448 opp-peak-kBps = <3072000 19353600>;
451 }; 449 };
452 450
453 cpu0_opp16: opp-1612800000 { 451 cpu0_opp16: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 452 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <40680 453 opp-peak-kBps = <4068000 19353600>;
456 }; 454 };
457 455
458 cpu0_opp17: opp-1689600000 { 456 cpu0_opp17: opp-1689600000 {
459 opp-hz = /bits/ 64 <16 457 opp-hz = /bits/ 64 <1689600000>;
460 opp-peak-kBps = <40680 458 opp-peak-kBps = <4068000 20889600>;
461 }; 459 };
462 460
463 cpu0_opp18: opp-1766400000 { 461 cpu0_opp18: opp-1766400000 {
464 opp-hz = /bits/ 64 <17 462 opp-hz = /bits/ 64 <1766400000>;
465 opp-peak-kBps = <40680 463 opp-peak-kBps = <4068000 22425600>;
466 }; 464 };
467 }; 465 };
468 466
469 cpu4_opp_table: opp-table-cpu4 { 467 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 468 compatible = "operating-points-v2";
471 opp-shared; 469 opp-shared;
472 470
473 cpu4_opp1: opp-300000000 { 471 cpu4_opp1: opp-300000000 {
474 opp-hz = /bits/ 64 <30 472 opp-hz = /bits/ 64 <300000000>;
475 opp-peak-kBps = <80000 473 opp-peak-kBps = <800000 4800000>;
476 }; 474 };
477 475
478 cpu4_opp2: opp-403200000 { 476 cpu4_opp2: opp-403200000 {
479 opp-hz = /bits/ 64 <40 477 opp-hz = /bits/ 64 <403200000>;
480 opp-peak-kBps = <80000 478 opp-peak-kBps = <800000 4800000>;
481 }; 479 };
482 480
483 cpu4_opp3: opp-480000000 { 481 cpu4_opp3: opp-480000000 {
484 opp-hz = /bits/ 64 <48 482 opp-hz = /bits/ 64 <480000000>;
485 opp-peak-kBps = <18040 483 opp-peak-kBps = <1804000 4800000>;
486 }; 484 };
487 485
488 cpu4_opp4: opp-576000000 { 486 cpu4_opp4: opp-576000000 {
489 opp-hz = /bits/ 64 <57 487 opp-hz = /bits/ 64 <576000000>;
490 opp-peak-kBps = <18040 488 opp-peak-kBps = <1804000 4800000>;
491 }; 489 };
492 490
493 cpu4_opp5: opp-652800000 { 491 cpu4_opp5: opp-652800000 {
494 opp-hz = /bits/ 64 <65 492 opp-hz = /bits/ 64 <652800000>;
495 opp-peak-kBps = <18040 493 opp-peak-kBps = <1804000 4800000>;
496 }; 494 };
497 495
498 cpu4_opp6: opp-748800000 { 496 cpu4_opp6: opp-748800000 {
499 opp-hz = /bits/ 64 <74 497 opp-hz = /bits/ 64 <748800000>;
500 opp-peak-kBps = <18040 498 opp-peak-kBps = <1804000 4800000>;
501 }; 499 };
502 500
503 cpu4_opp7: opp-825600000 { 501 cpu4_opp7: opp-825600000 {
504 opp-hz = /bits/ 64 <82 502 opp-hz = /bits/ 64 <825600000>;
505 opp-peak-kBps = <21880 503 opp-peak-kBps = <2188000 9216000>;
506 }; 504 };
507 505
508 cpu4_opp8: opp-902400000 { 506 cpu4_opp8: opp-902400000 {
509 opp-hz = /bits/ 64 <90 507 opp-hz = /bits/ 64 <902400000>;
510 opp-peak-kBps = <21880 508 opp-peak-kBps = <2188000 9216000>;
511 }; 509 };
512 510
513 cpu4_opp9: opp-979200000 { 511 cpu4_opp9: opp-979200000 {
514 opp-hz = /bits/ 64 <97 512 opp-hz = /bits/ 64 <979200000>;
515 opp-peak-kBps = <21880 513 opp-peak-kBps = <2188000 9216000>;
516 }; 514 };
517 515
518 cpu4_opp10: opp-1056000000 { 516 cpu4_opp10: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 517 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 518 opp-peak-kBps = <3072000 9216000>;
521 }; 519 };
522 520
523 cpu4_opp11: opp-1132800000 { 521 cpu4_opp11: opp-1132800000 {
524 opp-hz = /bits/ 64 <11 522 opp-hz = /bits/ 64 <1132800000>;
525 opp-peak-kBps = <30720 523 opp-peak-kBps = <3072000 11980800>;
526 }; 524 };
527 525
528 cpu4_opp12: opp-1209600000 { 526 cpu4_opp12: opp-1209600000 {
529 opp-hz = /bits/ 64 <12 527 opp-hz = /bits/ 64 <1209600000>;
530 opp-peak-kBps = <40680 528 opp-peak-kBps = <4068000 11980800>;
531 }; 529 };
532 530
533 cpu4_opp13: opp-1286400000 { 531 cpu4_opp13: opp-1286400000 {
534 opp-hz = /bits/ 64 <12 532 opp-hz = /bits/ 64 <1286400000>;
535 opp-peak-kBps = <40680 533 opp-peak-kBps = <4068000 11980800>;
536 }; 534 };
537 535
538 cpu4_opp14: opp-1363200000 { 536 cpu4_opp14: opp-1363200000 {
539 opp-hz = /bits/ 64 <13 537 opp-hz = /bits/ 64 <1363200000>;
540 opp-peak-kBps = <40680 538 opp-peak-kBps = <4068000 15052800>;
541 }; 539 };
542 540
543 cpu4_opp15: opp-1459200000 { 541 cpu4_opp15: opp-1459200000 {
544 opp-hz = /bits/ 64 <14 542 opp-hz = /bits/ 64 <1459200000>;
545 opp-peak-kBps = <40680 543 opp-peak-kBps = <4068000 15052800>;
546 }; 544 };
547 545
548 cpu4_opp16: opp-1536000000 { 546 cpu4_opp16: opp-1536000000 {
549 opp-hz = /bits/ 64 <15 547 opp-hz = /bits/ 64 <1536000000>;
550 opp-peak-kBps = <54120 548 opp-peak-kBps = <5412000 15052800>;
551 }; 549 };
552 550
553 cpu4_opp17: opp-1612800000 { 551 cpu4_opp17: opp-1612800000 {
554 opp-hz = /bits/ 64 <16 552 opp-hz = /bits/ 64 <1612800000>;
555 opp-peak-kBps = <54120 553 opp-peak-kBps = <5412000 15052800>;
556 }; 554 };
557 555
558 cpu4_opp18: opp-1689600000 { 556 cpu4_opp18: opp-1689600000 {
559 opp-hz = /bits/ 64 <16 557 opp-hz = /bits/ 64 <1689600000>;
560 opp-peak-kBps = <54120 558 opp-peak-kBps = <5412000 19353600>;
561 }; 559 };
562 560
563 cpu4_opp19: opp-1766400000 { 561 cpu4_opp19: opp-1766400000 {
564 opp-hz = /bits/ 64 <17 562 opp-hz = /bits/ 64 <1766400000>;
565 opp-peak-kBps = <62200 563 opp-peak-kBps = <6220000 19353600>;
566 }; 564 };
567 565
568 cpu4_opp20: opp-1843200000 { 566 cpu4_opp20: opp-1843200000 {
569 opp-hz = /bits/ 64 <18 567 opp-hz = /bits/ 64 <1843200000>;
570 opp-peak-kBps = <62200 568 opp-peak-kBps = <6220000 19353600>;
571 }; 569 };
572 570
573 cpu4_opp21: opp-1920000000 { 571 cpu4_opp21: opp-1920000000 {
574 opp-hz = /bits/ 64 <19 572 opp-hz = /bits/ 64 <1920000000>;
575 opp-peak-kBps = <72160 573 opp-peak-kBps = <7216000 19353600>;
576 }; 574 };
577 575
578 cpu4_opp22: opp-1996800000 { 576 cpu4_opp22: opp-1996800000 {
579 opp-hz = /bits/ 64 <19 577 opp-hz = /bits/ 64 <1996800000>;
580 opp-peak-kBps = <72160 578 opp-peak-kBps = <7216000 20889600>;
581 }; 579 };
582 580
583 cpu4_opp23: opp-2092800000 { 581 cpu4_opp23: opp-2092800000 {
584 opp-hz = /bits/ 64 <20 582 opp-hz = /bits/ 64 <2092800000>;
585 opp-peak-kBps = <72160 583 opp-peak-kBps = <7216000 20889600>;
586 }; 584 };
587 585
588 cpu4_opp24: opp-2169600000 { 586 cpu4_opp24: opp-2169600000 {
589 opp-hz = /bits/ 64 <21 587 opp-hz = /bits/ 64 <2169600000>;
590 opp-peak-kBps = <72160 588 opp-peak-kBps = <7216000 20889600>;
591 }; 589 };
592 590
593 cpu4_opp25: opp-2246400000 { 591 cpu4_opp25: opp-2246400000 {
594 opp-hz = /bits/ 64 <22 592 opp-hz = /bits/ 64 <2246400000>;
595 opp-peak-kBps = <72160 593 opp-peak-kBps = <7216000 20889600>;
596 }; 594 };
597 595
598 cpu4_opp26: opp-2323200000 { 596 cpu4_opp26: opp-2323200000 {
599 opp-hz = /bits/ 64 <23 597 opp-hz = /bits/ 64 <2323200000>;
600 opp-peak-kBps = <72160 598 opp-peak-kBps = <7216000 20889600>;
601 }; 599 };
602 600
603 cpu4_opp27: opp-2400000000 { 601 cpu4_opp27: opp-2400000000 {
604 opp-hz = /bits/ 64 <24 602 opp-hz = /bits/ 64 <2400000000>;
605 opp-peak-kBps = <72160 603 opp-peak-kBps = <7216000 22425600>;
606 }; 604 };
607 605
608 cpu4_opp28: opp-2476800000 { 606 cpu4_opp28: opp-2476800000 {
609 opp-hz = /bits/ 64 <24 607 opp-hz = /bits/ 64 <2476800000>;
610 opp-peak-kBps = <72160 608 opp-peak-kBps = <7216000 22425600>;
611 }; 609 };
612 610
613 cpu4_opp29: opp-2553600000 { 611 cpu4_opp29: opp-2553600000 {
614 opp-hz = /bits/ 64 <25 612 opp-hz = /bits/ 64 <2553600000>;
615 opp-peak-kBps = <72160 613 opp-peak-kBps = <7216000 22425600>;
616 }; 614 };
617 615
618 cpu4_opp30: opp-2649600000 { 616 cpu4_opp30: opp-2649600000 {
619 opp-hz = /bits/ 64 <26 617 opp-hz = /bits/ 64 <2649600000>;
620 opp-peak-kBps = <72160 618 opp-peak-kBps = <7216000 22425600>;
621 }; 619 };
622 620
623 cpu4_opp31: opp-2745600000 { 621 cpu4_opp31: opp-2745600000 {
624 opp-hz = /bits/ 64 <27 622 opp-hz = /bits/ 64 <2745600000>;
625 opp-peak-kBps = <72160 623 opp-peak-kBps = <7216000 25497600>;
626 }; 624 };
627 625
628 cpu4_opp32: opp-2803200000 { 626 cpu4_opp32: opp-2803200000 {
629 opp-hz = /bits/ 64 <28 627 opp-hz = /bits/ 64 <2803200000>;
630 opp-peak-kBps = <72160 628 opp-peak-kBps = <7216000 25497600>;
631 }; 629 };
632 }; 630 };
633 631
634 dsi_opp_table: opp-table-dsi { 632 dsi_opp_table: opp-table-dsi {
635 compatible = "operating-points 633 compatible = "operating-points-v2";
636 634
637 opp-19200000 { 635 opp-19200000 {
638 opp-hz = /bits/ 64 <19 636 opp-hz = /bits/ 64 <19200000>;
639 required-opps = <&rpmh 637 required-opps = <&rpmhpd_opp_min_svs>;
640 }; 638 };
641 639
642 opp-180000000 { 640 opp-180000000 {
643 opp-hz = /bits/ 64 <18 641 opp-hz = /bits/ 64 <180000000>;
644 required-opps = <&rpmh 642 required-opps = <&rpmhpd_opp_low_svs>;
645 }; 643 };
646 644
647 opp-275000000 { 645 opp-275000000 {
648 opp-hz = /bits/ 64 <27 646 opp-hz = /bits/ 64 <275000000>;
649 required-opps = <&rpmh 647 required-opps = <&rpmhpd_opp_svs>;
650 }; 648 };
651 649
652 opp-328580000 { 650 opp-328580000 {
653 opp-hz = /bits/ 64 <32 651 opp-hz = /bits/ 64 <328580000>;
654 required-opps = <&rpmh 652 required-opps = <&rpmhpd_opp_svs_l1>;
655 }; 653 };
656 654
657 opp-358000000 { 655 opp-358000000 {
658 opp-hz = /bits/ 64 <35 656 opp-hz = /bits/ 64 <358000000>;
659 required-opps = <&rpmh 657 required-opps = <&rpmhpd_opp_nom>;
660 }; 658 };
661 }; 659 };
662 660
663 qspi_opp_table: opp-table-qspi { 661 qspi_opp_table: opp-table-qspi {
664 compatible = "operating-points 662 compatible = "operating-points-v2";
665 663
666 opp-19200000 { 664 opp-19200000 {
667 opp-hz = /bits/ 64 <19 665 opp-hz = /bits/ 64 <19200000>;
668 required-opps = <&rpmh 666 required-opps = <&rpmhpd_opp_min_svs>;
669 }; 667 };
670 668
671 opp-100000000 { 669 opp-100000000 {
672 opp-hz = /bits/ 64 <10 670 opp-hz = /bits/ 64 <100000000>;
673 required-opps = <&rpmh 671 required-opps = <&rpmhpd_opp_low_svs>;
674 }; 672 };
675 673
676 opp-150000000 { 674 opp-150000000 {
677 opp-hz = /bits/ 64 <15 675 opp-hz = /bits/ 64 <150000000>;
678 required-opps = <&rpmh 676 required-opps = <&rpmhpd_opp_svs>;
679 }; 677 };
680 678
681 opp-300000000 { 679 opp-300000000 {
682 opp-hz = /bits/ 64 <30 680 opp-hz = /bits/ 64 <300000000>;
683 required-opps = <&rpmh 681 required-opps = <&rpmhpd_opp_nom>;
684 }; 682 };
685 }; 683 };
686 684
687 qup_opp_table: opp-table-qup { 685 qup_opp_table: opp-table-qup {
688 compatible = "operating-points 686 compatible = "operating-points-v2";
689 687
690 opp-50000000 { 688 opp-50000000 {
691 opp-hz = /bits/ 64 <50 689 opp-hz = /bits/ 64 <50000000>;
692 required-opps = <&rpmh 690 required-opps = <&rpmhpd_opp_min_svs>;
693 }; 691 };
694 692
695 opp-75000000 { 693 opp-75000000 {
696 opp-hz = /bits/ 64 <75 694 opp-hz = /bits/ 64 <75000000>;
697 required-opps = <&rpmh 695 required-opps = <&rpmhpd_opp_low_svs>;
698 }; 696 };
699 697
700 opp-100000000 { 698 opp-100000000 {
701 opp-hz = /bits/ 64 <10 699 opp-hz = /bits/ 64 <100000000>;
702 required-opps = <&rpmh 700 required-opps = <&rpmhpd_opp_svs>;
703 }; 701 };
704 702
705 opp-128000000 { 703 opp-128000000 {
706 opp-hz = /bits/ 64 <12 704 opp-hz = /bits/ 64 <128000000>;
707 required-opps = <&rpmh 705 required-opps = <&rpmhpd_opp_nom>;
708 }; 706 };
709 }; 707 };
710 708
711 pmu { 709 pmu {
712 compatible = "arm,armv8-pmuv3" 710 compatible = "arm,armv8-pmuv3";
713 interrupts = <GIC_PPI 5 IRQ_TY 711 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
714 }; 712 };
715 713
716 psci: psci { 714 psci: psci {
717 compatible = "arm,psci-1.0"; 715 compatible = "arm,psci-1.0";
718 method = "smc"; 716 method = "smc";
719 717
720 CPU_PD0: power-domain-cpu0 { 718 CPU_PD0: power-domain-cpu0 {
721 #power-domain-cells = 719 #power-domain-cells = <0>;
722 power-domains = <&CLUS 720 power-domains = <&CLUSTER_PD>;
723 domain-idle-states = < 721 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
724 }; 722 };
725 723
726 CPU_PD1: power-domain-cpu1 { 724 CPU_PD1: power-domain-cpu1 {
727 #power-domain-cells = 725 #power-domain-cells = <0>;
728 power-domains = <&CLUS 726 power-domains = <&CLUSTER_PD>;
729 domain-idle-states = < 727 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
730 }; 728 };
731 729
732 CPU_PD2: power-domain-cpu2 { 730 CPU_PD2: power-domain-cpu2 {
733 #power-domain-cells = 731 #power-domain-cells = <0>;
734 power-domains = <&CLUS 732 power-domains = <&CLUSTER_PD>;
735 domain-idle-states = < 733 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
736 }; 734 };
737 735
738 CPU_PD3: power-domain-cpu3 { 736 CPU_PD3: power-domain-cpu3 {
739 #power-domain-cells = 737 #power-domain-cells = <0>;
740 power-domains = <&CLUS 738 power-domains = <&CLUSTER_PD>;
741 domain-idle-states = < 739 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
742 }; 740 };
743 741
744 CPU_PD4: power-domain-cpu4 { 742 CPU_PD4: power-domain-cpu4 {
745 #power-domain-cells = 743 #power-domain-cells = <0>;
746 power-domains = <&CLUS 744 power-domains = <&CLUSTER_PD>;
747 domain-idle-states = < 745 domain-idle-states = <&BIG_CPU_SLEEP_0>;
748 }; 746 };
749 747
750 CPU_PD5: power-domain-cpu5 { 748 CPU_PD5: power-domain-cpu5 {
751 #power-domain-cells = 749 #power-domain-cells = <0>;
752 power-domains = <&CLUS 750 power-domains = <&CLUSTER_PD>;
753 domain-idle-states = < 751 domain-idle-states = <&BIG_CPU_SLEEP_0>;
754 }; 752 };
755 753
756 CPU_PD6: power-domain-cpu6 { 754 CPU_PD6: power-domain-cpu6 {
757 #power-domain-cells = 755 #power-domain-cells = <0>;
758 power-domains = <&CLUS 756 power-domains = <&CLUSTER_PD>;
759 domain-idle-states = < 757 domain-idle-states = <&BIG_CPU_SLEEP_0>;
760 }; 758 };
761 759
762 CPU_PD7: power-domain-cpu7 { 760 CPU_PD7: power-domain-cpu7 {
763 #power-domain-cells = 761 #power-domain-cells = <0>;
764 power-domains = <&CLUS 762 power-domains = <&CLUSTER_PD>;
765 domain-idle-states = < 763 domain-idle-states = <&BIG_CPU_SLEEP_0>;
766 }; 764 };
767 765
768 CLUSTER_PD: power-domain-clust 766 CLUSTER_PD: power-domain-cluster {
769 #power-domain-cells = 767 #power-domain-cells = <0>;
770 domain-idle-states = < 768 domain-idle-states = <&CLUSTER_SLEEP_0>;
771 }; 769 };
772 }; 770 };
773 771
774 reserved-memory { 772 reserved-memory {
775 #address-cells = <2>; 773 #address-cells = <2>;
776 #size-cells = <2>; 774 #size-cells = <2>;
777 ranges; 775 ranges;
778 776
779 hyp_mem: hyp-mem@85700000 { 777 hyp_mem: hyp-mem@85700000 {
780 reg = <0 0x85700000 0 778 reg = <0 0x85700000 0 0x600000>;
781 no-map; 779 no-map;
782 }; 780 };
783 781
784 xbl_mem: xbl-mem@85e00000 { 782 xbl_mem: xbl-mem@85e00000 {
785 reg = <0 0x85e00000 0 783 reg = <0 0x85e00000 0 0x100000>;
786 no-map; 784 no-map;
787 }; 785 };
788 786
789 aop_mem: aop-mem@85fc0000 { 787 aop_mem: aop-mem@85fc0000 {
790 reg = <0 0x85fc0000 0 788 reg = <0 0x85fc0000 0 0x20000>;
791 no-map; 789 no-map;
792 }; 790 };
793 791
794 aop_cmd_db_mem: aop-cmd-db-mem 792 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
795 compatible = "qcom,cmd 793 compatible = "qcom,cmd-db";
796 reg = <0x0 0x85fe0000 794 reg = <0x0 0x85fe0000 0 0x20000>;
797 no-map; 795 no-map;
798 }; 796 };
799 797
800 smem@86000000 { 798 smem@86000000 {
801 compatible = "qcom,sme 799 compatible = "qcom,smem";
802 reg = <0x0 0x86000000 800 reg = <0x0 0x86000000 0 0x200000>;
803 no-map; 801 no-map;
804 hwlocks = <&tcsr_mutex 802 hwlocks = <&tcsr_mutex 3>;
805 }; 803 };
806 804
807 tz_mem: tz@86200000 { 805 tz_mem: tz@86200000 {
808 reg = <0 0x86200000 0 806 reg = <0 0x86200000 0 0x2d00000>;
809 no-map; 807 no-map;
810 }; 808 };
811 809
812 rmtfs_mem: rmtfs@88f00000 { 810 rmtfs_mem: rmtfs@88f00000 {
813 compatible = "qcom,rmt 811 compatible = "qcom,rmtfs-mem";
814 reg = <0 0x88f00000 0 812 reg = <0 0x88f00000 0 0x200000>;
815 no-map; 813 no-map;
816 814
817 qcom,client-id = <1>; 815 qcom,client-id = <1>;
818 qcom,vmid = <QCOM_SCM_ !! 816 qcom,vmid = <15>;
819 }; 817 };
820 818
821 qseecom_mem: qseecom@8ab00000 819 qseecom_mem: qseecom@8ab00000 {
822 reg = <0 0x8ab00000 0 820 reg = <0 0x8ab00000 0 0x1400000>;
823 no-map; 821 no-map;
824 }; 822 };
825 823
826 camera_mem: camera-mem@8bf0000 824 camera_mem: camera-mem@8bf00000 {
827 reg = <0 0x8bf00000 0 825 reg = <0 0x8bf00000 0 0x500000>;
828 no-map; 826 no-map;
829 }; 827 };
830 828
831 ipa_fw_mem: ipa-fw@8c400000 { 829 ipa_fw_mem: ipa-fw@8c400000 {
832 reg = <0 0x8c400000 0 830 reg = <0 0x8c400000 0 0x10000>;
833 no-map; 831 no-map;
834 }; 832 };
835 833
836 ipa_gsi_mem: ipa-gsi@8c410000 834 ipa_gsi_mem: ipa-gsi@8c410000 {
837 reg = <0 0x8c410000 0 835 reg = <0 0x8c410000 0 0x5000>;
838 no-map; 836 no-map;
839 }; 837 };
840 838
841 gpu_mem: gpu@8c415000 { 839 gpu_mem: gpu@8c415000 {
842 reg = <0 0x8c415000 0 840 reg = <0 0x8c415000 0 0x2000>;
843 no-map; 841 no-map;
844 }; 842 };
845 843
846 adsp_mem: adsp@8c500000 { 844 adsp_mem: adsp@8c500000 {
847 reg = <0 0x8c500000 0 845 reg = <0 0x8c500000 0 0x1a00000>;
848 no-map; 846 no-map;
849 }; 847 };
850 848
851 wlan_msa_mem: wlan-msa@8df0000 849 wlan_msa_mem: wlan-msa@8df00000 {
852 reg = <0 0x8df00000 0 850 reg = <0 0x8df00000 0 0x100000>;
853 no-map; 851 no-map;
854 }; 852 };
855 853
856 mpss_region: mpss@8e000000 { 854 mpss_region: mpss@8e000000 {
857 reg = <0 0x8e000000 0 855 reg = <0 0x8e000000 0 0x7800000>;
858 no-map; 856 no-map;
859 }; 857 };
860 858
861 venus_mem: venus@95800000 { 859 venus_mem: venus@95800000 {
862 reg = <0 0x95800000 0 860 reg = <0 0x95800000 0 0x500000>;
863 no-map; 861 no-map;
864 }; 862 };
865 863
866 cdsp_mem: cdsp@95d00000 { 864 cdsp_mem: cdsp@95d00000 {
867 reg = <0 0x95d00000 0 865 reg = <0 0x95d00000 0 0x800000>;
868 no-map; 866 no-map;
869 }; 867 };
870 868
871 mba_region: mba@96500000 { 869 mba_region: mba@96500000 {
872 reg = <0 0x96500000 0 870 reg = <0 0x96500000 0 0x200000>;
873 no-map; 871 no-map;
874 }; 872 };
875 873
876 slpi_mem: slpi@96700000 { 874 slpi_mem: slpi@96700000 {
877 reg = <0 0x96700000 0 875 reg = <0 0x96700000 0 0x1400000>;
878 no-map; 876 no-map;
879 }; 877 };
880 878
881 spss_mem: spss@97b00000 { 879 spss_mem: spss@97b00000 {
882 reg = <0 0x97b00000 0 880 reg = <0 0x97b00000 0 0x100000>;
883 no-map; 881 no-map;
884 }; 882 };
885 883
886 mdata_mem: mpss-metadata { 884 mdata_mem: mpss-metadata {
887 alloc-ranges = <0 0xa0 885 alloc-ranges = <0 0xa0000000 0 0x20000000>;
888 size = <0 0x4000>; 886 size = <0 0x4000>;
889 no-map; 887 no-map;
890 }; 888 };
891 889
892 fastrpc_mem: fastrpc { 890 fastrpc_mem: fastrpc {
893 compatible = "shared-d 891 compatible = "shared-dma-pool";
894 alloc-ranges = <0x0 0x 892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
895 alignment = <0x0 0x400 893 alignment = <0x0 0x400000>;
896 size = <0x0 0x1000000> 894 size = <0x0 0x1000000>;
897 reusable; 895 reusable;
898 }; 896 };
899 }; 897 };
900 898
901 adsp_pas: remoteproc-adsp { 899 adsp_pas: remoteproc-adsp {
902 compatible = "qcom,sdm845-adsp 900 compatible = "qcom,sdm845-adsp-pas";
903 901
904 interrupts-extended = <&intc G 902 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
905 <&adsp_s 903 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
906 <&adsp_s 904 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
907 <&adsp_s 905 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
908 <&adsp_s 906 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
909 interrupt-names = "wdog", "fat 907 interrupt-names = "wdog", "fatal", "ready",
910 "handover", 908 "handover", "stop-ack";
911 909
912 clocks = <&rpmhcc RPMH_CXO_CLK 910 clocks = <&rpmhcc RPMH_CXO_CLK>;
913 clock-names = "xo"; 911 clock-names = "xo";
914 912
915 memory-region = <&adsp_mem>; 913 memory-region = <&adsp_mem>;
916 914
917 qcom,qmp = <&aoss_qmp>; 915 qcom,qmp = <&aoss_qmp>;
918 916
919 qcom,smem-states = <&adsp_smp2 917 qcom,smem-states = <&adsp_smp2p_out 0>;
920 qcom,smem-state-names = "stop" 918 qcom,smem-state-names = "stop";
921 919
922 status = "disabled"; 920 status = "disabled";
923 921
924 glink-edge { 922 glink-edge {
925 interrupts = <GIC_SPI 923 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
926 label = "lpass"; 924 label = "lpass";
927 qcom,remote-pid = <2>; 925 qcom,remote-pid = <2>;
928 mboxes = <&apss_shared 926 mboxes = <&apss_shared 8>;
929 927
930 apr { 928 apr {
931 compatible = " 929 compatible = "qcom,apr-v2";
932 qcom,glink-cha 930 qcom,glink-channels = "apr_audio_svc";
933 qcom,domain = 931 qcom,domain = <APR_DOMAIN_ADSP>;
934 #address-cells 932 #address-cells = <1>;
935 #size-cells = 933 #size-cells = <0>;
936 qcom,intents = 934 qcom,intents = <512 20>;
937 935
938 service@3 { 936 service@3 {
939 reg = 937 reg = <APR_SVC_ADSP_CORE>;
940 compat 938 compatible = "qcom,q6core";
941 qcom,p 939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
942 }; 940 };
943 941
944 q6afe: service 942 q6afe: service@4 {
945 compat 943 compatible = "qcom,q6afe";
946 reg = 944 reg = <APR_SVC_AFE>;
947 qcom,p 945 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
948 q6afed 946 q6afedai: dais {
949 947 compatible = "qcom,q6afe-dais";
950 948 #address-cells = <1>;
951 949 #size-cells = <0>;
952 950 #sound-dai-cells = <1>;
953 }; 951 };
954 }; 952 };
955 953
956 q6asm: service 954 q6asm: service@7 {
957 compat 955 compatible = "qcom,q6asm";
958 reg = 956 reg = <APR_SVC_ASM>;
959 qcom,p 957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
960 q6asmd 958 q6asmdai: dais {
961 959 compatible = "qcom,q6asm-dais";
962 960 #address-cells = <1>;
963 961 #size-cells = <0>;
964 962 #sound-dai-cells = <1>;
965 963 iommus = <&apps_smmu 0x1821 0x0>;
966 }; 964 };
967 }; 965 };
968 966
969 q6adm: service 967 q6adm: service@8 {
970 compat 968 compatible = "qcom,q6adm";
971 reg = 969 reg = <APR_SVC_ADM>;
972 qcom,p 970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
973 q6rout 971 q6routing: routing {
974 972 compatible = "qcom,q6adm-routing";
975 973 #sound-dai-cells = <0>;
976 }; 974 };
977 }; 975 };
978 }; 976 };
979 977
980 fastrpc { 978 fastrpc {
981 compatible = " 979 compatible = "qcom,fastrpc";
982 qcom,glink-cha 980 qcom,glink-channels = "fastrpcglink-apps-dsp";
983 label = "adsp" 981 label = "adsp";
984 qcom,non-secur 982 qcom,non-secure-domain;
985 #address-cells 983 #address-cells = <1>;
986 #size-cells = 984 #size-cells = <0>;
987 985
988 compute-cb@3 { 986 compute-cb@3 {
989 compat 987 compatible = "qcom,fastrpc-compute-cb";
990 reg = 988 reg = <3>;
991 iommus 989 iommus = <&apps_smmu 0x1823 0x0>;
992 }; 990 };
993 991
994 compute-cb@4 { 992 compute-cb@4 {
995 compat 993 compatible = "qcom,fastrpc-compute-cb";
996 reg = 994 reg = <4>;
997 iommus 995 iommus = <&apps_smmu 0x1824 0x0>;
998 }; 996 };
999 }; 997 };
1000 }; 998 };
1001 }; 999 };
1002 1000
1003 cdsp_pas: remoteproc-cdsp { 1001 cdsp_pas: remoteproc-cdsp {
1004 compatible = "qcom,sdm845-cds 1002 compatible = "qcom,sdm845-cdsp-pas";
1005 1003
1006 interrupts-extended = <&intc 1004 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1007 <&cdsp_ 1005 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1008 <&cdsp_ 1006 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1009 <&cdsp_ 1007 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1010 <&cdsp_ 1008 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1011 interrupt-names = "wdog", "fa 1009 interrupt-names = "wdog", "fatal", "ready",
1012 "handover", 1010 "handover", "stop-ack";
1013 1011
1014 clocks = <&rpmhcc RPMH_CXO_CL 1012 clocks = <&rpmhcc RPMH_CXO_CLK>;
1015 clock-names = "xo"; 1013 clock-names = "xo";
1016 1014
1017 memory-region = <&cdsp_mem>; 1015 memory-region = <&cdsp_mem>;
1018 1016
1019 qcom,qmp = <&aoss_qmp>; 1017 qcom,qmp = <&aoss_qmp>;
1020 1018
1021 qcom,smem-states = <&cdsp_smp 1019 qcom,smem-states = <&cdsp_smp2p_out 0>;
1022 qcom,smem-state-names = "stop 1020 qcom,smem-state-names = "stop";
1023 1021
1024 status = "disabled"; 1022 status = "disabled";
1025 1023
1026 glink-edge { 1024 glink-edge {
1027 interrupts = <GIC_SPI 1025 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
1028 label = "turing"; 1026 label = "turing";
1029 qcom,remote-pid = <5> 1027 qcom,remote-pid = <5>;
1030 mboxes = <&apss_share 1028 mboxes = <&apss_shared 4>;
1031 fastrpc { 1029 fastrpc {
1032 compatible = 1030 compatible = "qcom,fastrpc";
1033 qcom,glink-ch 1031 qcom,glink-channels = "fastrpcglink-apps-dsp";
1034 label = "cdsp 1032 label = "cdsp";
1035 qcom,non-secu 1033 qcom,non-secure-domain;
1036 #address-cell 1034 #address-cells = <1>;
1037 #size-cells = 1035 #size-cells = <0>;
1038 1036
1039 compute-cb@1 1037 compute-cb@1 {
1040 compa 1038 compatible = "qcom,fastrpc-compute-cb";
1041 reg = 1039 reg = <1>;
1042 iommu 1040 iommus = <&apps_smmu 0x1401 0x30>;
1043 }; 1041 };
1044 1042
1045 compute-cb@2 1043 compute-cb@2 {
1046 compa 1044 compatible = "qcom,fastrpc-compute-cb";
1047 reg = 1045 reg = <2>;
1048 iommu 1046 iommus = <&apps_smmu 0x1402 0x30>;
1049 }; 1047 };
1050 1048
1051 compute-cb@3 1049 compute-cb@3 {
1052 compa 1050 compatible = "qcom,fastrpc-compute-cb";
1053 reg = 1051 reg = <3>;
1054 iommu 1052 iommus = <&apps_smmu 0x1403 0x30>;
1055 }; 1053 };
1056 1054
1057 compute-cb@4 1055 compute-cb@4 {
1058 compa 1056 compatible = "qcom,fastrpc-compute-cb";
1059 reg = 1057 reg = <4>;
1060 iommu 1058 iommus = <&apps_smmu 0x1404 0x30>;
1061 }; 1059 };
1062 1060
1063 compute-cb@5 1061 compute-cb@5 {
1064 compa 1062 compatible = "qcom,fastrpc-compute-cb";
1065 reg = 1063 reg = <5>;
1066 iommu 1064 iommus = <&apps_smmu 0x1405 0x30>;
1067 }; 1065 };
1068 1066
1069 compute-cb@6 1067 compute-cb@6 {
1070 compa 1068 compatible = "qcom,fastrpc-compute-cb";
1071 reg = 1069 reg = <6>;
1072 iommu 1070 iommus = <&apps_smmu 0x1406 0x30>;
1073 }; 1071 };
1074 1072
1075 compute-cb@7 1073 compute-cb@7 {
1076 compa 1074 compatible = "qcom,fastrpc-compute-cb";
1077 reg = 1075 reg = <7>;
1078 iommu 1076 iommus = <&apps_smmu 0x1407 0x30>;
1079 }; 1077 };
1080 1078
1081 compute-cb@8 1079 compute-cb@8 {
1082 compa 1080 compatible = "qcom,fastrpc-compute-cb";
1083 reg = 1081 reg = <8>;
1084 iommu 1082 iommus = <&apps_smmu 0x1408 0x30>;
1085 }; 1083 };
1086 }; 1084 };
1087 }; 1085 };
1088 }; 1086 };
1089 1087
1090 smp2p-cdsp { 1088 smp2p-cdsp {
1091 compatible = "qcom,smp2p"; 1089 compatible = "qcom,smp2p";
1092 qcom,smem = <94>, <432>; 1090 qcom,smem = <94>, <432>;
1093 1091
1094 interrupts = <GIC_SPI 576 IRQ 1092 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
1095 1093
1096 mboxes = <&apss_shared 6>; 1094 mboxes = <&apss_shared 6>;
1097 1095
1098 qcom,local-pid = <0>; 1096 qcom,local-pid = <0>;
1099 qcom,remote-pid = <5>; 1097 qcom,remote-pid = <5>;
1100 1098
1101 cdsp_smp2p_out: master-kernel 1099 cdsp_smp2p_out: master-kernel {
1102 qcom,entry-name = "ma 1100 qcom,entry-name = "master-kernel";
1103 #qcom,smem-state-cell 1101 #qcom,smem-state-cells = <1>;
1104 }; 1102 };
1105 1103
1106 cdsp_smp2p_in: slave-kernel { 1104 cdsp_smp2p_in: slave-kernel {
1107 qcom,entry-name = "sl 1105 qcom,entry-name = "slave-kernel";
1108 1106
1109 interrupt-controller; 1107 interrupt-controller;
1110 #interrupt-cells = <2 1108 #interrupt-cells = <2>;
1111 }; 1109 };
1112 }; 1110 };
1113 1111
1114 smp2p-lpass { 1112 smp2p-lpass {
1115 compatible = "qcom,smp2p"; 1113 compatible = "qcom,smp2p";
1116 qcom,smem = <443>, <429>; 1114 qcom,smem = <443>, <429>;
1117 1115
1118 interrupts = <GIC_SPI 158 IRQ 1116 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1119 1117
1120 mboxes = <&apss_shared 10>; 1118 mboxes = <&apss_shared 10>;
1121 1119
1122 qcom,local-pid = <0>; 1120 qcom,local-pid = <0>;
1123 qcom,remote-pid = <2>; 1121 qcom,remote-pid = <2>;
1124 1122
1125 adsp_smp2p_out: master-kernel 1123 adsp_smp2p_out: master-kernel {
1126 qcom,entry-name = "ma 1124 qcom,entry-name = "master-kernel";
1127 #qcom,smem-state-cell 1125 #qcom,smem-state-cells = <1>;
1128 }; 1126 };
1129 1127
1130 adsp_smp2p_in: slave-kernel { 1128 adsp_smp2p_in: slave-kernel {
1131 qcom,entry-name = "sl 1129 qcom,entry-name = "slave-kernel";
1132 1130
1133 interrupt-controller; 1131 interrupt-controller;
1134 #interrupt-cells = <2 1132 #interrupt-cells = <2>;
1135 }; 1133 };
1136 }; 1134 };
1137 1135
1138 smp2p-mpss { 1136 smp2p-mpss {
1139 compatible = "qcom,smp2p"; 1137 compatible = "qcom,smp2p";
1140 qcom,smem = <435>, <428>; 1138 qcom,smem = <435>, <428>;
1141 interrupts = <GIC_SPI 451 IRQ 1139 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1142 mboxes = <&apss_shared 14>; 1140 mboxes = <&apss_shared 14>;
1143 qcom,local-pid = <0>; 1141 qcom,local-pid = <0>;
1144 qcom,remote-pid = <1>; 1142 qcom,remote-pid = <1>;
1145 1143
1146 modem_smp2p_out: master-kerne 1144 modem_smp2p_out: master-kernel {
1147 qcom,entry-name = "ma 1145 qcom,entry-name = "master-kernel";
1148 #qcom,smem-state-cell 1146 #qcom,smem-state-cells = <1>;
1149 }; 1147 };
1150 1148
1151 modem_smp2p_in: slave-kernel 1149 modem_smp2p_in: slave-kernel {
1152 qcom,entry-name = "sl 1150 qcom,entry-name = "slave-kernel";
1153 interrupt-controller; 1151 interrupt-controller;
1154 #interrupt-cells = <2 1152 #interrupt-cells = <2>;
1155 }; 1153 };
1156 1154
1157 ipa_smp2p_out: ipa-ap-to-mode 1155 ipa_smp2p_out: ipa-ap-to-modem {
1158 qcom,entry-name = "ip 1156 qcom,entry-name = "ipa";
1159 #qcom,smem-state-cell 1157 #qcom,smem-state-cells = <1>;
1160 }; 1158 };
1161 1159
1162 ipa_smp2p_in: ipa-modem-to-ap 1160 ipa_smp2p_in: ipa-modem-to-ap {
1163 qcom,entry-name = "ip 1161 qcom,entry-name = "ipa";
1164 interrupt-controller; 1162 interrupt-controller;
1165 #interrupt-cells = <2 1163 #interrupt-cells = <2>;
1166 }; 1164 };
1167 }; 1165 };
1168 1166
1169 smp2p-slpi { 1167 smp2p-slpi {
1170 compatible = "qcom,smp2p"; 1168 compatible = "qcom,smp2p";
1171 qcom,smem = <481>, <430>; 1169 qcom,smem = <481>, <430>;
1172 interrupts = <GIC_SPI 172 IRQ 1170 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
1173 mboxes = <&apss_shared 26>; 1171 mboxes = <&apss_shared 26>;
1174 qcom,local-pid = <0>; 1172 qcom,local-pid = <0>;
1175 qcom,remote-pid = <3>; 1173 qcom,remote-pid = <3>;
1176 1174
1177 slpi_smp2p_out: master-kernel 1175 slpi_smp2p_out: master-kernel {
1178 qcom,entry-name = "ma 1176 qcom,entry-name = "master-kernel";
1179 #qcom,smem-state-cell 1177 #qcom,smem-state-cells = <1>;
1180 }; 1178 };
1181 1179
1182 slpi_smp2p_in: slave-kernel { 1180 slpi_smp2p_in: slave-kernel {
1183 qcom,entry-name = "sl 1181 qcom,entry-name = "slave-kernel";
1184 interrupt-controller; 1182 interrupt-controller;
1185 #interrupt-cells = <2 1183 #interrupt-cells = <2>;
1186 }; 1184 };
1187 }; 1185 };
1188 1186
1189 soc: soc@0 { 1187 soc: soc@0 {
1190 #address-cells = <2>; 1188 #address-cells = <2>;
1191 #size-cells = <2>; 1189 #size-cells = <2>;
1192 ranges = <0 0 0 0 0x10 0>; 1190 ranges = <0 0 0 0 0x10 0>;
1193 dma-ranges = <0 0 0 0 0x10 0> 1191 dma-ranges = <0 0 0 0 0x10 0>;
1194 compatible = "simple-bus"; 1192 compatible = "simple-bus";
1195 1193
1196 gcc: clock-controller@100000 1194 gcc: clock-controller@100000 {
1197 compatible = "qcom,gc 1195 compatible = "qcom,gcc-sdm845";
1198 reg = <0 0x00100000 0 1196 reg = <0 0x00100000 0 0x1f0000>;
1199 clocks = <&rpmhcc RPM 1197 clocks = <&rpmhcc RPMH_CXO_CLK>,
1200 <&rpmhcc RPM 1198 <&rpmhcc RPMH_CXO_CLK_A>,
1201 <&sleep_clk> 1199 <&sleep_clk>,
1202 <&pcie0_phy> !! 1200 <&pcie0_lane>,
1203 <&pcie1_phy> !! 1201 <&pcie1_lane>;
1204 clock-names = "bi_tcx 1202 clock-names = "bi_tcxo",
1205 "bi_tcx 1203 "bi_tcxo_ao",
1206 "sleep_ 1204 "sleep_clk",
1207 "pcie_0 1205 "pcie_0_pipe_clk",
1208 "pcie_1 1206 "pcie_1_pipe_clk";
1209 #clock-cells = <1>; 1207 #clock-cells = <1>;
1210 #reset-cells = <1>; 1208 #reset-cells = <1>;
1211 #power-domain-cells = 1209 #power-domain-cells = <1>;
1212 power-domains = <&rpm 1210 power-domains = <&rpmhpd SDM845_CX>;
1213 }; 1211 };
1214 1212
1215 qfprom@784000 { 1213 qfprom@784000 {
1216 compatible = "qcom,sd 1214 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1217 reg = <0 0x00784000 0 1215 reg = <0 0x00784000 0 0x8ff>;
1218 #address-cells = <1>; 1216 #address-cells = <1>;
1219 #size-cells = <1>; 1217 #size-cells = <1>;
1220 1218
1221 qusb2p_hstx_trim: hst 1219 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1222 reg = <0x1eb 1220 reg = <0x1eb 0x1>;
1223 bits = <1 4>; 1221 bits = <1 4>;
1224 }; 1222 };
1225 1223
1226 qusb2s_hstx_trim: hst 1224 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1227 reg = <0x1eb 1225 reg = <0x1eb 0x2>;
1228 bits = <6 4>; 1226 bits = <6 4>;
1229 }; 1227 };
1230 }; 1228 };
1231 1229
1232 rng: rng@793000 { 1230 rng: rng@793000 {
1233 compatible = "qcom,pr 1231 compatible = "qcom,prng-ee";
1234 reg = <0 0x00793000 0 1232 reg = <0 0x00793000 0 0x1000>;
1235 clocks = <&gcc GCC_PR 1233 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1236 clock-names = "core"; 1234 clock-names = "core";
1237 }; 1235 };
1238 1236
1239 gpi_dma0: dma-controller@8000 1237 gpi_dma0: dma-controller@800000 {
1240 #dma-cells = <3>; 1238 #dma-cells = <3>;
1241 compatible = "qcom,sd 1239 compatible = "qcom,sdm845-gpi-dma";
1242 reg = <0 0x00800000 0 1240 reg = <0 0x00800000 0 0x60000>;
1243 interrupts = <GIC_SPI 1241 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 1242 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 1243 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 1244 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 1245 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 1246 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 1247 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 1248 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 1249 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 1250 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 1251 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 1252 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 1253 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1256 dma-channels = <13>; 1254 dma-channels = <13>;
1257 dma-channel-mask = <0 1255 dma-channel-mask = <0xfa>;
1258 iommus = <&apps_smmu 1256 iommus = <&apps_smmu 0x0016 0x0>;
1259 status = "disabled"; 1257 status = "disabled";
1260 }; 1258 };
1261 1259
1262 qupv3_id_0: geniqup@8c0000 { 1260 qupv3_id_0: geniqup@8c0000 {
1263 compatible = "qcom,ge 1261 compatible = "qcom,geni-se-qup";
1264 reg = <0 0x008c0000 0 1262 reg = <0 0x008c0000 0 0x6000>;
1265 clock-names = "m-ahb" 1263 clock-names = "m-ahb", "s-ahb";
1266 clocks = <&gcc GCC_QU 1264 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1267 <&gcc GCC_QU 1265 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1268 iommus = <&apps_smmu 1266 iommus = <&apps_smmu 0x3 0x0>;
1269 #address-cells = <2>; 1267 #address-cells = <2>;
1270 #size-cells = <2>; 1268 #size-cells = <2>;
1271 ranges; 1269 ranges;
1272 interconnects = <&agg 1270 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1273 interconnect-names = 1271 interconnect-names = "qup-core";
1274 status = "disabled"; 1272 status = "disabled";
1275 1273
1276 i2c0: i2c@880000 { 1274 i2c0: i2c@880000 {
1277 compatible = 1275 compatible = "qcom,geni-i2c";
1278 reg = <0 0x00 1276 reg = <0 0x00880000 0 0x4000>;
1279 clock-names = 1277 clock-names = "se";
1280 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1281 pinctrl-names 1279 pinctrl-names = "default";
1282 pinctrl-0 = < 1280 pinctrl-0 = <&qup_i2c0_default>;
1283 interrupts = 1281 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1284 #address-cell 1282 #address-cells = <1>;
1285 #size-cells = 1283 #size-cells = <0>;
1286 power-domains 1284 power-domains = <&rpmhpd SDM845_CX>;
1287 operating-poi 1285 operating-points-v2 = <&qup_opp_table>;
1288 interconnects 1286 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1289 1287 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1290 1288 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1291 interconnect- 1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dmas = <&gpi_ 1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1293 <&gpi_ 1291 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1294 dma-names = " 1292 dma-names = "tx", "rx";
1295 status = "dis 1293 status = "disabled";
1296 }; 1294 };
1297 1295
1298 spi0: spi@880000 { 1296 spi0: spi@880000 {
1299 compatible = 1297 compatible = "qcom,geni-spi";
1300 reg = <0 0x00 1298 reg = <0 0x00880000 0 0x4000>;
1301 clock-names = 1299 clock-names = "se";
1302 clocks = <&gc 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1303 pinctrl-names 1301 pinctrl-names = "default";
1304 pinctrl-0 = < 1302 pinctrl-0 = <&qup_spi0_default>;
1305 interrupts = 1303 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1306 #address-cell 1304 #address-cells = <1>;
1307 #size-cells = 1305 #size-cells = <0>;
1308 interconnects 1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1309 1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1310 interconnect- 1308 interconnect-names = "qup-core", "qup-config";
1311 dmas = <&gpi_ 1309 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1312 <&gpi_ 1310 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1313 dma-names = " 1311 dma-names = "tx", "rx";
1314 status = "dis 1312 status = "disabled";
1315 }; 1313 };
1316 1314
1317 uart0: serial@880000 1315 uart0: serial@880000 {
1318 compatible = 1316 compatible = "qcom,geni-uart";
1319 reg = <0 0x00 1317 reg = <0 0x00880000 0 0x4000>;
1320 clock-names = 1318 clock-names = "se";
1321 clocks = <&gc 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1322 pinctrl-names 1320 pinctrl-names = "default";
1323 pinctrl-0 = < 1321 pinctrl-0 = <&qup_uart0_default>;
1324 interrupts = 1322 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1325 power-domains 1323 power-domains = <&rpmhpd SDM845_CX>;
1326 operating-poi 1324 operating-points-v2 = <&qup_opp_table>;
1327 interconnects 1325 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1328 1326 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1329 interconnect- 1327 interconnect-names = "qup-core", "qup-config";
1330 status = "dis 1328 status = "disabled";
1331 }; 1329 };
1332 1330
1333 i2c1: i2c@884000 { 1331 i2c1: i2c@884000 {
1334 compatible = 1332 compatible = "qcom,geni-i2c";
1335 reg = <0 0x00 1333 reg = <0 0x00884000 0 0x4000>;
1336 clock-names = 1334 clock-names = "se";
1337 clocks = <&gc 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1338 pinctrl-names 1336 pinctrl-names = "default";
1339 pinctrl-0 = < 1337 pinctrl-0 = <&qup_i2c1_default>;
1340 interrupts = 1338 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1341 #address-cell 1339 #address-cells = <1>;
1342 #size-cells = 1340 #size-cells = <0>;
1343 power-domains 1341 power-domains = <&rpmhpd SDM845_CX>;
1344 operating-poi 1342 operating-points-v2 = <&qup_opp_table>;
1345 interconnects 1343 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1346 1344 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1347 1345 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1348 interconnect- 1346 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dmas = <&gpi_ 1347 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1350 <&gpi_ 1348 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1351 dma-names = " 1349 dma-names = "tx", "rx";
1352 status = "dis 1350 status = "disabled";
1353 }; 1351 };
1354 1352
1355 spi1: spi@884000 { 1353 spi1: spi@884000 {
1356 compatible = 1354 compatible = "qcom,geni-spi";
1357 reg = <0 0x00 1355 reg = <0 0x00884000 0 0x4000>;
1358 clock-names = 1356 clock-names = "se";
1359 clocks = <&gc 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1360 pinctrl-names 1358 pinctrl-names = "default";
1361 pinctrl-0 = < 1359 pinctrl-0 = <&qup_spi1_default>;
1362 interrupts = 1360 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1363 #address-cell 1361 #address-cells = <1>;
1364 #size-cells = 1362 #size-cells = <0>;
1365 interconnects 1363 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1366 1364 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1367 interconnect- 1365 interconnect-names = "qup-core", "qup-config";
1368 dmas = <&gpi_ 1366 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1369 <&gpi_ 1367 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1370 dma-names = " 1368 dma-names = "tx", "rx";
1371 status = "dis 1369 status = "disabled";
1372 }; 1370 };
1373 1371
1374 uart1: serial@884000 1372 uart1: serial@884000 {
1375 compatible = 1373 compatible = "qcom,geni-uart";
1376 reg = <0 0x00 1374 reg = <0 0x00884000 0 0x4000>;
1377 clock-names = 1375 clock-names = "se";
1378 clocks = <&gc 1376 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1379 pinctrl-names 1377 pinctrl-names = "default";
1380 pinctrl-0 = < 1378 pinctrl-0 = <&qup_uart1_default>;
1381 interrupts = 1379 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1382 power-domains 1380 power-domains = <&rpmhpd SDM845_CX>;
1383 operating-poi 1381 operating-points-v2 = <&qup_opp_table>;
1384 interconnects 1382 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1385 1383 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1386 interconnect- 1384 interconnect-names = "qup-core", "qup-config";
1387 status = "dis 1385 status = "disabled";
1388 }; 1386 };
1389 1387
1390 i2c2: i2c@888000 { 1388 i2c2: i2c@888000 {
1391 compatible = 1389 compatible = "qcom,geni-i2c";
1392 reg = <0 0x00 1390 reg = <0 0x00888000 0 0x4000>;
1393 clock-names = 1391 clock-names = "se";
1394 clocks = <&gc 1392 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1395 pinctrl-names 1393 pinctrl-names = "default";
1396 pinctrl-0 = < 1394 pinctrl-0 = <&qup_i2c2_default>;
1397 interrupts = 1395 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1398 #address-cell 1396 #address-cells = <1>;
1399 #size-cells = 1397 #size-cells = <0>;
1400 power-domains 1398 power-domains = <&rpmhpd SDM845_CX>;
1401 operating-poi 1399 operating-points-v2 = <&qup_opp_table>;
1402 interconnects 1400 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1403 1401 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1404 1402 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1405 interconnect- 1403 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dmas = <&gpi_ 1404 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1407 <&gpi_ 1405 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1408 dma-names = " 1406 dma-names = "tx", "rx";
1409 status = "dis 1407 status = "disabled";
1410 }; 1408 };
1411 1409
1412 spi2: spi@888000 { 1410 spi2: spi@888000 {
1413 compatible = 1411 compatible = "qcom,geni-spi";
1414 reg = <0 0x00 1412 reg = <0 0x00888000 0 0x4000>;
1415 clock-names = 1413 clock-names = "se";
1416 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1417 pinctrl-names 1415 pinctrl-names = "default";
1418 pinctrl-0 = < 1416 pinctrl-0 = <&qup_spi2_default>;
1419 interrupts = 1417 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1420 #address-cell 1418 #address-cells = <1>;
1421 #size-cells = 1419 #size-cells = <0>;
1422 interconnects 1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1423 1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1424 interconnect- 1422 interconnect-names = "qup-core", "qup-config";
1425 dmas = <&gpi_ 1423 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1426 <&gpi_ 1424 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1427 dma-names = " 1425 dma-names = "tx", "rx";
1428 status = "dis 1426 status = "disabled";
1429 }; 1427 };
1430 1428
1431 uart2: serial@888000 1429 uart2: serial@888000 {
1432 compatible = 1430 compatible = "qcom,geni-uart";
1433 reg = <0 0x00 1431 reg = <0 0x00888000 0 0x4000>;
1434 clock-names = 1432 clock-names = "se";
1435 clocks = <&gc 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1436 pinctrl-names 1434 pinctrl-names = "default";
1437 pinctrl-0 = < 1435 pinctrl-0 = <&qup_uart2_default>;
1438 interrupts = 1436 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1439 power-domains 1437 power-domains = <&rpmhpd SDM845_CX>;
1440 operating-poi 1438 operating-points-v2 = <&qup_opp_table>;
1441 interconnects 1439 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1442 1440 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1443 interconnect- 1441 interconnect-names = "qup-core", "qup-config";
1444 status = "dis 1442 status = "disabled";
1445 }; 1443 };
1446 1444
1447 i2c3: i2c@88c000 { 1445 i2c3: i2c@88c000 {
1448 compatible = 1446 compatible = "qcom,geni-i2c";
1449 reg = <0 0x00 1447 reg = <0 0x0088c000 0 0x4000>;
1450 clock-names = 1448 clock-names = "se";
1451 clocks = <&gc 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1452 pinctrl-names 1450 pinctrl-names = "default";
1453 pinctrl-0 = < 1451 pinctrl-0 = <&qup_i2c3_default>;
1454 interrupts = 1452 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1455 #address-cell 1453 #address-cells = <1>;
1456 #size-cells = 1454 #size-cells = <0>;
1457 power-domains 1455 power-domains = <&rpmhpd SDM845_CX>;
1458 operating-poi 1456 operating-points-v2 = <&qup_opp_table>;
1459 interconnects 1457 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1460 1458 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1461 1459 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1462 interconnect- 1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dmas = <&gpi_ 1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1464 <&gpi_ 1462 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1465 dma-names = " 1463 dma-names = "tx", "rx";
1466 status = "dis 1464 status = "disabled";
1467 }; 1465 };
1468 1466
1469 spi3: spi@88c000 { 1467 spi3: spi@88c000 {
1470 compatible = 1468 compatible = "qcom,geni-spi";
1471 reg = <0 0x00 1469 reg = <0 0x0088c000 0 0x4000>;
1472 clock-names = 1470 clock-names = "se";
1473 clocks = <&gc 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1474 pinctrl-names 1472 pinctrl-names = "default";
1475 pinctrl-0 = < 1473 pinctrl-0 = <&qup_spi3_default>;
1476 interrupts = 1474 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1477 #address-cell 1475 #address-cells = <1>;
1478 #size-cells = 1476 #size-cells = <0>;
1479 interconnects 1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1480 1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1481 interconnect- 1479 interconnect-names = "qup-core", "qup-config";
1482 dmas = <&gpi_ 1480 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1483 <&gpi_ 1481 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1484 dma-names = " 1482 dma-names = "tx", "rx";
1485 status = "dis 1483 status = "disabled";
1486 }; 1484 };
1487 1485
1488 uart3: serial@88c000 1486 uart3: serial@88c000 {
1489 compatible = 1487 compatible = "qcom,geni-uart";
1490 reg = <0 0x00 1488 reg = <0 0x0088c000 0 0x4000>;
1491 clock-names = 1489 clock-names = "se";
1492 clocks = <&gc 1490 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1493 pinctrl-names 1491 pinctrl-names = "default";
1494 pinctrl-0 = < 1492 pinctrl-0 = <&qup_uart3_default>;
1495 interrupts = 1493 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1496 power-domains 1494 power-domains = <&rpmhpd SDM845_CX>;
1497 operating-poi 1495 operating-points-v2 = <&qup_opp_table>;
1498 interconnects 1496 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1499 1497 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1500 interconnect- 1498 interconnect-names = "qup-core", "qup-config";
1501 status = "dis 1499 status = "disabled";
1502 }; 1500 };
1503 1501
1504 i2c4: i2c@890000 { 1502 i2c4: i2c@890000 {
1505 compatible = 1503 compatible = "qcom,geni-i2c";
1506 reg = <0 0x00 1504 reg = <0 0x00890000 0 0x4000>;
1507 clock-names = 1505 clock-names = "se";
1508 clocks = <&gc 1506 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1509 pinctrl-names 1507 pinctrl-names = "default";
1510 pinctrl-0 = < 1508 pinctrl-0 = <&qup_i2c4_default>;
1511 interrupts = 1509 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1512 #address-cell 1510 #address-cells = <1>;
1513 #size-cells = 1511 #size-cells = <0>;
1514 power-domains 1512 power-domains = <&rpmhpd SDM845_CX>;
1515 operating-poi 1513 operating-points-v2 = <&qup_opp_table>;
1516 interconnects 1514 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1517 1515 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1518 1516 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1519 interconnect- 1517 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dmas = <&gpi_ 1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521 <&gpi_ 1519 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522 dma-names = " 1520 dma-names = "tx", "rx";
1523 status = "dis 1521 status = "disabled";
1524 }; 1522 };
1525 1523
1526 spi4: spi@890000 { 1524 spi4: spi@890000 {
1527 compatible = 1525 compatible = "qcom,geni-spi";
1528 reg = <0 0x00 1526 reg = <0 0x00890000 0 0x4000>;
1529 clock-names = 1527 clock-names = "se";
1530 clocks = <&gc 1528 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1531 pinctrl-names 1529 pinctrl-names = "default";
1532 pinctrl-0 = < 1530 pinctrl-0 = <&qup_spi4_default>;
1533 interrupts = 1531 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1534 #address-cell 1532 #address-cells = <1>;
1535 #size-cells = 1533 #size-cells = <0>;
1536 interconnects 1534 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1537 1535 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1538 interconnect- 1536 interconnect-names = "qup-core", "qup-config";
1539 dmas = <&gpi_ 1537 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1540 <&gpi_ 1538 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1541 dma-names = " 1539 dma-names = "tx", "rx";
1542 status = "dis 1540 status = "disabled";
1543 }; 1541 };
1544 1542
1545 uart4: serial@890000 1543 uart4: serial@890000 {
1546 compatible = 1544 compatible = "qcom,geni-uart";
1547 reg = <0 0x00 1545 reg = <0 0x00890000 0 0x4000>;
1548 clock-names = 1546 clock-names = "se";
1549 clocks = <&gc 1547 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550 pinctrl-names 1548 pinctrl-names = "default";
1551 pinctrl-0 = < 1549 pinctrl-0 = <&qup_uart4_default>;
1552 interrupts = 1550 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1553 power-domains 1551 power-domains = <&rpmhpd SDM845_CX>;
1554 operating-poi 1552 operating-points-v2 = <&qup_opp_table>;
1555 interconnects 1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1556 1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1557 interconnect- 1555 interconnect-names = "qup-core", "qup-config";
1558 status = "dis 1556 status = "disabled";
1559 }; 1557 };
1560 1558
1561 i2c5: i2c@894000 { 1559 i2c5: i2c@894000 {
1562 compatible = 1560 compatible = "qcom,geni-i2c";
1563 reg = <0 0x00 1561 reg = <0 0x00894000 0 0x4000>;
1564 clock-names = 1562 clock-names = "se";
1565 clocks = <&gc 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1566 pinctrl-names 1564 pinctrl-names = "default";
1567 pinctrl-0 = < 1565 pinctrl-0 = <&qup_i2c5_default>;
1568 interrupts = 1566 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1569 #address-cell 1567 #address-cells = <1>;
1570 #size-cells = 1568 #size-cells = <0>;
1571 power-domains 1569 power-domains = <&rpmhpd SDM845_CX>;
1572 operating-poi 1570 operating-points-v2 = <&qup_opp_table>;
1573 interconnects 1571 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1574 1572 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1575 1573 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1576 interconnect- 1574 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dmas = <&gpi_ 1575 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1578 <&gpi_ 1576 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1579 dma-names = " 1577 dma-names = "tx", "rx";
1580 status = "dis 1578 status = "disabled";
1581 }; 1579 };
1582 1580
1583 spi5: spi@894000 { 1581 spi5: spi@894000 {
1584 compatible = 1582 compatible = "qcom,geni-spi";
1585 reg = <0 0x00 1583 reg = <0 0x00894000 0 0x4000>;
1586 clock-names = 1584 clock-names = "se";
1587 clocks = <&gc 1585 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1588 pinctrl-names 1586 pinctrl-names = "default";
1589 pinctrl-0 = < 1587 pinctrl-0 = <&qup_spi5_default>;
1590 interrupts = 1588 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1591 #address-cell 1589 #address-cells = <1>;
1592 #size-cells = 1590 #size-cells = <0>;
1593 interconnects 1591 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1594 1592 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1595 interconnect- 1593 interconnect-names = "qup-core", "qup-config";
1596 dmas = <&gpi_ 1594 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1597 <&gpi_ 1595 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1598 dma-names = " 1596 dma-names = "tx", "rx";
1599 status = "dis 1597 status = "disabled";
1600 }; 1598 };
1601 1599
1602 uart5: serial@894000 1600 uart5: serial@894000 {
1603 compatible = 1601 compatible = "qcom,geni-uart";
1604 reg = <0 0x00 1602 reg = <0 0x00894000 0 0x4000>;
1605 clock-names = 1603 clock-names = "se";
1606 clocks = <&gc 1604 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607 pinctrl-names 1605 pinctrl-names = "default";
1608 pinctrl-0 = < 1606 pinctrl-0 = <&qup_uart5_default>;
1609 interrupts = 1607 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1610 power-domains 1608 power-domains = <&rpmhpd SDM845_CX>;
1611 operating-poi 1609 operating-points-v2 = <&qup_opp_table>;
1612 interconnects 1610 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1613 1611 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1614 interconnect- 1612 interconnect-names = "qup-core", "qup-config";
1615 status = "dis 1613 status = "disabled";
1616 }; 1614 };
1617 1615
1618 i2c6: i2c@898000 { 1616 i2c6: i2c@898000 {
1619 compatible = 1617 compatible = "qcom,geni-i2c";
1620 reg = <0 0x00 1618 reg = <0 0x00898000 0 0x4000>;
1621 clock-names = 1619 clock-names = "se";
1622 clocks = <&gc 1620 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1623 pinctrl-names 1621 pinctrl-names = "default";
1624 pinctrl-0 = < 1622 pinctrl-0 = <&qup_i2c6_default>;
1625 interrupts = 1623 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1626 #address-cell 1624 #address-cells = <1>;
1627 #size-cells = 1625 #size-cells = <0>;
1628 power-domains 1626 power-domains = <&rpmhpd SDM845_CX>;
1629 operating-poi 1627 operating-points-v2 = <&qup_opp_table>;
1630 interconnects 1628 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1631 1629 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1632 1630 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1633 interconnect- 1631 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dmas = <&gpi_ 1632 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1635 <&gpi_ 1633 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1636 dma-names = " 1634 dma-names = "tx", "rx";
1637 status = "dis 1635 status = "disabled";
1638 }; 1636 };
1639 1637
1640 spi6: spi@898000 { 1638 spi6: spi@898000 {
1641 compatible = 1639 compatible = "qcom,geni-spi";
1642 reg = <0 0x00 1640 reg = <0 0x00898000 0 0x4000>;
1643 clock-names = 1641 clock-names = "se";
1644 clocks = <&gc 1642 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1645 pinctrl-names 1643 pinctrl-names = "default";
1646 pinctrl-0 = < 1644 pinctrl-0 = <&qup_spi6_default>;
1647 interrupts = 1645 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1648 #address-cell 1646 #address-cells = <1>;
1649 #size-cells = 1647 #size-cells = <0>;
1650 interconnects 1648 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1651 1649 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1652 interconnect- 1650 interconnect-names = "qup-core", "qup-config";
1653 dmas = <&gpi_ 1651 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1654 <&gpi_ 1652 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1655 dma-names = " 1653 dma-names = "tx", "rx";
1656 status = "dis 1654 status = "disabled";
1657 }; 1655 };
1658 1656
1659 uart6: serial@898000 1657 uart6: serial@898000 {
1660 compatible = 1658 compatible = "qcom,geni-uart";
1661 reg = <0 0x00 1659 reg = <0 0x00898000 0 0x4000>;
1662 clock-names = 1660 clock-names = "se";
1663 clocks = <&gc 1661 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1664 pinctrl-names 1662 pinctrl-names = "default";
1665 pinctrl-0 = < 1663 pinctrl-0 = <&qup_uart6_default>;
1666 interrupts = 1664 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1667 power-domains 1665 power-domains = <&rpmhpd SDM845_CX>;
1668 operating-poi 1666 operating-points-v2 = <&qup_opp_table>;
1669 interconnects 1667 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1670 1668 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1671 interconnect- 1669 interconnect-names = "qup-core", "qup-config";
1672 status = "dis 1670 status = "disabled";
1673 }; 1671 };
1674 1672
1675 i2c7: i2c@89c000 { 1673 i2c7: i2c@89c000 {
1676 compatible = 1674 compatible = "qcom,geni-i2c";
1677 reg = <0 0x00 1675 reg = <0 0x0089c000 0 0x4000>;
1678 clock-names = 1676 clock-names = "se";
1679 clocks = <&gc 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1680 pinctrl-names 1678 pinctrl-names = "default";
1681 pinctrl-0 = < 1679 pinctrl-0 = <&qup_i2c7_default>;
1682 interrupts = 1680 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1683 #address-cell 1681 #address-cells = <1>;
1684 #size-cells = 1682 #size-cells = <0>;
1685 power-domains 1683 power-domains = <&rpmhpd SDM845_CX>;
1686 operating-poi 1684 operating-points-v2 = <&qup_opp_table>;
1687 status = "dis 1685 status = "disabled";
1688 }; 1686 };
1689 1687
1690 spi7: spi@89c000 { 1688 spi7: spi@89c000 {
1691 compatible = 1689 compatible = "qcom,geni-spi";
1692 reg = <0 0x00 1690 reg = <0 0x0089c000 0 0x4000>;
1693 clock-names = 1691 clock-names = "se";
1694 clocks = <&gc 1692 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1695 pinctrl-names 1693 pinctrl-names = "default";
1696 pinctrl-0 = < 1694 pinctrl-0 = <&qup_spi7_default>;
1697 interrupts = 1695 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1698 #address-cell 1696 #address-cells = <1>;
1699 #size-cells = 1697 #size-cells = <0>;
1700 interconnects 1698 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1701 1699 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1702 interconnect- 1700 interconnect-names = "qup-core", "qup-config";
1703 dmas = <&gpi_ 1701 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1704 <&gpi_ 1702 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1705 dma-names = " 1703 dma-names = "tx", "rx";
1706 status = "dis 1704 status = "disabled";
1707 }; 1705 };
1708 1706
1709 uart7: serial@89c000 1707 uart7: serial@89c000 {
1710 compatible = 1708 compatible = "qcom,geni-uart";
1711 reg = <0 0x00 1709 reg = <0 0x0089c000 0 0x4000>;
1712 clock-names = 1710 clock-names = "se";
1713 clocks = <&gc 1711 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1714 pinctrl-names 1712 pinctrl-names = "default";
1715 pinctrl-0 = < 1713 pinctrl-0 = <&qup_uart7_default>;
1716 interrupts = 1714 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1717 power-domains 1715 power-domains = <&rpmhpd SDM845_CX>;
1718 operating-poi 1716 operating-points-v2 = <&qup_opp_table>;
1719 interconnects 1717 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1720 1718 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1721 interconnect- 1719 interconnect-names = "qup-core", "qup-config";
1722 status = "dis 1720 status = "disabled";
1723 }; 1721 };
1724 }; 1722 };
1725 1723
1726 gpi_dma1: dma-controller@a000 1724 gpi_dma1: dma-controller@a00000 {
1727 #dma-cells = <3>; 1725 #dma-cells = <3>;
1728 compatible = "qcom,sd 1726 compatible = "qcom,sdm845-gpi-dma";
1729 reg = <0 0x00a00000 0 1727 reg = <0 0x00a00000 0 0x60000>;
1730 interrupts = <GIC_SPI 1728 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 1729 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 1730 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 1731 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 1732 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 1733 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 1734 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 1735 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 1736 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 1737 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 1738 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 1739 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 1740 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1743 dma-channels = <13>; 1741 dma-channels = <13>;
1744 dma-channel-mask = <0 1742 dma-channel-mask = <0xfa>;
1745 iommus = <&apps_smmu 1743 iommus = <&apps_smmu 0x06d6 0x0>;
1746 status = "disabled"; 1744 status = "disabled";
1747 }; 1745 };
1748 1746
1749 qupv3_id_1: geniqup@ac0000 { 1747 qupv3_id_1: geniqup@ac0000 {
1750 compatible = "qcom,ge 1748 compatible = "qcom,geni-se-qup";
1751 reg = <0 0x00ac0000 0 1749 reg = <0 0x00ac0000 0 0x6000>;
1752 clock-names = "m-ahb" 1750 clock-names = "m-ahb", "s-ahb";
1753 clocks = <&gcc GCC_QU 1751 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1754 <&gcc GCC_QU 1752 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1755 iommus = <&apps_smmu 1753 iommus = <&apps_smmu 0x6c3 0x0>;
1756 #address-cells = <2>; 1754 #address-cells = <2>;
1757 #size-cells = <2>; 1755 #size-cells = <2>;
1758 ranges; 1756 ranges;
1759 interconnects = <&agg 1757 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1760 interconnect-names = 1758 interconnect-names = "qup-core";
1761 status = "disabled"; 1759 status = "disabled";
1762 1760
1763 i2c8: i2c@a80000 { 1761 i2c8: i2c@a80000 {
1764 compatible = 1762 compatible = "qcom,geni-i2c";
1765 reg = <0 0x00 1763 reg = <0 0x00a80000 0 0x4000>;
1766 clock-names = 1764 clock-names = "se";
1767 clocks = <&gc 1765 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1768 pinctrl-names 1766 pinctrl-names = "default";
1769 pinctrl-0 = < 1767 pinctrl-0 = <&qup_i2c8_default>;
1770 interrupts = 1768 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1771 #address-cell 1769 #address-cells = <1>;
1772 #size-cells = 1770 #size-cells = <0>;
1773 power-domains 1771 power-domains = <&rpmhpd SDM845_CX>;
1774 operating-poi 1772 operating-points-v2 = <&qup_opp_table>;
1775 interconnects 1773 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1776 1774 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1777 1775 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1778 interconnect- 1776 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dmas = <&gpi_ 1777 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1780 <&gpi_ 1778 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1781 dma-names = " 1779 dma-names = "tx", "rx";
1782 status = "dis 1780 status = "disabled";
1783 }; 1781 };
1784 1782
1785 spi8: spi@a80000 { 1783 spi8: spi@a80000 {
1786 compatible = 1784 compatible = "qcom,geni-spi";
1787 reg = <0 0x00 1785 reg = <0 0x00a80000 0 0x4000>;
1788 clock-names = 1786 clock-names = "se";
1789 clocks = <&gc 1787 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1790 pinctrl-names 1788 pinctrl-names = "default";
1791 pinctrl-0 = < 1789 pinctrl-0 = <&qup_spi8_default>;
1792 interrupts = 1790 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1793 #address-cell 1791 #address-cells = <1>;
1794 #size-cells = 1792 #size-cells = <0>;
1795 interconnects 1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1796 1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1797 interconnect- 1795 interconnect-names = "qup-core", "qup-config";
1798 dmas = <&gpi_ 1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1799 <&gpi_ 1797 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1800 dma-names = " 1798 dma-names = "tx", "rx";
1801 status = "dis 1799 status = "disabled";
1802 }; 1800 };
1803 1801
1804 uart8: serial@a80000 1802 uart8: serial@a80000 {
1805 compatible = 1803 compatible = "qcom,geni-uart";
1806 reg = <0 0x00 1804 reg = <0 0x00a80000 0 0x4000>;
1807 clock-names = 1805 clock-names = "se";
1808 clocks = <&gc 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1809 pinctrl-names 1807 pinctrl-names = "default";
1810 pinctrl-0 = < 1808 pinctrl-0 = <&qup_uart8_default>;
1811 interrupts = 1809 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1812 power-domains 1810 power-domains = <&rpmhpd SDM845_CX>;
1813 operating-poi 1811 operating-points-v2 = <&qup_opp_table>;
1814 interconnects 1812 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1815 1813 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1816 interconnect- 1814 interconnect-names = "qup-core", "qup-config";
1817 status = "dis 1815 status = "disabled";
1818 }; 1816 };
1819 1817
1820 i2c9: i2c@a84000 { 1818 i2c9: i2c@a84000 {
1821 compatible = 1819 compatible = "qcom,geni-i2c";
1822 reg = <0 0x00 1820 reg = <0 0x00a84000 0 0x4000>;
1823 clock-names = 1821 clock-names = "se";
1824 clocks = <&gc 1822 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1825 pinctrl-names 1823 pinctrl-names = "default";
1826 pinctrl-0 = < 1824 pinctrl-0 = <&qup_i2c9_default>;
1827 interrupts = 1825 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1828 #address-cell 1826 #address-cells = <1>;
1829 #size-cells = 1827 #size-cells = <0>;
1830 power-domains 1828 power-domains = <&rpmhpd SDM845_CX>;
1831 operating-poi 1829 operating-points-v2 = <&qup_opp_table>;
1832 interconnects 1830 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1833 1831 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1834 1832 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1835 interconnect- 1833 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dmas = <&gpi_ 1834 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1837 <&gpi_ 1835 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1838 dma-names = " 1836 dma-names = "tx", "rx";
1839 status = "dis 1837 status = "disabled";
1840 }; 1838 };
1841 1839
1842 spi9: spi@a84000 { 1840 spi9: spi@a84000 {
1843 compatible = 1841 compatible = "qcom,geni-spi";
1844 reg = <0 0x00 1842 reg = <0 0x00a84000 0 0x4000>;
1845 clock-names = 1843 clock-names = "se";
1846 clocks = <&gc 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1847 pinctrl-names 1845 pinctrl-names = "default";
1848 pinctrl-0 = < 1846 pinctrl-0 = <&qup_spi9_default>;
1849 interrupts = 1847 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1850 #address-cell 1848 #address-cells = <1>;
1851 #size-cells = 1849 #size-cells = <0>;
1852 interconnects 1850 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1853 1851 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1854 interconnect- 1852 interconnect-names = "qup-core", "qup-config";
1855 dmas = <&gpi_ 1853 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1856 <&gpi_ 1854 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1857 dma-names = " 1855 dma-names = "tx", "rx";
1858 status = "dis 1856 status = "disabled";
1859 }; 1857 };
1860 1858
1861 uart9: serial@a84000 1859 uart9: serial@a84000 {
1862 compatible = 1860 compatible = "qcom,geni-debug-uart";
1863 reg = <0 0x00 1861 reg = <0 0x00a84000 0 0x4000>;
1864 clock-names = 1862 clock-names = "se";
1865 clocks = <&gc 1863 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1866 pinctrl-names 1864 pinctrl-names = "default";
1867 pinctrl-0 = < 1865 pinctrl-0 = <&qup_uart9_default>;
1868 interrupts = 1866 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1869 power-domains 1867 power-domains = <&rpmhpd SDM845_CX>;
1870 operating-poi 1868 operating-points-v2 = <&qup_opp_table>;
1871 interconnects 1869 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1872 1870 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1873 interconnect- 1871 interconnect-names = "qup-core", "qup-config";
1874 status = "dis 1872 status = "disabled";
1875 }; 1873 };
1876 1874
1877 i2c10: i2c@a88000 { 1875 i2c10: i2c@a88000 {
1878 compatible = 1876 compatible = "qcom,geni-i2c";
1879 reg = <0 0x00 1877 reg = <0 0x00a88000 0 0x4000>;
1880 clock-names = 1878 clock-names = "se";
1881 clocks = <&gc 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1882 pinctrl-names 1880 pinctrl-names = "default";
1883 pinctrl-0 = < 1881 pinctrl-0 = <&qup_i2c10_default>;
1884 interrupts = 1882 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1885 #address-cell 1883 #address-cells = <1>;
1886 #size-cells = 1884 #size-cells = <0>;
1887 power-domains 1885 power-domains = <&rpmhpd SDM845_CX>;
1888 operating-poi 1886 operating-points-v2 = <&qup_opp_table>;
1889 interconnects 1887 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1890 1888 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1891 1889 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1892 interconnect- 1890 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dmas = <&gpi_ 1891 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1894 <&gpi_ 1892 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1895 dma-names = " 1893 dma-names = "tx", "rx";
1896 status = "dis 1894 status = "disabled";
1897 }; 1895 };
1898 1896
1899 spi10: spi@a88000 { 1897 spi10: spi@a88000 {
1900 compatible = 1898 compatible = "qcom,geni-spi";
1901 reg = <0 0x00 1899 reg = <0 0x00a88000 0 0x4000>;
1902 clock-names = 1900 clock-names = "se";
1903 clocks = <&gc 1901 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1904 pinctrl-names 1902 pinctrl-names = "default";
1905 pinctrl-0 = < 1903 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1904 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 #address-cell 1905 #address-cells = <1>;
1908 #size-cells = 1906 #size-cells = <0>;
1909 interconnects 1907 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1910 1908 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1911 interconnect- 1909 interconnect-names = "qup-core", "qup-config";
1912 dmas = <&gpi_ 1910 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1913 <&gpi_ 1911 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1914 dma-names = " 1912 dma-names = "tx", "rx";
1915 status = "dis 1913 status = "disabled";
1916 }; 1914 };
1917 1915
1918 uart10: serial@a88000 1916 uart10: serial@a88000 {
1919 compatible = 1917 compatible = "qcom,geni-uart";
1920 reg = <0 0x00 1918 reg = <0 0x00a88000 0 0x4000>;
1921 clock-names = 1919 clock-names = "se";
1922 clocks = <&gc 1920 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1923 pinctrl-names 1921 pinctrl-names = "default";
1924 pinctrl-0 = < 1922 pinctrl-0 = <&qup_uart10_default>;
1925 interrupts = 1923 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1926 power-domains 1924 power-domains = <&rpmhpd SDM845_CX>;
1927 operating-poi 1925 operating-points-v2 = <&qup_opp_table>;
1928 interconnects 1926 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1929 1927 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1930 interconnect- 1928 interconnect-names = "qup-core", "qup-config";
1931 status = "dis 1929 status = "disabled";
1932 }; 1930 };
1933 1931
1934 i2c11: i2c@a8c000 { 1932 i2c11: i2c@a8c000 {
1935 compatible = 1933 compatible = "qcom,geni-i2c";
1936 reg = <0 0x00 1934 reg = <0 0x00a8c000 0 0x4000>;
1937 clock-names = 1935 clock-names = "se";
1938 clocks = <&gc 1936 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1939 pinctrl-names 1937 pinctrl-names = "default";
1940 pinctrl-0 = < 1938 pinctrl-0 = <&qup_i2c11_default>;
1941 interrupts = 1939 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1942 #address-cell 1940 #address-cells = <1>;
1943 #size-cells = 1941 #size-cells = <0>;
1944 power-domains 1942 power-domains = <&rpmhpd SDM845_CX>;
1945 operating-poi 1943 operating-points-v2 = <&qup_opp_table>;
1946 interconnects 1944 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1947 1945 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1948 1946 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1949 interconnect- 1947 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dmas = <&gpi_ 1948 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1951 <&gpi_ 1949 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1952 dma-names = " 1950 dma-names = "tx", "rx";
1953 status = "dis 1951 status = "disabled";
1954 }; 1952 };
1955 1953
1956 spi11: spi@a8c000 { 1954 spi11: spi@a8c000 {
1957 compatible = 1955 compatible = "qcom,geni-spi";
1958 reg = <0 0x00 1956 reg = <0 0x00a8c000 0 0x4000>;
1959 clock-names = 1957 clock-names = "se";
1960 clocks = <&gc 1958 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1961 pinctrl-names 1959 pinctrl-names = "default";
1962 pinctrl-0 = < 1960 pinctrl-0 = <&qup_spi11_default>;
1963 interrupts = 1961 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1964 #address-cell 1962 #address-cells = <1>;
1965 #size-cells = 1963 #size-cells = <0>;
1966 interconnects 1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1967 1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1968 interconnect- 1966 interconnect-names = "qup-core", "qup-config";
1969 dmas = <&gpi_ 1967 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1970 <&gpi_ 1968 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1971 dma-names = " 1969 dma-names = "tx", "rx";
1972 status = "dis 1970 status = "disabled";
1973 }; 1971 };
1974 1972
1975 uart11: serial@a8c000 1973 uart11: serial@a8c000 {
1976 compatible = 1974 compatible = "qcom,geni-uart";
1977 reg = <0 0x00 1975 reg = <0 0x00a8c000 0 0x4000>;
1978 clock-names = 1976 clock-names = "se";
1979 clocks = <&gc 1977 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1980 pinctrl-names 1978 pinctrl-names = "default";
1981 pinctrl-0 = < 1979 pinctrl-0 = <&qup_uart11_default>;
1982 interrupts = 1980 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1983 power-domains 1981 power-domains = <&rpmhpd SDM845_CX>;
1984 operating-poi 1982 operating-points-v2 = <&qup_opp_table>;
1985 interconnects 1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1986 1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1987 interconnect- 1985 interconnect-names = "qup-core", "qup-config";
1988 status = "dis 1986 status = "disabled";
1989 }; 1987 };
1990 1988
1991 i2c12: i2c@a90000 { 1989 i2c12: i2c@a90000 {
1992 compatible = 1990 compatible = "qcom,geni-i2c";
1993 reg = <0 0x00 1991 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1992 clock-names = "se";
1995 clocks = <&gc 1993 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 pinctrl-names 1994 pinctrl-names = "default";
1997 pinctrl-0 = < 1995 pinctrl-0 = <&qup_i2c12_default>;
1998 interrupts = 1996 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1999 #address-cell 1997 #address-cells = <1>;
2000 #size-cells = 1998 #size-cells = <0>;
2001 power-domains 1999 power-domains = <&rpmhpd SDM845_CX>;
2002 operating-poi 2000 operating-points-v2 = <&qup_opp_table>;
2003 interconnects 2001 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2004 2002 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2005 2003 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2006 interconnect- 2004 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dmas = <&gpi_ 2005 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2008 <&gpi_ 2006 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
2009 dma-names = " 2007 dma-names = "tx", "rx";
2010 status = "dis 2008 status = "disabled";
2011 }; 2009 };
2012 2010
2013 spi12: spi@a90000 { 2011 spi12: spi@a90000 {
2014 compatible = 2012 compatible = "qcom,geni-spi";
2015 reg = <0 0x00 2013 reg = <0 0x00a90000 0 0x4000>;
2016 clock-names = 2014 clock-names = "se";
2017 clocks = <&gc 2015 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 2016 pinctrl-names = "default";
2019 pinctrl-0 = < 2017 pinctrl-0 = <&qup_spi12_default>;
2020 interrupts = 2018 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 #address-cell 2019 #address-cells = <1>;
2022 #size-cells = 2020 #size-cells = <0>;
2023 interconnects 2021 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2024 2022 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2025 interconnect- 2023 interconnect-names = "qup-core", "qup-config";
2026 dmas = <&gpi_ 2024 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2027 <&gpi_ 2025 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
2028 dma-names = " 2026 dma-names = "tx", "rx";
2029 status = "dis 2027 status = "disabled";
2030 }; 2028 };
2031 2029
2032 uart12: serial@a90000 2030 uart12: serial@a90000 {
2033 compatible = 2031 compatible = "qcom,geni-uart";
2034 reg = <0 0x00 2032 reg = <0 0x00a90000 0 0x4000>;
2035 clock-names = 2033 clock-names = "se";
2036 clocks = <&gc 2034 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2037 pinctrl-names 2035 pinctrl-names = "default";
2038 pinctrl-0 = < 2036 pinctrl-0 = <&qup_uart12_default>;
2039 interrupts = 2037 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2040 power-domains 2038 power-domains = <&rpmhpd SDM845_CX>;
2041 operating-poi 2039 operating-points-v2 = <&qup_opp_table>;
2042 interconnects 2040 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2043 2041 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2044 interconnect- 2042 interconnect-names = "qup-core", "qup-config";
2045 status = "dis 2043 status = "disabled";
2046 }; 2044 };
2047 2045
2048 i2c13: i2c@a94000 { 2046 i2c13: i2c@a94000 {
2049 compatible = 2047 compatible = "qcom,geni-i2c";
2050 reg = <0 0x00 2048 reg = <0 0x00a94000 0 0x4000>;
2051 clock-names = 2049 clock-names = "se";
2052 clocks = <&gc 2050 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2053 pinctrl-names 2051 pinctrl-names = "default";
2054 pinctrl-0 = < 2052 pinctrl-0 = <&qup_i2c13_default>;
2055 interrupts = 2053 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2056 #address-cell 2054 #address-cells = <1>;
2057 #size-cells = 2055 #size-cells = <0>;
2058 power-domains 2056 power-domains = <&rpmhpd SDM845_CX>;
2059 operating-poi 2057 operating-points-v2 = <&qup_opp_table>;
2060 interconnects 2058 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2061 2059 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2062 2060 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2063 interconnect- 2061 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dmas = <&gpi_ 2062 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2065 <&gpi_ 2063 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2066 dma-names = " 2064 dma-names = "tx", "rx";
2067 status = "dis 2065 status = "disabled";
2068 }; 2066 };
2069 2067
2070 spi13: spi@a94000 { 2068 spi13: spi@a94000 {
2071 compatible = 2069 compatible = "qcom,geni-spi";
2072 reg = <0 0x00 2070 reg = <0 0x00a94000 0 0x4000>;
2073 clock-names = 2071 clock-names = "se";
2074 clocks = <&gc 2072 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2075 pinctrl-names 2073 pinctrl-names = "default";
2076 pinctrl-0 = < 2074 pinctrl-0 = <&qup_spi13_default>;
2077 interrupts = 2075 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2078 #address-cell 2076 #address-cells = <1>;
2079 #size-cells = 2077 #size-cells = <0>;
2080 interconnects 2078 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2081 2079 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2082 interconnect- 2080 interconnect-names = "qup-core", "qup-config";
2083 dmas = <&gpi_ 2081 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2084 <&gpi_ 2082 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2085 dma-names = " 2083 dma-names = "tx", "rx";
2086 status = "dis 2084 status = "disabled";
2087 }; 2085 };
2088 2086
2089 uart13: serial@a94000 2087 uart13: serial@a94000 {
2090 compatible = 2088 compatible = "qcom,geni-uart";
2091 reg = <0 0x00 2089 reg = <0 0x00a94000 0 0x4000>;
2092 clock-names = 2090 clock-names = "se";
2093 clocks = <&gc 2091 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2094 pinctrl-names 2092 pinctrl-names = "default";
2095 pinctrl-0 = < 2093 pinctrl-0 = <&qup_uart13_default>;
2096 interrupts = 2094 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2097 power-domains 2095 power-domains = <&rpmhpd SDM845_CX>;
2098 operating-poi 2096 operating-points-v2 = <&qup_opp_table>;
2099 interconnects 2097 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2100 2098 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2101 interconnect- 2099 interconnect-names = "qup-core", "qup-config";
2102 status = "dis 2100 status = "disabled";
2103 }; 2101 };
2104 2102
2105 i2c14: i2c@a98000 { 2103 i2c14: i2c@a98000 {
2106 compatible = 2104 compatible = "qcom,geni-i2c";
2107 reg = <0 0x00 2105 reg = <0 0x00a98000 0 0x4000>;
2108 clock-names = 2106 clock-names = "se";
2109 clocks = <&gc 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2110 pinctrl-names 2108 pinctrl-names = "default";
2111 pinctrl-0 = < 2109 pinctrl-0 = <&qup_i2c14_default>;
2112 interrupts = 2110 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2113 #address-cell 2111 #address-cells = <1>;
2114 #size-cells = 2112 #size-cells = <0>;
2115 power-domains 2113 power-domains = <&rpmhpd SDM845_CX>;
2116 operating-poi 2114 operating-points-v2 = <&qup_opp_table>;
2117 interconnects 2115 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2118 2116 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2119 2117 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2120 interconnect- 2118 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dmas = <&gpi_ 2119 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2122 <&gpi_ 2120 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2123 dma-names = " 2121 dma-names = "tx", "rx";
2124 status = "dis 2122 status = "disabled";
2125 }; 2123 };
2126 2124
2127 spi14: spi@a98000 { 2125 spi14: spi@a98000 {
2128 compatible = 2126 compatible = "qcom,geni-spi";
2129 reg = <0 0x00 2127 reg = <0 0x00a98000 0 0x4000>;
2130 clock-names = 2128 clock-names = "se";
2131 clocks = <&gc 2129 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2132 pinctrl-names 2130 pinctrl-names = "default";
2133 pinctrl-0 = < 2131 pinctrl-0 = <&qup_spi14_default>;
2134 interrupts = 2132 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2135 #address-cell 2133 #address-cells = <1>;
2136 #size-cells = 2134 #size-cells = <0>;
2137 interconnects 2135 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2138 2136 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2139 interconnect- 2137 interconnect-names = "qup-core", "qup-config";
2140 dmas = <&gpi_ 2138 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2141 <&gpi_ 2139 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2142 dma-names = " 2140 dma-names = "tx", "rx";
2143 status = "dis 2141 status = "disabled";
2144 }; 2142 };
2145 2143
2146 uart14: serial@a98000 2144 uart14: serial@a98000 {
2147 compatible = 2145 compatible = "qcom,geni-uart";
2148 reg = <0 0x00 2146 reg = <0 0x00a98000 0 0x4000>;
2149 clock-names = 2147 clock-names = "se";
2150 clocks = <&gc 2148 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2151 pinctrl-names 2149 pinctrl-names = "default";
2152 pinctrl-0 = < 2150 pinctrl-0 = <&qup_uart14_default>;
2153 interrupts = 2151 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
2154 power-domains 2152 power-domains = <&rpmhpd SDM845_CX>;
2155 operating-poi 2153 operating-points-v2 = <&qup_opp_table>;
2156 interconnects 2154 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2157 2155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2158 interconnect- 2156 interconnect-names = "qup-core", "qup-config";
2159 status = "dis 2157 status = "disabled";
2160 }; 2158 };
2161 2159
2162 i2c15: i2c@a9c000 { 2160 i2c15: i2c@a9c000 {
2163 compatible = 2161 compatible = "qcom,geni-i2c";
2164 reg = <0 0x00 2162 reg = <0 0x00a9c000 0 0x4000>;
2165 clock-names = 2163 clock-names = "se";
2166 clocks = <&gc 2164 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2167 pinctrl-names 2165 pinctrl-names = "default";
2168 pinctrl-0 = < 2166 pinctrl-0 = <&qup_i2c15_default>;
2169 interrupts = 2167 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2170 #address-cell 2168 #address-cells = <1>;
2171 #size-cells = 2169 #size-cells = <0>;
2172 power-domains 2170 power-domains = <&rpmhpd SDM845_CX>;
2173 operating-poi 2171 operating-points-v2 = <&qup_opp_table>;
2174 status = "dis 2172 status = "disabled";
2175 interconnects 2173 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2176 2174 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2177 2175 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2178 interconnect- 2176 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dmas = <&gpi_ 2177 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2180 <&gpi_ 2178 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2181 dma-names = " 2179 dma-names = "tx", "rx";
2182 }; 2180 };
2183 2181
2184 spi15: spi@a9c000 { 2182 spi15: spi@a9c000 {
2185 compatible = 2183 compatible = "qcom,geni-spi";
2186 reg = <0 0x00 2184 reg = <0 0x00a9c000 0 0x4000>;
2187 clock-names = 2185 clock-names = "se";
2188 clocks = <&gc 2186 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2189 pinctrl-names 2187 pinctrl-names = "default";
2190 pinctrl-0 = < 2188 pinctrl-0 = <&qup_spi15_default>;
2191 interrupts = 2189 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2192 #address-cell 2190 #address-cells = <1>;
2193 #size-cells = 2191 #size-cells = <0>;
2194 interconnects 2192 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2195 2193 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2196 interconnect- 2194 interconnect-names = "qup-core", "qup-config";
2197 dmas = <&gpi_ 2195 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2198 <&gpi_ 2196 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2199 dma-names = " 2197 dma-names = "tx", "rx";
2200 status = "dis 2198 status = "disabled";
2201 }; 2199 };
2202 2200
2203 uart15: serial@a9c000 2201 uart15: serial@a9c000 {
2204 compatible = 2202 compatible = "qcom,geni-uart";
2205 reg = <0 0x00 2203 reg = <0 0x00a9c000 0 0x4000>;
2206 clock-names = 2204 clock-names = "se";
2207 clocks = <&gc 2205 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2208 pinctrl-names 2206 pinctrl-names = "default";
2209 pinctrl-0 = < 2207 pinctrl-0 = <&qup_uart15_default>;
2210 interrupts = 2208 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2211 power-domains 2209 power-domains = <&rpmhpd SDM845_CX>;
2212 operating-poi 2210 operating-points-v2 = <&qup_opp_table>;
2213 interconnects 2211 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2214 2212 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2215 interconnect- 2213 interconnect-names = "qup-core", "qup-config";
2216 status = "dis 2214 status = "disabled";
2217 }; 2215 };
2218 }; 2216 };
2219 2217
2220 llcc: system-cache-controller 2218 llcc: system-cache-controller@1100000 {
2221 compatible = "qcom,sd 2219 compatible = "qcom,sdm845-llcc";
2222 reg = <0 0x01100000 0 2220 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2223 <0 0x01200000 0 2221 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2224 <0 0x01300000 0 2222 <0 0x01300000 0 0x50000>;
2225 reg-names = "llcc0_ba 2223 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2226 "llcc3_ba 2224 "llcc3_base", "llcc_broadcast_base";
2227 interrupts = <GIC_SPI 2225 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2228 }; 2226 };
2229 2227
2230 dma@10a2000 { 2228 dma@10a2000 {
2231 compatible = "qcom,sd 2229 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2232 reg = <0x0 0x010a2000 2230 reg = <0x0 0x010a2000 0x0 0x1000>,
2233 <0x0 0x010ae000 2231 <0x0 0x010ae000 0x0 0x2000>;
2234 }; 2232 };
2235 2233
2236 pmu@114a000 { 2234 pmu@114a000 {
2237 compatible = "qcom,sd 2235 compatible = "qcom,sdm845-llcc-bwmon";
2238 reg = <0 0x0114a000 0 2236 reg = <0 0x0114a000 0 0x1000>;
2239 interrupts = <GIC_SPI 2237 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
2240 interconnects = <&mem 2238 interconnects = <&mem_noc MASTER_LLCC 3 &mem_noc SLAVE_EBI1 3>;
2241 2239
2242 operating-points-v2 = 2240 operating-points-v2 = <&llcc_bwmon_opp_table>;
2243 2241
2244 llcc_bwmon_opp_table: 2242 llcc_bwmon_opp_table: opp-table {
2245 compatible = 2243 compatible = "operating-points-v2";
2246 2244
2247 /* 2245 /*
2248 * The interc 2246 * The interconnect path bandwidth taken from
2249 * cpu4_opp_t 2247 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2250 * interconne 2248 * interconnect. This also matches the
2251 * bandwidth 2249 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2252 * bus width: 2250 * bus width: 4 bytes) from msm-4.9 downstream
2253 * kernel. 2251 * kernel.
2254 */ 2252 */
2255 opp-0 { 2253 opp-0 {
2256 opp-p 2254 opp-peak-kBps = <800000>;
2257 }; 2255 };
2258 opp-1 { 2256 opp-1 {
2259 opp-p 2257 opp-peak-kBps = <1804000>;
2260 }; 2258 };
2261 opp-2 { 2259 opp-2 {
2262 opp-p 2260 opp-peak-kBps = <3072000>;
2263 }; 2261 };
2264 opp-3 { 2262 opp-3 {
2265 opp-p 2263 opp-peak-kBps = <5412000>;
2266 }; 2264 };
2267 opp-4 { 2265 opp-4 {
2268 opp-p 2266 opp-peak-kBps = <7216000>;
2269 }; 2267 };
2270 }; 2268 };
2271 }; 2269 };
2272 2270
2273 pmu@1436400 { 2271 pmu@1436400 {
2274 compatible = "qcom,sd 2272 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2275 reg = <0 0x01436400 0 2273 reg = <0 0x01436400 0 0x600>;
2276 interrupts = <GIC_SPI 2274 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
2277 interconnects = <&gla 2275 interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
2278 2276
2279 operating-points-v2 = 2277 operating-points-v2 = <&cpu_bwmon_opp_table>;
2280 2278
2281 cpu_bwmon_opp_table: 2279 cpu_bwmon_opp_table: opp-table {
2282 compatible = 2280 compatible = "operating-points-v2";
2283 2281
2284 /* 2282 /*
2285 * The interc 2283 * The interconnect path bandwidth taken from
2286 * cpu4_opp_t 2284 * cpu4_opp_table bandwidth for OSM L3
2287 * interconne 2285 * interconnect. This also matches the OSM L3
2288 * from bandw 2286 * from bandwidth table of qcom,cpu4-l3lat-mon
2289 * (qcom,core 2287 * (qcom,core-dev-table, bus width: 16 bytes)
2290 * from msm-4 2288 * from msm-4.9 downstream kernel.
2291 */ 2289 */
2292 opp-0 { 2290 opp-0 {
2293 opp-p 2291 opp-peak-kBps = <4800000>;
2294 }; 2292 };
2295 opp-1 { 2293 opp-1 {
2296 opp-p 2294 opp-peak-kBps = <9216000>;
2297 }; 2295 };
2298 opp-2 { 2296 opp-2 {
2299 opp-p 2297 opp-peak-kBps = <15052800>;
2300 }; 2298 };
2301 opp-3 { 2299 opp-3 {
2302 opp-p 2300 opp-peak-kBps = <20889600>;
2303 }; 2301 };
2304 opp-4 { 2302 opp-4 {
2305 opp-p 2303 opp-peak-kBps = <25497600>;
2306 }; 2304 };
2307 }; 2305 };
2308 }; 2306 };
2309 2307
2310 pcie0: pcie@1c00000 { !! 2308 pcie0: pci@1c00000 {
2311 compatible = "qcom,pc 2309 compatible = "qcom,pcie-sdm845";
2312 reg = <0 0x01c00000 0 2310 reg = <0 0x01c00000 0 0x2000>,
2313 <0 0x60000000 0 2311 <0 0x60000000 0 0xf1d>,
2314 <0 0x60000f20 0 2312 <0 0x60000f20 0 0xa8>,
2315 <0 0x60100000 0 2313 <0 0x60100000 0 0x100000>,
2316 <0 0x01c07000 0 2314 <0 0x01c07000 0 0x1000>;
2317 reg-names = "parf", " 2315 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2318 device_type = "pci"; 2316 device_type = "pci";
2319 linux,pci-domain = <0 2317 linux,pci-domain = <0>;
2320 bus-range = <0x00 0xf 2318 bus-range = <0x00 0xff>;
2321 num-lanes = <1>; 2319 num-lanes = <1>;
2322 2320
2323 #address-cells = <3>; 2321 #address-cells = <3>;
2324 #size-cells = <2>; 2322 #size-cells = <2>;
2325 2323
2326 ranges = <0x01000000 2324 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2327 <0x02000000 2325 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2328 2326
2329 interrupts = <GIC_SPI 2327 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2330 interrupt-names = "ms 2328 interrupt-names = "msi";
2331 #interrupt-cells = <1 2329 #interrupt-cells = <1>;
2332 interrupt-map-mask = 2330 interrupt-map-mask = <0 0 0 0x7>;
2333 interrupt-map = <0 0 2331 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2334 <0 0 2332 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2335 <0 0 2333 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2336 <0 0 2334 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2337 2335
2338 clocks = <&gcc GCC_PC 2336 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2339 <&gcc GCC_PC 2337 <&gcc GCC_PCIE_0_AUX_CLK>,
2340 <&gcc GCC_PC 2338 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2341 <&gcc GCC_PC 2339 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2342 <&gcc GCC_PC 2340 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2343 <&gcc GCC_PC 2341 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2344 <&gcc GCC_AG 2342 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2345 clock-names = "pipe", 2343 clock-names = "pipe",
2346 "aux", 2344 "aux",
2347 "cfg", 2345 "cfg",
2348 "bus_ma 2346 "bus_master",
2349 "bus_sl 2347 "bus_slave",
2350 "slave_ 2348 "slave_q2a",
2351 "tbu"; 2349 "tbu";
2352 2350
2353 iommu-map = <0x0 &a 2351 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2354 <0x100 &a 2352 <0x100 &apps_smmu 0x1c11 0x1>,
2355 <0x200 &a 2353 <0x200 &apps_smmu 0x1c12 0x1>,
2356 <0x300 &a 2354 <0x300 &apps_smmu 0x1c13 0x1>,
2357 <0x400 &a 2355 <0x400 &apps_smmu 0x1c14 0x1>,
2358 <0x500 &a 2356 <0x500 &apps_smmu 0x1c15 0x1>,
2359 <0x600 &a 2357 <0x600 &apps_smmu 0x1c16 0x1>,
2360 <0x700 &a 2358 <0x700 &apps_smmu 0x1c17 0x1>,
2361 <0x800 &a 2359 <0x800 &apps_smmu 0x1c18 0x1>,
2362 <0x900 &a 2360 <0x900 &apps_smmu 0x1c19 0x1>,
2363 <0xa00 &a 2361 <0xa00 &apps_smmu 0x1c1a 0x1>,
2364 <0xb00 &a 2362 <0xb00 &apps_smmu 0x1c1b 0x1>,
2365 <0xc00 &a 2363 <0xc00 &apps_smmu 0x1c1c 0x1>,
2366 <0xd00 &a 2364 <0xd00 &apps_smmu 0x1c1d 0x1>,
2367 <0xe00 &a 2365 <0xe00 &apps_smmu 0x1c1e 0x1>,
2368 <0xf00 &a 2366 <0xf00 &apps_smmu 0x1c1f 0x1>;
2369 2367
2370 resets = <&gcc GCC_PC 2368 resets = <&gcc GCC_PCIE_0_BCR>;
2371 reset-names = "pci"; 2369 reset-names = "pci";
2372 2370
2373 power-domains = <&gcc 2371 power-domains = <&gcc PCIE_0_GDSC>;
2374 2372
2375 phys = <&pcie0_phy>; !! 2373 phys = <&pcie0_lane>;
2376 phy-names = "pciephy" 2374 phy-names = "pciephy";
2377 2375
2378 status = "disabled"; 2376 status = "disabled";
2379 <<
2380 pcie@0 { <<
2381 device_type = <<
2382 reg = <0x0 0x <<
2383 bus-range = < <<
2384 <<
2385 #address-cell <<
2386 #size-cells = <<
2387 ranges; <<
2388 }; <<
2389 }; 2377 };
2390 2378
2391 pcie0_phy: phy@1c06000 { 2379 pcie0_phy: phy@1c06000 {
2392 compatible = "qcom,sd 2380 compatible = "qcom,sdm845-qmp-pcie-phy";
2393 reg = <0 0x01c06000 0 !! 2381 reg = <0 0x01c06000 0 0x18c>;
>> 2382 #address-cells = <2>;
>> 2383 #size-cells = <2>;
>> 2384 ranges;
2394 clocks = <&gcc GCC_PC 2385 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2395 <&gcc GCC_PC 2386 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2396 <&gcc GCC_PC 2387 <&gcc GCC_PCIE_0_CLKREF_CLK>,
2397 <&gcc GCC_PC !! 2388 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2398 <&gcc GCC_PC !! 2389 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2399 clock-names = "aux", <<
2400 "cfg_ah <<
2401 "ref", <<
2402 "refgen <<
2403 "pipe"; <<
2404 <<
2405 clock-output-names = <<
2406 #clock-cells = <0>; <<
2407 <<
2408 #phy-cells = <0>; <<
2409 2390
2410 resets = <&gcc GCC_PC 2391 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2411 reset-names = "phy"; 2392 reset-names = "phy";
2412 2393
2413 assigned-clocks = <&g 2394 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2414 assigned-clock-rates 2395 assigned-clock-rates = <100000000>;
2415 2396
2416 status = "disabled"; 2397 status = "disabled";
>> 2398
>> 2399 pcie0_lane: phy@1c06200 {
>> 2400 reg = <0 0x01c06200 0 0x128>,
>> 2401 <0 0x01c06400 0 0x1fc>,
>> 2402 <0 0x01c06800 0 0x218>,
>> 2403 <0 0x01c06600 0 0x70>;
>> 2404 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 2405 clock-names = "pipe0";
>> 2406
>> 2407 #clock-cells = <0>;
>> 2408 #phy-cells = <0>;
>> 2409 clock-output-names = "pcie_0_pipe_clk";
>> 2410 };
2417 }; 2411 };
2418 2412
2419 pcie1: pcie@1c08000 { !! 2413 pcie1: pci@1c08000 {
2420 compatible = "qcom,pc 2414 compatible = "qcom,pcie-sdm845";
2421 reg = <0 0x01c08000 0 2415 reg = <0 0x01c08000 0 0x2000>,
2422 <0 0x40000000 0 2416 <0 0x40000000 0 0xf1d>,
2423 <0 0x40000f20 0 2417 <0 0x40000f20 0 0xa8>,
2424 <0 0x40100000 0 2418 <0 0x40100000 0 0x100000>,
2425 <0 0x01c0c000 0 2419 <0 0x01c0c000 0 0x1000>;
2426 reg-names = "parf", " 2420 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2427 device_type = "pci"; 2421 device_type = "pci";
2428 linux,pci-domain = <1 2422 linux,pci-domain = <1>;
2429 bus-range = <0x00 0xf 2423 bus-range = <0x00 0xff>;
2430 num-lanes = <1>; 2424 num-lanes = <1>;
2431 2425
2432 #address-cells = <3>; 2426 #address-cells = <3>;
2433 #size-cells = <2>; 2427 #size-cells = <2>;
2434 2428
2435 ranges = <0x01000000 2429 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2436 <0x02000000 2430 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2437 2431
2438 interrupts = <GIC_SPI 2432 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
2439 interrupt-names = "ms 2433 interrupt-names = "msi";
2440 #interrupt-cells = <1 2434 #interrupt-cells = <1>;
2441 interrupt-map-mask = 2435 interrupt-map-mask = <0 0 0 0x7>;
2442 interrupt-map = <0 0 2436 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2443 <0 0 2437 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2444 <0 0 2438 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2445 <0 0 2439 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2446 2440
2447 clocks = <&gcc GCC_PC 2441 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2448 <&gcc GCC_PC 2442 <&gcc GCC_PCIE_1_AUX_CLK>,
2449 <&gcc GCC_PC 2443 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2450 <&gcc GCC_PC 2444 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2451 <&gcc GCC_PC 2445 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2452 <&gcc GCC_PC 2446 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2453 <&gcc GCC_PC 2447 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2454 <&gcc GCC_AG 2448 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2455 clock-names = "pipe", 2449 clock-names = "pipe",
2456 "aux", 2450 "aux",
2457 "cfg", 2451 "cfg",
2458 "bus_ma 2452 "bus_master",
2459 "bus_sl 2453 "bus_slave",
2460 "slave_ 2454 "slave_q2a",
2461 "ref", 2455 "ref",
2462 "tbu"; 2456 "tbu";
2463 2457
2464 assigned-clocks = <&g 2458 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2465 assigned-clock-rates 2459 assigned-clock-rates = <19200000>;
2466 2460
2467 iommu-map = <0x0 &a 2461 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2468 <0x100 &a 2462 <0x100 &apps_smmu 0x1c01 0x1>,
2469 <0x200 &a 2463 <0x200 &apps_smmu 0x1c02 0x1>,
2470 <0x300 &a 2464 <0x300 &apps_smmu 0x1c03 0x1>,
2471 <0x400 &a 2465 <0x400 &apps_smmu 0x1c04 0x1>,
2472 <0x500 &a 2466 <0x500 &apps_smmu 0x1c05 0x1>,
2473 <0x600 &a 2467 <0x600 &apps_smmu 0x1c06 0x1>,
2474 <0x700 &a 2468 <0x700 &apps_smmu 0x1c07 0x1>,
2475 <0x800 &a 2469 <0x800 &apps_smmu 0x1c08 0x1>,
2476 <0x900 &a 2470 <0x900 &apps_smmu 0x1c09 0x1>,
2477 <0xa00 &a 2471 <0xa00 &apps_smmu 0x1c0a 0x1>,
2478 <0xb00 &a 2472 <0xb00 &apps_smmu 0x1c0b 0x1>,
2479 <0xc00 &a 2473 <0xc00 &apps_smmu 0x1c0c 0x1>,
2480 <0xd00 &a 2474 <0xd00 &apps_smmu 0x1c0d 0x1>,
2481 <0xe00 &a 2475 <0xe00 &apps_smmu 0x1c0e 0x1>,
2482 <0xf00 &a 2476 <0xf00 &apps_smmu 0x1c0f 0x1>;
2483 2477
2484 resets = <&gcc GCC_PC 2478 resets = <&gcc GCC_PCIE_1_BCR>;
2485 reset-names = "pci"; 2479 reset-names = "pci";
2486 2480
2487 power-domains = <&gcc 2481 power-domains = <&gcc PCIE_1_GDSC>;
2488 2482
2489 phys = <&pcie1_phy>; !! 2483 phys = <&pcie1_lane>;
2490 phy-names = "pciephy" 2484 phy-names = "pciephy";
2491 2485
2492 status = "disabled"; 2486 status = "disabled";
2493 <<
2494 pcie@0 { <<
2495 device_type = <<
2496 reg = <0x0 0x <<
2497 bus-range = < <<
2498 <<
2499 #address-cell <<
2500 #size-cells = <<
2501 ranges; <<
2502 }; <<
2503 }; 2487 };
2504 2488
2505 pcie1_phy: phy@1c0a000 { 2489 pcie1_phy: phy@1c0a000 {
2506 compatible = "qcom,sd 2490 compatible = "qcom,sdm845-qhp-pcie-phy";
2507 reg = <0 0x01c0a000 0 !! 2491 reg = <0 0x01c0a000 0 0x800>;
>> 2492 #address-cells = <2>;
>> 2493 #size-cells = <2>;
>> 2494 ranges;
2508 clocks = <&gcc GCC_PC 2495 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2509 <&gcc GCC_PC 2496 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2510 <&gcc GCC_PC 2497 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2511 <&gcc GCC_PC !! 2498 <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2512 <&gcc GCC_PC !! 2499 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2513 clock-names = "aux", <<
2514 "cfg_ah <<
2515 "ref", <<
2516 "refgen <<
2517 "pipe"; <<
2518 <<
2519 clock-output-names = <<
2520 #clock-cells = <0>; <<
2521 <<
2522 #phy-cells = <0>; <<
2523 2500
2524 resets = <&gcc GCC_PC 2501 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2525 reset-names = "phy"; 2502 reset-names = "phy";
2526 2503
2527 assigned-clocks = <&g 2504 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2528 assigned-clock-rates 2505 assigned-clock-rates = <100000000>;
2529 2506
2530 status = "disabled"; 2507 status = "disabled";
>> 2508
>> 2509 pcie1_lane: phy@1c06200 {
>> 2510 reg = <0 0x01c0a800 0 0x800>,
>> 2511 <0 0x01c0a800 0 0x800>,
>> 2512 <0 0x01c0b800 0 0x400>;
>> 2513 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2514 clock-names = "pipe0";
>> 2515
>> 2516 #clock-cells = <0>;
>> 2517 #phy-cells = <0>;
>> 2518 clock-output-names = "pcie_1_pipe_clk";
>> 2519 };
2531 }; 2520 };
2532 2521
2533 mem_noc: interconnect@1380000 2522 mem_noc: interconnect@1380000 {
2534 compatible = "qcom,sd 2523 compatible = "qcom,sdm845-mem-noc";
2535 reg = <0 0x01380000 0 2524 reg = <0 0x01380000 0 0x27200>;
2536 #interconnect-cells = 2525 #interconnect-cells = <2>;
2537 qcom,bcm-voters = <&a 2526 qcom,bcm-voters = <&apps_bcm_voter>;
2538 }; 2527 };
2539 2528
2540 dc_noc: interconnect@14e0000 2529 dc_noc: interconnect@14e0000 {
2541 compatible = "qcom,sd 2530 compatible = "qcom,sdm845-dc-noc";
2542 reg = <0 0x014e0000 0 2531 reg = <0 0x014e0000 0 0x400>;
2543 #interconnect-cells = 2532 #interconnect-cells = <2>;
2544 qcom,bcm-voters = <&a 2533 qcom,bcm-voters = <&apps_bcm_voter>;
2545 }; 2534 };
2546 2535
2547 config_noc: interconnect@1500 2536 config_noc: interconnect@1500000 {
2548 compatible = "qcom,sd 2537 compatible = "qcom,sdm845-config-noc";
2549 reg = <0 0x01500000 0 2538 reg = <0 0x01500000 0 0x5080>;
2550 #interconnect-cells = 2539 #interconnect-cells = <2>;
2551 qcom,bcm-voters = <&a 2540 qcom,bcm-voters = <&apps_bcm_voter>;
2552 }; 2541 };
2553 2542
2554 system_noc: interconnect@1620 2543 system_noc: interconnect@1620000 {
2555 compatible = "qcom,sd 2544 compatible = "qcom,sdm845-system-noc";
2556 reg = <0 0x01620000 0 2545 reg = <0 0x01620000 0 0x18080>;
2557 #interconnect-cells = 2546 #interconnect-cells = <2>;
2558 qcom,bcm-voters = <&a 2547 qcom,bcm-voters = <&apps_bcm_voter>;
2559 }; 2548 };
2560 2549
2561 aggre1_noc: interconnect@16e0 2550 aggre1_noc: interconnect@16e0000 {
2562 compatible = "qcom,sd 2551 compatible = "qcom,sdm845-aggre1-noc";
2563 reg = <0 0x016e0000 0 2552 reg = <0 0x016e0000 0 0x15080>;
2564 #interconnect-cells = 2553 #interconnect-cells = <2>;
2565 qcom,bcm-voters = <&a 2554 qcom,bcm-voters = <&apps_bcm_voter>;
2566 }; 2555 };
2567 2556
2568 aggre2_noc: interconnect@1700 2557 aggre2_noc: interconnect@1700000 {
2569 compatible = "qcom,sd 2558 compatible = "qcom,sdm845-aggre2-noc";
2570 reg = <0 0x01700000 0 2559 reg = <0 0x01700000 0 0x1f300>;
2571 #interconnect-cells = 2560 #interconnect-cells = <2>;
2572 qcom,bcm-voters = <&a 2561 qcom,bcm-voters = <&apps_bcm_voter>;
2573 }; 2562 };
2574 2563
2575 mmss_noc: interconnect@174000 2564 mmss_noc: interconnect@1740000 {
2576 compatible = "qcom,sd 2565 compatible = "qcom,sdm845-mmss-noc";
2577 reg = <0 0x01740000 0 2566 reg = <0 0x01740000 0 0x1c100>;
2578 #interconnect-cells = 2567 #interconnect-cells = <2>;
2579 qcom,bcm-voters = <&a 2568 qcom,bcm-voters = <&apps_bcm_voter>;
2580 }; 2569 };
2581 2570
2582 ufs_mem_hc: ufshc@1d84000 { 2571 ufs_mem_hc: ufshc@1d84000 {
2583 compatible = "qcom,sd 2572 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2584 "jedec,u 2573 "jedec,ufs-2.0";
2585 reg = <0 0x01d84000 0 2574 reg = <0 0x01d84000 0 0x2500>,
2586 <0 0x01d90000 0 2575 <0 0x01d90000 0 0x8000>;
2587 reg-names = "std", "i 2576 reg-names = "std", "ice";
2588 interrupts = <GIC_SPI 2577 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2589 phys = <&ufs_mem_phy> !! 2578 phys = <&ufs_mem_phy_lanes>;
2590 phy-names = "ufsphy"; 2579 phy-names = "ufsphy";
2591 lanes-per-direction = 2580 lanes-per-direction = <2>;
2592 power-domains = <&gcc 2581 power-domains = <&gcc UFS_PHY_GDSC>;
2593 #reset-cells = <1>; 2582 #reset-cells = <1>;
2594 resets = <&gcc GCC_UF 2583 resets = <&gcc GCC_UFS_PHY_BCR>;
2595 reset-names = "rst"; 2584 reset-names = "rst";
2596 2585
2597 iommus = <&apps_smmu 2586 iommus = <&apps_smmu 0x100 0xf>;
2598 2587
2599 clock-names = 2588 clock-names =
2600 "core_clk", 2589 "core_clk",
2601 "bus_aggr_clk 2590 "bus_aggr_clk",
2602 "iface_clk", 2591 "iface_clk",
2603 "core_clk_uni 2592 "core_clk_unipro",
2604 "ref_clk", 2593 "ref_clk",
2605 "tx_lane0_syn 2594 "tx_lane0_sync_clk",
2606 "rx_lane0_syn 2595 "rx_lane0_sync_clk",
2607 "rx_lane1_syn 2596 "rx_lane1_sync_clk",
2608 "ice_core_clk 2597 "ice_core_clk";
2609 clocks = 2598 clocks =
2610 <&gcc GCC_UFS 2599 <&gcc GCC_UFS_PHY_AXI_CLK>,
2611 <&gcc GCC_AGG 2600 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2612 <&gcc GCC_UFS 2601 <&gcc GCC_UFS_PHY_AHB_CLK>,
2613 <&gcc GCC_UFS 2602 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2614 <&rpmhcc RPMH 2603 <&rpmhcc RPMH_CXO_CLK>,
2615 <&gcc GCC_UFS 2604 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2616 <&gcc GCC_UFS 2605 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2617 <&gcc GCC_UFS 2606 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2618 <&gcc GCC_UFS 2607 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2619 !! 2608 freq-table-hz =
2620 operating-points-v2 = !! 2609 <50000000 200000000>,
2621 !! 2610 <0 0>,
2622 interconnects = <&agg !! 2611 <0 0>,
2623 <&gla !! 2612 <37500000 150000000>,
2624 interconnect-names = !! 2613 <0 0>,
>> 2614 <0 0>,
>> 2615 <0 0>,
>> 2616 <0 0>,
>> 2617 <75000000 300000000>;
2625 2618
2626 status = "disabled"; 2619 status = "disabled";
2627 <<
2628 ufs_opp_table: opp-ta <<
2629 compatible = <<
2630 <<
2631 opp-50000000 <<
2632 opp-h <<
2633 <<
2634 <<
2635 <<
2636 <<
2637 <<
2638 <<
2639 <<
2640 <<
2641 requi <<
2642 }; <<
2643 <<
2644 opp-200000000 <<
2645 opp-h <<
2646 <<
2647 <<
2648 <<
2649 <<
2650 <<
2651 <<
2652 <<
2653 <<
2654 requi <<
2655 }; <<
2656 }; <<
2657 }; 2620 };
2658 2621
2659 ufs_mem_phy: phy@1d87000 { 2622 ufs_mem_phy: phy@1d87000 {
2660 compatible = "qcom,sd 2623 compatible = "qcom,sdm845-qmp-ufs-phy";
2661 reg = <0 0x01d87000 0 !! 2624 reg = <0 0x01d87000 0 0x18c>;
2662 !! 2625 #address-cells = <2>;
2663 clocks = <&rpmhcc RPM !! 2626 #size-cells = <2>;
2664 <&gcc GCC_UF !! 2627 ranges;
2665 <&gcc GCC_UF <<
2666 clock-names = "ref", 2628 clock-names = "ref",
2667 "ref_au !! 2629 "ref_aux";
2668 "qref"; !! 2630 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2669 !! 2631 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2670 power-domains = <&gcc <<
2671 2632
2672 resets = <&ufs_mem_hc 2633 resets = <&ufs_mem_hc 0>;
2673 reset-names = "ufsphy 2634 reset-names = "ufsphy";
2674 <<
2675 #phy-cells = <0>; <<
2676 status = "disabled"; 2635 status = "disabled";
>> 2636
>> 2637 ufs_mem_phy_lanes: phy@1d87400 {
>> 2638 reg = <0 0x01d87400 0 0x108>,
>> 2639 <0 0x01d87600 0 0x1e0>,
>> 2640 <0 0x01d87c00 0 0x1dc>,
>> 2641 <0 0x01d87800 0 0x108>,
>> 2642 <0 0x01d87a00 0 0x1e0>;
>> 2643 #phy-cells = <0>;
>> 2644 };
2677 }; 2645 };
2678 2646
2679 cryptobam: dma-controller@1dc 2647 cryptobam: dma-controller@1dc4000 {
2680 compatible = "qcom,ba 2648 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2681 reg = <0 0x01dc4000 0 2649 reg = <0 0x01dc4000 0 0x24000>;
2682 interrupts = <GIC_SPI 2650 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&rpmhcc RPM 2651 clocks = <&rpmhcc RPMH_CE_CLK>;
2684 clock-names = "bam_cl 2652 clock-names = "bam_clk";
2685 #dma-cells = <1>; 2653 #dma-cells = <1>;
2686 qcom,ee = <0>; 2654 qcom,ee = <0>;
2687 qcom,controlled-remot 2655 qcom,controlled-remotely;
2688 iommus = <&apps_smmu 2656 iommus = <&apps_smmu 0x704 0x1>,
2689 <&apps_smmu 2657 <&apps_smmu 0x706 0x1>,
2690 <&apps_smmu 2658 <&apps_smmu 0x714 0x1>,
2691 <&apps_smmu 2659 <&apps_smmu 0x716 0x1>;
2692 }; 2660 };
2693 2661
2694 crypto: crypto@1dfa000 { 2662 crypto: crypto@1dfa000 {
2695 compatible = "qcom,cr 2663 compatible = "qcom,crypto-v5.4";
2696 reg = <0 0x01dfa000 0 2664 reg = <0 0x01dfa000 0 0x6000>;
2697 clocks = <&gcc GCC_CE 2665 clocks = <&gcc GCC_CE1_AHB_CLK>,
2698 <&gcc GCC_CE 2666 <&gcc GCC_CE1_AXI_CLK>,
2699 <&rpmhcc RPM 2667 <&rpmhcc RPMH_CE_CLK>;
2700 clock-names = "iface" 2668 clock-names = "iface", "bus", "core";
2701 dmas = <&cryptobam 6> 2669 dmas = <&cryptobam 6>, <&cryptobam 7>;
2702 dma-names = "rx", "tx 2670 dma-names = "rx", "tx";
2703 iommus = <&apps_smmu 2671 iommus = <&apps_smmu 0x704 0x1>,
2704 <&apps_smmu 2672 <&apps_smmu 0x706 0x1>,
2705 <&apps_smmu 2673 <&apps_smmu 0x714 0x1>,
2706 <&apps_smmu 2674 <&apps_smmu 0x716 0x1>;
2707 }; 2675 };
2708 2676
2709 ipa: ipa@1e40000 { 2677 ipa: ipa@1e40000 {
2710 compatible = "qcom,sd 2678 compatible = "qcom,sdm845-ipa";
2711 2679
2712 iommus = <&apps_smmu 2680 iommus = <&apps_smmu 0x720 0x0>,
2713 <&apps_smmu 2681 <&apps_smmu 0x722 0x0>;
2714 reg = <0 0x01e40000 0 2682 reg = <0 0x01e40000 0 0x7000>,
2715 <0 0x01e47000 0 2683 <0 0x01e47000 0 0x2000>,
2716 <0 0x01e04000 0 2684 <0 0x01e04000 0 0x2c000>;
2717 reg-names = "ipa-reg" 2685 reg-names = "ipa-reg",
2718 "ipa-shar 2686 "ipa-shared",
2719 "gsi"; 2687 "gsi";
2720 2688
2721 interrupts-extended = 2689 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2722 2690 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2723 2691 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2724 2692 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2725 interrupt-names = "ip 2693 interrupt-names = "ipa",
2726 "gs 2694 "gsi",
2727 "ip 2695 "ipa-clock-query",
2728 "ip 2696 "ipa-setup-ready";
2729 2697
2730 clocks = <&rpmhcc RPM 2698 clocks = <&rpmhcc RPMH_IPA_CLK>;
2731 clock-names = "core"; 2699 clock-names = "core";
2732 2700
2733 interconnects = <&agg 2701 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2734 <&agg 2702 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2735 <&gla 2703 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2736 interconnect-names = 2704 interconnect-names = "memory",
2737 2705 "imem",
2738 2706 "config";
2739 2707
2740 qcom,smem-states = <& 2708 qcom,smem-states = <&ipa_smp2p_out 0>,
2741 <& 2709 <&ipa_smp2p_out 1>;
2742 qcom,smem-state-names 2710 qcom,smem-state-names = "ipa-clock-enabled-valid",
2743 2711 "ipa-clock-enabled";
2744 2712
2745 status = "disabled"; 2713 status = "disabled";
2746 }; 2714 };
2747 2715
2748 tcsr_mutex: hwlock@1f40000 { 2716 tcsr_mutex: hwlock@1f40000 {
2749 compatible = "qcom,tc 2717 compatible = "qcom,tcsr-mutex";
2750 reg = <0 0x01f40000 0 2718 reg = <0 0x01f40000 0 0x20000>;
2751 #hwlock-cells = <1>; 2719 #hwlock-cells = <1>;
2752 }; 2720 };
2753 2721
2754 tcsr_regs_1: syscon@1f60000 { 2722 tcsr_regs_1: syscon@1f60000 {
2755 compatible = "qcom,sd 2723 compatible = "qcom,sdm845-tcsr", "syscon";
2756 reg = <0 0x01f60000 0 2724 reg = <0 0x01f60000 0 0x20000>;
2757 }; 2725 };
2758 2726
2759 tlmm: pinctrl@3400000 { 2727 tlmm: pinctrl@3400000 {
2760 compatible = "qcom,sd 2728 compatible = "qcom,sdm845-pinctrl";
2761 reg = <0 0x03400000 0 2729 reg = <0 0x03400000 0 0xc00000>;
2762 interrupts = <GIC_SPI 2730 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2763 gpio-controller; 2731 gpio-controller;
2764 #gpio-cells = <2>; 2732 #gpio-cells = <2>;
2765 interrupt-controller; 2733 interrupt-controller;
2766 #interrupt-cells = <2 2734 #interrupt-cells = <2>;
2767 gpio-ranges = <&tlmm 2735 gpio-ranges = <&tlmm 0 0 151>;
2768 wakeup-parent = <&pdc 2736 wakeup-parent = <&pdc_intc>;
2769 2737
2770 cci0_default: cci0-de 2738 cci0_default: cci0-default-state {
2771 /* SDA, SCL * 2739 /* SDA, SCL */
2772 pins = "gpio1 2740 pins = "gpio17", "gpio18";
2773 function = "c 2741 function = "cci_i2c";
2774 2742
2775 bias-pull-up; 2743 bias-pull-up;
2776 drive-strengt 2744 drive-strength = <2>; /* 2 mA */
2777 }; 2745 };
2778 2746
2779 cci0_sleep: cci0-slee 2747 cci0_sleep: cci0-sleep-state {
2780 /* SDA, SCL * 2748 /* SDA, SCL */
2781 pins = "gpio1 2749 pins = "gpio17", "gpio18";
2782 function = "c 2750 function = "cci_i2c";
2783 2751
2784 drive-strengt 2752 drive-strength = <2>; /* 2 mA */
2785 bias-pull-dow 2753 bias-pull-down;
2786 }; 2754 };
2787 2755
2788 cci1_default: cci1-de 2756 cci1_default: cci1-default-state {
2789 /* SDA, SCL * 2757 /* SDA, SCL */
2790 pins = "gpio1 2758 pins = "gpio19", "gpio20";
2791 function = "c 2759 function = "cci_i2c";
2792 2760
2793 bias-pull-up; 2761 bias-pull-up;
2794 drive-strengt 2762 drive-strength = <2>; /* 2 mA */
2795 }; 2763 };
2796 2764
2797 cci1_sleep: cci1-slee 2765 cci1_sleep: cci1-sleep-state {
2798 /* SDA, SCL * 2766 /* SDA, SCL */
2799 pins = "gpio1 2767 pins = "gpio19", "gpio20";
2800 function = "c 2768 function = "cci_i2c";
2801 2769
2802 drive-strengt 2770 drive-strength = <2>; /* 2 mA */
2803 bias-pull-dow 2771 bias-pull-down;
2804 }; 2772 };
2805 2773
2806 qspi_clk: qspi-clk-st 2774 qspi_clk: qspi-clk-state {
2807 pins = "gpio9 2775 pins = "gpio95";
2808 function = "q 2776 function = "qspi_clk";
2809 }; 2777 };
2810 2778
2811 qspi_cs0: qspi-cs0-st 2779 qspi_cs0: qspi-cs0-state {
2812 pins = "gpio9 2780 pins = "gpio90";
2813 function = "q 2781 function = "qspi_cs";
2814 }; 2782 };
2815 2783
2816 qspi_cs1: qspi-cs1-st 2784 qspi_cs1: qspi-cs1-state {
2817 pins = "gpio8 2785 pins = "gpio89";
2818 function = "q 2786 function = "qspi_cs";
2819 }; 2787 };
2820 2788
2821 qspi_data0: qspi-data 2789 qspi_data0: qspi-data0-state {
2822 pins = "gpio9 2790 pins = "gpio91";
2823 function = "q 2791 function = "qspi_data";
2824 }; 2792 };
2825 2793
2826 qspi_data1: qspi-data 2794 qspi_data1: qspi-data1-state {
2827 pins = "gpio9 2795 pins = "gpio92";
2828 function = "q 2796 function = "qspi_data";
2829 }; 2797 };
2830 2798
2831 qspi_data23: qspi-dat 2799 qspi_data23: qspi-data23-state {
2832 pins = "gpio9 2800 pins = "gpio93", "gpio94";
2833 function = "q 2801 function = "qspi_data";
2834 }; 2802 };
2835 2803
2836 qup_i2c0_default: qup 2804 qup_i2c0_default: qup-i2c0-default-state {
2837 pins = "gpio0 2805 pins = "gpio0", "gpio1";
2838 function = "q 2806 function = "qup0";
2839 }; 2807 };
2840 2808
2841 qup_i2c1_default: qup 2809 qup_i2c1_default: qup-i2c1-default-state {
2842 pins = "gpio1 2810 pins = "gpio17", "gpio18";
2843 function = "q 2811 function = "qup1";
2844 }; 2812 };
2845 2813
2846 qup_i2c2_default: qup 2814 qup_i2c2_default: qup-i2c2-default-state {
2847 pins = "gpio2 2815 pins = "gpio27", "gpio28";
2848 function = "q 2816 function = "qup2";
2849 }; 2817 };
2850 2818
2851 qup_i2c3_default: qup 2819 qup_i2c3_default: qup-i2c3-default-state {
2852 pins = "gpio4 2820 pins = "gpio41", "gpio42";
2853 function = "q 2821 function = "qup3";
2854 }; 2822 };
2855 2823
2856 qup_i2c4_default: qup 2824 qup_i2c4_default: qup-i2c4-default-state {
2857 pins = "gpio8 2825 pins = "gpio89", "gpio90";
2858 function = "q 2826 function = "qup4";
2859 }; 2827 };
2860 2828
2861 qup_i2c5_default: qup 2829 qup_i2c5_default: qup-i2c5-default-state {
2862 pins = "gpio8 2830 pins = "gpio85", "gpio86";
2863 function = "q 2831 function = "qup5";
2864 }; 2832 };
2865 2833
2866 qup_i2c6_default: qup 2834 qup_i2c6_default: qup-i2c6-default-state {
2867 pins = "gpio4 2835 pins = "gpio45", "gpio46";
2868 function = "q 2836 function = "qup6";
2869 }; 2837 };
2870 2838
2871 qup_i2c7_default: qup 2839 qup_i2c7_default: qup-i2c7-default-state {
2872 pins = "gpio9 2840 pins = "gpio93", "gpio94";
2873 function = "q 2841 function = "qup7";
2874 }; 2842 };
2875 2843
2876 qup_i2c8_default: qup 2844 qup_i2c8_default: qup-i2c8-default-state {
2877 pins = "gpio6 2845 pins = "gpio65", "gpio66";
2878 function = "q 2846 function = "qup8";
2879 }; 2847 };
2880 2848
2881 qup_i2c9_default: qup 2849 qup_i2c9_default: qup-i2c9-default-state {
2882 pins = "gpio6 2850 pins = "gpio6", "gpio7";
2883 function = "q 2851 function = "qup9";
2884 }; 2852 };
2885 2853
2886 qup_i2c10_default: qu 2854 qup_i2c10_default: qup-i2c10-default-state {
2887 pins = "gpio5 2855 pins = "gpio55", "gpio56";
2888 function = "q 2856 function = "qup10";
2889 }; 2857 };
2890 2858
2891 qup_i2c11_default: qu 2859 qup_i2c11_default: qup-i2c11-default-state {
2892 pins = "gpio3 2860 pins = "gpio31", "gpio32";
2893 function = "q 2861 function = "qup11";
2894 }; 2862 };
2895 2863
2896 qup_i2c12_default: qu 2864 qup_i2c12_default: qup-i2c12-default-state {
2897 pins = "gpio4 2865 pins = "gpio49", "gpio50";
2898 function = "q 2866 function = "qup12";
2899 }; 2867 };
2900 2868
2901 qup_i2c13_default: qu 2869 qup_i2c13_default: qup-i2c13-default-state {
2902 pins = "gpio1 2870 pins = "gpio105", "gpio106";
2903 function = "q 2871 function = "qup13";
2904 }; 2872 };
2905 2873
2906 qup_i2c14_default: qu 2874 qup_i2c14_default: qup-i2c14-default-state {
2907 pins = "gpio3 2875 pins = "gpio33", "gpio34";
2908 function = "q 2876 function = "qup14";
2909 }; 2877 };
2910 2878
2911 qup_i2c15_default: qu 2879 qup_i2c15_default: qup-i2c15-default-state {
2912 pins = "gpio8 2880 pins = "gpio81", "gpio82";
2913 function = "q 2881 function = "qup15";
2914 }; 2882 };
2915 2883
2916 qup_spi0_default: qup 2884 qup_spi0_default: qup-spi0-default-state {
2917 pins = "gpio0 2885 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2918 function = "q 2886 function = "qup0";
2919 }; 2887 };
2920 2888
2921 qup_spi1_default: qup 2889 qup_spi1_default: qup-spi1-default-state {
2922 pins = "gpio1 2890 pins = "gpio17", "gpio18", "gpio19", "gpio20";
2923 function = "q 2891 function = "qup1";
2924 }; 2892 };
2925 2893
2926 qup_spi2_default: qup 2894 qup_spi2_default: qup-spi2-default-state {
2927 pins = "gpio2 2895 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2928 function = "q 2896 function = "qup2";
2929 }; 2897 };
2930 2898
2931 qup_spi3_default: qup 2899 qup_spi3_default: qup-spi3-default-state {
2932 pins = "gpio4 2900 pins = "gpio41", "gpio42", "gpio43", "gpio44";
2933 function = "q 2901 function = "qup3";
2934 }; 2902 };
2935 2903
2936 qup_spi4_default: qup 2904 qup_spi4_default: qup-spi4-default-state {
2937 pins = "gpio8 2905 pins = "gpio89", "gpio90", "gpio91", "gpio92";
2938 function = "q 2906 function = "qup4";
2939 }; 2907 };
2940 2908
2941 qup_spi5_default: qup 2909 qup_spi5_default: qup-spi5-default-state {
2942 pins = "gpio8 2910 pins = "gpio85", "gpio86", "gpio87", "gpio88";
2943 function = "q 2911 function = "qup5";
2944 }; 2912 };
2945 2913
2946 qup_spi6_default: qup 2914 qup_spi6_default: qup-spi6-default-state {
2947 pins = "gpio4 2915 pins = "gpio45", "gpio46", "gpio47", "gpio48";
2948 function = "q 2916 function = "qup6";
2949 }; 2917 };
2950 2918
2951 qup_spi7_default: qup 2919 qup_spi7_default: qup-spi7-default-state {
2952 pins = "gpio9 2920 pins = "gpio93", "gpio94", "gpio95", "gpio96";
2953 function = "q 2921 function = "qup7";
2954 }; 2922 };
2955 2923
2956 qup_spi8_default: qup 2924 qup_spi8_default: qup-spi8-default-state {
2957 pins = "gpio6 2925 pins = "gpio65", "gpio66", "gpio67", "gpio68";
2958 function = "q 2926 function = "qup8";
2959 }; 2927 };
2960 2928
2961 qup_spi9_default: qup 2929 qup_spi9_default: qup-spi9-default-state {
2962 pins = "gpio6 2930 pins = "gpio6", "gpio7", "gpio4", "gpio5";
2963 function = "q 2931 function = "qup9";
2964 }; 2932 };
2965 2933
2966 qup_spi10_default: qu 2934 qup_spi10_default: qup-spi10-default-state {
2967 pins = "gpio5 2935 pins = "gpio55", "gpio56", "gpio53", "gpio54";
2968 function = "q 2936 function = "qup10";
2969 }; 2937 };
2970 2938
2971 qup_spi11_default: qu 2939 qup_spi11_default: qup-spi11-default-state {
2972 pins = "gpio3 2940 pins = "gpio31", "gpio32", "gpio33", "gpio34";
2973 function = "q 2941 function = "qup11";
2974 }; 2942 };
2975 2943
2976 qup_spi12_default: qu 2944 qup_spi12_default: qup-spi12-default-state {
2977 pins = "gpio4 2945 pins = "gpio49", "gpio50", "gpio51", "gpio52";
2978 function = "q 2946 function = "qup12";
2979 }; 2947 };
2980 2948
2981 qup_spi13_default: qu 2949 qup_spi13_default: qup-spi13-default-state {
2982 pins = "gpio1 2950 pins = "gpio105", "gpio106", "gpio107", "gpio108";
2983 function = "q 2951 function = "qup13";
2984 }; 2952 };
2985 2953
2986 qup_spi14_default: qu 2954 qup_spi14_default: qup-spi14-default-state {
2987 pins = "gpio3 2955 pins = "gpio33", "gpio34", "gpio31", "gpio32";
2988 function = "q 2956 function = "qup14";
2989 }; 2957 };
2990 2958
2991 qup_spi15_default: qu 2959 qup_spi15_default: qup-spi15-default-state {
2992 pins = "gpio8 2960 pins = "gpio81", "gpio82", "gpio83", "gpio84";
2993 function = "q 2961 function = "qup15";
2994 }; 2962 };
2995 2963
2996 qup_uart0_default: qu 2964 qup_uart0_default: qup-uart0-default-state {
2997 qup_uart0_tx: 2965 qup_uart0_tx: tx-pins {
2998 pins 2966 pins = "gpio2";
2999 funct 2967 function = "qup0";
3000 }; 2968 };
3001 2969
3002 qup_uart0_rx: 2970 qup_uart0_rx: rx-pins {
3003 pins 2971 pins = "gpio3";
3004 funct 2972 function = "qup0";
3005 }; 2973 };
3006 }; 2974 };
3007 2975
3008 qup_uart1_default: qu 2976 qup_uart1_default: qup-uart1-default-state {
3009 qup_uart1_tx: 2977 qup_uart1_tx: tx-pins {
3010 pins 2978 pins = "gpio19";
3011 funct 2979 function = "qup1";
3012 }; 2980 };
3013 2981
3014 qup_uart1_rx: 2982 qup_uart1_rx: rx-pins {
3015 pins 2983 pins = "gpio20";
3016 funct 2984 function = "qup1";
3017 }; 2985 };
3018 }; 2986 };
3019 2987
3020 qup_uart2_default: qu 2988 qup_uart2_default: qup-uart2-default-state {
3021 qup_uart2_tx: 2989 qup_uart2_tx: tx-pins {
3022 pins 2990 pins = "gpio29";
3023 funct 2991 function = "qup2";
3024 }; 2992 };
3025 2993
3026 qup_uart2_rx: 2994 qup_uart2_rx: rx-pins {
3027 pins 2995 pins = "gpio30";
3028 funct 2996 function = "qup2";
3029 }; 2997 };
3030 }; 2998 };
3031 2999
3032 qup_uart3_default: qu 3000 qup_uart3_default: qup-uart3-default-state {
3033 qup_uart3_tx: 3001 qup_uart3_tx: tx-pins {
3034 pins 3002 pins = "gpio43";
3035 funct 3003 function = "qup3";
3036 }; 3004 };
3037 3005
3038 qup_uart3_rx: 3006 qup_uart3_rx: rx-pins {
3039 pins 3007 pins = "gpio44";
3040 funct 3008 function = "qup3";
3041 }; 3009 };
3042 }; 3010 };
3043 3011
3044 qup_uart3_4pin: qup-u 3012 qup_uart3_4pin: qup-uart3-4pin-state {
3045 qup_uart3_4pi 3013 qup_uart3_4pin_cts: cts-pins {
3046 pins 3014 pins = "gpio41";
3047 funct 3015 function = "qup3";
3048 }; 3016 };
3049 3017
3050 qup_uart3_4pi 3018 qup_uart3_4pin_rts_tx: rts-tx-pins {
3051 pins 3019 pins = "gpio42", "gpio43";
3052 funct 3020 function = "qup3";
3053 }; 3021 };
3054 3022
3055 qup_uart3_4pi 3023 qup_uart3_4pin_rx: rx-pins {
3056 pins 3024 pins = "gpio44";
3057 funct 3025 function = "qup3";
3058 }; 3026 };
3059 }; 3027 };
3060 3028
3061 qup_uart4_default: qu 3029 qup_uart4_default: qup-uart4-default-state {
3062 qup_uart4_tx: 3030 qup_uart4_tx: tx-pins {
3063 pins 3031 pins = "gpio91";
3064 funct 3032 function = "qup4";
3065 }; 3033 };
3066 3034
3067 qup_uart4_rx: 3035 qup_uart4_rx: rx-pins {
3068 pins 3036 pins = "gpio92";
3069 funct 3037 function = "qup4";
3070 }; 3038 };
3071 }; 3039 };
3072 3040
3073 qup_uart5_default: qu 3041 qup_uart5_default: qup-uart5-default-state {
3074 qup_uart5_tx: 3042 qup_uart5_tx: tx-pins {
3075 pins 3043 pins = "gpio87";
3076 funct 3044 function = "qup5";
3077 }; 3045 };
3078 3046
3079 qup_uart5_rx: 3047 qup_uart5_rx: rx-pins {
3080 pins 3048 pins = "gpio88";
3081 funct 3049 function = "qup5";
3082 }; 3050 };
3083 }; 3051 };
3084 3052
3085 qup_uart6_default: qu 3053 qup_uart6_default: qup-uart6-default-state {
3086 qup_uart6_tx: 3054 qup_uart6_tx: tx-pins {
3087 pins 3055 pins = "gpio47";
3088 funct 3056 function = "qup6";
3089 }; 3057 };
3090 3058
3091 qup_uart6_rx: 3059 qup_uart6_rx: rx-pins {
3092 pins 3060 pins = "gpio48";
3093 funct 3061 function = "qup6";
3094 }; 3062 };
3095 }; 3063 };
3096 3064
3097 qup_uart6_4pin: qup-u 3065 qup_uart6_4pin: qup-uart6-4pin-state {
3098 qup_uart6_4pi 3066 qup_uart6_4pin_cts: cts-pins {
3099 pins 3067 pins = "gpio45";
3100 funct 3068 function = "qup6";
3101 bias- 3069 bias-pull-down;
3102 }; 3070 };
3103 3071
3104 qup_uart6_4pi 3072 qup_uart6_4pin_rts_tx: rts-tx-pins {
3105 pins 3073 pins = "gpio46", "gpio47";
3106 funct 3074 function = "qup6";
3107 drive 3075 drive-strength = <2>;
3108 bias- 3076 bias-disable;
3109 }; 3077 };
3110 3078
3111 qup_uart6_4pi 3079 qup_uart6_4pin_rx: rx-pins {
3112 pins 3080 pins = "gpio48";
3113 funct 3081 function = "qup6";
3114 bias- 3082 bias-pull-up;
3115 }; 3083 };
3116 }; 3084 };
3117 3085
3118 qup_uart7_default: qu 3086 qup_uart7_default: qup-uart7-default-state {
3119 qup_uart7_tx: 3087 qup_uart7_tx: tx-pins {
3120 pins 3088 pins = "gpio95";
3121 funct 3089 function = "qup7";
3122 }; 3090 };
3123 3091
3124 qup_uart7_rx: 3092 qup_uart7_rx: rx-pins {
3125 pins 3093 pins = "gpio96";
3126 funct 3094 function = "qup7";
3127 }; 3095 };
3128 }; 3096 };
3129 3097
3130 qup_uart8_default: qu 3098 qup_uart8_default: qup-uart8-default-state {
3131 qup_uart8_tx: 3099 qup_uart8_tx: tx-pins {
3132 pins 3100 pins = "gpio67";
3133 funct 3101 function = "qup8";
3134 }; 3102 };
3135 3103
3136 qup_uart8_rx: 3104 qup_uart8_rx: rx-pins {
3137 pins 3105 pins = "gpio68";
3138 funct 3106 function = "qup8";
3139 }; 3107 };
3140 }; 3108 };
3141 3109
3142 qup_uart9_default: qu 3110 qup_uart9_default: qup-uart9-default-state {
3143 qup_uart9_tx: 3111 qup_uart9_tx: tx-pins {
3144 pins 3112 pins = "gpio4";
3145 funct 3113 function = "qup9";
3146 }; 3114 };
3147 3115
3148 qup_uart9_rx: 3116 qup_uart9_rx: rx-pins {
3149 pins 3117 pins = "gpio5";
3150 funct 3118 function = "qup9";
3151 }; 3119 };
3152 }; 3120 };
3153 3121
3154 qup_uart10_default: q 3122 qup_uart10_default: qup-uart10-default-state {
3155 qup_uart10_tx 3123 qup_uart10_tx: tx-pins {
3156 pins 3124 pins = "gpio53";
3157 funct 3125 function = "qup10";
3158 }; 3126 };
3159 3127
3160 qup_uart10_rx 3128 qup_uart10_rx: rx-pins {
3161 pins 3129 pins = "gpio54";
3162 funct 3130 function = "qup10";
3163 }; 3131 };
3164 }; 3132 };
3165 3133
3166 qup_uart11_default: q 3134 qup_uart11_default: qup-uart11-default-state {
3167 qup_uart11_tx 3135 qup_uart11_tx: tx-pins {
3168 pins 3136 pins = "gpio33";
3169 funct 3137 function = "qup11";
3170 }; 3138 };
3171 3139
3172 qup_uart11_rx 3140 qup_uart11_rx: rx-pins {
3173 pins 3141 pins = "gpio34";
3174 funct 3142 function = "qup11";
3175 }; 3143 };
3176 }; 3144 };
3177 3145
3178 qup_uart12_default: q 3146 qup_uart12_default: qup-uart12-default-state {
3179 qup_uart12_tx 3147 qup_uart12_tx: tx-pins {
3180 pins 3148 pins = "gpio51";
3181 funct 3149 function = "qup0";
3182 }; 3150 };
3183 3151
3184 qup_uart12_rx 3152 qup_uart12_rx: rx-pins {
3185 pins 3153 pins = "gpio52";
3186 funct 3154 function = "qup0";
3187 }; 3155 };
3188 }; 3156 };
3189 3157
3190 qup_uart13_default: q 3158 qup_uart13_default: qup-uart13-default-state {
3191 qup_uart13_tx 3159 qup_uart13_tx: tx-pins {
3192 pins 3160 pins = "gpio107";
3193 funct 3161 function = "qup13";
3194 }; 3162 };
3195 3163
3196 qup_uart13_rx 3164 qup_uart13_rx: rx-pins {
3197 pins 3165 pins = "gpio108";
3198 funct 3166 function = "qup13";
3199 }; 3167 };
3200 }; 3168 };
3201 3169
3202 qup_uart14_default: q 3170 qup_uart14_default: qup-uart14-default-state {
3203 qup_uart14_tx 3171 qup_uart14_tx: tx-pins {
3204 pins 3172 pins = "gpio31";
3205 funct 3173 function = "qup14";
3206 }; 3174 };
3207 3175
3208 qup_uart14_rx 3176 qup_uart14_rx: rx-pins {
3209 pins 3177 pins = "gpio32";
3210 funct 3178 function = "qup14";
3211 }; 3179 };
3212 }; 3180 };
3213 3181
3214 qup_uart15_default: q 3182 qup_uart15_default: qup-uart15-default-state {
3215 qup_uart15_tx 3183 qup_uart15_tx: tx-pins {
3216 pins 3184 pins = "gpio83";
3217 funct 3185 function = "qup15";
3218 }; 3186 };
3219 3187
3220 qup_uart15_rx 3188 qup_uart15_rx: rx-pins {
3221 pins 3189 pins = "gpio84";
3222 funct 3190 function = "qup15";
3223 }; 3191 };
3224 }; 3192 };
3225 3193
3226 quat_mi2s_sleep: quat 3194 quat_mi2s_sleep: quat-mi2s-sleep-state {
3227 pins = "gpio5 3195 pins = "gpio58", "gpio59";
3228 function = "g 3196 function = "gpio";
3229 drive-strengt 3197 drive-strength = <2>;
3230 bias-pull-dow 3198 bias-pull-down;
3231 }; 3199 };
3232 3200
3233 quat_mi2s_active: qua 3201 quat_mi2s_active: quat-mi2s-active-state {
3234 pins = "gpio5 3202 pins = "gpio58", "gpio59";
3235 function = "q 3203 function = "qua_mi2s";
3236 drive-strengt 3204 drive-strength = <8>;
3237 bias-disable; 3205 bias-disable;
3238 output-high; 3206 output-high;
3239 }; 3207 };
3240 3208
3241 quat_mi2s_sd0_sleep: 3209 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3242 pins = "gpio6 3210 pins = "gpio60";
3243 function = "g 3211 function = "gpio";
3244 drive-strengt 3212 drive-strength = <2>;
3245 bias-pull-dow 3213 bias-pull-down;
3246 }; 3214 };
3247 3215
3248 quat_mi2s_sd0_active: 3216 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3249 pins = "gpio6 3217 pins = "gpio60";
3250 function = "q 3218 function = "qua_mi2s";
3251 drive-strengt 3219 drive-strength = <8>;
3252 bias-disable; 3220 bias-disable;
3253 }; 3221 };
3254 3222
3255 quat_mi2s_sd1_sleep: 3223 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3256 pins = "gpio6 3224 pins = "gpio61";
3257 function = "g 3225 function = "gpio";
3258 drive-strengt 3226 drive-strength = <2>;
3259 bias-pull-dow 3227 bias-pull-down;
3260 }; 3228 };
3261 3229
3262 quat_mi2s_sd1_active: 3230 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3263 pins = "gpio6 3231 pins = "gpio61";
3264 function = "q 3232 function = "qua_mi2s";
3265 drive-strengt 3233 drive-strength = <8>;
3266 bias-disable; 3234 bias-disable;
3267 }; 3235 };
3268 3236
3269 quat_mi2s_sd2_sleep: 3237 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3270 pins = "gpio6 3238 pins = "gpio62";
3271 function = "g 3239 function = "gpio";
3272 drive-strengt 3240 drive-strength = <2>;
3273 bias-pull-dow 3241 bias-pull-down;
3274 }; 3242 };
3275 3243
3276 quat_mi2s_sd2_active: 3244 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3277 pins = "gpio6 3245 pins = "gpio62";
3278 function = "q 3246 function = "qua_mi2s";
3279 drive-strengt 3247 drive-strength = <8>;
3280 bias-disable; 3248 bias-disable;
3281 }; 3249 };
3282 3250
3283 quat_mi2s_sd3_sleep: 3251 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3284 pins = "gpio6 3252 pins = "gpio63";
3285 function = "g 3253 function = "gpio";
3286 drive-strengt 3254 drive-strength = <2>;
3287 bias-pull-dow 3255 bias-pull-down;
3288 }; 3256 };
3289 3257
3290 quat_mi2s_sd3_active: 3258 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3291 pins = "gpio6 3259 pins = "gpio63";
3292 function = "q 3260 function = "qua_mi2s";
3293 drive-strengt 3261 drive-strength = <8>;
3294 bias-disable; 3262 bias-disable;
3295 }; 3263 };
3296 }; 3264 };
3297 3265
3298 mss_pil: remoteproc@4080000 { 3266 mss_pil: remoteproc@4080000 {
3299 compatible = "qcom,sd 3267 compatible = "qcom,sdm845-mss-pil";
3300 reg = <0 0x04080000 0 3268 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3301 reg-names = "qdsp6", 3269 reg-names = "qdsp6", "rmb";
3302 3270
3303 interrupts-extended = 3271 interrupts-extended =
3304 <&intc GIC_SP 3272 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
3305 <&modem_smp2p 3273 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3306 <&modem_smp2p 3274 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3307 <&modem_smp2p 3275 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3308 <&modem_smp2p 3276 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3309 <&modem_smp2p 3277 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3310 interrupt-names = "wd 3278 interrupt-names = "wdog", "fatal", "ready",
3311 "ha 3279 "handover", "stop-ack",
3312 "sh 3280 "shutdown-ack";
3313 3281
3314 clocks = <&gcc GCC_MS 3282 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
3315 <&gcc GCC_MS 3283 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
3316 <&gcc GCC_BO 3284 <&gcc GCC_BOOT_ROM_AHB_CLK>,
3317 <&gcc GCC_MS 3285 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
3318 <&gcc GCC_MS 3286 <&gcc GCC_MSS_SNOC_AXI_CLK>,
3319 <&gcc GCC_MS 3287 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
3320 <&gcc GCC_PR 3288 <&gcc GCC_PRNG_AHB_CLK>,
3321 <&rpmhcc RPM 3289 <&rpmhcc RPMH_CXO_CLK>;
3322 clock-names = "iface" 3290 clock-names = "iface", "bus", "mem", "gpll0_mss",
3323 "snoc_a 3291 "snoc_axi", "mnoc_axi", "prng", "xo";
3324 3292
3325 qcom,qmp = <&aoss_qmp 3293 qcom,qmp = <&aoss_qmp>;
3326 3294
3327 qcom,smem-states = <& 3295 qcom,smem-states = <&modem_smp2p_out 0>;
3328 qcom,smem-state-names 3296 qcom,smem-state-names = "stop";
3329 3297
3330 resets = <&aoss_reset 3298 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
3331 <&pdc_reset 3299 <&pdc_reset PDC_MODEM_SYNC_RESET>;
3332 reset-names = "mss_re 3300 reset-names = "mss_restart", "pdc_reset";
3333 3301
3334 qcom,halt-regs = <&tc 3302 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3335 3303
3336 power-domains = <&rpm 3304 power-domains = <&rpmhpd SDM845_CX>,
3337 <&rpm 3305 <&rpmhpd SDM845_MX>,
3338 <&rpm 3306 <&rpmhpd SDM845_MSS>;
3339 power-domain-names = 3307 power-domain-names = "cx", "mx", "mss";
3340 3308
3341 status = "disabled"; 3309 status = "disabled";
3342 3310
3343 mba { 3311 mba {
3344 memory-region 3312 memory-region = <&mba_region>;
3345 }; 3313 };
3346 3314
3347 mpss { 3315 mpss {
3348 memory-region 3316 memory-region = <&mpss_region>;
3349 }; 3317 };
3350 3318
3351 metadata { 3319 metadata {
3352 memory-region 3320 memory-region = <&mdata_mem>;
3353 }; 3321 };
3354 3322
3355 glink-edge { 3323 glink-edge {
3356 interrupts = 3324 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
3357 label = "mode 3325 label = "modem";
3358 qcom,remote-p 3326 qcom,remote-pid = <1>;
3359 mboxes = <&ap 3327 mboxes = <&apss_shared 12>;
3360 }; 3328 };
3361 }; 3329 };
3362 3330
3363 gpucc: clock-controller@50900 3331 gpucc: clock-controller@5090000 {
3364 compatible = "qcom,sd 3332 compatible = "qcom,sdm845-gpucc";
3365 reg = <0 0x05090000 0 3333 reg = <0 0x05090000 0 0x9000>;
3366 #clock-cells = <1>; 3334 #clock-cells = <1>;
3367 #reset-cells = <1>; 3335 #reset-cells = <1>;
3368 #power-domain-cells = 3336 #power-domain-cells = <1>;
3369 clocks = <&rpmhcc RPM 3337 clocks = <&rpmhcc RPMH_CXO_CLK>,
3370 <&gcc GCC_GP 3338 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3371 <&gcc GCC_GP 3339 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3372 clock-names = "bi_tcx 3340 clock-names = "bi_tcxo",
3373 "gcc_gp 3341 "gcc_gpu_gpll0_clk_src",
3374 "gcc_gp 3342 "gcc_gpu_gpll0_div_clk_src";
3375 }; 3343 };
3376 3344
3377 slpi_pas: remoteproc@5c00000 3345 slpi_pas: remoteproc@5c00000 {
3378 compatible = "qcom,sd 3346 compatible = "qcom,sdm845-slpi-pas";
3379 reg = <0 0x5c00000 0 3347 reg = <0 0x5c00000 0 0x4000>;
3380 3348
3381 interrupts-extended = 3349 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3382 3350 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3383 3351 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3384 3352 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3385 3353 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3386 interrupt-names = "wd 3354 interrupt-names = "wdog", "fatal", "ready",
3387 3355 "handover", "stop-ack";
3388 3356
3389 clocks = <&rpmhcc RPM 3357 clocks = <&rpmhcc RPMH_CXO_CLK>;
3390 clock-names = "xo"; 3358 clock-names = "xo";
3391 3359
3392 qcom,qmp = <&aoss_qmp 3360 qcom,qmp = <&aoss_qmp>;
3393 3361
3394 power-domains = <&rpm !! 3362 power-domains = <&rpmhpd SDM845_CX>,
3395 <&rpm !! 3363 <&rpmhpd SDM845_MX>;
3396 power-domain-names = 3364 power-domain-names = "lcx", "lmx";
3397 3365
3398 memory-region = <&slp 3366 memory-region = <&slpi_mem>;
3399 3367
3400 qcom,smem-states = <& 3368 qcom,smem-states = <&slpi_smp2p_out 0>;
3401 qcom,smem-state-names 3369 qcom,smem-state-names = "stop";
3402 3370
3403 status = "disabled"; 3371 status = "disabled";
3404 3372
3405 glink-edge { 3373 glink-edge {
3406 interrupts = 3374 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
3407 label = "dsps 3375 label = "dsps";
3408 qcom,remote-p 3376 qcom,remote-pid = <3>;
3409 mboxes = <&ap 3377 mboxes = <&apss_shared 24>;
3410 3378
3411 fastrpc { 3379 fastrpc {
3412 compa 3380 compatible = "qcom,fastrpc";
3413 qcom, 3381 qcom,glink-channels = "fastrpcglink-apps-dsp";
3414 label 3382 label = "sdsp";
3415 qcom, 3383 qcom,non-secure-domain;
3416 qcom, 3384 qcom,vmids = <QCOM_SCM_VMID_HLOS QCOM_SCM_VMID_MSS_MSA
3417 3385 QCOM_SCM_VMID_SSC_Q6 QCOM_SCM_VMID_ADSP_Q6>;
3418 memor 3386 memory-region = <&fastrpc_mem>;
3419 #addr 3387 #address-cells = <1>;
3420 #size 3388 #size-cells = <0>;
3421 3389
3422 compu 3390 compute-cb@0 {
3423 3391 compatible = "qcom,fastrpc-compute-cb";
3424 3392 reg = <0>;
3425 }; 3393 };
3426 }; 3394 };
3427 }; 3395 };
3428 }; 3396 };
3429 3397
3430 stm@6002000 { 3398 stm@6002000 {
3431 compatible = "arm,cor 3399 compatible = "arm,coresight-stm", "arm,primecell";
3432 reg = <0 0x06002000 0 3400 reg = <0 0x06002000 0 0x1000>,
3433 <0 0x16280000 0 3401 <0 0x16280000 0 0x180000>;
3434 reg-names = "stm-base 3402 reg-names = "stm-base", "stm-stimulus-base";
3435 3403
3436 clocks = <&aoss_qmp>; 3404 clocks = <&aoss_qmp>;
3437 clock-names = "apb_pc 3405 clock-names = "apb_pclk";
3438 3406
3439 out-ports { 3407 out-ports {
3440 port { 3408 port {
3441 stm_o 3409 stm_out: endpoint {
3442 3410 remote-endpoint =
3443 3411 <&funnel0_in7>;
3444 }; 3412 };
3445 }; 3413 };
3446 }; 3414 };
3447 }; 3415 };
3448 3416
3449 funnel@6041000 { 3417 funnel@6041000 {
3450 compatible = "arm,cor 3418 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3451 reg = <0 0x06041000 0 3419 reg = <0 0x06041000 0 0x1000>;
3452 3420
3453 clocks = <&aoss_qmp>; 3421 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc 3422 clock-names = "apb_pclk";
3455 3423
3456 out-ports { 3424 out-ports {
3457 port { 3425 port {
3458 funne 3426 funnel0_out: endpoint {
3459 3427 remote-endpoint =
3460 3428 <&merge_funnel_in0>;
3461 }; 3429 };
3462 }; 3430 };
3463 }; 3431 };
3464 3432
3465 in-ports { 3433 in-ports {
3466 #address-cell 3434 #address-cells = <1>;
3467 #size-cells = 3435 #size-cells = <0>;
3468 3436
3469 port@7 { 3437 port@7 {
3470 reg = 3438 reg = <7>;
3471 funne 3439 funnel0_in7: endpoint {
3472 3440 remote-endpoint = <&stm_out>;
3473 }; 3441 };
3474 }; 3442 };
3475 }; 3443 };
3476 }; 3444 };
3477 3445
3478 funnel@6043000 { 3446 funnel@6043000 {
3479 compatible = "arm,cor 3447 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3480 reg = <0 0x06043000 0 3448 reg = <0 0x06043000 0 0x1000>;
3481 3449
3482 clocks = <&aoss_qmp>; 3450 clocks = <&aoss_qmp>;
3483 clock-names = "apb_pc 3451 clock-names = "apb_pclk";
3484 3452
3485 out-ports { 3453 out-ports {
3486 port { 3454 port {
3487 funne 3455 funnel2_out: endpoint {
3488 3456 remote-endpoint =
3489 3457 <&merge_funnel_in2>;
3490 }; 3458 };
3491 }; 3459 };
3492 }; 3460 };
3493 3461
3494 in-ports { 3462 in-ports {
3495 #address-cell 3463 #address-cells = <1>;
3496 #size-cells = 3464 #size-cells = <0>;
3497 3465
3498 port@5 { 3466 port@5 {
3499 reg = 3467 reg = <5>;
3500 funne 3468 funnel2_in5: endpoint {
3501 3469 remote-endpoint =
3502 3470 <&apss_merge_funnel_out>;
3503 }; 3471 };
3504 }; 3472 };
3505 }; 3473 };
3506 }; 3474 };
3507 3475
3508 funnel@6045000 { 3476 funnel@6045000 {
3509 compatible = "arm,cor 3477 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3510 reg = <0 0x06045000 0 3478 reg = <0 0x06045000 0 0x1000>;
3511 3479
3512 clocks = <&aoss_qmp>; 3480 clocks = <&aoss_qmp>;
3513 clock-names = "apb_pc 3481 clock-names = "apb_pclk";
3514 3482
3515 out-ports { 3483 out-ports {
3516 port { 3484 port {
3517 merge 3485 merge_funnel_out: endpoint {
3518 3486 remote-endpoint = <&etf_in>;
3519 }; 3487 };
3520 }; 3488 };
3521 }; 3489 };
3522 3490
3523 in-ports { 3491 in-ports {
3524 #address-cell 3492 #address-cells = <1>;
3525 #size-cells = 3493 #size-cells = <0>;
3526 3494
3527 port@0 { 3495 port@0 {
3528 reg = 3496 reg = <0>;
3529 merge 3497 merge_funnel_in0: endpoint {
3530 3498 remote-endpoint =
3531 3499 <&funnel0_out>;
3532 }; 3500 };
3533 }; 3501 };
3534 3502
3535 port@2 { 3503 port@2 {
3536 reg = 3504 reg = <2>;
3537 merge 3505 merge_funnel_in2: endpoint {
3538 3506 remote-endpoint =
3539 3507 <&funnel2_out>;
3540 }; 3508 };
3541 }; 3509 };
3542 }; 3510 };
3543 }; 3511 };
3544 3512
3545 replicator@6046000 { 3513 replicator@6046000 {
3546 compatible = "arm,cor 3514 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3547 reg = <0 0x06046000 0 3515 reg = <0 0x06046000 0 0x1000>;
3548 3516
3549 clocks = <&aoss_qmp>; 3517 clocks = <&aoss_qmp>;
3550 clock-names = "apb_pc 3518 clock-names = "apb_pclk";
3551 3519
3552 out-ports { 3520 out-ports {
3553 port { 3521 port {
3554 repli 3522 replicator_out: endpoint {
3555 3523 remote-endpoint = <&etr_in>;
3556 }; 3524 };
3557 }; 3525 };
3558 }; 3526 };
3559 3527
3560 in-ports { 3528 in-ports {
3561 port { 3529 port {
3562 repli 3530 replicator_in: endpoint {
3563 3531 remote-endpoint = <&etf_out>;
3564 }; 3532 };
3565 }; 3533 };
3566 }; 3534 };
3567 }; 3535 };
3568 3536
3569 etf@6047000 { 3537 etf@6047000 {
3570 compatible = "arm,cor 3538 compatible = "arm,coresight-tmc", "arm,primecell";
3571 reg = <0 0x06047000 0 3539 reg = <0 0x06047000 0 0x1000>;
3572 3540
3573 clocks = <&aoss_qmp>; 3541 clocks = <&aoss_qmp>;
3574 clock-names = "apb_pc 3542 clock-names = "apb_pclk";
3575 3543
3576 out-ports { 3544 out-ports {
3577 port { 3545 port {
3578 etf_o 3546 etf_out: endpoint {
3579 3547 remote-endpoint =
3580 3548 <&replicator_in>;
3581 }; 3549 };
3582 }; 3550 };
3583 }; 3551 };
3584 3552
3585 in-ports { 3553 in-ports {
>> 3554 #address-cells = <1>;
>> 3555 #size-cells = <0>;
3586 3556
3587 port { !! 3557 port@1 {
>> 3558 reg = <1>;
3588 etf_i 3559 etf_in: endpoint {
3589 3560 remote-endpoint =
3590 3561 <&merge_funnel_out>;
3591 }; 3562 };
3592 }; 3563 };
3593 }; 3564 };
3594 }; 3565 };
3595 3566
3596 etr@6048000 { 3567 etr@6048000 {
3597 compatible = "arm,cor 3568 compatible = "arm,coresight-tmc", "arm,primecell";
3598 reg = <0 0x06048000 0 3569 reg = <0 0x06048000 0 0x1000>;
3599 3570
3600 clocks = <&aoss_qmp>; 3571 clocks = <&aoss_qmp>;
3601 clock-names = "apb_pc 3572 clock-names = "apb_pclk";
3602 arm,scatter-gather; 3573 arm,scatter-gather;
3603 3574
3604 in-ports { 3575 in-ports {
3605 port { 3576 port {
3606 etr_i 3577 etr_in: endpoint {
3607 3578 remote-endpoint =
3608 3579 <&replicator_out>;
3609 }; 3580 };
3610 }; 3581 };
3611 }; 3582 };
3612 }; 3583 };
3613 3584
3614 etm@7040000 { 3585 etm@7040000 {
3615 compatible = "arm,cor 3586 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 reg = <0 0x07040000 0 3587 reg = <0 0x07040000 0 0x1000>;
3617 3588
3618 cpu = <&CPU0>; 3589 cpu = <&CPU0>;
3619 3590
3620 clocks = <&aoss_qmp>; 3591 clocks = <&aoss_qmp>;
3621 clock-names = "apb_pc 3592 clock-names = "apb_pclk";
3622 arm,coresight-loses-c 3593 arm,coresight-loses-context-with-cpu;
3623 3594
3624 out-ports { 3595 out-ports {
3625 port { 3596 port {
3626 etm0_ 3597 etm0_out: endpoint {
3627 3598 remote-endpoint =
3628 3599 <&apss_funnel_in0>;
3629 }; 3600 };
3630 }; 3601 };
3631 }; 3602 };
3632 }; 3603 };
3633 3604
3634 etm@7140000 { 3605 etm@7140000 {
3635 compatible = "arm,cor 3606 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 reg = <0 0x07140000 0 3607 reg = <0 0x07140000 0 0x1000>;
3637 3608
3638 cpu = <&CPU1>; 3609 cpu = <&CPU1>;
3639 3610
3640 clocks = <&aoss_qmp>; 3611 clocks = <&aoss_qmp>;
3641 clock-names = "apb_pc 3612 clock-names = "apb_pclk";
3642 arm,coresight-loses-c 3613 arm,coresight-loses-context-with-cpu;
3643 3614
3644 out-ports { 3615 out-ports {
3645 port { 3616 port {
3646 etm1_ 3617 etm1_out: endpoint {
3647 3618 remote-endpoint =
3648 3619 <&apss_funnel_in1>;
3649 }; 3620 };
3650 }; 3621 };
3651 }; 3622 };
3652 }; 3623 };
3653 3624
3654 etm@7240000 { 3625 etm@7240000 {
3655 compatible = "arm,cor 3626 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07240000 0 3627 reg = <0 0x07240000 0 0x1000>;
3657 3628
3658 cpu = <&CPU2>; 3629 cpu = <&CPU2>;
3659 3630
3660 clocks = <&aoss_qmp>; 3631 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3632 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3633 arm,coresight-loses-context-with-cpu;
3663 3634
3664 out-ports { 3635 out-ports {
3665 port { 3636 port {
3666 etm2_ 3637 etm2_out: endpoint {
3667 3638 remote-endpoint =
3668 3639 <&apss_funnel_in2>;
3669 }; 3640 };
3670 }; 3641 };
3671 }; 3642 };
3672 }; 3643 };
3673 3644
3674 etm@7340000 { 3645 etm@7340000 {
3675 compatible = "arm,cor 3646 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 reg = <0 0x07340000 0 3647 reg = <0 0x07340000 0 0x1000>;
3677 3648
3678 cpu = <&CPU3>; 3649 cpu = <&CPU3>;
3679 3650
3680 clocks = <&aoss_qmp>; 3651 clocks = <&aoss_qmp>;
3681 clock-names = "apb_pc 3652 clock-names = "apb_pclk";
3682 arm,coresight-loses-c 3653 arm,coresight-loses-context-with-cpu;
3683 3654
3684 out-ports { 3655 out-ports {
3685 port { 3656 port {
3686 etm3_ 3657 etm3_out: endpoint {
3687 3658 remote-endpoint =
3688 3659 <&apss_funnel_in3>;
3689 }; 3660 };
3690 }; 3661 };
3691 }; 3662 };
3692 }; 3663 };
3693 3664
3694 etm@7440000 { 3665 etm@7440000 {
3695 compatible = "arm,cor 3666 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 reg = <0 0x07440000 0 3667 reg = <0 0x07440000 0 0x1000>;
3697 3668
3698 cpu = <&CPU4>; 3669 cpu = <&CPU4>;
3699 3670
3700 clocks = <&aoss_qmp>; 3671 clocks = <&aoss_qmp>;
3701 clock-names = "apb_pc 3672 clock-names = "apb_pclk";
3702 arm,coresight-loses-c 3673 arm,coresight-loses-context-with-cpu;
3703 3674
3704 out-ports { 3675 out-ports {
3705 port { 3676 port {
3706 etm4_ 3677 etm4_out: endpoint {
3707 3678 remote-endpoint =
3708 3679 <&apss_funnel_in4>;
3709 }; 3680 };
3710 }; 3681 };
3711 }; 3682 };
3712 }; 3683 };
3713 3684
3714 etm@7540000 { 3685 etm@7540000 {
3715 compatible = "arm,cor 3686 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 reg = <0 0x07540000 0 3687 reg = <0 0x07540000 0 0x1000>;
3717 3688
3718 cpu = <&CPU5>; 3689 cpu = <&CPU5>;
3719 3690
3720 clocks = <&aoss_qmp>; 3691 clocks = <&aoss_qmp>;
3721 clock-names = "apb_pc 3692 clock-names = "apb_pclk";
3722 arm,coresight-loses-c 3693 arm,coresight-loses-context-with-cpu;
3723 3694
3724 out-ports { 3695 out-ports {
3725 port { 3696 port {
3726 etm5_ 3697 etm5_out: endpoint {
3727 3698 remote-endpoint =
3728 3699 <&apss_funnel_in5>;
3729 }; 3700 };
3730 }; 3701 };
3731 }; 3702 };
3732 }; 3703 };
3733 3704
3734 etm@7640000 { 3705 etm@7640000 {
3735 compatible = "arm,cor 3706 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 reg = <0 0x07640000 0 3707 reg = <0 0x07640000 0 0x1000>;
3737 3708
3738 cpu = <&CPU6>; 3709 cpu = <&CPU6>;
3739 3710
3740 clocks = <&aoss_qmp>; 3711 clocks = <&aoss_qmp>;
3741 clock-names = "apb_pc 3712 clock-names = "apb_pclk";
3742 arm,coresight-loses-c 3713 arm,coresight-loses-context-with-cpu;
3743 3714
3744 out-ports { 3715 out-ports {
3745 port { 3716 port {
3746 etm6_ 3717 etm6_out: endpoint {
3747 3718 remote-endpoint =
3748 3719 <&apss_funnel_in6>;
3749 }; 3720 };
3750 }; 3721 };
3751 }; 3722 };
3752 }; 3723 };
3753 3724
3754 etm@7740000 { 3725 etm@7740000 {
3755 compatible = "arm,cor 3726 compatible = "arm,coresight-etm4x", "arm,primecell";
3756 reg = <0 0x07740000 0 3727 reg = <0 0x07740000 0 0x1000>;
3757 3728
3758 cpu = <&CPU7>; 3729 cpu = <&CPU7>;
3759 3730
3760 clocks = <&aoss_qmp>; 3731 clocks = <&aoss_qmp>;
3761 clock-names = "apb_pc 3732 clock-names = "apb_pclk";
3762 arm,coresight-loses-c 3733 arm,coresight-loses-context-with-cpu;
3763 3734
3764 out-ports { 3735 out-ports {
3765 port { 3736 port {
3766 etm7_ 3737 etm7_out: endpoint {
3767 3738 remote-endpoint =
3768 3739 <&apss_funnel_in7>;
3769 }; 3740 };
3770 }; 3741 };
3771 }; 3742 };
3772 }; 3743 };
3773 3744
3774 funnel@7800000 { /* APSS Funn 3745 funnel@7800000 { /* APSS Funnel */
3775 compatible = "arm,cor 3746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3776 reg = <0 0x07800000 0 3747 reg = <0 0x07800000 0 0x1000>;
3777 3748
3778 clocks = <&aoss_qmp>; 3749 clocks = <&aoss_qmp>;
3779 clock-names = "apb_pc 3750 clock-names = "apb_pclk";
3780 3751
3781 out-ports { 3752 out-ports {
3782 port { 3753 port {
3783 apss_ 3754 apss_funnel_out: endpoint {
3784 3755 remote-endpoint =
3785 3756 <&apss_merge_funnel_in>;
3786 }; 3757 };
3787 }; 3758 };
3788 }; 3759 };
3789 3760
3790 in-ports { 3761 in-ports {
3791 #address-cell 3762 #address-cells = <1>;
3792 #size-cells = 3763 #size-cells = <0>;
3793 3764
3794 port@0 { 3765 port@0 {
3795 reg = 3766 reg = <0>;
3796 apss_ 3767 apss_funnel_in0: endpoint {
3797 3768 remote-endpoint =
3798 3769 <&etm0_out>;
3799 }; 3770 };
3800 }; 3771 };
3801 3772
3802 port@1 { 3773 port@1 {
3803 reg = 3774 reg = <1>;
3804 apss_ 3775 apss_funnel_in1: endpoint {
3805 3776 remote-endpoint =
3806 3777 <&etm1_out>;
3807 }; 3778 };
3808 }; 3779 };
3809 3780
3810 port@2 { 3781 port@2 {
3811 reg = 3782 reg = <2>;
3812 apss_ 3783 apss_funnel_in2: endpoint {
3813 3784 remote-endpoint =
3814 3785 <&etm2_out>;
3815 }; 3786 };
3816 }; 3787 };
3817 3788
3818 port@3 { 3789 port@3 {
3819 reg = 3790 reg = <3>;
3820 apss_ 3791 apss_funnel_in3: endpoint {
3821 3792 remote-endpoint =
3822 3793 <&etm3_out>;
3823 }; 3794 };
3824 }; 3795 };
3825 3796
3826 port@4 { 3797 port@4 {
3827 reg = 3798 reg = <4>;
3828 apss_ 3799 apss_funnel_in4: endpoint {
3829 3800 remote-endpoint =
3830 3801 <&etm4_out>;
3831 }; 3802 };
3832 }; 3803 };
3833 3804
3834 port@5 { 3805 port@5 {
3835 reg = 3806 reg = <5>;
3836 apss_ 3807 apss_funnel_in5: endpoint {
3837 3808 remote-endpoint =
3838 3809 <&etm5_out>;
3839 }; 3810 };
3840 }; 3811 };
3841 3812
3842 port@6 { 3813 port@6 {
3843 reg = 3814 reg = <6>;
3844 apss_ 3815 apss_funnel_in6: endpoint {
3845 3816 remote-endpoint =
3846 3817 <&etm6_out>;
3847 }; 3818 };
3848 }; 3819 };
3849 3820
3850 port@7 { 3821 port@7 {
3851 reg = 3822 reg = <7>;
3852 apss_ 3823 apss_funnel_in7: endpoint {
3853 3824 remote-endpoint =
3854 3825 <&etm7_out>;
3855 }; 3826 };
3856 }; 3827 };
3857 }; 3828 };
3858 }; 3829 };
3859 3830
3860 funnel@7810000 { 3831 funnel@7810000 {
3861 compatible = "arm,cor 3832 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3862 reg = <0 0x07810000 0 3833 reg = <0 0x07810000 0 0x1000>;
3863 3834
3864 clocks = <&aoss_qmp>; 3835 clocks = <&aoss_qmp>;
3865 clock-names = "apb_pc 3836 clock-names = "apb_pclk";
3866 3837
3867 out-ports { 3838 out-ports {
3868 port { 3839 port {
3869 apss_ 3840 apss_merge_funnel_out: endpoint {
3870 3841 remote-endpoint =
3871 3842 <&funnel2_in5>;
3872 }; 3843 };
3873 }; 3844 };
3874 }; 3845 };
3875 3846
3876 in-ports { 3847 in-ports {
3877 port { 3848 port {
3878 apss_ 3849 apss_merge_funnel_in: endpoint {
3879 3850 remote-endpoint =
3880 3851 <&apss_funnel_out>;
3881 }; 3852 };
3882 }; 3853 };
3883 }; 3854 };
3884 }; 3855 };
3885 3856
3886 sdhc_2: mmc@8804000 { 3857 sdhc_2: mmc@8804000 {
3887 compatible = "qcom,sd 3858 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3888 reg = <0 0x08804000 0 3859 reg = <0 0x08804000 0 0x1000>;
3889 3860
3890 interrupts = <GIC_SPI 3861 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3891 <GIC_SPI 3862 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3892 interrupt-names = "hc 3863 interrupt-names = "hc_irq", "pwr_irq";
3893 3864
3894 clocks = <&gcc GCC_SD 3865 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3895 <&gcc GCC_SD 3866 <&gcc GCC_SDCC2_APPS_CLK>,
3896 <&rpmhcc RPM 3867 <&rpmhcc RPMH_CXO_CLK>;
3897 clock-names = "iface" 3868 clock-names = "iface", "core", "xo";
3898 iommus = <&apps_smmu 3869 iommus = <&apps_smmu 0xa0 0xf>;
3899 power-domains = <&rpm 3870 power-domains = <&rpmhpd SDM845_CX>;
3900 operating-points-v2 = 3871 operating-points-v2 = <&sdhc2_opp_table>;
3901 3872
3902 status = "disabled"; 3873 status = "disabled";
3903 3874
3904 sdhc2_opp_table: opp- 3875 sdhc2_opp_table: opp-table {
3905 compatible = 3876 compatible = "operating-points-v2";
3906 3877
3907 opp-9600000 { 3878 opp-9600000 {
3908 opp-h 3879 opp-hz = /bits/ 64 <9600000>;
3909 requi 3880 required-opps = <&rpmhpd_opp_min_svs>;
3910 }; 3881 };
3911 3882
3912 opp-19200000 3883 opp-19200000 {
3913 opp-h 3884 opp-hz = /bits/ 64 <19200000>;
3914 requi 3885 required-opps = <&rpmhpd_opp_low_svs>;
3915 }; 3886 };
3916 3887
3917 opp-100000000 3888 opp-100000000 {
3918 opp-h 3889 opp-hz = /bits/ 64 <100000000>;
3919 requi 3890 required-opps = <&rpmhpd_opp_svs>;
3920 }; 3891 };
3921 3892
3922 opp-201500000 3893 opp-201500000 {
3923 opp-h 3894 opp-hz = /bits/ 64 <201500000>;
3924 requi 3895 required-opps = <&rpmhpd_opp_svs_l1>;
3925 }; 3896 };
3926 }; 3897 };
3927 }; 3898 };
3928 3899
3929 qspi: spi@88df000 { 3900 qspi: spi@88df000 {
3930 compatible = "qcom,sd 3901 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3931 reg = <0 0x088df000 0 3902 reg = <0 0x088df000 0 0x600>;
3932 iommus = <&apps_smmu 3903 iommus = <&apps_smmu 0x160 0x0>;
3933 #address-cells = <1>; 3904 #address-cells = <1>;
3934 #size-cells = <0>; 3905 #size-cells = <0>;
3935 interrupts = <GIC_SPI 3906 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3936 clocks = <&gcc GCC_QS 3907 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3937 <&gcc GCC_QS 3908 <&gcc GCC_QSPI_CORE_CLK>;
3938 clock-names = "iface" 3909 clock-names = "iface", "core";
3939 power-domains = <&rpm 3910 power-domains = <&rpmhpd SDM845_CX>;
3940 operating-points-v2 = 3911 operating-points-v2 = <&qspi_opp_table>;
3941 status = "disabled"; 3912 status = "disabled";
3942 }; 3913 };
3943 3914
3944 slim: slim-ngd@171c0000 { 3915 slim: slim-ngd@171c0000 {
3945 compatible = "qcom,sl 3916 compatible = "qcom,slim-ngd-v2.1.0";
3946 reg = <0 0x171c0000 0 3917 reg = <0 0x171c0000 0 0x2c000>;
3947 interrupts = <GIC_SPI 3918 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
3948 3919
3949 dmas = <&slimbam 3>, 3920 dmas = <&slimbam 3>, <&slimbam 4>;
3950 dma-names = "rx", "tx 3921 dma-names = "rx", "tx";
3951 3922
3952 iommus = <&apps_smmu 3923 iommus = <&apps_smmu 0x1806 0x0>;
3953 #address-cells = <1>; 3924 #address-cells = <1>;
3954 #size-cells = <0>; 3925 #size-cells = <0>;
3955 status = "disabled"; 3926 status = "disabled";
3956 }; 3927 };
3957 3928
3958 lmh_cluster1: lmh@17d70800 { 3929 lmh_cluster1: lmh@17d70800 {
3959 compatible = "qcom,sd 3930 compatible = "qcom,sdm845-lmh";
3960 reg = <0 0x17d70800 0 3931 reg = <0 0x17d70800 0 0x400>;
3961 interrupts = <GIC_SPI 3932 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3962 cpus = <&CPU4>; 3933 cpus = <&CPU4>;
3963 qcom,lmh-temp-arm-mil 3934 qcom,lmh-temp-arm-millicelsius = <65000>;
3964 qcom,lmh-temp-low-mil 3935 qcom,lmh-temp-low-millicelsius = <94500>;
3965 qcom,lmh-temp-high-mi 3936 qcom,lmh-temp-high-millicelsius = <95000>;
3966 interrupt-controller; 3937 interrupt-controller;
3967 #interrupt-cells = <1 3938 #interrupt-cells = <1>;
3968 }; 3939 };
3969 3940
3970 lmh_cluster0: lmh@17d78800 { 3941 lmh_cluster0: lmh@17d78800 {
3971 compatible = "qcom,sd 3942 compatible = "qcom,sdm845-lmh";
3972 reg = <0 0x17d78800 0 3943 reg = <0 0x17d78800 0 0x400>;
3973 interrupts = <GIC_SPI 3944 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3974 cpus = <&CPU0>; 3945 cpus = <&CPU0>;
3975 qcom,lmh-temp-arm-mil 3946 qcom,lmh-temp-arm-millicelsius = <65000>;
3976 qcom,lmh-temp-low-mil 3947 qcom,lmh-temp-low-millicelsius = <94500>;
3977 qcom,lmh-temp-high-mi 3948 qcom,lmh-temp-high-millicelsius = <95000>;
3978 interrupt-controller; 3949 interrupt-controller;
3979 #interrupt-cells = <1 3950 #interrupt-cells = <1>;
3980 }; 3951 };
3981 3952
3982 usb_1_hsphy: phy@88e2000 { 3953 usb_1_hsphy: phy@88e2000 {
3983 compatible = "qcom,sd 3954 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3984 reg = <0 0x088e2000 0 3955 reg = <0 0x088e2000 0 0x400>;
3985 status = "disabled"; 3956 status = "disabled";
3986 #phy-cells = <0>; 3957 #phy-cells = <0>;
3987 3958
3988 clocks = <&gcc GCC_US 3959 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
3989 <&rpmhcc RPM 3960 <&rpmhcc RPMH_CXO_CLK>;
3990 clock-names = "cfg_ah 3961 clock-names = "cfg_ahb", "ref";
3991 3962
3992 resets = <&gcc GCC_QU 3963 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3993 3964
3994 nvmem-cells = <&qusb2 3965 nvmem-cells = <&qusb2p_hstx_trim>;
3995 }; 3966 };
3996 3967
3997 usb_2_hsphy: phy@88e3000 { 3968 usb_2_hsphy: phy@88e3000 {
3998 compatible = "qcom,sd 3969 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3999 reg = <0 0x088e3000 0 3970 reg = <0 0x088e3000 0 0x400>;
4000 status = "disabled"; 3971 status = "disabled";
4001 #phy-cells = <0>; 3972 #phy-cells = <0>;
4002 3973
4003 clocks = <&gcc GCC_US 3974 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4004 <&rpmhcc RPM 3975 <&rpmhcc RPMH_CXO_CLK>;
4005 clock-names = "cfg_ah 3976 clock-names = "cfg_ahb", "ref";
4006 3977
4007 resets = <&gcc GCC_QU 3978 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
4008 3979
4009 nvmem-cells = <&qusb2 3980 nvmem-cells = <&qusb2s_hstx_trim>;
4010 }; 3981 };
4011 3982
4012 usb_1_qmpphy: phy@88e8000 { !! 3983 usb_1_qmpphy: phy@88e9000 {
4013 compatible = "qcom,sd 3984 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
4014 reg = <0 0x088e8000 0 !! 3985 reg = <0 0x088e9000 0 0x18c>,
>> 3986 <0 0x088e8000 0 0x38>,
>> 3987 <0 0x088ea000 0 0x40>;
4015 status = "disabled"; 3988 status = "disabled";
>> 3989 #address-cells = <2>;
>> 3990 #size-cells = <2>;
>> 3991 ranges;
4016 3992
4017 clocks = <&gcc GCC_US 3993 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3994 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4018 <&gcc GCC_US 3995 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
4019 <&gcc GCC_US !! 3996 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
4020 <&gcc GCC_US !! 3997 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4021 <&gcc GCC_US <<
4022 clock-names = "aux", <<
4023 "ref", <<
4024 "com_au <<
4025 "usb3_p <<
4026 "cfg_ah <<
4027 3998
4028 resets = <&gcc GCC_US 3999 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
4029 <&gcc GCC_US 4000 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
4030 reset-names = "phy", 4001 reset-names = "phy", "common";
4031 4002
4032 #clock-cells = <1>; !! 4003 usb_1_ssphy: usb3-phy@88e9200 {
4033 #phy-cells = <1>; !! 4004 reg = <0 0x088e9200 0 0x128>,
4034 orientation-switch; !! 4005 <0 0x088e9400 0 0x200>,
4035 !! 4006 <0 0x088e9c00 0 0x218>,
4036 ports { !! 4007 <0 0x088e9600 0 0x128>,
4037 #address-cell !! 4008 <0 0x088e9800 0 0x200>,
4038 #size-cells = !! 4009 <0 0x088e9a00 0 0x100>;
4039 !! 4010 #clock-cells = <0>;
4040 port@0 { !! 4011 #phy-cells = <0>;
4041 reg = !! 4012 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
4042 !! 4013 clock-names = "pipe0";
4043 usb_1 !! 4014 clock-output-names = "usb3_phy_pipe_clk_src";
4044 }; !! 4015 };
4045 }; <<
4046 <<
4047 port@1 { <<
4048 reg = <<
4049 <<
4050 usb_1 <<
4051 <<
4052 }; <<
4053 }; <<
4054 <<
4055 port@2 { <<
4056 reg = <<
4057 4016
4058 usb_1 !! 4017 dp_phy: dp-phy@88ea200 {
4059 !! 4018 reg = <0 0x088ea200 0 0x200>,
4060 }; !! 4019 <0 0x088ea400 0 0x200>,
4061 }; !! 4020 <0 0x088eaa00 0 0x200>,
>> 4021 <0 0x088ea600 0 0x200>,
>> 4022 <0 0x088ea800 0 0x200>;
>> 4023 #clock-cells = <1>;
>> 4024 #phy-cells = <0>;
4062 }; 4025 };
4063 }; 4026 };
4064 4027
4065 usb_2_qmpphy: phy@88eb000 { 4028 usb_2_qmpphy: phy@88eb000 {
4066 compatible = "qcom,sd 4029 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4067 reg = <0 0x088eb000 0 !! 4030 reg = <0 0x088eb000 0 0x18c>;
>> 4031 status = "disabled";
>> 4032 #address-cells = <2>;
>> 4033 #size-cells = <2>;
>> 4034 ranges;
4068 4035
4069 clocks = <&gcc GCC_US 4036 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
4070 <&gcc GCC_US 4037 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
4071 <&gcc GCC_US 4038 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
4072 <&gcc GCC_US !! 4039 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
4073 <&gcc GCC_US !! 4040 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4074 clock-names = "aux", <<
4075 "cfg_ah <<
4076 "ref", <<
4077 "com_au <<
4078 "pipe"; <<
4079 clock-output-names = <<
4080 #clock-cells = <0>; <<
4081 #phy-cells = <0>; <<
4082 4041
4083 resets = <&gcc GCC_US !! 4042 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
4084 <&gcc GCC_US !! 4043 <&gcc GCC_USB3_PHY_SEC_BCR>;
4085 reset-names = "phy", !! 4044 reset-names = "phy", "common";
4086 "phy_ph <<
4087 4045
4088 status = "disabled"; !! 4046 usb_2_ssphy: phy@88eb200 {
>> 4047 reg = <0 0x088eb200 0 0x128>,
>> 4048 <0 0x088eb400 0 0x1fc>,
>> 4049 <0 0x088eb800 0 0x218>,
>> 4050 <0 0x088eb600 0 0x70>;
>> 4051 #clock-cells = <0>;
>> 4052 #phy-cells = <0>;
>> 4053 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 4054 clock-names = "pipe0";
>> 4055 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 4056 };
4089 }; 4057 };
4090 4058
4091 usb_1: usb@a6f8800 { 4059 usb_1: usb@a6f8800 {
4092 compatible = "qcom,sd 4060 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4093 reg = <0 0x0a6f8800 0 4061 reg = <0 0x0a6f8800 0 0x400>;
4094 status = "disabled"; 4062 status = "disabled";
4095 #address-cells = <2>; 4063 #address-cells = <2>;
4096 #size-cells = <2>; 4064 #size-cells = <2>;
4097 ranges; 4065 ranges;
4098 dma-ranges; 4066 dma-ranges;
4099 4067
4100 clocks = <&gcc GCC_CF 4068 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4101 <&gcc GCC_US 4069 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4102 <&gcc GCC_AG 4070 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4103 <&gcc GCC_US 4071 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4104 <&gcc GCC_US 4072 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
4105 clock-names = "cfg_no 4073 clock-names = "cfg_noc",
4106 "core", 4074 "core",
4107 "iface" 4075 "iface",
4108 "sleep" 4076 "sleep",
4109 "mock_u 4077 "mock_utmi";
4110 4078
4111 assigned-clocks = <&g 4079 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4112 <&g 4080 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4113 assigned-clock-rates 4081 assigned-clock-rates = <19200000>, <150000000>;
4114 4082
4115 interrupts-extended = !! 4083 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4116 !! 4084 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
4117 !! 4085 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
4118 !! 4086 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
4119 !! 4087 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4120 interrupt-names = "pw !! 4088 "dm_hs_phy_irq", "dp_hs_phy_irq";
4121 "hs <<
4122 "dp <<
4123 "dm <<
4124 "ss <<
4125 4089
4126 power-domains = <&gcc 4090 power-domains = <&gcc USB30_PRIM_GDSC>;
4127 4091
4128 resets = <&gcc GCC_US 4092 resets = <&gcc GCC_USB30_PRIM_BCR>;
4129 4093
4130 interconnects = <&agg 4094 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4131 <&gla 4095 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4132 interconnect-names = 4096 interconnect-names = "usb-ddr", "apps-usb";
4133 4097
4134 usb_1_dwc3: usb@a6000 4098 usb_1_dwc3: usb@a600000 {
4135 compatible = 4099 compatible = "snps,dwc3";
4136 reg = <0 0x0a 4100 reg = <0 0x0a600000 0 0xcd00>;
4137 interrupts = 4101 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4138 iommus = <&ap 4102 iommus = <&apps_smmu 0x740 0>;
4139 snps,dis_u2_s 4103 snps,dis_u2_susphy_quirk;
4140 snps,dis_enbl 4104 snps,dis_enblslpm_quirk;
4141 snps,parkmode !! 4105 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4142 phys = <&usb_ <<
4143 phy-names = " 4106 phy-names = "usb2-phy", "usb3-phy";
4144 <<
4145 ports { <<
4146 #addr <<
4147 #size <<
4148 <<
4149 port@ <<
4150 <<
4151 <<
4152 <<
4153 <<
4154 }; <<
4155 <<
4156 port@ <<
4157 <<
4158 <<
4159 <<
4160 <<
4161 <<
4162 }; <<
4163 }; <<
4164 }; 4107 };
4165 }; 4108 };
4166 4109
4167 usb_2: usb@a8f8800 { 4110 usb_2: usb@a8f8800 {
4168 compatible = "qcom,sd 4111 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4169 reg = <0 0x0a8f8800 0 4112 reg = <0 0x0a8f8800 0 0x400>;
4170 status = "disabled"; 4113 status = "disabled";
4171 #address-cells = <2>; 4114 #address-cells = <2>;
4172 #size-cells = <2>; 4115 #size-cells = <2>;
4173 ranges; 4116 ranges;
4174 dma-ranges; 4117 dma-ranges;
4175 4118
4176 clocks = <&gcc GCC_CF 4119 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4177 <&gcc GCC_US 4120 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4178 <&gcc GCC_AG 4121 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4179 <&gcc GCC_US 4122 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4180 <&gcc GCC_US 4123 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
4181 clock-names = "cfg_no 4124 clock-names = "cfg_noc",
4182 "core", 4125 "core",
4183 "iface" 4126 "iface",
4184 "sleep" 4127 "sleep",
4185 "mock_u 4128 "mock_utmi";
4186 4129
4187 assigned-clocks = <&g 4130 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4188 <&g 4131 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4189 assigned-clock-rates 4132 assigned-clock-rates = <19200000>, <150000000>;
4190 4133
4191 interrupts-extended = !! 4134 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4192 !! 4135 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
4193 !! 4136 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
4194 !! 4137 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
4195 !! 4138 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4196 interrupt-names = "pw !! 4139 "dm_hs_phy_irq", "dp_hs_phy_irq";
4197 "hs <<
4198 "dp <<
4199 "dm <<
4200 "ss <<
4201 4140
4202 power-domains = <&gcc 4141 power-domains = <&gcc USB30_SEC_GDSC>;
4203 4142
4204 resets = <&gcc GCC_US 4143 resets = <&gcc GCC_USB30_SEC_BCR>;
4205 4144
4206 interconnects = <&agg 4145 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4207 <&gla 4146 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4208 interconnect-names = 4147 interconnect-names = "usb-ddr", "apps-usb";
4209 4148
4210 usb_2_dwc3: usb@a8000 4149 usb_2_dwc3: usb@a800000 {
4211 compatible = 4150 compatible = "snps,dwc3";
4212 reg = <0 0x0a 4151 reg = <0 0x0a800000 0 0xcd00>;
4213 interrupts = 4152 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4214 iommus = <&ap 4153 iommus = <&apps_smmu 0x760 0>;
4215 snps,dis_u2_s 4154 snps,dis_u2_susphy_quirk;
4216 snps,dis_enbl 4155 snps,dis_enblslpm_quirk;
4217 snps,parkmode !! 4156 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4218 phys = <&usb_ <<
4219 phy-names = " 4157 phy-names = "usb2-phy", "usb3-phy";
4220 }; 4158 };
4221 }; 4159 };
4222 4160
4223 venus: video-codec@aa00000 { 4161 venus: video-codec@aa00000 {
4224 compatible = "qcom,sd 4162 compatible = "qcom,sdm845-venus-v2";
4225 reg = <0 0x0aa00000 0 4163 reg = <0 0x0aa00000 0 0xff000>;
4226 interrupts = <GIC_SPI 4164 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4227 power-domains = <&vid 4165 power-domains = <&videocc VENUS_GDSC>,
4228 <&vid 4166 <&videocc VCODEC0_GDSC>,
4229 <&vid 4167 <&videocc VCODEC1_GDSC>,
4230 <&rpm 4168 <&rpmhpd SDM845_CX>;
4231 power-domain-names = 4169 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4232 operating-points-v2 = 4170 operating-points-v2 = <&venus_opp_table>;
4233 clocks = <&videocc VI 4171 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
4234 <&videocc VI 4172 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
4235 <&videocc VI 4173 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
4236 <&videocc VI 4174 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
4237 <&videocc VI 4175 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
4238 <&videocc VI 4176 <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
4239 <&videocc VI 4177 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
4240 clock-names = "core", 4178 clock-names = "core", "iface", "bus",
4241 "vcodec 4179 "vcodec0_core", "vcodec0_bus",
4242 "vcodec 4180 "vcodec1_core", "vcodec1_bus";
4243 iommus = <&apps_smmu 4181 iommus = <&apps_smmu 0x10a0 0x8>,
4244 <&apps_smmu 4182 <&apps_smmu 0x10b0 0x0>;
4245 memory-region = <&ven 4183 memory-region = <&venus_mem>;
4246 interconnects = <&mms 4184 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4247 <&gla 4185 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4248 interconnect-names = 4186 interconnect-names = "video-mem", "cpu-cfg";
4249 4187
4250 status = "disabled"; 4188 status = "disabled";
4251 4189
4252 video-core0 { 4190 video-core0 {
4253 compatible = 4191 compatible = "venus-decoder";
4254 }; 4192 };
4255 4193
4256 video-core1 { 4194 video-core1 {
4257 compatible = 4195 compatible = "venus-encoder";
4258 }; 4196 };
4259 4197
4260 venus_opp_table: opp- 4198 venus_opp_table: opp-table {
4261 compatible = 4199 compatible = "operating-points-v2";
4262 4200
4263 opp-100000000 4201 opp-100000000 {
4264 opp-h 4202 opp-hz = /bits/ 64 <100000000>;
4265 requi 4203 required-opps = <&rpmhpd_opp_min_svs>;
4266 }; 4204 };
4267 4205
4268 opp-200000000 4206 opp-200000000 {
4269 opp-h 4207 opp-hz = /bits/ 64 <200000000>;
4270 requi 4208 required-opps = <&rpmhpd_opp_low_svs>;
4271 }; 4209 };
4272 4210
4273 opp-320000000 4211 opp-320000000 {
4274 opp-h 4212 opp-hz = /bits/ 64 <320000000>;
4275 requi 4213 required-opps = <&rpmhpd_opp_svs>;
4276 }; 4214 };
4277 4215
4278 opp-380000000 4216 opp-380000000 {
4279 opp-h 4217 opp-hz = /bits/ 64 <380000000>;
4280 requi 4218 required-opps = <&rpmhpd_opp_svs_l1>;
4281 }; 4219 };
4282 4220
4283 opp-444000000 4221 opp-444000000 {
4284 opp-h 4222 opp-hz = /bits/ 64 <444000000>;
4285 requi 4223 required-opps = <&rpmhpd_opp_nom>;
4286 }; 4224 };
4287 4225
4288 opp-533000097 4226 opp-533000097 {
4289 opp-h 4227 opp-hz = /bits/ 64 <533000097>;
4290 requi 4228 required-opps = <&rpmhpd_opp_turbo>;
4291 }; 4229 };
4292 }; 4230 };
4293 }; 4231 };
4294 4232
4295 videocc: clock-controller@ab0 4233 videocc: clock-controller@ab00000 {
4296 compatible = "qcom,sd 4234 compatible = "qcom,sdm845-videocc";
4297 reg = <0 0x0ab00000 0 4235 reg = <0 0x0ab00000 0 0x10000>;
4298 clocks = <&rpmhcc RPM 4236 clocks = <&rpmhcc RPMH_CXO_CLK>;
4299 clock-names = "bi_tcx 4237 clock-names = "bi_tcxo";
4300 #clock-cells = <1>; 4238 #clock-cells = <1>;
4301 #power-domain-cells = 4239 #power-domain-cells = <1>;
4302 #reset-cells = <1>; 4240 #reset-cells = <1>;
4303 }; 4241 };
4304 4242
4305 camss: camss@acb3000 { 4243 camss: camss@acb3000 {
4306 compatible = "qcom,sd 4244 compatible = "qcom,sdm845-camss";
4307 4245
4308 reg = <0 0x0acb3000 0 4246 reg = <0 0x0acb3000 0 0x1000>,
4309 <0 0x0acba000 4247 <0 0x0acba000 0 0x1000>,
4310 <0 0x0acc8000 4248 <0 0x0acc8000 0 0x1000>,
4311 <0 0x0ac65000 4249 <0 0x0ac65000 0 0x1000>,
4312 <0 0x0ac66000 4250 <0 0x0ac66000 0 0x1000>,
4313 <0 0x0ac67000 4251 <0 0x0ac67000 0 0x1000>,
4314 <0 0x0ac68000 4252 <0 0x0ac68000 0 0x1000>,
4315 <0 0x0acaf000 4253 <0 0x0acaf000 0 0x4000>,
4316 <0 0x0acb6000 4254 <0 0x0acb6000 0 0x4000>,
4317 <0 0x0acc4000 4255 <0 0x0acc4000 0 0x4000>;
4318 reg-names = "csid0", 4256 reg-names = "csid0",
4319 "csid1", 4257 "csid1",
4320 "csid2", 4258 "csid2",
4321 "csiphy0", 4259 "csiphy0",
4322 "csiphy1", 4260 "csiphy1",
4323 "csiphy2", 4261 "csiphy2",
4324 "csiphy3", 4262 "csiphy3",
4325 "vfe0", 4263 "vfe0",
4326 "vfe1", 4264 "vfe1",
4327 "vfe_lite"; 4265 "vfe_lite";
4328 4266
4329 interrupts = <GIC_SPI 4267 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4330 <GIC_SPI 466 4268 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4331 <GIC_SPI 468 4269 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4332 <GIC_SPI 477 4270 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4333 <GIC_SPI 478 4271 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4334 <GIC_SPI 479 4272 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4335 <GIC_SPI 448 4273 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4336 <GIC_SPI 465 4274 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4337 <GIC_SPI 467 4275 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4338 <GIC_SPI 469 4276 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
4339 interrupt-names = "cs 4277 interrupt-names = "csid0",
4340 "csid1", 4278 "csid1",
4341 "csid2", 4279 "csid2",
4342 "csiphy0", 4280 "csiphy0",
4343 "csiphy1", 4281 "csiphy1",
4344 "csiphy2", 4282 "csiphy2",
4345 "csiphy3", 4283 "csiphy3",
4346 "vfe0", 4284 "vfe0",
4347 "vfe1", 4285 "vfe1",
4348 "vfe_lite"; 4286 "vfe_lite";
4349 4287
4350 power-domains = <&clo 4288 power-domains = <&clock_camcc IFE_0_GDSC>,
4351 <&clock_camcc 4289 <&clock_camcc IFE_1_GDSC>,
4352 <&clock_camcc 4290 <&clock_camcc TITAN_TOP_GDSC>;
4353 4291
4354 clocks = <&clock_camc 4292 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4355 <&clock_camcc 4293 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4356 <&clock_camcc 4294 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
4357 <&clock_camcc 4295 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
4358 <&clock_camcc 4296 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
4359 <&clock_camcc 4297 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
4360 <&clock_camcc 4298 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
4361 <&clock_camcc 4299 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
4362 <&clock_camcc 4300 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
4363 <&clock_camcc 4301 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
4364 <&clock_camcc 4302 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
4365 <&clock_camcc 4303 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
4366 <&clock_camcc 4304 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
4367 <&clock_camcc 4305 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
4368 <&clock_camcc 4306 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
4369 <&clock_camcc 4307 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
4370 <&clock_camcc 4308 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
4371 <&clock_camcc 4309 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
4372 <&clock_camcc 4310 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
4373 <&clock_camcc 4311 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
4374 <&clock_camcc 4312 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
4375 <&gcc GCC_CAM 4313 <&gcc GCC_CAMERA_AHB_CLK>,
4376 <&gcc GCC_CAM 4314 <&gcc GCC_CAMERA_AXI_CLK>,
4377 <&clock_camcc 4315 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4378 <&clock_camcc 4316 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4379 <&clock_camcc 4317 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
4380 <&clock_camcc 4318 <&clock_camcc CAM_CC_IFE_0_CLK>,
4381 <&clock_camcc 4319 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4382 <&clock_camcc 4320 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
4383 <&clock_camcc 4321 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
4384 <&clock_camcc 4322 <&clock_camcc CAM_CC_IFE_1_CLK>,
4385 <&clock_camcc 4323 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4386 <&clock_camcc 4324 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
4387 <&clock_camcc 4325 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
4388 <&clock_camcc 4326 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4389 <&clock_camcc 4327 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
4390 clock-names = "camnoc 4328 clock-names = "camnoc_axi",
4391 "cpas_ahb", 4329 "cpas_ahb",
4392 "cphy_rx_src" 4330 "cphy_rx_src",
4393 "csi0", 4331 "csi0",
4394 "csi0_src", 4332 "csi0_src",
4395 "csi1", 4333 "csi1",
4396 "csi1_src", 4334 "csi1_src",
4397 "csi2", 4335 "csi2",
4398 "csi2_src", 4336 "csi2_src",
4399 "csiphy0", 4337 "csiphy0",
4400 "csiphy0_time 4338 "csiphy0_timer",
4401 "csiphy0_time 4339 "csiphy0_timer_src",
4402 "csiphy1", 4340 "csiphy1",
4403 "csiphy1_time 4341 "csiphy1_timer",
4404 "csiphy1_time 4342 "csiphy1_timer_src",
4405 "csiphy2", 4343 "csiphy2",
4406 "csiphy2_time 4344 "csiphy2_timer",
4407 "csiphy2_time 4345 "csiphy2_timer_src",
4408 "csiphy3", 4346 "csiphy3",
4409 "csiphy3_time 4347 "csiphy3_timer",
4410 "csiphy3_time 4348 "csiphy3_timer_src",
4411 "gcc_camera_a 4349 "gcc_camera_ahb",
4412 "gcc_camera_a 4350 "gcc_camera_axi",
4413 "slow_ahb_src 4351 "slow_ahb_src",
4414 "soc_ahb", 4352 "soc_ahb",
4415 "vfe0_axi", 4353 "vfe0_axi",
4416 "vfe0", 4354 "vfe0",
4417 "vfe0_cphy_rx 4355 "vfe0_cphy_rx",
4418 "vfe0_src", 4356 "vfe0_src",
4419 "vfe1_axi", 4357 "vfe1_axi",
4420 "vfe1", 4358 "vfe1",
4421 "vfe1_cphy_rx 4359 "vfe1_cphy_rx",
4422 "vfe1_src", 4360 "vfe1_src",
4423 "vfe_lite", 4361 "vfe_lite",
4424 "vfe_lite_cph 4362 "vfe_lite_cphy_rx",
4425 "vfe_lite_src 4363 "vfe_lite_src";
4426 4364
4427 iommus = <&apps_smmu 4365 iommus = <&apps_smmu 0x0808 0x0>,
4428 <&apps_smmu 4366 <&apps_smmu 0x0810 0x8>,
4429 <&apps_smmu 4367 <&apps_smmu 0x0c08 0x0>,
4430 <&apps_smmu 4368 <&apps_smmu 0x0c10 0x8>;
4431 4369
4432 status = "disabled"; 4370 status = "disabled";
4433 4371
4434 ports { 4372 ports {
4435 #address-cell 4373 #address-cells = <1>;
4436 #size-cells = 4374 #size-cells = <0>;
4437 4375
4438 port@0 { 4376 port@0 {
4439 reg = 4377 reg = <0>;
4440 }; 4378 };
4441 4379
4442 port@1 { 4380 port@1 {
4443 reg = 4381 reg = <1>;
4444 }; 4382 };
4445 4383
4446 port@2 { 4384 port@2 {
4447 reg = 4385 reg = <2>;
4448 }; 4386 };
4449 4387
4450 port@3 { 4388 port@3 {
4451 reg = 4389 reg = <3>;
4452 }; 4390 };
4453 }; 4391 };
4454 }; 4392 };
4455 4393
4456 cci: cci@ac4a000 { 4394 cci: cci@ac4a000 {
4457 compatible = "qcom,sd 4395 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4458 #address-cells = <1>; 4396 #address-cells = <1>;
4459 #size-cells = <0>; 4397 #size-cells = <0>;
4460 4398
4461 reg = <0 0x0ac4a000 0 4399 reg = <0 0x0ac4a000 0 0x4000>;
4462 interrupts = <GIC_SPI 4400 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4463 power-domains = <&clo 4401 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4464 4402
4465 clocks = <&clock_camc 4403 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4466 <&clock_camcc 4404 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
4467 <&clock_camcc 4405 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4468 <&clock_camcc 4406 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
4469 <&clock_camcc 4407 <&clock_camcc CAM_CC_CCI_CLK>,
4470 <&clock_camcc 4408 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
4471 clock-names = "camnoc 4409 clock-names = "camnoc_axi",
4472 "soc_ahb", 4410 "soc_ahb",
4473 "slow_ahb_src 4411 "slow_ahb_src",
4474 "cpas_ahb", 4412 "cpas_ahb",
4475 "cci", 4413 "cci",
4476 "cci_src"; 4414 "cci_src";
4477 4415
4478 assigned-clocks = <&c 4416 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4479 <&clock_camcc 4417 <&clock_camcc CAM_CC_CCI_CLK>;
4480 assigned-clock-rates 4418 assigned-clock-rates = <80000000>, <37500000>;
4481 4419
4482 pinctrl-names = "defa 4420 pinctrl-names = "default", "sleep";
4483 pinctrl-0 = <&cci0_de 4421 pinctrl-0 = <&cci0_default &cci1_default>;
4484 pinctrl-1 = <&cci0_sl 4422 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4485 4423
4486 status = "disabled"; 4424 status = "disabled";
4487 4425
4488 cci_i2c0: i2c-bus@0 { 4426 cci_i2c0: i2c-bus@0 {
4489 reg = <0>; 4427 reg = <0>;
4490 clock-frequen 4428 clock-frequency = <1000000>;
4491 #address-cell 4429 #address-cells = <1>;
4492 #size-cells = 4430 #size-cells = <0>;
4493 }; 4431 };
4494 4432
4495 cci_i2c1: i2c-bus@1 { 4433 cci_i2c1: i2c-bus@1 {
4496 reg = <1>; 4434 reg = <1>;
4497 clock-frequen 4435 clock-frequency = <1000000>;
4498 #address-cell 4436 #address-cells = <1>;
4499 #size-cells = 4437 #size-cells = <0>;
4500 }; 4438 };
4501 }; 4439 };
4502 4440
4503 clock_camcc: clock-controller 4441 clock_camcc: clock-controller@ad00000 {
4504 compatible = "qcom,sd 4442 compatible = "qcom,sdm845-camcc";
4505 reg = <0 0x0ad00000 0 4443 reg = <0 0x0ad00000 0 0x10000>;
4506 #clock-cells = <1>; 4444 #clock-cells = <1>;
4507 #reset-cells = <1>; 4445 #reset-cells = <1>;
4508 #power-domain-cells = 4446 #power-domain-cells = <1>;
4509 clocks = <&rpmhcc RPM 4447 clocks = <&rpmhcc RPMH_CXO_CLK>;
4510 clock-names = "bi_tcx 4448 clock-names = "bi_tcxo";
4511 }; 4449 };
4512 4450
4513 mdss: display-subsystem@ae000 4451 mdss: display-subsystem@ae00000 {
4514 compatible = "qcom,sd 4452 compatible = "qcom,sdm845-mdss";
4515 reg = <0 0x0ae00000 0 4453 reg = <0 0x0ae00000 0 0x1000>;
4516 reg-names = "mdss"; 4454 reg-names = "mdss";
4517 4455
4518 power-domains = <&dis 4456 power-domains = <&dispcc MDSS_GDSC>;
4519 4457
4520 clocks = <&dispcc DIS 4458 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4521 <&dispcc DIS 4459 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4522 clock-names = "iface" 4460 clock-names = "iface", "core";
4523 4461
4524 interrupts = <GIC_SPI 4462 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4525 interrupt-controller; 4463 interrupt-controller;
4526 #interrupt-cells = <1 4464 #interrupt-cells = <1>;
4527 4465
4528 interconnects = <&mms 4466 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4529 <&mms 4467 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4530 interconnect-names = 4468 interconnect-names = "mdp0-mem", "mdp1-mem";
4531 4469
4532 iommus = <&apps_smmu 4470 iommus = <&apps_smmu 0x880 0x8>,
4533 <&apps_smmu 4471 <&apps_smmu 0xc80 0x8>;
4534 4472
4535 status = "disabled"; 4473 status = "disabled";
4536 4474
4537 #address-cells = <2>; 4475 #address-cells = <2>;
4538 #size-cells = <2>; 4476 #size-cells = <2>;
4539 ranges; 4477 ranges;
4540 4478
4541 mdss_mdp: display-con 4479 mdss_mdp: display-controller@ae01000 {
4542 compatible = 4480 compatible = "qcom,sdm845-dpu";
4543 reg = <0 0x0a 4481 reg = <0 0x0ae01000 0 0x8f000>,
4544 <0 0x0a 4482 <0 0x0aeb0000 0 0x2008>;
4545 reg-names = " 4483 reg-names = "mdp", "vbif";
4546 4484
4547 clocks = <&gc 4485 clocks = <&gcc GCC_DISP_AXI_CLK>,
4548 <&di 4486 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4549 <&di 4487 <&dispcc DISP_CC_MDSS_AXI_CLK>,
4550 <&di 4488 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4551 <&di 4489 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4552 clock-names = 4490 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4553 4491
4554 assigned-cloc 4492 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4555 assigned-cloc 4493 assigned-clock-rates = <19200000>;
4556 operating-poi 4494 operating-points-v2 = <&mdp_opp_table>;
4557 power-domains 4495 power-domains = <&rpmhpd SDM845_CX>;
4558 4496
4559 interrupt-par 4497 interrupt-parent = <&mdss>;
4560 interrupts = 4498 interrupts = <0>;
4561 4499
4562 ports { 4500 ports {
4563 #addr 4501 #address-cells = <1>;
4564 #size 4502 #size-cells = <0>;
4565 4503
4566 port@ 4504 port@0 {
4567 4505 reg = <0>;
4568 4506 dpu_intf0_out: endpoint {
4569 4507 remote-endpoint = <&dp_in>;
4570 4508 };
4571 }; 4509 };
4572 4510
4573 port@ 4511 port@1 {
4574 4512 reg = <1>;
4575 4513 dpu_intf1_out: endpoint {
4576 4514 remote-endpoint = <&mdss_dsi0_in>;
4577 4515 };
4578 }; 4516 };
4579 4517
4580 port@ 4518 port@2 {
4581 4519 reg = <2>;
4582 4520 dpu_intf2_out: endpoint {
4583 4521 remote-endpoint = <&mdss_dsi1_in>;
4584 4522 };
4585 }; 4523 };
4586 }; 4524 };
4587 4525
4588 mdp_opp_table 4526 mdp_opp_table: opp-table {
4589 compa 4527 compatible = "operating-points-v2";
4590 4528
4591 opp-1 4529 opp-19200000 {
4592 4530 opp-hz = /bits/ 64 <19200000>;
4593 4531 required-opps = <&rpmhpd_opp_min_svs>;
4594 }; 4532 };
4595 4533
4596 opp-1 4534 opp-171428571 {
4597 4535 opp-hz = /bits/ 64 <171428571>;
4598 4536 required-opps = <&rpmhpd_opp_low_svs>;
4599 }; 4537 };
4600 4538
4601 opp-3 4539 opp-344000000 {
4602 4540 opp-hz = /bits/ 64 <344000000>;
4603 4541 required-opps = <&rpmhpd_opp_svs_l1>;
4604 }; 4542 };
4605 4543
4606 opp-4 4544 opp-430000000 {
4607 4545 opp-hz = /bits/ 64 <430000000>;
4608 4546 required-opps = <&rpmhpd_opp_nom>;
4609 }; 4547 };
4610 }; 4548 };
4611 }; 4549 };
4612 4550
4613 mdss_dp: displayport- 4551 mdss_dp: displayport-controller@ae90000 {
4614 status = "dis 4552 status = "disabled";
4615 compatible = 4553 compatible = "qcom,sdm845-dp";
4616 4554
4617 reg = <0 0x0a 4555 reg = <0 0x0ae90000 0 0x200>,
4618 <0 0x0a 4556 <0 0x0ae90200 0 0x200>,
4619 <0 0x0a 4557 <0 0x0ae90400 0 0x600>,
4620 <0 0x0a 4558 <0 0x0ae90a00 0 0x600>,
4621 <0 0x0a 4559 <0 0x0ae91000 0 0x600>;
4622 4560
4623 interrupt-par 4561 interrupt-parent = <&mdss>;
4624 interrupts = 4562 interrupts = <12>;
4625 4563
4626 clocks = <&di 4564 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4627 <&di 4565 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4628 <&di 4566 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4629 <&di 4567 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4630 <&di 4568 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4631 clock-names = 4569 clock-names = "core_iface", "core_aux", "ctrl_link",
4632 4570 "ctrl_link_iface", "stream_pixel";
4633 assigned-cloc 4571 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4634 4572 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4635 assigned-cloc !! 4573 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4636 !! 4574 phys = <&dp_phy>;
4637 phys = <&usb_ <<
4638 phy-names = " 4575 phy-names = "dp";
4639 4576
4640 operating-poi 4577 operating-points-v2 = <&dp_opp_table>;
4641 power-domains 4578 power-domains = <&rpmhpd SDM845_CX>;
4642 4579
4643 ports { 4580 ports {
4644 #addr 4581 #address-cells = <1>;
4645 #size 4582 #size-cells = <0>;
4646 port@ 4583 port@0 {
4647 4584 reg = <0>;
4648 4585 dp_in: endpoint {
4649 4586 remote-endpoint = <&dpu_intf0_out>;
4650 4587 };
4651 }; 4588 };
4652 4589
4653 port@ 4590 port@1 {
4654 4591 reg = <1>;
4655 !! 4592 dp_out: endpoint { };
4656 <<
4657 <<
4658 }; 4593 };
4659 }; 4594 };
4660 4595
4661 dp_opp_table: 4596 dp_opp_table: opp-table {
4662 compa 4597 compatible = "operating-points-v2";
4663 4598
4664 opp-1 4599 opp-162000000 {
4665 4600 opp-hz = /bits/ 64 <162000000>;
4666 4601 required-opps = <&rpmhpd_opp_low_svs>;
4667 }; 4602 };
4668 4603
4669 opp-2 4604 opp-270000000 {
4670 4605 opp-hz = /bits/ 64 <270000000>;
4671 4606 required-opps = <&rpmhpd_opp_svs>;
4672 }; 4607 };
4673 4608
4674 opp-5 4609 opp-540000000 {
4675 4610 opp-hz = /bits/ 64 <540000000>;
4676 4611 required-opps = <&rpmhpd_opp_svs_l1>;
4677 }; 4612 };
4678 4613
4679 opp-8 4614 opp-810000000 {
4680 4615 opp-hz = /bits/ 64 <810000000>;
4681 4616 required-opps = <&rpmhpd_opp_nom>;
4682 }; 4617 };
4683 }; 4618 };
4684 }; 4619 };
4685 4620
4686 mdss_dsi0: dsi@ae9400 4621 mdss_dsi0: dsi@ae94000 {
4687 compatible = 4622 compatible = "qcom,sdm845-dsi-ctrl",
4688 4623 "qcom,mdss-dsi-ctrl";
4689 reg = <0 0x0a 4624 reg = <0 0x0ae94000 0 0x400>;
4690 reg-names = " 4625 reg-names = "dsi_ctrl";
4691 4626
4692 interrupt-par 4627 interrupt-parent = <&mdss>;
4693 interrupts = 4628 interrupts = <4>;
4694 4629
4695 clocks = <&di 4630 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4696 <&di 4631 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4697 <&di 4632 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4698 <&di 4633 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4699 <&di 4634 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4700 <&di 4635 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4701 clock-names = 4636 clock-names = "byte",
4702 4637 "byte_intf",
4703 4638 "pixel",
4704 4639 "core",
4705 4640 "iface",
4706 4641 "bus";
4707 assigned-cloc 4642 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4708 assigned-cloc 4643 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4709 4644
4710 operating-poi 4645 operating-points-v2 = <&dsi_opp_table>;
4711 power-domains 4646 power-domains = <&rpmhpd SDM845_CX>;
4712 4647
4713 phys = <&mdss 4648 phys = <&mdss_dsi0_phy>;
4714 4649
4715 status = "dis 4650 status = "disabled";
4716 4651
4717 #address-cell 4652 #address-cells = <1>;
4718 #size-cells = 4653 #size-cells = <0>;
4719 4654
4720 ports { 4655 ports {
4721 #addr 4656 #address-cells = <1>;
4722 #size 4657 #size-cells = <0>;
4723 4658
4724 port@ 4659 port@0 {
4725 4660 reg = <0>;
4726 4661 mdss_dsi0_in: endpoint {
4727 4662 remote-endpoint = <&dpu_intf1_out>;
4728 4663 };
4729 }; 4664 };
4730 4665
4731 port@ 4666 port@1 {
4732 4667 reg = <1>;
4733 4668 mdss_dsi0_out: endpoint {
4734 4669 };
4735 }; 4670 };
4736 }; 4671 };
4737 }; 4672 };
4738 4673
4739 mdss_dsi0_phy: phy@ae 4674 mdss_dsi0_phy: phy@ae94400 {
4740 compatible = 4675 compatible = "qcom,dsi-phy-10nm";
4741 reg = <0 0x0a 4676 reg = <0 0x0ae94400 0 0x200>,
4742 <0 0x0a 4677 <0 0x0ae94600 0 0x280>,
4743 <0 0x0a 4678 <0 0x0ae94a00 0 0x1e0>;
4744 reg-names = " 4679 reg-names = "dsi_phy",
4745 " 4680 "dsi_phy_lane",
4746 " 4681 "dsi_pll";
4747 4682
4748 #clock-cells 4683 #clock-cells = <1>;
4749 #phy-cells = 4684 #phy-cells = <0>;
4750 4685
4751 clocks = <&di 4686 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4752 <&rp 4687 <&rpmhcc RPMH_CXO_CLK>;
4753 clock-names = 4688 clock-names = "iface", "ref";
4754 4689
4755 status = "dis 4690 status = "disabled";
4756 }; 4691 };
4757 4692
4758 mdss_dsi1: dsi@ae9600 4693 mdss_dsi1: dsi@ae96000 {
4759 compatible = 4694 compatible = "qcom,sdm845-dsi-ctrl",
4760 4695 "qcom,mdss-dsi-ctrl";
4761 reg = <0 0x0a 4696 reg = <0 0x0ae96000 0 0x400>;
4762 reg-names = " 4697 reg-names = "dsi_ctrl";
4763 4698
4764 interrupt-par 4699 interrupt-parent = <&mdss>;
4765 interrupts = 4700 interrupts = <5>;
4766 4701
4767 clocks = <&di 4702 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4768 <&di 4703 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4769 <&di 4704 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4770 <&di 4705 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4771 <&di 4706 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4772 <&di 4707 <&dispcc DISP_CC_MDSS_AXI_CLK>;
4773 clock-names = 4708 clock-names = "byte",
4774 4709 "byte_intf",
4775 4710 "pixel",
4776 4711 "core",
4777 4712 "iface",
4778 4713 "bus";
4779 assigned-cloc 4714 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4780 assigned-cloc 4715 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4781 4716
4782 operating-poi 4717 operating-points-v2 = <&dsi_opp_table>;
4783 power-domains 4718 power-domains = <&rpmhpd SDM845_CX>;
4784 4719
4785 phys = <&mdss 4720 phys = <&mdss_dsi1_phy>;
4786 4721
4787 status = "dis 4722 status = "disabled";
4788 4723
4789 #address-cell 4724 #address-cells = <1>;
4790 #size-cells = 4725 #size-cells = <0>;
4791 4726
4792 ports { 4727 ports {
4793 #addr 4728 #address-cells = <1>;
4794 #size 4729 #size-cells = <0>;
4795 4730
4796 port@ 4731 port@0 {
4797 4732 reg = <0>;
4798 4733 mdss_dsi1_in: endpoint {
4799 4734 remote-endpoint = <&dpu_intf2_out>;
4800 4735 };
4801 }; 4736 };
4802 4737
4803 port@ 4738 port@1 {
4804 4739 reg = <1>;
4805 4740 mdss_dsi1_out: endpoint {
4806 4741 };
4807 }; 4742 };
4808 }; 4743 };
4809 }; 4744 };
4810 4745
4811 mdss_dsi1_phy: phy@ae 4746 mdss_dsi1_phy: phy@ae96400 {
4812 compatible = 4747 compatible = "qcom,dsi-phy-10nm";
4813 reg = <0 0x0a 4748 reg = <0 0x0ae96400 0 0x200>,
4814 <0 0x0a 4749 <0 0x0ae96600 0 0x280>,
4815 <0 0x0a 4750 <0 0x0ae96a00 0 0x10e>;
4816 reg-names = " 4751 reg-names = "dsi_phy",
4817 " 4752 "dsi_phy_lane",
4818 " 4753 "dsi_pll";
4819 4754
4820 #clock-cells 4755 #clock-cells = <1>;
4821 #phy-cells = 4756 #phy-cells = <0>;
4822 4757
4823 clocks = <&di 4758 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4824 <&rp 4759 <&rpmhcc RPMH_CXO_CLK>;
4825 clock-names = 4760 clock-names = "iface", "ref";
4826 4761
4827 status = "dis 4762 status = "disabled";
4828 }; 4763 };
4829 }; 4764 };
4830 4765
4831 gpu: gpu@5000000 { 4766 gpu: gpu@5000000 {
4832 compatible = "qcom,ad 4767 compatible = "qcom,adreno-630.2", "qcom,adreno";
4833 4768
4834 reg = <0 0x05000000 0 4769 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4835 reg-names = "kgsl_3d0 4770 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4836 4771
4837 /* 4772 /*
4838 * Look ma, no clocks 4773 * Look ma, no clocks! The GPU clocks and power are
4839 * controlled entirel 4774 * controlled entirely by the GMU
4840 */ 4775 */
4841 4776
4842 interrupts = <GIC_SPI 4777 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
4843 4778
4844 iommus = <&adreno_smm 4779 iommus = <&adreno_smmu 0>;
4845 4780
4846 operating-points-v2 = 4781 operating-points-v2 = <&gpu_opp_table>;
4847 4782
4848 qcom,gmu = <&gmu>; 4783 qcom,gmu = <&gmu>;
4849 #cooling-cells = <2>; <<
4850 4784
4851 interconnects = <&mem 4785 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4852 interconnect-names = 4786 interconnect-names = "gfx-mem";
4853 4787
4854 status = "disabled"; 4788 status = "disabled";
4855 4789
4856 gpu_opp_table: opp-ta 4790 gpu_opp_table: opp-table {
4857 compatible = 4791 compatible = "operating-points-v2";
4858 4792
4859 opp-710000000 4793 opp-710000000 {
4860 opp-h 4794 opp-hz = /bits/ 64 <710000000>;
4861 opp-l 4795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4862 opp-p 4796 opp-peak-kBps = <7216000>;
4863 }; 4797 };
4864 4798
4865 opp-675000000 4799 opp-675000000 {
4866 opp-h 4800 opp-hz = /bits/ 64 <675000000>;
4867 opp-l 4801 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4868 opp-p 4802 opp-peak-kBps = <7216000>;
4869 }; 4803 };
4870 4804
4871 opp-596000000 4805 opp-596000000 {
4872 opp-h 4806 opp-hz = /bits/ 64 <596000000>;
4873 opp-l 4807 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4874 opp-p 4808 opp-peak-kBps = <6220000>;
4875 }; 4809 };
4876 4810
4877 opp-520000000 4811 opp-520000000 {
4878 opp-h 4812 opp-hz = /bits/ 64 <520000000>;
4879 opp-l 4813 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4880 opp-p 4814 opp-peak-kBps = <6220000>;
4881 }; 4815 };
4882 4816
4883 opp-414000000 4817 opp-414000000 {
4884 opp-h 4818 opp-hz = /bits/ 64 <414000000>;
4885 opp-l 4819 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4886 opp-p 4820 opp-peak-kBps = <4068000>;
4887 }; 4821 };
4888 4822
4889 opp-342000000 4823 opp-342000000 {
4890 opp-h 4824 opp-hz = /bits/ 64 <342000000>;
4891 opp-l 4825 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4892 opp-p 4826 opp-peak-kBps = <2724000>;
4893 }; 4827 };
4894 4828
4895 opp-257000000 4829 opp-257000000 {
4896 opp-h 4830 opp-hz = /bits/ 64 <257000000>;
4897 opp-l 4831 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4898 opp-p 4832 opp-peak-kBps = <1648000>;
4899 }; 4833 };
4900 }; 4834 };
4901 }; 4835 };
4902 4836
4903 adreno_smmu: iommu@5040000 { 4837 adreno_smmu: iommu@5040000 {
4904 compatible = "qcom,sd 4838 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4905 reg = <0 0x05040000 0 4839 reg = <0 0x05040000 0 0x10000>;
4906 #iommu-cells = <1>; 4840 #iommu-cells = <1>;
4907 #global-interrupts = 4841 #global-interrupts = <2>;
4908 interrupts = <GIC_SPI 4842 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
4909 <GIC_SPI 4843 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
4910 <GIC_SPI 4844 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
4911 <GIC_SPI 4845 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
4912 <GIC_SPI 4846 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
4913 <GIC_SPI 4847 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
4914 <GIC_SPI 4848 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
4915 <GIC_SPI 4849 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
4916 <GIC_SPI 4850 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
4917 <GIC_SPI 4851 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
4918 clocks = <&gcc GCC_GP 4852 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4919 <&gcc GCC_GP 4853 <&gcc GCC_GPU_CFG_AHB_CLK>;
4920 clock-names = "bus", 4854 clock-names = "bus", "iface";
4921 4855
4922 power-domains = <&gpu 4856 power-domains = <&gpucc GPU_CX_GDSC>;
4923 }; 4857 };
4924 4858
4925 gmu: gmu@506a000 { 4859 gmu: gmu@506a000 {
4926 compatible = "qcom,ad 4860 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4927 4861
4928 reg = <0 0x0506a000 0 4862 reg = <0 0x0506a000 0 0x30000>,
4929 <0 0x0b280000 0 4863 <0 0x0b280000 0 0x10000>,
4930 <0 0x0b480000 0 4864 <0 0x0b480000 0 0x10000>;
4931 reg-names = "gmu", "g 4865 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4932 4866
4933 interrupts = <GIC_SPI 4867 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4934 <GIC_SPI 4868 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4935 interrupt-names = "hf 4869 interrupt-names = "hfi", "gmu";
4936 4870
4937 clocks = <&gpucc GPU_ 4871 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
4938 <&gpucc GPU_ 4872 <&gpucc GPU_CC_CXO_CLK>,
4939 <&gcc GCC_DD 4873 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4940 <&gcc GCC_GP 4874 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
4941 clock-names = "gmu", 4875 clock-names = "gmu", "cxo", "axi", "memnoc";
4942 4876
4943 power-domains = <&gpu 4877 power-domains = <&gpucc GPU_CX_GDSC>,
4944 <&gpu 4878 <&gpucc GPU_GX_GDSC>;
4945 power-domain-names = 4879 power-domain-names = "cx", "gx";
4946 4880
4947 iommus = <&adreno_smm 4881 iommus = <&adreno_smmu 5>;
4948 4882
4949 operating-points-v2 = 4883 operating-points-v2 = <&gmu_opp_table>;
4950 4884
4951 status = "disabled"; 4885 status = "disabled";
4952 4886
4953 gmu_opp_table: opp-ta 4887 gmu_opp_table: opp-table {
4954 compatible = 4888 compatible = "operating-points-v2";
4955 4889
4956 opp-400000000 4890 opp-400000000 {
4957 opp-h 4891 opp-hz = /bits/ 64 <400000000>;
4958 opp-l 4892 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4959 }; 4893 };
4960 4894
4961 opp-200000000 4895 opp-200000000 {
4962 opp-h 4896 opp-hz = /bits/ 64 <200000000>;
4963 opp-l 4897 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4964 }; 4898 };
4965 }; 4899 };
4966 }; 4900 };
4967 4901
4968 dispcc: clock-controller@af00 4902 dispcc: clock-controller@af00000 {
4969 compatible = "qcom,sd 4903 compatible = "qcom,sdm845-dispcc";
4970 reg = <0 0x0af00000 0 4904 reg = <0 0x0af00000 0 0x10000>;
4971 clocks = <&rpmhcc RPM 4905 clocks = <&rpmhcc RPMH_CXO_CLK>,
4972 <&gcc GCC_DI 4906 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
4973 <&gcc GCC_DI 4907 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
4974 <&mdss_dsi0_ 4908 <&mdss_dsi0_phy 0>,
4975 <&mdss_dsi0_ 4909 <&mdss_dsi0_phy 1>,
4976 <&mdss_dsi1_ 4910 <&mdss_dsi1_phy 0>,
4977 <&mdss_dsi1_ 4911 <&mdss_dsi1_phy 1>,
4978 <&usb_1_qmpp !! 4912 <&dp_phy 0>,
4979 <&usb_1_qmpp !! 4913 <&dp_phy 1>;
4980 clock-names = "bi_tcx 4914 clock-names = "bi_tcxo",
4981 "gcc_di 4915 "gcc_disp_gpll0_clk_src",
4982 "gcc_di 4916 "gcc_disp_gpll0_div_clk_src",
4983 "dsi0_p 4917 "dsi0_phy_pll_out_byteclk",
4984 "dsi0_p 4918 "dsi0_phy_pll_out_dsiclk",
4985 "dsi1_p 4919 "dsi1_phy_pll_out_byteclk",
4986 "dsi1_p 4920 "dsi1_phy_pll_out_dsiclk",
4987 "dp_lin 4921 "dp_link_clk_divsel_ten",
4988 "dp_vco 4922 "dp_vco_divided_clk_src_mux";
4989 #clock-cells = <1>; 4923 #clock-cells = <1>;
4990 #reset-cells = <1>; 4924 #reset-cells = <1>;
4991 #power-domain-cells = 4925 #power-domain-cells = <1>;
4992 }; 4926 };
4993 4927
4994 pdc_intc: interrupt-controlle 4928 pdc_intc: interrupt-controller@b220000 {
4995 compatible = "qcom,sd 4929 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4996 reg = <0 0x0b220000 0 4930 reg = <0 0x0b220000 0 0x30000>;
4997 qcom,pdc-ranges = <0 4931 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4998 #interrupt-cells = <2 4932 #interrupt-cells = <2>;
4999 interrupt-parent = <& 4933 interrupt-parent = <&intc>;
5000 interrupt-controller; 4934 interrupt-controller;
5001 }; 4935 };
5002 4936
5003 pdc_reset: reset-controller@b 4937 pdc_reset: reset-controller@b2e0000 {
5004 compatible = "qcom,sd 4938 compatible = "qcom,sdm845-pdc-global";
5005 reg = <0 0x0b2e0000 0 4939 reg = <0 0x0b2e0000 0 0x20000>;
5006 #reset-cells = <1>; 4940 #reset-cells = <1>;
5007 }; 4941 };
5008 4942
5009 tsens0: thermal-sensor@c26300 4943 tsens0: thermal-sensor@c263000 {
5010 compatible = "qcom,sd 4944 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5011 reg = <0 0x0c263000 0 4945 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5012 <0 0x0c222000 0 4946 <0 0x0c222000 0 0x1ff>; /* SROT */
5013 #qcom,sensors = <13>; 4947 #qcom,sensors = <13>;
5014 interrupts = <GIC_SPI 4948 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5015 <GIC_SPI 4949 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5016 interrupt-names = "up 4950 interrupt-names = "uplow", "critical";
5017 #thermal-sensor-cells 4951 #thermal-sensor-cells = <1>;
5018 }; 4952 };
5019 4953
5020 tsens1: thermal-sensor@c26500 4954 tsens1: thermal-sensor@c265000 {
5021 compatible = "qcom,sd 4955 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
5022 reg = <0 0x0c265000 0 4956 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5023 <0 0x0c223000 0 4957 <0 0x0c223000 0 0x1ff>; /* SROT */
5024 #qcom,sensors = <8>; 4958 #qcom,sensors = <8>;
5025 interrupts = <GIC_SPI 4959 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5026 <GIC_SPI 4960 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5027 interrupt-names = "up 4961 interrupt-names = "uplow", "critical";
5028 #thermal-sensor-cells 4962 #thermal-sensor-cells = <1>;
5029 }; 4963 };
5030 4964
5031 aoss_reset: reset-controller@ 4965 aoss_reset: reset-controller@c2a0000 {
5032 compatible = "qcom,sd 4966 compatible = "qcom,sdm845-aoss-cc";
5033 reg = <0 0x0c2a0000 0 4967 reg = <0 0x0c2a0000 0 0x31000>;
5034 #reset-cells = <1>; 4968 #reset-cells = <1>;
5035 }; 4969 };
5036 4970
5037 aoss_qmp: power-management@c3 4971 aoss_qmp: power-management@c300000 {
5038 compatible = "qcom,sd 4972 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
5039 reg = <0 0x0c300000 0 4973 reg = <0 0x0c300000 0 0x400>;
5040 interrupts = <GIC_SPI 4974 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
5041 mboxes = <&apss_share 4975 mboxes = <&apss_shared 0>;
5042 4976
5043 #clock-cells = <0>; 4977 #clock-cells = <0>;
5044 4978
5045 cx_cdev: cx { 4979 cx_cdev: cx {
5046 #cooling-cell 4980 #cooling-cells = <2>;
5047 }; 4981 };
5048 4982
5049 ebi_cdev: ebi { 4983 ebi_cdev: ebi {
5050 #cooling-cell 4984 #cooling-cells = <2>;
5051 }; 4985 };
5052 }; 4986 };
5053 4987
5054 sram@c3f0000 { 4988 sram@c3f0000 {
5055 compatible = "qcom,sd 4989 compatible = "qcom,sdm845-rpmh-stats";
5056 reg = <0 0x0c3f0000 0 4990 reg = <0 0x0c3f0000 0 0x400>;
5057 }; 4991 };
5058 4992
5059 spmi_bus: spmi@c440000 { 4993 spmi_bus: spmi@c440000 {
5060 compatible = "qcom,sp 4994 compatible = "qcom,spmi-pmic-arb";
5061 reg = <0 0x0c440000 0 4995 reg = <0 0x0c440000 0 0x1100>,
5062 <0 0x0c600000 0 4996 <0 0x0c600000 0 0x2000000>,
5063 <0 0x0e600000 0 4997 <0 0x0e600000 0 0x100000>,
5064 <0 0x0e700000 0 4998 <0 0x0e700000 0 0xa0000>,
5065 <0 0x0c40a000 0 4999 <0 0x0c40a000 0 0x26000>;
5066 reg-names = "core", " 5000 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5067 interrupt-names = "pe 5001 interrupt-names = "periph_irq";
5068 interrupts = <GIC_SPI 5002 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
5069 qcom,ee = <0>; 5003 qcom,ee = <0>;
5070 qcom,channel = <0>; 5004 qcom,channel = <0>;
5071 #address-cells = <2>; 5005 #address-cells = <2>;
5072 #size-cells = <0>; 5006 #size-cells = <0>;
5073 interrupt-controller; 5007 interrupt-controller;
5074 #interrupt-cells = <4 5008 #interrupt-cells = <4>;
5075 }; 5009 };
5076 5010
5077 sram@146bf000 { 5011 sram@146bf000 {
5078 compatible = "qcom,sd 5012 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5079 reg = <0 0x146bf000 0 5013 reg = <0 0x146bf000 0 0x1000>;
5080 5014
5081 #address-cells = <1>; 5015 #address-cells = <1>;
5082 #size-cells = <1>; 5016 #size-cells = <1>;
5083 5017
5084 ranges = <0 0 0x146bf 5018 ranges = <0 0 0x146bf000 0x1000>;
5085 5019
5086 pil-reloc@94c { 5020 pil-reloc@94c {
5087 compatible = 5021 compatible = "qcom,pil-reloc-info";
5088 reg = <0x94c 5022 reg = <0x94c 0xc8>;
5089 }; 5023 };
5090 }; 5024 };
5091 5025
5092 apps_smmu: iommu@15000000 { 5026 apps_smmu: iommu@15000000 {
5093 compatible = "qcom,sd 5027 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5094 reg = <0 0x15000000 0 5028 reg = <0 0x15000000 0 0x80000>;
5095 #iommu-cells = <2>; 5029 #iommu-cells = <2>;
5096 #global-interrupts = 5030 #global-interrupts = <1>;
5097 interrupts = <GIC_SPI 5031 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 5032 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 5033 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 5034 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 5035 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 5036 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 5037 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 5038 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 5039 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 5040 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 5041 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 5042 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 5043 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 5044 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 5045 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 5046 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 5047 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 5048 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 5049 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 5050 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 5051 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 5052 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 5053 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 5054 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 5055 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 5056 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 5057 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 5058 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 5059 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 5060 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 5061 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 5062 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 5063 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 5064 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 5065 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 5066 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 5067 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 5068 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 5069 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 5070 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 5071 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 5072 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 5073 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 5074 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 5075 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 5076 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 5077 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 5078 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 5079 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 5080 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 5081 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 5082 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 5083 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 5084 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 5085 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 5086 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 5087 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 5088 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 5089 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 5090 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 5091 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 5092 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 5093 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 5094 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 5095 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
5162 }; 5096 };
5163 5097
5164 anoc_1_tbu: tbu@150c5000 { <<
5165 compatible = "qcom,sd <<
5166 reg = <0x0 0x150c5000 <<
5167 interconnects = <&sys <<
5168 &con <<
5169 power-domains = <&gcc <<
5170 qcom,stream-id-range <<
5171 }; <<
5172 <<
5173 anoc_2_tbu: tbu@150c9000 { <<
5174 compatible = "qcom,sd <<
5175 reg = <0x0 0x150c9000 <<
5176 interconnects = <&sys <<
5177 &con <<
5178 power-domains = <&gcc <<
5179 qcom,stream-id-range <<
5180 }; <<
5181 <<
5182 mnoc_hf_0_tbu: tbu@150cd000 { <<
5183 compatible = "qcom,sd <<
5184 reg = <0x0 0x150cd000 <<
5185 interconnects = <&mms <<
5186 &mms <<
5187 power-domains = <&gcc <<
5188 qcom,stream-id-range <<
5189 }; <<
5190 <<
5191 mnoc_hf_1_tbu: tbu@150d1000 { <<
5192 compatible = "qcom,sd <<
5193 reg = <0x0 0x150d1000 <<
5194 interconnects = <&mms <<
5195 &mms <<
5196 power-domains = <&gcc <<
5197 qcom,stream-id-range <<
5198 }; <<
5199 <<
5200 mnoc_sf_0_tbu: tbu@150d5000 { <<
5201 compatible = "qcom,sd <<
5202 reg = <0x0 0x150d5000 <<
5203 interconnects = <&mms <<
5204 &mms <<
5205 power-domains = <&gcc <<
5206 qcom,stream-id-range <<
5207 }; <<
5208 <<
5209 compute_dsp_tbu: tbu@150d9000 <<
5210 compatible = "qcom,sd <<
5211 reg = <0x0 0x150d9000 <<
5212 interconnects = <&sys <<
5213 &con <<
5214 qcom,stream-id-range <<
5215 }; <<
5216 <<
5217 adsp_tbu: tbu@150dd000 { <<
5218 compatible = "qcom,sd <<
5219 reg = <0x0 0x150dd000 <<
5220 interconnects = <&sys <<
5221 &con <<
5222 power-domains = <&gcc <<
5223 qcom,stream-id-range <<
5224 }; <<
5225 <<
5226 anoc_1_pcie_tbu: tbu@150e1000 <<
5227 compatible = "qcom,sd <<
5228 reg = <0x0 0x150e1000 <<
5229 clocks = <&gcc GCC_AG <<
5230 interconnects = <&sys <<
5231 &con <<
5232 power-domains = <&gcc <<
5233 qcom,stream-id-range <<
5234 }; <<
5235 <<
5236 lpasscc: clock-controller@170 5098 lpasscc: clock-controller@17014000 {
5237 compatible = "qcom,sd 5099 compatible = "qcom,sdm845-lpasscc";
5238 reg = <0 0x17014000 0 5100 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5239 reg-names = "cc", "qd 5101 reg-names = "cc", "qdsp6ss";
5240 #clock-cells = <1>; 5102 #clock-cells = <1>;
5241 status = "disabled"; 5103 status = "disabled";
5242 }; 5104 };
5243 5105
5244 gladiator_noc: interconnect@1 5106 gladiator_noc: interconnect@17900000 {
5245 compatible = "qcom,sd 5107 compatible = "qcom,sdm845-gladiator-noc";
5246 reg = <0 0x17900000 0 5108 reg = <0 0x17900000 0 0xd080>;
5247 #interconnect-cells = 5109 #interconnect-cells = <2>;
5248 qcom,bcm-voters = <&a 5110 qcom,bcm-voters = <&apps_bcm_voter>;
5249 }; 5111 };
5250 5112
5251 watchdog@17980000 { 5113 watchdog@17980000 {
5252 compatible = "qcom,ap 5114 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5253 reg = <0 0x17980000 0 5115 reg = <0 0x17980000 0 0x1000>;
5254 clocks = <&sleep_clk> 5116 clocks = <&sleep_clk>;
5255 interrupts = <GIC_SPI !! 5117 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5256 }; 5118 };
5257 5119
5258 apss_shared: mailbox@17990000 5120 apss_shared: mailbox@17990000 {
5259 compatible = "qcom,sd 5121 compatible = "qcom,sdm845-apss-shared";
5260 reg = <0 0x17990000 0 5122 reg = <0 0x17990000 0 0x1000>;
5261 #mbox-cells = <1>; 5123 #mbox-cells = <1>;
5262 }; 5124 };
5263 5125
5264 apps_rsc: rsc@179c0000 { 5126 apps_rsc: rsc@179c0000 {
5265 label = "apps_rsc"; 5127 label = "apps_rsc";
5266 compatible = "qcom,rp 5128 compatible = "qcom,rpmh-rsc";
5267 reg = <0 0x179c0000 0 5129 reg = <0 0x179c0000 0 0x10000>,
5268 <0 0x179d0000 0 5130 <0 0x179d0000 0 0x10000>,
5269 <0 0x179e0000 0 5131 <0 0x179e0000 0 0x10000>;
5270 reg-names = "drv-0", 5132 reg-names = "drv-0", "drv-1", "drv-2";
5271 interrupts = <GIC_SPI 5133 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5272 <GIC_SPI 5134 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5273 <GIC_SPI 5135 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5274 qcom,tcs-offset = <0x 5136 qcom,tcs-offset = <0xd00>;
5275 qcom,drv-id = <2>; 5137 qcom,drv-id = <2>;
5276 qcom,tcs-config = <AC 5138 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 <SL 5139 <SLEEP_TCS 3>,
5278 <WA 5140 <WAKE_TCS 3>,
5279 <CO 5141 <CONTROL_TCS 1>;
5280 power-domains = <&CLU 5142 power-domains = <&CLUSTER_PD>;
5281 5143
5282 apps_bcm_voter: bcm-v 5144 apps_bcm_voter: bcm-voter {
5283 compatible = 5145 compatible = "qcom,bcm-voter";
5284 }; 5146 };
5285 5147
5286 rpmhcc: clock-control 5148 rpmhcc: clock-controller {
5287 compatible = 5149 compatible = "qcom,sdm845-rpmh-clk";
5288 #clock-cells 5150 #clock-cells = <1>;
5289 clock-names = 5151 clock-names = "xo";
5290 clocks = <&xo 5152 clocks = <&xo_board>;
5291 }; 5153 };
5292 5154
5293 rpmhpd: power-control 5155 rpmhpd: power-controller {
5294 compatible = 5156 compatible = "qcom,sdm845-rpmhpd";
5295 #power-domain 5157 #power-domain-cells = <1>;
5296 operating-poi 5158 operating-points-v2 = <&rpmhpd_opp_table>;
5297 5159
5298 rpmhpd_opp_ta 5160 rpmhpd_opp_table: opp-table {
5299 compa 5161 compatible = "operating-points-v2";
5300 5162
5301 rpmhp 5163 rpmhpd_opp_ret: opp1 {
5302 5164 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5303 }; 5165 };
5304 5166
5305 rpmhp 5167 rpmhpd_opp_min_svs: opp2 {
5306 5168 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5307 }; 5169 };
5308 5170
5309 rpmhp 5171 rpmhpd_opp_low_svs: opp3 {
5310 5172 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5311 }; 5173 };
5312 5174
5313 rpmhp 5175 rpmhpd_opp_svs: opp4 {
5314 5176 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5315 }; 5177 };
5316 5178
5317 rpmhp 5179 rpmhpd_opp_svs_l1: opp5 {
5318 5180 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5319 }; 5181 };
5320 5182
5321 rpmhp 5183 rpmhpd_opp_nom: opp6 {
5322 5184 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5323 }; 5185 };
5324 5186
5325 rpmhp 5187 rpmhpd_opp_nom_l1: opp7 {
5326 5188 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5327 }; 5189 };
5328 5190
5329 rpmhp 5191 rpmhpd_opp_nom_l2: opp8 {
5330 5192 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5331 }; 5193 };
5332 5194
5333 rpmhp 5195 rpmhpd_opp_turbo: opp9 {
5334 5196 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5335 }; 5197 };
5336 5198
5337 rpmhp 5199 rpmhpd_opp_turbo_l1: opp10 {
5338 5200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5339 }; 5201 };
5340 }; 5202 };
5341 }; 5203 };
5342 }; 5204 };
5343 5205
5344 intc: interrupt-controller@17 5206 intc: interrupt-controller@17a00000 {
5345 compatible = "arm,gic 5207 compatible = "arm,gic-v3";
5346 #address-cells = <2>; 5208 #address-cells = <2>;
5347 #size-cells = <2>; 5209 #size-cells = <2>;
5348 ranges; 5210 ranges;
5349 #interrupt-cells = <3 5211 #interrupt-cells = <3>;
5350 interrupt-controller; 5212 interrupt-controller;
5351 reg = <0 0x17a00000 0 5213 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5352 <0 0x17a60000 0 5214 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5353 interrupts = <GIC_PPI 5215 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
5354 5216
5355 msi-controller@17a400 5217 msi-controller@17a40000 {
5356 compatible = 5218 compatible = "arm,gic-v3-its";
5357 msi-controlle 5219 msi-controller;
5358 #msi-cells = 5220 #msi-cells = <1>;
5359 reg = <0 0x17 5221 reg = <0 0x17a40000 0 0x20000>;
5360 status = "dis 5222 status = "disabled";
5361 }; 5223 };
5362 }; 5224 };
5363 5225
5364 slimbam: dma-controller@17184 5226 slimbam: dma-controller@17184000 {
5365 compatible = "qcom,ba 5227 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5366 qcom,controlled-remot 5228 qcom,controlled-remotely;
5367 reg = <0 0x17184000 0 5229 reg = <0 0x17184000 0 0x2a000>;
5368 num-channels = <31>; 5230 num-channels = <31>;
5369 interrupts = <GIC_SPI 5231 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
5370 #dma-cells = <1>; 5232 #dma-cells = <1>;
5371 qcom,ee = <1>; 5233 qcom,ee = <1>;
5372 qcom,num-ees = <2>; 5234 qcom,num-ees = <2>;
5373 iommus = <&apps_smmu 5235 iommus = <&apps_smmu 0x1806 0x0>;
5374 }; 5236 };
5375 5237
5376 timer@17c90000 { 5238 timer@17c90000 {
5377 #address-cells = <1>; 5239 #address-cells = <1>;
5378 #size-cells = <1>; 5240 #size-cells = <1>;
5379 ranges = <0 0 0 0x200 5241 ranges = <0 0 0 0x20000000>;
5380 compatible = "arm,arm 5242 compatible = "arm,armv7-timer-mem";
5381 reg = <0 0x17c90000 0 5243 reg = <0 0x17c90000 0 0x1000>;
5382 5244
5383 frame@17ca0000 { 5245 frame@17ca0000 {
5384 frame-number 5246 frame-number = <0>;
5385 interrupts = 5247 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
5386 5248 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5387 reg = <0x17ca 5249 reg = <0x17ca0000 0x1000>,
5388 <0x17cb 5250 <0x17cb0000 0x1000>;
5389 }; 5251 };
5390 5252
5391 frame@17cc0000 { 5253 frame@17cc0000 {
5392 frame-number 5254 frame-number = <1>;
5393 interrupts = 5255 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
5394 reg = <0x17cc 5256 reg = <0x17cc0000 0x1000>;
5395 status = "dis 5257 status = "disabled";
5396 }; 5258 };
5397 5259
5398 frame@17cd0000 { 5260 frame@17cd0000 {
5399 frame-number 5261 frame-number = <2>;
5400 interrupts = 5262 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5401 reg = <0x17cd 5263 reg = <0x17cd0000 0x1000>;
5402 status = "dis 5264 status = "disabled";
5403 }; 5265 };
5404 5266
5405 frame@17ce0000 { 5267 frame@17ce0000 {
5406 frame-number 5268 frame-number = <3>;
5407 interrupts = 5269 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5408 reg = <0x17ce 5270 reg = <0x17ce0000 0x1000>;
5409 status = "dis 5271 status = "disabled";
5410 }; 5272 };
5411 5273
5412 frame@17cf0000 { 5274 frame@17cf0000 {
5413 frame-number 5275 frame-number = <4>;
5414 interrupts = 5276 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5415 reg = <0x17cf 5277 reg = <0x17cf0000 0x1000>;
5416 status = "dis 5278 status = "disabled";
5417 }; 5279 };
5418 5280
5419 frame@17d00000 { 5281 frame@17d00000 {
5420 frame-number 5282 frame-number = <5>;
5421 interrupts = 5283 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5422 reg = <0x17d0 5284 reg = <0x17d00000 0x1000>;
5423 status = "dis 5285 status = "disabled";
5424 }; 5286 };
5425 5287
5426 frame@17d10000 { 5288 frame@17d10000 {
5427 frame-number 5289 frame-number = <6>;
5428 interrupts = 5290 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5429 reg = <0x17d1 5291 reg = <0x17d10000 0x1000>;
5430 status = "dis 5292 status = "disabled";
5431 }; 5293 };
5432 }; 5294 };
5433 5295
5434 osm_l3: interconnect@17d41000 5296 osm_l3: interconnect@17d41000 {
5435 compatible = "qcom,sd 5297 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5436 reg = <0 0x17d41000 0 5298 reg = <0 0x17d41000 0 0x1400>;
5437 5299
5438 clocks = <&rpmhcc RPM 5300 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5439 clock-names = "xo", " 5301 clock-names = "xo", "alternate";
5440 5302
5441 #interconnect-cells = 5303 #interconnect-cells = <1>;
5442 }; 5304 };
5443 5305
5444 cpufreq_hw: cpufreq@17d43000 5306 cpufreq_hw: cpufreq@17d43000 {
5445 compatible = "qcom,sd 5307 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5446 reg = <0 0x17d43000 0 5308 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5447 reg-names = "freq-dom 5309 reg-names = "freq-domain0", "freq-domain1";
5448 5310
5449 interrupts-extended = 5311 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5450 5312
5451 clocks = <&rpmhcc RPM 5313 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
5452 clock-names = "xo", " 5314 clock-names = "xo", "alternate";
5453 5315
5454 #freq-domain-cells = 5316 #freq-domain-cells = <1>;
5455 #clock-cells = <1>; 5317 #clock-cells = <1>;
5456 }; 5318 };
5457 5319
5458 wifi: wifi@18800000 { 5320 wifi: wifi@18800000 {
5459 compatible = "qcom,wc 5321 compatible = "qcom,wcn3990-wifi";
5460 status = "disabled"; 5322 status = "disabled";
5461 reg = <0 0x18800000 0 5323 reg = <0 0x18800000 0 0x800000>;
5462 reg-names = "membase" 5324 reg-names = "membase";
5463 memory-region = <&wla 5325 memory-region = <&wlan_msa_mem>;
5464 clock-names = "cxo_re 5326 clock-names = "cxo_ref_clk_pin";
5465 clocks = <&rpmhcc RPM 5327 clocks = <&rpmhcc RPMH_RF_CLK2>;
5466 interrupts = 5328 interrupts =
5467 <GIC_SPI 414 5329 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
5468 <GIC_SPI 415 5330 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
5469 <GIC_SPI 416 5331 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
5470 <GIC_SPI 417 5332 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
5471 <GIC_SPI 418 5333 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5472 <GIC_SPI 419 5334 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5473 <GIC_SPI 420 5335 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
5474 <GIC_SPI 421 5336 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5475 <GIC_SPI 422 5337 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
5476 <GIC_SPI 423 5338 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5477 <GIC_SPI 424 5339 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5478 <GIC_SPI 425 5340 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
5479 iommus = <&apps_smmu 5341 iommus = <&apps_smmu 0x0040 0x1>;
5480 }; 5342 };
5481 }; 5343 };
5482 5344
5483 sound: sound { 5345 sound: sound {
5484 }; 5346 };
5485 5347
5486 thermal-zones { 5348 thermal-zones {
5487 cpu0-thermal { 5349 cpu0-thermal {
5488 polling-delay-passive 5350 polling-delay-passive = <250>;
>> 5351 polling-delay = <1000>;
5489 5352
5490 thermal-sensors = <&t 5353 thermal-sensors = <&tsens0 1>;
5491 5354
5492 trips { 5355 trips {
5493 cpu0_alert0: 5356 cpu0_alert0: trip-point0 {
5494 tempe 5357 temperature = <90000>;
5495 hyste 5358 hysteresis = <2000>;
5496 type 5359 type = "passive";
5497 }; 5360 };
5498 5361
5499 cpu0_alert1: 5362 cpu0_alert1: trip-point1 {
5500 tempe 5363 temperature = <95000>;
5501 hyste 5364 hysteresis = <2000>;
5502 type 5365 type = "passive";
5503 }; 5366 };
5504 5367
5505 cpu0_crit: cp 5368 cpu0_crit: cpu-crit {
5506 tempe 5369 temperature = <110000>;
5507 hyste 5370 hysteresis = <1000>;
5508 type 5371 type = "critical";
5509 }; 5372 };
5510 }; 5373 };
5511 }; 5374 };
5512 5375
5513 cpu1-thermal { 5376 cpu1-thermal {
5514 polling-delay-passive 5377 polling-delay-passive = <250>;
>> 5378 polling-delay = <1000>;
5515 5379
5516 thermal-sensors = <&t 5380 thermal-sensors = <&tsens0 2>;
5517 5381
5518 trips { 5382 trips {
5519 cpu1_alert0: 5383 cpu1_alert0: trip-point0 {
5520 tempe 5384 temperature = <90000>;
5521 hyste 5385 hysteresis = <2000>;
5522 type 5386 type = "passive";
5523 }; 5387 };
5524 5388
5525 cpu1_alert1: 5389 cpu1_alert1: trip-point1 {
5526 tempe 5390 temperature = <95000>;
5527 hyste 5391 hysteresis = <2000>;
5528 type 5392 type = "passive";
5529 }; 5393 };
5530 5394
5531 cpu1_crit: cp 5395 cpu1_crit: cpu-crit {
5532 tempe 5396 temperature = <110000>;
5533 hyste 5397 hysteresis = <1000>;
5534 type 5398 type = "critical";
5535 }; 5399 };
5536 }; 5400 };
5537 }; 5401 };
5538 5402
5539 cpu2-thermal { 5403 cpu2-thermal {
5540 polling-delay-passive 5404 polling-delay-passive = <250>;
>> 5405 polling-delay = <1000>;
5541 5406
5542 thermal-sensors = <&t 5407 thermal-sensors = <&tsens0 3>;
5543 5408
5544 trips { 5409 trips {
5545 cpu2_alert0: 5410 cpu2_alert0: trip-point0 {
5546 tempe 5411 temperature = <90000>;
5547 hyste 5412 hysteresis = <2000>;
5548 type 5413 type = "passive";
5549 }; 5414 };
5550 5415
5551 cpu2_alert1: 5416 cpu2_alert1: trip-point1 {
5552 tempe 5417 temperature = <95000>;
5553 hyste 5418 hysteresis = <2000>;
5554 type 5419 type = "passive";
5555 }; 5420 };
5556 5421
5557 cpu2_crit: cp 5422 cpu2_crit: cpu-crit {
5558 tempe 5423 temperature = <110000>;
5559 hyste 5424 hysteresis = <1000>;
5560 type 5425 type = "critical";
5561 }; 5426 };
5562 }; 5427 };
5563 }; 5428 };
5564 5429
5565 cpu3-thermal { 5430 cpu3-thermal {
5566 polling-delay-passive 5431 polling-delay-passive = <250>;
>> 5432 polling-delay = <1000>;
5567 5433
5568 thermal-sensors = <&t 5434 thermal-sensors = <&tsens0 4>;
5569 5435
5570 trips { 5436 trips {
5571 cpu3_alert0: 5437 cpu3_alert0: trip-point0 {
5572 tempe 5438 temperature = <90000>;
5573 hyste 5439 hysteresis = <2000>;
5574 type 5440 type = "passive";
5575 }; 5441 };
5576 5442
5577 cpu3_alert1: 5443 cpu3_alert1: trip-point1 {
5578 tempe 5444 temperature = <95000>;
5579 hyste 5445 hysteresis = <2000>;
5580 type 5446 type = "passive";
5581 }; 5447 };
5582 5448
5583 cpu3_crit: cp 5449 cpu3_crit: cpu-crit {
5584 tempe 5450 temperature = <110000>;
5585 hyste 5451 hysteresis = <1000>;
5586 type 5452 type = "critical";
5587 }; 5453 };
5588 }; 5454 };
5589 }; 5455 };
5590 5456
5591 cpu4-thermal { 5457 cpu4-thermal {
5592 polling-delay-passive 5458 polling-delay-passive = <250>;
>> 5459 polling-delay = <1000>;
5593 5460
5594 thermal-sensors = <&t 5461 thermal-sensors = <&tsens0 7>;
5595 5462
5596 trips { 5463 trips {
5597 cpu4_alert0: 5464 cpu4_alert0: trip-point0 {
5598 tempe 5465 temperature = <90000>;
5599 hyste 5466 hysteresis = <2000>;
5600 type 5467 type = "passive";
5601 }; 5468 };
5602 5469
5603 cpu4_alert1: 5470 cpu4_alert1: trip-point1 {
5604 tempe 5471 temperature = <95000>;
5605 hyste 5472 hysteresis = <2000>;
5606 type 5473 type = "passive";
5607 }; 5474 };
5608 5475
5609 cpu4_crit: cp 5476 cpu4_crit: cpu-crit {
5610 tempe 5477 temperature = <110000>;
5611 hyste 5478 hysteresis = <1000>;
5612 type 5479 type = "critical";
5613 }; 5480 };
5614 }; 5481 };
5615 }; 5482 };
5616 5483
5617 cpu5-thermal { 5484 cpu5-thermal {
5618 polling-delay-passive 5485 polling-delay-passive = <250>;
>> 5486 polling-delay = <1000>;
5619 5487
5620 thermal-sensors = <&t 5488 thermal-sensors = <&tsens0 8>;
5621 5489
5622 trips { 5490 trips {
5623 cpu5_alert0: 5491 cpu5_alert0: trip-point0 {
5624 tempe 5492 temperature = <90000>;
5625 hyste 5493 hysteresis = <2000>;
5626 type 5494 type = "passive";
5627 }; 5495 };
5628 5496
5629 cpu5_alert1: 5497 cpu5_alert1: trip-point1 {
5630 tempe 5498 temperature = <95000>;
5631 hyste 5499 hysteresis = <2000>;
5632 type 5500 type = "passive";
5633 }; 5501 };
5634 5502
5635 cpu5_crit: cp 5503 cpu5_crit: cpu-crit {
5636 tempe 5504 temperature = <110000>;
5637 hyste 5505 hysteresis = <1000>;
5638 type 5506 type = "critical";
5639 }; 5507 };
5640 }; 5508 };
5641 }; 5509 };
5642 5510
5643 cpu6-thermal { 5511 cpu6-thermal {
5644 polling-delay-passive 5512 polling-delay-passive = <250>;
>> 5513 polling-delay = <1000>;
5645 5514
5646 thermal-sensors = <&t 5515 thermal-sensors = <&tsens0 9>;
5647 5516
5648 trips { 5517 trips {
5649 cpu6_alert0: 5518 cpu6_alert0: trip-point0 {
5650 tempe 5519 temperature = <90000>;
5651 hyste 5520 hysteresis = <2000>;
5652 type 5521 type = "passive";
5653 }; 5522 };
5654 5523
5655 cpu6_alert1: 5524 cpu6_alert1: trip-point1 {
5656 tempe 5525 temperature = <95000>;
5657 hyste 5526 hysteresis = <2000>;
5658 type 5527 type = "passive";
5659 }; 5528 };
5660 5529
5661 cpu6_crit: cp 5530 cpu6_crit: cpu-crit {
5662 tempe 5531 temperature = <110000>;
5663 hyste 5532 hysteresis = <1000>;
5664 type 5533 type = "critical";
5665 }; 5534 };
5666 }; 5535 };
5667 }; 5536 };
5668 5537
5669 cpu7-thermal { 5538 cpu7-thermal {
5670 polling-delay-passive 5539 polling-delay-passive = <250>;
>> 5540 polling-delay = <1000>;
5671 5541
5672 thermal-sensors = <&t 5542 thermal-sensors = <&tsens0 10>;
5673 5543
5674 trips { 5544 trips {
5675 cpu7_alert0: 5545 cpu7_alert0: trip-point0 {
5676 tempe 5546 temperature = <90000>;
5677 hyste 5547 hysteresis = <2000>;
5678 type 5548 type = "passive";
5679 }; 5549 };
5680 5550
5681 cpu7_alert1: 5551 cpu7_alert1: trip-point1 {
5682 tempe 5552 temperature = <95000>;
5683 hyste 5553 hysteresis = <2000>;
5684 type 5554 type = "passive";
5685 }; 5555 };
5686 5556
5687 cpu7_crit: cp 5557 cpu7_crit: cpu-crit {
5688 tempe 5558 temperature = <110000>;
5689 hyste 5559 hysteresis = <1000>;
5690 type 5560 type = "critical";
5691 }; 5561 };
5692 }; 5562 };
5693 }; 5563 };
5694 5564
5695 aoss0-thermal { 5565 aoss0-thermal {
5696 polling-delay-passive 5566 polling-delay-passive = <250>;
>> 5567 polling-delay = <1000>;
5697 5568
5698 thermal-sensors = <&t 5569 thermal-sensors = <&tsens0 0>;
5699 5570
5700 trips { 5571 trips {
5701 aoss0_alert0: 5572 aoss0_alert0: trip-point0 {
5702 tempe 5573 temperature = <90000>;
5703 hyste 5574 hysteresis = <2000>;
5704 type 5575 type = "hot";
5705 }; 5576 };
5706 }; 5577 };
5707 }; 5578 };
5708 5579
5709 cluster0-thermal { 5580 cluster0-thermal {
5710 polling-delay-passive 5581 polling-delay-passive = <250>;
>> 5582 polling-delay = <1000>;
5711 5583
5712 thermal-sensors = <&t 5584 thermal-sensors = <&tsens0 5>;
5713 5585
5714 trips { 5586 trips {
5715 cluster0_aler 5587 cluster0_alert0: trip-point0 {
5716 tempe 5588 temperature = <90000>;
5717 hyste 5589 hysteresis = <2000>;
5718 type 5590 type = "hot";
5719 }; 5591 };
5720 cluster0_crit !! 5592 cluster0_crit: cluster0_crit {
5721 tempe 5593 temperature = <110000>;
5722 hyste 5594 hysteresis = <2000>;
5723 type 5595 type = "critical";
5724 }; 5596 };
5725 }; 5597 };
5726 }; 5598 };
5727 5599
5728 cluster1-thermal { 5600 cluster1-thermal {
5729 polling-delay-passive 5601 polling-delay-passive = <250>;
>> 5602 polling-delay = <1000>;
5730 5603
5731 thermal-sensors = <&t 5604 thermal-sensors = <&tsens0 6>;
5732 5605
5733 trips { 5606 trips {
5734 cluster1_aler 5607 cluster1_alert0: trip-point0 {
5735 tempe 5608 temperature = <90000>;
5736 hyste 5609 hysteresis = <2000>;
5737 type 5610 type = "hot";
5738 }; 5611 };
5739 cluster1_crit !! 5612 cluster1_crit: cluster1_crit {
5740 tempe 5613 temperature = <110000>;
5741 hyste 5614 hysteresis = <2000>;
5742 type 5615 type = "critical";
5743 }; 5616 };
5744 }; 5617 };
5745 }; 5618 };
5746 5619
5747 gpu-top-thermal { 5620 gpu-top-thermal {
5748 polling-delay-passive 5621 polling-delay-passive = <250>;
>> 5622 polling-delay = <1000>;
5749 5623
5750 thermal-sensors = <&t 5624 thermal-sensors = <&tsens0 11>;
5751 5625
5752 cooling-maps { <<
5753 map0 { <<
5754 trip <<
5755 cooli <<
5756 }; <<
5757 }; <<
5758 <<
5759 trips { 5626 trips {
5760 gpu_top_alert !! 5627 gpu1_alert0: trip-point0 {
5761 tempe <<
5762 hyste <<
5763 type <<
5764 }; <<
5765 <<
5766 trip-point1 { <<
5767 tempe 5628 temperature = <90000>;
5768 hyste !! 5629 hysteresis = <2000>;
5769 type 5630 type = "hot";
5770 }; 5631 };
5771 <<
5772 trip-point2 { <<
5773 tempe <<
5774 hyste <<
5775 type <<
5776 }; <<
5777 }; 5632 };
5778 }; 5633 };
5779 5634
5780 gpu-bottom-thermal { 5635 gpu-bottom-thermal {
5781 polling-delay-passive 5636 polling-delay-passive = <250>;
>> 5637 polling-delay = <1000>;
5782 5638
5783 thermal-sensors = <&t 5639 thermal-sensors = <&tsens0 12>;
5784 5640
5785 cooling-maps { <<
5786 map0 { <<
5787 trip <<
5788 cooli <<
5789 }; <<
5790 }; <<
5791 <<
5792 trips { 5641 trips {
5793 gpu_bottom_al !! 5642 gpu2_alert0: trip-point0 {
5794 tempe <<
5795 hyste <<
5796 type <<
5797 }; <<
5798 <<
5799 trip-point1 { <<
5800 tempe 5643 temperature = <90000>;
5801 hyste !! 5644 hysteresis = <2000>;
5802 type 5645 type = "hot";
5803 }; 5646 };
5804 <<
5805 trip-point2 { <<
5806 tempe <<
5807 hyste <<
5808 type <<
5809 }; <<
5810 }; 5647 };
5811 }; 5648 };
5812 5649
5813 aoss1-thermal { 5650 aoss1-thermal {
5814 polling-delay-passive 5651 polling-delay-passive = <250>;
>> 5652 polling-delay = <1000>;
5815 5653
5816 thermal-sensors = <&t 5654 thermal-sensors = <&tsens1 0>;
5817 5655
5818 trips { 5656 trips {
5819 aoss1_alert0: 5657 aoss1_alert0: trip-point0 {
5820 tempe 5658 temperature = <90000>;
5821 hyste 5659 hysteresis = <2000>;
5822 type 5660 type = "hot";
5823 }; 5661 };
5824 }; 5662 };
5825 }; 5663 };
5826 5664
5827 q6-modem-thermal { 5665 q6-modem-thermal {
5828 polling-delay-passive 5666 polling-delay-passive = <250>;
>> 5667 polling-delay = <1000>;
5829 5668
5830 thermal-sensors = <&t 5669 thermal-sensors = <&tsens1 1>;
5831 5670
5832 trips { 5671 trips {
5833 q6_modem_aler 5672 q6_modem_alert0: trip-point0 {
5834 tempe 5673 temperature = <90000>;
5835 hyste 5674 hysteresis = <2000>;
5836 type 5675 type = "hot";
5837 }; 5676 };
5838 }; 5677 };
5839 }; 5678 };
5840 5679
5841 mem-thermal { 5680 mem-thermal {
5842 polling-delay-passive 5681 polling-delay-passive = <250>;
>> 5682 polling-delay = <1000>;
5843 5683
5844 thermal-sensors = <&t 5684 thermal-sensors = <&tsens1 2>;
5845 5685
5846 trips { 5686 trips {
5847 mem_alert0: t 5687 mem_alert0: trip-point0 {
5848 tempe 5688 temperature = <90000>;
5849 hyste 5689 hysteresis = <2000>;
5850 type 5690 type = "hot";
5851 }; 5691 };
5852 }; 5692 };
5853 }; 5693 };
5854 5694
5855 wlan-thermal { 5695 wlan-thermal {
5856 polling-delay-passive 5696 polling-delay-passive = <250>;
>> 5697 polling-delay = <1000>;
5857 5698
5858 thermal-sensors = <&t 5699 thermal-sensors = <&tsens1 3>;
5859 5700
5860 trips { 5701 trips {
5861 wlan_alert0: 5702 wlan_alert0: trip-point0 {
5862 tempe 5703 temperature = <90000>;
5863 hyste 5704 hysteresis = <2000>;
5864 type 5705 type = "hot";
5865 }; 5706 };
5866 }; 5707 };
5867 }; 5708 };
5868 5709
5869 q6-hvx-thermal { 5710 q6-hvx-thermal {
5870 polling-delay-passive 5711 polling-delay-passive = <250>;
>> 5712 polling-delay = <1000>;
5871 5713
5872 thermal-sensors = <&t 5714 thermal-sensors = <&tsens1 4>;
5873 5715
5874 trips { 5716 trips {
5875 q6_hvx_alert0 5717 q6_hvx_alert0: trip-point0 {
5876 tempe 5718 temperature = <90000>;
5877 hyste 5719 hysteresis = <2000>;
5878 type 5720 type = "hot";
5879 }; 5721 };
5880 }; 5722 };
5881 }; 5723 };
5882 5724
5883 camera-thermal { 5725 camera-thermal {
5884 polling-delay-passive 5726 polling-delay-passive = <250>;
>> 5727 polling-delay = <1000>;
5885 5728
5886 thermal-sensors = <&t 5729 thermal-sensors = <&tsens1 5>;
5887 5730
5888 trips { 5731 trips {
5889 camera_alert0 5732 camera_alert0: trip-point0 {
5890 tempe 5733 temperature = <90000>;
5891 hyste 5734 hysteresis = <2000>;
5892 type 5735 type = "hot";
5893 }; 5736 };
5894 }; 5737 };
5895 }; 5738 };
5896 5739
5897 video-thermal { 5740 video-thermal {
5898 polling-delay-passive 5741 polling-delay-passive = <250>;
>> 5742 polling-delay = <1000>;
5899 5743
5900 thermal-sensors = <&t 5744 thermal-sensors = <&tsens1 6>;
5901 5745
5902 trips { 5746 trips {
5903 video_alert0: 5747 video_alert0: trip-point0 {
5904 tempe 5748 temperature = <90000>;
5905 hyste 5749 hysteresis = <2000>;
5906 type 5750 type = "hot";
5907 }; 5751 };
5908 }; 5752 };
5909 }; 5753 };
5910 5754
5911 modem-thermal { 5755 modem-thermal {
5912 polling-delay-passive 5756 polling-delay-passive = <250>;
>> 5757 polling-delay = <1000>;
5913 5758
5914 thermal-sensors = <&t 5759 thermal-sensors = <&tsens1 7>;
5915 5760
5916 trips { 5761 trips {
5917 modem_alert0: 5762 modem_alert0: trip-point0 {
5918 tempe 5763 temperature = <90000>;
5919 hyste 5764 hysteresis = <2000>;
5920 type 5765 type = "hot";
5921 }; 5766 };
5922 }; 5767 };
5923 }; 5768 };
5924 }; 5769 };
5925 5770
5926 timer { 5771 timer {
5927 compatible = "arm,armv8-timer 5772 compatible = "arm,armv8-timer";
5928 interrupts = <GIC_PPI 1 IRQ_T 5773 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
5929 <GIC_PPI 2 IRQ_T 5774 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
5930 <GIC_PPI 3 IRQ_T 5775 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
5931 <GIC_PPI 0 IRQ_T 5776 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
5932 }; 5777 };
5933 }; 5778 };
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