1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SDX75 SoC device tree source 3 * SDX75 SoC device tree source
4 * 4 *
5 * Copyright (c) 2023 Qualcomm Innovation Cent 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,rpmh.h> 9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h> 10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> <<
12 #include <dt-bindings/gpio/gpio.h> <<
13 #include <dt-bindings/interconnect/qcom,icc.h> 11 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75. 12 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> <<
17 #include <dt-bindings/power/qcom,rpmhpd.h> 14 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 17
21 / { 18 / {
22 #address-cells = <2>; 19 #address-cells = <2>;
23 #size-cells = <2>; 20 #size-cells = <2>;
24 interrupt-parent = <&intc>; 21 interrupt-parent = <&intc>;
25 22
26 chosen: chosen { }; 23 chosen: chosen { };
27 24
28 clocks { 25 clocks {
29 xo_board: xo-board { 26 xo_board: xo-board {
30 compatible = "fixed-cl 27 compatible = "fixed-clock";
31 clock-frequency = <768 28 clock-frequency = <76800000>;
32 #clock-cells = <0>; 29 #clock-cells = <0>;
33 }; 30 };
34 31
35 sleep_clk: sleep-clk { 32 sleep_clk: sleep-clk {
36 compatible = "fixed-cl 33 compatible = "fixed-clock";
37 clock-frequency = <320 34 clock-frequency = <32000>;
38 #clock-cells = <0>; 35 #clock-cells = <0>;
39 }; 36 };
40 }; 37 };
41 38
42 cpus { 39 cpus {
43 #address-cells = <2>; 40 #address-cells = <2>;
44 #size-cells = <0>; 41 #size-cells = <0>;
45 42
46 CPU0: cpu@0 { 43 CPU0: cpu@0 {
47 device_type = "cpu"; 44 device_type = "cpu";
48 compatible = "arm,cort 45 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>; 46 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 47 clocks = <&cpufreq_hw 0>;
51 enable-method = "psci" 48 enable-method = "psci";
52 power-domains = <&CPU_ 49 power-domains = <&CPU_PD0>;
53 power-domain-names = " 50 power-domain-names = "psci";
54 qcom,freq-domain = <&c 51 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = < 52 capacity-dmips-mhz = <1024>;
56 dynamic-power-coeffici 53 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
58 55
59 L2_0: l2-cache { 56 L2_0: l2-cache {
60 compatible = " 57 compatible = "cache";
61 cache-level = 58 cache-level = <2>;
62 cache-unified; 59 cache-unified;
63 next-level-cac 60 next-level-cache = <&L3_0>;
64 L3_0: l3-cache 61 L3_0: l3-cache {
65 compat 62 compatible = "cache";
66 cache- 63 cache-level = <3>;
67 cache- 64 cache-unified;
68 }; 65 };
69 }; 66 };
70 }; 67 };
71 68
72 CPU1: cpu@100 { 69 CPU1: cpu@100 {
73 device_type = "cpu"; 70 device_type = "cpu";
74 compatible = "arm,cort 71 compatible = "arm,cortex-a55";
75 reg = <0x0 0x100>; 72 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 73 clocks = <&cpufreq_hw 0>;
77 enable-method = "psci" 74 enable-method = "psci";
78 power-domains = <&CPU_ 75 power-domains = <&CPU_PD1>;
79 power-domain-names = " 76 power-domain-names = "psci";
80 qcom,freq-domain = <&c 77 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <1024>;
82 dynamic-power-coeffici 79 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L 80 next-level-cache = <&L2_100>;
84 81
85 L2_100: l2-cache { 82 L2_100: l2-cache {
86 compatible = " 83 compatible = "cache";
87 cache-level = 84 cache-level = <2>;
88 cache-unified; 85 cache-unified;
89 next-level-cac 86 next-level-cache = <&L3_0>;
90 }; 87 };
91 }; 88 };
92 89
93 CPU2: cpu@200 { 90 CPU2: cpu@200 {
94 device_type = "cpu"; 91 device_type = "cpu";
95 compatible = "arm,cort 92 compatible = "arm,cortex-a55";
96 reg = <0x0 0x200>; 93 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 94 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci" 95 enable-method = "psci";
99 power-domains = <&CPU_ 96 power-domains = <&CPU_PD2>;
100 power-domain-names = " 97 power-domain-names = "psci";
101 qcom,freq-domain = <&c 98 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = < 99 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici 100 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L 101 next-level-cache = <&L2_200>;
105 102
106 L2_200: l2-cache { 103 L2_200: l2-cache {
107 compatible = " 104 compatible = "cache";
108 cache-level = 105 cache-level = <2>;
109 cache-unified; 106 cache-unified;
110 next-level-cac 107 next-level-cache = <&L3_0>;
111 }; 108 };
112 }; 109 };
113 110
114 CPU3: cpu@300 { 111 CPU3: cpu@300 {
115 device_type = "cpu"; 112 device_type = "cpu";
116 compatible = "arm,cort 113 compatible = "arm,cortex-a55";
117 reg = <0x0 0x300>; 114 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 115 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci" 116 enable-method = "psci";
120 power-domains = <&CPU_ 117 power-domains = <&CPU_PD3>;
121 power-domain-names = " 118 power-domain-names = "psci";
122 qcom,freq-domain = <&c 119 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = < 120 capacity-dmips-mhz = <1024>;
124 dynamic-power-coeffici 121 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L 122 next-level-cache = <&L2_300>;
126 123
127 L2_300: l2-cache { 124 L2_300: l2-cache {
128 compatible = " 125 compatible = "cache";
129 cache-level = 126 cache-level = <2>;
130 cache-unified; 127 cache-unified;
131 next-level-cac 128 next-level-cache = <&L3_0>;
132 }; 129 };
133 }; 130 };
134 131
135 cpu-map { 132 cpu-map {
136 cluster0 { 133 cluster0 {
137 core0 { 134 core0 {
138 cpu = 135 cpu = <&CPU0>;
139 }; 136 };
140 137
141 core1 { 138 core1 {
142 cpu = 139 cpu = <&CPU1>;
143 }; 140 };
144 141
145 core2 { 142 core2 {
146 cpu = 143 cpu = <&CPU2>;
147 }; 144 };
148 145
149 core3 { 146 core3 {
150 cpu = 147 cpu = <&CPU3>;
151 }; 148 };
152 }; 149 };
153 }; 150 };
154 151
155 idle-states { 152 idle-states {
156 entry-method = "psci"; 153 entry-method = "psci";
157 154
158 CPU_OFF: cpu-sleep-0 { 155 CPU_OFF: cpu-sleep-0 {
159 compatible = " 156 compatible = "arm,idle-state";
160 entry-latency- 157 entry-latency-us = <235>;
161 exit-latency-u 158 exit-latency-us = <428>;
162 min-residency- 159 min-residency-us = <1774>;
163 arm,psci-suspe 160 arm,psci-suspend-param = <0x40000003>;
164 local-timer-st 161 local-timer-stop;
165 }; 162 };
166 163
167 CPU_RAIL_OFF: cpu-rail 164 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = " 165 compatible = "arm,idle-state";
169 entry-latency- 166 entry-latency-us = <800>;
170 exit-latency-u 167 exit-latency-us = <750>;
171 min-residency- 168 min-residency-us = <4090>;
172 arm,psci-suspe 169 arm,psci-suspend-param = <0x40000004>;
173 local-timer-st 170 local-timer-stop;
174 }; 171 };
175 172
176 }; 173 };
177 174
178 domain-idle-states { 175 domain-idle-states {
179 CLUSTER_SLEEP_0: clust 176 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = " 177 compatible = "domain-idle-state";
181 arm,psci-suspe 178 arm,psci-suspend-param = <0x41000044>;
182 entry-latency- 179 entry-latency-us = <1050>;
183 exit-latency-u 180 exit-latency-us = <2500>;
184 min-residency- 181 min-residency-us = <5309>;
185 }; 182 };
186 183
187 CLUSTER_SLEEP_1: clust 184 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = " 185 compatible = "domain-idle-state";
189 arm,psci-suspe 186 arm,psci-suspend-param = <0x41001344>;
190 entry-latency- 187 entry-latency-us = <2761>;
191 exit-latency-u 188 exit-latency-us = <3964>;
192 min-residency- 189 min-residency-us = <8467>;
193 }; 190 };
194 191
195 CLUSTER_SLEEP_2: clust 192 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = " 193 compatible = "domain-idle-state";
197 arm,psci-suspe 194 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency- 195 entry-latency-us = <2793>;
199 exit-latency-u 196 exit-latency-us = <4023>;
200 min-residency- 197 min-residency-us = <9826>;
201 }; 198 };
202 }; 199 };
203 }; 200 };
204 201
205 firmware { 202 firmware {
206 scm: scm { 203 scm: scm {
207 compatible = "qcom,scm 204 compatible = "qcom,scm-sdx75", "qcom,scm";
208 }; 205 };
209 }; 206 };
210 207
211 clk_virt: interconnect-0 { 208 clk_virt: interconnect-0 {
212 compatible = "qcom,sdx75-clk-v 209 compatible = "qcom,sdx75-clk-virt";
213 #interconnect-cells = <2>; 210 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_v 211 qcom,bcm-voters = <&apps_bcm_voter>;
215 clocks = <&rpmhcc RPMH_QPIC_CL 212 clocks = <&rpmhcc RPMH_QPIC_CLK>;
216 }; 213 };
217 214
218 mc_virt: interconnect-1 { 215 mc_virt: interconnect-1 {
219 compatible = "qcom,sdx75-mc-vi 216 compatible = "qcom,sdx75-mc-virt";
220 #interconnect-cells = <2>; 217 #interconnect-cells = <2>;
221 qcom,bcm-voters = <&apps_bcm_v 218 qcom,bcm-voters = <&apps_bcm_voter>;
222 }; 219 };
223 220
224 memory@80000000 { 221 memory@80000000 {
225 device_type = "memory"; 222 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0> 223 reg = <0x0 0x80000000 0x0 0x0>;
227 }; 224 };
228 225
229 pmu { 226 pmu {
230 compatible = "arm,cortex-a55-p 227 compatible = "arm,cortex-a55-pmu";
231 interrupts = <GIC_PPI 7 IRQ_TY 228 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 }; 229 };
233 230
234 psci { 231 psci {
235 compatible = "arm,psci-1.0"; 232 compatible = "arm,psci-1.0";
236 method = "smc"; 233 method = "smc";
237 234
238 CPU_PD0: power-domain-cpu0 { 235 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = 236 #power-domain-cells = <0>;
240 power-domains = <&CLUS 237 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = < 238 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
242 }; 239 };
243 240
244 CPU_PD1: power-domain-cpu1 { 241 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = 242 #power-domain-cells = <0>;
246 power-domains = <&CLUS 243 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = < 244 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
248 }; 245 };
249 246
250 CPU_PD2: power-domain-cpu2 { 247 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = 248 #power-domain-cells = <0>;
252 power-domains = <&CLUS 249 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = < 250 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
254 }; 251 };
255 252
256 CPU_PD3: power-domain-cpu3 { 253 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = 254 #power-domain-cells = <0>;
258 power-domains = <&CLUS 255 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = < 256 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
260 }; 257 };
261 258
262 CLUSTER_PD: power-domain-cpu-c 259 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = 260 #power-domain-cells = <0>;
264 domain-idle-states = < 261 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 }; 262 };
266 }; 263 };
267 264
268 reserved-memory { 265 reserved-memory {
269 #address-cells = <2>; 266 #address-cells = <2>;
270 #size-cells = <2>; 267 #size-cells = <2>;
271 ranges; 268 ranges;
272 269
273 gunyah_hyp_mem: gunyah-hyp@800 270 gunyah_hyp_mem: gunyah-hyp@80000000 {
274 reg = <0x0 0x80000000 271 reg = <0x0 0x80000000 0x0 0x800000>;
275 no-map; 272 no-map;
276 }; 273 };
277 274
278 hyp_elf_package_mem: hyp-elf-p 275 hyp_elf_package_mem: hyp-elf-package@80800000 {
279 reg = <0x0 0x80800000 276 reg = <0x0 0x80800000 0x0 0x200000>;
280 no-map; 277 no-map;
281 }; 278 };
282 279
283 access_control_db_mem: access- 280 access_control_db_mem: access-control-db@81380000 {
284 reg = <0x0 0x81380000 281 reg = <0x0 0x81380000 0x0 0x80000>;
285 no-map; 282 no-map;
286 }; 283 };
287 284
288 qteetz_mem: qteetz@814e0000 { 285 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000 286 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 no-map; 287 no-map;
291 }; 288 };
292 289
293 trusted_apps_mem: trusted-apps 290 trusted_apps_mem: trusted-apps@81780000 {
294 reg = <0x0 0x81780000 291 reg = <0x0 0x81780000 0x0 0xa00000>;
295 no-map; 292 no-map;
296 }; 293 };
297 294
298 xbl_ramdump_mem: xbl-ramdump@8 295 xbl_ramdump_mem: xbl-ramdump@87a00000 {
299 reg = <0x0 0x87a00000 296 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 no-map; 297 no-map;
301 }; 298 };
302 299
303 cpucp_fw_mem: cpucp-fw@87c0000 300 cpucp_fw_mem: cpucp-fw@87c00000 {
304 reg = <0x0 0x87c00000 301 reg = <0x0 0x87c00000 0x0 0x100000>;
305 no-map; 302 no-map;
306 }; 303 };
307 304
308 xbl_dtlog_mem: xbl-dtlog@87d00 305 xbl_dtlog_mem: xbl-dtlog@87d00000 {
309 reg = <0x0 0x87d00000 306 reg = <0x0 0x87d00000 0x0 0x40000>;
310 no-map; 307 no-map;
311 }; 308 };
312 309
313 xbl_sc_mem: xbl-sc@87d40000 { 310 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000 311 reg = <0x0 0x87d40000 0x0 0x40000>;
315 no-map; 312 no-map;
316 }; 313 };
317 314
318 modem_efs_shared_mem: modem-ef 315 modem_efs_shared_mem: modem-efs-shared@87d80000 {
319 reg = <0x0 0x87d80000 316 reg = <0x0 0x87d80000 0x0 0x10000>;
320 no-map; 317 no-map;
321 }; 318 };
322 319
323 aop_image_mem: aop-image@87e00 320 aop_image_mem: aop-image@87e00000 {
324 reg = <0x0 0x87e00000 321 reg = <0x0 0x87e00000 0x0 0x20000>;
325 no-map; 322 no-map;
326 }; 323 };
327 324
328 smem_mem: smem@87e20000 { 325 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000 326 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 no-map; 327 no-map;
331 }; 328 };
332 329
333 aop_cmd_db_mem: aop-cmd-db@87e 330 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd 331 compatible = "qcom,cmd-db";
335 reg = <0x0 0x87ee0000 332 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 no-map; 333 no-map;
337 }; 334 };
338 335
339 aop_config_mem: aop-config@87f 336 aop_config_mem: aop-config@87f00000 {
340 reg = <0x0 0x87f00000 337 reg = <0x0 0x87f00000 0x0 0x20000>;
341 no-map; 338 no-map;
342 }; 339 };
343 340
344 ipa_fw_mem: ipa-fw@87f20000 { 341 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000 342 reg = <0x0 0x87f20000 0x0 0x10000>;
346 no-map; 343 no-map;
347 }; 344 };
348 345
349 secdata_mem: secdata@87f30000 346 secdata_mem: secdata@87f30000 {
350 reg = <0x0 0x87f30000 347 reg = <0x0 0x87f30000 0x0 0x1000>;
351 no-map; 348 no-map;
352 }; 349 };
353 350
354 tme_crashdump_mem: tme-crashdu 351 tme_crashdump_mem: tme-crashdump@87f31000 {
355 reg = <0x0 0x87f31000 352 reg = <0x0 0x87f31000 0x0 0x40000>;
356 no-map; 353 no-map;
357 }; 354 };
358 355
359 tme_log_mem: tme-log@87f71000 356 tme_log_mem: tme-log@87f71000 {
360 reg = <0x0 0x87f71000 357 reg = <0x0 0x87f71000 0x0 0x4000>;
361 no-map; 358 no-map;
362 }; 359 };
363 360
364 uefi_log_mem: uefi-log@87f7500 361 uefi_log_mem: uefi-log@87f75000 {
365 reg = <0x0 0x87f75000 362 reg = <0x0 0x87f75000 0x0 0x10000>;
366 no-map; 363 no-map;
367 }; 364 };
368 365
369 qdss_mem: qdss@88500000 { !! 366 qdss_mem: qdss@88800000 {
370 reg = <0x0 0x88500000 <<
371 no-map; <<
372 }; <<
373 <<
374 qlink_logging_mem: qlink-loggi <<
375 reg = <0x0 0x88800000 367 reg = <0x0 0x88800000 0x0 0x300000>;
376 no-map; 368 no-map;
377 }; 369 };
378 370
379 audio_heap_mem: audio-heap@88b 371 audio_heap_mem: audio-heap@88b00000 {
380 compatible = "shared-d 372 compatible = "shared-dma-pool";
381 reg = <0x0 0x88b00000 373 reg = <0x0 0x88b00000 0x0 0x400000>;
382 no-map; 374 no-map;
383 }; 375 };
384 376
385 mpss_dsm_mem_2: mpss-dsm-2@88f !! 377 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
386 reg = <0x0 0x88f00000 !! 378 reg = <0x0 0x88f00000 0x0 0x5080000>;
387 no-map; <<
388 }; <<
389 <<
390 mpss_dsm_mem: mpss-dsm@8b40000 <<
391 reg = <0x0 0x8b400000 <<
392 no-map; 379 no-map;
393 }; 380 };
394 381
395 q6_mpss_dtb_mem: q6-mpss-dtb@8 382 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
396 reg = <0x0 0x8df80000 383 reg = <0x0 0x8df80000 0x0 0x80000>;
397 no-map; 384 no-map;
398 }; 385 };
399 386
400 mpssadsp_mem: mpssadsp@8e00000 387 mpssadsp_mem: mpssadsp@8e000000 {
401 reg = <0x0 0x8e000000 !! 388 reg = <0x0 0x8e000000 0x0 0xf400000>;
402 no-map; 389 no-map;
403 }; 390 };
404 391
405 gunyah_trace_buffer_mem: gunya 392 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
406 reg = <0x0 0xbdb00000 393 reg = <0x0 0xbdb00000 0x0 0x2000000>;
407 no-map; 394 no-map;
408 }; 395 };
409 396
410 smmu_debug_buf_mem: smmu-debug 397 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
411 reg = <0x0 0xbfb00000 398 reg = <0x0 0xbfb00000 0x0 0x100000>;
412 no-map; 399 no-map;
413 }; 400 };
414 401
415 hyp_smmu_s2_pt_mem: hyp-smmu-s 402 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
416 reg = <0x0 0xbfc00000 403 reg = <0x0 0xbfc00000 0x0 0x400000>;
417 no-map; 404 no-map;
418 }; 405 };
419 }; 406 };
420 407
421 smp2p-modem { !! 408 smem: qcom,smem {
422 compatible = "qcom,smp2p"; <<
423 qcom,smem = <435>, <428>; <<
424 interrupts-extended = <&ipcc I <<
425 I <<
426 I <<
427 mboxes = <&ipcc IPCC_CLIENT_MP <<
428 IPCC_MPROC_SIG <<
429 <<
430 qcom,local-pid = <0>; <<
431 qcom,remote-pid = <1>; <<
432 <<
433 smp2p_modem_out: master-kernel <<
434 qcom,entry-name = "mas <<
435 #qcom,smem-state-cells <<
436 }; <<
437 <<
438 smp2p_modem_in: slave-kernel { <<
439 qcom,entry-name = "sla <<
440 interrupt-controller; <<
441 #interrupt-cells = <2> <<
442 }; <<
443 <<
444 ipa_smp2p_out: ipa-ap-to-modem <<
445 qcom,entry-name = "ipa <<
446 #qcom,smem-state-cells <<
447 }; <<
448 <<
449 ipa_smp2p_in: ipa-modem-to-ap <<
450 qcom,entry-name = "ipa <<
451 interrupt-controller; <<
452 #interrupt-cells = <2> <<
453 }; <<
454 }; <<
455 <<
456 smem: smem { <<
457 compatible = "qcom,smem"; 409 compatible = "qcom,smem";
458 memory-region = <&smem_mem>; 410 memory-region = <&smem_mem>;
459 hwlocks = <&tcsr_mutex 3>; 411 hwlocks = <&tcsr_mutex 3>;
460 }; 412 };
461 413
462 soc: soc@0 { 414 soc: soc@0 {
463 compatible = "simple-bus"; 415 compatible = "simple-bus";
464 #address-cells = <2>; 416 #address-cells = <2>;
465 #size-cells = <2>; 417 #size-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>; 418 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>; 419 dma-ranges = <0 0 0 0 0x10 0>;
468 420
469 gcc: clock-controller@80000 { 421 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx 422 compatible = "qcom,sdx75-gcc";
471 reg = <0x0 0x0080000 0 423 reg = <0x0 0x0080000 0x0 0x1f7400>;
472 clocks = <&rpmhcc RPMH 424 clocks = <&rpmhcc RPMH_CXO_CLK>,
473 <&sleep_clk>, 425 <&sleep_clk>,
474 <0>, 426 <0>,
475 <0>, 427 <0>,
476 <0>, 428 <0>,
477 <0>, 429 <0>,
478 <0>, 430 <0>,
479 <0>, 431 <0>,
480 <0>, 432 <0>,
481 <0>, 433 <0>,
482 <0>, 434 <0>,
483 <0>, 435 <0>,
484 <0>, 436 <0>,
485 <0>, 437 <0>,
486 <0>; 438 <0>;
487 #clock-cells = <1>; 439 #clock-cells = <1>;
488 #reset-cells = <1>; 440 #reset-cells = <1>;
489 #power-domain-cells = 441 #power-domain-cells = <1>;
490 }; 442 };
491 443
492 ipcc: mailbox@408000 { <<
493 compatible = "qcom,sdx <<
494 reg = <0 0x00408000 0 <<
495 interrupts = <GIC_SPI <<
496 interrupt-controller; <<
497 #interrupt-cells = <3> <<
498 #mbox-cells = <2>; <<
499 }; <<
500 <<
501 gpi_dma: dma-controller@900000 <<
502 compatible = "qcom,sdx <<
503 reg = <0x0 0x00900000 <<
504 #dma-cells = <3>; <<
505 interrupts = <GIC_SPI <<
506 <GIC_SPI <<
507 <GIC_SPI <<
508 <GIC_SPI <<
509 <GIC_SPI <<
510 <GIC_SPI <<
511 <GIC_SPI <<
512 <GIC_SPI <<
513 <GIC_SPI <<
514 <GIC_SPI <<
515 <GIC_SPI <<
516 <GIC_SPI <<
517 dma-channels = <12>; <<
518 dma-channel-mask = <0x <<
519 iommus = <&apps_smmu 0 <<
520 status = "disabled"; <<
521 }; <<
522 <<
523 qupv3_id_0: geniqup@9c0000 { 444 qupv3_id_0: geniqup@9c0000 {
524 compatible = "qcom,gen 445 compatible = "qcom,geni-se-qup";
525 reg = <0x0 0x009c0000 446 reg = <0x0 0x009c0000 0x0 0x2000>;
526 clocks = <&gcc GCC_QUP 447 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
527 <&gcc GCC_QUP 448 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
528 clock-names = "m-ahb", 449 clock-names = "m-ahb",
529 "s-ahb"; 450 "s-ahb";
530 iommus = <&apps_smmu 0 451 iommus = <&apps_smmu 0xe3 0x0>;
531 interconnects = <&clk_ 452 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
532 &clk_ 453 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
533 interconnect-names = " 454 interconnect-names = "qup-core";
534 #address-cells = <2>; 455 #address-cells = <2>;
535 #size-cells = <2>; 456 #size-cells = <2>;
536 ranges; 457 ranges;
537 status = "disabled"; 458 status = "disabled";
538 459
539 i2c0: i2c@980000 { <<
540 compatible = " <<
541 reg = <0x0 0x0 <<
542 clocks = <&gcc <<
543 clock-names = <<
544 interrupts = < <<
545 #address-cells <<
546 #size-cells = <<
547 pinctrl-0 = <& <<
548 pinctrl-names <<
549 interconnects <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 interconnect-n <<
556 dmas = <&gpi_d <<
557 <&gpi_d <<
558 dma-names = "t <<
559 status = "disa <<
560 }; <<
561 <<
562 spi0: spi@980000 { <<
563 compatible = " <<
564 reg = <0x0 0x0 <<
565 clocks = <&gcc <<
566 clock-names = <<
567 interrupts = < <<
568 #address-cells <<
569 #size-cells = <<
570 pinctrl-0 = <& <<
571 pinctrl-names <<
572 interconnects <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 interconnect-n <<
579 dmas = <&gpi_d <<
580 <&gpi_d <<
581 dma-names = "t <<
582 status = "disa <<
583 }; <<
584 <<
585 uart1: serial@984000 { 460 uart1: serial@984000 {
586 compatible = " 461 compatible = "qcom,geni-debug-uart";
587 reg = <0x0 0x0 462 reg = <0x0 0x00984000 0x0 0x4000>;
588 clocks = <&gcc 463 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
589 clock-names = 464 clock-names = "se";
590 interconnects 465 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
591 466 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
592 467 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
593 468 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
594 interconnect-n 469 interconnect-names = "qup-core",
595 470 "qup-config";
596 interrupts = < 471 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-0 = <& 472 pinctrl-0 = <&qupv3_se1_2uart_active>;
598 pinctrl-1 = <& 473 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
599 pinctrl-names 474 pinctrl-names = "default",
600 475 "sleep";
601 status = "disa 476 status = "disabled";
602 }; 477 };
603 <<
604 i2c2: i2c@988000 { <<
605 compatible = " <<
606 reg = <0x0 0x0 <<
607 clocks = <&gcc <<
608 clock-names = <<
609 interrupts = < <<
610 #address-cells <<
611 #size-cells = <<
612 pinctrl-0 = <& <<
613 pinctrl-names <<
614 interconnects <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 interconnect-n <<
621 dmas = <&gpi_d <<
622 <&gpi_d <<
623 dma-names = "t <<
624 status = "disa <<
625 }; <<
626 <<
627 spi2: spi@988000 { <<
628 compatible = " <<
629 reg = <0x0 0x0 <<
630 clocks = <&gcc <<
631 clock-names = <<
632 interrupts = < <<
633 #address-cells <<
634 #size-cells = <<
635 pinctrl-0 = <& <<
636 pinctrl-names <<
637 interconnects <<
638 <<
639 <<
640 <<
641 <<
642 <<
643 interconnect-n <<
644 dmas = <&gpi_d <<
645 <&gpi_d <<
646 dma-names = "t <<
647 status = "disa <<
648 }; <<
649 <<
650 i2c3: i2c@98c000 { <<
651 compatible = " <<
652 reg = <0x0 0x0 <<
653 clocks = <&gcc <<
654 clock-names = <<
655 interrupts = < <<
656 #address-cells <<
657 #size-cells = <<
658 pinctrl-0 = <& <<
659 pinctrl-names <<
660 interconnects <<
661 <<
662 <<
663 <<
664 <<
665 <<
666 interconnect-n <<
667 dmas = <&gpi_d <<
668 <&gpi_d <<
669 dma-names = "t <<
670 status = "disa <<
671 }; <<
672 <<
673 spi3: spi@98c000 { <<
674 compatible = " <<
675 reg = <0x0 0x0 <<
676 clocks = <&gcc <<
677 clock-names = <<
678 interrupts = < <<
679 #address-cells <<
680 #size-cells = <<
681 pinctrl-0 = <& <<
682 pinctrl-names <<
683 interconnects <<
684 <<
685 <<
686 <<
687 <<
688 <<
689 interconnect-n <<
690 dmas = <&gpi_d <<
691 <&gpi_d <<
692 dma-names = "t <<
693 status = "disa <<
694 }; <<
695 <<
696 uart4: serial@990000 { <<
697 compatible = " <<
698 reg = <0x0 0x0 <<
699 clocks = <&gcc <<
700 clock-names = <<
701 interrupts = < <<
702 pinctrl-0 = <& <<
703 pinctrl-names <<
704 interconnects <<
705 <<
706 <<
707 <<
708 interconnect-n <<
709 status = "disa <<
710 }; <<
711 <<
712 i2c5: i2c@994000 { <<
713 compatible = " <<
714 reg = <0x0 0x0 <<
715 clocks = <&gcc <<
716 clock-names = <<
717 interrupts = < <<
718 #address-cells <<
719 #size-cells = <<
720 pinctrl-0 = <& <<
721 pinctrl-names <<
722 interconnects <<
723 <<
724 <<
725 <<
726 <<
727 <<
728 interconnect-n <<
729 dmas = <&gpi_d <<
730 <&gpi_d <<
731 dma-names = "t <<
732 status = "disa <<
733 }; <<
734 <<
735 i2c6: i2c@998000 { <<
736 compatible = " <<
737 reg = <0x0 0x0 <<
738 clocks = <&gcc <<
739 clock-names = <<
740 interrupts = < <<
741 #address-cells <<
742 #size-cells = <<
743 pinctrl-0 = <& <<
744 pinctrl-names <<
745 interconnects <<
746 <<
747 <<
748 <<
749 <<
750 <<
751 interconnect-n <<
752 dmas = <&gpi_d <<
753 <&gpi_d <<
754 dma-names = "t <<
755 status = "disa <<
756 }; <<
757 <<
758 spi6: spi@998000 { <<
759 compatible = " <<
760 reg = <0x0 0x0 <<
761 clocks = <&gcc <<
762 clock-names = <<
763 interrupts = < <<
764 #address-cells <<
765 #size-cells = <<
766 pinctrl-0 = <& <<
767 pinctrl-names <<
768 interconnects <<
769 <<
770 <<
771 <<
772 <<
773 <<
774 interconnect-n <<
775 dmas = <&gpi_d <<
776 <&gpi_d <<
777 dma-names = "t <<
778 status = "disa <<
779 }; <<
780 <<
781 i2c7: i2c@99c000 { <<
782 compatible = " <<
783 reg = <0x0 0x0 <<
784 clocks = <&gcc <<
785 clock-names = <<
786 interrupts = < <<
787 #address-cells <<
788 #size-cells = <<
789 pinctrl-0 = <& <<
790 pinctrl-names <<
791 interconnects <<
792 <<
793 <<
794 <<
795 <<
796 <<
797 interconnect-n <<
798 dmas = <&gpi_d <<
799 <&gpi_d <<
800 dma-names = "t <<
801 status = "disa <<
802 }; <<
803 <<
804 spi7: spi@99c000 { <<
805 compatible = " <<
806 reg = <0x0 0x0 <<
807 clocks = <&gcc <<
808 clock-names = <<
809 interrupts = < <<
810 #address-cells <<
811 #size-cells = <<
812 pinctrl-0 = <& <<
813 pinctrl-names <<
814 interconnects <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 interconnect-n <<
821 dmas = <&gpi_d <<
822 <&gpi_d <<
823 dma-names = "t <<
824 status = "disa <<
825 }; <<
826 }; 478 };
827 479
828 usb_hsphy: phy@ff4000 { 480 usb_hsphy: phy@ff4000 {
829 compatible = "qcom,sdx 481 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
830 reg = <0x0 0x00ff4000 482 reg = <0x0 0x00ff4000 0x0 0x154>;
831 #phy-cells = <0>; 483 #phy-cells = <0>;
832 484
833 clocks = <&rpmhcc RPMH 485 clocks = <&rpmhcc RPMH_CXO_CLK>;
834 clock-names = "ref"; 486 clock-names = "ref";
835 487
836 resets = <&gcc GCC_QUS 488 resets = <&gcc GCC_QUSB2PHY_BCR>;
837 489
838 status = "disabled"; 490 status = "disabled";
839 }; 491 };
840 492
841 usb_qmpphy: phy@ff6000 { 493 usb_qmpphy: phy@ff6000 {
842 compatible = "qcom,sdx 494 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
843 reg = <0x0 0x00ff6000 495 reg = <0x0 0x00ff6000 0x0 0x2000>;
844 496
845 clocks = <&gcc GCC_USB 497 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
846 <&gcc GCC_USB 498 <&gcc GCC_USB2_CLKREF_EN>,
847 <&gcc GCC_USB 499 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
848 <&gcc GCC_USB 500 <&gcc GCC_USB3_PHY_PIPE_CLK>;
849 clock-names = "aux", 501 clock-names = "aux",
850 "ref", 502 "ref",
851 "cfg_ahb 503 "cfg_ahb",
852 "pipe"; 504 "pipe";
853 505
854 power-domains = <&gcc 506 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
855 507
856 resets = <&gcc GCC_USB 508 resets = <&gcc GCC_USB3_PHY_BCR>,
857 <&gcc GCC_USB 509 <&gcc GCC_USB3PHY_PHY_BCR>;
858 reset-names = "phy", 510 reset-names = "phy",
859 "phy_phy 511 "phy_phy";
860 512
861 #clock-cells = <0>; 513 #clock-cells = <0>;
862 clock-output-names = " 514 clock-output-names = "usb3_uni_phy_pipe_clk_src";
863 515
864 #phy-cells = <0>; 516 #phy-cells = <0>;
865 517
866 status = "disabled"; 518 status = "disabled";
867 }; 519 };
868 520
869 system_noc: interconnect@16400 521 system_noc: interconnect@1640000 {
870 compatible = "qcom,sdx 522 compatible = "qcom,sdx75-system-noc";
871 reg = <0x0 0x01640000 523 reg = <0x0 0x01640000 0x0 0x4b400>;
872 #interconnect-cells = 524 #interconnect-cells = <2>;
873 qcom,bcm-voters = <&ap 525 qcom,bcm-voters = <&apps_bcm_voter>;
874 }; 526 };
875 527
876 pcie_anoc: interconnect@16c000 528 pcie_anoc: interconnect@16c0000 {
877 compatible = "qcom,sdx 529 compatible = "qcom,sdx75-pcie-anoc";
878 reg = <0x0 0x016c0000 530 reg = <0x0 0x016c0000 0x0 0x14200>;
879 #interconnect-cells = 531 #interconnect-cells = <2>;
880 qcom,bcm-voters = <&ap 532 qcom,bcm-voters = <&apps_bcm_voter>;
881 }; 533 };
882 534
883 tcsr_mutex: hwlock@1f40000 { 535 tcsr_mutex: hwlock@1f40000 {
884 compatible = "qcom,tcs 536 compatible = "qcom,tcsr-mutex";
885 reg = <0x0 0x01f40000 537 reg = <0x0 0x01f40000 0x0 0x40000>;
886 #hwlock-cells = <1>; 538 #hwlock-cells = <1>;
887 }; 539 };
888 540
889 tcsr: syscon@1fc0000 { <<
890 compatible = "qcom,sdx <<
891 reg = <0x0 0x01fc0000 <<
892 }; <<
893 <<
894 remoteproc_mpss: remoteproc@40 <<
895 compatible = "qcom,sdx <<
896 reg = <0 0x04080000 0 <<
897 <<
898 interrupts-extended = <<
899 <<
900 <<
901 <<
902 <<
903 <<
904 interrupt-names = "wdo <<
905 "fat <<
906 "rea <<
907 "han <<
908 "sto <<
909 "shu <<
910 <<
911 clocks = <&rpmhcc RPMH <<
912 clock-names = "xo"; <<
913 <<
914 power-domains = <&rpmh <<
915 <&rpmh <<
916 power-domain-names = " <<
917 " <<
918 <<
919 memory-region = <&mpss <<
920 <&mpss <<
921 <&qlin <<
922 <<
923 qcom,qmp = <&aoss_qmp> <<
924 <<
925 qcom,smem-states = <&s <<
926 qcom,smem-state-names <<
927 <<
928 status = "disabled"; <<
929 <<
930 glink-edge { <<
931 interrupts-ext <<
932 <<
933 <<
934 mboxes = <&ipc <<
935 <<
936 label = "mpss" <<
937 qcom,remote-pi <<
938 }; <<
939 }; <<
940 <<
941 sdhc: mmc@8804000 { <<
942 compatible = "qcom,sdx <<
943 reg = <0x0 0x08804000 <<
944 <<
945 interrupts = <GIC_SPI <<
946 <GIC_SPI <<
947 interrupt-names = "hc_ <<
948 "pwr <<
949 <<
950 clocks = <&gcc GCC_SDC <<
951 <&gcc GCC_SDC <<
952 <&rpmhcc RPMH <<
953 clock-names = "iface", <<
954 "core", <<
955 "xo"; <<
956 iommus = <&apps_smmu 0 <<
957 qcom,dll-config = <0x0 <<
958 qcom,ddr-config = <0x8 <<
959 power-domains = <&rpmh <<
960 operating-points-v2 = <<
961 <<
962 interconnects = <&syst <<
963 <&gem_ <<
964 interconnect-names = " <<
965 " <<
966 bus-width = <4>; <<
967 dma-coherent; <<
968 <<
969 /* Forbid SDR104/SDR50 <<
970 sdhci-caps-mask = <0x3 <<
971 <<
972 status = "disabled"; <<
973 <<
974 sdhc1_opp_table: opp-t <<
975 compatible = " <<
976 <<
977 opp-100000000 <<
978 opp-hz <<
979 requir <<
980 }; <<
981 <<
982 opp-384000000 <<
983 opp-hz <<
984 requir <<
985 }; <<
986 }; <<
987 }; <<
988 <<
989 usb: usb@a6f8800 { 541 usb: usb@a6f8800 {
990 compatible = "qcom,sdx 542 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
991 reg = <0x0 0x0a6f8800 543 reg = <0x0 0x0a6f8800 0x0 0x400>;
992 #address-cells = <2>; 544 #address-cells = <2>;
993 #size-cells = <2>; 545 #size-cells = <2>;
994 ranges; 546 ranges;
995 547
996 clocks = <&gcc GCC_USB 548 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
997 <&gcc GCC_USB 549 <&gcc GCC_USB30_MASTER_CLK>,
998 <&gcc GCC_USB 550 <&gcc GCC_USB30_MSTR_AXI_CLK>,
999 <&gcc GCC_USB 551 <&gcc GCC_USB30_SLEEP_CLK>,
1000 <&gcc GCC_US 552 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1001 clock-names = "cfg_no 553 clock-names = "cfg_noc",
1002 "core", 554 "core",
1003 "iface" 555 "iface",
1004 "sleep" 556 "sleep",
1005 "mock_u 557 "mock_utmi";
1006 558
1007 assigned-clocks = <&g 559 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1008 <&g 560 <&gcc GCC_USB30_MASTER_CLK>;
1009 assigned-clock-rates 561 assigned-clock-rates = <19200000>, <200000000>;
1010 562
1011 interrupts-extended = 563 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1012 564 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1013 565 <&pdc 9 IRQ_TYPE_EDGE_RISING>,
1014 566 <&pdc 10 IRQ_TYPE_EDGE_RISING>;
1015 interrupt-names = "hs 567 interrupt-names = "hs_phy_irq",
1016 "ss 568 "ss_phy_irq",
1017 "dm 569 "dm_hs_phy_irq",
1018 "dp 570 "dp_hs_phy_irq";
1019 571
1020 power-domains = <&gcc 572 power-domains = <&gcc GCC_USB30_GDSC>;
1021 573
1022 resets = <&gcc GCC_US 574 resets = <&gcc GCC_USB30_BCR>;
1023 575
1024 interconnects = <&sys 576 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
1025 &mc_ 577 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1026 <&gem 578 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1027 &sys 579 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
1028 interconnect-names = 580 interconnect-names = "usb-ddr",
1029 581 "apps-usb";
1030 582
1031 status = "disabled"; 583 status = "disabled";
1032 584
1033 usb_dwc3: usb@a600000 585 usb_dwc3: usb@a600000 {
1034 compatible = 586 compatible = "snps,dwc3";
1035 reg = <0x0 0x 587 reg = <0x0 0x0a600000 0x0 0xcd00>;
1036 interrupts = 588 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1037 iommus = <&ap 589 iommus = <&apps_smmu 0x80 0x0>;
1038 snps,dis_u2_s 590 snps,dis_u2_susphy_quirk;
1039 snps,dis_enbl 591 snps,dis_enblslpm_quirk;
1040 phys = <&usb_ 592 phys = <&usb_hsphy>,
1041 <&usb_ 593 <&usb_qmpphy>;
1042 phy-names = " 594 phy-names = "usb2-phy",
1043 " 595 "usb3-phy";
1044 596
1045 ports { 597 ports {
1046 #addr 598 #address-cells = <1>;
1047 #size 599 #size-cells = <0>;
1048 600
1049 port@ 601 port@0 {
1050 602 reg = <0>;
1051 603
1052 604 usb_1_dwc3_hs: endpoint {
1053 605 };
1054 }; 606 };
1055 607
1056 port@ 608 port@1 {
1057 609 reg = <1>;
1058 610
1059 611 usb_1_dwc3_ss: endpoint {
1060 612 };
1061 }; 613 };
1062 }; 614 };
1063 }; 615 };
1064 }; 616 };
1065 617
1066 pdc: interrupt-controller@b22 618 pdc: interrupt-controller@b220000 {
1067 compatible = "qcom,sd 619 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1068 reg = <0x0 0xb220000 620 reg = <0x0 0xb220000 0x0 0x30000>,
1069 <0x0 0x174000f0 621 <0x0 0x174000f0 0x0 0x64>;
1070 qcom,pdc-ranges = <0 622 qcom,pdc-ranges = <0 147 52>,
1071 <52 623 <52 266 32>,
1072 <84 624 <84 500 59>;
1073 #interrupt-cells = <2 625 #interrupt-cells = <2>;
1074 interrupt-parent = <& 626 interrupt-parent = <&intc>;
1075 interrupt-controller; 627 interrupt-controller;
1076 }; 628 };
1077 629
1078 aoss_qmp: power-controller@c3 <<
1079 compatible = "qcom,sd <<
1080 reg = <0 0x0c310000 0 <<
1081 interrupt-parent = <& <<
1082 interrupts-extended = <<
1083 <<
1084 mboxes = <&ipcc IPCC_ <<
1085 <<
1086 #clock-cells = <0>; <<
1087 }; <<
1088 <<
1089 spmi_bus: spmi@c400000 { 630 spmi_bus: spmi@c400000 {
1090 compatible = "qcom,sp 631 compatible = "qcom,spmi-pmic-arb";
1091 reg = <0x0 0x0c400000 632 reg = <0x0 0x0c400000 0x0 0x3000>,
1092 <0x0 0x0c500000 633 <0x0 0x0c500000 0x0 0x400000>,
1093 <0x0 0x0c440000 634 <0x0 0x0c440000 0x0 0x80000>,
1094 <0x0 0x0c4c0000 635 <0x0 0x0c4c0000 0x0 0x10000>,
1095 <0x0 0x0c42d000 636 <0x0 0x0c42d000 0x0 0x4000>;
1096 reg-names = "core", 637 reg-names = "core",
1097 "chnls", 638 "chnls",
1098 "obsrvr", 639 "obsrvr",
1099 "intr", 640 "intr",
1100 "cnfg"; 641 "cnfg";
1101 interrupts-extended = 642 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1102 interrupt-names = "pe 643 interrupt-names = "periph_irq";
1103 qcom,ee = <0>; 644 qcom,ee = <0>;
1104 qcom,channel = <0>; 645 qcom,channel = <0>;
1105 qcom,bus-id = <0>; 646 qcom,bus-id = <0>;
1106 #address-cells = <2>; 647 #address-cells = <2>;
1107 #size-cells = <0>; 648 #size-cells = <0>;
1108 interrupt-controller; 649 interrupt-controller;
1109 #interrupt-cells = <4 650 #interrupt-cells = <4>;
1110 }; 651 };
1111 652
1112 tlmm: pinctrl@f000000 { 653 tlmm: pinctrl@f000000 {
1113 compatible = "qcom,sd 654 compatible = "qcom,sdx75-tlmm";
1114 reg = <0x0 0x0f000000 655 reg = <0x0 0x0f000000 0x0 0x400000>;
1115 interrupts = <GIC_SPI 656 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1116 gpio-controller; 657 gpio-controller;
1117 #gpio-cells = <2>; 658 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm 659 gpio-ranges = <&tlmm 0 0 133>;
1119 interrupt-controller; 660 interrupt-controller;
1120 #interrupt-cells = <2 661 #interrupt-cells = <2>;
1121 wakeup-parent = <&pdc 662 wakeup-parent = <&pdc>;
1122 663
1123 qup_i2c0_data_clk: qu <<
1124 /* SDA, SCL * <<
1125 pins = "gpio8 <<
1126 function = "q <<
1127 drive-strengt <<
1128 bias-pull-up; <<
1129 }; <<
1130 <<
1131 qup_i2c2_data_clk: qu <<
1132 /* SDA, SCL * <<
1133 pins = "gpio1 <<
1134 function = "q <<
1135 drive-strengt <<
1136 bias-pull-up; <<
1137 }; <<
1138 <<
1139 qup_i2c3_data_clk: qu <<
1140 /* SDA, SCL * <<
1141 pins = "gpio5 <<
1142 function = "q <<
1143 drive-strengt <<
1144 bias-pull-up; <<
1145 }; <<
1146 <<
1147 qup_i2c5_data_clk: qu <<
1148 /* SDA, SCL * <<
1149 pins = "gpio1 <<
1150 function = "q <<
1151 drive-strengt <<
1152 bias-pull-up; <<
1153 }; <<
1154 <<
1155 qup_i2c6_data_clk: qu <<
1156 /* SDA, SCL * <<
1157 pins = "gpio1 <<
1158 function = "q <<
1159 drive-strengt <<
1160 bias-pull-up; <<
1161 }; <<
1162 <<
1163 qup_i2c7_data_clk: qu <<
1164 /* SDA, SCL * <<
1165 pins = "gpio1 <<
1166 function = "q <<
1167 drive-strengt <<
1168 bias-pull-up; <<
1169 }; <<
1170 <<
1171 qup_spi0_cs: qup-spi0 <<
1172 pins = "gpio1 <<
1173 function = "q <<
1174 drive-strengt <<
1175 bias-pull-dow <<
1176 }; <<
1177 <<
1178 qup_spi0_data_clk: qu <<
1179 /* MISO, MOSI <<
1180 pins = "gpio8 <<
1181 function = "q <<
1182 drive-strengt <<
1183 bias-pull-dow <<
1184 }; <<
1185 <<
1186 qup_spi2_cs: qup-spi2 <<
1187 pins = "gpio1 <<
1188 function = "q <<
1189 drive-strengt <<
1190 bias-pull-dow <<
1191 }; <<
1192 <<
1193 qup_spi2_data_clk: qu <<
1194 /* MISO, MOSI <<
1195 pins = "gpio1 <<
1196 function = "q <<
1197 drive-strengt <<
1198 bias-pull-dow <<
1199 }; <<
1200 <<
1201 qup_spi3_cs: qup-spi3 <<
1202 pins = "gpio5 <<
1203 function = "q <<
1204 drive-strengt <<
1205 bias-pull-dow <<
1206 }; <<
1207 <<
1208 qup_spi3_data_clk: qu <<
1209 /* MISO, MOSI <<
1210 pins = "gpio5 <<
1211 function = "q <<
1212 drive-strengt <<
1213 bias-pull-dow <<
1214 }; <<
1215 <<
1216 qup_spi6_cs: qup-spi6 <<
1217 pins = "gpio1 <<
1218 function = "q <<
1219 drive-strengt <<
1220 bias-pull-dow <<
1221 }; <<
1222 <<
1223 qup_spi6_data_clk: qu <<
1224 /* MISO, MOSI <<
1225 pins = "gpio1 <<
1226 function = "q <<
1227 drive-strengt <<
1228 bias-pull-dow <<
1229 }; <<
1230 <<
1231 qup_spi7_cs: qup-spi7 <<
1232 pins = "gpio1 <<
1233 function = "q <<
1234 drive-strengt <<
1235 bias-pull-dow <<
1236 }; <<
1237 <<
1238 qup_spi7_data_clk: qu <<
1239 /* MISO, MOSI <<
1240 pins = "gpio1 <<
1241 function = "q <<
1242 drive-strengt <<
1243 bias-pull-dow <<
1244 }; <<
1245 <<
1246 qup_uart4_cts_rts: qu <<
1247 /* CTS, RTS * <<
1248 pins = "gpio5 <<
1249 function = "q <<
1250 drive-strengt <<
1251 bias-pull-dow <<
1252 }; <<
1253 <<
1254 qup_uart4_default: qu <<
1255 /* TX, RX */ <<
1256 pins = "gpio5 <<
1257 function = "q <<
1258 drive-strengt <<
1259 bias-pull-up; <<
1260 }; <<
1261 <<
1262 qupv3_se1_2uart_activ 664 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1263 tx-pins { 665 tx-pins {
1264 pins 666 pins = "gpio12";
1265 funct 667 function = "qup_se1_l2_mira";
1266 drive 668 drive-strength = <2>;
1267 bias- 669 bias-disable;
1268 }; 670 };
1269 671
1270 rx-pins { 672 rx-pins {
1271 pins 673 pins = "gpio13";
1272 funct 674 function = "qup_se1_l3_mira";
1273 drive 675 drive-strength = <2>;
1274 bias- 676 bias-disable;
1275 }; 677 };
1276 }; 678 };
1277 679
1278 qupv3_se1_2uart_sleep 680 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1279 pins = "gpio1 681 pins = "gpio12", "gpio13";
1280 function = "g 682 function = "gpio";
1281 drive-strengt 683 drive-strength = <2>;
1282 bias-pull-dow 684 bias-pull-down;
1283 }; <<
1284 <<
1285 sdc1_default: sdc1-de <<
1286 clk-pins { <<
1287 pins <<
1288 drive <<
1289 bias- <<
1290 }; <<
1291 <<
1292 cmd-pins { <<
1293 pins <<
1294 drive <<
1295 bias- <<
1296 }; <<
1297 <<
1298 data-pins { <<
1299 pins <<
1300 drive <<
1301 bias- <<
1302 }; <<
1303 }; <<
1304 <<
1305 sdc1_sleep: sdc1-slee <<
1306 clk-pins { <<
1307 pins <<
1308 drive <<
1309 bias- <<
1310 }; <<
1311 <<
1312 cmd-pins { <<
1313 pins <<
1314 drive <<
1315 bias- <<
1316 }; <<
1317 <<
1318 data-pins { <<
1319 pins <<
1320 drive <<
1321 bias- <<
1322 }; <<
1323 }; 685 };
1324 }; 686 };
1325 687
1326 apps_smmu: iommu@15000000 { 688 apps_smmu: iommu@15000000 {
1327 compatible = "qcom,sd 689 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1328 reg = <0x0 0x15000000 690 reg = <0x0 0x15000000 0x0 0x40000>;
1329 #iommu-cells = <2>; 691 #iommu-cells = <2>;
1330 #global-interrupts = 692 #global-interrupts = <2>;
1331 dma-coherent; 693 dma-coherent;
1332 interrupts = <GIC_SPI 694 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 695 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 696 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 697 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 698 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 699 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 700 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 701 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 702 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 703 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 704 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 705 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 706 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 707 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 708 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 709 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 710 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 711 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 712 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 713 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 714 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 715 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 716 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 717 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 718 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 719 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 720 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 721 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 722 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 723 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 724 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 725 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 726 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1365 }; 727 };
1366 728
1367 intc: interrupt-controller@17 729 intc: interrupt-controller@17200000 {
1368 compatible = "arm,gic 730 compatible = "arm,gic-v3";
1369 #interrupt-cells = <3 731 #interrupt-cells = <3>;
1370 interrupt-controller; 732 interrupt-controller;
1371 #redistributor-region 733 #redistributor-regions = <1>;
1372 redistributor-stride 734 redistributor-stride = <0x0 0x20000>;
1373 reg = <0x0 0x17200000 735 reg = <0x0 0x17200000 0x0 0x10000>,
1374 <0x0 0x17260000 736 <0x0 0x17260000 0x0 0x80000>;
1375 interrupts = <GIC_PPI 737 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1376 }; 738 };
1377 739
1378 timer@17420000 { 740 timer@17420000 {
1379 compatible = "arm,arm 741 compatible = "arm,armv7-timer-mem";
1380 reg = <0x0 0x17420000 742 reg = <0x0 0x17420000 0x0 0x1000>;
1381 #address-cells = <1>; 743 #address-cells = <1>;
1382 #size-cells = <1>; 744 #size-cells = <1>;
1383 ranges = <0 0 0 0x200 745 ranges = <0 0 0 0x20000000>;
1384 746
1385 frame@17421000 { 747 frame@17421000 {
1386 reg = <0x1742 748 reg = <0x17421000 0x1000>,
1387 <0x1742 749 <0x17422000 0x1000>;
1388 frame-number 750 frame-number = <0>;
1389 interrupts = 751 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1390 752 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1391 }; 753 };
1392 754
1393 frame@17423000 { 755 frame@17423000 {
1394 reg = <0x1742 756 reg = <0x17423000 0x1000>;
1395 frame-number 757 frame-number = <1>;
1396 interrupts = 758 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1397 status = "dis 759 status = "disabled";
1398 }; 760 };
1399 761
1400 frame@17425000 { 762 frame@17425000 {
1401 reg = <0x1742 763 reg = <0x17425000 0x1000>;
1402 frame-number 764 frame-number = <2>;
1403 interrupts = 765 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1404 status = "dis 766 status = "disabled";
1405 }; 767 };
1406 768
1407 frame@17427000 { 769 frame@17427000 {
1408 reg = <0x1742 770 reg = <0x17427000 0x1000>;
1409 frame-number 771 frame-number = <3>;
1410 interrupts = 772 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1411 status = "dis 773 status = "disabled";
1412 }; 774 };
1413 775
1414 frame@17429000 { 776 frame@17429000 {
1415 reg = <0x1742 777 reg = <0x17429000 0x1000>;
1416 frame-number 778 frame-number = <4>;
1417 interrupts = 779 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1418 status = "dis 780 status = "disabled";
1419 }; 781 };
1420 782
1421 frame@1742b000 { 783 frame@1742b000 {
1422 reg = <0x1742 784 reg = <0x1742b000 0x1000>;
1423 frame-number 785 frame-number = <5>;
1424 interrupts = 786 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1425 status = "dis 787 status = "disabled";
1426 }; 788 };
1427 789
1428 frame@1742d000 { 790 frame@1742d000 {
1429 reg = <0x1742 791 reg = <0x1742d000 0x1000>;
1430 frame-number 792 frame-number = <6>;
1431 interrupts = 793 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1432 status = "dis 794 status = "disabled";
1433 }; 795 };
1434 }; 796 };
1435 797
1436 apps_rsc: rsc@17a00000 { 798 apps_rsc: rsc@17a00000 {
1437 label = "apps_rsc"; 799 label = "apps_rsc";
1438 compatible = "qcom,rp 800 compatible = "qcom,rpmh-rsc";
1439 reg = <0x0 0x17a00000 801 reg = <0x0 0x17a00000 0x0 0x10000>,
1440 <0x0 0x17a10000 802 <0x0 0x17a10000 0x0 0x10000>,
1441 <0x0 0x17a20000 803 <0x0 0x17a20000 0x0 0x10000>;
1442 reg-names = "drv-0", 804 reg-names = "drv-0", "drv-1", "drv-2";
1443 interrupts = <GIC_SPI 805 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 806 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 807 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1446 808
1447 power-domains = <&CLU 809 power-domains = <&CLUSTER_PD>;
1448 qcom,tcs-offset = <0x 810 qcom,tcs-offset = <0xd00>;
1449 qcom,drv-id = <2>; 811 qcom,drv-id = <2>;
1450 qcom,tcs-config = <AC 812 qcom,tcs-config = <ACTIVE_TCS 3>,
1451 <SL 813 <SLEEP_TCS 2>,
1452 <WA 814 <WAKE_TCS 2>,
1453 <CO 815 <CONTROL_TCS 0>;
1454 816
1455 apps_bcm_voter: bcm-v 817 apps_bcm_voter: bcm-voter {
1456 compatible = 818 compatible = "qcom,bcm-voter";
1457 }; 819 };
1458 820
1459 rpmhcc: clock-control 821 rpmhcc: clock-controller {
1460 compatible = 822 compatible = "qcom,sdx75-rpmh-clk";
1461 clocks = <&xo 823 clocks = <&xo_board>;
1462 clock-names = 824 clock-names = "xo";
1463 #clock-cells 825 #clock-cells = <1>;
1464 }; 826 };
1465 827
1466 rpmhpd: power-control 828 rpmhpd: power-controller {
1467 compatible = 829 compatible = "qcom,sdx75-rpmhpd";
1468 #power-domain 830 #power-domain-cells = <1>;
1469 operating-poi 831 operating-points-v2 = <&rpmhpd_opp_table>;
1470 832
1471 rpmhpd_opp_ta 833 rpmhpd_opp_table: opp-table {
1472 compa 834 compatible = "operating-points-v2";
1473 835
1474 rpmhp 836 rpmhpd_opp_ret: opp-16 {
1475 837 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1476 }; 838 };
1477 839
1478 rpmhp 840 rpmhpd_opp_min_svs: opp-48 {
1479 841 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1480 }; 842 };
1481 843
1482 rpmhp 844 rpmhpd_opp_low_svs: opp-64 {
1483 845 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1484 }; 846 };
1485 847
1486 rpmhp 848 rpmhpd_opp_svs: opp-128 {
1487 849 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1488 }; 850 };
1489 851
1490 rpmhp 852 rpmhpd_opp_svs_l1: opp-192 {
1491 853 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1492 }; 854 };
1493 855
1494 rpmhp 856 rpmhpd_opp_nom: opp-256 {
1495 857 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1496 }; 858 };
1497 859
1498 rpmhp 860 rpmhpd_opp_nom_l1: opp-320 {
1499 861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1500 }; 862 };
1501 863
1502 rpmhp 864 rpmhpd_opp_nom_l2: opp-336 {
1503 865 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1504 }; 866 };
1505 867
1506 rpmhp 868 rpmhpd_opp_turbo: opp-384 {
1507 869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1508 }; 870 };
1509 871
1510 rpmhp 872 rpmhpd_opp_turbo_l1: opp-416 {
1511 873 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1512 }; 874 };
1513 }; 875 };
1514 }; 876 };
1515 }; 877 };
1516 878
1517 cpufreq_hw: cpufreq@17d91000 879 cpufreq_hw: cpufreq@17d91000 {
1518 compatible = "qcom,sd 880 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1519 reg = <0x0 0x17d91000 881 reg = <0x0 0x17d91000 0x0 0x1000>;
1520 reg-names = "freq-dom 882 reg-names = "freq-domain0";
1521 clocks = <&rpmhcc RPM 883 clocks = <&rpmhcc RPMH_CXO_CLK>,
1522 <&gcc GPLL0> 884 <&gcc GPLL0>;
1523 clock-names = "xo", 885 clock-names = "xo",
1524 "altern 886 "alternate";
1525 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1526 interrupt-names = "dc 888 interrupt-names = "dcvsh-irq-0";
1527 #freq-domain-cells = 889 #freq-domain-cells = <1>;
1528 #clock-cells = <1>; 890 #clock-cells = <1>;
1529 }; 891 };
1530 892
1531 dc_noc: interconnect@190e0000 893 dc_noc: interconnect@190e0000 {
1532 compatible = "qcom,sd 894 compatible = "qcom,sdx75-dc-noc";
1533 reg = <0x0 0x190e0000 895 reg = <0x0 0x190e0000 0x0 0x8200>;
1534 #interconnect-cells = 896 #interconnect-cells = <2>;
1535 qcom,bcm-voters = <&a 897 qcom,bcm-voters = <&apps_bcm_voter>;
1536 }; 898 };
1537 899
1538 gem_noc: interconnect@1910000 900 gem_noc: interconnect@19100000 {
1539 compatible = "qcom,sd 901 compatible = "qcom,sdx75-gem-noc";
1540 reg = <0x0 0x19100000 902 reg = <0x0 0x19100000 0x0 0x34080>;
1541 #interconnect-cells = 903 #interconnect-cells = <2>;
1542 qcom,bcm-voters = <&a 904 qcom,bcm-voters = <&apps_bcm_voter>;
1543 }; 905 };
1544 }; 906 };
1545 907
1546 timer { 908 timer {
1547 compatible = "arm,armv8-timer 909 compatible = "arm,armv8-timer";
1548 interrupts = <GIC_PPI 13 (GIC 910 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1549 <GIC_PPI 14 (GIC 911 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1550 <GIC_PPI 11 (GIC 912 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1551 <GIC_PPI 12 (GIC 913 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1552 }; 914 };
1553 }; 915 };
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