1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SDX75 SoC device tree source 3 * SDX75 SoC device tree source
4 * 4 *
5 * Copyright (c) 2023 Qualcomm Innovation Cent 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,rpmh.h> 9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h> 10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h> 13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75. 14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm 15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> 16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h> 17 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 20
21 / { 21 / {
22 #address-cells = <2>; 22 #address-cells = <2>;
23 #size-cells = <2>; 23 #size-cells = <2>;
24 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
25 25
26 chosen: chosen { }; 26 chosen: chosen { };
27 27
28 clocks { 28 clocks {
29 xo_board: xo-board { 29 xo_board: xo-board {
30 compatible = "fixed-cl 30 compatible = "fixed-clock";
31 clock-frequency = <768 31 clock-frequency = <76800000>;
32 #clock-cells = <0>; 32 #clock-cells = <0>;
33 }; 33 };
34 34
35 sleep_clk: sleep-clk { 35 sleep_clk: sleep-clk {
36 compatible = "fixed-cl 36 compatible = "fixed-clock";
37 clock-frequency = <320 37 clock-frequency = <32000>;
38 #clock-cells = <0>; 38 #clock-cells = <0>;
39 }; 39 };
40 }; 40 };
41 41
42 cpus { 42 cpus {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 45
46 CPU0: cpu@0 { 46 CPU0: cpu@0 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cort 48 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 50 clocks = <&cpufreq_hw 0>;
51 enable-method = "psci" 51 enable-method = "psci";
52 power-domains = <&CPU_ 52 power-domains = <&CPU_PD0>;
53 power-domain-names = " 53 power-domain-names = "psci";
54 qcom,freq-domain = <&c 54 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = < 55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coeffici 56 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L 57 next-level-cache = <&L2_0>;
58 58
59 L2_0: l2-cache { 59 L2_0: l2-cache {
60 compatible = " 60 compatible = "cache";
61 cache-level = 61 cache-level = <2>;
62 cache-unified; 62 cache-unified;
63 next-level-cac 63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache 64 L3_0: l3-cache {
65 compat 65 compatible = "cache";
66 cache- 66 cache-level = <3>;
67 cache- 67 cache-unified;
68 }; 68 };
69 }; 69 };
70 }; 70 };
71 71
72 CPU1: cpu@100 { 72 CPU1: cpu@100 {
73 device_type = "cpu"; 73 device_type = "cpu";
74 compatible = "arm,cort 74 compatible = "arm,cortex-a55";
75 reg = <0x0 0x100>; 75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 76 clocks = <&cpufreq_hw 0>;
77 enable-method = "psci" 77 enable-method = "psci";
78 power-domains = <&CPU_ 78 power-domains = <&CPU_PD1>;
79 power-domain-names = " 79 power-domain-names = "psci";
80 qcom,freq-domain = <&c 80 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = < 81 capacity-dmips-mhz = <1024>;
82 dynamic-power-coeffici 82 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L 83 next-level-cache = <&L2_100>;
84 84
85 L2_100: l2-cache { 85 L2_100: l2-cache {
86 compatible = " 86 compatible = "cache";
87 cache-level = 87 cache-level = <2>;
88 cache-unified; 88 cache-unified;
89 next-level-cac 89 next-level-cache = <&L3_0>;
90 }; 90 };
91 }; 91 };
92 92
93 CPU2: cpu@200 { 93 CPU2: cpu@200 {
94 device_type = "cpu"; 94 device_type = "cpu";
95 compatible = "arm,cort 95 compatible = "arm,cortex-a55";
96 reg = <0x0 0x200>; 96 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 97 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci" 98 enable-method = "psci";
99 power-domains = <&CPU_ 99 power-domains = <&CPU_PD2>;
100 power-domain-names = " 100 power-domain-names = "psci";
101 qcom,freq-domain = <&c 101 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = < 102 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici 103 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L 104 next-level-cache = <&L2_200>;
105 105
106 L2_200: l2-cache { 106 L2_200: l2-cache {
107 compatible = " 107 compatible = "cache";
108 cache-level = 108 cache-level = <2>;
109 cache-unified; 109 cache-unified;
110 next-level-cac 110 next-level-cache = <&L3_0>;
111 }; 111 };
112 }; 112 };
113 113
114 CPU3: cpu@300 { 114 CPU3: cpu@300 {
115 device_type = "cpu"; 115 device_type = "cpu";
116 compatible = "arm,cort 116 compatible = "arm,cortex-a55";
117 reg = <0x0 0x300>; 117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 118 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci" 119 enable-method = "psci";
120 power-domains = <&CPU_ 120 power-domains = <&CPU_PD3>;
121 power-domain-names = " 121 power-domain-names = "psci";
122 qcom,freq-domain = <&c 122 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = < 123 capacity-dmips-mhz = <1024>;
124 dynamic-power-coeffici 124 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L 125 next-level-cache = <&L2_300>;
126 126
127 L2_300: l2-cache { 127 L2_300: l2-cache {
128 compatible = " 128 compatible = "cache";
129 cache-level = 129 cache-level = <2>;
130 cache-unified; 130 cache-unified;
131 next-level-cac 131 next-level-cache = <&L3_0>;
132 }; 132 };
133 }; 133 };
134 134
135 cpu-map { 135 cpu-map {
136 cluster0 { 136 cluster0 {
137 core0 { 137 core0 {
138 cpu = 138 cpu = <&CPU0>;
139 }; 139 };
140 140
141 core1 { 141 core1 {
142 cpu = 142 cpu = <&CPU1>;
143 }; 143 };
144 144
145 core2 { 145 core2 {
146 cpu = 146 cpu = <&CPU2>;
147 }; 147 };
148 148
149 core3 { 149 core3 {
150 cpu = 150 cpu = <&CPU3>;
151 }; 151 };
152 }; 152 };
153 }; 153 };
154 154
155 idle-states { 155 idle-states {
156 entry-method = "psci"; 156 entry-method = "psci";
157 157
158 CPU_OFF: cpu-sleep-0 { 158 CPU_OFF: cpu-sleep-0 {
159 compatible = " 159 compatible = "arm,idle-state";
160 entry-latency- 160 entry-latency-us = <235>;
161 exit-latency-u 161 exit-latency-us = <428>;
162 min-residency- 162 min-residency-us = <1774>;
163 arm,psci-suspe 163 arm,psci-suspend-param = <0x40000003>;
164 local-timer-st 164 local-timer-stop;
165 }; 165 };
166 166
167 CPU_RAIL_OFF: cpu-rail 167 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = " 168 compatible = "arm,idle-state";
169 entry-latency- 169 entry-latency-us = <800>;
170 exit-latency-u 170 exit-latency-us = <750>;
171 min-residency- 171 min-residency-us = <4090>;
172 arm,psci-suspe 172 arm,psci-suspend-param = <0x40000004>;
173 local-timer-st 173 local-timer-stop;
174 }; 174 };
175 175
176 }; 176 };
177 177
178 domain-idle-states { 178 domain-idle-states {
179 CLUSTER_SLEEP_0: clust 179 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = " 180 compatible = "domain-idle-state";
181 arm,psci-suspe 181 arm,psci-suspend-param = <0x41000044>;
182 entry-latency- 182 entry-latency-us = <1050>;
183 exit-latency-u 183 exit-latency-us = <2500>;
184 min-residency- 184 min-residency-us = <5309>;
185 }; 185 };
186 186
187 CLUSTER_SLEEP_1: clust 187 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = " 188 compatible = "domain-idle-state";
189 arm,psci-suspe 189 arm,psci-suspend-param = <0x41001344>;
190 entry-latency- 190 entry-latency-us = <2761>;
191 exit-latency-u 191 exit-latency-us = <3964>;
192 min-residency- 192 min-residency-us = <8467>;
193 }; 193 };
194 194
195 CLUSTER_SLEEP_2: clust 195 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = " 196 compatible = "domain-idle-state";
197 arm,psci-suspe 197 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency- 198 entry-latency-us = <2793>;
199 exit-latency-u 199 exit-latency-us = <4023>;
200 min-residency- 200 min-residency-us = <9826>;
201 }; 201 };
202 }; 202 };
203 }; 203 };
204 204
205 firmware { 205 firmware {
206 scm: scm { 206 scm: scm {
207 compatible = "qcom,scm 207 compatible = "qcom,scm-sdx75", "qcom,scm";
208 }; 208 };
209 }; 209 };
210 210
211 clk_virt: interconnect-0 { 211 clk_virt: interconnect-0 {
212 compatible = "qcom,sdx75-clk-v 212 compatible = "qcom,sdx75-clk-virt";
213 #interconnect-cells = <2>; 213 #interconnect-cells = <2>;
214 qcom,bcm-voters = <&apps_bcm_v 214 qcom,bcm-voters = <&apps_bcm_voter>;
215 clocks = <&rpmhcc RPMH_QPIC_CL 215 clocks = <&rpmhcc RPMH_QPIC_CLK>;
216 }; 216 };
217 217
218 mc_virt: interconnect-1 { 218 mc_virt: interconnect-1 {
219 compatible = "qcom,sdx75-mc-vi 219 compatible = "qcom,sdx75-mc-virt";
220 #interconnect-cells = <2>; 220 #interconnect-cells = <2>;
221 qcom,bcm-voters = <&apps_bcm_v 221 qcom,bcm-voters = <&apps_bcm_voter>;
222 }; 222 };
223 223
224 memory@80000000 { 224 memory@80000000 {
225 device_type = "memory"; 225 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0> 226 reg = <0x0 0x80000000 0x0 0x0>;
227 }; 227 };
228 228
229 pmu { 229 pmu {
230 compatible = "arm,cortex-a55-p 230 compatible = "arm,cortex-a55-pmu";
231 interrupts = <GIC_PPI 7 IRQ_TY 231 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 }; 232 };
233 233
234 psci { 234 psci {
235 compatible = "arm,psci-1.0"; 235 compatible = "arm,psci-1.0";
236 method = "smc"; 236 method = "smc";
237 237
238 CPU_PD0: power-domain-cpu0 { 238 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = 239 #power-domain-cells = <0>;
240 power-domains = <&CLUS 240 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = < 241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
242 }; 242 };
243 243
244 CPU_PD1: power-domain-cpu1 { 244 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = 245 #power-domain-cells = <0>;
246 power-domains = <&CLUS 246 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = < 247 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
248 }; 248 };
249 249
250 CPU_PD2: power-domain-cpu2 { 250 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = 251 #power-domain-cells = <0>;
252 power-domains = <&CLUS 252 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = < 253 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
254 }; 254 };
255 255
256 CPU_PD3: power-domain-cpu3 { 256 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = 257 #power-domain-cells = <0>;
258 power-domains = <&CLUS 258 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = < 259 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
260 }; 260 };
261 261
262 CLUSTER_PD: power-domain-cpu-c 262 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = 263 #power-domain-cells = <0>;
264 domain-idle-states = < 264 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 }; 265 };
266 }; 266 };
267 267
268 reserved-memory { 268 reserved-memory {
269 #address-cells = <2>; 269 #address-cells = <2>;
270 #size-cells = <2>; 270 #size-cells = <2>;
271 ranges; 271 ranges;
272 272
273 gunyah_hyp_mem: gunyah-hyp@800 273 gunyah_hyp_mem: gunyah-hyp@80000000 {
274 reg = <0x0 0x80000000 274 reg = <0x0 0x80000000 0x0 0x800000>;
275 no-map; 275 no-map;
276 }; 276 };
277 277
278 hyp_elf_package_mem: hyp-elf-p 278 hyp_elf_package_mem: hyp-elf-package@80800000 {
279 reg = <0x0 0x80800000 279 reg = <0x0 0x80800000 0x0 0x200000>;
280 no-map; 280 no-map;
281 }; 281 };
282 282
283 access_control_db_mem: access- 283 access_control_db_mem: access-control-db@81380000 {
284 reg = <0x0 0x81380000 284 reg = <0x0 0x81380000 0x0 0x80000>;
285 no-map; 285 no-map;
286 }; 286 };
287 287
288 qteetz_mem: qteetz@814e0000 { 288 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000 289 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 no-map; 290 no-map;
291 }; 291 };
292 292
293 trusted_apps_mem: trusted-apps 293 trusted_apps_mem: trusted-apps@81780000 {
294 reg = <0x0 0x81780000 294 reg = <0x0 0x81780000 0x0 0xa00000>;
295 no-map; 295 no-map;
296 }; 296 };
297 297
298 xbl_ramdump_mem: xbl-ramdump@8 298 xbl_ramdump_mem: xbl-ramdump@87a00000 {
299 reg = <0x0 0x87a00000 299 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 no-map; 300 no-map;
301 }; 301 };
302 302
303 cpucp_fw_mem: cpucp-fw@87c0000 303 cpucp_fw_mem: cpucp-fw@87c00000 {
304 reg = <0x0 0x87c00000 304 reg = <0x0 0x87c00000 0x0 0x100000>;
305 no-map; 305 no-map;
306 }; 306 };
307 307
308 xbl_dtlog_mem: xbl-dtlog@87d00 308 xbl_dtlog_mem: xbl-dtlog@87d00000 {
309 reg = <0x0 0x87d00000 309 reg = <0x0 0x87d00000 0x0 0x40000>;
310 no-map; 310 no-map;
311 }; 311 };
312 312
313 xbl_sc_mem: xbl-sc@87d40000 { 313 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000 314 reg = <0x0 0x87d40000 0x0 0x40000>;
315 no-map; 315 no-map;
316 }; 316 };
317 317
318 modem_efs_shared_mem: modem-ef 318 modem_efs_shared_mem: modem-efs-shared@87d80000 {
319 reg = <0x0 0x87d80000 319 reg = <0x0 0x87d80000 0x0 0x10000>;
320 no-map; 320 no-map;
321 }; 321 };
322 322
323 aop_image_mem: aop-image@87e00 323 aop_image_mem: aop-image@87e00000 {
324 reg = <0x0 0x87e00000 324 reg = <0x0 0x87e00000 0x0 0x20000>;
325 no-map; 325 no-map;
326 }; 326 };
327 327
328 smem_mem: smem@87e20000 { 328 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000 329 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 no-map; 330 no-map;
331 }; 331 };
332 332
333 aop_cmd_db_mem: aop-cmd-db@87e 333 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd 334 compatible = "qcom,cmd-db";
335 reg = <0x0 0x87ee0000 335 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 no-map; 336 no-map;
337 }; 337 };
338 338
339 aop_config_mem: aop-config@87f 339 aop_config_mem: aop-config@87f00000 {
340 reg = <0x0 0x87f00000 340 reg = <0x0 0x87f00000 0x0 0x20000>;
341 no-map; 341 no-map;
342 }; 342 };
343 343
344 ipa_fw_mem: ipa-fw@87f20000 { 344 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000 345 reg = <0x0 0x87f20000 0x0 0x10000>;
346 no-map; 346 no-map;
347 }; 347 };
348 348
349 secdata_mem: secdata@87f30000 349 secdata_mem: secdata@87f30000 {
350 reg = <0x0 0x87f30000 350 reg = <0x0 0x87f30000 0x0 0x1000>;
351 no-map; 351 no-map;
352 }; 352 };
353 353
354 tme_crashdump_mem: tme-crashdu 354 tme_crashdump_mem: tme-crashdump@87f31000 {
355 reg = <0x0 0x87f31000 355 reg = <0x0 0x87f31000 0x0 0x40000>;
356 no-map; 356 no-map;
357 }; 357 };
358 358
359 tme_log_mem: tme-log@87f71000 359 tme_log_mem: tme-log@87f71000 {
360 reg = <0x0 0x87f71000 360 reg = <0x0 0x87f71000 0x0 0x4000>;
361 no-map; 361 no-map;
362 }; 362 };
363 363
364 uefi_log_mem: uefi-log@87f7500 364 uefi_log_mem: uefi-log@87f75000 {
365 reg = <0x0 0x87f75000 365 reg = <0x0 0x87f75000 0x0 0x10000>;
366 no-map; 366 no-map;
367 }; 367 };
368 368
369 qdss_mem: qdss@88500000 { !! 369 qdss_mem: qdss@88800000 {
370 reg = <0x0 0x88500000 <<
371 no-map; <<
372 }; <<
373 <<
374 qlink_logging_mem: qlink-loggi <<
375 reg = <0x0 0x88800000 370 reg = <0x0 0x88800000 0x0 0x300000>;
376 no-map; 371 no-map;
377 }; 372 };
378 373
379 audio_heap_mem: audio-heap@88b 374 audio_heap_mem: audio-heap@88b00000 {
380 compatible = "shared-d 375 compatible = "shared-dma-pool";
381 reg = <0x0 0x88b00000 376 reg = <0x0 0x88b00000 0x0 0x400000>;
382 no-map; 377 no-map;
383 }; 378 };
384 379
385 mpss_dsm_mem_2: mpss-dsm-2@88f !! 380 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
386 reg = <0x0 0x88f00000 !! 381 reg = <0x0 0x88f00000 0x0 0x5080000>;
387 no-map; <<
388 }; <<
389 <<
390 mpss_dsm_mem: mpss-dsm@8b40000 <<
391 reg = <0x0 0x8b400000 <<
392 no-map; 382 no-map;
393 }; 383 };
394 384
395 q6_mpss_dtb_mem: q6-mpss-dtb@8 385 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
396 reg = <0x0 0x8df80000 386 reg = <0x0 0x8df80000 0x0 0x80000>;
397 no-map; 387 no-map;
398 }; 388 };
399 389
400 mpssadsp_mem: mpssadsp@8e00000 390 mpssadsp_mem: mpssadsp@8e000000 {
401 reg = <0x0 0x8e000000 !! 391 reg = <0x0 0x8e000000 0x0 0xf400000>;
402 no-map; 392 no-map;
403 }; 393 };
404 394
405 gunyah_trace_buffer_mem: gunya 395 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
406 reg = <0x0 0xbdb00000 396 reg = <0x0 0xbdb00000 0x0 0x2000000>;
407 no-map; 397 no-map;
408 }; 398 };
409 399
410 smmu_debug_buf_mem: smmu-debug 400 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
411 reg = <0x0 0xbfb00000 401 reg = <0x0 0xbfb00000 0x0 0x100000>;
412 no-map; 402 no-map;
413 }; 403 };
414 404
415 hyp_smmu_s2_pt_mem: hyp-smmu-s 405 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
416 reg = <0x0 0xbfc00000 406 reg = <0x0 0xbfc00000 0x0 0x400000>;
417 no-map; 407 no-map;
418 }; 408 };
419 }; 409 };
420 410
421 smp2p-modem { 411 smp2p-modem {
422 compatible = "qcom,smp2p"; 412 compatible = "qcom,smp2p";
423 qcom,smem = <435>, <428>; 413 qcom,smem = <435>, <428>;
424 interrupts-extended = <&ipcc I 414 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
425 I 415 IPCC_MPROC_SIGNAL_SMP2P
426 I 416 IRQ_TYPE_EDGE_RISING>;
427 mboxes = <&ipcc IPCC_CLIENT_MP 417 mboxes = <&ipcc IPCC_CLIENT_MPSS
428 IPCC_MPROC_SIG 418 IPCC_MPROC_SIGNAL_SMP2P>;
429 419
430 qcom,local-pid = <0>; 420 qcom,local-pid = <0>;
431 qcom,remote-pid = <1>; 421 qcom,remote-pid = <1>;
432 422
433 smp2p_modem_out: master-kernel 423 smp2p_modem_out: master-kernel {
434 qcom,entry-name = "mas 424 qcom,entry-name = "master-kernel";
435 #qcom,smem-state-cells 425 #qcom,smem-state-cells = <1>;
436 }; 426 };
437 427
438 smp2p_modem_in: slave-kernel { 428 smp2p_modem_in: slave-kernel {
439 qcom,entry-name = "sla 429 qcom,entry-name = "slave-kernel";
440 interrupt-controller; 430 interrupt-controller;
441 #interrupt-cells = <2> 431 #interrupt-cells = <2>;
442 }; 432 };
443 433
444 ipa_smp2p_out: ipa-ap-to-modem 434 ipa_smp2p_out: ipa-ap-to-modem {
445 qcom,entry-name = "ipa 435 qcom,entry-name = "ipa";
446 #qcom,smem-state-cells 436 #qcom,smem-state-cells = <1>;
447 }; 437 };
448 438
449 ipa_smp2p_in: ipa-modem-to-ap 439 ipa_smp2p_in: ipa-modem-to-ap {
450 qcom,entry-name = "ipa 440 qcom,entry-name = "ipa";
451 interrupt-controller; 441 interrupt-controller;
452 #interrupt-cells = <2> 442 #interrupt-cells = <2>;
453 }; 443 };
454 }; 444 };
455 445
456 smem: smem { 446 smem: smem {
457 compatible = "qcom,smem"; 447 compatible = "qcom,smem";
458 memory-region = <&smem_mem>; 448 memory-region = <&smem_mem>;
459 hwlocks = <&tcsr_mutex 3>; 449 hwlocks = <&tcsr_mutex 3>;
460 }; 450 };
461 451
462 soc: soc@0 { 452 soc: soc@0 {
463 compatible = "simple-bus"; 453 compatible = "simple-bus";
464 #address-cells = <2>; 454 #address-cells = <2>;
465 #size-cells = <2>; 455 #size-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>; 456 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>; 457 dma-ranges = <0 0 0 0 0x10 0>;
468 458
469 gcc: clock-controller@80000 { 459 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx 460 compatible = "qcom,sdx75-gcc";
471 reg = <0x0 0x0080000 0 461 reg = <0x0 0x0080000 0x0 0x1f7400>;
472 clocks = <&rpmhcc RPMH 462 clocks = <&rpmhcc RPMH_CXO_CLK>,
473 <&sleep_clk>, 463 <&sleep_clk>,
474 <0>, 464 <0>,
475 <0>, 465 <0>,
476 <0>, 466 <0>,
477 <0>, 467 <0>,
478 <0>, 468 <0>,
479 <0>, 469 <0>,
480 <0>, 470 <0>,
481 <0>, 471 <0>,
482 <0>, 472 <0>,
483 <0>, 473 <0>,
484 <0>, 474 <0>,
485 <0>, 475 <0>,
486 <0>; 476 <0>;
487 #clock-cells = <1>; 477 #clock-cells = <1>;
488 #reset-cells = <1>; 478 #reset-cells = <1>;
489 #power-domain-cells = 479 #power-domain-cells = <1>;
490 }; 480 };
491 481
492 ipcc: mailbox@408000 { 482 ipcc: mailbox@408000 {
493 compatible = "qcom,sdx 483 compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
494 reg = <0 0x00408000 0 484 reg = <0 0x00408000 0 0x1000>;
495 interrupts = <GIC_SPI 485 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-controller; 486 interrupt-controller;
497 #interrupt-cells = <3> 487 #interrupt-cells = <3>;
498 #mbox-cells = <2>; 488 #mbox-cells = <2>;
499 }; 489 };
500 490
501 gpi_dma: dma-controller@900000 491 gpi_dma: dma-controller@900000 {
502 compatible = "qcom,sdx 492 compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
503 reg = <0x0 0x00900000 493 reg = <0x0 0x00900000 0x0 0x60000>;
504 #dma-cells = <3>; 494 #dma-cells = <3>;
505 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 496 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 497 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 498 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 499 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 500 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 501 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 502 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 503 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 504 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 505 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 506 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
517 dma-channels = <12>; 507 dma-channels = <12>;
518 dma-channel-mask = <0x 508 dma-channel-mask = <0x7f>;
519 iommus = <&apps_smmu 0 509 iommus = <&apps_smmu 0xf6 0x0>;
520 status = "disabled"; 510 status = "disabled";
521 }; 511 };
522 512
523 qupv3_id_0: geniqup@9c0000 { 513 qupv3_id_0: geniqup@9c0000 {
524 compatible = "qcom,gen 514 compatible = "qcom,geni-se-qup";
525 reg = <0x0 0x009c0000 515 reg = <0x0 0x009c0000 0x0 0x2000>;
526 clocks = <&gcc GCC_QUP 516 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
527 <&gcc GCC_QUP 517 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
528 clock-names = "m-ahb", 518 clock-names = "m-ahb",
529 "s-ahb"; 519 "s-ahb";
530 iommus = <&apps_smmu 0 520 iommus = <&apps_smmu 0xe3 0x0>;
531 interconnects = <&clk_ 521 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
532 &clk_ 522 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
533 interconnect-names = " 523 interconnect-names = "qup-core";
534 #address-cells = <2>; 524 #address-cells = <2>;
535 #size-cells = <2>; 525 #size-cells = <2>;
536 ranges; 526 ranges;
537 status = "disabled"; 527 status = "disabled";
538 528
539 i2c0: i2c@980000 { 529 i2c0: i2c@980000 {
540 compatible = " 530 compatible = "qcom,geni-i2c";
541 reg = <0x0 0x0 531 reg = <0x0 0x00980000 0x0 0x4000>;
542 clocks = <&gcc 532 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
543 clock-names = 533 clock-names = "se";
544 interrupts = < 534 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells 535 #address-cells = <1>;
546 #size-cells = 536 #size-cells = <0>;
547 pinctrl-0 = <& 537 pinctrl-0 = <&qup_i2c0_data_clk>;
548 pinctrl-names 538 pinctrl-names = "default";
549 interconnects 539 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
550 540 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
551 541 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
552 542 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
553 543 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
554 544 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
555 interconnect-n 545 interconnect-names = "qup-core", "qup-config", "qup-memory";
556 dmas = <&gpi_d 546 dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
557 <&gpi_d 547 <&gpi_dma 1 0 QCOM_GPI_I2C>;
558 dma-names = "t 548 dma-names = "tx", "rx";
559 status = "disa 549 status = "disabled";
560 }; 550 };
561 551
562 spi0: spi@980000 { 552 spi0: spi@980000 {
563 compatible = " 553 compatible = "qcom,geni-spi";
564 reg = <0x0 0x0 554 reg = <0x0 0x00980000 0x0 0x4000>;
565 clocks = <&gcc 555 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
566 clock-names = 556 clock-names = "se";
567 interrupts = < 557 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
568 #address-cells 558 #address-cells = <1>;
569 #size-cells = 559 #size-cells = <0>;
570 pinctrl-0 = <& 560 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
571 pinctrl-names 561 pinctrl-names = "default";
572 interconnects 562 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
573 563 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
574 564 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
575 565 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
576 566 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
577 567 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
578 interconnect-n 568 interconnect-names = "qup-core", "qup-config", "qup-memory";
579 dmas = <&gpi_d 569 dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
580 <&gpi_d 570 <&gpi_dma 1 0 QCOM_GPI_SPI>;
581 dma-names = "t 571 dma-names = "tx", "rx";
582 status = "disa 572 status = "disabled";
583 }; 573 };
584 574
585 uart1: serial@984000 { 575 uart1: serial@984000 {
586 compatible = " 576 compatible = "qcom,geni-debug-uart";
587 reg = <0x0 0x0 577 reg = <0x0 0x00984000 0x0 0x4000>;
588 clocks = <&gcc 578 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
589 clock-names = 579 clock-names = "se";
590 interconnects 580 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
591 581 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
592 582 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
593 583 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
594 interconnect-n 584 interconnect-names = "qup-core",
595 585 "qup-config";
596 interrupts = < 586 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-0 = <& 587 pinctrl-0 = <&qupv3_se1_2uart_active>;
598 pinctrl-1 = <& 588 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
599 pinctrl-names 589 pinctrl-names = "default",
600 590 "sleep";
601 status = "disa 591 status = "disabled";
602 }; 592 };
603 593
604 i2c2: i2c@988000 { 594 i2c2: i2c@988000 {
605 compatible = " 595 compatible = "qcom,geni-i2c";
606 reg = <0x0 0x0 596 reg = <0x0 0x00988000 0x0 0x4000>;
607 clocks = <&gcc 597 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
608 clock-names = 598 clock-names = "se";
609 interrupts = < 599 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells 600 #address-cells = <1>;
611 #size-cells = 601 #size-cells = <0>;
612 pinctrl-0 = <& 602 pinctrl-0 = <&qup_i2c2_data_clk>;
613 pinctrl-names 603 pinctrl-names = "default";
614 interconnects 604 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
615 605 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
616 606 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
617 607 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
618 608 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
619 609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
620 interconnect-n 610 interconnect-names = "qup-core", "qup-config", "qup-memory";
621 dmas = <&gpi_d 611 dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
622 <&gpi_d 612 <&gpi_dma 1 2 QCOM_GPI_I2C>;
623 dma-names = "t 613 dma-names = "tx", "rx";
624 status = "disa 614 status = "disabled";
625 }; 615 };
626 616
627 spi2: spi@988000 { 617 spi2: spi@988000 {
628 compatible = " 618 compatible = "qcom,geni-spi";
629 reg = <0x0 0x0 619 reg = <0x0 0x00988000 0x0 0x4000>;
630 clocks = <&gcc 620 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
631 clock-names = 621 clock-names = "se";
632 interrupts = < 622 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells 623 #address-cells = <1>;
634 #size-cells = 624 #size-cells = <0>;
635 pinctrl-0 = <& 625 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
636 pinctrl-names 626 pinctrl-names = "default";
637 interconnects 627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
638 628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
639 629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
640 630 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
641 631 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
642 632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
643 interconnect-n 633 interconnect-names = "qup-core", "qup-config", "qup-memory";
644 dmas = <&gpi_d 634 dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
645 <&gpi_d 635 <&gpi_dma 1 2 QCOM_GPI_SPI>;
646 dma-names = "t 636 dma-names = "tx", "rx";
647 status = "disa 637 status = "disabled";
648 }; 638 };
649 639
650 i2c3: i2c@98c000 { 640 i2c3: i2c@98c000 {
651 compatible = " 641 compatible = "qcom,geni-i2c";
652 reg = <0x0 0x0 642 reg = <0x0 0x0098c000 0x0 0x4000>;
653 clocks = <&gcc 643 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
654 clock-names = 644 clock-names = "se";
655 interrupts = < 645 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
656 #address-cells 646 #address-cells = <1>;
657 #size-cells = 647 #size-cells = <0>;
658 pinctrl-0 = <& 648 pinctrl-0 = <&qup_i2c3_data_clk>;
659 pinctrl-names 649 pinctrl-names = "default";
660 interconnects 650 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
661 651 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
662 652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
663 653 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
664 654 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
665 655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
666 interconnect-n 656 interconnect-names = "qup-core", "qup-config", "qup-memory";
667 dmas = <&gpi_d 657 dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
668 <&gpi_d 658 <&gpi_dma 1 3 QCOM_GPI_I2C>;
669 dma-names = "t 659 dma-names = "tx", "rx";
670 status = "disa 660 status = "disabled";
671 }; 661 };
672 662
673 spi3: spi@98c000 { 663 spi3: spi@98c000 {
674 compatible = " 664 compatible = "qcom,geni-spi";
675 reg = <0x0 0x0 665 reg = <0x0 0x0098c000 0x0 0x4000>;
676 clocks = <&gcc 666 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
677 clock-names = 667 clock-names = "se";
678 interrupts = < 668 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
679 #address-cells 669 #address-cells = <1>;
680 #size-cells = 670 #size-cells = <0>;
681 pinctrl-0 = <& 671 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
682 pinctrl-names 672 pinctrl-names = "default";
683 interconnects 673 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
684 674 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
685 675 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
686 676 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
687 677 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
688 678 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
689 interconnect-n 679 interconnect-names = "qup-core", "qup-config", "qup-memory";
690 dmas = <&gpi_d 680 dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
691 <&gpi_d 681 <&gpi_dma 1 3 QCOM_GPI_SPI>;
692 dma-names = "t 682 dma-names = "tx", "rx";
693 status = "disa 683 status = "disabled";
694 }; 684 };
695 685
696 uart4: serial@990000 { 686 uart4: serial@990000 {
697 compatible = " 687 compatible = "qcom,geni-uart";
698 reg = <0x0 0x0 688 reg = <0x0 0x00990000 0x0 0x4000>;
699 clocks = <&gcc 689 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
700 clock-names = 690 clock-names = "se";
701 interrupts = < 691 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
702 pinctrl-0 = <& 692 pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
703 pinctrl-names 693 pinctrl-names = "default";
704 interconnects 694 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
705 695 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
706 696 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
707 697 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
708 interconnect-n 698 interconnect-names = "qup-core", "qup-config";
709 status = "disa 699 status = "disabled";
710 }; 700 };
711 701
712 i2c5: i2c@994000 { 702 i2c5: i2c@994000 {
713 compatible = " 703 compatible = "qcom,geni-i2c";
714 reg = <0x0 0x0 704 reg = <0x0 0x00994000 0x0 0x4000>;
715 clocks = <&gcc 705 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
716 clock-names = 706 clock-names = "se";
717 interrupts = < 707 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells 708 #address-cells = <1>;
719 #size-cells = 709 #size-cells = <0>;
720 pinctrl-0 = <& 710 pinctrl-0 = <&qup_i2c5_data_clk>;
721 pinctrl-names 711 pinctrl-names = "default";
722 interconnects 712 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
723 713 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
724 714 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
725 715 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
726 716 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
727 717 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
728 interconnect-n 718 interconnect-names = "qup-core", "qup-config", "qup-memory";
729 dmas = <&gpi_d 719 dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
730 <&gpi_d 720 <&gpi_dma 1 5 QCOM_GPI_I2C>;
731 dma-names = "t 721 dma-names = "tx", "rx";
732 status = "disa 722 status = "disabled";
733 }; 723 };
734 724
735 i2c6: i2c@998000 { 725 i2c6: i2c@998000 {
736 compatible = " 726 compatible = "qcom,geni-i2c";
737 reg = <0x0 0x0 727 reg = <0x0 0x00998000 0x0 0x4000>;
738 clocks = <&gcc 728 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
739 clock-names = 729 clock-names = "se";
740 interrupts = < 730 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
741 #address-cells 731 #address-cells = <1>;
742 #size-cells = 732 #size-cells = <0>;
743 pinctrl-0 = <& 733 pinctrl-0 = <&qup_i2c6_data_clk>;
744 pinctrl-names 734 pinctrl-names = "default";
745 interconnects 735 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
746 736 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
747 737 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
748 738 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
749 739 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
750 740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
751 interconnect-n 741 interconnect-names = "qup-core", "qup-config", "qup-memory";
752 dmas = <&gpi_d 742 dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
753 <&gpi_d 743 <&gpi_dma 1 6 QCOM_GPI_I2C>;
754 dma-names = "t 744 dma-names = "tx", "rx";
755 status = "disa 745 status = "disabled";
756 }; 746 };
757 747
758 spi6: spi@998000 { 748 spi6: spi@998000 {
759 compatible = " 749 compatible = "qcom,geni-spi";
760 reg = <0x0 0x0 750 reg = <0x0 0x00998000 0x0 0x4000>;
761 clocks = <&gcc 751 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
762 clock-names = 752 clock-names = "se";
763 interrupts = < 753 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
764 #address-cells 754 #address-cells = <1>;
765 #size-cells = 755 #size-cells = <0>;
766 pinctrl-0 = <& 756 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
767 pinctrl-names 757 pinctrl-names = "default";
768 interconnects 758 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
769 759 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
770 760 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
771 761 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
772 762 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
773 763 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
774 interconnect-n 764 interconnect-names = "qup-core", "qup-config", "qup-memory";
775 dmas = <&gpi_d 765 dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
776 <&gpi_d 766 <&gpi_dma 1 6 QCOM_GPI_SPI>;
777 dma-names = "t 767 dma-names = "tx", "rx";
778 status = "disa 768 status = "disabled";
779 }; 769 };
780 770
781 i2c7: i2c@99c000 { 771 i2c7: i2c@99c000 {
782 compatible = " 772 compatible = "qcom,geni-i2c";
783 reg = <0x0 0x0 773 reg = <0x0 0x0099c000 0x0 0x4000>;
784 clocks = <&gcc 774 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
785 clock-names = 775 clock-names = "se";
786 interrupts = < 776 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells 777 #address-cells = <1>;
788 #size-cells = 778 #size-cells = <0>;
789 pinctrl-0 = <& 779 pinctrl-0 = <&qup_i2c7_data_clk>;
790 pinctrl-names 780 pinctrl-names = "default";
791 interconnects 781 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
792 782 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
793 783 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
794 784 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
795 785 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
796 786 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
797 interconnect-n 787 interconnect-names = "qup-core", "qup-config", "qup-memory";
798 dmas = <&gpi_d 788 dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
799 <&gpi_d 789 <&gpi_dma 1 7 QCOM_GPI_I2C>;
800 dma-names = "t 790 dma-names = "tx", "rx";
801 status = "disa 791 status = "disabled";
802 }; 792 };
803 793
804 spi7: spi@99c000 { 794 spi7: spi@99c000 {
805 compatible = " 795 compatible = "qcom,geni-spi";
806 reg = <0x0 0x0 796 reg = <0x0 0x0099c000 0x0 0x4000>;
807 clocks = <&gcc 797 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
808 clock-names = 798 clock-names = "se";
809 interrupts = < 799 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
810 #address-cells 800 #address-cells = <1>;
811 #size-cells = 801 #size-cells = <0>;
812 pinctrl-0 = <& 802 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
813 pinctrl-names 803 pinctrl-names = "default";
814 interconnects 804 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
815 805 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
816 806 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
817 807 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
818 808 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
819 809 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
820 interconnect-n 810 interconnect-names = "qup-core", "qup-config", "qup-memory";
821 dmas = <&gpi_d 811 dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
822 <&gpi_d 812 <&gpi_dma 1 7 QCOM_GPI_SPI>;
823 dma-names = "t 813 dma-names = "tx", "rx";
824 status = "disa 814 status = "disabled";
825 }; 815 };
826 }; 816 };
827 817
828 usb_hsphy: phy@ff4000 { 818 usb_hsphy: phy@ff4000 {
829 compatible = "qcom,sdx 819 compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
830 reg = <0x0 0x00ff4000 820 reg = <0x0 0x00ff4000 0x0 0x154>;
831 #phy-cells = <0>; 821 #phy-cells = <0>;
832 822
833 clocks = <&rpmhcc RPMH 823 clocks = <&rpmhcc RPMH_CXO_CLK>;
834 clock-names = "ref"; 824 clock-names = "ref";
835 825
836 resets = <&gcc GCC_QUS 826 resets = <&gcc GCC_QUSB2PHY_BCR>;
837 827
838 status = "disabled"; 828 status = "disabled";
839 }; 829 };
840 830
841 usb_qmpphy: phy@ff6000 { 831 usb_qmpphy: phy@ff6000 {
842 compatible = "qcom,sdx 832 compatible = "qcom,sdx75-qmp-usb3-uni-phy";
843 reg = <0x0 0x00ff6000 833 reg = <0x0 0x00ff6000 0x0 0x2000>;
844 834
845 clocks = <&gcc GCC_USB 835 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
846 <&gcc GCC_USB 836 <&gcc GCC_USB2_CLKREF_EN>,
847 <&gcc GCC_USB 837 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
848 <&gcc GCC_USB 838 <&gcc GCC_USB3_PHY_PIPE_CLK>;
849 clock-names = "aux", 839 clock-names = "aux",
850 "ref", 840 "ref",
851 "cfg_ahb 841 "cfg_ahb",
852 "pipe"; 842 "pipe";
853 843
854 power-domains = <&gcc 844 power-domains = <&gcc GCC_USB3_PHY_GDSC>;
855 845
856 resets = <&gcc GCC_USB 846 resets = <&gcc GCC_USB3_PHY_BCR>,
857 <&gcc GCC_USB 847 <&gcc GCC_USB3PHY_PHY_BCR>;
858 reset-names = "phy", 848 reset-names = "phy",
859 "phy_phy 849 "phy_phy";
860 850
861 #clock-cells = <0>; 851 #clock-cells = <0>;
862 clock-output-names = " 852 clock-output-names = "usb3_uni_phy_pipe_clk_src";
863 853
864 #phy-cells = <0>; 854 #phy-cells = <0>;
865 855
866 status = "disabled"; 856 status = "disabled";
867 }; 857 };
868 858
869 system_noc: interconnect@16400 859 system_noc: interconnect@1640000 {
870 compatible = "qcom,sdx 860 compatible = "qcom,sdx75-system-noc";
871 reg = <0x0 0x01640000 861 reg = <0x0 0x01640000 0x0 0x4b400>;
872 #interconnect-cells = 862 #interconnect-cells = <2>;
873 qcom,bcm-voters = <&ap 863 qcom,bcm-voters = <&apps_bcm_voter>;
874 }; 864 };
875 865
876 pcie_anoc: interconnect@16c000 866 pcie_anoc: interconnect@16c0000 {
877 compatible = "qcom,sdx 867 compatible = "qcom,sdx75-pcie-anoc";
878 reg = <0x0 0x016c0000 868 reg = <0x0 0x016c0000 0x0 0x14200>;
879 #interconnect-cells = 869 #interconnect-cells = <2>;
880 qcom,bcm-voters = <&ap 870 qcom,bcm-voters = <&apps_bcm_voter>;
881 }; 871 };
882 872
883 tcsr_mutex: hwlock@1f40000 { 873 tcsr_mutex: hwlock@1f40000 {
884 compatible = "qcom,tcs 874 compatible = "qcom,tcsr-mutex";
885 reg = <0x0 0x01f40000 875 reg = <0x0 0x01f40000 0x0 0x40000>;
886 #hwlock-cells = <1>; 876 #hwlock-cells = <1>;
887 }; 877 };
888 878
889 tcsr: syscon@1fc0000 { 879 tcsr: syscon@1fc0000 {
890 compatible = "qcom,sdx 880 compatible = "qcom,sdx75-tcsr", "syscon";
891 reg = <0x0 0x01fc0000 881 reg = <0x0 0x01fc0000 0x0 0x30000>;
892 }; <<
893 <<
894 remoteproc_mpss: remoteproc@40 <<
895 compatible = "qcom,sdx <<
896 reg = <0 0x04080000 0 <<
897 <<
898 interrupts-extended = <<
899 <<
900 <<
901 <<
902 <<
903 <<
904 interrupt-names = "wdo <<
905 "fat <<
906 "rea <<
907 "han <<
908 "sto <<
909 "shu <<
910 <<
911 clocks = <&rpmhcc RPMH <<
912 clock-names = "xo"; <<
913 <<
914 power-domains = <&rpmh <<
915 <&rpmh <<
916 power-domain-names = " <<
917 " <<
918 <<
919 memory-region = <&mpss <<
920 <&mpss <<
921 <&qlin <<
922 <<
923 qcom,qmp = <&aoss_qmp> <<
924 <<
925 qcom,smem-states = <&s <<
926 qcom,smem-state-names <<
927 <<
928 status = "disabled"; <<
929 <<
930 glink-edge { <<
931 interrupts-ext <<
932 <<
933 <<
934 mboxes = <&ipc <<
935 <<
936 label = "mpss" <<
937 qcom,remote-pi <<
938 }; <<
939 }; 882 };
940 883
941 sdhc: mmc@8804000 { 884 sdhc: mmc@8804000 {
942 compatible = "qcom,sdx 885 compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
943 reg = <0x0 0x08804000 886 reg = <0x0 0x08804000 0x0 0x1000>;
944 887
945 interrupts = <GIC_SPI 888 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 889 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
947 interrupt-names = "hc_ 890 interrupt-names = "hc_irq",
948 "pwr 891 "pwr_irq";
949 892
950 clocks = <&gcc GCC_SDC 893 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
951 <&gcc GCC_SDC 894 <&gcc GCC_SDCC1_APPS_CLK>,
952 <&rpmhcc RPMH 895 <&rpmhcc RPMH_CXO_CLK>;
953 clock-names = "iface", 896 clock-names = "iface",
954 "core", 897 "core",
955 "xo"; 898 "xo";
956 iommus = <&apps_smmu 0 899 iommus = <&apps_smmu 0x00a0 0x0>;
957 qcom,dll-config = <0x0 900 qcom,dll-config = <0x0007442c>;
958 qcom,ddr-config = <0x8 901 qcom,ddr-config = <0x80040868>;
959 power-domains = <&rpmh 902 power-domains = <&rpmhpd RPMHPD_CX>;
960 operating-points-v2 = 903 operating-points-v2 = <&sdhc1_opp_table>;
961 904
962 interconnects = <&syst 905 interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
963 <&gem_ 906 <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
964 interconnect-names = " 907 interconnect-names = "sdhc-ddr",
965 " 908 "cpu-sdhc";
966 bus-width = <4>; 909 bus-width = <4>;
967 dma-coherent; 910 dma-coherent;
968 911
969 /* Forbid SDR104/SDR50 912 /* Forbid SDR104/SDR50 - broken hw! */
970 sdhci-caps-mask = <0x3 913 sdhci-caps-mask = <0x3 0>;
971 914
972 status = "disabled"; 915 status = "disabled";
973 916
974 sdhc1_opp_table: opp-t 917 sdhc1_opp_table: opp-table {
975 compatible = " 918 compatible = "operating-points-v2";
976 919
977 opp-100000000 920 opp-100000000 {
978 opp-hz 921 opp-hz = /bits/ 64 <100000000>;
979 requir 922 required-opps = <&rpmhpd_opp_low_svs>;
980 }; 923 };
981 924
982 opp-384000000 925 opp-384000000 {
983 opp-hz 926 opp-hz = /bits/ 64 <384000000>;
984 requir 927 required-opps = <&rpmhpd_opp_nom>;
985 }; 928 };
986 }; 929 };
987 }; 930 };
988 931
989 usb: usb@a6f8800 { 932 usb: usb@a6f8800 {
990 compatible = "qcom,sdx 933 compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
991 reg = <0x0 0x0a6f8800 934 reg = <0x0 0x0a6f8800 0x0 0x400>;
992 #address-cells = <2>; 935 #address-cells = <2>;
993 #size-cells = <2>; 936 #size-cells = <2>;
994 ranges; 937 ranges;
995 938
996 clocks = <&gcc GCC_USB 939 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
997 <&gcc GCC_USB 940 <&gcc GCC_USB30_MASTER_CLK>,
998 <&gcc GCC_USB 941 <&gcc GCC_USB30_MSTR_AXI_CLK>,
999 <&gcc GCC_USB 942 <&gcc GCC_USB30_SLEEP_CLK>,
1000 <&gcc GCC_US 943 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1001 clock-names = "cfg_no 944 clock-names = "cfg_noc",
1002 "core", 945 "core",
1003 "iface" 946 "iface",
1004 "sleep" 947 "sleep",
1005 "mock_u 948 "mock_utmi";
1006 949
1007 assigned-clocks = <&g 950 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1008 <&g 951 <&gcc GCC_USB30_MASTER_CLK>;
1009 assigned-clock-rates 952 assigned-clock-rates = <19200000>, <200000000>;
1010 953
1011 interrupts-extended = 954 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1012 955 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1013 956 <&pdc 9 IRQ_TYPE_EDGE_RISING>,
1014 957 <&pdc 10 IRQ_TYPE_EDGE_RISING>;
1015 interrupt-names = "hs 958 interrupt-names = "hs_phy_irq",
1016 "ss 959 "ss_phy_irq",
1017 "dm 960 "dm_hs_phy_irq",
1018 "dp 961 "dp_hs_phy_irq";
1019 962
1020 power-domains = <&gcc 963 power-domains = <&gcc GCC_USB30_GDSC>;
1021 964
1022 resets = <&gcc GCC_US 965 resets = <&gcc GCC_USB30_BCR>;
1023 966
1024 interconnects = <&sys 967 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
1025 &mc_ 968 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1026 <&gem 969 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1027 &sys 970 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
1028 interconnect-names = 971 interconnect-names = "usb-ddr",
1029 972 "apps-usb";
1030 973
1031 status = "disabled"; 974 status = "disabled";
1032 975
1033 usb_dwc3: usb@a600000 976 usb_dwc3: usb@a600000 {
1034 compatible = 977 compatible = "snps,dwc3";
1035 reg = <0x0 0x 978 reg = <0x0 0x0a600000 0x0 0xcd00>;
1036 interrupts = 979 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1037 iommus = <&ap 980 iommus = <&apps_smmu 0x80 0x0>;
1038 snps,dis_u2_s 981 snps,dis_u2_susphy_quirk;
1039 snps,dis_enbl 982 snps,dis_enblslpm_quirk;
1040 phys = <&usb_ 983 phys = <&usb_hsphy>,
1041 <&usb_ 984 <&usb_qmpphy>;
1042 phy-names = " 985 phy-names = "usb2-phy",
1043 " 986 "usb3-phy";
1044 987
1045 ports { 988 ports {
1046 #addr 989 #address-cells = <1>;
1047 #size 990 #size-cells = <0>;
1048 991
1049 port@ 992 port@0 {
1050 993 reg = <0>;
1051 994
1052 995 usb_1_dwc3_hs: endpoint {
1053 996 };
1054 }; 997 };
1055 998
1056 port@ 999 port@1 {
1057 1000 reg = <1>;
1058 1001
1059 1002 usb_1_dwc3_ss: endpoint {
1060 1003 };
1061 }; 1004 };
1062 }; 1005 };
1063 }; 1006 };
1064 }; 1007 };
1065 1008
1066 pdc: interrupt-controller@b22 1009 pdc: interrupt-controller@b220000 {
1067 compatible = "qcom,sd 1010 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1068 reg = <0x0 0xb220000 1011 reg = <0x0 0xb220000 0x0 0x30000>,
1069 <0x0 0x174000f0 1012 <0x0 0x174000f0 0x0 0x64>;
1070 qcom,pdc-ranges = <0 1013 qcom,pdc-ranges = <0 147 52>,
1071 <52 1014 <52 266 32>,
1072 <84 1015 <84 500 59>;
1073 #interrupt-cells = <2 1016 #interrupt-cells = <2>;
1074 interrupt-parent = <& 1017 interrupt-parent = <&intc>;
1075 interrupt-controller; 1018 interrupt-controller;
1076 }; 1019 };
1077 1020
1078 aoss_qmp: power-controller@c3 1021 aoss_qmp: power-controller@c310000 {
1079 compatible = "qcom,sd 1022 compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
1080 reg = <0 0x0c310000 0 1023 reg = <0 0x0c310000 0 0x1000>;
1081 interrupt-parent = <& 1024 interrupt-parent = <&ipcc>;
1082 interrupts-extended = 1025 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1083 1026 IRQ_TYPE_EDGE_RISING>;
1084 mboxes = <&ipcc IPCC_ 1027 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1085 1028
1086 #clock-cells = <0>; 1029 #clock-cells = <0>;
1087 }; 1030 };
1088 1031
1089 spmi_bus: spmi@c400000 { 1032 spmi_bus: spmi@c400000 {
1090 compatible = "qcom,sp 1033 compatible = "qcom,spmi-pmic-arb";
1091 reg = <0x0 0x0c400000 1034 reg = <0x0 0x0c400000 0x0 0x3000>,
1092 <0x0 0x0c500000 1035 <0x0 0x0c500000 0x0 0x400000>,
1093 <0x0 0x0c440000 1036 <0x0 0x0c440000 0x0 0x80000>,
1094 <0x0 0x0c4c0000 1037 <0x0 0x0c4c0000 0x0 0x10000>,
1095 <0x0 0x0c42d000 1038 <0x0 0x0c42d000 0x0 0x4000>;
1096 reg-names = "core", 1039 reg-names = "core",
1097 "chnls", 1040 "chnls",
1098 "obsrvr", 1041 "obsrvr",
1099 "intr", 1042 "intr",
1100 "cnfg"; 1043 "cnfg";
1101 interrupts-extended = 1044 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1102 interrupt-names = "pe 1045 interrupt-names = "periph_irq";
1103 qcom,ee = <0>; 1046 qcom,ee = <0>;
1104 qcom,channel = <0>; 1047 qcom,channel = <0>;
1105 qcom,bus-id = <0>; 1048 qcom,bus-id = <0>;
1106 #address-cells = <2>; 1049 #address-cells = <2>;
1107 #size-cells = <0>; 1050 #size-cells = <0>;
1108 interrupt-controller; 1051 interrupt-controller;
1109 #interrupt-cells = <4 1052 #interrupt-cells = <4>;
1110 }; 1053 };
1111 1054
1112 tlmm: pinctrl@f000000 { 1055 tlmm: pinctrl@f000000 {
1113 compatible = "qcom,sd 1056 compatible = "qcom,sdx75-tlmm";
1114 reg = <0x0 0x0f000000 1057 reg = <0x0 0x0f000000 0x0 0x400000>;
1115 interrupts = <GIC_SPI 1058 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1116 gpio-controller; 1059 gpio-controller;
1117 #gpio-cells = <2>; 1060 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm 1061 gpio-ranges = <&tlmm 0 0 133>;
1119 interrupt-controller; 1062 interrupt-controller;
1120 #interrupt-cells = <2 1063 #interrupt-cells = <2>;
1121 wakeup-parent = <&pdc 1064 wakeup-parent = <&pdc>;
1122 1065
1123 qup_i2c0_data_clk: qu 1066 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
1124 /* SDA, SCL * 1067 /* SDA, SCL */
1125 pins = "gpio8 1068 pins = "gpio8", "gpio9";
1126 function = "q 1069 function = "qup_se0";
1127 drive-strengt 1070 drive-strength = <2>;
1128 bias-pull-up; 1071 bias-pull-up;
1129 }; 1072 };
1130 1073
1131 qup_i2c2_data_clk: qu 1074 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1132 /* SDA, SCL * 1075 /* SDA, SCL */
1133 pins = "gpio1 1076 pins = "gpio14", "gpio15";
1134 function = "q 1077 function = "qup_se2";
1135 drive-strengt 1078 drive-strength = <2>;
1136 bias-pull-up; 1079 bias-pull-up;
1137 }; 1080 };
1138 1081
1139 qup_i2c3_data_clk: qu 1082 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1140 /* SDA, SCL * 1083 /* SDA, SCL */
1141 pins = "gpio5 1084 pins = "gpio52", "gpio53";
1142 function = "q 1085 function = "qup_se3";
1143 drive-strengt 1086 drive-strength = <2>;
1144 bias-pull-up; 1087 bias-pull-up;
1145 }; 1088 };
1146 1089
1147 qup_i2c5_data_clk: qu 1090 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1148 /* SDA, SCL * 1091 /* SDA, SCL */
1149 pins = "gpio1 1092 pins = "gpio110", "gpio111";
1150 function = "q 1093 function = "qup_se5";
1151 drive-strengt 1094 drive-strength = <2>;
1152 bias-pull-up; 1095 bias-pull-up;
1153 }; 1096 };
1154 1097
1155 qup_i2c6_data_clk: qu 1098 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1156 /* SDA, SCL * 1099 /* SDA, SCL */
1157 pins = "gpio1 1100 pins = "gpio112", "gpio113";
1158 function = "q 1101 function = "qup_se6";
1159 drive-strengt 1102 drive-strength = <2>;
1160 bias-pull-up; 1103 bias-pull-up;
1161 }; 1104 };
1162 1105
1163 qup_i2c7_data_clk: qu 1106 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1164 /* SDA, SCL * 1107 /* SDA, SCL */
1165 pins = "gpio1 1108 pins = "gpio116", "gpio117";
1166 function = "q 1109 function = "qup_se7";
1167 drive-strengt 1110 drive-strength = <2>;
1168 bias-pull-up; 1111 bias-pull-up;
1169 }; 1112 };
1170 1113
1171 qup_spi0_cs: qup-spi0 1114 qup_spi0_cs: qup-spi0-cs-state {
1172 pins = "gpio1 1115 pins = "gpio11";
1173 function = "q 1116 function = "qup_se0";
1174 drive-strengt 1117 drive-strength = <6>;
1175 bias-pull-dow 1118 bias-pull-down;
1176 }; 1119 };
1177 1120
1178 qup_spi0_data_clk: qu 1121 qup_spi0_data_clk: qup-spi0-data-clk-state {
1179 /* MISO, MOSI 1122 /* MISO, MOSI, CLK */
1180 pins = "gpio8 1123 pins = "gpio8", "gpio9", "gpio10";
1181 function = "q 1124 function = "qup_se0";
1182 drive-strengt 1125 drive-strength = <6>;
1183 bias-pull-dow 1126 bias-pull-down;
1184 }; 1127 };
1185 1128
1186 qup_spi2_cs: qup-spi2 1129 qup_spi2_cs: qup-spi2-cs-state {
1187 pins = "gpio1 1130 pins = "gpio17";
1188 function = "q 1131 function = "qup_se2";
1189 drive-strengt 1132 drive-strength = <6>;
1190 bias-pull-dow 1133 bias-pull-down;
1191 }; 1134 };
1192 1135
1193 qup_spi2_data_clk: qu 1136 qup_spi2_data_clk: qup-spi2-data-clk-state {
1194 /* MISO, MOSI 1137 /* MISO, MOSI, CLK */
1195 pins = "gpio1 1138 pins = "gpio14", "gpio15", "gpio16";
1196 function = "q 1139 function = "qup_se2";
1197 drive-strengt 1140 drive-strength = <6>;
1198 bias-pull-dow 1141 bias-pull-down;
1199 }; 1142 };
1200 1143
1201 qup_spi3_cs: qup-spi3 1144 qup_spi3_cs: qup-spi3-cs-state {
1202 pins = "gpio5 1145 pins = "gpio55";
1203 function = "q 1146 function = "qup_se3";
1204 drive-strengt 1147 drive-strength = <6>;
1205 bias-pull-dow 1148 bias-pull-down;
1206 }; 1149 };
1207 1150
1208 qup_spi3_data_clk: qu 1151 qup_spi3_data_clk: qup-spi3-data-clk-state {
1209 /* MISO, MOSI 1152 /* MISO, MOSI, CLK */
1210 pins = "gpio5 1153 pins = "gpio52", "gpio53", "gpio54";
1211 function = "q 1154 function = "qup_se3";
1212 drive-strengt 1155 drive-strength = <6>;
1213 bias-pull-dow 1156 bias-pull-down;
1214 }; 1157 };
1215 1158
1216 qup_spi6_cs: qup-spi6 1159 qup_spi6_cs: qup-spi6-cs-state {
1217 pins = "gpio1 1160 pins = "gpio115";
1218 function = "q 1161 function = "qup_se6";
1219 drive-strengt 1162 drive-strength = <6>;
1220 bias-pull-dow 1163 bias-pull-down;
1221 }; 1164 };
1222 1165
1223 qup_spi6_data_clk: qu 1166 qup_spi6_data_clk: qup-spi6-data-clk-state {
1224 /* MISO, MOSI 1167 /* MISO, MOSI, CLK */
1225 pins = "gpio1 1168 pins = "gpio112", "gpio113", "gpio114";
1226 function = "q 1169 function = "qup_se6";
1227 drive-strengt 1170 drive-strength = <6>;
1228 bias-pull-dow 1171 bias-pull-down;
1229 }; 1172 };
1230 1173
1231 qup_spi7_cs: qup-spi7 1174 qup_spi7_cs: qup-spi7-cs-state {
1232 pins = "gpio1 1175 pins = "gpio119";
1233 function = "q 1176 function = "qup_se7";
1234 drive-strengt 1177 drive-strength = <6>;
1235 bias-pull-dow 1178 bias-pull-down;
1236 }; 1179 };
1237 1180
1238 qup_spi7_data_clk: qu 1181 qup_spi7_data_clk: qup-spi7-data-clk-state {
1239 /* MISO, MOSI 1182 /* MISO, MOSI, CLK */
1240 pins = "gpio1 1183 pins = "gpio116", "gpio117", "gpio118";
1241 function = "q 1184 function = "qup_se7";
1242 drive-strengt 1185 drive-strength = <6>;
1243 bias-pull-dow 1186 bias-pull-down;
1244 }; 1187 };
1245 1188
1246 qup_uart4_cts_rts: qu 1189 qup_uart4_cts_rts: qup-uart4-cts-rts-state {
1247 /* CTS, RTS * 1190 /* CTS, RTS */
1248 pins = "gpio5 1191 pins = "gpio52", "gpio53";
1249 function = "q 1192 function = "qup_se3";
1250 drive-strengt 1193 drive-strength = <2>;
1251 bias-pull-dow 1194 bias-pull-down;
1252 }; 1195 };
1253 1196
1254 qup_uart4_default: qu 1197 qup_uart4_default: qup-uart4-default-state {
1255 /* TX, RX */ 1198 /* TX, RX */
1256 pins = "gpio5 1199 pins = "gpio54", "gpio55";
1257 function = "q 1200 function = "qup_se3";
1258 drive-strengt 1201 drive-strength = <2>;
1259 bias-pull-up; 1202 bias-pull-up;
1260 }; 1203 };
1261 1204
1262 qupv3_se1_2uart_activ 1205 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1263 tx-pins { 1206 tx-pins {
1264 pins 1207 pins = "gpio12";
1265 funct 1208 function = "qup_se1_l2_mira";
1266 drive 1209 drive-strength = <2>;
1267 bias- 1210 bias-disable;
1268 }; 1211 };
1269 1212
1270 rx-pins { 1213 rx-pins {
1271 pins 1214 pins = "gpio13";
1272 funct 1215 function = "qup_se1_l3_mira";
1273 drive 1216 drive-strength = <2>;
1274 bias- 1217 bias-disable;
1275 }; 1218 };
1276 }; 1219 };
1277 1220
1278 qupv3_se1_2uart_sleep 1221 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1279 pins = "gpio1 1222 pins = "gpio12", "gpio13";
1280 function = "g 1223 function = "gpio";
1281 drive-strengt 1224 drive-strength = <2>;
1282 bias-pull-dow 1225 bias-pull-down;
1283 }; 1226 };
1284 1227
1285 sdc1_default: sdc1-de 1228 sdc1_default: sdc1-default-state {
1286 clk-pins { 1229 clk-pins {
1287 pins 1230 pins = "sdc1_clk";
1288 drive 1231 drive-strength = <16>;
1289 bias- 1232 bias-disable;
1290 }; 1233 };
1291 1234
1292 cmd-pins { 1235 cmd-pins {
1293 pins 1236 pins = "sdc1_cmd";
1294 drive 1237 drive-strength = <10>;
1295 bias- 1238 bias-pull-up;
1296 }; 1239 };
1297 1240
1298 data-pins { 1241 data-pins {
1299 pins 1242 pins = "sdc1_data";
1300 drive 1243 drive-strength = <10>;
1301 bias- 1244 bias-pull-up;
1302 }; 1245 };
1303 }; 1246 };
1304 1247
1305 sdc1_sleep: sdc1-slee 1248 sdc1_sleep: sdc1-sleep-state {
1306 clk-pins { 1249 clk-pins {
1307 pins 1250 pins = "sdc1_clk";
1308 drive 1251 drive-strength = <2>;
1309 bias- 1252 bias-disable;
1310 }; 1253 };
1311 1254
1312 cmd-pins { 1255 cmd-pins {
1313 pins 1256 pins = "sdc1_cmd";
1314 drive 1257 drive-strength = <2>;
1315 bias- 1258 bias-pull-up;
1316 }; 1259 };
1317 1260
1318 data-pins { 1261 data-pins {
1319 pins 1262 pins = "sdc1_data";
1320 drive 1263 drive-strength = <2>;
1321 bias- 1264 bias-pull-up;
1322 }; 1265 };
1323 }; 1266 };
1324 }; 1267 };
1325 1268
1326 apps_smmu: iommu@15000000 { 1269 apps_smmu: iommu@15000000 {
1327 compatible = "qcom,sd 1270 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1328 reg = <0x0 0x15000000 1271 reg = <0x0 0x15000000 0x0 0x40000>;
1329 #iommu-cells = <2>; 1272 #iommu-cells = <2>;
1330 #global-interrupts = 1273 #global-interrupts = <2>;
1331 dma-coherent; 1274 dma-coherent;
1332 interrupts = <GIC_SPI 1275 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1276 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1277 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1278 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1279 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1280 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1281 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1282 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1283 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1284 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 1285 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 1286 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 1287 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 1288 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 1289 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 1290 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 1291 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 1292 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 1293 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 1294 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 1295 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 1296 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 1297 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 1298 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 1299 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 1300 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 1301 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 1302 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 1303 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 1304 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 1305 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 1306 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1307 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1365 }; 1308 };
1366 1309
1367 intc: interrupt-controller@17 1310 intc: interrupt-controller@17200000 {
1368 compatible = "arm,gic 1311 compatible = "arm,gic-v3";
1369 #interrupt-cells = <3 1312 #interrupt-cells = <3>;
1370 interrupt-controller; 1313 interrupt-controller;
1371 #redistributor-region 1314 #redistributor-regions = <1>;
1372 redistributor-stride 1315 redistributor-stride = <0x0 0x20000>;
1373 reg = <0x0 0x17200000 1316 reg = <0x0 0x17200000 0x0 0x10000>,
1374 <0x0 0x17260000 1317 <0x0 0x17260000 0x0 0x80000>;
1375 interrupts = <GIC_PPI 1318 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1376 }; 1319 };
1377 1320
1378 timer@17420000 { 1321 timer@17420000 {
1379 compatible = "arm,arm 1322 compatible = "arm,armv7-timer-mem";
1380 reg = <0x0 0x17420000 1323 reg = <0x0 0x17420000 0x0 0x1000>;
1381 #address-cells = <1>; 1324 #address-cells = <1>;
1382 #size-cells = <1>; 1325 #size-cells = <1>;
1383 ranges = <0 0 0 0x200 1326 ranges = <0 0 0 0x20000000>;
1384 1327
1385 frame@17421000 { 1328 frame@17421000 {
1386 reg = <0x1742 1329 reg = <0x17421000 0x1000>,
1387 <0x1742 1330 <0x17422000 0x1000>;
1388 frame-number 1331 frame-number = <0>;
1389 interrupts = 1332 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1390 1333 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1391 }; 1334 };
1392 1335
1393 frame@17423000 { 1336 frame@17423000 {
1394 reg = <0x1742 1337 reg = <0x17423000 0x1000>;
1395 frame-number 1338 frame-number = <1>;
1396 interrupts = 1339 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1397 status = "dis 1340 status = "disabled";
1398 }; 1341 };
1399 1342
1400 frame@17425000 { 1343 frame@17425000 {
1401 reg = <0x1742 1344 reg = <0x17425000 0x1000>;
1402 frame-number 1345 frame-number = <2>;
1403 interrupts = 1346 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1404 status = "dis 1347 status = "disabled";
1405 }; 1348 };
1406 1349
1407 frame@17427000 { 1350 frame@17427000 {
1408 reg = <0x1742 1351 reg = <0x17427000 0x1000>;
1409 frame-number 1352 frame-number = <3>;
1410 interrupts = 1353 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1411 status = "dis 1354 status = "disabled";
1412 }; 1355 };
1413 1356
1414 frame@17429000 { 1357 frame@17429000 {
1415 reg = <0x1742 1358 reg = <0x17429000 0x1000>;
1416 frame-number 1359 frame-number = <4>;
1417 interrupts = 1360 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1418 status = "dis 1361 status = "disabled";
1419 }; 1362 };
1420 1363
1421 frame@1742b000 { 1364 frame@1742b000 {
1422 reg = <0x1742 1365 reg = <0x1742b000 0x1000>;
1423 frame-number 1366 frame-number = <5>;
1424 interrupts = 1367 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1425 status = "dis 1368 status = "disabled";
1426 }; 1369 };
1427 1370
1428 frame@1742d000 { 1371 frame@1742d000 {
1429 reg = <0x1742 1372 reg = <0x1742d000 0x1000>;
1430 frame-number 1373 frame-number = <6>;
1431 interrupts = 1374 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1432 status = "dis 1375 status = "disabled";
1433 }; 1376 };
1434 }; 1377 };
1435 1378
1436 apps_rsc: rsc@17a00000 { 1379 apps_rsc: rsc@17a00000 {
1437 label = "apps_rsc"; 1380 label = "apps_rsc";
1438 compatible = "qcom,rp 1381 compatible = "qcom,rpmh-rsc";
1439 reg = <0x0 0x17a00000 1382 reg = <0x0 0x17a00000 0x0 0x10000>,
1440 <0x0 0x17a10000 1383 <0x0 0x17a10000 0x0 0x10000>,
1441 <0x0 0x17a20000 1384 <0x0 0x17a20000 0x0 0x10000>;
1442 reg-names = "drv-0", 1385 reg-names = "drv-0", "drv-1", "drv-2";
1443 interrupts = <GIC_SPI 1386 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 1387 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 1388 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1446 1389
1447 power-domains = <&CLU 1390 power-domains = <&CLUSTER_PD>;
1448 qcom,tcs-offset = <0x 1391 qcom,tcs-offset = <0xd00>;
1449 qcom,drv-id = <2>; 1392 qcom,drv-id = <2>;
1450 qcom,tcs-config = <AC 1393 qcom,tcs-config = <ACTIVE_TCS 3>,
1451 <SL 1394 <SLEEP_TCS 2>,
1452 <WA 1395 <WAKE_TCS 2>,
1453 <CO 1396 <CONTROL_TCS 0>;
1454 1397
1455 apps_bcm_voter: bcm-v 1398 apps_bcm_voter: bcm-voter {
1456 compatible = 1399 compatible = "qcom,bcm-voter";
1457 }; 1400 };
1458 1401
1459 rpmhcc: clock-control 1402 rpmhcc: clock-controller {
1460 compatible = 1403 compatible = "qcom,sdx75-rpmh-clk";
1461 clocks = <&xo 1404 clocks = <&xo_board>;
1462 clock-names = 1405 clock-names = "xo";
1463 #clock-cells 1406 #clock-cells = <1>;
1464 }; 1407 };
1465 1408
1466 rpmhpd: power-control 1409 rpmhpd: power-controller {
1467 compatible = 1410 compatible = "qcom,sdx75-rpmhpd";
1468 #power-domain 1411 #power-domain-cells = <1>;
1469 operating-poi 1412 operating-points-v2 = <&rpmhpd_opp_table>;
1470 1413
1471 rpmhpd_opp_ta 1414 rpmhpd_opp_table: opp-table {
1472 compa 1415 compatible = "operating-points-v2";
1473 1416
1474 rpmhp 1417 rpmhpd_opp_ret: opp-16 {
1475 1418 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1476 }; 1419 };
1477 1420
1478 rpmhp 1421 rpmhpd_opp_min_svs: opp-48 {
1479 1422 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1480 }; 1423 };
1481 1424
1482 rpmhp 1425 rpmhpd_opp_low_svs: opp-64 {
1483 1426 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1484 }; 1427 };
1485 1428
1486 rpmhp 1429 rpmhpd_opp_svs: opp-128 {
1487 1430 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1488 }; 1431 };
1489 1432
1490 rpmhp 1433 rpmhpd_opp_svs_l1: opp-192 {
1491 1434 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1492 }; 1435 };
1493 1436
1494 rpmhp 1437 rpmhpd_opp_nom: opp-256 {
1495 1438 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1496 }; 1439 };
1497 1440
1498 rpmhp 1441 rpmhpd_opp_nom_l1: opp-320 {
1499 1442 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1500 }; 1443 };
1501 1444
1502 rpmhp 1445 rpmhpd_opp_nom_l2: opp-336 {
1503 1446 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1504 }; 1447 };
1505 1448
1506 rpmhp 1449 rpmhpd_opp_turbo: opp-384 {
1507 1450 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1508 }; 1451 };
1509 1452
1510 rpmhp 1453 rpmhpd_opp_turbo_l1: opp-416 {
1511 1454 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1512 }; 1455 };
1513 }; 1456 };
1514 }; 1457 };
1515 }; 1458 };
1516 1459
1517 cpufreq_hw: cpufreq@17d91000 1460 cpufreq_hw: cpufreq@17d91000 {
1518 compatible = "qcom,sd 1461 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1519 reg = <0x0 0x17d91000 1462 reg = <0x0 0x17d91000 0x0 0x1000>;
1520 reg-names = "freq-dom 1463 reg-names = "freq-domain0";
1521 clocks = <&rpmhcc RPM 1464 clocks = <&rpmhcc RPMH_CXO_CLK>,
1522 <&gcc GPLL0> 1465 <&gcc GPLL0>;
1523 clock-names = "xo", 1466 clock-names = "xo",
1524 "altern 1467 "alternate";
1525 interrupts = <GIC_SPI 1468 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1526 interrupt-names = "dc 1469 interrupt-names = "dcvsh-irq-0";
1527 #freq-domain-cells = 1470 #freq-domain-cells = <1>;
1528 #clock-cells = <1>; 1471 #clock-cells = <1>;
1529 }; 1472 };
1530 1473
1531 dc_noc: interconnect@190e0000 1474 dc_noc: interconnect@190e0000 {
1532 compatible = "qcom,sd 1475 compatible = "qcom,sdx75-dc-noc";
1533 reg = <0x0 0x190e0000 1476 reg = <0x0 0x190e0000 0x0 0x8200>;
1534 #interconnect-cells = 1477 #interconnect-cells = <2>;
1535 qcom,bcm-voters = <&a 1478 qcom,bcm-voters = <&apps_bcm_voter>;
1536 }; 1479 };
1537 1480
1538 gem_noc: interconnect@1910000 1481 gem_noc: interconnect@19100000 {
1539 compatible = "qcom,sd 1482 compatible = "qcom,sdx75-gem-noc";
1540 reg = <0x0 0x19100000 1483 reg = <0x0 0x19100000 0x0 0x34080>;
1541 #interconnect-cells = 1484 #interconnect-cells = <2>;
1542 qcom,bcm-voters = <&a 1485 qcom,bcm-voters = <&apps_bcm_voter>;
1543 }; 1486 };
1544 }; 1487 };
1545 1488
1546 timer { 1489 timer {
1547 compatible = "arm,armv8-timer 1490 compatible = "arm,armv8-timer";
1548 interrupts = <GIC_PPI 13 (GIC 1491 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1549 <GIC_PPI 14 (GIC 1492 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1550 <GIC_PPI 11 (GIC 1493 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1551 <GIC_PPI 12 (GIC 1494 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1552 }; 1495 };
1553 }; 1496 };
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