1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SDX75 SoC device tree source 3 * SDX75 SoC device tree source
4 * 4 *
5 * Copyright (c) 2023 Qualcomm Innovation Cent 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,rpmh.h> 9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h> 10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> <<
12 #include <dt-bindings/gpio/gpio.h> <<
13 #include <dt-bindings/interconnect/qcom,icc.h> <<
14 #include <dt-bindings/interconnect/qcom,sdx75. <<
15 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> <<
17 #include <dt-bindings/power/qcom,rpmhpd.h> <<
18 #include <dt-bindings/power/qcom-rpmpd.h> <<
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 13
21 / { 14 / {
22 #address-cells = <2>; 15 #address-cells = <2>;
23 #size-cells = <2>; 16 #size-cells = <2>;
24 interrupt-parent = <&intc>; 17 interrupt-parent = <&intc>;
25 18
26 chosen: chosen { }; 19 chosen: chosen { };
27 20
28 clocks { 21 clocks {
29 xo_board: xo-board { 22 xo_board: xo-board {
30 compatible = "fixed-cl 23 compatible = "fixed-clock";
31 clock-frequency = <768 24 clock-frequency = <76800000>;
32 #clock-cells = <0>; 25 #clock-cells = <0>;
33 }; 26 };
34 27
35 sleep_clk: sleep-clk { 28 sleep_clk: sleep-clk {
36 compatible = "fixed-cl 29 compatible = "fixed-clock";
37 clock-frequency = <320 30 clock-frequency = <32000>;
38 #clock-cells = <0>; 31 #clock-cells = <0>;
39 }; 32 };
40 }; 33 };
41 34
42 cpus { 35 cpus {
43 #address-cells = <2>; 36 #address-cells = <2>;
44 #size-cells = <0>; 37 #size-cells = <0>;
45 38
46 CPU0: cpu@0 { 39 CPU0: cpu@0 {
47 device_type = "cpu"; 40 device_type = "cpu";
48 compatible = "arm,cort 41 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>; 42 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 43 clocks = <&cpufreq_hw 0>;
51 enable-method = "psci" 44 enable-method = "psci";
52 power-domains = <&CPU_ 45 power-domains = <&CPU_PD0>;
53 power-domain-names = " 46 power-domain-names = "psci";
54 qcom,freq-domain = <&c 47 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = < 48 capacity-dmips-mhz = <1024>;
56 dynamic-power-coeffici 49 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L 50 next-level-cache = <&L2_0>;
58 51
59 L2_0: l2-cache { 52 L2_0: l2-cache {
60 compatible = " 53 compatible = "cache";
61 cache-level = 54 cache-level = <2>;
62 cache-unified; 55 cache-unified;
63 next-level-cac 56 next-level-cache = <&L3_0>;
64 L3_0: l3-cache 57 L3_0: l3-cache {
65 compat 58 compatible = "cache";
66 cache- 59 cache-level = <3>;
67 cache- 60 cache-unified;
68 }; 61 };
69 }; 62 };
70 }; 63 };
71 64
72 CPU1: cpu@100 { 65 CPU1: cpu@100 {
73 device_type = "cpu"; 66 device_type = "cpu";
74 compatible = "arm,cort 67 compatible = "arm,cortex-a55";
75 reg = <0x0 0x100>; 68 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 69 clocks = <&cpufreq_hw 0>;
77 enable-method = "psci" 70 enable-method = "psci";
78 power-domains = <&CPU_ 71 power-domains = <&CPU_PD1>;
79 power-domain-names = " 72 power-domain-names = "psci";
80 qcom,freq-domain = <&c 73 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = < 74 capacity-dmips-mhz = <1024>;
82 dynamic-power-coeffici 75 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L 76 next-level-cache = <&L2_100>;
84 77
85 L2_100: l2-cache { 78 L2_100: l2-cache {
86 compatible = " 79 compatible = "cache";
87 cache-level = 80 cache-level = <2>;
88 cache-unified; 81 cache-unified;
89 next-level-cac 82 next-level-cache = <&L3_0>;
90 }; 83 };
91 }; 84 };
92 85
93 CPU2: cpu@200 { 86 CPU2: cpu@200 {
94 device_type = "cpu"; 87 device_type = "cpu";
95 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
96 reg = <0x0 0x200>; 89 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 90 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci" 91 enable-method = "psci";
99 power-domains = <&CPU_ 92 power-domains = <&CPU_PD2>;
100 power-domain-names = " 93 power-domain-names = "psci";
101 qcom,freq-domain = <&c 94 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = < 95 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici 96 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L 97 next-level-cache = <&L2_200>;
105 98
106 L2_200: l2-cache { 99 L2_200: l2-cache {
107 compatible = " 100 compatible = "cache";
108 cache-level = 101 cache-level = <2>;
109 cache-unified; 102 cache-unified;
110 next-level-cac 103 next-level-cache = <&L3_0>;
111 }; 104 };
112 }; 105 };
113 106
114 CPU3: cpu@300 { 107 CPU3: cpu@300 {
115 device_type = "cpu"; 108 device_type = "cpu";
116 compatible = "arm,cort 109 compatible = "arm,cortex-a55";
117 reg = <0x0 0x300>; 110 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 111 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci" 112 enable-method = "psci";
120 power-domains = <&CPU_ 113 power-domains = <&CPU_PD3>;
121 power-domain-names = " 114 power-domain-names = "psci";
122 qcom,freq-domain = <&c 115 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = < 116 capacity-dmips-mhz = <1024>;
124 dynamic-power-coeffici 117 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L 118 next-level-cache = <&L2_300>;
126 119
127 L2_300: l2-cache { 120 L2_300: l2-cache {
128 compatible = " 121 compatible = "cache";
129 cache-level = 122 cache-level = <2>;
130 cache-unified; 123 cache-unified;
131 next-level-cac 124 next-level-cache = <&L3_0>;
132 }; 125 };
133 }; 126 };
134 127
135 cpu-map { 128 cpu-map {
136 cluster0 { 129 cluster0 {
137 core0 { 130 core0 {
138 cpu = 131 cpu = <&CPU0>;
139 }; 132 };
140 133
141 core1 { 134 core1 {
142 cpu = 135 cpu = <&CPU1>;
143 }; 136 };
144 137
145 core2 { 138 core2 {
146 cpu = 139 cpu = <&CPU2>;
147 }; 140 };
148 141
149 core3 { 142 core3 {
150 cpu = 143 cpu = <&CPU3>;
151 }; 144 };
152 }; 145 };
153 }; 146 };
154 147
155 idle-states { 148 idle-states {
156 entry-method = "psci"; 149 entry-method = "psci";
157 150
158 CPU_OFF: cpu-sleep-0 { 151 CPU_OFF: cpu-sleep-0 {
159 compatible = " 152 compatible = "arm,idle-state";
160 entry-latency- 153 entry-latency-us = <235>;
161 exit-latency-u 154 exit-latency-us = <428>;
162 min-residency- 155 min-residency-us = <1774>;
163 arm,psci-suspe 156 arm,psci-suspend-param = <0x40000003>;
164 local-timer-st 157 local-timer-stop;
165 }; 158 };
166 159
167 CPU_RAIL_OFF: cpu-rail 160 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = " 161 compatible = "arm,idle-state";
169 entry-latency- 162 entry-latency-us = <800>;
170 exit-latency-u 163 exit-latency-us = <750>;
171 min-residency- 164 min-residency-us = <4090>;
172 arm,psci-suspe 165 arm,psci-suspend-param = <0x40000004>;
173 local-timer-st 166 local-timer-stop;
174 }; 167 };
175 168
176 }; 169 };
177 170
178 domain-idle-states { 171 domain-idle-states {
179 CLUSTER_SLEEP_0: clust 172 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = " 173 compatible = "domain-idle-state";
181 arm,psci-suspe 174 arm,psci-suspend-param = <0x41000044>;
182 entry-latency- 175 entry-latency-us = <1050>;
183 exit-latency-u 176 exit-latency-us = <2500>;
184 min-residency- 177 min-residency-us = <5309>;
185 }; 178 };
186 179
187 CLUSTER_SLEEP_1: clust 180 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = " 181 compatible = "domain-idle-state";
189 arm,psci-suspe 182 arm,psci-suspend-param = <0x41001344>;
190 entry-latency- 183 entry-latency-us = <2761>;
191 exit-latency-u 184 exit-latency-us = <3964>;
192 min-residency- 185 min-residency-us = <8467>;
193 }; 186 };
194 187
195 CLUSTER_SLEEP_2: clust 188 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = " 189 compatible = "domain-idle-state";
197 arm,psci-suspe 190 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency- 191 entry-latency-us = <2793>;
199 exit-latency-u 192 exit-latency-us = <4023>;
200 min-residency- 193 min-residency-us = <9826>;
201 }; 194 };
202 }; 195 };
203 }; 196 };
204 197
205 firmware { 198 firmware {
206 scm: scm { 199 scm: scm {
207 compatible = "qcom,scm 200 compatible = "qcom,scm-sdx75", "qcom,scm";
208 }; 201 };
209 }; 202 };
210 203
211 clk_virt: interconnect-0 { <<
212 compatible = "qcom,sdx75-clk-v <<
213 #interconnect-cells = <2>; <<
214 qcom,bcm-voters = <&apps_bcm_v <<
215 clocks = <&rpmhcc RPMH_QPIC_CL <<
216 }; <<
217 <<
218 mc_virt: interconnect-1 { <<
219 compatible = "qcom,sdx75-mc-vi <<
220 #interconnect-cells = <2>; <<
221 qcom,bcm-voters = <&apps_bcm_v <<
222 }; <<
223 <<
224 memory@80000000 { 204 memory@80000000 {
225 device_type = "memory"; 205 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0> 206 reg = <0x0 0x80000000 0x0 0x0>;
227 }; 207 };
228 208
229 pmu { 209 pmu {
230 compatible = "arm,cortex-a55-p !! 210 compatible = "arm,armv8-pmuv3";
231 interrupts = <GIC_PPI 7 IRQ_TY 211 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 }; 212 };
233 213
234 psci { 214 psci {
235 compatible = "arm,psci-1.0"; 215 compatible = "arm,psci-1.0";
236 method = "smc"; 216 method = "smc";
237 217
238 CPU_PD0: power-domain-cpu0 { 218 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = 219 #power-domain-cells = <0>;
240 power-domains = <&CLUS 220 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = < 221 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
242 }; 222 };
243 223
244 CPU_PD1: power-domain-cpu1 { 224 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = 225 #power-domain-cells = <0>;
246 power-domains = <&CLUS 226 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = < 227 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
248 }; 228 };
249 229
250 CPU_PD2: power-domain-cpu2 { 230 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = 231 #power-domain-cells = <0>;
252 power-domains = <&CLUS 232 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = < 233 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
254 }; 234 };
255 235
256 CPU_PD3: power-domain-cpu3 { 236 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = 237 #power-domain-cells = <0>;
258 power-domains = <&CLUS 238 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = < 239 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
260 }; 240 };
261 241
262 CLUSTER_PD: power-domain-cpu-c 242 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = 243 #power-domain-cells = <0>;
264 domain-idle-states = < 244 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 }; 245 };
266 }; 246 };
267 247
268 reserved-memory { 248 reserved-memory {
269 #address-cells = <2>; 249 #address-cells = <2>;
270 #size-cells = <2>; 250 #size-cells = <2>;
271 ranges; 251 ranges;
272 252
273 gunyah_hyp_mem: gunyah-hyp@800 253 gunyah_hyp_mem: gunyah-hyp@80000000 {
274 reg = <0x0 0x80000000 254 reg = <0x0 0x80000000 0x0 0x800000>;
275 no-map; 255 no-map;
276 }; 256 };
277 257
278 hyp_elf_package_mem: hyp-elf-p 258 hyp_elf_package_mem: hyp-elf-package@80800000 {
279 reg = <0x0 0x80800000 259 reg = <0x0 0x80800000 0x0 0x200000>;
280 no-map; 260 no-map;
281 }; 261 };
282 262
283 access_control_db_mem: access- 263 access_control_db_mem: access-control-db@81380000 {
284 reg = <0x0 0x81380000 264 reg = <0x0 0x81380000 0x0 0x80000>;
285 no-map; 265 no-map;
286 }; 266 };
287 267
288 qteetz_mem: qteetz@814e0000 { 268 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000 269 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 no-map; 270 no-map;
291 }; 271 };
292 272
293 trusted_apps_mem: trusted-apps 273 trusted_apps_mem: trusted-apps@81780000 {
294 reg = <0x0 0x81780000 274 reg = <0x0 0x81780000 0x0 0xa00000>;
295 no-map; 275 no-map;
296 }; 276 };
297 277
298 xbl_ramdump_mem: xbl-ramdump@8 278 xbl_ramdump_mem: xbl-ramdump@87a00000 {
299 reg = <0x0 0x87a00000 279 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 no-map; 280 no-map;
301 }; 281 };
302 282
303 cpucp_fw_mem: cpucp-fw@87c0000 283 cpucp_fw_mem: cpucp-fw@87c00000 {
304 reg = <0x0 0x87c00000 284 reg = <0x0 0x87c00000 0x0 0x100000>;
305 no-map; 285 no-map;
306 }; 286 };
307 287
308 xbl_dtlog_mem: xbl-dtlog@87d00 288 xbl_dtlog_mem: xbl-dtlog@87d00000 {
309 reg = <0x0 0x87d00000 289 reg = <0x0 0x87d00000 0x0 0x40000>;
310 no-map; 290 no-map;
311 }; 291 };
312 292
313 xbl_sc_mem: xbl-sc@87d40000 { 293 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000 294 reg = <0x0 0x87d40000 0x0 0x40000>;
315 no-map; 295 no-map;
316 }; 296 };
317 297
318 modem_efs_shared_mem: modem-ef 298 modem_efs_shared_mem: modem-efs-shared@87d80000 {
319 reg = <0x0 0x87d80000 299 reg = <0x0 0x87d80000 0x0 0x10000>;
320 no-map; 300 no-map;
321 }; 301 };
322 302
323 aop_image_mem: aop-image@87e00 303 aop_image_mem: aop-image@87e00000 {
324 reg = <0x0 0x87e00000 304 reg = <0x0 0x87e00000 0x0 0x20000>;
325 no-map; 305 no-map;
326 }; 306 };
327 307
328 smem_mem: smem@87e20000 { 308 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000 309 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 no-map; 310 no-map;
331 }; 311 };
332 312
333 aop_cmd_db_mem: aop-cmd-db@87e 313 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd 314 compatible = "qcom,cmd-db";
335 reg = <0x0 0x87ee0000 315 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 no-map; 316 no-map;
337 }; 317 };
338 318
339 aop_config_mem: aop-config@87f 319 aop_config_mem: aop-config@87f00000 {
340 reg = <0x0 0x87f00000 320 reg = <0x0 0x87f00000 0x0 0x20000>;
341 no-map; 321 no-map;
342 }; 322 };
343 323
344 ipa_fw_mem: ipa-fw@87f20000 { 324 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000 325 reg = <0x0 0x87f20000 0x0 0x10000>;
346 no-map; 326 no-map;
347 }; 327 };
348 328
349 secdata_mem: secdata@87f30000 329 secdata_mem: secdata@87f30000 {
350 reg = <0x0 0x87f30000 330 reg = <0x0 0x87f30000 0x0 0x1000>;
351 no-map; 331 no-map;
352 }; 332 };
353 333
354 tme_crashdump_mem: tme-crashdu 334 tme_crashdump_mem: tme-crashdump@87f31000 {
355 reg = <0x0 0x87f31000 335 reg = <0x0 0x87f31000 0x0 0x40000>;
356 no-map; 336 no-map;
357 }; 337 };
358 338
359 tme_log_mem: tme-log@87f71000 339 tme_log_mem: tme-log@87f71000 {
360 reg = <0x0 0x87f71000 340 reg = <0x0 0x87f71000 0x0 0x4000>;
361 no-map; 341 no-map;
362 }; 342 };
363 343
364 uefi_log_mem: uefi-log@87f7500 344 uefi_log_mem: uefi-log@87f75000 {
365 reg = <0x0 0x87f75000 345 reg = <0x0 0x87f75000 0x0 0x10000>;
366 no-map; 346 no-map;
367 }; 347 };
368 348
369 qdss_mem: qdss@88500000 { !! 349 qdss_mem: qdss@88800000 {
370 reg = <0x0 0x88500000 <<
371 no-map; <<
372 }; <<
373 <<
374 qlink_logging_mem: qlink-loggi <<
375 reg = <0x0 0x88800000 350 reg = <0x0 0x88800000 0x0 0x300000>;
376 no-map; 351 no-map;
377 }; 352 };
378 353
379 audio_heap_mem: audio-heap@88b 354 audio_heap_mem: audio-heap@88b00000 {
380 compatible = "shared-d 355 compatible = "shared-dma-pool";
381 reg = <0x0 0x88b00000 356 reg = <0x0 0x88b00000 0x0 0x400000>;
382 no-map; 357 no-map;
383 }; 358 };
384 359
385 mpss_dsm_mem_2: mpss-dsm-2@88f !! 360 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
386 reg = <0x0 0x88f00000 !! 361 reg = <0x0 0x88f00000 0x0 0x5080000>;
387 no-map; <<
388 }; <<
389 <<
390 mpss_dsm_mem: mpss-dsm@8b40000 <<
391 reg = <0x0 0x8b400000 <<
392 no-map; 362 no-map;
393 }; 363 };
394 364
395 q6_mpss_dtb_mem: q6-mpss-dtb@8 365 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
396 reg = <0x0 0x8df80000 366 reg = <0x0 0x8df80000 0x0 0x80000>;
397 no-map; 367 no-map;
398 }; 368 };
399 369
400 mpssadsp_mem: mpssadsp@8e00000 370 mpssadsp_mem: mpssadsp@8e000000 {
401 reg = <0x0 0x8e000000 !! 371 reg = <0x0 0x8e000000 0x0 0xf400000>;
402 no-map; 372 no-map;
403 }; 373 };
404 374
405 gunyah_trace_buffer_mem: gunya 375 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
406 reg = <0x0 0xbdb00000 376 reg = <0x0 0xbdb00000 0x0 0x2000000>;
407 no-map; 377 no-map;
408 }; 378 };
409 379
410 smmu_debug_buf_mem: smmu-debug 380 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
411 reg = <0x0 0xbfb00000 381 reg = <0x0 0xbfb00000 0x0 0x100000>;
412 no-map; 382 no-map;
413 }; 383 };
414 384
415 hyp_smmu_s2_pt_mem: hyp-smmu-s 385 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
416 reg = <0x0 0xbfc00000 386 reg = <0x0 0xbfc00000 0x0 0x400000>;
417 no-map; 387 no-map;
418 }; 388 };
419 }; 389 };
420 390
421 smp2p-modem { !! 391 smem: qcom,smem {
422 compatible = "qcom,smp2p"; <<
423 qcom,smem = <435>, <428>; <<
424 interrupts-extended = <&ipcc I <<
425 I <<
426 I <<
427 mboxes = <&ipcc IPCC_CLIENT_MP <<
428 IPCC_MPROC_SIG <<
429 <<
430 qcom,local-pid = <0>; <<
431 qcom,remote-pid = <1>; <<
432 <<
433 smp2p_modem_out: master-kernel <<
434 qcom,entry-name = "mas <<
435 #qcom,smem-state-cells <<
436 }; <<
437 <<
438 smp2p_modem_in: slave-kernel { <<
439 qcom,entry-name = "sla <<
440 interrupt-controller; <<
441 #interrupt-cells = <2> <<
442 }; <<
443 <<
444 ipa_smp2p_out: ipa-ap-to-modem <<
445 qcom,entry-name = "ipa <<
446 #qcom,smem-state-cells <<
447 }; <<
448 <<
449 ipa_smp2p_in: ipa-modem-to-ap <<
450 qcom,entry-name = "ipa <<
451 interrupt-controller; <<
452 #interrupt-cells = <2> <<
453 }; <<
454 }; <<
455 <<
456 smem: smem { <<
457 compatible = "qcom,smem"; 392 compatible = "qcom,smem";
458 memory-region = <&smem_mem>; 393 memory-region = <&smem_mem>;
459 hwlocks = <&tcsr_mutex 3>; 394 hwlocks = <&tcsr_mutex 3>;
460 }; 395 };
461 396
462 soc: soc@0 { !! 397 soc: soc {
463 compatible = "simple-bus"; 398 compatible = "simple-bus";
464 #address-cells = <2>; 399 #address-cells = <2>;
465 #size-cells = <2>; 400 #size-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>; 401 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>; 402 dma-ranges = <0 0 0 0 0x10 0>;
468 403
469 gcc: clock-controller@80000 { 404 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx 405 compatible = "qcom,sdx75-gcc";
471 reg = <0x0 0x0080000 0 406 reg = <0x0 0x0080000 0x0 0x1f7400>;
472 clocks = <&rpmhcc RPMH 407 clocks = <&rpmhcc RPMH_CXO_CLK>,
473 <&sleep_clk>, 408 <&sleep_clk>,
474 <0>, 409 <0>,
475 <0>, 410 <0>,
476 <0>, 411 <0>,
477 <0>, 412 <0>,
478 <0>, 413 <0>,
479 <0>, 414 <0>,
480 <0>, 415 <0>,
481 <0>, 416 <0>,
482 <0>, 417 <0>,
483 <0>, 418 <0>,
484 <0>, 419 <0>,
485 <0>, 420 <0>,
486 <0>; 421 <0>;
487 #clock-cells = <1>; 422 #clock-cells = <1>;
488 #reset-cells = <1>; 423 #reset-cells = <1>;
489 #power-domain-cells = 424 #power-domain-cells = <1>;
490 }; 425 };
491 426
492 ipcc: mailbox@408000 { <<
493 compatible = "qcom,sdx <<
494 reg = <0 0x00408000 0 <<
495 interrupts = <GIC_SPI <<
496 interrupt-controller; <<
497 #interrupt-cells = <3> <<
498 #mbox-cells = <2>; <<
499 }; <<
500 <<
501 gpi_dma: dma-controller@900000 <<
502 compatible = "qcom,sdx <<
503 reg = <0x0 0x00900000 <<
504 #dma-cells = <3>; <<
505 interrupts = <GIC_SPI <<
506 <GIC_SPI <<
507 <GIC_SPI <<
508 <GIC_SPI <<
509 <GIC_SPI <<
510 <GIC_SPI <<
511 <GIC_SPI <<
512 <GIC_SPI <<
513 <GIC_SPI <<
514 <GIC_SPI <<
515 <GIC_SPI <<
516 <GIC_SPI <<
517 dma-channels = <12>; <<
518 dma-channel-mask = <0x <<
519 iommus = <&apps_smmu 0 <<
520 status = "disabled"; <<
521 }; <<
522 <<
523 qupv3_id_0: geniqup@9c0000 { 427 qupv3_id_0: geniqup@9c0000 {
524 compatible = "qcom,gen 428 compatible = "qcom,geni-se-qup";
525 reg = <0x0 0x009c0000 429 reg = <0x0 0x009c0000 0x0 0x2000>;
526 clocks = <&gcc GCC_QUP 430 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
527 <&gcc GCC_QUP 431 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
528 clock-names = "m-ahb", 432 clock-names = "m-ahb",
529 "s-ahb"; 433 "s-ahb";
530 iommus = <&apps_smmu 0 434 iommus = <&apps_smmu 0xe3 0x0>;
531 interconnects = <&clk_ <<
532 &clk_ <<
533 interconnect-names = " <<
534 #address-cells = <2>; 435 #address-cells = <2>;
535 #size-cells = <2>; 436 #size-cells = <2>;
536 ranges; 437 ranges;
537 status = "disabled"; 438 status = "disabled";
538 439
539 i2c0: i2c@980000 { <<
540 compatible = " <<
541 reg = <0x0 0x0 <<
542 clocks = <&gcc <<
543 clock-names = <<
544 interrupts = < <<
545 #address-cells <<
546 #size-cells = <<
547 pinctrl-0 = <& <<
548 pinctrl-names <<
549 interconnects <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 interconnect-n <<
556 dmas = <&gpi_d <<
557 <&gpi_d <<
558 dma-names = "t <<
559 status = "disa <<
560 }; <<
561 <<
562 spi0: spi@980000 { <<
563 compatible = " <<
564 reg = <0x0 0x0 <<
565 clocks = <&gcc <<
566 clock-names = <<
567 interrupts = < <<
568 #address-cells <<
569 #size-cells = <<
570 pinctrl-0 = <& <<
571 pinctrl-names <<
572 interconnects <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 interconnect-n <<
579 dmas = <&gpi_d <<
580 <&gpi_d <<
581 dma-names = "t <<
582 status = "disa <<
583 }; <<
584 <<
585 uart1: serial@984000 { 440 uart1: serial@984000 {
586 compatible = " 441 compatible = "qcom,geni-debug-uart";
587 reg = <0x0 0x0 442 reg = <0x0 0x00984000 0x0 0x4000>;
588 clocks = <&gcc 443 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
589 clock-names = 444 clock-names = "se";
590 interconnects <<
591 <<
592 <<
593 <<
594 interconnect-n <<
595 <<
596 interrupts = < 445 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-0 = <& 446 pinctrl-0 = <&qupv3_se1_2uart_active>;
598 pinctrl-1 = <& 447 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
599 pinctrl-names 448 pinctrl-names = "default",
600 449 "sleep";
601 status = "disa 450 status = "disabled";
602 }; 451 };
603 <<
604 i2c2: i2c@988000 { <<
605 compatible = " <<
606 reg = <0x0 0x0 <<
607 clocks = <&gcc <<
608 clock-names = <<
609 interrupts = < <<
610 #address-cells <<
611 #size-cells = <<
612 pinctrl-0 = <& <<
613 pinctrl-names <<
614 interconnects <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 interconnect-n <<
621 dmas = <&gpi_d <<
622 <&gpi_d <<
623 dma-names = "t <<
624 status = "disa <<
625 }; <<
626 <<
627 spi2: spi@988000 { <<
628 compatible = " <<
629 reg = <0x0 0x0 <<
630 clocks = <&gcc <<
631 clock-names = <<
632 interrupts = < <<
633 #address-cells <<
634 #size-cells = <<
635 pinctrl-0 = <& <<
636 pinctrl-names <<
637 interconnects <<
638 <<
639 <<
640 <<
641 <<
642 <<
643 interconnect-n <<
644 dmas = <&gpi_d <<
645 <&gpi_d <<
646 dma-names = "t <<
647 status = "disa <<
648 }; <<
649 <<
650 i2c3: i2c@98c000 { <<
651 compatible = " <<
652 reg = <0x0 0x0 <<
653 clocks = <&gcc <<
654 clock-names = <<
655 interrupts = < <<
656 #address-cells <<
657 #size-cells = <<
658 pinctrl-0 = <& <<
659 pinctrl-names <<
660 interconnects <<
661 <<
662 <<
663 <<
664 <<
665 <<
666 interconnect-n <<
667 dmas = <&gpi_d <<
668 <&gpi_d <<
669 dma-names = "t <<
670 status = "disa <<
671 }; <<
672 <<
673 spi3: spi@98c000 { <<
674 compatible = " <<
675 reg = <0x0 0x0 <<
676 clocks = <&gcc <<
677 clock-names = <<
678 interrupts = < <<
679 #address-cells <<
680 #size-cells = <<
681 pinctrl-0 = <& <<
682 pinctrl-names <<
683 interconnects <<
684 <<
685 <<
686 <<
687 <<
688 <<
689 interconnect-n <<
690 dmas = <&gpi_d <<
691 <&gpi_d <<
692 dma-names = "t <<
693 status = "disa <<
694 }; <<
695 <<
696 uart4: serial@990000 { <<
697 compatible = " <<
698 reg = <0x0 0x0 <<
699 clocks = <&gcc <<
700 clock-names = <<
701 interrupts = < <<
702 pinctrl-0 = <& <<
703 pinctrl-names <<
704 interconnects <<
705 <<
706 <<
707 <<
708 interconnect-n <<
709 status = "disa <<
710 }; <<
711 <<
712 i2c5: i2c@994000 { <<
713 compatible = " <<
714 reg = <0x0 0x0 <<
715 clocks = <&gcc <<
716 clock-names = <<
717 interrupts = < <<
718 #address-cells <<
719 #size-cells = <<
720 pinctrl-0 = <& <<
721 pinctrl-names <<
722 interconnects <<
723 <<
724 <<
725 <<
726 <<
727 <<
728 interconnect-n <<
729 dmas = <&gpi_d <<
730 <&gpi_d <<
731 dma-names = "t <<
732 status = "disa <<
733 }; <<
734 <<
735 i2c6: i2c@998000 { <<
736 compatible = " <<
737 reg = <0x0 0x0 <<
738 clocks = <&gcc <<
739 clock-names = <<
740 interrupts = < <<
741 #address-cells <<
742 #size-cells = <<
743 pinctrl-0 = <& <<
744 pinctrl-names <<
745 interconnects <<
746 <<
747 <<
748 <<
749 <<
750 <<
751 interconnect-n <<
752 dmas = <&gpi_d <<
753 <&gpi_d <<
754 dma-names = "t <<
755 status = "disa <<
756 }; <<
757 <<
758 spi6: spi@998000 { <<
759 compatible = " <<
760 reg = <0x0 0x0 <<
761 clocks = <&gcc <<
762 clock-names = <<
763 interrupts = < <<
764 #address-cells <<
765 #size-cells = <<
766 pinctrl-0 = <& <<
767 pinctrl-names <<
768 interconnects <<
769 <<
770 <<
771 <<
772 <<
773 <<
774 interconnect-n <<
775 dmas = <&gpi_d <<
776 <&gpi_d <<
777 dma-names = "t <<
778 status = "disa <<
779 }; <<
780 <<
781 i2c7: i2c@99c000 { <<
782 compatible = " <<
783 reg = <0x0 0x0 <<
784 clocks = <&gcc <<
785 clock-names = <<
786 interrupts = < <<
787 #address-cells <<
788 #size-cells = <<
789 pinctrl-0 = <& <<
790 pinctrl-names <<
791 interconnects <<
792 <<
793 <<
794 <<
795 <<
796 <<
797 interconnect-n <<
798 dmas = <&gpi_d <<
799 <&gpi_d <<
800 dma-names = "t <<
801 status = "disa <<
802 }; <<
803 <<
804 spi7: spi@99c000 { <<
805 compatible = " <<
806 reg = <0x0 0x0 <<
807 clocks = <&gcc <<
808 clock-names = <<
809 interrupts = < <<
810 #address-cells <<
811 #size-cells = <<
812 pinctrl-0 = <& <<
813 pinctrl-names <<
814 interconnects <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 interconnect-n <<
821 dmas = <&gpi_d <<
822 <&gpi_d <<
823 dma-names = "t <<
824 status = "disa <<
825 }; <<
826 }; <<
827 <<
828 usb_hsphy: phy@ff4000 { <<
829 compatible = "qcom,sdx <<
830 reg = <0x0 0x00ff4000 <<
831 #phy-cells = <0>; <<
832 <<
833 clocks = <&rpmhcc RPMH <<
834 clock-names = "ref"; <<
835 <<
836 resets = <&gcc GCC_QUS <<
837 <<
838 status = "disabled"; <<
839 }; <<
840 <<
841 usb_qmpphy: phy@ff6000 { <<
842 compatible = "qcom,sdx <<
843 reg = <0x0 0x00ff6000 <<
844 <<
845 clocks = <&gcc GCC_USB <<
846 <&gcc GCC_USB <<
847 <&gcc GCC_USB <<
848 <&gcc GCC_USB <<
849 clock-names = "aux", <<
850 "ref", <<
851 "cfg_ahb <<
852 "pipe"; <<
853 <<
854 power-domains = <&gcc <<
855 <<
856 resets = <&gcc GCC_USB <<
857 <&gcc GCC_USB <<
858 reset-names = "phy", <<
859 "phy_phy <<
860 <<
861 #clock-cells = <0>; <<
862 clock-output-names = " <<
863 <<
864 #phy-cells = <0>; <<
865 <<
866 status = "disabled"; <<
867 }; <<
868 <<
869 system_noc: interconnect@16400 <<
870 compatible = "qcom,sdx <<
871 reg = <0x0 0x01640000 <<
872 #interconnect-cells = <<
873 qcom,bcm-voters = <&ap <<
874 }; <<
875 <<
876 pcie_anoc: interconnect@16c000 <<
877 compatible = "qcom,sdx <<
878 reg = <0x0 0x016c0000 <<
879 #interconnect-cells = <<
880 qcom,bcm-voters = <&ap <<
881 }; 452 };
882 453
883 tcsr_mutex: hwlock@1f40000 { 454 tcsr_mutex: hwlock@1f40000 {
884 compatible = "qcom,tcs 455 compatible = "qcom,tcsr-mutex";
885 reg = <0x0 0x01f40000 456 reg = <0x0 0x01f40000 0x0 0x40000>;
886 #hwlock-cells = <1>; 457 #hwlock-cells = <1>;
887 }; 458 };
888 459
889 tcsr: syscon@1fc0000 { <<
890 compatible = "qcom,sdx <<
891 reg = <0x0 0x01fc0000 <<
892 }; <<
893 <<
894 remoteproc_mpss: remoteproc@40 <<
895 compatible = "qcom,sdx <<
896 reg = <0 0x04080000 0 <<
897 <<
898 interrupts-extended = <<
899 <<
900 <<
901 <<
902 <<
903 <<
904 interrupt-names = "wdo <<
905 "fat <<
906 "rea <<
907 "han <<
908 "sto <<
909 "shu <<
910 <<
911 clocks = <&rpmhcc RPMH <<
912 clock-names = "xo"; <<
913 <<
914 power-domains = <&rpmh <<
915 <&rpmh <<
916 power-domain-names = " <<
917 " <<
918 <<
919 memory-region = <&mpss <<
920 <&mpss <<
921 <&qlin <<
922 <<
923 qcom,qmp = <&aoss_qmp> <<
924 <<
925 qcom,smem-states = <&s <<
926 qcom,smem-state-names <<
927 <<
928 status = "disabled"; <<
929 <<
930 glink-edge { <<
931 interrupts-ext <<
932 <<
933 <<
934 mboxes = <&ipc <<
935 <<
936 label = "mpss" <<
937 qcom,remote-pi <<
938 }; <<
939 }; <<
940 <<
941 sdhc: mmc@8804000 { <<
942 compatible = "qcom,sdx <<
943 reg = <0x0 0x08804000 <<
944 <<
945 interrupts = <GIC_SPI <<
946 <GIC_SPI <<
947 interrupt-names = "hc_ <<
948 "pwr <<
949 <<
950 clocks = <&gcc GCC_SDC <<
951 <&gcc GCC_SDC <<
952 <&rpmhcc RPMH <<
953 clock-names = "iface", <<
954 "core", <<
955 "xo"; <<
956 iommus = <&apps_smmu 0 <<
957 qcom,dll-config = <0x0 <<
958 qcom,ddr-config = <0x8 <<
959 power-domains = <&rpmh <<
960 operating-points-v2 = <<
961 <<
962 interconnects = <&syst <<
963 <&gem_ <<
964 interconnect-names = " <<
965 " <<
966 bus-width = <4>; <<
967 dma-coherent; <<
968 <<
969 /* Forbid SDR104/SDR50 <<
970 sdhci-caps-mask = <0x3 <<
971 <<
972 status = "disabled"; <<
973 <<
974 sdhc1_opp_table: opp-t <<
975 compatible = " <<
976 <<
977 opp-100000000 <<
978 opp-hz <<
979 requir <<
980 }; <<
981 <<
982 opp-384000000 <<
983 opp-hz <<
984 requir <<
985 }; <<
986 }; <<
987 }; <<
988 <<
989 usb: usb@a6f8800 { <<
990 compatible = "qcom,sdx <<
991 reg = <0x0 0x0a6f8800 <<
992 #address-cells = <2>; <<
993 #size-cells = <2>; <<
994 ranges; <<
995 <<
996 clocks = <&gcc GCC_USB <<
997 <&gcc GCC_USB <<
998 <&gcc GCC_USB <<
999 <&gcc GCC_USB <<
1000 <&gcc GCC_US <<
1001 clock-names = "cfg_no <<
1002 "core", <<
1003 "iface" <<
1004 "sleep" <<
1005 "mock_u <<
1006 <<
1007 assigned-clocks = <&g <<
1008 <&g <<
1009 assigned-clock-rates <<
1010 <<
1011 interrupts-extended = <<
1012 <<
1013 <<
1014 <<
1015 interrupt-names = "hs <<
1016 "ss <<
1017 "dm <<
1018 "dp <<
1019 <<
1020 power-domains = <&gcc <<
1021 <<
1022 resets = <&gcc GCC_US <<
1023 <<
1024 interconnects = <&sys <<
1025 &mc_ <<
1026 <&gem <<
1027 &sys <<
1028 interconnect-names = <<
1029 <<
1030 <<
1031 status = "disabled"; <<
1032 <<
1033 usb_dwc3: usb@a600000 <<
1034 compatible = <<
1035 reg = <0x0 0x <<
1036 interrupts = <<
1037 iommus = <&ap <<
1038 snps,dis_u2_s <<
1039 snps,dis_enbl <<
1040 phys = <&usb_ <<
1041 <&usb_ <<
1042 phy-names = " <<
1043 " <<
1044 <<
1045 ports { <<
1046 #addr <<
1047 #size <<
1048 <<
1049 port@ <<
1050 <<
1051 <<
1052 <<
1053 <<
1054 }; <<
1055 <<
1056 port@ <<
1057 <<
1058 <<
1059 <<
1060 <<
1061 }; <<
1062 }; <<
1063 }; <<
1064 }; <<
1065 <<
1066 pdc: interrupt-controller@b22 460 pdc: interrupt-controller@b220000 {
1067 compatible = "qcom,sd 461 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1068 reg = <0x0 0xb220000 462 reg = <0x0 0xb220000 0x0 0x30000>,
1069 <0x0 0x174000f0 463 <0x0 0x174000f0 0x0 0x64>;
1070 qcom,pdc-ranges = <0 464 qcom,pdc-ranges = <0 147 52>,
1071 <52 465 <52 266 32>,
1072 <84 466 <84 500 59>;
1073 #interrupt-cells = <2 467 #interrupt-cells = <2>;
1074 interrupt-parent = <& 468 interrupt-parent = <&intc>;
1075 interrupt-controller; 469 interrupt-controller;
1076 }; 470 };
1077 471
1078 aoss_qmp: power-controller@c3 <<
1079 compatible = "qcom,sd <<
1080 reg = <0 0x0c310000 0 <<
1081 interrupt-parent = <& <<
1082 interrupts-extended = <<
1083 <<
1084 mboxes = <&ipcc IPCC_ <<
1085 <<
1086 #clock-cells = <0>; <<
1087 }; <<
1088 <<
1089 spmi_bus: spmi@c400000 { <<
1090 compatible = "qcom,sp <<
1091 reg = <0x0 0x0c400000 <<
1092 <0x0 0x0c500000 <<
1093 <0x0 0x0c440000 <<
1094 <0x0 0x0c4c0000 <<
1095 <0x0 0x0c42d000 <<
1096 reg-names = "core", <<
1097 "chnls", <<
1098 "obsrvr", <<
1099 "intr", <<
1100 "cnfg"; <<
1101 interrupts-extended = <<
1102 interrupt-names = "pe <<
1103 qcom,ee = <0>; <<
1104 qcom,channel = <0>; <<
1105 qcom,bus-id = <0>; <<
1106 #address-cells = <2>; <<
1107 #size-cells = <0>; <<
1108 interrupt-controller; <<
1109 #interrupt-cells = <4 <<
1110 }; <<
1111 <<
1112 tlmm: pinctrl@f000000 { 472 tlmm: pinctrl@f000000 {
1113 compatible = "qcom,sd 473 compatible = "qcom,sdx75-tlmm";
1114 reg = <0x0 0x0f000000 474 reg = <0x0 0x0f000000 0x0 0x400000>;
1115 interrupts = <GIC_SPI 475 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1116 gpio-controller; 476 gpio-controller;
1117 #gpio-cells = <2>; 477 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm 478 gpio-ranges = <&tlmm 0 0 133>;
1119 interrupt-controller; 479 interrupt-controller;
1120 #interrupt-cells = <2 480 #interrupt-cells = <2>;
1121 wakeup-parent = <&pdc 481 wakeup-parent = <&pdc>;
1122 482
1123 qup_i2c0_data_clk: qu <<
1124 /* SDA, SCL * <<
1125 pins = "gpio8 <<
1126 function = "q <<
1127 drive-strengt <<
1128 bias-pull-up; <<
1129 }; <<
1130 <<
1131 qup_i2c2_data_clk: qu <<
1132 /* SDA, SCL * <<
1133 pins = "gpio1 <<
1134 function = "q <<
1135 drive-strengt <<
1136 bias-pull-up; <<
1137 }; <<
1138 <<
1139 qup_i2c3_data_clk: qu <<
1140 /* SDA, SCL * <<
1141 pins = "gpio5 <<
1142 function = "q <<
1143 drive-strengt <<
1144 bias-pull-up; <<
1145 }; <<
1146 <<
1147 qup_i2c5_data_clk: qu <<
1148 /* SDA, SCL * <<
1149 pins = "gpio1 <<
1150 function = "q <<
1151 drive-strengt <<
1152 bias-pull-up; <<
1153 }; <<
1154 <<
1155 qup_i2c6_data_clk: qu <<
1156 /* SDA, SCL * <<
1157 pins = "gpio1 <<
1158 function = "q <<
1159 drive-strengt <<
1160 bias-pull-up; <<
1161 }; <<
1162 <<
1163 qup_i2c7_data_clk: qu <<
1164 /* SDA, SCL * <<
1165 pins = "gpio1 <<
1166 function = "q <<
1167 drive-strengt <<
1168 bias-pull-up; <<
1169 }; <<
1170 <<
1171 qup_spi0_cs: qup-spi0 <<
1172 pins = "gpio1 <<
1173 function = "q <<
1174 drive-strengt <<
1175 bias-pull-dow <<
1176 }; <<
1177 <<
1178 qup_spi0_data_clk: qu <<
1179 /* MISO, MOSI <<
1180 pins = "gpio8 <<
1181 function = "q <<
1182 drive-strengt <<
1183 bias-pull-dow <<
1184 }; <<
1185 <<
1186 qup_spi2_cs: qup-spi2 <<
1187 pins = "gpio1 <<
1188 function = "q <<
1189 drive-strengt <<
1190 bias-pull-dow <<
1191 }; <<
1192 <<
1193 qup_spi2_data_clk: qu <<
1194 /* MISO, MOSI <<
1195 pins = "gpio1 <<
1196 function = "q <<
1197 drive-strengt <<
1198 bias-pull-dow <<
1199 }; <<
1200 <<
1201 qup_spi3_cs: qup-spi3 <<
1202 pins = "gpio5 <<
1203 function = "q <<
1204 drive-strengt <<
1205 bias-pull-dow <<
1206 }; <<
1207 <<
1208 qup_spi3_data_clk: qu <<
1209 /* MISO, MOSI <<
1210 pins = "gpio5 <<
1211 function = "q <<
1212 drive-strengt <<
1213 bias-pull-dow <<
1214 }; <<
1215 <<
1216 qup_spi6_cs: qup-spi6 <<
1217 pins = "gpio1 <<
1218 function = "q <<
1219 drive-strengt <<
1220 bias-pull-dow <<
1221 }; <<
1222 <<
1223 qup_spi6_data_clk: qu <<
1224 /* MISO, MOSI <<
1225 pins = "gpio1 <<
1226 function = "q <<
1227 drive-strengt <<
1228 bias-pull-dow <<
1229 }; <<
1230 <<
1231 qup_spi7_cs: qup-spi7 <<
1232 pins = "gpio1 <<
1233 function = "q <<
1234 drive-strengt <<
1235 bias-pull-dow <<
1236 }; <<
1237 <<
1238 qup_spi7_data_clk: qu <<
1239 /* MISO, MOSI <<
1240 pins = "gpio1 <<
1241 function = "q <<
1242 drive-strengt <<
1243 bias-pull-dow <<
1244 }; <<
1245 <<
1246 qup_uart4_cts_rts: qu <<
1247 /* CTS, RTS * <<
1248 pins = "gpio5 <<
1249 function = "q <<
1250 drive-strengt <<
1251 bias-pull-dow <<
1252 }; <<
1253 <<
1254 qup_uart4_default: qu <<
1255 /* TX, RX */ <<
1256 pins = "gpio5 <<
1257 function = "q <<
1258 drive-strengt <<
1259 bias-pull-up; <<
1260 }; <<
1261 <<
1262 qupv3_se1_2uart_activ 483 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1263 tx-pins { 484 tx-pins {
1264 pins 485 pins = "gpio12";
1265 funct 486 function = "qup_se1_l2_mira";
1266 drive 487 drive-strength = <2>;
1267 bias- 488 bias-disable;
1268 }; 489 };
1269 490
1270 rx-pins { 491 rx-pins {
1271 pins 492 pins = "gpio13";
1272 funct 493 function = "qup_se1_l3_mira";
1273 drive 494 drive-strength = <2>;
1274 bias- 495 bias-disable;
1275 }; 496 };
1276 }; 497 };
1277 498
1278 qupv3_se1_2uart_sleep 499 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1279 pins = "gpio1 500 pins = "gpio12", "gpio13";
1280 function = "g 501 function = "gpio";
1281 drive-strengt 502 drive-strength = <2>;
1282 bias-pull-dow 503 bias-pull-down;
1283 }; 504 };
1284 <<
1285 sdc1_default: sdc1-de <<
1286 clk-pins { <<
1287 pins <<
1288 drive <<
1289 bias- <<
1290 }; <<
1291 <<
1292 cmd-pins { <<
1293 pins <<
1294 drive <<
1295 bias- <<
1296 }; <<
1297 <<
1298 data-pins { <<
1299 pins <<
1300 drive <<
1301 bias- <<
1302 }; <<
1303 }; <<
1304 <<
1305 sdc1_sleep: sdc1-slee <<
1306 clk-pins { <<
1307 pins <<
1308 drive <<
1309 bias- <<
1310 }; <<
1311 <<
1312 cmd-pins { <<
1313 pins <<
1314 drive <<
1315 bias- <<
1316 }; <<
1317 <<
1318 data-pins { <<
1319 pins <<
1320 drive <<
1321 bias- <<
1322 }; <<
1323 }; <<
1324 }; 505 };
1325 506
1326 apps_smmu: iommu@15000000 { 507 apps_smmu: iommu@15000000 {
1327 compatible = "qcom,sd 508 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1328 reg = <0x0 0x15000000 509 reg = <0x0 0x15000000 0x0 0x40000>;
1329 #iommu-cells = <2>; 510 #iommu-cells = <2>;
1330 #global-interrupts = 511 #global-interrupts = <2>;
1331 dma-coherent; 512 dma-coherent;
1332 interrupts = <GIC_SPI 513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 514 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 515 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 516 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 517 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 518 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 519 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 520 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 521 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 522 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 523 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 524 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 525 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 526 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 527 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 528 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 529 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 530 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 531 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 532 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 533 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 534 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 535 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 536 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 537 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 538 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 539 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 540 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 541 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 542 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 543 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 544 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 545 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1365 }; 546 };
1366 547
1367 intc: interrupt-controller@17 548 intc: interrupt-controller@17200000 {
1368 compatible = "arm,gic 549 compatible = "arm,gic-v3";
1369 #interrupt-cells = <3 550 #interrupt-cells = <3>;
1370 interrupt-controller; 551 interrupt-controller;
1371 #redistributor-region 552 #redistributor-regions = <1>;
1372 redistributor-stride 553 redistributor-stride = <0x0 0x20000>;
1373 reg = <0x0 0x17200000 554 reg = <0x0 0x17200000 0x0 0x10000>,
1374 <0x0 0x17260000 555 <0x0 0x17260000 0x0 0x80000>;
1375 interrupts = <GIC_PPI 556 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1376 }; 557 };
1377 558
1378 timer@17420000 { 559 timer@17420000 {
1379 compatible = "arm,arm 560 compatible = "arm,armv7-timer-mem";
1380 reg = <0x0 0x17420000 561 reg = <0x0 0x17420000 0x0 0x1000>;
1381 #address-cells = <1>; 562 #address-cells = <1>;
1382 #size-cells = <1>; 563 #size-cells = <1>;
1383 ranges = <0 0 0 0x200 564 ranges = <0 0 0 0x20000000>;
1384 565
1385 frame@17421000 { 566 frame@17421000 {
1386 reg = <0x1742 567 reg = <0x17421000 0x1000>,
1387 <0x1742 568 <0x17422000 0x1000>;
1388 frame-number 569 frame-number = <0>;
1389 interrupts = 570 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1390 571 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1391 }; 572 };
1392 573
1393 frame@17423000 { 574 frame@17423000 {
1394 reg = <0x1742 575 reg = <0x17423000 0x1000>;
1395 frame-number 576 frame-number = <1>;
1396 interrupts = 577 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1397 status = "dis 578 status = "disabled";
1398 }; 579 };
1399 580
1400 frame@17425000 { 581 frame@17425000 {
1401 reg = <0x1742 582 reg = <0x17425000 0x1000>;
1402 frame-number 583 frame-number = <2>;
1403 interrupts = 584 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1404 status = "dis 585 status = "disabled";
1405 }; 586 };
1406 587
1407 frame@17427000 { 588 frame@17427000 {
1408 reg = <0x1742 589 reg = <0x17427000 0x1000>;
1409 frame-number 590 frame-number = <3>;
1410 interrupts = 591 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1411 status = "dis 592 status = "disabled";
1412 }; 593 };
1413 594
1414 frame@17429000 { 595 frame@17429000 {
1415 reg = <0x1742 596 reg = <0x17429000 0x1000>;
1416 frame-number 597 frame-number = <4>;
1417 interrupts = 598 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1418 status = "dis 599 status = "disabled";
1419 }; 600 };
1420 601
1421 frame@1742b000 { 602 frame@1742b000 {
1422 reg = <0x1742 603 reg = <0x1742b000 0x1000>;
1423 frame-number 604 frame-number = <5>;
1424 interrupts = 605 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1425 status = "dis 606 status = "disabled";
1426 }; 607 };
1427 608
1428 frame@1742d000 { 609 frame@1742d000 {
1429 reg = <0x1742 610 reg = <0x1742d000 0x1000>;
1430 frame-number 611 frame-number = <6>;
1431 interrupts = 612 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1432 status = "dis 613 status = "disabled";
1433 }; 614 };
1434 }; 615 };
1435 616
1436 apps_rsc: rsc@17a00000 { 617 apps_rsc: rsc@17a00000 {
1437 label = "apps_rsc"; 618 label = "apps_rsc";
1438 compatible = "qcom,rp 619 compatible = "qcom,rpmh-rsc";
1439 reg = <0x0 0x17a00000 620 reg = <0x0 0x17a00000 0x0 0x10000>,
1440 <0x0 0x17a10000 621 <0x0 0x17a10000 0x0 0x10000>,
1441 <0x0 0x17a20000 622 <0x0 0x17a20000 0x0 0x10000>;
1442 reg-names = "drv-0", 623 reg-names = "drv-0", "drv-1", "drv-2";
1443 interrupts = <GIC_SPI 624 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 625 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 626 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1446 627
1447 power-domains = <&CLU 628 power-domains = <&CLUSTER_PD>;
1448 qcom,tcs-offset = <0x 629 qcom,tcs-offset = <0xd00>;
1449 qcom,drv-id = <2>; 630 qcom,drv-id = <2>;
1450 qcom,tcs-config = <AC 631 qcom,tcs-config = <ACTIVE_TCS 3>,
1451 <SL 632 <SLEEP_TCS 2>,
1452 <WA 633 <WAKE_TCS 2>,
1453 <CO 634 <CONTROL_TCS 0>;
1454 635
1455 apps_bcm_voter: bcm-v 636 apps_bcm_voter: bcm-voter {
1456 compatible = 637 compatible = "qcom,bcm-voter";
1457 }; 638 };
1458 639
1459 rpmhcc: clock-control 640 rpmhcc: clock-controller {
1460 compatible = 641 compatible = "qcom,sdx75-rpmh-clk";
1461 clocks = <&xo 642 clocks = <&xo_board>;
1462 clock-names = 643 clock-names = "xo";
1463 #clock-cells 644 #clock-cells = <1>;
1464 }; 645 };
1465 <<
1466 rpmhpd: power-control <<
1467 compatible = <<
1468 #power-domain <<
1469 operating-poi <<
1470 <<
1471 rpmhpd_opp_ta <<
1472 compa <<
1473 <<
1474 rpmhp <<
1475 <<
1476 }; <<
1477 <<
1478 rpmhp <<
1479 <<
1480 }; <<
1481 <<
1482 rpmhp <<
1483 <<
1484 }; <<
1485 <<
1486 rpmhp <<
1487 <<
1488 }; <<
1489 <<
1490 rpmhp <<
1491 <<
1492 }; <<
1493 <<
1494 rpmhp <<
1495 <<
1496 }; <<
1497 <<
1498 rpmhp <<
1499 <<
1500 }; <<
1501 <<
1502 rpmhp <<
1503 <<
1504 }; <<
1505 <<
1506 rpmhp <<
1507 <<
1508 }; <<
1509 <<
1510 rpmhp <<
1511 <<
1512 }; <<
1513 }; <<
1514 }; <<
1515 }; 646 };
1516 647
1517 cpufreq_hw: cpufreq@17d91000 648 cpufreq_hw: cpufreq@17d91000 {
1518 compatible = "qcom,sd 649 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1519 reg = <0x0 0x17d91000 650 reg = <0x0 0x17d91000 0x0 0x1000>;
1520 reg-names = "freq-dom 651 reg-names = "freq-domain0";
1521 clocks = <&rpmhcc RPM 652 clocks = <&rpmhcc RPMH_CXO_CLK>,
1522 <&gcc GPLL0> 653 <&gcc GPLL0>;
1523 clock-names = "xo", 654 clock-names = "xo",
1524 "altern 655 "alternate";
1525 interrupts = <GIC_SPI 656 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1526 interrupt-names = "dc 657 interrupt-names = "dcvsh-irq-0";
1527 #freq-domain-cells = 658 #freq-domain-cells = <1>;
1528 #clock-cells = <1>; 659 #clock-cells = <1>;
1529 }; <<
1530 <<
1531 dc_noc: interconnect@190e0000 <<
1532 compatible = "qcom,sd <<
1533 reg = <0x0 0x190e0000 <<
1534 #interconnect-cells = <<
1535 qcom,bcm-voters = <&a <<
1536 }; <<
1537 <<
1538 gem_noc: interconnect@1910000 <<
1539 compatible = "qcom,sd <<
1540 reg = <0x0 0x19100000 <<
1541 #interconnect-cells = <<
1542 qcom,bcm-voters = <&a <<
1543 }; 660 };
1544 }; 661 };
1545 662
1546 timer { 663 timer {
1547 compatible = "arm,armv8-timer 664 compatible = "arm,armv8-timer";
1548 interrupts = <GIC_PPI 13 (GIC 665 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1549 <GIC_PPI 14 (GIC 666 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1550 <GIC_PPI 11 (GIC 667 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1551 <GIC_PPI 12 (GIC 668 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1552 }; 669 };
1553 }; 670 };
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