1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * SDX75 SoC device tree source 3 * SDX75 SoC device tree source
4 * 4 *
5 * Copyright (c) 2023 Qualcomm Innovation Cent 5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/qcom,rpmh.h> 9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h> 10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> <<
12 #include <dt-bindings/gpio/gpio.h> <<
13 #include <dt-bindings/interconnect/qcom,icc.h> <<
14 #include <dt-bindings/interconnect/qcom,sdx75. <<
15 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h> <<
17 #include <dt-bindings/power/qcom,rpmhpd.h> 12 #include <dt-bindings/power/qcom,rpmhpd.h>
18 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 15
21 / { 16 / {
22 #address-cells = <2>; 17 #address-cells = <2>;
23 #size-cells = <2>; 18 #size-cells = <2>;
24 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
25 20
26 chosen: chosen { }; 21 chosen: chosen { };
27 22
28 clocks { 23 clocks {
29 xo_board: xo-board { 24 xo_board: xo-board {
30 compatible = "fixed-cl 25 compatible = "fixed-clock";
31 clock-frequency = <768 26 clock-frequency = <76800000>;
32 #clock-cells = <0>; 27 #clock-cells = <0>;
33 }; 28 };
34 29
35 sleep_clk: sleep-clk { 30 sleep_clk: sleep-clk {
36 compatible = "fixed-cl 31 compatible = "fixed-clock";
37 clock-frequency = <320 32 clock-frequency = <32000>;
38 #clock-cells = <0>; 33 #clock-cells = <0>;
39 }; 34 };
40 }; 35 };
41 36
42 cpus { 37 cpus {
43 #address-cells = <2>; 38 #address-cells = <2>;
44 #size-cells = <0>; 39 #size-cells = <0>;
45 40
46 CPU0: cpu@0 { 41 CPU0: cpu@0 {
47 device_type = "cpu"; 42 device_type = "cpu";
48 compatible = "arm,cort 43 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 45 clocks = <&cpufreq_hw 0>;
51 enable-method = "psci" 46 enable-method = "psci";
52 power-domains = <&CPU_ 47 power-domains = <&CPU_PD0>;
53 power-domain-names = " 48 power-domain-names = "psci";
54 qcom,freq-domain = <&c 49 qcom,freq-domain = <&cpufreq_hw 0>;
55 capacity-dmips-mhz = < 50 capacity-dmips-mhz = <1024>;
56 dynamic-power-coeffici 51 dynamic-power-coefficient = <100>;
57 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
58 53
59 L2_0: l2-cache { 54 L2_0: l2-cache {
60 compatible = " 55 compatible = "cache";
61 cache-level = 56 cache-level = <2>;
62 cache-unified; 57 cache-unified;
63 next-level-cac 58 next-level-cache = <&L3_0>;
64 L3_0: l3-cache 59 L3_0: l3-cache {
65 compat 60 compatible = "cache";
66 cache- 61 cache-level = <3>;
67 cache- 62 cache-unified;
68 }; 63 };
69 }; 64 };
70 }; 65 };
71 66
72 CPU1: cpu@100 { 67 CPU1: cpu@100 {
73 device_type = "cpu"; 68 device_type = "cpu";
74 compatible = "arm,cort 69 compatible = "arm,cortex-a55";
75 reg = <0x0 0x100>; 70 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 71 clocks = <&cpufreq_hw 0>;
77 enable-method = "psci" 72 enable-method = "psci";
78 power-domains = <&CPU_ 73 power-domains = <&CPU_PD1>;
79 power-domain-names = " 74 power-domain-names = "psci";
80 qcom,freq-domain = <&c 75 qcom,freq-domain = <&cpufreq_hw 0>;
81 capacity-dmips-mhz = < 76 capacity-dmips-mhz = <1024>;
82 dynamic-power-coeffici 77 dynamic-power-coefficient = <100>;
83 next-level-cache = <&L 78 next-level-cache = <&L2_100>;
84 79
85 L2_100: l2-cache { 80 L2_100: l2-cache {
86 compatible = " 81 compatible = "cache";
87 cache-level = 82 cache-level = <2>;
88 cache-unified; 83 cache-unified;
89 next-level-cac 84 next-level-cache = <&L3_0>;
90 }; 85 };
91 }; 86 };
92 87
93 CPU2: cpu@200 { 88 CPU2: cpu@200 {
94 device_type = "cpu"; 89 device_type = "cpu";
95 compatible = "arm,cort 90 compatible = "arm,cortex-a55";
96 reg = <0x0 0x200>; 91 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 92 clocks = <&cpufreq_hw 0>;
98 enable-method = "psci" 93 enable-method = "psci";
99 power-domains = <&CPU_ 94 power-domains = <&CPU_PD2>;
100 power-domain-names = " 95 power-domain-names = "psci";
101 qcom,freq-domain = <&c 96 qcom,freq-domain = <&cpufreq_hw 0>;
102 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <1024>;
103 dynamic-power-coeffici 98 dynamic-power-coefficient = <100>;
104 next-level-cache = <&L 99 next-level-cache = <&L2_200>;
105 100
106 L2_200: l2-cache { 101 L2_200: l2-cache {
107 compatible = " 102 compatible = "cache";
108 cache-level = 103 cache-level = <2>;
109 cache-unified; 104 cache-unified;
110 next-level-cac 105 next-level-cache = <&L3_0>;
111 }; 106 };
112 }; 107 };
113 108
114 CPU3: cpu@300 { 109 CPU3: cpu@300 {
115 device_type = "cpu"; 110 device_type = "cpu";
116 compatible = "arm,cort 111 compatible = "arm,cortex-a55";
117 reg = <0x0 0x300>; 112 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 113 clocks = <&cpufreq_hw 0>;
119 enable-method = "psci" 114 enable-method = "psci";
120 power-domains = <&CPU_ 115 power-domains = <&CPU_PD3>;
121 power-domain-names = " 116 power-domain-names = "psci";
122 qcom,freq-domain = <&c 117 qcom,freq-domain = <&cpufreq_hw 0>;
123 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <1024>;
124 dynamic-power-coeffici 119 dynamic-power-coefficient = <100>;
125 next-level-cache = <&L 120 next-level-cache = <&L2_300>;
126 121
127 L2_300: l2-cache { 122 L2_300: l2-cache {
128 compatible = " 123 compatible = "cache";
129 cache-level = 124 cache-level = <2>;
130 cache-unified; 125 cache-unified;
131 next-level-cac 126 next-level-cache = <&L3_0>;
132 }; 127 };
133 }; 128 };
134 129
135 cpu-map { 130 cpu-map {
136 cluster0 { 131 cluster0 {
137 core0 { 132 core0 {
138 cpu = 133 cpu = <&CPU0>;
139 }; 134 };
140 135
141 core1 { 136 core1 {
142 cpu = 137 cpu = <&CPU1>;
143 }; 138 };
144 139
145 core2 { 140 core2 {
146 cpu = 141 cpu = <&CPU2>;
147 }; 142 };
148 143
149 core3 { 144 core3 {
150 cpu = 145 cpu = <&CPU3>;
151 }; 146 };
152 }; 147 };
153 }; 148 };
154 149
155 idle-states { 150 idle-states {
156 entry-method = "psci"; 151 entry-method = "psci";
157 152
158 CPU_OFF: cpu-sleep-0 { 153 CPU_OFF: cpu-sleep-0 {
159 compatible = " 154 compatible = "arm,idle-state";
160 entry-latency- 155 entry-latency-us = <235>;
161 exit-latency-u 156 exit-latency-us = <428>;
162 min-residency- 157 min-residency-us = <1774>;
163 arm,psci-suspe 158 arm,psci-suspend-param = <0x40000003>;
164 local-timer-st 159 local-timer-stop;
165 }; 160 };
166 161
167 CPU_RAIL_OFF: cpu-rail 162 CPU_RAIL_OFF: cpu-rail-sleep-1 {
168 compatible = " 163 compatible = "arm,idle-state";
169 entry-latency- 164 entry-latency-us = <800>;
170 exit-latency-u 165 exit-latency-us = <750>;
171 min-residency- 166 min-residency-us = <4090>;
172 arm,psci-suspe 167 arm,psci-suspend-param = <0x40000004>;
173 local-timer-st 168 local-timer-stop;
174 }; 169 };
175 170
176 }; 171 };
177 172
178 domain-idle-states { 173 domain-idle-states {
179 CLUSTER_SLEEP_0: clust 174 CLUSTER_SLEEP_0: cluster-sleep-0 {
180 compatible = " 175 compatible = "domain-idle-state";
181 arm,psci-suspe 176 arm,psci-suspend-param = <0x41000044>;
182 entry-latency- 177 entry-latency-us = <1050>;
183 exit-latency-u 178 exit-latency-us = <2500>;
184 min-residency- 179 min-residency-us = <5309>;
185 }; 180 };
186 181
187 CLUSTER_SLEEP_1: clust 182 CLUSTER_SLEEP_1: cluster-sleep-1 {
188 compatible = " 183 compatible = "domain-idle-state";
189 arm,psci-suspe 184 arm,psci-suspend-param = <0x41001344>;
190 entry-latency- 185 entry-latency-us = <2761>;
191 exit-latency-u 186 exit-latency-us = <3964>;
192 min-residency- 187 min-residency-us = <8467>;
193 }; 188 };
194 189
195 CLUSTER_SLEEP_2: clust 190 CLUSTER_SLEEP_2: cluster-sleep-2 {
196 compatible = " 191 compatible = "domain-idle-state";
197 arm,psci-suspe 192 arm,psci-suspend-param = <0x4100b344>;
198 entry-latency- 193 entry-latency-us = <2793>;
199 exit-latency-u 194 exit-latency-us = <4023>;
200 min-residency- 195 min-residency-us = <9826>;
201 }; 196 };
202 }; 197 };
203 }; 198 };
204 199
205 firmware { 200 firmware {
206 scm: scm { 201 scm: scm {
207 compatible = "qcom,scm 202 compatible = "qcom,scm-sdx75", "qcom,scm";
208 }; 203 };
209 }; 204 };
210 205
211 clk_virt: interconnect-0 { <<
212 compatible = "qcom,sdx75-clk-v <<
213 #interconnect-cells = <2>; <<
214 qcom,bcm-voters = <&apps_bcm_v <<
215 clocks = <&rpmhcc RPMH_QPIC_CL <<
216 }; <<
217 <<
218 mc_virt: interconnect-1 { <<
219 compatible = "qcom,sdx75-mc-vi <<
220 #interconnect-cells = <2>; <<
221 qcom,bcm-voters = <&apps_bcm_v <<
222 }; <<
223 <<
224 memory@80000000 { 206 memory@80000000 {
225 device_type = "memory"; 207 device_type = "memory";
226 reg = <0x0 0x80000000 0x0 0x0> 208 reg = <0x0 0x80000000 0x0 0x0>;
227 }; 209 };
228 210
229 pmu { 211 pmu {
230 compatible = "arm,cortex-a55-p !! 212 compatible = "arm,armv8-pmuv3";
231 interrupts = <GIC_PPI 7 IRQ_TY 213 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
232 }; 214 };
233 215
234 psci { 216 psci {
235 compatible = "arm,psci-1.0"; 217 compatible = "arm,psci-1.0";
236 method = "smc"; 218 method = "smc";
237 219
238 CPU_PD0: power-domain-cpu0 { 220 CPU_PD0: power-domain-cpu0 {
239 #power-domain-cells = 221 #power-domain-cells = <0>;
240 power-domains = <&CLUS 222 power-domains = <&CLUSTER_PD>;
241 domain-idle-states = < 223 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
242 }; 224 };
243 225
244 CPU_PD1: power-domain-cpu1 { 226 CPU_PD1: power-domain-cpu1 {
245 #power-domain-cells = 227 #power-domain-cells = <0>;
246 power-domains = <&CLUS 228 power-domains = <&CLUSTER_PD>;
247 domain-idle-states = < 229 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
248 }; 230 };
249 231
250 CPU_PD2: power-domain-cpu2 { 232 CPU_PD2: power-domain-cpu2 {
251 #power-domain-cells = 233 #power-domain-cells = <0>;
252 power-domains = <&CLUS 234 power-domains = <&CLUSTER_PD>;
253 domain-idle-states = < 235 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
254 }; 236 };
255 237
256 CPU_PD3: power-domain-cpu3 { 238 CPU_PD3: power-domain-cpu3 {
257 #power-domain-cells = 239 #power-domain-cells = <0>;
258 power-domains = <&CLUS 240 power-domains = <&CLUSTER_PD>;
259 domain-idle-states = < 241 domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
260 }; 242 };
261 243
262 CLUSTER_PD: power-domain-cpu-c 244 CLUSTER_PD: power-domain-cpu-cluster0 {
263 #power-domain-cells = 245 #power-domain-cells = <0>;
264 domain-idle-states = < 246 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
265 }; 247 };
266 }; 248 };
267 249
268 reserved-memory { 250 reserved-memory {
269 #address-cells = <2>; 251 #address-cells = <2>;
270 #size-cells = <2>; 252 #size-cells = <2>;
271 ranges; 253 ranges;
272 254
273 gunyah_hyp_mem: gunyah-hyp@800 255 gunyah_hyp_mem: gunyah-hyp@80000000 {
274 reg = <0x0 0x80000000 256 reg = <0x0 0x80000000 0x0 0x800000>;
275 no-map; 257 no-map;
276 }; 258 };
277 259
278 hyp_elf_package_mem: hyp-elf-p 260 hyp_elf_package_mem: hyp-elf-package@80800000 {
279 reg = <0x0 0x80800000 261 reg = <0x0 0x80800000 0x0 0x200000>;
280 no-map; 262 no-map;
281 }; 263 };
282 264
283 access_control_db_mem: access- 265 access_control_db_mem: access-control-db@81380000 {
284 reg = <0x0 0x81380000 266 reg = <0x0 0x81380000 0x0 0x80000>;
285 no-map; 267 no-map;
286 }; 268 };
287 269
288 qteetz_mem: qteetz@814e0000 { 270 qteetz_mem: qteetz@814e0000 {
289 reg = <0x0 0x814e0000 271 reg = <0x0 0x814e0000 0x0 0x2a0000>;
290 no-map; 272 no-map;
291 }; 273 };
292 274
293 trusted_apps_mem: trusted-apps 275 trusted_apps_mem: trusted-apps@81780000 {
294 reg = <0x0 0x81780000 276 reg = <0x0 0x81780000 0x0 0xa00000>;
295 no-map; 277 no-map;
296 }; 278 };
297 279
298 xbl_ramdump_mem: xbl-ramdump@8 280 xbl_ramdump_mem: xbl-ramdump@87a00000 {
299 reg = <0x0 0x87a00000 281 reg = <0x0 0x87a00000 0x0 0x1c0000>;
300 no-map; 282 no-map;
301 }; 283 };
302 284
303 cpucp_fw_mem: cpucp-fw@87c0000 285 cpucp_fw_mem: cpucp-fw@87c00000 {
304 reg = <0x0 0x87c00000 286 reg = <0x0 0x87c00000 0x0 0x100000>;
305 no-map; 287 no-map;
306 }; 288 };
307 289
308 xbl_dtlog_mem: xbl-dtlog@87d00 290 xbl_dtlog_mem: xbl-dtlog@87d00000 {
309 reg = <0x0 0x87d00000 291 reg = <0x0 0x87d00000 0x0 0x40000>;
310 no-map; 292 no-map;
311 }; 293 };
312 294
313 xbl_sc_mem: xbl-sc@87d40000 { 295 xbl_sc_mem: xbl-sc@87d40000 {
314 reg = <0x0 0x87d40000 296 reg = <0x0 0x87d40000 0x0 0x40000>;
315 no-map; 297 no-map;
316 }; 298 };
317 299
318 modem_efs_shared_mem: modem-ef 300 modem_efs_shared_mem: modem-efs-shared@87d80000 {
319 reg = <0x0 0x87d80000 301 reg = <0x0 0x87d80000 0x0 0x10000>;
320 no-map; 302 no-map;
321 }; 303 };
322 304
323 aop_image_mem: aop-image@87e00 305 aop_image_mem: aop-image@87e00000 {
324 reg = <0x0 0x87e00000 306 reg = <0x0 0x87e00000 0x0 0x20000>;
325 no-map; 307 no-map;
326 }; 308 };
327 309
328 smem_mem: smem@87e20000 { 310 smem_mem: smem@87e20000 {
329 reg = <0x0 0x87e20000 311 reg = <0x0 0x87e20000 0x0 0xc0000>;
330 no-map; 312 no-map;
331 }; 313 };
332 314
333 aop_cmd_db_mem: aop-cmd-db@87e 315 aop_cmd_db_mem: aop-cmd-db@87ee0000 {
334 compatible = "qcom,cmd 316 compatible = "qcom,cmd-db";
335 reg = <0x0 0x87ee0000 317 reg = <0x0 0x87ee0000 0x0 0x20000>;
336 no-map; 318 no-map;
337 }; 319 };
338 320
339 aop_config_mem: aop-config@87f 321 aop_config_mem: aop-config@87f00000 {
340 reg = <0x0 0x87f00000 322 reg = <0x0 0x87f00000 0x0 0x20000>;
341 no-map; 323 no-map;
342 }; 324 };
343 325
344 ipa_fw_mem: ipa-fw@87f20000 { 326 ipa_fw_mem: ipa-fw@87f20000 {
345 reg = <0x0 0x87f20000 327 reg = <0x0 0x87f20000 0x0 0x10000>;
346 no-map; 328 no-map;
347 }; 329 };
348 330
349 secdata_mem: secdata@87f30000 331 secdata_mem: secdata@87f30000 {
350 reg = <0x0 0x87f30000 332 reg = <0x0 0x87f30000 0x0 0x1000>;
351 no-map; 333 no-map;
352 }; 334 };
353 335
354 tme_crashdump_mem: tme-crashdu 336 tme_crashdump_mem: tme-crashdump@87f31000 {
355 reg = <0x0 0x87f31000 337 reg = <0x0 0x87f31000 0x0 0x40000>;
356 no-map; 338 no-map;
357 }; 339 };
358 340
359 tme_log_mem: tme-log@87f71000 341 tme_log_mem: tme-log@87f71000 {
360 reg = <0x0 0x87f71000 342 reg = <0x0 0x87f71000 0x0 0x4000>;
361 no-map; 343 no-map;
362 }; 344 };
363 345
364 uefi_log_mem: uefi-log@87f7500 346 uefi_log_mem: uefi-log@87f75000 {
365 reg = <0x0 0x87f75000 347 reg = <0x0 0x87f75000 0x0 0x10000>;
366 no-map; 348 no-map;
367 }; 349 };
368 350
369 qdss_mem: qdss@88500000 { !! 351 qdss_mem: qdss@88800000 {
370 reg = <0x0 0x88500000 <<
371 no-map; <<
372 }; <<
373 <<
374 qlink_logging_mem: qlink-loggi <<
375 reg = <0x0 0x88800000 352 reg = <0x0 0x88800000 0x0 0x300000>;
376 no-map; 353 no-map;
377 }; 354 };
378 355
379 audio_heap_mem: audio-heap@88b 356 audio_heap_mem: audio-heap@88b00000 {
380 compatible = "shared-d 357 compatible = "shared-dma-pool";
381 reg = <0x0 0x88b00000 358 reg = <0x0 0x88b00000 0x0 0x400000>;
382 no-map; 359 no-map;
383 }; 360 };
384 361
385 mpss_dsm_mem_2: mpss-dsm-2@88f !! 362 mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
386 reg = <0x0 0x88f00000 !! 363 reg = <0x0 0x88f00000 0x0 0x5080000>;
387 no-map; <<
388 }; <<
389 <<
390 mpss_dsm_mem: mpss-dsm@8b40000 <<
391 reg = <0x0 0x8b400000 <<
392 no-map; 364 no-map;
393 }; 365 };
394 366
395 q6_mpss_dtb_mem: q6-mpss-dtb@8 367 q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
396 reg = <0x0 0x8df80000 368 reg = <0x0 0x8df80000 0x0 0x80000>;
397 no-map; 369 no-map;
398 }; 370 };
399 371
400 mpssadsp_mem: mpssadsp@8e00000 372 mpssadsp_mem: mpssadsp@8e000000 {
401 reg = <0x0 0x8e000000 !! 373 reg = <0x0 0x8e000000 0x0 0xf400000>;
402 no-map; 374 no-map;
403 }; 375 };
404 376
405 gunyah_trace_buffer_mem: gunya 377 gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
406 reg = <0x0 0xbdb00000 378 reg = <0x0 0xbdb00000 0x0 0x2000000>;
407 no-map; 379 no-map;
408 }; 380 };
409 381
410 smmu_debug_buf_mem: smmu-debug 382 smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
411 reg = <0x0 0xbfb00000 383 reg = <0x0 0xbfb00000 0x0 0x100000>;
412 no-map; 384 no-map;
413 }; 385 };
414 386
415 hyp_smmu_s2_pt_mem: hyp-smmu-s 387 hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
416 reg = <0x0 0xbfc00000 388 reg = <0x0 0xbfc00000 0x0 0x400000>;
417 no-map; 389 no-map;
418 }; 390 };
419 }; 391 };
420 392
421 smp2p-modem { !! 393 smem: qcom,smem {
422 compatible = "qcom,smp2p"; <<
423 qcom,smem = <435>, <428>; <<
424 interrupts-extended = <&ipcc I <<
425 I <<
426 I <<
427 mboxes = <&ipcc IPCC_CLIENT_MP <<
428 IPCC_MPROC_SIG <<
429 <<
430 qcom,local-pid = <0>; <<
431 qcom,remote-pid = <1>; <<
432 <<
433 smp2p_modem_out: master-kernel <<
434 qcom,entry-name = "mas <<
435 #qcom,smem-state-cells <<
436 }; <<
437 <<
438 smp2p_modem_in: slave-kernel { <<
439 qcom,entry-name = "sla <<
440 interrupt-controller; <<
441 #interrupt-cells = <2> <<
442 }; <<
443 <<
444 ipa_smp2p_out: ipa-ap-to-modem <<
445 qcom,entry-name = "ipa <<
446 #qcom,smem-state-cells <<
447 }; <<
448 <<
449 ipa_smp2p_in: ipa-modem-to-ap <<
450 qcom,entry-name = "ipa <<
451 interrupt-controller; <<
452 #interrupt-cells = <2> <<
453 }; <<
454 }; <<
455 <<
456 smem: smem { <<
457 compatible = "qcom,smem"; 394 compatible = "qcom,smem";
458 memory-region = <&smem_mem>; 395 memory-region = <&smem_mem>;
459 hwlocks = <&tcsr_mutex 3>; 396 hwlocks = <&tcsr_mutex 3>;
460 }; 397 };
461 398
462 soc: soc@0 { !! 399 soc: soc {
463 compatible = "simple-bus"; 400 compatible = "simple-bus";
464 #address-cells = <2>; 401 #address-cells = <2>;
465 #size-cells = <2>; 402 #size-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>; 403 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>; 404 dma-ranges = <0 0 0 0 0x10 0>;
468 405
469 gcc: clock-controller@80000 { 406 gcc: clock-controller@80000 {
470 compatible = "qcom,sdx 407 compatible = "qcom,sdx75-gcc";
471 reg = <0x0 0x0080000 0 408 reg = <0x0 0x0080000 0x0 0x1f7400>;
472 clocks = <&rpmhcc RPMH 409 clocks = <&rpmhcc RPMH_CXO_CLK>,
473 <&sleep_clk>, 410 <&sleep_clk>,
474 <0>, 411 <0>,
475 <0>, 412 <0>,
476 <0>, 413 <0>,
477 <0>, 414 <0>,
478 <0>, 415 <0>,
479 <0>, 416 <0>,
480 <0>, 417 <0>,
481 <0>, 418 <0>,
482 <0>, 419 <0>,
483 <0>, 420 <0>,
484 <0>, 421 <0>,
485 <0>, 422 <0>,
486 <0>; 423 <0>;
487 #clock-cells = <1>; 424 #clock-cells = <1>;
488 #reset-cells = <1>; 425 #reset-cells = <1>;
489 #power-domain-cells = 426 #power-domain-cells = <1>;
490 }; 427 };
491 428
492 ipcc: mailbox@408000 { <<
493 compatible = "qcom,sdx <<
494 reg = <0 0x00408000 0 <<
495 interrupts = <GIC_SPI <<
496 interrupt-controller; <<
497 #interrupt-cells = <3> <<
498 #mbox-cells = <2>; <<
499 }; <<
500 <<
501 gpi_dma: dma-controller@900000 <<
502 compatible = "qcom,sdx <<
503 reg = <0x0 0x00900000 <<
504 #dma-cells = <3>; <<
505 interrupts = <GIC_SPI <<
506 <GIC_SPI <<
507 <GIC_SPI <<
508 <GIC_SPI <<
509 <GIC_SPI <<
510 <GIC_SPI <<
511 <GIC_SPI <<
512 <GIC_SPI <<
513 <GIC_SPI <<
514 <GIC_SPI <<
515 <GIC_SPI <<
516 <GIC_SPI <<
517 dma-channels = <12>; <<
518 dma-channel-mask = <0x <<
519 iommus = <&apps_smmu 0 <<
520 status = "disabled"; <<
521 }; <<
522 <<
523 qupv3_id_0: geniqup@9c0000 { 429 qupv3_id_0: geniqup@9c0000 {
524 compatible = "qcom,gen 430 compatible = "qcom,geni-se-qup";
525 reg = <0x0 0x009c0000 431 reg = <0x0 0x009c0000 0x0 0x2000>;
526 clocks = <&gcc GCC_QUP 432 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
527 <&gcc GCC_QUP 433 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
528 clock-names = "m-ahb", 434 clock-names = "m-ahb",
529 "s-ahb"; 435 "s-ahb";
530 iommus = <&apps_smmu 0 436 iommus = <&apps_smmu 0xe3 0x0>;
531 interconnects = <&clk_ <<
532 &clk_ <<
533 interconnect-names = " <<
534 #address-cells = <2>; 437 #address-cells = <2>;
535 #size-cells = <2>; 438 #size-cells = <2>;
536 ranges; 439 ranges;
537 status = "disabled"; 440 status = "disabled";
538 441
539 i2c0: i2c@980000 { <<
540 compatible = " <<
541 reg = <0x0 0x0 <<
542 clocks = <&gcc <<
543 clock-names = <<
544 interrupts = < <<
545 #address-cells <<
546 #size-cells = <<
547 pinctrl-0 = <& <<
548 pinctrl-names <<
549 interconnects <<
550 <<
551 <<
552 <<
553 <<
554 <<
555 interconnect-n <<
556 dmas = <&gpi_d <<
557 <&gpi_d <<
558 dma-names = "t <<
559 status = "disa <<
560 }; <<
561 <<
562 spi0: spi@980000 { <<
563 compatible = " <<
564 reg = <0x0 0x0 <<
565 clocks = <&gcc <<
566 clock-names = <<
567 interrupts = < <<
568 #address-cells <<
569 #size-cells = <<
570 pinctrl-0 = <& <<
571 pinctrl-names <<
572 interconnects <<
573 <<
574 <<
575 <<
576 <<
577 <<
578 interconnect-n <<
579 dmas = <&gpi_d <<
580 <&gpi_d <<
581 dma-names = "t <<
582 status = "disa <<
583 }; <<
584 <<
585 uart1: serial@984000 { 442 uart1: serial@984000 {
586 compatible = " 443 compatible = "qcom,geni-debug-uart";
587 reg = <0x0 0x0 444 reg = <0x0 0x00984000 0x0 0x4000>;
588 clocks = <&gcc 445 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
589 clock-names = 446 clock-names = "se";
590 interconnects <<
591 <<
592 <<
593 <<
594 interconnect-n <<
595 <<
596 interrupts = < 447 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-0 = <& 448 pinctrl-0 = <&qupv3_se1_2uart_active>;
598 pinctrl-1 = <& 449 pinctrl-1 = <&qupv3_se1_2uart_sleep>;
599 pinctrl-names 450 pinctrl-names = "default",
600 451 "sleep";
601 status = "disa 452 status = "disabled";
602 }; 453 };
603 <<
604 i2c2: i2c@988000 { <<
605 compatible = " <<
606 reg = <0x0 0x0 <<
607 clocks = <&gcc <<
608 clock-names = <<
609 interrupts = < <<
610 #address-cells <<
611 #size-cells = <<
612 pinctrl-0 = <& <<
613 pinctrl-names <<
614 interconnects <<
615 <<
616 <<
617 <<
618 <<
619 <<
620 interconnect-n <<
621 dmas = <&gpi_d <<
622 <&gpi_d <<
623 dma-names = "t <<
624 status = "disa <<
625 }; <<
626 <<
627 spi2: spi@988000 { <<
628 compatible = " <<
629 reg = <0x0 0x0 <<
630 clocks = <&gcc <<
631 clock-names = <<
632 interrupts = < <<
633 #address-cells <<
634 #size-cells = <<
635 pinctrl-0 = <& <<
636 pinctrl-names <<
637 interconnects <<
638 <<
639 <<
640 <<
641 <<
642 <<
643 interconnect-n <<
644 dmas = <&gpi_d <<
645 <&gpi_d <<
646 dma-names = "t <<
647 status = "disa <<
648 }; <<
649 <<
650 i2c3: i2c@98c000 { <<
651 compatible = " <<
652 reg = <0x0 0x0 <<
653 clocks = <&gcc <<
654 clock-names = <<
655 interrupts = < <<
656 #address-cells <<
657 #size-cells = <<
658 pinctrl-0 = <& <<
659 pinctrl-names <<
660 interconnects <<
661 <<
662 <<
663 <<
664 <<
665 <<
666 interconnect-n <<
667 dmas = <&gpi_d <<
668 <&gpi_d <<
669 dma-names = "t <<
670 status = "disa <<
671 }; <<
672 <<
673 spi3: spi@98c000 { <<
674 compatible = " <<
675 reg = <0x0 0x0 <<
676 clocks = <&gcc <<
677 clock-names = <<
678 interrupts = < <<
679 #address-cells <<
680 #size-cells = <<
681 pinctrl-0 = <& <<
682 pinctrl-names <<
683 interconnects <<
684 <<
685 <<
686 <<
687 <<
688 <<
689 interconnect-n <<
690 dmas = <&gpi_d <<
691 <&gpi_d <<
692 dma-names = "t <<
693 status = "disa <<
694 }; <<
695 <<
696 uart4: serial@990000 { <<
697 compatible = " <<
698 reg = <0x0 0x0 <<
699 clocks = <&gcc <<
700 clock-names = <<
701 interrupts = < <<
702 pinctrl-0 = <& <<
703 pinctrl-names <<
704 interconnects <<
705 <<
706 <<
707 <<
708 interconnect-n <<
709 status = "disa <<
710 }; <<
711 <<
712 i2c5: i2c@994000 { <<
713 compatible = " <<
714 reg = <0x0 0x0 <<
715 clocks = <&gcc <<
716 clock-names = <<
717 interrupts = < <<
718 #address-cells <<
719 #size-cells = <<
720 pinctrl-0 = <& <<
721 pinctrl-names <<
722 interconnects <<
723 <<
724 <<
725 <<
726 <<
727 <<
728 interconnect-n <<
729 dmas = <&gpi_d <<
730 <&gpi_d <<
731 dma-names = "t <<
732 status = "disa <<
733 }; <<
734 <<
735 i2c6: i2c@998000 { <<
736 compatible = " <<
737 reg = <0x0 0x0 <<
738 clocks = <&gcc <<
739 clock-names = <<
740 interrupts = < <<
741 #address-cells <<
742 #size-cells = <<
743 pinctrl-0 = <& <<
744 pinctrl-names <<
745 interconnects <<
746 <<
747 <<
748 <<
749 <<
750 <<
751 interconnect-n <<
752 dmas = <&gpi_d <<
753 <&gpi_d <<
754 dma-names = "t <<
755 status = "disa <<
756 }; <<
757 <<
758 spi6: spi@998000 { <<
759 compatible = " <<
760 reg = <0x0 0x0 <<
761 clocks = <&gcc <<
762 clock-names = <<
763 interrupts = < <<
764 #address-cells <<
765 #size-cells = <<
766 pinctrl-0 = <& <<
767 pinctrl-names <<
768 interconnects <<
769 <<
770 <<
771 <<
772 <<
773 <<
774 interconnect-n <<
775 dmas = <&gpi_d <<
776 <&gpi_d <<
777 dma-names = "t <<
778 status = "disa <<
779 }; <<
780 <<
781 i2c7: i2c@99c000 { <<
782 compatible = " <<
783 reg = <0x0 0x0 <<
784 clocks = <&gcc <<
785 clock-names = <<
786 interrupts = < <<
787 #address-cells <<
788 #size-cells = <<
789 pinctrl-0 = <& <<
790 pinctrl-names <<
791 interconnects <<
792 <<
793 <<
794 <<
795 <<
796 <<
797 interconnect-n <<
798 dmas = <&gpi_d <<
799 <&gpi_d <<
800 dma-names = "t <<
801 status = "disa <<
802 }; <<
803 <<
804 spi7: spi@99c000 { <<
805 compatible = " <<
806 reg = <0x0 0x0 <<
807 clocks = <&gcc <<
808 clock-names = <<
809 interrupts = < <<
810 #address-cells <<
811 #size-cells = <<
812 pinctrl-0 = <& <<
813 pinctrl-names <<
814 interconnects <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 interconnect-n <<
821 dmas = <&gpi_d <<
822 <&gpi_d <<
823 dma-names = "t <<
824 status = "disa <<
825 }; <<
826 }; <<
827 <<
828 usb_hsphy: phy@ff4000 { <<
829 compatible = "qcom,sdx <<
830 reg = <0x0 0x00ff4000 <<
831 #phy-cells = <0>; <<
832 <<
833 clocks = <&rpmhcc RPMH <<
834 clock-names = "ref"; <<
835 <<
836 resets = <&gcc GCC_QUS <<
837 <<
838 status = "disabled"; <<
839 }; <<
840 <<
841 usb_qmpphy: phy@ff6000 { <<
842 compatible = "qcom,sdx <<
843 reg = <0x0 0x00ff6000 <<
844 <<
845 clocks = <&gcc GCC_USB <<
846 <&gcc GCC_USB <<
847 <&gcc GCC_USB <<
848 <&gcc GCC_USB <<
849 clock-names = "aux", <<
850 "ref", <<
851 "cfg_ahb <<
852 "pipe"; <<
853 <<
854 power-domains = <&gcc <<
855 <<
856 resets = <&gcc GCC_USB <<
857 <&gcc GCC_USB <<
858 reset-names = "phy", <<
859 "phy_phy <<
860 <<
861 #clock-cells = <0>; <<
862 clock-output-names = " <<
863 <<
864 #phy-cells = <0>; <<
865 <<
866 status = "disabled"; <<
867 }; <<
868 <<
869 system_noc: interconnect@16400 <<
870 compatible = "qcom,sdx <<
871 reg = <0x0 0x01640000 <<
872 #interconnect-cells = <<
873 qcom,bcm-voters = <&ap <<
874 }; <<
875 <<
876 pcie_anoc: interconnect@16c000 <<
877 compatible = "qcom,sdx <<
878 reg = <0x0 0x016c0000 <<
879 #interconnect-cells = <<
880 qcom,bcm-voters = <&ap <<
881 }; 454 };
882 455
883 tcsr_mutex: hwlock@1f40000 { 456 tcsr_mutex: hwlock@1f40000 {
884 compatible = "qcom,tcs 457 compatible = "qcom,tcsr-mutex";
885 reg = <0x0 0x01f40000 458 reg = <0x0 0x01f40000 0x0 0x40000>;
886 #hwlock-cells = <1>; 459 #hwlock-cells = <1>;
887 }; 460 };
888 461
889 tcsr: syscon@1fc0000 { <<
890 compatible = "qcom,sdx <<
891 reg = <0x0 0x01fc0000 <<
892 }; <<
893 <<
894 remoteproc_mpss: remoteproc@40 <<
895 compatible = "qcom,sdx <<
896 reg = <0 0x04080000 0 <<
897 <<
898 interrupts-extended = <<
899 <<
900 <<
901 <<
902 <<
903 <<
904 interrupt-names = "wdo <<
905 "fat <<
906 "rea <<
907 "han <<
908 "sto <<
909 "shu <<
910 <<
911 clocks = <&rpmhcc RPMH <<
912 clock-names = "xo"; <<
913 <<
914 power-domains = <&rpmh <<
915 <&rpmh <<
916 power-domain-names = " <<
917 " <<
918 <<
919 memory-region = <&mpss <<
920 <&mpss <<
921 <&qlin <<
922 <<
923 qcom,qmp = <&aoss_qmp> <<
924 <<
925 qcom,smem-states = <&s <<
926 qcom,smem-state-names <<
927 <<
928 status = "disabled"; <<
929 <<
930 glink-edge { <<
931 interrupts-ext <<
932 <<
933 <<
934 mboxes = <&ipc <<
935 <<
936 label = "mpss" <<
937 qcom,remote-pi <<
938 }; <<
939 }; <<
940 <<
941 sdhc: mmc@8804000 { <<
942 compatible = "qcom,sdx <<
943 reg = <0x0 0x08804000 <<
944 <<
945 interrupts = <GIC_SPI <<
946 <GIC_SPI <<
947 interrupt-names = "hc_ <<
948 "pwr <<
949 <<
950 clocks = <&gcc GCC_SDC <<
951 <&gcc GCC_SDC <<
952 <&rpmhcc RPMH <<
953 clock-names = "iface", <<
954 "core", <<
955 "xo"; <<
956 iommus = <&apps_smmu 0 <<
957 qcom,dll-config = <0x0 <<
958 qcom,ddr-config = <0x8 <<
959 power-domains = <&rpmh <<
960 operating-points-v2 = <<
961 <<
962 interconnects = <&syst <<
963 <&gem_ <<
964 interconnect-names = " <<
965 " <<
966 bus-width = <4>; <<
967 dma-coherent; <<
968 <<
969 /* Forbid SDR104/SDR50 <<
970 sdhci-caps-mask = <0x3 <<
971 <<
972 status = "disabled"; <<
973 <<
974 sdhc1_opp_table: opp-t <<
975 compatible = " <<
976 <<
977 opp-100000000 <<
978 opp-hz <<
979 requir <<
980 }; <<
981 <<
982 opp-384000000 <<
983 opp-hz <<
984 requir <<
985 }; <<
986 }; <<
987 }; <<
988 <<
989 usb: usb@a6f8800 { <<
990 compatible = "qcom,sdx <<
991 reg = <0x0 0x0a6f8800 <<
992 #address-cells = <2>; <<
993 #size-cells = <2>; <<
994 ranges; <<
995 <<
996 clocks = <&gcc GCC_USB <<
997 <&gcc GCC_USB <<
998 <&gcc GCC_USB <<
999 <&gcc GCC_USB <<
1000 <&gcc GCC_US <<
1001 clock-names = "cfg_no <<
1002 "core", <<
1003 "iface" <<
1004 "sleep" <<
1005 "mock_u <<
1006 <<
1007 assigned-clocks = <&g <<
1008 <&g <<
1009 assigned-clock-rates <<
1010 <<
1011 interrupts-extended = <<
1012 <<
1013 <<
1014 <<
1015 interrupt-names = "hs <<
1016 "ss <<
1017 "dm <<
1018 "dp <<
1019 <<
1020 power-domains = <&gcc <<
1021 <<
1022 resets = <&gcc GCC_US <<
1023 <<
1024 interconnects = <&sys <<
1025 &mc_ <<
1026 <&gem <<
1027 &sys <<
1028 interconnect-names = <<
1029 <<
1030 <<
1031 status = "disabled"; <<
1032 <<
1033 usb_dwc3: usb@a600000 <<
1034 compatible = <<
1035 reg = <0x0 0x <<
1036 interrupts = <<
1037 iommus = <&ap <<
1038 snps,dis_u2_s <<
1039 snps,dis_enbl <<
1040 phys = <&usb_ <<
1041 <&usb_ <<
1042 phy-names = " <<
1043 " <<
1044 <<
1045 ports { <<
1046 #addr <<
1047 #size <<
1048 <<
1049 port@ <<
1050 <<
1051 <<
1052 <<
1053 <<
1054 }; <<
1055 <<
1056 port@ <<
1057 <<
1058 <<
1059 <<
1060 <<
1061 }; <<
1062 }; <<
1063 }; <<
1064 }; <<
1065 <<
1066 pdc: interrupt-controller@b22 462 pdc: interrupt-controller@b220000 {
1067 compatible = "qcom,sd 463 compatible = "qcom,sdx75-pdc", "qcom,pdc";
1068 reg = <0x0 0xb220000 464 reg = <0x0 0xb220000 0x0 0x30000>,
1069 <0x0 0x174000f0 465 <0x0 0x174000f0 0x0 0x64>;
1070 qcom,pdc-ranges = <0 466 qcom,pdc-ranges = <0 147 52>,
1071 <52 467 <52 266 32>,
1072 <84 468 <84 500 59>;
1073 #interrupt-cells = <2 469 #interrupt-cells = <2>;
1074 interrupt-parent = <& 470 interrupt-parent = <&intc>;
1075 interrupt-controller; 471 interrupt-controller;
1076 }; 472 };
1077 473
1078 aoss_qmp: power-controller@c3 <<
1079 compatible = "qcom,sd <<
1080 reg = <0 0x0c310000 0 <<
1081 interrupt-parent = <& <<
1082 interrupts-extended = <<
1083 <<
1084 mboxes = <&ipcc IPCC_ <<
1085 <<
1086 #clock-cells = <0>; <<
1087 }; <<
1088 <<
1089 spmi_bus: spmi@c400000 { 474 spmi_bus: spmi@c400000 {
1090 compatible = "qcom,sp 475 compatible = "qcom,spmi-pmic-arb";
1091 reg = <0x0 0x0c400000 476 reg = <0x0 0x0c400000 0x0 0x3000>,
1092 <0x0 0x0c500000 477 <0x0 0x0c500000 0x0 0x400000>,
1093 <0x0 0x0c440000 478 <0x0 0x0c440000 0x0 0x80000>,
1094 <0x0 0x0c4c0000 479 <0x0 0x0c4c0000 0x0 0x10000>,
1095 <0x0 0x0c42d000 480 <0x0 0x0c42d000 0x0 0x4000>;
1096 reg-names = "core", 481 reg-names = "core",
1097 "chnls", 482 "chnls",
1098 "obsrvr", 483 "obsrvr",
1099 "intr", 484 "intr",
1100 "cnfg"; 485 "cnfg";
1101 interrupts-extended = 486 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1102 interrupt-names = "pe 487 interrupt-names = "periph_irq";
1103 qcom,ee = <0>; 488 qcom,ee = <0>;
1104 qcom,channel = <0>; 489 qcom,channel = <0>;
1105 qcom,bus-id = <0>; 490 qcom,bus-id = <0>;
1106 #address-cells = <2>; 491 #address-cells = <2>;
1107 #size-cells = <0>; 492 #size-cells = <0>;
1108 interrupt-controller; 493 interrupt-controller;
1109 #interrupt-cells = <4 494 #interrupt-cells = <4>;
1110 }; 495 };
1111 496
1112 tlmm: pinctrl@f000000 { 497 tlmm: pinctrl@f000000 {
1113 compatible = "qcom,sd 498 compatible = "qcom,sdx75-tlmm";
1114 reg = <0x0 0x0f000000 499 reg = <0x0 0x0f000000 0x0 0x400000>;
1115 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1116 gpio-controller; 501 gpio-controller;
1117 #gpio-cells = <2>; 502 #gpio-cells = <2>;
1118 gpio-ranges = <&tlmm 503 gpio-ranges = <&tlmm 0 0 133>;
1119 interrupt-controller; 504 interrupt-controller;
1120 #interrupt-cells = <2 505 #interrupt-cells = <2>;
1121 wakeup-parent = <&pdc 506 wakeup-parent = <&pdc>;
1122 507
1123 qup_i2c0_data_clk: qu <<
1124 /* SDA, SCL * <<
1125 pins = "gpio8 <<
1126 function = "q <<
1127 drive-strengt <<
1128 bias-pull-up; <<
1129 }; <<
1130 <<
1131 qup_i2c2_data_clk: qu <<
1132 /* SDA, SCL * <<
1133 pins = "gpio1 <<
1134 function = "q <<
1135 drive-strengt <<
1136 bias-pull-up; <<
1137 }; <<
1138 <<
1139 qup_i2c3_data_clk: qu <<
1140 /* SDA, SCL * <<
1141 pins = "gpio5 <<
1142 function = "q <<
1143 drive-strengt <<
1144 bias-pull-up; <<
1145 }; <<
1146 <<
1147 qup_i2c5_data_clk: qu <<
1148 /* SDA, SCL * <<
1149 pins = "gpio1 <<
1150 function = "q <<
1151 drive-strengt <<
1152 bias-pull-up; <<
1153 }; <<
1154 <<
1155 qup_i2c6_data_clk: qu <<
1156 /* SDA, SCL * <<
1157 pins = "gpio1 <<
1158 function = "q <<
1159 drive-strengt <<
1160 bias-pull-up; <<
1161 }; <<
1162 <<
1163 qup_i2c7_data_clk: qu <<
1164 /* SDA, SCL * <<
1165 pins = "gpio1 <<
1166 function = "q <<
1167 drive-strengt <<
1168 bias-pull-up; <<
1169 }; <<
1170 <<
1171 qup_spi0_cs: qup-spi0 <<
1172 pins = "gpio1 <<
1173 function = "q <<
1174 drive-strengt <<
1175 bias-pull-dow <<
1176 }; <<
1177 <<
1178 qup_spi0_data_clk: qu <<
1179 /* MISO, MOSI <<
1180 pins = "gpio8 <<
1181 function = "q <<
1182 drive-strengt <<
1183 bias-pull-dow <<
1184 }; <<
1185 <<
1186 qup_spi2_cs: qup-spi2 <<
1187 pins = "gpio1 <<
1188 function = "q <<
1189 drive-strengt <<
1190 bias-pull-dow <<
1191 }; <<
1192 <<
1193 qup_spi2_data_clk: qu <<
1194 /* MISO, MOSI <<
1195 pins = "gpio1 <<
1196 function = "q <<
1197 drive-strengt <<
1198 bias-pull-dow <<
1199 }; <<
1200 <<
1201 qup_spi3_cs: qup-spi3 <<
1202 pins = "gpio5 <<
1203 function = "q <<
1204 drive-strengt <<
1205 bias-pull-dow <<
1206 }; <<
1207 <<
1208 qup_spi3_data_clk: qu <<
1209 /* MISO, MOSI <<
1210 pins = "gpio5 <<
1211 function = "q <<
1212 drive-strengt <<
1213 bias-pull-dow <<
1214 }; <<
1215 <<
1216 qup_spi6_cs: qup-spi6 <<
1217 pins = "gpio1 <<
1218 function = "q <<
1219 drive-strengt <<
1220 bias-pull-dow <<
1221 }; <<
1222 <<
1223 qup_spi6_data_clk: qu <<
1224 /* MISO, MOSI <<
1225 pins = "gpio1 <<
1226 function = "q <<
1227 drive-strengt <<
1228 bias-pull-dow <<
1229 }; <<
1230 <<
1231 qup_spi7_cs: qup-spi7 <<
1232 pins = "gpio1 <<
1233 function = "q <<
1234 drive-strengt <<
1235 bias-pull-dow <<
1236 }; <<
1237 <<
1238 qup_spi7_data_clk: qu <<
1239 /* MISO, MOSI <<
1240 pins = "gpio1 <<
1241 function = "q <<
1242 drive-strengt <<
1243 bias-pull-dow <<
1244 }; <<
1245 <<
1246 qup_uart4_cts_rts: qu <<
1247 /* CTS, RTS * <<
1248 pins = "gpio5 <<
1249 function = "q <<
1250 drive-strengt <<
1251 bias-pull-dow <<
1252 }; <<
1253 <<
1254 qup_uart4_default: qu <<
1255 /* TX, RX */ <<
1256 pins = "gpio5 <<
1257 function = "q <<
1258 drive-strengt <<
1259 bias-pull-up; <<
1260 }; <<
1261 <<
1262 qupv3_se1_2uart_activ 508 qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1263 tx-pins { 509 tx-pins {
1264 pins 510 pins = "gpio12";
1265 funct 511 function = "qup_se1_l2_mira";
1266 drive 512 drive-strength = <2>;
1267 bias- 513 bias-disable;
1268 }; 514 };
1269 515
1270 rx-pins { 516 rx-pins {
1271 pins 517 pins = "gpio13";
1272 funct 518 function = "qup_se1_l3_mira";
1273 drive 519 drive-strength = <2>;
1274 bias- 520 bias-disable;
1275 }; 521 };
1276 }; 522 };
1277 523
1278 qupv3_se1_2uart_sleep 524 qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1279 pins = "gpio1 525 pins = "gpio12", "gpio13";
1280 function = "g 526 function = "gpio";
1281 drive-strengt 527 drive-strength = <2>;
1282 bias-pull-dow 528 bias-pull-down;
1283 }; 529 };
1284 <<
1285 sdc1_default: sdc1-de <<
1286 clk-pins { <<
1287 pins <<
1288 drive <<
1289 bias- <<
1290 }; <<
1291 <<
1292 cmd-pins { <<
1293 pins <<
1294 drive <<
1295 bias- <<
1296 }; <<
1297 <<
1298 data-pins { <<
1299 pins <<
1300 drive <<
1301 bias- <<
1302 }; <<
1303 }; <<
1304 <<
1305 sdc1_sleep: sdc1-slee <<
1306 clk-pins { <<
1307 pins <<
1308 drive <<
1309 bias- <<
1310 }; <<
1311 <<
1312 cmd-pins { <<
1313 pins <<
1314 drive <<
1315 bias- <<
1316 }; <<
1317 <<
1318 data-pins { <<
1319 pins <<
1320 drive <<
1321 bias- <<
1322 }; <<
1323 }; <<
1324 }; 530 };
1325 531
1326 apps_smmu: iommu@15000000 { 532 apps_smmu: iommu@15000000 {
1327 compatible = "qcom,sd 533 compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1328 reg = <0x0 0x15000000 534 reg = <0x0 0x15000000 0x0 0x40000>;
1329 #iommu-cells = <2>; 535 #iommu-cells = <2>;
1330 #global-interrupts = 536 #global-interrupts = <2>;
1331 dma-coherent; 537 dma-coherent;
1332 interrupts = <GIC_SPI 538 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 539 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 540 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 541 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 542 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 543 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 544 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 545 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 546 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 547 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1342 <GIC_SPI 548 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1343 <GIC_SPI 549 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1344 <GIC_SPI 550 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1345 <GIC_SPI 551 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1346 <GIC_SPI 552 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1347 <GIC_SPI 553 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1348 <GIC_SPI 554 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1349 <GIC_SPI 555 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1350 <GIC_SPI 556 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 557 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 558 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 559 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 560 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 561 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 562 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 563 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 564 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 565 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1360 <GIC_SPI 566 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1361 <GIC_SPI 567 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 568 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 569 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 570 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1365 }; 571 };
1366 572
1367 intc: interrupt-controller@17 573 intc: interrupt-controller@17200000 {
1368 compatible = "arm,gic 574 compatible = "arm,gic-v3";
1369 #interrupt-cells = <3 575 #interrupt-cells = <3>;
1370 interrupt-controller; 576 interrupt-controller;
1371 #redistributor-region 577 #redistributor-regions = <1>;
1372 redistributor-stride 578 redistributor-stride = <0x0 0x20000>;
1373 reg = <0x0 0x17200000 579 reg = <0x0 0x17200000 0x0 0x10000>,
1374 <0x0 0x17260000 580 <0x0 0x17260000 0x0 0x80000>;
1375 interrupts = <GIC_PPI 581 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1376 }; 582 };
1377 583
1378 timer@17420000 { 584 timer@17420000 {
1379 compatible = "arm,arm 585 compatible = "arm,armv7-timer-mem";
1380 reg = <0x0 0x17420000 586 reg = <0x0 0x17420000 0x0 0x1000>;
1381 #address-cells = <1>; 587 #address-cells = <1>;
1382 #size-cells = <1>; 588 #size-cells = <1>;
1383 ranges = <0 0 0 0x200 589 ranges = <0 0 0 0x20000000>;
1384 590
1385 frame@17421000 { 591 frame@17421000 {
1386 reg = <0x1742 592 reg = <0x17421000 0x1000>,
1387 <0x1742 593 <0x17422000 0x1000>;
1388 frame-number 594 frame-number = <0>;
1389 interrupts = 595 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1390 596 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1391 }; 597 };
1392 598
1393 frame@17423000 { 599 frame@17423000 {
1394 reg = <0x1742 600 reg = <0x17423000 0x1000>;
1395 frame-number 601 frame-number = <1>;
1396 interrupts = 602 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1397 status = "dis 603 status = "disabled";
1398 }; 604 };
1399 605
1400 frame@17425000 { 606 frame@17425000 {
1401 reg = <0x1742 607 reg = <0x17425000 0x1000>;
1402 frame-number 608 frame-number = <2>;
1403 interrupts = 609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1404 status = "dis 610 status = "disabled";
1405 }; 611 };
1406 612
1407 frame@17427000 { 613 frame@17427000 {
1408 reg = <0x1742 614 reg = <0x17427000 0x1000>;
1409 frame-number 615 frame-number = <3>;
1410 interrupts = 616 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1411 status = "dis 617 status = "disabled";
1412 }; 618 };
1413 619
1414 frame@17429000 { 620 frame@17429000 {
1415 reg = <0x1742 621 reg = <0x17429000 0x1000>;
1416 frame-number 622 frame-number = <4>;
1417 interrupts = 623 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1418 status = "dis 624 status = "disabled";
1419 }; 625 };
1420 626
1421 frame@1742b000 { 627 frame@1742b000 {
1422 reg = <0x1742 628 reg = <0x1742b000 0x1000>;
1423 frame-number 629 frame-number = <5>;
1424 interrupts = 630 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1425 status = "dis 631 status = "disabled";
1426 }; 632 };
1427 633
1428 frame@1742d000 { 634 frame@1742d000 {
1429 reg = <0x1742 635 reg = <0x1742d000 0x1000>;
1430 frame-number 636 frame-number = <6>;
1431 interrupts = 637 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1432 status = "dis 638 status = "disabled";
1433 }; 639 };
1434 }; 640 };
1435 641
1436 apps_rsc: rsc@17a00000 { 642 apps_rsc: rsc@17a00000 {
1437 label = "apps_rsc"; 643 label = "apps_rsc";
1438 compatible = "qcom,rp 644 compatible = "qcom,rpmh-rsc";
1439 reg = <0x0 0x17a00000 645 reg = <0x0 0x17a00000 0x0 0x10000>,
1440 <0x0 0x17a10000 646 <0x0 0x17a10000 0x0 0x10000>,
1441 <0x0 0x17a20000 647 <0x0 0x17a20000 0x0 0x10000>;
1442 reg-names = "drv-0", 648 reg-names = "drv-0", "drv-1", "drv-2";
1443 interrupts = <GIC_SPI 649 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 650 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 651 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1446 652
1447 power-domains = <&CLU 653 power-domains = <&CLUSTER_PD>;
1448 qcom,tcs-offset = <0x 654 qcom,tcs-offset = <0xd00>;
1449 qcom,drv-id = <2>; 655 qcom,drv-id = <2>;
1450 qcom,tcs-config = <AC 656 qcom,tcs-config = <ACTIVE_TCS 3>,
1451 <SL 657 <SLEEP_TCS 2>,
1452 <WA 658 <WAKE_TCS 2>,
1453 <CO 659 <CONTROL_TCS 0>;
1454 660
1455 apps_bcm_voter: bcm-v 661 apps_bcm_voter: bcm-voter {
1456 compatible = 662 compatible = "qcom,bcm-voter";
1457 }; 663 };
1458 664
1459 rpmhcc: clock-control 665 rpmhcc: clock-controller {
1460 compatible = 666 compatible = "qcom,sdx75-rpmh-clk";
1461 clocks = <&xo 667 clocks = <&xo_board>;
1462 clock-names = 668 clock-names = "xo";
1463 #clock-cells 669 #clock-cells = <1>;
1464 }; 670 };
1465 671
1466 rpmhpd: power-control 672 rpmhpd: power-controller {
1467 compatible = 673 compatible = "qcom,sdx75-rpmhpd";
1468 #power-domain 674 #power-domain-cells = <1>;
1469 operating-poi 675 operating-points-v2 = <&rpmhpd_opp_table>;
1470 676
1471 rpmhpd_opp_ta 677 rpmhpd_opp_table: opp-table {
1472 compa 678 compatible = "operating-points-v2";
1473 679
1474 rpmhp 680 rpmhpd_opp_ret: opp-16 {
1475 681 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1476 }; 682 };
1477 683
1478 rpmhp 684 rpmhpd_opp_min_svs: opp-48 {
1479 685 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1480 }; 686 };
1481 687
1482 rpmhp 688 rpmhpd_opp_low_svs: opp-64 {
1483 689 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1484 }; 690 };
1485 691
1486 rpmhp 692 rpmhpd_opp_svs: opp-128 {
1487 693 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1488 }; 694 };
1489 695
1490 rpmhp 696 rpmhpd_opp_svs_l1: opp-192 {
1491 697 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1492 }; 698 };
1493 699
1494 rpmhp 700 rpmhpd_opp_nom: opp-256 {
1495 701 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1496 }; 702 };
1497 703
1498 rpmhp 704 rpmhpd_opp_nom_l1: opp-320 {
1499 705 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1500 }; 706 };
1501 707
1502 rpmhp 708 rpmhpd_opp_nom_l2: opp-336 {
1503 709 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1504 }; 710 };
1505 711
1506 rpmhp 712 rpmhpd_opp_turbo: opp-384 {
1507 713 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1508 }; 714 };
1509 715
1510 rpmhp 716 rpmhpd_opp_turbo_l1: opp-416 {
1511 717 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1512 }; 718 };
1513 }; 719 };
1514 }; 720 };
1515 }; 721 };
1516 722
1517 cpufreq_hw: cpufreq@17d91000 723 cpufreq_hw: cpufreq@17d91000 {
1518 compatible = "qcom,sd 724 compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1519 reg = <0x0 0x17d91000 725 reg = <0x0 0x17d91000 0x0 0x1000>;
1520 reg-names = "freq-dom 726 reg-names = "freq-domain0";
1521 clocks = <&rpmhcc RPM 727 clocks = <&rpmhcc RPMH_CXO_CLK>,
1522 <&gcc GPLL0> 728 <&gcc GPLL0>;
1523 clock-names = "xo", 729 clock-names = "xo",
1524 "altern 730 "alternate";
1525 interrupts = <GIC_SPI 731 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1526 interrupt-names = "dc 732 interrupt-names = "dcvsh-irq-0";
1527 #freq-domain-cells = 733 #freq-domain-cells = <1>;
1528 #clock-cells = <1>; 734 #clock-cells = <1>;
1529 }; <<
1530 <<
1531 dc_noc: interconnect@190e0000 <<
1532 compatible = "qcom,sd <<
1533 reg = <0x0 0x190e0000 <<
1534 #interconnect-cells = <<
1535 qcom,bcm-voters = <&a <<
1536 }; <<
1537 <<
1538 gem_noc: interconnect@1910000 <<
1539 compatible = "qcom,sd <<
1540 reg = <0x0 0x19100000 <<
1541 #interconnect-cells = <<
1542 qcom,bcm-voters = <&a <<
1543 }; 735 };
1544 }; 736 };
1545 737
1546 timer { 738 timer {
1547 compatible = "arm,armv8-timer 739 compatible = "arm,armv8-timer";
1548 interrupts = <GIC_PPI 13 (GIC 740 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1549 <GIC_PPI 14 (GIC 741 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1550 <GIC_PPI 11 (GIC 742 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1551 <GIC_PPI 12 (GIC 743 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1552 }; 744 };
1553 }; 745 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.