1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dy
4 * Copyright (c) 2022, Luca Weiss <luca.weiss@f
5 */
6
7 #include <dt-bindings/clock/qcom,dispcc-sm6350
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350.
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc.
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3
16 #include <dt-bindings/interconnect/qcom,sm6350
17 #include <dt-bindings/interrupt-controller/arm
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h>
23
24 / {
25 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 clocks {
30 xo_board: xo-board {
31 compatible = "fixed-cl
32 #clock-cells = <0>;
33 clock-frequency = <768
34 clock-output-names = "
35 };
36
37 sleep_clk: sleep-clk {
38 compatible = "fixed-cl
39 clock-frequency = <327
40 #clock-cells = <0>;
41 };
42 };
43
44 cpus {
45 #address-cells = <2>;
46 #size-cells = <0>;
47
48 CPU0: cpu@0 {
49 device_type = "cpu";
50 compatible = "qcom,kry
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw
53 enable-method = "psci"
54 capacity-dmips-mhz = <
55 dynamic-power-coeffici
56 next-level-cache = <&L
57 qcom,freq-domain = <&c
58 operating-points-v2 =
59 interconnects = <&gem_
60 &clk_
61 <&osm_
62 power-domains = <&CPU_
63 power-domain-names = "
64 #cooling-cells = <2>;
65 L2_0: l2-cache {
66 compatible = "
67 cache-level =
68 cache-unified;
69 next-level-cac
70 L3_0: l3-cache
71 compat
72 cache-
73 cache-
74 };
75 };
76 };
77
78 CPU1: cpu@100 {
79 device_type = "cpu";
80 compatible = "qcom,kry
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw
83 enable-method = "psci"
84 capacity-dmips-mhz = <
85 dynamic-power-coeffici
86 next-level-cache = <&L
87 qcom,freq-domain = <&c
88 operating-points-v2 =
89 interconnects = <&gem_
90 &clk_
91 <&osm_
92 power-domains = <&CPU_
93 power-domain-names = "
94 #cooling-cells = <2>;
95 L2_100: l2-cache {
96 compatible = "
97 cache-level =
98 cache-unified;
99 next-level-cac
100 };
101 };
102
103 CPU2: cpu@200 {
104 device_type = "cpu";
105 compatible = "qcom,kry
106 reg = <0x0 0x200>;
107 clocks = <&cpufreq_hw
108 enable-method = "psci"
109 capacity-dmips-mhz = <
110 dynamic-power-coeffici
111 next-level-cache = <&L
112 qcom,freq-domain = <&c
113 operating-points-v2 =
114 interconnects = <&gem_
115 &clk_
116 <&osm_
117 power-domains = <&CPU_
118 power-domain-names = "
119 #cooling-cells = <2>;
120 L2_200: l2-cache {
121 compatible = "
122 cache-level =
123 cache-unified;
124 next-level-cac
125 };
126 };
127
128 CPU3: cpu@300 {
129 device_type = "cpu";
130 compatible = "qcom,kry
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw
133 enable-method = "psci"
134 capacity-dmips-mhz = <
135 dynamic-power-coeffici
136 next-level-cache = <&L
137 qcom,freq-domain = <&c
138 operating-points-v2 =
139 interconnects = <&gem_
140 &clk_
141 <&osm_
142 power-domains = <&CPU_
143 power-domain-names = "
144 #cooling-cells = <2>;
145 L2_300: l2-cache {
146 compatible = "
147 cache-level =
148 cache-unified;
149 next-level-cac
150 };
151 };
152
153 CPU4: cpu@400 {
154 device_type = "cpu";
155 compatible = "qcom,kry
156 reg = <0x0 0x400>;
157 clocks = <&cpufreq_hw
158 enable-method = "psci"
159 capacity-dmips-mhz = <
160 dynamic-power-coeffici
161 next-level-cache = <&L
162 qcom,freq-domain = <&c
163 operating-points-v2 =
164 interconnects = <&gem_
165 &clk_
166 <&osm_
167 power-domains = <&CPU_
168 power-domain-names = "
169 #cooling-cells = <2>;
170 L2_400: l2-cache {
171 compatible = "
172 cache-level =
173 cache-unified;
174 next-level-cac
175 };
176 };
177
178 CPU5: cpu@500 {
179 device_type = "cpu";
180 compatible = "qcom,kry
181 reg = <0x0 0x500>;
182 clocks = <&cpufreq_hw
183 enable-method = "psci"
184 capacity-dmips-mhz = <
185 dynamic-power-coeffici
186 next-level-cache = <&L
187 qcom,freq-domain = <&c
188 operating-points-v2 =
189 interconnects = <&gem_
190 &clk_
191 <&osm_
192 power-domains = <&CPU_
193 power-domain-names = "
194 #cooling-cells = <2>;
195 L2_500: l2-cache {
196 compatible = "
197 cache-level =
198 cache-unified;
199 next-level-cac
200 };
201 };
202
203 CPU6: cpu@600 {
204 device_type = "cpu";
205 compatible = "qcom,kry
206 reg = <0x0 0x600>;
207 clocks = <&cpufreq_hw
208 enable-method = "psci"
209 capacity-dmips-mhz = <
210 dynamic-power-coeffici
211 next-level-cache = <&L
212 qcom,freq-domain = <&c
213 operating-points-v2 =
214 interconnects = <&gem_
215 &clk_
216 <&osm_
217 power-domains = <&CPU_
218 power-domain-names = "
219 #cooling-cells = <2>;
220 L2_600: l2-cache {
221 compatible = "
222 cache-level =
223 cache-unified;
224 next-level-cac
225 };
226 };
227
228 CPU7: cpu@700 {
229 device_type = "cpu";
230 compatible = "qcom,kry
231 reg = <0x0 0x700>;
232 clocks = <&cpufreq_hw
233 enable-method = "psci"
234 capacity-dmips-mhz = <
235 dynamic-power-coeffici
236 next-level-cache = <&L
237 qcom,freq-domain = <&c
238 operating-points-v2 =
239 interconnects = <&gem_
240 &clk_
241 <&osm_
242 power-domains = <&CPU_
243 power-domain-names = "
244 #cooling-cells = <2>;
245 L2_700: l2-cache {
246 compatible = "
247 cache-level =
248 cache-unified;
249 next-level-cac
250 };
251 };
252
253 cpu-map {
254 cluster0 {
255 core0 {
256 cpu =
257 };
258
259 core1 {
260 cpu =
261 };
262
263 core2 {
264 cpu =
265 };
266
267 core3 {
268 cpu =
269 };
270
271 core4 {
272 cpu =
273 };
274
275 core5 {
276 cpu =
277 };
278
279 core6 {
280 cpu =
281 };
282
283 core7 {
284 cpu =
285 };
286 };
287 };
288
289 domain-idle-states {
290 CLUSTER_SLEEP_PC: clus
291 compatible = "
292 arm,psci-suspe
293 entry-latency-
294 exit-latency-u
295 min-residency-
296 };
297
298 CLUSTER_SLEEP_CX_RET:
299 compatible = "
300 arm,psci-suspe
301 entry-latency-
302 exit-latency-u
303 min-residency-
304 };
305
306 CLUSTER_AOSS_SLEEP: cl
307 compatible = "
308 arm,psci-suspe
309 entry-latency-
310 exit-latency-u
311 min-residency-
312 };
313 };
314
315 cpu_idle_states: idle-states {
316 entry-method = "psci";
317
318 LITTLE_CPU_SLEEP_0: cp
319 compatible = "
320 idle-state-nam
321 arm,psci-suspe
322 entry-latency-
323 exit-latency-u
324 min-residency-
325 local-timer-st
326 };
327
328 LITTLE_CPU_SLEEP_1: cp
329 compatible = "
330 idle-state-nam
331 arm,psci-suspe
332 entry-latency-
333 exit-latency-u
334 min-residency-
335 local-timer-st
336 };
337
338 BIG_CPU_SLEEP_0: cpu-s
339 compatible = "
340 idle-state-nam
341 arm,psci-suspe
342 entry-latency-
343 exit-latency-u
344 min-residency-
345 local-timer-st
346 };
347
348 BIG_CPU_SLEEP_1: cpu-s
349 compatible = "
350 idle-state-nam
351 arm,psci-suspe
352 entry-latency-
353 exit-latency-u
354 min-residency-
355 local-timer-st
356 };
357 };
358 };
359
360 firmware {
361 scm: scm {
362 compatible = "qcom,scm
363 #reset-cells = <1>;
364 };
365 };
366
367 memory@80000000 {
368 device_type = "memory";
369 /* We expect the bootloader to
370 reg = <0x0 0x80000000 0x0 0x0>
371 };
372
373 cpu0_opp_table: opp-table-cpu0 {
374 compatible = "operating-points
375 opp-shared;
376
377 opp-300000000 {
378 opp-hz = /bits/ 64 <30
379 /* DDR: 4-wide, 2 chan
380 opp-peak-kBps = <(2000
381 };
382
383 opp-576000000 {
384 opp-hz = /bits/ 64 <57
385 opp-peak-kBps = <(5470
386 };
387
388 opp-768000000 {
389 opp-hz = /bits/ 64 <76
390 opp-peak-kBps = <(7680
391 };
392
393 opp-1017600000 {
394 opp-hz = /bits/ 64 <10
395 opp-peak-kBps = <(1017
396 };
397
398 opp-1248000000 {
399 opp-hz = /bits/ 64 <12
400 opp-peak-kBps = <(1017
401 };
402
403 opp-1324800000 {
404 opp-hz = /bits/ 64 <13
405 opp-peak-kBps = <(1017
406 };
407
408 opp-1516800000 {
409 opp-hz = /bits/ 64 <15
410 opp-peak-kBps = <(1353
411 };
412
413 opp-1612800000 {
414 opp-hz = /bits/ 64 <16
415 opp-peak-kBps = <(1555
416 };
417
418 opp-1708800000 {
419 opp-hz = /bits/ 64 <17
420 opp-peak-kBps = <(1555
421 };
422 };
423
424 cpu6_opp_table: opp-table-cpu6 {
425 compatible = "operating-points
426 opp-shared;
427
428 opp-300000000 {
429 opp-hz = /bits/ 64 <30
430 opp-peak-kBps = <(2000
431 };
432
433 opp-787200000 {
434 opp-hz = /bits/ 64 <78
435 opp-peak-kBps = <(7680
436 };
437
438 opp-979200000 {
439 opp-hz = /bits/ 64 <97
440 opp-peak-kBps = <(7680
441 };
442
443 opp-1036800000 {
444 opp-hz = /bits/ 64 <10
445 opp-peak-kBps = <(1017
446 };
447
448 opp-1248000000 {
449 opp-hz = /bits/ 64 <12
450 opp-peak-kBps = <(1017
451 };
452
453 opp-1401600000 {
454 opp-hz = /bits/ 64 <14
455 opp-peak-kBps = <(1353
456 };
457
458 opp-1555200000 {
459 opp-hz = /bits/ 64 <15
460 opp-peak-kBps = <(1555
461 };
462
463 opp-1766400000 {
464 opp-hz = /bits/ 64 <17
465 opp-peak-kBps = <(1555
466 };
467
468 opp-1900800000 {
469 opp-hz = /bits/ 64 <19
470 opp-peak-kBps = <(1804
471 };
472
473 opp-2073600000 {
474 opp-hz = /bits/ 64 <20
475 opp-peak-kBps = <(2092
476 };
477 };
478
479 qup_opp_table: opp-table-qup {
480 compatible = "operating-points
481
482 opp-75000000 {
483 opp-hz = /bits/ 64 <75
484 required-opps = <&rpmh
485 };
486
487 opp-100000000 {
488 opp-hz = /bits/ 64 <10
489 required-opps = <&rpmh
490 };
491
492 opp-128000000 {
493 opp-hz = /bits/ 64 <12
494 required-opps = <&rpmh
495 };
496 };
497
498 pmu {
499 compatible = "arm,armv8-pmuv3"
500 interrupts = <GIC_PPI 5 IRQ_TY
501 };
502
503 psci {
504 compatible = "arm,psci-1.0";
505 method = "smc";
506
507 CPU_PD0: power-domain-cpu0 {
508 #power-domain-cells =
509 power-domains = <&CLUS
510 domain-idle-states = <
511 };
512
513 CPU_PD1: power-domain-cpu1 {
514 #power-domain-cells =
515 power-domains = <&CLUS
516 domain-idle-states = <
517 };
518
519 CPU_PD2: power-domain-cpu2 {
520 #power-domain-cells =
521 power-domains = <&CLUS
522 domain-idle-states = <
523 };
524
525 CPU_PD3: power-domain-cpu3 {
526 #power-domain-cells =
527 power-domains = <&CLUS
528 domain-idle-states = <
529 };
530
531 CPU_PD4: power-domain-cpu4 {
532 #power-domain-cells =
533 power-domains = <&CLUS
534 domain-idle-states = <
535 };
536
537 CPU_PD5: power-domain-cpu5 {
538 #power-domain-cells =
539 power-domains = <&CLUS
540 domain-idle-states = <
541 };
542
543 CPU_PD6: power-domain-cpu6 {
544 #power-domain-cells =
545 power-domains = <&CLUS
546 domain-idle-states = <
547 };
548
549 CPU_PD7: power-domain-cpu7 {
550 #power-domain-cells =
551 power-domains = <&CLUS
552 domain-idle-states = <
553 };
554
555 CLUSTER_PD: power-domain-cpu-c
556 #power-domain-cells =
557 domain-idle-states = <
558
559
560 };
561 };
562
563 reserved_memory: reserved-memory {
564 #address-cells = <2>;
565 #size-cells = <2>;
566 ranges;
567
568 hyp_mem: memory@80000000 {
569 reg = <0 0x80000000 0
570 no-map;
571 };
572
573 xbl_aop_mem: memory@80700000 {
574 reg = <0 0x80700000 0
575 no-map;
576 };
577
578 cmd_db: memory@80860000 {
579 compatible = "qcom,cmd
580 reg = <0 0x80860000 0
581 no-map;
582 };
583
584 sec_apps_mem: memory@808ff000
585 reg = <0 0x808ff000 0
586 no-map;
587 };
588
589 smem_mem: memory@80900000 {
590 reg = <0 0x80900000 0
591 no-map;
592 };
593
594 cdsp_sec_mem: memory@80b00000
595 reg = <0 0x80b00000 0
596 no-map;
597 };
598
599 pil_camera_mem: memory@8600000
600 reg = <0 0x86000000 0
601 no-map;
602 };
603
604 pil_npu_mem: memory@86500000 {
605 reg = <0 0x86500000 0
606 no-map;
607 };
608
609 pil_video_mem: memory@86a00000
610 reg = <0 0x86a00000 0
611 no-map;
612 };
613
614 pil_cdsp_mem: memory@86f00000
615 reg = <0 0x86f00000 0
616 no-map;
617 };
618
619 pil_adsp_mem: memory@88d00000
620 reg = <0 0x88d00000 0
621 no-map;
622 };
623
624 wlan_fw_mem: memory@8b500000 {
625 reg = <0 0x8b500000 0
626 no-map;
627 };
628
629 pil_ipa_fw_mem: memory@8b70000
630 reg = <0 0x8b700000 0
631 no-map;
632 };
633
634 pil_ipa_gsi_mem: memory@8b7100
635 reg = <0 0x8b710000 0
636 no-map;
637 };
638
639 pil_modem_mem: memory@8b800000
640 reg = <0 0x8b800000 0
641 no-map;
642 };
643
644 cont_splash_memory: memory@a00
645 reg = <0 0xa0000000 0
646 no-map;
647 };
648
649 dfps_data_memory: memory@a2300
650 reg = <0 0xa2300000 0
651 no-map;
652 };
653
654 removed_region: memory@c000000
655 reg = <0 0xc0000000 0
656 no-map;
657 };
658
659 pil_gpu_mem: memory@f0d00000 {
660 reg = <0 0xf0d00000 0
661 no-map;
662 };
663
664 debug_region: memory@ffb00000
665 reg = <0 0xffb00000 0
666 no-map;
667 };
668
669 last_log_region: memory@ffbc00
670 reg = <0 0xffbc0000 0
671 no-map;
672 };
673
674 ramoops: ramoops@ffc00000 {
675 compatible = "ramoops"
676 reg = <0 0xffc00000 0
677 record-size = <0x1000>
678 console-size = <0x4000
679 pmsg-size = <0x20000>;
680 ecc-size = <16>;
681 no-map;
682 };
683
684 cmdline_region: memory@ffd0000
685 reg = <0 0xffd00000 0
686 no-map;
687 };
688 };
689
690 smem {
691 compatible = "qcom,smem";
692 memory-region = <&smem_mem>;
693 hwlocks = <&tcsr_mutex 3>;
694 };
695
696 smp2p-adsp {
697 compatible = "qcom,smp2p";
698 qcom,smem = <443>, <429>;
699 interrupts-extended = <&ipcc I
700 I
701 I
702 mboxes = <&ipcc IPCC_CLIENT_LP
703 IPCC_MPROC_SIG
704
705 qcom,local-pid = <0>;
706 qcom,remote-pid = <2>;
707
708 smp2p_adsp_out: master-kernel
709 qcom,entry-name = "mas
710 #qcom,smem-state-cells
711 };
712
713 smp2p_adsp_in: slave-kernel {
714 qcom,entry-name = "sla
715 interrupt-controller;
716 #interrupt-cells = <2>
717 };
718 };
719
720 smp2p-cdsp {
721 compatible = "qcom,smp2p";
722 qcom,smem = <94>, <432>;
723 interrupts-extended = <&ipcc I
724 I
725 I
726 mboxes = <&ipcc IPCC_CLIENT_CD
727 IPCC_MPROC_SIG
728
729 qcom,local-pid = <0>;
730 qcom,remote-pid = <5>;
731
732 smp2p_cdsp_out: master-kernel
733 qcom,entry-name = "mas
734 #qcom,smem-state-cells
735 };
736
737 smp2p_cdsp_in: slave-kernel {
738 qcom,entry-name = "sla
739 interrupt-controller;
740 #interrupt-cells = <2>
741 };
742 };
743
744 smp2p-mpss {
745 compatible = "qcom,smp2p";
746 qcom,smem = <435>, <428>;
747
748 interrupts-extended = <&ipcc I
749 I
750 I
751 mboxes = <&ipcc IPCC_CLIENT_MP
752 IPCC_MPROC_SIG
753
754 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>;
756
757 modem_smp2p_out: master-kernel
758 qcom,entry-name = "mas
759 #qcom,smem-state-cells
760 };
761
762 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "sla
764 interrupt-controller;
765 #interrupt-cells = <2>
766 };
767
768 ipa_smp2p_out: ipa-ap-to-modem
769 qcom,entry-name = "ipa
770 #qcom,smem-state-cells
771 };
772
773 ipa_smp2p_in: ipa-modem-to-ap
774 qcom,entry-name = "ipa
775 interrupt-controller;
776 #interrupt-cells = <2>
777 };
778 };
779
780 soc: soc@0 {
781 #address-cells = <2>;
782 #size-cells = <2>;
783 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus";
786
787 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc
789 reg = <0 0x00100000 0
790 #clock-cells = <1>;
791 #reset-cells = <1>;
792 #power-domain-cells =
793 clock-names = "bi_tcxo
794 "bi_tcxo
795 "sleep_c
796 clocks = <&rpmhcc RPMH
797 <&rpmhcc RPMH
798 <&sleep_clk>;
799 };
800
801 ipcc: mailbox@408000 {
802 compatible = "qcom,sm6
803 reg = <0 0x00408000 0
804 interrupts = <GIC_SPI
805 interrupt-controller;
806 #interrupt-cells = <3>
807 #mbox-cells = <2>;
808 };
809
810 qfprom: qfprom@784000 {
811 compatible = "qcom,sm6
812 reg = <0 0x00784000 0
813 #address-cells = <1>;
814 #size-cells = <1>;
815
816 gpu_speed_bin: gpu-spe
817 reg = <0x2015
818 bits = <0 8>;
819 };
820 };
821
822 rng: rng@793000 {
823 compatible = "qcom,prn
824 reg = <0 0x00793000 0
825 clocks = <&gcc GCC_PRN
826 clock-names = "core";
827 };
828
829 sdhc_1: mmc@7c4000 {
830 compatible = "qcom,sm6
831 reg = <0 0x007c4000 0
832 <0 0x007c5000
833 <0 0x007c8000
834 reg-names = "hc", "cqh
835
836 interrupts = <GIC_SPI
837 <GIC_SPI
838 interrupt-names = "hc_
839 iommus = <&apps_smmu 0
840
841 clocks = <&gcc GCC_SDC
842 <&gcc GCC_SDC
843 <&rpmhcc RPMH
844 clock-names = "iface",
845 resets = <&gcc GCC_SDC
846 qcom,dll-config = <0x0
847 qcom,ddr-config = <0x8
848 power-domains = <&rpmh
849 operating-points-v2 =
850 bus-width = <8>;
851 non-removable;
852 supports-cqe;
853
854 status = "disabled";
855
856 sdhc1_opp_table: opp-t
857 compatible = "
858
859 opp-19200000 {
860 opp-hz
861 requir
862 };
863
864 opp-100000000
865 opp-hz
866 requir
867 };
868
869 opp-384000000
870 opp-hz
871 requir
872 };
873 };
874 };
875
876 gpi_dma0: dma-controller@80000
877 compatible = "qcom,sm6
878 reg = <0 0x00800000 0
879 interrupts = <GIC_SPI
880 <GIC_SPI
881 <GIC_SPI
882 <GIC_SPI
883 <GIC_SPI
884 <GIC_SPI
885 <GIC_SPI
886 <GIC_SPI
887 <GIC_SPI
888 <GIC_SPI
889 dma-channels = <10>;
890 dma-channel-mask = <0x
891 iommus = <&apps_smmu 0
892 #dma-cells = <3>;
893 status = "disabled";
894 };
895
896 qupv3_id_0: geniqup@8c0000 {
897 compatible = "qcom,gen
898 reg = <0x0 0x008c0000
899 clock-names = "m-ahb",
900 clocks = <&gcc GCC_QUP
901 <&gcc GCC_QUP
902 #address-cells = <2>;
903 #size-cells = <2>;
904 iommus = <&apps_smmu 0
905 ranges;
906 status = "disabled";
907
908 i2c0: i2c@880000 {
909 compatible = "
910 reg = <0 0x008
911 clock-names =
912 clocks = <&gcc
913 pinctrl-names
914 pinctrl-0 = <&
915 interrupts = <
916 dmas = <&gpi_d
917 <&gpi_d
918 dma-names = "t
919 #address-cells
920 #size-cells =
921 interconnects
922
923
924 interconnect-n
925 status = "disa
926 };
927
928 uart1: serial@884000 {
929 compatible = "
930 reg = <0 0x008
931 clock-names =
932 clocks = <&gcc
933 pinctrl-names
934 pinctrl-0 = <&
935 interrupts = <
936 power-domains
937 operating-poin
938 interconnects
939
940 interconnect-n
941 status = "disa
942 };
943
944 i2c2: i2c@888000 {
945 compatible = "
946 reg = <0 0x008
947 clock-names =
948 clocks = <&gcc
949 pinctrl-names
950 pinctrl-0 = <&
951 interrupts = <
952 dmas = <&gpi_d
953 <&gpi_d
954 dma-names = "t
955 #address-cells
956 #size-cells =
957 interconnects
958
959
960 interconnect-n
961 status = "disa
962 };
963 };
964
965 gpi_dma1: dma-controller@90000
966 compatible = "qcom,sm6
967 reg = <0 0x00900000 0
968 interrupts = <GIC_SPI
969 <GIC_SPI
970 <GIC_SPI
971 <GIC_SPI
972 <GIC_SPI
973 <GIC_SPI
974 <GIC_SPI
975 <GIC_SPI
976 <GIC_SPI
977 <GIC_SPI
978 dma-channels = <10>;
979 dma-channel-mask = <0x
980 iommus = <&apps_smmu 0
981 #dma-cells = <3>;
982 status = "disabled";
983 };
984
985 qupv3_id_1: geniqup@9c0000 {
986 compatible = "qcom,gen
987 reg = <0x0 0x009c0000
988 clock-names = "m-ahb",
989 clocks = <&gcc GCC_QUP
990 <&gcc GCC_QUP
991 #address-cells = <2>;
992 #size-cells = <2>;
993 iommus = <&apps_smmu 0
994 ranges;
995 status = "disabled";
996
997 i2c6: i2c@980000 {
998 compatible = "
999 reg = <0 0x009
1000 clock-names =
1001 clocks = <&gc
1002 pinctrl-names
1003 pinctrl-0 = <
1004 interrupts =
1005 dmas = <&gpi_
1006 <&gpi_
1007 dma-names = "
1008 #address-cell
1009 #size-cells =
1010 interconnects
1011
1012
1013 interconnect-
1014 status = "dis
1015 };
1016
1017 i2c7: i2c@984000 {
1018 compatible =
1019 reg = <0 0x00
1020 clock-names =
1021 clocks = <&gc
1022 pinctrl-names
1023 pinctrl-0 = <
1024 interrupts =
1025 dmas = <&gpi_
1026 <&gpi_
1027 dma-names = "
1028 #address-cell
1029 #size-cells =
1030 interconnects
1031
1032
1033 interconnect-
1034 status = "dis
1035 };
1036
1037 i2c8: i2c@988000 {
1038 compatible =
1039 reg = <0 0x00
1040 clock-names =
1041 clocks = <&gc
1042 pinctrl-names
1043 pinctrl-0 = <
1044 interrupts =
1045 dmas = <&gpi_
1046 <&gpi_
1047 dma-names = "
1048 #address-cell
1049 #size-cells =
1050 interconnects
1051
1052
1053 interconnect-
1054 status = "dis
1055 };
1056
1057 uart9: serial@98c000
1058 compatible =
1059 reg = <0 0x00
1060 clock-names =
1061 clocks = <&gc
1062 pinctrl-names
1063 pinctrl-0 = <
1064 interrupts =
1065 interconnects
1066
1067 interconnect-
1068 status = "dis
1069 };
1070
1071 i2c10: i2c@990000 {
1072 compatible =
1073 reg = <0 0x00
1074 clock-names =
1075 clocks = <&gc
1076 pinctrl-names
1077 pinctrl-0 = <
1078 interrupts =
1079 dmas = <&gpi_
1080 <&gpi_
1081 dma-names = "
1082 #address-cell
1083 #size-cells =
1084 interconnects
1085
1086
1087 interconnect-
1088 status = "dis
1089 };
1090 };
1091
1092 config_noc: interconnect@1500
1093 compatible = "qcom,sm
1094 reg = <0 0x01500000 0
1095 #interconnect-cells =
1096 qcom,bcm-voters = <&a
1097 };
1098
1099 system_noc: interconnect@1620
1100 compatible = "qcom,sm
1101 reg = <0 0x01620000 0
1102 #interconnect-cells =
1103 qcom,bcm-voters = <&a
1104
1105 clk_virt: interconnec
1106 compatible =
1107 #interconnect
1108 qcom,bcm-vote
1109 };
1110 };
1111
1112 aggre1_noc: interconnect@16e0
1113 compatible = "qcom,sm
1114 reg = <0 0x016e0000 0
1115 #interconnect-cells =
1116 qcom,bcm-voters = <&a
1117 };
1118
1119 aggre2_noc: interconnect@1700
1120 compatible = "qcom,sm
1121 reg = <0 0x01700000 0
1122 #interconnect-cells =
1123 qcom,bcm-voters = <&a
1124
1125 compute_noc: intercon
1126 compatible =
1127 #interconnect
1128 qcom,bcm-vote
1129 };
1130 };
1131
1132 mmss_noc: interconnect@174000
1133 compatible = "qcom,sm
1134 reg = <0 0x01740000 0
1135 #interconnect-cells =
1136 qcom,bcm-voters = <&a
1137 };
1138
1139 ufs_mem_hc: ufs@1d84000 {
1140 compatible = "qcom,sm
1141 "jedec,u
1142 reg = <0 0x01d84000 0
1143 <0 0x01d90000 0
1144 reg-names = "std", "i
1145 interrupts = <GIC_SPI
1146 phys = <&ufs_mem_phy>
1147 phy-names = "ufsphy";
1148 lanes-per-direction =
1149 #reset-cells = <1>;
1150 resets = <&gcc GCC_UF
1151 reset-names = "rst";
1152
1153 power-domains = <&gcc
1154
1155 iommus = <&apps_smmu
1156
1157 clock-names = "core_c
1158 "bus_ag
1159 "iface_
1160 "core_c
1161 "ref_cl
1162 "tx_lan
1163 "rx_lan
1164 "rx_lan
1165 "ice_co
1166 clocks = <&gcc GCC_UF
1167 <&gcc GCC_AG
1168 <&gcc GCC_UF
1169 <&gcc GCC_UF
1170 <&rpmhcc RPM
1171 <&gcc GCC_UF
1172 <&gcc GCC_UF
1173 <&gcc GCC_UF
1174 <&gcc GCC_UF
1175 freq-table-hz =
1176 <50000000 200
1177 <0 0>,
1178 <0 0>,
1179 <37500000 150
1180 <75000000 300
1181 <0 0>,
1182 <0 0>,
1183 <0 0>,
1184 <0 0>;
1185
1186 status = "disabled";
1187 };
1188
1189 ufs_mem_phy: phy@1d87000 {
1190 compatible = "qcom,sm
1191 reg = <0 0x01d87000 0
1192
1193 clocks = <&rpmhcc RPM
1194 <&gcc GCC_UF
1195 <&gcc GCC_UF
1196 clock-names = "ref",
1197 "ref_au
1198 "qref";
1199
1200 power-domains = <&gcc
1201
1202 resets = <&ufs_mem_hc
1203 reset-names = "ufsphy
1204
1205 #phy-cells = <0>;
1206
1207 status = "disabled";
1208 };
1209
1210 cryptobam: dma-controller@1dc
1211 compatible = "qcom,ba
1212 reg = <0 0x01dc4000 0
1213 interrupts = <GIC_SPI
1214 #dma-cells = <1>;
1215 qcom,ee = <0>;
1216 qcom,controlled-remot
1217 num-channels = <16>;
1218 qcom,num-ees = <4>;
1219 iommus = <&apps_smmu
1220 <&apps_smmu
1221 <&apps_smmu
1222 <&apps_smmu
1223 <&apps_smmu
1224 };
1225
1226 crypto: crypto@1dfa000 {
1227 compatible = "qcom,sm
1228 reg = <0 0x01dfa000 0
1229 dmas = <&cryptobam 4>
1230 dma-names = "rx", "tx
1231 iommus = <&apps_smmu
1232 <&apps_smmu
1233 <&apps_smmu
1234 <&apps_smmu
1235 <&apps_smmu
1236 interconnects = <&agg
1237 &clk
1238 interconnect-names =
1239 };
1240
1241 ipa: ipa@1e40000 {
1242 compatible = "qcom,sm
1243
1244 iommus = <&apps_smmu
1245 <&apps_smmu
1246 reg = <0 0x01e40000 0
1247 <0 0x01e50000 0
1248 <0 0x01e04000 0
1249 reg-names = "ipa-reg"
1250 "ipa-shar
1251 "gsi";
1252
1253 interrupts-extended =
1254
1255
1256
1257 interrupt-names = "ip
1258 "gs
1259 "ip
1260 "ip
1261
1262 clocks = <&rpmhcc RPM
1263 clock-names = "core";
1264
1265 interconnects = <&agg
1266 <&agg
1267 <&gem
1268 interconnect-names =
1269
1270 qcom,smem-states = <&
1271 <&
1272 qcom,smem-state-names
1273
1274
1275 status = "disabled";
1276 };
1277
1278 tcsr_mutex: hwlock@1f40000 {
1279 compatible = "qcom,tc
1280 reg = <0x0 0x01f40000
1281 #hwlock-cells = <1>;
1282 };
1283
1284 adsp: remoteproc@3000000 {
1285 compatible = "qcom,sm
1286 reg = <0 0x03000000 0
1287
1288 interrupts-extended =
1289
1290
1291
1292
1293 interrupt-names = "wd
1294 "ha
1295
1296 clocks = <&rpmhcc RPM
1297 clock-names = "xo";
1298
1299 power-domains = <&rpm
1300 <&rpm
1301 power-domain-names =
1302
1303 memory-region = <&pil
1304
1305 qcom,qmp = <&aoss_qmp
1306
1307 qcom,smem-states = <&
1308 qcom,smem-state-names
1309
1310 status = "disabled";
1311
1312 glink-edge {
1313 interrupts-ex
1314
1315
1316 mboxes = <&ip
1317
1318
1319 label = "lpas
1320 qcom,remote-p
1321
1322 fastrpc {
1323 compa
1324 qcom,
1325 label
1326 qcom,
1327 #addr
1328 #size
1329
1330 compu
1331
1332
1333
1334 };
1335
1336 compu
1337
1338
1339
1340 };
1341
1342 compu
1343
1344
1345
1346
1347 };
1348 };
1349 };
1350 };
1351
1352 gpu: gpu@3d00000 {
1353 compatible = "qcom,ad
1354 reg = <0 0x03d00000 0
1355 <0 0x03d9e000 0
1356 reg-names = "kgsl_3d0
1357 "cx_mem";
1358 interrupts = <GIC_SPI
1359
1360 iommus = <&adreno_smm
1361 operating-points-v2 =
1362 qcom,gmu = <&gmu>;
1363 nvmem-cells = <&gpu_s
1364 nvmem-cell-names = "s
1365 #cooling-cells = <2>;
1366
1367 status = "disabled";
1368
1369 gpu_zap_shader: zap-s
1370 memory-region
1371 };
1372
1373 gpu_opp_table: opp-ta
1374 compatible =
1375
1376 opp-850000000
1377 opp-h
1378 opp-l
1379 opp-s
1380 };
1381
1382 opp-800000000
1383 opp-h
1384 opp-l
1385 opp-s
1386 };
1387
1388 opp-650000000
1389 opp-h
1390 opp-l
1391 opp-s
1392 };
1393
1394 opp-565000000
1395 opp-h
1396 opp-l
1397 opp-s
1398 };
1399
1400 opp-430000000
1401 opp-h
1402 opp-l
1403 opp-s
1404 };
1405
1406 opp-355000000
1407 opp-h
1408 opp-l
1409 opp-s
1410 };
1411
1412 opp-253000000
1413 opp-h
1414 opp-l
1415 opp-s
1416 };
1417 };
1418 };
1419
1420 adreno_smmu: iommu@3d40000 {
1421 compatible = "qcom,sm
1422 reg = <0 0x03d40000 0
1423 #iommu-cells = <1>;
1424 #global-interrupts =
1425 interrupts = <GIC_SPI
1426 <GIC_SPI
1427 <GIC_SPI
1428 <GIC_SPI
1429 <GIC_SPI
1430 <GIC_SPI
1431 <GIC_SPI
1432 <GIC_SPI
1433 <GIC_SPI
1434 <GIC_SPI
1435
1436 clocks = <&gpucc GPU_
1437 <&gcc GCC_GP
1438 <&gcc GCC_GP
1439 clock-names = "ahb",
1440 "bus",
1441 "iface"
1442
1443 power-domains = <&gpu
1444 };
1445
1446 gmu: gmu@3d6a000 {
1447 compatible = "qcom,ad
1448 reg = <0 0x03d6a000 0
1449 <0 0x0b290000 0
1450 <0 0x0b490000 0
1451 reg-names = "gmu",
1452 "gmu_pdc"
1453 "gmu_pdc_
1454
1455 interrupts = <GIC_SPI
1456 <GIC_SPI
1457 interrupt-names = "hf
1458 "gm
1459
1460 clocks = <&gpucc GPU_
1461 <&gpucc GPU_
1462 <&gpucc GPU_
1463 <&gcc GCC_DD
1464 <&gcc GCC_GP
1465 clock-names = "ahb",
1466 "gmu",
1467 "cxo",
1468 "axi",
1469 "memnoc
1470
1471 power-domains = <&gpu
1472 <&gpu
1473 power-domain-names =
1474
1475
1476 iommus = <&adreno_smm
1477
1478 operating-points-v2 =
1479
1480 gmu_opp_table: opp-ta
1481 compatible =
1482
1483 opp-200000000
1484 opp-h
1485 opp-l
1486 };
1487 };
1488 };
1489
1490 gpucc: clock-controller@3d900
1491 compatible = "qcom,sm
1492 reg = <0 0x03d90000 0
1493 clocks = <&rpmhcc RPM
1494 <&gcc GCC_GP
1495 <&gcc GCC_GP
1496 clock-names = "bi_tcx
1497 "gcc_gp
1498 "gcc_gp
1499 #clock-cells = <1>;
1500 #reset-cells = <1>;
1501 #power-domain-cells =
1502 };
1503
1504 mpss: remoteproc@4080000 {
1505 compatible = "qcom,sm
1506 reg = <0x0 0x04080000
1507
1508 interrupts-extended =
1509
1510
1511
1512
1513
1514 interrupt-names = "wd
1515 "st
1516
1517 clocks = <&rpmhcc RPM
1518 clock-names = "xo";
1519
1520 power-domains = <&rpm
1521 <&rpm
1522 power-domain-names =
1523
1524 memory-region = <&pil
1525
1526 qcom,qmp = <&aoss_qmp
1527
1528 qcom,smem-states = <&
1529 qcom,smem-state-names
1530
1531 status = "disabled";
1532
1533 glink-edge {
1534 interrupts-ex
1535
1536
1537 mboxes = <&ip
1538
1539 label = "mode
1540 qcom,remote-p
1541 };
1542 };
1543
1544 cdsp: remoteproc@8300000 {
1545 compatible = "qcom,sm
1546 reg = <0 0x08300000 0
1547
1548 interrupts-extended =
1549
1550
1551
1552
1553 interrupt-names = "wd
1554 "ha
1555
1556 clocks = <&rpmhcc RPM
1557 clock-names = "xo";
1558
1559 power-domains = <&rpm
1560 <&rpm
1561 power-domain-names =
1562
1563 memory-region = <&pil
1564
1565 qcom,qmp = <&aoss_qmp
1566
1567 qcom,smem-states = <&
1568 qcom,smem-state-names
1569
1570 status = "disabled";
1571
1572 glink-edge {
1573 interrupts-ex
1574
1575
1576 mboxes = <&ip
1577
1578
1579 label = "cdsp
1580 qcom,remote-p
1581
1582 fastrpc {
1583 compa
1584 qcom,
1585 label
1586 qcom,
1587 #addr
1588 #size
1589
1590 compu
1591
1592
1593
1594 };
1595
1596 compu
1597
1598
1599
1600 };
1601
1602 compu
1603
1604
1605
1606 };
1607
1608 compu
1609
1610
1611
1612 };
1613
1614 compu
1615
1616
1617
1618 };
1619
1620 compu
1621
1622
1623
1624 };
1625
1626 compu
1627
1628
1629
1630 };
1631
1632 compu
1633
1634
1635
1636 };
1637
1638 /* no
1639 };
1640 };
1641 };
1642
1643 sdhc_2: mmc@8804000 {
1644 compatible = "qcom,sm
1645 reg = <0 0x08804000 0
1646
1647 interrupts = <GIC_SPI
1648 <GIC_SPI
1649 interrupt-names = "hc
1650 iommus = <&apps_smmu
1651
1652 clocks = <&gcc GCC_SD
1653 <&gcc GCC_SD
1654 <&rpmhcc RPM
1655 clock-names = "iface"
1656 resets = <&gcc GCC_SD
1657 interconnects = <&agg
1658 <&gem
1659 interconnect-names =
1660
1661 pinctrl-0 = <&sdc2_on
1662 pinctrl-1 = <&sdc2_of
1663 pinctrl-names = "defa
1664
1665 qcom,dll-config = <0x
1666 qcom,ddr-config = <0x
1667 power-domains = <&rpm
1668 operating-points-v2 =
1669 bus-width = <4>;
1670
1671 status = "disabled";
1672
1673 sdhc2_opp_table: opp-
1674 compatible =
1675
1676 opp-100000000
1677 opp-h
1678 requi
1679 opp-p
1680 opp-a
1681 };
1682
1683 opp-202000000
1684 opp-h
1685 requi
1686 opp-p
1687 opp-a
1688 };
1689 };
1690 };
1691
1692 usb_1_hsphy: phy@88e3000 {
1693 compatible = "qcom,sm
1694 reg = <0 0x088e3000 0
1695 status = "disabled";
1696 #phy-cells = <0>;
1697
1698 clocks = <&xo_board>,
1699 clock-names = "cfg_ah
1700
1701 resets = <&gcc GCC_QU
1702 };
1703
1704 usb_1_qmpphy: phy@88e8000 {
1705 compatible = "qcom,sm
1706 reg = <0 0x088e8000 0
1707
1708 clocks = <&gcc GCC_US
1709 <&gcc GCC_US
1710 <&gcc GCC_US
1711 <&gcc GCC_US
1712 clock-names = "aux",
1713
1714 power-domains = <&gcc
1715
1716 resets = <&gcc GCC_US
1717 <&gcc GCC_US
1718 reset-names = "phy",
1719
1720 orientation-switch;
1721
1722 #clock-cells = <1>;
1723 #phy-cells = <1>;
1724
1725 status = "disabled";
1726
1727 ports {
1728 #address-cell
1729 #size-cells =
1730
1731 port@0 {
1732 reg =
1733
1734 usb_1
1735 };
1736 };
1737
1738 port@1 {
1739 reg =
1740
1741 usb_1
1742
1743 };
1744 };
1745
1746 port@2 {
1747 reg =
1748
1749 usb_1
1750 };
1751 };
1752 };
1753 };
1754
1755 dc_noc: interconnect@9160000
1756 compatible = "qcom,sm
1757 reg = <0 0x09160000 0
1758 #interconnect-cells =
1759 qcom,bcm-voters = <&a
1760 };
1761
1762 system-cache-controller@92000
1763 compatible = "qcom,sm
1764 reg = <0 0x09200000 0
1765 reg-names = "llcc0_ba
1766 };
1767
1768 gem_noc: interconnect@9680000
1769 compatible = "qcom,sm
1770 reg = <0 0x09680000 0
1771 #interconnect-cells =
1772 qcom,bcm-voters = <&a
1773 };
1774
1775 npu_noc: interconnect@9990000
1776 compatible = "qcom,sm
1777 reg = <0 0x09990000 0
1778 #interconnect-cells =
1779 qcom,bcm-voters = <&a
1780 };
1781
1782 pmu@90b6300 {
1783 compatible = "qcom,sm
1784 reg = <0x0 0x090b6300
1785 interrupts = <GIC_SPI
1786
1787 operating-points-v2 =
1788 interconnects = <&clk
1789 &clk
1790
1791 llcc_bwmon_opp_table:
1792 compatible =
1793
1794 opp-0 {
1795 opp-p
1796 };
1797
1798 opp-1 {
1799 opp-p
1800 };
1801
1802 opp-2 {
1803 opp-p
1804 };
1805
1806 opp-3 {
1807 opp-p
1808 };
1809
1810 opp-4 {
1811 opp-p
1812 };
1813
1814 opp-5 {
1815 opp-p
1816 };
1817
1818 };
1819 };
1820
1821 pmu@90cd000 {
1822 compatible = "qcom,sm
1823 reg = <0x0 0x090cd000
1824 interrupts = <GIC_SPI
1825
1826 operating-points-v2 =
1827 interconnects = <&gem
1828 &clk
1829
1830 cpu_bwmon_opp_table:
1831 compatible =
1832
1833 opp-0 {
1834 opp-p
1835 };
1836
1837 opp-1 {
1838 opp-p
1839 };
1840
1841 opp-2 {
1842 opp-p
1843 };
1844
1845 opp-3 {
1846 opp-p
1847 };
1848
1849 opp-4 {
1850 opp-p
1851 };
1852
1853 opp-5 {
1854 opp-p
1855 };
1856
1857 opp-6 {
1858 opp-p
1859 };
1860
1861 opp-7 {
1862 opp-p
1863 };
1864
1865 opp-8 {
1866 opp-p
1867 };
1868
1869 opp-9 {
1870 opp-p
1871 };
1872
1873 opp-10 {
1874 opp-p
1875 };
1876 };
1877 };
1878
1879 usb_1: usb@a6f8800 {
1880 compatible = "qcom,sm
1881 reg = <0 0x0a6f8800 0
1882 status = "disabled";
1883 #address-cells = <2>;
1884 #size-cells = <2>;
1885 ranges;
1886
1887 clocks = <&gcc GCC_CF
1888 <&gcc GCC_US
1889 <&gcc GCC_AG
1890 <&gcc GCC_US
1891 <&gcc GCC_US
1892 clock-names = "cfg_no
1893 "core",
1894 "iface"
1895 "sleep"
1896 "mock_u
1897
1898 interrupts-extended =
1899
1900
1901
1902
1903 interrupt-names = "pw
1904 "hs
1905 "dp
1906 "dm
1907 "ss
1908
1909 power-domains = <&gcc
1910
1911 resets = <&gcc GCC_US
1912
1913 interconnects = <&agg
1914 <&gem
1915 interconnect-names =
1916
1917 usb_1_dwc3: usb@a6000
1918 compatible =
1919 reg = <0 0x0a
1920 interrupts =
1921 iommus = <&ap
1922 snps,dis_u2_s
1923 snps,dis_enbl
1924 snps,has-lpm-
1925 snps,hird-thr
1926 snps,parkmode
1927 phys = <&usb_
1928 phy-names = "
1929 usb-role-swit
1930
1931 ports {
1932 #addr
1933 #size
1934
1935 port@
1936
1937
1938
1939
1940 };
1941
1942 port@
1943
1944
1945
1946
1947
1948 };
1949 };
1950 };
1951 };
1952
1953 cci0: cci@ac4a000 {
1954 compatible = "qcom,sm
1955 reg = <0 0x0ac4a000 0
1956 interrupts = <GIC_SPI
1957 power-domains = <&cam
1958
1959 clocks = <&camcc CAMC
1960 <&camcc CAMC
1961 <&camcc CAMC
1962 <&camcc CAMC
1963 <&camcc CAMC
1964 <&camcc CAMC
1965 clock-names = "camnoc
1966 "soc_ah
1967 "slow_a
1968 "cpas_a
1969 "cci",
1970 "cci_sr
1971
1972 assigned-clocks = <&c
1973 <&c
1974 assigned-clock-rates
1975
1976 pinctrl-0 = <&cci0_de
1977 pinctrl-1 = <&cci0_sl
1978 pinctrl-names = "defa
1979
1980 #address-cells = <1>;
1981 #size-cells = <0>;
1982
1983 status = "disabled";
1984
1985 cci0_i2c0: i2c-bus@0
1986 reg = <0>;
1987 clock-frequen
1988 #address-cell
1989 #size-cells =
1990 };
1991
1992 cci0_i2c1: i2c-bus@1
1993 reg = <1>;
1994 clock-frequen
1995 #address-cell
1996 #size-cells =
1997 };
1998 };
1999
2000 cci1: cci@ac4b000 {
2001 compatible = "qcom,sm
2002 reg = <0 0x0ac4b000 0
2003 interrupts = <GIC_SPI
2004 power-domains = <&cam
2005
2006 clocks = <&camcc CAMC
2007 <&camcc CAMC
2008 <&camcc CAMC
2009 <&camcc CAMC
2010 <&camcc CAMC
2011 <&camcc CAMC
2012 clock-names = "camnoc
2013 "soc_ah
2014 "slow_a
2015 "cpas_a
2016 "cci",
2017 "cci_sr
2018
2019 assigned-clocks = <&c
2020 <&c
2021 assigned-clock-rates
2022
2023 pinctrl-0 = <&cci2_de
2024 pinctrl-1 = <&cci2_sl
2025 pinctrl-names = "defa
2026
2027 #address-cells = <1>;
2028 #size-cells = <0>;
2029
2030 status = "disabled";
2031
2032 cci1_i2c0: i2c-bus@0
2033 reg = <0>;
2034 clock-frequen
2035 #address-cell
2036 #size-cells =
2037 };
2038
2039 /* SM6350 seems to ha
2040 };
2041
2042 camcc: clock-controller@ad000
2043 compatible = "qcom,sm
2044 reg = <0 0x0ad00000 0
2045 clocks = <&rpmhcc RPM
2046 #clock-cells = <1>;
2047 #reset-cells = <1>;
2048 #power-domain-cells =
2049 };
2050
2051 mdss: display-subsystem@ae000
2052 compatible = "qcom,sm
2053 reg = <0 0x0ae00000 0
2054 reg-names = "mdss";
2055
2056 interrupts = <GIC_SPI
2057 interrupt-controller;
2058 #interrupt-cells = <1
2059
2060 interconnects = <&mms
2061 &clk
2062 <&gem
2063 &con
2064 interconnect-names =
2065
2066
2067 clocks = <&gcc GCC_DI
2068 <&gcc GCC_DI
2069 <&dispcc DIS
2070 clock-names = "iface"
2071 "bus",
2072 "core";
2073
2074 power-domains = <&dis
2075 iommus = <&apps_smmu
2076
2077 #address-cells = <2>;
2078 #size-cells = <2>;
2079 ranges;
2080
2081 status = "disabled";
2082
2083 mdss_mdp: display-con
2084 compatible =
2085 reg = <0 0x0a
2086 <0 0x0a
2087 reg-names = "
2088
2089 interrupt-par
2090 interrupts =
2091
2092 clocks = <&gc
2093 <&di
2094 <&di
2095 <&di
2096 <&di
2097 <&di
2098 clock-names =
2099
2100
2101
2102
2103
2104
2105 assigned-cloc
2106 assigned-cloc
2107
2108 operating-poi
2109 power-domains
2110
2111 ports {
2112 #addr
2113 #size
2114
2115 port@
2116
2117
2118
2119
2120
2121 };
2122
2123 port@
2124
2125
2126
2127
2128
2129 };
2130 };
2131
2132 mdp_opp_table
2133 compa
2134
2135 opp-1
2136
2137
2138 };
2139
2140 opp-2
2141
2142
2143 };
2144
2145 opp-3
2146
2147
2148 };
2149
2150 opp-3
2151
2152
2153 };
2154
2155 opp-4
2156
2157
2158 };
2159
2160 opp-5
2161
2162
2163 };
2164 };
2165 };
2166
2167 mdss_dp: displayport-
2168 compatible =
2169 reg = <0 0xae
2170 <0 0xae
2171 <0 0xae
2172 <0 0xae
2173 <0 0xae
2174 interrupt-par
2175 interrupts =
2176 clocks = <&di
2177 <&di
2178 <&di
2179 <&di
2180 <&di
2181 clock-names =
2182
2183
2184
2185
2186
2187 assigned-cloc
2188
2189 assigned-cloc
2190
2191
2192 phys = <&usb_
2193 phy-names = "
2194
2195 #sound-dai-ce
2196
2197 operating-poi
2198 power-domains
2199
2200 status = "dis
2201
2202 ports {
2203 #addr
2204 #size
2205
2206 port@
2207
2208
2209
2210
2211
2212 };
2213
2214 port@
2215
2216
2217
2218
2219 };
2220 };
2221
2222 dp_opp_table:
2223 compa
2224
2225 opp-1
2226
2227
2228 };
2229
2230 opp-2
2231
2232
2233 };
2234
2235 opp-5
2236
2237
2238 };
2239
2240 opp-8
2241
2242
2243 };
2244 };
2245 };
2246
2247 mdss_dsi0: dsi@ae9400
2248 compatible =
2249 reg = <0 0x0a
2250 reg-names = "
2251
2252 interrupt-par
2253 interrupts =
2254
2255 clocks = <&di
2256 <&di
2257 <&di
2258 <&di
2259 <&di
2260 <&gc
2261 clock-names =
2262
2263
2264
2265
2266
2267
2268 assigned-cloc
2269
2270 assigned-cloc
2271
2272 operating-poi
2273 power-domains
2274
2275 phys = <&mdss
2276 phy-names = "
2277
2278 #address-cell
2279 #size-cells =
2280
2281 status = "dis
2282
2283 ports {
2284 #addr
2285 #size
2286
2287 port@
2288
2289
2290
2291
2292
2293 };
2294
2295 port@
2296
2297
2298
2299
2300 };
2301 };
2302
2303 mdss_dsi_opp_
2304 compa
2305
2306 opp-1
2307
2308
2309 };
2310
2311 opp-3
2312
2313
2314 };
2315
2316 opp-3
2317
2318
2319 };
2320 };
2321 };
2322
2323 mdss_dsi0_phy: phy@ae
2324 compatible =
2325 reg = <0 0x0a
2326 <0 0x0a
2327 <0 0x0a
2328 reg-names = "
2329 "
2330 "
2331
2332 #clock-cells
2333 #phy-cells =
2334
2335 clocks = <&di
2336 <&rp
2337 clock-names =
2338
2339 status = "dis
2340 };
2341 };
2342
2343 dispcc: clock-controller@af00
2344 compatible = "qcom,sm
2345 reg = <0 0x0af00000 0
2346 clocks = <&rpmhcc RPM
2347 <&gcc GCC_DI
2348 <&mdss_dsi0_
2349 <&mdss_dsi0_
2350 <&usb_1_qmpp
2351 <&usb_1_qmpp
2352 clock-names = "bi_tcx
2353 "gcc_di
2354 "dsi0_p
2355 "dsi0_p
2356 "dp_phy
2357 "dp_phy
2358 #clock-cells = <1>;
2359 #reset-cells = <1>;
2360 #power-domain-cells =
2361 };
2362
2363 pdc: interrupt-controller@b22
2364 compatible = "qcom,sm
2365 reg = <0 0x0b220000 0
2366 qcom,pdc-ranges = <0
2367 <12
2368 #interrupt-cells = <2
2369 interrupt-parent = <&
2370 interrupt-controller;
2371 };
2372
2373 tsens0: thermal-sensor@c26300
2374 compatible = "qcom,sm
2375 reg = <0 0x0c263000 0
2376 <0 0x0c222000 0
2377 #qcom,sensors = <16>;
2378 interrupts-extended =
2379 <&pdc 28
2380 interrupt-names = "up
2381 #thermal-sensor-cells
2382 };
2383
2384 tsens1: thermal-sensor@c26500
2385 compatible = "qcom,sm
2386 reg = <0 0x0c265000 0
2387 <0 0x0c223000 0
2388 #qcom,sensors = <16>;
2389 interrupts-extended =
2390 <&pdc 29
2391 interrupt-names = "up
2392 #thermal-sensor-cells
2393 };
2394
2395 aoss_qmp: power-management@c3
2396 compatible = "qcom,sm
2397 reg = <0 0x0c300000 0
2398 interrupts-extended =
2399
2400 mboxes = <&ipcc IPCC_
2401
2402 #clock-cells = <0>;
2403 };
2404
2405 spmi_bus: spmi@c440000 {
2406 compatible = "qcom,sp
2407 reg = <0 0x0c440000 0
2408 <0 0x0c600000 0
2409 <0 0x0e600000 0
2410 <0 0x0e700000 0
2411 <0 0x0c40a000 0
2412 reg-names = "core", "
2413 interrupt-names = "pe
2414 interrupts-extended =
2415 qcom,ee = <0>;
2416 qcom,channel = <0>;
2417 #address-cells = <2>;
2418 #size-cells = <0>;
2419 interrupt-controller;
2420 #interrupt-cells = <4
2421 };
2422
2423 tlmm: pinctrl@f100000 {
2424 compatible = "qcom,sm
2425 reg = <0 0x0f100000 0
2426 interrupts = <GIC_SPI
2427 <GIC_
2428 <GIC_
2429 <GIC_
2430 <GIC_
2431 <GIC_
2432 <GIC_
2433 <GIC_
2434 <GIC_
2435 gpio-controller;
2436 #gpio-cells = <2>;
2437 interrupt-controller;
2438 #interrupt-cells = <2
2439 gpio-ranges = <&tlmm
2440 wakeup-parent = <&pdc
2441
2442 cci0_default: cci0-de
2443 pins = "gpio3
2444 function = "c
2445 drive-strengt
2446 bias-pull-up;
2447 };
2448
2449 cci0_sleep: cci0-slee
2450 pins = "gpio3
2451 function = "c
2452 drive-strengt
2453 bias-pull-dow
2454 };
2455
2456 cci1_default: cci1-de
2457 pins = "gpio4
2458 function = "c
2459 drive-strengt
2460 bias-pull-up;
2461 };
2462
2463 cci1_sleep: cci1-slee
2464 pins = "gpio4
2465 function = "c
2466 drive-strengt
2467 bias-pull-dow
2468 };
2469
2470 cci2_default: cci2-de
2471 pins = "gpio4
2472 function = "c
2473 drive-strengt
2474 bias-pull-up;
2475 };
2476
2477 cci2_sleep: cci2-slee
2478 pins = "gpio4
2479 function = "c
2480 drive-strengt
2481 bias-pull-dow
2482 };
2483
2484 sdc2_off_state: sdc2-
2485 clk-pins {
2486 pins
2487 drive
2488 bias-
2489 };
2490
2491 cmd-pins {
2492 pins
2493 drive
2494 bias-
2495 };
2496
2497 data-pins {
2498 pins
2499 drive
2500 bias-
2501 };
2502 };
2503
2504 sdc2_on_state: sdc2-o
2505 clk-pins {
2506 pins
2507 drive
2508 bias-
2509 };
2510
2511 cmd-pins {
2512 pins
2513 drive
2514 bias-
2515 };
2516
2517 data-pins {
2518 pins
2519 drive
2520 bias-
2521 };
2522 };
2523
2524 qup_uart9_default: qu
2525 pins = "gpio2
2526 function = "q
2527 drive-strengt
2528 bias-disable;
2529 };
2530
2531 qup_i2c0_default: qup
2532 pins = "gpio0
2533 function = "q
2534 drive-strengt
2535 bias-pull-up;
2536 };
2537
2538 qup_i2c2_default: qup
2539 pins = "gpio4
2540 function = "q
2541 drive-strengt
2542 bias-pull-up;
2543 };
2544
2545 qup_i2c6_default: qup
2546 pins = "gpio1
2547 function = "q
2548 drive-strengt
2549 bias-pull-up;
2550 };
2551
2552 qup_i2c7_default: qup
2553 pins = "gpio2
2554 function = "q
2555 drive-strengt
2556 bias-pull-up;
2557 };
2558
2559 qup_i2c8_default: qup
2560 pins = "gpio1
2561 function = "q
2562 drive-strengt
2563 bias-pull-up;
2564 };
2565
2566 qup_i2c10_default: qu
2567 pins = "gpio4
2568 function = "q
2569 drive-strengt
2570 bias-pull-up;
2571 };
2572
2573 qup_uart1_cts: qup-ua
2574 pins = "gpio6
2575 function = "q
2576 drive-strengt
2577 bias-disable;
2578 };
2579
2580 qup_uart1_rts: qup-ua
2581 pins = "gpio6
2582 function = "q
2583 drive-strengt
2584 bias-pull-dow
2585 };
2586
2587 qup_uart1_rx: qup-uar
2588 pins = "gpio6
2589 function = "q
2590 drive-strengt
2591 bias-disable;
2592 };
2593
2594 qup_uart1_tx: qup-uar
2595 pins = "gpio6
2596 function = "q
2597 drive-strengt
2598 bias-pull-up;
2599 };
2600 };
2601
2602 apps_smmu: iommu@15000000 {
2603 compatible = "qcom,sm
2604 reg = <0 0x15000000 0
2605 #iommu-cells = <2>;
2606 #global-interrupts =
2607 interrupts = <GIC_SPI
2608 <GIC_SPI
2609 <GIC_SPI
2610 <GIC_SPI
2611 <GIC_SPI
2612 <GIC_SPI
2613 <GIC_SPI
2614 <GIC_SPI
2615 <GIC_SPI
2616 <GIC_SPI
2617 <GIC_SPI
2618 <GIC_SPI
2619 <GIC_SPI
2620 <GIC_SPI
2621 <GIC_SPI
2622 <GIC_SPI
2623 <GIC_SPI
2624 <GIC_SPI
2625 <GIC_SPI
2626 <GIC_SPI
2627 <GIC_SPI
2628 <GIC_SPI
2629 <GIC_SPI
2630 <GIC_SPI
2631 <GIC_SPI
2632 <GIC_SPI
2633 <GIC_SPI
2634 <GIC_SPI
2635 <GIC_SPI
2636 <GIC_SPI
2637 <GIC_SPI
2638 <GIC_SPI
2639 <GIC_SPI
2640 <GIC_SPI
2641 <GIC_SPI
2642 <GIC_SPI
2643 <GIC_SPI
2644 <GIC_SPI
2645 <GIC_SPI
2646 <GIC_SPI
2647 <GIC_SPI
2648 <GIC_SPI
2649 <GIC_SPI
2650 <GIC_SPI
2651 <GIC_SPI
2652 <GIC_SPI
2653 <GIC_SPI
2654 <GIC_SPI
2655 <GIC_SPI
2656 <GIC_SPI
2657 <GIC_SPI
2658 <GIC_SPI
2659 <GIC_SPI
2660 <GIC_SPI
2661 <GIC_SPI
2662 <GIC_SPI
2663 <GIC_SPI
2664 <GIC_SPI
2665 <GIC_SPI
2666 <GIC_SPI
2667 <GIC_SPI
2668 <GIC_SPI
2669 <GIC_SPI
2670 <GIC_SPI
2671 <GIC_SPI
2672 <GIC_SPI
2673 <GIC_SPI
2674 <GIC_SPI
2675 <GIC_SPI
2676 <GIC_SPI
2677 <GIC_SPI
2678 <GIC_SPI
2679 <GIC_SPI
2680 <GIC_SPI
2681 <GIC_SPI
2682 <GIC_SPI
2683 <GIC_SPI
2684 <GIC_SPI
2685 <GIC_SPI
2686 <GIC_SPI
2687 <GIC_SPI
2688 };
2689
2690 intc: interrupt-controller@17
2691 compatible = "arm,gic
2692 #interrupt-cells = <3
2693 interrupt-controller;
2694 reg = <0x0 0x17a00000
2695 <0x0 0x17a60000
2696 interrupts = <GIC_PPI
2697 };
2698
2699 watchdog@17c10000 {
2700 compatible = "qcom,ap
2701 reg = <0 0x17c10000 0
2702 clocks = <&sleep_clk>
2703 interrupts = <GIC_SPI
2704 };
2705
2706 timer@17c20000 {
2707 compatible = "arm,arm
2708 reg = <0x0 0x17c20000
2709 clock-frequency = <19
2710 #address-cells = <1>;
2711 #size-cells = <1>;
2712 ranges = <0 0 0 0x200
2713
2714 frame@17c21000 {
2715 frame-number
2716 interrupts =
2717
2718 reg = <0x17c2
2719 <0x17c2
2720 };
2721
2722 frame@17c23000 {
2723 frame-number
2724 interrupts =
2725 reg = <0x17c2
2726 status = "dis
2727 };
2728
2729 frame@17c25000 {
2730 frame-number
2731 interrupts =
2732 reg = <0x17c2
2733 status = "dis
2734 };
2735
2736 frame@17c27000 {
2737 frame-number
2738 interrupts =
2739 reg = <0x17c2
2740 status = "dis
2741 };
2742
2743 frame@17c29000 {
2744 frame-number
2745 interrupts =
2746 reg = <0x17c2
2747 status = "dis
2748 };
2749
2750 frame@17c2b000 {
2751 frame-number
2752 interrupts =
2753 reg = <0x17c2
2754 status = "dis
2755 };
2756
2757 frame@17c2d000 {
2758 frame-number
2759 interrupts =
2760 reg = <0x17c2
2761 status = "dis
2762 };
2763 };
2764
2765 apps_rsc: rsc@18200000 {
2766 compatible = "qcom,rp
2767 label = "apps_rsc";
2768 reg = <0x0 0x18200000
2769 <0x0 0x182100
2770 <0x0 0x182200
2771 reg-names = "drv-0",
2772 interrupts = <GIC_SPI
2773 <GIC_SPI
2774 <GIC_SPI
2775 qcom,tcs-offset = <0x
2776 qcom,drv-id = <2>;
2777 qcom,tcs-config = <AC
2778 <WA
2779 power-domains = <&CLU
2780
2781 rpmhcc: clock-control
2782 compatible =
2783 #clock-cells
2784 clock-names =
2785 clocks = <&xo
2786 };
2787
2788 rpmhpd: power-control
2789 compatible =
2790 #power-domain
2791 operating-poi
2792
2793 rpmhpd_opp_ta
2794 compa
2795
2796 rpmhp
2797
2798 };
2799
2800 rpmhp
2801
2802 };
2803
2804 rpmhp
2805
2806 };
2807
2808 rpmhp
2809
2810 };
2811
2812 rpmhp
2813
2814 };
2815
2816 rpmhp
2817
2818 };
2819
2820 rpmhp
2821
2822 };
2823
2824 rpmhp
2825
2826 };
2827
2828 rpmhp
2829
2830 };
2831
2832 rpmhp
2833
2834 };
2835 };
2836 };
2837
2838 apps_bcm_voter: bcm-v
2839 compatible =
2840 };
2841 };
2842
2843 osm_l3: interconnect@18321000
2844 compatible = "qcom,sm
2845 reg = <0x0 0x18321000
2846
2847 clocks = <&rpmhcc RPM
2848 clock-names = "xo", "
2849
2850 #interconnect-cells =
2851 };
2852
2853 cpufreq_hw: cpufreq@18323000
2854 compatible = "qcom,sm
2855 reg = <0 0x18323000 0
2856 reg-names = "freq-dom
2857 clocks = <&rpmhcc RPM
2858 clock-names = "xo", "
2859
2860 #freq-domain-cells =
2861 #clock-cells = <1>;
2862 };
2863
2864 wifi: wifi@18800000 {
2865 compatible = "qcom,wc
2866 reg = <0 0x18800000 0
2867 reg-names = "membase"
2868 memory-region = <&wla
2869 interrupts = <GIC_SPI
2870 <GIC_SPI
2871 <GIC_SPI
2872 <GIC_SPI
2873 <GIC_SPI
2874 <GIC_SPI
2875 <GIC_SPI
2876 <GIC_SPI
2877 <GIC_SPI
2878 <GIC_SPI
2879 <GIC_SPI
2880 <GIC_SPI
2881 iommus = <&apps_smmu
2882 qcom,msa-fixed-perm;
2883 status = "disabled";
2884 };
2885 };
2886
2887 thermal-zones {
2888 aoss0-thermal {
2889 thermal-sensors = <&t
2890
2891 trips {
2892 aoss0-crit {
2893 tempe
2894 hyste
2895 type
2896 };
2897 };
2898 };
2899
2900 aoss1-thermal {
2901 thermal-sensors = <&t
2902
2903 trips {
2904 aoss1-crit {
2905 tempe
2906 hyste
2907 type
2908 };
2909 };
2910 };
2911
2912 audio-thermal {
2913 thermal-sensors = <&t
2914
2915 trips {
2916 audio-crit {
2917 tempe
2918 hyste
2919 type
2920 };
2921 };
2922 };
2923
2924 camera-thermal {
2925 thermal-sensors = <&t
2926
2927 trips {
2928 camera-crit {
2929 tempe
2930 hyste
2931 type
2932 };
2933 };
2934 };
2935
2936 cpu0-thermal {
2937 thermal-sensors = <&t
2938
2939 trips {
2940 cpu0_alert0:
2941 tempe
2942 hyste
2943 type
2944 };
2945
2946 cpu0-crit {
2947 tempe
2948 hyste
2949 type
2950 };
2951 };
2952
2953 cooling-maps {
2954 map0 {
2955 trip
2956 cooli
2957 };
2958 };
2959 };
2960
2961 cpu1-thermal {
2962 thermal-sensors = <&t
2963
2964 trips {
2965 cpu1_alert0:
2966 tempe
2967 hyste
2968 type
2969 };
2970
2971 cpu1-crit {
2972 tempe
2973 hyste
2974 type
2975 };
2976 };
2977
2978 cooling-maps {
2979 map0 {
2980 trip
2981 cooli
2982 };
2983 };
2984 };
2985
2986 cpu2-thermal {
2987 thermal-sensors = <&t
2988
2989 trips {
2990 cpu2_alert0:
2991 tempe
2992 hyste
2993 type
2994 };
2995
2996 cpu2-crit {
2997 tempe
2998 hyste
2999 type
3000 };
3001 };
3002
3003 cooling-maps {
3004 map0 {
3005 trip
3006 cooli
3007 };
3008 };
3009 };
3010
3011 cpu3-thermal {
3012 thermal-sensors = <&t
3013
3014 trips {
3015 cpu3_alert0:
3016 tempe
3017 hyste
3018 type
3019 };
3020
3021 cpu3-crit {
3022 tempe
3023 hyste
3024 type
3025 };
3026 };
3027
3028 cooling-maps {
3029 map0 {
3030 trip
3031 cooli
3032 };
3033 };
3034 };
3035
3036 cpu4-thermal {
3037 thermal-sensors = <&t
3038
3039 trips {
3040 cpu4_alert0:
3041 tempe
3042 hyste
3043 type
3044 };
3045
3046 cpu4-crit {
3047 tempe
3048 hyste
3049 type
3050 };
3051 };
3052
3053 cooling-maps {
3054 map0 {
3055 trip
3056 cooli
3057 };
3058 };
3059 };
3060
3061 cpu5-thermal {
3062 thermal-sensors = <&t
3063
3064 trips {
3065 cpu5_alert0:
3066 tempe
3067 hyste
3068 type
3069 };
3070
3071 cpu5-crit {
3072 tempe
3073 hyste
3074 type
3075 };
3076 };
3077
3078 cooling-maps {
3079 map0 {
3080 trip
3081 cooli
3082 };
3083 };
3084 };
3085
3086 cpu6-left-thermal {
3087 thermal-sensors = <&t
3088
3089 trips {
3090 cpu6_left_ale
3091 tempe
3092 hyste
3093 type
3094 };
3095
3096 cpu6-left-cri
3097 tempe
3098 hyste
3099 type
3100 };
3101 };
3102
3103 cooling-maps {
3104 map0 {
3105 trip
3106 cooli
3107 };
3108 };
3109 };
3110
3111 cpu6-right-thermal {
3112 thermal-sensors = <&t
3113
3114 trips {
3115 cpu6_right_al
3116 tempe
3117 hyste
3118 type
3119 };
3120
3121 cpu6-right-cr
3122 tempe
3123 hyste
3124 type
3125 };
3126 };
3127
3128 cooling-maps {
3129 map0 {
3130 trip
3131 cooli
3132 };
3133 };
3134 };
3135
3136 cpu7-left-thermal {
3137 thermal-sensors = <&t
3138
3139 trips {
3140 cpu7_left_ale
3141 tempe
3142 hyste
3143 type
3144 };
3145
3146 cpu7-left-cri
3147 tempe
3148 hyste
3149 type
3150 };
3151 };
3152
3153 cooling-maps {
3154 map0 {
3155 trip
3156 cooli
3157 };
3158 };
3159 };
3160
3161 cpu7-right-thermal {
3162 thermal-sensors = <&t
3163
3164 trips {
3165 cpu7_right_al
3166 tempe
3167 hyste
3168 type
3169 };
3170
3171 cpu7-right-cr
3172 tempe
3173 hyste
3174 type
3175 };
3176 };
3177
3178 cooling-maps {
3179 map0 {
3180 trip
3181 cooli
3182 };
3183 };
3184 };
3185
3186 cpuss0-thermal {
3187 thermal-sensors = <&t
3188
3189 trips {
3190 cpuss0-crit {
3191 tempe
3192 hyste
3193 type
3194 };
3195 };
3196 };
3197
3198 cpuss1-thermal {
3199 thermal-sensors = <&t
3200
3201 trips {
3202 cpuss1-crit {
3203 tempe
3204 hyste
3205 type
3206 };
3207 };
3208 };
3209
3210 cwlan-thermal {
3211 thermal-sensors = <&t
3212
3213 trips {
3214 cwlan-crit {
3215 tempe
3216 hyste
3217 type
3218 };
3219 };
3220 };
3221
3222 ddr-thermal {
3223 thermal-sensors = <&t
3224
3225 trips {
3226 ddr-crit {
3227 tempe
3228 hyste
3229 type
3230 };
3231 };
3232 };
3233
3234 gpuss0-thermal {
3235 polling-delay-passive
3236
3237 thermal-sensors = <&t
3238
3239 trips {
3240 gpuss0_alert0
3241 tempe
3242 hyste
3243 type
3244 };
3245
3246 gpuss0-crit {
3247 tempe
3248 hyste
3249 type
3250 };
3251 };
3252
3253 cooling-maps {
3254 map0 {
3255 trip
3256 cooli
3257 };
3258 };
3259 };
3260
3261 gpuss1-thermal {
3262 polling-delay-passive
3263
3264 thermal-sensors = <&t
3265
3266 trips {
3267 gpuss1_alert0
3268 tempe
3269 hyste
3270 type
3271 };
3272
3273 gpuss1-crit {
3274 tempe
3275 hyste
3276 type
3277 };
3278 };
3279
3280 cooling-maps {
3281 map0 {
3282 trip
3283 cooli
3284 };
3285 };
3286 };
3287
3288 modem-core0-thermal {
3289 thermal-sensors = <&t
3290
3291 trips {
3292 modem-core0-c
3293 tempe
3294 hyste
3295 type
3296 };
3297 };
3298 };
3299
3300 modem-core1-thermal {
3301 thermal-sensors = <&t
3302
3303 trips {
3304 modem-core1-c
3305 tempe
3306 hyste
3307 type
3308 };
3309 };
3310 };
3311
3312 modem-scl-thermal {
3313 thermal-sensors = <&t
3314
3315 trips {
3316 modem-scl-cri
3317 tempe
3318 hyste
3319 type
3320 };
3321 };
3322 };
3323
3324 modem-vec-thermal {
3325 thermal-sensors = <&t
3326
3327 trips {
3328 modem-vec-cri
3329 tempe
3330 hyste
3331 type
3332 };
3333 };
3334 };
3335
3336 npu-thermal {
3337 thermal-sensors = <&t
3338
3339 trips {
3340 npu-crit {
3341 tempe
3342 hyste
3343 type
3344 };
3345 };
3346 };
3347
3348 q6-hvx-thermal {
3349 thermal-sensors = <&t
3350
3351 trips {
3352 q6-hvx-crit {
3353 tempe
3354 hyste
3355 type
3356 };
3357 };
3358 };
3359
3360 video-thermal {
3361 thermal-sensors = <&t
3362
3363 trips {
3364 video-crit {
3365 tempe
3366 hyste
3367 type
3368 };
3369 };
3370 };
3371 };
3372
3373 timer {
3374 compatible = "arm,armv8-timer
3375 clock-frequency = <19200000>;
3376 interrupts = <GIC_PPI 1 (GIC_
3377 <GIC_PPI 2 (GIC_
3378 <GIC_PPI 3 (GIC_
3379 <GIC_PPI 0 (GIC_
3380 };
3381 };
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