1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dy 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
4 * Copyright (c) 2022, Luca Weiss <luca.weiss@f <<
5 */ 4 */
6 5
7 #include <dt-bindings/clock/qcom,dispcc-sm6350 <<
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h> 6 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350. <<
10 #include <dt-bindings/clock/qcom,rpmh.h> 7 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc. <<
12 #include <dt-bindings/dma/qcom-gpi.h> <<
13 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h> <<
15 #include <dt-bindings/interconnect/qcom,osm-l3 <<
16 #include <dt-bindings/interconnect/qcom,sm6350 <<
17 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h> 10 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
20 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h> <<
23 13
24 / { 14 / {
25 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
26 #address-cells = <2>; 16 #address-cells = <2>;
27 #size-cells = <2>; 17 #size-cells = <2>;
28 18
29 clocks { 19 clocks {
30 xo_board: xo-board { 20 xo_board: xo-board {
31 compatible = "fixed-cl 21 compatible = "fixed-clock";
32 #clock-cells = <0>; 22 #clock-cells = <0>;
33 clock-frequency = <768 23 clock-frequency = <76800000>;
34 clock-output-names = " 24 clock-output-names = "xo_board";
35 }; 25 };
36 26
37 sleep_clk: sleep-clk { 27 sleep_clk: sleep-clk {
38 compatible = "fixed-cl 28 compatible = "fixed-clock";
39 clock-frequency = <327 29 clock-frequency = <32764>;
40 #clock-cells = <0>; 30 #clock-cells = <0>;
41 }; 31 };
42 }; 32 };
43 33
44 cpus { 34 cpus {
45 #address-cells = <2>; 35 #address-cells = <2>;
46 #size-cells = <0>; 36 #size-cells = <0>;
47 37
48 CPU0: cpu@0 { 38 CPU0: cpu@0 {
49 device_type = "cpu"; 39 device_type = "cpu";
50 compatible = "qcom,kry 40 compatible = "qcom,kryo560";
51 reg = <0x0 0x0>; 41 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw <<
53 enable-method = "psci" 42 enable-method = "psci";
54 capacity-dmips-mhz = < 43 capacity-dmips-mhz = <1024>;
55 dynamic-power-coeffici 44 dynamic-power-coefficient = <100>;
56 next-level-cache = <&L 45 next-level-cache = <&L2_0>;
57 qcom,freq-domain = <&c 46 qcom,freq-domain = <&cpufreq_hw 0>;
58 operating-points-v2 = <<
59 interconnects = <&gem_ <<
60 &clk_ <<
61 <&osm_ <<
62 power-domains = <&CPU_ <<
63 power-domain-names = " <<
64 #cooling-cells = <2>; 47 #cooling-cells = <2>;
65 L2_0: l2-cache { 48 L2_0: l2-cache {
66 compatible = " 49 compatible = "cache";
67 cache-level = <<
68 cache-unified; <<
69 next-level-cac 50 next-level-cache = <&L3_0>;
70 L3_0: l3-cache 51 L3_0: l3-cache {
71 compat 52 compatible = "cache";
72 cache- <<
73 cache- <<
74 }; 53 };
75 }; 54 };
76 }; 55 };
77 56
78 CPU1: cpu@100 { 57 CPU1: cpu@100 {
79 device_type = "cpu"; 58 device_type = "cpu";
80 compatible = "qcom,kry 59 compatible = "qcom,kryo560";
81 reg = <0x0 0x100>; 60 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw <<
83 enable-method = "psci" 61 enable-method = "psci";
84 capacity-dmips-mhz = < 62 capacity-dmips-mhz = <1024>;
85 dynamic-power-coeffici 63 dynamic-power-coefficient = <100>;
86 next-level-cache = <&L 64 next-level-cache = <&L2_100>;
87 qcom,freq-domain = <&c 65 qcom,freq-domain = <&cpufreq_hw 0>;
88 operating-points-v2 = <<
89 interconnects = <&gem_ <<
90 &clk_ <<
91 <&osm_ <<
92 power-domains = <&CPU_ <<
93 power-domain-names = " <<
94 #cooling-cells = <2>; 66 #cooling-cells = <2>;
95 L2_100: l2-cache { 67 L2_100: l2-cache {
96 compatible = " 68 compatible = "cache";
97 cache-level = <<
98 cache-unified; <<
99 next-level-cac 69 next-level-cache = <&L3_0>;
100 }; 70 };
101 }; 71 };
102 72
103 CPU2: cpu@200 { 73 CPU2: cpu@200 {
104 device_type = "cpu"; 74 device_type = "cpu";
105 compatible = "qcom,kry 75 compatible = "qcom,kryo560";
106 reg = <0x0 0x200>; 76 reg = <0x0 0x200>;
107 clocks = <&cpufreq_hw <<
108 enable-method = "psci" 77 enable-method = "psci";
109 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <1024>;
110 dynamic-power-coeffici 79 dynamic-power-coefficient = <100>;
111 next-level-cache = <&L 80 next-level-cache = <&L2_200>;
112 qcom,freq-domain = <&c 81 qcom,freq-domain = <&cpufreq_hw 0>;
113 operating-points-v2 = <<
114 interconnects = <&gem_ <<
115 &clk_ <<
116 <&osm_ <<
117 power-domains = <&CPU_ <<
118 power-domain-names = " <<
119 #cooling-cells = <2>; 82 #cooling-cells = <2>;
120 L2_200: l2-cache { 83 L2_200: l2-cache {
121 compatible = " 84 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 85 next-level-cache = <&L3_0>;
125 }; 86 };
126 }; 87 };
127 88
128 CPU3: cpu@300 { 89 CPU3: cpu@300 {
129 device_type = "cpu"; 90 device_type = "cpu";
130 compatible = "qcom,kry 91 compatible = "qcom,kryo560";
131 reg = <0x0 0x300>; 92 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 93 enable-method = "psci";
134 capacity-dmips-mhz = < 94 capacity-dmips-mhz = <1024>;
135 dynamic-power-coeffici 95 dynamic-power-coefficient = <100>;
136 next-level-cache = <&L 96 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 97 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <<
139 interconnects = <&gem_ <<
140 &clk_ <<
141 <&osm_ <<
142 power-domains = <&CPU_ <<
143 power-domain-names = " <<
144 #cooling-cells = <2>; 98 #cooling-cells = <2>;
145 L2_300: l2-cache { 99 L2_300: l2-cache {
146 compatible = " 100 compatible = "cache";
147 cache-level = <<
148 cache-unified; <<
149 next-level-cac 101 next-level-cache = <&L3_0>;
150 }; 102 };
151 }; 103 };
152 104
153 CPU4: cpu@400 { 105 CPU4: cpu@400 {
154 device_type = "cpu"; 106 device_type = "cpu";
155 compatible = "qcom,kry 107 compatible = "qcom,kryo560";
156 reg = <0x0 0x400>; 108 reg = <0x0 0x400>;
157 clocks = <&cpufreq_hw <<
158 enable-method = "psci" 109 enable-method = "psci";
159 capacity-dmips-mhz = < 110 capacity-dmips-mhz = <1024>;
160 dynamic-power-coeffici 111 dynamic-power-coefficient = <100>;
161 next-level-cache = <&L 112 next-level-cache = <&L2_400>;
162 qcom,freq-domain = <&c 113 qcom,freq-domain = <&cpufreq_hw 0>;
163 operating-points-v2 = <<
164 interconnects = <&gem_ <<
165 &clk_ <<
166 <&osm_ <<
167 power-domains = <&CPU_ <<
168 power-domain-names = " <<
169 #cooling-cells = <2>; 114 #cooling-cells = <2>;
170 L2_400: l2-cache { 115 L2_400: l2-cache {
171 compatible = " 116 compatible = "cache";
172 cache-level = <<
173 cache-unified; <<
174 next-level-cac 117 next-level-cache = <&L3_0>;
175 }; 118 };
176 }; 119 };
177 120
178 CPU5: cpu@500 { 121 CPU5: cpu@500 {
179 device_type = "cpu"; 122 device_type = "cpu";
180 compatible = "qcom,kry 123 compatible = "qcom,kryo560";
181 reg = <0x0 0x500>; 124 reg = <0x0 0x500>;
182 clocks = <&cpufreq_hw <<
183 enable-method = "psci" 125 enable-method = "psci";
184 capacity-dmips-mhz = < 126 capacity-dmips-mhz = <1024>;
185 dynamic-power-coeffici 127 dynamic-power-coefficient = <100>;
186 next-level-cache = <&L 128 next-level-cache = <&L2_500>;
187 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 0>;
188 operating-points-v2 = <<
189 interconnects = <&gem_ <<
190 &clk_ <<
191 <&osm_ <<
192 power-domains = <&CPU_ <<
193 power-domain-names = " <<
194 #cooling-cells = <2>; 130 #cooling-cells = <2>;
195 L2_500: l2-cache { 131 L2_500: l2-cache {
196 compatible = " 132 compatible = "cache";
197 cache-level = <<
198 cache-unified; <<
199 next-level-cac 133 next-level-cache = <&L3_0>;
200 }; 134 };
>> 135
201 }; 136 };
202 137
203 CPU6: cpu@600 { 138 CPU6: cpu@600 {
204 device_type = "cpu"; 139 device_type = "cpu";
205 compatible = "qcom,kry 140 compatible = "qcom,kryo560";
206 reg = <0x0 0x600>; 141 reg = <0x0 0x600>;
207 clocks = <&cpufreq_hw <<
208 enable-method = "psci" 142 enable-method = "psci";
209 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <1894>;
210 dynamic-power-coeffici 144 dynamic-power-coefficient = <703>;
211 next-level-cache = <&L 145 next-level-cache = <&L2_600>;
212 qcom,freq-domain = <&c 146 qcom,freq-domain = <&cpufreq_hw 1>;
213 operating-points-v2 = <<
214 interconnects = <&gem_ <<
215 &clk_ <<
216 <&osm_ <<
217 power-domains = <&CPU_ <<
218 power-domain-names = " <<
219 #cooling-cells = <2>; 147 #cooling-cells = <2>;
220 L2_600: l2-cache { 148 L2_600: l2-cache {
221 compatible = " 149 compatible = "cache";
222 cache-level = <<
223 cache-unified; <<
224 next-level-cac 150 next-level-cache = <&L3_0>;
225 }; 151 };
226 }; 152 };
227 153
228 CPU7: cpu@700 { 154 CPU7: cpu@700 {
229 device_type = "cpu"; 155 device_type = "cpu";
230 compatible = "qcom,kry 156 compatible = "qcom,kryo560";
231 reg = <0x0 0x700>; 157 reg = <0x0 0x700>;
232 clocks = <&cpufreq_hw <<
233 enable-method = "psci" 158 enable-method = "psci";
234 capacity-dmips-mhz = < 159 capacity-dmips-mhz = <1894>;
235 dynamic-power-coeffici 160 dynamic-power-coefficient = <703>;
236 next-level-cache = <&L 161 next-level-cache = <&L2_700>;
237 qcom,freq-domain = <&c 162 qcom,freq-domain = <&cpufreq_hw 1>;
238 operating-points-v2 = <<
239 interconnects = <&gem_ <<
240 &clk_ <<
241 <&osm_ <<
242 power-domains = <&CPU_ <<
243 power-domain-names = " <<
244 #cooling-cells = <2>; 163 #cooling-cells = <2>;
245 L2_700: l2-cache { 164 L2_700: l2-cache {
246 compatible = " 165 compatible = "cache";
247 cache-level = <<
248 cache-unified; <<
249 next-level-cac 166 next-level-cache = <&L3_0>;
250 }; 167 };
251 }; 168 };
252 169
253 cpu-map { 170 cpu-map {
254 cluster0 { 171 cluster0 {
255 core0 { 172 core0 {
256 cpu = 173 cpu = <&CPU0>;
257 }; 174 };
258 175
259 core1 { 176 core1 {
260 cpu = 177 cpu = <&CPU1>;
261 }; 178 };
262 179
263 core2 { 180 core2 {
264 cpu = 181 cpu = <&CPU2>;
265 }; 182 };
266 183
267 core3 { 184 core3 {
268 cpu = 185 cpu = <&CPU3>;
269 }; 186 };
270 187
271 core4 { 188 core4 {
272 cpu = 189 cpu = <&CPU4>;
273 }; 190 };
274 191
275 core5 { 192 core5 {
276 cpu = 193 cpu = <&CPU5>;
277 }; 194 };
278 195
279 core6 { 196 core6 {
280 cpu = 197 cpu = <&CPU6>;
281 }; 198 };
282 199
283 core7 { 200 core7 {
284 cpu = 201 cpu = <&CPU7>;
285 }; 202 };
286 }; 203 };
287 }; 204 };
288 <<
289 domain-idle-states { <<
290 CLUSTER_SLEEP_PC: clus <<
291 compatible = " <<
292 arm,psci-suspe <<
293 entry-latency- <<
294 exit-latency-u <<
295 min-residency- <<
296 }; <<
297 <<
298 CLUSTER_SLEEP_CX_RET: <<
299 compatible = " <<
300 arm,psci-suspe <<
301 entry-latency- <<
302 exit-latency-u <<
303 min-residency- <<
304 }; <<
305 <<
306 CLUSTER_AOSS_SLEEP: cl <<
307 compatible = " <<
308 arm,psci-suspe <<
309 entry-latency- <<
310 exit-latency-u <<
311 min-residency- <<
312 }; <<
313 }; <<
314 <<
315 cpu_idle_states: idle-states { <<
316 entry-method = "psci"; <<
317 <<
318 LITTLE_CPU_SLEEP_0: cp <<
319 compatible = " <<
320 idle-state-nam <<
321 arm,psci-suspe <<
322 entry-latency- <<
323 exit-latency-u <<
324 min-residency- <<
325 local-timer-st <<
326 }; <<
327 <<
328 LITTLE_CPU_SLEEP_1: cp <<
329 compatible = " <<
330 idle-state-nam <<
331 arm,psci-suspe <<
332 entry-latency- <<
333 exit-latency-u <<
334 min-residency- <<
335 local-timer-st <<
336 }; <<
337 <<
338 BIG_CPU_SLEEP_0: cpu-s <<
339 compatible = " <<
340 idle-state-nam <<
341 arm,psci-suspe <<
342 entry-latency- <<
343 exit-latency-u <<
344 min-residency- <<
345 local-timer-st <<
346 }; <<
347 <<
348 BIG_CPU_SLEEP_1: cpu-s <<
349 compatible = " <<
350 idle-state-nam <<
351 arm,psci-suspe <<
352 entry-latency- <<
353 exit-latency-u <<
354 min-residency- <<
355 local-timer-st <<
356 }; <<
357 }; <<
358 }; 205 };
359 206
360 firmware { 207 firmware {
361 scm: scm { 208 scm: scm {
362 compatible = "qcom,scm 209 compatible = "qcom,scm-sm6350", "qcom,scm";
363 #reset-cells = <1>; 210 #reset-cells = <1>;
364 }; 211 };
365 }; 212 };
366 213
367 memory@80000000 { 214 memory@80000000 {
368 device_type = "memory"; 215 device_type = "memory";
369 /* We expect the bootloader to 216 /* We expect the bootloader to fill in the size */
370 reg = <0x0 0x80000000 0x0 0x0> 217 reg = <0x0 0x80000000 0x0 0x0>;
371 }; 218 };
372 219
373 cpu0_opp_table: opp-table-cpu0 { <<
374 compatible = "operating-points <<
375 opp-shared; <<
376 <<
377 opp-300000000 { <<
378 opp-hz = /bits/ 64 <30 <<
379 /* DDR: 4-wide, 2 chan <<
380 opp-peak-kBps = <(2000 <<
381 }; <<
382 <<
383 opp-576000000 { <<
384 opp-hz = /bits/ 64 <57 <<
385 opp-peak-kBps = <(5470 <<
386 }; <<
387 <<
388 opp-768000000 { <<
389 opp-hz = /bits/ 64 <76 <<
390 opp-peak-kBps = <(7680 <<
391 }; <<
392 <<
393 opp-1017600000 { <<
394 opp-hz = /bits/ 64 <10 <<
395 opp-peak-kBps = <(1017 <<
396 }; <<
397 <<
398 opp-1248000000 { <<
399 opp-hz = /bits/ 64 <12 <<
400 opp-peak-kBps = <(1017 <<
401 }; <<
402 <<
403 opp-1324800000 { <<
404 opp-hz = /bits/ 64 <13 <<
405 opp-peak-kBps = <(1017 <<
406 }; <<
407 <<
408 opp-1516800000 { <<
409 opp-hz = /bits/ 64 <15 <<
410 opp-peak-kBps = <(1353 <<
411 }; <<
412 <<
413 opp-1612800000 { <<
414 opp-hz = /bits/ 64 <16 <<
415 opp-peak-kBps = <(1555 <<
416 }; <<
417 <<
418 opp-1708800000 { <<
419 opp-hz = /bits/ 64 <17 <<
420 opp-peak-kBps = <(1555 <<
421 }; <<
422 }; <<
423 <<
424 cpu6_opp_table: opp-table-cpu6 { <<
425 compatible = "operating-points <<
426 opp-shared; <<
427 <<
428 opp-300000000 { <<
429 opp-hz = /bits/ 64 <30 <<
430 opp-peak-kBps = <(2000 <<
431 }; <<
432 <<
433 opp-787200000 { <<
434 opp-hz = /bits/ 64 <78 <<
435 opp-peak-kBps = <(7680 <<
436 }; <<
437 <<
438 opp-979200000 { <<
439 opp-hz = /bits/ 64 <97 <<
440 opp-peak-kBps = <(7680 <<
441 }; <<
442 <<
443 opp-1036800000 { <<
444 opp-hz = /bits/ 64 <10 <<
445 opp-peak-kBps = <(1017 <<
446 }; <<
447 <<
448 opp-1248000000 { <<
449 opp-hz = /bits/ 64 <12 <<
450 opp-peak-kBps = <(1017 <<
451 }; <<
452 <<
453 opp-1401600000 { <<
454 opp-hz = /bits/ 64 <14 <<
455 opp-peak-kBps = <(1353 <<
456 }; <<
457 <<
458 opp-1555200000 { <<
459 opp-hz = /bits/ 64 <15 <<
460 opp-peak-kBps = <(1555 <<
461 }; <<
462 <<
463 opp-1766400000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <(1555 <<
466 }; <<
467 <<
468 opp-1900800000 { <<
469 opp-hz = /bits/ 64 <19 <<
470 opp-peak-kBps = <(1804 <<
471 }; <<
472 <<
473 opp-2073600000 { <<
474 opp-hz = /bits/ 64 <20 <<
475 opp-peak-kBps = <(2092 <<
476 }; <<
477 }; <<
478 <<
479 qup_opp_table: opp-table-qup { <<
480 compatible = "operating-points <<
481 <<
482 opp-75000000 { <<
483 opp-hz = /bits/ 64 <75 <<
484 required-opps = <&rpmh <<
485 }; <<
486 <<
487 opp-100000000 { <<
488 opp-hz = /bits/ 64 <10 <<
489 required-opps = <&rpmh <<
490 }; <<
491 <<
492 opp-128000000 { <<
493 opp-hz = /bits/ 64 <12 <<
494 required-opps = <&rpmh <<
495 }; <<
496 }; <<
497 <<
498 pmu { 220 pmu {
499 compatible = "arm,armv8-pmuv3" 221 compatible = "arm,armv8-pmuv3";
500 interrupts = <GIC_PPI 5 IRQ_TY 222 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
501 }; 223 };
502 224
503 psci { 225 psci {
504 compatible = "arm,psci-1.0"; 226 compatible = "arm,psci-1.0";
505 method = "smc"; 227 method = "smc";
506 <<
507 CPU_PD0: power-domain-cpu0 { <<
508 #power-domain-cells = <<
509 power-domains = <&CLUS <<
510 domain-idle-states = < <<
511 }; <<
512 <<
513 CPU_PD1: power-domain-cpu1 { <<
514 #power-domain-cells = <<
515 power-domains = <&CLUS <<
516 domain-idle-states = < <<
517 }; <<
518 <<
519 CPU_PD2: power-domain-cpu2 { <<
520 #power-domain-cells = <<
521 power-domains = <&CLUS <<
522 domain-idle-states = < <<
523 }; <<
524 <<
525 CPU_PD3: power-domain-cpu3 { <<
526 #power-domain-cells = <<
527 power-domains = <&CLUS <<
528 domain-idle-states = < <<
529 }; <<
530 <<
531 CPU_PD4: power-domain-cpu4 { <<
532 #power-domain-cells = <<
533 power-domains = <&CLUS <<
534 domain-idle-states = < <<
535 }; <<
536 <<
537 CPU_PD5: power-domain-cpu5 { <<
538 #power-domain-cells = <<
539 power-domains = <&CLUS <<
540 domain-idle-states = < <<
541 }; <<
542 <<
543 CPU_PD6: power-domain-cpu6 { <<
544 #power-domain-cells = <<
545 power-domains = <&CLUS <<
546 domain-idle-states = < <<
547 }; <<
548 <<
549 CPU_PD7: power-domain-cpu7 { <<
550 #power-domain-cells = <<
551 power-domains = <&CLUS <<
552 domain-idle-states = < <<
553 }; <<
554 <<
555 CLUSTER_PD: power-domain-cpu-c <<
556 #power-domain-cells = <<
557 domain-idle-states = < <<
558 <<
559 <<
560 }; <<
561 }; 228 };
562 229
563 reserved_memory: reserved-memory { 230 reserved_memory: reserved-memory {
564 #address-cells = <2>; 231 #address-cells = <2>;
565 #size-cells = <2>; 232 #size-cells = <2>;
566 ranges; 233 ranges;
567 234
568 hyp_mem: memory@80000000 { 235 hyp_mem: memory@80000000 {
569 reg = <0 0x80000000 0 236 reg = <0 0x80000000 0 0x600000>;
570 no-map; 237 no-map;
571 }; 238 };
572 239
573 xbl_aop_mem: memory@80700000 { 240 xbl_aop_mem: memory@80700000 {
574 reg = <0 0x80700000 0 241 reg = <0 0x80700000 0 0x160000>;
575 no-map; 242 no-map;
576 }; 243 };
577 244
578 cmd_db: memory@80860000 { 245 cmd_db: memory@80860000 {
579 compatible = "qcom,cmd 246 compatible = "qcom,cmd-db";
580 reg = <0 0x80860000 0 247 reg = <0 0x80860000 0 0x20000>;
581 no-map; 248 no-map;
582 }; 249 };
583 250
584 sec_apps_mem: memory@808ff000 251 sec_apps_mem: memory@808ff000 {
585 reg = <0 0x808ff000 0 252 reg = <0 0x808ff000 0 0x1000>;
586 no-map; 253 no-map;
587 }; 254 };
588 255
589 smem_mem: memory@80900000 { 256 smem_mem: memory@80900000 {
590 reg = <0 0x80900000 0 257 reg = <0 0x80900000 0 0x200000>;
591 no-map; 258 no-map;
592 }; 259 };
593 260
594 cdsp_sec_mem: memory@80b00000 261 cdsp_sec_mem: memory@80b00000 {
595 reg = <0 0x80b00000 0 262 reg = <0 0x80b00000 0 0x1e00000>;
596 no-map; 263 no-map;
597 }; 264 };
598 265
599 pil_camera_mem: memory@8600000 266 pil_camera_mem: memory@86000000 {
600 reg = <0 0x86000000 0 267 reg = <0 0x86000000 0 0x500000>;
601 no-map; 268 no-map;
602 }; 269 };
603 270
604 pil_npu_mem: memory@86500000 { 271 pil_npu_mem: memory@86500000 {
605 reg = <0 0x86500000 0 272 reg = <0 0x86500000 0 0x500000>;
606 no-map; 273 no-map;
607 }; 274 };
608 275
609 pil_video_mem: memory@86a00000 276 pil_video_mem: memory@86a00000 {
610 reg = <0 0x86a00000 0 277 reg = <0 0x86a00000 0 0x500000>;
611 no-map; 278 no-map;
612 }; 279 };
613 280
614 pil_cdsp_mem: memory@86f00000 281 pil_cdsp_mem: memory@86f00000 {
615 reg = <0 0x86f00000 0 282 reg = <0 0x86f00000 0 0x1e00000>;
616 no-map; 283 no-map;
617 }; 284 };
618 285
619 pil_adsp_mem: memory@88d00000 286 pil_adsp_mem: memory@88d00000 {
620 reg = <0 0x88d00000 0 287 reg = <0 0x88d00000 0 0x2800000>;
621 no-map; 288 no-map;
622 }; 289 };
623 290
624 wlan_fw_mem: memory@8b500000 { 291 wlan_fw_mem: memory@8b500000 {
625 reg = <0 0x8b500000 0 292 reg = <0 0x8b500000 0 0x200000>;
626 no-map; 293 no-map;
627 }; 294 };
628 295
629 pil_ipa_fw_mem: memory@8b70000 296 pil_ipa_fw_mem: memory@8b700000 {
630 reg = <0 0x8b700000 0 297 reg = <0 0x8b700000 0 0x10000>;
631 no-map; 298 no-map;
632 }; 299 };
633 300
634 pil_ipa_gsi_mem: memory@8b7100 301 pil_ipa_gsi_mem: memory@8b710000 {
635 reg = <0 0x8b710000 0 302 reg = <0 0x8b710000 0 0x5400>;
636 no-map; 303 no-map;
637 }; 304 };
638 305
>> 306 pil_gpu_mem: memory@8b715400 {
>> 307 reg = <0 0x8b715400 0 0x2000>;
>> 308 no-map;
>> 309 };
>> 310
639 pil_modem_mem: memory@8b800000 311 pil_modem_mem: memory@8b800000 {
640 reg = <0 0x8b800000 0 312 reg = <0 0x8b800000 0 0xf800000>;
641 no-map; 313 no-map;
642 }; 314 };
643 315
644 cont_splash_memory: memory@a00 316 cont_splash_memory: memory@a0000000 {
645 reg = <0 0xa0000000 0 317 reg = <0 0xa0000000 0 0x2300000>;
646 no-map; 318 no-map;
647 }; 319 };
648 320
649 dfps_data_memory: memory@a2300 321 dfps_data_memory: memory@a2300000 {
650 reg = <0 0xa2300000 0 322 reg = <0 0xa2300000 0 0x100000>;
651 no-map; 323 no-map;
652 }; 324 };
653 325
654 removed_region: memory@c000000 326 removed_region: memory@c0000000 {
655 reg = <0 0xc0000000 0 327 reg = <0 0xc0000000 0 0x3900000>;
656 no-map; 328 no-map;
657 }; 329 };
658 330
659 pil_gpu_mem: memory@f0d00000 { <<
660 reg = <0 0xf0d00000 0 <<
661 no-map; <<
662 }; <<
663 <<
664 debug_region: memory@ffb00000 331 debug_region: memory@ffb00000 {
665 reg = <0 0xffb00000 0 332 reg = <0 0xffb00000 0 0xc0000>;
666 no-map; 333 no-map;
667 }; 334 };
668 335
669 last_log_region: memory@ffbc00 336 last_log_region: memory@ffbc0000 {
670 reg = <0 0xffbc0000 0 337 reg = <0 0xffbc0000 0 0x40000>;
671 no-map; 338 no-map;
672 }; 339 };
673 340
674 ramoops: ramoops@ffc00000 { 341 ramoops: ramoops@ffc00000 {
675 compatible = "ramoops" !! 342 compatible = "removed-dma-pool", "ramoops";
676 reg = <0 0xffc00000 0 !! 343 reg = <0 0xffc00000 0 0x00100000>;
677 record-size = <0x1000> 344 record-size = <0x1000>;
678 console-size = <0x4000 345 console-size = <0x40000>;
679 pmsg-size = <0x20000>; !! 346 ftrace-size = <0x0>;
680 ecc-size = <16>; !! 347 msg-size = <0x20000 0x20000>;
>> 348 cc-size = <0x0>;
681 no-map; 349 no-map;
682 }; 350 };
683 351
684 cmdline_region: memory@ffd0000 352 cmdline_region: memory@ffd00000 {
685 reg = <0 0xffd00000 0 353 reg = <0 0xffd00000 0 0x1000>;
686 no-map; 354 no-map;
687 }; 355 };
688 }; 356 };
689 357
690 smem { 358 smem {
691 compatible = "qcom,smem"; 359 compatible = "qcom,smem";
692 memory-region = <&smem_mem>; 360 memory-region = <&smem_mem>;
693 hwlocks = <&tcsr_mutex 3>; 361 hwlocks = <&tcsr_mutex 3>;
694 }; 362 };
695 363
696 smp2p-adsp { 364 smp2p-adsp {
697 compatible = "qcom,smp2p"; 365 compatible = "qcom,smp2p";
698 qcom,smem = <443>, <429>; 366 qcom,smem = <443>, <429>;
699 interrupts-extended = <&ipcc I 367 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
700 I 368 IPCC_MPROC_SIGNAL_SMP2P
701 I 369 IRQ_TYPE_EDGE_RISING>;
702 mboxes = <&ipcc IPCC_CLIENT_LP 370 mboxes = <&ipcc IPCC_CLIENT_LPASS
703 IPCC_MPROC_SIG 371 IPCC_MPROC_SIGNAL_SMP2P>;
704 372
705 qcom,local-pid = <0>; 373 qcom,local-pid = <0>;
706 qcom,remote-pid = <2>; 374 qcom,remote-pid = <2>;
707 375
708 smp2p_adsp_out: master-kernel 376 smp2p_adsp_out: master-kernel {
709 qcom,entry-name = "mas 377 qcom,entry-name = "master-kernel";
710 #qcom,smem-state-cells 378 #qcom,smem-state-cells = <1>;
711 }; 379 };
712 380
713 smp2p_adsp_in: slave-kernel { 381 smp2p_adsp_in: slave-kernel {
714 qcom,entry-name = "sla 382 qcom,entry-name = "slave-kernel";
715 interrupt-controller; 383 interrupt-controller;
716 #interrupt-cells = <2> 384 #interrupt-cells = <2>;
717 }; 385 };
718 }; 386 };
719 387
720 smp2p-cdsp { 388 smp2p-cdsp {
721 compatible = "qcom,smp2p"; 389 compatible = "qcom,smp2p";
722 qcom,smem = <94>, <432>; 390 qcom,smem = <94>, <432>;
723 interrupts-extended = <&ipcc I 391 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
724 I 392 IPCC_MPROC_SIGNAL_SMP2P
725 I 393 IRQ_TYPE_EDGE_RISING>;
726 mboxes = <&ipcc IPCC_CLIENT_CD 394 mboxes = <&ipcc IPCC_CLIENT_CDSP
727 IPCC_MPROC_SIG 395 IPCC_MPROC_SIGNAL_SMP2P>;
728 396
729 qcom,local-pid = <0>; 397 qcom,local-pid = <0>;
730 qcom,remote-pid = <5>; 398 qcom,remote-pid = <5>;
731 399
732 smp2p_cdsp_out: master-kernel 400 smp2p_cdsp_out: master-kernel {
733 qcom,entry-name = "mas 401 qcom,entry-name = "master-kernel";
734 #qcom,smem-state-cells 402 #qcom,smem-state-cells = <1>;
735 }; 403 };
736 404
737 smp2p_cdsp_in: slave-kernel { 405 smp2p_cdsp_in: slave-kernel {
738 qcom,entry-name = "sla 406 qcom,entry-name = "slave-kernel";
739 interrupt-controller; 407 interrupt-controller;
740 #interrupt-cells = <2> 408 #interrupt-cells = <2>;
741 }; 409 };
742 }; 410 };
743 411
744 smp2p-mpss { 412 smp2p-mpss {
745 compatible = "qcom,smp2p"; 413 compatible = "qcom,smp2p";
746 qcom,smem = <435>, <428>; 414 qcom,smem = <435>, <428>;
747 415
748 interrupts-extended = <&ipcc I 416 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
749 I 417 IPCC_MPROC_SIGNAL_SMP2P
750 I 418 IRQ_TYPE_EDGE_RISING>;
751 mboxes = <&ipcc IPCC_CLIENT_MP 419 mboxes = <&ipcc IPCC_CLIENT_MPSS
752 IPCC_MPROC_SIG 420 IPCC_MPROC_SIGNAL_SMP2P>;
753 421
754 qcom,local-pid = <0>; 422 qcom,local-pid = <0>;
755 qcom,remote-pid = <1>; 423 qcom,remote-pid = <1>;
756 424
757 modem_smp2p_out: master-kernel 425 modem_smp2p_out: master-kernel {
758 qcom,entry-name = "mas 426 qcom,entry-name = "master-kernel";
759 #qcom,smem-state-cells 427 #qcom,smem-state-cells = <1>;
760 }; 428 };
761 429
762 modem_smp2p_in: slave-kernel { 430 modem_smp2p_in: slave-kernel {
763 qcom,entry-name = "sla 431 qcom,entry-name = "slave-kernel";
764 interrupt-controller; <<
765 #interrupt-cells = <2> <<
766 }; <<
767 <<
768 ipa_smp2p_out: ipa-ap-to-modem <<
769 qcom,entry-name = "ipa <<
770 #qcom,smem-state-cells <<
771 }; <<
772 432
773 ipa_smp2p_in: ipa-modem-to-ap <<
774 qcom,entry-name = "ipa <<
775 interrupt-controller; 433 interrupt-controller;
776 #interrupt-cells = <2> 434 #interrupt-cells = <2>;
777 }; 435 };
778 }; 436 };
779 437
780 soc: soc@0 { 438 soc: soc@0 {
781 #address-cells = <2>; 439 #address-cells = <2>;
782 #size-cells = <2>; 440 #size-cells = <2>;
783 ranges = <0 0 0 0 0x10 0>; 441 ranges = <0 0 0 0 0x10 0>;
784 dma-ranges = <0 0 0 0 0x10 0>; 442 dma-ranges = <0 0 0 0 0x10 0>;
785 compatible = "simple-bus"; 443 compatible = "simple-bus";
786 444
787 gcc: clock-controller@100000 { 445 gcc: clock-controller@100000 {
788 compatible = "qcom,gcc 446 compatible = "qcom,gcc-sm6350";
789 reg = <0 0x00100000 0 447 reg = <0 0x00100000 0 0x1f0000>;
790 #clock-cells = <1>; 448 #clock-cells = <1>;
791 #reset-cells = <1>; 449 #reset-cells = <1>;
792 #power-domain-cells = 450 #power-domain-cells = <1>;
793 clock-names = "bi_tcxo 451 clock-names = "bi_tcxo",
794 "bi_tcxo 452 "bi_tcxo_ao",
795 "sleep_c 453 "sleep_clk";
796 clocks = <&rpmhcc RPMH 454 clocks = <&rpmhcc RPMH_CXO_CLK>,
797 <&rpmhcc RPMH 455 <&rpmhcc RPMH_CXO_CLK_A>,
798 <&sleep_clk>; 456 <&sleep_clk>;
799 }; 457 };
800 458
801 ipcc: mailbox@408000 { 459 ipcc: mailbox@408000 {
802 compatible = "qcom,sm6 460 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
803 reg = <0 0x00408000 0 461 reg = <0 0x00408000 0 0x1000>;
804 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
805 interrupt-controller; 463 interrupt-controller;
806 #interrupt-cells = <3> 464 #interrupt-cells = <3>;
807 #mbox-cells = <2>; 465 #mbox-cells = <2>;
808 }; 466 };
809 467
810 qfprom: qfprom@784000 { <<
811 compatible = "qcom,sm6 <<
812 reg = <0 0x00784000 0 <<
813 #address-cells = <1>; <<
814 #size-cells = <1>; <<
815 <<
816 gpu_speed_bin: gpu-spe <<
817 reg = <0x2015 <<
818 bits = <0 8>; <<
819 }; <<
820 }; <<
821 <<
822 rng: rng@793000 { 468 rng: rng@793000 {
823 compatible = "qcom,prn 469 compatible = "qcom,prng-ee";
824 reg = <0 0x00793000 0 470 reg = <0 0x00793000 0 0x1000>;
825 clocks = <&gcc GCC_PRN 471 clocks = <&gcc GCC_PRNG_AHB_CLK>;
826 clock-names = "core"; 472 clock-names = "core";
827 }; 473 };
828 474
829 sdhc_1: mmc@7c4000 { !! 475 sdhc_1: sdhci@7c4000 {
830 compatible = "qcom,sm6 476 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
831 reg = <0 0x007c4000 0 477 reg = <0 0x007c4000 0 0x1000>,
832 <0 0x007c5000 478 <0 0x007c5000 0 0x1000>,
833 <0 0x007c8000 479 <0 0x007c8000 0 0x8000>;
834 reg-names = "hc", "cqh 480 reg-names = "hc", "cqhci", "ice";
835 481
836 interrupts = <GIC_SPI 482 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 483 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
838 interrupt-names = "hc_ 484 interrupt-names = "hc_irq", "pwr_irq";
839 iommus = <&apps_smmu 0 <<
840 485
841 clocks = <&gcc GCC_SDC 486 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
842 <&gcc GCC_SDC 487 <&gcc GCC_SDCC1_APPS_CLK>,
843 <&rpmhcc RPMH 488 <&rpmhcc RPMH_CXO_CLK>;
844 clock-names = "iface", 489 clock-names = "iface", "core", "xo";
845 resets = <&gcc GCC_SDC <<
846 qcom,dll-config = <0x0 490 qcom,dll-config = <0x000f642c>;
847 qcom,ddr-config = <0x8 491 qcom,ddr-config = <0x80040868>;
848 power-domains = <&rpmh !! 492 power-domains = <&rpmhpd 0>;
849 operating-points-v2 = 493 operating-points-v2 = <&sdhc1_opp_table>;
850 bus-width = <8>; 494 bus-width = <8>;
851 non-removable; 495 non-removable;
852 supports-cqe; 496 supports-cqe;
853 497
854 status = "disabled"; 498 status = "disabled";
855 499
856 sdhc1_opp_table: opp-t !! 500 sdhc1_opp_table: sdhc1-opp-table {
857 compatible = " 501 compatible = "operating-points-v2";
858 502
859 opp-19200000 { 503 opp-19200000 {
860 opp-hz 504 opp-hz = /bits/ 64 <19200000>;
861 requir 505 required-opps = <&rpmhpd_opp_min_svs>;
862 }; 506 };
863 507
864 opp-100000000 508 opp-100000000 {
865 opp-hz 509 opp-hz = /bits/ 64 <100000000>;
866 requir 510 required-opps = <&rpmhpd_opp_low_svs>;
867 }; 511 };
868 512
869 opp-384000000 513 opp-384000000 {
870 opp-hz 514 opp-hz = /bits/ 64 <384000000>;
871 requir 515 required-opps = <&rpmhpd_opp_svs_l1>;
872 }; 516 };
873 }; 517 };
874 }; 518 };
875 519
876 gpi_dma0: dma-controller@80000 <<
877 compatible = "qcom,sm6 <<
878 reg = <0 0x00800000 0 <<
879 interrupts = <GIC_SPI <<
880 <GIC_SPI <<
881 <GIC_SPI <<
882 <GIC_SPI <<
883 <GIC_SPI <<
884 <GIC_SPI <<
885 <GIC_SPI <<
886 <GIC_SPI <<
887 <GIC_SPI <<
888 <GIC_SPI <<
889 dma-channels = <10>; <<
890 dma-channel-mask = <0x <<
891 iommus = <&apps_smmu 0 <<
892 #dma-cells = <3>; <<
893 status = "disabled"; <<
894 }; <<
895 <<
896 qupv3_id_0: geniqup@8c0000 { <<
897 compatible = "qcom,gen <<
898 reg = <0x0 0x008c0000 <<
899 clock-names = "m-ahb", <<
900 clocks = <&gcc GCC_QUP <<
901 <&gcc GCC_QUP <<
902 #address-cells = <2>; <<
903 #size-cells = <2>; <<
904 iommus = <&apps_smmu 0 <<
905 ranges; <<
906 status = "disabled"; <<
907 <<
908 i2c0: i2c@880000 { <<
909 compatible = " <<
910 reg = <0 0x008 <<
911 clock-names = <<
912 clocks = <&gcc <<
913 pinctrl-names <<
914 pinctrl-0 = <& <<
915 interrupts = < <<
916 dmas = <&gpi_d <<
917 <&gpi_d <<
918 dma-names = "t <<
919 #address-cells <<
920 #size-cells = <<
921 interconnects <<
922 <<
923 <<
924 interconnect-n <<
925 status = "disa <<
926 }; <<
927 <<
928 uart1: serial@884000 { <<
929 compatible = " <<
930 reg = <0 0x008 <<
931 clock-names = <<
932 clocks = <&gcc <<
933 pinctrl-names <<
934 pinctrl-0 = <& <<
935 interrupts = < <<
936 power-domains <<
937 operating-poin <<
938 interconnects <<
939 <<
940 interconnect-n <<
941 status = "disa <<
942 }; <<
943 <<
944 i2c2: i2c@888000 { <<
945 compatible = " <<
946 reg = <0 0x008 <<
947 clock-names = <<
948 clocks = <&gcc <<
949 pinctrl-names <<
950 pinctrl-0 = <& <<
951 interrupts = < <<
952 dmas = <&gpi_d <<
953 <&gpi_d <<
954 dma-names = "t <<
955 #address-cells <<
956 #size-cells = <<
957 interconnects <<
958 <<
959 <<
960 interconnect-n <<
961 status = "disa <<
962 }; <<
963 }; <<
964 <<
965 gpi_dma1: dma-controller@90000 <<
966 compatible = "qcom,sm6 <<
967 reg = <0 0x00900000 0 <<
968 interrupts = <GIC_SPI <<
969 <GIC_SPI <<
970 <GIC_SPI <<
971 <GIC_SPI <<
972 <GIC_SPI <<
973 <GIC_SPI <<
974 <GIC_SPI <<
975 <GIC_SPI <<
976 <GIC_SPI <<
977 <GIC_SPI <<
978 dma-channels = <10>; <<
979 dma-channel-mask = <0x <<
980 iommus = <&apps_smmu 0 <<
981 #dma-cells = <3>; <<
982 status = "disabled"; <<
983 }; <<
984 <<
985 qupv3_id_1: geniqup@9c0000 { 520 qupv3_id_1: geniqup@9c0000 {
986 compatible = "qcom,gen 521 compatible = "qcom,geni-se-qup";
987 reg = <0x0 0x009c0000 !! 522 reg = <0x0 0x9c0000 0x0 0x2000>;
988 clock-names = "m-ahb", 523 clock-names = "m-ahb", "s-ahb";
989 clocks = <&gcc GCC_QUP 524 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
990 <&gcc GCC_QUP 525 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
991 #address-cells = <2>; 526 #address-cells = <2>;
992 #size-cells = <2>; 527 #size-cells = <2>;
993 iommus = <&apps_smmu 0 528 iommus = <&apps_smmu 0x4c3 0x0>;
994 ranges; 529 ranges;
995 status = "disabled"; 530 status = "disabled";
996 531
997 i2c6: i2c@980000 { !! 532 uart2: serial@98c000 {
998 compatible = " <<
999 reg = <0 0x009 <<
1000 clock-names = <<
1001 clocks = <&gc <<
1002 pinctrl-names <<
1003 pinctrl-0 = < <<
1004 interrupts = <<
1005 dmas = <&gpi_ <<
1006 <&gpi_ <<
1007 dma-names = " <<
1008 #address-cell <<
1009 #size-cells = <<
1010 interconnects <<
1011 <<
1012 <<
1013 interconnect- <<
1014 status = "dis <<
1015 }; <<
1016 <<
1017 i2c7: i2c@984000 { <<
1018 compatible = <<
1019 reg = <0 0x00 <<
1020 clock-names = <<
1021 clocks = <&gc <<
1022 pinctrl-names <<
1023 pinctrl-0 = < <<
1024 interrupts = <<
1025 dmas = <&gpi_ <<
1026 <&gpi_ <<
1027 dma-names = " <<
1028 #address-cell <<
1029 #size-cells = <<
1030 interconnects <<
1031 <<
1032 <<
1033 interconnect- <<
1034 status = "dis <<
1035 }; <<
1036 <<
1037 i2c8: i2c@988000 { <<
1038 compatible = <<
1039 reg = <0 0x00 <<
1040 clock-names = <<
1041 clocks = <&gc <<
1042 pinctrl-names <<
1043 pinctrl-0 = < <<
1044 interrupts = <<
1045 dmas = <&gpi_ <<
1046 <&gpi_ <<
1047 dma-names = " <<
1048 #address-cell <<
1049 #size-cells = <<
1050 interconnects <<
1051 <<
1052 <<
1053 interconnect- <<
1054 status = "dis <<
1055 }; <<
1056 <<
1057 uart9: serial@98c000 <<
1058 compatible = 533 compatible = "qcom,geni-debug-uart";
1059 reg = <0 0x00 !! 534 reg = <0 0x98c000 0 0x4000>;
1060 clock-names = 535 clock-names = "se";
1061 clocks = <&gc 536 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1062 pinctrl-names 537 pinctrl-names = "default";
1063 pinctrl-0 = < !! 538 pinctrl-0 = <&qup_uart2_default>;
1064 interrupts = 539 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1065 interconnects <<
1066 <<
1067 interconnect- <<
1068 status = "dis 540 status = "disabled";
1069 }; 541 };
1070 <<
1071 i2c10: i2c@990000 { <<
1072 compatible = <<
1073 reg = <0 0x00 <<
1074 clock-names = <<
1075 clocks = <&gc <<
1076 pinctrl-names <<
1077 pinctrl-0 = < <<
1078 interrupts = <<
1079 dmas = <&gpi_ <<
1080 <&gpi_ <<
1081 dma-names = " <<
1082 #address-cell <<
1083 #size-cells = <<
1084 interconnects <<
1085 <<
1086 <<
1087 interconnect- <<
1088 status = "dis <<
1089 }; <<
1090 }; <<
1091 <<
1092 config_noc: interconnect@1500 <<
1093 compatible = "qcom,sm <<
1094 reg = <0 0x01500000 0 <<
1095 #interconnect-cells = <<
1096 qcom,bcm-voters = <&a <<
1097 }; <<
1098 <<
1099 system_noc: interconnect@1620 <<
1100 compatible = "qcom,sm <<
1101 reg = <0 0x01620000 0 <<
1102 #interconnect-cells = <<
1103 qcom,bcm-voters = <&a <<
1104 <<
1105 clk_virt: interconnec <<
1106 compatible = <<
1107 #interconnect <<
1108 qcom,bcm-vote <<
1109 }; <<
1110 }; <<
1111 <<
1112 aggre1_noc: interconnect@16e0 <<
1113 compatible = "qcom,sm <<
1114 reg = <0 0x016e0000 0 <<
1115 #interconnect-cells = <<
1116 qcom,bcm-voters = <&a <<
1117 }; <<
1118 <<
1119 aggre2_noc: interconnect@1700 <<
1120 compatible = "qcom,sm <<
1121 reg = <0 0x01700000 0 <<
1122 #interconnect-cells = <<
1123 qcom,bcm-voters = <&a <<
1124 <<
1125 compute_noc: intercon <<
1126 compatible = <<
1127 #interconnect <<
1128 qcom,bcm-vote <<
1129 }; <<
1130 }; <<
1131 <<
1132 mmss_noc: interconnect@174000 <<
1133 compatible = "qcom,sm <<
1134 reg = <0 0x01740000 0 <<
1135 #interconnect-cells = <<
1136 qcom,bcm-voters = <&a <<
1137 }; <<
1138 <<
1139 ufs_mem_hc: ufs@1d84000 { <<
1140 compatible = "qcom,sm <<
1141 "jedec,u <<
1142 reg = <0 0x01d84000 0 <<
1143 <0 0x01d90000 0 <<
1144 reg-names = "std", "i <<
1145 interrupts = <GIC_SPI <<
1146 phys = <&ufs_mem_phy> <<
1147 phy-names = "ufsphy"; <<
1148 lanes-per-direction = <<
1149 #reset-cells = <1>; <<
1150 resets = <&gcc GCC_UF <<
1151 reset-names = "rst"; <<
1152 <<
1153 power-domains = <&gcc <<
1154 <<
1155 iommus = <&apps_smmu <<
1156 <<
1157 clock-names = "core_c <<
1158 "bus_ag <<
1159 "iface_ <<
1160 "core_c <<
1161 "ref_cl <<
1162 "tx_lan <<
1163 "rx_lan <<
1164 "rx_lan <<
1165 "ice_co <<
1166 clocks = <&gcc GCC_UF <<
1167 <&gcc GCC_AG <<
1168 <&gcc GCC_UF <<
1169 <&gcc GCC_UF <<
1170 <&rpmhcc RPM <<
1171 <&gcc GCC_UF <<
1172 <&gcc GCC_UF <<
1173 <&gcc GCC_UF <<
1174 <&gcc GCC_UF <<
1175 freq-table-hz = <<
1176 <50000000 200 <<
1177 <0 0>, <<
1178 <0 0>, <<
1179 <37500000 150 <<
1180 <75000000 300 <<
1181 <0 0>, <<
1182 <0 0>, <<
1183 <0 0>, <<
1184 <0 0>; <<
1185 <<
1186 status = "disabled"; <<
1187 }; <<
1188 <<
1189 ufs_mem_phy: phy@1d87000 { <<
1190 compatible = "qcom,sm <<
1191 reg = <0 0x01d87000 0 <<
1192 <<
1193 clocks = <&rpmhcc RPM <<
1194 <&gcc GCC_UF <<
1195 <&gcc GCC_UF <<
1196 clock-names = "ref", <<
1197 "ref_au <<
1198 "qref"; <<
1199 <<
1200 power-domains = <&gcc <<
1201 <<
1202 resets = <&ufs_mem_hc <<
1203 reset-names = "ufsphy <<
1204 <<
1205 #phy-cells = <0>; <<
1206 <<
1207 status = "disabled"; <<
1208 }; <<
1209 <<
1210 cryptobam: dma-controller@1dc <<
1211 compatible = "qcom,ba <<
1212 reg = <0 0x01dc4000 0 <<
1213 interrupts = <GIC_SPI <<
1214 #dma-cells = <1>; <<
1215 qcom,ee = <0>; <<
1216 qcom,controlled-remot <<
1217 num-channels = <16>; <<
1218 qcom,num-ees = <4>; <<
1219 iommus = <&apps_smmu <<
1220 <&apps_smmu <<
1221 <&apps_smmu <<
1222 <&apps_smmu <<
1223 <&apps_smmu <<
1224 }; <<
1225 <<
1226 crypto: crypto@1dfa000 { <<
1227 compatible = "qcom,sm <<
1228 reg = <0 0x01dfa000 0 <<
1229 dmas = <&cryptobam 4> <<
1230 dma-names = "rx", "tx <<
1231 iommus = <&apps_smmu <<
1232 <&apps_smmu <<
1233 <&apps_smmu <<
1234 <&apps_smmu <<
1235 <&apps_smmu <<
1236 interconnects = <&agg <<
1237 &clk <<
1238 interconnect-names = <<
1239 }; <<
1240 <<
1241 ipa: ipa@1e40000 { <<
1242 compatible = "qcom,sm <<
1243 <<
1244 iommus = <&apps_smmu <<
1245 <&apps_smmu <<
1246 reg = <0 0x01e40000 0 <<
1247 <0 0x01e50000 0 <<
1248 <0 0x01e04000 0 <<
1249 reg-names = "ipa-reg" <<
1250 "ipa-shar <<
1251 "gsi"; <<
1252 <<
1253 interrupts-extended = <<
1254 <<
1255 <<
1256 <<
1257 interrupt-names = "ip <<
1258 "gs <<
1259 "ip <<
1260 "ip <<
1261 <<
1262 clocks = <&rpmhcc RPM <<
1263 clock-names = "core"; <<
1264 <<
1265 interconnects = <&agg <<
1266 <&agg <<
1267 <&gem <<
1268 interconnect-names = <<
1269 <<
1270 qcom,smem-states = <& <<
1271 <& <<
1272 qcom,smem-state-names <<
1273 <<
1274 <<
1275 status = "disabled"; <<
1276 }; 542 };
1277 543
1278 tcsr_mutex: hwlock@1f40000 { 544 tcsr_mutex: hwlock@1f40000 {
1279 compatible = "qcom,tc 545 compatible = "qcom,tcsr-mutex";
1280 reg = <0x0 0x01f40000 546 reg = <0x0 0x01f40000 0x0 0x40000>;
1281 #hwlock-cells = <1>; 547 #hwlock-cells = <1>;
1282 }; 548 };
1283 549
1284 adsp: remoteproc@3000000 { 550 adsp: remoteproc@3000000 {
1285 compatible = "qcom,sm 551 compatible = "qcom,sm6350-adsp-pas";
1286 reg = <0 0x03000000 0 552 reg = <0 0x03000000 0 0x100>;
1287 553
1288 interrupts-extended = !! 554 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1289 555 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1290 556 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1291 557 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1292 558 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1293 interrupt-names = "wd 559 interrupt-names = "wdog", "fatal", "ready",
1294 "ha 560 "handover", "stop-ack";
1295 561
1296 clocks = <&rpmhcc RPM 562 clocks = <&rpmhcc RPMH_CXO_CLK>;
1297 clock-names = "xo"; 563 clock-names = "xo";
1298 564
1299 power-domains = <&rpm 565 power-domains = <&rpmhpd SM6350_LCX>,
1300 <&rpm 566 <&rpmhpd SM6350_LMX>;
1301 power-domain-names = 567 power-domain-names = "lcx", "lmx";
1302 568
1303 memory-region = <&pil 569 memory-region = <&pil_adsp_mem>;
1304 570
1305 qcom,qmp = <&aoss_qmp 571 qcom,qmp = <&aoss_qmp>;
1306 572
1307 qcom,smem-states = <& 573 qcom,smem-states = <&smp2p_adsp_out 0>;
1308 qcom,smem-state-names 574 qcom,smem-state-names = "stop";
1309 575
1310 status = "disabled"; 576 status = "disabled";
1311 577
1312 glink-edge { 578 glink-edge {
1313 interrupts-ex 579 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1314 580 IPCC_MPROC_SIGNAL_GLINK_QMP
1315 581 IRQ_TYPE_EDGE_RISING>;
1316 mboxes = <&ip 582 mboxes = <&ipcc IPCC_CLIENT_LPASS
1317 583 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1318 584
1319 label = "lpas 585 label = "lpass";
1320 qcom,remote-p 586 qcom,remote-pid = <2>;
1321 587
1322 fastrpc { 588 fastrpc {
1323 compa 589 compatible = "qcom,fastrpc";
1324 qcom, 590 qcom,glink-channels = "fastrpcglink-apps-dsp";
1325 label 591 label = "adsp";
1326 qcom, <<
1327 #addr 592 #address-cells = <1>;
1328 #size 593 #size-cells = <0>;
1329 594
1330 compu 595 compute-cb@3 {
1331 596 compatible = "qcom,fastrpc-compute-cb";
1332 597 reg = <3>;
1333 598 iommus = <&apps_smmu 0x1003 0x0>;
1334 }; 599 };
1335 600
1336 compu 601 compute-cb@4 {
1337 602 compatible = "qcom,fastrpc-compute-cb";
1338 603 reg = <4>;
1339 604 iommus = <&apps_smmu 0x1004 0x0>;
1340 }; 605 };
1341 606
1342 compu 607 compute-cb@5 {
1343 608 compatible = "qcom,fastrpc-compute-cb";
1344 609 reg = <5>;
1345 610 iommus = <&apps_smmu 0x1005 0x0>;
1346 611 qcom,nsessions = <5>;
1347 }; 612 };
1348 }; 613 };
1349 }; 614 };
1350 }; 615 };
1351 616
1352 gpu: gpu@3d00000 { <<
1353 compatible = "qcom,ad <<
1354 reg = <0 0x03d00000 0 <<
1355 <0 0x03d9e000 0 <<
1356 reg-names = "kgsl_3d0 <<
1357 "cx_mem"; <<
1358 interrupts = <GIC_SPI <<
1359 <<
1360 iommus = <&adreno_smm <<
1361 operating-points-v2 = <<
1362 qcom,gmu = <&gmu>; <<
1363 nvmem-cells = <&gpu_s <<
1364 nvmem-cell-names = "s <<
1365 #cooling-cells = <2>; <<
1366 <<
1367 status = "disabled"; <<
1368 <<
1369 gpu_zap_shader: zap-s <<
1370 memory-region <<
1371 }; <<
1372 <<
1373 gpu_opp_table: opp-ta <<
1374 compatible = <<
1375 <<
1376 opp-850000000 <<
1377 opp-h <<
1378 opp-l <<
1379 opp-s <<
1380 }; <<
1381 <<
1382 opp-800000000 <<
1383 opp-h <<
1384 opp-l <<
1385 opp-s <<
1386 }; <<
1387 <<
1388 opp-650000000 <<
1389 opp-h <<
1390 opp-l <<
1391 opp-s <<
1392 }; <<
1393 <<
1394 opp-565000000 <<
1395 opp-h <<
1396 opp-l <<
1397 opp-s <<
1398 }; <<
1399 <<
1400 opp-430000000 <<
1401 opp-h <<
1402 opp-l <<
1403 opp-s <<
1404 }; <<
1405 <<
1406 opp-355000000 <<
1407 opp-h <<
1408 opp-l <<
1409 opp-s <<
1410 }; <<
1411 <<
1412 opp-253000000 <<
1413 opp-h <<
1414 opp-l <<
1415 opp-s <<
1416 }; <<
1417 }; <<
1418 }; <<
1419 <<
1420 adreno_smmu: iommu@3d40000 { <<
1421 compatible = "qcom,sm <<
1422 reg = <0 0x03d40000 0 <<
1423 #iommu-cells = <1>; <<
1424 #global-interrupts = <<
1425 interrupts = <GIC_SPI <<
1426 <GIC_SPI <<
1427 <GIC_SPI <<
1428 <GIC_SPI <<
1429 <GIC_SPI <<
1430 <GIC_SPI <<
1431 <GIC_SPI <<
1432 <GIC_SPI <<
1433 <GIC_SPI <<
1434 <GIC_SPI <<
1435 <<
1436 clocks = <&gpucc GPU_ <<
1437 <&gcc GCC_GP <<
1438 <&gcc GCC_GP <<
1439 clock-names = "ahb", <<
1440 "bus", <<
1441 "iface" <<
1442 <<
1443 power-domains = <&gpu <<
1444 }; <<
1445 <<
1446 gmu: gmu@3d6a000 { <<
1447 compatible = "qcom,ad <<
1448 reg = <0 0x03d6a000 0 <<
1449 <0 0x0b290000 0 <<
1450 <0 0x0b490000 0 <<
1451 reg-names = "gmu", <<
1452 "gmu_pdc" <<
1453 "gmu_pdc_ <<
1454 <<
1455 interrupts = <GIC_SPI <<
1456 <GIC_SPI <<
1457 interrupt-names = "hf <<
1458 "gm <<
1459 <<
1460 clocks = <&gpucc GPU_ <<
1461 <&gpucc GPU_ <<
1462 <&gpucc GPU_ <<
1463 <&gcc GCC_DD <<
1464 <&gcc GCC_GP <<
1465 clock-names = "ahb", <<
1466 "gmu", <<
1467 "cxo", <<
1468 "axi", <<
1469 "memnoc <<
1470 <<
1471 power-domains = <&gpu <<
1472 <&gpu <<
1473 power-domain-names = <<
1474 <<
1475 <<
1476 iommus = <&adreno_smm <<
1477 <<
1478 operating-points-v2 = <<
1479 <<
1480 gmu_opp_table: opp-ta <<
1481 compatible = <<
1482 <<
1483 opp-200000000 <<
1484 opp-h <<
1485 opp-l <<
1486 }; <<
1487 }; <<
1488 }; <<
1489 <<
1490 gpucc: clock-controller@3d900 <<
1491 compatible = "qcom,sm <<
1492 reg = <0 0x03d90000 0 <<
1493 clocks = <&rpmhcc RPM <<
1494 <&gcc GCC_GP <<
1495 <&gcc GCC_GP <<
1496 clock-names = "bi_tcx <<
1497 "gcc_gp <<
1498 "gcc_gp <<
1499 #clock-cells = <1>; <<
1500 #reset-cells = <1>; <<
1501 #power-domain-cells = <<
1502 }; <<
1503 <<
1504 mpss: remoteproc@4080000 { 617 mpss: remoteproc@4080000 {
1505 compatible = "qcom,sm 618 compatible = "qcom,sm6350-mpss-pas";
1506 reg = <0x0 0x04080000 619 reg = <0x0 0x04080000 0x0 0x4040>;
1507 620
1508 interrupts-extended = 621 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1509 622 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1510 623 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1511 624 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1512 625 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1513 626 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1514 interrupt-names = "wd 627 interrupt-names = "wdog", "fatal", "ready", "handover",
1515 "st 628 "stop-ack", "shutdown-ack";
1516 629
1517 clocks = <&rpmhcc RPM 630 clocks = <&rpmhcc RPMH_CXO_CLK>;
1518 clock-names = "xo"; 631 clock-names = "xo";
1519 632
1520 power-domains = <&rpm 633 power-domains = <&rpmhpd SM6350_CX>,
1521 <&rpm 634 <&rpmhpd SM6350_MSS>;
1522 power-domain-names = 635 power-domain-names = "cx", "mss";
1523 636
1524 memory-region = <&pil 637 memory-region = <&pil_modem_mem>;
1525 638
1526 qcom,qmp = <&aoss_qmp 639 qcom,qmp = <&aoss_qmp>;
1527 640
1528 qcom,smem-states = <& 641 qcom,smem-states = <&modem_smp2p_out 0>;
1529 qcom,smem-state-names 642 qcom,smem-state-names = "stop";
1530 643
1531 status = "disabled"; 644 status = "disabled";
1532 645
1533 glink-edge { 646 glink-edge {
1534 interrupts-ex 647 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1535 648 IPCC_MPROC_SIGNAL_GLINK_QMP
1536 649 IRQ_TYPE_EDGE_RISING>;
1537 mboxes = <&ip 650 mboxes = <&ipcc IPCC_CLIENT_MPSS
1538 651 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1539 label = "mode 652 label = "modem";
1540 qcom,remote-p 653 qcom,remote-pid = <1>;
1541 }; 654 };
1542 }; 655 };
1543 656
1544 cdsp: remoteproc@8300000 { 657 cdsp: remoteproc@8300000 {
1545 compatible = "qcom,sm 658 compatible = "qcom,sm6350-cdsp-pas";
1546 reg = <0 0x08300000 0 659 reg = <0 0x08300000 0 0x10000>;
1547 660
1548 interrupts-extended = !! 661 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1549 662 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1550 663 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1551 664 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1552 665 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1553 interrupt-names = "wd 666 interrupt-names = "wdog", "fatal", "ready",
1554 "ha 667 "handover", "stop-ack";
1555 668
1556 clocks = <&rpmhcc RPM 669 clocks = <&rpmhcc RPMH_CXO_CLK>;
1557 clock-names = "xo"; 670 clock-names = "xo";
1558 671
1559 power-domains = <&rpm 672 power-domains = <&rpmhpd SM6350_CX>,
1560 <&rpm 673 <&rpmhpd SM6350_MX>;
1561 power-domain-names = 674 power-domain-names = "cx", "mx";
1562 675
1563 memory-region = <&pil 676 memory-region = <&pil_cdsp_mem>;
1564 677
1565 qcom,qmp = <&aoss_qmp 678 qcom,qmp = <&aoss_qmp>;
1566 679
1567 qcom,smem-states = <& 680 qcom,smem-states = <&smp2p_cdsp_out 0>;
1568 qcom,smem-state-names 681 qcom,smem-state-names = "stop";
1569 682
1570 status = "disabled"; 683 status = "disabled";
1571 684
1572 glink-edge { 685 glink-edge {
1573 interrupts-ex 686 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1574 687 IPCC_MPROC_SIGNAL_GLINK_QMP
1575 688 IRQ_TYPE_EDGE_RISING>;
1576 mboxes = <&ip 689 mboxes = <&ipcc IPCC_CLIENT_CDSP
1577 690 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1578 691
1579 label = "cdsp 692 label = "cdsp";
1580 qcom,remote-p 693 qcom,remote-pid = <5>;
1581 694
1582 fastrpc { 695 fastrpc {
1583 compa 696 compatible = "qcom,fastrpc";
1584 qcom, 697 qcom,glink-channels = "fastrpcglink-apps-dsp";
1585 label 698 label = "cdsp";
1586 qcom, <<
1587 #addr 699 #address-cells = <1>;
1588 #size 700 #size-cells = <0>;
1589 701
1590 compu 702 compute-cb@1 {
1591 703 compatible = "qcom,fastrpc-compute-cb";
1592 704 reg = <1>;
1593 705 iommus = <&apps_smmu 0x1401 0x20>;
1594 }; 706 };
1595 707
1596 compu 708 compute-cb@2 {
1597 709 compatible = "qcom,fastrpc-compute-cb";
1598 710 reg = <2>;
1599 711 iommus = <&apps_smmu 0x1402 0x20>;
1600 }; 712 };
1601 713
1602 compu 714 compute-cb@3 {
1603 715 compatible = "qcom,fastrpc-compute-cb";
1604 716 reg = <3>;
1605 717 iommus = <&apps_smmu 0x1403 0x20>;
1606 }; 718 };
1607 719
1608 compu 720 compute-cb@4 {
1609 721 compatible = "qcom,fastrpc-compute-cb";
1610 722 reg = <4>;
1611 723 iommus = <&apps_smmu 0x1404 0x20>;
1612 }; 724 };
1613 725
1614 compu 726 compute-cb@5 {
1615 727 compatible = "qcom,fastrpc-compute-cb";
1616 728 reg = <5>;
1617 729 iommus = <&apps_smmu 0x1405 0x20>;
1618 }; 730 };
1619 731
1620 compu 732 compute-cb@6 {
1621 733 compatible = "qcom,fastrpc-compute-cb";
1622 734 reg = <6>;
1623 735 iommus = <&apps_smmu 0x1406 0x20>;
1624 }; 736 };
1625 737
1626 compu 738 compute-cb@7 {
1627 739 compatible = "qcom,fastrpc-compute-cb";
1628 740 reg = <7>;
1629 741 iommus = <&apps_smmu 0x1407 0x20>;
1630 }; 742 };
1631 743
1632 compu 744 compute-cb@8 {
1633 745 compatible = "qcom,fastrpc-compute-cb";
1634 746 reg = <8>;
1635 747 iommus = <&apps_smmu 0x1408 0x20>;
1636 }; 748 };
1637 749
1638 /* no 750 /* note: secure cb9 in downstream */
1639 }; 751 };
1640 }; 752 };
1641 }; 753 };
1642 754
1643 sdhc_2: mmc@8804000 { !! 755 sdhc_2: sdhci@8804000 {
1644 compatible = "qcom,sm 756 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1645 reg = <0 0x08804000 0 757 reg = <0 0x08804000 0 0x1000>;
1646 758
1647 interrupts = <GIC_SPI 759 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 760 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1649 interrupt-names = "hc 761 interrupt-names = "hc_irq", "pwr_irq";
1650 iommus = <&apps_smmu <<
1651 762
1652 clocks = <&gcc GCC_SD 763 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1653 <&gcc GCC_SD 764 <&gcc GCC_SDCC2_APPS_CLK>,
1654 <&rpmhcc RPM 765 <&rpmhcc RPMH_CXO_CLK>;
1655 clock-names = "iface" 766 clock-names = "iface", "core", "xo";
1656 resets = <&gcc GCC_SD <<
1657 interconnects = <&agg <<
1658 <&gem <<
1659 interconnect-names = <<
1660 <<
1661 pinctrl-0 = <&sdc2_on <<
1662 pinctrl-1 = <&sdc2_of <<
1663 pinctrl-names = "defa <<
1664 <<
1665 qcom,dll-config = <0x 767 qcom,dll-config = <0x0007642c>;
1666 qcom,ddr-config = <0x 768 qcom,ddr-config = <0x80040868>;
1667 power-domains = <&rpm !! 769 power-domains = <&rpmhpd 0>;
1668 operating-points-v2 = 770 operating-points-v2 = <&sdhc2_opp_table>;
1669 bus-width = <4>; 771 bus-width = <4>;
1670 772
1671 status = "disabled"; 773 status = "disabled";
1672 774
1673 sdhc2_opp_table: opp- !! 775 sdhc2_opp_table: sdhc2-opp-table {
1674 compatible = 776 compatible = "operating-points-v2";
1675 777
1676 opp-100000000 778 opp-100000000 {
1677 opp-h 779 opp-hz = /bits/ 64 <100000000>;
1678 requi 780 required-opps = <&rpmhpd_opp_svs_l1>;
1679 opp-p <<
1680 opp-a <<
1681 }; 781 };
1682 782
1683 opp-202000000 783 opp-202000000 {
1684 opp-h 784 opp-hz = /bits/ 64 <202000000>;
1685 requi 785 required-opps = <&rpmhpd_opp_nom>;
1686 opp-p <<
1687 opp-a <<
1688 }; 786 };
1689 }; 787 };
1690 }; 788 };
1691 789
1692 usb_1_hsphy: phy@88e3000 { 790 usb_1_hsphy: phy@88e3000 {
1693 compatible = "qcom,sm 791 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1694 reg = <0 0x088e3000 0 792 reg = <0 0x088e3000 0 0x400>;
1695 status = "disabled"; 793 status = "disabled";
1696 #phy-cells = <0>; 794 #phy-cells = <0>;
1697 795
1698 clocks = <&xo_board>, 796 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
1699 clock-names = "cfg_ah 797 clock-names = "cfg_ahb", "ref";
1700 798
1701 resets = <&gcc GCC_QU 799 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1702 }; 800 };
1703 801
1704 usb_1_qmpphy: phy@88e8000 { !! 802 usb_1_qmpphy: phy@88e9000 {
1705 compatible = "qcom,sm !! 803 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
1706 reg = <0 0x088e8000 0 !! 804 reg = <0 0x088e9000 0 0x200>,
>> 805 <0 0x088e8000 0 0x40>,
>> 806 <0 0x088ea000 0 0x200>;
>> 807 status = "disabled";
>> 808 #address-cells = <2>;
>> 809 #size-cells = <2>;
>> 810 ranges;
1707 811
1708 clocks = <&gcc GCC_US 812 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1709 <&gcc GCC_US !! 813 <&xo_board>,
1710 <&gcc GCC_US !! 814 <&rpmhcc RPMH_QLINK_CLK>,
1711 <&gcc GCC_US !! 815 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1712 clock-names = "aux", !! 816 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1713 <<
1714 power-domains = <&gcc <<
1715 817
1716 resets = <&gcc GCC_US !! 818 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1717 <&gcc GCC_US !! 819 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1718 reset-names = "phy", 820 reset-names = "phy", "common";
1719 821
1720 orientation-switch; !! 822 usb_1_ssphy: usb3-phy@88e9200 {
1721 !! 823 reg = <0 0x088e9200 0 0x200>,
1722 #clock-cells = <1>; !! 824 <0 0x088e9400 0 0x200>,
1723 #phy-cells = <1>; !! 825 <0 0x088e9c00 0 0x400>,
1724 !! 826 <0 0x088e9600 0 0x200>,
1725 status = "disabled"; !! 827 <0 0x088e9800 0 0x200>,
1726 !! 828 <0 0x088e9a00 0 0x100>;
1727 ports { !! 829 #clock-cells = <0>;
1728 #address-cell !! 830 #phy-cells = <0>;
1729 #size-cells = !! 831 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1730 !! 832 clock-names = "pipe0";
1731 port@0 { !! 833 clock-output-names = "usb3_phy_pipe_clk_src";
1732 reg = <<
1733 <<
1734 usb_1 <<
1735 }; <<
1736 }; <<
1737 <<
1738 port@1 { <<
1739 reg = <<
1740 <<
1741 usb_1 <<
1742 <<
1743 }; <<
1744 }; <<
1745 <<
1746 port@2 { <<
1747 reg = <<
1748 <<
1749 usb_1 <<
1750 }; <<
1751 }; <<
1752 }; 834 };
1753 }; <<
1754 835
1755 dc_noc: interconnect@9160000 !! 836 dp_phy: dp-phy@88ea200 {
1756 compatible = "qcom,sm !! 837 reg = <0 0x088ea200 0 0x200>,
1757 reg = <0 0x09160000 0 !! 838 <0 0x088ea400 0 0x200>,
1758 #interconnect-cells = !! 839 <0 0x088eac00 0 0x400>,
1759 qcom,bcm-voters = <&a !! 840 <0 0x088ea600 0 0x200>,
>> 841 <0 0x088ea800 0 0x200>,
>> 842 <0 0x088eaa00 0 0x100>;
>> 843 #phy-cells = <0>;
>> 844 #clock-cells = <1>;
>> 845 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 846 clock-names = "pipe0";
>> 847 clock-output-names = "usb3_phy_pipe_clk_src";
>> 848 };
1760 }; 849 };
1761 850
1762 system-cache-controller@92000 851 system-cache-controller@9200000 {
1763 compatible = "qcom,sm 852 compatible = "qcom,sm6350-llcc";
1764 reg = <0 0x09200000 0 853 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
1765 reg-names = "llcc0_ba !! 854 reg-names = "llcc_base", "llcc_broadcast_base";
1766 }; <<
1767 <<
1768 gem_noc: interconnect@9680000 <<
1769 compatible = "qcom,sm <<
1770 reg = <0 0x09680000 0 <<
1771 #interconnect-cells = <<
1772 qcom,bcm-voters = <&a <<
1773 }; <<
1774 <<
1775 npu_noc: interconnect@9990000 <<
1776 compatible = "qcom,sm <<
1777 reg = <0 0x09990000 0 <<
1778 #interconnect-cells = <<
1779 qcom,bcm-voters = <&a <<
1780 }; <<
1781 <<
1782 pmu@90b6300 { <<
1783 compatible = "qcom,sm <<
1784 reg = <0x0 0x090b6300 <<
1785 interrupts = <GIC_SPI <<
1786 <<
1787 operating-points-v2 = <<
1788 interconnects = <&clk <<
1789 &clk <<
1790 <<
1791 llcc_bwmon_opp_table: <<
1792 compatible = <<
1793 <<
1794 opp-0 { <<
1795 opp-p <<
1796 }; <<
1797 <<
1798 opp-1 { <<
1799 opp-p <<
1800 }; <<
1801 <<
1802 opp-2 { <<
1803 opp-p <<
1804 }; <<
1805 <<
1806 opp-3 { <<
1807 opp-p <<
1808 }; <<
1809 <<
1810 opp-4 { <<
1811 opp-p <<
1812 }; <<
1813 <<
1814 opp-5 { <<
1815 opp-p <<
1816 }; <<
1817 <<
1818 }; <<
1819 }; <<
1820 <<
1821 pmu@90cd000 { <<
1822 compatible = "qcom,sm <<
1823 reg = <0x0 0x090cd000 <<
1824 interrupts = <GIC_SPI <<
1825 <<
1826 operating-points-v2 = <<
1827 interconnects = <&gem <<
1828 &clk <<
1829 <<
1830 cpu_bwmon_opp_table: <<
1831 compatible = <<
1832 <<
1833 opp-0 { <<
1834 opp-p <<
1835 }; <<
1836 <<
1837 opp-1 { <<
1838 opp-p <<
1839 }; <<
1840 <<
1841 opp-2 { <<
1842 opp-p <<
1843 }; <<
1844 <<
1845 opp-3 { <<
1846 opp-p <<
1847 }; <<
1848 <<
1849 opp-4 { <<
1850 opp-p <<
1851 }; <<
1852 <<
1853 opp-5 { <<
1854 opp-p <<
1855 }; <<
1856 <<
1857 opp-6 { <<
1858 opp-p <<
1859 }; <<
1860 <<
1861 opp-7 { <<
1862 opp-p <<
1863 }; <<
1864 <<
1865 opp-8 { <<
1866 opp-p <<
1867 }; <<
1868 <<
1869 opp-9 { <<
1870 opp-p <<
1871 }; <<
1872 <<
1873 opp-10 { <<
1874 opp-p <<
1875 }; <<
1876 }; <<
1877 }; 855 };
1878 856
1879 usb_1: usb@a6f8800 { 857 usb_1: usb@a6f8800 {
1880 compatible = "qcom,sm 858 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1881 reg = <0 0x0a6f8800 0 859 reg = <0 0x0a6f8800 0 0x400>;
1882 status = "disabled"; 860 status = "disabled";
1883 #address-cells = <2>; 861 #address-cells = <2>;
1884 #size-cells = <2>; 862 #size-cells = <2>;
1885 ranges; 863 ranges;
1886 864
1887 clocks = <&gcc GCC_CF 865 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1888 <&gcc GCC_US 866 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1889 <&gcc GCC_AG 867 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1890 <&gcc GCC_US !! 868 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1891 <&gcc GCC_US !! 869 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1892 clock-names = "cfg_no !! 870 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1893 "core", !! 871 "sleep";
1894 "iface" <<
1895 "sleep" <<
1896 "mock_u <<
1897 872
1898 interrupts-extended = 873 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1899 !! 874 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
1900 <<
1901 875 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
1902 !! 876 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
1903 interrupt-names = "pw !! 877
1904 "hs !! 878 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1905 "dp !! 879 "dm_hs_phy_irq", "dp_hs_phy_irq";
1906 "dm <<
1907 "ss <<
1908 880
1909 power-domains = <&gcc 881 power-domains = <&gcc USB30_PRIM_GDSC>;
1910 882
1911 resets = <&gcc GCC_US 883 resets = <&gcc GCC_USB30_PRIM_BCR>;
1912 884
1913 interconnects = <&agg <<
1914 <&gem <<
1915 interconnect-names = <<
1916 <<
1917 usb_1_dwc3: usb@a6000 885 usb_1_dwc3: usb@a600000 {
1918 compatible = 886 compatible = "snps,dwc3";
1919 reg = <0 0x0a 887 reg = <0 0x0a600000 0 0xcd00>;
1920 interrupts = 888 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1921 iommus = <&ap 889 iommus = <&apps_smmu 0x540 0x0>;
1922 snps,dis_u2_s 890 snps,dis_u2_susphy_quirk;
1923 snps,dis_enbl 891 snps,dis_enblslpm_quirk;
1924 snps,has-lpm- 892 snps,has-lpm-erratum;
1925 snps,hird-thr 893 snps,hird-threshold = /bits/ 8 <0x10>;
1926 snps,parkmode !! 894 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1927 phys = <&usb_ <<
1928 phy-names = " 895 phy-names = "usb2-phy", "usb3-phy";
1929 usb-role-swit <<
1930 <<
1931 ports { <<
1932 #addr <<
1933 #size <<
1934 <<
1935 port@ <<
1936 <<
1937 <<
1938 <<
1939 <<
1940 }; <<
1941 <<
1942 port@ <<
1943 <<
1944 <<
1945 <<
1946 <<
1947 <<
1948 }; <<
1949 }; <<
1950 }; <<
1951 }; <<
1952 <<
1953 cci0: cci@ac4a000 { <<
1954 compatible = "qcom,sm <<
1955 reg = <0 0x0ac4a000 0 <<
1956 interrupts = <GIC_SPI <<
1957 power-domains = <&cam <<
1958 <<
1959 clocks = <&camcc CAMC <<
1960 <&camcc CAMC <<
1961 <&camcc CAMC <<
1962 <&camcc CAMC <<
1963 <&camcc CAMC <<
1964 <&camcc CAMC <<
1965 clock-names = "camnoc <<
1966 "soc_ah <<
1967 "slow_a <<
1968 "cpas_a <<
1969 "cci", <<
1970 "cci_sr <<
1971 <<
1972 assigned-clocks = <&c <<
1973 <&c <<
1974 assigned-clock-rates <<
1975 <<
1976 pinctrl-0 = <&cci0_de <<
1977 pinctrl-1 = <&cci0_sl <<
1978 pinctrl-names = "defa <<
1979 <<
1980 #address-cells = <1>; <<
1981 #size-cells = <0>; <<
1982 <<
1983 status = "disabled"; <<
1984 <<
1985 cci0_i2c0: i2c-bus@0 <<
1986 reg = <0>; <<
1987 clock-frequen <<
1988 #address-cell <<
1989 #size-cells = <<
1990 }; <<
1991 <<
1992 cci0_i2c1: i2c-bus@1 <<
1993 reg = <1>; <<
1994 clock-frequen <<
1995 #address-cell <<
1996 #size-cells = <<
1997 }; <<
1998 }; <<
1999 <<
2000 cci1: cci@ac4b000 { <<
2001 compatible = "qcom,sm <<
2002 reg = <0 0x0ac4b000 0 <<
2003 interrupts = <GIC_SPI <<
2004 power-domains = <&cam <<
2005 <<
2006 clocks = <&camcc CAMC <<
2007 <&camcc CAMC <<
2008 <&camcc CAMC <<
2009 <&camcc CAMC <<
2010 <&camcc CAMC <<
2011 <&camcc CAMC <<
2012 clock-names = "camnoc <<
2013 "soc_ah <<
2014 "slow_a <<
2015 "cpas_a <<
2016 "cci", <<
2017 "cci_sr <<
2018 <<
2019 assigned-clocks = <&c <<
2020 <&c <<
2021 assigned-clock-rates <<
2022 <<
2023 pinctrl-0 = <&cci2_de <<
2024 pinctrl-1 = <&cci2_sl <<
2025 pinctrl-names = "defa <<
2026 <<
2027 #address-cells = <1>; <<
2028 #size-cells = <0>; <<
2029 <<
2030 status = "disabled"; <<
2031 <<
2032 cci1_i2c0: i2c-bus@0 <<
2033 reg = <0>; <<
2034 clock-frequen <<
2035 #address-cell <<
2036 #size-cells = <<
2037 }; <<
2038 <<
2039 /* SM6350 seems to ha <<
2040 }; <<
2041 <<
2042 camcc: clock-controller@ad000 <<
2043 compatible = "qcom,sm <<
2044 reg = <0 0x0ad00000 0 <<
2045 clocks = <&rpmhcc RPM <<
2046 #clock-cells = <1>; <<
2047 #reset-cells = <1>; <<
2048 #power-domain-cells = <<
2049 }; <<
2050 <<
2051 mdss: display-subsystem@ae000 <<
2052 compatible = "qcom,sm <<
2053 reg = <0 0x0ae00000 0 <<
2054 reg-names = "mdss"; <<
2055 <<
2056 interrupts = <GIC_SPI <<
2057 interrupt-controller; <<
2058 #interrupt-cells = <1 <<
2059 <<
2060 interconnects = <&mms <<
2061 &clk <<
2062 <&gem <<
2063 &con <<
2064 interconnect-names = <<
2065 <<
2066 <<
2067 clocks = <&gcc GCC_DI <<
2068 <&gcc GCC_DI <<
2069 <&dispcc DIS <<
2070 clock-names = "iface" <<
2071 "bus", <<
2072 "core"; <<
2073 <<
2074 power-domains = <&dis <<
2075 iommus = <&apps_smmu <<
2076 <<
2077 #address-cells = <2>; <<
2078 #size-cells = <2>; <<
2079 ranges; <<
2080 <<
2081 status = "disabled"; <<
2082 <<
2083 mdss_mdp: display-con <<
2084 compatible = <<
2085 reg = <0 0x0a <<
2086 <0 0x0a <<
2087 reg-names = " <<
2088 <<
2089 interrupt-par <<
2090 interrupts = <<
2091 <<
2092 clocks = <&gc <<
2093 <&di <<
2094 <&di <<
2095 <&di <<
2096 <&di <<
2097 <&di <<
2098 clock-names = <<
2099 <<
2100 <<
2101 <<
2102 <<
2103 <<
2104 <<
2105 assigned-cloc <<
2106 assigned-cloc <<
2107 <<
2108 operating-poi <<
2109 power-domains <<
2110 <<
2111 ports { <<
2112 #addr <<
2113 #size <<
2114 <<
2115 port@ <<
2116 <<
2117 <<
2118 <<
2119 <<
2120 <<
2121 }; <<
2122 <<
2123 port@ <<
2124 <<
2125 <<
2126 <<
2127 <<
2128 <<
2129 }; <<
2130 }; <<
2131 <<
2132 mdp_opp_table <<
2133 compa <<
2134 <<
2135 opp-1 <<
2136 <<
2137 <<
2138 }; <<
2139 <<
2140 opp-2 <<
2141 <<
2142 <<
2143 }; <<
2144 <<
2145 opp-3 <<
2146 <<
2147 <<
2148 }; <<
2149 <<
2150 opp-3 <<
2151 <<
2152 <<
2153 }; <<
2154 <<
2155 opp-4 <<
2156 <<
2157 <<
2158 }; <<
2159 <<
2160 opp-5 <<
2161 <<
2162 <<
2163 }; <<
2164 }; <<
2165 }; 896 };
2166 <<
2167 mdss_dp: displayport- <<
2168 compatible = <<
2169 reg = <0 0xae <<
2170 <0 0xae <<
2171 <0 0xae <<
2172 <0 0xae <<
2173 <0 0xae <<
2174 interrupt-par <<
2175 interrupts = <<
2176 clocks = <&di <<
2177 <&di <<
2178 <&di <<
2179 <&di <<
2180 <&di <<
2181 clock-names = <<
2182 <<
2183 <<
2184 <<
2185 <<
2186 <<
2187 assigned-cloc <<
2188 <<
2189 assigned-cloc <<
2190 <<
2191 <<
2192 phys = <&usb_ <<
2193 phy-names = " <<
2194 <<
2195 #sound-dai-ce <<
2196 <<
2197 operating-poi <<
2198 power-domains <<
2199 <<
2200 status = "dis <<
2201 <<
2202 ports { <<
2203 #addr <<
2204 #size <<
2205 <<
2206 port@ <<
2207 <<
2208 <<
2209 <<
2210 <<
2211 <<
2212 }; <<
2213 <<
2214 port@ <<
2215 <<
2216 <<
2217 <<
2218 <<
2219 }; <<
2220 }; <<
2221 <<
2222 dp_opp_table: <<
2223 compa <<
2224 <<
2225 opp-1 <<
2226 <<
2227 <<
2228 }; <<
2229 <<
2230 opp-2 <<
2231 <<
2232 <<
2233 }; <<
2234 <<
2235 opp-5 <<
2236 <<
2237 <<
2238 }; <<
2239 <<
2240 opp-8 <<
2241 <<
2242 <<
2243 }; <<
2244 }; <<
2245 }; <<
2246 <<
2247 mdss_dsi0: dsi@ae9400 <<
2248 compatible = <<
2249 reg = <0 0x0a <<
2250 reg-names = " <<
2251 <<
2252 interrupt-par <<
2253 interrupts = <<
2254 <<
2255 clocks = <&di <<
2256 <&di <<
2257 <&di <<
2258 <&di <<
2259 <&di <<
2260 <&gc <<
2261 clock-names = <<
2262 <<
2263 <<
2264 <<
2265 <<
2266 <<
2267 <<
2268 assigned-cloc <<
2269 <<
2270 assigned-cloc <<
2271 <<
2272 operating-poi <<
2273 power-domains <<
2274 <<
2275 phys = <&mdss <<
2276 phy-names = " <<
2277 <<
2278 #address-cell <<
2279 #size-cells = <<
2280 <<
2281 status = "dis <<
2282 <<
2283 ports { <<
2284 #addr <<
2285 #size <<
2286 <<
2287 port@ <<
2288 <<
2289 <<
2290 <<
2291 <<
2292 <<
2293 }; <<
2294 <<
2295 port@ <<
2296 <<
2297 <<
2298 <<
2299 <<
2300 }; <<
2301 }; <<
2302 <<
2303 mdss_dsi_opp_ <<
2304 compa <<
2305 <<
2306 opp-1 <<
2307 <<
2308 <<
2309 }; <<
2310 <<
2311 opp-3 <<
2312 <<
2313 <<
2314 }; <<
2315 <<
2316 opp-3 <<
2317 <<
2318 <<
2319 }; <<
2320 }; <<
2321 }; <<
2322 <<
2323 mdss_dsi0_phy: phy@ae <<
2324 compatible = <<
2325 reg = <0 0x0a <<
2326 <0 0x0a <<
2327 <0 0x0a <<
2328 reg-names = " <<
2329 " <<
2330 " <<
2331 <<
2332 #clock-cells <<
2333 #phy-cells = <<
2334 <<
2335 clocks = <&di <<
2336 <&rp <<
2337 clock-names = <<
2338 <<
2339 status = "dis <<
2340 }; <<
2341 }; <<
2342 <<
2343 dispcc: clock-controller@af00 <<
2344 compatible = "qcom,sm <<
2345 reg = <0 0x0af00000 0 <<
2346 clocks = <&rpmhcc RPM <<
2347 <&gcc GCC_DI <<
2348 <&mdss_dsi0_ <<
2349 <&mdss_dsi0_ <<
2350 <&usb_1_qmpp <<
2351 <&usb_1_qmpp <<
2352 clock-names = "bi_tcx <<
2353 "gcc_di <<
2354 "dsi0_p <<
2355 "dsi0_p <<
2356 "dp_phy <<
2357 "dp_phy <<
2358 #clock-cells = <1>; <<
2359 #reset-cells = <1>; <<
2360 #power-domain-cells = <<
2361 }; 897 };
2362 898
2363 pdc: interrupt-controller@b22 899 pdc: interrupt-controller@b220000 {
2364 compatible = "qcom,sm 900 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2365 reg = <0 0x0b220000 0 901 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
2366 qcom,pdc-ranges = <0 902 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2367 <12 903 <125 63 1>, <126 655 12>, <138 139 15>;
2368 #interrupt-cells = <2 904 #interrupt-cells = <2>;
2369 interrupt-parent = <& 905 interrupt-parent = <&intc>;
2370 interrupt-controller; 906 interrupt-controller;
2371 }; 907 };
2372 908
2373 tsens0: thermal-sensor@c26300 909 tsens0: thermal-sensor@c263000 {
2374 compatible = "qcom,sm 910 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2375 reg = <0 0x0c263000 0 911 reg = <0 0x0c263000 0 0x1ff>, /* TM */
2376 <0 0x0c222000 0 912 <0 0x0c222000 0 0x8>; /* SROT */
2377 #qcom,sensors = <16>; 913 #qcom,sensors = <16>;
2378 interrupts-extended = 914 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2379 <&pdc 28 915 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
2380 interrupt-names = "up 916 interrupt-names = "uplow", "critical";
2381 #thermal-sensor-cells 917 #thermal-sensor-cells = <1>;
2382 }; 918 };
2383 919
2384 tsens1: thermal-sensor@c26500 920 tsens1: thermal-sensor@c265000 {
2385 compatible = "qcom,sm 921 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2386 reg = <0 0x0c265000 0 922 reg = <0 0x0c265000 0 0x1ff>, /* TM */
2387 <0 0x0c223000 0 923 <0 0x0c223000 0 0x8>; /* SROT */
2388 #qcom,sensors = <16>; 924 #qcom,sensors = <16>;
2389 interrupts-extended = 925 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2390 <&pdc 29 926 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
2391 interrupt-names = "up 927 interrupt-names = "uplow", "critical";
2392 #thermal-sensor-cells 928 #thermal-sensor-cells = <1>;
2393 }; 929 };
2394 930
2395 aoss_qmp: power-management@c3 !! 931 aoss_qmp: power-controller@c300000 {
2396 compatible = "qcom,sm 932 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2397 reg = <0 0x0c300000 0 933 reg = <0 0x0c300000 0 0x1000>;
2398 interrupts-extended = 934 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2399 935 IRQ_TYPE_EDGE_RISING>;
2400 mboxes = <&ipcc IPCC_ 936 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
2401 937
2402 #clock-cells = <0>; 938 #clock-cells = <0>;
2403 }; 939 };
2404 940
2405 spmi_bus: spmi@c440000 { 941 spmi_bus: spmi@c440000 {
2406 compatible = "qcom,sp 942 compatible = "qcom,spmi-pmic-arb";
2407 reg = <0 0x0c440000 0 !! 943 reg = <0 0xc440000 0 0x1100>,
2408 <0 0x0c600000 0 !! 944 <0 0xc600000 0 0x2000000>,
2409 <0 0x0e600000 0 !! 945 <0 0xe600000 0 0x100000>,
2410 <0 0x0e700000 0 !! 946 <0 0xe700000 0 0xa0000>,
2411 <0 0x0c40a000 0 !! 947 <0 0xc40a000 0 0x26000>;
2412 reg-names = "core", " 948 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2413 interrupt-names = "pe 949 interrupt-names = "periph_irq";
2414 interrupts-extended = 950 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2415 qcom,ee = <0>; 951 qcom,ee = <0>;
2416 qcom,channel = <0>; 952 qcom,channel = <0>;
2417 #address-cells = <2>; 953 #address-cells = <2>;
2418 #size-cells = <0>; 954 #size-cells = <0>;
2419 interrupt-controller; 955 interrupt-controller;
2420 #interrupt-cells = <4 956 #interrupt-cells = <4>;
2421 }; 957 };
2422 958
2423 tlmm: pinctrl@f100000 { 959 tlmm: pinctrl@f100000 {
2424 compatible = "qcom,sm 960 compatible = "qcom,sm6350-tlmm";
2425 reg = <0 0x0f100000 0 961 reg = <0 0x0f100000 0 0x300000>;
2426 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
2427 <GIC_ 963 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
2428 <GIC_ 964 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
2429 <GIC_ 965 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
2430 <GIC_ 966 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
2431 <GIC_ 967 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
2432 <GIC_ 968 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
2433 <GIC_ 969 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
2434 <GIC_ 970 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
2435 gpio-controller; 971 gpio-controller;
2436 #gpio-cells = <2>; 972 #gpio-cells = <2>;
2437 interrupt-controller; 973 interrupt-controller;
2438 #interrupt-cells = <2 974 #interrupt-cells = <2>;
2439 gpio-ranges = <&tlmm 975 gpio-ranges = <&tlmm 0 0 157>;
2440 wakeup-parent = <&pdc <<
2441 <<
2442 cci0_default: cci0-de <<
2443 pins = "gpio3 <<
2444 function = "c <<
2445 drive-strengt <<
2446 bias-pull-up; <<
2447 }; <<
2448 <<
2449 cci0_sleep: cci0-slee <<
2450 pins = "gpio3 <<
2451 function = "c <<
2452 drive-strengt <<
2453 bias-pull-dow <<
2454 }; <<
2455 <<
2456 cci1_default: cci1-de <<
2457 pins = "gpio4 <<
2458 function = "c <<
2459 drive-strengt <<
2460 bias-pull-up; <<
2461 }; <<
2462 <<
2463 cci1_sleep: cci1-slee <<
2464 pins = "gpio4 <<
2465 function = "c <<
2466 drive-strengt <<
2467 bias-pull-dow <<
2468 }; <<
2469 <<
2470 cci2_default: cci2-de <<
2471 pins = "gpio4 <<
2472 function = "c <<
2473 drive-strengt <<
2474 bias-pull-up; <<
2475 }; <<
2476 <<
2477 cci2_sleep: cci2-slee <<
2478 pins = "gpio4 <<
2479 function = "c <<
2480 drive-strengt <<
2481 bias-pull-dow <<
2482 }; <<
2483 976
2484 sdc2_off_state: sdc2- !! 977 qup_uart2_default: qup-uart2-default {
2485 clk-pins { <<
2486 pins <<
2487 drive <<
2488 bias- <<
2489 }; <<
2490 <<
2491 cmd-pins { <<
2492 pins <<
2493 drive <<
2494 bias- <<
2495 }; <<
2496 <<
2497 data-pins { <<
2498 pins <<
2499 drive <<
2500 bias- <<
2501 }; <<
2502 }; <<
2503 <<
2504 sdc2_on_state: sdc2-o <<
2505 clk-pins { <<
2506 pins <<
2507 drive <<
2508 bias- <<
2509 }; <<
2510 <<
2511 cmd-pins { <<
2512 pins <<
2513 drive <<
2514 bias- <<
2515 }; <<
2516 <<
2517 data-pins { <<
2518 pins <<
2519 drive <<
2520 bias- <<
2521 }; <<
2522 }; <<
2523 <<
2524 qup_uart9_default: qu <<
2525 pins = "gpio2 978 pins = "gpio25", "gpio26";
2526 function = "q 979 function = "qup13_f2";
2527 drive-strengt 980 drive-strength = <2>;
2528 bias-disable; 981 bias-disable;
2529 }; 982 };
2530 <<
2531 qup_i2c0_default: qup <<
2532 pins = "gpio0 <<
2533 function = "q <<
2534 drive-strengt <<
2535 bias-pull-up; <<
2536 }; <<
2537 <<
2538 qup_i2c2_default: qup <<
2539 pins = "gpio4 <<
2540 function = "q <<
2541 drive-strengt <<
2542 bias-pull-up; <<
2543 }; <<
2544 <<
2545 qup_i2c6_default: qup <<
2546 pins = "gpio1 <<
2547 function = "q <<
2548 drive-strengt <<
2549 bias-pull-up; <<
2550 }; <<
2551 <<
2552 qup_i2c7_default: qup <<
2553 pins = "gpio2 <<
2554 function = "q <<
2555 drive-strengt <<
2556 bias-pull-up; <<
2557 }; <<
2558 <<
2559 qup_i2c8_default: qup <<
2560 pins = "gpio1 <<
2561 function = "q <<
2562 drive-strengt <<
2563 bias-pull-up; <<
2564 }; <<
2565 <<
2566 qup_i2c10_default: qu <<
2567 pins = "gpio4 <<
2568 function = "q <<
2569 drive-strengt <<
2570 bias-pull-up; <<
2571 }; <<
2572 <<
2573 qup_uart1_cts: qup-ua <<
2574 pins = "gpio6 <<
2575 function = "q <<
2576 drive-strengt <<
2577 bias-disable; <<
2578 }; <<
2579 <<
2580 qup_uart1_rts: qup-ua <<
2581 pins = "gpio6 <<
2582 function = "q <<
2583 drive-strengt <<
2584 bias-pull-dow <<
2585 }; <<
2586 <<
2587 qup_uart1_rx: qup-uar <<
2588 pins = "gpio6 <<
2589 function = "q <<
2590 drive-strengt <<
2591 bias-disable; <<
2592 }; <<
2593 <<
2594 qup_uart1_tx: qup-uar <<
2595 pins = "gpio6 <<
2596 function = "q <<
2597 drive-strengt <<
2598 bias-pull-up; <<
2599 }; <<
2600 }; 983 };
2601 984
2602 apps_smmu: iommu@15000000 { 985 apps_smmu: iommu@15000000 {
2603 compatible = "qcom,sm 986 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2604 reg = <0 0x15000000 0 987 reg = <0 0x15000000 0 0x100000>;
2605 #iommu-cells = <2>; 988 #iommu-cells = <2>;
2606 #global-interrupts = 989 #global-interrupts = <1>;
2607 interrupts = <GIC_SPI 990 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
2608 <GIC_SPI 991 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2609 <GIC_SPI 992 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2610 <GIC_SPI 993 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2611 <GIC_SPI 994 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2612 <GIC_SPI 995 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2613 <GIC_SPI 996 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2614 <GIC_SPI 997 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2615 <GIC_SPI 998 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2616 <GIC_SPI 999 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2617 <GIC_SPI 1000 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2618 <GIC_SPI 1001 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2619 <GIC_SPI 1002 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2620 <GIC_SPI 1003 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2621 <GIC_SPI 1004 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2622 <GIC_SPI 1005 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2623 <GIC_SPI 1006 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2624 <GIC_SPI 1007 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2625 <GIC_SPI 1008 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2626 <GIC_SPI 1009 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2627 <GIC_SPI 1010 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2628 <GIC_SPI 1011 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2629 <GIC_SPI 1012 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2630 <GIC_SPI 1013 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2631 <GIC_SPI 1014 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2632 <GIC_SPI 1015 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
2633 <GIC_SPI 1016 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
2634 <GIC_SPI 1017 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
2635 <GIC_SPI 1018 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
2636 <GIC_SPI 1019 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
2637 <GIC_SPI 1020 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
2638 <GIC_SPI 1021 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
2639 <GIC_SPI 1022 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
2640 <GIC_SPI 1023 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
2641 <GIC_SPI 1024 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
2642 <GIC_SPI 1025 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
2643 <GIC_SPI 1026 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
2644 <GIC_SPI 1027 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2645 <GIC_SPI 1028 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
2646 <GIC_SPI 1029 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2647 <GIC_SPI 1030 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
2648 <GIC_SPI 1031 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
2649 <GIC_SPI 1032 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
2650 <GIC_SPI 1033 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
2651 <GIC_SPI 1034 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
2652 <GIC_SPI 1035 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
2653 <GIC_SPI 1036 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
2654 <GIC_SPI 1037 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
2655 <GIC_SPI 1038 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
2656 <GIC_SPI 1039 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
2657 <GIC_SPI 1040 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
2658 <GIC_SPI 1041 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
2659 <GIC_SPI 1042 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2660 <GIC_SPI 1043 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
2661 <GIC_SPI 1044 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
2662 <GIC_SPI 1045 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
2663 <GIC_SPI 1046 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
2664 <GIC_SPI 1047 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2665 <GIC_SPI 1048 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2666 <GIC_SPI 1049 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2667 <GIC_SPI 1050 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2668 <GIC_SPI 1051 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2669 <GIC_SPI 1052 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2670 <GIC_SPI 1053 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
2671 <GIC_SPI 1054 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
2672 <GIC_SPI 1055 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
2673 <GIC_SPI 1056 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
2674 <GIC_SPI 1057 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
2675 <GIC_SPI 1058 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2676 <GIC_SPI 1059 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2677 <GIC_SPI 1060 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2678 <GIC_SPI 1061 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2679 <GIC_SPI 1062 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2680 <GIC_SPI 1063 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2681 <GIC_SPI 1064 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2682 <GIC_SPI 1065 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2683 <GIC_SPI 1066 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2684 <GIC_SPI 1067 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2685 <GIC_SPI 1068 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2686 <GIC_SPI 1069 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2687 <GIC_SPI 1070 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
2688 }; 1071 };
2689 1072
2690 intc: interrupt-controller@17 1073 intc: interrupt-controller@17a00000 {
2691 compatible = "arm,gic 1074 compatible = "arm,gic-v3";
2692 #interrupt-cells = <3 1075 #interrupt-cells = <3>;
2693 interrupt-controller; 1076 interrupt-controller;
2694 reg = <0x0 0x17a00000 1077 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2695 <0x0 0x17a60000 1078 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2696 interrupts = <GIC_PPI 1079 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
2697 }; 1080 };
2698 1081
2699 watchdog@17c10000 { 1082 watchdog@17c10000 {
2700 compatible = "qcom,ap 1083 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2701 reg = <0 0x17c10000 0 1084 reg = <0 0x17c10000 0 0x1000>;
2702 clocks = <&sleep_clk> 1085 clocks = <&sleep_clk>;
2703 interrupts = <GIC_SPI !! 1086 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2704 }; 1087 };
2705 1088
2706 timer@17c20000 { 1089 timer@17c20000 {
2707 compatible = "arm,arm 1090 compatible = "arm,armv7-timer-mem";
2708 reg = <0x0 0x17c20000 1091 reg = <0x0 0x17c20000 0x0 0x1000>;
2709 clock-frequency = <19 1092 clock-frequency = <19200000>;
2710 #address-cells = <1>; !! 1093 #address-cells = <2>;
2711 #size-cells = <1>; !! 1094 #size-cells = <2>;
2712 ranges = <0 0 0 0x200 !! 1095 ranges;
2713 1096
2714 frame@17c21000 { 1097 frame@17c21000 {
2715 frame-number 1098 frame-number = <0>;
2716 interrupts = 1099 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2717 1100 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2718 reg = <0x17c2 !! 1101 reg = <0x0 0x17c21000 0x0 0x1000>,
2719 <0x17c2 !! 1102 <0x0 0x17c22000 0x0 0x1000>;
2720 }; 1103 };
2721 1104
2722 frame@17c23000 { 1105 frame@17c23000 {
2723 frame-number 1106 frame-number = <1>;
2724 interrupts = 1107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2725 reg = <0x17c2 !! 1108 reg = <0x0 0x17c23000 0x0 0x1000>;
2726 status = "dis 1109 status = "disabled";
2727 }; 1110 };
2728 1111
2729 frame@17c25000 { 1112 frame@17c25000 {
2730 frame-number 1113 frame-number = <2>;
2731 interrupts = 1114 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2732 reg = <0x17c2 !! 1115 reg = <0x0 0x17c25000 0x0 0x1000>;
2733 status = "dis 1116 status = "disabled";
2734 }; 1117 };
2735 1118
2736 frame@17c27000 { 1119 frame@17c27000 {
2737 frame-number 1120 frame-number = <3>;
2738 interrupts = 1121 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2739 reg = <0x17c2 !! 1122 reg = <0x0 0x17c27000 0x0 0x1000>;
2740 status = "dis 1123 status = "disabled";
2741 }; 1124 };
2742 1125
2743 frame@17c29000 { 1126 frame@17c29000 {
2744 frame-number 1127 frame-number = <4>;
2745 interrupts = 1128 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2746 reg = <0x17c2 !! 1129 reg = <0x0 0x17c29000 0x0 0x1000>;
2747 status = "dis 1130 status = "disabled";
2748 }; 1131 };
2749 1132
2750 frame@17c2b000 { 1133 frame@17c2b000 {
2751 frame-number 1134 frame-number = <5>;
2752 interrupts = 1135 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2753 reg = <0x17c2 !! 1136 reg = <0x0 0x17c2b000 0x0 0x1000>;
2754 status = "dis 1137 status = "disabled";
2755 }; 1138 };
2756 1139
2757 frame@17c2d000 { 1140 frame@17c2d000 {
2758 frame-number 1141 frame-number = <6>;
2759 interrupts = 1142 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2760 reg = <0x17c2 !! 1143 reg = <0x0 0x17c2d000 0x0 0x1000>;
2761 status = "dis 1144 status = "disabled";
2762 }; 1145 };
2763 }; 1146 };
2764 1147
2765 apps_rsc: rsc@18200000 { 1148 apps_rsc: rsc@18200000 {
2766 compatible = "qcom,rp 1149 compatible = "qcom,rpmh-rsc";
2767 label = "apps_rsc"; 1150 label = "apps_rsc";
2768 reg = <0x0 0x18200000 1151 reg = <0x0 0x18200000 0x0 0x10000>,
2769 <0x0 0x182100 1152 <0x0 0x18210000 0x0 0x10000>,
2770 <0x0 0x182200 1153 <0x0 0x18220000 0x0 0x10000>;
2771 reg-names = "drv-0", 1154 reg-names = "drv-0", "drv-1", "drv-2";
2772 interrupts = <GIC_SPI 1155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2773 <GIC_SPI 1156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2774 <GIC_SPI 1157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2775 qcom,tcs-offset = <0x 1158 qcom,tcs-offset = <0xd00>;
2776 qcom,drv-id = <2>; 1159 qcom,drv-id = <2>;
2777 qcom,tcs-config = <AC 1160 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2778 <WA 1161 <WAKE_TCS 3>, <CONTROL_TCS 1>;
2779 power-domains = <&CLU <<
2780 1162
2781 rpmhcc: clock-control 1163 rpmhcc: clock-controller {
2782 compatible = 1164 compatible = "qcom,sm6350-rpmh-clk";
2783 #clock-cells 1165 #clock-cells = <1>;
2784 clock-names = 1166 clock-names = "xo";
2785 clocks = <&xo 1167 clocks = <&xo_board>;
2786 }; 1168 };
2787 1169
2788 rpmhpd: power-control 1170 rpmhpd: power-controller {
2789 compatible = 1171 compatible = "qcom,sm6350-rpmhpd";
2790 #power-domain 1172 #power-domain-cells = <1>;
2791 operating-poi 1173 operating-points-v2 = <&rpmhpd_opp_table>;
2792 1174
2793 rpmhpd_opp_ta 1175 rpmhpd_opp_table: opp-table {
2794 compa 1176 compatible = "operating-points-v2";
2795 1177
2796 rpmhp 1178 rpmhpd_opp_ret: opp1 {
2797 1179 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2798 }; 1180 };
2799 1181
2800 rpmhp 1182 rpmhpd_opp_min_svs: opp2 {
2801 1183 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2802 }; 1184 };
2803 1185
2804 rpmhp 1186 rpmhpd_opp_low_svs: opp3 {
2805 1187 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2806 }; 1188 };
2807 1189
2808 rpmhp 1190 rpmhpd_opp_svs: opp4 {
2809 1191 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2810 }; 1192 };
2811 1193
2812 rpmhp 1194 rpmhpd_opp_svs_l1: opp5 {
2813 1195 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2814 }; 1196 };
2815 1197
2816 rpmhp 1198 rpmhpd_opp_nom: opp6 {
2817 1199 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2818 }; 1200 };
2819 1201
2820 rpmhp 1202 rpmhpd_opp_nom_l1: opp7 {
2821 1203 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2822 }; 1204 };
2823 1205
2824 rpmhp 1206 rpmhpd_opp_nom_l2: opp8 {
2825 1207 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2826 }; 1208 };
2827 1209
2828 rpmhp 1210 rpmhpd_opp_turbo: opp9 {
2829 1211 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2830 }; 1212 };
2831 1213
2832 rpmhp 1214 rpmhpd_opp_turbo_l1: opp10 {
2833 1215 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2834 }; 1216 };
2835 }; 1217 };
2836 }; 1218 };
2837 1219
2838 apps_bcm_voter: bcm-v !! 1220 apps_bcm_voter: bcm_voter {
2839 compatible = 1221 compatible = "qcom,bcm-voter";
2840 }; 1222 };
2841 }; 1223 };
2842 1224
2843 osm_l3: interconnect@18321000 <<
2844 compatible = "qcom,sm <<
2845 reg = <0x0 0x18321000 <<
2846 <<
2847 clocks = <&rpmhcc RPM <<
2848 clock-names = "xo", " <<
2849 <<
2850 #interconnect-cells = <<
2851 }; <<
2852 <<
2853 cpufreq_hw: cpufreq@18323000 1225 cpufreq_hw: cpufreq@18323000 {
2854 compatible = "qcom,sm !! 1226 compatible = "qcom,cpufreq-hw";
2855 reg = <0 0x18323000 0 1227 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
2856 reg-names = "freq-dom 1228 reg-names = "freq-domain0", "freq-domain1";
2857 clocks = <&rpmhcc RPM 1229 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2858 clock-names = "xo", " 1230 clock-names = "xo", "alternate";
2859 1231
2860 #freq-domain-cells = 1232 #freq-domain-cells = <1>;
2861 #clock-cells = <1>; <<
2862 }; <<
2863 <<
2864 wifi: wifi@18800000 { <<
2865 compatible = "qcom,wc <<
2866 reg = <0 0x18800000 0 <<
2867 reg-names = "membase" <<
2868 memory-region = <&wla <<
2869 interrupts = <GIC_SPI <<
2870 <GIC_SPI <<
2871 <GIC_SPI <<
2872 <GIC_SPI <<
2873 <GIC_SPI <<
2874 <GIC_SPI <<
2875 <GIC_SPI <<
2876 <GIC_SPI <<
2877 <GIC_SPI <<
2878 <GIC_SPI <<
2879 <GIC_SPI <<
2880 <GIC_SPI <<
2881 iommus = <&apps_smmu <<
2882 qcom,msa-fixed-perm; <<
2883 status = "disabled"; <<
2884 }; <<
2885 }; <<
2886 <<
2887 thermal-zones { <<
2888 aoss0-thermal { <<
2889 thermal-sensors = <&t <<
2890 <<
2891 trips { <<
2892 aoss0-crit { <<
2893 tempe <<
2894 hyste <<
2895 type <<
2896 }; <<
2897 }; <<
2898 }; <<
2899 <<
2900 aoss1-thermal { <<
2901 thermal-sensors = <&t <<
2902 <<
2903 trips { <<
2904 aoss1-crit { <<
2905 tempe <<
2906 hyste <<
2907 type <<
2908 }; <<
2909 }; <<
2910 }; <<
2911 <<
2912 audio-thermal { <<
2913 thermal-sensors = <&t <<
2914 <<
2915 trips { <<
2916 audio-crit { <<
2917 tempe <<
2918 hyste <<
2919 type <<
2920 }; <<
2921 }; <<
2922 }; <<
2923 <<
2924 camera-thermal { <<
2925 thermal-sensors = <&t <<
2926 <<
2927 trips { <<
2928 camera-crit { <<
2929 tempe <<
2930 hyste <<
2931 type <<
2932 }; <<
2933 }; <<
2934 }; <<
2935 <<
2936 cpu0-thermal { <<
2937 thermal-sensors = <&t <<
2938 <<
2939 trips { <<
2940 cpu0_alert0: <<
2941 tempe <<
2942 hyste <<
2943 type <<
2944 }; <<
2945 <<
2946 cpu0-crit { <<
2947 tempe <<
2948 hyste <<
2949 type <<
2950 }; <<
2951 }; <<
2952 <<
2953 cooling-maps { <<
2954 map0 { <<
2955 trip <<
2956 cooli <<
2957 }; <<
2958 }; <<
2959 }; <<
2960 <<
2961 cpu1-thermal { <<
2962 thermal-sensors = <&t <<
2963 <<
2964 trips { <<
2965 cpu1_alert0: <<
2966 tempe <<
2967 hyste <<
2968 type <<
2969 }; <<
2970 <<
2971 cpu1-crit { <<
2972 tempe <<
2973 hyste <<
2974 type <<
2975 }; <<
2976 }; <<
2977 <<
2978 cooling-maps { <<
2979 map0 { <<
2980 trip <<
2981 cooli <<
2982 }; <<
2983 }; <<
2984 }; <<
2985 <<
2986 cpu2-thermal { <<
2987 thermal-sensors = <&t <<
2988 <<
2989 trips { <<
2990 cpu2_alert0: <<
2991 tempe <<
2992 hyste <<
2993 type <<
2994 }; <<
2995 <<
2996 cpu2-crit { <<
2997 tempe <<
2998 hyste <<
2999 type <<
3000 }; <<
3001 }; <<
3002 <<
3003 cooling-maps { <<
3004 map0 { <<
3005 trip <<
3006 cooli <<
3007 }; <<
3008 }; <<
3009 }; <<
3010 <<
3011 cpu3-thermal { <<
3012 thermal-sensors = <&t <<
3013 <<
3014 trips { <<
3015 cpu3_alert0: <<
3016 tempe <<
3017 hyste <<
3018 type <<
3019 }; <<
3020 <<
3021 cpu3-crit { <<
3022 tempe <<
3023 hyste <<
3024 type <<
3025 }; <<
3026 }; <<
3027 <<
3028 cooling-maps { <<
3029 map0 { <<
3030 trip <<
3031 cooli <<
3032 }; <<
3033 }; <<
3034 }; <<
3035 <<
3036 cpu4-thermal { <<
3037 thermal-sensors = <&t <<
3038 <<
3039 trips { <<
3040 cpu4_alert0: <<
3041 tempe <<
3042 hyste <<
3043 type <<
3044 }; <<
3045 <<
3046 cpu4-crit { <<
3047 tempe <<
3048 hyste <<
3049 type <<
3050 }; <<
3051 }; <<
3052 <<
3053 cooling-maps { <<
3054 map0 { <<
3055 trip <<
3056 cooli <<
3057 }; <<
3058 }; <<
3059 }; <<
3060 <<
3061 cpu5-thermal { <<
3062 thermal-sensors = <&t <<
3063 <<
3064 trips { <<
3065 cpu5_alert0: <<
3066 tempe <<
3067 hyste <<
3068 type <<
3069 }; <<
3070 <<
3071 cpu5-crit { <<
3072 tempe <<
3073 hyste <<
3074 type <<
3075 }; <<
3076 }; <<
3077 <<
3078 cooling-maps { <<
3079 map0 { <<
3080 trip <<
3081 cooli <<
3082 }; <<
3083 }; <<
3084 }; <<
3085 <<
3086 cpu6-left-thermal { <<
3087 thermal-sensors = <&t <<
3088 <<
3089 trips { <<
3090 cpu6_left_ale <<
3091 tempe <<
3092 hyste <<
3093 type <<
3094 }; <<
3095 <<
3096 cpu6-left-cri <<
3097 tempe <<
3098 hyste <<
3099 type <<
3100 }; <<
3101 }; <<
3102 <<
3103 cooling-maps { <<
3104 map0 { <<
3105 trip <<
3106 cooli <<
3107 }; <<
3108 }; <<
3109 }; <<
3110 <<
3111 cpu6-right-thermal { <<
3112 thermal-sensors = <&t <<
3113 <<
3114 trips { <<
3115 cpu6_right_al <<
3116 tempe <<
3117 hyste <<
3118 type <<
3119 }; <<
3120 <<
3121 cpu6-right-cr <<
3122 tempe <<
3123 hyste <<
3124 type <<
3125 }; <<
3126 }; <<
3127 <<
3128 cooling-maps { <<
3129 map0 { <<
3130 trip <<
3131 cooli <<
3132 }; <<
3133 }; <<
3134 }; <<
3135 <<
3136 cpu7-left-thermal { <<
3137 thermal-sensors = <&t <<
3138 <<
3139 trips { <<
3140 cpu7_left_ale <<
3141 tempe <<
3142 hyste <<
3143 type <<
3144 }; <<
3145 <<
3146 cpu7-left-cri <<
3147 tempe <<
3148 hyste <<
3149 type <<
3150 }; <<
3151 }; <<
3152 <<
3153 cooling-maps { <<
3154 map0 { <<
3155 trip <<
3156 cooli <<
3157 }; <<
3158 }; <<
3159 }; <<
3160 <<
3161 cpu7-right-thermal { <<
3162 thermal-sensors = <&t <<
3163 <<
3164 trips { <<
3165 cpu7_right_al <<
3166 tempe <<
3167 hyste <<
3168 type <<
3169 }; <<
3170 <<
3171 cpu7-right-cr <<
3172 tempe <<
3173 hyste <<
3174 type <<
3175 }; <<
3176 }; <<
3177 <<
3178 cooling-maps { <<
3179 map0 { <<
3180 trip <<
3181 cooli <<
3182 }; <<
3183 }; <<
3184 }; <<
3185 <<
3186 cpuss0-thermal { <<
3187 thermal-sensors = <&t <<
3188 <<
3189 trips { <<
3190 cpuss0-crit { <<
3191 tempe <<
3192 hyste <<
3193 type <<
3194 }; <<
3195 }; <<
3196 }; <<
3197 <<
3198 cpuss1-thermal { <<
3199 thermal-sensors = <&t <<
3200 <<
3201 trips { <<
3202 cpuss1-crit { <<
3203 tempe <<
3204 hyste <<
3205 type <<
3206 }; <<
3207 }; <<
3208 }; <<
3209 <<
3210 cwlan-thermal { <<
3211 thermal-sensors = <&t <<
3212 <<
3213 trips { <<
3214 cwlan-crit { <<
3215 tempe <<
3216 hyste <<
3217 type <<
3218 }; <<
3219 }; <<
3220 }; <<
3221 <<
3222 ddr-thermal { <<
3223 thermal-sensors = <&t <<
3224 <<
3225 trips { <<
3226 ddr-crit { <<
3227 tempe <<
3228 hyste <<
3229 type <<
3230 }; <<
3231 }; <<
3232 }; <<
3233 <<
3234 gpuss0-thermal { <<
3235 polling-delay-passive <<
3236 <<
3237 thermal-sensors = <&t <<
3238 <<
3239 trips { <<
3240 gpuss0_alert0 <<
3241 tempe <<
3242 hyste <<
3243 type <<
3244 }; <<
3245 <<
3246 gpuss0-crit { <<
3247 tempe <<
3248 hyste <<
3249 type <<
3250 }; <<
3251 }; <<
3252 <<
3253 cooling-maps { <<
3254 map0 { <<
3255 trip <<
3256 cooli <<
3257 }; <<
3258 }; <<
3259 }; <<
3260 <<
3261 gpuss1-thermal { <<
3262 polling-delay-passive <<
3263 <<
3264 thermal-sensors = <&t <<
3265 <<
3266 trips { <<
3267 gpuss1_alert0 <<
3268 tempe <<
3269 hyste <<
3270 type <<
3271 }; <<
3272 <<
3273 gpuss1-crit { <<
3274 tempe <<
3275 hyste <<
3276 type <<
3277 }; <<
3278 }; <<
3279 <<
3280 cooling-maps { <<
3281 map0 { <<
3282 trip <<
3283 cooli <<
3284 }; <<
3285 }; <<
3286 }; <<
3287 <<
3288 modem-core0-thermal { <<
3289 thermal-sensors = <&t <<
3290 <<
3291 trips { <<
3292 modem-core0-c <<
3293 tempe <<
3294 hyste <<
3295 type <<
3296 }; <<
3297 }; <<
3298 }; <<
3299 <<
3300 modem-core1-thermal { <<
3301 thermal-sensors = <&t <<
3302 <<
3303 trips { <<
3304 modem-core1-c <<
3305 tempe <<
3306 hyste <<
3307 type <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 <<
3312 modem-scl-thermal { <<
3313 thermal-sensors = <&t <<
3314 <<
3315 trips { <<
3316 modem-scl-cri <<
3317 tempe <<
3318 hyste <<
3319 type <<
3320 }; <<
3321 }; <<
3322 }; <<
3323 <<
3324 modem-vec-thermal { <<
3325 thermal-sensors = <&t <<
3326 <<
3327 trips { <<
3328 modem-vec-cri <<
3329 tempe <<
3330 hyste <<
3331 type <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 <<
3336 npu-thermal { <<
3337 thermal-sensors = <&t <<
3338 <<
3339 trips { <<
3340 npu-crit { <<
3341 tempe <<
3342 hyste <<
3343 type <<
3344 }; <<
3345 }; <<
3346 }; <<
3347 <<
3348 q6-hvx-thermal { <<
3349 thermal-sensors = <&t <<
3350 <<
3351 trips { <<
3352 q6-hvx-crit { <<
3353 tempe <<
3354 hyste <<
3355 type <<
3356 }; <<
3357 }; <<
3358 }; <<
3359 <<
3360 video-thermal { <<
3361 thermal-sensors = <&t <<
3362 <<
3363 trips { <<
3364 video-crit { <<
3365 tempe <<
3366 hyste <<
3367 type <<
3368 }; <<
3369 }; <<
3370 }; 1233 };
3371 }; 1234 };
3372 1235
3373 timer { 1236 timer {
3374 compatible = "arm,armv8-timer 1237 compatible = "arm,armv8-timer";
3375 clock-frequency = <19200000>; 1238 clock-frequency = <19200000>;
3376 interrupts = <GIC_PPI 1 (GIC_ 1239 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3377 <GIC_PPI 2 (GIC_ 1240 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3378 <GIC_PPI 3 (GIC_ 1241 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3379 <GIC_PPI 0 (GIC_ 1242 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3380 }; 1243 };
3381 }; 1244 };
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