1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati
4 * Copyright (c) 2019, Linaro Limited
5 */
6
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150.
17 #include <dt-bindings/clock/qcom,videocc-sm815
18 #include <dt-bindings/interconnect/qcom,osm-l3
19 #include <dt-bindings/interconnect/qcom,sm8150
20 #include <dt-bindings/clock/qcom,sm8150-camcc.
21 #include <dt-bindings/thermal/thermal.h>
22
23 / {
24 interrupt-parent = <&intc>;
25
26 #address-cells = <2>;
27 #size-cells = <2>;
28
29 chosen { };
30
31 clocks {
32 xo_board: xo-board {
33 compatible = "fixed-cl
34 #clock-cells = <0>;
35 clock-frequency = <384
36 clock-output-names = "
37 };
38
39 sleep_clk: sleep-clk {
40 compatible = "fixed-cl
41 #clock-cells = <0>;
42 clock-frequency = <327
43 clock-output-names = "
44 };
45 };
46
47 cpus {
48 #address-cells = <2>;
49 #size-cells = <0>;
50
51 CPU0: cpu@0 {
52 device_type = "cpu";
53 compatible = "qcom,kry
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw
56 enable-method = "psci"
57 capacity-dmips-mhz = <
58 dynamic-power-coeffici
59 next-level-cache = <&L
60 qcom,freq-domain = <&c
61 operating-points-v2 =
62 interconnects = <&gem_
63 <&osm_
64 power-domains = <&CPU_
65 power-domain-names = "
66 #cooling-cells = <2>;
67 L2_0: l2-cache {
68 compatible = "
69 cache-level =
70 cache-unified;
71 next-level-cac
72 L3_0: l3-cache
73 compat
74 cache-
75 cache-
76 };
77 };
78 };
79
80 CPU1: cpu@100 {
81 device_type = "cpu";
82 compatible = "qcom,kry
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw
85 enable-method = "psci"
86 capacity-dmips-mhz = <
87 dynamic-power-coeffici
88 next-level-cache = <&L
89 qcom,freq-domain = <&c
90 operating-points-v2 =
91 interconnects = <&gem_
92 <&osm_
93 power-domains = <&CPU_
94 power-domain-names = "
95 #cooling-cells = <2>;
96 L2_100: l2-cache {
97 compatible = "
98 cache-level =
99 cache-unified;
100 next-level-cac
101 };
102 };
103
104 CPU2: cpu@200 {
105 device_type = "cpu";
106 compatible = "qcom,kry
107 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw
109 enable-method = "psci"
110 capacity-dmips-mhz = <
111 dynamic-power-coeffici
112 next-level-cache = <&L
113 qcom,freq-domain = <&c
114 operating-points-v2 =
115 interconnects = <&gem_
116 <&osm_
117 power-domains = <&CPU_
118 power-domain-names = "
119 #cooling-cells = <2>;
120 L2_200: l2-cache {
121 compatible = "
122 cache-level =
123 cache-unified;
124 next-level-cac
125 };
126 };
127
128 CPU3: cpu@300 {
129 device_type = "cpu";
130 compatible = "qcom,kry
131 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw
133 enable-method = "psci"
134 capacity-dmips-mhz = <
135 dynamic-power-coeffici
136 next-level-cache = <&L
137 qcom,freq-domain = <&c
138 operating-points-v2 =
139 interconnects = <&gem_
140 <&osm_
141 power-domains = <&CPU_
142 power-domain-names = "
143 #cooling-cells = <2>;
144 L2_300: l2-cache {
145 compatible = "
146 cache-level =
147 cache-unified;
148 next-level-cac
149 };
150 };
151
152 CPU4: cpu@400 {
153 device_type = "cpu";
154 compatible = "qcom,kry
155 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw
157 enable-method = "psci"
158 capacity-dmips-mhz = <
159 dynamic-power-coeffici
160 next-level-cache = <&L
161 qcom,freq-domain = <&c
162 operating-points-v2 =
163 interconnects = <&gem_
164 <&osm_
165 power-domains = <&CPU_
166 power-domain-names = "
167 #cooling-cells = <2>;
168 L2_400: l2-cache {
169 compatible = "
170 cache-level =
171 cache-unified;
172 next-level-cac
173 };
174 };
175
176 CPU5: cpu@500 {
177 device_type = "cpu";
178 compatible = "qcom,kry
179 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw
181 enable-method = "psci"
182 capacity-dmips-mhz = <
183 dynamic-power-coeffici
184 next-level-cache = <&L
185 qcom,freq-domain = <&c
186 operating-points-v2 =
187 interconnects = <&gem_
188 <&osm_
189 power-domains = <&CPU_
190 power-domain-names = "
191 #cooling-cells = <2>;
192 L2_500: l2-cache {
193 compatible = "
194 cache-level =
195 cache-unified;
196 next-level-cac
197 };
198 };
199
200 CPU6: cpu@600 {
201 device_type = "cpu";
202 compatible = "qcom,kry
203 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw
205 enable-method = "psci"
206 capacity-dmips-mhz = <
207 dynamic-power-coeffici
208 next-level-cache = <&L
209 qcom,freq-domain = <&c
210 operating-points-v2 =
211 interconnects = <&gem_
212 <&osm_
213 power-domains = <&CPU_
214 power-domain-names = "
215 #cooling-cells = <2>;
216 L2_600: l2-cache {
217 compatible = "
218 cache-level =
219 cache-unified;
220 next-level-cac
221 };
222 };
223
224 CPU7: cpu@700 {
225 device_type = "cpu";
226 compatible = "qcom,kry
227 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw
229 enable-method = "psci"
230 capacity-dmips-mhz = <
231 dynamic-power-coeffici
232 next-level-cache = <&L
233 qcom,freq-domain = <&c
234 operating-points-v2 =
235 interconnects = <&gem_
236 <&osm_
237 power-domains = <&CPU_
238 power-domain-names = "
239 #cooling-cells = <2>;
240 L2_700: l2-cache {
241 compatible = "
242 cache-level =
243 cache-unified;
244 next-level-cac
245 };
246 };
247
248 cpu-map {
249 cluster0 {
250 core0 {
251 cpu =
252 };
253
254 core1 {
255 cpu =
256 };
257
258 core2 {
259 cpu =
260 };
261
262 core3 {
263 cpu =
264 };
265
266 core4 {
267 cpu =
268 };
269
270 core5 {
271 cpu =
272 };
273
274 core6 {
275 cpu =
276 };
277
278 core7 {
279 cpu =
280 };
281 };
282 };
283
284 idle-states {
285 entry-method = "psci";
286
287 LITTLE_CPU_SLEEP_0: cp
288 compatible = "
289 idle-state-nam
290 arm,psci-suspe
291 entry-latency-
292 exit-latency-u
293 min-residency-
294 local-timer-st
295 };
296
297 BIG_CPU_SLEEP_0: cpu-s
298 compatible = "
299 idle-state-nam
300 arm,psci-suspe
301 entry-latency-
302 exit-latency-u
303 min-residency-
304 local-timer-st
305 };
306 };
307
308 domain-idle-states {
309 CLUSTER_SLEEP_0: clust
310 compatible = "
311 arm,psci-suspe
312 entry-latency-
313 exit-latency-u
314 min-residency-
315 };
316 };
317 };
318
319 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points
321 opp-shared;
322
323 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30
325 opp-peak-kBps = <80000
326 };
327
328 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40
330 opp-peak-kBps = <80000
331 };
332
333 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49
335 opp-peak-kBps = <80000
336 };
337
338 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57
340 opp-peak-kBps = <80000
341 };
342
343 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67
345 opp-peak-kBps = <80000
346 };
347
348 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76
350 opp-peak-kBps = <18040
351 };
352
353 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84
355 opp-peak-kBps = <18040
356 };
357
358 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94
360 opp-peak-kBps = <18040
361 };
362
363 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10
365 opp-peak-kBps = <18040
366 };
367
368 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11
370 opp-peak-kBps = <21880
371 };
372
373 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12
375 opp-peak-kBps = <21880
376 };
377
378 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13
380 opp-peak-kBps = <30720
381 };
382
383 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13
385 opp-peak-kBps = <30720
386 };
387
388 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14
390 opp-peak-kBps = <30720
391 };
392
393 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15
395 opp-peak-kBps = <30720
396 };
397
398 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16
400 opp-peak-kBps = <30720
401 };
402
403 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17
405 opp-peak-kBps = <30720
406 };
407
408 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17
410 opp-peak-kBps = <30720
411 };
412 };
413
414 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points
416 opp-shared;
417
418 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71
420 opp-peak-kBps = <18040
421 };
422
423 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82
425 opp-peak-kBps = <21880
426 };
427
428 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94
430 opp-peak-kBps = <21880
431 };
432
433 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10
435 opp-peak-kBps = <30720
436 };
437
438 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11
440 opp-peak-kBps = <30720
441 };
442
443 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12
445 opp-peak-kBps = <40680
446 };
447
448 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14
450 opp-peak-kBps = <40680
451 };
452
453 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14
455 opp-peak-kBps = <40680
456 };
457
458 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16
460 opp-peak-kBps = <40680
461 };
462
463 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17
465 opp-peak-kBps = <40680
466 };
467
468 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18
470 opp-peak-kBps = <62200
471 };
472
473 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19
475 opp-peak-kBps = <62200
476 };
477
478 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20
480 opp-peak-kBps = <72160
481 };
482
483 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21
485 opp-peak-kBps = <83680
486 };
487
488 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22
490 opp-peak-kBps = <83680
491 };
492
493 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23
495 opp-peak-kBps = <83680
496 };
497
498 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24
500 opp-peak-kBps = <83680
501 };
502 };
503
504 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points
506 opp-shared;
507
508 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82
510 opp-peak-kBps = <21880
511 };
512
513 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94
515 opp-peak-kBps = <21880
516 };
517
518 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10
520 opp-peak-kBps = <30720
521 };
522
523 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11
525 opp-peak-kBps = <30720
526 };
527
528 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12
530 opp-peak-kBps = <40680
531 };
532
533 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14
535 opp-peak-kBps = <40680
536 };
537
538 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14
540 opp-peak-kBps = <40680
541 };
542
543 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16
545 opp-peak-kBps = <40680
546 };
547
548 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17
550 opp-peak-kBps = <40680
551 };
552
553 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18
555 opp-peak-kBps = <62200
556 };
557
558 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19
560 opp-peak-kBps = <62200
561 };
562
563 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20
565 opp-peak-kBps = <72160
566 };
567
568 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21
570 opp-peak-kBps = <83680
571 };
572
573 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22
575 opp-peak-kBps = <83680
576 };
577
578 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23
580 opp-peak-kBps = <83680
581 };
582
583 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24
585 opp-peak-kBps = <83680
586 };
587
588 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25
590 opp-peak-kBps = <83680
591 };
592
593 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26
595 opp-peak-kBps = <83680
596 };
597
598 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27
600 opp-peak-kBps = <83680
601 };
602
603 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28
605 opp-peak-kBps = <83680
606 };
607 };
608
609 firmware {
610 scm: scm {
611 compatible = "qcom,scm
612 #reset-cells = <1>;
613 };
614 };
615
616 memory@80000000 {
617 device_type = "memory";
618 /* We expect the bootloader to
619 reg = <0x0 0x80000000 0x0 0x0>
620 };
621
622 pmu {
623 compatible = "arm,armv8-pmuv3"
624 interrupts = <GIC_PPI 5 IRQ_TY
625 };
626
627 psci {
628 compatible = "arm,psci-1.0";
629 method = "smc";
630
631 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells =
633 power-domains = <&CLUS
634 domain-idle-states = <
635 };
636
637 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells =
639 power-domains = <&CLUS
640 domain-idle-states = <
641 };
642
643 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells =
645 power-domains = <&CLUS
646 domain-idle-states = <
647 };
648
649 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells =
651 power-domains = <&CLUS
652 domain-idle-states = <
653 };
654
655 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells =
657 power-domains = <&CLUS
658 domain-idle-states = <
659 };
660
661 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells =
663 power-domains = <&CLUS
664 domain-idle-states = <
665 };
666
667 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells =
669 power-domains = <&CLUS
670 domain-idle-states = <
671 };
672
673 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells =
675 power-domains = <&CLUS
676 domain-idle-states = <
677 };
678
679 CLUSTER_PD: power-domain-cpu-c
680 #power-domain-cells =
681 domain-idle-states = <
682 };
683 };
684
685 reserved-memory {
686 #address-cells = <2>;
687 #size-cells = <2>;
688 ranges;
689
690 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000
692 no-map;
693 };
694
695 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000
697 no-map;
698 };
699
700 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000
702 no-map;
703 };
704
705 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd
707 reg = <0x0 0x85f20000
708 no-map;
709 };
710
711 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000
713 no-map;
714 };
715
716 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000
718 no-map;
719 };
720
721 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt
723 reg = <0x0 0x89b00000
724 no-map;
725
726 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_
728 };
729
730 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000
732 no-map;
733 };
734
735 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000
737 no-map;
738 };
739
740 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000
742 no-map;
743 };
744
745 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000
747 no-map;
748 };
749
750 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000
752 no-map;
753 };
754
755 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000
757 no-map;
758 };
759
760 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000
762 no-map;
763 };
764
765 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000
767 no-map;
768 };
769
770 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000
772 no-map;
773 };
774
775 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000
777 no-map;
778 };
779
780 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000
782 no-map;
783 };
784
785 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000
787 no-map;
788 };
789
790 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000
792 no-map;
793 };
794 };
795
796 smem {
797 compatible = "qcom,smem";
798 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>;
800 };
801
802 smp2p-cdsp {
803 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>;
805
806 interrupts = <GIC_SPI 576 IRQ_
807
808 mboxes = <&apss_shared 6>;
809
810 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>;
812
813 cdsp_smp2p_out: master-kernel
814 qcom,entry-name = "mas
815 #qcom,smem-state-cells
816 };
817
818 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla
820
821 interrupt-controller;
822 #interrupt-cells = <2>
823 };
824 };
825
826 smp2p-lpass {
827 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>;
829
830 interrupts = <GIC_SPI 158 IRQ_
831
832 mboxes = <&apss_shared 10>;
833
834 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>;
836
837 adsp_smp2p_out: master-kernel
838 qcom,entry-name = "mas
839 #qcom,smem-state-cells
840 };
841
842 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla
844
845 interrupt-controller;
846 #interrupt-cells = <2>
847 };
848 };
849
850 smp2p-mpss {
851 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>;
853
854 interrupts = <GIC_SPI 451 IRQ_
855
856 mboxes = <&apss_shared 14>;
857
858 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>;
860
861 modem_smp2p_out: master-kernel
862 qcom,entry-name = "mas
863 #qcom,smem-state-cells
864 };
865
866 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla
868
869 interrupt-controller;
870 #interrupt-cells = <2>
871 };
872 };
873
874 smp2p-slpi {
875 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>;
877
878 interrupts = <GIC_SPI 172 IRQ_
879
880 mboxes = <&apss_shared 26>;
881
882 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>;
884
885 slpi_smp2p_out: master-kernel
886 qcom,entry-name = "mas
887 #qcom,smem-state-cells
888 };
889
890 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla
892
893 interrupt-controller;
894 #interrupt-cells = <2>
895 };
896 };
897
898 soc: soc@0 {
899 #address-cells = <2>;
900 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus";
904
905 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc
907 reg = <0x0 0x00100000
908 #clock-cells = <1>;
909 #reset-cells = <1>;
910 #power-domain-cells =
911 clock-names = "bi_tcxo
912 "sleep_c
913 clocks = <&rpmhcc RPMH
914 <&sleep_clk>;
915 };
916
917 gpi_dma0: dma-controller@80000
918 compatible = "qcom,sm8
919 reg = <0 0x00800000 0
920 interrupts = <GIC_SPI
921 <GIC_SPI
922 <GIC_SPI
923 <GIC_SPI
924 <GIC_SPI
925 <GIC_SPI
926 <GIC_SPI
927 <GIC_SPI
928 <GIC_SPI
929 <GIC_SPI
930 <GIC_SPI
931 <GIC_SPI
932 <GIC_SPI
933 dma-channels = <13>;
934 dma-channel-mask = <0x
935 iommus = <&apps_smmu 0
936 #dma-cells = <3>;
937 status = "disabled";
938 };
939
940 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8
942 reg = <0x0 0x00020000
943 <0x0 0x00036000
944 reg-names = "stmmaceth
945 clock-names = "stmmace
946 clocks = <&gcc GCC_EMA
947 <&gcc GCC_EMAC
948 <&gcc GCC_EMAC
949 <&gcc GCC_EMAC
950 interrupts = <GIC_SPI
951 <GIC_SPI
952 interrupt-names = "mac
953
954 power-domains = <&gcc
955 resets = <&gcc GCC_EMA
956
957 iommus = <&apps_smmu 0
958
959 snps,tso;
960 rx-fifo-depth = <4096>
961 tx-fifo-depth = <4096>
962
963 status = "disabled";
964 };
965
966 qfprom: efuse@784000 {
967 compatible = "qcom,sm8
968 reg = <0 0x00784000 0
969 #address-cells = <1>;
970 #size-cells = <1>;
971
972 gpu_speed_bin: gpu-spe
973 reg = <0x133 0
974 bits = <5 3>;
975 };
976 };
977
978 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen
980 reg = <0x0 0x008c0000
981 clock-names = "m-ahb",
982 clocks = <&gcc GCC_QUP
983 <&gcc GCC_QUP
984 iommus = <&apps_smmu 0
985 #address-cells = <2>;
986 #size-cells = <2>;
987 ranges;
988 status = "disabled";
989
990 i2c0: i2c@880000 {
991 compatible = "
992 reg = <0 0x008
993 clock-names =
994 clocks = <&gcc
995 dmas = <&gpi_d
996 <&gpi_d
997 dma-names = "t
998 pinctrl-names
999 pinctrl-0 = <&
1000 interrupts =
1001 #address-cell
1002 #size-cells =
1003 status = "dis
1004 };
1005
1006 spi0: spi@880000 {
1007 compatible =
1008 reg = <0 0x00
1009 reg-names = "
1010 clock-names =
1011 clocks = <&gc
1012 dmas = <&gpi_
1013 <&gpi_
1014 dma-names = "
1015 pinctrl-names
1016 pinctrl-0 = <
1017 interrupts =
1018 spi-max-frequ
1019 #address-cell
1020 #size-cells =
1021 status = "dis
1022 };
1023
1024 i2c1: i2c@884000 {
1025 compatible =
1026 reg = <0 0x00
1027 clock-names =
1028 clocks = <&gc
1029 dmas = <&gpi_
1030 <&gpi_
1031 dma-names = "
1032 pinctrl-names
1033 pinctrl-0 = <
1034 interrupts =
1035 #address-cell
1036 #size-cells =
1037 status = "dis
1038 };
1039
1040 spi1: spi@884000 {
1041 compatible =
1042 reg = <0 0x00
1043 reg-names = "
1044 clock-names =
1045 clocks = <&gc
1046 dmas = <&gpi_
1047 <&gpi_
1048 dma-names = "
1049 pinctrl-names
1050 pinctrl-0 = <
1051 interrupts =
1052 spi-max-frequ
1053 #address-cell
1054 #size-cells =
1055 status = "dis
1056 };
1057
1058 i2c2: i2c@888000 {
1059 compatible =
1060 reg = <0 0x00
1061 clock-names =
1062 clocks = <&gc
1063 dmas = <&gpi_
1064 <&gpi_
1065 dma-names = "
1066 pinctrl-names
1067 pinctrl-0 = <
1068 interrupts =
1069 #address-cell
1070 #size-cells =
1071 status = "dis
1072 };
1073
1074 spi2: spi@888000 {
1075 compatible =
1076 reg = <0 0x00
1077 reg-names = "
1078 clock-names =
1079 clocks = <&gc
1080 dmas = <&gpi_
1081 <&gpi_
1082 dma-names = "
1083 pinctrl-names
1084 pinctrl-0 = <
1085 interrupts =
1086 spi-max-frequ
1087 #address-cell
1088 #size-cells =
1089 status = "dis
1090 };
1091
1092 i2c3: i2c@88c000 {
1093 compatible =
1094 reg = <0 0x00
1095 clock-names =
1096 clocks = <&gc
1097 dmas = <&gpi_
1098 <&gpi_
1099 dma-names = "
1100 pinctrl-names
1101 pinctrl-0 = <
1102 interrupts =
1103 #address-cell
1104 #size-cells =
1105 status = "dis
1106 };
1107
1108 spi3: spi@88c000 {
1109 compatible =
1110 reg = <0 0x00
1111 reg-names = "
1112 clock-names =
1113 clocks = <&gc
1114 dmas = <&gpi_
1115 <&gpi_
1116 dma-names = "
1117 pinctrl-names
1118 pinctrl-0 = <
1119 interrupts =
1120 spi-max-frequ
1121 #address-cell
1122 #size-cells =
1123 status = "dis
1124 };
1125
1126 i2c4: i2c@890000 {
1127 compatible =
1128 reg = <0 0x00
1129 clock-names =
1130 clocks = <&gc
1131 dmas = <&gpi_
1132 <&gpi_
1133 dma-names = "
1134 pinctrl-names
1135 pinctrl-0 = <
1136 interrupts =
1137 #address-cell
1138 #size-cells =
1139 status = "dis
1140 };
1141
1142 spi4: spi@890000 {
1143 compatible =
1144 reg = <0 0x00
1145 reg-names = "
1146 clock-names =
1147 clocks = <&gc
1148 dmas = <&gpi_
1149 <&gpi_
1150 dma-names = "
1151 pinctrl-names
1152 pinctrl-0 = <
1153 interrupts =
1154 spi-max-frequ
1155 #address-cell
1156 #size-cells =
1157 status = "dis
1158 };
1159
1160 i2c5: i2c@894000 {
1161 compatible =
1162 reg = <0 0x00
1163 clock-names =
1164 clocks = <&gc
1165 dmas = <&gpi_
1166 <&gpi_
1167 dma-names = "
1168 pinctrl-names
1169 pinctrl-0 = <
1170 interrupts =
1171 #address-cell
1172 #size-cells =
1173 status = "dis
1174 };
1175
1176 spi5: spi@894000 {
1177 compatible =
1178 reg = <0 0x00
1179 reg-names = "
1180 clock-names =
1181 clocks = <&gc
1182 dmas = <&gpi_
1183 <&gpi_
1184 dma-names = "
1185 pinctrl-names
1186 pinctrl-0 = <
1187 interrupts =
1188 spi-max-frequ
1189 #address-cell
1190 #size-cells =
1191 status = "dis
1192 };
1193
1194 i2c6: i2c@898000 {
1195 compatible =
1196 reg = <0 0x00
1197 clock-names =
1198 clocks = <&gc
1199 dmas = <&gpi_
1200 <&gpi_
1201 dma-names = "
1202 pinctrl-names
1203 pinctrl-0 = <
1204 interrupts =
1205 #address-cell
1206 #size-cells =
1207 status = "dis
1208 };
1209
1210 spi6: spi@898000 {
1211 compatible =
1212 reg = <0 0x00
1213 reg-names = "
1214 clock-names =
1215 clocks = <&gc
1216 dmas = <&gpi_
1217 <&gpi_
1218 dma-names = "
1219 pinctrl-names
1220 pinctrl-0 = <
1221 interrupts =
1222 spi-max-frequ
1223 #address-cell
1224 #size-cells =
1225 status = "dis
1226 };
1227
1228 i2c7: i2c@89c000 {
1229 compatible =
1230 reg = <0 0x00
1231 clock-names =
1232 clocks = <&gc
1233 dmas = <&gpi_
1234 <&gpi_
1235 dma-names = "
1236 pinctrl-names
1237 pinctrl-0 = <
1238 interrupts =
1239 #address-cell
1240 #size-cells =
1241 status = "dis
1242 };
1243
1244 spi7: spi@89c000 {
1245 compatible =
1246 reg = <0 0x00
1247 reg-names = "
1248 clock-names =
1249 clocks = <&gc
1250 dmas = <&gpi_
1251 <&gpi_
1252 dma-names = "
1253 pinctrl-names
1254 pinctrl-0 = <
1255 interrupts =
1256 spi-max-frequ
1257 #address-cell
1258 #size-cells =
1259 status = "dis
1260 };
1261 };
1262
1263 gpi_dma1: dma-controller@a000
1264 compatible = "qcom,sm
1265 reg = <0 0x00a00000 0
1266 interrupts = <GIC_SPI
1267 <GIC_SPI
1268 <GIC_SPI
1269 <GIC_SPI
1270 <GIC_SPI
1271 <GIC_SPI
1272 <GIC_SPI
1273 <GIC_SPI
1274 <GIC_SPI
1275 <GIC_SPI
1276 <GIC_SPI
1277 <GIC_SPI
1278 <GIC_SPI
1279 dma-channels = <13>;
1280 dma-channel-mask = <0
1281 iommus = <&apps_smmu
1282 #dma-cells = <3>;
1283 status = "disabled";
1284 };
1285
1286 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge
1288 reg = <0x0 0x00ac0000
1289 clock-names = "m-ahb"
1290 clocks = <&gcc GCC_QU
1291 <&gcc GCC_QU
1292 iommus = <&apps_smmu
1293 #address-cells = <2>;
1294 #size-cells = <2>;
1295 ranges;
1296 status = "disabled";
1297
1298 i2c8: i2c@a80000 {
1299 compatible =
1300 reg = <0 0x00
1301 clock-names =
1302 clocks = <&gc
1303 dmas = <&gpi_
1304 <&gpi_
1305 dma-names = "
1306 pinctrl-names
1307 pinctrl-0 = <
1308 interrupts =
1309 #address-cell
1310 #size-cells =
1311 status = "dis
1312 };
1313
1314 spi8: spi@a80000 {
1315 compatible =
1316 reg = <0 0x00
1317 reg-names = "
1318 clock-names =
1319 clocks = <&gc
1320 dmas = <&gpi_
1321 <&gpi_
1322 dma-names = "
1323 pinctrl-names
1324 pinctrl-0 = <
1325 interrupts =
1326 spi-max-frequ
1327 #address-cell
1328 #size-cells =
1329 status = "dis
1330 };
1331
1332 i2c9: i2c@a84000 {
1333 compatible =
1334 reg = <0 0x00
1335 clock-names =
1336 clocks = <&gc
1337 dmas = <&gpi_
1338 <&gpi_
1339 dma-names = "
1340 pinctrl-names
1341 pinctrl-0 = <
1342 interrupts =
1343 #address-cell
1344 #size-cells =
1345 status = "dis
1346 };
1347
1348 spi9: spi@a84000 {
1349 compatible =
1350 reg = <0 0x00
1351 reg-names = "
1352 clock-names =
1353 clocks = <&gc
1354 dmas = <&gpi_
1355 <&gpi_
1356 dma-names = "
1357 pinctrl-names
1358 pinctrl-0 = <
1359 interrupts =
1360 spi-max-frequ
1361 #address-cell
1362 #size-cells =
1363 status = "dis
1364 };
1365
1366 uart9: serial@a84000
1367 compatible =
1368 reg = <0x0 0x
1369 clocks = <&gc
1370 clock-names =
1371 pinctrl-0 = <
1372 pinctrl-names
1373 interrupts =
1374 status = "dis
1375 };
1376
1377 i2c10: i2c@a88000 {
1378 compatible =
1379 reg = <0 0x00
1380 clock-names =
1381 clocks = <&gc
1382 dmas = <&gpi_
1383 <&gpi_
1384 dma-names = "
1385 pinctrl-names
1386 pinctrl-0 = <
1387 interrupts =
1388 #address-cell
1389 #size-cells =
1390 status = "dis
1391 };
1392
1393 spi10: spi@a88000 {
1394 compatible =
1395 reg = <0 0x00
1396 reg-names = "
1397 clock-names =
1398 clocks = <&gc
1399 dmas = <&gpi_
1400 <&gpi_
1401 dma-names = "
1402 pinctrl-names
1403 pinctrl-0 = <
1404 interrupts =
1405 spi-max-frequ
1406 #address-cell
1407 #size-cells =
1408 status = "dis
1409 };
1410
1411 i2c11: i2c@a8c000 {
1412 compatible =
1413 reg = <0 0x00
1414 clock-names =
1415 clocks = <&gc
1416 dmas = <&gpi_
1417 <&gpi_
1418 dma-names = "
1419 pinctrl-names
1420 pinctrl-0 = <
1421 interrupts =
1422 #address-cell
1423 #size-cells =
1424 status = "dis
1425 };
1426
1427 spi11: spi@a8c000 {
1428 compatible =
1429 reg = <0 0x00
1430 reg-names = "
1431 clock-names =
1432 clocks = <&gc
1433 dmas = <&gpi_
1434 <&gpi_
1435 dma-names = "
1436 pinctrl-names
1437 pinctrl-0 = <
1438 interrupts =
1439 spi-max-frequ
1440 #address-cell
1441 #size-cells =
1442 status = "dis
1443 };
1444
1445 uart2: serial@a90000
1446 compatible =
1447 reg = <0x0 0x
1448 clock-names =
1449 clocks = <&gc
1450 interrupts =
1451 status = "dis
1452 };
1453
1454 i2c12: i2c@a90000 {
1455 compatible =
1456 reg = <0 0x00
1457 clock-names =
1458 clocks = <&gc
1459 dmas = <&gpi_
1460 <&gpi_
1461 dma-names = "
1462 pinctrl-names
1463 pinctrl-0 = <
1464 interrupts =
1465 #address-cell
1466 #size-cells =
1467 status = "dis
1468 };
1469
1470 spi12: spi@a90000 {
1471 compatible =
1472 reg = <0 0x00
1473 reg-names = "
1474 clock-names =
1475 clocks = <&gc
1476 dmas = <&gpi_
1477 <&gpi_
1478 dma-names = "
1479 pinctrl-names
1480 pinctrl-0 = <
1481 interrupts =
1482 spi-max-frequ
1483 #address-cell
1484 #size-cells =
1485 status = "dis
1486 };
1487
1488 i2c16: i2c@94000 {
1489 compatible =
1490 reg = <0 0x00
1491 clock-names =
1492 clocks = <&gc
1493 dmas = <&gpi_
1494 <&gpi_
1495 dma-names = "
1496 pinctrl-names
1497 pinctrl-0 = <
1498 interrupts =
1499 #address-cell
1500 #size-cells =
1501 status = "dis
1502 };
1503
1504 spi16: spi@a94000 {
1505 compatible =
1506 reg = <0 0x00
1507 reg-names = "
1508 clock-names =
1509 clocks = <&gc
1510 dmas = <&gpi_
1511 <&gpi_
1512 dma-names = "
1513 pinctrl-names
1514 pinctrl-0 = <
1515 interrupts =
1516 spi-max-frequ
1517 #address-cell
1518 #size-cells =
1519 status = "dis
1520 };
1521 };
1522
1523 gpi_dma2: dma-controller@c000
1524 compatible = "qcom,sm
1525 reg = <0 0x00c00000 0
1526 interrupts = <GIC_SPI
1527 <GIC_SPI
1528 <GIC_SPI
1529 <GIC_SPI
1530 <GIC_SPI
1531 <GIC_SPI
1532 <GIC_SPI
1533 <GIC_SPI
1534 <GIC_SPI
1535 <GIC_SPI
1536 <GIC_SPI
1537 <GIC_SPI
1538 <GIC_SPI
1539 dma-channels = <13>;
1540 dma-channel-mask = <0
1541 iommus = <&apps_smmu
1542 #dma-cells = <3>;
1543 status = "disabled";
1544 };
1545
1546 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge
1548 reg = <0x0 0x00cc0000
1549
1550 clock-names = "m-ahb"
1551 clocks = <&gcc GCC_QU
1552 <&gcc GCC_QU
1553 iommus = <&apps_smmu
1554 #address-cells = <2>;
1555 #size-cells = <2>;
1556 ranges;
1557 status = "disabled";
1558
1559 i2c17: i2c@c80000 {
1560 compatible =
1561 reg = <0 0x00
1562 clock-names =
1563 clocks = <&gc
1564 dmas = <&gpi_
1565 <&gpi_
1566 dma-names = "
1567 pinctrl-names
1568 pinctrl-0 = <
1569 interrupts =
1570 #address-cell
1571 #size-cells =
1572 status = "dis
1573 };
1574
1575 spi17: spi@c80000 {
1576 compatible =
1577 reg = <0 0x00
1578 reg-names = "
1579 clock-names =
1580 clocks = <&gc
1581 dmas = <&gpi_
1582 <&gpi_
1583 dma-names = "
1584 pinctrl-names
1585 pinctrl-0 = <
1586 interrupts =
1587 spi-max-frequ
1588 #address-cell
1589 #size-cells =
1590 status = "dis
1591 };
1592
1593 i2c18: i2c@c84000 {
1594 compatible =
1595 reg = <0 0x00
1596 clock-names =
1597 clocks = <&gc
1598 dmas = <&gpi_
1599 <&gpi_
1600 dma-names = "
1601 pinctrl-names
1602 pinctrl-0 = <
1603 interrupts =
1604 #address-cell
1605 #size-cells =
1606 status = "dis
1607 };
1608
1609 spi18: spi@c84000 {
1610 compatible =
1611 reg = <0 0x00
1612 reg-names = "
1613 clock-names =
1614 clocks = <&gc
1615 dmas = <&gpi_
1616 <&gpi_
1617 dma-names = "
1618 pinctrl-names
1619 pinctrl-0 = <
1620 interrupts =
1621 spi-max-frequ
1622 #address-cell
1623 #size-cells =
1624 status = "dis
1625 };
1626
1627 i2c19: i2c@c88000 {
1628 compatible =
1629 reg = <0 0x00
1630 clock-names =
1631 clocks = <&gc
1632 dmas = <&gpi_
1633 <&gpi_
1634 dma-names = "
1635 pinctrl-names
1636 pinctrl-0 = <
1637 interrupts =
1638 #address-cell
1639 #size-cells =
1640 status = "dis
1641 };
1642
1643 spi19: spi@c88000 {
1644 compatible =
1645 reg = <0 0x00
1646 reg-names = "
1647 clock-names =
1648 clocks = <&gc
1649 dmas = <&gpi_
1650 <&gpi_
1651 dma-names = "
1652 pinctrl-names
1653 pinctrl-0 = <
1654 interrupts =
1655 spi-max-frequ
1656 #address-cell
1657 #size-cells =
1658 status = "dis
1659 };
1660
1661 i2c13: i2c@c8c000 {
1662 compatible =
1663 reg = <0 0x00
1664 clock-names =
1665 clocks = <&gc
1666 dmas = <&gpi_
1667 <&gpi_
1668 dma-names = "
1669 pinctrl-names
1670 pinctrl-0 = <
1671 interrupts =
1672 #address-cell
1673 #size-cells =
1674 status = "dis
1675 };
1676
1677 spi13: spi@c8c000 {
1678 compatible =
1679 reg = <0 0x00
1680 reg-names = "
1681 clock-names =
1682 clocks = <&gc
1683 dmas = <&gpi_
1684 <&gpi_
1685 dma-names = "
1686 pinctrl-names
1687 pinctrl-0 = <
1688 interrupts =
1689 spi-max-frequ
1690 #address-cell
1691 #size-cells =
1692 status = "dis
1693 };
1694
1695 i2c14: i2c@c90000 {
1696 compatible =
1697 reg = <0 0x00
1698 clock-names =
1699 clocks = <&gc
1700 dmas = <&gpi_
1701 <&gpi_
1702 dma-names = "
1703 pinctrl-names
1704 pinctrl-0 = <
1705 interrupts =
1706 #address-cell
1707 #size-cells =
1708 status = "dis
1709 };
1710
1711 spi14: spi@c90000 {
1712 compatible =
1713 reg = <0 0x00
1714 reg-names = "
1715 clock-names =
1716 clocks = <&gc
1717 dmas = <&gpi_
1718 <&gpi_
1719 dma-names = "
1720 pinctrl-names
1721 pinctrl-0 = <
1722 interrupts =
1723 spi-max-frequ
1724 #address-cell
1725 #size-cells =
1726 status = "dis
1727 };
1728
1729 i2c15: i2c@c94000 {
1730 compatible =
1731 reg = <0 0x00
1732 clock-names =
1733 clocks = <&gc
1734 dmas = <&gpi_
1735 <&gpi_
1736 dma-names = "
1737 pinctrl-names
1738 pinctrl-0 = <
1739 interrupts =
1740 #address-cell
1741 #size-cells =
1742 status = "dis
1743 };
1744
1745 spi15: spi@c94000 {
1746 compatible =
1747 reg = <0 0x00
1748 reg-names = "
1749 clock-names =
1750 clocks = <&gc
1751 dmas = <&gpi_
1752 <&gpi_
1753 dma-names = "
1754 pinctrl-names
1755 pinctrl-0 = <
1756 interrupts =
1757 spi-max-frequ
1758 #address-cell
1759 #size-cells =
1760 status = "dis
1761 };
1762 };
1763
1764 config_noc: interconnect@1500
1765 compatible = "qcom,sm
1766 reg = <0 0x01500000 0
1767 #interconnect-cells =
1768 qcom,bcm-voters = <&a
1769 };
1770
1771 system_noc: interconnect@1620
1772 compatible = "qcom,sm
1773 reg = <0 0x01620000 0
1774 #interconnect-cells =
1775 qcom,bcm-voters = <&a
1776 };
1777
1778 mc_virt: interconnect@163a000
1779 compatible = "qcom,sm
1780 reg = <0 0x0163a000 0
1781 #interconnect-cells =
1782 qcom,bcm-voters = <&a
1783 };
1784
1785 aggre1_noc: interconnect@16e0
1786 compatible = "qcom,sm
1787 reg = <0 0x016e0000 0
1788 #interconnect-cells =
1789 qcom,bcm-voters = <&a
1790 };
1791
1792 aggre2_noc: interconnect@1700
1793 compatible = "qcom,sm
1794 reg = <0 0x01700000 0
1795 #interconnect-cells =
1796 qcom,bcm-voters = <&a
1797 };
1798
1799 compute_noc: interconnect@172
1800 compatible = "qcom,sm
1801 reg = <0 0x01720000 0
1802 #interconnect-cells =
1803 qcom,bcm-voters = <&a
1804 };
1805
1806 mmss_noc: interconnect@174000
1807 compatible = "qcom,sm
1808 reg = <0 0x01740000 0
1809 #interconnect-cells =
1810 qcom,bcm-voters = <&a
1811 };
1812
1813 system-cache-controller@92000
1814 compatible = "qcom,sm
1815 reg = <0 0x09200000 0
1816 <0 0x09300000 0
1817 <0 0x09600000 0
1818 reg-names = "llcc0_ba
1819 "llcc3_ba
1820 interrupts = <GIC_SPI
1821 };
1822
1823 dma@10a2000 {
1824 compatible = "qcom,sm
1825 reg = <0x0 0x010a2000
1826 <0x0 0x010ad000
1827 };
1828
1829 pcie0: pcie@1c00000 {
1830 compatible = "qcom,pc
1831 reg = <0 0x01c00000 0
1832 <0 0x60000000 0
1833 <0 0x60000f20 0
1834 <0 0x60001000 0
1835 <0 0x60100000 0
1836 reg-names = "parf", "
1837 device_type = "pci";
1838 linux,pci-domain = <0
1839 bus-range = <0x00 0xf
1840 num-lanes = <1>;
1841
1842 #address-cells = <3>;
1843 #size-cells = <2>;
1844
1845 ranges = <0x01000000
1846 <0x02000000
1847
1848 interrupts = <GIC_SPI
1849 <GIC_SPI
1850 <GIC_SPI
1851 <GIC_SPI
1852 <GIC_SPI
1853 <GIC_SPI
1854 <GIC_SPI
1855 <GIC_SPI
1856 interrupt-names = "ms
1857 "ms
1858 "ms
1859 "ms
1860 "ms
1861 "ms
1862 "ms
1863 "ms
1864 #interrupt-cells = <1
1865 interrupt-map-mask =
1866 interrupt-map = <0 0
1867 <0 0
1868 <0 0
1869 <0 0
1870
1871 clocks = <&gcc GCC_PC
1872 <&gcc GCC_PC
1873 <&gcc GCC_PC
1874 <&gcc GCC_PC
1875 <&gcc GCC_PC
1876 <&gcc GCC_PC
1877 <&gcc GCC_AG
1878 <&rpmhcc RPM
1879 clock-names = "pipe",
1880 "aux",
1881 "cfg",
1882 "bus_ma
1883 "bus_sl
1884 "slave_
1885 "tbu",
1886 "ref";
1887
1888 iommu-map = <0x0 &a
1889 <0x100 &a
1890
1891 resets = <&gcc GCC_PC
1892 reset-names = "pci";
1893
1894 power-domains = <&gcc
1895
1896 phys = <&pcie0_phy>;
1897 phy-names = "pciephy"
1898
1899 perst-gpios = <&tlmm
1900 wake-gpios = <&tlmm 3
1901
1902 pinctrl-names = "defa
1903 pinctrl-0 = <&pcie0_d
1904
1905 status = "disabled";
1906
1907 pcie@0 {
1908 device_type =
1909 reg = <0x0 0x
1910 bus-range = <
1911
1912 #address-cell
1913 #size-cells =
1914 ranges;
1915 };
1916 };
1917
1918 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm
1920 reg = <0 0x01c06000 0
1921 clocks = <&gcc GCC_PC
1922 <&gcc GCC_PC
1923 <&gcc GCC_PC
1924 <&gcc GCC_PC
1925 <&gcc GCC_PC
1926 clock-names = "aux",
1927 "cfg_ah
1928 "ref",
1929 "refgen
1930 "pipe";
1931
1932 clock-output-names =
1933 #clock-cells = <0>;
1934
1935 #phy-cells = <0>;
1936
1937 resets = <&gcc GCC_PC
1938 reset-names = "phy";
1939
1940 assigned-clocks = <&g
1941 assigned-clock-rates
1942
1943 status = "disabled";
1944 };
1945
1946 pcie1: pcie@1c08000 {
1947 compatible = "qcom,pc
1948 reg = <0 0x01c08000 0
1949 <0 0x40000000 0
1950 <0 0x40000f20 0
1951 <0 0x40001000 0
1952 <0 0x40100000 0
1953 reg-names = "parf", "
1954 device_type = "pci";
1955 linux,pci-domain = <1
1956 bus-range = <0x00 0xf
1957 num-lanes = <2>;
1958
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1961
1962 ranges = <0x01000000
1963 <0x02000000
1964
1965 interrupts = <GIC_SPI
1966 <GIC_SPI
1967 <GIC_SPI
1968 <GIC_SPI
1969 <GIC_SPI
1970 <GIC_SPI
1971 <GIC_SPI
1972 <GIC_SPI
1973 interrupt-names = "ms
1974 "ms
1975 "ms
1976 "ms
1977 "ms
1978 "ms
1979 "ms
1980 "ms
1981 #interrupt-cells = <1
1982 interrupt-map-mask =
1983 interrupt-map = <0 0
1984 <0 0
1985 <0 0
1986 <0 0
1987
1988 clocks = <&gcc GCC_PC
1989 <&gcc GCC_PC
1990 <&gcc GCC_PC
1991 <&gcc GCC_PC
1992 <&gcc GCC_PC
1993 <&gcc GCC_PC
1994 <&gcc GCC_AG
1995 <&rpmhcc RPM
1996 clock-names = "pipe",
1997 "aux",
1998 "cfg",
1999 "bus_ma
2000 "bus_sl
2001 "slave_
2002 "tbu",
2003 "ref";
2004
2005 assigned-clocks = <&g
2006 assigned-clock-rates
2007
2008 iommu-map = <0x0 &a
2009 <0x100 &a
2010
2011 resets = <&gcc GCC_PC
2012 reset-names = "pci";
2013
2014 power-domains = <&gcc
2015
2016 phys = <&pcie1_phy>;
2017 phy-names = "pciephy"
2018
2019 perst-gpios = <&tlmm
2020 enable-gpio = <&tlmm
2021
2022 pinctrl-names = "defa
2023 pinctrl-0 = <&pcie1_d
2024
2025 status = "disabled";
2026
2027 pcie@0 {
2028 device_type =
2029 reg = <0x0 0x
2030 bus-range = <
2031
2032 #address-cell
2033 #size-cells =
2034 ranges;
2035 };
2036 };
2037
2038 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm
2040 reg = <0 0x01c0e000 0
2041 clocks = <&gcc GCC_PC
2042 <&gcc GCC_PC
2043 <&gcc GCC_PC
2044 <&gcc GCC_PC
2045 <&gcc GCC_PC
2046 clock-names = "aux",
2047 "cfg_ah
2048 "ref",
2049 "refgen
2050 "pipe";
2051
2052 clock-output-names =
2053 #clock-cells = <0>;
2054
2055 #phy-cells = <0>;
2056
2057 resets = <&gcc GCC_PC
2058 reset-names = "phy";
2059
2060 assigned-clocks = <&g
2061 assigned-clock-rates
2062
2063 status = "disabled";
2064 };
2065
2066 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm
2068 "jedec,u
2069 reg = <0 0x01d84000 0
2070 <0 0x01d90000 0
2071 reg-names = "std", "i
2072 interrupts = <GIC_SPI
2073 phys = <&ufs_mem_phy>
2074 phy-names = "ufsphy";
2075 lanes-per-direction =
2076 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF
2078 reset-names = "rst";
2079
2080 iommus = <&apps_smmu
2081
2082 clock-names =
2083 "core_clk",
2084 "bus_aggr_clk
2085 "iface_clk",
2086 "core_clk_uni
2087 "ref_clk",
2088 "tx_lane0_syn
2089 "rx_lane0_syn
2090 "rx_lane1_syn
2091 "ice_core_clk
2092 clocks =
2093 <&gcc GCC_UFS
2094 <&gcc GCC_AGG
2095 <&gcc GCC_UFS
2096 <&gcc GCC_UFS
2097 <&rpmhcc RPMH
2098 <&gcc GCC_UFS
2099 <&gcc GCC_UFS
2100 <&gcc GCC_UFS
2101 <&gcc GCC_UFS
2102 freq-table-hz =
2103 <37500000 300
2104 <0 0>,
2105 <0 0>,
2106 <37500000 300
2107 <0 0>,
2108 <0 0>,
2109 <0 0>,
2110 <0 0>,
2111 <0 300000000>
2112
2113 status = "disabled";
2114 };
2115
2116 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm
2118 reg = <0 0x01d87000 0
2119
2120 clocks = <&rpmhcc RPM
2121 <&gcc GCC_UF
2122 <&gcc GCC_UF
2123 clock-names = "ref",
2124 "ref_au
2125 "qref";
2126
2127 power-domains = <&gcc
2128
2129 resets = <&ufs_mem_hc
2130 reset-names = "ufsphy
2131
2132 #phy-cells = <0>;
2133
2134 status = "disabled";
2135 };
2136
2137 cryptobam: dma-controller@1dc
2138 compatible = "qcom,ba
2139 reg = <0 0x01dc4000 0
2140 interrupts = <GIC_SPI
2141 #dma-cells = <1>;
2142 qcom,ee = <0>;
2143 qcom,controlled-remot
2144 num-channels = <8>;
2145 qcom,num-ees = <2>;
2146 iommus = <&apps_smmu
2147 <&apps_smmu
2148 <&apps_smmu
2149 <&apps_smmu
2150 <&apps_smmu
2151 };
2152
2153 crypto: crypto@1dfa000 {
2154 compatible = "qcom,sm
2155 reg = <0 0x01dfa000 0
2156 dmas = <&cryptobam 4>
2157 dma-names = "rx", "tx
2158 iommus = <&apps_smmu
2159 <&apps_smmu
2160 <&apps_smmu
2161 <&apps_smmu
2162 <&apps_smmu
2163 interconnects = <&agg
2164 interconnect-names =
2165 };
2166
2167 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc
2169 reg = <0x0 0x01f40000
2170 #hwlock-cells = <1>;
2171 };
2172
2173 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm
2175 reg = <0x0 0x01f60000
2176 };
2177
2178 remoteproc_slpi: remoteproc@2
2179 compatible = "qcom,sm
2180 reg = <0x0 0x02400000
2181
2182 interrupts-extended =
2183
2184
2185
2186
2187 interrupt-names = "wd
2188 "ha
2189
2190 clocks = <&rpmhcc RPM
2191 clock-names = "xo";
2192
2193 power-domains = <&rpm
2194 <&rpm
2195 power-domain-names =
2196
2197 memory-region = <&slp
2198
2199 qcom,qmp = <&aoss_qmp
2200
2201 qcom,smem-states = <&
2202 qcom,smem-state-names
2203
2204 status = "disabled";
2205
2206 glink-edge {
2207 interrupts =
2208 label = "dsps
2209 qcom,remote-p
2210 mboxes = <&ap
2211
2212 fastrpc {
2213 compa
2214 qcom,
2215 label
2216 qcom,
2217 #addr
2218 #size
2219
2220 compu
2221
2222
2223
2224 };
2225
2226 compu
2227
2228
2229
2230 };
2231
2232 compu
2233
2234
2235
2236
2237 };
2238 };
2239 };
2240 };
2241
2242 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad
2244 reg = <0 0x02c00000 0
2245 reg-names = "kgsl_3d0
2246
2247 interrupts = <GIC_SPI
2248
2249 iommus = <&adreno_smm
2250
2251 operating-points-v2 =
2252
2253 qcom,gmu = <&gmu>;
2254
2255 nvmem-cells = <&gpu_s
2256 nvmem-cell-names = "s
2257 #cooling-cells = <2>;
2258
2259 status = "disabled";
2260
2261 zap-shader {
2262 memory-region
2263 };
2264
2265 gpu_opp_table: opp-ta
2266 compatible =
2267
2268 opp-675000000
2269 opp-h
2270 opp-l
2271 opp-s
2272 };
2273
2274 opp-585000000
2275 opp-h
2276 opp-l
2277 opp-s
2278 };
2279
2280 opp-499200000
2281 opp-h
2282 opp-l
2283 opp-s
2284 };
2285
2286 opp-427000000
2287 opp-h
2288 opp-l
2289 opp-s
2290 };
2291
2292 opp-345000000
2293 opp-h
2294 opp-l
2295 opp-s
2296 };
2297
2298 opp-257000000
2299 opp-h
2300 opp-l
2301 opp-s
2302 };
2303 };
2304 };
2305
2306 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad
2308
2309 reg = <0 0x02c6a000 0
2310 <0 0x0b290000 0
2311 <0 0x0b490000 0
2312 reg-names = "gmu", "g
2313
2314 interrupts = <GIC_SPI
2315 <GIC_SPI
2316 interrupt-names = "hf
2317
2318 clocks = <&gpucc GPU_
2319 <&gpucc GPU_
2320 <&gpucc GPU_
2321 <&gcc GCC_DD
2322 <&gcc GCC_GP
2323 clock-names = "ahb",
2324
2325 power-domains = <&gpu
2326 <&gpu
2327 power-domain-names =
2328
2329 iommus = <&adreno_smm
2330
2331 operating-points-v2 =
2332
2333 status = "disabled";
2334
2335 gmu_opp_table: opp-ta
2336 compatible =
2337
2338 opp-200000000
2339 opp-h
2340 opp-l
2341 };
2342 };
2343 };
2344
2345 gpucc: clock-controller@2c900
2346 compatible = "qcom,sm
2347 reg = <0 0x02c90000 0
2348 clocks = <&rpmhcc RPM
2349 <&gcc GCC_GP
2350 <&gcc GCC_GP
2351 clock-names = "bi_tcx
2352 "gcc_gp
2353 "gcc_gp
2354 #clock-cells = <1>;
2355 #reset-cells = <1>;
2356 #power-domain-cells =
2357 };
2358
2359 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm
2361 "qcom,sm
2362 reg = <0 0x02ca0000 0
2363 #iommu-cells = <2>;
2364 #global-interrupts =
2365 interrupts = <GIC_SPI
2366 <GIC_SPI 681
2367 <GIC_SPI 682
2368 <GIC_SPI 683
2369 <GIC_SPI 684
2370 <GIC_SPI 685
2371 <GIC_SPI 686
2372 <GIC_SPI 687
2373 <GIC_SPI 688
2374 clocks = <&gpucc GPU_
2375 <&gcc GCC_GP
2376 <&gcc GCC_GP
2377 clock-names = "ahb",
2378
2379 power-domains = <&gpu
2380 };
2381
2382 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm
2384 reg = <0x0 0x03100000
2385 <0x0 0x03500000
2386 <0x0 0x03900000
2387 <0x0 0x03D00000
2388 reg-names = "west", "
2389 interrupts = <GIC_SPI
2390 gpio-ranges = <&tlmm
2391 gpio-controller;
2392 #gpio-cells = <2>;
2393 interrupt-controller;
2394 #interrupt-cells = <2
2395 wakeup-parent = <&pdc
2396
2397 qup_i2c0_default: qup
2398 pins = "gpio0
2399 function = "q
2400 drive-strengt
2401 bias-disable;
2402 };
2403
2404 qup_spi0_default: qup
2405 pins = "gpio0
2406 function = "q
2407 drive-strengt
2408 bias-disable;
2409 };
2410
2411 qup_i2c1_default: qup
2412 pins = "gpio1
2413 function = "q
2414 drive-strengt
2415 bias-disable;
2416 };
2417
2418 qup_spi1_default: qup
2419 pins = "gpio1
2420 function = "q
2421 drive-strengt
2422 bias-disable;
2423 };
2424
2425 qup_i2c2_default: qup
2426 pins = "gpio1
2427 function = "q
2428 drive-strengt
2429 bias-disable;
2430 };
2431
2432 qup_spi2_default: qup
2433 pins = "gpio1
2434 function = "q
2435 drive-strengt
2436 bias-disable;
2437 };
2438
2439 qup_i2c3_default: qup
2440 pins = "gpio1
2441 function = "q
2442 drive-strengt
2443 bias-disable;
2444 };
2445
2446 qup_spi3_default: qup
2447 pins = "gpio1
2448 function = "q
2449 drive-strengt
2450 bias-disable;
2451 };
2452
2453 qup_i2c4_default: qup
2454 pins = "gpio5
2455 function = "q
2456 drive-strengt
2457 bias-disable;
2458 };
2459
2460 qup_spi4_default: qup
2461 pins = "gpio5
2462 function = "q
2463 drive-strengt
2464 bias-disable;
2465 };
2466
2467 qup_i2c5_default: qup
2468 pins = "gpio1
2469 function = "q
2470 drive-strengt
2471 bias-disable;
2472 };
2473
2474 qup_spi5_default: qup
2475 pins = "gpio1
2476 function = "q
2477 drive-strengt
2478 bias-disable;
2479 };
2480
2481 qup_i2c6_default: qup
2482 pins = "gpio6
2483 function = "q
2484 drive-strengt
2485 bias-disable;
2486 };
2487
2488 qup_spi6_default: qup
2489 pins = "gpio4
2490 function = "q
2491 drive-strengt
2492 bias-disable;
2493 };
2494
2495 qup_i2c7_default: qup
2496 pins = "gpio9
2497 function = "q
2498 drive-strengt
2499 bias-disable;
2500 };
2501
2502 qup_spi7_default: qup
2503 pins = "gpio9
2504 function = "q
2505 drive-strengt
2506 bias-disable;
2507 };
2508
2509 qup_i2c8_default: qup
2510 pins = "gpio8
2511 function = "q
2512 drive-strengt
2513 bias-disable;
2514 };
2515
2516 qup_spi8_default: qup
2517 pins = "gpio8
2518 function = "q
2519 drive-strengt
2520 bias-disable;
2521 };
2522
2523 qup_i2c9_default: qup
2524 pins = "gpio3
2525 function = "q
2526 drive-strengt
2527 bias-disable;
2528 };
2529
2530 qup_spi9_default: qup
2531 pins = "gpio3
2532 function = "q
2533 drive-strengt
2534 bias-disable;
2535 };
2536
2537 qup_uart9_default: qu
2538 pins = "gpio4
2539 function = "q
2540 drive-strengt
2541 bias-disable;
2542 };
2543
2544 qup_i2c10_default: qu
2545 pins = "gpio9
2546 function = "q
2547 drive-strengt
2548 bias-disable;
2549 };
2550
2551 qup_spi10_default: qu
2552 pins = "gpio9
2553 function = "q
2554 drive-strengt
2555 bias-disable;
2556 };
2557
2558 qup_i2c11_default: qu
2559 pins = "gpio9
2560 function = "q
2561 drive-strengt
2562 bias-disable;
2563 };
2564
2565 qup_spi11_default: qu
2566 pins = "gpio9
2567 function = "q
2568 drive-strengt
2569 bias-disable;
2570 };
2571
2572 qup_i2c12_default: qu
2573 pins = "gpio8
2574 function = "q
2575 drive-strengt
2576 bias-disable;
2577 };
2578
2579 qup_spi12_default: qu
2580 pins = "gpio8
2581 function = "q
2582 drive-strengt
2583 bias-disable;
2584 };
2585
2586 qup_i2c13_default: qu
2587 pins = "gpio4
2588 function = "q
2589 drive-strengt
2590 bias-disable;
2591 };
2592
2593 qup_spi13_default: qu
2594 pins = "gpio4
2595 function = "q
2596 drive-strengt
2597 bias-disable;
2598 };
2599
2600 qup_i2c14_default: qu
2601 pins = "gpio4
2602 function = "q
2603 drive-strengt
2604 bias-disable;
2605 };
2606
2607 qup_spi14_default: qu
2608 pins = "gpio4
2609 function = "q
2610 drive-strengt
2611 bias-disable;
2612 };
2613
2614 qup_i2c15_default: qu
2615 pins = "gpio2
2616 function = "q
2617 drive-strengt
2618 bias-disable;
2619 };
2620
2621 qup_spi15_default: qu
2622 pins = "gpio2
2623 function = "q
2624 drive-strengt
2625 bias-disable;
2626 };
2627
2628 qup_i2c16_default: qu
2629 pins = "gpio8
2630 function = "q
2631 drive-strengt
2632 bias-disable;
2633 };
2634
2635 qup_spi16_default: qu
2636 pins = "gpio8
2637 function = "q
2638 drive-strengt
2639 bias-disable;
2640 };
2641
2642 qup_i2c17_default: qu
2643 pins = "gpio5
2644 function = "q
2645 drive-strengt
2646 bias-disable;
2647 };
2648
2649 qup_spi17_default: qu
2650 pins = "gpio5
2651 function = "q
2652 drive-strengt
2653 bias-disable;
2654 };
2655
2656 qup_i2c18_default: qu
2657 pins = "gpio2
2658 function = "q
2659 drive-strengt
2660 bias-disable;
2661 };
2662
2663 qup_spi18_default: qu
2664 pins = "gpio2
2665 function = "q
2666 drive-strengt
2667 bias-disable;
2668 };
2669
2670 qup_i2c19_default: qu
2671 pins = "gpio5
2672 function = "q
2673 drive-strengt
2674 bias-disable;
2675 };
2676
2677 qup_spi19_default: qu
2678 pins = "gpio5
2679 function = "q
2680 drive-strengt
2681 bias-disable;
2682 };
2683
2684 pcie0_default_state:
2685 perst-pins {
2686 pins
2687 funct
2688 drive
2689 bias-
2690 };
2691
2692 clkreq-pins {
2693 pins
2694 funct
2695 drive
2696 bias-
2697 };
2698
2699 wake-pins {
2700 pins
2701 funct
2702 drive
2703 bias-
2704 };
2705 };
2706
2707 pcie1_default_state:
2708 perst-pins {
2709 pins
2710 funct
2711 drive
2712 bias-
2713 };
2714
2715 clkreq-pins {
2716 pins
2717 funct
2718 drive
2719 bias-
2720 };
2721
2722 wake-pins {
2723 pins
2724 funct
2725 drive
2726 bias-
2727 };
2728 };
2729 };
2730
2731 remoteproc_mpss: remoteproc@4
2732 compatible = "qcom,sm
2733 reg = <0x0 0x04080000
2734
2735 interrupts-extended =
2736
2737
2738
2739
2740
2741 interrupt-names = "wd
2742 "st
2743
2744 clocks = <&rpmhcc RPM
2745 clock-names = "xo";
2746
2747 power-domains = <&rpm
2748 <&rpm
2749 power-domain-names =
2750
2751 memory-region = <&mps
2752
2753 qcom,qmp = <&aoss_qmp
2754
2755 qcom,smem-states = <&
2756 qcom,smem-state-names
2757
2758 status = "disabled";
2759
2760 glink-edge {
2761 interrupts =
2762 label = "mode
2763 qcom,remote-p
2764 mboxes = <&ap
2765 };
2766 };
2767
2768 stm@6002000 {
2769 compatible = "arm,cor
2770 reg = <0 0x06002000 0
2771 <0 0x16280000 0
2772 reg-names = "stm-base
2773
2774 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc
2776
2777 out-ports {
2778 port {
2779 stm_o
2780
2781 };
2782 };
2783 };
2784 };
2785
2786 funnel@6041000 {
2787 compatible = "arm,cor
2788 reg = <0 0x06041000 0
2789
2790 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc
2792
2793 out-ports {
2794 port {
2795 funne
2796
2797 };
2798 };
2799 };
2800
2801 in-ports {
2802 #address-cell
2803 #size-cells =
2804
2805 port@7 {
2806 reg =
2807 funne
2808
2809 };
2810 };
2811 };
2812 };
2813
2814 funnel@6042000 {
2815 compatible = "arm,cor
2816 reg = <0 0x06042000 0
2817
2818 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc
2820
2821 out-ports {
2822 port {
2823 funne
2824
2825 };
2826 };
2827 };
2828
2829 in-ports {
2830 #address-cell
2831 #size-cells =
2832
2833 port@4 {
2834 reg =
2835 funne
2836
2837 };
2838 };
2839 };
2840 };
2841
2842 funnel@6043000 {
2843 compatible = "arm,cor
2844 reg = <0 0x06043000 0
2845
2846 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc
2848
2849 out-ports {
2850 port {
2851 funne
2852
2853 };
2854 };
2855 };
2856
2857 in-ports {
2858 #address-cell
2859 #size-cells =
2860
2861 port@2 {
2862 reg =
2863 funne
2864
2865 };
2866 };
2867 };
2868 };
2869
2870 funnel@6045000 {
2871 compatible = "arm,cor
2872 reg = <0 0x06045000 0
2873
2874 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc
2876
2877 out-ports {
2878 port {
2879 merge
2880
2881 };
2882 };
2883 };
2884
2885 in-ports {
2886 #address-cell
2887 #size-cells =
2888
2889 port@0 {
2890 reg =
2891 merge
2892
2893 };
2894 };
2895
2896 port@1 {
2897 reg =
2898 merge
2899
2900 };
2901 };
2902
2903 port@2 {
2904 reg =
2905 merge
2906
2907 };
2908 };
2909 };
2910 };
2911
2912 replicator@6046000 {
2913 compatible = "arm,cor
2914 reg = <0 0x06046000 0
2915
2916 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc
2918
2919 out-ports {
2920 #address-cell
2921 #size-cells =
2922
2923 port@0 {
2924 reg =
2925 repli
2926
2927 };
2928 };
2929
2930 port@1 {
2931 reg =
2932 repli
2933
2934 };
2935 };
2936 };
2937
2938 in-ports {
2939 port {
2940 repli
2941
2942 };
2943 };
2944 };
2945 };
2946
2947 etf@6047000 {
2948 compatible = "arm,cor
2949 reg = <0 0x06047000 0
2950
2951 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc
2953
2954 out-ports {
2955 port {
2956 etf_o
2957
2958 };
2959 };
2960 };
2961
2962 in-ports {
2963 port {
2964 etf_i
2965
2966 };
2967 };
2968 };
2969 };
2970
2971 etr@6048000 {
2972 compatible = "arm,cor
2973 reg = <0 0x06048000 0
2974 iommus = <&apps_smmu
2975
2976 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc
2978 arm,scatter-gather;
2979
2980 in-ports {
2981 port {
2982 etr_i
2983
2984 };
2985 };
2986 };
2987 };
2988
2989 replicator@604a000 {
2990 compatible = "arm,cor
2991 reg = <0 0x0604a000 0
2992
2993 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc
2995
2996 out-ports {
2997 #address-cell
2998 #size-cells =
2999
3000 port@1 {
3001 reg =
3002 repli
3003
3004 };
3005 };
3006 };
3007
3008 in-ports {
3009
3010 port {
3011 repli
3012
3013 };
3014 };
3015 };
3016 };
3017
3018 funnel@6b08000 {
3019 compatible = "arm,cor
3020 reg = <0 0x06b08000 0
3021
3022 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc
3024
3025 out-ports {
3026 port {
3027 swao_
3028
3029 };
3030 };
3031 };
3032
3033 in-ports {
3034 #address-cell
3035 #size-cells =
3036
3037 port@6 {
3038 reg =
3039 swao_
3040
3041 };
3042 };
3043 };
3044 };
3045
3046 etf@6b09000 {
3047 compatible = "arm,cor
3048 reg = <0 0x06b09000 0
3049
3050 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc
3052
3053 out-ports {
3054 port {
3055 swao_
3056
3057 };
3058 };
3059 };
3060
3061 in-ports {
3062 port {
3063 swao_
3064
3065 };
3066 };
3067 };
3068 };
3069
3070 replicator@6b0a000 {
3071 compatible = "arm,cor
3072 reg = <0 0x06b0a000 0
3073
3074 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc
3076 qcom,replicator-loses
3077
3078 out-ports {
3079 port {
3080 swao_
3081
3082 };
3083 };
3084 };
3085
3086 in-ports {
3087 port {
3088 swao_
3089
3090 };
3091 };
3092 };
3093 };
3094
3095 etm@7040000 {
3096 compatible = "arm,cor
3097 reg = <0 0x07040000 0
3098
3099 cpu = <&CPU0>;
3100
3101 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc
3103 arm,coresight-loses-c
3104 qcom,skip-power-up;
3105
3106 out-ports {
3107 port {
3108 etm0_
3109
3110 };
3111 };
3112 };
3113 };
3114
3115 etm@7140000 {
3116 compatible = "arm,cor
3117 reg = <0 0x07140000 0
3118
3119 cpu = <&CPU1>;
3120
3121 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc
3123 arm,coresight-loses-c
3124 qcom,skip-power-up;
3125
3126 out-ports {
3127 port {
3128 etm1_
3129
3130 };
3131 };
3132 };
3133 };
3134
3135 etm@7240000 {
3136 compatible = "arm,cor
3137 reg = <0 0x07240000 0
3138
3139 cpu = <&CPU2>;
3140
3141 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc
3143 arm,coresight-loses-c
3144 qcom,skip-power-up;
3145
3146 out-ports {
3147 port {
3148 etm2_
3149
3150 };
3151 };
3152 };
3153 };
3154
3155 etm@7340000 {
3156 compatible = "arm,cor
3157 reg = <0 0x07340000 0
3158
3159 cpu = <&CPU3>;
3160
3161 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc
3163 arm,coresight-loses-c
3164 qcom,skip-power-up;
3165
3166 out-ports {
3167 port {
3168 etm3_
3169
3170 };
3171 };
3172 };
3173 };
3174
3175 etm@7440000 {
3176 compatible = "arm,cor
3177 reg = <0 0x07440000 0
3178
3179 cpu = <&CPU4>;
3180
3181 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc
3183 arm,coresight-loses-c
3184 qcom,skip-power-up;
3185
3186 out-ports {
3187 port {
3188 etm4_
3189
3190 };
3191 };
3192 };
3193 };
3194
3195 etm@7540000 {
3196 compatible = "arm,cor
3197 reg = <0 0x07540000 0
3198
3199 cpu = <&CPU5>;
3200
3201 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc
3203 arm,coresight-loses-c
3204 qcom,skip-power-up;
3205
3206 out-ports {
3207 port {
3208 etm5_
3209
3210 };
3211 };
3212 };
3213 };
3214
3215 etm@7640000 {
3216 compatible = "arm,cor
3217 reg = <0 0x07640000 0
3218
3219 cpu = <&CPU6>;
3220
3221 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc
3223 arm,coresight-loses-c
3224 qcom,skip-power-up;
3225
3226 out-ports {
3227 port {
3228 etm6_
3229
3230 };
3231 };
3232 };
3233 };
3234
3235 etm@7740000 {
3236 compatible = "arm,cor
3237 reg = <0 0x07740000 0
3238
3239 cpu = <&CPU7>;
3240
3241 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc
3243 arm,coresight-loses-c
3244 qcom,skip-power-up;
3245
3246 out-ports {
3247 port {
3248 etm7_
3249
3250 };
3251 };
3252 };
3253 };
3254
3255 funnel@7800000 { /* APSS Funn
3256 compatible = "arm,cor
3257 reg = <0 0x07800000 0
3258
3259 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc
3261
3262 out-ports {
3263 port {
3264 apss_
3265
3266 };
3267 };
3268 };
3269
3270 in-ports {
3271 #address-cell
3272 #size-cells =
3273
3274 port@0 {
3275 reg =
3276 apss_
3277
3278 };
3279 };
3280
3281 port@1 {
3282 reg =
3283 apss_
3284
3285 };
3286 };
3287
3288 port@2 {
3289 reg =
3290 apss_
3291
3292 };
3293 };
3294
3295 port@3 {
3296 reg =
3297 apss_
3298
3299 };
3300 };
3301
3302 port@4 {
3303 reg =
3304 apss_
3305
3306 };
3307 };
3308
3309 port@5 {
3310 reg =
3311 apss_
3312
3313 };
3314 };
3315
3316 port@6 {
3317 reg =
3318 apss_
3319
3320 };
3321 };
3322
3323 port@7 {
3324 reg =
3325 apss_
3326
3327 };
3328 };
3329 };
3330 };
3331
3332 funnel@7810000 {
3333 compatible = "arm,cor
3334 reg = <0 0x07810000 0
3335
3336 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc
3338
3339 out-ports {
3340 port {
3341 apss_
3342
3343 };
3344 };
3345 };
3346
3347 in-ports {
3348 port {
3349 apss_
3350
3351 };
3352 };
3353 };
3354 };
3355
3356 remoteproc_cdsp: remoteproc@8
3357 compatible = "qcom,sm
3358 reg = <0x0 0x08300000
3359
3360 interrupts-extended =
3361
3362
3363
3364
3365 interrupt-names = "wd
3366 "ha
3367
3368 clocks = <&rpmhcc RPM
3369 clock-names = "xo";
3370
3371 power-domains = <&rpm
3372
3373 memory-region = <&cds
3374
3375 qcom,qmp = <&aoss_qmp
3376
3377 qcom,smem-states = <&
3378 qcom,smem-state-names
3379
3380 status = "disabled";
3381
3382 glink-edge {
3383 interrupts =
3384 label = "cdsp
3385 qcom,remote-p
3386 mboxes = <&ap
3387
3388 fastrpc {
3389 compa
3390 qcom,
3391 label
3392 qcom,
3393 #addr
3394 #size
3395
3396 compu
3397
3398
3399
3400 };
3401
3402 compu
3403
3404
3405
3406 };
3407
3408 compu
3409
3410
3411
3412 };
3413
3414 compu
3415
3416
3417
3418 };
3419
3420 compu
3421
3422
3423
3424 };
3425
3426 compu
3427
3428
3429
3430 };
3431
3432 compu
3433
3434
3435
3436 };
3437
3438 compu
3439
3440
3441
3442 };
3443
3444 /* no
3445 };
3446 };
3447 };
3448
3449 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm
3451 "qcom,us
3452 reg = <0 0x088e2000 0
3453 status = "disabled";
3454 #phy-cells = <0>;
3455
3456 clocks = <&rpmhcc RPM
3457 clock-names = "ref";
3458
3459 resets = <&gcc GCC_QU
3460 };
3461
3462 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm
3464 "qcom,us
3465 reg = <0 0x088e3000 0
3466 status = "disabled";
3467 #phy-cells = <0>;
3468
3469 clocks = <&rpmhcc RPM
3470 clock-names = "ref";
3471
3472 resets = <&gcc GCC_QU
3473 };
3474
3475 usb_1_qmpphy: phy@88e8000 {
3476 compatible = "qcom,sm
3477 reg = <0 0x088e8000 0
3478
3479 clocks = <&gcc GCC_US
3480 <&gcc GCC_US
3481 <&gcc GCC_US
3482 <&gcc GCC_US
3483 clock-names = "aux",
3484 "ref",
3485 "com_au
3486 "usb3_p
3487
3488 resets = <&gcc GCC_US
3489 <&gcc GCC_US
3490 reset-names = "phy",
3491
3492 #clock-cells = <1>;
3493 #phy-cells = <1>;
3494
3495 status = "disabled";
3496
3497 ports {
3498 #address-cell
3499 #size-cells =
3500
3501 port@0 {
3502 reg =
3503
3504 usb_1
3505 };
3506 };
3507
3508 port@1 {
3509 reg =
3510
3511 usb_1
3512
3513 };
3514 };
3515
3516 port@2 {
3517 reg =
3518
3519 usb_1
3520
3521 };
3522 };
3523 };
3524 };
3525
3526 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm
3528 reg = <0 0x088eb000 0
3529
3530 clocks = <&gcc GCC_US
3531 <&gcc GCC_US
3532 <&gcc GCC_US
3533 <&gcc GCC_US
3534 clock-names = "aux",
3535 "ref",
3536 "com_au
3537 "pipe";
3538 clock-output-names =
3539 #clock-cells = <0>;
3540 #phy-cells = <0>;
3541
3542 resets = <&gcc GCC_US
3543 <&gcc GCC_US
3544 reset-names = "phy",
3545 "phy_ph
3546
3547 status = "disabled";
3548 };
3549
3550 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm
3552 reg = <0 0x08804000 0
3553
3554 interrupts = <GIC_SPI
3555 <GIC_SPI
3556 interrupt-names = "hc
3557
3558 clocks = <&gcc GCC_SD
3559 <&gcc GCC_SD
3560 <&rpmhcc RPM
3561 clock-names = "iface"
3562 iommus = <&apps_smmu
3563 qcom,dll-config = <0x
3564 qcom,ddr-config = <0x
3565 power-domains = <&rpm
3566 operating-points-v2 =
3567
3568 status = "disabled";
3569
3570 sdhc2_opp_table: opp-
3571 compatible =
3572
3573 opp-19200000
3574 opp-h
3575 requi
3576 };
3577
3578 opp-50000000
3579 opp-h
3580 requi
3581 };
3582
3583 opp-100000000
3584 opp-h
3585 requi
3586 };
3587
3588 opp-202000000
3589 opp-h
3590 requi
3591 };
3592 };
3593 };
3594
3595 dc_noc: interconnect@9160000
3596 compatible = "qcom,sm
3597 reg = <0 0x09160000 0
3598 #interconnect-cells =
3599 qcom,bcm-voters = <&a
3600 };
3601
3602 gem_noc: interconnect@9680000
3603 compatible = "qcom,sm
3604 reg = <0 0x09680000 0
3605 #interconnect-cells =
3606 qcom,bcm-voters = <&a
3607 };
3608
3609 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm
3611 reg = <0 0x0a6f8800 0
3612 status = "disabled";
3613 #address-cells = <2>;
3614 #size-cells = <2>;
3615 ranges;
3616 dma-ranges;
3617
3618 clocks = <&gcc GCC_CF
3619 <&gcc GCC_US
3620 <&gcc GCC_AG
3621 <&gcc GCC_US
3622 <&gcc GCC_US
3623 <&gcc GCC_US
3624 clock-names = "cfg_no
3625 "core",
3626 "iface"
3627 "sleep"
3628 "mock_u
3629 "xo";
3630
3631 assigned-clocks = <&g
3632 <&g
3633 assigned-clock-rates
3634
3635 interrupts-extended =
3636
3637
3638
3639
3640 interrupt-names = "pw
3641 "hs
3642 "dp
3643 "dm
3644 "ss
3645
3646 power-domains = <&gcc
3647
3648 resets = <&gcc GCC_US
3649
3650 interconnects = <&agg
3651 <&gem
3652 interconnect-names =
3653
3654 usb_1_dwc3: usb@a6000
3655 compatible =
3656 reg = <0 0x0a
3657 interrupts =
3658 iommus = <&ap
3659 snps,dis_u2_s
3660 snps,dis_enbl
3661 phys = <&usb_
3662 phy-names = "
3663
3664 ports {
3665 #addr
3666 #size
3667
3668 port@
3669
3670
3671
3672
3673 };
3674
3675 port@
3676
3677
3678
3679
3680
3681 };
3682 };
3683 };
3684 };
3685
3686 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm
3688 reg = <0 0x0a8f8800 0
3689 status = "disabled";
3690 #address-cells = <2>;
3691 #size-cells = <2>;
3692 ranges;
3693 dma-ranges;
3694
3695 clocks = <&gcc GCC_CF
3696 <&gcc GCC_US
3697 <&gcc GCC_AG
3698 <&gcc GCC_US
3699 <&gcc GCC_US
3700 <&gcc GCC_US
3701 clock-names = "cfg_no
3702 "core",
3703 "iface"
3704 "sleep"
3705 "mock_u
3706 "xo";
3707
3708 assigned-clocks = <&g
3709 <&g
3710 assigned-clock-rates
3711
3712 interrupts-extended =
3713
3714
3715
3716
3717 interrupt-names = "pw
3718 "hs
3719 "dp
3720 "dm
3721 "ss
3722
3723 power-domains = <&gcc
3724
3725 resets = <&gcc GCC_US
3726
3727 interconnects = <&agg
3728 <&gem
3729 interconnect-names =
3730
3731 usb_2_dwc3: usb@a8000
3732 compatible =
3733 reg = <0 0x0a
3734 interrupts =
3735 iommus = <&ap
3736 snps,dis_u2_s
3737 snps,dis_enbl
3738 phys = <&usb_
3739 phy-names = "
3740 };
3741 };
3742
3743 videocc: clock-controller@ab0
3744 compatible = "qcom,sm
3745 reg = <0 0x0ab00000 0
3746 clocks = <&gcc GCC_VI
3747 <&rpmhcc RPM
3748 clock-names = "iface"
3749 power-domains = <&rpm
3750 required-opps = <&rpm
3751 #clock-cells = <1>;
3752 #reset-cells = <1>;
3753 #power-domain-cells =
3754 };
3755
3756 camnoc_virt: interconnect@ac0
3757 compatible = "qcom,sm
3758 reg = <0 0x0ac00000 0
3759 #interconnect-cells =
3760 qcom,bcm-voters = <&a
3761 };
3762
3763 camcc: clock-controller@ad000
3764 compatible = "qcom,sm
3765 reg = <0 0x0ad00000 0
3766 clocks = <&rpmhcc RPM
3767 <&gcc GCC_CA
3768 power-domains = <&rpm
3769 required-opps = <&rpm
3770 #clock-cells = <1>;
3771 #reset-cells = <1>;
3772 #power-domain-cells =
3773 };
3774
3775 mdss: display-subsystem@ae000
3776 compatible = "qcom,sm
3777 reg = <0 0x0ae00000 0
3778 reg-names = "mdss";
3779
3780 interconnects = <&mms
3781 <&mms
3782 interconnect-names =
3783
3784 power-domains = <&dis
3785
3786 clocks = <&dispcc DIS
3787 <&gcc GCC_DI
3788 <&gcc GCC_DI
3789 <&dispcc DIS
3790 clock-names = "iface"
3791
3792 interrupts = <GIC_SPI
3793 interrupt-controller;
3794 #interrupt-cells = <1
3795
3796 iommus = <&apps_smmu
3797
3798 status = "disabled";
3799
3800 #address-cells = <2>;
3801 #size-cells = <2>;
3802 ranges;
3803
3804 mdss_mdp: display-con
3805 compatible =
3806 reg = <0 0x0a
3807 <0 0x0a
3808 reg-names = "
3809
3810 clocks = <&di
3811 <&gc
3812 <&di
3813 <&di
3814 clock-names =
3815
3816 assigned-cloc
3817 assigned-cloc
3818
3819 operating-poi
3820 power-domains
3821
3822 interrupt-par
3823 interrupts =
3824
3825 ports {
3826 #addr
3827 #size
3828
3829 port@
3830
3831
3832
3833
3834 };
3835
3836 port@
3837
3838
3839
3840
3841 };
3842
3843 port@
3844
3845
3846
3847
3848 };
3849 };
3850
3851 mdp_opp_table
3852 compa
3853
3854 opp-1
3855
3856
3857 };
3858
3859 opp-3
3860
3861
3862 };
3863
3864 opp-3
3865
3866
3867 };
3868
3869 opp-4
3870
3871
3872 };
3873 };
3874 };
3875
3876 mdss_dp: displayport-
3877 compatible =
3878 reg = <0 0xae
3879 <0 0xae
3880 <0 0xae
3881 <0 0x0a
3882 <0 0x0a
3883
3884 interrupt-par
3885 interrupts =
3886 clocks = <&di
3887 <&di
3888 <&di
3889 <&di
3890 <&di
3891 clock-names =
3892
3893
3894
3895
3896
3897 assigned-cloc
3898
3899 assigned-cloc
3900
3901
3902 phys = <&usb_
3903 phy-names = "
3904
3905 #sound-dai-ce
3906
3907 operating-poi
3908 power-domains
3909
3910 status = "dis
3911
3912 ports {
3913 #addr
3914 #size
3915
3916 port@
3917
3918
3919
3920
3921 };
3922
3923 port@
3924
3925
3926
3927
3928
3929 };
3930 };
3931
3932 dp_opp_table:
3933 compa
3934
3935 opp-1
3936
3937
3938 };
3939
3940 opp-2
3941
3942
3943 };
3944
3945 opp-5
3946
3947
3948 };
3949
3950 opp-8
3951
3952
3953 };
3954 };
3955 };
3956
3957 mdss_dsi0: dsi@ae9400
3958 compatible =
3959 reg = <0 0x0a
3960 reg-names = "
3961
3962 interrupt-par
3963 interrupts =
3964
3965 clocks = <&di
3966 <&di
3967 <&di
3968 <&di
3969 <&di
3970 <&gc
3971 clock-names =
3972
3973
3974
3975
3976
3977
3978 assigned-cloc
3979
3980 assigned-cloc
3981
3982
3983 operating-poi
3984 power-domains
3985
3986 phys = <&mdss
3987
3988 status = "dis
3989
3990 #address-cell
3991 #size-cells =
3992
3993 ports {
3994 #addr
3995 #size
3996
3997 port@
3998
3999
4000
4001
4002 };
4003
4004 port@
4005
4006
4007
4008 };
4009 };
4010
4011 dsi_opp_table
4012 compa
4013
4014 opp-1
4015
4016
4017 };
4018
4019 opp-3
4020
4021
4022 };
4023
4024 opp-3
4025
4026
4027 };
4028 };
4029 };
4030
4031 mdss_dsi0_phy: phy@ae
4032 compatible =
4033 reg = <0 0x0a
4034 <0 0x0a
4035 <0 0x0a
4036 reg-names = "
4037 "
4038 "
4039
4040 #clock-cells
4041 #phy-cells =
4042
4043 clocks = <&di
4044 <&rp
4045 clock-names =
4046
4047 status = "dis
4048 };
4049
4050 mdss_dsi1: dsi@ae9600
4051 compatible =
4052 reg = <0 0x0a
4053 reg-names = "
4054
4055 interrupt-par
4056 interrupts =
4057
4058 clocks = <&di
4059 <&di
4060 <&di
4061 <&di
4062 <&di
4063 <&gc
4064 clock-names =
4065
4066
4067
4068
4069
4070
4071 assigned-cloc
4072
4073 assigned-cloc
4074
4075
4076 operating-poi
4077 power-domains
4078
4079 phys = <&mdss
4080
4081 status = "dis
4082
4083 #address-cell
4084 #size-cells =
4085
4086 ports {
4087 #addr
4088 #size
4089
4090 port@
4091
4092
4093
4094
4095 };
4096
4097 port@
4098
4099
4100
4101 };
4102 };
4103 };
4104
4105 mdss_dsi1_phy: phy@ae
4106 compatible =
4107 reg = <0 0x0a
4108 <0 0x0a
4109 <0 0x0a
4110 reg-names = "
4111 "
4112 "
4113
4114 #clock-cells
4115 #phy-cells =
4116
4117 clocks = <&di
4118 <&rp
4119 clock-names =
4120
4121 status = "dis
4122 };
4123 };
4124
4125 dispcc: clock-controller@af00
4126 compatible = "qcom,sm
4127 reg = <0 0x0af00000 0
4128 clocks = <&rpmhcc RPM
4129 <&mdss_dsi0_
4130 <&mdss_dsi0_
4131 <&mdss_dsi1_
4132 <&mdss_dsi1_
4133 <&usb_1_qmpp
4134 <&usb_1_qmpp
4135 clock-names = "bi_tcx
4136 "dsi0_p
4137 "dsi0_p
4138 "dsi1_p
4139 "dsi1_p
4140 "dp_phy
4141 "dp_phy
4142 power-domains = <&rpm
4143 required-opps = <&rpm
4144 #clock-cells = <1>;
4145 #reset-cells = <1>;
4146 #power-domain-cells =
4147 };
4148
4149 pdc: interrupt-controller@b22
4150 compatible = "qcom,sm
4151 reg = <0 0x0b220000 0
4152 qcom,pdc-ranges = <0
4153 <12
4154 #interrupt-cells = <2
4155 interrupt-parent = <&
4156 interrupt-controller;
4157 };
4158
4159 aoss_qmp: power-management@c3
4160 compatible = "qcom,sm
4161 reg = <0x0 0x0c300000
4162 interrupts = <GIC_SPI
4163 mboxes = <&apss_share
4164
4165 #clock-cells = <0>;
4166 };
4167
4168 sram@c3f0000 {
4169 compatible = "qcom,rp
4170 reg = <0 0x0c3f0000 0
4171 };
4172
4173 tsens0: thermal-sensor@c26300
4174 compatible = "qcom,sm
4175 reg = <0 0x0c263000 0
4176 <0 0x0c222000 0
4177 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI
4179 <GIC_SPI
4180 interrupt-names = "up
4181 #thermal-sensor-cells
4182 };
4183
4184 tsens1: thermal-sensor@c26500
4185 compatible = "qcom,sm
4186 reg = <0 0x0c265000 0
4187 <0 0x0c223000 0
4188 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI
4190 <GIC_SPI
4191 interrupt-names = "up
4192 #thermal-sensor-cells
4193 };
4194
4195 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp
4197 reg = <0x0 0x0c440000
4198 <0x0 0x0c600000
4199 <0x0 0x0e600000
4200 <0x0 0x0e700000
4201 <0x0 0x0c40a000
4202 reg-names = "core", "
4203 interrupt-names = "pe
4204 interrupts = <GIC_SPI
4205 qcom,ee = <0>;
4206 qcom,channel = <0>;
4207 #address-cells = <2>;
4208 #size-cells = <0>;
4209 interrupt-controller;
4210 #interrupt-cells = <4
4211 };
4212
4213 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm
4215 reg = <0 0x15000000 0
4216 #iommu-cells = <2>;
4217 #global-interrupts =
4218 interrupts = <GIC_SPI
4219 <GIC_SPI
4220 <GIC_SPI
4221 <GIC_SPI
4222 <GIC_SPI
4223 <GIC_SPI
4224 <GIC_SPI
4225 <GIC_SPI
4226 <GIC_SPI
4227 <GIC_SPI
4228 <GIC_SPI
4229 <GIC_SPI
4230 <GIC_SPI
4231 <GIC_SPI
4232 <GIC_SPI
4233 <GIC_SPI
4234 <GIC_SPI
4235 <GIC_SPI
4236 <GIC_SPI
4237 <GIC_SPI
4238 <GIC_SPI
4239 <GIC_SPI
4240 <GIC_SPI
4241 <GIC_SPI
4242 <GIC_SPI
4243 <GIC_SPI
4244 <GIC_SPI
4245 <GIC_SPI
4246 <GIC_SPI
4247 <GIC_SPI
4248 <GIC_SPI
4249 <GIC_SPI
4250 <GIC_SPI
4251 <GIC_SPI
4252 <GIC_SPI
4253 <GIC_SPI
4254 <GIC_SPI
4255 <GIC_SPI
4256 <GIC_SPI
4257 <GIC_SPI
4258 <GIC_SPI
4259 <GIC_SPI
4260 <GIC_SPI
4261 <GIC_SPI
4262 <GIC_SPI
4263 <GIC_SPI
4264 <GIC_SPI
4265 <GIC_SPI
4266 <GIC_SPI
4267 <GIC_SPI
4268 <GIC_SPI
4269 <GIC_SPI
4270 <GIC_SPI
4271 <GIC_SPI
4272 <GIC_SPI
4273 <GIC_SPI
4274 <GIC_SPI
4275 <GIC_SPI
4276 <GIC_SPI
4277 <GIC_SPI
4278 <GIC_SPI
4279 <GIC_SPI
4280 <GIC_SPI
4281 <GIC_SPI
4282 <GIC_SPI
4283 <GIC_SPI
4284 <GIC_SPI
4285 <GIC_SPI
4286 <GIC_SPI
4287 <GIC_SPI
4288 <GIC_SPI
4289 <GIC_SPI
4290 <GIC_SPI
4291 <GIC_SPI
4292 <GIC_SPI
4293 <GIC_SPI
4294 <GIC_SPI
4295 <GIC_SPI
4296 <GIC_SPI
4297 <GIC_SPI
4298 <GIC_SPI
4299 };
4300
4301 remoteproc_adsp: remoteproc@1
4302 compatible = "qcom,sm
4303 reg = <0x0 0x17300000
4304
4305 interrupts-extended =
4306
4307
4308
4309
4310 interrupt-names = "wd
4311 "ha
4312
4313 clocks = <&rpmhcc RPM
4314 clock-names = "xo";
4315
4316 power-domains = <&rpm
4317
4318 memory-region = <&ads
4319
4320 qcom,qmp = <&aoss_qmp
4321
4322 qcom,smem-states = <&
4323 qcom,smem-state-names
4324
4325 status = "disabled";
4326
4327 glink-edge {
4328 interrupts =
4329 label = "lpas
4330 qcom,remote-p
4331 mboxes = <&ap
4332
4333 fastrpc {
4334 compa
4335 qcom,
4336 label
4337 qcom,
4338 #addr
4339 #size
4340
4341 compu
4342
4343
4344
4345 };
4346
4347 compu
4348
4349
4350
4351 };
4352
4353 compu
4354
4355
4356
4357 };
4358 };
4359 };
4360 };
4361
4362 intc: interrupt-controller@17
4363 compatible = "arm,gic
4364 interrupt-controller;
4365 #interrupt-cells = <3
4366 reg = <0x0 0x17a00000
4367 <0x0 0x17a60000
4368 interrupts = <GIC_PPI
4369 };
4370
4371 apss_shared: mailbox@17c00000
4372 compatible = "qcom,sm
4373 "qcom,sd
4374 reg = <0x0 0x17c00000
4375 #mbox-cells = <1>;
4376 };
4377
4378 watchdog@17c10000 {
4379 compatible = "qcom,ap
4380 reg = <0 0x17c10000 0
4381 clocks = <&sleep_clk>
4382 interrupts = <GIC_SPI
4383 };
4384
4385 timer@17c20000 {
4386 #address-cells = <1>;
4387 #size-cells = <1>;
4388 ranges = <0 0 0 0x200
4389 compatible = "arm,arm
4390 reg = <0x0 0x17c20000
4391 clock-frequency = <19
4392
4393 frame@17c21000 {
4394 frame-number
4395 interrupts =
4396
4397 reg = <0x17c2
4398 <0x17c2
4399 };
4400
4401 frame@17c23000 {
4402 frame-number
4403 interrupts =
4404 reg = <0x17c2
4405 status = "dis
4406 };
4407
4408 frame@17c25000 {
4409 frame-number
4410 interrupts =
4411 reg = <0x17c2
4412 status = "dis
4413 };
4414
4415 frame@17c27000 {
4416 frame-number
4417 interrupts =
4418 reg = <0x17c2
4419 status = "dis
4420 };
4421
4422 frame@17c29000 {
4423 frame-number
4424 interrupts =
4425 reg = <0x17c2
4426 status = "dis
4427 };
4428
4429 frame@17c2b000 {
4430 frame-number
4431 interrupts =
4432 reg = <0x17c2
4433 status = "dis
4434 };
4435
4436 frame@17c2d000 {
4437 frame-number
4438 interrupts =
4439 reg = <0x17c2
4440 status = "dis
4441 };
4442 };
4443
4444 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc";
4446 compatible = "qcom,rp
4447 reg = <0x0 0x18200000
4448 <0x0 0x18210000
4449 <0x0 0x18220000
4450 reg-names = "drv-0",
4451 interrupts = <GIC_SPI
4452 <GIC_SPI
4453 <GIC_SPI
4454 qcom,tcs-offset = <0x
4455 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC
4457 <SL
4458 <WA
4459 <CO
4460 power-domains = <&CLU
4461
4462 rpmhcc: clock-control
4463 compatible =
4464 #clock-cells
4465 clock-names =
4466 clocks = <&xo
4467 };
4468
4469 rpmhpd: power-control
4470 compatible =
4471 #power-domain
4472 operating-poi
4473
4474 rpmhpd_opp_ta
4475 compa
4476
4477 rpmhp
4478
4479 };
4480
4481 rpmhp
4482
4483 };
4484
4485 rpmhp
4486
4487 };
4488
4489 rpmhp
4490
4491 };
4492
4493 rpmhp
4494
4495 };
4496
4497 rpmhp
4498
4499 };
4500
4501 rpmhp
4502
4503 };
4504
4505 rpmhp
4506
4507 };
4508
4509 rpmhp
4510
4511 };
4512
4513 rpmhp
4514
4515 };
4516
4517 rpmhp
4518
4519 };
4520 };
4521 };
4522
4523 apps_bcm_voter: bcm-v
4524 compatible =
4525 };
4526 };
4527
4528 osm_l3: interconnect@18321000
4529 compatible = "qcom,sm
4530 reg = <0 0x18321000 0
4531
4532 clocks = <&rpmhcc RPM
4533 clock-names = "xo", "
4534
4535 #interconnect-cells =
4536 };
4537
4538 cpufreq_hw: cpufreq@18323000
4539 compatible = "qcom,sm
4540 reg = <0 0x18323000 0
4541 <0 0x18327800 0
4542 reg-names = "freq-dom
4543 "freq-dom
4544
4545 clocks = <&rpmhcc RPM
4546 clock-names = "xo", "
4547
4548 #freq-domain-cells =
4549 #clock-cells = <1>;
4550 };
4551
4552 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm
4554 reg = <0 0x18350800 0
4555 interrupts = <GIC_SPI
4556 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil
4558 qcom,lmh-temp-low-mil
4559 qcom,lmh-temp-high-mi
4560 interrupt-controller;
4561 #interrupt-cells = <1
4562 };
4563
4564 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm
4566 reg = <0 0x18358800 0
4567 interrupts = <GIC_SPI
4568 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil
4570 qcom,lmh-temp-low-mil
4571 qcom,lmh-temp-high-mi
4572 interrupt-controller;
4573 #interrupt-cells = <1
4574 };
4575
4576 wifi: wifi@18800000 {
4577 compatible = "qcom,wc
4578 reg = <0 0x18800000 0
4579 reg-names = "membase"
4580 memory-region = <&wla
4581 clock-names = "cxo_re
4582 clocks = <&rpmhcc RPM
4583 interrupts = <GIC_SPI
4584 <GIC_SPI
4585 <GIC_SPI
4586 <GIC_SPI
4587 <GIC_SPI
4588 <GIC_SPI
4589 <GIC_SPI
4590 <GIC_SPI
4591 <GIC_SPI
4592 <GIC_SPI
4593 <GIC_SPI
4594 <GIC_SPI
4595 iommus = <&apps_smmu
4596 status = "disabled";
4597 };
4598 };
4599
4600 timer {
4601 compatible = "arm,armv8-timer
4602 interrupts = <GIC_PPI 1 IRQ_T
4603 <GIC_PPI 2 IRQ_T
4604 <GIC_PPI 3 IRQ_T
4605 <GIC_PPI 0 IRQ_T
4606 };
4607
4608 thermal-zones {
4609 cpu0-thermal {
4610 polling-delay-passive
4611
4612 thermal-sensors = <&t
4613
4614 trips {
4615 cpu0_alert0:
4616 tempe
4617 hyste
4618 type
4619 };
4620
4621 cpu0_alert1:
4622 tempe
4623 hyste
4624 type
4625 };
4626
4627 cpu0_crit: cp
4628 tempe
4629 hyste
4630 type
4631 };
4632 };
4633
4634 cooling-maps {
4635 map0 {
4636 trip
4637 cooli
4638
4639
4640
4641 };
4642 map1 {
4643 trip
4644 cooli
4645
4646
4647
4648 };
4649 };
4650 };
4651
4652 cpu1-thermal {
4653 polling-delay-passive
4654
4655 thermal-sensors = <&t
4656
4657 trips {
4658 cpu1_alert0:
4659 tempe
4660 hyste
4661 type
4662 };
4663
4664 cpu1_alert1:
4665 tempe
4666 hyste
4667 type
4668 };
4669
4670 cpu1_crit: cp
4671 tempe
4672 hyste
4673 type
4674 };
4675 };
4676
4677 cooling-maps {
4678 map0 {
4679 trip
4680 cooli
4681
4682
4683
4684 };
4685 map1 {
4686 trip
4687 cooli
4688
4689
4690
4691 };
4692 };
4693 };
4694
4695 cpu2-thermal {
4696 polling-delay-passive
4697
4698 thermal-sensors = <&t
4699
4700 trips {
4701 cpu2_alert0:
4702 tempe
4703 hyste
4704 type
4705 };
4706
4707 cpu2_alert1:
4708 tempe
4709 hyste
4710 type
4711 };
4712
4713 cpu2_crit: cp
4714 tempe
4715 hyste
4716 type
4717 };
4718 };
4719
4720 cooling-maps {
4721 map0 {
4722 trip
4723 cooli
4724
4725
4726
4727 };
4728 map1 {
4729 trip
4730 cooli
4731
4732
4733
4734 };
4735 };
4736 };
4737
4738 cpu3-thermal {
4739 polling-delay-passive
4740
4741 thermal-sensors = <&t
4742
4743 trips {
4744 cpu3_alert0:
4745 tempe
4746 hyste
4747 type
4748 };
4749
4750 cpu3_alert1:
4751 tempe
4752 hyste
4753 type
4754 };
4755
4756 cpu3_crit: cp
4757 tempe
4758 hyste
4759 type
4760 };
4761 };
4762
4763 cooling-maps {
4764 map0 {
4765 trip
4766 cooli
4767
4768
4769
4770 };
4771 map1 {
4772 trip
4773 cooli
4774
4775
4776
4777 };
4778 };
4779 };
4780
4781 cpu4-top-thermal {
4782 polling-delay-passive
4783
4784 thermal-sensors = <&t
4785
4786 trips {
4787 cpu4_top_aler
4788 tempe
4789 hyste
4790 type
4791 };
4792
4793 cpu4_top_aler
4794 tempe
4795 hyste
4796 type
4797 };
4798
4799 cpu4_top_crit
4800 tempe
4801 hyste
4802 type
4803 };
4804 };
4805
4806 cooling-maps {
4807 map0 {
4808 trip
4809 cooli
4810
4811
4812
4813 };
4814 map1 {
4815 trip
4816 cooli
4817
4818
4819
4820 };
4821 };
4822 };
4823
4824 cpu5-top-thermal {
4825 polling-delay-passive
4826
4827 thermal-sensors = <&t
4828
4829 trips {
4830 cpu5_top_aler
4831 tempe
4832 hyste
4833 type
4834 };
4835
4836 cpu5_top_aler
4837 tempe
4838 hyste
4839 type
4840 };
4841
4842 cpu5_top_crit
4843 tempe
4844 hyste
4845 type
4846 };
4847 };
4848
4849 cooling-maps {
4850 map0 {
4851 trip
4852 cooli
4853
4854
4855
4856 };
4857 map1 {
4858 trip
4859 cooli
4860
4861
4862
4863 };
4864 };
4865 };
4866
4867 cpu6-top-thermal {
4868 polling-delay-passive
4869
4870 thermal-sensors = <&t
4871
4872 trips {
4873 cpu6_top_aler
4874 tempe
4875 hyste
4876 type
4877 };
4878
4879 cpu6_top_aler
4880 tempe
4881 hyste
4882 type
4883 };
4884
4885 cpu6_top_crit
4886 tempe
4887 hyste
4888 type
4889 };
4890 };
4891
4892 cooling-maps {
4893 map0 {
4894 trip
4895 cooli
4896
4897
4898
4899 };
4900 map1 {
4901 trip
4902 cooli
4903
4904
4905
4906 };
4907 };
4908 };
4909
4910 cpu7-top-thermal {
4911 polling-delay-passive
4912
4913 thermal-sensors = <&t
4914
4915 trips {
4916 cpu7_top_aler
4917 tempe
4918 hyste
4919 type
4920 };
4921
4922 cpu7_top_aler
4923 tempe
4924 hyste
4925 type
4926 };
4927
4928 cpu7_top_crit
4929 tempe
4930 hyste
4931 type
4932 };
4933 };
4934
4935 cooling-maps {
4936 map0 {
4937 trip
4938 cooli
4939
4940
4941
4942 };
4943 map1 {
4944 trip
4945 cooli
4946
4947
4948
4949 };
4950 };
4951 };
4952
4953 cpu4-bottom-thermal {
4954 polling-delay-passive
4955
4956 thermal-sensors = <&t
4957
4958 trips {
4959 cpu4_bottom_a
4960 tempe
4961 hyste
4962 type
4963 };
4964
4965 cpu4_bottom_a
4966 tempe
4967 hyste
4968 type
4969 };
4970
4971 cpu4_bottom_c
4972 tempe
4973 hyste
4974 type
4975 };
4976 };
4977
4978 cooling-maps {
4979 map0 {
4980 trip
4981 cooli
4982
4983
4984
4985 };
4986 map1 {
4987 trip
4988 cooli
4989
4990
4991
4992 };
4993 };
4994 };
4995
4996 cpu5-bottom-thermal {
4997 polling-delay-passive
4998
4999 thermal-sensors = <&t
5000
5001 trips {
5002 cpu5_bottom_a
5003 tempe
5004 hyste
5005 type
5006 };
5007
5008 cpu5_bottom_a
5009 tempe
5010 hyste
5011 type
5012 };
5013
5014 cpu5_bottom_c
5015 tempe
5016 hyste
5017 type
5018 };
5019 };
5020
5021 cooling-maps {
5022 map0 {
5023 trip
5024 cooli
5025
5026
5027
5028 };
5029 map1 {
5030 trip
5031 cooli
5032
5033
5034
5035 };
5036 };
5037 };
5038
5039 cpu6-bottom-thermal {
5040 polling-delay-passive
5041
5042 thermal-sensors = <&t
5043
5044 trips {
5045 cpu6_bottom_a
5046 tempe
5047 hyste
5048 type
5049 };
5050
5051 cpu6_bottom_a
5052 tempe
5053 hyste
5054 type
5055 };
5056
5057 cpu6_bottom_c
5058 tempe
5059 hyste
5060 type
5061 };
5062 };
5063
5064 cooling-maps {
5065 map0 {
5066 trip
5067 cooli
5068
5069
5070
5071 };
5072 map1 {
5073 trip
5074 cooli
5075
5076
5077
5078 };
5079 };
5080 };
5081
5082 cpu7-bottom-thermal {
5083 polling-delay-passive
5084
5085 thermal-sensors = <&t
5086
5087 trips {
5088 cpu7_bottom_a
5089 tempe
5090 hyste
5091 type
5092 };
5093
5094 cpu7_bottom_a
5095 tempe
5096 hyste
5097 type
5098 };
5099
5100 cpu7_bottom_c
5101 tempe
5102 hyste
5103 type
5104 };
5105 };
5106
5107 cooling-maps {
5108 map0 {
5109 trip
5110 cooli
5111
5112
5113
5114 };
5115 map1 {
5116 trip
5117 cooli
5118
5119
5120
5121 };
5122 };
5123 };
5124
5125 aoss0-thermal {
5126 polling-delay-passive
5127
5128 thermal-sensors = <&t
5129
5130 trips {
5131 aoss0_alert0:
5132 tempe
5133 hyste
5134 type
5135 };
5136 };
5137 };
5138
5139 cluster0-thermal {
5140 polling-delay-passive
5141
5142 thermal-sensors = <&t
5143
5144 trips {
5145 cluster0_aler
5146 tempe
5147 hyste
5148 type
5149 };
5150 cluster0_crit
5151 tempe
5152 hyste
5153 type
5154 };
5155 };
5156 };
5157
5158 cluster1-thermal {
5159 polling-delay-passive
5160
5161 thermal-sensors = <&t
5162
5163 trips {
5164 cluster1_aler
5165 tempe
5166 hyste
5167 type
5168 };
5169 cluster1_crit
5170 tempe
5171 hyste
5172 type
5173 };
5174 };
5175 };
5176
5177 gpu-top-thermal {
5178 polling-delay-passive
5179
5180 thermal-sensors = <&t
5181
5182 cooling-maps {
5183 map0 {
5184 trip
5185 cooli
5186 };
5187 };
5188
5189 trips {
5190 gpu_top_alert
5191 tempe
5192 hyste
5193 type
5194 };
5195
5196 trip-point1 {
5197 tempe
5198 hyste
5199 type
5200 };
5201
5202 trip-point2 {
5203 tempe
5204 hyste
5205 type
5206 };
5207 };
5208 };
5209
5210 aoss1-thermal {
5211 polling-delay-passive
5212
5213 thermal-sensors = <&t
5214
5215 trips {
5216 aoss1_alert0:
5217 tempe
5218 hyste
5219 type
5220 };
5221 };
5222 };
5223
5224 wlan-thermal {
5225 polling-delay-passive
5226
5227 thermal-sensors = <&t
5228
5229 trips {
5230 wlan_alert0:
5231 tempe
5232 hyste
5233 type
5234 };
5235 };
5236 };
5237
5238 video-thermal {
5239 polling-delay-passive
5240
5241 thermal-sensors = <&t
5242
5243 trips {
5244 video_alert0:
5245 tempe
5246 hyste
5247 type
5248 };
5249 };
5250 };
5251
5252 mem-thermal {
5253 polling-delay-passive
5254
5255 thermal-sensors = <&t
5256
5257 trips {
5258 mem_alert0: t
5259 tempe
5260 hyste
5261 type
5262 };
5263 };
5264 };
5265
5266 q6-hvx-thermal {
5267 polling-delay-passive
5268
5269 thermal-sensors = <&t
5270
5271 trips {
5272 q6_hvx_alert0
5273 tempe
5274 hyste
5275 type
5276 };
5277 };
5278 };
5279
5280 camera-thermal {
5281 polling-delay-passive
5282
5283 thermal-sensors = <&t
5284
5285 trips {
5286 camera_alert0
5287 tempe
5288 hyste
5289 type
5290 };
5291 };
5292 };
5293
5294 compute-thermal {
5295 polling-delay-passive
5296
5297 thermal-sensors = <&t
5298
5299 trips {
5300 compute_alert
5301 tempe
5302 hyste
5303 type
5304 };
5305 };
5306 };
5307
5308 modem-thermal {
5309 polling-delay-passive
5310
5311 thermal-sensors = <&t
5312
5313 trips {
5314 modem_alert0:
5315 tempe
5316 hyste
5317 type
5318 };
5319 };
5320 };
5321
5322 npu-thermal {
5323 polling-delay-passive
5324
5325 thermal-sensors = <&t
5326
5327 trips {
5328 npu_alert0: t
5329 tempe
5330 hyste
5331 type
5332 };
5333 };
5334 };
5335
5336 modem-vec-thermal {
5337 polling-delay-passive
5338
5339 thermal-sensors = <&t
5340
5341 trips {
5342 modem_vec_ale
5343 tempe
5344 hyste
5345 type
5346 };
5347 };
5348 };
5349
5350 modem-scl-thermal {
5351 polling-delay-passive
5352
5353 thermal-sensors = <&t
5354
5355 trips {
5356 modem_scl_ale
5357 tempe
5358 hyste
5359 type
5360 };
5361 };
5362 };
5363
5364 gpu-bottom-thermal {
5365 polling-delay-passive
5366
5367 thermal-sensors = <&t
5368
5369 cooling-maps {
5370 map0 {
5371 trip
5372 cooli
5373 };
5374 };
5375
5376 trips {
5377 gpu_bottom_al
5378 tempe
5379 hyste
5380 type
5381 };
5382
5383 trip-point1 {
5384 tempe
5385 hyste
5386 type
5387 };
5388
5389 trip-point2 {
5390 tempe
5391 hyste
5392 type
5393 };
5394 };
5395 };
5396 };
5397 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.