1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> <<
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 8 #include <dt-bindings/power/qcom-aoss-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 <<
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
22 16
23 / { 17 / {
24 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
25 19
26 #address-cells = <2>; 20 #address-cells = <2>;
27 #size-cells = <2>; 21 #size-cells = <2>;
28 22
29 chosen { }; 23 chosen { };
30 24
31 clocks { 25 clocks {
32 xo_board: xo-board { 26 xo_board: xo-board {
33 compatible = "fixed-cl 27 compatible = "fixed-clock";
34 #clock-cells = <0>; 28 #clock-cells = <0>;
35 clock-frequency = <384 29 clock-frequency = <38400000>;
36 clock-output-names = " 30 clock-output-names = "xo_board";
37 }; 31 };
38 32
39 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 34 compatible = "fixed-clock";
41 #clock-cells = <0>; 35 #clock-cells = <0>;
42 clock-frequency = <327 36 clock-frequency = <32764>;
43 clock-output-names = " 37 clock-output-names = "sleep_clk";
44 }; 38 };
45 }; 39 };
46 40
47 cpus { 41 cpus {
48 #address-cells = <2>; 42 #address-cells = <2>;
49 #size-cells = <0>; 43 #size-cells = <0>;
50 44
51 CPU0: cpu@0 { 45 CPU0: cpu@0 {
52 device_type = "cpu"; 46 device_type = "cpu";
53 compatible = "qcom,kry 47 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 48 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 49 enable-method = "psci";
57 capacity-dmips-mhz = < <<
58 dynamic-power-coeffici <<
59 next-level-cache = <&L 50 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 51 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <<
62 interconnects = <&gem_ <<
63 <&osm_ <<
64 power-domains = <&CPU_ <<
65 power-domain-names = " <<
66 #cooling-cells = <2>; 52 #cooling-cells = <2>;
67 L2_0: l2-cache { 53 L2_0: l2-cache {
68 compatible = " 54 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 55 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 56 L3_0: l3-cache {
73 compat !! 57 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 58 };
77 }; 59 };
78 }; 60 };
79 61
80 CPU1: cpu@100 { 62 CPU1: cpu@100 {
81 device_type = "cpu"; 63 device_type = "cpu";
82 compatible = "qcom,kry 64 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 65 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 66 enable-method = "psci";
86 capacity-dmips-mhz = < <<
87 dynamic-power-coeffici <<
88 next-level-cache = <&L 67 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 68 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <<
91 interconnects = <&gem_ <<
92 <&osm_ <<
93 power-domains = <&CPU_ <<
94 power-domain-names = " <<
95 #cooling-cells = <2>; 69 #cooling-cells = <2>;
96 L2_100: l2-cache { 70 L2_100: l2-cache {
97 compatible = " 71 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 72 next-level-cache = <&L3_0>;
101 }; 73 };
>> 74
102 }; 75 };
103 76
104 CPU2: cpu@200 { 77 CPU2: cpu@200 {
105 device_type = "cpu"; 78 device_type = "cpu";
106 compatible = "qcom,kry 79 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 80 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 81 enable-method = "psci";
110 capacity-dmips-mhz = < <<
111 dynamic-power-coeffici <<
112 next-level-cache = <&L 82 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 83 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <<
115 interconnects = <&gem_ <<
116 <&osm_ <<
117 power-domains = <&CPU_ <<
118 power-domain-names = " <<
119 #cooling-cells = <2>; 84 #cooling-cells = <2>;
120 L2_200: l2-cache { 85 L2_200: l2-cache {
121 compatible = " 86 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 87 next-level-cache = <&L3_0>;
125 }; 88 };
126 }; 89 };
127 90
128 CPU3: cpu@300 { 91 CPU3: cpu@300 {
129 device_type = "cpu"; 92 device_type = "cpu";
130 compatible = "qcom,kry 93 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 94 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 95 enable-method = "psci";
134 capacity-dmips-mhz = < <<
135 dynamic-power-coeffici <<
136 next-level-cache = <&L 96 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 97 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <<
139 interconnects = <&gem_ <<
140 <&osm_ <<
141 power-domains = <&CPU_ <<
142 power-domain-names = " <<
143 #cooling-cells = <2>; 98 #cooling-cells = <2>;
144 L2_300: l2-cache { 99 L2_300: l2-cache {
145 compatible = " 100 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 101 next-level-cache = <&L3_0>;
149 }; 102 };
150 }; 103 };
151 104
152 CPU4: cpu@400 { 105 CPU4: cpu@400 {
153 device_type = "cpu"; 106 device_type = "cpu";
154 compatible = "qcom,kry 107 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 108 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 109 enable-method = "psci";
158 capacity-dmips-mhz = < <<
159 dynamic-power-coeffici <<
160 next-level-cache = <&L 110 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 111 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = <<
163 interconnects = <&gem_ <<
164 <&osm_ <<
165 power-domains = <&CPU_ <<
166 power-domain-names = " <<
167 #cooling-cells = <2>; 112 #cooling-cells = <2>;
168 L2_400: l2-cache { 113 L2_400: l2-cache {
169 compatible = " 114 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 115 next-level-cache = <&L3_0>;
173 }; 116 };
174 }; 117 };
175 118
176 CPU5: cpu@500 { 119 CPU5: cpu@500 {
177 device_type = "cpu"; 120 device_type = "cpu";
178 compatible = "qcom,kry 121 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 122 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 123 enable-method = "psci";
182 capacity-dmips-mhz = < <<
183 dynamic-power-coeffici <<
184 next-level-cache = <&L 124 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 125 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <<
187 interconnects = <&gem_ <<
188 <&osm_ <<
189 power-domains = <&CPU_ <<
190 power-domain-names = " <<
191 #cooling-cells = <2>; 126 #cooling-cells = <2>;
192 L2_500: l2-cache { 127 L2_500: l2-cache {
193 compatible = " 128 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 129 next-level-cache = <&L3_0>;
197 }; 130 };
198 }; 131 };
199 132
200 CPU6: cpu@600 { 133 CPU6: cpu@600 {
201 device_type = "cpu"; 134 device_type = "cpu";
202 compatible = "qcom,kry 135 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 136 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 137 enable-method = "psci";
206 capacity-dmips-mhz = < <<
207 dynamic-power-coeffici <<
208 next-level-cache = <&L 138 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 139 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = <<
211 interconnects = <&gem_ <<
212 <&osm_ <<
213 power-domains = <&CPU_ <<
214 power-domain-names = " <<
215 #cooling-cells = <2>; 140 #cooling-cells = <2>;
216 L2_600: l2-cache { 141 L2_600: l2-cache {
217 compatible = " 142 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 143 next-level-cache = <&L3_0>;
221 }; 144 };
222 }; 145 };
223 146
224 CPU7: cpu@700 { 147 CPU7: cpu@700 {
225 device_type = "cpu"; 148 device_type = "cpu";
226 compatible = "qcom,kry 149 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 150 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 151 enable-method = "psci";
230 capacity-dmips-mhz = < <<
231 dynamic-power-coeffici <<
232 next-level-cache = <&L 152 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 153 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = <<
235 interconnects = <&gem_ <<
236 <&osm_ <<
237 power-domains = <&CPU_ <<
238 power-domain-names = " <<
239 #cooling-cells = <2>; 154 #cooling-cells = <2>;
240 L2_700: l2-cache { 155 L2_700: l2-cache {
241 compatible = " 156 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 157 next-level-cache = <&L3_0>;
245 }; 158 };
246 }; 159 };
247 <<
248 cpu-map { <<
249 cluster0 { <<
250 core0 { <<
251 cpu = <<
252 }; <<
253 <<
254 core1 { <<
255 cpu = <<
256 }; <<
257 <<
258 core2 { <<
259 cpu = <<
260 }; <<
261 <<
262 core3 { <<
263 cpu = <<
264 }; <<
265 <<
266 core4 { <<
267 cpu = <<
268 }; <<
269 <<
270 core5 { <<
271 cpu = <<
272 }; <<
273 <<
274 core6 { <<
275 cpu = <<
276 }; <<
277 <<
278 core7 { <<
279 cpu = <<
280 }; <<
281 }; <<
282 }; <<
283 <<
284 idle-states { <<
285 entry-method = "psci"; <<
286 <<
287 LITTLE_CPU_SLEEP_0: cp <<
288 compatible = " <<
289 idle-state-nam <<
290 arm,psci-suspe <<
291 entry-latency- <<
292 exit-latency-u <<
293 min-residency- <<
294 local-timer-st <<
295 }; <<
296 <<
297 BIG_CPU_SLEEP_0: cpu-s <<
298 compatible = " <<
299 idle-state-nam <<
300 arm,psci-suspe <<
301 entry-latency- <<
302 exit-latency-u <<
303 min-residency- <<
304 local-timer-st <<
305 }; <<
306 }; <<
307 <<
308 domain-idle-states { <<
309 CLUSTER_SLEEP_0: clust <<
310 compatible = " <<
311 arm,psci-suspe <<
312 entry-latency- <<
313 exit-latency-u <<
314 min-residency- <<
315 }; <<
316 }; <<
317 }; <<
318 <<
319 cpu0_opp_table: opp-table-cpu0 { <<
320 compatible = "operating-points <<
321 opp-shared; <<
322 <<
323 cpu0_opp1: opp-300000000 { <<
324 opp-hz = /bits/ 64 <30 <<
325 opp-peak-kBps = <80000 <<
326 }; <<
327 <<
328 cpu0_opp2: opp-403200000 { <<
329 opp-hz = /bits/ 64 <40 <<
330 opp-peak-kBps = <80000 <<
331 }; <<
332 <<
333 cpu0_opp3: opp-499200000 { <<
334 opp-hz = /bits/ 64 <49 <<
335 opp-peak-kBps = <80000 <<
336 }; <<
337 <<
338 cpu0_opp4: opp-576000000 { <<
339 opp-hz = /bits/ 64 <57 <<
340 opp-peak-kBps = <80000 <<
341 }; <<
342 <<
343 cpu0_opp5: opp-672000000 { <<
344 opp-hz = /bits/ 64 <67 <<
345 opp-peak-kBps = <80000 <<
346 }; <<
347 <<
348 cpu0_opp6: opp-768000000 { <<
349 opp-hz = /bits/ 64 <76 <<
350 opp-peak-kBps = <18040 <<
351 }; <<
352 <<
353 cpu0_opp7: opp-844800000 { <<
354 opp-hz = /bits/ 64 <84 <<
355 opp-peak-kBps = <18040 <<
356 }; <<
357 <<
358 cpu0_opp8: opp-940800000 { <<
359 opp-hz = /bits/ 64 <94 <<
360 opp-peak-kBps = <18040 <<
361 }; <<
362 <<
363 cpu0_opp9: opp-1036800000 { <<
364 opp-hz = /bits/ 64 <10 <<
365 opp-peak-kBps = <18040 <<
366 }; <<
367 <<
368 cpu0_opp10: opp-1113600000 { <<
369 opp-hz = /bits/ 64 <11 <<
370 opp-peak-kBps = <21880 <<
371 }; <<
372 <<
373 cpu0_opp11: opp-1209600000 { <<
374 opp-hz = /bits/ 64 <12 <<
375 opp-peak-kBps = <21880 <<
376 }; <<
377 <<
378 cpu0_opp12: opp-1305600000 { <<
379 opp-hz = /bits/ 64 <13 <<
380 opp-peak-kBps = <30720 <<
381 }; <<
382 <<
383 cpu0_opp13: opp-1382400000 { <<
384 opp-hz = /bits/ 64 <13 <<
385 opp-peak-kBps = <30720 <<
386 }; <<
387 <<
388 cpu0_opp14: opp-1478400000 { <<
389 opp-hz = /bits/ 64 <14 <<
390 opp-peak-kBps = <30720 <<
391 }; <<
392 <<
393 cpu0_opp15: opp-1555200000 { <<
394 opp-hz = /bits/ 64 <15 <<
395 opp-peak-kBps = <30720 <<
396 }; <<
397 <<
398 cpu0_opp16: opp-1632000000 { <<
399 opp-hz = /bits/ 64 <16 <<
400 opp-peak-kBps = <30720 <<
401 }; <<
402 <<
403 cpu0_opp17: opp-1708800000 { <<
404 opp-hz = /bits/ 64 <17 <<
405 opp-peak-kBps = <30720 <<
406 }; <<
407 <<
408 cpu0_opp18: opp-1785600000 { <<
409 opp-hz = /bits/ 64 <17 <<
410 opp-peak-kBps = <30720 <<
411 }; <<
412 }; <<
413 <<
414 cpu4_opp_table: opp-table-cpu4 { <<
415 compatible = "operating-points <<
416 opp-shared; <<
417 <<
418 cpu4_opp1: opp-710400000 { <<
419 opp-hz = /bits/ 64 <71 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu4_opp2: opp-825600000 { <<
424 opp-hz = /bits/ 64 <82 <<
425 opp-peak-kBps = <21880 <<
426 }; <<
427 <<
428 cpu4_opp3: opp-940800000 { <<
429 opp-hz = /bits/ 64 <94 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu4_opp4: opp-1056000000 { <<
434 opp-hz = /bits/ 64 <10 <<
435 opp-peak-kBps = <30720 <<
436 }; <<
437 <<
438 cpu4_opp5: opp-1171200000 { <<
439 opp-hz = /bits/ 64 <11 <<
440 opp-peak-kBps = <30720 <<
441 }; <<
442 <<
443 cpu4_opp6: opp-1286400000 { <<
444 opp-hz = /bits/ 64 <12 <<
445 opp-peak-kBps = <40680 <<
446 }; <<
447 <<
448 cpu4_opp7: opp-1401600000 { <<
449 opp-hz = /bits/ 64 <14 <<
450 opp-peak-kBps = <40680 <<
451 }; <<
452 <<
453 cpu4_opp8: opp-1497600000 { <<
454 opp-hz = /bits/ 64 <14 <<
455 opp-peak-kBps = <40680 <<
456 }; <<
457 <<
458 cpu4_opp9: opp-1612800000 { <<
459 opp-hz = /bits/ 64 <16 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu4_opp10: opp-1708800000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 <<
468 cpu4_opp11: opp-1804800000 { <<
469 opp-hz = /bits/ 64 <18 <<
470 opp-peak-kBps = <62200 <<
471 }; <<
472 <<
473 cpu4_opp12: opp-1920000000 { <<
474 opp-hz = /bits/ 64 <19 <<
475 opp-peak-kBps = <62200 <<
476 }; <<
477 <<
478 cpu4_opp13: opp-2016000000 { <<
479 opp-hz = /bits/ 64 <20 <<
480 opp-peak-kBps = <72160 <<
481 }; <<
482 <<
483 cpu4_opp14: opp-2131200000 { <<
484 opp-hz = /bits/ 64 <21 <<
485 opp-peak-kBps = <83680 <<
486 }; <<
487 <<
488 cpu4_opp15: opp-2227200000 { <<
489 opp-hz = /bits/ 64 <22 <<
490 opp-peak-kBps = <83680 <<
491 }; <<
492 <<
493 cpu4_opp16: opp-2323200000 { <<
494 opp-hz = /bits/ 64 <23 <<
495 opp-peak-kBps = <83680 <<
496 }; <<
497 <<
498 cpu4_opp17: opp-2419200000 { <<
499 opp-hz = /bits/ 64 <24 <<
500 opp-peak-kBps = <83680 <<
501 }; <<
502 }; <<
503 <<
504 cpu7_opp_table: opp-table-cpu7 { <<
505 compatible = "operating-points <<
506 opp-shared; <<
507 <<
508 cpu7_opp1: opp-825600000 { <<
509 opp-hz = /bits/ 64 <82 <<
510 opp-peak-kBps = <21880 <<
511 }; <<
512 <<
513 cpu7_opp2: opp-940800000 { <<
514 opp-hz = /bits/ 64 <94 <<
515 opp-peak-kBps = <21880 <<
516 }; <<
517 <<
518 cpu7_opp3: opp-1056000000 { <<
519 opp-hz = /bits/ 64 <10 <<
520 opp-peak-kBps = <30720 <<
521 }; <<
522 <<
523 cpu7_opp4: opp-1171200000 { <<
524 opp-hz = /bits/ 64 <11 <<
525 opp-peak-kBps = <30720 <<
526 }; <<
527 <<
528 cpu7_opp5: opp-1286400000 { <<
529 opp-hz = /bits/ 64 <12 <<
530 opp-peak-kBps = <40680 <<
531 }; <<
532 <<
533 cpu7_opp6: opp-1401600000 { <<
534 opp-hz = /bits/ 64 <14 <<
535 opp-peak-kBps = <40680 <<
536 }; <<
537 <<
538 cpu7_opp7: opp-1497600000 { <<
539 opp-hz = /bits/ 64 <14 <<
540 opp-peak-kBps = <40680 <<
541 }; <<
542 <<
543 cpu7_opp8: opp-1612800000 { <<
544 opp-hz = /bits/ 64 <16 <<
545 opp-peak-kBps = <40680 <<
546 }; <<
547 <<
548 cpu7_opp9: opp-1708800000 { <<
549 opp-hz = /bits/ 64 <17 <<
550 opp-peak-kBps = <40680 <<
551 }; <<
552 <<
553 cpu7_opp10: opp-1804800000 { <<
554 opp-hz = /bits/ 64 <18 <<
555 opp-peak-kBps = <62200 <<
556 }; <<
557 <<
558 cpu7_opp11: opp-1920000000 { <<
559 opp-hz = /bits/ 64 <19 <<
560 opp-peak-kBps = <62200 <<
561 }; <<
562 <<
563 cpu7_opp12: opp-2016000000 { <<
564 opp-hz = /bits/ 64 <20 <<
565 opp-peak-kBps = <72160 <<
566 }; <<
567 <<
568 cpu7_opp13: opp-2131200000 { <<
569 opp-hz = /bits/ 64 <21 <<
570 opp-peak-kBps = <83680 <<
571 }; <<
572 <<
573 cpu7_opp14: opp-2227200000 { <<
574 opp-hz = /bits/ 64 <22 <<
575 opp-peak-kBps = <83680 <<
576 }; <<
577 <<
578 cpu7_opp15: opp-2323200000 { <<
579 opp-hz = /bits/ 64 <23 <<
580 opp-peak-kBps = <83680 <<
581 }; <<
582 <<
583 cpu7_opp16: opp-2419200000 { <<
584 opp-hz = /bits/ 64 <24 <<
585 opp-peak-kBps = <83680 <<
586 }; <<
587 <<
588 cpu7_opp17: opp-2534400000 { <<
589 opp-hz = /bits/ 64 <25 <<
590 opp-peak-kBps = <83680 <<
591 }; <<
592 <<
593 cpu7_opp18: opp-2649600000 { <<
594 opp-hz = /bits/ 64 <26 <<
595 opp-peak-kBps = <83680 <<
596 }; <<
597 <<
598 cpu7_opp19: opp-2745600000 { <<
599 opp-hz = /bits/ 64 <27 <<
600 opp-peak-kBps = <83680 <<
601 }; <<
602 <<
603 cpu7_opp20: opp-2841600000 { <<
604 opp-hz = /bits/ 64 <28 <<
605 opp-peak-kBps = <83680 <<
606 }; <<
607 }; 160 };
608 161
609 firmware { 162 firmware {
610 scm: scm { 163 scm: scm {
611 compatible = "qcom,scm 164 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 165 #reset-cells = <1>;
613 }; 166 };
614 }; 167 };
615 168
>> 169 tcsr_mutex: hwlock {
>> 170 compatible = "qcom,tcsr-mutex";
>> 171 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 172 #hwlock-cells = <1>;
>> 173 };
>> 174
616 memory@80000000 { 175 memory@80000000 {
617 device_type = "memory"; 176 device_type = "memory";
618 /* We expect the bootloader to 177 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 178 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 179 };
621 180
622 pmu { 181 pmu {
623 compatible = "arm,armv8-pmuv3" 182 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 183 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 184 };
626 185
627 psci { 186 psci {
628 compatible = "arm,psci-1.0"; 187 compatible = "arm,psci-1.0";
629 method = "smc"; 188 method = "smc";
630 <<
631 CPU_PD0: power-domain-cpu0 { <<
632 #power-domain-cells = <<
633 power-domains = <&CLUS <<
634 domain-idle-states = < <<
635 }; <<
636 <<
637 CPU_PD1: power-domain-cpu1 { <<
638 #power-domain-cells = <<
639 power-domains = <&CLUS <<
640 domain-idle-states = < <<
641 }; <<
642 <<
643 CPU_PD2: power-domain-cpu2 { <<
644 #power-domain-cells = <<
645 power-domains = <&CLUS <<
646 domain-idle-states = < <<
647 }; <<
648 <<
649 CPU_PD3: power-domain-cpu3 { <<
650 #power-domain-cells = <<
651 power-domains = <&CLUS <<
652 domain-idle-states = < <<
653 }; <<
654 <<
655 CPU_PD4: power-domain-cpu4 { <<
656 #power-domain-cells = <<
657 power-domains = <&CLUS <<
658 domain-idle-states = < <<
659 }; <<
660 <<
661 CPU_PD5: power-domain-cpu5 { <<
662 #power-domain-cells = <<
663 power-domains = <&CLUS <<
664 domain-idle-states = < <<
665 }; <<
666 <<
667 CPU_PD6: power-domain-cpu6 { <<
668 #power-domain-cells = <<
669 power-domains = <&CLUS <<
670 domain-idle-states = < <<
671 }; <<
672 <<
673 CPU_PD7: power-domain-cpu7 { <<
674 #power-domain-cells = <<
675 power-domains = <&CLUS <<
676 domain-idle-states = < <<
677 }; <<
678 <<
679 CLUSTER_PD: power-domain-cpu-c <<
680 #power-domain-cells = <<
681 domain-idle-states = < <<
682 }; <<
683 }; 189 };
684 190
685 reserved-memory { 191 reserved-memory {
686 #address-cells = <2>; 192 #address-cells = <2>;
687 #size-cells = <2>; 193 #size-cells = <2>;
688 ranges; 194 ranges;
689 195
690 hyp_mem: memory@85700000 { 196 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 197 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 198 no-map;
693 }; 199 };
694 200
695 xbl_mem: memory@85d00000 { 201 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 202 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 203 no-map;
698 }; 204 };
699 205
700 aop_mem: memory@85f00000 { 206 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 207 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 208 no-map;
703 }; 209 };
704 210
705 aop_cmd_db: memory@85f20000 { 211 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 212 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 213 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 214 no-map;
709 }; 215 };
710 216
711 smem_mem: memory@86000000 { 217 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 218 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 219 no-map;
714 }; 220 };
715 221
716 tz_mem: memory@86200000 { 222 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 223 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 224 no-map;
719 }; 225 };
720 226
721 rmtfs_mem: memory@89b00000 { 227 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 228 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 229 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 230 no-map;
725 231
726 qcom,client-id = <1>; 232 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 233 qcom,vmid = <15>;
728 }; 234 };
729 235
730 camera_mem: memory@8b700000 { 236 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 237 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 238 no-map;
733 }; 239 };
734 240
735 wlan_mem: memory@8bc00000 { 241 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 242 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 243 no-map;
738 }; 244 };
739 245
740 npu_mem: memory@8bd80000 { 246 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 247 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 248 no-map;
743 }; 249 };
744 250
745 adsp_mem: memory@8be00000 { 251 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 252 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 253 no-map;
748 }; 254 };
749 255
750 mpss_mem: memory@8d800000 { 256 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 257 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 258 no-map;
753 }; 259 };
754 260
755 venus_mem: memory@96e00000 { 261 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 262 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 263 no-map;
758 }; 264 };
759 265
760 slpi_mem: memory@97300000 { 266 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 267 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 268 no-map;
763 }; 269 };
764 270
765 ipa_fw_mem: memory@98700000 { 271 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 272 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 273 no-map;
768 }; 274 };
769 275
770 ipa_gsi_mem: memory@98710000 { 276 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 277 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 278 no-map;
773 }; 279 };
774 280
775 gpu_mem: memory@98715000 { 281 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 282 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 283 no-map;
778 }; 284 };
779 285
780 spss_mem: memory@98800000 { 286 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 287 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 288 no-map;
783 }; 289 };
784 290
785 cdsp_mem: memory@98900000 { 291 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 292 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 293 no-map;
788 }; 294 };
789 295
790 qseecom_mem: memory@9e400000 { 296 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 297 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 298 no-map;
793 }; 299 };
794 }; 300 };
795 301
796 smem { 302 smem {
797 compatible = "qcom,smem"; 303 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 304 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 305 hwlocks = <&tcsr_mutex 3>;
800 }; 306 };
801 307
802 smp2p-cdsp { 308 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 309 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 310 qcom,smem = <94>, <432>;
805 311
806 interrupts = <GIC_SPI 576 IRQ_ 312 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 313
808 mboxes = <&apss_shared 6>; 314 mboxes = <&apss_shared 6>;
809 315
810 qcom,local-pid = <0>; 316 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 317 qcom,remote-pid = <5>;
812 318
813 cdsp_smp2p_out: master-kernel 319 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 320 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 321 #qcom,smem-state-cells = <1>;
816 }; 322 };
817 323
818 cdsp_smp2p_in: slave-kernel { 324 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 325 qcom,entry-name = "slave-kernel";
820 326
821 interrupt-controller; 327 interrupt-controller;
822 #interrupt-cells = <2> 328 #interrupt-cells = <2>;
823 }; 329 };
824 }; 330 };
825 331
826 smp2p-lpass { 332 smp2p-lpass {
827 compatible = "qcom,smp2p"; 333 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 334 qcom,smem = <443>, <429>;
829 335
830 interrupts = <GIC_SPI 158 IRQ_ 336 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 337
832 mboxes = <&apss_shared 10>; 338 mboxes = <&apss_shared 10>;
833 339
834 qcom,local-pid = <0>; 340 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 341 qcom,remote-pid = <2>;
836 342
837 adsp_smp2p_out: master-kernel 343 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 344 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 345 #qcom,smem-state-cells = <1>;
840 }; 346 };
841 347
842 adsp_smp2p_in: slave-kernel { 348 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 349 qcom,entry-name = "slave-kernel";
844 350
845 interrupt-controller; 351 interrupt-controller;
846 #interrupt-cells = <2> 352 #interrupt-cells = <2>;
847 }; 353 };
848 }; 354 };
849 355
850 smp2p-mpss { 356 smp2p-mpss {
851 compatible = "qcom,smp2p"; 357 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 358 qcom,smem = <435>, <428>;
853 359
854 interrupts = <GIC_SPI 451 IRQ_ 360 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 361
856 mboxes = <&apss_shared 14>; 362 mboxes = <&apss_shared 14>;
857 363
858 qcom,local-pid = <0>; 364 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 365 qcom,remote-pid = <1>;
860 366
861 modem_smp2p_out: master-kernel 367 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 368 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 369 #qcom,smem-state-cells = <1>;
864 }; 370 };
865 371
866 modem_smp2p_in: slave-kernel { 372 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 373 qcom,entry-name = "slave-kernel";
868 374
869 interrupt-controller; 375 interrupt-controller;
870 #interrupt-cells = <2> 376 #interrupt-cells = <2>;
871 }; 377 };
872 }; 378 };
873 379
874 smp2p-slpi { 380 smp2p-slpi {
875 compatible = "qcom,smp2p"; 381 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 382 qcom,smem = <481>, <430>;
877 383
878 interrupts = <GIC_SPI 172 IRQ_ 384 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 385
880 mboxes = <&apss_shared 26>; 386 mboxes = <&apss_shared 26>;
881 387
882 qcom,local-pid = <0>; 388 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 389 qcom,remote-pid = <3>;
884 390
885 slpi_smp2p_out: master-kernel 391 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 392 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 393 #qcom,smem-state-cells = <1>;
888 }; 394 };
889 395
890 slpi_smp2p_in: slave-kernel { 396 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 397 qcom,entry-name = "slave-kernel";
892 398
893 interrupt-controller; 399 interrupt-controller;
894 #interrupt-cells = <2> 400 #interrupt-cells = <2>;
895 }; 401 };
896 }; 402 };
897 403
898 soc: soc@0 { 404 soc: soc@0 {
899 #address-cells = <2>; 405 #address-cells = <2>;
900 #size-cells = <2>; 406 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 407 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 408 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 409 compatible = "simple-bus";
904 410
905 gcc: clock-controller@100000 { 411 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 412 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 413 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 414 #clock-cells = <1>;
909 #reset-cells = <1>; 415 #reset-cells = <1>;
910 #power-domain-cells = 416 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 417 clock-names = "bi_tcxo",
912 "sleep_c 418 "sleep_clk";
913 clocks = <&rpmhcc RPMH 419 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 420 <&sleep_clk>;
915 }; 421 };
916 422
917 gpi_dma0: dma-controller@80000 <<
918 compatible = "qcom,sm8 <<
919 reg = <0 0x00800000 0 <<
920 interrupts = <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 dma-channels = <13>; <<
934 dma-channel-mask = <0x <<
935 iommus = <&apps_smmu 0 <<
936 #dma-cells = <3>; <<
937 status = "disabled"; <<
938 }; <<
939 <<
940 ethernet: ethernet@20000 { <<
941 compatible = "qcom,sm8 <<
942 reg = <0x0 0x00020000 <<
943 <0x0 0x00036000 <<
944 reg-names = "stmmaceth <<
945 clock-names = "stmmace <<
946 clocks = <&gcc GCC_EMA <<
947 <&gcc GCC_EMAC <<
948 <&gcc GCC_EMAC <<
949 <&gcc GCC_EMAC <<
950 interrupts = <GIC_SPI <<
951 <GIC_SPI <<
952 interrupt-names = "mac <<
953 <<
954 power-domains = <&gcc <<
955 resets = <&gcc GCC_EMA <<
956 <<
957 iommus = <&apps_smmu 0 <<
958 <<
959 snps,tso; <<
960 rx-fifo-depth = <4096> <<
961 tx-fifo-depth = <4096> <<
962 <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 <<
978 qupv3_id_0: geniqup@8c0000 { <<
979 compatible = "qcom,gen <<
980 reg = <0x0 0x008c0000 <<
981 clock-names = "m-ahb", <<
982 clocks = <&gcc GCC_QUP <<
983 <&gcc GCC_QUP <<
984 iommus = <&apps_smmu 0 <<
985 #address-cells = <2>; <<
986 #size-cells = <2>; <<
987 ranges; <<
988 status = "disabled"; <<
989 <<
990 i2c0: i2c@880000 { <<
991 compatible = " <<
992 reg = <0 0x008 <<
993 clock-names = <<
994 clocks = <&gcc <<
995 dmas = <&gpi_d <<
996 <&gpi_d <<
997 dma-names = "t <<
998 pinctrl-names <<
999 pinctrl-0 = <& <<
1000 interrupts = <<
1001 #address-cell <<
1002 #size-cells = <<
1003 status = "dis <<
1004 }; <<
1005 <<
1006 spi0: spi@880000 { <<
1007 compatible = <<
1008 reg = <0 0x00 <<
1009 reg-names = " <<
1010 clock-names = <<
1011 clocks = <&gc <<
1012 dmas = <&gpi_ <<
1013 <&gpi_ <<
1014 dma-names = " <<
1015 pinctrl-names <<
1016 pinctrl-0 = < <<
1017 interrupts = <<
1018 spi-max-frequ <<
1019 #address-cell <<
1020 #size-cells = <<
1021 status = "dis <<
1022 }; <<
1023 <<
1024 i2c1: i2c@884000 { <<
1025 compatible = <<
1026 reg = <0 0x00 <<
1027 clock-names = <<
1028 clocks = <&gc <<
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 pinctrl-names <<
1033 pinctrl-0 = < <<
1034 interrupts = <<
1035 #address-cell <<
1036 #size-cells = <<
1037 status = "dis <<
1038 }; <<
1039 <<
1040 spi1: spi@884000 { <<
1041 compatible = <<
1042 reg = <0 0x00 <<
1043 reg-names = " <<
1044 clock-names = <<
1045 clocks = <&gc <<
1046 dmas = <&gpi_ <<
1047 <&gpi_ <<
1048 dma-names = " <<
1049 pinctrl-names <<
1050 pinctrl-0 = < <<
1051 interrupts = <<
1052 spi-max-frequ <<
1053 #address-cell <<
1054 #size-cells = <<
1055 status = "dis <<
1056 }; <<
1057 <<
1058 i2c2: i2c@888000 { <<
1059 compatible = <<
1060 reg = <0 0x00 <<
1061 clock-names = <<
1062 clocks = <&gc <<
1063 dmas = <&gpi_ <<
1064 <&gpi_ <<
1065 dma-names = " <<
1066 pinctrl-names <<
1067 pinctrl-0 = < <<
1068 interrupts = <<
1069 #address-cell <<
1070 #size-cells = <<
1071 status = "dis <<
1072 }; <<
1073 <<
1074 spi2: spi@888000 { <<
1075 compatible = <<
1076 reg = <0 0x00 <<
1077 reg-names = " <<
1078 clock-names = <<
1079 clocks = <&gc <<
1080 dmas = <&gpi_ <<
1081 <&gpi_ <<
1082 dma-names = " <<
1083 pinctrl-names <<
1084 pinctrl-0 = < <<
1085 interrupts = <<
1086 spi-max-frequ <<
1087 #address-cell <<
1088 #size-cells = <<
1089 status = "dis <<
1090 }; <<
1091 <<
1092 i2c3: i2c@88c000 { <<
1093 compatible = <<
1094 reg = <0 0x00 <<
1095 clock-names = <<
1096 clocks = <&gc <<
1097 dmas = <&gpi_ <<
1098 <&gpi_ <<
1099 dma-names = " <<
1100 pinctrl-names <<
1101 pinctrl-0 = < <<
1102 interrupts = <<
1103 #address-cell <<
1104 #size-cells = <<
1105 status = "dis <<
1106 }; <<
1107 <<
1108 spi3: spi@88c000 { <<
1109 compatible = <<
1110 reg = <0 0x00 <<
1111 reg-names = " <<
1112 clock-names = <<
1113 clocks = <&gc <<
1114 dmas = <&gpi_ <<
1115 <&gpi_ <<
1116 dma-names = " <<
1117 pinctrl-names <<
1118 pinctrl-0 = < <<
1119 interrupts = <<
1120 spi-max-frequ <<
1121 #address-cell <<
1122 #size-cells = <<
1123 status = "dis <<
1124 }; <<
1125 <<
1126 i2c4: i2c@890000 { <<
1127 compatible = <<
1128 reg = <0 0x00 <<
1129 clock-names = <<
1130 clocks = <&gc <<
1131 dmas = <&gpi_ <<
1132 <&gpi_ <<
1133 dma-names = " <<
1134 pinctrl-names <<
1135 pinctrl-0 = < <<
1136 interrupts = <<
1137 #address-cell <<
1138 #size-cells = <<
1139 status = "dis <<
1140 }; <<
1141 <<
1142 spi4: spi@890000 { <<
1143 compatible = <<
1144 reg = <0 0x00 <<
1145 reg-names = " <<
1146 clock-names = <<
1147 clocks = <&gc <<
1148 dmas = <&gpi_ <<
1149 <&gpi_ <<
1150 dma-names = " <<
1151 pinctrl-names <<
1152 pinctrl-0 = < <<
1153 interrupts = <<
1154 spi-max-frequ <<
1155 #address-cell <<
1156 #size-cells = <<
1157 status = "dis <<
1158 }; <<
1159 <<
1160 i2c5: i2c@894000 { <<
1161 compatible = <<
1162 reg = <0 0x00 <<
1163 clock-names = <<
1164 clocks = <&gc <<
1165 dmas = <&gpi_ <<
1166 <&gpi_ <<
1167 dma-names = " <<
1168 pinctrl-names <<
1169 pinctrl-0 = < <<
1170 interrupts = <<
1171 #address-cell <<
1172 #size-cells = <<
1173 status = "dis <<
1174 }; <<
1175 <<
1176 spi5: spi@894000 { <<
1177 compatible = <<
1178 reg = <0 0x00 <<
1179 reg-names = " <<
1180 clock-names = <<
1181 clocks = <&gc <<
1182 dmas = <&gpi_ <<
1183 <&gpi_ <<
1184 dma-names = " <<
1185 pinctrl-names <<
1186 pinctrl-0 = < <<
1187 interrupts = <<
1188 spi-max-frequ <<
1189 #address-cell <<
1190 #size-cells = <<
1191 status = "dis <<
1192 }; <<
1193 <<
1194 i2c6: i2c@898000 { <<
1195 compatible = <<
1196 reg = <0 0x00 <<
1197 clock-names = <<
1198 clocks = <&gc <<
1199 dmas = <&gpi_ <<
1200 <&gpi_ <<
1201 dma-names = " <<
1202 pinctrl-names <<
1203 pinctrl-0 = < <<
1204 interrupts = <<
1205 #address-cell <<
1206 #size-cells = <<
1207 status = "dis <<
1208 }; <<
1209 <<
1210 spi6: spi@898000 { <<
1211 compatible = <<
1212 reg = <0 0x00 <<
1213 reg-names = " <<
1214 clock-names = <<
1215 clocks = <&gc <<
1216 dmas = <&gpi_ <<
1217 <&gpi_ <<
1218 dma-names = " <<
1219 pinctrl-names <<
1220 pinctrl-0 = < <<
1221 interrupts = <<
1222 spi-max-frequ <<
1223 #address-cell <<
1224 #size-cells = <<
1225 status = "dis <<
1226 }; <<
1227 <<
1228 i2c7: i2c@89c000 { <<
1229 compatible = <<
1230 reg = <0 0x00 <<
1231 clock-names = <<
1232 clocks = <&gc <<
1233 dmas = <&gpi_ <<
1234 <&gpi_ <<
1235 dma-names = " <<
1236 pinctrl-names <<
1237 pinctrl-0 = < <<
1238 interrupts = <<
1239 #address-cell <<
1240 #size-cells = <<
1241 status = "dis <<
1242 }; <<
1243 <<
1244 spi7: spi@89c000 { <<
1245 compatible = <<
1246 reg = <0 0x00 <<
1247 reg-names = " <<
1248 clock-names = <<
1249 clocks = <&gc <<
1250 dmas = <&gpi_ <<
1251 <&gpi_ <<
1252 dma-names = " <<
1253 pinctrl-names <<
1254 pinctrl-0 = < <<
1255 interrupts = <<
1256 spi-max-frequ <<
1257 #address-cell <<
1258 #size-cells = <<
1259 status = "dis <<
1260 }; <<
1261 }; <<
1262 <<
1263 gpi_dma1: dma-controller@a000 <<
1264 compatible = "qcom,sm <<
1265 reg = <0 0x00a00000 0 <<
1266 interrupts = <GIC_SPI <<
1267 <GIC_SPI <<
1268 <GIC_SPI <<
1269 <GIC_SPI <<
1270 <GIC_SPI <<
1271 <GIC_SPI <<
1272 <GIC_SPI <<
1273 <GIC_SPI <<
1274 <GIC_SPI <<
1275 <GIC_SPI <<
1276 <GIC_SPI <<
1277 <GIC_SPI <<
1278 <GIC_SPI <<
1279 dma-channels = <13>; <<
1280 dma-channel-mask = <0 <<
1281 iommus = <&apps_smmu <<
1282 #dma-cells = <3>; <<
1283 status = "disabled"; <<
1284 }; <<
1285 <<
1286 qupv3_id_1: geniqup@ac0000 { 423 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 424 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 425 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 426 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 427 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 428 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu <<
1293 #address-cells = <2>; 429 #address-cells = <2>;
1294 #size-cells = <2>; 430 #size-cells = <2>;
1295 ranges; 431 ranges;
1296 status = "disabled"; 432 status = "disabled";
1297 433
1298 i2c8: i2c@a80000 { <<
1299 compatible = <<
1300 reg = <0 0x00 <<
1301 clock-names = <<
1302 clocks = <&gc <<
1303 dmas = <&gpi_ <<
1304 <&gpi_ <<
1305 dma-names = " <<
1306 pinctrl-names <<
1307 pinctrl-0 = < <<
1308 interrupts = <<
1309 #address-cell <<
1310 #size-cells = <<
1311 status = "dis <<
1312 }; <<
1313 <<
1314 spi8: spi@a80000 { <<
1315 compatible = <<
1316 reg = <0 0x00 <<
1317 reg-names = " <<
1318 clock-names = <<
1319 clocks = <&gc <<
1320 dmas = <&gpi_ <<
1321 <&gpi_ <<
1322 dma-names = " <<
1323 pinctrl-names <<
1324 pinctrl-0 = < <<
1325 interrupts = <<
1326 spi-max-frequ <<
1327 #address-cell <<
1328 #size-cells = <<
1329 status = "dis <<
1330 }; <<
1331 <<
1332 i2c9: i2c@a84000 { <<
1333 compatible = <<
1334 reg = <0 0x00 <<
1335 clock-names = <<
1336 clocks = <&gc <<
1337 dmas = <&gpi_ <<
1338 <&gpi_ <<
1339 dma-names = " <<
1340 pinctrl-names <<
1341 pinctrl-0 = < <<
1342 interrupts = <<
1343 #address-cell <<
1344 #size-cells = <<
1345 status = "dis <<
1346 }; <<
1347 <<
1348 spi9: spi@a84000 { <<
1349 compatible = <<
1350 reg = <0 0x00 <<
1351 reg-names = " <<
1352 clock-names = <<
1353 clocks = <&gc <<
1354 dmas = <&gpi_ <<
1355 <&gpi_ <<
1356 dma-names = " <<
1357 pinctrl-names <<
1358 pinctrl-0 = < <<
1359 interrupts = <<
1360 spi-max-frequ <<
1361 #address-cell <<
1362 #size-cells = <<
1363 status = "dis <<
1364 }; <<
1365 <<
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { <<
1378 compatible = <<
1379 reg = <0 0x00 <<
1380 clock-names = <<
1381 clocks = <&gc <<
1382 dmas = <&gpi_ <<
1383 <&gpi_ <<
1384 dma-names = " <<
1385 pinctrl-names <<
1386 pinctrl-0 = < <<
1387 interrupts = <<
1388 #address-cell <<
1389 #size-cells = <<
1390 status = "dis <<
1391 }; <<
1392 <<
1393 spi10: spi@a88000 { <<
1394 compatible = <<
1395 reg = <0 0x00 <<
1396 reg-names = " <<
1397 clock-names = <<
1398 clocks = <&gc <<
1399 dmas = <&gpi_ <<
1400 <&gpi_ <<
1401 dma-names = " <<
1402 pinctrl-names <<
1403 pinctrl-0 = < <<
1404 interrupts = <<
1405 spi-max-frequ <<
1406 #address-cell <<
1407 #size-cells = <<
1408 status = "dis <<
1409 }; <<
1410 <<
1411 i2c11: i2c@a8c000 { <<
1412 compatible = <<
1413 reg = <0 0x00 <<
1414 clock-names = <<
1415 clocks = <&gc <<
1416 dmas = <&gpi_ <<
1417 <&gpi_ <<
1418 dma-names = " <<
1419 pinctrl-names <<
1420 pinctrl-0 = < <<
1421 interrupts = <<
1422 #address-cell <<
1423 #size-cells = <<
1424 status = "dis <<
1425 }; <<
1426 <<
1427 spi11: spi@a8c000 { <<
1428 compatible = <<
1429 reg = <0 0x00 <<
1430 reg-names = " <<
1431 clock-names = <<
1432 clocks = <&gc <<
1433 dmas = <&gpi_ <<
1434 <&gpi_ <<
1435 dma-names = " <<
1436 pinctrl-names <<
1437 pinctrl-0 = < <<
1438 interrupts = <<
1439 spi-max-frequ <<
1440 #address-cell <<
1441 #size-cells = <<
1442 status = "dis <<
1443 }; <<
1444 <<
1445 uart2: serial@a90000 434 uart2: serial@a90000 {
1446 compatible = 435 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 436 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 437 clock-names = "se";
1449 clocks = <&gc 438 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 439 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 440 status = "disabled";
1452 }; 441 };
1453 <<
1454 i2c12: i2c@a90000 { <<
1455 compatible = <<
1456 reg = <0 0x00 <<
1457 clock-names = <<
1458 clocks = <&gc <<
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 pinctrl-names <<
1463 pinctrl-0 = < <<
1464 interrupts = <<
1465 #address-cell <<
1466 #size-cells = <<
1467 status = "dis <<
1468 }; <<
1469 <<
1470 spi12: spi@a90000 { <<
1471 compatible = <<
1472 reg = <0 0x00 <<
1473 reg-names = " <<
1474 clock-names = <<
1475 clocks = <&gc <<
1476 dmas = <&gpi_ <<
1477 <&gpi_ <<
1478 dma-names = " <<
1479 pinctrl-names <<
1480 pinctrl-0 = < <<
1481 interrupts = <<
1482 spi-max-frequ <<
1483 #address-cell <<
1484 #size-cells = <<
1485 status = "dis <<
1486 }; <<
1487 <<
1488 i2c16: i2c@94000 { <<
1489 compatible = <<
1490 reg = <0 0x00 <<
1491 clock-names = <<
1492 clocks = <&gc <<
1493 dmas = <&gpi_ <<
1494 <&gpi_ <<
1495 dma-names = " <<
1496 pinctrl-names <<
1497 pinctrl-0 = < <<
1498 interrupts = <<
1499 #address-cell <<
1500 #size-cells = <<
1501 status = "dis <<
1502 }; <<
1503 <<
1504 spi16: spi@a94000 { <<
1505 compatible = <<
1506 reg = <0 0x00 <<
1507 reg-names = " <<
1508 clock-names = <<
1509 clocks = <&gc <<
1510 dmas = <&gpi_ <<
1511 <&gpi_ <<
1512 dma-names = " <<
1513 pinctrl-names <<
1514 pinctrl-0 = < <<
1515 interrupts = <<
1516 spi-max-frequ <<
1517 #address-cell <<
1518 #size-cells = <<
1519 status = "dis <<
1520 }; <<
1521 }; <<
1522 <<
1523 gpi_dma2: dma-controller@c000 <<
1524 compatible = "qcom,sm <<
1525 reg = <0 0x00c00000 0 <<
1526 interrupts = <GIC_SPI <<
1527 <GIC_SPI <<
1528 <GIC_SPI <<
1529 <GIC_SPI <<
1530 <GIC_SPI <<
1531 <GIC_SPI <<
1532 <GIC_SPI <<
1533 <GIC_SPI <<
1534 <GIC_SPI <<
1535 <GIC_SPI <<
1536 <GIC_SPI <<
1537 <GIC_SPI <<
1538 <GIC_SPI <<
1539 dma-channels = <13>; <<
1540 dma-channel-mask = <0 <<
1541 iommus = <&apps_smmu <<
1542 #dma-cells = <3>; <<
1543 status = "disabled"; <<
1544 }; <<
1545 <<
1546 qupv3_id_2: geniqup@cc0000 { <<
1547 compatible = "qcom,ge <<
1548 reg = <0x0 0x00cc0000 <<
1549 <<
1550 clock-names = "m-ahb" <<
1551 clocks = <&gcc GCC_QU <<
1552 <&gcc GCC_QU <<
1553 iommus = <&apps_smmu <<
1554 #address-cells = <2>; <<
1555 #size-cells = <2>; <<
1556 ranges; <<
1557 status = "disabled"; <<
1558 <<
1559 i2c17: i2c@c80000 { <<
1560 compatible = <<
1561 reg = <0 0x00 <<
1562 clock-names = <<
1563 clocks = <&gc <<
1564 dmas = <&gpi_ <<
1565 <&gpi_ <<
1566 dma-names = " <<
1567 pinctrl-names <<
1568 pinctrl-0 = < <<
1569 interrupts = <<
1570 #address-cell <<
1571 #size-cells = <<
1572 status = "dis <<
1573 }; <<
1574 <<
1575 spi17: spi@c80000 { <<
1576 compatible = <<
1577 reg = <0 0x00 <<
1578 reg-names = " <<
1579 clock-names = <<
1580 clocks = <&gc <<
1581 dmas = <&gpi_ <<
1582 <&gpi_ <<
1583 dma-names = " <<
1584 pinctrl-names <<
1585 pinctrl-0 = < <<
1586 interrupts = <<
1587 spi-max-frequ <<
1588 #address-cell <<
1589 #size-cells = <<
1590 status = "dis <<
1591 }; <<
1592 <<
1593 i2c18: i2c@c84000 { <<
1594 compatible = <<
1595 reg = <0 0x00 <<
1596 clock-names = <<
1597 clocks = <&gc <<
1598 dmas = <&gpi_ <<
1599 <&gpi_ <<
1600 dma-names = " <<
1601 pinctrl-names <<
1602 pinctrl-0 = < <<
1603 interrupts = <<
1604 #address-cell <<
1605 #size-cells = <<
1606 status = "dis <<
1607 }; <<
1608 <<
1609 spi18: spi@c84000 { <<
1610 compatible = <<
1611 reg = <0 0x00 <<
1612 reg-names = " <<
1613 clock-names = <<
1614 clocks = <&gc <<
1615 dmas = <&gpi_ <<
1616 <&gpi_ <<
1617 dma-names = " <<
1618 pinctrl-names <<
1619 pinctrl-0 = < <<
1620 interrupts = <<
1621 spi-max-frequ <<
1622 #address-cell <<
1623 #size-cells = <<
1624 status = "dis <<
1625 }; <<
1626 <<
1627 i2c19: i2c@c88000 { <<
1628 compatible = <<
1629 reg = <0 0x00 <<
1630 clock-names = <<
1631 clocks = <&gc <<
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 pinctrl-names <<
1636 pinctrl-0 = < <<
1637 interrupts = <<
1638 #address-cell <<
1639 #size-cells = <<
1640 status = "dis <<
1641 }; <<
1642 <<
1643 spi19: spi@c88000 { <<
1644 compatible = <<
1645 reg = <0 0x00 <<
1646 reg-names = " <<
1647 clock-names = <<
1648 clocks = <&gc <<
1649 dmas = <&gpi_ <<
1650 <&gpi_ <<
1651 dma-names = " <<
1652 pinctrl-names <<
1653 pinctrl-0 = < <<
1654 interrupts = <<
1655 spi-max-frequ <<
1656 #address-cell <<
1657 #size-cells = <<
1658 status = "dis <<
1659 }; <<
1660 <<
1661 i2c13: i2c@c8c000 { <<
1662 compatible = <<
1663 reg = <0 0x00 <<
1664 clock-names = <<
1665 clocks = <&gc <<
1666 dmas = <&gpi_ <<
1667 <&gpi_ <<
1668 dma-names = " <<
1669 pinctrl-names <<
1670 pinctrl-0 = < <<
1671 interrupts = <<
1672 #address-cell <<
1673 #size-cells = <<
1674 status = "dis <<
1675 }; <<
1676 <<
1677 spi13: spi@c8c000 { <<
1678 compatible = <<
1679 reg = <0 0x00 <<
1680 reg-names = " <<
1681 clock-names = <<
1682 clocks = <&gc <<
1683 dmas = <&gpi_ <<
1684 <&gpi_ <<
1685 dma-names = " <<
1686 pinctrl-names <<
1687 pinctrl-0 = < <<
1688 interrupts = <<
1689 spi-max-frequ <<
1690 #address-cell <<
1691 #size-cells = <<
1692 status = "dis <<
1693 }; <<
1694 <<
1695 i2c14: i2c@c90000 { <<
1696 compatible = <<
1697 reg = <0 0x00 <<
1698 clock-names = <<
1699 clocks = <&gc <<
1700 dmas = <&gpi_ <<
1701 <&gpi_ <<
1702 dma-names = " <<
1703 pinctrl-names <<
1704 pinctrl-0 = < <<
1705 interrupts = <<
1706 #address-cell <<
1707 #size-cells = <<
1708 status = "dis <<
1709 }; <<
1710 <<
1711 spi14: spi@c90000 { <<
1712 compatible = <<
1713 reg = <0 0x00 <<
1714 reg-names = " <<
1715 clock-names = <<
1716 clocks = <&gc <<
1717 dmas = <&gpi_ <<
1718 <&gpi_ <<
1719 dma-names = " <<
1720 pinctrl-names <<
1721 pinctrl-0 = < <<
1722 interrupts = <<
1723 spi-max-frequ <<
1724 #address-cell <<
1725 #size-cells = <<
1726 status = "dis <<
1727 }; <<
1728 <<
1729 i2c15: i2c@c94000 { <<
1730 compatible = <<
1731 reg = <0 0x00 <<
1732 clock-names = <<
1733 clocks = <&gc <<
1734 dmas = <&gpi_ <<
1735 <&gpi_ <<
1736 dma-names = " <<
1737 pinctrl-names <<
1738 pinctrl-0 = < <<
1739 interrupts = <<
1740 #address-cell <<
1741 #size-cells = <<
1742 status = "dis <<
1743 }; <<
1744 <<
1745 spi15: spi@c94000 { <<
1746 compatible = <<
1747 reg = <0 0x00 <<
1748 reg-names = " <<
1749 clock-names = <<
1750 clocks = <&gc <<
1751 dmas = <&gpi_ <<
1752 <&gpi_ <<
1753 dma-names = " <<
1754 pinctrl-names <<
1755 pinctrl-0 = < <<
1756 interrupts = <<
1757 spi-max-frequ <<
1758 #address-cell <<
1759 #size-cells = <<
1760 status = "dis <<
1761 }; <<
1762 }; 442 };
1763 443
1764 config_noc: interconnect@1500 444 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 445 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 446 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 447 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 448 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 449 };
1770 450
1771 system_noc: interconnect@1620 451 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 452 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 453 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 454 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 455 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 456 };
1777 457
1778 mc_virt: interconnect@163a000 458 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 459 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 460 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 461 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 462 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 463 };
1784 464
1785 aggre1_noc: interconnect@16e0 465 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 466 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 467 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 468 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 469 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 470 };
1791 471
1792 aggre2_noc: interconnect@1700 472 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 473 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 474 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 475 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 476 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 477 };
1798 478
1799 compute_noc: interconnect@172 479 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 480 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 481 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 482 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 483 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 484 };
1805 485
1806 mmss_noc: interconnect@174000 486 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 487 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 488 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 489 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 490 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 491 };
1812 492
1813 system-cache-controller@92000 493 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 494 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 495 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 496 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 497 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 498 };
1822 499
1823 dma@10a2000 { <<
1824 compatible = "qcom,sm <<
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 <<
1832 <0 0x60000000 0 <<
1833 <0 0x60000f20 0 <<
1834 <0 0x60001000 0 <<
1835 <0 0x60100000 0 <<
1836 reg-names = "parf", " <<
1837 device_type = "pci"; <<
1838 linux,pci-domain = <0 <<
1839 bus-range = <0x00 0xf <<
1840 num-lanes = <1>; <<
1841 <<
1842 #address-cells = <3>; <<
1843 #size-cells = <2>; <<
1844 <<
1845 ranges = <0x01000000 <<
1846 <0x02000000 <<
1847 <<
1848 interrupts = <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 <<
1865 interrupt-map-mask = <<
1866 interrupt-map = <0 0 <<
1867 <0 0 <<
1868 <0 0 <<
1869 <0 0 <<
1870 <<
1871 clocks = <&gcc GCC_PC <<
1872 <&gcc GCC_PC <<
1873 <&gcc GCC_PC <<
1874 <&gcc GCC_PC <<
1875 <&gcc GCC_PC <<
1876 <&gcc GCC_PC <<
1877 <&gcc GCC_AG <<
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", <<
1880 "aux", <<
1881 "cfg", <<
1882 "bus_ma <<
1883 "bus_sl <<
1884 "slave_ <<
1885 "tbu", <<
1886 "ref"; <<
1887 <<
1888 iommu-map = <0x0 &a <<
1889 <0x100 &a <<
1890 <<
1891 resets = <&gcc GCC_PC <<
1892 reset-names = "pci"; <<
1893 <<
1894 power-domains = <&gcc <<
1895 <<
1896 phys = <&pcie0_phy>; <<
1897 phy-names = "pciephy" <<
1898 <<
1899 perst-gpios = <&tlmm <<
1900 wake-gpios = <&tlmm 3 <<
1901 <<
1902 pinctrl-names = "defa <<
1903 pinctrl-0 = <&pcie0_d <<
1904 <<
1905 status = "disabled"; <<
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; <<
1917 <<
1918 pcie0_phy: phy@1c06000 { <<
1919 compatible = "qcom,sm <<
1920 reg = <0 0x01c06000 0 <<
1921 clocks = <&gcc GCC_PC <<
1922 <&gcc GCC_PC <<
1923 <&gcc GCC_PC <<
1924 <&gcc GCC_PC <<
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 <<
1937 resets = <&gcc GCC_PC <<
1938 reset-names = "phy"; <<
1939 <<
1940 assigned-clocks = <&g <<
1941 assigned-clock-rates <<
1942 <<
1943 status = "disabled"; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@1c08000 { <<
1947 compatible = "qcom,pc <<
1948 reg = <0 0x01c08000 0 <<
1949 <0 0x40000000 0 <<
1950 <0 0x40000f20 0 <<
1951 <0 0x40001000 0 <<
1952 <0 0x40100000 0 <<
1953 reg-names = "parf", " <<
1954 device_type = "pci"; <<
1955 linux,pci-domain = <1 <<
1956 bus-range = <0x00 0xf <<
1957 num-lanes = <2>; <<
1958 <<
1959 #address-cells = <3>; <<
1960 #size-cells = <2>; <<
1961 <<
1962 ranges = <0x01000000 <<
1963 <0x02000000 <<
1964 <<
1965 interrupts = <GIC_SPI <<
1966 <GIC_SPI <<
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 <<
1982 interrupt-map-mask = <<
1983 interrupt-map = <0 0 <<
1984 <0 0 <<
1985 <0 0 <<
1986 <0 0 <<
1987 <<
1988 clocks = <&gcc GCC_PC <<
1989 <&gcc GCC_PC <<
1990 <&gcc GCC_PC <<
1991 <&gcc GCC_PC <<
1992 <&gcc GCC_PC <<
1993 <&gcc GCC_PC <<
1994 <&gcc GCC_AG <<
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", <<
1997 "aux", <<
1998 "cfg", <<
1999 "bus_ma <<
2000 "bus_sl <<
2001 "slave_ <<
2002 "tbu", <<
2003 "ref"; <<
2004 <<
2005 assigned-clocks = <&g <<
2006 assigned-clock-rates <<
2007 <<
2008 iommu-map = <0x0 &a <<
2009 <0x100 &a <<
2010 <<
2011 resets = <&gcc GCC_PC <<
2012 reset-names = "pci"; <<
2013 <<
2014 power-domains = <&gcc <<
2015 <<
2016 phys = <&pcie1_phy>; <<
2017 phy-names = "pciephy" <<
2018 <<
2019 perst-gpios = <&tlmm <<
2020 enable-gpio = <&tlmm <<
2021 <<
2022 pinctrl-names = "defa <<
2023 pinctrl-0 = <&pcie1_d <<
2024 <<
2025 status = "disabled"; <<
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; <<
2037 <<
2038 pcie1_phy: phy@1c0e000 { <<
2039 compatible = "qcom,sm <<
2040 reg = <0 0x01c0e000 0 <<
2041 clocks = <&gcc GCC_PC <<
2042 <&gcc GCC_PC <<
2043 <&gcc GCC_PC <<
2044 <&gcc GCC_PC <<
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 <<
2057 resets = <&gcc GCC_PC <<
2058 reset-names = "phy"; <<
2059 <<
2060 assigned-clocks = <&g <<
2061 assigned-clock-rates <<
2062 <<
2063 status = "disabled"; <<
2064 }; <<
2065 <<
2066 ufs_mem_hc: ufshc@1d84000 { 500 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 501 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 502 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 !! 503 reg = <0 0x01d84000 0 0x2500>;
2070 <0 0x01d90000 0 <<
2071 reg-names = "std", "i <<
2072 interrupts = <GIC_SPI 504 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 505 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 506 phy-names = "ufsphy";
2075 lanes-per-direction = 507 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 508 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 509 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 510 reset-names = "rst";
2079 511
2080 iommus = <&apps_smmu 512 iommus = <&apps_smmu 0x300 0>;
2081 513
2082 clock-names = 514 clock-names =
2083 "core_clk", 515 "core_clk",
2084 "bus_aggr_clk 516 "bus_aggr_clk",
2085 "iface_clk", 517 "iface_clk",
2086 "core_clk_uni 518 "core_clk_unipro",
2087 "ref_clk", 519 "ref_clk",
2088 "tx_lane0_syn 520 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 521 "rx_lane0_sync_clk",
2090 "rx_lane1_syn !! 522 "rx_lane1_sync_clk";
2091 "ice_core_clk <<
2092 clocks = 523 clocks =
2093 <&gcc GCC_UFS 524 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 525 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 526 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 527 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 528 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 529 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 530 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS !! 531 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2101 <&gcc GCC_UFS <<
2102 freq-table-hz = 532 freq-table-hz =
2103 <37500000 300 533 <37500000 300000000>,
2104 <0 0>, 534 <0 0>,
2105 <0 0>, 535 <0 0>,
2106 <37500000 300 536 <37500000 300000000>,
2107 <0 0>, 537 <0 0>,
2108 <0 0>, 538 <0 0>,
2109 <0 0>, 539 <0 0>,
2110 <0 0>, !! 540 <0 0>;
2111 <0 300000000> <<
2112 541
2113 status = "disabled"; 542 status = "disabled";
2114 }; 543 };
2115 544
2116 ufs_mem_phy: phy@1d87000 { 545 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 546 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 547 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 548 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 549 #size-cells = <2>;
2121 <&gcc GCC_UF !! 550 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 551 clock-names = "ref",
2124 "ref_au !! 552 "ref_aux";
2125 "qref"; !! 553 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2126 !! 554 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2127 power-domains = <&gcc <<
2128 555
2129 resets = <&ufs_mem_hc 556 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 557 reset-names = "ufsphy";
>> 558 status = "disabled";
2131 559
2132 #phy-cells = <0>; !! 560 ufs_mem_phy_lanes: lanes@1d87400 {
>> 561 reg = <0 0x01d87400 0 0x108>,
>> 562 <0 0x01d87600 0 0x1e0>,
>> 563 <0 0x01d87c00 0 0x1dc>,
>> 564 <0 0x01d87800 0 0x108>,
>> 565 <0 0x01d87a00 0 0x1e0>;
>> 566 #phy-cells = <0>;
>> 567 };
>> 568 };
2133 569
2134 status = "disabled"; !! 570 ipa_virt: interconnect@1e00000 {
>> 571 compatible = "qcom,sm8150-ipa-virt";
>> 572 reg = <0 0x01e00000 0 0x1000>;
>> 573 #interconnect-cells = <1>;
>> 574 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 575 };
2136 576
2137 cryptobam: dma-controller@1dc !! 577 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 578 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 579 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 580 };
2177 581
2178 remoteproc_slpi: remoteproc@2 582 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 583 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 584 reg = <0x0 0x02400000 0x0 0x4040>;
2181 585
2182 interrupts-extended = 586 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 587 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 588 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 589 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 590 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 591 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 592 "handover", "stop-ack";
2189 593
2190 clocks = <&rpmhcc RPM 594 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 595 clock-names = "xo";
2192 596
2193 power-domains = <&rpm !! 597 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
2194 <&rpm !! 598 <&rpmhpd 3>,
2195 power-domain-names = !! 599 <&rpmhpd 2>;
>> 600 power-domain-names = "load_state", "lcx", "lmx";
2196 601
2197 memory-region = <&slp 602 memory-region = <&slpi_mem>;
2198 603
2199 qcom,qmp = <&aoss_qmp <<
2200 <<
2201 qcom,smem-states = <& 604 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 605 qcom,smem-state-names = "stop";
2203 606
2204 status = "disabled"; 607 status = "disabled";
2205 608
2206 glink-edge { 609 glink-edge {
2207 interrupts = 610 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 611 label = "dsps";
2209 qcom,remote-p 612 qcom,remote-pid = <3>;
2210 mboxes = <&ap 613 mboxes = <&apss_shared 24>;
2211 <<
2212 fastrpc { <<
2213 compa <<
2214 qcom, <<
2215 label <<
2216 qcom, <<
2217 #addr <<
2218 #size <<
2219 <<
2220 compu <<
2221 <<
2222 <<
2223 <<
2224 }; <<
2225 <<
2226 compu <<
2227 <<
2228 <<
2229 <<
2230 }; <<
2231 <<
2232 compu <<
2233 <<
2234 <<
2235 <<
2236 <<
2237 }; <<
2238 }; <<
2239 }; 614 };
2240 }; 615 };
2241 616
2242 gpu: gpu@2c00000 { 617 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 618 /*
>> 619 * note: the amd,imageon compatible makes it possible
>> 620 * to use the drm/msm driver without the display node,
>> 621 * make sure to remove it when display node is added
>> 622 */
>> 623 compatible = "qcom,adreno-640.1",
>> 624 "qcom,adreno",
>> 625 "amd,imageon";
>> 626 #stream-id-cells = <16>;
>> 627
2244 reg = <0 0x02c00000 0 628 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 629 reg-names = "kgsl_3d0_reg_memory";
2246 630
2247 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 632
2249 iommus = <&adreno_smm 633 iommus = <&adreno_smmu 0 0x401>;
2250 634
2251 operating-points-v2 = 635 operating-points-v2 = <&gpu_opp_table>;
2252 636
2253 qcom,gmu = <&gmu>; 637 qcom,gmu = <&gmu>;
2254 638
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; <<
2260 <<
2261 zap-shader { 639 zap-shader {
2262 memory-region 640 memory-region = <&gpu_mem>;
2263 }; 641 };
2264 642
>> 643 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 644 gpu_opp_table: opp-table {
2266 compatible = 645 compatible = "operating-points-v2";
2267 646
2268 opp-675000000 647 opp-675000000 {
2269 opp-h 648 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 649 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 650 };
2273 651
2274 opp-585000000 652 opp-585000000 {
2275 opp-h 653 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 654 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 655 };
2279 656
2280 opp-499200000 657 opp-499200000 {
2281 opp-h 658 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 659 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 660 };
2285 661
2286 opp-427000000 662 opp-427000000 {
2287 opp-h 663 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 664 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 665 };
2291 666
2292 opp-345000000 667 opp-345000000 {
2293 opp-h 668 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 669 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 670 };
2297 671
2298 opp-257000000 672 opp-257000000 {
2299 opp-h 673 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 674 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 675 };
2303 }; 676 };
2304 }; 677 };
2305 678
2306 gmu: gmu@2c6a000 { 679 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 680 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 681
2309 reg = <0 0x02c6a000 0 682 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 683 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 684 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 685 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 686
2314 interrupts = <GIC_SPI 687 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 688 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 689 interrupt-names = "hfi", "gmu";
2317 690
2318 clocks = <&gpucc GPU_ 691 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 692 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 693 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 694 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 695 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 696 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 697
2325 power-domains = <&gpu 698 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 699 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 700 power-domain-names = "cx", "gx";
2328 701
2329 iommus = <&adreno_smm 702 iommus = <&adreno_smmu 5 0x400>;
2330 703
2331 operating-points-v2 = 704 operating-points-v2 = <&gmu_opp_table>;
2332 705
2333 status = "disabled"; <<
2334 <<
2335 gmu_opp_table: opp-ta 706 gmu_opp_table: opp-table {
2336 compatible = 707 compatible = "operating-points-v2";
2337 708
2338 opp-200000000 709 opp-200000000 {
2339 opp-h 710 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 711 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 712 };
2342 }; 713 };
2343 }; 714 };
2344 715
2345 gpucc: clock-controller@2c900 716 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 717 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 718 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 719 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 720 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 721 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 722 clock-names = "bi_tcxo",
2352 "gcc_gp 723 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 724 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 725 #clock-cells = <1>;
2355 #reset-cells = <1>; 726 #reset-cells = <1>;
2356 #power-domain-cells = 727 #power-domain-cells = <1>;
2357 }; 728 };
2358 729
2359 adreno_smmu: iommu@2ca0000 { 730 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 731 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 732 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 733 #iommu-cells = <2>;
2364 #global-interrupts = 734 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 735 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 736 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 737 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 738 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 739 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 740 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 741 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 742 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 743 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 744 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 745 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 746 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 747 clock-names = "ahb", "bus", "iface";
2378 748
2379 power-domains = <&gpu 749 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 750 };
2381 751
2382 tlmm: pinctrl@3100000 { 752 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 753 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 754 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 755 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 756 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 757 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 758 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 759 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 760 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 761 gpio-controller;
2392 #gpio-cells = <2>; 762 #gpio-cells = <2>;
2393 interrupt-controller; 763 interrupt-controller;
2394 #interrupt-cells = <2 764 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc <<
2396 <<
2397 qup_i2c0_default: qup <<
2398 pins = "gpio0 <<
2399 function = "q <<
2400 drive-strengt <<
2401 bias-disable; <<
2402 }; <<
2403 <<
2404 qup_spi0_default: qup <<
2405 pins = "gpio0 <<
2406 function = "q <<
2407 drive-strengt <<
2408 bias-disable; <<
2409 }; <<
2410 <<
2411 qup_i2c1_default: qup <<
2412 pins = "gpio1 <<
2413 function = "q <<
2414 drive-strengt <<
2415 bias-disable; <<
2416 }; <<
2417 <<
2418 qup_spi1_default: qup <<
2419 pins = "gpio1 <<
2420 function = "q <<
2421 drive-strengt <<
2422 bias-disable; <<
2423 }; <<
2424 <<
2425 qup_i2c2_default: qup <<
2426 pins = "gpio1 <<
2427 function = "q <<
2428 drive-strengt <<
2429 bias-disable; <<
2430 }; <<
2431 <<
2432 qup_spi2_default: qup <<
2433 pins = "gpio1 <<
2434 function = "q <<
2435 drive-strengt <<
2436 bias-disable; <<
2437 }; <<
2438 <<
2439 qup_i2c3_default: qup <<
2440 pins = "gpio1 <<
2441 function = "q <<
2442 drive-strengt <<
2443 bias-disable; <<
2444 }; <<
2445 <<
2446 qup_spi3_default: qup <<
2447 pins = "gpio1 <<
2448 function = "q <<
2449 drive-strengt <<
2450 bias-disable; <<
2451 }; <<
2452 <<
2453 qup_i2c4_default: qup <<
2454 pins = "gpio5 <<
2455 function = "q <<
2456 drive-strengt <<
2457 bias-disable; <<
2458 }; <<
2459 <<
2460 qup_spi4_default: qup <<
2461 pins = "gpio5 <<
2462 function = "q <<
2463 drive-strengt <<
2464 bias-disable; <<
2465 }; <<
2466 <<
2467 qup_i2c5_default: qup <<
2468 pins = "gpio1 <<
2469 function = "q <<
2470 drive-strengt <<
2471 bias-disable; <<
2472 }; <<
2473 <<
2474 qup_spi5_default: qup <<
2475 pins = "gpio1 <<
2476 function = "q <<
2477 drive-strengt <<
2478 bias-disable; <<
2479 }; <<
2480 <<
2481 qup_i2c6_default: qup <<
2482 pins = "gpio6 <<
2483 function = "q <<
2484 drive-strengt <<
2485 bias-disable; <<
2486 }; <<
2487 <<
2488 qup_spi6_default: qup <<
2489 pins = "gpio4 <<
2490 function = "q <<
2491 drive-strengt <<
2492 bias-disable; <<
2493 }; <<
2494 <<
2495 qup_i2c7_default: qup <<
2496 pins = "gpio9 <<
2497 function = "q <<
2498 drive-strengt <<
2499 bias-disable; <<
2500 }; <<
2501 <<
2502 qup_spi7_default: qup <<
2503 pins = "gpio9 <<
2504 function = "q <<
2505 drive-strengt <<
2506 bias-disable; <<
2507 }; <<
2508 <<
2509 qup_i2c8_default: qup <<
2510 pins = "gpio8 <<
2511 function = "q <<
2512 drive-strengt <<
2513 bias-disable; <<
2514 }; <<
2515 <<
2516 qup_spi8_default: qup <<
2517 pins = "gpio8 <<
2518 function = "q <<
2519 drive-strengt <<
2520 bias-disable; <<
2521 }; <<
2522 <<
2523 qup_i2c9_default: qup <<
2524 pins = "gpio3 <<
2525 function = "q <<
2526 drive-strengt <<
2527 bias-disable; <<
2528 }; <<
2529 <<
2530 qup_spi9_default: qup <<
2531 pins = "gpio3 <<
2532 function = "q <<
2533 drive-strengt <<
2534 bias-disable; <<
2535 }; <<
2536 <<
2537 qup_uart9_default: qu <<
2538 pins = "gpio4 <<
2539 function = "q <<
2540 drive-strengt <<
2541 bias-disable; <<
2542 }; <<
2543 <<
2544 qup_i2c10_default: qu <<
2545 pins = "gpio9 <<
2546 function = "q <<
2547 drive-strengt <<
2548 bias-disable; <<
2549 }; <<
2550 <<
2551 qup_spi10_default: qu <<
2552 pins = "gpio9 <<
2553 function = "q <<
2554 drive-strengt <<
2555 bias-disable; <<
2556 }; <<
2557 <<
2558 qup_i2c11_default: qu <<
2559 pins = "gpio9 <<
2560 function = "q <<
2561 drive-strengt <<
2562 bias-disable; <<
2563 }; <<
2564 <<
2565 qup_spi11_default: qu <<
2566 pins = "gpio9 <<
2567 function = "q <<
2568 drive-strengt <<
2569 bias-disable; <<
2570 }; <<
2571 <<
2572 qup_i2c12_default: qu <<
2573 pins = "gpio8 <<
2574 function = "q <<
2575 drive-strengt <<
2576 bias-disable; <<
2577 }; <<
2578 <<
2579 qup_spi12_default: qu <<
2580 pins = "gpio8 <<
2581 function = "q <<
2582 drive-strengt <<
2583 bias-disable; <<
2584 }; <<
2585 <<
2586 qup_i2c13_default: qu <<
2587 pins = "gpio4 <<
2588 function = "q <<
2589 drive-strengt <<
2590 bias-disable; <<
2591 }; <<
2592 <<
2593 qup_spi13_default: qu <<
2594 pins = "gpio4 <<
2595 function = "q <<
2596 drive-strengt <<
2597 bias-disable; <<
2598 }; <<
2599 <<
2600 qup_i2c14_default: qu <<
2601 pins = "gpio4 <<
2602 function = "q <<
2603 drive-strengt <<
2604 bias-disable; <<
2605 }; <<
2606 <<
2607 qup_spi14_default: qu <<
2608 pins = "gpio4 <<
2609 function = "q <<
2610 drive-strengt <<
2611 bias-disable; <<
2612 }; <<
2613 <<
2614 qup_i2c15_default: qu <<
2615 pins = "gpio2 <<
2616 function = "q <<
2617 drive-strengt <<
2618 bias-disable; <<
2619 }; <<
2620 <<
2621 qup_spi15_default: qu <<
2622 pins = "gpio2 <<
2623 function = "q <<
2624 drive-strengt <<
2625 bias-disable; <<
2626 }; <<
2627 <<
2628 qup_i2c16_default: qu <<
2629 pins = "gpio8 <<
2630 function = "q <<
2631 drive-strengt <<
2632 bias-disable; <<
2633 }; <<
2634 <<
2635 qup_spi16_default: qu <<
2636 pins = "gpio8 <<
2637 function = "q <<
2638 drive-strengt <<
2639 bias-disable; <<
2640 }; <<
2641 <<
2642 qup_i2c17_default: qu <<
2643 pins = "gpio5 <<
2644 function = "q <<
2645 drive-strengt <<
2646 bias-disable; <<
2647 }; <<
2648 <<
2649 qup_spi17_default: qu <<
2650 pins = "gpio5 <<
2651 function = "q <<
2652 drive-strengt <<
2653 bias-disable; <<
2654 }; <<
2655 <<
2656 qup_i2c18_default: qu <<
2657 pins = "gpio2 <<
2658 function = "q <<
2659 drive-strengt <<
2660 bias-disable; <<
2661 }; <<
2662 <<
2663 qup_spi18_default: qu <<
2664 pins = "gpio2 <<
2665 function = "q <<
2666 drive-strengt <<
2667 bias-disable; <<
2668 }; <<
2669 <<
2670 qup_i2c19_default: qu <<
2671 pins = "gpio5 <<
2672 function = "q <<
2673 drive-strengt <<
2674 bias-disable; <<
2675 }; <<
2676 <<
2677 qup_spi19_default: qu <<
2678 pins = "gpio5 <<
2679 function = "q <<
2680 drive-strengt <<
2681 bias-disable; <<
2682 }; <<
2683 <<
2684 pcie0_default_state: <<
2685 perst-pins { <<
2686 pins <<
2687 funct <<
2688 drive <<
2689 bias- <<
2690 }; <<
2691 <<
2692 clkreq-pins { <<
2693 pins <<
2694 funct <<
2695 drive <<
2696 bias- <<
2697 }; <<
2698 <<
2699 wake-pins { <<
2700 pins <<
2701 funct <<
2702 drive <<
2703 bias- <<
2704 }; <<
2705 }; <<
2706 <<
2707 pcie1_default_state: <<
2708 perst-pins { <<
2709 pins <<
2710 funct <<
2711 drive <<
2712 bias- <<
2713 }; <<
2714 <<
2715 clkreq-pins { <<
2716 pins <<
2717 funct <<
2718 drive <<
2719 bias- <<
2720 }; <<
2721 <<
2722 wake-pins { <<
2723 pins <<
2724 funct <<
2725 drive <<
2726 bias- <<
2727 }; <<
2728 }; <<
2729 }; 765 };
2730 766
2731 remoteproc_mpss: remoteproc@4 767 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 768 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 769 reg = <0x0 0x04080000 0x0 0x4040>;
2734 770
2735 interrupts-extended = 771 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 772 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 773 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 774 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 775 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 776 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 777 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 778 "stop-ack", "shutdown-ack";
2743 779
2744 clocks = <&rpmhcc RPM 780 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 781 clock-names = "xo";
2746 782
2747 power-domains = <&rpm !! 783 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2748 <&rpm !! 784 <&rpmhpd 7>,
2749 power-domain-names = !! 785 <&rpmhpd 0>;
>> 786 power-domain-names = "load_state", "cx", "mss";
2750 787
2751 memory-region = <&mps 788 memory-region = <&mpss_mem>;
2752 789
2753 qcom,qmp = <&aoss_qmp <<
2754 <<
2755 qcom,smem-states = <& 790 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 791 qcom,smem-state-names = "stop";
2757 792
2758 status = "disabled"; <<
2759 <<
2760 glink-edge { 793 glink-edge {
2761 interrupts = 794 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 795 label = "modem";
2763 qcom,remote-p 796 qcom,remote-pid = <1>;
2764 mboxes = <&ap 797 mboxes = <&apss_shared 12>;
2765 }; 798 };
2766 }; 799 };
2767 800
2768 stm@6002000 { 801 stm@6002000 {
2769 compatible = "arm,cor 802 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 803 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 804 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 805 reg-names = "stm-base", "stm-stimulus-base";
2773 806
2774 clocks = <&aoss_qmp>; 807 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 808 clock-names = "apb_pclk";
2776 809
2777 out-ports { 810 out-ports {
2778 port { 811 port {
2779 stm_o 812 stm_out: endpoint {
2780 813 remote-endpoint = <&funnel0_in7>;
2781 }; 814 };
2782 }; 815 };
2783 }; 816 };
2784 }; 817 };
2785 818
2786 funnel@6041000 { 819 funnel@6041000 {
2787 compatible = "arm,cor 820 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 821 reg = <0 0x06041000 0 0x1000>;
2789 822
2790 clocks = <&aoss_qmp>; 823 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 824 clock-names = "apb_pclk";
2792 825
2793 out-ports { 826 out-ports {
2794 port { 827 port {
2795 funne 828 funnel0_out: endpoint {
2796 829 remote-endpoint = <&merge_funnel_in0>;
2797 }; 830 };
2798 }; 831 };
2799 }; 832 };
2800 833
2801 in-ports { 834 in-ports {
2802 #address-cell 835 #address-cells = <1>;
2803 #size-cells = 836 #size-cells = <0>;
2804 837
2805 port@7 { 838 port@7 {
2806 reg = 839 reg = <7>;
2807 funne 840 funnel0_in7: endpoint {
2808 841 remote-endpoint = <&stm_out>;
2809 }; 842 };
2810 }; 843 };
2811 }; 844 };
2812 }; 845 };
2813 846
2814 funnel@6042000 { 847 funnel@6042000 {
2815 compatible = "arm,cor 848 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 849 reg = <0 0x06042000 0 0x1000>;
2817 850
2818 clocks = <&aoss_qmp>; 851 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 852 clock-names = "apb_pclk";
2820 853
2821 out-ports { 854 out-ports {
2822 port { 855 port {
2823 funne 856 funnel1_out: endpoint {
2824 857 remote-endpoint = <&merge_funnel_in1>;
2825 }; 858 };
2826 }; 859 };
2827 }; 860 };
2828 861
2829 in-ports { 862 in-ports {
2830 #address-cell 863 #address-cells = <1>;
2831 #size-cells = 864 #size-cells = <0>;
2832 865
2833 port@4 { 866 port@4 {
2834 reg = 867 reg = <4>;
2835 funne 868 funnel1_in4: endpoint {
2836 869 remote-endpoint = <&swao_replicator_out>;
2837 }; 870 };
2838 }; 871 };
2839 }; 872 };
2840 }; 873 };
2841 874
2842 funnel@6043000 { 875 funnel@6043000 {
2843 compatible = "arm,cor 876 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 877 reg = <0 0x06043000 0 0x1000>;
2845 878
2846 clocks = <&aoss_qmp>; 879 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 880 clock-names = "apb_pclk";
2848 881
2849 out-ports { 882 out-ports {
2850 port { 883 port {
2851 funne 884 funnel2_out: endpoint {
2852 885 remote-endpoint = <&merge_funnel_in2>;
2853 }; 886 };
2854 }; 887 };
2855 }; 888 };
2856 889
2857 in-ports { 890 in-ports {
2858 #address-cell 891 #address-cells = <1>;
2859 #size-cells = 892 #size-cells = <0>;
2860 893
2861 port@2 { 894 port@2 {
2862 reg = 895 reg = <2>;
2863 funne 896 funnel2_in2: endpoint {
2864 897 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 898 };
2866 }; 899 };
2867 }; 900 };
2868 }; 901 };
2869 902
2870 funnel@6045000 { 903 funnel@6045000 {
2871 compatible = "arm,cor 904 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 905 reg = <0 0x06045000 0 0x1000>;
2873 906
2874 clocks = <&aoss_qmp>; 907 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 908 clock-names = "apb_pclk";
2876 909
2877 out-ports { 910 out-ports {
2878 port { 911 port {
2879 merge 912 merge_funnel_out: endpoint {
2880 913 remote-endpoint = <&etf_in>;
2881 }; 914 };
2882 }; 915 };
2883 }; 916 };
2884 917
2885 in-ports { 918 in-ports {
2886 #address-cell 919 #address-cells = <1>;
2887 #size-cells = 920 #size-cells = <0>;
2888 921
2889 port@0 { 922 port@0 {
2890 reg = 923 reg = <0>;
2891 merge 924 merge_funnel_in0: endpoint {
2892 925 remote-endpoint = <&funnel0_out>;
2893 }; 926 };
2894 }; 927 };
2895 928
2896 port@1 { 929 port@1 {
2897 reg = 930 reg = <1>;
2898 merge 931 merge_funnel_in1: endpoint {
2899 932 remote-endpoint = <&funnel1_out>;
2900 }; 933 };
2901 }; 934 };
2902 935
2903 port@2 { 936 port@2 {
2904 reg = 937 reg = <2>;
2905 merge 938 merge_funnel_in2: endpoint {
2906 939 remote-endpoint = <&funnel2_out>;
2907 }; 940 };
2908 }; 941 };
2909 }; 942 };
2910 }; 943 };
2911 944
2912 replicator@6046000 { 945 replicator@6046000 {
2913 compatible = "arm,cor 946 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 947 reg = <0 0x06046000 0 0x1000>;
2915 948
2916 clocks = <&aoss_qmp>; 949 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 950 clock-names = "apb_pclk";
2918 951
2919 out-ports { 952 out-ports {
2920 #address-cell 953 #address-cells = <1>;
2921 #size-cells = 954 #size-cells = <0>;
2922 955
2923 port@0 { 956 port@0 {
2924 reg = 957 reg = <0>;
2925 repli 958 replicator_out0: endpoint {
2926 959 remote-endpoint = <&etr_in>;
2927 }; 960 };
2928 }; 961 };
2929 962
2930 port@1 { 963 port@1 {
2931 reg = 964 reg = <1>;
2932 repli 965 replicator_out1: endpoint {
2933 966 remote-endpoint = <&replicator1_in>;
2934 }; 967 };
2935 }; 968 };
2936 }; 969 };
2937 970
2938 in-ports { 971 in-ports {
2939 port { 972 port {
2940 repli 973 replicator_in0: endpoint {
2941 974 remote-endpoint = <&etf_out>;
2942 }; 975 };
2943 }; 976 };
2944 }; 977 };
2945 }; 978 };
2946 979
2947 etf@6047000 { 980 etf@6047000 {
2948 compatible = "arm,cor 981 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 982 reg = <0 0x06047000 0 0x1000>;
2950 983
2951 clocks = <&aoss_qmp>; 984 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 985 clock-names = "apb_pclk";
2953 986
2954 out-ports { 987 out-ports {
2955 port { 988 port {
2956 etf_o 989 etf_out: endpoint {
2957 990 remote-endpoint = <&replicator_in0>;
2958 }; 991 };
2959 }; 992 };
2960 }; 993 };
2961 994
2962 in-ports { 995 in-ports {
2963 port { 996 port {
2964 etf_i 997 etf_in: endpoint {
2965 998 remote-endpoint = <&merge_funnel_out>;
2966 }; 999 };
2967 }; 1000 };
2968 }; 1001 };
2969 }; 1002 };
2970 1003
2971 etr@6048000 { 1004 etr@6048000 {
2972 compatible = "arm,cor 1005 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 1006 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 1007 iommus = <&apps_smmu 0x05e0 0x0>;
2975 1008
2976 clocks = <&aoss_qmp>; 1009 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 1010 clock-names = "apb_pclk";
2978 arm,scatter-gather; 1011 arm,scatter-gather;
2979 1012
2980 in-ports { 1013 in-ports {
2981 port { 1014 port {
2982 etr_i 1015 etr_in: endpoint {
2983 1016 remote-endpoint = <&replicator_out0>;
2984 }; 1017 };
2985 }; 1018 };
2986 }; 1019 };
2987 }; 1020 };
2988 1021
2989 replicator@604a000 { 1022 replicator@604a000 {
2990 compatible = "arm,cor 1023 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 1024 reg = <0 0x0604a000 0 0x1000>;
2992 1025
2993 clocks = <&aoss_qmp>; 1026 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 1027 clock-names = "apb_pclk";
2995 1028
2996 out-ports { 1029 out-ports {
2997 #address-cell 1030 #address-cells = <1>;
2998 #size-cells = 1031 #size-cells = <0>;
2999 1032
3000 port@1 { 1033 port@1 {
3001 reg = 1034 reg = <1>;
3002 repli 1035 replicator1_out: endpoint {
3003 1036 remote-endpoint = <&swao_funnel_in>;
3004 }; 1037 };
3005 }; 1038 };
3006 }; 1039 };
3007 1040
3008 in-ports { 1041 in-ports {
>> 1042 #address-cells = <1>;
>> 1043 #size-cells = <0>;
3009 1044
3010 port { !! 1045 port@1 {
>> 1046 reg = <1>;
3011 repli 1047 replicator1_in: endpoint {
3012 1048 remote-endpoint = <&replicator_out1>;
3013 }; 1049 };
3014 }; 1050 };
3015 }; 1051 };
3016 }; 1052 };
3017 1053
3018 funnel@6b08000 { 1054 funnel@6b08000 {
3019 compatible = "arm,cor 1055 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 1056 reg = <0 0x06b08000 0 0x1000>;
3021 1057
3022 clocks = <&aoss_qmp>; 1058 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 1059 clock-names = "apb_pclk";
3024 1060
3025 out-ports { 1061 out-ports {
3026 port { 1062 port {
3027 swao_ 1063 swao_funnel_out: endpoint {
3028 1064 remote-endpoint = <&swao_etf_in>;
3029 }; 1065 };
3030 }; 1066 };
3031 }; 1067 };
3032 1068
3033 in-ports { 1069 in-ports {
3034 #address-cell 1070 #address-cells = <1>;
3035 #size-cells = 1071 #size-cells = <0>;
3036 1072
3037 port@6 { 1073 port@6 {
3038 reg = 1074 reg = <6>;
3039 swao_ 1075 swao_funnel_in: endpoint {
3040 1076 remote-endpoint = <&replicator1_out>;
3041 }; 1077 };
3042 }; 1078 };
3043 }; 1079 };
3044 }; 1080 };
3045 1081
3046 etf@6b09000 { 1082 etf@6b09000 {
3047 compatible = "arm,cor 1083 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 1084 reg = <0 0x06b09000 0 0x1000>;
3049 1085
3050 clocks = <&aoss_qmp>; 1086 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 1087 clock-names = "apb_pclk";
3052 1088
3053 out-ports { 1089 out-ports {
3054 port { 1090 port {
3055 swao_ 1091 swao_etf_out: endpoint {
3056 1092 remote-endpoint = <&swao_replicator_in>;
3057 }; 1093 };
3058 }; 1094 };
3059 }; 1095 };
3060 1096
3061 in-ports { 1097 in-ports {
3062 port { 1098 port {
3063 swao_ 1099 swao_etf_in: endpoint {
3064 1100 remote-endpoint = <&swao_funnel_out>;
3065 }; 1101 };
3066 }; 1102 };
3067 }; 1103 };
3068 }; 1104 };
3069 1105
3070 replicator@6b0a000 { 1106 replicator@6b0a000 {
3071 compatible = "arm,cor 1107 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 1108 reg = <0 0x06b0a000 0 0x1000>;
3073 1109
3074 clocks = <&aoss_qmp>; 1110 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 1111 clock-names = "apb_pclk";
3076 qcom,replicator-loses 1112 qcom,replicator-loses-context;
3077 1113
3078 out-ports { 1114 out-ports {
3079 port { 1115 port {
3080 swao_ 1116 swao_replicator_out: endpoint {
3081 1117 remote-endpoint = <&funnel1_in4>;
3082 }; 1118 };
3083 }; 1119 };
3084 }; 1120 };
3085 1121
3086 in-ports { 1122 in-ports {
3087 port { 1123 port {
3088 swao_ 1124 swao_replicator_in: endpoint {
3089 1125 remote-endpoint = <&swao_etf_out>;
3090 }; 1126 };
3091 }; 1127 };
3092 }; 1128 };
3093 }; 1129 };
3094 1130
3095 etm@7040000 { 1131 etm@7040000 {
3096 compatible = "arm,cor 1132 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 1133 reg = <0 0x07040000 0 0x1000>;
3098 1134
3099 cpu = <&CPU0>; 1135 cpu = <&CPU0>;
3100 1136
3101 clocks = <&aoss_qmp>; 1137 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 1138 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 1139 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 1140 qcom,skip-power-up;
3105 1141
3106 out-ports { 1142 out-ports {
3107 port { 1143 port {
3108 etm0_ 1144 etm0_out: endpoint {
3109 1145 remote-endpoint = <&apss_funnel_in0>;
3110 }; 1146 };
3111 }; 1147 };
3112 }; 1148 };
3113 }; 1149 };
3114 1150
3115 etm@7140000 { 1151 etm@7140000 {
3116 compatible = "arm,cor 1152 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 1153 reg = <0 0x07140000 0 0x1000>;
3118 1154
3119 cpu = <&CPU1>; 1155 cpu = <&CPU1>;
3120 1156
3121 clocks = <&aoss_qmp>; 1157 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 1158 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 1159 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 1160 qcom,skip-power-up;
3125 1161
3126 out-ports { 1162 out-ports {
3127 port { 1163 port {
3128 etm1_ 1164 etm1_out: endpoint {
3129 1165 remote-endpoint = <&apss_funnel_in1>;
3130 }; 1166 };
3131 }; 1167 };
3132 }; 1168 };
3133 }; 1169 };
3134 1170
3135 etm@7240000 { 1171 etm@7240000 {
3136 compatible = "arm,cor 1172 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 1173 reg = <0 0x07240000 0 0x1000>;
3138 1174
3139 cpu = <&CPU2>; 1175 cpu = <&CPU2>;
3140 1176
3141 clocks = <&aoss_qmp>; 1177 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 1178 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 1179 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 1180 qcom,skip-power-up;
3145 1181
3146 out-ports { 1182 out-ports {
3147 port { 1183 port {
3148 etm2_ 1184 etm2_out: endpoint {
3149 1185 remote-endpoint = <&apss_funnel_in2>;
3150 }; 1186 };
3151 }; 1187 };
3152 }; 1188 };
3153 }; 1189 };
3154 1190
3155 etm@7340000 { 1191 etm@7340000 {
3156 compatible = "arm,cor 1192 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 1193 reg = <0 0x07340000 0 0x1000>;
3158 1194
3159 cpu = <&CPU3>; 1195 cpu = <&CPU3>;
3160 1196
3161 clocks = <&aoss_qmp>; 1197 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 1198 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 1199 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 1200 qcom,skip-power-up;
3165 1201
3166 out-ports { 1202 out-ports {
3167 port { 1203 port {
3168 etm3_ 1204 etm3_out: endpoint {
3169 1205 remote-endpoint = <&apss_funnel_in3>;
3170 }; 1206 };
3171 }; 1207 };
3172 }; 1208 };
3173 }; 1209 };
3174 1210
3175 etm@7440000 { 1211 etm@7440000 {
3176 compatible = "arm,cor 1212 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 1213 reg = <0 0x07440000 0 0x1000>;
3178 1214
3179 cpu = <&CPU4>; 1215 cpu = <&CPU4>;
3180 1216
3181 clocks = <&aoss_qmp>; 1217 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 1218 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 1219 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 1220 qcom,skip-power-up;
3185 1221
3186 out-ports { 1222 out-ports {
3187 port { 1223 port {
3188 etm4_ 1224 etm4_out: endpoint {
3189 1225 remote-endpoint = <&apss_funnel_in4>;
3190 }; 1226 };
3191 }; 1227 };
3192 }; 1228 };
3193 }; 1229 };
3194 1230
3195 etm@7540000 { 1231 etm@7540000 {
3196 compatible = "arm,cor 1232 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 1233 reg = <0 0x07540000 0 0x1000>;
3198 1234
3199 cpu = <&CPU5>; 1235 cpu = <&CPU5>;
3200 1236
3201 clocks = <&aoss_qmp>; 1237 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 1238 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 1239 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 1240 qcom,skip-power-up;
3205 1241
3206 out-ports { 1242 out-ports {
3207 port { 1243 port {
3208 etm5_ 1244 etm5_out: endpoint {
3209 1245 remote-endpoint = <&apss_funnel_in5>;
3210 }; 1246 };
3211 }; 1247 };
3212 }; 1248 };
3213 }; 1249 };
3214 1250
3215 etm@7640000 { 1251 etm@7640000 {
3216 compatible = "arm,cor 1252 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 1253 reg = <0 0x07640000 0 0x1000>;
3218 1254
3219 cpu = <&CPU6>; 1255 cpu = <&CPU6>;
3220 1256
3221 clocks = <&aoss_qmp>; 1257 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 1258 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 1259 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 1260 qcom,skip-power-up;
3225 1261
3226 out-ports { 1262 out-ports {
3227 port { 1263 port {
3228 etm6_ 1264 etm6_out: endpoint {
3229 1265 remote-endpoint = <&apss_funnel_in6>;
3230 }; 1266 };
3231 }; 1267 };
3232 }; 1268 };
3233 }; 1269 };
3234 1270
3235 etm@7740000 { 1271 etm@7740000 {
3236 compatible = "arm,cor 1272 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 1273 reg = <0 0x07740000 0 0x1000>;
3238 1274
3239 cpu = <&CPU7>; 1275 cpu = <&CPU7>;
3240 1276
3241 clocks = <&aoss_qmp>; 1277 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 1278 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 1279 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 1280 qcom,skip-power-up;
3245 1281
3246 out-ports { 1282 out-ports {
3247 port { 1283 port {
3248 etm7_ 1284 etm7_out: endpoint {
3249 1285 remote-endpoint = <&apss_funnel_in7>;
3250 }; 1286 };
3251 }; 1287 };
3252 }; 1288 };
3253 }; 1289 };
3254 1290
3255 funnel@7800000 { /* APSS Funn 1291 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 1292 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 1293 reg = <0 0x07800000 0 0x1000>;
3258 1294
3259 clocks = <&aoss_qmp>; 1295 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 1296 clock-names = "apb_pclk";
3261 1297
3262 out-ports { 1298 out-ports {
3263 port { 1299 port {
3264 apss_ 1300 apss_funnel_out: endpoint {
3265 1301 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 1302 };
3267 }; 1303 };
3268 }; 1304 };
3269 1305
3270 in-ports { 1306 in-ports {
3271 #address-cell 1307 #address-cells = <1>;
3272 #size-cells = 1308 #size-cells = <0>;
3273 1309
3274 port@0 { 1310 port@0 {
3275 reg = 1311 reg = <0>;
3276 apss_ 1312 apss_funnel_in0: endpoint {
3277 1313 remote-endpoint = <&etm0_out>;
3278 }; 1314 };
3279 }; 1315 };
3280 1316
3281 port@1 { 1317 port@1 {
3282 reg = 1318 reg = <1>;
3283 apss_ 1319 apss_funnel_in1: endpoint {
3284 1320 remote-endpoint = <&etm1_out>;
3285 }; 1321 };
3286 }; 1322 };
3287 1323
3288 port@2 { 1324 port@2 {
3289 reg = 1325 reg = <2>;
3290 apss_ 1326 apss_funnel_in2: endpoint {
3291 1327 remote-endpoint = <&etm2_out>;
3292 }; 1328 };
3293 }; 1329 };
3294 1330
3295 port@3 { 1331 port@3 {
3296 reg = 1332 reg = <3>;
3297 apss_ 1333 apss_funnel_in3: endpoint {
3298 1334 remote-endpoint = <&etm3_out>;
3299 }; 1335 };
3300 }; 1336 };
3301 1337
3302 port@4 { 1338 port@4 {
3303 reg = 1339 reg = <4>;
3304 apss_ 1340 apss_funnel_in4: endpoint {
3305 1341 remote-endpoint = <&etm4_out>;
3306 }; 1342 };
3307 }; 1343 };
3308 1344
3309 port@5 { 1345 port@5 {
3310 reg = 1346 reg = <5>;
3311 apss_ 1347 apss_funnel_in5: endpoint {
3312 1348 remote-endpoint = <&etm5_out>;
3313 }; 1349 };
3314 }; 1350 };
3315 1351
3316 port@6 { 1352 port@6 {
3317 reg = 1353 reg = <6>;
3318 apss_ 1354 apss_funnel_in6: endpoint {
3319 1355 remote-endpoint = <&etm6_out>;
3320 }; 1356 };
3321 }; 1357 };
3322 1358
3323 port@7 { 1359 port@7 {
3324 reg = 1360 reg = <7>;
3325 apss_ 1361 apss_funnel_in7: endpoint {
3326 1362 remote-endpoint = <&etm7_out>;
3327 }; 1363 };
3328 }; 1364 };
3329 }; 1365 };
3330 }; 1366 };
3331 1367
3332 funnel@7810000 { 1368 funnel@7810000 {
3333 compatible = "arm,cor 1369 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 1370 reg = <0 0x07810000 0 0x1000>;
3335 1371
3336 clocks = <&aoss_qmp>; 1372 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 1373 clock-names = "apb_pclk";
3338 1374
3339 out-ports { 1375 out-ports {
3340 port { 1376 port {
3341 apss_ 1377 apss_merge_funnel_out: endpoint {
3342 1378 remote-endpoint = <&funnel2_in2>;
3343 }; 1379 };
3344 }; 1380 };
3345 }; 1381 };
3346 1382
3347 in-ports { 1383 in-ports {
3348 port { 1384 port {
3349 apss_ 1385 apss_merge_funnel_in: endpoint {
3350 1386 remote-endpoint = <&apss_funnel_out>;
3351 }; 1387 };
3352 }; 1388 };
3353 }; 1389 };
3354 }; 1390 };
3355 1391
3356 remoteproc_cdsp: remoteproc@8 1392 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 1393 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 1394 reg = <0x0 0x08300000 0x0 0x4040>;
3359 1395
3360 interrupts-extended = 1396 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 1397 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 1398 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 1399 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 1400 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 1401 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 1402 "handover", "stop-ack";
3367 1403
3368 clocks = <&rpmhcc RPM 1404 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 1405 clock-names = "xo";
3370 1406
3371 power-domains = <&rpm !! 1407 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 1408 <&rpmhpd 7>;
>> 1409 power-domain-names = "load_state", "cx";
3372 1410
3373 memory-region = <&cds 1411 memory-region = <&cdsp_mem>;
3374 1412
3375 qcom,qmp = <&aoss_qmp <<
3376 <<
3377 qcom,smem-states = <& 1413 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 1414 qcom,smem-state-names = "stop";
3379 1415
3380 status = "disabled"; 1416 status = "disabled";
3381 1417
3382 glink-edge { 1418 glink-edge {
3383 interrupts = 1419 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 1420 label = "cdsp";
3385 qcom,remote-p 1421 qcom,remote-pid = <5>;
3386 mboxes = <&ap 1422 mboxes = <&apss_shared 4>;
3387 <<
3388 fastrpc { <<
3389 compa <<
3390 qcom, <<
3391 label <<
3392 qcom, <<
3393 #addr <<
3394 #size <<
3395 <<
3396 compu <<
3397 <<
3398 <<
3399 <<
3400 }; <<
3401 <<
3402 compu <<
3403 <<
3404 <<
3405 <<
3406 }; <<
3407 <<
3408 compu <<
3409 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 compu <<
3415 <<
3416 <<
3417 <<
3418 }; <<
3419 <<
3420 compu <<
3421 <<
3422 <<
3423 <<
3424 }; <<
3425 <<
3426 compu <<
3427 <<
3428 <<
3429 <<
3430 }; <<
3431 <<
3432 compu <<
3433 <<
3434 <<
3435 <<
3436 }; <<
3437 <<
3438 compu <<
3439 <<
3440 <<
3441 <<
3442 }; <<
3443 <<
3444 /* no <<
3445 }; <<
3446 }; 1423 };
3447 }; 1424 };
3448 1425
3449 usb_1_hsphy: phy@88e2000 { 1426 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 1427 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 1428 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 1429 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 1430 status = "disabled";
3454 #phy-cells = <0>; 1431 #phy-cells = <0>;
3455 1432
3456 clocks = <&rpmhcc RPM 1433 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 1434 clock-names = "ref";
3458 1435
3459 resets = <&gcc GCC_QU 1436 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 1437 };
3461 1438
3462 usb_2_hsphy: phy@88e3000 { 1439 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 1440 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 1441 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 1442 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 1443 status = "disabled";
3467 #phy-cells = <0>; 1444 #phy-cells = <0>;
3468 1445
3469 clocks = <&rpmhcc RPM 1446 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 1447 clock-names = "ref";
3471 1448
3472 resets = <&gcc GCC_QU 1449 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 1450 };
3474 1451
3475 usb_1_qmpphy: phy@88e8000 { !! 1452 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 1453 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 1454 reg = <0 0x088e9000 0 0x18c>,
>> 1455 <0 0x088e8000 0 0x10>;
>> 1456 reg-names = "reg-base", "dp_com";
>> 1457 status = "disabled";
>> 1458 #clock-cells = <1>;
>> 1459 #address-cells = <2>;
>> 1460 #size-cells = <2>;
>> 1461 ranges;
3478 1462
3479 clocks = <&gcc GCC_US 1463 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 1464 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 1465 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 1466 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 1467 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 1468
3488 resets = <&gcc GCC_US 1469 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 1470 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 1471 reset-names = "phy", "common";
3491 1472
3492 #clock-cells = <1>; !! 1473 usb_1_ssphy: lanes@88e9200 {
3493 #phy-cells = <1>; !! 1474 reg = <0 0x088e9200 0 0x200>,
3494 !! 1475 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 1476 <0 0x088e9c00 0 0x218>,
3496 !! 1477 <0 0x088e9600 0 0x200>,
3497 ports { !! 1478 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 1479 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 1480 #phy-cells = <0>;
3500 !! 1481 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3501 port@0 { !! 1482 clock-names = "pipe0";
3502 reg = !! 1483 clock-output-names = "usb3_phy_pipe_clk_src";
3503 <<
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; <<
3524 }; <<
3525 <<
3526 usb_2_qmpphy: phy@88eb000 { <<
3527 compatible = "qcom,sm <<
3528 reg = <0 0x088eb000 0 <<
3529 <<
3530 clocks = <&gcc GCC_US <<
3531 <&gcc GCC_US <<
3532 <&gcc GCC_US <<
3533 <&gcc GCC_US <<
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 <<
3542 resets = <&gcc GCC_US <<
3543 <&gcc GCC_US <<
3544 reset-names = "phy", <<
3545 "phy_ph <<
3546 <<
3547 status = "disabled"; <<
3548 }; <<
3549 <<
3550 sdhc_2: mmc@8804000 { <<
3551 compatible = "qcom,sm <<
3552 reg = <0 0x08804000 0 <<
3553 <<
3554 interrupts = <GIC_SPI <<
3555 <GIC_SPI <<
3556 interrupt-names = "hc <<
3557 <<
3558 clocks = <&gcc GCC_SD <<
3559 <&gcc GCC_SD <<
3560 <&rpmhcc RPM <<
3561 clock-names = "iface" <<
3562 iommus = <&apps_smmu <<
3563 qcom,dll-config = <0x <<
3564 qcom,ddr-config = <0x <<
3565 power-domains = <&rpm <<
3566 operating-points-v2 = <<
3567 <<
3568 status = "disabled"; <<
3569 <<
3570 sdhc2_opp_table: opp- <<
3571 compatible = <<
3572 <<
3573 opp-19200000 <<
3574 opp-h <<
3575 requi <<
3576 }; <<
3577 <<
3578 opp-50000000 <<
3579 opp-h <<
3580 requi <<
3581 }; <<
3582 <<
3583 opp-100000000 <<
3584 opp-h <<
3585 requi <<
3586 }; <<
3587 <<
3588 opp-202000000 <<
3589 opp-h <<
3590 requi <<
3591 }; <<
3592 }; 1484 };
3593 }; 1485 };
3594 1486
3595 dc_noc: interconnect@9160000 1487 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 1488 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 1489 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 1490 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 1491 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 1492 };
3601 1493
3602 gem_noc: interconnect@9680000 1494 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 1495 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 1496 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 1497 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 1498 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 1499 };
3608 1500
>> 1501 usb_2_qmpphy: phy@88eb000 {
>> 1502 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
>> 1503 reg = <0 0x088eb000 0 0x200>;
>> 1504 status = "disabled";
>> 1505 #clock-cells = <1>;
>> 1506 #address-cells = <2>;
>> 1507 #size-cells = <2>;
>> 1508 ranges;
>> 1509
>> 1510 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 1511 <&rpmhcc RPMH_CXO_CLK>,
>> 1512 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
>> 1513 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
>> 1514 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
>> 1515
>> 1516 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
>> 1517 <&gcc GCC_USB3_PHY_SEC_BCR>;
>> 1518 reset-names = "phy", "common";
>> 1519
>> 1520 usb_2_ssphy: lane@88eb200 {
>> 1521 reg = <0 0x088eb200 0 0x200>,
>> 1522 <0 0x088eb400 0 0x200>,
>> 1523 <0 0x088eb800 0 0x800>,
>> 1524 <0 0x088eb600 0 0x200>;
>> 1525 #phy-cells = <0>;
>> 1526 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 1527 clock-names = "pipe0";
>> 1528 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 1529 };
>> 1530 };
>> 1531
3609 usb_1: usb@a6f8800 { 1532 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 1533 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 1534 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 1535 status = "disabled";
3613 #address-cells = <2>; 1536 #address-cells = <2>;
3614 #size-cells = <2>; 1537 #size-cells = <2>;
3615 ranges; 1538 ranges;
3616 dma-ranges; 1539 dma-ranges;
3617 1540
3618 clocks = <&gcc GCC_CF 1541 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 1542 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 1543 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US <<
3622 <&gcc GCC_US 1544 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 1545 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3623 <&gcc GCC_US 1546 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no !! 1547 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3625 "core", !! 1548 "sleep", "xo";
3626 "iface" <<
3627 "sleep" <<
3628 "mock_u <<
3629 "xo"; <<
3630 1549
3631 assigned-clocks = <&g 1550 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 1551 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 1552 assigned-clock-rates = <19200000>, <200000000>;
3634 1553
3635 interrupts-extended = !! 1554 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 1555 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 1556 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 1557 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 1558 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 1559 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 1560
3646 power-domains = <&gcc 1561 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 1562
3648 resets = <&gcc GCC_US 1563 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 1564
3650 interconnects = <&agg !! 1565 usb_1_dwc3: dwc3@a600000 {
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 <<
3655 compatible = 1566 compatible = "snps,dwc3";
3656 reg = <0 0x0a 1567 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 1568 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 1569 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 1570 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 1571 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 1572 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 1573 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 1574 };
3684 }; 1575 };
3685 1576
3686 usb_2: usb@a8f8800 { 1577 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 1578 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 1579 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 1580 status = "disabled";
3690 #address-cells = <2>; 1581 #address-cells = <2>;
3691 #size-cells = <2>; 1582 #size-cells = <2>;
3692 ranges; 1583 ranges;
3693 dma-ranges; 1584 dma-ranges;
3694 1585
3695 clocks = <&gcc GCC_CF 1586 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 1587 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 1588 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US <<
3699 <&gcc GCC_US 1589 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 1590 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3700 <&gcc GCC_US 1591 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no !! 1592 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3702 "core", !! 1593 "sleep", "xo";
3703 "iface" <<
3704 "sleep" <<
3705 "mock_u <<
3706 "xo"; <<
3707 1594
3708 assigned-clocks = <&g 1595 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 1596 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 1597 assigned-clock-rates = <19200000>, <200000000>;
3711 1598
3712 interrupts-extended = !! 1599 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 1600 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 1601 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 1602 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 1603 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 1604 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 1605
3723 power-domains = <&gcc 1606 power-domains = <&gcc USB30_SEC_GDSC>;
3724 1607
3725 resets = <&gcc GCC_US 1608 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 1609
3727 interconnects = <&agg !! 1610 usb_2_dwc3: dwc3@a800000 {
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 <<
3732 compatible = 1611 compatible = "snps,dwc3";
3733 reg = <0 0x0a 1612 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 1613 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 1614 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 1615 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 1616 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 1617 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 1618 phy-names = "usb2-phy", "usb3-phy";
3740 }; 1619 };
3741 }; 1620 };
3742 1621
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 1622 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 1623 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 1624 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 1625 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 1626 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 1627 };
3762 1628
3763 camcc: clock-controller@ad000 !! 1629 aoss_qmp: power-controller@c300000 {
3764 compatible = "qcom,sm !! 1630 compatible = "qcom,sm8150-aoss-qmp";
3765 reg = <0 0x0ad00000 0 !! 1631 reg = <0x0 0x0c300000 0x0 0x100000>;
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 <<
4150 compatible = "qcom,sm <<
4151 reg = <0 0x0b220000 0 <<
4152 qcom,pdc-ranges = <0 <<
4153 <12 <<
4154 #interrupt-cells = <2 <<
4155 interrupt-parent = <& <<
4156 interrupt-controller; <<
4157 }; <<
4158 <<
4159 aoss_qmp: power-management@c3 <<
4160 compatible = "qcom,sm <<
4161 reg = <0x0 0x0c300000 <<
4162 interrupts = <GIC_SPI 1632 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 1633 mboxes = <&apss_shared 0>;
4164 1634
4165 #clock-cells = <0>; 1635 #clock-cells = <0>;
4166 }; !! 1636 #power-domain-cells = <1>;
4167 <<
4168 sram@c3f0000 { <<
4169 compatible = "qcom,rp <<
4170 reg = <0 0x0c3f0000 0 <<
4171 }; 1637 };
4172 1638
4173 tsens0: thermal-sensor@c26300 1639 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 1640 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 1641 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 1642 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 1643 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 1644 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 1645 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 1646 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 1647 #thermal-sensor-cells = <1>;
4182 }; 1648 };
4183 1649
4184 tsens1: thermal-sensor@c26500 1650 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 1651 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 1652 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 1653 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 1654 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 1655 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 1656 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 1657 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 1658 #thermal-sensor-cells = <1>;
4193 }; 1659 };
4194 1660
4195 spmi_bus: spmi@c440000 { 1661 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 1662 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 1663 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 1664 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 1665 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 1666 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 1667 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 1668 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 1669 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 1670 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 1671 qcom,ee = <0>;
4206 qcom,channel = <0>; 1672 qcom,channel = <0>;
4207 #address-cells = <2>; 1673 #address-cells = <2>;
4208 #size-cells = <0>; 1674 #size-cells = <0>;
4209 interrupt-controller; 1675 interrupt-controller;
4210 #interrupt-cells = <4 1676 #interrupt-cells = <4>;
>> 1677 cell-index = <0>;
4211 }; 1678 };
4212 1679
4213 apps_smmu: iommu@15000000 { 1680 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 1681 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 1682 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 1683 #iommu-cells = <2>;
4217 #global-interrupts = 1684 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 1685 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 1686 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 1687 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 1688 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 1689 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 1690 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 1691 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 1692 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 1693 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 1694 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 1695 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 1696 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 1697 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 1698 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 1699 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 1700 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 1701 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 1702 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 1703 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 1704 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 1705 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 1706 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 1707 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 1708 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 1709 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 1710 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 1711 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 1712 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 1713 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 1714 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 1715 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 1716 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 1717 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 1718 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 1719 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 1720 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 1721 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 1722 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 1723 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 1724 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 1725 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 1726 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 1727 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 1728 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 1729 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 1730 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 1731 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 1732 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 1733 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 1734 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 1735 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 1736 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 1737 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 1738 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 1739 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 1740 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 1741 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 1742 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 1743 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 1744 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 1745 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 1746 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 1747 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 1748 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 1749 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 1750 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 1751 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 1752 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 1753 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 1754 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 1755 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 1756 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 1757 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 1758 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 1759 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 1760 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 1761 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 1762 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 1763 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 1764 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 1765 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 1766 };
4300 1767
4301 remoteproc_adsp: remoteproc@1 1768 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 1769 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 1770 reg = <0x0 0x17300000 0x0 0x4040>;
4304 1771
4305 interrupts-extended = 1772 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 1773 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 1774 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 1775 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 1776 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 1777 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 1778 "handover", "stop-ack";
4312 1779
4313 clocks = <&rpmhcc RPM 1780 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 1781 clock-names = "xo";
4315 1782
4316 power-domains = <&rpm !! 1783 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
>> 1784 <&rpmhpd 7>;
>> 1785 power-domain-names = "load_state", "cx";
4317 1786
4318 memory-region = <&ads 1787 memory-region = <&adsp_mem>;
4319 1788
4320 qcom,qmp = <&aoss_qmp <<
4321 <<
4322 qcom,smem-states = <& 1789 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 1790 qcom,smem-state-names = "stop";
4324 1791
4325 status = "disabled"; 1792 status = "disabled";
4326 1793
4327 glink-edge { 1794 glink-edge {
4328 interrupts = 1795 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 1796 label = "lpass";
4330 qcom,remote-p 1797 qcom,remote-pid = <2>;
4331 mboxes = <&ap 1798 mboxes = <&apss_shared 8>;
4332 <<
4333 fastrpc { <<
4334 compa <<
4335 qcom, <<
4336 label <<
4337 qcom, <<
4338 #addr <<
4339 #size <<
4340 <<
4341 compu <<
4342 <<
4343 <<
4344 <<
4345 }; <<
4346 <<
4347 compu <<
4348 <<
4349 <<
4350 <<
4351 }; <<
4352 <<
4353 compu <<
4354 <<
4355 <<
4356 <<
4357 }; <<
4358 }; <<
4359 }; 1799 };
4360 }; 1800 };
4361 1801
4362 intc: interrupt-controller@17 1802 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 1803 compatible = "arm,gic-v3";
4364 interrupt-controller; 1804 interrupt-controller;
4365 #interrupt-cells = <3 1805 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 1806 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 1807 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 1808 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 1809 };
4370 1810
4371 apss_shared: mailbox@17c00000 1811 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 1812 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 1813 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 1814 #mbox-cells = <1>;
4376 }; 1815 };
4377 1816
4378 watchdog@17c10000 { 1817 watchdog@17c10000 {
4379 compatible = "qcom,ap 1818 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 1819 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 1820 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI <<
4383 }; 1821 };
4384 1822
4385 timer@17c20000 { 1823 timer@17c20000 {
4386 #address-cells = <1>; !! 1824 #address-cells = <2>;
4387 #size-cells = <1>; !! 1825 #size-cells = <2>;
4388 ranges = <0 0 0 0x200 !! 1826 ranges;
4389 compatible = "arm,arm 1827 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 1828 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 1829 clock-frequency = <19200000>;
4392 1830
4393 frame@17c21000 { !! 1831 frame@17c21000{
4394 frame-number 1832 frame-number = <0>;
4395 interrupts = 1833 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 1834 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 !! 1835 reg = <0x0 0x17c21000 0x0 0x1000>,
4398 <0x17c2 !! 1836 <0x0 0x17c22000 0x0 0x1000>;
4399 }; 1837 };
4400 1838
4401 frame@17c23000 { 1839 frame@17c23000 {
4402 frame-number 1840 frame-number = <1>;
4403 interrupts = 1841 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 !! 1842 reg = <0x0 0x17c23000 0x0 0x1000>;
4405 status = "dis 1843 status = "disabled";
4406 }; 1844 };
4407 1845
4408 frame@17c25000 { 1846 frame@17c25000 {
4409 frame-number 1847 frame-number = <2>;
4410 interrupts = 1848 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 !! 1849 reg = <0x0 0x17c25000 0x0 0x1000>;
4412 status = "dis 1850 status = "disabled";
4413 }; 1851 };
4414 1852
4415 frame@17c27000 { 1853 frame@17c27000 {
4416 frame-number 1854 frame-number = <3>;
4417 interrupts = 1855 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 !! 1856 reg = <0x0 0x17c26000 0x0 0x1000>;
4419 status = "dis 1857 status = "disabled";
4420 }; 1858 };
4421 1859
4422 frame@17c29000 { 1860 frame@17c29000 {
4423 frame-number 1861 frame-number = <4>;
4424 interrupts = 1862 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 !! 1863 reg = <0x0 0x17c29000 0x0 0x1000>;
4426 status = "dis 1864 status = "disabled";
4427 }; 1865 };
4428 1866
4429 frame@17c2b000 { 1867 frame@17c2b000 {
4430 frame-number 1868 frame-number = <5>;
4431 interrupts = 1869 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 !! 1870 reg = <0x0 0x17c2b000 0x0 0x1000>;
4433 status = "dis 1871 status = "disabled";
4434 }; 1872 };
4435 1873
4436 frame@17c2d000 { 1874 frame@17c2d000 {
4437 frame-number 1875 frame-number = <6>;
4438 interrupts = 1876 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 !! 1877 reg = <0x0 0x17c2d000 0x0 0x1000>;
4440 status = "dis 1878 status = "disabled";
4441 }; 1879 };
4442 }; 1880 };
4443 1881
4444 apps_rsc: rsc@18200000 { 1882 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 1883 label = "apps_rsc";
4446 compatible = "qcom,rp 1884 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 1885 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 1886 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 1887 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 1888 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 1889 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 1890 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 1891 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 1892 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 1893 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 1894 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL !! 1895 <SLEEP_TCS 1>,
4458 <WA !! 1896 <WAKE_TCS 1>,
4459 <CO !! 1897 <CONTROL_TCS 0>;
4460 power-domains = <&CLU <<
4461 1898
4462 rpmhcc: clock-control 1899 rpmhcc: clock-controller {
4463 compatible = 1900 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 1901 #clock-cells = <1>;
4465 clock-names = 1902 clock-names = "xo";
4466 clocks = <&xo 1903 clocks = <&xo_board>;
4467 }; 1904 };
4468 1905
4469 rpmhpd: power-control 1906 rpmhpd: power-controller {
4470 compatible = 1907 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 1908 #power-domain-cells = <1>;
4472 operating-poi 1909 operating-points-v2 = <&rpmhpd_opp_table>;
4473 1910
4474 rpmhpd_opp_ta 1911 rpmhpd_opp_table: opp-table {
4475 compa 1912 compatible = "operating-points-v2";
4476 1913
4477 rpmhp 1914 rpmhpd_opp_ret: opp1 {
4478 1915 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 1916 };
4480 1917
4481 rpmhp 1918 rpmhpd_opp_min_svs: opp2 {
4482 1919 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 1920 };
4484 1921
4485 rpmhp 1922 rpmhpd_opp_low_svs: opp3 {
4486 1923 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 1924 };
4488 1925
4489 rpmhp 1926 rpmhpd_opp_svs: opp4 {
4490 1927 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 1928 };
4492 1929
4493 rpmhp 1930 rpmhpd_opp_svs_l1: opp5 {
4494 1931 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 1932 };
4496 1933
4497 rpmhp 1934 rpmhpd_opp_svs_l2: opp6 {
4498 1935 opp-level = <224>;
4499 }; 1936 };
4500 1937
4501 rpmhp 1938 rpmhpd_opp_nom: opp7 {
4502 1939 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 1940 };
4504 1941
4505 rpmhp 1942 rpmhpd_opp_nom_l1: opp8 {
4506 1943 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 1944 };
4508 1945
4509 rpmhp 1946 rpmhpd_opp_nom_l2: opp9 {
4510 1947 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 1948 };
4512 1949
4513 rpmhp 1950 rpmhpd_opp_turbo: opp10 {
4514 1951 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 1952 };
4516 1953
4517 rpmhp 1954 rpmhpd_opp_turbo_l1: opp11 {
4518 1955 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 1956 };
4520 }; 1957 };
4521 }; 1958 };
4522 1959
4523 apps_bcm_voter: bcm-v !! 1960 apps_bcm_voter: bcm_voter {
4524 compatible = 1961 compatible = "qcom,bcm-voter";
4525 }; 1962 };
4526 }; 1963 };
4527 1964
4528 osm_l3: interconnect@18321000 1965 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 1966 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 1967 reg = <0 0x18321000 0 0x1400>;
4531 1968
4532 clocks = <&rpmhcc RPM 1969 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 1970 clock-names = "xo", "alternate";
4534 1971
4535 #interconnect-cells = 1972 #interconnect-cells = <1>;
4536 }; 1973 };
4537 1974
4538 cpufreq_hw: cpufreq@18323000 1975 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 1976 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 1977 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 1978 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 1979 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 1980 "freq-domain2";
4544 1981
4545 clocks = <&rpmhcc RPM 1982 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 1983 clock-names = "xo", "alternate";
4547 1984
4548 #freq-domain-cells = 1985 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; <<
4551 <<
4552 lmh_cluster1: lmh@18350800 { <<
4553 compatible = "qcom,sm <<
4554 reg = <0 0x18350800 0 <<
4555 interrupts = <GIC_SPI <<
4556 cpus = <&CPU4>; <<
4557 qcom,lmh-temp-arm-mil <<
4558 qcom,lmh-temp-low-mil <<
4559 qcom,lmh-temp-high-mi <<
4560 interrupt-controller; <<
4561 #interrupt-cells = <1 <<
4562 }; <<
4563 <<
4564 lmh_cluster0: lmh@18358800 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x18358800 0 <<
4567 interrupts = <GIC_SPI <<
4568 cpus = <&CPU0>; <<
4569 qcom,lmh-temp-arm-mil <<
4570 qcom,lmh-temp-low-mil <<
4571 qcom,lmh-temp-high-mi <<
4572 interrupt-controller; <<
4573 #interrupt-cells = <1 <<
4574 }; 1986 };
4575 1987
4576 wifi: wifi@18800000 { 1988 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 1989 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 1990 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 1991 reg-names = "membase";
4580 memory-region = <&wla 1992 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 1993 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 1994 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 1995 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 1996 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 1997 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 1998 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 1999 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 2000 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 2001 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 2002 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 2003 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 2004 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 2005 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 2006 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 2007 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 2008 status = "disabled";
4597 }; 2009 };
4598 }; 2010 };
4599 2011
4600 timer { 2012 timer {
4601 compatible = "arm,armv8-timer 2013 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 2014 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 2015 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 2016 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 2017 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 2018 };
4607 2019
4608 thermal-zones { 2020 thermal-zones {
4609 cpu0-thermal { 2021 cpu0-thermal {
4610 polling-delay-passive 2022 polling-delay-passive = <250>;
>> 2023 polling-delay = <1000>;
4611 2024
4612 thermal-sensors = <&t 2025 thermal-sensors = <&tsens0 1>;
4613 2026
4614 trips { 2027 trips {
4615 cpu0_alert0: 2028 cpu0_alert0: trip-point0 {
4616 tempe 2029 temperature = <90000>;
4617 hyste 2030 hysteresis = <2000>;
4618 type 2031 type = "passive";
4619 }; 2032 };
4620 2033
4621 cpu0_alert1: 2034 cpu0_alert1: trip-point1 {
4622 tempe 2035 temperature = <95000>;
4623 hyste 2036 hysteresis = <2000>;
4624 type 2037 type = "passive";
4625 }; 2038 };
4626 2039
4627 cpu0_crit: cp !! 2040 cpu0_crit: cpu_crit {
4628 tempe 2041 temperature = <110000>;
4629 hyste 2042 hysteresis = <1000>;
4630 type 2043 type = "critical";
4631 }; 2044 };
4632 }; 2045 };
4633 2046
4634 cooling-maps { 2047 cooling-maps {
4635 map0 { 2048 map0 {
4636 trip 2049 trip = <&cpu0_alert0>;
4637 cooli 2050 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 2051 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 2052 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 2053 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 2054 };
4642 map1 { 2055 map1 {
4643 trip 2056 trip = <&cpu0_alert1>;
4644 cooli 2057 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 2058 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 2059 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 2060 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 2061 };
4649 }; 2062 };
4650 }; 2063 };
4651 2064
4652 cpu1-thermal { 2065 cpu1-thermal {
4653 polling-delay-passive 2066 polling-delay-passive = <250>;
>> 2067 polling-delay = <1000>;
4654 2068
4655 thermal-sensors = <&t 2069 thermal-sensors = <&tsens0 2>;
4656 2070
4657 trips { 2071 trips {
4658 cpu1_alert0: 2072 cpu1_alert0: trip-point0 {
4659 tempe 2073 temperature = <90000>;
4660 hyste 2074 hysteresis = <2000>;
4661 type 2075 type = "passive";
4662 }; 2076 };
4663 2077
4664 cpu1_alert1: 2078 cpu1_alert1: trip-point1 {
4665 tempe 2079 temperature = <95000>;
4666 hyste 2080 hysteresis = <2000>;
4667 type 2081 type = "passive";
4668 }; 2082 };
4669 2083
4670 cpu1_crit: cp !! 2084 cpu1_crit: cpu_crit {
4671 tempe 2085 temperature = <110000>;
4672 hyste 2086 hysteresis = <1000>;
4673 type 2087 type = "critical";
4674 }; 2088 };
4675 }; 2089 };
4676 2090
4677 cooling-maps { 2091 cooling-maps {
4678 map0 { 2092 map0 {
4679 trip 2093 trip = <&cpu1_alert0>;
4680 cooli 2094 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 2095 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 2096 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 2097 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 2098 };
4685 map1 { 2099 map1 {
4686 trip 2100 trip = <&cpu1_alert1>;
4687 cooli 2101 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 2102 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 2103 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 2104 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 2105 };
4692 }; 2106 };
4693 }; 2107 };
4694 2108
4695 cpu2-thermal { 2109 cpu2-thermal {
4696 polling-delay-passive 2110 polling-delay-passive = <250>;
>> 2111 polling-delay = <1000>;
4697 2112
4698 thermal-sensors = <&t 2113 thermal-sensors = <&tsens0 3>;
4699 2114
4700 trips { 2115 trips {
4701 cpu2_alert0: 2116 cpu2_alert0: trip-point0 {
4702 tempe 2117 temperature = <90000>;
4703 hyste 2118 hysteresis = <2000>;
4704 type 2119 type = "passive";
4705 }; 2120 };
4706 2121
4707 cpu2_alert1: 2122 cpu2_alert1: trip-point1 {
4708 tempe 2123 temperature = <95000>;
4709 hyste 2124 hysteresis = <2000>;
4710 type 2125 type = "passive";
4711 }; 2126 };
4712 2127
4713 cpu2_crit: cp !! 2128 cpu2_crit: cpu_crit {
4714 tempe 2129 temperature = <110000>;
4715 hyste 2130 hysteresis = <1000>;
4716 type 2131 type = "critical";
4717 }; 2132 };
4718 }; 2133 };
4719 2134
4720 cooling-maps { 2135 cooling-maps {
4721 map0 { 2136 map0 {
4722 trip 2137 trip = <&cpu2_alert0>;
4723 cooli 2138 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 2139 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 2140 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 2141 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 2142 };
4728 map1 { 2143 map1 {
4729 trip 2144 trip = <&cpu2_alert1>;
4730 cooli 2145 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 2146 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 2147 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 2148 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 2149 };
4735 }; 2150 };
4736 }; 2151 };
4737 2152
4738 cpu3-thermal { 2153 cpu3-thermal {
4739 polling-delay-passive 2154 polling-delay-passive = <250>;
>> 2155 polling-delay = <1000>;
4740 2156
4741 thermal-sensors = <&t 2157 thermal-sensors = <&tsens0 4>;
4742 2158
4743 trips { 2159 trips {
4744 cpu3_alert0: 2160 cpu3_alert0: trip-point0 {
4745 tempe 2161 temperature = <90000>;
4746 hyste 2162 hysteresis = <2000>;
4747 type 2163 type = "passive";
4748 }; 2164 };
4749 2165
4750 cpu3_alert1: 2166 cpu3_alert1: trip-point1 {
4751 tempe 2167 temperature = <95000>;
4752 hyste 2168 hysteresis = <2000>;
4753 type 2169 type = "passive";
4754 }; 2170 };
4755 2171
4756 cpu3_crit: cp !! 2172 cpu3_crit: cpu_crit {
4757 tempe 2173 temperature = <110000>;
4758 hyste 2174 hysteresis = <1000>;
4759 type 2175 type = "critical";
4760 }; 2176 };
4761 }; 2177 };
4762 2178
4763 cooling-maps { 2179 cooling-maps {
4764 map0 { 2180 map0 {
4765 trip 2181 trip = <&cpu3_alert0>;
4766 cooli 2182 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 2183 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 2184 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 2185 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 2186 };
4771 map1 { 2187 map1 {
4772 trip 2188 trip = <&cpu3_alert1>;
4773 cooli 2189 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 2190 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 2191 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 2192 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 2193 };
4778 }; 2194 };
4779 }; 2195 };
4780 2196
4781 cpu4-top-thermal { 2197 cpu4-top-thermal {
4782 polling-delay-passive 2198 polling-delay-passive = <250>;
>> 2199 polling-delay = <1000>;
4783 2200
4784 thermal-sensors = <&t 2201 thermal-sensors = <&tsens0 7>;
4785 2202
4786 trips { 2203 trips {
4787 cpu4_top_aler 2204 cpu4_top_alert0: trip-point0 {
4788 tempe 2205 temperature = <90000>;
4789 hyste 2206 hysteresis = <2000>;
4790 type 2207 type = "passive";
4791 }; 2208 };
4792 2209
4793 cpu4_top_aler 2210 cpu4_top_alert1: trip-point1 {
4794 tempe 2211 temperature = <95000>;
4795 hyste 2212 hysteresis = <2000>;
4796 type 2213 type = "passive";
4797 }; 2214 };
4798 2215
4799 cpu4_top_crit !! 2216 cpu4_top_crit: cpu_crit {
4800 tempe 2217 temperature = <110000>;
4801 hyste 2218 hysteresis = <1000>;
4802 type 2219 type = "critical";
4803 }; 2220 };
4804 }; 2221 };
4805 2222
4806 cooling-maps { 2223 cooling-maps {
4807 map0 { 2224 map0 {
4808 trip 2225 trip = <&cpu4_top_alert0>;
4809 cooli 2226 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 2227 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 2228 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 2229 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 2230 };
4814 map1 { 2231 map1 {
4815 trip 2232 trip = <&cpu4_top_alert1>;
4816 cooli 2233 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 2234 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 2235 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 2236 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 2237 };
4821 }; 2238 };
4822 }; 2239 };
4823 2240
4824 cpu5-top-thermal { 2241 cpu5-top-thermal {
4825 polling-delay-passive 2242 polling-delay-passive = <250>;
>> 2243 polling-delay = <1000>;
4826 2244
4827 thermal-sensors = <&t 2245 thermal-sensors = <&tsens0 8>;
4828 2246
4829 trips { 2247 trips {
4830 cpu5_top_aler 2248 cpu5_top_alert0: trip-point0 {
4831 tempe 2249 temperature = <90000>;
4832 hyste 2250 hysteresis = <2000>;
4833 type 2251 type = "passive";
4834 }; 2252 };
4835 2253
4836 cpu5_top_aler 2254 cpu5_top_alert1: trip-point1 {
4837 tempe 2255 temperature = <95000>;
4838 hyste 2256 hysteresis = <2000>;
4839 type 2257 type = "passive";
4840 }; 2258 };
4841 2259
4842 cpu5_top_crit !! 2260 cpu5_top_crit: cpu_crit {
4843 tempe 2261 temperature = <110000>;
4844 hyste 2262 hysteresis = <1000>;
4845 type 2263 type = "critical";
4846 }; 2264 };
4847 }; 2265 };
4848 2266
4849 cooling-maps { 2267 cooling-maps {
4850 map0 { 2268 map0 {
4851 trip 2269 trip = <&cpu5_top_alert0>;
4852 cooli 2270 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 2271 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 2272 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 2273 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 2274 };
4857 map1 { 2275 map1 {
4858 trip 2276 trip = <&cpu5_top_alert1>;
4859 cooli 2277 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 2278 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 2279 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 2280 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 2281 };
4864 }; 2282 };
4865 }; 2283 };
4866 2284
4867 cpu6-top-thermal { 2285 cpu6-top-thermal {
4868 polling-delay-passive 2286 polling-delay-passive = <250>;
>> 2287 polling-delay = <1000>;
4869 2288
4870 thermal-sensors = <&t 2289 thermal-sensors = <&tsens0 9>;
4871 2290
4872 trips { 2291 trips {
4873 cpu6_top_aler 2292 cpu6_top_alert0: trip-point0 {
4874 tempe 2293 temperature = <90000>;
4875 hyste 2294 hysteresis = <2000>;
4876 type 2295 type = "passive";
4877 }; 2296 };
4878 2297
4879 cpu6_top_aler 2298 cpu6_top_alert1: trip-point1 {
4880 tempe 2299 temperature = <95000>;
4881 hyste 2300 hysteresis = <2000>;
4882 type 2301 type = "passive";
4883 }; 2302 };
4884 2303
4885 cpu6_top_crit !! 2304 cpu6_top_crit: cpu_crit {
4886 tempe 2305 temperature = <110000>;
4887 hyste 2306 hysteresis = <1000>;
4888 type 2307 type = "critical";
4889 }; 2308 };
4890 }; 2309 };
4891 2310
4892 cooling-maps { 2311 cooling-maps {
4893 map0 { 2312 map0 {
4894 trip 2313 trip = <&cpu6_top_alert0>;
4895 cooli 2314 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 2315 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 2316 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 2317 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 2318 };
4900 map1 { 2319 map1 {
4901 trip 2320 trip = <&cpu6_top_alert1>;
4902 cooli 2321 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 2322 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 2323 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 2324 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 2325 };
4907 }; 2326 };
4908 }; 2327 };
4909 2328
4910 cpu7-top-thermal { 2329 cpu7-top-thermal {
4911 polling-delay-passive 2330 polling-delay-passive = <250>;
>> 2331 polling-delay = <1000>;
4912 2332
4913 thermal-sensors = <&t 2333 thermal-sensors = <&tsens0 10>;
4914 2334
4915 trips { 2335 trips {
4916 cpu7_top_aler 2336 cpu7_top_alert0: trip-point0 {
4917 tempe 2337 temperature = <90000>;
4918 hyste 2338 hysteresis = <2000>;
4919 type 2339 type = "passive";
4920 }; 2340 };
4921 2341
4922 cpu7_top_aler 2342 cpu7_top_alert1: trip-point1 {
4923 tempe 2343 temperature = <95000>;
4924 hyste 2344 hysteresis = <2000>;
4925 type 2345 type = "passive";
4926 }; 2346 };
4927 2347
4928 cpu7_top_crit !! 2348 cpu7_top_crit: cpu_crit {
4929 tempe 2349 temperature = <110000>;
4930 hyste 2350 hysteresis = <1000>;
4931 type 2351 type = "critical";
4932 }; 2352 };
4933 }; 2353 };
4934 2354
4935 cooling-maps { 2355 cooling-maps {
4936 map0 { 2356 map0 {
4937 trip 2357 trip = <&cpu7_top_alert0>;
4938 cooli 2358 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 2359 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 2360 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 2361 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 2362 };
4943 map1 { 2363 map1 {
4944 trip 2364 trip = <&cpu7_top_alert1>;
4945 cooli 2365 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 2366 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 2367 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 2368 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 2369 };
4950 }; 2370 };
4951 }; 2371 };
4952 2372
4953 cpu4-bottom-thermal { 2373 cpu4-bottom-thermal {
4954 polling-delay-passive 2374 polling-delay-passive = <250>;
>> 2375 polling-delay = <1000>;
4955 2376
4956 thermal-sensors = <&t 2377 thermal-sensors = <&tsens0 11>;
4957 2378
4958 trips { 2379 trips {
4959 cpu4_bottom_a 2380 cpu4_bottom_alert0: trip-point0 {
4960 tempe 2381 temperature = <90000>;
4961 hyste 2382 hysteresis = <2000>;
4962 type 2383 type = "passive";
4963 }; 2384 };
4964 2385
4965 cpu4_bottom_a 2386 cpu4_bottom_alert1: trip-point1 {
4966 tempe 2387 temperature = <95000>;
4967 hyste 2388 hysteresis = <2000>;
4968 type 2389 type = "passive";
4969 }; 2390 };
4970 2391
4971 cpu4_bottom_c !! 2392 cpu4_bottom_crit: cpu_crit {
4972 tempe 2393 temperature = <110000>;
4973 hyste 2394 hysteresis = <1000>;
4974 type 2395 type = "critical";
4975 }; 2396 };
4976 }; 2397 };
4977 2398
4978 cooling-maps { 2399 cooling-maps {
4979 map0 { 2400 map0 {
4980 trip 2401 trip = <&cpu4_bottom_alert0>;
4981 cooli 2402 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 2403 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 2404 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 2405 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 2406 };
4986 map1 { 2407 map1 {
4987 trip 2408 trip = <&cpu4_bottom_alert1>;
4988 cooli 2409 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 2410 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 2411 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 2412 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 2413 };
4993 }; 2414 };
4994 }; 2415 };
4995 2416
4996 cpu5-bottom-thermal { 2417 cpu5-bottom-thermal {
4997 polling-delay-passive 2418 polling-delay-passive = <250>;
>> 2419 polling-delay = <1000>;
4998 2420
4999 thermal-sensors = <&t 2421 thermal-sensors = <&tsens0 12>;
5000 2422
5001 trips { 2423 trips {
5002 cpu5_bottom_a 2424 cpu5_bottom_alert0: trip-point0 {
5003 tempe 2425 temperature = <90000>;
5004 hyste 2426 hysteresis = <2000>;
5005 type 2427 type = "passive";
5006 }; 2428 };
5007 2429
5008 cpu5_bottom_a 2430 cpu5_bottom_alert1: trip-point1 {
5009 tempe 2431 temperature = <95000>;
5010 hyste 2432 hysteresis = <2000>;
5011 type 2433 type = "passive";
5012 }; 2434 };
5013 2435
5014 cpu5_bottom_c !! 2436 cpu5_bottom_crit: cpu_crit {
5015 tempe 2437 temperature = <110000>;
5016 hyste 2438 hysteresis = <1000>;
5017 type 2439 type = "critical";
5018 }; 2440 };
5019 }; 2441 };
5020 2442
5021 cooling-maps { 2443 cooling-maps {
5022 map0 { 2444 map0 {
5023 trip 2445 trip = <&cpu5_bottom_alert0>;
5024 cooli 2446 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 2447 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 2448 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 2449 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 2450 };
5029 map1 { 2451 map1 {
5030 trip 2452 trip = <&cpu5_bottom_alert1>;
5031 cooli 2453 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 2454 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 2455 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 2456 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 2457 };
5036 }; 2458 };
5037 }; 2459 };
5038 2460
5039 cpu6-bottom-thermal { 2461 cpu6-bottom-thermal {
5040 polling-delay-passive 2462 polling-delay-passive = <250>;
>> 2463 polling-delay = <1000>;
5041 2464
5042 thermal-sensors = <&t 2465 thermal-sensors = <&tsens0 13>;
5043 2466
5044 trips { 2467 trips {
5045 cpu6_bottom_a 2468 cpu6_bottom_alert0: trip-point0 {
5046 tempe 2469 temperature = <90000>;
5047 hyste 2470 hysteresis = <2000>;
5048 type 2471 type = "passive";
5049 }; 2472 };
5050 2473
5051 cpu6_bottom_a 2474 cpu6_bottom_alert1: trip-point1 {
5052 tempe 2475 temperature = <95000>;
5053 hyste 2476 hysteresis = <2000>;
5054 type 2477 type = "passive";
5055 }; 2478 };
5056 2479
5057 cpu6_bottom_c !! 2480 cpu6_bottom_crit: cpu_crit {
5058 tempe 2481 temperature = <110000>;
5059 hyste 2482 hysteresis = <1000>;
5060 type 2483 type = "critical";
5061 }; 2484 };
5062 }; 2485 };
5063 2486
5064 cooling-maps { 2487 cooling-maps {
5065 map0 { 2488 map0 {
5066 trip 2489 trip = <&cpu6_bottom_alert0>;
5067 cooli 2490 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 2491 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 2492 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 2493 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 2494 };
5072 map1 { 2495 map1 {
5073 trip 2496 trip = <&cpu6_bottom_alert1>;
5074 cooli 2497 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 2498 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 2499 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 2500 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 2501 };
5079 }; 2502 };
5080 }; 2503 };
5081 2504
5082 cpu7-bottom-thermal { 2505 cpu7-bottom-thermal {
5083 polling-delay-passive 2506 polling-delay-passive = <250>;
>> 2507 polling-delay = <1000>;
5084 2508
5085 thermal-sensors = <&t 2509 thermal-sensors = <&tsens0 14>;
5086 2510
5087 trips { 2511 trips {
5088 cpu7_bottom_a 2512 cpu7_bottom_alert0: trip-point0 {
5089 tempe 2513 temperature = <90000>;
5090 hyste 2514 hysteresis = <2000>;
5091 type 2515 type = "passive";
5092 }; 2516 };
5093 2517
5094 cpu7_bottom_a 2518 cpu7_bottom_alert1: trip-point1 {
5095 tempe 2519 temperature = <95000>;
5096 hyste 2520 hysteresis = <2000>;
5097 type 2521 type = "passive";
5098 }; 2522 };
5099 2523
5100 cpu7_bottom_c !! 2524 cpu7_bottom_crit: cpu_crit {
5101 tempe 2525 temperature = <110000>;
5102 hyste 2526 hysteresis = <1000>;
5103 type 2527 type = "critical";
5104 }; 2528 };
5105 }; 2529 };
5106 2530
5107 cooling-maps { 2531 cooling-maps {
5108 map0 { 2532 map0 {
5109 trip 2533 trip = <&cpu7_bottom_alert0>;
5110 cooli 2534 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 2535 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 2536 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 2537 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 2538 };
5115 map1 { 2539 map1 {
5116 trip 2540 trip = <&cpu7_bottom_alert1>;
5117 cooli 2541 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 2542 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 2543 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 2544 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 2545 };
5122 }; 2546 };
5123 }; 2547 };
5124 2548
5125 aoss0-thermal { 2549 aoss0-thermal {
5126 polling-delay-passive 2550 polling-delay-passive = <250>;
>> 2551 polling-delay = <1000>;
5127 2552
5128 thermal-sensors = <&t 2553 thermal-sensors = <&tsens0 0>;
5129 2554
5130 trips { 2555 trips {
5131 aoss0_alert0: 2556 aoss0_alert0: trip-point0 {
5132 tempe 2557 temperature = <90000>;
5133 hyste 2558 hysteresis = <2000>;
5134 type 2559 type = "hot";
5135 }; 2560 };
5136 }; 2561 };
5137 }; 2562 };
5138 2563
5139 cluster0-thermal { 2564 cluster0-thermal {
5140 polling-delay-passive 2565 polling-delay-passive = <250>;
>> 2566 polling-delay = <1000>;
5141 2567
5142 thermal-sensors = <&t 2568 thermal-sensors = <&tsens0 5>;
5143 2569
5144 trips { 2570 trips {
5145 cluster0_aler 2571 cluster0_alert0: trip-point0 {
5146 tempe 2572 temperature = <90000>;
5147 hyste 2573 hysteresis = <2000>;
5148 type 2574 type = "hot";
5149 }; 2575 };
5150 cluster0_crit !! 2576 cluster0_crit: cluster0_crit {
5151 tempe 2577 temperature = <110000>;
5152 hyste 2578 hysteresis = <2000>;
5153 type 2579 type = "critical";
5154 }; 2580 };
5155 }; 2581 };
5156 }; 2582 };
5157 2583
5158 cluster1-thermal { 2584 cluster1-thermal {
5159 polling-delay-passive 2585 polling-delay-passive = <250>;
>> 2586 polling-delay = <1000>;
5160 2587
5161 thermal-sensors = <&t 2588 thermal-sensors = <&tsens0 6>;
5162 2589
5163 trips { 2590 trips {
5164 cluster1_aler 2591 cluster1_alert0: trip-point0 {
5165 tempe 2592 temperature = <90000>;
5166 hyste 2593 hysteresis = <2000>;
5167 type 2594 type = "hot";
5168 }; 2595 };
5169 cluster1_crit !! 2596 cluster1_crit: cluster1_crit {
5170 tempe 2597 temperature = <110000>;
5171 hyste 2598 hysteresis = <2000>;
5172 type 2599 type = "critical";
5173 }; 2600 };
5174 }; 2601 };
5175 }; 2602 };
5176 2603
5177 gpu-top-thermal { !! 2604 gpu-thermal-top {
5178 polling-delay-passive 2605 polling-delay-passive = <250>;
>> 2606 polling-delay = <1000>;
5179 2607
5180 thermal-sensors = <&t 2608 thermal-sensors = <&tsens0 15>;
5181 2609
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 2610 trips {
5190 gpu_top_alert !! 2611 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 2612 temperature = <90000>;
5198 hyste !! 2613 hysteresis = <2000>;
5199 type 2614 type = "hot";
5200 }; 2615 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 2616 };
5208 }; 2617 };
5209 2618
5210 aoss1-thermal { 2619 aoss1-thermal {
5211 polling-delay-passive 2620 polling-delay-passive = <250>;
>> 2621 polling-delay = <1000>;
5212 2622
5213 thermal-sensors = <&t 2623 thermal-sensors = <&tsens1 0>;
5214 2624
5215 trips { 2625 trips {
5216 aoss1_alert0: 2626 aoss1_alert0: trip-point0 {
5217 tempe 2627 temperature = <90000>;
5218 hyste 2628 hysteresis = <2000>;
5219 type 2629 type = "hot";
5220 }; 2630 };
5221 }; 2631 };
5222 }; 2632 };
5223 2633
5224 wlan-thermal { 2634 wlan-thermal {
5225 polling-delay-passive 2635 polling-delay-passive = <250>;
>> 2636 polling-delay = <1000>;
5226 2637
5227 thermal-sensors = <&t 2638 thermal-sensors = <&tsens1 1>;
5228 2639
5229 trips { 2640 trips {
5230 wlan_alert0: 2641 wlan_alert0: trip-point0 {
5231 tempe 2642 temperature = <90000>;
5232 hyste 2643 hysteresis = <2000>;
5233 type 2644 type = "hot";
5234 }; 2645 };
5235 }; 2646 };
5236 }; 2647 };
5237 2648
5238 video-thermal { 2649 video-thermal {
5239 polling-delay-passive 2650 polling-delay-passive = <250>;
>> 2651 polling-delay = <1000>;
5240 2652
5241 thermal-sensors = <&t 2653 thermal-sensors = <&tsens1 2>;
5242 2654
5243 trips { 2655 trips {
5244 video_alert0: 2656 video_alert0: trip-point0 {
5245 tempe 2657 temperature = <90000>;
5246 hyste 2658 hysteresis = <2000>;
5247 type 2659 type = "hot";
5248 }; 2660 };
5249 }; 2661 };
5250 }; 2662 };
5251 2663
5252 mem-thermal { 2664 mem-thermal {
5253 polling-delay-passive 2665 polling-delay-passive = <250>;
>> 2666 polling-delay = <1000>;
5254 2667
5255 thermal-sensors = <&t 2668 thermal-sensors = <&tsens1 3>;
5256 2669
5257 trips { 2670 trips {
5258 mem_alert0: t 2671 mem_alert0: trip-point0 {
5259 tempe 2672 temperature = <90000>;
5260 hyste 2673 hysteresis = <2000>;
5261 type 2674 type = "hot";
5262 }; 2675 };
5263 }; 2676 };
5264 }; 2677 };
5265 2678
5266 q6-hvx-thermal { 2679 q6-hvx-thermal {
5267 polling-delay-passive 2680 polling-delay-passive = <250>;
>> 2681 polling-delay = <1000>;
5268 2682
5269 thermal-sensors = <&t 2683 thermal-sensors = <&tsens1 4>;
5270 2684
5271 trips { 2685 trips {
5272 q6_hvx_alert0 2686 q6_hvx_alert0: trip-point0 {
5273 tempe 2687 temperature = <90000>;
5274 hyste 2688 hysteresis = <2000>;
5275 type 2689 type = "hot";
5276 }; 2690 };
5277 }; 2691 };
5278 }; 2692 };
5279 2693
5280 camera-thermal { 2694 camera-thermal {
5281 polling-delay-passive 2695 polling-delay-passive = <250>;
>> 2696 polling-delay = <1000>;
5282 2697
5283 thermal-sensors = <&t 2698 thermal-sensors = <&tsens1 5>;
5284 2699
5285 trips { 2700 trips {
5286 camera_alert0 2701 camera_alert0: trip-point0 {
5287 tempe 2702 temperature = <90000>;
5288 hyste 2703 hysteresis = <2000>;
5289 type 2704 type = "hot";
5290 }; 2705 };
5291 }; 2706 };
5292 }; 2707 };
5293 2708
5294 compute-thermal { 2709 compute-thermal {
5295 polling-delay-passive 2710 polling-delay-passive = <250>;
>> 2711 polling-delay = <1000>;
5296 2712
5297 thermal-sensors = <&t 2713 thermal-sensors = <&tsens1 6>;
5298 2714
5299 trips { 2715 trips {
5300 compute_alert 2716 compute_alert0: trip-point0 {
5301 tempe 2717 temperature = <90000>;
5302 hyste 2718 hysteresis = <2000>;
5303 type 2719 type = "hot";
5304 }; 2720 };
5305 }; 2721 };
5306 }; 2722 };
5307 2723
5308 modem-thermal { 2724 modem-thermal {
5309 polling-delay-passive 2725 polling-delay-passive = <250>;
>> 2726 polling-delay = <1000>;
5310 2727
5311 thermal-sensors = <&t 2728 thermal-sensors = <&tsens1 7>;
5312 2729
5313 trips { 2730 trips {
5314 modem_alert0: 2731 modem_alert0: trip-point0 {
5315 tempe 2732 temperature = <90000>;
5316 hyste 2733 hysteresis = <2000>;
5317 type 2734 type = "hot";
5318 }; 2735 };
5319 }; 2736 };
5320 }; 2737 };
5321 2738
5322 npu-thermal { 2739 npu-thermal {
5323 polling-delay-passive 2740 polling-delay-passive = <250>;
>> 2741 polling-delay = <1000>;
5324 2742
5325 thermal-sensors = <&t 2743 thermal-sensors = <&tsens1 8>;
5326 2744
5327 trips { 2745 trips {
5328 npu_alert0: t 2746 npu_alert0: trip-point0 {
5329 tempe 2747 temperature = <90000>;
5330 hyste 2748 hysteresis = <2000>;
5331 type 2749 type = "hot";
5332 }; 2750 };
5333 }; 2751 };
5334 }; 2752 };
5335 2753
5336 modem-vec-thermal { 2754 modem-vec-thermal {
5337 polling-delay-passive 2755 polling-delay-passive = <250>;
>> 2756 polling-delay = <1000>;
5338 2757
5339 thermal-sensors = <&t 2758 thermal-sensors = <&tsens1 9>;
5340 2759
5341 trips { 2760 trips {
5342 modem_vec_ale 2761 modem_vec_alert0: trip-point0 {
5343 tempe 2762 temperature = <90000>;
5344 hyste 2763 hysteresis = <2000>;
5345 type 2764 type = "hot";
5346 }; 2765 };
5347 }; 2766 };
5348 }; 2767 };
5349 2768
5350 modem-scl-thermal { 2769 modem-scl-thermal {
5351 polling-delay-passive 2770 polling-delay-passive = <250>;
>> 2771 polling-delay = <1000>;
5352 2772
5353 thermal-sensors = <&t 2773 thermal-sensors = <&tsens1 10>;
5354 2774
5355 trips { 2775 trips {
5356 modem_scl_ale 2776 modem_scl_alert0: trip-point0 {
5357 tempe 2777 temperature = <90000>;
5358 hyste 2778 hysteresis = <2000>;
5359 type 2779 type = "hot";
5360 }; 2780 };
5361 }; 2781 };
5362 }; 2782 };
5363 2783
5364 gpu-bottom-thermal { !! 2784 gpu-thermal-bottom {
5365 polling-delay-passive 2785 polling-delay-passive = <250>;
>> 2786 polling-delay = <1000>;
5366 2787
5367 thermal-sensors = <&t 2788 thermal-sensors = <&tsens1 11>;
5368 2789
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 2790 trips {
5377 gpu_bottom_al !! 2791 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 2792 temperature = <90000>;
5385 hyste !! 2793 hysteresis = <2000>;
5386 type 2794 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 2795 };
5394 }; 2796 };
5395 }; 2797 };
5396 }; 2798 };
5397 }; 2799 };
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