1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> <<
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 8 #include <dt-bindings/power/qcom-aoss-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 <<
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
22 16
23 / { 17 / {
24 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
25 19
26 #address-cells = <2>; 20 #address-cells = <2>;
27 #size-cells = <2>; 21 #size-cells = <2>;
28 22
29 chosen { }; 23 chosen { };
30 24
31 clocks { 25 clocks {
32 xo_board: xo-board { 26 xo_board: xo-board {
33 compatible = "fixed-cl 27 compatible = "fixed-clock";
34 #clock-cells = <0>; 28 #clock-cells = <0>;
35 clock-frequency = <384 29 clock-frequency = <38400000>;
36 clock-output-names = " 30 clock-output-names = "xo_board";
37 }; 31 };
38 32
39 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 34 compatible = "fixed-clock";
41 #clock-cells = <0>; 35 #clock-cells = <0>;
42 clock-frequency = <327 36 clock-frequency = <32764>;
43 clock-output-names = " 37 clock-output-names = "sleep_clk";
44 }; 38 };
45 }; 39 };
46 40
47 cpus { 41 cpus {
48 #address-cells = <2>; 42 #address-cells = <2>;
49 #size-cells = <0>; 43 #size-cells = <0>;
50 44
51 CPU0: cpu@0 { 45 CPU0: cpu@0 {
52 device_type = "cpu"; 46 device_type = "cpu";
53 compatible = "qcom,kry 47 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 48 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 49 enable-method = "psci";
57 capacity-dmips-mhz = < 50 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 51 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 53 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <<
62 interconnects = <&gem_ <<
63 <&osm_ <<
64 power-domains = <&CPU_ 54 power-domains = <&CPU_PD0>;
65 power-domain-names = " 55 power-domain-names = "psci";
66 #cooling-cells = <2>; 56 #cooling-cells = <2>;
67 L2_0: l2-cache { 57 L2_0: l2-cache {
68 compatible = " 58 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 59 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 60 L3_0: l3-cache {
73 compat !! 61 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 62 };
77 }; 63 };
78 }; 64 };
79 65
80 CPU1: cpu@100 { 66 CPU1: cpu@100 {
81 device_type = "cpu"; 67 device_type = "cpu";
82 compatible = "qcom,kry 68 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 69 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 70 enable-method = "psci";
86 capacity-dmips-mhz = < 71 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 72 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 73 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 74 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <<
91 interconnects = <&gem_ <<
92 <&osm_ <<
93 power-domains = <&CPU_ 75 power-domains = <&CPU_PD1>;
94 power-domain-names = " 76 power-domain-names = "psci";
95 #cooling-cells = <2>; 77 #cooling-cells = <2>;
96 L2_100: l2-cache { 78 L2_100: l2-cache {
97 compatible = " 79 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 80 next-level-cache = <&L3_0>;
101 }; 81 };
>> 82
102 }; 83 };
103 84
104 CPU2: cpu@200 { 85 CPU2: cpu@200 {
105 device_type = "cpu"; 86 device_type = "cpu";
106 compatible = "qcom,kry 87 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 88 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 89 enable-method = "psci";
110 capacity-dmips-mhz = < 90 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 91 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 92 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 93 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <<
115 interconnects = <&gem_ <<
116 <&osm_ <<
117 power-domains = <&CPU_ 94 power-domains = <&CPU_PD2>;
118 power-domain-names = " 95 power-domain-names = "psci";
119 #cooling-cells = <2>; 96 #cooling-cells = <2>;
120 L2_200: l2-cache { 97 L2_200: l2-cache {
121 compatible = " 98 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 99 next-level-cache = <&L3_0>;
125 }; 100 };
126 }; 101 };
127 102
128 CPU3: cpu@300 { 103 CPU3: cpu@300 {
129 device_type = "cpu"; 104 device_type = "cpu";
130 compatible = "qcom,kry 105 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 106 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 107 enable-method = "psci";
134 capacity-dmips-mhz = < 108 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 109 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 110 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 111 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <<
139 interconnects = <&gem_ <<
140 <&osm_ <<
141 power-domains = <&CPU_ 112 power-domains = <&CPU_PD3>;
142 power-domain-names = " 113 power-domain-names = "psci";
143 #cooling-cells = <2>; 114 #cooling-cells = <2>;
144 L2_300: l2-cache { 115 L2_300: l2-cache {
145 compatible = " 116 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 117 next-level-cache = <&L3_0>;
149 }; 118 };
150 }; 119 };
151 120
152 CPU4: cpu@400 { 121 CPU4: cpu@400 {
153 device_type = "cpu"; 122 device_type = "cpu";
154 compatible = "qcom,kry 123 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 124 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 125 enable-method = "psci";
158 capacity-dmips-mhz = < 126 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 127 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 128 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = <<
163 interconnects = <&gem_ <<
164 <&osm_ <<
165 power-domains = <&CPU_ 130 power-domains = <&CPU_PD4>;
166 power-domain-names = " 131 power-domain-names = "psci";
167 #cooling-cells = <2>; 132 #cooling-cells = <2>;
168 L2_400: l2-cache { 133 L2_400: l2-cache {
169 compatible = " 134 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 135 next-level-cache = <&L3_0>;
173 }; 136 };
174 }; 137 };
175 138
176 CPU5: cpu@500 { 139 CPU5: cpu@500 {
177 device_type = "cpu"; 140 device_type = "cpu";
178 compatible = "qcom,kry 141 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 142 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 143 enable-method = "psci";
182 capacity-dmips-mhz = < 144 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 145 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 146 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 147 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <<
187 interconnects = <&gem_ <<
188 <&osm_ <<
189 power-domains = <&CPU_ 148 power-domains = <&CPU_PD5>;
190 power-domain-names = " 149 power-domain-names = "psci";
191 #cooling-cells = <2>; 150 #cooling-cells = <2>;
192 L2_500: l2-cache { 151 L2_500: l2-cache {
193 compatible = " 152 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 153 next-level-cache = <&L3_0>;
197 }; 154 };
198 }; 155 };
199 156
200 CPU6: cpu@600 { 157 CPU6: cpu@600 {
201 device_type = "cpu"; 158 device_type = "cpu";
202 compatible = "qcom,kry 159 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 160 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 161 enable-method = "psci";
206 capacity-dmips-mhz = < 162 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 163 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 164 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 165 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = <<
211 interconnects = <&gem_ <<
212 <&osm_ <<
213 power-domains = <&CPU_ 166 power-domains = <&CPU_PD6>;
214 power-domain-names = " 167 power-domain-names = "psci";
215 #cooling-cells = <2>; 168 #cooling-cells = <2>;
216 L2_600: l2-cache { 169 L2_600: l2-cache {
217 compatible = " 170 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 171 next-level-cache = <&L3_0>;
221 }; 172 };
222 }; 173 };
223 174
224 CPU7: cpu@700 { 175 CPU7: cpu@700 {
225 device_type = "cpu"; 176 device_type = "cpu";
226 compatible = "qcom,kry 177 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 178 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 179 enable-method = "psci";
230 capacity-dmips-mhz = < 180 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 181 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 182 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 183 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = <<
235 interconnects = <&gem_ <<
236 <&osm_ <<
237 power-domains = <&CPU_ 184 power-domains = <&CPU_PD7>;
238 power-domain-names = " 185 power-domain-names = "psci";
239 #cooling-cells = <2>; 186 #cooling-cells = <2>;
240 L2_700: l2-cache { 187 L2_700: l2-cache {
241 compatible = " 188 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 189 next-level-cache = <&L3_0>;
245 }; 190 };
246 }; 191 };
247 192
248 cpu-map { 193 cpu-map {
249 cluster0 { 194 cluster0 {
250 core0 { 195 core0 {
251 cpu = 196 cpu = <&CPU0>;
252 }; 197 };
253 198
254 core1 { 199 core1 {
255 cpu = 200 cpu = <&CPU1>;
256 }; 201 };
257 202
258 core2 { 203 core2 {
259 cpu = 204 cpu = <&CPU2>;
260 }; 205 };
261 206
262 core3 { 207 core3 {
263 cpu = 208 cpu = <&CPU3>;
264 }; 209 };
265 210
266 core4 { 211 core4 {
267 cpu = 212 cpu = <&CPU4>;
268 }; 213 };
269 214
270 core5 { 215 core5 {
271 cpu = 216 cpu = <&CPU5>;
272 }; 217 };
273 218
274 core6 { 219 core6 {
275 cpu = 220 cpu = <&CPU6>;
276 }; 221 };
277 222
278 core7 { 223 core7 {
279 cpu = 224 cpu = <&CPU7>;
280 }; 225 };
281 }; 226 };
282 }; 227 };
283 228
284 idle-states { 229 idle-states {
285 entry-method = "psci"; 230 entry-method = "psci";
286 231
287 LITTLE_CPU_SLEEP_0: cp 232 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 233 compatible = "arm,idle-state";
289 idle-state-nam 234 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 235 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 236 entry-latency-us = <355>;
292 exit-latency-u 237 exit-latency-us = <909>;
293 min-residency- 238 min-residency-us = <3934>;
294 local-timer-st 239 local-timer-stop;
295 }; 240 };
296 241
297 BIG_CPU_SLEEP_0: cpu-s 242 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 243 compatible = "arm,idle-state";
299 idle-state-nam 244 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 245 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 246 entry-latency-us = <241>;
302 exit-latency-u 247 exit-latency-us = <1461>;
303 min-residency- 248 min-residency-us = <4488>;
304 local-timer-st 249 local-timer-stop;
305 }; 250 };
306 }; 251 };
307 252
308 domain-idle-states { 253 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 254 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 255 compatible = "domain-idle-state";
>> 256 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 257 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 258 entry-latency-us = <3263>;
313 exit-latency-u 259 exit-latency-us = <6562>;
314 min-residency- 260 min-residency-us = <9987>;
>> 261 local-timer-stop;
315 }; 262 };
316 }; 263 };
317 }; 264 };
318 265
319 cpu0_opp_table: opp-table-cpu0 { <<
320 compatible = "operating-points <<
321 opp-shared; <<
322 <<
323 cpu0_opp1: opp-300000000 { <<
324 opp-hz = /bits/ 64 <30 <<
325 opp-peak-kBps = <80000 <<
326 }; <<
327 <<
328 cpu0_opp2: opp-403200000 { <<
329 opp-hz = /bits/ 64 <40 <<
330 opp-peak-kBps = <80000 <<
331 }; <<
332 <<
333 cpu0_opp3: opp-499200000 { <<
334 opp-hz = /bits/ 64 <49 <<
335 opp-peak-kBps = <80000 <<
336 }; <<
337 <<
338 cpu0_opp4: opp-576000000 { <<
339 opp-hz = /bits/ 64 <57 <<
340 opp-peak-kBps = <80000 <<
341 }; <<
342 <<
343 cpu0_opp5: opp-672000000 { <<
344 opp-hz = /bits/ 64 <67 <<
345 opp-peak-kBps = <80000 <<
346 }; <<
347 <<
348 cpu0_opp6: opp-768000000 { <<
349 opp-hz = /bits/ 64 <76 <<
350 opp-peak-kBps = <18040 <<
351 }; <<
352 <<
353 cpu0_opp7: opp-844800000 { <<
354 opp-hz = /bits/ 64 <84 <<
355 opp-peak-kBps = <18040 <<
356 }; <<
357 <<
358 cpu0_opp8: opp-940800000 { <<
359 opp-hz = /bits/ 64 <94 <<
360 opp-peak-kBps = <18040 <<
361 }; <<
362 <<
363 cpu0_opp9: opp-1036800000 { <<
364 opp-hz = /bits/ 64 <10 <<
365 opp-peak-kBps = <18040 <<
366 }; <<
367 <<
368 cpu0_opp10: opp-1113600000 { <<
369 opp-hz = /bits/ 64 <11 <<
370 opp-peak-kBps = <21880 <<
371 }; <<
372 <<
373 cpu0_opp11: opp-1209600000 { <<
374 opp-hz = /bits/ 64 <12 <<
375 opp-peak-kBps = <21880 <<
376 }; <<
377 <<
378 cpu0_opp12: opp-1305600000 { <<
379 opp-hz = /bits/ 64 <13 <<
380 opp-peak-kBps = <30720 <<
381 }; <<
382 <<
383 cpu0_opp13: opp-1382400000 { <<
384 opp-hz = /bits/ 64 <13 <<
385 opp-peak-kBps = <30720 <<
386 }; <<
387 <<
388 cpu0_opp14: opp-1478400000 { <<
389 opp-hz = /bits/ 64 <14 <<
390 opp-peak-kBps = <30720 <<
391 }; <<
392 <<
393 cpu0_opp15: opp-1555200000 { <<
394 opp-hz = /bits/ 64 <15 <<
395 opp-peak-kBps = <30720 <<
396 }; <<
397 <<
398 cpu0_opp16: opp-1632000000 { <<
399 opp-hz = /bits/ 64 <16 <<
400 opp-peak-kBps = <30720 <<
401 }; <<
402 <<
403 cpu0_opp17: opp-1708800000 { <<
404 opp-hz = /bits/ 64 <17 <<
405 opp-peak-kBps = <30720 <<
406 }; <<
407 <<
408 cpu0_opp18: opp-1785600000 { <<
409 opp-hz = /bits/ 64 <17 <<
410 opp-peak-kBps = <30720 <<
411 }; <<
412 }; <<
413 <<
414 cpu4_opp_table: opp-table-cpu4 { <<
415 compatible = "operating-points <<
416 opp-shared; <<
417 <<
418 cpu4_opp1: opp-710400000 { <<
419 opp-hz = /bits/ 64 <71 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu4_opp2: opp-825600000 { <<
424 opp-hz = /bits/ 64 <82 <<
425 opp-peak-kBps = <21880 <<
426 }; <<
427 <<
428 cpu4_opp3: opp-940800000 { <<
429 opp-hz = /bits/ 64 <94 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu4_opp4: opp-1056000000 { <<
434 opp-hz = /bits/ 64 <10 <<
435 opp-peak-kBps = <30720 <<
436 }; <<
437 <<
438 cpu4_opp5: opp-1171200000 { <<
439 opp-hz = /bits/ 64 <11 <<
440 opp-peak-kBps = <30720 <<
441 }; <<
442 <<
443 cpu4_opp6: opp-1286400000 { <<
444 opp-hz = /bits/ 64 <12 <<
445 opp-peak-kBps = <40680 <<
446 }; <<
447 <<
448 cpu4_opp7: opp-1401600000 { <<
449 opp-hz = /bits/ 64 <14 <<
450 opp-peak-kBps = <40680 <<
451 }; <<
452 <<
453 cpu4_opp8: opp-1497600000 { <<
454 opp-hz = /bits/ 64 <14 <<
455 opp-peak-kBps = <40680 <<
456 }; <<
457 <<
458 cpu4_opp9: opp-1612800000 { <<
459 opp-hz = /bits/ 64 <16 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu4_opp10: opp-1708800000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 <<
468 cpu4_opp11: opp-1804800000 { <<
469 opp-hz = /bits/ 64 <18 <<
470 opp-peak-kBps = <62200 <<
471 }; <<
472 <<
473 cpu4_opp12: opp-1920000000 { <<
474 opp-hz = /bits/ 64 <19 <<
475 opp-peak-kBps = <62200 <<
476 }; <<
477 <<
478 cpu4_opp13: opp-2016000000 { <<
479 opp-hz = /bits/ 64 <20 <<
480 opp-peak-kBps = <72160 <<
481 }; <<
482 <<
483 cpu4_opp14: opp-2131200000 { <<
484 opp-hz = /bits/ 64 <21 <<
485 opp-peak-kBps = <83680 <<
486 }; <<
487 <<
488 cpu4_opp15: opp-2227200000 { <<
489 opp-hz = /bits/ 64 <22 <<
490 opp-peak-kBps = <83680 <<
491 }; <<
492 <<
493 cpu4_opp16: opp-2323200000 { <<
494 opp-hz = /bits/ 64 <23 <<
495 opp-peak-kBps = <83680 <<
496 }; <<
497 <<
498 cpu4_opp17: opp-2419200000 { <<
499 opp-hz = /bits/ 64 <24 <<
500 opp-peak-kBps = <83680 <<
501 }; <<
502 }; <<
503 <<
504 cpu7_opp_table: opp-table-cpu7 { <<
505 compatible = "operating-points <<
506 opp-shared; <<
507 <<
508 cpu7_opp1: opp-825600000 { <<
509 opp-hz = /bits/ 64 <82 <<
510 opp-peak-kBps = <21880 <<
511 }; <<
512 <<
513 cpu7_opp2: opp-940800000 { <<
514 opp-hz = /bits/ 64 <94 <<
515 opp-peak-kBps = <21880 <<
516 }; <<
517 <<
518 cpu7_opp3: opp-1056000000 { <<
519 opp-hz = /bits/ 64 <10 <<
520 opp-peak-kBps = <30720 <<
521 }; <<
522 <<
523 cpu7_opp4: opp-1171200000 { <<
524 opp-hz = /bits/ 64 <11 <<
525 opp-peak-kBps = <30720 <<
526 }; <<
527 <<
528 cpu7_opp5: opp-1286400000 { <<
529 opp-hz = /bits/ 64 <12 <<
530 opp-peak-kBps = <40680 <<
531 }; <<
532 <<
533 cpu7_opp6: opp-1401600000 { <<
534 opp-hz = /bits/ 64 <14 <<
535 opp-peak-kBps = <40680 <<
536 }; <<
537 <<
538 cpu7_opp7: opp-1497600000 { <<
539 opp-hz = /bits/ 64 <14 <<
540 opp-peak-kBps = <40680 <<
541 }; <<
542 <<
543 cpu7_opp8: opp-1612800000 { <<
544 opp-hz = /bits/ 64 <16 <<
545 opp-peak-kBps = <40680 <<
546 }; <<
547 <<
548 cpu7_opp9: opp-1708800000 { <<
549 opp-hz = /bits/ 64 <17 <<
550 opp-peak-kBps = <40680 <<
551 }; <<
552 <<
553 cpu7_opp10: opp-1804800000 { <<
554 opp-hz = /bits/ 64 <18 <<
555 opp-peak-kBps = <62200 <<
556 }; <<
557 <<
558 cpu7_opp11: opp-1920000000 { <<
559 opp-hz = /bits/ 64 <19 <<
560 opp-peak-kBps = <62200 <<
561 }; <<
562 <<
563 cpu7_opp12: opp-2016000000 { <<
564 opp-hz = /bits/ 64 <20 <<
565 opp-peak-kBps = <72160 <<
566 }; <<
567 <<
568 cpu7_opp13: opp-2131200000 { <<
569 opp-hz = /bits/ 64 <21 <<
570 opp-peak-kBps = <83680 <<
571 }; <<
572 <<
573 cpu7_opp14: opp-2227200000 { <<
574 opp-hz = /bits/ 64 <22 <<
575 opp-peak-kBps = <83680 <<
576 }; <<
577 <<
578 cpu7_opp15: opp-2323200000 { <<
579 opp-hz = /bits/ 64 <23 <<
580 opp-peak-kBps = <83680 <<
581 }; <<
582 <<
583 cpu7_opp16: opp-2419200000 { <<
584 opp-hz = /bits/ 64 <24 <<
585 opp-peak-kBps = <83680 <<
586 }; <<
587 <<
588 cpu7_opp17: opp-2534400000 { <<
589 opp-hz = /bits/ 64 <25 <<
590 opp-peak-kBps = <83680 <<
591 }; <<
592 <<
593 cpu7_opp18: opp-2649600000 { <<
594 opp-hz = /bits/ 64 <26 <<
595 opp-peak-kBps = <83680 <<
596 }; <<
597 <<
598 cpu7_opp19: opp-2745600000 { <<
599 opp-hz = /bits/ 64 <27 <<
600 opp-peak-kBps = <83680 <<
601 }; <<
602 <<
603 cpu7_opp20: opp-2841600000 { <<
604 opp-hz = /bits/ 64 <28 <<
605 opp-peak-kBps = <83680 <<
606 }; <<
607 }; <<
608 <<
609 firmware { 266 firmware {
610 scm: scm { 267 scm: scm {
611 compatible = "qcom,scm 268 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 269 #reset-cells = <1>;
613 }; 270 };
614 }; 271 };
615 272
>> 273 tcsr_mutex: hwlock {
>> 274 compatible = "qcom,tcsr-mutex";
>> 275 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 276 #hwlock-cells = <1>;
>> 277 };
>> 278
616 memory@80000000 { 279 memory@80000000 {
617 device_type = "memory"; 280 device_type = "memory";
618 /* We expect the bootloader to 281 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 282 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 283 };
621 284
622 pmu { 285 pmu {
623 compatible = "arm,armv8-pmuv3" 286 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 287 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 288 };
626 289
627 psci { 290 psci {
628 compatible = "arm,psci-1.0"; 291 compatible = "arm,psci-1.0";
629 method = "smc"; 292 method = "smc";
630 293
631 CPU_PD0: power-domain-cpu0 { !! 294 CPU_PD0: cpu0 {
632 #power-domain-cells = 295 #power-domain-cells = <0>;
633 power-domains = <&CLUS 296 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 298 };
636 299
637 CPU_PD1: power-domain-cpu1 { !! 300 CPU_PD1: cpu1 {
638 #power-domain-cells = 301 #power-domain-cells = <0>;
639 power-domains = <&CLUS 302 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 304 };
642 305
643 CPU_PD2: power-domain-cpu2 { !! 306 CPU_PD2: cpu2 {
644 #power-domain-cells = 307 #power-domain-cells = <0>;
645 power-domains = <&CLUS 308 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 310 };
648 311
649 CPU_PD3: power-domain-cpu3 { !! 312 CPU_PD3: cpu3 {
650 #power-domain-cells = 313 #power-domain-cells = <0>;
651 power-domains = <&CLUS 314 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 316 };
654 317
655 CPU_PD4: power-domain-cpu4 { !! 318 CPU_PD4: cpu4 {
656 #power-domain-cells = 319 #power-domain-cells = <0>;
657 power-domains = <&CLUS 320 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 322 };
660 323
661 CPU_PD5: power-domain-cpu5 { !! 324 CPU_PD5: cpu5 {
662 #power-domain-cells = 325 #power-domain-cells = <0>;
663 power-domains = <&CLUS 326 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 328 };
666 329
667 CPU_PD6: power-domain-cpu6 { !! 330 CPU_PD6: cpu6 {
668 #power-domain-cells = 331 #power-domain-cells = <0>;
669 power-domains = <&CLUS 332 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 333 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 334 };
672 335
673 CPU_PD7: power-domain-cpu7 { !! 336 CPU_PD7: cpu7 {
674 #power-domain-cells = 337 #power-domain-cells = <0>;
675 power-domains = <&CLUS 338 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 340 };
678 341
679 CLUSTER_PD: power-domain-cpu-c !! 342 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 343 #power-domain-cells = <0>;
681 domain-idle-states = < 344 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 345 };
683 }; 346 };
684 347
685 reserved-memory { 348 reserved-memory {
686 #address-cells = <2>; 349 #address-cells = <2>;
687 #size-cells = <2>; 350 #size-cells = <2>;
688 ranges; 351 ranges;
689 352
690 hyp_mem: memory@85700000 { 353 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 354 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 355 no-map;
693 }; 356 };
694 357
695 xbl_mem: memory@85d00000 { 358 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 359 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 360 no-map;
698 }; 361 };
699 362
700 aop_mem: memory@85f00000 { 363 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 364 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 365 no-map;
703 }; 366 };
704 367
705 aop_cmd_db: memory@85f20000 { 368 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 369 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 370 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 371 no-map;
709 }; 372 };
710 373
711 smem_mem: memory@86000000 { 374 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 375 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 376 no-map;
714 }; 377 };
715 378
716 tz_mem: memory@86200000 { 379 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 380 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 381 no-map;
719 }; 382 };
720 383
721 rmtfs_mem: memory@89b00000 { 384 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 385 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 386 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 387 no-map;
725 388
726 qcom,client-id = <1>; 389 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 390 qcom,vmid = <15>;
728 }; 391 };
729 392
730 camera_mem: memory@8b700000 { 393 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 394 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 395 no-map;
733 }; 396 };
734 397
735 wlan_mem: memory@8bc00000 { 398 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 399 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 400 no-map;
738 }; 401 };
739 402
740 npu_mem: memory@8bd80000 { 403 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 404 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 405 no-map;
743 }; 406 };
744 407
745 adsp_mem: memory@8be00000 { 408 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 409 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 410 no-map;
748 }; 411 };
749 412
750 mpss_mem: memory@8d800000 { 413 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 414 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 415 no-map;
753 }; 416 };
754 417
755 venus_mem: memory@96e00000 { 418 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 419 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 420 no-map;
758 }; 421 };
759 422
760 slpi_mem: memory@97300000 { 423 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 424 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 425 no-map;
763 }; 426 };
764 427
765 ipa_fw_mem: memory@98700000 { 428 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 429 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 430 no-map;
768 }; 431 };
769 432
770 ipa_gsi_mem: memory@98710000 { 433 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 434 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 435 no-map;
773 }; 436 };
774 437
775 gpu_mem: memory@98715000 { 438 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 439 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 440 no-map;
778 }; 441 };
779 442
780 spss_mem: memory@98800000 { 443 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 444 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 445 no-map;
783 }; 446 };
784 447
785 cdsp_mem: memory@98900000 { 448 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 449 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 450 no-map;
788 }; 451 };
789 452
790 qseecom_mem: memory@9e400000 { 453 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 454 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 455 no-map;
793 }; 456 };
794 }; 457 };
795 458
796 smem { 459 smem {
797 compatible = "qcom,smem"; 460 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 461 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 462 hwlocks = <&tcsr_mutex 3>;
800 }; 463 };
801 464
802 smp2p-cdsp { 465 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 466 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 467 qcom,smem = <94>, <432>;
805 468
806 interrupts = <GIC_SPI 576 IRQ_ 469 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 470
808 mboxes = <&apss_shared 6>; 471 mboxes = <&apss_shared 6>;
809 472
810 qcom,local-pid = <0>; 473 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 474 qcom,remote-pid = <5>;
812 475
813 cdsp_smp2p_out: master-kernel 476 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 477 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 478 #qcom,smem-state-cells = <1>;
816 }; 479 };
817 480
818 cdsp_smp2p_in: slave-kernel { 481 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 482 qcom,entry-name = "slave-kernel";
820 483
821 interrupt-controller; 484 interrupt-controller;
822 #interrupt-cells = <2> 485 #interrupt-cells = <2>;
823 }; 486 };
824 }; 487 };
825 488
826 smp2p-lpass { 489 smp2p-lpass {
827 compatible = "qcom,smp2p"; 490 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 491 qcom,smem = <443>, <429>;
829 492
830 interrupts = <GIC_SPI 158 IRQ_ 493 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 494
832 mboxes = <&apss_shared 10>; 495 mboxes = <&apss_shared 10>;
833 496
834 qcom,local-pid = <0>; 497 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 498 qcom,remote-pid = <2>;
836 499
837 adsp_smp2p_out: master-kernel 500 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 501 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 502 #qcom,smem-state-cells = <1>;
840 }; 503 };
841 504
842 adsp_smp2p_in: slave-kernel { 505 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 506 qcom,entry-name = "slave-kernel";
844 507
845 interrupt-controller; 508 interrupt-controller;
846 #interrupt-cells = <2> 509 #interrupt-cells = <2>;
847 }; 510 };
848 }; 511 };
849 512
850 smp2p-mpss { 513 smp2p-mpss {
851 compatible = "qcom,smp2p"; 514 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 515 qcom,smem = <435>, <428>;
853 516
854 interrupts = <GIC_SPI 451 IRQ_ 517 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 518
856 mboxes = <&apss_shared 14>; 519 mboxes = <&apss_shared 14>;
857 520
858 qcom,local-pid = <0>; 521 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 522 qcom,remote-pid = <1>;
860 523
861 modem_smp2p_out: master-kernel 524 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 525 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 526 #qcom,smem-state-cells = <1>;
864 }; 527 };
865 528
866 modem_smp2p_in: slave-kernel { 529 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 530 qcom,entry-name = "slave-kernel";
868 531
869 interrupt-controller; 532 interrupt-controller;
870 #interrupt-cells = <2> 533 #interrupt-cells = <2>;
871 }; 534 };
872 }; 535 };
873 536
874 smp2p-slpi { 537 smp2p-slpi {
875 compatible = "qcom,smp2p"; 538 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 539 qcom,smem = <481>, <430>;
877 540
878 interrupts = <GIC_SPI 172 IRQ_ 541 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 542
880 mboxes = <&apss_shared 26>; 543 mboxes = <&apss_shared 26>;
881 544
882 qcom,local-pid = <0>; 545 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 546 qcom,remote-pid = <3>;
884 547
885 slpi_smp2p_out: master-kernel 548 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 549 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 550 #qcom,smem-state-cells = <1>;
888 }; 551 };
889 552
890 slpi_smp2p_in: slave-kernel { 553 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 554 qcom,entry-name = "slave-kernel";
892 555
893 interrupt-controller; 556 interrupt-controller;
894 #interrupt-cells = <2> 557 #interrupt-cells = <2>;
895 }; 558 };
896 }; 559 };
897 560
898 soc: soc@0 { 561 soc: soc@0 {
899 #address-cells = <2>; 562 #address-cells = <2>;
900 #size-cells = <2>; 563 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 564 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 565 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 566 compatible = "simple-bus";
904 567
905 gcc: clock-controller@100000 { 568 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 569 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 570 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 571 #clock-cells = <1>;
909 #reset-cells = <1>; 572 #reset-cells = <1>;
910 #power-domain-cells = 573 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 574 clock-names = "bi_tcxo",
912 "sleep_c 575 "sleep_clk";
913 clocks = <&rpmhcc RPMH 576 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 577 <&sleep_clk>;
915 }; 578 };
916 579
917 gpi_dma0: dma-controller@80000 <<
918 compatible = "qcom,sm8 <<
919 reg = <0 0x00800000 0 <<
920 interrupts = <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 dma-channels = <13>; <<
934 dma-channel-mask = <0x <<
935 iommus = <&apps_smmu 0 <<
936 #dma-cells = <3>; <<
937 status = "disabled"; <<
938 }; <<
939 <<
940 ethernet: ethernet@20000 { <<
941 compatible = "qcom,sm8 <<
942 reg = <0x0 0x00020000 <<
943 <0x0 0x00036000 <<
944 reg-names = "stmmaceth <<
945 clock-names = "stmmace <<
946 clocks = <&gcc GCC_EMA <<
947 <&gcc GCC_EMAC <<
948 <&gcc GCC_EMAC <<
949 <&gcc GCC_EMAC <<
950 interrupts = <GIC_SPI <<
951 <GIC_SPI <<
952 interrupt-names = "mac <<
953 <<
954 power-domains = <&gcc <<
955 resets = <&gcc GCC_EMA <<
956 <<
957 iommus = <&apps_smmu 0 <<
958 <<
959 snps,tso; <<
960 rx-fifo-depth = <4096> <<
961 tx-fifo-depth = <4096> <<
962 <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 <<
978 qupv3_id_0: geniqup@8c0000 { <<
979 compatible = "qcom,gen <<
980 reg = <0x0 0x008c0000 <<
981 clock-names = "m-ahb", <<
982 clocks = <&gcc GCC_QUP <<
983 <&gcc GCC_QUP <<
984 iommus = <&apps_smmu 0 <<
985 #address-cells = <2>; <<
986 #size-cells = <2>; <<
987 ranges; <<
988 status = "disabled"; <<
989 <<
990 i2c0: i2c@880000 { <<
991 compatible = " <<
992 reg = <0 0x008 <<
993 clock-names = <<
994 clocks = <&gcc <<
995 dmas = <&gpi_d <<
996 <&gpi_d <<
997 dma-names = "t <<
998 pinctrl-names <<
999 pinctrl-0 = <& <<
1000 interrupts = <<
1001 #address-cell <<
1002 #size-cells = <<
1003 status = "dis <<
1004 }; <<
1005 <<
1006 spi0: spi@880000 { <<
1007 compatible = <<
1008 reg = <0 0x00 <<
1009 reg-names = " <<
1010 clock-names = <<
1011 clocks = <&gc <<
1012 dmas = <&gpi_ <<
1013 <&gpi_ <<
1014 dma-names = " <<
1015 pinctrl-names <<
1016 pinctrl-0 = < <<
1017 interrupts = <<
1018 spi-max-frequ <<
1019 #address-cell <<
1020 #size-cells = <<
1021 status = "dis <<
1022 }; <<
1023 <<
1024 i2c1: i2c@884000 { <<
1025 compatible = <<
1026 reg = <0 0x00 <<
1027 clock-names = <<
1028 clocks = <&gc <<
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 pinctrl-names <<
1033 pinctrl-0 = < <<
1034 interrupts = <<
1035 #address-cell <<
1036 #size-cells = <<
1037 status = "dis <<
1038 }; <<
1039 <<
1040 spi1: spi@884000 { <<
1041 compatible = <<
1042 reg = <0 0x00 <<
1043 reg-names = " <<
1044 clock-names = <<
1045 clocks = <&gc <<
1046 dmas = <&gpi_ <<
1047 <&gpi_ <<
1048 dma-names = " <<
1049 pinctrl-names <<
1050 pinctrl-0 = < <<
1051 interrupts = <<
1052 spi-max-frequ <<
1053 #address-cell <<
1054 #size-cells = <<
1055 status = "dis <<
1056 }; <<
1057 <<
1058 i2c2: i2c@888000 { <<
1059 compatible = <<
1060 reg = <0 0x00 <<
1061 clock-names = <<
1062 clocks = <&gc <<
1063 dmas = <&gpi_ <<
1064 <&gpi_ <<
1065 dma-names = " <<
1066 pinctrl-names <<
1067 pinctrl-0 = < <<
1068 interrupts = <<
1069 #address-cell <<
1070 #size-cells = <<
1071 status = "dis <<
1072 }; <<
1073 <<
1074 spi2: spi@888000 { <<
1075 compatible = <<
1076 reg = <0 0x00 <<
1077 reg-names = " <<
1078 clock-names = <<
1079 clocks = <&gc <<
1080 dmas = <&gpi_ <<
1081 <&gpi_ <<
1082 dma-names = " <<
1083 pinctrl-names <<
1084 pinctrl-0 = < <<
1085 interrupts = <<
1086 spi-max-frequ <<
1087 #address-cell <<
1088 #size-cells = <<
1089 status = "dis <<
1090 }; <<
1091 <<
1092 i2c3: i2c@88c000 { <<
1093 compatible = <<
1094 reg = <0 0x00 <<
1095 clock-names = <<
1096 clocks = <&gc <<
1097 dmas = <&gpi_ <<
1098 <&gpi_ <<
1099 dma-names = " <<
1100 pinctrl-names <<
1101 pinctrl-0 = < <<
1102 interrupts = <<
1103 #address-cell <<
1104 #size-cells = <<
1105 status = "dis <<
1106 }; <<
1107 <<
1108 spi3: spi@88c000 { <<
1109 compatible = <<
1110 reg = <0 0x00 <<
1111 reg-names = " <<
1112 clock-names = <<
1113 clocks = <&gc <<
1114 dmas = <&gpi_ <<
1115 <&gpi_ <<
1116 dma-names = " <<
1117 pinctrl-names <<
1118 pinctrl-0 = < <<
1119 interrupts = <<
1120 spi-max-frequ <<
1121 #address-cell <<
1122 #size-cells = <<
1123 status = "dis <<
1124 }; <<
1125 <<
1126 i2c4: i2c@890000 { <<
1127 compatible = <<
1128 reg = <0 0x00 <<
1129 clock-names = <<
1130 clocks = <&gc <<
1131 dmas = <&gpi_ <<
1132 <&gpi_ <<
1133 dma-names = " <<
1134 pinctrl-names <<
1135 pinctrl-0 = < <<
1136 interrupts = <<
1137 #address-cell <<
1138 #size-cells = <<
1139 status = "dis <<
1140 }; <<
1141 <<
1142 spi4: spi@890000 { <<
1143 compatible = <<
1144 reg = <0 0x00 <<
1145 reg-names = " <<
1146 clock-names = <<
1147 clocks = <&gc <<
1148 dmas = <&gpi_ <<
1149 <&gpi_ <<
1150 dma-names = " <<
1151 pinctrl-names <<
1152 pinctrl-0 = < <<
1153 interrupts = <<
1154 spi-max-frequ <<
1155 #address-cell <<
1156 #size-cells = <<
1157 status = "dis <<
1158 }; <<
1159 <<
1160 i2c5: i2c@894000 { <<
1161 compatible = <<
1162 reg = <0 0x00 <<
1163 clock-names = <<
1164 clocks = <&gc <<
1165 dmas = <&gpi_ <<
1166 <&gpi_ <<
1167 dma-names = " <<
1168 pinctrl-names <<
1169 pinctrl-0 = < <<
1170 interrupts = <<
1171 #address-cell <<
1172 #size-cells = <<
1173 status = "dis <<
1174 }; <<
1175 <<
1176 spi5: spi@894000 { <<
1177 compatible = <<
1178 reg = <0 0x00 <<
1179 reg-names = " <<
1180 clock-names = <<
1181 clocks = <&gc <<
1182 dmas = <&gpi_ <<
1183 <&gpi_ <<
1184 dma-names = " <<
1185 pinctrl-names <<
1186 pinctrl-0 = < <<
1187 interrupts = <<
1188 spi-max-frequ <<
1189 #address-cell <<
1190 #size-cells = <<
1191 status = "dis <<
1192 }; <<
1193 <<
1194 i2c6: i2c@898000 { <<
1195 compatible = <<
1196 reg = <0 0x00 <<
1197 clock-names = <<
1198 clocks = <&gc <<
1199 dmas = <&gpi_ <<
1200 <&gpi_ <<
1201 dma-names = " <<
1202 pinctrl-names <<
1203 pinctrl-0 = < <<
1204 interrupts = <<
1205 #address-cell <<
1206 #size-cells = <<
1207 status = "dis <<
1208 }; <<
1209 <<
1210 spi6: spi@898000 { <<
1211 compatible = <<
1212 reg = <0 0x00 <<
1213 reg-names = " <<
1214 clock-names = <<
1215 clocks = <&gc <<
1216 dmas = <&gpi_ <<
1217 <&gpi_ <<
1218 dma-names = " <<
1219 pinctrl-names <<
1220 pinctrl-0 = < <<
1221 interrupts = <<
1222 spi-max-frequ <<
1223 #address-cell <<
1224 #size-cells = <<
1225 status = "dis <<
1226 }; <<
1227 <<
1228 i2c7: i2c@89c000 { <<
1229 compatible = <<
1230 reg = <0 0x00 <<
1231 clock-names = <<
1232 clocks = <&gc <<
1233 dmas = <&gpi_ <<
1234 <&gpi_ <<
1235 dma-names = " <<
1236 pinctrl-names <<
1237 pinctrl-0 = < <<
1238 interrupts = <<
1239 #address-cell <<
1240 #size-cells = <<
1241 status = "dis <<
1242 }; <<
1243 <<
1244 spi7: spi@89c000 { <<
1245 compatible = <<
1246 reg = <0 0x00 <<
1247 reg-names = " <<
1248 clock-names = <<
1249 clocks = <&gc <<
1250 dmas = <&gpi_ <<
1251 <&gpi_ <<
1252 dma-names = " <<
1253 pinctrl-names <<
1254 pinctrl-0 = < <<
1255 interrupts = <<
1256 spi-max-frequ <<
1257 #address-cell <<
1258 #size-cells = <<
1259 status = "dis <<
1260 }; <<
1261 }; <<
1262 <<
1263 gpi_dma1: dma-controller@a000 <<
1264 compatible = "qcom,sm <<
1265 reg = <0 0x00a00000 0 <<
1266 interrupts = <GIC_SPI <<
1267 <GIC_SPI <<
1268 <GIC_SPI <<
1269 <GIC_SPI <<
1270 <GIC_SPI <<
1271 <GIC_SPI <<
1272 <GIC_SPI <<
1273 <GIC_SPI <<
1274 <GIC_SPI <<
1275 <GIC_SPI <<
1276 <GIC_SPI <<
1277 <GIC_SPI <<
1278 <GIC_SPI <<
1279 dma-channels = <13>; <<
1280 dma-channel-mask = <0 <<
1281 iommus = <&apps_smmu <<
1282 #dma-cells = <3>; <<
1283 status = "disabled"; <<
1284 }; <<
1285 <<
1286 qupv3_id_1: geniqup@ac0000 { 580 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 581 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 582 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 583 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 584 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 585 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu <<
1293 #address-cells = <2>; 586 #address-cells = <2>;
1294 #size-cells = <2>; 587 #size-cells = <2>;
1295 ranges; 588 ranges;
1296 status = "disabled"; 589 status = "disabled";
1297 590
1298 i2c8: i2c@a80000 { <<
1299 compatible = <<
1300 reg = <0 0x00 <<
1301 clock-names = <<
1302 clocks = <&gc <<
1303 dmas = <&gpi_ <<
1304 <&gpi_ <<
1305 dma-names = " <<
1306 pinctrl-names <<
1307 pinctrl-0 = < <<
1308 interrupts = <<
1309 #address-cell <<
1310 #size-cells = <<
1311 status = "dis <<
1312 }; <<
1313 <<
1314 spi8: spi@a80000 { <<
1315 compatible = <<
1316 reg = <0 0x00 <<
1317 reg-names = " <<
1318 clock-names = <<
1319 clocks = <&gc <<
1320 dmas = <&gpi_ <<
1321 <&gpi_ <<
1322 dma-names = " <<
1323 pinctrl-names <<
1324 pinctrl-0 = < <<
1325 interrupts = <<
1326 spi-max-frequ <<
1327 #address-cell <<
1328 #size-cells = <<
1329 status = "dis <<
1330 }; <<
1331 <<
1332 i2c9: i2c@a84000 { <<
1333 compatible = <<
1334 reg = <0 0x00 <<
1335 clock-names = <<
1336 clocks = <&gc <<
1337 dmas = <&gpi_ <<
1338 <&gpi_ <<
1339 dma-names = " <<
1340 pinctrl-names <<
1341 pinctrl-0 = < <<
1342 interrupts = <<
1343 #address-cell <<
1344 #size-cells = <<
1345 status = "dis <<
1346 }; <<
1347 <<
1348 spi9: spi@a84000 { <<
1349 compatible = <<
1350 reg = <0 0x00 <<
1351 reg-names = " <<
1352 clock-names = <<
1353 clocks = <&gc <<
1354 dmas = <&gpi_ <<
1355 <&gpi_ <<
1356 dma-names = " <<
1357 pinctrl-names <<
1358 pinctrl-0 = < <<
1359 interrupts = <<
1360 spi-max-frequ <<
1361 #address-cell <<
1362 #size-cells = <<
1363 status = "dis <<
1364 }; <<
1365 <<
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { <<
1378 compatible = <<
1379 reg = <0 0x00 <<
1380 clock-names = <<
1381 clocks = <&gc <<
1382 dmas = <&gpi_ <<
1383 <&gpi_ <<
1384 dma-names = " <<
1385 pinctrl-names <<
1386 pinctrl-0 = < <<
1387 interrupts = <<
1388 #address-cell <<
1389 #size-cells = <<
1390 status = "dis <<
1391 }; <<
1392 <<
1393 spi10: spi@a88000 { <<
1394 compatible = <<
1395 reg = <0 0x00 <<
1396 reg-names = " <<
1397 clock-names = <<
1398 clocks = <&gc <<
1399 dmas = <&gpi_ <<
1400 <&gpi_ <<
1401 dma-names = " <<
1402 pinctrl-names <<
1403 pinctrl-0 = < <<
1404 interrupts = <<
1405 spi-max-frequ <<
1406 #address-cell <<
1407 #size-cells = <<
1408 status = "dis <<
1409 }; <<
1410 <<
1411 i2c11: i2c@a8c000 { <<
1412 compatible = <<
1413 reg = <0 0x00 <<
1414 clock-names = <<
1415 clocks = <&gc <<
1416 dmas = <&gpi_ <<
1417 <&gpi_ <<
1418 dma-names = " <<
1419 pinctrl-names <<
1420 pinctrl-0 = < <<
1421 interrupts = <<
1422 #address-cell <<
1423 #size-cells = <<
1424 status = "dis <<
1425 }; <<
1426 <<
1427 spi11: spi@a8c000 { <<
1428 compatible = <<
1429 reg = <0 0x00 <<
1430 reg-names = " <<
1431 clock-names = <<
1432 clocks = <&gc <<
1433 dmas = <&gpi_ <<
1434 <&gpi_ <<
1435 dma-names = " <<
1436 pinctrl-names <<
1437 pinctrl-0 = < <<
1438 interrupts = <<
1439 spi-max-frequ <<
1440 #address-cell <<
1441 #size-cells = <<
1442 status = "dis <<
1443 }; <<
1444 <<
1445 uart2: serial@a90000 591 uart2: serial@a90000 {
1446 compatible = 592 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 593 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 594 clock-names = "se";
1449 clocks = <&gc 595 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 596 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 597 status = "disabled";
1452 }; 598 };
1453 <<
1454 i2c12: i2c@a90000 { <<
1455 compatible = <<
1456 reg = <0 0x00 <<
1457 clock-names = <<
1458 clocks = <&gc <<
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 pinctrl-names <<
1463 pinctrl-0 = < <<
1464 interrupts = <<
1465 #address-cell <<
1466 #size-cells = <<
1467 status = "dis <<
1468 }; <<
1469 <<
1470 spi12: spi@a90000 { <<
1471 compatible = <<
1472 reg = <0 0x00 <<
1473 reg-names = " <<
1474 clock-names = <<
1475 clocks = <&gc <<
1476 dmas = <&gpi_ <<
1477 <&gpi_ <<
1478 dma-names = " <<
1479 pinctrl-names <<
1480 pinctrl-0 = < <<
1481 interrupts = <<
1482 spi-max-frequ <<
1483 #address-cell <<
1484 #size-cells = <<
1485 status = "dis <<
1486 }; <<
1487 <<
1488 i2c16: i2c@94000 { <<
1489 compatible = <<
1490 reg = <0 0x00 <<
1491 clock-names = <<
1492 clocks = <&gc <<
1493 dmas = <&gpi_ <<
1494 <&gpi_ <<
1495 dma-names = " <<
1496 pinctrl-names <<
1497 pinctrl-0 = < <<
1498 interrupts = <<
1499 #address-cell <<
1500 #size-cells = <<
1501 status = "dis <<
1502 }; <<
1503 <<
1504 spi16: spi@a94000 { <<
1505 compatible = <<
1506 reg = <0 0x00 <<
1507 reg-names = " <<
1508 clock-names = <<
1509 clocks = <&gc <<
1510 dmas = <&gpi_ <<
1511 <&gpi_ <<
1512 dma-names = " <<
1513 pinctrl-names <<
1514 pinctrl-0 = < <<
1515 interrupts = <<
1516 spi-max-frequ <<
1517 #address-cell <<
1518 #size-cells = <<
1519 status = "dis <<
1520 }; <<
1521 }; <<
1522 <<
1523 gpi_dma2: dma-controller@c000 <<
1524 compatible = "qcom,sm <<
1525 reg = <0 0x00c00000 0 <<
1526 interrupts = <GIC_SPI <<
1527 <GIC_SPI <<
1528 <GIC_SPI <<
1529 <GIC_SPI <<
1530 <GIC_SPI <<
1531 <GIC_SPI <<
1532 <GIC_SPI <<
1533 <GIC_SPI <<
1534 <GIC_SPI <<
1535 <GIC_SPI <<
1536 <GIC_SPI <<
1537 <GIC_SPI <<
1538 <GIC_SPI <<
1539 dma-channels = <13>; <<
1540 dma-channel-mask = <0 <<
1541 iommus = <&apps_smmu <<
1542 #dma-cells = <3>; <<
1543 status = "disabled"; <<
1544 }; <<
1545 <<
1546 qupv3_id_2: geniqup@cc0000 { <<
1547 compatible = "qcom,ge <<
1548 reg = <0x0 0x00cc0000 <<
1549 <<
1550 clock-names = "m-ahb" <<
1551 clocks = <&gcc GCC_QU <<
1552 <&gcc GCC_QU <<
1553 iommus = <&apps_smmu <<
1554 #address-cells = <2>; <<
1555 #size-cells = <2>; <<
1556 ranges; <<
1557 status = "disabled"; <<
1558 <<
1559 i2c17: i2c@c80000 { <<
1560 compatible = <<
1561 reg = <0 0x00 <<
1562 clock-names = <<
1563 clocks = <&gc <<
1564 dmas = <&gpi_ <<
1565 <&gpi_ <<
1566 dma-names = " <<
1567 pinctrl-names <<
1568 pinctrl-0 = < <<
1569 interrupts = <<
1570 #address-cell <<
1571 #size-cells = <<
1572 status = "dis <<
1573 }; <<
1574 <<
1575 spi17: spi@c80000 { <<
1576 compatible = <<
1577 reg = <0 0x00 <<
1578 reg-names = " <<
1579 clock-names = <<
1580 clocks = <&gc <<
1581 dmas = <&gpi_ <<
1582 <&gpi_ <<
1583 dma-names = " <<
1584 pinctrl-names <<
1585 pinctrl-0 = < <<
1586 interrupts = <<
1587 spi-max-frequ <<
1588 #address-cell <<
1589 #size-cells = <<
1590 status = "dis <<
1591 }; <<
1592 <<
1593 i2c18: i2c@c84000 { <<
1594 compatible = <<
1595 reg = <0 0x00 <<
1596 clock-names = <<
1597 clocks = <&gc <<
1598 dmas = <&gpi_ <<
1599 <&gpi_ <<
1600 dma-names = " <<
1601 pinctrl-names <<
1602 pinctrl-0 = < <<
1603 interrupts = <<
1604 #address-cell <<
1605 #size-cells = <<
1606 status = "dis <<
1607 }; <<
1608 <<
1609 spi18: spi@c84000 { <<
1610 compatible = <<
1611 reg = <0 0x00 <<
1612 reg-names = " <<
1613 clock-names = <<
1614 clocks = <&gc <<
1615 dmas = <&gpi_ <<
1616 <&gpi_ <<
1617 dma-names = " <<
1618 pinctrl-names <<
1619 pinctrl-0 = < <<
1620 interrupts = <<
1621 spi-max-frequ <<
1622 #address-cell <<
1623 #size-cells = <<
1624 status = "dis <<
1625 }; <<
1626 <<
1627 i2c19: i2c@c88000 { <<
1628 compatible = <<
1629 reg = <0 0x00 <<
1630 clock-names = <<
1631 clocks = <&gc <<
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 pinctrl-names <<
1636 pinctrl-0 = < <<
1637 interrupts = <<
1638 #address-cell <<
1639 #size-cells = <<
1640 status = "dis <<
1641 }; <<
1642 <<
1643 spi19: spi@c88000 { <<
1644 compatible = <<
1645 reg = <0 0x00 <<
1646 reg-names = " <<
1647 clock-names = <<
1648 clocks = <&gc <<
1649 dmas = <&gpi_ <<
1650 <&gpi_ <<
1651 dma-names = " <<
1652 pinctrl-names <<
1653 pinctrl-0 = < <<
1654 interrupts = <<
1655 spi-max-frequ <<
1656 #address-cell <<
1657 #size-cells = <<
1658 status = "dis <<
1659 }; <<
1660 <<
1661 i2c13: i2c@c8c000 { <<
1662 compatible = <<
1663 reg = <0 0x00 <<
1664 clock-names = <<
1665 clocks = <&gc <<
1666 dmas = <&gpi_ <<
1667 <&gpi_ <<
1668 dma-names = " <<
1669 pinctrl-names <<
1670 pinctrl-0 = < <<
1671 interrupts = <<
1672 #address-cell <<
1673 #size-cells = <<
1674 status = "dis <<
1675 }; <<
1676 <<
1677 spi13: spi@c8c000 { <<
1678 compatible = <<
1679 reg = <0 0x00 <<
1680 reg-names = " <<
1681 clock-names = <<
1682 clocks = <&gc <<
1683 dmas = <&gpi_ <<
1684 <&gpi_ <<
1685 dma-names = " <<
1686 pinctrl-names <<
1687 pinctrl-0 = < <<
1688 interrupts = <<
1689 spi-max-frequ <<
1690 #address-cell <<
1691 #size-cells = <<
1692 status = "dis <<
1693 }; <<
1694 <<
1695 i2c14: i2c@c90000 { <<
1696 compatible = <<
1697 reg = <0 0x00 <<
1698 clock-names = <<
1699 clocks = <&gc <<
1700 dmas = <&gpi_ <<
1701 <&gpi_ <<
1702 dma-names = " <<
1703 pinctrl-names <<
1704 pinctrl-0 = < <<
1705 interrupts = <<
1706 #address-cell <<
1707 #size-cells = <<
1708 status = "dis <<
1709 }; <<
1710 <<
1711 spi14: spi@c90000 { <<
1712 compatible = <<
1713 reg = <0 0x00 <<
1714 reg-names = " <<
1715 clock-names = <<
1716 clocks = <&gc <<
1717 dmas = <&gpi_ <<
1718 <&gpi_ <<
1719 dma-names = " <<
1720 pinctrl-names <<
1721 pinctrl-0 = < <<
1722 interrupts = <<
1723 spi-max-frequ <<
1724 #address-cell <<
1725 #size-cells = <<
1726 status = "dis <<
1727 }; <<
1728 <<
1729 i2c15: i2c@c94000 { <<
1730 compatible = <<
1731 reg = <0 0x00 <<
1732 clock-names = <<
1733 clocks = <&gc <<
1734 dmas = <&gpi_ <<
1735 <&gpi_ <<
1736 dma-names = " <<
1737 pinctrl-names <<
1738 pinctrl-0 = < <<
1739 interrupts = <<
1740 #address-cell <<
1741 #size-cells = <<
1742 status = "dis <<
1743 }; <<
1744 <<
1745 spi15: spi@c94000 { <<
1746 compatible = <<
1747 reg = <0 0x00 <<
1748 reg-names = " <<
1749 clock-names = <<
1750 clocks = <&gc <<
1751 dmas = <&gpi_ <<
1752 <&gpi_ <<
1753 dma-names = " <<
1754 pinctrl-names <<
1755 pinctrl-0 = < <<
1756 interrupts = <<
1757 spi-max-frequ <<
1758 #address-cell <<
1759 #size-cells = <<
1760 status = "dis <<
1761 }; <<
1762 }; 599 };
1763 600
1764 config_noc: interconnect@1500 601 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 602 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 603 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 604 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 605 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 606 };
1770 607
1771 system_noc: interconnect@1620 608 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 609 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 610 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 611 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 612 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 613 };
1777 614
1778 mc_virt: interconnect@163a000 615 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 616 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 617 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 618 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 619 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 620 };
1784 621
1785 aggre1_noc: interconnect@16e0 622 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 623 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 624 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 625 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 626 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 627 };
1791 628
1792 aggre2_noc: interconnect@1700 629 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 630 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 631 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 632 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 633 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 634 };
1798 635
1799 compute_noc: interconnect@172 636 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 637 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 638 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 639 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 640 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 641 };
1805 642
1806 mmss_noc: interconnect@174000 643 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 644 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 645 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 646 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 647 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 648 };
1812 649
1813 system-cache-controller@92000 650 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 651 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 652 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 653 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 654 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 655 };
1822 656
1823 dma@10a2000 { <<
1824 compatible = "qcom,sm <<
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 <<
1832 <0 0x60000000 0 <<
1833 <0 0x60000f20 0 <<
1834 <0 0x60001000 0 <<
1835 <0 0x60100000 0 <<
1836 reg-names = "parf", " <<
1837 device_type = "pci"; <<
1838 linux,pci-domain = <0 <<
1839 bus-range = <0x00 0xf <<
1840 num-lanes = <1>; <<
1841 <<
1842 #address-cells = <3>; <<
1843 #size-cells = <2>; <<
1844 <<
1845 ranges = <0x01000000 <<
1846 <0x02000000 <<
1847 <<
1848 interrupts = <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 <<
1865 interrupt-map-mask = <<
1866 interrupt-map = <0 0 <<
1867 <0 0 <<
1868 <0 0 <<
1869 <0 0 <<
1870 <<
1871 clocks = <&gcc GCC_PC <<
1872 <&gcc GCC_PC <<
1873 <&gcc GCC_PC <<
1874 <&gcc GCC_PC <<
1875 <&gcc GCC_PC <<
1876 <&gcc GCC_PC <<
1877 <&gcc GCC_AG <<
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", <<
1880 "aux", <<
1881 "cfg", <<
1882 "bus_ma <<
1883 "bus_sl <<
1884 "slave_ <<
1885 "tbu", <<
1886 "ref"; <<
1887 <<
1888 iommu-map = <0x0 &a <<
1889 <0x100 &a <<
1890 <<
1891 resets = <&gcc GCC_PC <<
1892 reset-names = "pci"; <<
1893 <<
1894 power-domains = <&gcc <<
1895 <<
1896 phys = <&pcie0_phy>; <<
1897 phy-names = "pciephy" <<
1898 <<
1899 perst-gpios = <&tlmm <<
1900 wake-gpios = <&tlmm 3 <<
1901 <<
1902 pinctrl-names = "defa <<
1903 pinctrl-0 = <&pcie0_d <<
1904 <<
1905 status = "disabled"; <<
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; <<
1917 <<
1918 pcie0_phy: phy@1c06000 { <<
1919 compatible = "qcom,sm <<
1920 reg = <0 0x01c06000 0 <<
1921 clocks = <&gcc GCC_PC <<
1922 <&gcc GCC_PC <<
1923 <&gcc GCC_PC <<
1924 <&gcc GCC_PC <<
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 <<
1937 resets = <&gcc GCC_PC <<
1938 reset-names = "phy"; <<
1939 <<
1940 assigned-clocks = <&g <<
1941 assigned-clock-rates <<
1942 <<
1943 status = "disabled"; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@1c08000 { <<
1947 compatible = "qcom,pc <<
1948 reg = <0 0x01c08000 0 <<
1949 <0 0x40000000 0 <<
1950 <0 0x40000f20 0 <<
1951 <0 0x40001000 0 <<
1952 <0 0x40100000 0 <<
1953 reg-names = "parf", " <<
1954 device_type = "pci"; <<
1955 linux,pci-domain = <1 <<
1956 bus-range = <0x00 0xf <<
1957 num-lanes = <2>; <<
1958 <<
1959 #address-cells = <3>; <<
1960 #size-cells = <2>; <<
1961 <<
1962 ranges = <0x01000000 <<
1963 <0x02000000 <<
1964 <<
1965 interrupts = <GIC_SPI <<
1966 <GIC_SPI <<
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 <<
1982 interrupt-map-mask = <<
1983 interrupt-map = <0 0 <<
1984 <0 0 <<
1985 <0 0 <<
1986 <0 0 <<
1987 <<
1988 clocks = <&gcc GCC_PC <<
1989 <&gcc GCC_PC <<
1990 <&gcc GCC_PC <<
1991 <&gcc GCC_PC <<
1992 <&gcc GCC_PC <<
1993 <&gcc GCC_PC <<
1994 <&gcc GCC_AG <<
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", <<
1997 "aux", <<
1998 "cfg", <<
1999 "bus_ma <<
2000 "bus_sl <<
2001 "slave_ <<
2002 "tbu", <<
2003 "ref"; <<
2004 <<
2005 assigned-clocks = <&g <<
2006 assigned-clock-rates <<
2007 <<
2008 iommu-map = <0x0 &a <<
2009 <0x100 &a <<
2010 <<
2011 resets = <&gcc GCC_PC <<
2012 reset-names = "pci"; <<
2013 <<
2014 power-domains = <&gcc <<
2015 <<
2016 phys = <&pcie1_phy>; <<
2017 phy-names = "pciephy" <<
2018 <<
2019 perst-gpios = <&tlmm <<
2020 enable-gpio = <&tlmm <<
2021 <<
2022 pinctrl-names = "defa <<
2023 pinctrl-0 = <&pcie1_d <<
2024 <<
2025 status = "disabled"; <<
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; <<
2037 <<
2038 pcie1_phy: phy@1c0e000 { <<
2039 compatible = "qcom,sm <<
2040 reg = <0 0x01c0e000 0 <<
2041 clocks = <&gcc GCC_PC <<
2042 <&gcc GCC_PC <<
2043 <&gcc GCC_PC <<
2044 <&gcc GCC_PC <<
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 <<
2057 resets = <&gcc GCC_PC <<
2058 reset-names = "phy"; <<
2059 <<
2060 assigned-clocks = <&g <<
2061 assigned-clock-rates <<
2062 <<
2063 status = "disabled"; <<
2064 }; <<
2065 <<
2066 ufs_mem_hc: ufshc@1d84000 { 657 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 658 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 659 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 !! 660 reg = <0 0x01d84000 0 0x2500>;
2070 <0 0x01d90000 0 <<
2071 reg-names = "std", "i <<
2072 interrupts = <GIC_SPI 661 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 662 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 663 phy-names = "ufsphy";
2075 lanes-per-direction = 664 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 665 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 666 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 667 reset-names = "rst";
2079 668
2080 iommus = <&apps_smmu 669 iommus = <&apps_smmu 0x300 0>;
2081 670
2082 clock-names = 671 clock-names =
2083 "core_clk", 672 "core_clk",
2084 "bus_aggr_clk 673 "bus_aggr_clk",
2085 "iface_clk", 674 "iface_clk",
2086 "core_clk_uni 675 "core_clk_unipro",
2087 "ref_clk", 676 "ref_clk",
2088 "tx_lane0_syn 677 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 678 "rx_lane0_sync_clk",
2090 "rx_lane1_syn !! 679 "rx_lane1_sync_clk";
2091 "ice_core_clk <<
2092 clocks = 680 clocks =
2093 <&gcc GCC_UFS 681 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 682 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 683 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 684 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 685 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 686 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 687 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS !! 688 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2101 <&gcc GCC_UFS <<
2102 freq-table-hz = 689 freq-table-hz =
2103 <37500000 300 690 <37500000 300000000>,
2104 <0 0>, 691 <0 0>,
2105 <0 0>, 692 <0 0>,
2106 <37500000 300 693 <37500000 300000000>,
2107 <0 0>, 694 <0 0>,
2108 <0 0>, 695 <0 0>,
2109 <0 0>, 696 <0 0>,
2110 <0 0>, !! 697 <0 0>;
2111 <0 300000000> <<
2112 698
2113 status = "disabled"; 699 status = "disabled";
2114 }; 700 };
2115 701
2116 ufs_mem_phy: phy@1d87000 { 702 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 703 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 704 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 705 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 706 #size-cells = <2>;
2121 <&gcc GCC_UF !! 707 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 708 clock-names = "ref",
2124 "ref_au !! 709 "ref_aux";
2125 "qref"; !! 710 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2126 !! 711 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2127 power-domains = <&gcc <<
2128 712
2129 resets = <&ufs_mem_hc 713 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 714 reset-names = "ufsphy";
>> 715 status = "disabled";
2131 716
2132 #phy-cells = <0>; !! 717 ufs_mem_phy_lanes: lanes@1d87400 {
>> 718 reg = <0 0x01d87400 0 0x108>,
>> 719 <0 0x01d87600 0 0x1e0>,
>> 720 <0 0x01d87c00 0 0x1dc>,
>> 721 <0 0x01d87800 0 0x108>,
>> 722 <0 0x01d87a00 0 0x1e0>;
>> 723 #phy-cells = <0>;
>> 724 };
>> 725 };
2133 726
2134 status = "disabled"; !! 727 ipa_virt: interconnect@1e00000 {
>> 728 compatible = "qcom,sm8150-ipa-virt";
>> 729 reg = <0 0x01e00000 0 0x1000>;
>> 730 #interconnect-cells = <1>;
>> 731 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 732 };
2136 733
2137 cryptobam: dma-controller@1dc !! 734 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 735 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 736 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 737 };
2177 738
2178 remoteproc_slpi: remoteproc@2 739 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 740 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 741 reg = <0x0 0x02400000 0x0 0x4040>;
2181 742
2182 interrupts-extended = 743 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 744 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 745 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 746 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 747 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 748 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 749 "handover", "stop-ack";
2189 750
2190 clocks = <&rpmhcc RPM 751 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 752 clock-names = "xo";
2192 753
2193 power-domains = <&rpm !! 754 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
2194 <&rpm !! 755 <&rpmhpd 3>,
2195 power-domain-names = !! 756 <&rpmhpd 2>;
>> 757 power-domain-names = "load_state", "lcx", "lmx";
2196 758
2197 memory-region = <&slp 759 memory-region = <&slpi_mem>;
2198 760
2199 qcom,qmp = <&aoss_qmp <<
2200 <<
2201 qcom,smem-states = <& 761 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 762 qcom,smem-state-names = "stop";
2203 763
2204 status = "disabled"; 764 status = "disabled";
2205 765
2206 glink-edge { 766 glink-edge {
2207 interrupts = 767 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 768 label = "dsps";
2209 qcom,remote-p 769 qcom,remote-pid = <3>;
2210 mboxes = <&ap 770 mboxes = <&apss_shared 24>;
2211 <<
2212 fastrpc { <<
2213 compa <<
2214 qcom, <<
2215 label <<
2216 qcom, <<
2217 #addr <<
2218 #size <<
2219 <<
2220 compu <<
2221 <<
2222 <<
2223 <<
2224 }; <<
2225 <<
2226 compu <<
2227 <<
2228 <<
2229 <<
2230 }; <<
2231 <<
2232 compu <<
2233 <<
2234 <<
2235 <<
2236 <<
2237 }; <<
2238 }; <<
2239 }; 771 };
2240 }; 772 };
2241 773
2242 gpu: gpu@2c00000 { 774 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 775 /*
>> 776 * note: the amd,imageon compatible makes it possible
>> 777 * to use the drm/msm driver without the display node,
>> 778 * make sure to remove it when display node is added
>> 779 */
>> 780 compatible = "qcom,adreno-640.1",
>> 781 "qcom,adreno",
>> 782 "amd,imageon";
>> 783 #stream-id-cells = <16>;
>> 784
2244 reg = <0 0x02c00000 0 785 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 786 reg-names = "kgsl_3d0_reg_memory";
2246 787
2247 interrupts = <GIC_SPI 788 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 789
2249 iommus = <&adreno_smm 790 iommus = <&adreno_smmu 0 0x401>;
2250 791
2251 operating-points-v2 = 792 operating-points-v2 = <&gpu_opp_table>;
2252 793
2253 qcom,gmu = <&gmu>; 794 qcom,gmu = <&gmu>;
2254 795
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; <<
2260 <<
2261 zap-shader { 796 zap-shader {
2262 memory-region 797 memory-region = <&gpu_mem>;
2263 }; 798 };
2264 799
>> 800 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 801 gpu_opp_table: opp-table {
2266 compatible = 802 compatible = "operating-points-v2";
2267 803
2268 opp-675000000 804 opp-675000000 {
2269 opp-h 805 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 806 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 807 };
2273 808
2274 opp-585000000 809 opp-585000000 {
2275 opp-h 810 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 811 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 812 };
2279 813
2280 opp-499200000 814 opp-499200000 {
2281 opp-h 815 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 816 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 817 };
2285 818
2286 opp-427000000 819 opp-427000000 {
2287 opp-h 820 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 821 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 822 };
2291 823
2292 opp-345000000 824 opp-345000000 {
2293 opp-h 825 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 826 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 827 };
2297 828
2298 opp-257000000 829 opp-257000000 {
2299 opp-h 830 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 831 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 832 };
2303 }; 833 };
2304 }; 834 };
2305 835
2306 gmu: gmu@2c6a000 { 836 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 837 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 838
2309 reg = <0 0x02c6a000 0 839 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 840 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 841 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 842 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 843
2314 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 845 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 846 interrupt-names = "hfi", "gmu";
2317 847
2318 clocks = <&gpucc GPU_ 848 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 849 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 850 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 851 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 852 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 853 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 854
2325 power-domains = <&gpu 855 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 856 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 857 power-domain-names = "cx", "gx";
2328 858
2329 iommus = <&adreno_smm 859 iommus = <&adreno_smmu 5 0x400>;
2330 860
2331 operating-points-v2 = 861 operating-points-v2 = <&gmu_opp_table>;
2332 862
2333 status = "disabled"; <<
2334 <<
2335 gmu_opp_table: opp-ta 863 gmu_opp_table: opp-table {
2336 compatible = 864 compatible = "operating-points-v2";
2337 865
2338 opp-200000000 866 opp-200000000 {
2339 opp-h 867 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 868 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 869 };
2342 }; 870 };
2343 }; 871 };
2344 872
2345 gpucc: clock-controller@2c900 873 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 874 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 875 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 876 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 877 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 878 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 879 clock-names = "bi_tcxo",
2352 "gcc_gp 880 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 881 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 882 #clock-cells = <1>;
2355 #reset-cells = <1>; 883 #reset-cells = <1>;
2356 #power-domain-cells = 884 #power-domain-cells = <1>;
2357 }; 885 };
2358 886
2359 adreno_smmu: iommu@2ca0000 { 887 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 888 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 889 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 890 #iommu-cells = <2>;
2364 #global-interrupts = 891 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 892 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 893 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 894 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 895 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 896 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 897 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 898 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 899 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 900 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 901 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 902 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 903 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 904 clock-names = "ahb", "bus", "iface";
2378 905
2379 power-domains = <&gpu 906 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 907 };
2381 908
2382 tlmm: pinctrl@3100000 { 909 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 910 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 911 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 912 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 913 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 914 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 915 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 916 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 917 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 918 gpio-controller;
2392 #gpio-cells = <2>; 919 #gpio-cells = <2>;
2393 interrupt-controller; 920 interrupt-controller;
2394 #interrupt-cells = <2 921 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc <<
2396 <<
2397 qup_i2c0_default: qup <<
2398 pins = "gpio0 <<
2399 function = "q <<
2400 drive-strengt <<
2401 bias-disable; <<
2402 }; <<
2403 <<
2404 qup_spi0_default: qup <<
2405 pins = "gpio0 <<
2406 function = "q <<
2407 drive-strengt <<
2408 bias-disable; <<
2409 }; <<
2410 <<
2411 qup_i2c1_default: qup <<
2412 pins = "gpio1 <<
2413 function = "q <<
2414 drive-strengt <<
2415 bias-disable; <<
2416 }; <<
2417 <<
2418 qup_spi1_default: qup <<
2419 pins = "gpio1 <<
2420 function = "q <<
2421 drive-strengt <<
2422 bias-disable; <<
2423 }; <<
2424 <<
2425 qup_i2c2_default: qup <<
2426 pins = "gpio1 <<
2427 function = "q <<
2428 drive-strengt <<
2429 bias-disable; <<
2430 }; <<
2431 <<
2432 qup_spi2_default: qup <<
2433 pins = "gpio1 <<
2434 function = "q <<
2435 drive-strengt <<
2436 bias-disable; <<
2437 }; <<
2438 <<
2439 qup_i2c3_default: qup <<
2440 pins = "gpio1 <<
2441 function = "q <<
2442 drive-strengt <<
2443 bias-disable; <<
2444 }; <<
2445 <<
2446 qup_spi3_default: qup <<
2447 pins = "gpio1 <<
2448 function = "q <<
2449 drive-strengt <<
2450 bias-disable; <<
2451 }; <<
2452 <<
2453 qup_i2c4_default: qup <<
2454 pins = "gpio5 <<
2455 function = "q <<
2456 drive-strengt <<
2457 bias-disable; <<
2458 }; <<
2459 <<
2460 qup_spi4_default: qup <<
2461 pins = "gpio5 <<
2462 function = "q <<
2463 drive-strengt <<
2464 bias-disable; <<
2465 }; <<
2466 <<
2467 qup_i2c5_default: qup <<
2468 pins = "gpio1 <<
2469 function = "q <<
2470 drive-strengt <<
2471 bias-disable; <<
2472 }; <<
2473 <<
2474 qup_spi5_default: qup <<
2475 pins = "gpio1 <<
2476 function = "q <<
2477 drive-strengt <<
2478 bias-disable; <<
2479 }; <<
2480 <<
2481 qup_i2c6_default: qup <<
2482 pins = "gpio6 <<
2483 function = "q <<
2484 drive-strengt <<
2485 bias-disable; <<
2486 }; <<
2487 <<
2488 qup_spi6_default: qup <<
2489 pins = "gpio4 <<
2490 function = "q <<
2491 drive-strengt <<
2492 bias-disable; <<
2493 }; <<
2494 <<
2495 qup_i2c7_default: qup <<
2496 pins = "gpio9 <<
2497 function = "q <<
2498 drive-strengt <<
2499 bias-disable; <<
2500 }; <<
2501 <<
2502 qup_spi7_default: qup <<
2503 pins = "gpio9 <<
2504 function = "q <<
2505 drive-strengt <<
2506 bias-disable; <<
2507 }; <<
2508 <<
2509 qup_i2c8_default: qup <<
2510 pins = "gpio8 <<
2511 function = "q <<
2512 drive-strengt <<
2513 bias-disable; <<
2514 }; <<
2515 <<
2516 qup_spi8_default: qup <<
2517 pins = "gpio8 <<
2518 function = "q <<
2519 drive-strengt <<
2520 bias-disable; <<
2521 }; <<
2522 <<
2523 qup_i2c9_default: qup <<
2524 pins = "gpio3 <<
2525 function = "q <<
2526 drive-strengt <<
2527 bias-disable; <<
2528 }; <<
2529 <<
2530 qup_spi9_default: qup <<
2531 pins = "gpio3 <<
2532 function = "q <<
2533 drive-strengt <<
2534 bias-disable; <<
2535 }; <<
2536 <<
2537 qup_uart9_default: qu <<
2538 pins = "gpio4 <<
2539 function = "q <<
2540 drive-strengt <<
2541 bias-disable; <<
2542 }; <<
2543 <<
2544 qup_i2c10_default: qu <<
2545 pins = "gpio9 <<
2546 function = "q <<
2547 drive-strengt <<
2548 bias-disable; <<
2549 }; <<
2550 <<
2551 qup_spi10_default: qu <<
2552 pins = "gpio9 <<
2553 function = "q <<
2554 drive-strengt <<
2555 bias-disable; <<
2556 }; <<
2557 <<
2558 qup_i2c11_default: qu <<
2559 pins = "gpio9 <<
2560 function = "q <<
2561 drive-strengt <<
2562 bias-disable; <<
2563 }; <<
2564 <<
2565 qup_spi11_default: qu <<
2566 pins = "gpio9 <<
2567 function = "q <<
2568 drive-strengt <<
2569 bias-disable; <<
2570 }; <<
2571 <<
2572 qup_i2c12_default: qu <<
2573 pins = "gpio8 <<
2574 function = "q <<
2575 drive-strengt <<
2576 bias-disable; <<
2577 }; <<
2578 <<
2579 qup_spi12_default: qu <<
2580 pins = "gpio8 <<
2581 function = "q <<
2582 drive-strengt <<
2583 bias-disable; <<
2584 }; <<
2585 <<
2586 qup_i2c13_default: qu <<
2587 pins = "gpio4 <<
2588 function = "q <<
2589 drive-strengt <<
2590 bias-disable; <<
2591 }; <<
2592 <<
2593 qup_spi13_default: qu <<
2594 pins = "gpio4 <<
2595 function = "q <<
2596 drive-strengt <<
2597 bias-disable; <<
2598 }; <<
2599 <<
2600 qup_i2c14_default: qu <<
2601 pins = "gpio4 <<
2602 function = "q <<
2603 drive-strengt <<
2604 bias-disable; <<
2605 }; <<
2606 <<
2607 qup_spi14_default: qu <<
2608 pins = "gpio4 <<
2609 function = "q <<
2610 drive-strengt <<
2611 bias-disable; <<
2612 }; <<
2613 <<
2614 qup_i2c15_default: qu <<
2615 pins = "gpio2 <<
2616 function = "q <<
2617 drive-strengt <<
2618 bias-disable; <<
2619 }; <<
2620 <<
2621 qup_spi15_default: qu <<
2622 pins = "gpio2 <<
2623 function = "q <<
2624 drive-strengt <<
2625 bias-disable; <<
2626 }; <<
2627 <<
2628 qup_i2c16_default: qu <<
2629 pins = "gpio8 <<
2630 function = "q <<
2631 drive-strengt <<
2632 bias-disable; <<
2633 }; <<
2634 <<
2635 qup_spi16_default: qu <<
2636 pins = "gpio8 <<
2637 function = "q <<
2638 drive-strengt <<
2639 bias-disable; <<
2640 }; <<
2641 <<
2642 qup_i2c17_default: qu <<
2643 pins = "gpio5 <<
2644 function = "q <<
2645 drive-strengt <<
2646 bias-disable; <<
2647 }; <<
2648 <<
2649 qup_spi17_default: qu <<
2650 pins = "gpio5 <<
2651 function = "q <<
2652 drive-strengt <<
2653 bias-disable; <<
2654 }; <<
2655 <<
2656 qup_i2c18_default: qu <<
2657 pins = "gpio2 <<
2658 function = "q <<
2659 drive-strengt <<
2660 bias-disable; <<
2661 }; <<
2662 <<
2663 qup_spi18_default: qu <<
2664 pins = "gpio2 <<
2665 function = "q <<
2666 drive-strengt <<
2667 bias-disable; <<
2668 }; <<
2669 <<
2670 qup_i2c19_default: qu <<
2671 pins = "gpio5 <<
2672 function = "q <<
2673 drive-strengt <<
2674 bias-disable; <<
2675 }; <<
2676 <<
2677 qup_spi19_default: qu <<
2678 pins = "gpio5 <<
2679 function = "q <<
2680 drive-strengt <<
2681 bias-disable; <<
2682 }; <<
2683 <<
2684 pcie0_default_state: <<
2685 perst-pins { <<
2686 pins <<
2687 funct <<
2688 drive <<
2689 bias- <<
2690 }; <<
2691 <<
2692 clkreq-pins { <<
2693 pins <<
2694 funct <<
2695 drive <<
2696 bias- <<
2697 }; <<
2698 <<
2699 wake-pins { <<
2700 pins <<
2701 funct <<
2702 drive <<
2703 bias- <<
2704 }; <<
2705 }; <<
2706 <<
2707 pcie1_default_state: <<
2708 perst-pins { <<
2709 pins <<
2710 funct <<
2711 drive <<
2712 bias- <<
2713 }; <<
2714 <<
2715 clkreq-pins { <<
2716 pins <<
2717 funct <<
2718 drive <<
2719 bias- <<
2720 }; <<
2721 <<
2722 wake-pins { <<
2723 pins <<
2724 funct <<
2725 drive <<
2726 bias- <<
2727 }; <<
2728 }; <<
2729 }; 922 };
2730 923
2731 remoteproc_mpss: remoteproc@4 924 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 925 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 926 reg = <0x0 0x04080000 0x0 0x4040>;
2734 927
2735 interrupts-extended = 928 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 929 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 930 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 931 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 932 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 933 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 934 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 935 "stop-ack", "shutdown-ack";
2743 936
2744 clocks = <&rpmhcc RPM 937 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 938 clock-names = "xo";
2746 939
2747 power-domains = <&rpm !! 940 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2748 <&rpm !! 941 <&rpmhpd 7>,
2749 power-domain-names = !! 942 <&rpmhpd 0>;
>> 943 power-domain-names = "load_state", "cx", "mss";
2750 944
2751 memory-region = <&mps 945 memory-region = <&mpss_mem>;
2752 946
2753 qcom,qmp = <&aoss_qmp <<
2754 <<
2755 qcom,smem-states = <& 947 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 948 qcom,smem-state-names = "stop";
2757 949
2758 status = "disabled"; <<
2759 <<
2760 glink-edge { 950 glink-edge {
2761 interrupts = 951 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 952 label = "modem";
2763 qcom,remote-p 953 qcom,remote-pid = <1>;
2764 mboxes = <&ap 954 mboxes = <&apss_shared 12>;
2765 }; 955 };
2766 }; 956 };
2767 957
2768 stm@6002000 { 958 stm@6002000 {
2769 compatible = "arm,cor 959 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 960 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 961 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 962 reg-names = "stm-base", "stm-stimulus-base";
2773 963
2774 clocks = <&aoss_qmp>; 964 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 965 clock-names = "apb_pclk";
2776 966
2777 out-ports { 967 out-ports {
2778 port { 968 port {
2779 stm_o 969 stm_out: endpoint {
2780 970 remote-endpoint = <&funnel0_in7>;
2781 }; 971 };
2782 }; 972 };
2783 }; 973 };
2784 }; 974 };
2785 975
2786 funnel@6041000 { 976 funnel@6041000 {
2787 compatible = "arm,cor 977 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 978 reg = <0 0x06041000 0 0x1000>;
2789 979
2790 clocks = <&aoss_qmp>; 980 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 981 clock-names = "apb_pclk";
2792 982
2793 out-ports { 983 out-ports {
2794 port { 984 port {
2795 funne 985 funnel0_out: endpoint {
2796 986 remote-endpoint = <&merge_funnel_in0>;
2797 }; 987 };
2798 }; 988 };
2799 }; 989 };
2800 990
2801 in-ports { 991 in-ports {
2802 #address-cell 992 #address-cells = <1>;
2803 #size-cells = 993 #size-cells = <0>;
2804 994
2805 port@7 { 995 port@7 {
2806 reg = 996 reg = <7>;
2807 funne 997 funnel0_in7: endpoint {
2808 998 remote-endpoint = <&stm_out>;
2809 }; 999 };
2810 }; 1000 };
2811 }; 1001 };
2812 }; 1002 };
2813 1003
2814 funnel@6042000 { 1004 funnel@6042000 {
2815 compatible = "arm,cor 1005 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 1006 reg = <0 0x06042000 0 0x1000>;
2817 1007
2818 clocks = <&aoss_qmp>; 1008 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 1009 clock-names = "apb_pclk";
2820 1010
2821 out-ports { 1011 out-ports {
2822 port { 1012 port {
2823 funne 1013 funnel1_out: endpoint {
2824 1014 remote-endpoint = <&merge_funnel_in1>;
2825 }; 1015 };
2826 }; 1016 };
2827 }; 1017 };
2828 1018
2829 in-ports { 1019 in-ports {
2830 #address-cell 1020 #address-cells = <1>;
2831 #size-cells = 1021 #size-cells = <0>;
2832 1022
2833 port@4 { 1023 port@4 {
2834 reg = 1024 reg = <4>;
2835 funne 1025 funnel1_in4: endpoint {
2836 1026 remote-endpoint = <&swao_replicator_out>;
2837 }; 1027 };
2838 }; 1028 };
2839 }; 1029 };
2840 }; 1030 };
2841 1031
2842 funnel@6043000 { 1032 funnel@6043000 {
2843 compatible = "arm,cor 1033 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 1034 reg = <0 0x06043000 0 0x1000>;
2845 1035
2846 clocks = <&aoss_qmp>; 1036 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 1037 clock-names = "apb_pclk";
2848 1038
2849 out-ports { 1039 out-ports {
2850 port { 1040 port {
2851 funne 1041 funnel2_out: endpoint {
2852 1042 remote-endpoint = <&merge_funnel_in2>;
2853 }; 1043 };
2854 }; 1044 };
2855 }; 1045 };
2856 1046
2857 in-ports { 1047 in-ports {
2858 #address-cell 1048 #address-cells = <1>;
2859 #size-cells = 1049 #size-cells = <0>;
2860 1050
2861 port@2 { 1051 port@2 {
2862 reg = 1052 reg = <2>;
2863 funne 1053 funnel2_in2: endpoint {
2864 1054 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 1055 };
2866 }; 1056 };
2867 }; 1057 };
2868 }; 1058 };
2869 1059
2870 funnel@6045000 { 1060 funnel@6045000 {
2871 compatible = "arm,cor 1061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 1062 reg = <0 0x06045000 0 0x1000>;
2873 1063
2874 clocks = <&aoss_qmp>; 1064 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 1065 clock-names = "apb_pclk";
2876 1066
2877 out-ports { 1067 out-ports {
2878 port { 1068 port {
2879 merge 1069 merge_funnel_out: endpoint {
2880 1070 remote-endpoint = <&etf_in>;
2881 }; 1071 };
2882 }; 1072 };
2883 }; 1073 };
2884 1074
2885 in-ports { 1075 in-ports {
2886 #address-cell 1076 #address-cells = <1>;
2887 #size-cells = 1077 #size-cells = <0>;
2888 1078
2889 port@0 { 1079 port@0 {
2890 reg = 1080 reg = <0>;
2891 merge 1081 merge_funnel_in0: endpoint {
2892 1082 remote-endpoint = <&funnel0_out>;
2893 }; 1083 };
2894 }; 1084 };
2895 1085
2896 port@1 { 1086 port@1 {
2897 reg = 1087 reg = <1>;
2898 merge 1088 merge_funnel_in1: endpoint {
2899 1089 remote-endpoint = <&funnel1_out>;
2900 }; 1090 };
2901 }; 1091 };
2902 1092
2903 port@2 { 1093 port@2 {
2904 reg = 1094 reg = <2>;
2905 merge 1095 merge_funnel_in2: endpoint {
2906 1096 remote-endpoint = <&funnel2_out>;
2907 }; 1097 };
2908 }; 1098 };
2909 }; 1099 };
2910 }; 1100 };
2911 1101
2912 replicator@6046000 { 1102 replicator@6046000 {
2913 compatible = "arm,cor 1103 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 1104 reg = <0 0x06046000 0 0x1000>;
2915 1105
2916 clocks = <&aoss_qmp>; 1106 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 1107 clock-names = "apb_pclk";
2918 1108
2919 out-ports { 1109 out-ports {
2920 #address-cell 1110 #address-cells = <1>;
2921 #size-cells = 1111 #size-cells = <0>;
2922 1112
2923 port@0 { 1113 port@0 {
2924 reg = 1114 reg = <0>;
2925 repli 1115 replicator_out0: endpoint {
2926 1116 remote-endpoint = <&etr_in>;
2927 }; 1117 };
2928 }; 1118 };
2929 1119
2930 port@1 { 1120 port@1 {
2931 reg = 1121 reg = <1>;
2932 repli 1122 replicator_out1: endpoint {
2933 1123 remote-endpoint = <&replicator1_in>;
2934 }; 1124 };
2935 }; 1125 };
2936 }; 1126 };
2937 1127
2938 in-ports { 1128 in-ports {
2939 port { 1129 port {
2940 repli 1130 replicator_in0: endpoint {
2941 1131 remote-endpoint = <&etf_out>;
2942 }; 1132 };
2943 }; 1133 };
2944 }; 1134 };
2945 }; 1135 };
2946 1136
2947 etf@6047000 { 1137 etf@6047000 {
2948 compatible = "arm,cor 1138 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 1139 reg = <0 0x06047000 0 0x1000>;
2950 1140
2951 clocks = <&aoss_qmp>; 1141 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 1142 clock-names = "apb_pclk";
2953 1143
2954 out-ports { 1144 out-ports {
2955 port { 1145 port {
2956 etf_o 1146 etf_out: endpoint {
2957 1147 remote-endpoint = <&replicator_in0>;
2958 }; 1148 };
2959 }; 1149 };
2960 }; 1150 };
2961 1151
2962 in-ports { 1152 in-ports {
2963 port { 1153 port {
2964 etf_i 1154 etf_in: endpoint {
2965 1155 remote-endpoint = <&merge_funnel_out>;
2966 }; 1156 };
2967 }; 1157 };
2968 }; 1158 };
2969 }; 1159 };
2970 1160
2971 etr@6048000 { 1161 etr@6048000 {
2972 compatible = "arm,cor 1162 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 1163 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 1164 iommus = <&apps_smmu 0x05e0 0x0>;
2975 1165
2976 clocks = <&aoss_qmp>; 1166 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 1167 clock-names = "apb_pclk";
2978 arm,scatter-gather; 1168 arm,scatter-gather;
2979 1169
2980 in-ports { 1170 in-ports {
2981 port { 1171 port {
2982 etr_i 1172 etr_in: endpoint {
2983 1173 remote-endpoint = <&replicator_out0>;
2984 }; 1174 };
2985 }; 1175 };
2986 }; 1176 };
2987 }; 1177 };
2988 1178
2989 replicator@604a000 { 1179 replicator@604a000 {
2990 compatible = "arm,cor 1180 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 1181 reg = <0 0x0604a000 0 0x1000>;
2992 1182
2993 clocks = <&aoss_qmp>; 1183 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 1184 clock-names = "apb_pclk";
2995 1185
2996 out-ports { 1186 out-ports {
2997 #address-cell 1187 #address-cells = <1>;
2998 #size-cells = 1188 #size-cells = <0>;
2999 1189
3000 port@1 { 1190 port@1 {
3001 reg = 1191 reg = <1>;
3002 repli 1192 replicator1_out: endpoint {
3003 1193 remote-endpoint = <&swao_funnel_in>;
3004 }; 1194 };
3005 }; 1195 };
3006 }; 1196 };
3007 1197
3008 in-ports { 1198 in-ports {
>> 1199 #address-cells = <1>;
>> 1200 #size-cells = <0>;
3009 1201
3010 port { !! 1202 port@1 {
>> 1203 reg = <1>;
3011 repli 1204 replicator1_in: endpoint {
3012 1205 remote-endpoint = <&replicator_out1>;
3013 }; 1206 };
3014 }; 1207 };
3015 }; 1208 };
3016 }; 1209 };
3017 1210
3018 funnel@6b08000 { 1211 funnel@6b08000 {
3019 compatible = "arm,cor 1212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 1213 reg = <0 0x06b08000 0 0x1000>;
3021 1214
3022 clocks = <&aoss_qmp>; 1215 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 1216 clock-names = "apb_pclk";
3024 1217
3025 out-ports { 1218 out-ports {
3026 port { 1219 port {
3027 swao_ 1220 swao_funnel_out: endpoint {
3028 1221 remote-endpoint = <&swao_etf_in>;
3029 }; 1222 };
3030 }; 1223 };
3031 }; 1224 };
3032 1225
3033 in-ports { 1226 in-ports {
3034 #address-cell 1227 #address-cells = <1>;
3035 #size-cells = 1228 #size-cells = <0>;
3036 1229
3037 port@6 { 1230 port@6 {
3038 reg = 1231 reg = <6>;
3039 swao_ 1232 swao_funnel_in: endpoint {
3040 1233 remote-endpoint = <&replicator1_out>;
3041 }; 1234 };
3042 }; 1235 };
3043 }; 1236 };
3044 }; 1237 };
3045 1238
3046 etf@6b09000 { 1239 etf@6b09000 {
3047 compatible = "arm,cor 1240 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 1241 reg = <0 0x06b09000 0 0x1000>;
3049 1242
3050 clocks = <&aoss_qmp>; 1243 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 1244 clock-names = "apb_pclk";
3052 1245
3053 out-ports { 1246 out-ports {
3054 port { 1247 port {
3055 swao_ 1248 swao_etf_out: endpoint {
3056 1249 remote-endpoint = <&swao_replicator_in>;
3057 }; 1250 };
3058 }; 1251 };
3059 }; 1252 };
3060 1253
3061 in-ports { 1254 in-ports {
3062 port { 1255 port {
3063 swao_ 1256 swao_etf_in: endpoint {
3064 1257 remote-endpoint = <&swao_funnel_out>;
3065 }; 1258 };
3066 }; 1259 };
3067 }; 1260 };
3068 }; 1261 };
3069 1262
3070 replicator@6b0a000 { 1263 replicator@6b0a000 {
3071 compatible = "arm,cor 1264 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 1265 reg = <0 0x06b0a000 0 0x1000>;
3073 1266
3074 clocks = <&aoss_qmp>; 1267 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 1268 clock-names = "apb_pclk";
3076 qcom,replicator-loses 1269 qcom,replicator-loses-context;
3077 1270
3078 out-ports { 1271 out-ports {
3079 port { 1272 port {
3080 swao_ 1273 swao_replicator_out: endpoint {
3081 1274 remote-endpoint = <&funnel1_in4>;
3082 }; 1275 };
3083 }; 1276 };
3084 }; 1277 };
3085 1278
3086 in-ports { 1279 in-ports {
3087 port { 1280 port {
3088 swao_ 1281 swao_replicator_in: endpoint {
3089 1282 remote-endpoint = <&swao_etf_out>;
3090 }; 1283 };
3091 }; 1284 };
3092 }; 1285 };
3093 }; 1286 };
3094 1287
3095 etm@7040000 { 1288 etm@7040000 {
3096 compatible = "arm,cor 1289 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 1290 reg = <0 0x07040000 0 0x1000>;
3098 1291
3099 cpu = <&CPU0>; 1292 cpu = <&CPU0>;
3100 1293
3101 clocks = <&aoss_qmp>; 1294 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 1295 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 1296 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 1297 qcom,skip-power-up;
3105 1298
3106 out-ports { 1299 out-ports {
3107 port { 1300 port {
3108 etm0_ 1301 etm0_out: endpoint {
3109 1302 remote-endpoint = <&apss_funnel_in0>;
3110 }; 1303 };
3111 }; 1304 };
3112 }; 1305 };
3113 }; 1306 };
3114 1307
3115 etm@7140000 { 1308 etm@7140000 {
3116 compatible = "arm,cor 1309 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 1310 reg = <0 0x07140000 0 0x1000>;
3118 1311
3119 cpu = <&CPU1>; 1312 cpu = <&CPU1>;
3120 1313
3121 clocks = <&aoss_qmp>; 1314 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 1315 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 1316 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 1317 qcom,skip-power-up;
3125 1318
3126 out-ports { 1319 out-ports {
3127 port { 1320 port {
3128 etm1_ 1321 etm1_out: endpoint {
3129 1322 remote-endpoint = <&apss_funnel_in1>;
3130 }; 1323 };
3131 }; 1324 };
3132 }; 1325 };
3133 }; 1326 };
3134 1327
3135 etm@7240000 { 1328 etm@7240000 {
3136 compatible = "arm,cor 1329 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 1330 reg = <0 0x07240000 0 0x1000>;
3138 1331
3139 cpu = <&CPU2>; 1332 cpu = <&CPU2>;
3140 1333
3141 clocks = <&aoss_qmp>; 1334 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 1335 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 1336 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 1337 qcom,skip-power-up;
3145 1338
3146 out-ports { 1339 out-ports {
3147 port { 1340 port {
3148 etm2_ 1341 etm2_out: endpoint {
3149 1342 remote-endpoint = <&apss_funnel_in2>;
3150 }; 1343 };
3151 }; 1344 };
3152 }; 1345 };
3153 }; 1346 };
3154 1347
3155 etm@7340000 { 1348 etm@7340000 {
3156 compatible = "arm,cor 1349 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 1350 reg = <0 0x07340000 0 0x1000>;
3158 1351
3159 cpu = <&CPU3>; 1352 cpu = <&CPU3>;
3160 1353
3161 clocks = <&aoss_qmp>; 1354 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 1355 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 1356 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 1357 qcom,skip-power-up;
3165 1358
3166 out-ports { 1359 out-ports {
3167 port { 1360 port {
3168 etm3_ 1361 etm3_out: endpoint {
3169 1362 remote-endpoint = <&apss_funnel_in3>;
3170 }; 1363 };
3171 }; 1364 };
3172 }; 1365 };
3173 }; 1366 };
3174 1367
3175 etm@7440000 { 1368 etm@7440000 {
3176 compatible = "arm,cor 1369 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 1370 reg = <0 0x07440000 0 0x1000>;
3178 1371
3179 cpu = <&CPU4>; 1372 cpu = <&CPU4>;
3180 1373
3181 clocks = <&aoss_qmp>; 1374 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 1375 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 1376 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 1377 qcom,skip-power-up;
3185 1378
3186 out-ports { 1379 out-ports {
3187 port { 1380 port {
3188 etm4_ 1381 etm4_out: endpoint {
3189 1382 remote-endpoint = <&apss_funnel_in4>;
3190 }; 1383 };
3191 }; 1384 };
3192 }; 1385 };
3193 }; 1386 };
3194 1387
3195 etm@7540000 { 1388 etm@7540000 {
3196 compatible = "arm,cor 1389 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 1390 reg = <0 0x07540000 0 0x1000>;
3198 1391
3199 cpu = <&CPU5>; 1392 cpu = <&CPU5>;
3200 1393
3201 clocks = <&aoss_qmp>; 1394 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 1395 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 1396 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 1397 qcom,skip-power-up;
3205 1398
3206 out-ports { 1399 out-ports {
3207 port { 1400 port {
3208 etm5_ 1401 etm5_out: endpoint {
3209 1402 remote-endpoint = <&apss_funnel_in5>;
3210 }; 1403 };
3211 }; 1404 };
3212 }; 1405 };
3213 }; 1406 };
3214 1407
3215 etm@7640000 { 1408 etm@7640000 {
3216 compatible = "arm,cor 1409 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 1410 reg = <0 0x07640000 0 0x1000>;
3218 1411
3219 cpu = <&CPU6>; 1412 cpu = <&CPU6>;
3220 1413
3221 clocks = <&aoss_qmp>; 1414 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 1415 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 1416 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 1417 qcom,skip-power-up;
3225 1418
3226 out-ports { 1419 out-ports {
3227 port { 1420 port {
3228 etm6_ 1421 etm6_out: endpoint {
3229 1422 remote-endpoint = <&apss_funnel_in6>;
3230 }; 1423 };
3231 }; 1424 };
3232 }; 1425 };
3233 }; 1426 };
3234 1427
3235 etm@7740000 { 1428 etm@7740000 {
3236 compatible = "arm,cor 1429 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 1430 reg = <0 0x07740000 0 0x1000>;
3238 1431
3239 cpu = <&CPU7>; 1432 cpu = <&CPU7>;
3240 1433
3241 clocks = <&aoss_qmp>; 1434 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 1435 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 1436 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 1437 qcom,skip-power-up;
3245 1438
3246 out-ports { 1439 out-ports {
3247 port { 1440 port {
3248 etm7_ 1441 etm7_out: endpoint {
3249 1442 remote-endpoint = <&apss_funnel_in7>;
3250 }; 1443 };
3251 }; 1444 };
3252 }; 1445 };
3253 }; 1446 };
3254 1447
3255 funnel@7800000 { /* APSS Funn 1448 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 1449 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 1450 reg = <0 0x07800000 0 0x1000>;
3258 1451
3259 clocks = <&aoss_qmp>; 1452 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 1453 clock-names = "apb_pclk";
3261 1454
3262 out-ports { 1455 out-ports {
3263 port { 1456 port {
3264 apss_ 1457 apss_funnel_out: endpoint {
3265 1458 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 1459 };
3267 }; 1460 };
3268 }; 1461 };
3269 1462
3270 in-ports { 1463 in-ports {
3271 #address-cell 1464 #address-cells = <1>;
3272 #size-cells = 1465 #size-cells = <0>;
3273 1466
3274 port@0 { 1467 port@0 {
3275 reg = 1468 reg = <0>;
3276 apss_ 1469 apss_funnel_in0: endpoint {
3277 1470 remote-endpoint = <&etm0_out>;
3278 }; 1471 };
3279 }; 1472 };
3280 1473
3281 port@1 { 1474 port@1 {
3282 reg = 1475 reg = <1>;
3283 apss_ 1476 apss_funnel_in1: endpoint {
3284 1477 remote-endpoint = <&etm1_out>;
3285 }; 1478 };
3286 }; 1479 };
3287 1480
3288 port@2 { 1481 port@2 {
3289 reg = 1482 reg = <2>;
3290 apss_ 1483 apss_funnel_in2: endpoint {
3291 1484 remote-endpoint = <&etm2_out>;
3292 }; 1485 };
3293 }; 1486 };
3294 1487
3295 port@3 { 1488 port@3 {
3296 reg = 1489 reg = <3>;
3297 apss_ 1490 apss_funnel_in3: endpoint {
3298 1491 remote-endpoint = <&etm3_out>;
3299 }; 1492 };
3300 }; 1493 };
3301 1494
3302 port@4 { 1495 port@4 {
3303 reg = 1496 reg = <4>;
3304 apss_ 1497 apss_funnel_in4: endpoint {
3305 1498 remote-endpoint = <&etm4_out>;
3306 }; 1499 };
3307 }; 1500 };
3308 1501
3309 port@5 { 1502 port@5 {
3310 reg = 1503 reg = <5>;
3311 apss_ 1504 apss_funnel_in5: endpoint {
3312 1505 remote-endpoint = <&etm5_out>;
3313 }; 1506 };
3314 }; 1507 };
3315 1508
3316 port@6 { 1509 port@6 {
3317 reg = 1510 reg = <6>;
3318 apss_ 1511 apss_funnel_in6: endpoint {
3319 1512 remote-endpoint = <&etm6_out>;
3320 }; 1513 };
3321 }; 1514 };
3322 1515
3323 port@7 { 1516 port@7 {
3324 reg = 1517 reg = <7>;
3325 apss_ 1518 apss_funnel_in7: endpoint {
3326 1519 remote-endpoint = <&etm7_out>;
3327 }; 1520 };
3328 }; 1521 };
3329 }; 1522 };
3330 }; 1523 };
3331 1524
3332 funnel@7810000 { 1525 funnel@7810000 {
3333 compatible = "arm,cor 1526 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 1527 reg = <0 0x07810000 0 0x1000>;
3335 1528
3336 clocks = <&aoss_qmp>; 1529 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 1530 clock-names = "apb_pclk";
3338 1531
3339 out-ports { 1532 out-ports {
3340 port { 1533 port {
3341 apss_ 1534 apss_merge_funnel_out: endpoint {
3342 1535 remote-endpoint = <&funnel2_in2>;
3343 }; 1536 };
3344 }; 1537 };
3345 }; 1538 };
3346 1539
3347 in-ports { 1540 in-ports {
3348 port { 1541 port {
3349 apss_ 1542 apss_merge_funnel_in: endpoint {
3350 1543 remote-endpoint = <&apss_funnel_out>;
3351 }; 1544 };
3352 }; 1545 };
3353 }; 1546 };
3354 }; 1547 };
3355 1548
3356 remoteproc_cdsp: remoteproc@8 1549 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 1550 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 1551 reg = <0x0 0x08300000 0x0 0x4040>;
3359 1552
3360 interrupts-extended = 1553 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 1554 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 1555 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 1556 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 1557 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 1558 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 1559 "handover", "stop-ack";
3367 1560
3368 clocks = <&rpmhcc RPM 1561 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 1562 clock-names = "xo";
3370 1563
3371 power-domains = <&rpm !! 1564 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 1565 <&rpmhpd 7>;
>> 1566 power-domain-names = "load_state", "cx";
3372 1567
3373 memory-region = <&cds 1568 memory-region = <&cdsp_mem>;
3374 1569
3375 qcom,qmp = <&aoss_qmp <<
3376 <<
3377 qcom,smem-states = <& 1570 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 1571 qcom,smem-state-names = "stop";
3379 1572
3380 status = "disabled"; 1573 status = "disabled";
3381 1574
3382 glink-edge { 1575 glink-edge {
3383 interrupts = 1576 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 1577 label = "cdsp";
3385 qcom,remote-p 1578 qcom,remote-pid = <5>;
3386 mboxes = <&ap 1579 mboxes = <&apss_shared 4>;
3387 <<
3388 fastrpc { <<
3389 compa <<
3390 qcom, <<
3391 label <<
3392 qcom, <<
3393 #addr <<
3394 #size <<
3395 <<
3396 compu <<
3397 <<
3398 <<
3399 <<
3400 }; <<
3401 <<
3402 compu <<
3403 <<
3404 <<
3405 <<
3406 }; <<
3407 <<
3408 compu <<
3409 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 compu <<
3415 <<
3416 <<
3417 <<
3418 }; <<
3419 <<
3420 compu <<
3421 <<
3422 <<
3423 <<
3424 }; <<
3425 <<
3426 compu <<
3427 <<
3428 <<
3429 <<
3430 }; <<
3431 <<
3432 compu <<
3433 <<
3434 <<
3435 <<
3436 }; <<
3437 <<
3438 compu <<
3439 <<
3440 <<
3441 <<
3442 }; <<
3443 <<
3444 /* no <<
3445 }; <<
3446 }; 1580 };
3447 }; 1581 };
3448 1582
3449 usb_1_hsphy: phy@88e2000 { 1583 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 1584 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 1585 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 1586 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 1587 status = "disabled";
3454 #phy-cells = <0>; 1588 #phy-cells = <0>;
3455 1589
3456 clocks = <&rpmhcc RPM 1590 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 1591 clock-names = "ref";
3458 1592
3459 resets = <&gcc GCC_QU 1593 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 1594 };
3461 1595
3462 usb_2_hsphy: phy@88e3000 { 1596 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 1597 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 1598 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 1599 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 1600 status = "disabled";
3467 #phy-cells = <0>; 1601 #phy-cells = <0>;
3468 1602
3469 clocks = <&rpmhcc RPM 1603 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 1604 clock-names = "ref";
3471 1605
3472 resets = <&gcc GCC_QU 1606 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 1607 };
3474 1608
3475 usb_1_qmpphy: phy@88e8000 { !! 1609 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 1610 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 1611 reg = <0 0x088e9000 0 0x18c>,
>> 1612 <0 0x088e8000 0 0x10>;
>> 1613 reg-names = "reg-base", "dp_com";
>> 1614 status = "disabled";
>> 1615 #clock-cells = <1>;
>> 1616 #address-cells = <2>;
>> 1617 #size-cells = <2>;
>> 1618 ranges;
3478 1619
3479 clocks = <&gcc GCC_US 1620 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 1621 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 1622 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 1623 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 1624 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 1625
3488 resets = <&gcc GCC_US 1626 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 1627 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 1628 reset-names = "phy", "common";
3491 1629
3492 #clock-cells = <1>; !! 1630 usb_1_ssphy: lanes@88e9200 {
3493 #phy-cells = <1>; !! 1631 reg = <0 0x088e9200 0 0x200>,
3494 !! 1632 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 1633 <0 0x088e9c00 0 0x218>,
3496 !! 1634 <0 0x088e9600 0 0x200>,
3497 ports { !! 1635 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 1636 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 1637 #phy-cells = <0>;
3500 !! 1638 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3501 port@0 { !! 1639 clock-names = "pipe0";
3502 reg = !! 1640 clock-output-names = "usb3_phy_pipe_clk_src";
3503 <<
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; <<
3524 }; <<
3525 <<
3526 usb_2_qmpphy: phy@88eb000 { <<
3527 compatible = "qcom,sm <<
3528 reg = <0 0x088eb000 0 <<
3529 <<
3530 clocks = <&gcc GCC_US <<
3531 <&gcc GCC_US <<
3532 <&gcc GCC_US <<
3533 <&gcc GCC_US <<
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 <<
3542 resets = <&gcc GCC_US <<
3543 <&gcc GCC_US <<
3544 reset-names = "phy", <<
3545 "phy_ph <<
3546 <<
3547 status = "disabled"; <<
3548 }; <<
3549 <<
3550 sdhc_2: mmc@8804000 { <<
3551 compatible = "qcom,sm <<
3552 reg = <0 0x08804000 0 <<
3553 <<
3554 interrupts = <GIC_SPI <<
3555 <GIC_SPI <<
3556 interrupt-names = "hc <<
3557 <<
3558 clocks = <&gcc GCC_SD <<
3559 <&gcc GCC_SD <<
3560 <&rpmhcc RPM <<
3561 clock-names = "iface" <<
3562 iommus = <&apps_smmu <<
3563 qcom,dll-config = <0x <<
3564 qcom,ddr-config = <0x <<
3565 power-domains = <&rpm <<
3566 operating-points-v2 = <<
3567 <<
3568 status = "disabled"; <<
3569 <<
3570 sdhc2_opp_table: opp- <<
3571 compatible = <<
3572 <<
3573 opp-19200000 <<
3574 opp-h <<
3575 requi <<
3576 }; <<
3577 <<
3578 opp-50000000 <<
3579 opp-h <<
3580 requi <<
3581 }; <<
3582 <<
3583 opp-100000000 <<
3584 opp-h <<
3585 requi <<
3586 }; <<
3587 <<
3588 opp-202000000 <<
3589 opp-h <<
3590 requi <<
3591 }; <<
3592 }; 1641 };
3593 }; 1642 };
3594 1643
3595 dc_noc: interconnect@9160000 1644 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 1645 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 1646 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 1647 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 1648 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 1649 };
3601 1650
3602 gem_noc: interconnect@9680000 1651 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 1652 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 1653 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 1654 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 1655 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 1656 };
3608 1657
>> 1658 usb_2_qmpphy: phy@88eb000 {
>> 1659 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
>> 1660 reg = <0 0x088eb000 0 0x200>;
>> 1661 status = "disabled";
>> 1662 #clock-cells = <1>;
>> 1663 #address-cells = <2>;
>> 1664 #size-cells = <2>;
>> 1665 ranges;
>> 1666
>> 1667 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 1668 <&rpmhcc RPMH_CXO_CLK>,
>> 1669 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
>> 1670 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
>> 1671 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
>> 1672
>> 1673 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
>> 1674 <&gcc GCC_USB3_PHY_SEC_BCR>;
>> 1675 reset-names = "phy", "common";
>> 1676
>> 1677 usb_2_ssphy: lane@88eb200 {
>> 1678 reg = <0 0x088eb200 0 0x200>,
>> 1679 <0 0x088eb400 0 0x200>,
>> 1680 <0 0x088eb800 0 0x800>,
>> 1681 <0 0x088eb600 0 0x200>;
>> 1682 #phy-cells = <0>;
>> 1683 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 1684 clock-names = "pipe0";
>> 1685 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 1686 };
>> 1687 };
>> 1688
3609 usb_1: usb@a6f8800 { 1689 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 1690 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 1691 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 1692 status = "disabled";
3613 #address-cells = <2>; 1693 #address-cells = <2>;
3614 #size-cells = <2>; 1694 #size-cells = <2>;
3615 ranges; 1695 ranges;
3616 dma-ranges; 1696 dma-ranges;
3617 1697
3618 clocks = <&gcc GCC_CF 1698 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 1699 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 1700 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US <<
3622 <&gcc GCC_US 1701 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 1702 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3623 <&gcc GCC_US 1703 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no !! 1704 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3625 "core", !! 1705 "sleep", "xo";
3626 "iface" <<
3627 "sleep" <<
3628 "mock_u <<
3629 "xo"; <<
3630 1706
3631 assigned-clocks = <&g 1707 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 1708 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 1709 assigned-clock-rates = <19200000>, <200000000>;
3634 1710
3635 interrupts-extended = !! 1711 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 1712 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 1713 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 1714 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 1715 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 1716 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 1717
3646 power-domains = <&gcc 1718 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 1719
3648 resets = <&gcc GCC_US 1720 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 1721
3650 interconnects = <&agg !! 1722 usb_1_dwc3: dwc3@a600000 {
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 <<
3655 compatible = 1723 compatible = "snps,dwc3";
3656 reg = <0 0x0a 1724 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 1725 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 1726 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 1727 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 1728 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 1729 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 1730 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 1731 };
3684 }; 1732 };
3685 1733
3686 usb_2: usb@a8f8800 { 1734 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 1735 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 1736 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 1737 status = "disabled";
3690 #address-cells = <2>; 1738 #address-cells = <2>;
3691 #size-cells = <2>; 1739 #size-cells = <2>;
3692 ranges; 1740 ranges;
3693 dma-ranges; 1741 dma-ranges;
3694 1742
3695 clocks = <&gcc GCC_CF 1743 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 1744 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 1745 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US <<
3699 <&gcc GCC_US 1746 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 1747 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3700 <&gcc GCC_US 1748 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no !! 1749 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3702 "core", !! 1750 "sleep", "xo";
3703 "iface" <<
3704 "sleep" <<
3705 "mock_u <<
3706 "xo"; <<
3707 1751
3708 assigned-clocks = <&g 1752 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 1753 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 1754 assigned-clock-rates = <19200000>, <200000000>;
3711 1755
3712 interrupts-extended = !! 1756 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 1757 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 1758 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 1759 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 1760 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 1761 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 1762
3723 power-domains = <&gcc 1763 power-domains = <&gcc USB30_SEC_GDSC>;
3724 1764
3725 resets = <&gcc GCC_US 1765 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 1766
3727 interconnects = <&agg !! 1767 usb_2_dwc3: dwc3@a800000 {
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 <<
3732 compatible = 1768 compatible = "snps,dwc3";
3733 reg = <0 0x0a 1769 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 1770 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 1771 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 1772 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 1773 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 1774 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 1775 phy-names = "usb2-phy", "usb3-phy";
3740 }; 1776 };
3741 }; 1777 };
3742 1778
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 1779 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 1780 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 1781 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 1782 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 1783 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 1784 };
3762 1785
3763 camcc: clock-controller@ad000 !! 1786 aoss_qmp: power-controller@c300000 {
3764 compatible = "qcom,sm !! 1787 compatible = "qcom,sm8150-aoss-qmp";
3765 reg = <0 0x0ad00000 0 !! 1788 reg = <0x0 0x0c300000 0x0 0x100000>;
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 <<
4150 compatible = "qcom,sm <<
4151 reg = <0 0x0b220000 0 <<
4152 qcom,pdc-ranges = <0 <<
4153 <12 <<
4154 #interrupt-cells = <2 <<
4155 interrupt-parent = <& <<
4156 interrupt-controller; <<
4157 }; <<
4158 <<
4159 aoss_qmp: power-management@c3 <<
4160 compatible = "qcom,sm <<
4161 reg = <0x0 0x0c300000 <<
4162 interrupts = <GIC_SPI 1789 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 1790 mboxes = <&apss_shared 0>;
4164 1791
4165 #clock-cells = <0>; 1792 #clock-cells = <0>;
4166 }; !! 1793 #power-domain-cells = <1>;
4167 <<
4168 sram@c3f0000 { <<
4169 compatible = "qcom,rp <<
4170 reg = <0 0x0c3f0000 0 <<
4171 }; 1794 };
4172 1795
4173 tsens0: thermal-sensor@c26300 1796 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 1797 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 1798 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 1799 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 1800 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 1801 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 1802 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 1803 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 1804 #thermal-sensor-cells = <1>;
4182 }; 1805 };
4183 1806
4184 tsens1: thermal-sensor@c26500 1807 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 1808 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 1809 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 1810 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 1811 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 1812 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 1813 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 1814 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 1815 #thermal-sensor-cells = <1>;
4193 }; 1816 };
4194 1817
4195 spmi_bus: spmi@c440000 { 1818 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 1819 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 1820 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 1821 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 1822 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 1823 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 1824 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 1825 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 1826 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 1827 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 1828 qcom,ee = <0>;
4206 qcom,channel = <0>; 1829 qcom,channel = <0>;
4207 #address-cells = <2>; 1830 #address-cells = <2>;
4208 #size-cells = <0>; 1831 #size-cells = <0>;
4209 interrupt-controller; 1832 interrupt-controller;
4210 #interrupt-cells = <4 1833 #interrupt-cells = <4>;
>> 1834 cell-index = <0>;
4211 }; 1835 };
4212 1836
4213 apps_smmu: iommu@15000000 { 1837 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 1838 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 1839 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 1840 #iommu-cells = <2>;
4217 #global-interrupts = 1841 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 1842 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 1843 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 1844 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 1845 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 1846 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 1847 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 1848 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 1849 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 1850 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 1851 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 1852 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 1853 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 1854 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 1855 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 1856 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 1857 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 1858 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 1859 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 1860 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 1861 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 1862 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 1863 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 1864 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 1865 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 1866 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 1867 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 1868 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 1869 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 1870 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 1871 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 1872 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 1873 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 1874 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 1875 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 1876 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 1877 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 1878 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 1879 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 1880 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 1881 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 1882 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 1883 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 1884 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 1885 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 1886 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 1887 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 1888 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 1889 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 1890 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 1891 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 1892 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 1893 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 1894 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 1895 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 1896 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 1897 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 1898 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 1899 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 1900 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 1901 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 1902 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 1903 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 1904 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 1905 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 1906 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 1907 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 1908 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 1909 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 1910 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 1911 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 1912 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 1913 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 1914 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 1915 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 1916 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 1917 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 1918 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 1919 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 1920 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 1921 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 1922 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 1923 };
4300 1924
4301 remoteproc_adsp: remoteproc@1 1925 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 1926 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 1927 reg = <0x0 0x17300000 0x0 0x4040>;
4304 1928
4305 interrupts-extended = 1929 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 1930 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 1931 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 1932 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 1933 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 1934 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 1935 "handover", "stop-ack";
4312 1936
4313 clocks = <&rpmhcc RPM 1937 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 1938 clock-names = "xo";
4315 1939
4316 power-domains = <&rpm !! 1940 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
>> 1941 <&rpmhpd 7>;
>> 1942 power-domain-names = "load_state", "cx";
4317 1943
4318 memory-region = <&ads 1944 memory-region = <&adsp_mem>;
4319 1945
4320 qcom,qmp = <&aoss_qmp <<
4321 <<
4322 qcom,smem-states = <& 1946 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 1947 qcom,smem-state-names = "stop";
4324 1948
4325 status = "disabled"; 1949 status = "disabled";
4326 1950
4327 glink-edge { 1951 glink-edge {
4328 interrupts = 1952 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 1953 label = "lpass";
4330 qcom,remote-p 1954 qcom,remote-pid = <2>;
4331 mboxes = <&ap 1955 mboxes = <&apss_shared 8>;
4332 <<
4333 fastrpc { <<
4334 compa <<
4335 qcom, <<
4336 label <<
4337 qcom, <<
4338 #addr <<
4339 #size <<
4340 <<
4341 compu <<
4342 <<
4343 <<
4344 <<
4345 }; <<
4346 <<
4347 compu <<
4348 <<
4349 <<
4350 <<
4351 }; <<
4352 <<
4353 compu <<
4354 <<
4355 <<
4356 <<
4357 }; <<
4358 }; <<
4359 }; 1956 };
4360 }; 1957 };
4361 1958
4362 intc: interrupt-controller@17 1959 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 1960 compatible = "arm,gic-v3";
4364 interrupt-controller; 1961 interrupt-controller;
4365 #interrupt-cells = <3 1962 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 1963 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 1964 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 1965 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 1966 };
4370 1967
4371 apss_shared: mailbox@17c00000 1968 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 1969 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 1970 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 1971 #mbox-cells = <1>;
4376 }; 1972 };
4377 1973
4378 watchdog@17c10000 { 1974 watchdog@17c10000 {
4379 compatible = "qcom,ap 1975 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 1976 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 1977 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 1978 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 1979 };
4384 1980
4385 timer@17c20000 { 1981 timer@17c20000 {
4386 #address-cells = <1>; !! 1982 #address-cells = <2>;
4387 #size-cells = <1>; !! 1983 #size-cells = <2>;
4388 ranges = <0 0 0 0x200 !! 1984 ranges;
4389 compatible = "arm,arm 1985 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 1986 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 1987 clock-frequency = <19200000>;
4392 1988
4393 frame@17c21000 { !! 1989 frame@17c21000{
4394 frame-number 1990 frame-number = <0>;
4395 interrupts = 1991 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 1992 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 !! 1993 reg = <0x0 0x17c21000 0x0 0x1000>,
4398 <0x17c2 !! 1994 <0x0 0x17c22000 0x0 0x1000>;
4399 }; 1995 };
4400 1996
4401 frame@17c23000 { 1997 frame@17c23000 {
4402 frame-number 1998 frame-number = <1>;
4403 interrupts = 1999 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 !! 2000 reg = <0x0 0x17c23000 0x0 0x1000>;
4405 status = "dis 2001 status = "disabled";
4406 }; 2002 };
4407 2003
4408 frame@17c25000 { 2004 frame@17c25000 {
4409 frame-number 2005 frame-number = <2>;
4410 interrupts = 2006 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 !! 2007 reg = <0x0 0x17c25000 0x0 0x1000>;
4412 status = "dis 2008 status = "disabled";
4413 }; 2009 };
4414 2010
4415 frame@17c27000 { 2011 frame@17c27000 {
4416 frame-number 2012 frame-number = <3>;
4417 interrupts = 2013 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 !! 2014 reg = <0x0 0x17c26000 0x0 0x1000>;
4419 status = "dis 2015 status = "disabled";
4420 }; 2016 };
4421 2017
4422 frame@17c29000 { 2018 frame@17c29000 {
4423 frame-number 2019 frame-number = <4>;
4424 interrupts = 2020 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 !! 2021 reg = <0x0 0x17c29000 0x0 0x1000>;
4426 status = "dis 2022 status = "disabled";
4427 }; 2023 };
4428 2024
4429 frame@17c2b000 { 2025 frame@17c2b000 {
4430 frame-number 2026 frame-number = <5>;
4431 interrupts = 2027 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 !! 2028 reg = <0x0 0x17c2b000 0x0 0x1000>;
4433 status = "dis 2029 status = "disabled";
4434 }; 2030 };
4435 2031
4436 frame@17c2d000 { 2032 frame@17c2d000 {
4437 frame-number 2033 frame-number = <6>;
4438 interrupts = 2034 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 !! 2035 reg = <0x0 0x17c2d000 0x0 0x1000>;
4440 status = "dis 2036 status = "disabled";
4441 }; 2037 };
4442 }; 2038 };
4443 2039
4444 apps_rsc: rsc@18200000 { 2040 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 2041 label = "apps_rsc";
4446 compatible = "qcom,rp 2042 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 2043 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 2044 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 2045 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 2046 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 2047 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 2048 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 2049 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 2050 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 2051 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 2052 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL !! 2053 <SLEEP_TCS 1>,
4458 <WA !! 2054 <WAKE_TCS 1>,
4459 <CO !! 2055 <CONTROL_TCS 0>;
4460 power-domains = <&CLU <<
4461 2056
4462 rpmhcc: clock-control 2057 rpmhcc: clock-controller {
4463 compatible = 2058 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 2059 #clock-cells = <1>;
4465 clock-names = 2060 clock-names = "xo";
4466 clocks = <&xo 2061 clocks = <&xo_board>;
4467 }; 2062 };
4468 2063
4469 rpmhpd: power-control 2064 rpmhpd: power-controller {
4470 compatible = 2065 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 2066 #power-domain-cells = <1>;
4472 operating-poi 2067 operating-points-v2 = <&rpmhpd_opp_table>;
4473 2068
4474 rpmhpd_opp_ta 2069 rpmhpd_opp_table: opp-table {
4475 compa 2070 compatible = "operating-points-v2";
4476 2071
4477 rpmhp 2072 rpmhpd_opp_ret: opp1 {
4478 2073 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 2074 };
4480 2075
4481 rpmhp 2076 rpmhpd_opp_min_svs: opp2 {
4482 2077 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 2078 };
4484 2079
4485 rpmhp 2080 rpmhpd_opp_low_svs: opp3 {
4486 2081 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 2082 };
4488 2083
4489 rpmhp 2084 rpmhpd_opp_svs: opp4 {
4490 2085 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 2086 };
4492 2087
4493 rpmhp 2088 rpmhpd_opp_svs_l1: opp5 {
4494 2089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 2090 };
4496 2091
4497 rpmhp 2092 rpmhpd_opp_svs_l2: opp6 {
4498 2093 opp-level = <224>;
4499 }; 2094 };
4500 2095
4501 rpmhp 2096 rpmhpd_opp_nom: opp7 {
4502 2097 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 2098 };
4504 2099
4505 rpmhp 2100 rpmhpd_opp_nom_l1: opp8 {
4506 2101 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 2102 };
4508 2103
4509 rpmhp 2104 rpmhpd_opp_nom_l2: opp9 {
4510 2105 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 2106 };
4512 2107
4513 rpmhp 2108 rpmhpd_opp_turbo: opp10 {
4514 2109 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 2110 };
4516 2111
4517 rpmhp 2112 rpmhpd_opp_turbo_l1: opp11 {
4518 2113 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 2114 };
4520 }; 2115 };
4521 }; 2116 };
4522 2117
4523 apps_bcm_voter: bcm-v !! 2118 apps_bcm_voter: bcm_voter {
4524 compatible = 2119 compatible = "qcom,bcm-voter";
4525 }; 2120 };
4526 }; 2121 };
4527 2122
4528 osm_l3: interconnect@18321000 2123 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 2124 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 2125 reg = <0 0x18321000 0 0x1400>;
4531 2126
4532 clocks = <&rpmhcc RPM 2127 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 2128 clock-names = "xo", "alternate";
4534 2129
4535 #interconnect-cells = 2130 #interconnect-cells = <1>;
4536 }; 2131 };
4537 2132
4538 cpufreq_hw: cpufreq@18323000 2133 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 2134 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 2135 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 2136 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 2137 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 2138 "freq-domain2";
4544 2139
4545 clocks = <&rpmhcc RPM 2140 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 2141 clock-names = "xo", "alternate";
4547 2142
4548 #freq-domain-cells = 2143 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; <<
4551 <<
4552 lmh_cluster1: lmh@18350800 { <<
4553 compatible = "qcom,sm <<
4554 reg = <0 0x18350800 0 <<
4555 interrupts = <GIC_SPI <<
4556 cpus = <&CPU4>; <<
4557 qcom,lmh-temp-arm-mil <<
4558 qcom,lmh-temp-low-mil <<
4559 qcom,lmh-temp-high-mi <<
4560 interrupt-controller; <<
4561 #interrupt-cells = <1 <<
4562 }; <<
4563 <<
4564 lmh_cluster0: lmh@18358800 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x18358800 0 <<
4567 interrupts = <GIC_SPI <<
4568 cpus = <&CPU0>; <<
4569 qcom,lmh-temp-arm-mil <<
4570 qcom,lmh-temp-low-mil <<
4571 qcom,lmh-temp-high-mi <<
4572 interrupt-controller; <<
4573 #interrupt-cells = <1 <<
4574 }; 2144 };
4575 2145
4576 wifi: wifi@18800000 { 2146 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 2147 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 2148 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 2149 reg-names = "membase";
4580 memory-region = <&wla 2150 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 2151 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 2152 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 2153 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 2154 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 2155 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 2156 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 2157 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 2158 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 2159 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 2160 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 2161 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 2162 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 2163 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 2164 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 2165 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 2166 status = "disabled";
4597 }; 2167 };
4598 }; 2168 };
4599 2169
4600 timer { 2170 timer {
4601 compatible = "arm,armv8-timer 2171 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 2172 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 2173 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 2174 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 2175 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 2176 };
4607 2177
4608 thermal-zones { 2178 thermal-zones {
4609 cpu0-thermal { 2179 cpu0-thermal {
4610 polling-delay-passive 2180 polling-delay-passive = <250>;
>> 2181 polling-delay = <1000>;
4611 2182
4612 thermal-sensors = <&t 2183 thermal-sensors = <&tsens0 1>;
4613 2184
4614 trips { 2185 trips {
4615 cpu0_alert0: 2186 cpu0_alert0: trip-point0 {
4616 tempe 2187 temperature = <90000>;
4617 hyste 2188 hysteresis = <2000>;
4618 type 2189 type = "passive";
4619 }; 2190 };
4620 2191
4621 cpu0_alert1: 2192 cpu0_alert1: trip-point1 {
4622 tempe 2193 temperature = <95000>;
4623 hyste 2194 hysteresis = <2000>;
4624 type 2195 type = "passive";
4625 }; 2196 };
4626 2197
4627 cpu0_crit: cp !! 2198 cpu0_crit: cpu_crit {
4628 tempe 2199 temperature = <110000>;
4629 hyste 2200 hysteresis = <1000>;
4630 type 2201 type = "critical";
4631 }; 2202 };
4632 }; 2203 };
4633 2204
4634 cooling-maps { 2205 cooling-maps {
4635 map0 { 2206 map0 {
4636 trip 2207 trip = <&cpu0_alert0>;
4637 cooli 2208 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 2209 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 2210 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 2211 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 2212 };
4642 map1 { 2213 map1 {
4643 trip 2214 trip = <&cpu0_alert1>;
4644 cooli 2215 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 2216 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 2217 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 2218 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 2219 };
4649 }; 2220 };
4650 }; 2221 };
4651 2222
4652 cpu1-thermal { 2223 cpu1-thermal {
4653 polling-delay-passive 2224 polling-delay-passive = <250>;
>> 2225 polling-delay = <1000>;
4654 2226
4655 thermal-sensors = <&t 2227 thermal-sensors = <&tsens0 2>;
4656 2228
4657 trips { 2229 trips {
4658 cpu1_alert0: 2230 cpu1_alert0: trip-point0 {
4659 tempe 2231 temperature = <90000>;
4660 hyste 2232 hysteresis = <2000>;
4661 type 2233 type = "passive";
4662 }; 2234 };
4663 2235
4664 cpu1_alert1: 2236 cpu1_alert1: trip-point1 {
4665 tempe 2237 temperature = <95000>;
4666 hyste 2238 hysteresis = <2000>;
4667 type 2239 type = "passive";
4668 }; 2240 };
4669 2241
4670 cpu1_crit: cp !! 2242 cpu1_crit: cpu_crit {
4671 tempe 2243 temperature = <110000>;
4672 hyste 2244 hysteresis = <1000>;
4673 type 2245 type = "critical";
4674 }; 2246 };
4675 }; 2247 };
4676 2248
4677 cooling-maps { 2249 cooling-maps {
4678 map0 { 2250 map0 {
4679 trip 2251 trip = <&cpu1_alert0>;
4680 cooli 2252 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 2253 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 2254 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 2255 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 2256 };
4685 map1 { 2257 map1 {
4686 trip 2258 trip = <&cpu1_alert1>;
4687 cooli 2259 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 2260 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 2261 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 2262 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 2263 };
4692 }; 2264 };
4693 }; 2265 };
4694 2266
4695 cpu2-thermal { 2267 cpu2-thermal {
4696 polling-delay-passive 2268 polling-delay-passive = <250>;
>> 2269 polling-delay = <1000>;
4697 2270
4698 thermal-sensors = <&t 2271 thermal-sensors = <&tsens0 3>;
4699 2272
4700 trips { 2273 trips {
4701 cpu2_alert0: 2274 cpu2_alert0: trip-point0 {
4702 tempe 2275 temperature = <90000>;
4703 hyste 2276 hysteresis = <2000>;
4704 type 2277 type = "passive";
4705 }; 2278 };
4706 2279
4707 cpu2_alert1: 2280 cpu2_alert1: trip-point1 {
4708 tempe 2281 temperature = <95000>;
4709 hyste 2282 hysteresis = <2000>;
4710 type 2283 type = "passive";
4711 }; 2284 };
4712 2285
4713 cpu2_crit: cp !! 2286 cpu2_crit: cpu_crit {
4714 tempe 2287 temperature = <110000>;
4715 hyste 2288 hysteresis = <1000>;
4716 type 2289 type = "critical";
4717 }; 2290 };
4718 }; 2291 };
4719 2292
4720 cooling-maps { 2293 cooling-maps {
4721 map0 { 2294 map0 {
4722 trip 2295 trip = <&cpu2_alert0>;
4723 cooli 2296 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 2297 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 2298 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 2299 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 2300 };
4728 map1 { 2301 map1 {
4729 trip 2302 trip = <&cpu2_alert1>;
4730 cooli 2303 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 2304 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 2305 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 2306 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 2307 };
4735 }; 2308 };
4736 }; 2309 };
4737 2310
4738 cpu3-thermal { 2311 cpu3-thermal {
4739 polling-delay-passive 2312 polling-delay-passive = <250>;
>> 2313 polling-delay = <1000>;
4740 2314
4741 thermal-sensors = <&t 2315 thermal-sensors = <&tsens0 4>;
4742 2316
4743 trips { 2317 trips {
4744 cpu3_alert0: 2318 cpu3_alert0: trip-point0 {
4745 tempe 2319 temperature = <90000>;
4746 hyste 2320 hysteresis = <2000>;
4747 type 2321 type = "passive";
4748 }; 2322 };
4749 2323
4750 cpu3_alert1: 2324 cpu3_alert1: trip-point1 {
4751 tempe 2325 temperature = <95000>;
4752 hyste 2326 hysteresis = <2000>;
4753 type 2327 type = "passive";
4754 }; 2328 };
4755 2329
4756 cpu3_crit: cp !! 2330 cpu3_crit: cpu_crit {
4757 tempe 2331 temperature = <110000>;
4758 hyste 2332 hysteresis = <1000>;
4759 type 2333 type = "critical";
4760 }; 2334 };
4761 }; 2335 };
4762 2336
4763 cooling-maps { 2337 cooling-maps {
4764 map0 { 2338 map0 {
4765 trip 2339 trip = <&cpu3_alert0>;
4766 cooli 2340 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 2341 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 2342 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 2343 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 2344 };
4771 map1 { 2345 map1 {
4772 trip 2346 trip = <&cpu3_alert1>;
4773 cooli 2347 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 2348 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 2349 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 2350 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 2351 };
4778 }; 2352 };
4779 }; 2353 };
4780 2354
4781 cpu4-top-thermal { 2355 cpu4-top-thermal {
4782 polling-delay-passive 2356 polling-delay-passive = <250>;
>> 2357 polling-delay = <1000>;
4783 2358
4784 thermal-sensors = <&t 2359 thermal-sensors = <&tsens0 7>;
4785 2360
4786 trips { 2361 trips {
4787 cpu4_top_aler 2362 cpu4_top_alert0: trip-point0 {
4788 tempe 2363 temperature = <90000>;
4789 hyste 2364 hysteresis = <2000>;
4790 type 2365 type = "passive";
4791 }; 2366 };
4792 2367
4793 cpu4_top_aler 2368 cpu4_top_alert1: trip-point1 {
4794 tempe 2369 temperature = <95000>;
4795 hyste 2370 hysteresis = <2000>;
4796 type 2371 type = "passive";
4797 }; 2372 };
4798 2373
4799 cpu4_top_crit !! 2374 cpu4_top_crit: cpu_crit {
4800 tempe 2375 temperature = <110000>;
4801 hyste 2376 hysteresis = <1000>;
4802 type 2377 type = "critical";
4803 }; 2378 };
4804 }; 2379 };
4805 2380
4806 cooling-maps { 2381 cooling-maps {
4807 map0 { 2382 map0 {
4808 trip 2383 trip = <&cpu4_top_alert0>;
4809 cooli 2384 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 2385 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 2386 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 2387 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 2388 };
4814 map1 { 2389 map1 {
4815 trip 2390 trip = <&cpu4_top_alert1>;
4816 cooli 2391 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 2392 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 2393 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 2394 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 2395 };
4821 }; 2396 };
4822 }; 2397 };
4823 2398
4824 cpu5-top-thermal { 2399 cpu5-top-thermal {
4825 polling-delay-passive 2400 polling-delay-passive = <250>;
>> 2401 polling-delay = <1000>;
4826 2402
4827 thermal-sensors = <&t 2403 thermal-sensors = <&tsens0 8>;
4828 2404
4829 trips { 2405 trips {
4830 cpu5_top_aler 2406 cpu5_top_alert0: trip-point0 {
4831 tempe 2407 temperature = <90000>;
4832 hyste 2408 hysteresis = <2000>;
4833 type 2409 type = "passive";
4834 }; 2410 };
4835 2411
4836 cpu5_top_aler 2412 cpu5_top_alert1: trip-point1 {
4837 tempe 2413 temperature = <95000>;
4838 hyste 2414 hysteresis = <2000>;
4839 type 2415 type = "passive";
4840 }; 2416 };
4841 2417
4842 cpu5_top_crit !! 2418 cpu5_top_crit: cpu_crit {
4843 tempe 2419 temperature = <110000>;
4844 hyste 2420 hysteresis = <1000>;
4845 type 2421 type = "critical";
4846 }; 2422 };
4847 }; 2423 };
4848 2424
4849 cooling-maps { 2425 cooling-maps {
4850 map0 { 2426 map0 {
4851 trip 2427 trip = <&cpu5_top_alert0>;
4852 cooli 2428 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 2429 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 2430 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 2431 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 2432 };
4857 map1 { 2433 map1 {
4858 trip 2434 trip = <&cpu5_top_alert1>;
4859 cooli 2435 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 2436 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 2437 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 2438 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 2439 };
4864 }; 2440 };
4865 }; 2441 };
4866 2442
4867 cpu6-top-thermal { 2443 cpu6-top-thermal {
4868 polling-delay-passive 2444 polling-delay-passive = <250>;
>> 2445 polling-delay = <1000>;
4869 2446
4870 thermal-sensors = <&t 2447 thermal-sensors = <&tsens0 9>;
4871 2448
4872 trips { 2449 trips {
4873 cpu6_top_aler 2450 cpu6_top_alert0: trip-point0 {
4874 tempe 2451 temperature = <90000>;
4875 hyste 2452 hysteresis = <2000>;
4876 type 2453 type = "passive";
4877 }; 2454 };
4878 2455
4879 cpu6_top_aler 2456 cpu6_top_alert1: trip-point1 {
4880 tempe 2457 temperature = <95000>;
4881 hyste 2458 hysteresis = <2000>;
4882 type 2459 type = "passive";
4883 }; 2460 };
4884 2461
4885 cpu6_top_crit !! 2462 cpu6_top_crit: cpu_crit {
4886 tempe 2463 temperature = <110000>;
4887 hyste 2464 hysteresis = <1000>;
4888 type 2465 type = "critical";
4889 }; 2466 };
4890 }; 2467 };
4891 2468
4892 cooling-maps { 2469 cooling-maps {
4893 map0 { 2470 map0 {
4894 trip 2471 trip = <&cpu6_top_alert0>;
4895 cooli 2472 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 2473 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 2474 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 2475 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 2476 };
4900 map1 { 2477 map1 {
4901 trip 2478 trip = <&cpu6_top_alert1>;
4902 cooli 2479 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 2480 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 2481 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 2482 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 2483 };
4907 }; 2484 };
4908 }; 2485 };
4909 2486
4910 cpu7-top-thermal { 2487 cpu7-top-thermal {
4911 polling-delay-passive 2488 polling-delay-passive = <250>;
>> 2489 polling-delay = <1000>;
4912 2490
4913 thermal-sensors = <&t 2491 thermal-sensors = <&tsens0 10>;
4914 2492
4915 trips { 2493 trips {
4916 cpu7_top_aler 2494 cpu7_top_alert0: trip-point0 {
4917 tempe 2495 temperature = <90000>;
4918 hyste 2496 hysteresis = <2000>;
4919 type 2497 type = "passive";
4920 }; 2498 };
4921 2499
4922 cpu7_top_aler 2500 cpu7_top_alert1: trip-point1 {
4923 tempe 2501 temperature = <95000>;
4924 hyste 2502 hysteresis = <2000>;
4925 type 2503 type = "passive";
4926 }; 2504 };
4927 2505
4928 cpu7_top_crit !! 2506 cpu7_top_crit: cpu_crit {
4929 tempe 2507 temperature = <110000>;
4930 hyste 2508 hysteresis = <1000>;
4931 type 2509 type = "critical";
4932 }; 2510 };
4933 }; 2511 };
4934 2512
4935 cooling-maps { 2513 cooling-maps {
4936 map0 { 2514 map0 {
4937 trip 2515 trip = <&cpu7_top_alert0>;
4938 cooli 2516 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 2517 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 2518 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 2519 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 2520 };
4943 map1 { 2521 map1 {
4944 trip 2522 trip = <&cpu7_top_alert1>;
4945 cooli 2523 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 2524 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 2525 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 2526 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 2527 };
4950 }; 2528 };
4951 }; 2529 };
4952 2530
4953 cpu4-bottom-thermal { 2531 cpu4-bottom-thermal {
4954 polling-delay-passive 2532 polling-delay-passive = <250>;
>> 2533 polling-delay = <1000>;
4955 2534
4956 thermal-sensors = <&t 2535 thermal-sensors = <&tsens0 11>;
4957 2536
4958 trips { 2537 trips {
4959 cpu4_bottom_a 2538 cpu4_bottom_alert0: trip-point0 {
4960 tempe 2539 temperature = <90000>;
4961 hyste 2540 hysteresis = <2000>;
4962 type 2541 type = "passive";
4963 }; 2542 };
4964 2543
4965 cpu4_bottom_a 2544 cpu4_bottom_alert1: trip-point1 {
4966 tempe 2545 temperature = <95000>;
4967 hyste 2546 hysteresis = <2000>;
4968 type 2547 type = "passive";
4969 }; 2548 };
4970 2549
4971 cpu4_bottom_c !! 2550 cpu4_bottom_crit: cpu_crit {
4972 tempe 2551 temperature = <110000>;
4973 hyste 2552 hysteresis = <1000>;
4974 type 2553 type = "critical";
4975 }; 2554 };
4976 }; 2555 };
4977 2556
4978 cooling-maps { 2557 cooling-maps {
4979 map0 { 2558 map0 {
4980 trip 2559 trip = <&cpu4_bottom_alert0>;
4981 cooli 2560 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 2561 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 2562 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 2563 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 2564 };
4986 map1 { 2565 map1 {
4987 trip 2566 trip = <&cpu4_bottom_alert1>;
4988 cooli 2567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 2568 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 2569 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 2570 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 2571 };
4993 }; 2572 };
4994 }; 2573 };
4995 2574
4996 cpu5-bottom-thermal { 2575 cpu5-bottom-thermal {
4997 polling-delay-passive 2576 polling-delay-passive = <250>;
>> 2577 polling-delay = <1000>;
4998 2578
4999 thermal-sensors = <&t 2579 thermal-sensors = <&tsens0 12>;
5000 2580
5001 trips { 2581 trips {
5002 cpu5_bottom_a 2582 cpu5_bottom_alert0: trip-point0 {
5003 tempe 2583 temperature = <90000>;
5004 hyste 2584 hysteresis = <2000>;
5005 type 2585 type = "passive";
5006 }; 2586 };
5007 2587
5008 cpu5_bottom_a 2588 cpu5_bottom_alert1: trip-point1 {
5009 tempe 2589 temperature = <95000>;
5010 hyste 2590 hysteresis = <2000>;
5011 type 2591 type = "passive";
5012 }; 2592 };
5013 2593
5014 cpu5_bottom_c !! 2594 cpu5_bottom_crit: cpu_crit {
5015 tempe 2595 temperature = <110000>;
5016 hyste 2596 hysteresis = <1000>;
5017 type 2597 type = "critical";
5018 }; 2598 };
5019 }; 2599 };
5020 2600
5021 cooling-maps { 2601 cooling-maps {
5022 map0 { 2602 map0 {
5023 trip 2603 trip = <&cpu5_bottom_alert0>;
5024 cooli 2604 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 2605 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 2606 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 2607 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 2608 };
5029 map1 { 2609 map1 {
5030 trip 2610 trip = <&cpu5_bottom_alert1>;
5031 cooli 2611 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 2612 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 2613 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 2614 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 2615 };
5036 }; 2616 };
5037 }; 2617 };
5038 2618
5039 cpu6-bottom-thermal { 2619 cpu6-bottom-thermal {
5040 polling-delay-passive 2620 polling-delay-passive = <250>;
>> 2621 polling-delay = <1000>;
5041 2622
5042 thermal-sensors = <&t 2623 thermal-sensors = <&tsens0 13>;
5043 2624
5044 trips { 2625 trips {
5045 cpu6_bottom_a 2626 cpu6_bottom_alert0: trip-point0 {
5046 tempe 2627 temperature = <90000>;
5047 hyste 2628 hysteresis = <2000>;
5048 type 2629 type = "passive";
5049 }; 2630 };
5050 2631
5051 cpu6_bottom_a 2632 cpu6_bottom_alert1: trip-point1 {
5052 tempe 2633 temperature = <95000>;
5053 hyste 2634 hysteresis = <2000>;
5054 type 2635 type = "passive";
5055 }; 2636 };
5056 2637
5057 cpu6_bottom_c !! 2638 cpu6_bottom_crit: cpu_crit {
5058 tempe 2639 temperature = <110000>;
5059 hyste 2640 hysteresis = <1000>;
5060 type 2641 type = "critical";
5061 }; 2642 };
5062 }; 2643 };
5063 2644
5064 cooling-maps { 2645 cooling-maps {
5065 map0 { 2646 map0 {
5066 trip 2647 trip = <&cpu6_bottom_alert0>;
5067 cooli 2648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 2649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 2650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 2651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 2652 };
5072 map1 { 2653 map1 {
5073 trip 2654 trip = <&cpu6_bottom_alert1>;
5074 cooli 2655 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 2656 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 2657 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 2658 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 2659 };
5079 }; 2660 };
5080 }; 2661 };
5081 2662
5082 cpu7-bottom-thermal { 2663 cpu7-bottom-thermal {
5083 polling-delay-passive 2664 polling-delay-passive = <250>;
>> 2665 polling-delay = <1000>;
5084 2666
5085 thermal-sensors = <&t 2667 thermal-sensors = <&tsens0 14>;
5086 2668
5087 trips { 2669 trips {
5088 cpu7_bottom_a 2670 cpu7_bottom_alert0: trip-point0 {
5089 tempe 2671 temperature = <90000>;
5090 hyste 2672 hysteresis = <2000>;
5091 type 2673 type = "passive";
5092 }; 2674 };
5093 2675
5094 cpu7_bottom_a 2676 cpu7_bottom_alert1: trip-point1 {
5095 tempe 2677 temperature = <95000>;
5096 hyste 2678 hysteresis = <2000>;
5097 type 2679 type = "passive";
5098 }; 2680 };
5099 2681
5100 cpu7_bottom_c !! 2682 cpu7_bottom_crit: cpu_crit {
5101 tempe 2683 temperature = <110000>;
5102 hyste 2684 hysteresis = <1000>;
5103 type 2685 type = "critical";
5104 }; 2686 };
5105 }; 2687 };
5106 2688
5107 cooling-maps { 2689 cooling-maps {
5108 map0 { 2690 map0 {
5109 trip 2691 trip = <&cpu7_bottom_alert0>;
5110 cooli 2692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 2693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 2694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 2695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 2696 };
5115 map1 { 2697 map1 {
5116 trip 2698 trip = <&cpu7_bottom_alert1>;
5117 cooli 2699 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 2700 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 2701 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 2702 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 2703 };
5122 }; 2704 };
5123 }; 2705 };
5124 2706
5125 aoss0-thermal { 2707 aoss0-thermal {
5126 polling-delay-passive 2708 polling-delay-passive = <250>;
>> 2709 polling-delay = <1000>;
5127 2710
5128 thermal-sensors = <&t 2711 thermal-sensors = <&tsens0 0>;
5129 2712
5130 trips { 2713 trips {
5131 aoss0_alert0: 2714 aoss0_alert0: trip-point0 {
5132 tempe 2715 temperature = <90000>;
5133 hyste 2716 hysteresis = <2000>;
5134 type 2717 type = "hot";
5135 }; 2718 };
5136 }; 2719 };
5137 }; 2720 };
5138 2721
5139 cluster0-thermal { 2722 cluster0-thermal {
5140 polling-delay-passive 2723 polling-delay-passive = <250>;
>> 2724 polling-delay = <1000>;
5141 2725
5142 thermal-sensors = <&t 2726 thermal-sensors = <&tsens0 5>;
5143 2727
5144 trips { 2728 trips {
5145 cluster0_aler 2729 cluster0_alert0: trip-point0 {
5146 tempe 2730 temperature = <90000>;
5147 hyste 2731 hysteresis = <2000>;
5148 type 2732 type = "hot";
5149 }; 2733 };
5150 cluster0_crit !! 2734 cluster0_crit: cluster0_crit {
5151 tempe 2735 temperature = <110000>;
5152 hyste 2736 hysteresis = <2000>;
5153 type 2737 type = "critical";
5154 }; 2738 };
5155 }; 2739 };
5156 }; 2740 };
5157 2741
5158 cluster1-thermal { 2742 cluster1-thermal {
5159 polling-delay-passive 2743 polling-delay-passive = <250>;
>> 2744 polling-delay = <1000>;
5160 2745
5161 thermal-sensors = <&t 2746 thermal-sensors = <&tsens0 6>;
5162 2747
5163 trips { 2748 trips {
5164 cluster1_aler 2749 cluster1_alert0: trip-point0 {
5165 tempe 2750 temperature = <90000>;
5166 hyste 2751 hysteresis = <2000>;
5167 type 2752 type = "hot";
5168 }; 2753 };
5169 cluster1_crit !! 2754 cluster1_crit: cluster1_crit {
5170 tempe 2755 temperature = <110000>;
5171 hyste 2756 hysteresis = <2000>;
5172 type 2757 type = "critical";
5173 }; 2758 };
5174 }; 2759 };
5175 }; 2760 };
5176 2761
5177 gpu-top-thermal { !! 2762 gpu-thermal-top {
5178 polling-delay-passive 2763 polling-delay-passive = <250>;
>> 2764 polling-delay = <1000>;
5179 2765
5180 thermal-sensors = <&t 2766 thermal-sensors = <&tsens0 15>;
5181 2767
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 2768 trips {
5190 gpu_top_alert !! 2769 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 2770 temperature = <90000>;
5198 hyste !! 2771 hysteresis = <2000>;
5199 type 2772 type = "hot";
5200 }; 2773 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 2774 };
5208 }; 2775 };
5209 2776
5210 aoss1-thermal { 2777 aoss1-thermal {
5211 polling-delay-passive 2778 polling-delay-passive = <250>;
>> 2779 polling-delay = <1000>;
5212 2780
5213 thermal-sensors = <&t 2781 thermal-sensors = <&tsens1 0>;
5214 2782
5215 trips { 2783 trips {
5216 aoss1_alert0: 2784 aoss1_alert0: trip-point0 {
5217 tempe 2785 temperature = <90000>;
5218 hyste 2786 hysteresis = <2000>;
5219 type 2787 type = "hot";
5220 }; 2788 };
5221 }; 2789 };
5222 }; 2790 };
5223 2791
5224 wlan-thermal { 2792 wlan-thermal {
5225 polling-delay-passive 2793 polling-delay-passive = <250>;
>> 2794 polling-delay = <1000>;
5226 2795
5227 thermal-sensors = <&t 2796 thermal-sensors = <&tsens1 1>;
5228 2797
5229 trips { 2798 trips {
5230 wlan_alert0: 2799 wlan_alert0: trip-point0 {
5231 tempe 2800 temperature = <90000>;
5232 hyste 2801 hysteresis = <2000>;
5233 type 2802 type = "hot";
5234 }; 2803 };
5235 }; 2804 };
5236 }; 2805 };
5237 2806
5238 video-thermal { 2807 video-thermal {
5239 polling-delay-passive 2808 polling-delay-passive = <250>;
>> 2809 polling-delay = <1000>;
5240 2810
5241 thermal-sensors = <&t 2811 thermal-sensors = <&tsens1 2>;
5242 2812
5243 trips { 2813 trips {
5244 video_alert0: 2814 video_alert0: trip-point0 {
5245 tempe 2815 temperature = <90000>;
5246 hyste 2816 hysteresis = <2000>;
5247 type 2817 type = "hot";
5248 }; 2818 };
5249 }; 2819 };
5250 }; 2820 };
5251 2821
5252 mem-thermal { 2822 mem-thermal {
5253 polling-delay-passive 2823 polling-delay-passive = <250>;
>> 2824 polling-delay = <1000>;
5254 2825
5255 thermal-sensors = <&t 2826 thermal-sensors = <&tsens1 3>;
5256 2827
5257 trips { 2828 trips {
5258 mem_alert0: t 2829 mem_alert0: trip-point0 {
5259 tempe 2830 temperature = <90000>;
5260 hyste 2831 hysteresis = <2000>;
5261 type 2832 type = "hot";
5262 }; 2833 };
5263 }; 2834 };
5264 }; 2835 };
5265 2836
5266 q6-hvx-thermal { 2837 q6-hvx-thermal {
5267 polling-delay-passive 2838 polling-delay-passive = <250>;
>> 2839 polling-delay = <1000>;
5268 2840
5269 thermal-sensors = <&t 2841 thermal-sensors = <&tsens1 4>;
5270 2842
5271 trips { 2843 trips {
5272 q6_hvx_alert0 2844 q6_hvx_alert0: trip-point0 {
5273 tempe 2845 temperature = <90000>;
5274 hyste 2846 hysteresis = <2000>;
5275 type 2847 type = "hot";
5276 }; 2848 };
5277 }; 2849 };
5278 }; 2850 };
5279 2851
5280 camera-thermal { 2852 camera-thermal {
5281 polling-delay-passive 2853 polling-delay-passive = <250>;
>> 2854 polling-delay = <1000>;
5282 2855
5283 thermal-sensors = <&t 2856 thermal-sensors = <&tsens1 5>;
5284 2857
5285 trips { 2858 trips {
5286 camera_alert0 2859 camera_alert0: trip-point0 {
5287 tempe 2860 temperature = <90000>;
5288 hyste 2861 hysteresis = <2000>;
5289 type 2862 type = "hot";
5290 }; 2863 };
5291 }; 2864 };
5292 }; 2865 };
5293 2866
5294 compute-thermal { 2867 compute-thermal {
5295 polling-delay-passive 2868 polling-delay-passive = <250>;
>> 2869 polling-delay = <1000>;
5296 2870
5297 thermal-sensors = <&t 2871 thermal-sensors = <&tsens1 6>;
5298 2872
5299 trips { 2873 trips {
5300 compute_alert 2874 compute_alert0: trip-point0 {
5301 tempe 2875 temperature = <90000>;
5302 hyste 2876 hysteresis = <2000>;
5303 type 2877 type = "hot";
5304 }; 2878 };
5305 }; 2879 };
5306 }; 2880 };
5307 2881
5308 modem-thermal { 2882 modem-thermal {
5309 polling-delay-passive 2883 polling-delay-passive = <250>;
>> 2884 polling-delay = <1000>;
5310 2885
5311 thermal-sensors = <&t 2886 thermal-sensors = <&tsens1 7>;
5312 2887
5313 trips { 2888 trips {
5314 modem_alert0: 2889 modem_alert0: trip-point0 {
5315 tempe 2890 temperature = <90000>;
5316 hyste 2891 hysteresis = <2000>;
5317 type 2892 type = "hot";
5318 }; 2893 };
5319 }; 2894 };
5320 }; 2895 };
5321 2896
5322 npu-thermal { 2897 npu-thermal {
5323 polling-delay-passive 2898 polling-delay-passive = <250>;
>> 2899 polling-delay = <1000>;
5324 2900
5325 thermal-sensors = <&t 2901 thermal-sensors = <&tsens1 8>;
5326 2902
5327 trips { 2903 trips {
5328 npu_alert0: t 2904 npu_alert0: trip-point0 {
5329 tempe 2905 temperature = <90000>;
5330 hyste 2906 hysteresis = <2000>;
5331 type 2907 type = "hot";
5332 }; 2908 };
5333 }; 2909 };
5334 }; 2910 };
5335 2911
5336 modem-vec-thermal { 2912 modem-vec-thermal {
5337 polling-delay-passive 2913 polling-delay-passive = <250>;
>> 2914 polling-delay = <1000>;
5338 2915
5339 thermal-sensors = <&t 2916 thermal-sensors = <&tsens1 9>;
5340 2917
5341 trips { 2918 trips {
5342 modem_vec_ale 2919 modem_vec_alert0: trip-point0 {
5343 tempe 2920 temperature = <90000>;
5344 hyste 2921 hysteresis = <2000>;
5345 type 2922 type = "hot";
5346 }; 2923 };
5347 }; 2924 };
5348 }; 2925 };
5349 2926
5350 modem-scl-thermal { 2927 modem-scl-thermal {
5351 polling-delay-passive 2928 polling-delay-passive = <250>;
>> 2929 polling-delay = <1000>;
5352 2930
5353 thermal-sensors = <&t 2931 thermal-sensors = <&tsens1 10>;
5354 2932
5355 trips { 2933 trips {
5356 modem_scl_ale 2934 modem_scl_alert0: trip-point0 {
5357 tempe 2935 temperature = <90000>;
5358 hyste 2936 hysteresis = <2000>;
5359 type 2937 type = "hot";
5360 }; 2938 };
5361 }; 2939 };
5362 }; 2940 };
5363 2941
5364 gpu-bottom-thermal { !! 2942 gpu-thermal-bottom {
5365 polling-delay-passive 2943 polling-delay-passive = <250>;
>> 2944 polling-delay = <1000>;
5366 2945
5367 thermal-sensors = <&t 2946 thermal-sensors = <&tsens1 11>;
5368 2947
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 2948 trips {
5377 gpu_bottom_al !! 2949 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 2950 temperature = <90000>;
5385 hyste !! 2951 hysteresis = <2000>;
5386 type 2952 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 2953 };
5394 }; 2954 };
5395 }; 2955 };
5396 }; 2956 };
5397 }; 2957 };
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