1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> <<
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 8 #include <dt-bindings/power/qcom-aoss-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 <<
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
22 16
23 / { 17 / {
24 interrupt-parent = <&intc>; 18 interrupt-parent = <&intc>;
25 19
26 #address-cells = <2>; 20 #address-cells = <2>;
27 #size-cells = <2>; 21 #size-cells = <2>;
28 22
29 chosen { }; 23 chosen { };
30 24
31 clocks { 25 clocks {
32 xo_board: xo-board { 26 xo_board: xo-board {
33 compatible = "fixed-cl 27 compatible = "fixed-clock";
34 #clock-cells = <0>; 28 #clock-cells = <0>;
35 clock-frequency = <384 29 clock-frequency = <38400000>;
36 clock-output-names = " 30 clock-output-names = "xo_board";
37 }; 31 };
38 32
39 sleep_clk: sleep-clk { 33 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 34 compatible = "fixed-clock";
41 #clock-cells = <0>; 35 #clock-cells = <0>;
42 clock-frequency = <327 36 clock-frequency = <32764>;
43 clock-output-names = " 37 clock-output-names = "sleep_clk";
44 }; 38 };
45 }; 39 };
46 40
47 cpus { 41 cpus {
48 #address-cells = <2>; 42 #address-cells = <2>;
49 #size-cells = <0>; 43 #size-cells = <0>;
50 44
51 CPU0: cpu@0 { 45 CPU0: cpu@0 {
52 device_type = "cpu"; 46 device_type = "cpu";
53 compatible = "qcom,kry 47 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 48 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 49 enable-method = "psci";
57 capacity-dmips-mhz = < 50 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 51 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 52 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 53 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = <<
62 interconnects = <&gem_ <<
63 <&osm_ <<
64 power-domains = <&CPU_ 54 power-domains = <&CPU_PD0>;
65 power-domain-names = " 55 power-domain-names = "psci";
66 #cooling-cells = <2>; 56 #cooling-cells = <2>;
67 L2_0: l2-cache { 57 L2_0: l2-cache {
68 compatible = " 58 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 59 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 60 L3_0: l3-cache {
73 compat !! 61 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 62 };
77 }; 63 };
78 }; 64 };
79 65
80 CPU1: cpu@100 { 66 CPU1: cpu@100 {
81 device_type = "cpu"; 67 device_type = "cpu";
82 compatible = "qcom,kry 68 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 69 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 70 enable-method = "psci";
86 capacity-dmips-mhz = < 71 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 72 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 73 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 74 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = <<
91 interconnects = <&gem_ <<
92 <&osm_ <<
93 power-domains = <&CPU_ 75 power-domains = <&CPU_PD1>;
94 power-domain-names = " 76 power-domain-names = "psci";
95 #cooling-cells = <2>; 77 #cooling-cells = <2>;
96 L2_100: l2-cache { 78 L2_100: l2-cache {
97 compatible = " 79 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 80 next-level-cache = <&L3_0>;
101 }; 81 };
>> 82
102 }; 83 };
103 84
104 CPU2: cpu@200 { 85 CPU2: cpu@200 {
105 device_type = "cpu"; 86 device_type = "cpu";
106 compatible = "qcom,kry 87 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 88 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 89 enable-method = "psci";
110 capacity-dmips-mhz = < 90 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 91 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 92 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 93 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = <<
115 interconnects = <&gem_ <<
116 <&osm_ <<
117 power-domains = <&CPU_ 94 power-domains = <&CPU_PD2>;
118 power-domain-names = " 95 power-domain-names = "psci";
119 #cooling-cells = <2>; 96 #cooling-cells = <2>;
120 L2_200: l2-cache { 97 L2_200: l2-cache {
121 compatible = " 98 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 99 next-level-cache = <&L3_0>;
125 }; 100 };
126 }; 101 };
127 102
128 CPU3: cpu@300 { 103 CPU3: cpu@300 {
129 device_type = "cpu"; 104 device_type = "cpu";
130 compatible = "qcom,kry 105 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 106 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 107 enable-method = "psci";
134 capacity-dmips-mhz = < 108 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 109 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 110 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 111 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <<
139 interconnects = <&gem_ <<
140 <&osm_ <<
141 power-domains = <&CPU_ 112 power-domains = <&CPU_PD3>;
142 power-domain-names = " 113 power-domain-names = "psci";
143 #cooling-cells = <2>; 114 #cooling-cells = <2>;
144 L2_300: l2-cache { 115 L2_300: l2-cache {
145 compatible = " 116 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 117 next-level-cache = <&L3_0>;
149 }; 118 };
150 }; 119 };
151 120
152 CPU4: cpu@400 { 121 CPU4: cpu@400 {
153 device_type = "cpu"; 122 device_type = "cpu";
154 compatible = "qcom,kry 123 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 124 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 125 enable-method = "psci";
158 capacity-dmips-mhz = < 126 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 127 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 128 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 129 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = <<
163 interconnects = <&gem_ <<
164 <&osm_ <<
165 power-domains = <&CPU_ 130 power-domains = <&CPU_PD4>;
166 power-domain-names = " 131 power-domain-names = "psci";
167 #cooling-cells = <2>; 132 #cooling-cells = <2>;
168 L2_400: l2-cache { 133 L2_400: l2-cache {
169 compatible = " 134 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 135 next-level-cache = <&L3_0>;
173 }; 136 };
174 }; 137 };
175 138
176 CPU5: cpu@500 { 139 CPU5: cpu@500 {
177 device_type = "cpu"; 140 device_type = "cpu";
178 compatible = "qcom,kry 141 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 142 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 143 enable-method = "psci";
182 capacity-dmips-mhz = < 144 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 145 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 146 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 147 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <<
187 interconnects = <&gem_ <<
188 <&osm_ <<
189 power-domains = <&CPU_ 148 power-domains = <&CPU_PD5>;
190 power-domain-names = " 149 power-domain-names = "psci";
191 #cooling-cells = <2>; 150 #cooling-cells = <2>;
192 L2_500: l2-cache { 151 L2_500: l2-cache {
193 compatible = " 152 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 153 next-level-cache = <&L3_0>;
197 }; 154 };
198 }; 155 };
199 156
200 CPU6: cpu@600 { 157 CPU6: cpu@600 {
201 device_type = "cpu"; 158 device_type = "cpu";
202 compatible = "qcom,kry 159 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 160 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 161 enable-method = "psci";
206 capacity-dmips-mhz = < 162 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 163 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 164 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 165 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = <<
211 interconnects = <&gem_ <<
212 <&osm_ <<
213 power-domains = <&CPU_ 166 power-domains = <&CPU_PD6>;
214 power-domain-names = " 167 power-domain-names = "psci";
215 #cooling-cells = <2>; 168 #cooling-cells = <2>;
216 L2_600: l2-cache { 169 L2_600: l2-cache {
217 compatible = " 170 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 171 next-level-cache = <&L3_0>;
221 }; 172 };
222 }; 173 };
223 174
224 CPU7: cpu@700 { 175 CPU7: cpu@700 {
225 device_type = "cpu"; 176 device_type = "cpu";
226 compatible = "qcom,kry 177 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 178 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 179 enable-method = "psci";
230 capacity-dmips-mhz = < 180 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 181 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 182 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 183 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = <<
235 interconnects = <&gem_ <<
236 <&osm_ <<
237 power-domains = <&CPU_ 184 power-domains = <&CPU_PD7>;
238 power-domain-names = " 185 power-domain-names = "psci";
239 #cooling-cells = <2>; 186 #cooling-cells = <2>;
240 L2_700: l2-cache { 187 L2_700: l2-cache {
241 compatible = " 188 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 189 next-level-cache = <&L3_0>;
245 }; 190 };
246 }; 191 };
247 192
248 cpu-map { 193 cpu-map {
249 cluster0 { 194 cluster0 {
250 core0 { 195 core0 {
251 cpu = 196 cpu = <&CPU0>;
252 }; 197 };
253 198
254 core1 { 199 core1 {
255 cpu = 200 cpu = <&CPU1>;
256 }; 201 };
257 202
258 core2 { 203 core2 {
259 cpu = 204 cpu = <&CPU2>;
260 }; 205 };
261 206
262 core3 { 207 core3 {
263 cpu = 208 cpu = <&CPU3>;
264 }; 209 };
265 210
266 core4 { 211 core4 {
267 cpu = 212 cpu = <&CPU4>;
268 }; 213 };
269 214
270 core5 { 215 core5 {
271 cpu = 216 cpu = <&CPU5>;
272 }; 217 };
273 218
274 core6 { 219 core6 {
275 cpu = 220 cpu = <&CPU6>;
276 }; 221 };
277 222
278 core7 { 223 core7 {
279 cpu = 224 cpu = <&CPU7>;
280 }; 225 };
281 }; 226 };
282 }; 227 };
283 228
284 idle-states { 229 idle-states {
285 entry-method = "psci"; 230 entry-method = "psci";
286 231
287 LITTLE_CPU_SLEEP_0: cp 232 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 233 compatible = "arm,idle-state";
289 idle-state-nam 234 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 235 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 236 entry-latency-us = <355>;
292 exit-latency-u 237 exit-latency-us = <909>;
293 min-residency- 238 min-residency-us = <3934>;
294 local-timer-st 239 local-timer-stop;
295 }; 240 };
296 241
297 BIG_CPU_SLEEP_0: cpu-s 242 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 243 compatible = "arm,idle-state";
299 idle-state-nam 244 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 245 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 246 entry-latency-us = <241>;
302 exit-latency-u 247 exit-latency-us = <1461>;
303 min-residency- 248 min-residency-us = <4488>;
304 local-timer-st 249 local-timer-stop;
305 }; 250 };
306 }; 251 };
307 252
308 domain-idle-states { 253 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 254 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 255 compatible = "domain-idle-state";
>> 256 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 257 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 258 entry-latency-us = <3263>;
313 exit-latency-u 259 exit-latency-us = <6562>;
314 min-residency- 260 min-residency-us = <9987>;
>> 261 local-timer-stop;
315 }; 262 };
316 }; 263 };
317 }; 264 };
318 265
319 cpu0_opp_table: opp-table-cpu0 { <<
320 compatible = "operating-points <<
321 opp-shared; <<
322 <<
323 cpu0_opp1: opp-300000000 { <<
324 opp-hz = /bits/ 64 <30 <<
325 opp-peak-kBps = <80000 <<
326 }; <<
327 <<
328 cpu0_opp2: opp-403200000 { <<
329 opp-hz = /bits/ 64 <40 <<
330 opp-peak-kBps = <80000 <<
331 }; <<
332 <<
333 cpu0_opp3: opp-499200000 { <<
334 opp-hz = /bits/ 64 <49 <<
335 opp-peak-kBps = <80000 <<
336 }; <<
337 <<
338 cpu0_opp4: opp-576000000 { <<
339 opp-hz = /bits/ 64 <57 <<
340 opp-peak-kBps = <80000 <<
341 }; <<
342 <<
343 cpu0_opp5: opp-672000000 { <<
344 opp-hz = /bits/ 64 <67 <<
345 opp-peak-kBps = <80000 <<
346 }; <<
347 <<
348 cpu0_opp6: opp-768000000 { <<
349 opp-hz = /bits/ 64 <76 <<
350 opp-peak-kBps = <18040 <<
351 }; <<
352 <<
353 cpu0_opp7: opp-844800000 { <<
354 opp-hz = /bits/ 64 <84 <<
355 opp-peak-kBps = <18040 <<
356 }; <<
357 <<
358 cpu0_opp8: opp-940800000 { <<
359 opp-hz = /bits/ 64 <94 <<
360 opp-peak-kBps = <18040 <<
361 }; <<
362 <<
363 cpu0_opp9: opp-1036800000 { <<
364 opp-hz = /bits/ 64 <10 <<
365 opp-peak-kBps = <18040 <<
366 }; <<
367 <<
368 cpu0_opp10: opp-1113600000 { <<
369 opp-hz = /bits/ 64 <11 <<
370 opp-peak-kBps = <21880 <<
371 }; <<
372 <<
373 cpu0_opp11: opp-1209600000 { <<
374 opp-hz = /bits/ 64 <12 <<
375 opp-peak-kBps = <21880 <<
376 }; <<
377 <<
378 cpu0_opp12: opp-1305600000 { <<
379 opp-hz = /bits/ 64 <13 <<
380 opp-peak-kBps = <30720 <<
381 }; <<
382 <<
383 cpu0_opp13: opp-1382400000 { <<
384 opp-hz = /bits/ 64 <13 <<
385 opp-peak-kBps = <30720 <<
386 }; <<
387 <<
388 cpu0_opp14: opp-1478400000 { <<
389 opp-hz = /bits/ 64 <14 <<
390 opp-peak-kBps = <30720 <<
391 }; <<
392 <<
393 cpu0_opp15: opp-1555200000 { <<
394 opp-hz = /bits/ 64 <15 <<
395 opp-peak-kBps = <30720 <<
396 }; <<
397 <<
398 cpu0_opp16: opp-1632000000 { <<
399 opp-hz = /bits/ 64 <16 <<
400 opp-peak-kBps = <30720 <<
401 }; <<
402 <<
403 cpu0_opp17: opp-1708800000 { <<
404 opp-hz = /bits/ 64 <17 <<
405 opp-peak-kBps = <30720 <<
406 }; <<
407 <<
408 cpu0_opp18: opp-1785600000 { <<
409 opp-hz = /bits/ 64 <17 <<
410 opp-peak-kBps = <30720 <<
411 }; <<
412 }; <<
413 <<
414 cpu4_opp_table: opp-table-cpu4 { <<
415 compatible = "operating-points <<
416 opp-shared; <<
417 <<
418 cpu4_opp1: opp-710400000 { <<
419 opp-hz = /bits/ 64 <71 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu4_opp2: opp-825600000 { <<
424 opp-hz = /bits/ 64 <82 <<
425 opp-peak-kBps = <21880 <<
426 }; <<
427 <<
428 cpu4_opp3: opp-940800000 { <<
429 opp-hz = /bits/ 64 <94 <<
430 opp-peak-kBps = <21880 <<
431 }; <<
432 <<
433 cpu4_opp4: opp-1056000000 { <<
434 opp-hz = /bits/ 64 <10 <<
435 opp-peak-kBps = <30720 <<
436 }; <<
437 <<
438 cpu4_opp5: opp-1171200000 { <<
439 opp-hz = /bits/ 64 <11 <<
440 opp-peak-kBps = <30720 <<
441 }; <<
442 <<
443 cpu4_opp6: opp-1286400000 { <<
444 opp-hz = /bits/ 64 <12 <<
445 opp-peak-kBps = <40680 <<
446 }; <<
447 <<
448 cpu4_opp7: opp-1401600000 { <<
449 opp-hz = /bits/ 64 <14 <<
450 opp-peak-kBps = <40680 <<
451 }; <<
452 <<
453 cpu4_opp8: opp-1497600000 { <<
454 opp-hz = /bits/ 64 <14 <<
455 opp-peak-kBps = <40680 <<
456 }; <<
457 <<
458 cpu4_opp9: opp-1612800000 { <<
459 opp-hz = /bits/ 64 <16 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu4_opp10: opp-1708800000 { <<
464 opp-hz = /bits/ 64 <17 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 <<
468 cpu4_opp11: opp-1804800000 { <<
469 opp-hz = /bits/ 64 <18 <<
470 opp-peak-kBps = <62200 <<
471 }; <<
472 <<
473 cpu4_opp12: opp-1920000000 { <<
474 opp-hz = /bits/ 64 <19 <<
475 opp-peak-kBps = <62200 <<
476 }; <<
477 <<
478 cpu4_opp13: opp-2016000000 { <<
479 opp-hz = /bits/ 64 <20 <<
480 opp-peak-kBps = <72160 <<
481 }; <<
482 <<
483 cpu4_opp14: opp-2131200000 { <<
484 opp-hz = /bits/ 64 <21 <<
485 opp-peak-kBps = <83680 <<
486 }; <<
487 <<
488 cpu4_opp15: opp-2227200000 { <<
489 opp-hz = /bits/ 64 <22 <<
490 opp-peak-kBps = <83680 <<
491 }; <<
492 <<
493 cpu4_opp16: opp-2323200000 { <<
494 opp-hz = /bits/ 64 <23 <<
495 opp-peak-kBps = <83680 <<
496 }; <<
497 <<
498 cpu4_opp17: opp-2419200000 { <<
499 opp-hz = /bits/ 64 <24 <<
500 opp-peak-kBps = <83680 <<
501 }; <<
502 }; <<
503 <<
504 cpu7_opp_table: opp-table-cpu7 { <<
505 compatible = "operating-points <<
506 opp-shared; <<
507 <<
508 cpu7_opp1: opp-825600000 { <<
509 opp-hz = /bits/ 64 <82 <<
510 opp-peak-kBps = <21880 <<
511 }; <<
512 <<
513 cpu7_opp2: opp-940800000 { <<
514 opp-hz = /bits/ 64 <94 <<
515 opp-peak-kBps = <21880 <<
516 }; <<
517 <<
518 cpu7_opp3: opp-1056000000 { <<
519 opp-hz = /bits/ 64 <10 <<
520 opp-peak-kBps = <30720 <<
521 }; <<
522 <<
523 cpu7_opp4: opp-1171200000 { <<
524 opp-hz = /bits/ 64 <11 <<
525 opp-peak-kBps = <30720 <<
526 }; <<
527 <<
528 cpu7_opp5: opp-1286400000 { <<
529 opp-hz = /bits/ 64 <12 <<
530 opp-peak-kBps = <40680 <<
531 }; <<
532 <<
533 cpu7_opp6: opp-1401600000 { <<
534 opp-hz = /bits/ 64 <14 <<
535 opp-peak-kBps = <40680 <<
536 }; <<
537 <<
538 cpu7_opp7: opp-1497600000 { <<
539 opp-hz = /bits/ 64 <14 <<
540 opp-peak-kBps = <40680 <<
541 }; <<
542 <<
543 cpu7_opp8: opp-1612800000 { <<
544 opp-hz = /bits/ 64 <16 <<
545 opp-peak-kBps = <40680 <<
546 }; <<
547 <<
548 cpu7_opp9: opp-1708800000 { <<
549 opp-hz = /bits/ 64 <17 <<
550 opp-peak-kBps = <40680 <<
551 }; <<
552 <<
553 cpu7_opp10: opp-1804800000 { <<
554 opp-hz = /bits/ 64 <18 <<
555 opp-peak-kBps = <62200 <<
556 }; <<
557 <<
558 cpu7_opp11: opp-1920000000 { <<
559 opp-hz = /bits/ 64 <19 <<
560 opp-peak-kBps = <62200 <<
561 }; <<
562 <<
563 cpu7_opp12: opp-2016000000 { <<
564 opp-hz = /bits/ 64 <20 <<
565 opp-peak-kBps = <72160 <<
566 }; <<
567 <<
568 cpu7_opp13: opp-2131200000 { <<
569 opp-hz = /bits/ 64 <21 <<
570 opp-peak-kBps = <83680 <<
571 }; <<
572 <<
573 cpu7_opp14: opp-2227200000 { <<
574 opp-hz = /bits/ 64 <22 <<
575 opp-peak-kBps = <83680 <<
576 }; <<
577 <<
578 cpu7_opp15: opp-2323200000 { <<
579 opp-hz = /bits/ 64 <23 <<
580 opp-peak-kBps = <83680 <<
581 }; <<
582 <<
583 cpu7_opp16: opp-2419200000 { <<
584 opp-hz = /bits/ 64 <24 <<
585 opp-peak-kBps = <83680 <<
586 }; <<
587 <<
588 cpu7_opp17: opp-2534400000 { <<
589 opp-hz = /bits/ 64 <25 <<
590 opp-peak-kBps = <83680 <<
591 }; <<
592 <<
593 cpu7_opp18: opp-2649600000 { <<
594 opp-hz = /bits/ 64 <26 <<
595 opp-peak-kBps = <83680 <<
596 }; <<
597 <<
598 cpu7_opp19: opp-2745600000 { <<
599 opp-hz = /bits/ 64 <27 <<
600 opp-peak-kBps = <83680 <<
601 }; <<
602 <<
603 cpu7_opp20: opp-2841600000 { <<
604 opp-hz = /bits/ 64 <28 <<
605 opp-peak-kBps = <83680 <<
606 }; <<
607 }; <<
608 <<
609 firmware { 266 firmware {
610 scm: scm { 267 scm: scm {
611 compatible = "qcom,scm 268 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 269 #reset-cells = <1>;
613 }; 270 };
614 }; 271 };
615 272
>> 273 tcsr_mutex: hwlock {
>> 274 compatible = "qcom,tcsr-mutex";
>> 275 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 276 #hwlock-cells = <1>;
>> 277 };
>> 278
616 memory@80000000 { 279 memory@80000000 {
617 device_type = "memory"; 280 device_type = "memory";
618 /* We expect the bootloader to 281 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 282 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 283 };
621 284
622 pmu { 285 pmu {
623 compatible = "arm,armv8-pmuv3" 286 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 287 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 288 };
626 289
627 psci { 290 psci {
628 compatible = "arm,psci-1.0"; 291 compatible = "arm,psci-1.0";
629 method = "smc"; 292 method = "smc";
630 293
631 CPU_PD0: power-domain-cpu0 { !! 294 CPU_PD0: cpu0 {
632 #power-domain-cells = 295 #power-domain-cells = <0>;
633 power-domains = <&CLUS 296 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 297 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 298 };
636 299
637 CPU_PD1: power-domain-cpu1 { !! 300 CPU_PD1: cpu1 {
638 #power-domain-cells = 301 #power-domain-cells = <0>;
639 power-domains = <&CLUS 302 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 303 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 304 };
642 305
643 CPU_PD2: power-domain-cpu2 { !! 306 CPU_PD2: cpu2 {
644 #power-domain-cells = 307 #power-domain-cells = <0>;
645 power-domains = <&CLUS 308 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 309 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 310 };
648 311
649 CPU_PD3: power-domain-cpu3 { !! 312 CPU_PD3: cpu3 {
650 #power-domain-cells = 313 #power-domain-cells = <0>;
651 power-domains = <&CLUS 314 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 316 };
654 317
655 CPU_PD4: power-domain-cpu4 { !! 318 CPU_PD4: cpu4 {
656 #power-domain-cells = 319 #power-domain-cells = <0>;
657 power-domains = <&CLUS 320 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 321 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 322 };
660 323
661 CPU_PD5: power-domain-cpu5 { !! 324 CPU_PD5: cpu5 {
662 #power-domain-cells = 325 #power-domain-cells = <0>;
663 power-domains = <&CLUS 326 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 327 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 328 };
666 329
667 CPU_PD6: power-domain-cpu6 { !! 330 CPU_PD6: cpu6 {
668 #power-domain-cells = 331 #power-domain-cells = <0>;
669 power-domains = <&CLUS 332 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 333 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 334 };
672 335
673 CPU_PD7: power-domain-cpu7 { !! 336 CPU_PD7: cpu7 {
674 #power-domain-cells = 337 #power-domain-cells = <0>;
675 power-domains = <&CLUS 338 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 339 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 340 };
678 341
679 CLUSTER_PD: power-domain-cpu-c !! 342 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 343 #power-domain-cells = <0>;
681 domain-idle-states = < 344 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 345 };
683 }; 346 };
684 347
685 reserved-memory { 348 reserved-memory {
686 #address-cells = <2>; 349 #address-cells = <2>;
687 #size-cells = <2>; 350 #size-cells = <2>;
688 ranges; 351 ranges;
689 352
690 hyp_mem: memory@85700000 { 353 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 354 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 355 no-map;
693 }; 356 };
694 357
695 xbl_mem: memory@85d00000 { 358 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 359 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 360 no-map;
698 }; 361 };
699 362
700 aop_mem: memory@85f00000 { 363 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 364 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 365 no-map;
703 }; 366 };
704 367
705 aop_cmd_db: memory@85f20000 { 368 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 369 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 370 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 371 no-map;
709 }; 372 };
710 373
711 smem_mem: memory@86000000 { 374 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 375 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 376 no-map;
714 }; 377 };
715 378
716 tz_mem: memory@86200000 { 379 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 380 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 381 no-map;
719 }; 382 };
720 383
721 rmtfs_mem: memory@89b00000 { 384 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 385 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 386 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 387 no-map;
725 388
726 qcom,client-id = <1>; 389 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 390 qcom,vmid = <15>;
728 }; 391 };
729 392
730 camera_mem: memory@8b700000 { 393 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 394 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 395 no-map;
733 }; 396 };
734 397
735 wlan_mem: memory@8bc00000 { 398 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 399 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 400 no-map;
738 }; 401 };
739 402
740 npu_mem: memory@8bd80000 { 403 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 404 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 405 no-map;
743 }; 406 };
744 407
745 adsp_mem: memory@8be00000 { 408 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 409 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 410 no-map;
748 }; 411 };
749 412
750 mpss_mem: memory@8d800000 { 413 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 414 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 415 no-map;
753 }; 416 };
754 417
755 venus_mem: memory@96e00000 { 418 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 419 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 420 no-map;
758 }; 421 };
759 422
760 slpi_mem: memory@97300000 { 423 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 424 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 425 no-map;
763 }; 426 };
764 427
765 ipa_fw_mem: memory@98700000 { 428 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 429 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 430 no-map;
768 }; 431 };
769 432
770 ipa_gsi_mem: memory@98710000 { 433 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 434 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 435 no-map;
773 }; 436 };
774 437
775 gpu_mem: memory@98715000 { 438 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 439 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 440 no-map;
778 }; 441 };
779 442
780 spss_mem: memory@98800000 { 443 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 444 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 445 no-map;
783 }; 446 };
784 447
785 cdsp_mem: memory@98900000 { 448 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 449 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 450 no-map;
788 }; 451 };
789 452
790 qseecom_mem: memory@9e400000 { 453 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 454 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 455 no-map;
793 }; 456 };
794 }; 457 };
795 458
796 smem { 459 smem {
797 compatible = "qcom,smem"; 460 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 461 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 462 hwlocks = <&tcsr_mutex 3>;
800 }; 463 };
801 464
802 smp2p-cdsp { 465 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 466 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 467 qcom,smem = <94>, <432>;
805 468
806 interrupts = <GIC_SPI 576 IRQ_ 469 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 470
808 mboxes = <&apss_shared 6>; 471 mboxes = <&apss_shared 6>;
809 472
810 qcom,local-pid = <0>; 473 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 474 qcom,remote-pid = <5>;
812 475
813 cdsp_smp2p_out: master-kernel 476 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 477 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 478 #qcom,smem-state-cells = <1>;
816 }; 479 };
817 480
818 cdsp_smp2p_in: slave-kernel { 481 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 482 qcom,entry-name = "slave-kernel";
820 483
821 interrupt-controller; 484 interrupt-controller;
822 #interrupt-cells = <2> 485 #interrupt-cells = <2>;
823 }; 486 };
824 }; 487 };
825 488
826 smp2p-lpass { 489 smp2p-lpass {
827 compatible = "qcom,smp2p"; 490 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 491 qcom,smem = <443>, <429>;
829 492
830 interrupts = <GIC_SPI 158 IRQ_ 493 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 494
832 mboxes = <&apss_shared 10>; 495 mboxes = <&apss_shared 10>;
833 496
834 qcom,local-pid = <0>; 497 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 498 qcom,remote-pid = <2>;
836 499
837 adsp_smp2p_out: master-kernel 500 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 501 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 502 #qcom,smem-state-cells = <1>;
840 }; 503 };
841 504
842 adsp_smp2p_in: slave-kernel { 505 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 506 qcom,entry-name = "slave-kernel";
844 507
845 interrupt-controller; 508 interrupt-controller;
846 #interrupt-cells = <2> 509 #interrupt-cells = <2>;
847 }; 510 };
848 }; 511 };
849 512
850 smp2p-mpss { 513 smp2p-mpss {
851 compatible = "qcom,smp2p"; 514 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 515 qcom,smem = <435>, <428>;
853 516
854 interrupts = <GIC_SPI 451 IRQ_ 517 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 518
856 mboxes = <&apss_shared 14>; 519 mboxes = <&apss_shared 14>;
857 520
858 qcom,local-pid = <0>; 521 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 522 qcom,remote-pid = <1>;
860 523
861 modem_smp2p_out: master-kernel 524 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 525 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 526 #qcom,smem-state-cells = <1>;
864 }; 527 };
865 528
866 modem_smp2p_in: slave-kernel { 529 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 530 qcom,entry-name = "slave-kernel";
868 531
869 interrupt-controller; 532 interrupt-controller;
870 #interrupt-cells = <2> 533 #interrupt-cells = <2>;
871 }; 534 };
872 }; 535 };
873 536
874 smp2p-slpi { 537 smp2p-slpi {
875 compatible = "qcom,smp2p"; 538 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 539 qcom,smem = <481>, <430>;
877 540
878 interrupts = <GIC_SPI 172 IRQ_ 541 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 542
880 mboxes = <&apss_shared 26>; 543 mboxes = <&apss_shared 26>;
881 544
882 qcom,local-pid = <0>; 545 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 546 qcom,remote-pid = <3>;
884 547
885 slpi_smp2p_out: master-kernel 548 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 549 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 550 #qcom,smem-state-cells = <1>;
888 }; 551 };
889 552
890 slpi_smp2p_in: slave-kernel { 553 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 554 qcom,entry-name = "slave-kernel";
892 555
893 interrupt-controller; 556 interrupt-controller;
894 #interrupt-cells = <2> 557 #interrupt-cells = <2>;
895 }; 558 };
896 }; 559 };
897 560
898 soc: soc@0 { 561 soc: soc@0 {
899 #address-cells = <2>; 562 #address-cells = <2>;
900 #size-cells = <2>; 563 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 564 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 565 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 566 compatible = "simple-bus";
904 567
905 gcc: clock-controller@100000 { 568 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 569 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 570 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 571 #clock-cells = <1>;
909 #reset-cells = <1>; 572 #reset-cells = <1>;
910 #power-domain-cells = 573 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 574 clock-names = "bi_tcxo",
912 "sleep_c 575 "sleep_clk";
913 clocks = <&rpmhcc RPMH 576 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 577 <&sleep_clk>;
915 }; 578 };
916 579
917 gpi_dma0: dma-controller@80000 <<
918 compatible = "qcom,sm8 <<
919 reg = <0 0x00800000 0 <<
920 interrupts = <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 dma-channels = <13>; <<
934 dma-channel-mask = <0x <<
935 iommus = <&apps_smmu 0 <<
936 #dma-cells = <3>; <<
937 status = "disabled"; <<
938 }; <<
939 <<
940 ethernet: ethernet@20000 { <<
941 compatible = "qcom,sm8 <<
942 reg = <0x0 0x00020000 <<
943 <0x0 0x00036000 <<
944 reg-names = "stmmaceth <<
945 clock-names = "stmmace <<
946 clocks = <&gcc GCC_EMA <<
947 <&gcc GCC_EMAC <<
948 <&gcc GCC_EMAC <<
949 <&gcc GCC_EMAC <<
950 interrupts = <GIC_SPI <<
951 <GIC_SPI <<
952 interrupt-names = "mac <<
953 <<
954 power-domains = <&gcc <<
955 resets = <&gcc GCC_EMA <<
956 <<
957 iommus = <&apps_smmu 0 <<
958 <<
959 snps,tso; <<
960 rx-fifo-depth = <4096> <<
961 tx-fifo-depth = <4096> <<
962 <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 <<
978 qupv3_id_0: geniqup@8c0000 { 580 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 581 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 582 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 583 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 584 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 585 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 586 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 587 #address-cells = <2>;
986 #size-cells = <2>; 588 #size-cells = <2>;
987 ranges; 589 ranges;
988 status = "disabled"; 590 status = "disabled";
989 591
990 i2c0: i2c@880000 { 592 i2c0: i2c@880000 {
991 compatible = " 593 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 594 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 595 clock-names = "se";
994 clocks = <&gcc 596 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d <<
996 <&gpi_d <<
997 dma-names = "t <<
998 pinctrl-names 597 pinctrl-names = "default";
999 pinctrl-0 = <& 598 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 599 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 600 #address-cells = <1>;
1002 #size-cells = 601 #size-cells = <0>;
1003 status = "dis 602 status = "disabled";
1004 }; 603 };
1005 604
1006 spi0: spi@880000 { <<
1007 compatible = <<
1008 reg = <0 0x00 <<
1009 reg-names = " <<
1010 clock-names = <<
1011 clocks = <&gc <<
1012 dmas = <&gpi_ <<
1013 <&gpi_ <<
1014 dma-names = " <<
1015 pinctrl-names <<
1016 pinctrl-0 = < <<
1017 interrupts = <<
1018 spi-max-frequ <<
1019 #address-cell <<
1020 #size-cells = <<
1021 status = "dis <<
1022 }; <<
1023 <<
1024 i2c1: i2c@884000 { 605 i2c1: i2c@884000 {
1025 compatible = 606 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 607 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 608 clock-names = "se";
1028 clocks = <&gc 609 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 pinctrl-names 610 pinctrl-names = "default";
1033 pinctrl-0 = < 611 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 612 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 613 #address-cells = <1>;
1036 #size-cells = 614 #size-cells = <0>;
1037 status = "dis 615 status = "disabled";
1038 }; 616 };
1039 617
1040 spi1: spi@884000 { <<
1041 compatible = <<
1042 reg = <0 0x00 <<
1043 reg-names = " <<
1044 clock-names = <<
1045 clocks = <&gc <<
1046 dmas = <&gpi_ <<
1047 <&gpi_ <<
1048 dma-names = " <<
1049 pinctrl-names <<
1050 pinctrl-0 = < <<
1051 interrupts = <<
1052 spi-max-frequ <<
1053 #address-cell <<
1054 #size-cells = <<
1055 status = "dis <<
1056 }; <<
1057 <<
1058 i2c2: i2c@888000 { 618 i2c2: i2c@888000 {
1059 compatible = 619 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 620 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 621 clock-names = "se";
1062 clocks = <&gc 622 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ <<
1064 <&gpi_ <<
1065 dma-names = " <<
1066 pinctrl-names 623 pinctrl-names = "default";
1067 pinctrl-0 = < 624 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 625 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 626 #address-cells = <1>;
1070 #size-cells = 627 #size-cells = <0>;
1071 status = "dis 628 status = "disabled";
1072 }; 629 };
1073 630
1074 spi2: spi@888000 { <<
1075 compatible = <<
1076 reg = <0 0x00 <<
1077 reg-names = " <<
1078 clock-names = <<
1079 clocks = <&gc <<
1080 dmas = <&gpi_ <<
1081 <&gpi_ <<
1082 dma-names = " <<
1083 pinctrl-names <<
1084 pinctrl-0 = < <<
1085 interrupts = <<
1086 spi-max-frequ <<
1087 #address-cell <<
1088 #size-cells = <<
1089 status = "dis <<
1090 }; <<
1091 <<
1092 i2c3: i2c@88c000 { 631 i2c3: i2c@88c000 {
1093 compatible = 632 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 633 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 634 clock-names = "se";
1096 clocks = <&gc 635 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ <<
1098 <&gpi_ <<
1099 dma-names = " <<
1100 pinctrl-names 636 pinctrl-names = "default";
1101 pinctrl-0 = < 637 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 638 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 639 #address-cells = <1>;
1104 #size-cells = 640 #size-cells = <0>;
1105 status = "dis 641 status = "disabled";
1106 }; 642 };
1107 643
1108 spi3: spi@88c000 { <<
1109 compatible = <<
1110 reg = <0 0x00 <<
1111 reg-names = " <<
1112 clock-names = <<
1113 clocks = <&gc <<
1114 dmas = <&gpi_ <<
1115 <&gpi_ <<
1116 dma-names = " <<
1117 pinctrl-names <<
1118 pinctrl-0 = < <<
1119 interrupts = <<
1120 spi-max-frequ <<
1121 #address-cell <<
1122 #size-cells = <<
1123 status = "dis <<
1124 }; <<
1125 <<
1126 i2c4: i2c@890000 { 644 i2c4: i2c@890000 {
1127 compatible = 645 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 646 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 647 clock-names = "se";
1130 clocks = <&gc 648 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ <<
1132 <&gpi_ <<
1133 dma-names = " <<
1134 pinctrl-names 649 pinctrl-names = "default";
1135 pinctrl-0 = < 650 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 651 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 652 #address-cells = <1>;
1138 #size-cells = 653 #size-cells = <0>;
1139 status = "dis 654 status = "disabled";
1140 }; 655 };
1141 656
1142 spi4: spi@890000 { <<
1143 compatible = <<
1144 reg = <0 0x00 <<
1145 reg-names = " <<
1146 clock-names = <<
1147 clocks = <&gc <<
1148 dmas = <&gpi_ <<
1149 <&gpi_ <<
1150 dma-names = " <<
1151 pinctrl-names <<
1152 pinctrl-0 = < <<
1153 interrupts = <<
1154 spi-max-frequ <<
1155 #address-cell <<
1156 #size-cells = <<
1157 status = "dis <<
1158 }; <<
1159 <<
1160 i2c5: i2c@894000 { 657 i2c5: i2c@894000 {
1161 compatible = 658 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 659 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 660 clock-names = "se";
1164 clocks = <&gc 661 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ <<
1166 <&gpi_ <<
1167 dma-names = " <<
1168 pinctrl-names 662 pinctrl-names = "default";
1169 pinctrl-0 = < 663 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 664 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 665 #address-cells = <1>;
1172 #size-cells = 666 #size-cells = <0>;
1173 status = "dis 667 status = "disabled";
1174 }; 668 };
1175 669
1176 spi5: spi@894000 { <<
1177 compatible = <<
1178 reg = <0 0x00 <<
1179 reg-names = " <<
1180 clock-names = <<
1181 clocks = <&gc <<
1182 dmas = <&gpi_ <<
1183 <&gpi_ <<
1184 dma-names = " <<
1185 pinctrl-names <<
1186 pinctrl-0 = < <<
1187 interrupts = <<
1188 spi-max-frequ <<
1189 #address-cell <<
1190 #size-cells = <<
1191 status = "dis <<
1192 }; <<
1193 <<
1194 i2c6: i2c@898000 { 670 i2c6: i2c@898000 {
1195 compatible = 671 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 672 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 673 clock-names = "se";
1198 clocks = <&gc 674 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ <<
1200 <&gpi_ <<
1201 dma-names = " <<
1202 pinctrl-names 675 pinctrl-names = "default";
1203 pinctrl-0 = < 676 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 678 #address-cells = <1>;
1206 #size-cells = 679 #size-cells = <0>;
1207 status = "dis 680 status = "disabled";
1208 }; 681 };
1209 682
1210 spi6: spi@898000 { <<
1211 compatible = <<
1212 reg = <0 0x00 <<
1213 reg-names = " <<
1214 clock-names = <<
1215 clocks = <&gc <<
1216 dmas = <&gpi_ <<
1217 <&gpi_ <<
1218 dma-names = " <<
1219 pinctrl-names <<
1220 pinctrl-0 = < <<
1221 interrupts = <<
1222 spi-max-frequ <<
1223 #address-cell <<
1224 #size-cells = <<
1225 status = "dis <<
1226 }; <<
1227 <<
1228 i2c7: i2c@89c000 { 683 i2c7: i2c@89c000 {
1229 compatible = 684 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 685 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 686 clock-names = "se";
1232 clocks = <&gc 687 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ <<
1234 <&gpi_ <<
1235 dma-names = " <<
1236 pinctrl-names 688 pinctrl-names = "default";
1237 pinctrl-0 = < 689 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = !! 690 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell <<
1240 #size-cells = <<
1241 status = "dis <<
1242 }; <<
1243 <<
1244 spi7: spi@89c000 { <<
1245 compatible = <<
1246 reg = <0 0x00 <<
1247 reg-names = " <<
1248 clock-names = <<
1249 clocks = <&gc <<
1250 dmas = <&gpi_ <<
1251 <&gpi_ <<
1252 dma-names = " <<
1253 pinctrl-names <<
1254 pinctrl-0 = < <<
1255 interrupts = <<
1256 spi-max-frequ <<
1257 #address-cell 691 #address-cells = <1>;
1258 #size-cells = 692 #size-cells = <0>;
1259 status = "dis 693 status = "disabled";
1260 }; 694 };
1261 }; <<
1262 695
1263 gpi_dma1: dma-controller@a000 <<
1264 compatible = "qcom,sm <<
1265 reg = <0 0x00a00000 0 <<
1266 interrupts = <GIC_SPI <<
1267 <GIC_SPI <<
1268 <GIC_SPI <<
1269 <GIC_SPI <<
1270 <GIC_SPI <<
1271 <GIC_SPI <<
1272 <GIC_SPI <<
1273 <GIC_SPI <<
1274 <GIC_SPI <<
1275 <GIC_SPI <<
1276 <GIC_SPI <<
1277 <GIC_SPI <<
1278 <GIC_SPI <<
1279 dma-channels = <13>; <<
1280 dma-channel-mask = <0 <<
1281 iommus = <&apps_smmu <<
1282 #dma-cells = <3>; <<
1283 status = "disabled"; <<
1284 }; 696 };
1285 697
1286 qupv3_id_1: geniqup@ac0000 { 698 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 699 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 700 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 701 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 702 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 703 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 704 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 705 #address-cells = <2>;
1294 #size-cells = <2>; 706 #size-cells = <2>;
1295 ranges; 707 ranges;
1296 status = "disabled"; 708 status = "disabled";
1297 709
1298 i2c8: i2c@a80000 { 710 i2c8: i2c@a80000 {
1299 compatible = 711 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 712 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 713 clock-names = "se";
1302 clocks = <&gc 714 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ <<
1304 <&gpi_ <<
1305 dma-names = " <<
1306 pinctrl-names 715 pinctrl-names = "default";
1307 pinctrl-0 = < 716 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 717 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 718 #address-cells = <1>;
1310 #size-cells = 719 #size-cells = <0>;
1311 status = "dis 720 status = "disabled";
1312 }; 721 };
1313 722
1314 spi8: spi@a80000 { <<
1315 compatible = <<
1316 reg = <0 0x00 <<
1317 reg-names = " <<
1318 clock-names = <<
1319 clocks = <&gc <<
1320 dmas = <&gpi_ <<
1321 <&gpi_ <<
1322 dma-names = " <<
1323 pinctrl-names <<
1324 pinctrl-0 = < <<
1325 interrupts = <<
1326 spi-max-frequ <<
1327 #address-cell <<
1328 #size-cells = <<
1329 status = "dis <<
1330 }; <<
1331 <<
1332 i2c9: i2c@a84000 { 723 i2c9: i2c@a84000 {
1333 compatible = 724 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 725 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 726 clock-names = "se";
1336 clocks = <&gc 727 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ <<
1338 <&gpi_ <<
1339 dma-names = " <<
1340 pinctrl-names 728 pinctrl-names = "default";
1341 pinctrl-0 = < 729 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 730 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 731 #address-cells = <1>;
1344 #size-cells = 732 #size-cells = <0>;
1345 status = "dis 733 status = "disabled";
1346 }; 734 };
1347 735
1348 spi9: spi@a84000 { <<
1349 compatible = <<
1350 reg = <0 0x00 <<
1351 reg-names = " <<
1352 clock-names = <<
1353 clocks = <&gc <<
1354 dmas = <&gpi_ <<
1355 <&gpi_ <<
1356 dma-names = " <<
1357 pinctrl-names <<
1358 pinctrl-0 = < <<
1359 interrupts = <<
1360 spi-max-frequ <<
1361 #address-cell <<
1362 #size-cells = <<
1363 status = "dis <<
1364 }; <<
1365 <<
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 736 i2c10: i2c@a88000 {
1378 compatible = 737 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 738 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 739 clock-names = "se";
1381 clocks = <&gc 740 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ <<
1383 <&gpi_ <<
1384 dma-names = " <<
1385 pinctrl-names 741 pinctrl-names = "default";
1386 pinctrl-0 = < 742 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 743 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 744 #address-cells = <1>;
1389 #size-cells = 745 #size-cells = <0>;
1390 status = "dis 746 status = "disabled";
1391 }; 747 };
1392 748
1393 spi10: spi@a88000 { <<
1394 compatible = <<
1395 reg = <0 0x00 <<
1396 reg-names = " <<
1397 clock-names = <<
1398 clocks = <&gc <<
1399 dmas = <&gpi_ <<
1400 <&gpi_ <<
1401 dma-names = " <<
1402 pinctrl-names <<
1403 pinctrl-0 = < <<
1404 interrupts = <<
1405 spi-max-frequ <<
1406 #address-cell <<
1407 #size-cells = <<
1408 status = "dis <<
1409 }; <<
1410 <<
1411 i2c11: i2c@a8c000 { 749 i2c11: i2c@a8c000 {
1412 compatible = 750 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 751 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 752 clock-names = "se";
1415 clocks = <&gc 753 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ <<
1417 <&gpi_ <<
1418 dma-names = " <<
1419 pinctrl-names 754 pinctrl-names = "default";
1420 pinctrl-0 = < 755 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 756 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 757 #address-cells = <1>;
1423 #size-cells = 758 #size-cells = <0>;
1424 status = "dis 759 status = "disabled";
1425 }; 760 };
1426 761
1427 spi11: spi@a8c000 { <<
1428 compatible = <<
1429 reg = <0 0x00 <<
1430 reg-names = " <<
1431 clock-names = <<
1432 clocks = <&gc <<
1433 dmas = <&gpi_ <<
1434 <&gpi_ <<
1435 dma-names = " <<
1436 pinctrl-names <<
1437 pinctrl-0 = < <<
1438 interrupts = <<
1439 spi-max-frequ <<
1440 #address-cell <<
1441 #size-cells = <<
1442 status = "dis <<
1443 }; <<
1444 <<
1445 uart2: serial@a90000 762 uart2: serial@a90000 {
1446 compatible = 763 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 764 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 765 clock-names = "se";
1449 clocks = <&gc 766 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 767 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 768 status = "disabled";
1452 }; 769 };
1453 770
1454 i2c12: i2c@a90000 { 771 i2c12: i2c@a90000 {
1455 compatible = 772 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 773 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 774 clock-names = "se";
1458 clocks = <&gc 775 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 pinctrl-names 776 pinctrl-names = "default";
1463 pinctrl-0 = < 777 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 778 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 779 #address-cells = <1>;
1466 #size-cells = 780 #size-cells = <0>;
1467 status = "dis 781 status = "disabled";
1468 }; 782 };
1469 783
1470 spi12: spi@a90000 { <<
1471 compatible = <<
1472 reg = <0 0x00 <<
1473 reg-names = " <<
1474 clock-names = <<
1475 clocks = <&gc <<
1476 dmas = <&gpi_ <<
1477 <&gpi_ <<
1478 dma-names = " <<
1479 pinctrl-names <<
1480 pinctrl-0 = < <<
1481 interrupts = <<
1482 spi-max-frequ <<
1483 #address-cell <<
1484 #size-cells = <<
1485 status = "dis <<
1486 }; <<
1487 <<
1488 i2c16: i2c@94000 { 784 i2c16: i2c@94000 {
1489 compatible = 785 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 !! 786 reg = <0 0x0094000 0 0x4000>;
1491 clock-names = 787 clock-names = "se";
1492 clocks = <&gc 788 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ <<
1494 <&gpi_ <<
1495 dma-names = " <<
1496 pinctrl-names 789 pinctrl-names = "default";
1497 pinctrl-0 = < 790 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 791 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 792 #address-cells = <1>;
1500 #size-cells = 793 #size-cells = <0>;
1501 status = "dis 794 status = "disabled";
1502 }; 795 };
1503 <<
1504 spi16: spi@a94000 { <<
1505 compatible = <<
1506 reg = <0 0x00 <<
1507 reg-names = " <<
1508 clock-names = <<
1509 clocks = <&gc <<
1510 dmas = <&gpi_ <<
1511 <&gpi_ <<
1512 dma-names = " <<
1513 pinctrl-names <<
1514 pinctrl-0 = < <<
1515 interrupts = <<
1516 spi-max-frequ <<
1517 #address-cell <<
1518 #size-cells = <<
1519 status = "dis <<
1520 }; <<
1521 }; <<
1522 <<
1523 gpi_dma2: dma-controller@c000 <<
1524 compatible = "qcom,sm <<
1525 reg = <0 0x00c00000 0 <<
1526 interrupts = <GIC_SPI <<
1527 <GIC_SPI <<
1528 <GIC_SPI <<
1529 <GIC_SPI <<
1530 <GIC_SPI <<
1531 <GIC_SPI <<
1532 <GIC_SPI <<
1533 <GIC_SPI <<
1534 <GIC_SPI <<
1535 <GIC_SPI <<
1536 <GIC_SPI <<
1537 <GIC_SPI <<
1538 <GIC_SPI <<
1539 dma-channels = <13>; <<
1540 dma-channel-mask = <0 <<
1541 iommus = <&apps_smmu <<
1542 #dma-cells = <3>; <<
1543 status = "disabled"; <<
1544 }; 796 };
1545 797
1546 qupv3_id_2: geniqup@cc0000 { 798 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 799 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 800 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 801
1550 clock-names = "m-ahb" 802 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 803 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 804 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 805 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 806 #address-cells = <2>;
1555 #size-cells = <2>; 807 #size-cells = <2>;
1556 ranges; 808 ranges;
1557 status = "disabled"; 809 status = "disabled";
1558 810
1559 i2c17: i2c@c80000 { 811 i2c17: i2c@c80000 {
1560 compatible = 812 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 813 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 814 clock-names = "se";
1563 clocks = <&gc 815 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ <<
1565 <&gpi_ <<
1566 dma-names = " <<
1567 pinctrl-names 816 pinctrl-names = "default";
1568 pinctrl-0 = < 817 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 818 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 819 #address-cells = <1>;
1571 #size-cells = 820 #size-cells = <0>;
1572 status = "dis 821 status = "disabled";
1573 }; 822 };
1574 823
1575 spi17: spi@c80000 { <<
1576 compatible = <<
1577 reg = <0 0x00 <<
1578 reg-names = " <<
1579 clock-names = <<
1580 clocks = <&gc <<
1581 dmas = <&gpi_ <<
1582 <&gpi_ <<
1583 dma-names = " <<
1584 pinctrl-names <<
1585 pinctrl-0 = < <<
1586 interrupts = <<
1587 spi-max-frequ <<
1588 #address-cell <<
1589 #size-cells = <<
1590 status = "dis <<
1591 }; <<
1592 <<
1593 i2c18: i2c@c84000 { 824 i2c18: i2c@c84000 {
1594 compatible = 825 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 826 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 827 clock-names = "se";
1597 clocks = <&gc 828 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ <<
1599 <&gpi_ <<
1600 dma-names = " <<
1601 pinctrl-names 829 pinctrl-names = "default";
1602 pinctrl-0 = < 830 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 831 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 832 #address-cells = <1>;
1605 #size-cells = 833 #size-cells = <0>;
1606 status = "dis 834 status = "disabled";
1607 }; 835 };
1608 836
1609 spi18: spi@c84000 { <<
1610 compatible = <<
1611 reg = <0 0x00 <<
1612 reg-names = " <<
1613 clock-names = <<
1614 clocks = <&gc <<
1615 dmas = <&gpi_ <<
1616 <&gpi_ <<
1617 dma-names = " <<
1618 pinctrl-names <<
1619 pinctrl-0 = < <<
1620 interrupts = <<
1621 spi-max-frequ <<
1622 #address-cell <<
1623 #size-cells = <<
1624 status = "dis <<
1625 }; <<
1626 <<
1627 i2c19: i2c@c88000 { 837 i2c19: i2c@c88000 {
1628 compatible = 838 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 839 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 840 clock-names = "se";
1631 clocks = <&gc 841 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 pinctrl-names 842 pinctrl-names = "default";
1636 pinctrl-0 = < 843 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 844 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 845 #address-cells = <1>;
1639 #size-cells = 846 #size-cells = <0>;
1640 status = "dis 847 status = "disabled";
1641 }; 848 };
1642 849
1643 spi19: spi@c88000 { <<
1644 compatible = <<
1645 reg = <0 0x00 <<
1646 reg-names = " <<
1647 clock-names = <<
1648 clocks = <&gc <<
1649 dmas = <&gpi_ <<
1650 <&gpi_ <<
1651 dma-names = " <<
1652 pinctrl-names <<
1653 pinctrl-0 = < <<
1654 interrupts = <<
1655 spi-max-frequ <<
1656 #address-cell <<
1657 #size-cells = <<
1658 status = "dis <<
1659 }; <<
1660 <<
1661 i2c13: i2c@c8c000 { 850 i2c13: i2c@c8c000 {
1662 compatible = 851 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 852 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 853 clock-names = "se";
1665 clocks = <&gc 854 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ <<
1667 <&gpi_ <<
1668 dma-names = " <<
1669 pinctrl-names 855 pinctrl-names = "default";
1670 pinctrl-0 = < 856 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 857 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 858 #address-cells = <1>;
1673 #size-cells = 859 #size-cells = <0>;
1674 status = "dis 860 status = "disabled";
1675 }; 861 };
1676 862
1677 spi13: spi@c8c000 { <<
1678 compatible = <<
1679 reg = <0 0x00 <<
1680 reg-names = " <<
1681 clock-names = <<
1682 clocks = <&gc <<
1683 dmas = <&gpi_ <<
1684 <&gpi_ <<
1685 dma-names = " <<
1686 pinctrl-names <<
1687 pinctrl-0 = < <<
1688 interrupts = <<
1689 spi-max-frequ <<
1690 #address-cell <<
1691 #size-cells = <<
1692 status = "dis <<
1693 }; <<
1694 <<
1695 i2c14: i2c@c90000 { 863 i2c14: i2c@c90000 {
1696 compatible = 864 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 865 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 866 clock-names = "se";
1699 clocks = <&gc 867 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ <<
1701 <&gpi_ <<
1702 dma-names = " <<
1703 pinctrl-names 868 pinctrl-names = "default";
1704 pinctrl-0 = < 869 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 870 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 871 #address-cells = <1>;
1707 #size-cells = 872 #size-cells = <0>;
1708 status = "dis 873 status = "disabled";
1709 }; 874 };
1710 875
1711 spi14: spi@c90000 { <<
1712 compatible = <<
1713 reg = <0 0x00 <<
1714 reg-names = " <<
1715 clock-names = <<
1716 clocks = <&gc <<
1717 dmas = <&gpi_ <<
1718 <&gpi_ <<
1719 dma-names = " <<
1720 pinctrl-names <<
1721 pinctrl-0 = < <<
1722 interrupts = <<
1723 spi-max-frequ <<
1724 #address-cell <<
1725 #size-cells = <<
1726 status = "dis <<
1727 }; <<
1728 <<
1729 i2c15: i2c@c94000 { 876 i2c15: i2c@c94000 {
1730 compatible = 877 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 878 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 879 clock-names = "se";
1733 clocks = <&gc 880 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ <<
1735 <&gpi_ <<
1736 dma-names = " <<
1737 pinctrl-names 881 pinctrl-names = "default";
1738 pinctrl-0 = < 882 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 883 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 884 #address-cells = <1>;
1741 #size-cells = 885 #size-cells = <0>;
1742 status = "dis 886 status = "disabled";
1743 }; 887 };
1744 <<
1745 spi15: spi@c94000 { <<
1746 compatible = <<
1747 reg = <0 0x00 <<
1748 reg-names = " <<
1749 clock-names = <<
1750 clocks = <&gc <<
1751 dmas = <&gpi_ <<
1752 <&gpi_ <<
1753 dma-names = " <<
1754 pinctrl-names <<
1755 pinctrl-0 = < <<
1756 interrupts = <<
1757 spi-max-frequ <<
1758 #address-cell <<
1759 #size-cells = <<
1760 status = "dis <<
1761 }; <<
1762 }; 888 };
1763 889
1764 config_noc: interconnect@1500 890 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 891 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 892 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 893 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 894 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 895 };
1770 896
1771 system_noc: interconnect@1620 897 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 898 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 899 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 900 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 901 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 902 };
1777 903
1778 mc_virt: interconnect@163a000 904 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 905 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 906 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 907 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 908 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 909 };
1784 910
1785 aggre1_noc: interconnect@16e0 911 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 912 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 913 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 914 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 915 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 916 };
1791 917
1792 aggre2_noc: interconnect@1700 918 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 919 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 920 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 921 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 922 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 923 };
1798 924
1799 compute_noc: interconnect@172 925 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 926 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 927 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 928 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 929 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 930 };
1805 931
1806 mmss_noc: interconnect@174000 932 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 933 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 934 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 935 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 936 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 937 };
1812 938
1813 system-cache-controller@92000 939 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 940 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 941 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 942 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 943 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 944 };
1822 945
1823 dma@10a2000 { <<
1824 compatible = "qcom,sm <<
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 <<
1832 <0 0x60000000 0 <<
1833 <0 0x60000f20 0 <<
1834 <0 0x60001000 0 <<
1835 <0 0x60100000 0 <<
1836 reg-names = "parf", " <<
1837 device_type = "pci"; <<
1838 linux,pci-domain = <0 <<
1839 bus-range = <0x00 0xf <<
1840 num-lanes = <1>; <<
1841 <<
1842 #address-cells = <3>; <<
1843 #size-cells = <2>; <<
1844 <<
1845 ranges = <0x01000000 <<
1846 <0x02000000 <<
1847 <<
1848 interrupts = <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 <<
1865 interrupt-map-mask = <<
1866 interrupt-map = <0 0 <<
1867 <0 0 <<
1868 <0 0 <<
1869 <0 0 <<
1870 <<
1871 clocks = <&gcc GCC_PC <<
1872 <&gcc GCC_PC <<
1873 <&gcc GCC_PC <<
1874 <&gcc GCC_PC <<
1875 <&gcc GCC_PC <<
1876 <&gcc GCC_PC <<
1877 <&gcc GCC_AG <<
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", <<
1880 "aux", <<
1881 "cfg", <<
1882 "bus_ma <<
1883 "bus_sl <<
1884 "slave_ <<
1885 "tbu", <<
1886 "ref"; <<
1887 <<
1888 iommu-map = <0x0 &a <<
1889 <0x100 &a <<
1890 <<
1891 resets = <&gcc GCC_PC <<
1892 reset-names = "pci"; <<
1893 <<
1894 power-domains = <&gcc <<
1895 <<
1896 phys = <&pcie0_phy>; <<
1897 phy-names = "pciephy" <<
1898 <<
1899 perst-gpios = <&tlmm <<
1900 wake-gpios = <&tlmm 3 <<
1901 <<
1902 pinctrl-names = "defa <<
1903 pinctrl-0 = <&pcie0_d <<
1904 <<
1905 status = "disabled"; <<
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; <<
1917 <<
1918 pcie0_phy: phy@1c06000 { <<
1919 compatible = "qcom,sm <<
1920 reg = <0 0x01c06000 0 <<
1921 clocks = <&gcc GCC_PC <<
1922 <&gcc GCC_PC <<
1923 <&gcc GCC_PC <<
1924 <&gcc GCC_PC <<
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 <<
1937 resets = <&gcc GCC_PC <<
1938 reset-names = "phy"; <<
1939 <<
1940 assigned-clocks = <&g <<
1941 assigned-clock-rates <<
1942 <<
1943 status = "disabled"; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@1c08000 { <<
1947 compatible = "qcom,pc <<
1948 reg = <0 0x01c08000 0 <<
1949 <0 0x40000000 0 <<
1950 <0 0x40000f20 0 <<
1951 <0 0x40001000 0 <<
1952 <0 0x40100000 0 <<
1953 reg-names = "parf", " <<
1954 device_type = "pci"; <<
1955 linux,pci-domain = <1 <<
1956 bus-range = <0x00 0xf <<
1957 num-lanes = <2>; <<
1958 <<
1959 #address-cells = <3>; <<
1960 #size-cells = <2>; <<
1961 <<
1962 ranges = <0x01000000 <<
1963 <0x02000000 <<
1964 <<
1965 interrupts = <GIC_SPI <<
1966 <GIC_SPI <<
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 <<
1982 interrupt-map-mask = <<
1983 interrupt-map = <0 0 <<
1984 <0 0 <<
1985 <0 0 <<
1986 <0 0 <<
1987 <<
1988 clocks = <&gcc GCC_PC <<
1989 <&gcc GCC_PC <<
1990 <&gcc GCC_PC <<
1991 <&gcc GCC_PC <<
1992 <&gcc GCC_PC <<
1993 <&gcc GCC_PC <<
1994 <&gcc GCC_AG <<
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", <<
1997 "aux", <<
1998 "cfg", <<
1999 "bus_ma <<
2000 "bus_sl <<
2001 "slave_ <<
2002 "tbu", <<
2003 "ref"; <<
2004 <<
2005 assigned-clocks = <&g <<
2006 assigned-clock-rates <<
2007 <<
2008 iommu-map = <0x0 &a <<
2009 <0x100 &a <<
2010 <<
2011 resets = <&gcc GCC_PC <<
2012 reset-names = "pci"; <<
2013 <<
2014 power-domains = <&gcc <<
2015 <<
2016 phys = <&pcie1_phy>; <<
2017 phy-names = "pciephy" <<
2018 <<
2019 perst-gpios = <&tlmm <<
2020 enable-gpio = <&tlmm <<
2021 <<
2022 pinctrl-names = "defa <<
2023 pinctrl-0 = <&pcie1_d <<
2024 <<
2025 status = "disabled"; <<
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; <<
2037 <<
2038 pcie1_phy: phy@1c0e000 { <<
2039 compatible = "qcom,sm <<
2040 reg = <0 0x01c0e000 0 <<
2041 clocks = <&gcc GCC_PC <<
2042 <&gcc GCC_PC <<
2043 <&gcc GCC_PC <<
2044 <&gcc GCC_PC <<
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 <<
2057 resets = <&gcc GCC_PC <<
2058 reset-names = "phy"; <<
2059 <<
2060 assigned-clocks = <&g <<
2061 assigned-clock-rates <<
2062 <<
2063 status = "disabled"; <<
2064 }; <<
2065 <<
2066 ufs_mem_hc: ufshc@1d84000 { 946 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 947 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 948 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 !! 949 reg = <0 0x01d84000 0 0x2500>;
2070 <0 0x01d90000 0 <<
2071 reg-names = "std", "i <<
2072 interrupts = <GIC_SPI 950 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 951 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 952 phy-names = "ufsphy";
2075 lanes-per-direction = 953 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 954 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 955 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 956 reset-names = "rst";
2079 957
2080 iommus = <&apps_smmu 958 iommus = <&apps_smmu 0x300 0>;
2081 959
2082 clock-names = 960 clock-names =
2083 "core_clk", 961 "core_clk",
2084 "bus_aggr_clk 962 "bus_aggr_clk",
2085 "iface_clk", 963 "iface_clk",
2086 "core_clk_uni 964 "core_clk_unipro",
2087 "ref_clk", 965 "ref_clk",
2088 "tx_lane0_syn 966 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 967 "rx_lane0_sync_clk",
2090 "rx_lane1_syn !! 968 "rx_lane1_sync_clk";
2091 "ice_core_clk <<
2092 clocks = 969 clocks =
2093 <&gcc GCC_UFS 970 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 971 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 972 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 973 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 974 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 975 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 976 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS !! 977 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2101 <&gcc GCC_UFS <<
2102 freq-table-hz = 978 freq-table-hz =
2103 <37500000 300 979 <37500000 300000000>,
2104 <0 0>, 980 <0 0>,
2105 <0 0>, 981 <0 0>,
2106 <37500000 300 982 <37500000 300000000>,
2107 <0 0>, 983 <0 0>,
2108 <0 0>, 984 <0 0>,
2109 <0 0>, 985 <0 0>,
2110 <0 0>, !! 986 <0 0>;
2111 <0 300000000> <<
2112 987
2113 status = "disabled"; 988 status = "disabled";
2114 }; 989 };
2115 990
2116 ufs_mem_phy: phy@1d87000 { 991 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 992 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 993 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 994 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 995 #size-cells = <2>;
2121 <&gcc GCC_UF !! 996 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 997 clock-names = "ref",
2124 "ref_au !! 998 "ref_aux";
2125 "qref"; !! 999 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2126 !! 1000 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2127 power-domains = <&gcc <<
2128 1001
2129 resets = <&ufs_mem_hc 1002 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 1003 reset-names = "ufsphy";
>> 1004 status = "disabled";
2131 1005
2132 #phy-cells = <0>; !! 1006 ufs_mem_phy_lanes: lanes@1d87400 {
>> 1007 reg = <0 0x01d87400 0 0x108>,
>> 1008 <0 0x01d87600 0 0x1e0>,
>> 1009 <0 0x01d87c00 0 0x1dc>,
>> 1010 <0 0x01d87800 0 0x108>,
>> 1011 <0 0x01d87a00 0 0x1e0>;
>> 1012 #phy-cells = <0>;
>> 1013 };
>> 1014 };
2133 1015
2134 status = "disabled"; !! 1016 ipa_virt: interconnect@1e00000 {
>> 1017 compatible = "qcom,sm8150-ipa-virt";
>> 1018 reg = <0 0x01e00000 0 0x1000>;
>> 1019 #interconnect-cells = <1>;
>> 1020 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 1021 };
2136 1022
2137 cryptobam: dma-controller@1dc !! 1023 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 1024 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 1025 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 1026 };
2177 1027
2178 remoteproc_slpi: remoteproc@2 1028 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 1029 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 1030 reg = <0x0 0x02400000 0x0 0x4040>;
2181 1031
2182 interrupts-extended = 1032 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 1033 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 1034 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 1035 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 1036 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 1037 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 1038 "handover", "stop-ack";
2189 1039
2190 clocks = <&rpmhcc RPM 1040 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 1041 clock-names = "xo";
2192 1042
2193 power-domains = <&rpm !! 1043 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
2194 <&rpm !! 1044 <&rpmhpd 3>,
2195 power-domain-names = !! 1045 <&rpmhpd 2>;
>> 1046 power-domain-names = "load_state", "lcx", "lmx";
2196 1047
2197 memory-region = <&slp 1048 memory-region = <&slpi_mem>;
2198 1049
2199 qcom,qmp = <&aoss_qmp <<
2200 <<
2201 qcom,smem-states = <& 1050 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 1051 qcom,smem-state-names = "stop";
2203 1052
2204 status = "disabled"; 1053 status = "disabled";
2205 1054
2206 glink-edge { 1055 glink-edge {
2207 interrupts = 1056 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 1057 label = "dsps";
2209 qcom,remote-p 1058 qcom,remote-pid = <3>;
2210 mboxes = <&ap 1059 mboxes = <&apss_shared 24>;
2211 <<
2212 fastrpc { <<
2213 compa <<
2214 qcom, <<
2215 label <<
2216 qcom, <<
2217 #addr <<
2218 #size <<
2219 <<
2220 compu <<
2221 <<
2222 <<
2223 <<
2224 }; <<
2225 <<
2226 compu <<
2227 <<
2228 <<
2229 <<
2230 }; <<
2231 <<
2232 compu <<
2233 <<
2234 <<
2235 <<
2236 <<
2237 }; <<
2238 }; <<
2239 }; 1060 };
2240 }; 1061 };
2241 1062
2242 gpu: gpu@2c00000 { 1063 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 1064 /*
>> 1065 * note: the amd,imageon compatible makes it possible
>> 1066 * to use the drm/msm driver without the display node,
>> 1067 * make sure to remove it when display node is added
>> 1068 */
>> 1069 compatible = "qcom,adreno-640.1",
>> 1070 "qcom,adreno",
>> 1071 "amd,imageon";
>> 1072 #stream-id-cells = <16>;
>> 1073
2244 reg = <0 0x02c00000 0 1074 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 1075 reg-names = "kgsl_3d0_reg_memory";
2246 1076
2247 interrupts = <GIC_SPI 1077 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 1078
2249 iommus = <&adreno_smm 1079 iommus = <&adreno_smmu 0 0x401>;
2250 1080
2251 operating-points-v2 = 1081 operating-points-v2 = <&gpu_opp_table>;
2252 1082
2253 qcom,gmu = <&gmu>; 1083 qcom,gmu = <&gmu>;
2254 1084
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 1085 status = "disabled";
2260 1086
2261 zap-shader { 1087 zap-shader {
2262 memory-region 1088 memory-region = <&gpu_mem>;
2263 }; 1089 };
2264 1090
>> 1091 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 1092 gpu_opp_table: opp-table {
2266 compatible = 1093 compatible = "operating-points-v2";
2267 1094
2268 opp-675000000 1095 opp-675000000 {
2269 opp-h 1096 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 1097 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 1098 };
2273 1099
2274 opp-585000000 1100 opp-585000000 {
2275 opp-h 1101 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 1102 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 1103 };
2279 1104
2280 opp-499200000 1105 opp-499200000 {
2281 opp-h 1106 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 1107 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 1108 };
2285 1109
2286 opp-427000000 1110 opp-427000000 {
2287 opp-h 1111 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 1112 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 1113 };
2291 1114
2292 opp-345000000 1115 opp-345000000 {
2293 opp-h 1116 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 1117 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 1118 };
2297 1119
2298 opp-257000000 1120 opp-257000000 {
2299 opp-h 1121 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 1122 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 1123 };
2303 }; 1124 };
2304 }; 1125 };
2305 1126
2306 gmu: gmu@2c6a000 { 1127 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 1128 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 1129
2309 reg = <0 0x02c6a000 0 1130 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 1131 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 1132 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 1133 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 1134
2314 interrupts = <GIC_SPI 1135 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1136 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 1137 interrupt-names = "hfi", "gmu";
2317 1138
2318 clocks = <&gpucc GPU_ 1139 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 1140 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 1141 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 1142 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 1143 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 1144 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 1145
2325 power-domains = <&gpu 1146 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 1147 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 1148 power-domain-names = "cx", "gx";
2328 1149
2329 iommus = <&adreno_smm 1150 iommus = <&adreno_smmu 5 0x400>;
2330 1151
2331 operating-points-v2 = 1152 operating-points-v2 = <&gmu_opp_table>;
2332 1153
2333 status = "disabled"; 1154 status = "disabled";
2334 1155
2335 gmu_opp_table: opp-ta 1156 gmu_opp_table: opp-table {
2336 compatible = 1157 compatible = "operating-points-v2";
2337 1158
2338 opp-200000000 1159 opp-200000000 {
2339 opp-h 1160 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 1161 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 1162 };
2342 }; 1163 };
2343 }; 1164 };
2344 1165
2345 gpucc: clock-controller@2c900 1166 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 1167 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 1168 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 1169 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 1170 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 1171 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 1172 clock-names = "bi_tcxo",
2352 "gcc_gp 1173 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 1174 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 1175 #clock-cells = <1>;
2355 #reset-cells = <1>; 1176 #reset-cells = <1>;
2356 #power-domain-cells = 1177 #power-domain-cells = <1>;
2357 }; 1178 };
2358 1179
2359 adreno_smmu: iommu@2ca0000 { 1180 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 1181 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 1182 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 1183 #iommu-cells = <2>;
2364 #global-interrupts = 1184 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 1185 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 1186 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 1187 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 1188 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 1189 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 1190 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 1191 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 1192 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 1193 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 1194 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 1195 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 1196 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 1197 clock-names = "ahb", "bus", "iface";
2378 1198
2379 power-domains = <&gpu 1199 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 1200 };
2381 1201
2382 tlmm: pinctrl@3100000 { 1202 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 1203 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 1204 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 1205 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 1206 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 1207 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 1208 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 1210 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 1211 gpio-controller;
2392 #gpio-cells = <2>; 1212 #gpio-cells = <2>;
2393 interrupt-controller; 1213 interrupt-controller;
2394 #interrupt-cells = <2 1214 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc <<
2396 <<
2397 qup_i2c0_default: qup <<
2398 pins = "gpio0 <<
2399 function = "q <<
2400 drive-strengt <<
2401 bias-disable; <<
2402 }; <<
2403 <<
2404 qup_spi0_default: qup <<
2405 pins = "gpio0 <<
2406 function = "q <<
2407 drive-strengt <<
2408 bias-disable; <<
2409 }; <<
2410 <<
2411 qup_i2c1_default: qup <<
2412 pins = "gpio1 <<
2413 function = "q <<
2414 drive-strengt <<
2415 bias-disable; <<
2416 }; <<
2417 <<
2418 qup_spi1_default: qup <<
2419 pins = "gpio1 <<
2420 function = "q <<
2421 drive-strengt <<
2422 bias-disable; <<
2423 }; <<
2424 <<
2425 qup_i2c2_default: qup <<
2426 pins = "gpio1 <<
2427 function = "q <<
2428 drive-strengt <<
2429 bias-disable; <<
2430 }; <<
2431 <<
2432 qup_spi2_default: qup <<
2433 pins = "gpio1 <<
2434 function = "q <<
2435 drive-strengt <<
2436 bias-disable; <<
2437 }; <<
2438 1215
2439 qup_i2c3_default: qup !! 1216 qup_i2c0_default: qup-i2c0-default {
2440 pins = "gpio1 !! 1217 mux {
2441 function = "q !! 1218 pins = "gpio0", "gpio1";
2442 drive-strengt !! 1219 function = "qup0";
2443 bias-disable; !! 1220 };
2444 }; <<
2445 <<
2446 qup_spi3_default: qup <<
2447 pins = "gpio1 <<
2448 function = "q <<
2449 drive-strengt <<
2450 bias-disable; <<
2451 }; <<
2452 1221
2453 qup_i2c4_default: qup !! 1222 config {
2454 pins = "gpio5 !! 1223 pins = "gpio0", "gpio1";
2455 function = "q !! 1224 drive-strength = <0x02>;
2456 drive-strengt !! 1225 bias-disable;
2457 bias-disable; !! 1226 };
2458 }; 1227 };
2459 1228
2460 qup_spi4_default: qup !! 1229 qup_i2c1_default: qup-i2c1-default {
2461 pins = "gpio5 !! 1230 mux {
2462 function = "q !! 1231 pins = "gpio114", "gpio115";
2463 drive-strengt !! 1232 function = "qup1";
2464 bias-disable; !! 1233 };
2465 }; <<
2466 1234
2467 qup_i2c5_default: qup !! 1235 config {
2468 pins = "gpio1 !! 1236 pins = "gpio114", "gpio115";
2469 function = "q !! 1237 drive-strength = <0x02>;
2470 drive-strengt !! 1238 bias-disable;
2471 bias-disable; !! 1239 };
2472 }; 1240 };
2473 1241
2474 qup_spi5_default: qup !! 1242 qup_i2c2_default: qup-i2c2-default {
2475 pins = "gpio1 !! 1243 mux {
2476 function = "q !! 1244 pins = "gpio126", "gpio127";
2477 drive-strengt !! 1245 function = "qup2";
2478 bias-disable; !! 1246 };
2479 }; <<
2480 1247
2481 qup_i2c6_default: qup !! 1248 config {
2482 pins = "gpio6 !! 1249 pins = "gpio126", "gpio127";
2483 function = "q !! 1250 drive-strength = <0x02>;
2484 drive-strengt !! 1251 bias-disable;
2485 bias-disable; !! 1252 };
2486 }; 1253 };
2487 1254
2488 qup_spi6_default: qup !! 1255 qup_i2c3_default: qup-i2c3-default {
2489 pins = "gpio4 !! 1256 mux {
2490 function = "q !! 1257 pins = "gpio144", "gpio145";
2491 drive-strengt !! 1258 function = "qup3";
2492 bias-disable; !! 1259 };
2493 }; <<
2494 1260
2495 qup_i2c7_default: qup !! 1261 config {
2496 pins = "gpio9 !! 1262 pins = "gpio144", "gpio145";
2497 function = "q !! 1263 drive-strength = <0x02>;
2498 drive-strengt !! 1264 bias-disable;
2499 bias-disable; !! 1265 };
2500 }; 1266 };
2501 1267
2502 qup_spi7_default: qup !! 1268 qup_i2c4_default: qup-i2c4-default {
2503 pins = "gpio9 !! 1269 mux {
2504 function = "q !! 1270 pins = "gpio51", "gpio52";
2505 drive-strengt !! 1271 function = "qup4";
2506 bias-disable; !! 1272 };
2507 }; <<
2508 1273
2509 qup_i2c8_default: qup !! 1274 config {
2510 pins = "gpio8 !! 1275 pins = "gpio51", "gpio52";
2511 function = "q !! 1276 drive-strength = <0x02>;
2512 drive-strengt !! 1277 bias-disable;
2513 bias-disable; !! 1278 };
2514 }; 1279 };
2515 1280
2516 qup_spi8_default: qup !! 1281 qup_i2c5_default: qup-i2c5-default {
2517 pins = "gpio8 !! 1282 mux {
2518 function = "q !! 1283 pins = "gpio121", "gpio122";
2519 drive-strengt !! 1284 function = "qup5";
2520 bias-disable; !! 1285 };
2521 }; <<
2522 1286
2523 qup_i2c9_default: qup !! 1287 config {
2524 pins = "gpio3 !! 1288 pins = "gpio121", "gpio122";
2525 function = "q !! 1289 drive-strength = <0x02>;
2526 drive-strengt !! 1290 bias-disable;
2527 bias-disable; !! 1291 };
2528 }; 1292 };
2529 1293
2530 qup_spi9_default: qup !! 1294 qup_i2c6_default: qup-i2c6-default {
2531 pins = "gpio3 !! 1295 mux {
2532 function = "q !! 1296 pins = "gpio6", "gpio7";
2533 drive-strengt !! 1297 function = "qup6";
2534 bias-disable; !! 1298 };
2535 }; <<
2536 1299
2537 qup_uart9_default: qu !! 1300 config {
2538 pins = "gpio4 !! 1301 pins = "gpio6", "gpio7";
2539 function = "q !! 1302 drive-strength = <0x02>;
2540 drive-strengt !! 1303 bias-disable;
2541 bias-disable; !! 1304 };
2542 }; 1305 };
2543 1306
2544 qup_i2c10_default: qu !! 1307 qup_i2c7_default: qup-i2c7-default {
2545 pins = "gpio9 !! 1308 mux {
2546 function = "q !! 1309 pins = "gpio98", "gpio99";
2547 drive-strengt !! 1310 function = "qup7";
2548 bias-disable; !! 1311 };
2549 }; <<
2550 1312
2551 qup_spi10_default: qu !! 1313 config {
2552 pins = "gpio9 !! 1314 pins = "gpio98", "gpio99";
2553 function = "q !! 1315 drive-strength = <0x02>;
2554 drive-strengt !! 1316 bias-disable;
2555 bias-disable; !! 1317 };
2556 }; 1318 };
2557 1319
2558 qup_i2c11_default: qu !! 1320 qup_i2c8_default: qup-i2c8-default {
2559 pins = "gpio9 !! 1321 mux {
2560 function = "q !! 1322 pins = "gpio88", "gpio89";
2561 drive-strengt !! 1323 function = "qup8";
2562 bias-disable; !! 1324 };
2563 }; <<
2564 1325
2565 qup_spi11_default: qu !! 1326 config {
2566 pins = "gpio9 !! 1327 pins = "gpio88", "gpio89";
2567 function = "q !! 1328 drive-strength = <0x02>;
2568 drive-strengt !! 1329 bias-disable;
2569 bias-disable; !! 1330 };
2570 }; 1331 };
2571 1332
2572 qup_i2c12_default: qu !! 1333 qup_i2c9_default: qup-i2c9-default {
2573 pins = "gpio8 !! 1334 mux {
2574 function = "q !! 1335 pins = "gpio39", "gpio40";
2575 drive-strengt !! 1336 function = "qup9";
2576 bias-disable; !! 1337 };
2577 }; <<
2578 1338
2579 qup_spi12_default: qu !! 1339 config {
2580 pins = "gpio8 !! 1340 pins = "gpio39", "gpio40";
2581 function = "q !! 1341 drive-strength = <0x02>;
2582 drive-strengt !! 1342 bias-disable;
2583 bias-disable; !! 1343 };
2584 }; 1344 };
2585 1345
2586 qup_i2c13_default: qu !! 1346 qup_i2c10_default: qup-i2c10-default {
2587 pins = "gpio4 !! 1347 mux {
2588 function = "q !! 1348 pins = "gpio9", "gpio10";
2589 drive-strengt !! 1349 function = "qup10";
2590 bias-disable; !! 1350 };
2591 }; <<
2592 1351
2593 qup_spi13_default: qu !! 1352 config {
2594 pins = "gpio4 !! 1353 pins = "gpio9", "gpio10";
2595 function = "q !! 1354 drive-strength = <0x02>;
2596 drive-strengt !! 1355 bias-disable;
2597 bias-disable; !! 1356 };
2598 }; 1357 };
2599 1358
2600 qup_i2c14_default: qu !! 1359 qup_i2c11_default: qup-i2c11-default {
2601 pins = "gpio4 !! 1360 mux {
2602 function = "q !! 1361 pins = "gpio94", "gpio95";
2603 drive-strengt !! 1362 function = "qup11";
2604 bias-disable; !! 1363 };
2605 }; <<
2606 1364
2607 qup_spi14_default: qu !! 1365 config {
2608 pins = "gpio4 !! 1366 pins = "gpio94", "gpio95";
2609 function = "q !! 1367 drive-strength = <0x02>;
2610 drive-strengt !! 1368 bias-disable;
2611 bias-disable; !! 1369 };
2612 }; 1370 };
2613 1371
2614 qup_i2c15_default: qu !! 1372 qup_i2c12_default: qup-i2c12-default {
2615 pins = "gpio2 !! 1373 mux {
2616 function = "q !! 1374 pins = "gpio83", "gpio84";
2617 drive-strengt !! 1375 function = "qup12";
2618 bias-disable; !! 1376 };
2619 }; <<
2620 1377
2621 qup_spi15_default: qu !! 1378 config {
2622 pins = "gpio2 !! 1379 pins = "gpio83", "gpio84";
2623 function = "q !! 1380 drive-strength = <0x02>;
2624 drive-strengt !! 1381 bias-disable;
2625 bias-disable; !! 1382 };
2626 }; 1383 };
2627 1384
2628 qup_i2c16_default: qu !! 1385 qup_i2c13_default: qup-i2c13-default {
2629 pins = "gpio8 !! 1386 mux {
2630 function = "q !! 1387 pins = "gpio43", "gpio44";
2631 drive-strengt !! 1388 function = "qup13";
2632 bias-disable; !! 1389 };
2633 }; <<
2634 1390
2635 qup_spi16_default: qu !! 1391 config {
2636 pins = "gpio8 !! 1392 pins = "gpio43", "gpio44";
2637 function = "q !! 1393 drive-strength = <0x02>;
2638 drive-strengt !! 1394 bias-disable;
2639 bias-disable; !! 1395 };
2640 }; 1396 };
2641 1397
2642 qup_i2c17_default: qu !! 1398 qup_i2c14_default: qup-i2c14-default {
2643 pins = "gpio5 !! 1399 mux {
2644 function = "q !! 1400 pins = "gpio47", "gpio48";
2645 drive-strengt !! 1401 function = "qup14";
2646 bias-disable; !! 1402 };
2647 }; <<
2648 1403
2649 qup_spi17_default: qu !! 1404 config {
2650 pins = "gpio5 !! 1405 pins = "gpio47", "gpio48";
2651 function = "q !! 1406 drive-strength = <0x02>;
2652 drive-strengt !! 1407 bias-disable;
2653 bias-disable; !! 1408 };
2654 }; 1409 };
2655 1410
2656 qup_i2c18_default: qu !! 1411 qup_i2c15_default: qup-i2c15-default {
2657 pins = "gpio2 !! 1412 mux {
2658 function = "q !! 1413 pins = "gpio27", "gpio28";
2659 drive-strengt !! 1414 function = "qup15";
2660 bias-disable; !! 1415 };
2661 }; <<
2662 1416
2663 qup_spi18_default: qu !! 1417 config {
2664 pins = "gpio2 !! 1418 pins = "gpio27", "gpio28";
2665 function = "q !! 1419 drive-strength = <0x02>;
2666 drive-strengt !! 1420 bias-disable;
2667 bias-disable; !! 1421 };
2668 }; 1422 };
2669 1423
2670 qup_i2c19_default: qu !! 1424 qup_i2c16_default: qup-i2c16-default {
2671 pins = "gpio5 !! 1425 mux {
2672 function = "q !! 1426 pins = "gpio86", "gpio85";
2673 drive-strengt !! 1427 function = "qup16";
2674 bias-disable; !! 1428 };
2675 }; <<
2676 1429
2677 qup_spi19_default: qu !! 1430 config {
2678 pins = "gpio5 !! 1431 pins = "gpio86", "gpio85";
2679 function = "q !! 1432 drive-strength = <0x02>;
2680 drive-strengt !! 1433 bias-disable;
2681 bias-disable; !! 1434 };
2682 }; 1435 };
2683 1436
2684 pcie0_default_state: !! 1437 qup_i2c17_default: qup-i2c17-default {
2685 perst-pins { !! 1438 mux {
2686 pins !! 1439 pins = "gpio55", "gpio56";
2687 funct !! 1440 function = "qup17";
2688 drive <<
2689 bias- <<
2690 }; 1441 };
2691 1442
2692 clkreq-pins { !! 1443 config {
2693 pins !! 1444 pins = "gpio55", "gpio56";
2694 funct !! 1445 drive-strength = <0x02>;
2695 drive !! 1446 bias-disable;
2696 bias- <<
2697 }; 1447 };
>> 1448 };
2698 1449
2699 wake-pins { !! 1450 qup_i2c18_default: qup-i2c18-default {
2700 pins !! 1451 mux {
2701 funct !! 1452 pins = "gpio23", "gpio24";
2702 drive !! 1453 function = "qup18";
2703 bias- <<
2704 }; 1454 };
2705 }; <<
2706 1455
2707 pcie1_default_state: !! 1456 config {
2708 perst-pins { !! 1457 pins = "gpio23", "gpio24";
2709 pins !! 1458 drive-strength = <0x02>;
2710 funct !! 1459 bias-disable;
2711 drive <<
2712 bias- <<
2713 }; 1460 };
>> 1461 };
2714 1462
2715 clkreq-pins { !! 1463 qup_i2c19_default: qup-i2c19-default {
2716 pins !! 1464 mux {
2717 funct !! 1465 pins = "gpio57", "gpio58";
2718 drive !! 1466 function = "qup19";
2719 bias- <<
2720 }; 1467 };
2721 1468
2722 wake-pins { !! 1469 config {
2723 pins !! 1470 pins = "gpio57", "gpio58";
2724 funct !! 1471 drive-strength = <0x02>;
2725 drive !! 1472 bias-disable;
2726 bias- <<
2727 }; 1473 };
2728 }; 1474 };
2729 }; 1475 };
2730 1476
2731 remoteproc_mpss: remoteproc@4 1477 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 1478 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 1479 reg = <0x0 0x04080000 0x0 0x4040>;
2734 1480
2735 interrupts-extended = 1481 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 1482 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 1483 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 1484 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 1485 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 1486 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 1487 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 1488 "stop-ack", "shutdown-ack";
2743 1489
2744 clocks = <&rpmhcc RPM 1490 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 1491 clock-names = "xo";
2746 1492
2747 power-domains = <&rpm !! 1493 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2748 <&rpm !! 1494 <&rpmhpd 7>,
2749 power-domain-names = !! 1495 <&rpmhpd 0>;
>> 1496 power-domain-names = "load_state", "cx", "mss";
2750 1497
2751 memory-region = <&mps 1498 memory-region = <&mpss_mem>;
2752 1499
2753 qcom,qmp = <&aoss_qmp <<
2754 <<
2755 qcom,smem-states = <& 1500 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 1501 qcom,smem-state-names = "stop";
2757 1502
2758 status = "disabled"; 1503 status = "disabled";
2759 1504
2760 glink-edge { 1505 glink-edge {
2761 interrupts = 1506 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 1507 label = "modem";
2763 qcom,remote-p 1508 qcom,remote-pid = <1>;
2764 mboxes = <&ap 1509 mboxes = <&apss_shared 12>;
2765 }; 1510 };
2766 }; 1511 };
2767 1512
2768 stm@6002000 { 1513 stm@6002000 {
2769 compatible = "arm,cor 1514 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 1515 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 1516 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 1517 reg-names = "stm-base", "stm-stimulus-base";
2773 1518
2774 clocks = <&aoss_qmp>; 1519 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 1520 clock-names = "apb_pclk";
2776 1521
2777 out-ports { 1522 out-ports {
2778 port { 1523 port {
2779 stm_o 1524 stm_out: endpoint {
2780 1525 remote-endpoint = <&funnel0_in7>;
2781 }; 1526 };
2782 }; 1527 };
2783 }; 1528 };
2784 }; 1529 };
2785 1530
2786 funnel@6041000 { 1531 funnel@6041000 {
2787 compatible = "arm,cor 1532 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 1533 reg = <0 0x06041000 0 0x1000>;
2789 1534
2790 clocks = <&aoss_qmp>; 1535 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 1536 clock-names = "apb_pclk";
2792 1537
2793 out-ports { 1538 out-ports {
2794 port { 1539 port {
2795 funne 1540 funnel0_out: endpoint {
2796 1541 remote-endpoint = <&merge_funnel_in0>;
2797 }; 1542 };
2798 }; 1543 };
2799 }; 1544 };
2800 1545
2801 in-ports { 1546 in-ports {
2802 #address-cell 1547 #address-cells = <1>;
2803 #size-cells = 1548 #size-cells = <0>;
2804 1549
2805 port@7 { 1550 port@7 {
2806 reg = 1551 reg = <7>;
2807 funne 1552 funnel0_in7: endpoint {
2808 1553 remote-endpoint = <&stm_out>;
2809 }; 1554 };
2810 }; 1555 };
2811 }; 1556 };
2812 }; 1557 };
2813 1558
2814 funnel@6042000 { 1559 funnel@6042000 {
2815 compatible = "arm,cor 1560 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 1561 reg = <0 0x06042000 0 0x1000>;
2817 1562
2818 clocks = <&aoss_qmp>; 1563 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 1564 clock-names = "apb_pclk";
2820 1565
2821 out-ports { 1566 out-ports {
2822 port { 1567 port {
2823 funne 1568 funnel1_out: endpoint {
2824 1569 remote-endpoint = <&merge_funnel_in1>;
2825 }; 1570 };
2826 }; 1571 };
2827 }; 1572 };
2828 1573
2829 in-ports { 1574 in-ports {
2830 #address-cell 1575 #address-cells = <1>;
2831 #size-cells = 1576 #size-cells = <0>;
2832 1577
2833 port@4 { 1578 port@4 {
2834 reg = 1579 reg = <4>;
2835 funne 1580 funnel1_in4: endpoint {
2836 1581 remote-endpoint = <&swao_replicator_out>;
2837 }; 1582 };
2838 }; 1583 };
2839 }; 1584 };
2840 }; 1585 };
2841 1586
2842 funnel@6043000 { 1587 funnel@6043000 {
2843 compatible = "arm,cor 1588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 1589 reg = <0 0x06043000 0 0x1000>;
2845 1590
2846 clocks = <&aoss_qmp>; 1591 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 1592 clock-names = "apb_pclk";
2848 1593
2849 out-ports { 1594 out-ports {
2850 port { 1595 port {
2851 funne 1596 funnel2_out: endpoint {
2852 1597 remote-endpoint = <&merge_funnel_in2>;
2853 }; 1598 };
2854 }; 1599 };
2855 }; 1600 };
2856 1601
2857 in-ports { 1602 in-ports {
2858 #address-cell 1603 #address-cells = <1>;
2859 #size-cells = 1604 #size-cells = <0>;
2860 1605
2861 port@2 { 1606 port@2 {
2862 reg = 1607 reg = <2>;
2863 funne 1608 funnel2_in2: endpoint {
2864 1609 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 1610 };
2866 }; 1611 };
2867 }; 1612 };
2868 }; 1613 };
2869 1614
2870 funnel@6045000 { 1615 funnel@6045000 {
2871 compatible = "arm,cor 1616 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 1617 reg = <0 0x06045000 0 0x1000>;
2873 1618
2874 clocks = <&aoss_qmp>; 1619 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 1620 clock-names = "apb_pclk";
2876 1621
2877 out-ports { 1622 out-ports {
2878 port { 1623 port {
2879 merge 1624 merge_funnel_out: endpoint {
2880 1625 remote-endpoint = <&etf_in>;
2881 }; 1626 };
2882 }; 1627 };
2883 }; 1628 };
2884 1629
2885 in-ports { 1630 in-ports {
2886 #address-cell 1631 #address-cells = <1>;
2887 #size-cells = 1632 #size-cells = <0>;
2888 1633
2889 port@0 { 1634 port@0 {
2890 reg = 1635 reg = <0>;
2891 merge 1636 merge_funnel_in0: endpoint {
2892 1637 remote-endpoint = <&funnel0_out>;
2893 }; 1638 };
2894 }; 1639 };
2895 1640
2896 port@1 { 1641 port@1 {
2897 reg = 1642 reg = <1>;
2898 merge 1643 merge_funnel_in1: endpoint {
2899 1644 remote-endpoint = <&funnel1_out>;
2900 }; 1645 };
2901 }; 1646 };
2902 1647
2903 port@2 { 1648 port@2 {
2904 reg = 1649 reg = <2>;
2905 merge 1650 merge_funnel_in2: endpoint {
2906 1651 remote-endpoint = <&funnel2_out>;
2907 }; 1652 };
2908 }; 1653 };
2909 }; 1654 };
2910 }; 1655 };
2911 1656
2912 replicator@6046000 { 1657 replicator@6046000 {
2913 compatible = "arm,cor 1658 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 1659 reg = <0 0x06046000 0 0x1000>;
2915 1660
2916 clocks = <&aoss_qmp>; 1661 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 1662 clock-names = "apb_pclk";
2918 1663
2919 out-ports { 1664 out-ports {
2920 #address-cell 1665 #address-cells = <1>;
2921 #size-cells = 1666 #size-cells = <0>;
2922 1667
2923 port@0 { 1668 port@0 {
2924 reg = 1669 reg = <0>;
2925 repli 1670 replicator_out0: endpoint {
2926 1671 remote-endpoint = <&etr_in>;
2927 }; 1672 };
2928 }; 1673 };
2929 1674
2930 port@1 { 1675 port@1 {
2931 reg = 1676 reg = <1>;
2932 repli 1677 replicator_out1: endpoint {
2933 1678 remote-endpoint = <&replicator1_in>;
2934 }; 1679 };
2935 }; 1680 };
2936 }; 1681 };
2937 1682
2938 in-ports { 1683 in-ports {
2939 port { 1684 port {
2940 repli 1685 replicator_in0: endpoint {
2941 1686 remote-endpoint = <&etf_out>;
2942 }; 1687 };
2943 }; 1688 };
2944 }; 1689 };
2945 }; 1690 };
2946 1691
2947 etf@6047000 { 1692 etf@6047000 {
2948 compatible = "arm,cor 1693 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 1694 reg = <0 0x06047000 0 0x1000>;
2950 1695
2951 clocks = <&aoss_qmp>; 1696 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 1697 clock-names = "apb_pclk";
2953 1698
2954 out-ports { 1699 out-ports {
2955 port { 1700 port {
2956 etf_o 1701 etf_out: endpoint {
2957 1702 remote-endpoint = <&replicator_in0>;
2958 }; 1703 };
2959 }; 1704 };
2960 }; 1705 };
2961 1706
2962 in-ports { 1707 in-ports {
2963 port { 1708 port {
2964 etf_i 1709 etf_in: endpoint {
2965 1710 remote-endpoint = <&merge_funnel_out>;
2966 }; 1711 };
2967 }; 1712 };
2968 }; 1713 };
2969 }; 1714 };
2970 1715
2971 etr@6048000 { 1716 etr@6048000 {
2972 compatible = "arm,cor 1717 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 1718 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 1719 iommus = <&apps_smmu 0x05e0 0x0>;
2975 1720
2976 clocks = <&aoss_qmp>; 1721 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 1722 clock-names = "apb_pclk";
2978 arm,scatter-gather; 1723 arm,scatter-gather;
2979 1724
2980 in-ports { 1725 in-ports {
2981 port { 1726 port {
2982 etr_i 1727 etr_in: endpoint {
2983 1728 remote-endpoint = <&replicator_out0>;
2984 }; 1729 };
2985 }; 1730 };
2986 }; 1731 };
2987 }; 1732 };
2988 1733
2989 replicator@604a000 { 1734 replicator@604a000 {
2990 compatible = "arm,cor 1735 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 1736 reg = <0 0x0604a000 0 0x1000>;
2992 1737
2993 clocks = <&aoss_qmp>; 1738 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 1739 clock-names = "apb_pclk";
2995 1740
2996 out-ports { 1741 out-ports {
2997 #address-cell 1742 #address-cells = <1>;
2998 #size-cells = 1743 #size-cells = <0>;
2999 1744
3000 port@1 { 1745 port@1 {
3001 reg = 1746 reg = <1>;
3002 repli 1747 replicator1_out: endpoint {
3003 1748 remote-endpoint = <&swao_funnel_in>;
3004 }; 1749 };
3005 }; 1750 };
3006 }; 1751 };
3007 1752
3008 in-ports { 1753 in-ports {
>> 1754 #address-cells = <1>;
>> 1755 #size-cells = <0>;
3009 1756
3010 port { !! 1757 port@1 {
>> 1758 reg = <1>;
3011 repli 1759 replicator1_in: endpoint {
3012 1760 remote-endpoint = <&replicator_out1>;
3013 }; 1761 };
3014 }; 1762 };
3015 }; 1763 };
3016 }; 1764 };
3017 1765
3018 funnel@6b08000 { 1766 funnel@6b08000 {
3019 compatible = "arm,cor 1767 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 1768 reg = <0 0x06b08000 0 0x1000>;
3021 1769
3022 clocks = <&aoss_qmp>; 1770 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 1771 clock-names = "apb_pclk";
3024 1772
3025 out-ports { 1773 out-ports {
3026 port { 1774 port {
3027 swao_ 1775 swao_funnel_out: endpoint {
3028 1776 remote-endpoint = <&swao_etf_in>;
3029 }; 1777 };
3030 }; 1778 };
3031 }; 1779 };
3032 1780
3033 in-ports { 1781 in-ports {
3034 #address-cell 1782 #address-cells = <1>;
3035 #size-cells = 1783 #size-cells = <0>;
3036 1784
3037 port@6 { 1785 port@6 {
3038 reg = 1786 reg = <6>;
3039 swao_ 1787 swao_funnel_in: endpoint {
3040 1788 remote-endpoint = <&replicator1_out>;
3041 }; 1789 };
3042 }; 1790 };
3043 }; 1791 };
3044 }; 1792 };
3045 1793
3046 etf@6b09000 { 1794 etf@6b09000 {
3047 compatible = "arm,cor 1795 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 1796 reg = <0 0x06b09000 0 0x1000>;
3049 1797
3050 clocks = <&aoss_qmp>; 1798 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 1799 clock-names = "apb_pclk";
3052 1800
3053 out-ports { 1801 out-ports {
3054 port { 1802 port {
3055 swao_ 1803 swao_etf_out: endpoint {
3056 1804 remote-endpoint = <&swao_replicator_in>;
3057 }; 1805 };
3058 }; 1806 };
3059 }; 1807 };
3060 1808
3061 in-ports { 1809 in-ports {
3062 port { 1810 port {
3063 swao_ 1811 swao_etf_in: endpoint {
3064 1812 remote-endpoint = <&swao_funnel_out>;
3065 }; 1813 };
3066 }; 1814 };
3067 }; 1815 };
3068 }; 1816 };
3069 1817
3070 replicator@6b0a000 { 1818 replicator@6b0a000 {
3071 compatible = "arm,cor 1819 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 1820 reg = <0 0x06b0a000 0 0x1000>;
3073 1821
3074 clocks = <&aoss_qmp>; 1822 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 1823 clock-names = "apb_pclk";
3076 qcom,replicator-loses 1824 qcom,replicator-loses-context;
3077 1825
3078 out-ports { 1826 out-ports {
3079 port { 1827 port {
3080 swao_ 1828 swao_replicator_out: endpoint {
3081 1829 remote-endpoint = <&funnel1_in4>;
3082 }; 1830 };
3083 }; 1831 };
3084 }; 1832 };
3085 1833
3086 in-ports { 1834 in-ports {
3087 port { 1835 port {
3088 swao_ 1836 swao_replicator_in: endpoint {
3089 1837 remote-endpoint = <&swao_etf_out>;
3090 }; 1838 };
3091 }; 1839 };
3092 }; 1840 };
3093 }; 1841 };
3094 1842
3095 etm@7040000 { 1843 etm@7040000 {
3096 compatible = "arm,cor 1844 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 1845 reg = <0 0x07040000 0 0x1000>;
3098 1846
3099 cpu = <&CPU0>; 1847 cpu = <&CPU0>;
3100 1848
3101 clocks = <&aoss_qmp>; 1849 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 1850 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 1851 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 1852 qcom,skip-power-up;
3105 1853
3106 out-ports { 1854 out-ports {
3107 port { 1855 port {
3108 etm0_ 1856 etm0_out: endpoint {
3109 1857 remote-endpoint = <&apss_funnel_in0>;
3110 }; 1858 };
3111 }; 1859 };
3112 }; 1860 };
3113 }; 1861 };
3114 1862
3115 etm@7140000 { 1863 etm@7140000 {
3116 compatible = "arm,cor 1864 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 1865 reg = <0 0x07140000 0 0x1000>;
3118 1866
3119 cpu = <&CPU1>; 1867 cpu = <&CPU1>;
3120 1868
3121 clocks = <&aoss_qmp>; 1869 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 1870 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 1871 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 1872 qcom,skip-power-up;
3125 1873
3126 out-ports { 1874 out-ports {
3127 port { 1875 port {
3128 etm1_ 1876 etm1_out: endpoint {
3129 1877 remote-endpoint = <&apss_funnel_in1>;
3130 }; 1878 };
3131 }; 1879 };
3132 }; 1880 };
3133 }; 1881 };
3134 1882
3135 etm@7240000 { 1883 etm@7240000 {
3136 compatible = "arm,cor 1884 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 1885 reg = <0 0x07240000 0 0x1000>;
3138 1886
3139 cpu = <&CPU2>; 1887 cpu = <&CPU2>;
3140 1888
3141 clocks = <&aoss_qmp>; 1889 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 1890 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 1891 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 1892 qcom,skip-power-up;
3145 1893
3146 out-ports { 1894 out-ports {
3147 port { 1895 port {
3148 etm2_ 1896 etm2_out: endpoint {
3149 1897 remote-endpoint = <&apss_funnel_in2>;
3150 }; 1898 };
3151 }; 1899 };
3152 }; 1900 };
3153 }; 1901 };
3154 1902
3155 etm@7340000 { 1903 etm@7340000 {
3156 compatible = "arm,cor 1904 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 1905 reg = <0 0x07340000 0 0x1000>;
3158 1906
3159 cpu = <&CPU3>; 1907 cpu = <&CPU3>;
3160 1908
3161 clocks = <&aoss_qmp>; 1909 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 1910 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 1911 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 1912 qcom,skip-power-up;
3165 1913
3166 out-ports { 1914 out-ports {
3167 port { 1915 port {
3168 etm3_ 1916 etm3_out: endpoint {
3169 1917 remote-endpoint = <&apss_funnel_in3>;
3170 }; 1918 };
3171 }; 1919 };
3172 }; 1920 };
3173 }; 1921 };
3174 1922
3175 etm@7440000 { 1923 etm@7440000 {
3176 compatible = "arm,cor 1924 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 1925 reg = <0 0x07440000 0 0x1000>;
3178 1926
3179 cpu = <&CPU4>; 1927 cpu = <&CPU4>;
3180 1928
3181 clocks = <&aoss_qmp>; 1929 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 1930 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 1931 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 1932 qcom,skip-power-up;
3185 1933
3186 out-ports { 1934 out-ports {
3187 port { 1935 port {
3188 etm4_ 1936 etm4_out: endpoint {
3189 1937 remote-endpoint = <&apss_funnel_in4>;
3190 }; 1938 };
3191 }; 1939 };
3192 }; 1940 };
3193 }; 1941 };
3194 1942
3195 etm@7540000 { 1943 etm@7540000 {
3196 compatible = "arm,cor 1944 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 1945 reg = <0 0x07540000 0 0x1000>;
3198 1946
3199 cpu = <&CPU5>; 1947 cpu = <&CPU5>;
3200 1948
3201 clocks = <&aoss_qmp>; 1949 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 1950 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 1951 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 1952 qcom,skip-power-up;
3205 1953
3206 out-ports { 1954 out-ports {
3207 port { 1955 port {
3208 etm5_ 1956 etm5_out: endpoint {
3209 1957 remote-endpoint = <&apss_funnel_in5>;
3210 }; 1958 };
3211 }; 1959 };
3212 }; 1960 };
3213 }; 1961 };
3214 1962
3215 etm@7640000 { 1963 etm@7640000 {
3216 compatible = "arm,cor 1964 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 1965 reg = <0 0x07640000 0 0x1000>;
3218 1966
3219 cpu = <&CPU6>; 1967 cpu = <&CPU6>;
3220 1968
3221 clocks = <&aoss_qmp>; 1969 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 1970 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 1971 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 1972 qcom,skip-power-up;
3225 1973
3226 out-ports { 1974 out-ports {
3227 port { 1975 port {
3228 etm6_ 1976 etm6_out: endpoint {
3229 1977 remote-endpoint = <&apss_funnel_in6>;
3230 }; 1978 };
3231 }; 1979 };
3232 }; 1980 };
3233 }; 1981 };
3234 1982
3235 etm@7740000 { 1983 etm@7740000 {
3236 compatible = "arm,cor 1984 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 1985 reg = <0 0x07740000 0 0x1000>;
3238 1986
3239 cpu = <&CPU7>; 1987 cpu = <&CPU7>;
3240 1988
3241 clocks = <&aoss_qmp>; 1989 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 1990 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 1991 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 1992 qcom,skip-power-up;
3245 1993
3246 out-ports { 1994 out-ports {
3247 port { 1995 port {
3248 etm7_ 1996 etm7_out: endpoint {
3249 1997 remote-endpoint = <&apss_funnel_in7>;
3250 }; 1998 };
3251 }; 1999 };
3252 }; 2000 };
3253 }; 2001 };
3254 2002
3255 funnel@7800000 { /* APSS Funn 2003 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 2004 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 2005 reg = <0 0x07800000 0 0x1000>;
3258 2006
3259 clocks = <&aoss_qmp>; 2007 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 2008 clock-names = "apb_pclk";
3261 2009
3262 out-ports { 2010 out-ports {
3263 port { 2011 port {
3264 apss_ 2012 apss_funnel_out: endpoint {
3265 2013 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 2014 };
3267 }; 2015 };
3268 }; 2016 };
3269 2017
3270 in-ports { 2018 in-ports {
3271 #address-cell 2019 #address-cells = <1>;
3272 #size-cells = 2020 #size-cells = <0>;
3273 2021
3274 port@0 { 2022 port@0 {
3275 reg = 2023 reg = <0>;
3276 apss_ 2024 apss_funnel_in0: endpoint {
3277 2025 remote-endpoint = <&etm0_out>;
3278 }; 2026 };
3279 }; 2027 };
3280 2028
3281 port@1 { 2029 port@1 {
3282 reg = 2030 reg = <1>;
3283 apss_ 2031 apss_funnel_in1: endpoint {
3284 2032 remote-endpoint = <&etm1_out>;
3285 }; 2033 };
3286 }; 2034 };
3287 2035
3288 port@2 { 2036 port@2 {
3289 reg = 2037 reg = <2>;
3290 apss_ 2038 apss_funnel_in2: endpoint {
3291 2039 remote-endpoint = <&etm2_out>;
3292 }; 2040 };
3293 }; 2041 };
3294 2042
3295 port@3 { 2043 port@3 {
3296 reg = 2044 reg = <3>;
3297 apss_ 2045 apss_funnel_in3: endpoint {
3298 2046 remote-endpoint = <&etm3_out>;
3299 }; 2047 };
3300 }; 2048 };
3301 2049
3302 port@4 { 2050 port@4 {
3303 reg = 2051 reg = <4>;
3304 apss_ 2052 apss_funnel_in4: endpoint {
3305 2053 remote-endpoint = <&etm4_out>;
3306 }; 2054 };
3307 }; 2055 };
3308 2056
3309 port@5 { 2057 port@5 {
3310 reg = 2058 reg = <5>;
3311 apss_ 2059 apss_funnel_in5: endpoint {
3312 2060 remote-endpoint = <&etm5_out>;
3313 }; 2061 };
3314 }; 2062 };
3315 2063
3316 port@6 { 2064 port@6 {
3317 reg = 2065 reg = <6>;
3318 apss_ 2066 apss_funnel_in6: endpoint {
3319 2067 remote-endpoint = <&etm6_out>;
3320 }; 2068 };
3321 }; 2069 };
3322 2070
3323 port@7 { 2071 port@7 {
3324 reg = 2072 reg = <7>;
3325 apss_ 2073 apss_funnel_in7: endpoint {
3326 2074 remote-endpoint = <&etm7_out>;
3327 }; 2075 };
3328 }; 2076 };
3329 }; 2077 };
3330 }; 2078 };
3331 2079
3332 funnel@7810000 { 2080 funnel@7810000 {
3333 compatible = "arm,cor 2081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 2082 reg = <0 0x07810000 0 0x1000>;
3335 2083
3336 clocks = <&aoss_qmp>; 2084 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 2085 clock-names = "apb_pclk";
3338 2086
3339 out-ports { 2087 out-ports {
3340 port { 2088 port {
3341 apss_ 2089 apss_merge_funnel_out: endpoint {
3342 2090 remote-endpoint = <&funnel2_in2>;
3343 }; 2091 };
3344 }; 2092 };
3345 }; 2093 };
3346 2094
3347 in-ports { 2095 in-ports {
3348 port { 2096 port {
3349 apss_ 2097 apss_merge_funnel_in: endpoint {
3350 2098 remote-endpoint = <&apss_funnel_out>;
3351 }; 2099 };
3352 }; 2100 };
3353 }; 2101 };
3354 }; 2102 };
3355 2103
3356 remoteproc_cdsp: remoteproc@8 2104 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 2105 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 2106 reg = <0x0 0x08300000 0x0 0x4040>;
3359 2107
3360 interrupts-extended = 2108 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 2109 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 2110 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 2111 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 2112 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 2113 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 2114 "handover", "stop-ack";
3367 2115
3368 clocks = <&rpmhcc RPM 2116 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 2117 clock-names = "xo";
3370 2118
3371 power-domains = <&rpm !! 2119 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 2120 <&rpmhpd 7>;
>> 2121 power-domain-names = "load_state", "cx";
3372 2122
3373 memory-region = <&cds 2123 memory-region = <&cdsp_mem>;
3374 2124
3375 qcom,qmp = <&aoss_qmp <<
3376 <<
3377 qcom,smem-states = <& 2125 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 2126 qcom,smem-state-names = "stop";
3379 2127
3380 status = "disabled"; 2128 status = "disabled";
3381 2129
3382 glink-edge { 2130 glink-edge {
3383 interrupts = 2131 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 2132 label = "cdsp";
3385 qcom,remote-p 2133 qcom,remote-pid = <5>;
3386 mboxes = <&ap 2134 mboxes = <&apss_shared 4>;
3387 <<
3388 fastrpc { <<
3389 compa <<
3390 qcom, <<
3391 label <<
3392 qcom, <<
3393 #addr <<
3394 #size <<
3395 <<
3396 compu <<
3397 <<
3398 <<
3399 <<
3400 }; <<
3401 <<
3402 compu <<
3403 <<
3404 <<
3405 <<
3406 }; <<
3407 <<
3408 compu <<
3409 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 compu <<
3415 <<
3416 <<
3417 <<
3418 }; <<
3419 <<
3420 compu <<
3421 <<
3422 <<
3423 <<
3424 }; <<
3425 <<
3426 compu <<
3427 <<
3428 <<
3429 <<
3430 }; <<
3431 <<
3432 compu <<
3433 <<
3434 <<
3435 <<
3436 }; <<
3437 <<
3438 compu <<
3439 <<
3440 <<
3441 <<
3442 }; <<
3443 <<
3444 /* no <<
3445 }; <<
3446 }; 2135 };
3447 }; 2136 };
3448 2137
3449 usb_1_hsphy: phy@88e2000 { 2138 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 2139 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 2140 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 2141 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 2142 status = "disabled";
3454 #phy-cells = <0>; 2143 #phy-cells = <0>;
3455 2144
3456 clocks = <&rpmhcc RPM 2145 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 2146 clock-names = "ref";
3458 2147
3459 resets = <&gcc GCC_QU 2148 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 2149 };
3461 2150
3462 usb_2_hsphy: phy@88e3000 { 2151 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 2152 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 2153 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 2154 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 2155 status = "disabled";
3467 #phy-cells = <0>; 2156 #phy-cells = <0>;
3468 2157
3469 clocks = <&rpmhcc RPM 2158 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 2159 clock-names = "ref";
3471 2160
3472 resets = <&gcc GCC_QU 2161 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 2162 };
3474 2163
3475 usb_1_qmpphy: phy@88e8000 { !! 2164 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 2165 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 2166 reg = <0 0x088e9000 0 0x18c>,
>> 2167 <0 0x088e8000 0 0x10>;
>> 2168 reg-names = "reg-base", "dp_com";
>> 2169 status = "disabled";
>> 2170 #address-cells = <2>;
>> 2171 #size-cells = <2>;
>> 2172 ranges;
3478 2173
3479 clocks = <&gcc GCC_US 2174 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 2175 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 2176 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 2177 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 2178 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 2179
3488 resets = <&gcc GCC_US 2180 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 2181 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 2182 reset-names = "phy", "common";
3491 2183
3492 #clock-cells = <1>; !! 2184 usb_1_ssphy: lanes@88e9200 {
3493 #phy-cells = <1>; !! 2185 reg = <0 0x088e9200 0 0x200>,
3494 !! 2186 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 2187 <0 0x088e9c00 0 0x218>,
3496 !! 2188 <0 0x088e9600 0 0x200>,
3497 ports { !! 2189 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 2190 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 2191 #clock-cells = <0>;
3500 !! 2192 #phy-cells = <0>;
3501 port@0 { !! 2193 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 2194 clock-names = "pipe0";
3503 !! 2195 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; <<
3524 }; <<
3525 <<
3526 usb_2_qmpphy: phy@88eb000 { <<
3527 compatible = "qcom,sm <<
3528 reg = <0 0x088eb000 0 <<
3529 <<
3530 clocks = <&gcc GCC_US <<
3531 <&gcc GCC_US <<
3532 <&gcc GCC_US <<
3533 <&gcc GCC_US <<
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 <<
3542 resets = <&gcc GCC_US <<
3543 <&gcc GCC_US <<
3544 reset-names = "phy", <<
3545 "phy_ph <<
3546 <<
3547 status = "disabled"; <<
3548 }; <<
3549 <<
3550 sdhc_2: mmc@8804000 { <<
3551 compatible = "qcom,sm <<
3552 reg = <0 0x08804000 0 <<
3553 <<
3554 interrupts = <GIC_SPI <<
3555 <GIC_SPI <<
3556 interrupt-names = "hc <<
3557 <<
3558 clocks = <&gcc GCC_SD <<
3559 <&gcc GCC_SD <<
3560 <&rpmhcc RPM <<
3561 clock-names = "iface" <<
3562 iommus = <&apps_smmu <<
3563 qcom,dll-config = <0x <<
3564 qcom,ddr-config = <0x <<
3565 power-domains = <&rpm <<
3566 operating-points-v2 = <<
3567 <<
3568 status = "disabled"; <<
3569 <<
3570 sdhc2_opp_table: opp- <<
3571 compatible = <<
3572 <<
3573 opp-19200000 <<
3574 opp-h <<
3575 requi <<
3576 }; <<
3577 <<
3578 opp-50000000 <<
3579 opp-h <<
3580 requi <<
3581 }; <<
3582 <<
3583 opp-100000000 <<
3584 opp-h <<
3585 requi <<
3586 }; <<
3587 <<
3588 opp-202000000 <<
3589 opp-h <<
3590 requi <<
3591 }; <<
3592 }; 2196 };
3593 }; 2197 };
3594 2198
3595 dc_noc: interconnect@9160000 2199 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 2200 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 2201 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 2202 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 2203 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 2204 };
3601 2205
3602 gem_noc: interconnect@9680000 2206 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 2207 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 2208 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 2209 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 2210 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 2211 };
3608 2212
>> 2213 usb_2_qmpphy: phy@88eb000 {
>> 2214 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
>> 2215 reg = <0 0x088eb000 0 0x200>;
>> 2216 status = "disabled";
>> 2217 #address-cells = <2>;
>> 2218 #size-cells = <2>;
>> 2219 ranges;
>> 2220
>> 2221 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2222 <&rpmhcc RPMH_CXO_CLK>,
>> 2223 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
>> 2224 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
>> 2225 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
>> 2226
>> 2227 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
>> 2228 <&gcc GCC_USB3_PHY_SEC_BCR>;
>> 2229 reset-names = "phy", "common";
>> 2230
>> 2231 usb_2_ssphy: lane@88eb200 {
>> 2232 reg = <0 0x088eb200 0 0x200>,
>> 2233 <0 0x088eb400 0 0x200>,
>> 2234 <0 0x088eb800 0 0x800>,
>> 2235 <0 0x088eb600 0 0x200>;
>> 2236 #clock-cells = <0>;
>> 2237 #phy-cells = <0>;
>> 2238 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2239 clock-names = "pipe0";
>> 2240 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2241 };
>> 2242 };
>> 2243
3609 usb_1: usb@a6f8800 { 2244 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 2245 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 2246 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 2247 status = "disabled";
3613 #address-cells = <2>; 2248 #address-cells = <2>;
3614 #size-cells = <2>; 2249 #size-cells = <2>;
3615 ranges; 2250 ranges;
3616 dma-ranges; 2251 dma-ranges;
3617 2252
3618 clocks = <&gcc GCC_CF 2253 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 2254 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 2255 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US <<
3622 <&gcc GCC_US 2256 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2257 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3623 <&gcc GCC_US 2258 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no !! 2259 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3625 "core", !! 2260 "sleep", "xo";
3626 "iface" <<
3627 "sleep" <<
3628 "mock_u <<
3629 "xo"; <<
3630 2261
3631 assigned-clocks = <&g 2262 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 2263 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 2264 assigned-clock-rates = <19200000>, <200000000>;
3634 2265
3635 interrupts-extended = !! 2266 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 2267 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 2268 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 2269 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 2270 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 2271 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 2272
3646 power-domains = <&gcc 2273 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 2274
3648 resets = <&gcc GCC_US 2275 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 2276
3650 interconnects = <&agg !! 2277 usb_1_dwc3: dwc3@a600000 {
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 <<
3655 compatible = 2278 compatible = "snps,dwc3";
3656 reg = <0 0x0a 2279 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 2280 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 2281 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 2282 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 2283 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 2284 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 2285 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 2286 };
3684 }; 2287 };
3685 2288
3686 usb_2: usb@a8f8800 { 2289 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 2290 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 2291 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 2292 status = "disabled";
3690 #address-cells = <2>; 2293 #address-cells = <2>;
3691 #size-cells = <2>; 2294 #size-cells = <2>;
3692 ranges; 2295 ranges;
3693 dma-ranges; 2296 dma-ranges;
3694 2297
3695 clocks = <&gcc GCC_CF 2298 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 2299 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 2300 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US <<
3699 <&gcc GCC_US 2301 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2302 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3700 <&gcc GCC_US 2303 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no !! 2304 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3702 "core", !! 2305 "sleep", "xo";
3703 "iface" <<
3704 "sleep" <<
3705 "mock_u <<
3706 "xo"; <<
3707 2306
3708 assigned-clocks = <&g 2307 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 2308 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 2309 assigned-clock-rates = <19200000>, <200000000>;
3711 2310
3712 interrupts-extended = !! 2311 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 2312 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 2313 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 2314 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 2315 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 2316 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 2317
3723 power-domains = <&gcc 2318 power-domains = <&gcc USB30_SEC_GDSC>;
3724 2319
3725 resets = <&gcc GCC_US 2320 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 2321
3727 interconnects = <&agg !! 2322 usb_2_dwc3: dwc3@a800000 {
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 <<
3732 compatible = 2323 compatible = "snps,dwc3";
3733 reg = <0 0x0a 2324 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 2325 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 2326 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 2327 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 2328 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 2329 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 2330 phy-names = "usb2-phy", "usb3-phy";
3740 }; 2331 };
3741 }; 2332 };
3742 2333
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 2334 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 2335 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 2336 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 2337 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 2338 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 2339 };
3762 2340
3763 camcc: clock-controller@ad000 !! 2341 aoss_qmp: power-controller@c300000 {
3764 compatible = "qcom,sm !! 2342 compatible = "qcom,sm8150-aoss-qmp";
3765 reg = <0 0x0ad00000 0 !! 2343 reg = <0x0 0x0c300000 0x0 0x100000>;
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 <<
4150 compatible = "qcom,sm <<
4151 reg = <0 0x0b220000 0 <<
4152 qcom,pdc-ranges = <0 <<
4153 <12 <<
4154 #interrupt-cells = <2 <<
4155 interrupt-parent = <& <<
4156 interrupt-controller; <<
4157 }; <<
4158 <<
4159 aoss_qmp: power-management@c3 <<
4160 compatible = "qcom,sm <<
4161 reg = <0x0 0x0c300000 <<
4162 interrupts = <GIC_SPI 2344 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 2345 mboxes = <&apss_shared 0>;
4164 2346
4165 #clock-cells = <0>; 2347 #clock-cells = <0>;
4166 }; !! 2348 #power-domain-cells = <1>;
4167 <<
4168 sram@c3f0000 { <<
4169 compatible = "qcom,rp <<
4170 reg = <0 0x0c3f0000 0 <<
4171 }; 2349 };
4172 2350
4173 tsens0: thermal-sensor@c26300 2351 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 2352 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 2353 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 2354 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 2355 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 2356 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 2357 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 2358 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 2359 #thermal-sensor-cells = <1>;
4182 }; 2360 };
4183 2361
4184 tsens1: thermal-sensor@c26500 2362 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 2363 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 2364 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 2365 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 2366 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 2367 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 2368 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 2369 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 2370 #thermal-sensor-cells = <1>;
4193 }; 2371 };
4194 2372
4195 spmi_bus: spmi@c440000 { 2373 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 2374 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 2375 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 2376 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 2377 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 2378 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 2379 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 2380 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 2381 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 2382 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 2383 qcom,ee = <0>;
4206 qcom,channel = <0>; 2384 qcom,channel = <0>;
4207 #address-cells = <2>; 2385 #address-cells = <2>;
4208 #size-cells = <0>; 2386 #size-cells = <0>;
4209 interrupt-controller; 2387 interrupt-controller;
4210 #interrupt-cells = <4 2388 #interrupt-cells = <4>;
>> 2389 cell-index = <0>;
4211 }; 2390 };
4212 2391
4213 apps_smmu: iommu@15000000 { 2392 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 2393 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 2394 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 2395 #iommu-cells = <2>;
4217 #global-interrupts = 2396 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 2397 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 2398 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 2399 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 2400 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 2401 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 2402 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 2403 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 2404 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 2405 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 2406 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 2407 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 2408 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 2409 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 2410 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 2411 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 2412 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 2413 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 2414 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 2415 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 2416 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 2417 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 2418 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 2419 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 2420 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 2421 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 2422 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 2423 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 2424 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 2425 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 2426 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 2427 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 2428 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 2429 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 2430 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 2431 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 2432 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 2433 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 2434 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 2435 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 2436 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 2437 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 2438 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 2439 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 2440 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 2441 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 2442 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 2443 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 2444 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 2445 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 2446 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 2447 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 2448 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 2449 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 2450 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 2451 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 2452 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 2453 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 2454 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 2455 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 2456 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 2457 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 2458 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 2459 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 2460 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 2461 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 2462 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 2463 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 2464 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 2465 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 2466 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 2467 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 2468 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 2469 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 2470 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 2471 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 2472 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 2473 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 2474 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 2475 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 2476 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 2477 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 2478 };
4300 2479
4301 remoteproc_adsp: remoteproc@1 2480 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 2481 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 2482 reg = <0x0 0x17300000 0x0 0x4040>;
4304 2483
4305 interrupts-extended = 2484 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 2485 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 2486 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 2487 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 2488 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 2489 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 2490 "handover", "stop-ack";
4312 2491
4313 clocks = <&rpmhcc RPM 2492 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 2493 clock-names = "xo";
4315 2494
4316 power-domains = <&rpm !! 2495 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
>> 2496 <&rpmhpd 7>;
>> 2497 power-domain-names = "load_state", "cx";
4317 2498
4318 memory-region = <&ads 2499 memory-region = <&adsp_mem>;
4319 2500
4320 qcom,qmp = <&aoss_qmp <<
4321 <<
4322 qcom,smem-states = <& 2501 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 2502 qcom,smem-state-names = "stop";
4324 2503
4325 status = "disabled"; 2504 status = "disabled";
4326 2505
4327 glink-edge { 2506 glink-edge {
4328 interrupts = 2507 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 2508 label = "lpass";
4330 qcom,remote-p 2509 qcom,remote-pid = <2>;
4331 mboxes = <&ap 2510 mboxes = <&apss_shared 8>;
4332 <<
4333 fastrpc { <<
4334 compa <<
4335 qcom, <<
4336 label <<
4337 qcom, <<
4338 #addr <<
4339 #size <<
4340 <<
4341 compu <<
4342 <<
4343 <<
4344 <<
4345 }; <<
4346 <<
4347 compu <<
4348 <<
4349 <<
4350 <<
4351 }; <<
4352 <<
4353 compu <<
4354 <<
4355 <<
4356 <<
4357 }; <<
4358 }; <<
4359 }; 2511 };
4360 }; 2512 };
4361 2513
4362 intc: interrupt-controller@17 2514 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 2515 compatible = "arm,gic-v3";
4364 interrupt-controller; 2516 interrupt-controller;
4365 #interrupt-cells = <3 2517 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 2518 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 2519 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 2520 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 2521 };
4370 2522
4371 apss_shared: mailbox@17c00000 2523 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 2524 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 2525 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 2526 #mbox-cells = <1>;
4376 }; 2527 };
4377 2528
4378 watchdog@17c10000 { 2529 watchdog@17c10000 {
4379 compatible = "qcom,ap 2530 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 2531 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 2532 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 2533 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 2534 };
4384 2535
4385 timer@17c20000 { 2536 timer@17c20000 {
4386 #address-cells = <1>; !! 2537 #address-cells = <2>;
4387 #size-cells = <1>; !! 2538 #size-cells = <2>;
4388 ranges = <0 0 0 0x200 !! 2539 ranges;
4389 compatible = "arm,arm 2540 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 2541 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 2542 clock-frequency = <19200000>;
4392 2543
4393 frame@17c21000 { !! 2544 frame@17c21000{
4394 frame-number 2545 frame-number = <0>;
4395 interrupts = 2546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 2547 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 !! 2548 reg = <0x0 0x17c21000 0x0 0x1000>,
4398 <0x17c2 !! 2549 <0x0 0x17c22000 0x0 0x1000>;
4399 }; 2550 };
4400 2551
4401 frame@17c23000 { 2552 frame@17c23000 {
4402 frame-number 2553 frame-number = <1>;
4403 interrupts = 2554 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 !! 2555 reg = <0x0 0x17c23000 0x0 0x1000>;
4405 status = "dis 2556 status = "disabled";
4406 }; 2557 };
4407 2558
4408 frame@17c25000 { 2559 frame@17c25000 {
4409 frame-number 2560 frame-number = <2>;
4410 interrupts = 2561 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 !! 2562 reg = <0x0 0x17c25000 0x0 0x1000>;
4412 status = "dis 2563 status = "disabled";
4413 }; 2564 };
4414 2565
4415 frame@17c27000 { 2566 frame@17c27000 {
4416 frame-number 2567 frame-number = <3>;
4417 interrupts = 2568 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 !! 2569 reg = <0x0 0x17c26000 0x0 0x1000>;
4419 status = "dis 2570 status = "disabled";
4420 }; 2571 };
4421 2572
4422 frame@17c29000 { 2573 frame@17c29000 {
4423 frame-number 2574 frame-number = <4>;
4424 interrupts = 2575 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 !! 2576 reg = <0x0 0x17c29000 0x0 0x1000>;
4426 status = "dis 2577 status = "disabled";
4427 }; 2578 };
4428 2579
4429 frame@17c2b000 { 2580 frame@17c2b000 {
4430 frame-number 2581 frame-number = <5>;
4431 interrupts = 2582 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 !! 2583 reg = <0x0 0x17c2b000 0x0 0x1000>;
4433 status = "dis 2584 status = "disabled";
4434 }; 2585 };
4435 2586
4436 frame@17c2d000 { 2587 frame@17c2d000 {
4437 frame-number 2588 frame-number = <6>;
4438 interrupts = 2589 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 !! 2590 reg = <0x0 0x17c2d000 0x0 0x1000>;
4440 status = "dis 2591 status = "disabled";
4441 }; 2592 };
4442 }; 2593 };
4443 2594
4444 apps_rsc: rsc@18200000 { 2595 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 2596 label = "apps_rsc";
4446 compatible = "qcom,rp 2597 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 2598 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 2599 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 2600 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 2601 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 2602 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 2603 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 2604 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 2605 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 2606 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 2607 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL !! 2608 <SLEEP_TCS 1>,
4458 <WA !! 2609 <WAKE_TCS 1>,
4459 <CO !! 2610 <CONTROL_TCS 0>;
4460 power-domains = <&CLU <<
4461 2611
4462 rpmhcc: clock-control 2612 rpmhcc: clock-controller {
4463 compatible = 2613 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 2614 #clock-cells = <1>;
4465 clock-names = 2615 clock-names = "xo";
4466 clocks = <&xo 2616 clocks = <&xo_board>;
4467 }; 2617 };
4468 2618
4469 rpmhpd: power-control 2619 rpmhpd: power-controller {
4470 compatible = 2620 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 2621 #power-domain-cells = <1>;
4472 operating-poi 2622 operating-points-v2 = <&rpmhpd_opp_table>;
4473 2623
4474 rpmhpd_opp_ta 2624 rpmhpd_opp_table: opp-table {
4475 compa 2625 compatible = "operating-points-v2";
4476 2626
4477 rpmhp 2627 rpmhpd_opp_ret: opp1 {
4478 2628 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 2629 };
4480 2630
4481 rpmhp 2631 rpmhpd_opp_min_svs: opp2 {
4482 2632 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 2633 };
4484 2634
4485 rpmhp 2635 rpmhpd_opp_low_svs: opp3 {
4486 2636 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 2637 };
4488 2638
4489 rpmhp 2639 rpmhpd_opp_svs: opp4 {
4490 2640 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 2641 };
4492 2642
4493 rpmhp 2643 rpmhpd_opp_svs_l1: opp5 {
4494 2644 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 2645 };
4496 2646
4497 rpmhp 2647 rpmhpd_opp_svs_l2: opp6 {
4498 2648 opp-level = <224>;
4499 }; 2649 };
4500 2650
4501 rpmhp 2651 rpmhpd_opp_nom: opp7 {
4502 2652 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 2653 };
4504 2654
4505 rpmhp 2655 rpmhpd_opp_nom_l1: opp8 {
4506 2656 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 2657 };
4508 2658
4509 rpmhp 2659 rpmhpd_opp_nom_l2: opp9 {
4510 2660 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 2661 };
4512 2662
4513 rpmhp 2663 rpmhpd_opp_turbo: opp10 {
4514 2664 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 2665 };
4516 2666
4517 rpmhp 2667 rpmhpd_opp_turbo_l1: opp11 {
4518 2668 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 2669 };
4520 }; 2670 };
4521 }; 2671 };
4522 2672
4523 apps_bcm_voter: bcm-v !! 2673 apps_bcm_voter: bcm_voter {
4524 compatible = 2674 compatible = "qcom,bcm-voter";
4525 }; 2675 };
4526 }; 2676 };
4527 2677
4528 osm_l3: interconnect@18321000 2678 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 2679 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 2680 reg = <0 0x18321000 0 0x1400>;
4531 2681
4532 clocks = <&rpmhcc RPM 2682 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 2683 clock-names = "xo", "alternate";
4534 2684
4535 #interconnect-cells = 2685 #interconnect-cells = <1>;
4536 }; 2686 };
4537 2687
4538 cpufreq_hw: cpufreq@18323000 2688 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 2689 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 2690 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 2691 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 2692 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 2693 "freq-domain2";
4544 2694
4545 clocks = <&rpmhcc RPM 2695 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 2696 clock-names = "xo", "alternate";
4547 2697
4548 #freq-domain-cells = 2698 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; <<
4551 <<
4552 lmh_cluster1: lmh@18350800 { <<
4553 compatible = "qcom,sm <<
4554 reg = <0 0x18350800 0 <<
4555 interrupts = <GIC_SPI <<
4556 cpus = <&CPU4>; <<
4557 qcom,lmh-temp-arm-mil <<
4558 qcom,lmh-temp-low-mil <<
4559 qcom,lmh-temp-high-mi <<
4560 interrupt-controller; <<
4561 #interrupt-cells = <1 <<
4562 }; <<
4563 <<
4564 lmh_cluster0: lmh@18358800 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x18358800 0 <<
4567 interrupts = <GIC_SPI <<
4568 cpus = <&CPU0>; <<
4569 qcom,lmh-temp-arm-mil <<
4570 qcom,lmh-temp-low-mil <<
4571 qcom,lmh-temp-high-mi <<
4572 interrupt-controller; <<
4573 #interrupt-cells = <1 <<
4574 }; 2699 };
4575 2700
4576 wifi: wifi@18800000 { 2701 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 2702 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 2703 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 2704 reg-names = "membase";
4580 memory-region = <&wla 2705 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 2706 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 2707 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 2708 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 2709 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 2710 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 2711 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 2712 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 2713 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 2714 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 2715 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 2716 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 2717 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 2718 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 2719 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 2720 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 2721 status = "disabled";
4597 }; 2722 };
4598 }; 2723 };
4599 2724
4600 timer { 2725 timer {
4601 compatible = "arm,armv8-timer 2726 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 2727 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 2728 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 2729 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 2730 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 2731 };
4607 2732
4608 thermal-zones { 2733 thermal-zones {
4609 cpu0-thermal { 2734 cpu0-thermal {
4610 polling-delay-passive 2735 polling-delay-passive = <250>;
>> 2736 polling-delay = <1000>;
4611 2737
4612 thermal-sensors = <&t 2738 thermal-sensors = <&tsens0 1>;
4613 2739
4614 trips { 2740 trips {
4615 cpu0_alert0: 2741 cpu0_alert0: trip-point0 {
4616 tempe 2742 temperature = <90000>;
4617 hyste 2743 hysteresis = <2000>;
4618 type 2744 type = "passive";
4619 }; 2745 };
4620 2746
4621 cpu0_alert1: 2747 cpu0_alert1: trip-point1 {
4622 tempe 2748 temperature = <95000>;
4623 hyste 2749 hysteresis = <2000>;
4624 type 2750 type = "passive";
4625 }; 2751 };
4626 2752
4627 cpu0_crit: cp !! 2753 cpu0_crit: cpu_crit {
4628 tempe 2754 temperature = <110000>;
4629 hyste 2755 hysteresis = <1000>;
4630 type 2756 type = "critical";
4631 }; 2757 };
4632 }; 2758 };
4633 2759
4634 cooling-maps { 2760 cooling-maps {
4635 map0 { 2761 map0 {
4636 trip 2762 trip = <&cpu0_alert0>;
4637 cooli 2763 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 2764 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 2765 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 2766 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 2767 };
4642 map1 { 2768 map1 {
4643 trip 2769 trip = <&cpu0_alert1>;
4644 cooli 2770 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 2771 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 2772 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 2773 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 2774 };
4649 }; 2775 };
4650 }; 2776 };
4651 2777
4652 cpu1-thermal { 2778 cpu1-thermal {
4653 polling-delay-passive 2779 polling-delay-passive = <250>;
>> 2780 polling-delay = <1000>;
4654 2781
4655 thermal-sensors = <&t 2782 thermal-sensors = <&tsens0 2>;
4656 2783
4657 trips { 2784 trips {
4658 cpu1_alert0: 2785 cpu1_alert0: trip-point0 {
4659 tempe 2786 temperature = <90000>;
4660 hyste 2787 hysteresis = <2000>;
4661 type 2788 type = "passive";
4662 }; 2789 };
4663 2790
4664 cpu1_alert1: 2791 cpu1_alert1: trip-point1 {
4665 tempe 2792 temperature = <95000>;
4666 hyste 2793 hysteresis = <2000>;
4667 type 2794 type = "passive";
4668 }; 2795 };
4669 2796
4670 cpu1_crit: cp !! 2797 cpu1_crit: cpu_crit {
4671 tempe 2798 temperature = <110000>;
4672 hyste 2799 hysteresis = <1000>;
4673 type 2800 type = "critical";
4674 }; 2801 };
4675 }; 2802 };
4676 2803
4677 cooling-maps { 2804 cooling-maps {
4678 map0 { 2805 map0 {
4679 trip 2806 trip = <&cpu1_alert0>;
4680 cooli 2807 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 2808 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 2809 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 2810 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 2811 };
4685 map1 { 2812 map1 {
4686 trip 2813 trip = <&cpu1_alert1>;
4687 cooli 2814 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 2815 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 2816 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 2817 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 2818 };
4692 }; 2819 };
4693 }; 2820 };
4694 2821
4695 cpu2-thermal { 2822 cpu2-thermal {
4696 polling-delay-passive 2823 polling-delay-passive = <250>;
>> 2824 polling-delay = <1000>;
4697 2825
4698 thermal-sensors = <&t 2826 thermal-sensors = <&tsens0 3>;
4699 2827
4700 trips { 2828 trips {
4701 cpu2_alert0: 2829 cpu2_alert0: trip-point0 {
4702 tempe 2830 temperature = <90000>;
4703 hyste 2831 hysteresis = <2000>;
4704 type 2832 type = "passive";
4705 }; 2833 };
4706 2834
4707 cpu2_alert1: 2835 cpu2_alert1: trip-point1 {
4708 tempe 2836 temperature = <95000>;
4709 hyste 2837 hysteresis = <2000>;
4710 type 2838 type = "passive";
4711 }; 2839 };
4712 2840
4713 cpu2_crit: cp !! 2841 cpu2_crit: cpu_crit {
4714 tempe 2842 temperature = <110000>;
4715 hyste 2843 hysteresis = <1000>;
4716 type 2844 type = "critical";
4717 }; 2845 };
4718 }; 2846 };
4719 2847
4720 cooling-maps { 2848 cooling-maps {
4721 map0 { 2849 map0 {
4722 trip 2850 trip = <&cpu2_alert0>;
4723 cooli 2851 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 2852 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 2853 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 2854 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 2855 };
4728 map1 { 2856 map1 {
4729 trip 2857 trip = <&cpu2_alert1>;
4730 cooli 2858 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 2859 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 2860 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 2861 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 2862 };
4735 }; 2863 };
4736 }; 2864 };
4737 2865
4738 cpu3-thermal { 2866 cpu3-thermal {
4739 polling-delay-passive 2867 polling-delay-passive = <250>;
>> 2868 polling-delay = <1000>;
4740 2869
4741 thermal-sensors = <&t 2870 thermal-sensors = <&tsens0 4>;
4742 2871
4743 trips { 2872 trips {
4744 cpu3_alert0: 2873 cpu3_alert0: trip-point0 {
4745 tempe 2874 temperature = <90000>;
4746 hyste 2875 hysteresis = <2000>;
4747 type 2876 type = "passive";
4748 }; 2877 };
4749 2878
4750 cpu3_alert1: 2879 cpu3_alert1: trip-point1 {
4751 tempe 2880 temperature = <95000>;
4752 hyste 2881 hysteresis = <2000>;
4753 type 2882 type = "passive";
4754 }; 2883 };
4755 2884
4756 cpu3_crit: cp !! 2885 cpu3_crit: cpu_crit {
4757 tempe 2886 temperature = <110000>;
4758 hyste 2887 hysteresis = <1000>;
4759 type 2888 type = "critical";
4760 }; 2889 };
4761 }; 2890 };
4762 2891
4763 cooling-maps { 2892 cooling-maps {
4764 map0 { 2893 map0 {
4765 trip 2894 trip = <&cpu3_alert0>;
4766 cooli 2895 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 2896 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 2897 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 2898 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 2899 };
4771 map1 { 2900 map1 {
4772 trip 2901 trip = <&cpu3_alert1>;
4773 cooli 2902 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 2903 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 2904 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 2905 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 2906 };
4778 }; 2907 };
4779 }; 2908 };
4780 2909
4781 cpu4-top-thermal { 2910 cpu4-top-thermal {
4782 polling-delay-passive 2911 polling-delay-passive = <250>;
>> 2912 polling-delay = <1000>;
4783 2913
4784 thermal-sensors = <&t 2914 thermal-sensors = <&tsens0 7>;
4785 2915
4786 trips { 2916 trips {
4787 cpu4_top_aler 2917 cpu4_top_alert0: trip-point0 {
4788 tempe 2918 temperature = <90000>;
4789 hyste 2919 hysteresis = <2000>;
4790 type 2920 type = "passive";
4791 }; 2921 };
4792 2922
4793 cpu4_top_aler 2923 cpu4_top_alert1: trip-point1 {
4794 tempe 2924 temperature = <95000>;
4795 hyste 2925 hysteresis = <2000>;
4796 type 2926 type = "passive";
4797 }; 2927 };
4798 2928
4799 cpu4_top_crit !! 2929 cpu4_top_crit: cpu_crit {
4800 tempe 2930 temperature = <110000>;
4801 hyste 2931 hysteresis = <1000>;
4802 type 2932 type = "critical";
4803 }; 2933 };
4804 }; 2934 };
4805 2935
4806 cooling-maps { 2936 cooling-maps {
4807 map0 { 2937 map0 {
4808 trip 2938 trip = <&cpu4_top_alert0>;
4809 cooli 2939 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 2940 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 2941 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 2942 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 2943 };
4814 map1 { 2944 map1 {
4815 trip 2945 trip = <&cpu4_top_alert1>;
4816 cooli 2946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 2947 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 2948 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 2949 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 2950 };
4821 }; 2951 };
4822 }; 2952 };
4823 2953
4824 cpu5-top-thermal { 2954 cpu5-top-thermal {
4825 polling-delay-passive 2955 polling-delay-passive = <250>;
>> 2956 polling-delay = <1000>;
4826 2957
4827 thermal-sensors = <&t 2958 thermal-sensors = <&tsens0 8>;
4828 2959
4829 trips { 2960 trips {
4830 cpu5_top_aler 2961 cpu5_top_alert0: trip-point0 {
4831 tempe 2962 temperature = <90000>;
4832 hyste 2963 hysteresis = <2000>;
4833 type 2964 type = "passive";
4834 }; 2965 };
4835 2966
4836 cpu5_top_aler 2967 cpu5_top_alert1: trip-point1 {
4837 tempe 2968 temperature = <95000>;
4838 hyste 2969 hysteresis = <2000>;
4839 type 2970 type = "passive";
4840 }; 2971 };
4841 2972
4842 cpu5_top_crit !! 2973 cpu5_top_crit: cpu_crit {
4843 tempe 2974 temperature = <110000>;
4844 hyste 2975 hysteresis = <1000>;
4845 type 2976 type = "critical";
4846 }; 2977 };
4847 }; 2978 };
4848 2979
4849 cooling-maps { 2980 cooling-maps {
4850 map0 { 2981 map0 {
4851 trip 2982 trip = <&cpu5_top_alert0>;
4852 cooli 2983 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 2984 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 2985 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 2986 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 2987 };
4857 map1 { 2988 map1 {
4858 trip 2989 trip = <&cpu5_top_alert1>;
4859 cooli 2990 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 2991 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 2992 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 2993 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 2994 };
4864 }; 2995 };
4865 }; 2996 };
4866 2997
4867 cpu6-top-thermal { 2998 cpu6-top-thermal {
4868 polling-delay-passive 2999 polling-delay-passive = <250>;
>> 3000 polling-delay = <1000>;
4869 3001
4870 thermal-sensors = <&t 3002 thermal-sensors = <&tsens0 9>;
4871 3003
4872 trips { 3004 trips {
4873 cpu6_top_aler 3005 cpu6_top_alert0: trip-point0 {
4874 tempe 3006 temperature = <90000>;
4875 hyste 3007 hysteresis = <2000>;
4876 type 3008 type = "passive";
4877 }; 3009 };
4878 3010
4879 cpu6_top_aler 3011 cpu6_top_alert1: trip-point1 {
4880 tempe 3012 temperature = <95000>;
4881 hyste 3013 hysteresis = <2000>;
4882 type 3014 type = "passive";
4883 }; 3015 };
4884 3016
4885 cpu6_top_crit !! 3017 cpu6_top_crit: cpu_crit {
4886 tempe 3018 temperature = <110000>;
4887 hyste 3019 hysteresis = <1000>;
4888 type 3020 type = "critical";
4889 }; 3021 };
4890 }; 3022 };
4891 3023
4892 cooling-maps { 3024 cooling-maps {
4893 map0 { 3025 map0 {
4894 trip 3026 trip = <&cpu6_top_alert0>;
4895 cooli 3027 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 3028 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 3029 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 3030 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 3031 };
4900 map1 { 3032 map1 {
4901 trip 3033 trip = <&cpu6_top_alert1>;
4902 cooli 3034 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 3035 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 3036 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 3037 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 3038 };
4907 }; 3039 };
4908 }; 3040 };
4909 3041
4910 cpu7-top-thermal { 3042 cpu7-top-thermal {
4911 polling-delay-passive 3043 polling-delay-passive = <250>;
>> 3044 polling-delay = <1000>;
4912 3045
4913 thermal-sensors = <&t 3046 thermal-sensors = <&tsens0 10>;
4914 3047
4915 trips { 3048 trips {
4916 cpu7_top_aler 3049 cpu7_top_alert0: trip-point0 {
4917 tempe 3050 temperature = <90000>;
4918 hyste 3051 hysteresis = <2000>;
4919 type 3052 type = "passive";
4920 }; 3053 };
4921 3054
4922 cpu7_top_aler 3055 cpu7_top_alert1: trip-point1 {
4923 tempe 3056 temperature = <95000>;
4924 hyste 3057 hysteresis = <2000>;
4925 type 3058 type = "passive";
4926 }; 3059 };
4927 3060
4928 cpu7_top_crit !! 3061 cpu7_top_crit: cpu_crit {
4929 tempe 3062 temperature = <110000>;
4930 hyste 3063 hysteresis = <1000>;
4931 type 3064 type = "critical";
4932 }; 3065 };
4933 }; 3066 };
4934 3067
4935 cooling-maps { 3068 cooling-maps {
4936 map0 { 3069 map0 {
4937 trip 3070 trip = <&cpu7_top_alert0>;
4938 cooli 3071 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 3072 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 3073 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 3074 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 3075 };
4943 map1 { 3076 map1 {
4944 trip 3077 trip = <&cpu7_top_alert1>;
4945 cooli 3078 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 3079 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 3080 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 3081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 3082 };
4950 }; 3083 };
4951 }; 3084 };
4952 3085
4953 cpu4-bottom-thermal { 3086 cpu4-bottom-thermal {
4954 polling-delay-passive 3087 polling-delay-passive = <250>;
>> 3088 polling-delay = <1000>;
4955 3089
4956 thermal-sensors = <&t 3090 thermal-sensors = <&tsens0 11>;
4957 3091
4958 trips { 3092 trips {
4959 cpu4_bottom_a 3093 cpu4_bottom_alert0: trip-point0 {
4960 tempe 3094 temperature = <90000>;
4961 hyste 3095 hysteresis = <2000>;
4962 type 3096 type = "passive";
4963 }; 3097 };
4964 3098
4965 cpu4_bottom_a 3099 cpu4_bottom_alert1: trip-point1 {
4966 tempe 3100 temperature = <95000>;
4967 hyste 3101 hysteresis = <2000>;
4968 type 3102 type = "passive";
4969 }; 3103 };
4970 3104
4971 cpu4_bottom_c !! 3105 cpu4_bottom_crit: cpu_crit {
4972 tempe 3106 temperature = <110000>;
4973 hyste 3107 hysteresis = <1000>;
4974 type 3108 type = "critical";
4975 }; 3109 };
4976 }; 3110 };
4977 3111
4978 cooling-maps { 3112 cooling-maps {
4979 map0 { 3113 map0 {
4980 trip 3114 trip = <&cpu4_bottom_alert0>;
4981 cooli 3115 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 3116 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 3117 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 3118 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 3119 };
4986 map1 { 3120 map1 {
4987 trip 3121 trip = <&cpu4_bottom_alert1>;
4988 cooli 3122 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 3123 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 3124 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 3125 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 3126 };
4993 }; 3127 };
4994 }; 3128 };
4995 3129
4996 cpu5-bottom-thermal { 3130 cpu5-bottom-thermal {
4997 polling-delay-passive 3131 polling-delay-passive = <250>;
>> 3132 polling-delay = <1000>;
4998 3133
4999 thermal-sensors = <&t 3134 thermal-sensors = <&tsens0 12>;
5000 3135
5001 trips { 3136 trips {
5002 cpu5_bottom_a 3137 cpu5_bottom_alert0: trip-point0 {
5003 tempe 3138 temperature = <90000>;
5004 hyste 3139 hysteresis = <2000>;
5005 type 3140 type = "passive";
5006 }; 3141 };
5007 3142
5008 cpu5_bottom_a 3143 cpu5_bottom_alert1: trip-point1 {
5009 tempe 3144 temperature = <95000>;
5010 hyste 3145 hysteresis = <2000>;
5011 type 3146 type = "passive";
5012 }; 3147 };
5013 3148
5014 cpu5_bottom_c !! 3149 cpu5_bottom_crit: cpu_crit {
5015 tempe 3150 temperature = <110000>;
5016 hyste 3151 hysteresis = <1000>;
5017 type 3152 type = "critical";
5018 }; 3153 };
5019 }; 3154 };
5020 3155
5021 cooling-maps { 3156 cooling-maps {
5022 map0 { 3157 map0 {
5023 trip 3158 trip = <&cpu5_bottom_alert0>;
5024 cooli 3159 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 3160 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 3161 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 3162 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 3163 };
5029 map1 { 3164 map1 {
5030 trip 3165 trip = <&cpu5_bottom_alert1>;
5031 cooli 3166 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 3167 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 3168 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 3169 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 3170 };
5036 }; 3171 };
5037 }; 3172 };
5038 3173
5039 cpu6-bottom-thermal { 3174 cpu6-bottom-thermal {
5040 polling-delay-passive 3175 polling-delay-passive = <250>;
>> 3176 polling-delay = <1000>;
5041 3177
5042 thermal-sensors = <&t 3178 thermal-sensors = <&tsens0 13>;
5043 3179
5044 trips { 3180 trips {
5045 cpu6_bottom_a 3181 cpu6_bottom_alert0: trip-point0 {
5046 tempe 3182 temperature = <90000>;
5047 hyste 3183 hysteresis = <2000>;
5048 type 3184 type = "passive";
5049 }; 3185 };
5050 3186
5051 cpu6_bottom_a 3187 cpu6_bottom_alert1: trip-point1 {
5052 tempe 3188 temperature = <95000>;
5053 hyste 3189 hysteresis = <2000>;
5054 type 3190 type = "passive";
5055 }; 3191 };
5056 3192
5057 cpu6_bottom_c !! 3193 cpu6_bottom_crit: cpu_crit {
5058 tempe 3194 temperature = <110000>;
5059 hyste 3195 hysteresis = <1000>;
5060 type 3196 type = "critical";
5061 }; 3197 };
5062 }; 3198 };
5063 3199
5064 cooling-maps { 3200 cooling-maps {
5065 map0 { 3201 map0 {
5066 trip 3202 trip = <&cpu6_bottom_alert0>;
5067 cooli 3203 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 3204 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 3205 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 3206 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 3207 };
5072 map1 { 3208 map1 {
5073 trip 3209 trip = <&cpu6_bottom_alert1>;
5074 cooli 3210 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 3211 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 3212 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 3213 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 3214 };
5079 }; 3215 };
5080 }; 3216 };
5081 3217
5082 cpu7-bottom-thermal { 3218 cpu7-bottom-thermal {
5083 polling-delay-passive 3219 polling-delay-passive = <250>;
>> 3220 polling-delay = <1000>;
5084 3221
5085 thermal-sensors = <&t 3222 thermal-sensors = <&tsens0 14>;
5086 3223
5087 trips { 3224 trips {
5088 cpu7_bottom_a 3225 cpu7_bottom_alert0: trip-point0 {
5089 tempe 3226 temperature = <90000>;
5090 hyste 3227 hysteresis = <2000>;
5091 type 3228 type = "passive";
5092 }; 3229 };
5093 3230
5094 cpu7_bottom_a 3231 cpu7_bottom_alert1: trip-point1 {
5095 tempe 3232 temperature = <95000>;
5096 hyste 3233 hysteresis = <2000>;
5097 type 3234 type = "passive";
5098 }; 3235 };
5099 3236
5100 cpu7_bottom_c !! 3237 cpu7_bottom_crit: cpu_crit {
5101 tempe 3238 temperature = <110000>;
5102 hyste 3239 hysteresis = <1000>;
5103 type 3240 type = "critical";
5104 }; 3241 };
5105 }; 3242 };
5106 3243
5107 cooling-maps { 3244 cooling-maps {
5108 map0 { 3245 map0 {
5109 trip 3246 trip = <&cpu7_bottom_alert0>;
5110 cooli 3247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 3248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 3249 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 3250 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 3251 };
5115 map1 { 3252 map1 {
5116 trip 3253 trip = <&cpu7_bottom_alert1>;
5117 cooli 3254 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 3255 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 3256 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 3257 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 3258 };
5122 }; 3259 };
5123 }; 3260 };
5124 3261
5125 aoss0-thermal { 3262 aoss0-thermal {
5126 polling-delay-passive 3263 polling-delay-passive = <250>;
>> 3264 polling-delay = <1000>;
5127 3265
5128 thermal-sensors = <&t 3266 thermal-sensors = <&tsens0 0>;
5129 3267
5130 trips { 3268 trips {
5131 aoss0_alert0: 3269 aoss0_alert0: trip-point0 {
5132 tempe 3270 temperature = <90000>;
5133 hyste 3271 hysteresis = <2000>;
5134 type 3272 type = "hot";
5135 }; 3273 };
5136 }; 3274 };
5137 }; 3275 };
5138 3276
5139 cluster0-thermal { 3277 cluster0-thermal {
5140 polling-delay-passive 3278 polling-delay-passive = <250>;
>> 3279 polling-delay = <1000>;
5141 3280
5142 thermal-sensors = <&t 3281 thermal-sensors = <&tsens0 5>;
5143 3282
5144 trips { 3283 trips {
5145 cluster0_aler 3284 cluster0_alert0: trip-point0 {
5146 tempe 3285 temperature = <90000>;
5147 hyste 3286 hysteresis = <2000>;
5148 type 3287 type = "hot";
5149 }; 3288 };
5150 cluster0_crit !! 3289 cluster0_crit: cluster0_crit {
5151 tempe 3290 temperature = <110000>;
5152 hyste 3291 hysteresis = <2000>;
5153 type 3292 type = "critical";
5154 }; 3293 };
5155 }; 3294 };
5156 }; 3295 };
5157 3296
5158 cluster1-thermal { 3297 cluster1-thermal {
5159 polling-delay-passive 3298 polling-delay-passive = <250>;
>> 3299 polling-delay = <1000>;
5160 3300
5161 thermal-sensors = <&t 3301 thermal-sensors = <&tsens0 6>;
5162 3302
5163 trips { 3303 trips {
5164 cluster1_aler 3304 cluster1_alert0: trip-point0 {
5165 tempe 3305 temperature = <90000>;
5166 hyste 3306 hysteresis = <2000>;
5167 type 3307 type = "hot";
5168 }; 3308 };
5169 cluster1_crit !! 3309 cluster1_crit: cluster1_crit {
5170 tempe 3310 temperature = <110000>;
5171 hyste 3311 hysteresis = <2000>;
5172 type 3312 type = "critical";
5173 }; 3313 };
5174 }; 3314 };
5175 }; 3315 };
5176 3316
5177 gpu-top-thermal { !! 3317 gpu-thermal-top {
5178 polling-delay-passive 3318 polling-delay-passive = <250>;
>> 3319 polling-delay = <1000>;
5179 3320
5180 thermal-sensors = <&t 3321 thermal-sensors = <&tsens0 15>;
5181 3322
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 3323 trips {
5190 gpu_top_alert !! 3324 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 3325 temperature = <90000>;
5198 hyste !! 3326 hysteresis = <2000>;
5199 type 3327 type = "hot";
5200 }; 3328 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 3329 };
5208 }; 3330 };
5209 3331
5210 aoss1-thermal { 3332 aoss1-thermal {
5211 polling-delay-passive 3333 polling-delay-passive = <250>;
>> 3334 polling-delay = <1000>;
5212 3335
5213 thermal-sensors = <&t 3336 thermal-sensors = <&tsens1 0>;
5214 3337
5215 trips { 3338 trips {
5216 aoss1_alert0: 3339 aoss1_alert0: trip-point0 {
5217 tempe 3340 temperature = <90000>;
5218 hyste 3341 hysteresis = <2000>;
5219 type 3342 type = "hot";
5220 }; 3343 };
5221 }; 3344 };
5222 }; 3345 };
5223 3346
5224 wlan-thermal { 3347 wlan-thermal {
5225 polling-delay-passive 3348 polling-delay-passive = <250>;
>> 3349 polling-delay = <1000>;
5226 3350
5227 thermal-sensors = <&t 3351 thermal-sensors = <&tsens1 1>;
5228 3352
5229 trips { 3353 trips {
5230 wlan_alert0: 3354 wlan_alert0: trip-point0 {
5231 tempe 3355 temperature = <90000>;
5232 hyste 3356 hysteresis = <2000>;
5233 type 3357 type = "hot";
5234 }; 3358 };
5235 }; 3359 };
5236 }; 3360 };
5237 3361
5238 video-thermal { 3362 video-thermal {
5239 polling-delay-passive 3363 polling-delay-passive = <250>;
>> 3364 polling-delay = <1000>;
5240 3365
5241 thermal-sensors = <&t 3366 thermal-sensors = <&tsens1 2>;
5242 3367
5243 trips { 3368 trips {
5244 video_alert0: 3369 video_alert0: trip-point0 {
5245 tempe 3370 temperature = <90000>;
5246 hyste 3371 hysteresis = <2000>;
5247 type 3372 type = "hot";
5248 }; 3373 };
5249 }; 3374 };
5250 }; 3375 };
5251 3376
5252 mem-thermal { 3377 mem-thermal {
5253 polling-delay-passive 3378 polling-delay-passive = <250>;
>> 3379 polling-delay = <1000>;
5254 3380
5255 thermal-sensors = <&t 3381 thermal-sensors = <&tsens1 3>;
5256 3382
5257 trips { 3383 trips {
5258 mem_alert0: t 3384 mem_alert0: trip-point0 {
5259 tempe 3385 temperature = <90000>;
5260 hyste 3386 hysteresis = <2000>;
5261 type 3387 type = "hot";
5262 }; 3388 };
5263 }; 3389 };
5264 }; 3390 };
5265 3391
5266 q6-hvx-thermal { 3392 q6-hvx-thermal {
5267 polling-delay-passive 3393 polling-delay-passive = <250>;
>> 3394 polling-delay = <1000>;
5268 3395
5269 thermal-sensors = <&t 3396 thermal-sensors = <&tsens1 4>;
5270 3397
5271 trips { 3398 trips {
5272 q6_hvx_alert0 3399 q6_hvx_alert0: trip-point0 {
5273 tempe 3400 temperature = <90000>;
5274 hyste 3401 hysteresis = <2000>;
5275 type 3402 type = "hot";
5276 }; 3403 };
5277 }; 3404 };
5278 }; 3405 };
5279 3406
5280 camera-thermal { 3407 camera-thermal {
5281 polling-delay-passive 3408 polling-delay-passive = <250>;
>> 3409 polling-delay = <1000>;
5282 3410
5283 thermal-sensors = <&t 3411 thermal-sensors = <&tsens1 5>;
5284 3412
5285 trips { 3413 trips {
5286 camera_alert0 3414 camera_alert0: trip-point0 {
5287 tempe 3415 temperature = <90000>;
5288 hyste 3416 hysteresis = <2000>;
5289 type 3417 type = "hot";
5290 }; 3418 };
5291 }; 3419 };
5292 }; 3420 };
5293 3421
5294 compute-thermal { 3422 compute-thermal {
5295 polling-delay-passive 3423 polling-delay-passive = <250>;
>> 3424 polling-delay = <1000>;
5296 3425
5297 thermal-sensors = <&t 3426 thermal-sensors = <&tsens1 6>;
5298 3427
5299 trips { 3428 trips {
5300 compute_alert 3429 compute_alert0: trip-point0 {
5301 tempe 3430 temperature = <90000>;
5302 hyste 3431 hysteresis = <2000>;
5303 type 3432 type = "hot";
5304 }; 3433 };
5305 }; 3434 };
5306 }; 3435 };
5307 3436
5308 modem-thermal { 3437 modem-thermal {
5309 polling-delay-passive 3438 polling-delay-passive = <250>;
>> 3439 polling-delay = <1000>;
5310 3440
5311 thermal-sensors = <&t 3441 thermal-sensors = <&tsens1 7>;
5312 3442
5313 trips { 3443 trips {
5314 modem_alert0: 3444 modem_alert0: trip-point0 {
5315 tempe 3445 temperature = <90000>;
5316 hyste 3446 hysteresis = <2000>;
5317 type 3447 type = "hot";
5318 }; 3448 };
5319 }; 3449 };
5320 }; 3450 };
5321 3451
5322 npu-thermal { 3452 npu-thermal {
5323 polling-delay-passive 3453 polling-delay-passive = <250>;
>> 3454 polling-delay = <1000>;
5324 3455
5325 thermal-sensors = <&t 3456 thermal-sensors = <&tsens1 8>;
5326 3457
5327 trips { 3458 trips {
5328 npu_alert0: t 3459 npu_alert0: trip-point0 {
5329 tempe 3460 temperature = <90000>;
5330 hyste 3461 hysteresis = <2000>;
5331 type 3462 type = "hot";
5332 }; 3463 };
5333 }; 3464 };
5334 }; 3465 };
5335 3466
5336 modem-vec-thermal { 3467 modem-vec-thermal {
5337 polling-delay-passive 3468 polling-delay-passive = <250>;
>> 3469 polling-delay = <1000>;
5338 3470
5339 thermal-sensors = <&t 3471 thermal-sensors = <&tsens1 9>;
5340 3472
5341 trips { 3473 trips {
5342 modem_vec_ale 3474 modem_vec_alert0: trip-point0 {
5343 tempe 3475 temperature = <90000>;
5344 hyste 3476 hysteresis = <2000>;
5345 type 3477 type = "hot";
5346 }; 3478 };
5347 }; 3479 };
5348 }; 3480 };
5349 3481
5350 modem-scl-thermal { 3482 modem-scl-thermal {
5351 polling-delay-passive 3483 polling-delay-passive = <250>;
>> 3484 polling-delay = <1000>;
5352 3485
5353 thermal-sensors = <&t 3486 thermal-sensors = <&tsens1 10>;
5354 3487
5355 trips { 3488 trips {
5356 modem_scl_ale 3489 modem_scl_alert0: trip-point0 {
5357 tempe 3490 temperature = <90000>;
5358 hyste 3491 hysteresis = <2000>;
5359 type 3492 type = "hot";
5360 }; 3493 };
5361 }; 3494 };
5362 }; 3495 };
5363 3496
5364 gpu-bottom-thermal { !! 3497 gpu-thermal-bottom {
5365 polling-delay-passive 3498 polling-delay-passive = <250>;
>> 3499 polling-delay = <1000>;
5366 3500
5367 thermal-sensors = <&t 3501 thermal-sensors = <&tsens1 11>;
5368 3502
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 3503 trips {
5377 gpu_bottom_al !! 3504 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 3505 temperature = <90000>;
5385 hyste !! 3506 hysteresis = <2000>;
5386 type 3507 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 3508 };
5394 }; 3509 };
5395 }; 3510 };
5396 }; 3511 };
5397 }; 3512 };
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