1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 9 #include <dt-bindings/power/qcom-aoss-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 10 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 11 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 12 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 16 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 17 #include <dt-bindings/thermal/thermal.h>
22 18
23 / { 19 / {
24 interrupt-parent = <&intc>; 20 interrupt-parent = <&intc>;
25 21
26 #address-cells = <2>; 22 #address-cells = <2>;
27 #size-cells = <2>; 23 #size-cells = <2>;
28 24
29 chosen { }; 25 chosen { };
30 26
31 clocks { 27 clocks {
32 xo_board: xo-board { 28 xo_board: xo-board {
33 compatible = "fixed-cl 29 compatible = "fixed-clock";
34 #clock-cells = <0>; 30 #clock-cells = <0>;
35 clock-frequency = <384 31 clock-frequency = <38400000>;
36 clock-output-names = " 32 clock-output-names = "xo_board";
37 }; 33 };
38 34
39 sleep_clk: sleep-clk { 35 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 36 compatible = "fixed-clock";
41 #clock-cells = <0>; 37 #clock-cells = <0>;
42 clock-frequency = <327 38 clock-frequency = <32764>;
43 clock-output-names = " 39 clock-output-names = "sleep_clk";
44 }; 40 };
45 }; 41 };
46 42
47 cpus { 43 cpus {
48 #address-cells = <2>; 44 #address-cells = <2>;
49 #size-cells = <0>; 45 #size-cells = <0>;
50 46
51 CPU0: cpu@0 { 47 CPU0: cpu@0 {
52 device_type = "cpu"; 48 device_type = "cpu";
53 compatible = "qcom,kry 49 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 50 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 51 enable-method = "psci";
57 capacity-dmips-mhz = < 52 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 53 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 55 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 56 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 57 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 59 power-domains = <&CPU_PD0>;
65 power-domain-names = " 60 power-domain-names = "psci";
66 #cooling-cells = <2>; 61 #cooling-cells = <2>;
67 L2_0: l2-cache { 62 L2_0: l2-cache {
68 compatible = " 63 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 64 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 65 L3_0: l3-cache {
73 compat !! 66 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 67 };
77 }; 68 };
78 }; 69 };
79 70
80 CPU1: cpu@100 { 71 CPU1: cpu@100 {
81 device_type = "cpu"; 72 device_type = "cpu";
82 compatible = "qcom,kry 73 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 74 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 75 enable-method = "psci";
86 capacity-dmips-mhz = < 76 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 77 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 78 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 79 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 80 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 81 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 83 power-domains = <&CPU_PD1>;
94 power-domain-names = " 84 power-domain-names = "psci";
95 #cooling-cells = <2>; 85 #cooling-cells = <2>;
96 L2_100: l2-cache { 86 L2_100: l2-cache {
97 compatible = " 87 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 88 next-level-cache = <&L3_0>;
101 }; 89 };
>> 90
102 }; 91 };
103 92
104 CPU2: cpu@200 { 93 CPU2: cpu@200 {
105 device_type = "cpu"; 94 device_type = "cpu";
106 compatible = "qcom,kry 95 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 96 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 97 enable-method = "psci";
110 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 99 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 100 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 101 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 102 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 103 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 104 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 105 power-domains = <&CPU_PD2>;
118 power-domain-names = " 106 power-domain-names = "psci";
119 #cooling-cells = <2>; 107 #cooling-cells = <2>;
120 L2_200: l2-cache { 108 L2_200: l2-cache {
121 compatible = " 109 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 110 next-level-cache = <&L3_0>;
125 }; 111 };
126 }; 112 };
127 113
128 CPU3: cpu@300 { 114 CPU3: cpu@300 {
129 device_type = "cpu"; 115 device_type = "cpu";
130 compatible = "qcom,kry 116 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 117 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 118 enable-method = "psci";
134 capacity-dmips-mhz = < 119 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 120 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 121 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 122 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 123 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 124 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 125 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 126 power-domains = <&CPU_PD3>;
142 power-domain-names = " 127 power-domain-names = "psci";
143 #cooling-cells = <2>; 128 #cooling-cells = <2>;
144 L2_300: l2-cache { 129 L2_300: l2-cache {
145 compatible = " 130 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 131 next-level-cache = <&L3_0>;
149 }; 132 };
150 }; 133 };
151 134
152 CPU4: cpu@400 { 135 CPU4: cpu@400 {
153 device_type = "cpu"; 136 device_type = "cpu";
154 compatible = "qcom,kry 137 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 138 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 139 enable-method = "psci";
158 capacity-dmips-mhz = < 140 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 141 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 142 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 143 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 144 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 145 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 146 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 147 power-domains = <&CPU_PD4>;
166 power-domain-names = " 148 power-domain-names = "psci";
167 #cooling-cells = <2>; 149 #cooling-cells = <2>;
168 L2_400: l2-cache { 150 L2_400: l2-cache {
169 compatible = " 151 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 152 next-level-cache = <&L3_0>;
173 }; 153 };
174 }; 154 };
175 155
176 CPU5: cpu@500 { 156 CPU5: cpu@500 {
177 device_type = "cpu"; 157 device_type = "cpu";
178 compatible = "qcom,kry 158 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 159 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 160 enable-method = "psci";
182 capacity-dmips-mhz = < 161 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 162 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 163 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 164 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 165 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 166 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 167 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 168 power-domains = <&CPU_PD5>;
190 power-domain-names = " 169 power-domain-names = "psci";
191 #cooling-cells = <2>; 170 #cooling-cells = <2>;
192 L2_500: l2-cache { 171 L2_500: l2-cache {
193 compatible = " 172 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 173 next-level-cache = <&L3_0>;
197 }; 174 };
198 }; 175 };
199 176
200 CPU6: cpu@600 { 177 CPU6: cpu@600 {
201 device_type = "cpu"; 178 device_type = "cpu";
202 compatible = "qcom,kry 179 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 180 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 181 enable-method = "psci";
206 capacity-dmips-mhz = < 182 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 183 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 184 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 185 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 186 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 187 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 188 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 189 power-domains = <&CPU_PD6>;
214 power-domain-names = " 190 power-domain-names = "psci";
215 #cooling-cells = <2>; 191 #cooling-cells = <2>;
216 L2_600: l2-cache { 192 L2_600: l2-cache {
217 compatible = " 193 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 194 next-level-cache = <&L3_0>;
221 }; 195 };
222 }; 196 };
223 197
224 CPU7: cpu@700 { 198 CPU7: cpu@700 {
225 device_type = "cpu"; 199 device_type = "cpu";
226 compatible = "qcom,kry 200 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 201 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 202 enable-method = "psci";
230 capacity-dmips-mhz = < 203 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 204 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 205 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 206 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 207 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 208 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 210 power-domains = <&CPU_PD7>;
238 power-domain-names = " 211 power-domain-names = "psci";
239 #cooling-cells = <2>; 212 #cooling-cells = <2>;
240 L2_700: l2-cache { 213 L2_700: l2-cache {
241 compatible = " 214 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 215 next-level-cache = <&L3_0>;
245 }; 216 };
246 }; 217 };
247 218
248 cpu-map { 219 cpu-map {
249 cluster0 { 220 cluster0 {
250 core0 { 221 core0 {
251 cpu = 222 cpu = <&CPU0>;
252 }; 223 };
253 224
254 core1 { 225 core1 {
255 cpu = 226 cpu = <&CPU1>;
256 }; 227 };
257 228
258 core2 { 229 core2 {
259 cpu = 230 cpu = <&CPU2>;
260 }; 231 };
261 232
262 core3 { 233 core3 {
263 cpu = 234 cpu = <&CPU3>;
264 }; 235 };
265 236
266 core4 { 237 core4 {
267 cpu = 238 cpu = <&CPU4>;
268 }; 239 };
269 240
270 core5 { 241 core5 {
271 cpu = 242 cpu = <&CPU5>;
272 }; 243 };
273 244
274 core6 { 245 core6 {
275 cpu = 246 cpu = <&CPU6>;
276 }; 247 };
277 248
278 core7 { 249 core7 {
279 cpu = 250 cpu = <&CPU7>;
280 }; 251 };
281 }; 252 };
282 }; 253 };
283 254
284 idle-states { 255 idle-states {
285 entry-method = "psci"; 256 entry-method = "psci";
286 257
287 LITTLE_CPU_SLEEP_0: cp 258 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 259 compatible = "arm,idle-state";
289 idle-state-nam 260 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 261 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 262 entry-latency-us = <355>;
292 exit-latency-u 263 exit-latency-us = <909>;
293 min-residency- 264 min-residency-us = <3934>;
294 local-timer-st 265 local-timer-stop;
295 }; 266 };
296 267
297 BIG_CPU_SLEEP_0: cpu-s 268 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 269 compatible = "arm,idle-state";
299 idle-state-nam 270 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 271 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 272 entry-latency-us = <241>;
302 exit-latency-u 273 exit-latency-us = <1461>;
303 min-residency- 274 min-residency-us = <4488>;
304 local-timer-st 275 local-timer-stop;
305 }; 276 };
306 }; 277 };
307 278
308 domain-idle-states { 279 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 280 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 281 compatible = "domain-idle-state";
>> 282 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 283 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 284 entry-latency-us = <3263>;
313 exit-latency-u 285 exit-latency-us = <6562>;
314 min-residency- 286 min-residency-us = <9987>;
>> 287 local-timer-stop;
315 }; 288 };
316 }; 289 };
317 }; 290 };
318 291
319 cpu0_opp_table: opp-table-cpu0 { !! 292 cpu0_opp_table: cpu0_opp_table {
320 compatible = "operating-points 293 compatible = "operating-points-v2";
321 opp-shared; 294 opp-shared;
322 295
323 cpu0_opp1: opp-300000000 { 296 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 297 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 298 opp-peak-kBps = <800000 9600000>;
326 }; 299 };
327 300
328 cpu0_opp2: opp-403200000 { 301 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 302 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 303 opp-peak-kBps = <800000 9600000>;
331 }; 304 };
332 305
333 cpu0_opp3: opp-499200000 { 306 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 307 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 308 opp-peak-kBps = <800000 12902400>;
336 }; 309 };
337 310
338 cpu0_opp4: opp-576000000 { 311 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 312 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 313 opp-peak-kBps = <800000 12902400>;
341 }; 314 };
342 315
343 cpu0_opp5: opp-672000000 { 316 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 317 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 318 opp-peak-kBps = <800000 15974400>;
346 }; 319 };
347 320
348 cpu0_opp6: opp-768000000 { 321 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 322 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 323 opp-peak-kBps = <1804000 19660800>;
351 }; 324 };
352 325
353 cpu0_opp7: opp-844800000 { 326 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 327 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 328 opp-peak-kBps = <1804000 19660800>;
356 }; 329 };
357 330
358 cpu0_opp8: opp-940800000 { 331 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 332 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 333 opp-peak-kBps = <1804000 22732800>;
361 }; 334 };
362 335
363 cpu0_opp9: opp-1036800000 { 336 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 337 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 338 opp-peak-kBps = <1804000 22732800>;
366 }; 339 };
367 340
368 cpu0_opp10: opp-1113600000 { 341 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 342 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 343 opp-peak-kBps = <2188000 25804800>;
371 }; 344 };
372 345
373 cpu0_opp11: opp-1209600000 { 346 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 347 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 348 opp-peak-kBps = <2188000 31948800>;
376 }; 349 };
377 350
378 cpu0_opp12: opp-1305600000 { 351 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 352 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 353 opp-peak-kBps = <3072000 31948800>;
381 }; 354 };
382 355
383 cpu0_opp13: opp-1382400000 { 356 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 357 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 358 opp-peak-kBps = <3072000 31948800>;
386 }; 359 };
387 360
388 cpu0_opp14: opp-1478400000 { 361 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 362 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 363 opp-peak-kBps = <3072000 31948800>;
391 }; 364 };
392 365
393 cpu0_opp15: opp-1555200000 { 366 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 367 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 368 opp-peak-kBps = <3072000 40550400>;
396 }; 369 };
397 370
398 cpu0_opp16: opp-1632000000 { 371 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 372 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 373 opp-peak-kBps = <3072000 40550400>;
401 }; 374 };
402 375
403 cpu0_opp17: opp-1708800000 { 376 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 377 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 378 opp-peak-kBps = <3072000 43008000>;
406 }; 379 };
407 380
408 cpu0_opp18: opp-1785600000 { 381 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 382 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 383 opp-peak-kBps = <3072000 43008000>;
411 }; 384 };
412 }; 385 };
413 386
414 cpu4_opp_table: opp-table-cpu4 { !! 387 cpu4_opp_table: cpu4_opp_table {
415 compatible = "operating-points 388 compatible = "operating-points-v2";
416 opp-shared; 389 opp-shared;
417 390
418 cpu4_opp1: opp-710400000 { 391 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 392 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 393 opp-peak-kBps = <1804000 15974400>;
421 }; 394 };
422 395
423 cpu4_opp2: opp-825600000 { 396 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 397 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 398 opp-peak-kBps = <2188000 19660800>;
426 }; 399 };
427 400
428 cpu4_opp3: opp-940800000 { 401 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 402 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 403 opp-peak-kBps = <2188000 22732800>;
431 }; 404 };
432 405
433 cpu4_opp4: opp-1056000000 { 406 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 407 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 408 opp-peak-kBps = <3072000 25804800>;
436 }; 409 };
437 410
438 cpu4_opp5: opp-1171200000 { 411 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 412 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 413 opp-peak-kBps = <3072000 31948800>;
441 }; 414 };
442 415
443 cpu4_opp6: opp-1286400000 { 416 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 417 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 418 opp-peak-kBps = <4068000 31948800>;
446 }; 419 };
447 420
448 cpu4_opp7: opp-1401600000 { 421 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 422 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 423 opp-peak-kBps = <4068000 31948800>;
451 }; 424 };
452 425
453 cpu4_opp8: opp-1497600000 { 426 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 427 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 428 opp-peak-kBps = <4068000 40550400>;
456 }; 429 };
457 430
458 cpu4_opp9: opp-1612800000 { 431 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 432 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 433 opp-peak-kBps = <4068000 40550400>;
461 }; 434 };
462 435
463 cpu4_opp10: opp-1708800000 { 436 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 437 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 438 opp-peak-kBps = <4068000 43008000>;
466 }; 439 };
467 440
468 cpu4_opp11: opp-1804800000 { 441 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 442 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 443 opp-peak-kBps = <6220000 43008000>;
471 }; 444 };
472 445
473 cpu4_opp12: opp-1920000000 { 446 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 447 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 448 opp-peak-kBps = <6220000 49152000>;
476 }; 449 };
477 450
478 cpu4_opp13: opp-2016000000 { 451 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 452 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 453 opp-peak-kBps = <7216000 49152000>;
481 }; 454 };
482 455
483 cpu4_opp14: opp-2131200000 { 456 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 457 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 458 opp-peak-kBps = <8368000 49152000>;
486 }; 459 };
487 460
488 cpu4_opp15: opp-2227200000 { 461 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 462 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 463 opp-peak-kBps = <8368000 51609600>;
491 }; 464 };
492 465
493 cpu4_opp16: opp-2323200000 { 466 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 467 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 468 opp-peak-kBps = <8368000 51609600>;
496 }; 469 };
497 470
498 cpu4_opp17: opp-2419200000 { 471 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 472 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 473 opp-peak-kBps = <8368000 51609600>;
501 }; 474 };
502 }; 475 };
503 476
504 cpu7_opp_table: opp-table-cpu7 { !! 477 cpu7_opp_table: cpu7_opp_table {
505 compatible = "operating-points 478 compatible = "operating-points-v2";
506 opp-shared; 479 opp-shared;
507 480
508 cpu7_opp1: opp-825600000 { 481 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 482 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 483 opp-peak-kBps = <2188000 19660800>;
511 }; 484 };
512 485
513 cpu7_opp2: opp-940800000 { 486 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 487 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 488 opp-peak-kBps = <2188000 22732800>;
516 }; 489 };
517 490
518 cpu7_opp3: opp-1056000000 { 491 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 492 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 493 opp-peak-kBps = <3072000 25804800>;
521 }; 494 };
522 495
523 cpu7_opp4: opp-1171200000 { 496 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 497 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 498 opp-peak-kBps = <3072000 31948800>;
526 }; 499 };
527 500
528 cpu7_opp5: opp-1286400000 { 501 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 502 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 503 opp-peak-kBps = <4068000 31948800>;
531 }; 504 };
532 505
533 cpu7_opp6: opp-1401600000 { 506 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 507 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 508 opp-peak-kBps = <4068000 31948800>;
536 }; 509 };
537 510
538 cpu7_opp7: opp-1497600000 { 511 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 512 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 513 opp-peak-kBps = <4068000 40550400>;
541 }; 514 };
542 515
543 cpu7_opp8: opp-1612800000 { 516 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 517 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 518 opp-peak-kBps = <4068000 40550400>;
546 }; 519 };
547 520
548 cpu7_opp9: opp-1708800000 { 521 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 522 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 523 opp-peak-kBps = <4068000 43008000>;
551 }; 524 };
552 525
553 cpu7_opp10: opp-1804800000 { 526 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 527 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 528 opp-peak-kBps = <6220000 43008000>;
556 }; 529 };
557 530
558 cpu7_opp11: opp-1920000000 { 531 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 532 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 533 opp-peak-kBps = <6220000 49152000>;
561 }; 534 };
562 535
563 cpu7_opp12: opp-2016000000 { 536 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 537 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 538 opp-peak-kBps = <7216000 49152000>;
566 }; 539 };
567 540
568 cpu7_opp13: opp-2131200000 { 541 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 542 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 543 opp-peak-kBps = <8368000 49152000>;
571 }; 544 };
572 545
573 cpu7_opp14: opp-2227200000 { 546 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 547 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 548 opp-peak-kBps = <8368000 51609600>;
576 }; 549 };
577 550
578 cpu7_opp15: opp-2323200000 { 551 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 552 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 553 opp-peak-kBps = <8368000 51609600>;
581 }; 554 };
582 555
583 cpu7_opp16: opp-2419200000 { 556 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 557 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 558 opp-peak-kBps = <8368000 51609600>;
586 }; 559 };
587 560
588 cpu7_opp17: opp-2534400000 { 561 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 562 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 563 opp-peak-kBps = <8368000 51609600>;
591 }; 564 };
592 565
593 cpu7_opp18: opp-2649600000 { 566 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 567 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 568 opp-peak-kBps = <8368000 51609600>;
596 }; 569 };
597 570
598 cpu7_opp19: opp-2745600000 { 571 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 572 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 573 opp-peak-kBps = <8368000 51609600>;
601 }; 574 };
602 575
603 cpu7_opp20: opp-2841600000 { 576 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 577 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 578 opp-peak-kBps = <8368000 51609600>;
606 }; 579 };
607 }; 580 };
608 581
609 firmware { 582 firmware {
610 scm: scm { 583 scm: scm {
611 compatible = "qcom,scm 584 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 585 #reset-cells = <1>;
613 }; 586 };
614 }; 587 };
615 588
>> 589 tcsr_mutex: hwlock {
>> 590 compatible = "qcom,tcsr-mutex";
>> 591 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 592 #hwlock-cells = <1>;
>> 593 };
>> 594
616 memory@80000000 { 595 memory@80000000 {
617 device_type = "memory"; 596 device_type = "memory";
618 /* We expect the bootloader to 597 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 598 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 599 };
621 600
622 pmu { 601 pmu {
623 compatible = "arm,armv8-pmuv3" 602 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 603 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 604 };
626 605
627 psci { 606 psci {
628 compatible = "arm,psci-1.0"; 607 compatible = "arm,psci-1.0";
629 method = "smc"; 608 method = "smc";
630 609
631 CPU_PD0: power-domain-cpu0 { !! 610 CPU_PD0: cpu0 {
632 #power-domain-cells = 611 #power-domain-cells = <0>;
633 power-domains = <&CLUS 612 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 613 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 614 };
636 615
637 CPU_PD1: power-domain-cpu1 { !! 616 CPU_PD1: cpu1 {
638 #power-domain-cells = 617 #power-domain-cells = <0>;
639 power-domains = <&CLUS 618 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 619 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 620 };
642 621
643 CPU_PD2: power-domain-cpu2 { !! 622 CPU_PD2: cpu2 {
644 #power-domain-cells = 623 #power-domain-cells = <0>;
645 power-domains = <&CLUS 624 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 625 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 626 };
648 627
649 CPU_PD3: power-domain-cpu3 { !! 628 CPU_PD3: cpu3 {
650 #power-domain-cells = 629 #power-domain-cells = <0>;
651 power-domains = <&CLUS 630 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 631 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 632 };
654 633
655 CPU_PD4: power-domain-cpu4 { !! 634 CPU_PD4: cpu4 {
656 #power-domain-cells = 635 #power-domain-cells = <0>;
657 power-domains = <&CLUS 636 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 637 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 638 };
660 639
661 CPU_PD5: power-domain-cpu5 { !! 640 CPU_PD5: cpu5 {
662 #power-domain-cells = 641 #power-domain-cells = <0>;
663 power-domains = <&CLUS 642 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 643 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 644 };
666 645
667 CPU_PD6: power-domain-cpu6 { !! 646 CPU_PD6: cpu6 {
668 #power-domain-cells = 647 #power-domain-cells = <0>;
669 power-domains = <&CLUS 648 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 649 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 650 };
672 651
673 CPU_PD7: power-domain-cpu7 { !! 652 CPU_PD7: cpu7 {
674 #power-domain-cells = 653 #power-domain-cells = <0>;
675 power-domains = <&CLUS 654 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 655 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 656 };
678 657
679 CLUSTER_PD: power-domain-cpu-c !! 658 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 659 #power-domain-cells = <0>;
681 domain-idle-states = < 660 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 661 };
683 }; 662 };
684 663
685 reserved-memory { 664 reserved-memory {
686 #address-cells = <2>; 665 #address-cells = <2>;
687 #size-cells = <2>; 666 #size-cells = <2>;
688 ranges; 667 ranges;
689 668
690 hyp_mem: memory@85700000 { 669 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 670 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 671 no-map;
693 }; 672 };
694 673
695 xbl_mem: memory@85d00000 { 674 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 675 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 676 no-map;
698 }; 677 };
699 678
700 aop_mem: memory@85f00000 { 679 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 680 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 681 no-map;
703 }; 682 };
704 683
705 aop_cmd_db: memory@85f20000 { 684 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 685 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 686 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 687 no-map;
709 }; 688 };
710 689
711 smem_mem: memory@86000000 { 690 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 691 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 692 no-map;
714 }; 693 };
715 694
716 tz_mem: memory@86200000 { 695 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 696 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 697 no-map;
719 }; 698 };
720 699
721 rmtfs_mem: memory@89b00000 { 700 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 701 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 702 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 703 no-map;
725 704
726 qcom,client-id = <1>; 705 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 706 qcom,vmid = <15>;
728 }; 707 };
729 708
730 camera_mem: memory@8b700000 { 709 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 710 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 711 no-map;
733 }; 712 };
734 713
735 wlan_mem: memory@8bc00000 { 714 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 715 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 716 no-map;
738 }; 717 };
739 718
740 npu_mem: memory@8bd80000 { 719 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 720 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 721 no-map;
743 }; 722 };
744 723
745 adsp_mem: memory@8be00000 { 724 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 725 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 726 no-map;
748 }; 727 };
749 728
750 mpss_mem: memory@8d800000 { 729 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 730 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 731 no-map;
753 }; 732 };
754 733
755 venus_mem: memory@96e00000 { 734 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 735 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 736 no-map;
758 }; 737 };
759 738
760 slpi_mem: memory@97300000 { 739 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 740 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 741 no-map;
763 }; 742 };
764 743
765 ipa_fw_mem: memory@98700000 { 744 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 745 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 746 no-map;
768 }; 747 };
769 748
770 ipa_gsi_mem: memory@98710000 { 749 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 750 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 751 no-map;
773 }; 752 };
774 753
775 gpu_mem: memory@98715000 { 754 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 755 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 756 no-map;
778 }; 757 };
779 758
780 spss_mem: memory@98800000 { 759 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 760 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 761 no-map;
783 }; 762 };
784 763
785 cdsp_mem: memory@98900000 { 764 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 765 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 766 no-map;
788 }; 767 };
789 768
790 qseecom_mem: memory@9e400000 { 769 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 770 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 771 no-map;
793 }; 772 };
794 }; 773 };
795 774
796 smem { 775 smem {
797 compatible = "qcom,smem"; 776 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 777 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 778 hwlocks = <&tcsr_mutex 3>;
800 }; 779 };
801 780
802 smp2p-cdsp { 781 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 782 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 783 qcom,smem = <94>, <432>;
805 784
806 interrupts = <GIC_SPI 576 IRQ_ 785 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 786
808 mboxes = <&apss_shared 6>; 787 mboxes = <&apss_shared 6>;
809 788
810 qcom,local-pid = <0>; 789 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 790 qcom,remote-pid = <5>;
812 791
813 cdsp_smp2p_out: master-kernel 792 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 793 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 794 #qcom,smem-state-cells = <1>;
816 }; 795 };
817 796
818 cdsp_smp2p_in: slave-kernel { 797 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 798 qcom,entry-name = "slave-kernel";
820 799
821 interrupt-controller; 800 interrupt-controller;
822 #interrupt-cells = <2> 801 #interrupt-cells = <2>;
823 }; 802 };
824 }; 803 };
825 804
826 smp2p-lpass { 805 smp2p-lpass {
827 compatible = "qcom,smp2p"; 806 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 807 qcom,smem = <443>, <429>;
829 808
830 interrupts = <GIC_SPI 158 IRQ_ 809 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 810
832 mboxes = <&apss_shared 10>; 811 mboxes = <&apss_shared 10>;
833 812
834 qcom,local-pid = <0>; 813 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 814 qcom,remote-pid = <2>;
836 815
837 adsp_smp2p_out: master-kernel 816 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 817 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 818 #qcom,smem-state-cells = <1>;
840 }; 819 };
841 820
842 adsp_smp2p_in: slave-kernel { 821 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 822 qcom,entry-name = "slave-kernel";
844 823
845 interrupt-controller; 824 interrupt-controller;
846 #interrupt-cells = <2> 825 #interrupt-cells = <2>;
847 }; 826 };
848 }; 827 };
849 828
850 smp2p-mpss { 829 smp2p-mpss {
851 compatible = "qcom,smp2p"; 830 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 831 qcom,smem = <435>, <428>;
853 832
854 interrupts = <GIC_SPI 451 IRQ_ 833 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 834
856 mboxes = <&apss_shared 14>; 835 mboxes = <&apss_shared 14>;
857 836
858 qcom,local-pid = <0>; 837 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 838 qcom,remote-pid = <1>;
860 839
861 modem_smp2p_out: master-kernel 840 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 841 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 842 #qcom,smem-state-cells = <1>;
864 }; 843 };
865 844
866 modem_smp2p_in: slave-kernel { 845 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 846 qcom,entry-name = "slave-kernel";
868 847
869 interrupt-controller; 848 interrupt-controller;
870 #interrupt-cells = <2> 849 #interrupt-cells = <2>;
871 }; 850 };
872 }; 851 };
873 852
874 smp2p-slpi { 853 smp2p-slpi {
875 compatible = "qcom,smp2p"; 854 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 855 qcom,smem = <481>, <430>;
877 856
878 interrupts = <GIC_SPI 172 IRQ_ 857 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 858
880 mboxes = <&apss_shared 26>; 859 mboxes = <&apss_shared 26>;
881 860
882 qcom,local-pid = <0>; 861 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 862 qcom,remote-pid = <3>;
884 863
885 slpi_smp2p_out: master-kernel 864 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 865 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 866 #qcom,smem-state-cells = <1>;
888 }; 867 };
889 868
890 slpi_smp2p_in: slave-kernel { 869 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 870 qcom,entry-name = "slave-kernel";
892 871
893 interrupt-controller; 872 interrupt-controller;
894 #interrupt-cells = <2> 873 #interrupt-cells = <2>;
895 }; 874 };
896 }; 875 };
897 876
898 soc: soc@0 { 877 soc: soc@0 {
899 #address-cells = <2>; 878 #address-cells = <2>;
900 #size-cells = <2>; 879 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 880 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 881 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 882 compatible = "simple-bus";
904 883
905 gcc: clock-controller@100000 { 884 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 885 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 886 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 887 #clock-cells = <1>;
909 #reset-cells = <1>; 888 #reset-cells = <1>;
910 #power-domain-cells = 889 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 890 clock-names = "bi_tcxo",
912 "sleep_c 891 "sleep_clk";
913 clocks = <&rpmhcc RPMH 892 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 893 <&sleep_clk>;
915 }; 894 };
916 895
917 gpi_dma0: dma-controller@80000 896 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 !! 897 compatible = "qcom,sm8150-gpi-dma";
919 reg = <0 0x00800000 0 !! 898 reg = <0 0x800000 0 0x60000>;
920 interrupts = <GIC_SPI 899 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 900 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 901 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 902 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 903 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 904 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 905 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 906 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 907 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 908 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 909 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 910 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 911 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 912 dma-channels = <13>;
934 dma-channel-mask = <0x 913 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 914 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 915 #dma-cells = <3>;
937 status = "disabled"; 916 status = "disabled";
938 }; 917 };
939 918
940 ethernet: ethernet@20000 { <<
941 compatible = "qcom,sm8 <<
942 reg = <0x0 0x00020000 <<
943 <0x0 0x00036000 <<
944 reg-names = "stmmaceth <<
945 clock-names = "stmmace <<
946 clocks = <&gcc GCC_EMA <<
947 <&gcc GCC_EMAC <<
948 <&gcc GCC_EMAC <<
949 <&gcc GCC_EMAC <<
950 interrupts = <GIC_SPI <<
951 <GIC_SPI <<
952 interrupt-names = "mac <<
953 <<
954 power-domains = <&gcc <<
955 resets = <&gcc GCC_EMA <<
956 <<
957 iommus = <&apps_smmu 0 <<
958 <<
959 snps,tso; <<
960 rx-fifo-depth = <4096> <<
961 tx-fifo-depth = <4096> <<
962 <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 <<
978 qupv3_id_0: geniqup@8c0000 { 919 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 920 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 921 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 922 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 923 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 924 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 925 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 926 #address-cells = <2>;
986 #size-cells = <2>; 927 #size-cells = <2>;
987 ranges; 928 ranges;
988 status = "disabled"; 929 status = "disabled";
989 930
990 i2c0: i2c@880000 { 931 i2c0: i2c@880000 {
991 compatible = " 932 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 933 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 934 clock-names = "se";
994 clocks = <&gcc 935 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d <<
996 <&gpi_d <<
997 dma-names = "t <<
998 pinctrl-names 936 pinctrl-names = "default";
999 pinctrl-0 = <& 937 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 938 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 939 #address-cells = <1>;
1002 #size-cells = 940 #size-cells = <0>;
1003 status = "dis 941 status = "disabled";
1004 }; 942 };
1005 943
1006 spi0: spi@880000 { 944 spi0: spi@880000 {
1007 compatible = 945 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 !! 946 reg = <0 0x880000 0 0x4000>;
1009 reg-names = " 947 reg-names = "se";
1010 clock-names = 948 clock-names = "se";
1011 clocks = <&gc 949 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ <<
1013 <&gpi_ <<
1014 dma-names = " <<
1015 pinctrl-names 950 pinctrl-names = "default";
1016 pinctrl-0 = < 951 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 952 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 953 spi-max-frequency = <50000000>;
1019 #address-cell 954 #address-cells = <1>;
1020 #size-cells = 955 #size-cells = <0>;
1021 status = "dis 956 status = "disabled";
1022 }; 957 };
1023 958
1024 i2c1: i2c@884000 { 959 i2c1: i2c@884000 {
1025 compatible = 960 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 961 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 962 clock-names = "se";
1028 clocks = <&gc 963 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 pinctrl-names 964 pinctrl-names = "default";
1033 pinctrl-0 = < 965 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 966 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 967 #address-cells = <1>;
1036 #size-cells = 968 #size-cells = <0>;
1037 status = "dis 969 status = "disabled";
1038 }; 970 };
1039 971
1040 spi1: spi@884000 { 972 spi1: spi@884000 {
1041 compatible = 973 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 !! 974 reg = <0 0x884000 0 0x4000>;
1043 reg-names = " 975 reg-names = "se";
1044 clock-names = 976 clock-names = "se";
1045 clocks = <&gc 977 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ <<
1047 <&gpi_ <<
1048 dma-names = " <<
1049 pinctrl-names 978 pinctrl-names = "default";
1050 pinctrl-0 = < 979 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 980 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 981 spi-max-frequency = <50000000>;
1053 #address-cell 982 #address-cells = <1>;
1054 #size-cells = 983 #size-cells = <0>;
1055 status = "dis 984 status = "disabled";
1056 }; 985 };
1057 986
1058 i2c2: i2c@888000 { 987 i2c2: i2c@888000 {
1059 compatible = 988 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 989 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 990 clock-names = "se";
1062 clocks = <&gc 991 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ <<
1064 <&gpi_ <<
1065 dma-names = " <<
1066 pinctrl-names 992 pinctrl-names = "default";
1067 pinctrl-0 = < 993 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 994 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 995 #address-cells = <1>;
1070 #size-cells = 996 #size-cells = <0>;
1071 status = "dis 997 status = "disabled";
1072 }; 998 };
1073 999
1074 spi2: spi@888000 { 1000 spi2: spi@888000 {
1075 compatible = 1001 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 !! 1002 reg = <0 0x888000 0 0x4000>;
1077 reg-names = " 1003 reg-names = "se";
1078 clock-names = 1004 clock-names = "se";
1079 clocks = <&gc 1005 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ <<
1081 <&gpi_ <<
1082 dma-names = " <<
1083 pinctrl-names 1006 pinctrl-names = "default";
1084 pinctrl-0 = < 1007 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1008 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1009 spi-max-frequency = <50000000>;
1087 #address-cell 1010 #address-cells = <1>;
1088 #size-cells = 1011 #size-cells = <0>;
1089 status = "dis 1012 status = "disabled";
1090 }; 1013 };
1091 1014
1092 i2c3: i2c@88c000 { 1015 i2c3: i2c@88c000 {
1093 compatible = 1016 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1017 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1018 clock-names = "se";
1096 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ <<
1098 <&gpi_ <<
1099 dma-names = " <<
1100 pinctrl-names 1020 pinctrl-names = "default";
1101 pinctrl-0 = < 1021 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1022 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1023 #address-cells = <1>;
1104 #size-cells = 1024 #size-cells = <0>;
1105 status = "dis 1025 status = "disabled";
1106 }; 1026 };
1107 1027
1108 spi3: spi@88c000 { 1028 spi3: spi@88c000 {
1109 compatible = 1029 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 !! 1030 reg = <0 0x88c000 0 0x4000>;
1111 reg-names = " 1031 reg-names = "se";
1112 clock-names = 1032 clock-names = "se";
1113 clocks = <&gc 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ <<
1115 <&gpi_ <<
1116 dma-names = " <<
1117 pinctrl-names 1034 pinctrl-names = "default";
1118 pinctrl-0 = < 1035 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1036 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1037 spi-max-frequency = <50000000>;
1121 #address-cell 1038 #address-cells = <1>;
1122 #size-cells = 1039 #size-cells = <0>;
1123 status = "dis 1040 status = "disabled";
1124 }; 1041 };
1125 1042
1126 i2c4: i2c@890000 { 1043 i2c4: i2c@890000 {
1127 compatible = 1044 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1045 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1046 clock-names = "se";
1130 clocks = <&gc 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ <<
1132 <&gpi_ <<
1133 dma-names = " <<
1134 pinctrl-names 1048 pinctrl-names = "default";
1135 pinctrl-0 = < 1049 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1050 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1051 #address-cells = <1>;
1138 #size-cells = 1052 #size-cells = <0>;
1139 status = "dis 1053 status = "disabled";
1140 }; 1054 };
1141 1055
1142 spi4: spi@890000 { 1056 spi4: spi@890000 {
1143 compatible = 1057 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 !! 1058 reg = <0 0x890000 0 0x4000>;
1145 reg-names = " 1059 reg-names = "se";
1146 clock-names = 1060 clock-names = "se";
1147 clocks = <&gc 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ <<
1149 <&gpi_ <<
1150 dma-names = " <<
1151 pinctrl-names 1062 pinctrl-names = "default";
1152 pinctrl-0 = < 1063 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1064 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1065 spi-max-frequency = <50000000>;
1155 #address-cell 1066 #address-cells = <1>;
1156 #size-cells = 1067 #size-cells = <0>;
1157 status = "dis 1068 status = "disabled";
1158 }; 1069 };
1159 1070
1160 i2c5: i2c@894000 { 1071 i2c5: i2c@894000 {
1161 compatible = 1072 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1073 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1074 clock-names = "se";
1164 clocks = <&gc 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ <<
1166 <&gpi_ <<
1167 dma-names = " <<
1168 pinctrl-names 1076 pinctrl-names = "default";
1169 pinctrl-0 = < 1077 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1078 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1079 #address-cells = <1>;
1172 #size-cells = 1080 #size-cells = <0>;
1173 status = "dis 1081 status = "disabled";
1174 }; 1082 };
1175 1083
1176 spi5: spi@894000 { 1084 spi5: spi@894000 {
1177 compatible = 1085 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 !! 1086 reg = <0 0x894000 0 0x4000>;
1179 reg-names = " 1087 reg-names = "se";
1180 clock-names = 1088 clock-names = "se";
1181 clocks = <&gc 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ <<
1183 <&gpi_ <<
1184 dma-names = " <<
1185 pinctrl-names 1090 pinctrl-names = "default";
1186 pinctrl-0 = < 1091 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1092 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1093 spi-max-frequency = <50000000>;
1189 #address-cell 1094 #address-cells = <1>;
1190 #size-cells = 1095 #size-cells = <0>;
1191 status = "dis 1096 status = "disabled";
1192 }; 1097 };
1193 1098
1194 i2c6: i2c@898000 { 1099 i2c6: i2c@898000 {
1195 compatible = 1100 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1101 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1102 clock-names = "se";
1198 clocks = <&gc 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ <<
1200 <&gpi_ <<
1201 dma-names = " <<
1202 pinctrl-names 1104 pinctrl-names = "default";
1203 pinctrl-0 = < 1105 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1106 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1107 #address-cells = <1>;
1206 #size-cells = 1108 #size-cells = <0>;
1207 status = "dis 1109 status = "disabled";
1208 }; 1110 };
1209 1111
1210 spi6: spi@898000 { 1112 spi6: spi@898000 {
1211 compatible = 1113 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 !! 1114 reg = <0 0x898000 0 0x4000>;
1213 reg-names = " 1115 reg-names = "se";
1214 clock-names = 1116 clock-names = "se";
1215 clocks = <&gc 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ <<
1217 <&gpi_ <<
1218 dma-names = " <<
1219 pinctrl-names 1118 pinctrl-names = "default";
1220 pinctrl-0 = < 1119 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1120 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1121 spi-max-frequency = <50000000>;
1223 #address-cell 1122 #address-cells = <1>;
1224 #size-cells = 1123 #size-cells = <0>;
1225 status = "dis 1124 status = "disabled";
1226 }; 1125 };
1227 1126
1228 i2c7: i2c@89c000 { 1127 i2c7: i2c@89c000 {
1229 compatible = 1128 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1129 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1130 clock-names = "se";
1232 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ <<
1234 <&gpi_ <<
1235 dma-names = " <<
1236 pinctrl-names 1132 pinctrl-names = "default";
1237 pinctrl-0 = < 1133 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = 1134 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1135 #address-cells = <1>;
1240 #size-cells = 1136 #size-cells = <0>;
1241 status = "dis 1137 status = "disabled";
1242 }; 1138 };
1243 1139
1244 spi7: spi@89c000 { 1140 spi7: spi@89c000 {
1245 compatible = 1141 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 !! 1142 reg = <0 0x89c000 0 0x4000>;
1247 reg-names = " 1143 reg-names = "se";
1248 clock-names = 1144 clock-names = "se";
1249 clocks = <&gc 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ <<
1251 <&gpi_ <<
1252 dma-names = " <<
1253 pinctrl-names 1146 pinctrl-names = "default";
1254 pinctrl-0 = < 1147 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1148 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1149 spi-max-frequency = <50000000>;
1257 #address-cell 1150 #address-cells = <1>;
1258 #size-cells = 1151 #size-cells = <0>;
1259 status = "dis 1152 status = "disabled";
1260 }; 1153 };
1261 }; 1154 };
1262 1155
1263 gpi_dma1: dma-controller@a000 1156 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm !! 1157 compatible = "qcom,sm8150-gpi-dma";
1265 reg = <0 0x00a00000 0 !! 1158 reg = <0 0xa00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1159 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1160 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1161 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1162 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1163 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1164 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1165 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1166 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1167 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1168 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1169 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1170 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1171 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1172 dma-channels = <13>;
1280 dma-channel-mask = <0 1173 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1174 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1175 #dma-cells = <3>;
1283 status = "disabled"; 1176 status = "disabled";
1284 }; 1177 };
1285 1178
1286 qupv3_id_1: geniqup@ac0000 { 1179 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1180 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1181 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1182 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1183 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1184 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1185 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1186 #address-cells = <2>;
1294 #size-cells = <2>; 1187 #size-cells = <2>;
1295 ranges; 1188 ranges;
1296 status = "disabled"; 1189 status = "disabled";
1297 1190
1298 i2c8: i2c@a80000 { 1191 i2c8: i2c@a80000 {
1299 compatible = 1192 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1193 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1194 clock-names = "se";
1302 clocks = <&gc 1195 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ <<
1304 <&gpi_ <<
1305 dma-names = " <<
1306 pinctrl-names 1196 pinctrl-names = "default";
1307 pinctrl-0 = < 1197 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1198 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1199 #address-cells = <1>;
1310 #size-cells = 1200 #size-cells = <0>;
1311 status = "dis 1201 status = "disabled";
1312 }; 1202 };
1313 1203
1314 spi8: spi@a80000 { 1204 spi8: spi@a80000 {
1315 compatible = 1205 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 !! 1206 reg = <0 0xa80000 0 0x4000>;
1317 reg-names = " 1207 reg-names = "se";
1318 clock-names = 1208 clock-names = "se";
1319 clocks = <&gc 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ <<
1321 <&gpi_ <<
1322 dma-names = " <<
1323 pinctrl-names 1210 pinctrl-names = "default";
1324 pinctrl-0 = < 1211 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1212 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1213 spi-max-frequency = <50000000>;
1327 #address-cell 1214 #address-cells = <1>;
1328 #size-cells = 1215 #size-cells = <0>;
1329 status = "dis 1216 status = "disabled";
1330 }; 1217 };
1331 1218
1332 i2c9: i2c@a84000 { 1219 i2c9: i2c@a84000 {
1333 compatible = 1220 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1221 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1222 clock-names = "se";
1336 clocks = <&gc 1223 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ <<
1338 <&gpi_ <<
1339 dma-names = " <<
1340 pinctrl-names 1224 pinctrl-names = "default";
1341 pinctrl-0 = < 1225 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1226 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1227 #address-cells = <1>;
1344 #size-cells = 1228 #size-cells = <0>;
1345 status = "dis 1229 status = "disabled";
1346 }; 1230 };
1347 1231
1348 spi9: spi@a84000 { 1232 spi9: spi@a84000 {
1349 compatible = 1233 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 !! 1234 reg = <0 0xa84000 0 0x4000>;
1351 reg-names = " 1235 reg-names = "se";
1352 clock-names = 1236 clock-names = "se";
1353 clocks = <&gc 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ <<
1355 <&gpi_ <<
1356 dma-names = " <<
1357 pinctrl-names 1238 pinctrl-names = "default";
1358 pinctrl-0 = < 1239 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1240 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1241 spi-max-frequency = <50000000>;
1361 #address-cell 1242 #address-cells = <1>;
1362 #size-cells = 1243 #size-cells = <0>;
1363 status = "dis 1244 status = "disabled";
1364 }; 1245 };
1365 1246
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 1247 i2c10: i2c@a88000 {
1378 compatible = 1248 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1249 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1250 clock-names = "se";
1381 clocks = <&gc 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ <<
1383 <&gpi_ <<
1384 dma-names = " <<
1385 pinctrl-names 1252 pinctrl-names = "default";
1386 pinctrl-0 = < 1253 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1255 #address-cells = <1>;
1389 #size-cells = 1256 #size-cells = <0>;
1390 status = "dis 1257 status = "disabled";
1391 }; 1258 };
1392 1259
1393 spi10: spi@a88000 { 1260 spi10: spi@a88000 {
1394 compatible = 1261 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 !! 1262 reg = <0 0xa88000 0 0x4000>;
1396 reg-names = " 1263 reg-names = "se";
1397 clock-names = 1264 clock-names = "se";
1398 clocks = <&gc 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ <<
1400 <&gpi_ <<
1401 dma-names = " <<
1402 pinctrl-names 1266 pinctrl-names = "default";
1403 pinctrl-0 = < 1267 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1268 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1269 spi-max-frequency = <50000000>;
1406 #address-cell 1270 #address-cells = <1>;
1407 #size-cells = 1271 #size-cells = <0>;
1408 status = "dis 1272 status = "disabled";
1409 }; 1273 };
1410 1274
1411 i2c11: i2c@a8c000 { 1275 i2c11: i2c@a8c000 {
1412 compatible = 1276 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1277 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1278 clock-names = "se";
1415 clocks = <&gc 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ <<
1417 <&gpi_ <<
1418 dma-names = " <<
1419 pinctrl-names 1280 pinctrl-names = "default";
1420 pinctrl-0 = < 1281 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1283 #address-cells = <1>;
1423 #size-cells = 1284 #size-cells = <0>;
1424 status = "dis 1285 status = "disabled";
1425 }; 1286 };
1426 1287
1427 spi11: spi@a8c000 { 1288 spi11: spi@a8c000 {
1428 compatible = 1289 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 !! 1290 reg = <0 0xa8c000 0 0x4000>;
1430 reg-names = " 1291 reg-names = "se";
1431 clock-names = 1292 clock-names = "se";
1432 clocks = <&gc 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ <<
1434 <&gpi_ <<
1435 dma-names = " <<
1436 pinctrl-names 1294 pinctrl-names = "default";
1437 pinctrl-0 = < 1295 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1297 spi-max-frequency = <50000000>;
1440 #address-cell 1298 #address-cells = <1>;
1441 #size-cells = 1299 #size-cells = <0>;
1442 status = "dis 1300 status = "disabled";
1443 }; 1301 };
1444 1302
1445 uart2: serial@a90000 1303 uart2: serial@a90000 {
1446 compatible = 1304 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1305 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1306 clock-names = "se";
1449 clocks = <&gc 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1309 status = "disabled";
1452 }; 1310 };
1453 1311
1454 i2c12: i2c@a90000 { 1312 i2c12: i2c@a90000 {
1455 compatible = 1313 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1314 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1315 clock-names = "se";
1458 clocks = <&gc 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 pinctrl-names 1317 pinctrl-names = "default";
1463 pinctrl-0 = < 1318 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1320 #address-cells = <1>;
1466 #size-cells = 1321 #size-cells = <0>;
1467 status = "dis 1322 status = "disabled";
1468 }; 1323 };
1469 1324
1470 spi12: spi@a90000 { 1325 spi12: spi@a90000 {
1471 compatible = 1326 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 !! 1327 reg = <0 0xa90000 0 0x4000>;
1473 reg-names = " 1328 reg-names = "se";
1474 clock-names = 1329 clock-names = "se";
1475 clocks = <&gc 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ <<
1477 <&gpi_ <<
1478 dma-names = " <<
1479 pinctrl-names 1331 pinctrl-names = "default";
1480 pinctrl-0 = < 1332 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1334 spi-max-frequency = <50000000>;
1483 #address-cell 1335 #address-cells = <1>;
1484 #size-cells = 1336 #size-cells = <0>;
1485 status = "dis 1337 status = "disabled";
1486 }; 1338 };
1487 1339
1488 i2c16: i2c@94000 { 1340 i2c16: i2c@94000 {
1489 compatible = 1341 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 !! 1342 reg = <0 0x0094000 0 0x4000>;
1491 clock-names = 1343 clock-names = "se";
1492 clocks = <&gc 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ <<
1494 <&gpi_ <<
1495 dma-names = " <<
1496 pinctrl-names 1345 pinctrl-names = "default";
1497 pinctrl-0 = < 1346 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1347 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1348 #address-cells = <1>;
1500 #size-cells = 1349 #size-cells = <0>;
1501 status = "dis 1350 status = "disabled";
1502 }; 1351 };
1503 1352
1504 spi16: spi@a94000 { 1353 spi16: spi@a94000 {
1505 compatible = 1354 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 !! 1355 reg = <0 0xa94000 0 0x4000>;
1507 reg-names = " 1356 reg-names = "se";
1508 clock-names = 1357 clock-names = "se";
1509 clocks = <&gc 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ <<
1511 <&gpi_ <<
1512 dma-names = " <<
1513 pinctrl-names 1359 pinctrl-names = "default";
1514 pinctrl-0 = < 1360 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1362 spi-max-frequency = <50000000>;
1517 #address-cell 1363 #address-cells = <1>;
1518 #size-cells = 1364 #size-cells = <0>;
1519 status = "dis 1365 status = "disabled";
1520 }; 1366 };
1521 }; 1367 };
1522 1368
1523 gpi_dma2: dma-controller@c000 1369 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm !! 1370 compatible = "qcom,sm8150-gpi-dma";
1525 reg = <0 0x00c00000 0 !! 1371 reg = <0 0xc00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1372 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1373 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1374 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1375 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1376 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1377 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1378 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1379 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1380 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1381 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1382 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1383 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1384 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1385 dma-channels = <13>;
1540 dma-channel-mask = <0 1386 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1387 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1388 #dma-cells = <3>;
1543 status = "disabled"; 1389 status = "disabled";
1544 }; 1390 };
1545 1391
1546 qupv3_id_2: geniqup@cc0000 { 1392 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1393 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1394 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1395
1550 clock-names = "m-ahb" 1396 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1397 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1398 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1399 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1400 #address-cells = <2>;
1555 #size-cells = <2>; 1401 #size-cells = <2>;
1556 ranges; 1402 ranges;
1557 status = "disabled"; 1403 status = "disabled";
1558 1404
1559 i2c17: i2c@c80000 { 1405 i2c17: i2c@c80000 {
1560 compatible = 1406 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1407 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1408 clock-names = "se";
1563 clocks = <&gc 1409 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ <<
1565 <&gpi_ <<
1566 dma-names = " <<
1567 pinctrl-names 1410 pinctrl-names = "default";
1568 pinctrl-0 = < 1411 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1412 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1413 #address-cells = <1>;
1571 #size-cells = 1414 #size-cells = <0>;
1572 status = "dis 1415 status = "disabled";
1573 }; 1416 };
1574 1417
1575 spi17: spi@c80000 { 1418 spi17: spi@c80000 {
1576 compatible = 1419 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 !! 1420 reg = <0 0xc80000 0 0x4000>;
1578 reg-names = " 1421 reg-names = "se";
1579 clock-names = 1422 clock-names = "se";
1580 clocks = <&gc 1423 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ <<
1582 <&gpi_ <<
1583 dma-names = " <<
1584 pinctrl-names 1424 pinctrl-names = "default";
1585 pinctrl-0 = < 1425 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1426 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1427 spi-max-frequency = <50000000>;
1588 #address-cell 1428 #address-cells = <1>;
1589 #size-cells = 1429 #size-cells = <0>;
1590 status = "dis 1430 status = "disabled";
1591 }; 1431 };
1592 1432
1593 i2c18: i2c@c84000 { 1433 i2c18: i2c@c84000 {
1594 compatible = 1434 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1435 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1436 clock-names = "se";
1597 clocks = <&gc 1437 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ <<
1599 <&gpi_ <<
1600 dma-names = " <<
1601 pinctrl-names 1438 pinctrl-names = "default";
1602 pinctrl-0 = < 1439 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1440 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1441 #address-cells = <1>;
1605 #size-cells = 1442 #size-cells = <0>;
1606 status = "dis 1443 status = "disabled";
1607 }; 1444 };
1608 1445
1609 spi18: spi@c84000 { 1446 spi18: spi@c84000 {
1610 compatible = 1447 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 !! 1448 reg = <0 0xc84000 0 0x4000>;
1612 reg-names = " 1449 reg-names = "se";
1613 clock-names = 1450 clock-names = "se";
1614 clocks = <&gc 1451 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ <<
1616 <&gpi_ <<
1617 dma-names = " <<
1618 pinctrl-names 1452 pinctrl-names = "default";
1619 pinctrl-0 = < 1453 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1454 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1455 spi-max-frequency = <50000000>;
1622 #address-cell 1456 #address-cells = <1>;
1623 #size-cells = 1457 #size-cells = <0>;
1624 status = "dis 1458 status = "disabled";
1625 }; 1459 };
1626 1460
1627 i2c19: i2c@c88000 { 1461 i2c19: i2c@c88000 {
1628 compatible = 1462 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1463 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1464 clock-names = "se";
1631 clocks = <&gc 1465 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 pinctrl-names 1466 pinctrl-names = "default";
1636 pinctrl-0 = < 1467 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1468 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1469 #address-cells = <1>;
1639 #size-cells = 1470 #size-cells = <0>;
1640 status = "dis 1471 status = "disabled";
1641 }; 1472 };
1642 1473
1643 spi19: spi@c88000 { 1474 spi19: spi@c88000 {
1644 compatible = 1475 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 !! 1476 reg = <0 0xc88000 0 0x4000>;
1646 reg-names = " 1477 reg-names = "se";
1647 clock-names = 1478 clock-names = "se";
1648 clocks = <&gc 1479 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ <<
1650 <&gpi_ <<
1651 dma-names = " <<
1652 pinctrl-names 1480 pinctrl-names = "default";
1653 pinctrl-0 = < 1481 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1482 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1483 spi-max-frequency = <50000000>;
1656 #address-cell 1484 #address-cells = <1>;
1657 #size-cells = 1485 #size-cells = <0>;
1658 status = "dis 1486 status = "disabled";
1659 }; 1487 };
1660 1488
1661 i2c13: i2c@c8c000 { 1489 i2c13: i2c@c8c000 {
1662 compatible = 1490 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1491 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1492 clock-names = "se";
1665 clocks = <&gc 1493 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ <<
1667 <&gpi_ <<
1668 dma-names = " <<
1669 pinctrl-names 1494 pinctrl-names = "default";
1670 pinctrl-0 = < 1495 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1496 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1497 #address-cells = <1>;
1673 #size-cells = 1498 #size-cells = <0>;
1674 status = "dis 1499 status = "disabled";
1675 }; 1500 };
1676 1501
1677 spi13: spi@c8c000 { 1502 spi13: spi@c8c000 {
1678 compatible = 1503 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 !! 1504 reg = <0 0xc8c000 0 0x4000>;
1680 reg-names = " 1505 reg-names = "se";
1681 clock-names = 1506 clock-names = "se";
1682 clocks = <&gc 1507 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ <<
1684 <&gpi_ <<
1685 dma-names = " <<
1686 pinctrl-names 1508 pinctrl-names = "default";
1687 pinctrl-0 = < 1509 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1510 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1511 spi-max-frequency = <50000000>;
1690 #address-cell 1512 #address-cells = <1>;
1691 #size-cells = 1513 #size-cells = <0>;
1692 status = "dis 1514 status = "disabled";
1693 }; 1515 };
1694 1516
1695 i2c14: i2c@c90000 { 1517 i2c14: i2c@c90000 {
1696 compatible = 1518 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1519 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1520 clock-names = "se";
1699 clocks = <&gc 1521 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ <<
1701 <&gpi_ <<
1702 dma-names = " <<
1703 pinctrl-names 1522 pinctrl-names = "default";
1704 pinctrl-0 = < 1523 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1524 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1525 #address-cells = <1>;
1707 #size-cells = 1526 #size-cells = <0>;
1708 status = "dis 1527 status = "disabled";
1709 }; 1528 };
1710 1529
1711 spi14: spi@c90000 { 1530 spi14: spi@c90000 {
1712 compatible = 1531 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 !! 1532 reg = <0 0xc90000 0 0x4000>;
1714 reg-names = " 1533 reg-names = "se";
1715 clock-names = 1534 clock-names = "se";
1716 clocks = <&gc 1535 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ <<
1718 <&gpi_ <<
1719 dma-names = " <<
1720 pinctrl-names 1536 pinctrl-names = "default";
1721 pinctrl-0 = < 1537 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1538 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1539 spi-max-frequency = <50000000>;
1724 #address-cell 1540 #address-cells = <1>;
1725 #size-cells = 1541 #size-cells = <0>;
1726 status = "dis 1542 status = "disabled";
1727 }; 1543 };
1728 1544
1729 i2c15: i2c@c94000 { 1545 i2c15: i2c@c94000 {
1730 compatible = 1546 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1547 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1548 clock-names = "se";
1733 clocks = <&gc 1549 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ <<
1735 <&gpi_ <<
1736 dma-names = " <<
1737 pinctrl-names 1550 pinctrl-names = "default";
1738 pinctrl-0 = < 1551 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1552 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1553 #address-cells = <1>;
1741 #size-cells = 1554 #size-cells = <0>;
1742 status = "dis 1555 status = "disabled";
1743 }; 1556 };
1744 1557
1745 spi15: spi@c94000 { 1558 spi15: spi@c94000 {
1746 compatible = 1559 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 !! 1560 reg = <0 0xc94000 0 0x4000>;
1748 reg-names = " 1561 reg-names = "se";
1749 clock-names = 1562 clock-names = "se";
1750 clocks = <&gc 1563 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ <<
1752 <&gpi_ <<
1753 dma-names = " <<
1754 pinctrl-names 1564 pinctrl-names = "default";
1755 pinctrl-0 = < 1565 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1566 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1567 spi-max-frequency = <50000000>;
1758 #address-cell 1568 #address-cells = <1>;
1759 #size-cells = 1569 #size-cells = <0>;
1760 status = "dis 1570 status = "disabled";
1761 }; 1571 };
1762 }; 1572 };
1763 1573
1764 config_noc: interconnect@1500 1574 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1575 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1576 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1577 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1578 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1579 };
1770 1580
1771 system_noc: interconnect@1620 1581 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1582 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1583 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1584 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1585 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1586 };
1777 1587
1778 mc_virt: interconnect@163a000 1588 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1589 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1590 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1591 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1592 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1593 };
1784 1594
1785 aggre1_noc: interconnect@16e0 1595 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1596 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1597 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1598 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1599 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1600 };
1791 1601
1792 aggre2_noc: interconnect@1700 1602 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1603 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1604 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1605 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1606 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1607 };
1798 1608
1799 compute_noc: interconnect@172 1609 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1610 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1611 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1612 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1613 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1614 };
1805 1615
1806 mmss_noc: interconnect@174000 1616 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1617 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1618 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1619 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1620 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1621 };
1812 1622
1813 system-cache-controller@92000 1623 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1624 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 1625 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 1626 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 1627 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1628 };
1822 1629
1823 dma@10a2000 { <<
1824 compatible = "qcom,sm <<
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 <<
1832 <0 0x60000000 0 <<
1833 <0 0x60000f20 0 <<
1834 <0 0x60001000 0 <<
1835 <0 0x60100000 0 <<
1836 reg-names = "parf", " <<
1837 device_type = "pci"; <<
1838 linux,pci-domain = <0 <<
1839 bus-range = <0x00 0xf <<
1840 num-lanes = <1>; <<
1841 <<
1842 #address-cells = <3>; <<
1843 #size-cells = <2>; <<
1844 <<
1845 ranges = <0x01000000 <<
1846 <0x02000000 <<
1847 <<
1848 interrupts = <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 <<
1865 interrupt-map-mask = <<
1866 interrupt-map = <0 0 <<
1867 <0 0 <<
1868 <0 0 <<
1869 <0 0 <<
1870 <<
1871 clocks = <&gcc GCC_PC <<
1872 <&gcc GCC_PC <<
1873 <&gcc GCC_PC <<
1874 <&gcc GCC_PC <<
1875 <&gcc GCC_PC <<
1876 <&gcc GCC_PC <<
1877 <&gcc GCC_AG <<
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", <<
1880 "aux", <<
1881 "cfg", <<
1882 "bus_ma <<
1883 "bus_sl <<
1884 "slave_ <<
1885 "tbu", <<
1886 "ref"; <<
1887 <<
1888 iommu-map = <0x0 &a <<
1889 <0x100 &a <<
1890 <<
1891 resets = <&gcc GCC_PC <<
1892 reset-names = "pci"; <<
1893 <<
1894 power-domains = <&gcc <<
1895 <<
1896 phys = <&pcie0_phy>; <<
1897 phy-names = "pciephy" <<
1898 <<
1899 perst-gpios = <&tlmm <<
1900 wake-gpios = <&tlmm 3 <<
1901 <<
1902 pinctrl-names = "defa <<
1903 pinctrl-0 = <&pcie0_d <<
1904 <<
1905 status = "disabled"; <<
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; <<
1917 <<
1918 pcie0_phy: phy@1c06000 { <<
1919 compatible = "qcom,sm <<
1920 reg = <0 0x01c06000 0 <<
1921 clocks = <&gcc GCC_PC <<
1922 <&gcc GCC_PC <<
1923 <&gcc GCC_PC <<
1924 <&gcc GCC_PC <<
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 <<
1937 resets = <&gcc GCC_PC <<
1938 reset-names = "phy"; <<
1939 <<
1940 assigned-clocks = <&g <<
1941 assigned-clock-rates <<
1942 <<
1943 status = "disabled"; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@1c08000 { <<
1947 compatible = "qcom,pc <<
1948 reg = <0 0x01c08000 0 <<
1949 <0 0x40000000 0 <<
1950 <0 0x40000f20 0 <<
1951 <0 0x40001000 0 <<
1952 <0 0x40100000 0 <<
1953 reg-names = "parf", " <<
1954 device_type = "pci"; <<
1955 linux,pci-domain = <1 <<
1956 bus-range = <0x00 0xf <<
1957 num-lanes = <2>; <<
1958 <<
1959 #address-cells = <3>; <<
1960 #size-cells = <2>; <<
1961 <<
1962 ranges = <0x01000000 <<
1963 <0x02000000 <<
1964 <<
1965 interrupts = <GIC_SPI <<
1966 <GIC_SPI <<
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 <<
1982 interrupt-map-mask = <<
1983 interrupt-map = <0 0 <<
1984 <0 0 <<
1985 <0 0 <<
1986 <0 0 <<
1987 <<
1988 clocks = <&gcc GCC_PC <<
1989 <&gcc GCC_PC <<
1990 <&gcc GCC_PC <<
1991 <&gcc GCC_PC <<
1992 <&gcc GCC_PC <<
1993 <&gcc GCC_PC <<
1994 <&gcc GCC_AG <<
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", <<
1997 "aux", <<
1998 "cfg", <<
1999 "bus_ma <<
2000 "bus_sl <<
2001 "slave_ <<
2002 "tbu", <<
2003 "ref"; <<
2004 <<
2005 assigned-clocks = <&g <<
2006 assigned-clock-rates <<
2007 <<
2008 iommu-map = <0x0 &a <<
2009 <0x100 &a <<
2010 <<
2011 resets = <&gcc GCC_PC <<
2012 reset-names = "pci"; <<
2013 <<
2014 power-domains = <&gcc <<
2015 <<
2016 phys = <&pcie1_phy>; <<
2017 phy-names = "pciephy" <<
2018 <<
2019 perst-gpios = <&tlmm <<
2020 enable-gpio = <&tlmm <<
2021 <<
2022 pinctrl-names = "defa <<
2023 pinctrl-0 = <&pcie1_d <<
2024 <<
2025 status = "disabled"; <<
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; <<
2037 <<
2038 pcie1_phy: phy@1c0e000 { <<
2039 compatible = "qcom,sm <<
2040 reg = <0 0x01c0e000 0 <<
2041 clocks = <&gcc GCC_PC <<
2042 <&gcc GCC_PC <<
2043 <&gcc GCC_PC <<
2044 <&gcc GCC_PC <<
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 <<
2057 resets = <&gcc GCC_PC <<
2058 reset-names = "phy"; <<
2059 <<
2060 assigned-clocks = <&g <<
2061 assigned-clock-rates <<
2062 <<
2063 status = "disabled"; <<
2064 }; <<
2065 <<
2066 ufs_mem_hc: ufshc@1d84000 { 1630 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 1631 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 1632 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 1633 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 1634 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 1635 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 1636 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 1637 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 1638 phy-names = "ufsphy";
2075 lanes-per-direction = 1639 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 1640 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 1641 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 1642 reset-names = "rst";
2079 1643
2080 iommus = <&apps_smmu 1644 iommus = <&apps_smmu 0x300 0>;
2081 1645
2082 clock-names = 1646 clock-names =
2083 "core_clk", 1647 "core_clk",
2084 "bus_aggr_clk 1648 "bus_aggr_clk",
2085 "iface_clk", 1649 "iface_clk",
2086 "core_clk_uni 1650 "core_clk_unipro",
2087 "ref_clk", 1651 "ref_clk",
2088 "tx_lane0_syn 1652 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 1653 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 1654 "rx_lane1_sync_clk",
2091 "ice_core_clk 1655 "ice_core_clk";
2092 clocks = 1656 clocks =
2093 <&gcc GCC_UFS 1657 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 1658 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 1659 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 1660 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 1661 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 1662 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1664 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 1665 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 1666 freq-table-hz =
2103 <37500000 300 1667 <37500000 300000000>,
2104 <0 0>, 1668 <0 0>,
2105 <0 0>, 1669 <0 0>,
2106 <37500000 300 1670 <37500000 300000000>,
2107 <0 0>, 1671 <0 0>,
2108 <0 0>, 1672 <0 0>,
2109 <0 0>, 1673 <0 0>,
2110 <0 0>, 1674 <0 0>,
2111 <0 300000000> 1675 <0 300000000>;
2112 1676
2113 status = "disabled"; 1677 status = "disabled";
2114 }; 1678 };
2115 1679
2116 ufs_mem_phy: phy@1d87000 { 1680 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 1681 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 1682 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 1683 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 1684 #size-cells = <2>;
2121 <&gcc GCC_UF !! 1685 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 1686 clock-names = "ref",
2124 "ref_au !! 1687 "ref_aux";
2125 "qref"; !! 1688 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2126 !! 1689 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2127 power-domains = <&gcc <<
2128 1690
2129 resets = <&ufs_mem_hc 1691 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 1692 reset-names = "ufsphy";
>> 1693 status = "disabled";
2131 1694
2132 #phy-cells = <0>; !! 1695 ufs_mem_phy_lanes: phy@1d87400 {
>> 1696 reg = <0 0x01d87400 0 0x16c>,
>> 1697 <0 0x01d87600 0 0x200>,
>> 1698 <0 0x01d87c00 0 0x200>,
>> 1699 <0 0x01d87800 0 0x16c>,
>> 1700 <0 0x01d87a00 0 0x200>;
>> 1701 #phy-cells = <0>;
>> 1702 };
>> 1703 };
2133 1704
2134 status = "disabled"; !! 1705 ipa_virt: interconnect@1e00000 {
>> 1706 compatible = "qcom,sm8150-ipa-virt";
>> 1707 reg = <0 0x01e00000 0 0x1000>;
>> 1708 #interconnect-cells = <1>;
>> 1709 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 1710 };
2136 1711
2137 cryptobam: dma-controller@1dc !! 1712 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 1713 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 1714 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 1715 };
2177 1716
2178 remoteproc_slpi: remoteproc@2 1717 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 1718 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 1719 reg = <0x0 0x02400000 0x0 0x4040>;
2181 1720
2182 interrupts-extended = 1721 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 1722 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 1723 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 1724 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 1725 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 1726 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 1727 "handover", "stop-ack";
2189 1728
2190 clocks = <&rpmhcc RPM 1729 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 1730 clock-names = "xo";
2192 1731
2193 power-domains = <&rpm !! 1732 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
2194 <&rpm !! 1733 <&rpmhpd 3>,
2195 power-domain-names = !! 1734 <&rpmhpd 2>;
>> 1735 power-domain-names = "load_state", "lcx", "lmx";
2196 1736
2197 memory-region = <&slp 1737 memory-region = <&slpi_mem>;
2198 1738
2199 qcom,qmp = <&aoss_qmp <<
2200 <<
2201 qcom,smem-states = <& 1739 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 1740 qcom,smem-state-names = "stop";
2203 1741
2204 status = "disabled"; 1742 status = "disabled";
2205 1743
2206 glink-edge { 1744 glink-edge {
2207 interrupts = 1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 1746 label = "dsps";
2209 qcom,remote-p 1747 qcom,remote-pid = <3>;
2210 mboxes = <&ap 1748 mboxes = <&apss_shared 24>;
2211 <<
2212 fastrpc { <<
2213 compa <<
2214 qcom, <<
2215 label <<
2216 qcom, <<
2217 #addr <<
2218 #size <<
2219 <<
2220 compu <<
2221 <<
2222 <<
2223 <<
2224 }; <<
2225 <<
2226 compu <<
2227 <<
2228 <<
2229 <<
2230 }; <<
2231 <<
2232 compu <<
2233 <<
2234 <<
2235 <<
2236 <<
2237 }; <<
2238 }; <<
2239 }; 1749 };
2240 }; 1750 };
2241 1751
2242 gpu: gpu@2c00000 { 1752 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 1753 /*
>> 1754 * note: the amd,imageon compatible makes it possible
>> 1755 * to use the drm/msm driver without the display node,
>> 1756 * make sure to remove it when display node is added
>> 1757 */
>> 1758 compatible = "qcom,adreno-640.1",
>> 1759 "qcom,adreno",
>> 1760 "amd,imageon";
>> 1761 #stream-id-cells = <16>;
>> 1762
2244 reg = <0 0x02c00000 0 1763 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 1764 reg-names = "kgsl_3d0_reg_memory";
2246 1765
2247 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 1767
2249 iommus = <&adreno_smm 1768 iommus = <&adreno_smmu 0 0x401>;
2250 1769
2251 operating-points-v2 = 1770 operating-points-v2 = <&gpu_opp_table>;
2252 1771
2253 qcom,gmu = <&gmu>; 1772 qcom,gmu = <&gmu>;
2254 1773
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 1774 status = "disabled";
2260 1775
2261 zap-shader { 1776 zap-shader {
2262 memory-region 1777 memory-region = <&gpu_mem>;
2263 }; 1778 };
2264 1779
>> 1780 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 1781 gpu_opp_table: opp-table {
2266 compatible = 1782 compatible = "operating-points-v2";
2267 1783
2268 opp-675000000 1784 opp-675000000 {
2269 opp-h 1785 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 1786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 1787 };
2273 1788
2274 opp-585000000 1789 opp-585000000 {
2275 opp-h 1790 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 1791 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 1792 };
2279 1793
2280 opp-499200000 1794 opp-499200000 {
2281 opp-h 1795 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 1796 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 1797 };
2285 1798
2286 opp-427000000 1799 opp-427000000 {
2287 opp-h 1800 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 1801 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 1802 };
2291 1803
2292 opp-345000000 1804 opp-345000000 {
2293 opp-h 1805 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 1806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 1807 };
2297 1808
2298 opp-257000000 1809 opp-257000000 {
2299 opp-h 1810 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 1811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 1812 };
2303 }; 1813 };
2304 }; 1814 };
2305 1815
2306 gmu: gmu@2c6a000 { 1816 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 1817 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 1818
2309 reg = <0 0x02c6a000 0 1819 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 1820 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 1821 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 1822 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 1823
2314 interrupts = <GIC_SPI 1824 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1825 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 1826 interrupt-names = "hfi", "gmu";
2317 1827
2318 clocks = <&gpucc GPU_ 1828 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 1829 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 1830 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 1831 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 1832 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 1833 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 1834
2325 power-domains = <&gpu 1835 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 1836 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 1837 power-domain-names = "cx", "gx";
2328 1838
2329 iommus = <&adreno_smm 1839 iommus = <&adreno_smmu 5 0x400>;
2330 1840
2331 operating-points-v2 = 1841 operating-points-v2 = <&gmu_opp_table>;
2332 1842
2333 status = "disabled"; 1843 status = "disabled";
2334 1844
2335 gmu_opp_table: opp-ta 1845 gmu_opp_table: opp-table {
2336 compatible = 1846 compatible = "operating-points-v2";
2337 1847
2338 opp-200000000 1848 opp-200000000 {
2339 opp-h 1849 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 1850 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 1851 };
2342 }; 1852 };
2343 }; 1853 };
2344 1854
2345 gpucc: clock-controller@2c900 1855 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 1856 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 1857 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 1858 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 1859 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 1860 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 1861 clock-names = "bi_tcxo",
2352 "gcc_gp 1862 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 1863 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 1864 #clock-cells = <1>;
2355 #reset-cells = <1>; 1865 #reset-cells = <1>;
2356 #power-domain-cells = 1866 #power-domain-cells = <1>;
2357 }; 1867 };
2358 1868
2359 adreno_smmu: iommu@2ca0000 { 1869 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 1870 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 1871 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 1872 #iommu-cells = <2>;
2364 #global-interrupts = 1873 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 1874 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 1875 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 1876 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 1877 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 1878 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 1879 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 1880 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 1881 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 1882 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 1883 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 1884 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 1885 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 1886 clock-names = "ahb", "bus", "iface";
2378 1887
2379 power-domains = <&gpu 1888 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 1889 };
2381 1890
2382 tlmm: pinctrl@3100000 { 1891 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 1892 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 1893 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 1894 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 1895 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 1896 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 1897 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 1898 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 1899 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 1900 gpio-controller;
2392 #gpio-cells = <2>; 1901 #gpio-cells = <2>;
2393 interrupt-controller; 1902 interrupt-controller;
2394 #interrupt-cells = <2 1903 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc <<
2396 1904
2397 qup_i2c0_default: qup !! 1905 qup_i2c0_default: qup-i2c0-default {
2398 pins = "gpio0 !! 1906 mux {
2399 function = "q !! 1907 pins = "gpio0", "gpio1";
2400 drive-strengt !! 1908 function = "qup0";
2401 bias-disable; !! 1909 };
>> 1910
>> 1911 config {
>> 1912 pins = "gpio0", "gpio1";
>> 1913 drive-strength = <0x02>;
>> 1914 bias-disable;
>> 1915 };
2402 }; 1916 };
2403 1917
2404 qup_spi0_default: qup !! 1918 qup_spi0_default: qup-spi0-default {
2405 pins = "gpio0 1919 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 1920 function = "qup0";
2407 drive-strengt 1921 drive-strength = <6>;
2408 bias-disable; 1922 bias-disable;
2409 }; 1923 };
2410 1924
2411 qup_i2c1_default: qup !! 1925 qup_i2c1_default: qup-i2c1-default {
2412 pins = "gpio1 !! 1926 mux {
2413 function = "q !! 1927 pins = "gpio114", "gpio115";
2414 drive-strengt !! 1928 function = "qup1";
2415 bias-disable; !! 1929 };
>> 1930
>> 1931 config {
>> 1932 pins = "gpio114", "gpio115";
>> 1933 drive-strength = <0x02>;
>> 1934 bias-disable;
>> 1935 };
2416 }; 1936 };
2417 1937
2418 qup_spi1_default: qup !! 1938 qup_spi1_default: qup-spi1-default {
2419 pins = "gpio1 1939 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 1940 function = "qup1";
2421 drive-strengt 1941 drive-strength = <6>;
2422 bias-disable; 1942 bias-disable;
2423 }; 1943 };
2424 1944
2425 qup_i2c2_default: qup !! 1945 qup_i2c2_default: qup-i2c2-default {
2426 pins = "gpio1 !! 1946 mux {
2427 function = "q !! 1947 pins = "gpio126", "gpio127";
2428 drive-strengt !! 1948 function = "qup2";
2429 bias-disable; !! 1949 };
>> 1950
>> 1951 config {
>> 1952 pins = "gpio126", "gpio127";
>> 1953 drive-strength = <0x02>;
>> 1954 bias-disable;
>> 1955 };
2430 }; 1956 };
2431 1957
2432 qup_spi2_default: qup !! 1958 qup_spi2_default: qup-spi2-default {
2433 pins = "gpio1 1959 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 1960 function = "qup2";
2435 drive-strengt 1961 drive-strength = <6>;
2436 bias-disable; 1962 bias-disable;
2437 }; 1963 };
2438 1964
2439 qup_i2c3_default: qup !! 1965 qup_i2c3_default: qup-i2c3-default {
2440 pins = "gpio1 !! 1966 mux {
2441 function = "q !! 1967 pins = "gpio144", "gpio145";
2442 drive-strengt !! 1968 function = "qup3";
2443 bias-disable; !! 1969 };
>> 1970
>> 1971 config {
>> 1972 pins = "gpio144", "gpio145";
>> 1973 drive-strength = <0x02>;
>> 1974 bias-disable;
>> 1975 };
2444 }; 1976 };
2445 1977
2446 qup_spi3_default: qup !! 1978 qup_spi3_default: qup-spi3-default {
2447 pins = "gpio1 1979 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 1980 function = "qup3";
2449 drive-strengt 1981 drive-strength = <6>;
2450 bias-disable; 1982 bias-disable;
2451 }; 1983 };
2452 1984
2453 qup_i2c4_default: qup !! 1985 qup_i2c4_default: qup-i2c4-default {
2454 pins = "gpio5 !! 1986 mux {
2455 function = "q !! 1987 pins = "gpio51", "gpio52";
2456 drive-strengt !! 1988 function = "qup4";
2457 bias-disable; !! 1989 };
>> 1990
>> 1991 config {
>> 1992 pins = "gpio51", "gpio52";
>> 1993 drive-strength = <0x02>;
>> 1994 bias-disable;
>> 1995 };
2458 }; 1996 };
2459 1997
2460 qup_spi4_default: qup !! 1998 qup_spi4_default: qup-spi4-default {
2461 pins = "gpio5 1999 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2000 function = "qup4";
2463 drive-strengt 2001 drive-strength = <6>;
2464 bias-disable; 2002 bias-disable;
2465 }; 2003 };
2466 2004
2467 qup_i2c5_default: qup !! 2005 qup_i2c5_default: qup-i2c5-default {
2468 pins = "gpio1 !! 2006 mux {
2469 function = "q !! 2007 pins = "gpio121", "gpio122";
2470 drive-strengt !! 2008 function = "qup5";
2471 bias-disable; !! 2009 };
>> 2010
>> 2011 config {
>> 2012 pins = "gpio121", "gpio122";
>> 2013 drive-strength = <0x02>;
>> 2014 bias-disable;
>> 2015 };
2472 }; 2016 };
2473 2017
2474 qup_spi5_default: qup !! 2018 qup_spi5_default: qup-spi5-default {
2475 pins = "gpio1 2019 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2020 function = "qup5";
2477 drive-strengt 2021 drive-strength = <6>;
2478 bias-disable; 2022 bias-disable;
2479 }; 2023 };
2480 2024
2481 qup_i2c6_default: qup !! 2025 qup_i2c6_default: qup-i2c6-default {
2482 pins = "gpio6 !! 2026 mux {
2483 function = "q !! 2027 pins = "gpio6", "gpio7";
2484 drive-strengt !! 2028 function = "qup6";
2485 bias-disable; !! 2029 };
>> 2030
>> 2031 config {
>> 2032 pins = "gpio6", "gpio7";
>> 2033 drive-strength = <0x02>;
>> 2034 bias-disable;
>> 2035 };
2486 }; 2036 };
2487 2037
2488 qup_spi6_default: qup !! 2038 qup_spi6_default: qup-spi6_default {
2489 pins = "gpio4 2039 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2040 function = "qup6";
2491 drive-strengt 2041 drive-strength = <6>;
2492 bias-disable; 2042 bias-disable;
2493 }; 2043 };
2494 2044
2495 qup_i2c7_default: qup !! 2045 qup_i2c7_default: qup-i2c7-default {
2496 pins = "gpio9 !! 2046 mux {
2497 function = "q !! 2047 pins = "gpio98", "gpio99";
2498 drive-strengt !! 2048 function = "qup7";
2499 bias-disable; !! 2049 };
>> 2050
>> 2051 config {
>> 2052 pins = "gpio98", "gpio99";
>> 2053 drive-strength = <0x02>;
>> 2054 bias-disable;
>> 2055 };
2500 }; 2056 };
2501 2057
2502 qup_spi7_default: qup !! 2058 qup_spi7_default: qup-spi7_default {
2503 pins = "gpio9 2059 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2060 function = "qup7";
2505 drive-strengt 2061 drive-strength = <6>;
2506 bias-disable; 2062 bias-disable;
2507 }; 2063 };
2508 2064
2509 qup_i2c8_default: qup !! 2065 qup_i2c8_default: qup-i2c8-default {
2510 pins = "gpio8 !! 2066 mux {
2511 function = "q !! 2067 pins = "gpio88", "gpio89";
2512 drive-strengt !! 2068 function = "qup8";
2513 bias-disable; !! 2069 };
>> 2070
>> 2071 config {
>> 2072 pins = "gpio88", "gpio89";
>> 2073 drive-strength = <0x02>;
>> 2074 bias-disable;
>> 2075 };
2514 }; 2076 };
2515 2077
2516 qup_spi8_default: qup !! 2078 qup_spi8_default: qup-spi8-default {
2517 pins = "gpio8 2079 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2080 function = "qup8";
2519 drive-strengt 2081 drive-strength = <6>;
2520 bias-disable; 2082 bias-disable;
2521 }; 2083 };
2522 2084
2523 qup_i2c9_default: qup !! 2085 qup_i2c9_default: qup-i2c9-default {
2524 pins = "gpio3 !! 2086 mux {
2525 function = "q !! 2087 pins = "gpio39", "gpio40";
2526 drive-strengt !! 2088 function = "qup9";
2527 bias-disable; !! 2089 };
>> 2090
>> 2091 config {
>> 2092 pins = "gpio39", "gpio40";
>> 2093 drive-strength = <0x02>;
>> 2094 bias-disable;
>> 2095 };
2528 }; 2096 };
2529 2097
2530 qup_spi9_default: qup !! 2098 qup_spi9_default: qup-spi9-default {
2531 pins = "gpio3 2099 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2100 function = "qup9";
2533 drive-strengt 2101 drive-strength = <6>;
2534 bias-disable; 2102 bias-disable;
2535 }; 2103 };
2536 2104
2537 qup_uart9_default: qu !! 2105 qup_i2c10_default: qup-i2c10-default {
2538 pins = "gpio4 !! 2106 mux {
2539 function = "q !! 2107 pins = "gpio9", "gpio10";
2540 drive-strengt !! 2108 function = "qup10";
2541 bias-disable; !! 2109 };
2542 }; <<
2543 2110
2544 qup_i2c10_default: qu !! 2111 config {
2545 pins = "gpio9 !! 2112 pins = "gpio9", "gpio10";
2546 function = "q !! 2113 drive-strength = <0x02>;
2547 drive-strengt !! 2114 bias-disable;
2548 bias-disable; !! 2115 };
2549 }; 2116 };
2550 2117
2551 qup_spi10_default: qu !! 2118 qup_spi10_default: qup-spi10-default {
2552 pins = "gpio9 2119 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2120 function = "qup10";
2554 drive-strengt 2121 drive-strength = <6>;
2555 bias-disable; 2122 bias-disable;
2556 }; 2123 };
2557 2124
2558 qup_i2c11_default: qu !! 2125 qup_i2c11_default: qup-i2c11-default {
2559 pins = "gpio9 !! 2126 mux {
2560 function = "q !! 2127 pins = "gpio94", "gpio95";
2561 drive-strengt !! 2128 function = "qup11";
2562 bias-disable; !! 2129 };
>> 2130
>> 2131 config {
>> 2132 pins = "gpio94", "gpio95";
>> 2133 drive-strength = <0x02>;
>> 2134 bias-disable;
>> 2135 };
2563 }; 2136 };
2564 2137
2565 qup_spi11_default: qu !! 2138 qup_spi11_default: qup-spi11-default {
2566 pins = "gpio9 2139 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2140 function = "qup11";
2568 drive-strengt 2141 drive-strength = <6>;
2569 bias-disable; 2142 bias-disable;
2570 }; 2143 };
2571 2144
2572 qup_i2c12_default: qu !! 2145 qup_i2c12_default: qup-i2c12-default {
2573 pins = "gpio8 !! 2146 mux {
2574 function = "q !! 2147 pins = "gpio83", "gpio84";
2575 drive-strengt !! 2148 function = "qup12";
2576 bias-disable; !! 2149 };
>> 2150
>> 2151 config {
>> 2152 pins = "gpio83", "gpio84";
>> 2153 drive-strength = <0x02>;
>> 2154 bias-disable;
>> 2155 };
2577 }; 2156 };
2578 2157
2579 qup_spi12_default: qu !! 2158 qup_spi12_default: qup-spi12-default {
2580 pins = "gpio8 2159 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2160 function = "qup12";
2582 drive-strengt 2161 drive-strength = <6>;
2583 bias-disable; 2162 bias-disable;
2584 }; 2163 };
2585 2164
2586 qup_i2c13_default: qu !! 2165 qup_i2c13_default: qup-i2c13-default {
2587 pins = "gpio4 !! 2166 mux {
2588 function = "q !! 2167 pins = "gpio43", "gpio44";
2589 drive-strengt !! 2168 function = "qup13";
2590 bias-disable; !! 2169 };
>> 2170
>> 2171 config {
>> 2172 pins = "gpio43", "gpio44";
>> 2173 drive-strength = <0x02>;
>> 2174 bias-disable;
>> 2175 };
2591 }; 2176 };
2592 2177
2593 qup_spi13_default: qu !! 2178 qup_spi13_default: qup-spi13-default {
2594 pins = "gpio4 2179 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2180 function = "qup13";
2596 drive-strengt 2181 drive-strength = <6>;
2597 bias-disable; 2182 bias-disable;
2598 }; 2183 };
2599 2184
2600 qup_i2c14_default: qu !! 2185 qup_i2c14_default: qup-i2c14-default {
2601 pins = "gpio4 !! 2186 mux {
2602 function = "q !! 2187 pins = "gpio47", "gpio48";
2603 drive-strengt !! 2188 function = "qup14";
2604 bias-disable; !! 2189 };
>> 2190
>> 2191 config {
>> 2192 pins = "gpio47", "gpio48";
>> 2193 drive-strength = <0x02>;
>> 2194 bias-disable;
>> 2195 };
2605 }; 2196 };
2606 2197
2607 qup_spi14_default: qu !! 2198 qup_spi14_default: qup-spi14-default {
2608 pins = "gpio4 2199 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2200 function = "qup14";
2610 drive-strengt 2201 drive-strength = <6>;
2611 bias-disable; 2202 bias-disable;
2612 }; 2203 };
2613 2204
2614 qup_i2c15_default: qu !! 2205 qup_i2c15_default: qup-i2c15-default {
2615 pins = "gpio2 !! 2206 mux {
2616 function = "q !! 2207 pins = "gpio27", "gpio28";
2617 drive-strengt !! 2208 function = "qup15";
2618 bias-disable; !! 2209 };
>> 2210
>> 2211 config {
>> 2212 pins = "gpio27", "gpio28";
>> 2213 drive-strength = <0x02>;
>> 2214 bias-disable;
>> 2215 };
2619 }; 2216 };
2620 2217
2621 qup_spi15_default: qu !! 2218 qup_spi15_default: qup-spi15-default {
2622 pins = "gpio2 2219 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2220 function = "qup15";
2624 drive-strengt 2221 drive-strength = <6>;
2625 bias-disable; 2222 bias-disable;
2626 }; 2223 };
2627 2224
2628 qup_i2c16_default: qu !! 2225 qup_i2c16_default: qup-i2c16-default {
2629 pins = "gpio8 !! 2226 mux {
2630 function = "q !! 2227 pins = "gpio86", "gpio85";
2631 drive-strengt !! 2228 function = "qup16";
2632 bias-disable; !! 2229 };
>> 2230
>> 2231 config {
>> 2232 pins = "gpio86", "gpio85";
>> 2233 drive-strength = <0x02>;
>> 2234 bias-disable;
>> 2235 };
2633 }; 2236 };
2634 2237
2635 qup_spi16_default: qu !! 2238 qup_spi16_default: qup-spi16-default {
2636 pins = "gpio8 2239 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2240 function = "qup16";
2638 drive-strengt 2241 drive-strength = <6>;
2639 bias-disable; 2242 bias-disable;
2640 }; 2243 };
2641 2244
2642 qup_i2c17_default: qu !! 2245 qup_i2c17_default: qup-i2c17-default {
2643 pins = "gpio5 !! 2246 mux {
2644 function = "q !! 2247 pins = "gpio55", "gpio56";
2645 drive-strengt !! 2248 function = "qup17";
2646 bias-disable; !! 2249 };
>> 2250
>> 2251 config {
>> 2252 pins = "gpio55", "gpio56";
>> 2253 drive-strength = <0x02>;
>> 2254 bias-disable;
>> 2255 };
2647 }; 2256 };
2648 2257
2649 qup_spi17_default: qu !! 2258 qup_spi17_default: qup-spi17-default {
2650 pins = "gpio5 2259 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2260 function = "qup17";
2652 drive-strengt 2261 drive-strength = <6>;
2653 bias-disable; 2262 bias-disable;
2654 }; 2263 };
2655 2264
2656 qup_i2c18_default: qu !! 2265 qup_i2c18_default: qup-i2c18-default {
2657 pins = "gpio2 !! 2266 mux {
2658 function = "q !! 2267 pins = "gpio23", "gpio24";
2659 drive-strengt !! 2268 function = "qup18";
2660 bias-disable; !! 2269 };
>> 2270
>> 2271 config {
>> 2272 pins = "gpio23", "gpio24";
>> 2273 drive-strength = <0x02>;
>> 2274 bias-disable;
>> 2275 };
2661 }; 2276 };
2662 2277
2663 qup_spi18_default: qu !! 2278 qup_spi18_default: qup-spi18-default {
2664 pins = "gpio2 2279 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2280 function = "qup18";
2666 drive-strengt 2281 drive-strength = <6>;
2667 bias-disable; 2282 bias-disable;
2668 }; 2283 };
2669 2284
2670 qup_i2c19_default: qu !! 2285 qup_i2c19_default: qup-i2c19-default {
2671 pins = "gpio5 !! 2286 mux {
2672 function = "q !! 2287 pins = "gpio57", "gpio58";
2673 drive-strengt !! 2288 function = "qup19";
2674 bias-disable; !! 2289 };
>> 2290
>> 2291 config {
>> 2292 pins = "gpio57", "gpio58";
>> 2293 drive-strength = <0x02>;
>> 2294 bias-disable;
>> 2295 };
2675 }; 2296 };
2676 2297
2677 qup_spi19_default: qu !! 2298 qup_spi19_default: qup-spi19-default {
2678 pins = "gpio5 2299 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2300 function = "qup19";
2680 drive-strengt 2301 drive-strength = <6>;
2681 bias-disable; 2302 bias-disable;
2682 }; 2303 };
2683 <<
2684 pcie0_default_state: <<
2685 perst-pins { <<
2686 pins <<
2687 funct <<
2688 drive <<
2689 bias- <<
2690 }; <<
2691 <<
2692 clkreq-pins { <<
2693 pins <<
2694 funct <<
2695 drive <<
2696 bias- <<
2697 }; <<
2698 <<
2699 wake-pins { <<
2700 pins <<
2701 funct <<
2702 drive <<
2703 bias- <<
2704 }; <<
2705 }; <<
2706 <<
2707 pcie1_default_state: <<
2708 perst-pins { <<
2709 pins <<
2710 funct <<
2711 drive <<
2712 bias- <<
2713 }; <<
2714 <<
2715 clkreq-pins { <<
2716 pins <<
2717 funct <<
2718 drive <<
2719 bias- <<
2720 }; <<
2721 <<
2722 wake-pins { <<
2723 pins <<
2724 funct <<
2725 drive <<
2726 bias- <<
2727 }; <<
2728 }; <<
2729 }; 2304 };
2730 2305
2731 remoteproc_mpss: remoteproc@4 2306 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2307 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2308 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2309
2735 interrupts-extended = 2310 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2311 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2312 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2313 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2314 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2315 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2316 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2317 "stop-ack", "shutdown-ack";
2743 2318
2744 clocks = <&rpmhcc RPM 2319 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2320 clock-names = "xo";
2746 2321
2747 power-domains = <&rpm !! 2322 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2748 <&rpm !! 2323 <&rpmhpd 7>,
2749 power-domain-names = !! 2324 <&rpmhpd 0>;
>> 2325 power-domain-names = "load_state", "cx", "mss";
2750 2326
2751 memory-region = <&mps 2327 memory-region = <&mpss_mem>;
2752 2328
2753 qcom,qmp = <&aoss_qmp <<
2754 <<
2755 qcom,smem-states = <& 2329 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2330 qcom,smem-state-names = "stop";
2757 2331
2758 status = "disabled"; 2332 status = "disabled";
2759 2333
2760 glink-edge { 2334 glink-edge {
2761 interrupts = 2335 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2336 label = "modem";
2763 qcom,remote-p 2337 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2338 mboxes = <&apss_shared 12>;
2765 }; 2339 };
2766 }; 2340 };
2767 2341
2768 stm@6002000 { 2342 stm@6002000 {
2769 compatible = "arm,cor 2343 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2344 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2345 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2346 reg-names = "stm-base", "stm-stimulus-base";
2773 2347
2774 clocks = <&aoss_qmp>; 2348 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2349 clock-names = "apb_pclk";
2776 2350
2777 out-ports { 2351 out-ports {
2778 port { 2352 port {
2779 stm_o 2353 stm_out: endpoint {
2780 2354 remote-endpoint = <&funnel0_in7>;
2781 }; 2355 };
2782 }; 2356 };
2783 }; 2357 };
2784 }; 2358 };
2785 2359
2786 funnel@6041000 { 2360 funnel@6041000 {
2787 compatible = "arm,cor 2361 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2362 reg = <0 0x06041000 0 0x1000>;
2789 2363
2790 clocks = <&aoss_qmp>; 2364 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2365 clock-names = "apb_pclk";
2792 2366
2793 out-ports { 2367 out-ports {
2794 port { 2368 port {
2795 funne 2369 funnel0_out: endpoint {
2796 2370 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2371 };
2798 }; 2372 };
2799 }; 2373 };
2800 2374
2801 in-ports { 2375 in-ports {
2802 #address-cell 2376 #address-cells = <1>;
2803 #size-cells = 2377 #size-cells = <0>;
2804 2378
2805 port@7 { 2379 port@7 {
2806 reg = 2380 reg = <7>;
2807 funne 2381 funnel0_in7: endpoint {
2808 2382 remote-endpoint = <&stm_out>;
2809 }; 2383 };
2810 }; 2384 };
2811 }; 2385 };
2812 }; 2386 };
2813 2387
2814 funnel@6042000 { 2388 funnel@6042000 {
2815 compatible = "arm,cor 2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2390 reg = <0 0x06042000 0 0x1000>;
2817 2391
2818 clocks = <&aoss_qmp>; 2392 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2393 clock-names = "apb_pclk";
2820 2394
2821 out-ports { 2395 out-ports {
2822 port { 2396 port {
2823 funne 2397 funnel1_out: endpoint {
2824 2398 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2399 };
2826 }; 2400 };
2827 }; 2401 };
2828 2402
2829 in-ports { 2403 in-ports {
2830 #address-cell 2404 #address-cells = <1>;
2831 #size-cells = 2405 #size-cells = <0>;
2832 2406
2833 port@4 { 2407 port@4 {
2834 reg = 2408 reg = <4>;
2835 funne 2409 funnel1_in4: endpoint {
2836 2410 remote-endpoint = <&swao_replicator_out>;
2837 }; 2411 };
2838 }; 2412 };
2839 }; 2413 };
2840 }; 2414 };
2841 2415
2842 funnel@6043000 { 2416 funnel@6043000 {
2843 compatible = "arm,cor 2417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2418 reg = <0 0x06043000 0 0x1000>;
2845 2419
2846 clocks = <&aoss_qmp>; 2420 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2421 clock-names = "apb_pclk";
2848 2422
2849 out-ports { 2423 out-ports {
2850 port { 2424 port {
2851 funne 2425 funnel2_out: endpoint {
2852 2426 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2427 };
2854 }; 2428 };
2855 }; 2429 };
2856 2430
2857 in-ports { 2431 in-ports {
2858 #address-cell 2432 #address-cells = <1>;
2859 #size-cells = 2433 #size-cells = <0>;
2860 2434
2861 port@2 { 2435 port@2 {
2862 reg = 2436 reg = <2>;
2863 funne 2437 funnel2_in2: endpoint {
2864 2438 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2439 };
2866 }; 2440 };
2867 }; 2441 };
2868 }; 2442 };
2869 2443
2870 funnel@6045000 { 2444 funnel@6045000 {
2871 compatible = "arm,cor 2445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2446 reg = <0 0x06045000 0 0x1000>;
2873 2447
2874 clocks = <&aoss_qmp>; 2448 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2449 clock-names = "apb_pclk";
2876 2450
2877 out-ports { 2451 out-ports {
2878 port { 2452 port {
2879 merge 2453 merge_funnel_out: endpoint {
2880 2454 remote-endpoint = <&etf_in>;
2881 }; 2455 };
2882 }; 2456 };
2883 }; 2457 };
2884 2458
2885 in-ports { 2459 in-ports {
2886 #address-cell 2460 #address-cells = <1>;
2887 #size-cells = 2461 #size-cells = <0>;
2888 2462
2889 port@0 { 2463 port@0 {
2890 reg = 2464 reg = <0>;
2891 merge 2465 merge_funnel_in0: endpoint {
2892 2466 remote-endpoint = <&funnel0_out>;
2893 }; 2467 };
2894 }; 2468 };
2895 2469
2896 port@1 { 2470 port@1 {
2897 reg = 2471 reg = <1>;
2898 merge 2472 merge_funnel_in1: endpoint {
2899 2473 remote-endpoint = <&funnel1_out>;
2900 }; 2474 };
2901 }; 2475 };
2902 2476
2903 port@2 { 2477 port@2 {
2904 reg = 2478 reg = <2>;
2905 merge 2479 merge_funnel_in2: endpoint {
2906 2480 remote-endpoint = <&funnel2_out>;
2907 }; 2481 };
2908 }; 2482 };
2909 }; 2483 };
2910 }; 2484 };
2911 2485
2912 replicator@6046000 { 2486 replicator@6046000 {
2913 compatible = "arm,cor 2487 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2488 reg = <0 0x06046000 0 0x1000>;
2915 2489
2916 clocks = <&aoss_qmp>; 2490 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2491 clock-names = "apb_pclk";
2918 2492
2919 out-ports { 2493 out-ports {
2920 #address-cell 2494 #address-cells = <1>;
2921 #size-cells = 2495 #size-cells = <0>;
2922 2496
2923 port@0 { 2497 port@0 {
2924 reg = 2498 reg = <0>;
2925 repli 2499 replicator_out0: endpoint {
2926 2500 remote-endpoint = <&etr_in>;
2927 }; 2501 };
2928 }; 2502 };
2929 2503
2930 port@1 { 2504 port@1 {
2931 reg = 2505 reg = <1>;
2932 repli 2506 replicator_out1: endpoint {
2933 2507 remote-endpoint = <&replicator1_in>;
2934 }; 2508 };
2935 }; 2509 };
2936 }; 2510 };
2937 2511
2938 in-ports { 2512 in-ports {
2939 port { 2513 port {
2940 repli 2514 replicator_in0: endpoint {
2941 2515 remote-endpoint = <&etf_out>;
2942 }; 2516 };
2943 }; 2517 };
2944 }; 2518 };
2945 }; 2519 };
2946 2520
2947 etf@6047000 { 2521 etf@6047000 {
2948 compatible = "arm,cor 2522 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2523 reg = <0 0x06047000 0 0x1000>;
2950 2524
2951 clocks = <&aoss_qmp>; 2525 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2526 clock-names = "apb_pclk";
2953 2527
2954 out-ports { 2528 out-ports {
2955 port { 2529 port {
2956 etf_o 2530 etf_out: endpoint {
2957 2531 remote-endpoint = <&replicator_in0>;
2958 }; 2532 };
2959 }; 2533 };
2960 }; 2534 };
2961 2535
2962 in-ports { 2536 in-ports {
2963 port { 2537 port {
2964 etf_i 2538 etf_in: endpoint {
2965 2539 remote-endpoint = <&merge_funnel_out>;
2966 }; 2540 };
2967 }; 2541 };
2968 }; 2542 };
2969 }; 2543 };
2970 2544
2971 etr@6048000 { 2545 etr@6048000 {
2972 compatible = "arm,cor 2546 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2547 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2548 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2549
2976 clocks = <&aoss_qmp>; 2550 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2551 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2552 arm,scatter-gather;
2979 2553
2980 in-ports { 2554 in-ports {
2981 port { 2555 port {
2982 etr_i 2556 etr_in: endpoint {
2983 2557 remote-endpoint = <&replicator_out0>;
2984 }; 2558 };
2985 }; 2559 };
2986 }; 2560 };
2987 }; 2561 };
2988 2562
2989 replicator@604a000 { 2563 replicator@604a000 {
2990 compatible = "arm,cor 2564 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2565 reg = <0 0x0604a000 0 0x1000>;
2992 2566
2993 clocks = <&aoss_qmp>; 2567 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2568 clock-names = "apb_pclk";
2995 2569
2996 out-ports { 2570 out-ports {
2997 #address-cell 2571 #address-cells = <1>;
2998 #size-cells = 2572 #size-cells = <0>;
2999 2573
3000 port@1 { 2574 port@1 {
3001 reg = 2575 reg = <1>;
3002 repli 2576 replicator1_out: endpoint {
3003 2577 remote-endpoint = <&swao_funnel_in>;
3004 }; 2578 };
3005 }; 2579 };
3006 }; 2580 };
3007 2581
3008 in-ports { 2582 in-ports {
>> 2583 #address-cells = <1>;
>> 2584 #size-cells = <0>;
3009 2585
3010 port { !! 2586 port@1 {
>> 2587 reg = <1>;
3011 repli 2588 replicator1_in: endpoint {
3012 2589 remote-endpoint = <&replicator_out1>;
3013 }; 2590 };
3014 }; 2591 };
3015 }; 2592 };
3016 }; 2593 };
3017 2594
3018 funnel@6b08000 { 2595 funnel@6b08000 {
3019 compatible = "arm,cor 2596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2597 reg = <0 0x06b08000 0 0x1000>;
3021 2598
3022 clocks = <&aoss_qmp>; 2599 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2600 clock-names = "apb_pclk";
3024 2601
3025 out-ports { 2602 out-ports {
3026 port { 2603 port {
3027 swao_ 2604 swao_funnel_out: endpoint {
3028 2605 remote-endpoint = <&swao_etf_in>;
3029 }; 2606 };
3030 }; 2607 };
3031 }; 2608 };
3032 2609
3033 in-ports { 2610 in-ports {
3034 #address-cell 2611 #address-cells = <1>;
3035 #size-cells = 2612 #size-cells = <0>;
3036 2613
3037 port@6 { 2614 port@6 {
3038 reg = 2615 reg = <6>;
3039 swao_ 2616 swao_funnel_in: endpoint {
3040 2617 remote-endpoint = <&replicator1_out>;
3041 }; 2618 };
3042 }; 2619 };
3043 }; 2620 };
3044 }; 2621 };
3045 2622
3046 etf@6b09000 { 2623 etf@6b09000 {
3047 compatible = "arm,cor 2624 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2625 reg = <0 0x06b09000 0 0x1000>;
3049 2626
3050 clocks = <&aoss_qmp>; 2627 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2628 clock-names = "apb_pclk";
3052 2629
3053 out-ports { 2630 out-ports {
3054 port { 2631 port {
3055 swao_ 2632 swao_etf_out: endpoint {
3056 2633 remote-endpoint = <&swao_replicator_in>;
3057 }; 2634 };
3058 }; 2635 };
3059 }; 2636 };
3060 2637
3061 in-ports { 2638 in-ports {
3062 port { 2639 port {
3063 swao_ 2640 swao_etf_in: endpoint {
3064 2641 remote-endpoint = <&swao_funnel_out>;
3065 }; 2642 };
3066 }; 2643 };
3067 }; 2644 };
3068 }; 2645 };
3069 2646
3070 replicator@6b0a000 { 2647 replicator@6b0a000 {
3071 compatible = "arm,cor 2648 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 2649 reg = <0 0x06b0a000 0 0x1000>;
3073 2650
3074 clocks = <&aoss_qmp>; 2651 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 2652 clock-names = "apb_pclk";
3076 qcom,replicator-loses 2653 qcom,replicator-loses-context;
3077 2654
3078 out-ports { 2655 out-ports {
3079 port { 2656 port {
3080 swao_ 2657 swao_replicator_out: endpoint {
3081 2658 remote-endpoint = <&funnel1_in4>;
3082 }; 2659 };
3083 }; 2660 };
3084 }; 2661 };
3085 2662
3086 in-ports { 2663 in-ports {
3087 port { 2664 port {
3088 swao_ 2665 swao_replicator_in: endpoint {
3089 2666 remote-endpoint = <&swao_etf_out>;
3090 }; 2667 };
3091 }; 2668 };
3092 }; 2669 };
3093 }; 2670 };
3094 2671
3095 etm@7040000 { 2672 etm@7040000 {
3096 compatible = "arm,cor 2673 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 2674 reg = <0 0x07040000 0 0x1000>;
3098 2675
3099 cpu = <&CPU0>; 2676 cpu = <&CPU0>;
3100 2677
3101 clocks = <&aoss_qmp>; 2678 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 2679 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 2680 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 2681 qcom,skip-power-up;
3105 2682
3106 out-ports { 2683 out-ports {
3107 port { 2684 port {
3108 etm0_ 2685 etm0_out: endpoint {
3109 2686 remote-endpoint = <&apss_funnel_in0>;
3110 }; 2687 };
3111 }; 2688 };
3112 }; 2689 };
3113 }; 2690 };
3114 2691
3115 etm@7140000 { 2692 etm@7140000 {
3116 compatible = "arm,cor 2693 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 2694 reg = <0 0x07140000 0 0x1000>;
3118 2695
3119 cpu = <&CPU1>; 2696 cpu = <&CPU1>;
3120 2697
3121 clocks = <&aoss_qmp>; 2698 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 2699 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 2700 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 2701 qcom,skip-power-up;
3125 2702
3126 out-ports { 2703 out-ports {
3127 port { 2704 port {
3128 etm1_ 2705 etm1_out: endpoint {
3129 2706 remote-endpoint = <&apss_funnel_in1>;
3130 }; 2707 };
3131 }; 2708 };
3132 }; 2709 };
3133 }; 2710 };
3134 2711
3135 etm@7240000 { 2712 etm@7240000 {
3136 compatible = "arm,cor 2713 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 2714 reg = <0 0x07240000 0 0x1000>;
3138 2715
3139 cpu = <&CPU2>; 2716 cpu = <&CPU2>;
3140 2717
3141 clocks = <&aoss_qmp>; 2718 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 2719 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 2720 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 2721 qcom,skip-power-up;
3145 2722
3146 out-ports { 2723 out-ports {
3147 port { 2724 port {
3148 etm2_ 2725 etm2_out: endpoint {
3149 2726 remote-endpoint = <&apss_funnel_in2>;
3150 }; 2727 };
3151 }; 2728 };
3152 }; 2729 };
3153 }; 2730 };
3154 2731
3155 etm@7340000 { 2732 etm@7340000 {
3156 compatible = "arm,cor 2733 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 2734 reg = <0 0x07340000 0 0x1000>;
3158 2735
3159 cpu = <&CPU3>; 2736 cpu = <&CPU3>;
3160 2737
3161 clocks = <&aoss_qmp>; 2738 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 2739 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 2740 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 2741 qcom,skip-power-up;
3165 2742
3166 out-ports { 2743 out-ports {
3167 port { 2744 port {
3168 etm3_ 2745 etm3_out: endpoint {
3169 2746 remote-endpoint = <&apss_funnel_in3>;
3170 }; 2747 };
3171 }; 2748 };
3172 }; 2749 };
3173 }; 2750 };
3174 2751
3175 etm@7440000 { 2752 etm@7440000 {
3176 compatible = "arm,cor 2753 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 2754 reg = <0 0x07440000 0 0x1000>;
3178 2755
3179 cpu = <&CPU4>; 2756 cpu = <&CPU4>;
3180 2757
3181 clocks = <&aoss_qmp>; 2758 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 2759 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 2760 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 2761 qcom,skip-power-up;
3185 2762
3186 out-ports { 2763 out-ports {
3187 port { 2764 port {
3188 etm4_ 2765 etm4_out: endpoint {
3189 2766 remote-endpoint = <&apss_funnel_in4>;
3190 }; 2767 };
3191 }; 2768 };
3192 }; 2769 };
3193 }; 2770 };
3194 2771
3195 etm@7540000 { 2772 etm@7540000 {
3196 compatible = "arm,cor 2773 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 2774 reg = <0 0x07540000 0 0x1000>;
3198 2775
3199 cpu = <&CPU5>; 2776 cpu = <&CPU5>;
3200 2777
3201 clocks = <&aoss_qmp>; 2778 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 2779 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 2780 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 2781 qcom,skip-power-up;
3205 2782
3206 out-ports { 2783 out-ports {
3207 port { 2784 port {
3208 etm5_ 2785 etm5_out: endpoint {
3209 2786 remote-endpoint = <&apss_funnel_in5>;
3210 }; 2787 };
3211 }; 2788 };
3212 }; 2789 };
3213 }; 2790 };
3214 2791
3215 etm@7640000 { 2792 etm@7640000 {
3216 compatible = "arm,cor 2793 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 2794 reg = <0 0x07640000 0 0x1000>;
3218 2795
3219 cpu = <&CPU6>; 2796 cpu = <&CPU6>;
3220 2797
3221 clocks = <&aoss_qmp>; 2798 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 2799 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 2800 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 2801 qcom,skip-power-up;
3225 2802
3226 out-ports { 2803 out-ports {
3227 port { 2804 port {
3228 etm6_ 2805 etm6_out: endpoint {
3229 2806 remote-endpoint = <&apss_funnel_in6>;
3230 }; 2807 };
3231 }; 2808 };
3232 }; 2809 };
3233 }; 2810 };
3234 2811
3235 etm@7740000 { 2812 etm@7740000 {
3236 compatible = "arm,cor 2813 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 2814 reg = <0 0x07740000 0 0x1000>;
3238 2815
3239 cpu = <&CPU7>; 2816 cpu = <&CPU7>;
3240 2817
3241 clocks = <&aoss_qmp>; 2818 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 2819 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 2820 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 2821 qcom,skip-power-up;
3245 2822
3246 out-ports { 2823 out-ports {
3247 port { 2824 port {
3248 etm7_ 2825 etm7_out: endpoint {
3249 2826 remote-endpoint = <&apss_funnel_in7>;
3250 }; 2827 };
3251 }; 2828 };
3252 }; 2829 };
3253 }; 2830 };
3254 2831
3255 funnel@7800000 { /* APSS Funn 2832 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 2834 reg = <0 0x07800000 0 0x1000>;
3258 2835
3259 clocks = <&aoss_qmp>; 2836 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 2837 clock-names = "apb_pclk";
3261 2838
3262 out-ports { 2839 out-ports {
3263 port { 2840 port {
3264 apss_ 2841 apss_funnel_out: endpoint {
3265 2842 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 2843 };
3267 }; 2844 };
3268 }; 2845 };
3269 2846
3270 in-ports { 2847 in-ports {
3271 #address-cell 2848 #address-cells = <1>;
3272 #size-cells = 2849 #size-cells = <0>;
3273 2850
3274 port@0 { 2851 port@0 {
3275 reg = 2852 reg = <0>;
3276 apss_ 2853 apss_funnel_in0: endpoint {
3277 2854 remote-endpoint = <&etm0_out>;
3278 }; 2855 };
3279 }; 2856 };
3280 2857
3281 port@1 { 2858 port@1 {
3282 reg = 2859 reg = <1>;
3283 apss_ 2860 apss_funnel_in1: endpoint {
3284 2861 remote-endpoint = <&etm1_out>;
3285 }; 2862 };
3286 }; 2863 };
3287 2864
3288 port@2 { 2865 port@2 {
3289 reg = 2866 reg = <2>;
3290 apss_ 2867 apss_funnel_in2: endpoint {
3291 2868 remote-endpoint = <&etm2_out>;
3292 }; 2869 };
3293 }; 2870 };
3294 2871
3295 port@3 { 2872 port@3 {
3296 reg = 2873 reg = <3>;
3297 apss_ 2874 apss_funnel_in3: endpoint {
3298 2875 remote-endpoint = <&etm3_out>;
3299 }; 2876 };
3300 }; 2877 };
3301 2878
3302 port@4 { 2879 port@4 {
3303 reg = 2880 reg = <4>;
3304 apss_ 2881 apss_funnel_in4: endpoint {
3305 2882 remote-endpoint = <&etm4_out>;
3306 }; 2883 };
3307 }; 2884 };
3308 2885
3309 port@5 { 2886 port@5 {
3310 reg = 2887 reg = <5>;
3311 apss_ 2888 apss_funnel_in5: endpoint {
3312 2889 remote-endpoint = <&etm5_out>;
3313 }; 2890 };
3314 }; 2891 };
3315 2892
3316 port@6 { 2893 port@6 {
3317 reg = 2894 reg = <6>;
3318 apss_ 2895 apss_funnel_in6: endpoint {
3319 2896 remote-endpoint = <&etm6_out>;
3320 }; 2897 };
3321 }; 2898 };
3322 2899
3323 port@7 { 2900 port@7 {
3324 reg = 2901 reg = <7>;
3325 apss_ 2902 apss_funnel_in7: endpoint {
3326 2903 remote-endpoint = <&etm7_out>;
3327 }; 2904 };
3328 }; 2905 };
3329 }; 2906 };
3330 }; 2907 };
3331 2908
3332 funnel@7810000 { 2909 funnel@7810000 {
3333 compatible = "arm,cor 2910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 2911 reg = <0 0x07810000 0 0x1000>;
3335 2912
3336 clocks = <&aoss_qmp>; 2913 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 2914 clock-names = "apb_pclk";
3338 2915
3339 out-ports { 2916 out-ports {
3340 port { 2917 port {
3341 apss_ 2918 apss_merge_funnel_out: endpoint {
3342 2919 remote-endpoint = <&funnel2_in2>;
3343 }; 2920 };
3344 }; 2921 };
3345 }; 2922 };
3346 2923
3347 in-ports { 2924 in-ports {
3348 port { 2925 port {
3349 apss_ 2926 apss_merge_funnel_in: endpoint {
3350 2927 remote-endpoint = <&apss_funnel_out>;
3351 }; 2928 };
3352 }; 2929 };
3353 }; 2930 };
3354 }; 2931 };
3355 2932
3356 remoteproc_cdsp: remoteproc@8 2933 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 2934 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 2935 reg = <0x0 0x08300000 0x0 0x4040>;
3359 2936
3360 interrupts-extended = 2937 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 2938 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 2939 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 2940 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 2941 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 2942 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 2943 "handover", "stop-ack";
3367 2944
3368 clocks = <&rpmhcc RPM 2945 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 2946 clock-names = "xo";
3370 2947
3371 power-domains = <&rpm !! 2948 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 2949 <&rpmhpd 7>;
>> 2950 power-domain-names = "load_state", "cx";
3372 2951
3373 memory-region = <&cds 2952 memory-region = <&cdsp_mem>;
3374 2953
3375 qcom,qmp = <&aoss_qmp <<
3376 <<
3377 qcom,smem-states = <& 2954 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 2955 qcom,smem-state-names = "stop";
3379 2956
3380 status = "disabled"; 2957 status = "disabled";
3381 2958
3382 glink-edge { 2959 glink-edge {
3383 interrupts = 2960 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 2961 label = "cdsp";
3385 qcom,remote-p 2962 qcom,remote-pid = <5>;
3386 mboxes = <&ap 2963 mboxes = <&apss_shared 4>;
3387 <<
3388 fastrpc { <<
3389 compa <<
3390 qcom, <<
3391 label <<
3392 qcom, <<
3393 #addr <<
3394 #size <<
3395 <<
3396 compu <<
3397 <<
3398 <<
3399 <<
3400 }; <<
3401 <<
3402 compu <<
3403 <<
3404 <<
3405 <<
3406 }; <<
3407 <<
3408 compu <<
3409 <<
3410 <<
3411 <<
3412 }; <<
3413 <<
3414 compu <<
3415 <<
3416 <<
3417 <<
3418 }; <<
3419 <<
3420 compu <<
3421 <<
3422 <<
3423 <<
3424 }; <<
3425 <<
3426 compu <<
3427 <<
3428 <<
3429 <<
3430 }; <<
3431 <<
3432 compu <<
3433 <<
3434 <<
3435 <<
3436 }; <<
3437 <<
3438 compu <<
3439 <<
3440 <<
3441 <<
3442 }; <<
3443 <<
3444 /* no <<
3445 }; <<
3446 }; 2964 };
3447 }; 2965 };
3448 2966
3449 usb_1_hsphy: phy@88e2000 { 2967 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 2968 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 2969 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 2970 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 2971 status = "disabled";
3454 #phy-cells = <0>; 2972 #phy-cells = <0>;
3455 2973
3456 clocks = <&rpmhcc RPM 2974 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 2975 clock-names = "ref";
3458 2976
3459 resets = <&gcc GCC_QU 2977 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 2978 };
3461 2979
3462 usb_2_hsphy: phy@88e3000 { 2980 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 2981 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 2982 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 2983 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 2984 status = "disabled";
3467 #phy-cells = <0>; 2985 #phy-cells = <0>;
3468 2986
3469 clocks = <&rpmhcc RPM 2987 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 2988 clock-names = "ref";
3471 2989
3472 resets = <&gcc GCC_QU 2990 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 2991 };
3474 2992
3475 usb_1_qmpphy: phy@88e8000 { !! 2993 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 2994 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 2995 reg = <0 0x088e9000 0 0x18c>,
>> 2996 <0 0x088e8000 0 0x10>;
>> 2997 reg-names = "reg-base", "dp_com";
>> 2998 status = "disabled";
>> 2999 #address-cells = <2>;
>> 3000 #size-cells = <2>;
>> 3001 ranges;
3478 3002
3479 clocks = <&gcc GCC_US 3003 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3004 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3005 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3006 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3007 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3008
3488 resets = <&gcc GCC_US 3009 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3010 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3011 reset-names = "phy", "common";
3491 3012
3492 #clock-cells = <1>; !! 3013 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3014 reg = <0 0x088e9200 0 0x200>,
3494 !! 3015 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3016 <0 0x088e9c00 0 0x218>,
3496 !! 3017 <0 0x088e9600 0 0x200>,
3497 ports { !! 3018 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3019 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3020 #clock-cells = <0>;
3500 !! 3021 #phy-cells = <0>;
3501 port@0 { !! 3022 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3023 clock-names = "pipe0";
3503 !! 3024 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3025 };
3524 }; 3026 };
3525 3027
3526 usb_2_qmpphy: phy@88eb000 { 3028 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3029 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3030 reg = <0 0x088eb000 0 0x200>;
>> 3031 status = "disabled";
>> 3032 #address-cells = <2>;
>> 3033 #size-cells = <2>;
>> 3034 ranges;
3529 3035
3530 clocks = <&gcc GCC_US 3036 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3037 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3038 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3039 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3040 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 <<
3542 resets = <&gcc GCC_US <<
3543 <&gcc GCC_US <<
3544 reset-names = "phy", <<
3545 "phy_ph <<
3546 <<
3547 status = "disabled"; <<
3548 }; <<
3549 3041
3550 sdhc_2: mmc@8804000 { !! 3042 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3551 compatible = "qcom,sm !! 3043 <&gcc GCC_USB3_PHY_SEC_BCR>;
3552 reg = <0 0x08804000 0 !! 3044 reset-names = "phy", "common";
3553 <<
3554 interrupts = <GIC_SPI <<
3555 <GIC_SPI <<
3556 interrupt-names = "hc <<
3557 <<
3558 clocks = <&gcc GCC_SD <<
3559 <&gcc GCC_SD <<
3560 <&rpmhcc RPM <<
3561 clock-names = "iface" <<
3562 iommus = <&apps_smmu <<
3563 qcom,dll-config = <0x <<
3564 qcom,ddr-config = <0x <<
3565 power-domains = <&rpm <<
3566 operating-points-v2 = <<
3567 <<
3568 status = "disabled"; <<
3569 <<
3570 sdhc2_opp_table: opp- <<
3571 compatible = <<
3572 <<
3573 opp-19200000 <<
3574 opp-h <<
3575 requi <<
3576 }; <<
3577 <<
3578 opp-50000000 <<
3579 opp-h <<
3580 requi <<
3581 }; <<
3582 <<
3583 opp-100000000 <<
3584 opp-h <<
3585 requi <<
3586 }; <<
3587 3045
3588 opp-202000000 !! 3046 usb_2_ssphy: phy@88eb200 {
3589 opp-h !! 3047 reg = <0 0x088eb200 0 0x200>,
3590 requi !! 3048 <0 0x088eb400 0 0x200>,
3591 }; !! 3049 <0 0x088eb800 0 0x800>,
>> 3050 <0 0x088eb600 0 0x200>;
>> 3051 #clock-cells = <0>;
>> 3052 #phy-cells = <0>;
>> 3053 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3054 clock-names = "pipe0";
>> 3055 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3592 }; 3056 };
3593 }; 3057 };
3594 3058
3595 dc_noc: interconnect@9160000 3059 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3060 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3061 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3062 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3063 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3064 };
3601 3065
3602 gem_noc: interconnect@9680000 3066 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3067 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3068 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3069 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3070 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3071 };
3608 3072
3609 usb_1: usb@a6f8800 { 3073 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3074 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3075 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3076 status = "disabled";
3613 #address-cells = <2>; 3077 #address-cells = <2>;
3614 #size-cells = <2>; 3078 #size-cells = <2>;
3615 ranges; 3079 ranges;
3616 dma-ranges; 3080 dma-ranges;
3617 3081
3618 clocks = <&gcc GCC_CF 3082 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3083 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3084 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US <<
3622 <&gcc GCC_US 3085 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 3086 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3623 <&gcc GCC_US 3087 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no !! 3088 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3625 "core", !! 3089 "sleep", "xo";
3626 "iface" <<
3627 "sleep" <<
3628 "mock_u <<
3629 "xo"; <<
3630 3090
3631 assigned-clocks = <&g 3091 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3092 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3093 assigned-clock-rates = <19200000>, <200000000>;
3634 3094
3635 interrupts-extended = !! 3095 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3096 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3097 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
3638 !! 3098 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
3639 !! 3099 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3100 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3101
3646 power-domains = <&gcc 3102 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3103
3648 resets = <&gcc GCC_US 3104 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3105
3650 interconnects = <&agg !! 3106 usb_1_dwc3: dwc3@a600000 {
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 <<
3655 compatible = 3107 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3108 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3109 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3110 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3111 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3112 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3113 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3114 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3115 };
3684 }; 3116 };
3685 3117
3686 usb_2: usb@a8f8800 { 3118 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3119 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3120 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3121 status = "disabled";
3690 #address-cells = <2>; 3122 #address-cells = <2>;
3691 #size-cells = <2>; 3123 #size-cells = <2>;
3692 ranges; 3124 ranges;
3693 dma-ranges; 3125 dma-ranges;
3694 3126
3695 clocks = <&gcc GCC_CF 3127 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3128 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3129 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US <<
3699 <&gcc GCC_US 3130 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 3131 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3700 <&gcc GCC_US 3132 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no !! 3133 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3702 "core", !! 3134 "sleep", "xo";
3703 "iface" <<
3704 "sleep" <<
3705 "mock_u <<
3706 "xo"; <<
3707 3135
3708 assigned-clocks = <&g 3136 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3137 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3138 assigned-clock-rates = <19200000>, <200000000>;
3711 3139
3712 interrupts-extended = !! 3140 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3141 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3142 <GIC_SPI 490 IRQ_TYPE_EDGE_BOTH>,
3715 !! 3143 <GIC_SPI 491 IRQ_TYPE_EDGE_BOTH>;
3716 !! 3144 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3145 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3146
3723 power-domains = <&gcc 3147 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3148
3725 resets = <&gcc GCC_US 3149 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3150
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3151 usb_2_dwc3: usb@a800000 {
3732 compatible = 3152 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3153 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3154 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3155 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3156 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3157 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3158 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3159 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3160 };
3741 }; 3161 };
3742 3162
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3163 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3164 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3165 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3166 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3167 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3168 };
3762 3169
3763 camcc: clock-controller@ad000 !! 3170 aoss_qmp: power-controller@c300000 {
3764 compatible = "qcom,sm !! 3171 compatible = "qcom,sm8150-aoss-qmp";
3765 reg = <0 0x0ad00000 0 !! 3172 reg = <0x0 0x0c300000 0x0 0x100000>;
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 <<
4150 compatible = "qcom,sm <<
4151 reg = <0 0x0b220000 0 <<
4152 qcom,pdc-ranges = <0 <<
4153 <12 <<
4154 #interrupt-cells = <2 <<
4155 interrupt-parent = <& <<
4156 interrupt-controller; <<
4157 }; <<
4158 <<
4159 aoss_qmp: power-management@c3 <<
4160 compatible = "qcom,sm <<
4161 reg = <0x0 0x0c300000 <<
4162 interrupts = <GIC_SPI 3173 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3174 mboxes = <&apss_shared 0>;
4164 3175
4165 #clock-cells = <0>; 3176 #clock-cells = <0>;
4166 }; !! 3177 #power-domain-cells = <1>;
4167 <<
4168 sram@c3f0000 { <<
4169 compatible = "qcom,rp <<
4170 reg = <0 0x0c3f0000 0 <<
4171 }; 3178 };
4172 3179
4173 tsens0: thermal-sensor@c26300 3180 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3181 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3182 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3183 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3184 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3185 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3186 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3187 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3188 #thermal-sensor-cells = <1>;
4182 }; 3189 };
4183 3190
4184 tsens1: thermal-sensor@c26500 3191 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3192 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3193 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3194 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3195 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3196 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3197 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3198 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3199 #thermal-sensor-cells = <1>;
4193 }; 3200 };
4194 3201
4195 spmi_bus: spmi@c440000 { 3202 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3203 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3204 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3205 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3206 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3207 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3208 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3209 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3210 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3211 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3212 qcom,ee = <0>;
4206 qcom,channel = <0>; 3213 qcom,channel = <0>;
4207 #address-cells = <2>; 3214 #address-cells = <2>;
4208 #size-cells = <0>; 3215 #size-cells = <0>;
4209 interrupt-controller; 3216 interrupt-controller;
4210 #interrupt-cells = <4 3217 #interrupt-cells = <4>;
>> 3218 cell-index = <0>;
4211 }; 3219 };
4212 3220
4213 apps_smmu: iommu@15000000 { 3221 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3222 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3223 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3224 #iommu-cells = <2>;
4217 #global-interrupts = 3225 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3226 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3227 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3228 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3229 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3230 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3231 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3232 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3233 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3234 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3235 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3236 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3237 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3238 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3239 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3240 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3241 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3242 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3243 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3244 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3245 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3246 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3247 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3248 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3249 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3250 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3251 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3252 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3253 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3254 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3255 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3256 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3257 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3258 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3259 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3260 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3261 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3262 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3263 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3264 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3265 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3266 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3267 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 3268 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 3269 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 3270 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 3271 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 3272 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 3273 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 3274 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 3275 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 3276 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 3277 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 3278 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 3279 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 3280 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 3281 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 3282 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 3283 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 3284 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 3285 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 3286 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 3287 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 3288 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 3289 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 3290 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 3291 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 3292 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 3293 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 3294 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 3295 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 3296 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 3297 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 3298 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 3299 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 3300 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 3301 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 3302 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 3303 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 3304 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 3305 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 3306 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 3307 };
4300 3308
4301 remoteproc_adsp: remoteproc@1 3309 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 3310 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 3311 reg = <0x0 0x17300000 0x0 0x4040>;
4304 3312
4305 interrupts-extended = 3313 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 3314 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 3315 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 3316 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 3317 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 3318 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 3319 "handover", "stop-ack";
4312 3320
4313 clocks = <&rpmhcc RPM 3321 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 3322 clock-names = "xo";
4315 3323
4316 power-domains = <&rpm !! 3324 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
>> 3325 <&rpmhpd 7>;
>> 3326 power-domain-names = "load_state", "cx";
4317 3327
4318 memory-region = <&ads 3328 memory-region = <&adsp_mem>;
4319 3329
4320 qcom,qmp = <&aoss_qmp <<
4321 <<
4322 qcom,smem-states = <& 3330 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 3331 qcom,smem-state-names = "stop";
4324 3332
4325 status = "disabled"; 3333 status = "disabled";
4326 3334
4327 glink-edge { 3335 glink-edge {
4328 interrupts = 3336 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 3337 label = "lpass";
4330 qcom,remote-p 3338 qcom,remote-pid = <2>;
4331 mboxes = <&ap 3339 mboxes = <&apss_shared 8>;
4332 <<
4333 fastrpc { <<
4334 compa <<
4335 qcom, <<
4336 label <<
4337 qcom, <<
4338 #addr <<
4339 #size <<
4340 <<
4341 compu <<
4342 <<
4343 <<
4344 <<
4345 }; <<
4346 <<
4347 compu <<
4348 <<
4349 <<
4350 <<
4351 }; <<
4352 <<
4353 compu <<
4354 <<
4355 <<
4356 <<
4357 }; <<
4358 }; <<
4359 }; 3340 };
4360 }; 3341 };
4361 3342
4362 intc: interrupt-controller@17 3343 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 3344 compatible = "arm,gic-v3";
4364 interrupt-controller; 3345 interrupt-controller;
4365 #interrupt-cells = <3 3346 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 3347 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 3348 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 3349 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 3350 };
4370 3351
4371 apss_shared: mailbox@17c00000 3352 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 3353 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 3354 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 3355 #mbox-cells = <1>;
4376 }; 3356 };
4377 3357
4378 watchdog@17c10000 { 3358 watchdog@17c10000 {
4379 compatible = "qcom,ap 3359 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 3360 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 3361 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI 3362 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4383 }; 3363 };
4384 3364
4385 timer@17c20000 { 3365 timer@17c20000 {
4386 #address-cells = <1>; !! 3366 #address-cells = <2>;
4387 #size-cells = <1>; !! 3367 #size-cells = <2>;
4388 ranges = <0 0 0 0x200 !! 3368 ranges;
4389 compatible = "arm,arm 3369 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 3370 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 3371 clock-frequency = <19200000>;
4392 3372
4393 frame@17c21000 { !! 3373 frame@17c21000{
4394 frame-number 3374 frame-number = <0>;
4395 interrupts = 3375 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 3376 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 !! 3377 reg = <0x0 0x17c21000 0x0 0x1000>,
4398 <0x17c2 !! 3378 <0x0 0x17c22000 0x0 0x1000>;
4399 }; 3379 };
4400 3380
4401 frame@17c23000 { 3381 frame@17c23000 {
4402 frame-number 3382 frame-number = <1>;
4403 interrupts = 3383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 !! 3384 reg = <0x0 0x17c23000 0x0 0x1000>;
4405 status = "dis 3385 status = "disabled";
4406 }; 3386 };
4407 3387
4408 frame@17c25000 { 3388 frame@17c25000 {
4409 frame-number 3389 frame-number = <2>;
4410 interrupts = 3390 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 !! 3391 reg = <0x0 0x17c25000 0x0 0x1000>;
4412 status = "dis 3392 status = "disabled";
4413 }; 3393 };
4414 3394
4415 frame@17c27000 { 3395 frame@17c27000 {
4416 frame-number 3396 frame-number = <3>;
4417 interrupts = 3397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 !! 3398 reg = <0x0 0x17c26000 0x0 0x1000>;
4419 status = "dis 3399 status = "disabled";
4420 }; 3400 };
4421 3401
4422 frame@17c29000 { 3402 frame@17c29000 {
4423 frame-number 3403 frame-number = <4>;
4424 interrupts = 3404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 !! 3405 reg = <0x0 0x17c29000 0x0 0x1000>;
4426 status = "dis 3406 status = "disabled";
4427 }; 3407 };
4428 3408
4429 frame@17c2b000 { 3409 frame@17c2b000 {
4430 frame-number 3410 frame-number = <5>;
4431 interrupts = 3411 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 !! 3412 reg = <0x0 0x17c2b000 0x0 0x1000>;
4433 status = "dis 3413 status = "disabled";
4434 }; 3414 };
4435 3415
4436 frame@17c2d000 { 3416 frame@17c2d000 {
4437 frame-number 3417 frame-number = <6>;
4438 interrupts = 3418 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 !! 3419 reg = <0x0 0x17c2d000 0x0 0x1000>;
4440 status = "dis 3420 status = "disabled";
4441 }; 3421 };
4442 }; 3422 };
4443 3423
4444 apps_rsc: rsc@18200000 { 3424 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 3425 label = "apps_rsc";
4446 compatible = "qcom,rp 3426 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 3427 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 3428 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 3429 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 3430 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 3431 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 3432 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 3433 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 3434 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 3435 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 3436 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 3437 <SLEEP_TCS 3>,
4458 <WA 3438 <WAKE_TCS 3>,
4459 <CO 3439 <CONTROL_TCS 1>;
4460 power-domains = <&CLU <<
4461 3440
4462 rpmhcc: clock-control 3441 rpmhcc: clock-controller {
4463 compatible = 3442 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 3443 #clock-cells = <1>;
4465 clock-names = 3444 clock-names = "xo";
4466 clocks = <&xo 3445 clocks = <&xo_board>;
4467 }; 3446 };
4468 3447
4469 rpmhpd: power-control 3448 rpmhpd: power-controller {
4470 compatible = 3449 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 3450 #power-domain-cells = <1>;
4472 operating-poi 3451 operating-points-v2 = <&rpmhpd_opp_table>;
4473 3452
4474 rpmhpd_opp_ta 3453 rpmhpd_opp_table: opp-table {
4475 compa 3454 compatible = "operating-points-v2";
4476 3455
4477 rpmhp 3456 rpmhpd_opp_ret: opp1 {
4478 3457 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 3458 };
4480 3459
4481 rpmhp 3460 rpmhpd_opp_min_svs: opp2 {
4482 3461 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 3462 };
4484 3463
4485 rpmhp 3464 rpmhpd_opp_low_svs: opp3 {
4486 3465 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 3466 };
4488 3467
4489 rpmhp 3468 rpmhpd_opp_svs: opp4 {
4490 3469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 3470 };
4492 3471
4493 rpmhp 3472 rpmhpd_opp_svs_l1: opp5 {
4494 3473 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 3474 };
4496 3475
4497 rpmhp 3476 rpmhpd_opp_svs_l2: opp6 {
4498 3477 opp-level = <224>;
4499 }; 3478 };
4500 3479
4501 rpmhp 3480 rpmhpd_opp_nom: opp7 {
4502 3481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 3482 };
4504 3483
4505 rpmhp 3484 rpmhpd_opp_nom_l1: opp8 {
4506 3485 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 3486 };
4508 3487
4509 rpmhp 3488 rpmhpd_opp_nom_l2: opp9 {
4510 3489 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 3490 };
4512 3491
4513 rpmhp 3492 rpmhpd_opp_turbo: opp10 {
4514 3493 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 3494 };
4516 3495
4517 rpmhp 3496 rpmhpd_opp_turbo_l1: opp11 {
4518 3497 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 3498 };
4520 }; 3499 };
4521 }; 3500 };
4522 3501
4523 apps_bcm_voter: bcm-v !! 3502 apps_bcm_voter: bcm_voter {
4524 compatible = 3503 compatible = "qcom,bcm-voter";
4525 }; 3504 };
4526 }; 3505 };
4527 3506
4528 osm_l3: interconnect@18321000 3507 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 3508 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 3509 reg = <0 0x18321000 0 0x1400>;
4531 3510
4532 clocks = <&rpmhcc RPM 3511 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 3512 clock-names = "xo", "alternate";
4534 3513
4535 #interconnect-cells = 3514 #interconnect-cells = <1>;
4536 }; 3515 };
4537 3516
4538 cpufreq_hw: cpufreq@18323000 3517 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 3518 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 3519 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 3520 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 3521 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 3522 "freq-domain2";
4544 3523
4545 clocks = <&rpmhcc RPM 3524 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 3525 clock-names = "xo", "alternate";
4547 3526
4548 #freq-domain-cells = 3527 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; <<
4551 <<
4552 lmh_cluster1: lmh@18350800 { <<
4553 compatible = "qcom,sm <<
4554 reg = <0 0x18350800 0 <<
4555 interrupts = <GIC_SPI <<
4556 cpus = <&CPU4>; <<
4557 qcom,lmh-temp-arm-mil <<
4558 qcom,lmh-temp-low-mil <<
4559 qcom,lmh-temp-high-mi <<
4560 interrupt-controller; <<
4561 #interrupt-cells = <1 <<
4562 }; <<
4563 <<
4564 lmh_cluster0: lmh@18358800 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x18358800 0 <<
4567 interrupts = <GIC_SPI <<
4568 cpus = <&CPU0>; <<
4569 qcom,lmh-temp-arm-mil <<
4570 qcom,lmh-temp-low-mil <<
4571 qcom,lmh-temp-high-mi <<
4572 interrupt-controller; <<
4573 #interrupt-cells = <1 <<
4574 }; 3528 };
4575 3529
4576 wifi: wifi@18800000 { 3530 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 3531 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 3532 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 3533 reg-names = "membase";
4580 memory-region = <&wla 3534 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 3535 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 3536 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 3537 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 3538 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 3539 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 3540 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 3541 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 3542 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 3543 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 3544 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 3545 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 3546 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 3547 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 3548 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 3549 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 3550 status = "disabled";
4597 }; 3551 };
4598 }; 3552 };
4599 3553
4600 timer { 3554 timer {
4601 compatible = "arm,armv8-timer 3555 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 3556 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 3557 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 3558 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 3559 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 3560 };
4607 3561
4608 thermal-zones { 3562 thermal-zones {
4609 cpu0-thermal { 3563 cpu0-thermal {
4610 polling-delay-passive 3564 polling-delay-passive = <250>;
>> 3565 polling-delay = <1000>;
4611 3566
4612 thermal-sensors = <&t 3567 thermal-sensors = <&tsens0 1>;
4613 3568
4614 trips { 3569 trips {
4615 cpu0_alert0: 3570 cpu0_alert0: trip-point0 {
4616 tempe 3571 temperature = <90000>;
4617 hyste 3572 hysteresis = <2000>;
4618 type 3573 type = "passive";
4619 }; 3574 };
4620 3575
4621 cpu0_alert1: 3576 cpu0_alert1: trip-point1 {
4622 tempe 3577 temperature = <95000>;
4623 hyste 3578 hysteresis = <2000>;
4624 type 3579 type = "passive";
4625 }; 3580 };
4626 3581
4627 cpu0_crit: cp !! 3582 cpu0_crit: cpu_crit {
4628 tempe 3583 temperature = <110000>;
4629 hyste 3584 hysteresis = <1000>;
4630 type 3585 type = "critical";
4631 }; 3586 };
4632 }; 3587 };
4633 3588
4634 cooling-maps { 3589 cooling-maps {
4635 map0 { 3590 map0 {
4636 trip 3591 trip = <&cpu0_alert0>;
4637 cooli 3592 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 3593 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 3594 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 3595 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 3596 };
4642 map1 { 3597 map1 {
4643 trip 3598 trip = <&cpu0_alert1>;
4644 cooli 3599 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 3600 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 3601 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 3602 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 3603 };
4649 }; 3604 };
4650 }; 3605 };
4651 3606
4652 cpu1-thermal { 3607 cpu1-thermal {
4653 polling-delay-passive 3608 polling-delay-passive = <250>;
>> 3609 polling-delay = <1000>;
4654 3610
4655 thermal-sensors = <&t 3611 thermal-sensors = <&tsens0 2>;
4656 3612
4657 trips { 3613 trips {
4658 cpu1_alert0: 3614 cpu1_alert0: trip-point0 {
4659 tempe 3615 temperature = <90000>;
4660 hyste 3616 hysteresis = <2000>;
4661 type 3617 type = "passive";
4662 }; 3618 };
4663 3619
4664 cpu1_alert1: 3620 cpu1_alert1: trip-point1 {
4665 tempe 3621 temperature = <95000>;
4666 hyste 3622 hysteresis = <2000>;
4667 type 3623 type = "passive";
4668 }; 3624 };
4669 3625
4670 cpu1_crit: cp !! 3626 cpu1_crit: cpu_crit {
4671 tempe 3627 temperature = <110000>;
4672 hyste 3628 hysteresis = <1000>;
4673 type 3629 type = "critical";
4674 }; 3630 };
4675 }; 3631 };
4676 3632
4677 cooling-maps { 3633 cooling-maps {
4678 map0 { 3634 map0 {
4679 trip 3635 trip = <&cpu1_alert0>;
4680 cooli 3636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 3637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 3638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 3639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 3640 };
4685 map1 { 3641 map1 {
4686 trip 3642 trip = <&cpu1_alert1>;
4687 cooli 3643 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 3644 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 3645 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 3646 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 3647 };
4692 }; 3648 };
4693 }; 3649 };
4694 3650
4695 cpu2-thermal { 3651 cpu2-thermal {
4696 polling-delay-passive 3652 polling-delay-passive = <250>;
>> 3653 polling-delay = <1000>;
4697 3654
4698 thermal-sensors = <&t 3655 thermal-sensors = <&tsens0 3>;
4699 3656
4700 trips { 3657 trips {
4701 cpu2_alert0: 3658 cpu2_alert0: trip-point0 {
4702 tempe 3659 temperature = <90000>;
4703 hyste 3660 hysteresis = <2000>;
4704 type 3661 type = "passive";
4705 }; 3662 };
4706 3663
4707 cpu2_alert1: 3664 cpu2_alert1: trip-point1 {
4708 tempe 3665 temperature = <95000>;
4709 hyste 3666 hysteresis = <2000>;
4710 type 3667 type = "passive";
4711 }; 3668 };
4712 3669
4713 cpu2_crit: cp !! 3670 cpu2_crit: cpu_crit {
4714 tempe 3671 temperature = <110000>;
4715 hyste 3672 hysteresis = <1000>;
4716 type 3673 type = "critical";
4717 }; 3674 };
4718 }; 3675 };
4719 3676
4720 cooling-maps { 3677 cooling-maps {
4721 map0 { 3678 map0 {
4722 trip 3679 trip = <&cpu2_alert0>;
4723 cooli 3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 3681 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 3682 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 3683 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 3684 };
4728 map1 { 3685 map1 {
4729 trip 3686 trip = <&cpu2_alert1>;
4730 cooli 3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 3688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 3689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 3690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 3691 };
4735 }; 3692 };
4736 }; 3693 };
4737 3694
4738 cpu3-thermal { 3695 cpu3-thermal {
4739 polling-delay-passive 3696 polling-delay-passive = <250>;
>> 3697 polling-delay = <1000>;
4740 3698
4741 thermal-sensors = <&t 3699 thermal-sensors = <&tsens0 4>;
4742 3700
4743 trips { 3701 trips {
4744 cpu3_alert0: 3702 cpu3_alert0: trip-point0 {
4745 tempe 3703 temperature = <90000>;
4746 hyste 3704 hysteresis = <2000>;
4747 type 3705 type = "passive";
4748 }; 3706 };
4749 3707
4750 cpu3_alert1: 3708 cpu3_alert1: trip-point1 {
4751 tempe 3709 temperature = <95000>;
4752 hyste 3710 hysteresis = <2000>;
4753 type 3711 type = "passive";
4754 }; 3712 };
4755 3713
4756 cpu3_crit: cp !! 3714 cpu3_crit: cpu_crit {
4757 tempe 3715 temperature = <110000>;
4758 hyste 3716 hysteresis = <1000>;
4759 type 3717 type = "critical";
4760 }; 3718 };
4761 }; 3719 };
4762 3720
4763 cooling-maps { 3721 cooling-maps {
4764 map0 { 3722 map0 {
4765 trip 3723 trip = <&cpu3_alert0>;
4766 cooli 3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 3728 };
4771 map1 { 3729 map1 {
4772 trip 3730 trip = <&cpu3_alert1>;
4773 cooli 3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 3732 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 3733 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 3734 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 3735 };
4778 }; 3736 };
4779 }; 3737 };
4780 3738
4781 cpu4-top-thermal { 3739 cpu4-top-thermal {
4782 polling-delay-passive 3740 polling-delay-passive = <250>;
>> 3741 polling-delay = <1000>;
4783 3742
4784 thermal-sensors = <&t 3743 thermal-sensors = <&tsens0 7>;
4785 3744
4786 trips { 3745 trips {
4787 cpu4_top_aler 3746 cpu4_top_alert0: trip-point0 {
4788 tempe 3747 temperature = <90000>;
4789 hyste 3748 hysteresis = <2000>;
4790 type 3749 type = "passive";
4791 }; 3750 };
4792 3751
4793 cpu4_top_aler 3752 cpu4_top_alert1: trip-point1 {
4794 tempe 3753 temperature = <95000>;
4795 hyste 3754 hysteresis = <2000>;
4796 type 3755 type = "passive";
4797 }; 3756 };
4798 3757
4799 cpu4_top_crit !! 3758 cpu4_top_crit: cpu_crit {
4800 tempe 3759 temperature = <110000>;
4801 hyste 3760 hysteresis = <1000>;
4802 type 3761 type = "critical";
4803 }; 3762 };
4804 }; 3763 };
4805 3764
4806 cooling-maps { 3765 cooling-maps {
4807 map0 { 3766 map0 {
4808 trip 3767 trip = <&cpu4_top_alert0>;
4809 cooli 3768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 3769 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 3770 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 3771 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 3772 };
4814 map1 { 3773 map1 {
4815 trip 3774 trip = <&cpu4_top_alert1>;
4816 cooli 3775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 3776 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 3777 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 3778 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 3779 };
4821 }; 3780 };
4822 }; 3781 };
4823 3782
4824 cpu5-top-thermal { 3783 cpu5-top-thermal {
4825 polling-delay-passive 3784 polling-delay-passive = <250>;
>> 3785 polling-delay = <1000>;
4826 3786
4827 thermal-sensors = <&t 3787 thermal-sensors = <&tsens0 8>;
4828 3788
4829 trips { 3789 trips {
4830 cpu5_top_aler 3790 cpu5_top_alert0: trip-point0 {
4831 tempe 3791 temperature = <90000>;
4832 hyste 3792 hysteresis = <2000>;
4833 type 3793 type = "passive";
4834 }; 3794 };
4835 3795
4836 cpu5_top_aler 3796 cpu5_top_alert1: trip-point1 {
4837 tempe 3797 temperature = <95000>;
4838 hyste 3798 hysteresis = <2000>;
4839 type 3799 type = "passive";
4840 }; 3800 };
4841 3801
4842 cpu5_top_crit !! 3802 cpu5_top_crit: cpu_crit {
4843 tempe 3803 temperature = <110000>;
4844 hyste 3804 hysteresis = <1000>;
4845 type 3805 type = "critical";
4846 }; 3806 };
4847 }; 3807 };
4848 3808
4849 cooling-maps { 3809 cooling-maps {
4850 map0 { 3810 map0 {
4851 trip 3811 trip = <&cpu5_top_alert0>;
4852 cooli 3812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 3813 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 3814 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 3815 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 3816 };
4857 map1 { 3817 map1 {
4858 trip 3818 trip = <&cpu5_top_alert1>;
4859 cooli 3819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 3820 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 3821 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 3822 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 3823 };
4864 }; 3824 };
4865 }; 3825 };
4866 3826
4867 cpu6-top-thermal { 3827 cpu6-top-thermal {
4868 polling-delay-passive 3828 polling-delay-passive = <250>;
>> 3829 polling-delay = <1000>;
4869 3830
4870 thermal-sensors = <&t 3831 thermal-sensors = <&tsens0 9>;
4871 3832
4872 trips { 3833 trips {
4873 cpu6_top_aler 3834 cpu6_top_alert0: trip-point0 {
4874 tempe 3835 temperature = <90000>;
4875 hyste 3836 hysteresis = <2000>;
4876 type 3837 type = "passive";
4877 }; 3838 };
4878 3839
4879 cpu6_top_aler 3840 cpu6_top_alert1: trip-point1 {
4880 tempe 3841 temperature = <95000>;
4881 hyste 3842 hysteresis = <2000>;
4882 type 3843 type = "passive";
4883 }; 3844 };
4884 3845
4885 cpu6_top_crit !! 3846 cpu6_top_crit: cpu_crit {
4886 tempe 3847 temperature = <110000>;
4887 hyste 3848 hysteresis = <1000>;
4888 type 3849 type = "critical";
4889 }; 3850 };
4890 }; 3851 };
4891 3852
4892 cooling-maps { 3853 cooling-maps {
4893 map0 { 3854 map0 {
4894 trip 3855 trip = <&cpu6_top_alert0>;
4895 cooli 3856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 3857 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 3858 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 3859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 3860 };
4900 map1 { 3861 map1 {
4901 trip 3862 trip = <&cpu6_top_alert1>;
4902 cooli 3863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 3864 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 3865 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 3866 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 3867 };
4907 }; 3868 };
4908 }; 3869 };
4909 3870
4910 cpu7-top-thermal { 3871 cpu7-top-thermal {
4911 polling-delay-passive 3872 polling-delay-passive = <250>;
>> 3873 polling-delay = <1000>;
4912 3874
4913 thermal-sensors = <&t 3875 thermal-sensors = <&tsens0 10>;
4914 3876
4915 trips { 3877 trips {
4916 cpu7_top_aler 3878 cpu7_top_alert0: trip-point0 {
4917 tempe 3879 temperature = <90000>;
4918 hyste 3880 hysteresis = <2000>;
4919 type 3881 type = "passive";
4920 }; 3882 };
4921 3883
4922 cpu7_top_aler 3884 cpu7_top_alert1: trip-point1 {
4923 tempe 3885 temperature = <95000>;
4924 hyste 3886 hysteresis = <2000>;
4925 type 3887 type = "passive";
4926 }; 3888 };
4927 3889
4928 cpu7_top_crit !! 3890 cpu7_top_crit: cpu_crit {
4929 tempe 3891 temperature = <110000>;
4930 hyste 3892 hysteresis = <1000>;
4931 type 3893 type = "critical";
4932 }; 3894 };
4933 }; 3895 };
4934 3896
4935 cooling-maps { 3897 cooling-maps {
4936 map0 { 3898 map0 {
4937 trip 3899 trip = <&cpu7_top_alert0>;
4938 cooli 3900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 3901 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 3902 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 3903 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 3904 };
4943 map1 { 3905 map1 {
4944 trip 3906 trip = <&cpu7_top_alert1>;
4945 cooli 3907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 3908 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 3909 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 3910 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 3911 };
4950 }; 3912 };
4951 }; 3913 };
4952 3914
4953 cpu4-bottom-thermal { 3915 cpu4-bottom-thermal {
4954 polling-delay-passive 3916 polling-delay-passive = <250>;
>> 3917 polling-delay = <1000>;
4955 3918
4956 thermal-sensors = <&t 3919 thermal-sensors = <&tsens0 11>;
4957 3920
4958 trips { 3921 trips {
4959 cpu4_bottom_a 3922 cpu4_bottom_alert0: trip-point0 {
4960 tempe 3923 temperature = <90000>;
4961 hyste 3924 hysteresis = <2000>;
4962 type 3925 type = "passive";
4963 }; 3926 };
4964 3927
4965 cpu4_bottom_a 3928 cpu4_bottom_alert1: trip-point1 {
4966 tempe 3929 temperature = <95000>;
4967 hyste 3930 hysteresis = <2000>;
4968 type 3931 type = "passive";
4969 }; 3932 };
4970 3933
4971 cpu4_bottom_c !! 3934 cpu4_bottom_crit: cpu_crit {
4972 tempe 3935 temperature = <110000>;
4973 hyste 3936 hysteresis = <1000>;
4974 type 3937 type = "critical";
4975 }; 3938 };
4976 }; 3939 };
4977 3940
4978 cooling-maps { 3941 cooling-maps {
4979 map0 { 3942 map0 {
4980 trip 3943 trip = <&cpu4_bottom_alert0>;
4981 cooli 3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 3945 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 3946 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 3947 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 3948 };
4986 map1 { 3949 map1 {
4987 trip 3950 trip = <&cpu4_bottom_alert1>;
4988 cooli 3951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 3952 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 3953 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 3954 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 3955 };
4993 }; 3956 };
4994 }; 3957 };
4995 3958
4996 cpu5-bottom-thermal { 3959 cpu5-bottom-thermal {
4997 polling-delay-passive 3960 polling-delay-passive = <250>;
>> 3961 polling-delay = <1000>;
4998 3962
4999 thermal-sensors = <&t 3963 thermal-sensors = <&tsens0 12>;
5000 3964
5001 trips { 3965 trips {
5002 cpu5_bottom_a 3966 cpu5_bottom_alert0: trip-point0 {
5003 tempe 3967 temperature = <90000>;
5004 hyste 3968 hysteresis = <2000>;
5005 type 3969 type = "passive";
5006 }; 3970 };
5007 3971
5008 cpu5_bottom_a 3972 cpu5_bottom_alert1: trip-point1 {
5009 tempe 3973 temperature = <95000>;
5010 hyste 3974 hysteresis = <2000>;
5011 type 3975 type = "passive";
5012 }; 3976 };
5013 3977
5014 cpu5_bottom_c !! 3978 cpu5_bottom_crit: cpu_crit {
5015 tempe 3979 temperature = <110000>;
5016 hyste 3980 hysteresis = <1000>;
5017 type 3981 type = "critical";
5018 }; 3982 };
5019 }; 3983 };
5020 3984
5021 cooling-maps { 3985 cooling-maps {
5022 map0 { 3986 map0 {
5023 trip 3987 trip = <&cpu5_bottom_alert0>;
5024 cooli 3988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 3989 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 3990 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 3991 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 3992 };
5029 map1 { 3993 map1 {
5030 trip 3994 trip = <&cpu5_bottom_alert1>;
5031 cooli 3995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 3996 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 3997 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 3998 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 3999 };
5036 }; 4000 };
5037 }; 4001 };
5038 4002
5039 cpu6-bottom-thermal { 4003 cpu6-bottom-thermal {
5040 polling-delay-passive 4004 polling-delay-passive = <250>;
>> 4005 polling-delay = <1000>;
5041 4006
5042 thermal-sensors = <&t 4007 thermal-sensors = <&tsens0 13>;
5043 4008
5044 trips { 4009 trips {
5045 cpu6_bottom_a 4010 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4011 temperature = <90000>;
5047 hyste 4012 hysteresis = <2000>;
5048 type 4013 type = "passive";
5049 }; 4014 };
5050 4015
5051 cpu6_bottom_a 4016 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4017 temperature = <95000>;
5053 hyste 4018 hysteresis = <2000>;
5054 type 4019 type = "passive";
5055 }; 4020 };
5056 4021
5057 cpu6_bottom_c !! 4022 cpu6_bottom_crit: cpu_crit {
5058 tempe 4023 temperature = <110000>;
5059 hyste 4024 hysteresis = <1000>;
5060 type 4025 type = "critical";
5061 }; 4026 };
5062 }; 4027 };
5063 4028
5064 cooling-maps { 4029 cooling-maps {
5065 map0 { 4030 map0 {
5066 trip 4031 trip = <&cpu6_bottom_alert0>;
5067 cooli 4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4033 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4034 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4035 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4036 };
5072 map1 { 4037 map1 {
5073 trip 4038 trip = <&cpu6_bottom_alert1>;
5074 cooli 4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4040 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4041 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4042 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4043 };
5079 }; 4044 };
5080 }; 4045 };
5081 4046
5082 cpu7-bottom-thermal { 4047 cpu7-bottom-thermal {
5083 polling-delay-passive 4048 polling-delay-passive = <250>;
>> 4049 polling-delay = <1000>;
5084 4050
5085 thermal-sensors = <&t 4051 thermal-sensors = <&tsens0 14>;
5086 4052
5087 trips { 4053 trips {
5088 cpu7_bottom_a 4054 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4055 temperature = <90000>;
5090 hyste 4056 hysteresis = <2000>;
5091 type 4057 type = "passive";
5092 }; 4058 };
5093 4059
5094 cpu7_bottom_a 4060 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4061 temperature = <95000>;
5096 hyste 4062 hysteresis = <2000>;
5097 type 4063 type = "passive";
5098 }; 4064 };
5099 4065
5100 cpu7_bottom_c !! 4066 cpu7_bottom_crit: cpu_crit {
5101 tempe 4067 temperature = <110000>;
5102 hyste 4068 hysteresis = <1000>;
5103 type 4069 type = "critical";
5104 }; 4070 };
5105 }; 4071 };
5106 4072
5107 cooling-maps { 4073 cooling-maps {
5108 map0 { 4074 map0 {
5109 trip 4075 trip = <&cpu7_bottom_alert0>;
5110 cooli 4076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4077 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4078 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4079 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4080 };
5115 map1 { 4081 map1 {
5116 trip 4082 trip = <&cpu7_bottom_alert1>;
5117 cooli 4083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4084 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4085 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4086 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4087 };
5122 }; 4088 };
5123 }; 4089 };
5124 4090
5125 aoss0-thermal { 4091 aoss0-thermal {
5126 polling-delay-passive 4092 polling-delay-passive = <250>;
>> 4093 polling-delay = <1000>;
5127 4094
5128 thermal-sensors = <&t 4095 thermal-sensors = <&tsens0 0>;
5129 4096
5130 trips { 4097 trips {
5131 aoss0_alert0: 4098 aoss0_alert0: trip-point0 {
5132 tempe 4099 temperature = <90000>;
5133 hyste 4100 hysteresis = <2000>;
5134 type 4101 type = "hot";
5135 }; 4102 };
5136 }; 4103 };
5137 }; 4104 };
5138 4105
5139 cluster0-thermal { 4106 cluster0-thermal {
5140 polling-delay-passive 4107 polling-delay-passive = <250>;
>> 4108 polling-delay = <1000>;
5141 4109
5142 thermal-sensors = <&t 4110 thermal-sensors = <&tsens0 5>;
5143 4111
5144 trips { 4112 trips {
5145 cluster0_aler 4113 cluster0_alert0: trip-point0 {
5146 tempe 4114 temperature = <90000>;
5147 hyste 4115 hysteresis = <2000>;
5148 type 4116 type = "hot";
5149 }; 4117 };
5150 cluster0_crit !! 4118 cluster0_crit: cluster0_crit {
5151 tempe 4119 temperature = <110000>;
5152 hyste 4120 hysteresis = <2000>;
5153 type 4121 type = "critical";
5154 }; 4122 };
5155 }; 4123 };
5156 }; 4124 };
5157 4125
5158 cluster1-thermal { 4126 cluster1-thermal {
5159 polling-delay-passive 4127 polling-delay-passive = <250>;
>> 4128 polling-delay = <1000>;
5160 4129
5161 thermal-sensors = <&t 4130 thermal-sensors = <&tsens0 6>;
5162 4131
5163 trips { 4132 trips {
5164 cluster1_aler 4133 cluster1_alert0: trip-point0 {
5165 tempe 4134 temperature = <90000>;
5166 hyste 4135 hysteresis = <2000>;
5167 type 4136 type = "hot";
5168 }; 4137 };
5169 cluster1_crit !! 4138 cluster1_crit: cluster1_crit {
5170 tempe 4139 temperature = <110000>;
5171 hyste 4140 hysteresis = <2000>;
5172 type 4141 type = "critical";
5173 }; 4142 };
5174 }; 4143 };
5175 }; 4144 };
5176 4145
5177 gpu-top-thermal { !! 4146 gpu-thermal-top {
5178 polling-delay-passive 4147 polling-delay-passive = <250>;
>> 4148 polling-delay = <1000>;
5179 4149
5180 thermal-sensors = <&t 4150 thermal-sensors = <&tsens0 15>;
5181 4151
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4152 trips {
5190 gpu_top_alert !! 4153 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4154 temperature = <90000>;
5198 hyste !! 4155 hysteresis = <2000>;
5199 type 4156 type = "hot";
5200 }; 4157 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4158 };
5208 }; 4159 };
5209 4160
5210 aoss1-thermal { 4161 aoss1-thermal {
5211 polling-delay-passive 4162 polling-delay-passive = <250>;
>> 4163 polling-delay = <1000>;
5212 4164
5213 thermal-sensors = <&t 4165 thermal-sensors = <&tsens1 0>;
5214 4166
5215 trips { 4167 trips {
5216 aoss1_alert0: 4168 aoss1_alert0: trip-point0 {
5217 tempe 4169 temperature = <90000>;
5218 hyste 4170 hysteresis = <2000>;
5219 type 4171 type = "hot";
5220 }; 4172 };
5221 }; 4173 };
5222 }; 4174 };
5223 4175
5224 wlan-thermal { 4176 wlan-thermal {
5225 polling-delay-passive 4177 polling-delay-passive = <250>;
>> 4178 polling-delay = <1000>;
5226 4179
5227 thermal-sensors = <&t 4180 thermal-sensors = <&tsens1 1>;
5228 4181
5229 trips { 4182 trips {
5230 wlan_alert0: 4183 wlan_alert0: trip-point0 {
5231 tempe 4184 temperature = <90000>;
5232 hyste 4185 hysteresis = <2000>;
5233 type 4186 type = "hot";
5234 }; 4187 };
5235 }; 4188 };
5236 }; 4189 };
5237 4190
5238 video-thermal { 4191 video-thermal {
5239 polling-delay-passive 4192 polling-delay-passive = <250>;
>> 4193 polling-delay = <1000>;
5240 4194
5241 thermal-sensors = <&t 4195 thermal-sensors = <&tsens1 2>;
5242 4196
5243 trips { 4197 trips {
5244 video_alert0: 4198 video_alert0: trip-point0 {
5245 tempe 4199 temperature = <90000>;
5246 hyste 4200 hysteresis = <2000>;
5247 type 4201 type = "hot";
5248 }; 4202 };
5249 }; 4203 };
5250 }; 4204 };
5251 4205
5252 mem-thermal { 4206 mem-thermal {
5253 polling-delay-passive 4207 polling-delay-passive = <250>;
>> 4208 polling-delay = <1000>;
5254 4209
5255 thermal-sensors = <&t 4210 thermal-sensors = <&tsens1 3>;
5256 4211
5257 trips { 4212 trips {
5258 mem_alert0: t 4213 mem_alert0: trip-point0 {
5259 tempe 4214 temperature = <90000>;
5260 hyste 4215 hysteresis = <2000>;
5261 type 4216 type = "hot";
5262 }; 4217 };
5263 }; 4218 };
5264 }; 4219 };
5265 4220
5266 q6-hvx-thermal { 4221 q6-hvx-thermal {
5267 polling-delay-passive 4222 polling-delay-passive = <250>;
>> 4223 polling-delay = <1000>;
5268 4224
5269 thermal-sensors = <&t 4225 thermal-sensors = <&tsens1 4>;
5270 4226
5271 trips { 4227 trips {
5272 q6_hvx_alert0 4228 q6_hvx_alert0: trip-point0 {
5273 tempe 4229 temperature = <90000>;
5274 hyste 4230 hysteresis = <2000>;
5275 type 4231 type = "hot";
5276 }; 4232 };
5277 }; 4233 };
5278 }; 4234 };
5279 4235
5280 camera-thermal { 4236 camera-thermal {
5281 polling-delay-passive 4237 polling-delay-passive = <250>;
>> 4238 polling-delay = <1000>;
5282 4239
5283 thermal-sensors = <&t 4240 thermal-sensors = <&tsens1 5>;
5284 4241
5285 trips { 4242 trips {
5286 camera_alert0 4243 camera_alert0: trip-point0 {
5287 tempe 4244 temperature = <90000>;
5288 hyste 4245 hysteresis = <2000>;
5289 type 4246 type = "hot";
5290 }; 4247 };
5291 }; 4248 };
5292 }; 4249 };
5293 4250
5294 compute-thermal { 4251 compute-thermal {
5295 polling-delay-passive 4252 polling-delay-passive = <250>;
>> 4253 polling-delay = <1000>;
5296 4254
5297 thermal-sensors = <&t 4255 thermal-sensors = <&tsens1 6>;
5298 4256
5299 trips { 4257 trips {
5300 compute_alert 4258 compute_alert0: trip-point0 {
5301 tempe 4259 temperature = <90000>;
5302 hyste 4260 hysteresis = <2000>;
5303 type 4261 type = "hot";
5304 }; 4262 };
5305 }; 4263 };
5306 }; 4264 };
5307 4265
5308 modem-thermal { 4266 modem-thermal {
5309 polling-delay-passive 4267 polling-delay-passive = <250>;
>> 4268 polling-delay = <1000>;
5310 4269
5311 thermal-sensors = <&t 4270 thermal-sensors = <&tsens1 7>;
5312 4271
5313 trips { 4272 trips {
5314 modem_alert0: 4273 modem_alert0: trip-point0 {
5315 tempe 4274 temperature = <90000>;
5316 hyste 4275 hysteresis = <2000>;
5317 type 4276 type = "hot";
5318 }; 4277 };
5319 }; 4278 };
5320 }; 4279 };
5321 4280
5322 npu-thermal { 4281 npu-thermal {
5323 polling-delay-passive 4282 polling-delay-passive = <250>;
>> 4283 polling-delay = <1000>;
5324 4284
5325 thermal-sensors = <&t 4285 thermal-sensors = <&tsens1 8>;
5326 4286
5327 trips { 4287 trips {
5328 npu_alert0: t 4288 npu_alert0: trip-point0 {
5329 tempe 4289 temperature = <90000>;
5330 hyste 4290 hysteresis = <2000>;
5331 type 4291 type = "hot";
5332 }; 4292 };
5333 }; 4293 };
5334 }; 4294 };
5335 4295
5336 modem-vec-thermal { 4296 modem-vec-thermal {
5337 polling-delay-passive 4297 polling-delay-passive = <250>;
>> 4298 polling-delay = <1000>;
5338 4299
5339 thermal-sensors = <&t 4300 thermal-sensors = <&tsens1 9>;
5340 4301
5341 trips { 4302 trips {
5342 modem_vec_ale 4303 modem_vec_alert0: trip-point0 {
5343 tempe 4304 temperature = <90000>;
5344 hyste 4305 hysteresis = <2000>;
5345 type 4306 type = "hot";
5346 }; 4307 };
5347 }; 4308 };
5348 }; 4309 };
5349 4310
5350 modem-scl-thermal { 4311 modem-scl-thermal {
5351 polling-delay-passive 4312 polling-delay-passive = <250>;
>> 4313 polling-delay = <1000>;
5352 4314
5353 thermal-sensors = <&t 4315 thermal-sensors = <&tsens1 10>;
5354 4316
5355 trips { 4317 trips {
5356 modem_scl_ale 4318 modem_scl_alert0: trip-point0 {
5357 tempe 4319 temperature = <90000>;
5358 hyste 4320 hysteresis = <2000>;
5359 type 4321 type = "hot";
5360 }; 4322 };
5361 }; 4323 };
5362 }; 4324 };
5363 4325
5364 gpu-bottom-thermal { !! 4326 gpu-thermal-bottom {
5365 polling-delay-passive 4327 polling-delay-passive = <250>;
>> 4328 polling-delay = <1000>;
5366 4329
5367 thermal-sensors = <&t 4330 thermal-sensors = <&tsens1 11>;
5368 4331
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 4332 trips {
5377 gpu_bottom_al !! 4333 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 4334 temperature = <90000>;
5385 hyste !! 4335 hysteresis = <2000>;
5386 type 4336 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 4337 };
5394 }; 4338 };
5395 }; 4339 };
5396 }; 4340 };
5397 }; 4341 };
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