1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 15 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
22 17
23 / { 18 / {
24 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
25 20
26 #address-cells = <2>; 21 #address-cells = <2>;
27 #size-cells = <2>; 22 #size-cells = <2>;
28 23
29 chosen { }; 24 chosen { };
30 25
31 clocks { 26 clocks {
32 xo_board: xo-board { 27 xo_board: xo-board {
33 compatible = "fixed-cl 28 compatible = "fixed-clock";
34 #clock-cells = <0>; 29 #clock-cells = <0>;
35 clock-frequency = <384 30 clock-frequency = <38400000>;
36 clock-output-names = " 31 clock-output-names = "xo_board";
37 }; 32 };
38 33
39 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 35 compatible = "fixed-clock";
41 #clock-cells = <0>; 36 #clock-cells = <0>;
42 clock-frequency = <327 37 clock-frequency = <32764>;
43 clock-output-names = " 38 clock-output-names = "sleep_clk";
44 }; 39 };
45 }; 40 };
46 41
47 cpus { 42 cpus {
48 #address-cells = <2>; 43 #address-cells = <2>;
49 #size-cells = <0>; 44 #size-cells = <0>;
50 45
51 CPU0: cpu@0 { 46 CPU0: cpu@0 {
52 device_type = "cpu"; 47 device_type = "cpu";
53 compatible = "qcom,kry 48 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 50 enable-method = "psci";
57 capacity-dmips-mhz = < 51 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 52 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 53 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 54 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 55 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 58 power-domains = <&CPU_PD0>;
65 power-domain-names = " 59 power-domain-names = "psci";
66 #cooling-cells = <2>; 60 #cooling-cells = <2>;
67 L2_0: l2-cache { 61 L2_0: l2-cache {
68 compatible = " 62 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 63 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 64 L3_0: l3-cache {
73 compat !! 65 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 66 };
77 }; 67 };
78 }; 68 };
79 69
80 CPU1: cpu@100 { 70 CPU1: cpu@100 {
81 device_type = "cpu"; 71 device_type = "cpu";
82 compatible = "qcom,kry 72 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 73 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 74 enable-method = "psci";
86 capacity-dmips-mhz = < 75 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 76 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 77 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 79 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 82 power-domains = <&CPU_PD1>;
94 power-domain-names = " 83 power-domain-names = "psci";
95 #cooling-cells = <2>; 84 #cooling-cells = <2>;
96 L2_100: l2-cache { 85 L2_100: l2-cache {
97 compatible = " 86 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 87 next-level-cache = <&L3_0>;
101 }; 88 };
>> 89
102 }; 90 };
103 91
104 CPU2: cpu@200 { 92 CPU2: cpu@200 {
105 device_type = "cpu"; 93 device_type = "cpu";
106 compatible = "qcom,kry 94 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 95 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 96 enable-method = "psci";
110 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 98 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 99 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 101 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 104 power-domains = <&CPU_PD2>;
118 power-domain-names = " 105 power-domain-names = "psci";
119 #cooling-cells = <2>; 106 #cooling-cells = <2>;
120 L2_200: l2-cache { 107 L2_200: l2-cache {
121 compatible = " 108 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 109 next-level-cache = <&L3_0>;
125 }; 110 };
126 }; 111 };
127 112
128 CPU3: cpu@300 { 113 CPU3: cpu@300 {
129 device_type = "cpu"; 114 device_type = "cpu";
130 compatible = "qcom,kry 115 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 116 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 117 enable-method = "psci";
134 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 119 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 120 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 122 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 125 power-domains = <&CPU_PD3>;
142 power-domain-names = " 126 power-domain-names = "psci";
143 #cooling-cells = <2>; 127 #cooling-cells = <2>;
144 L2_300: l2-cache { 128 L2_300: l2-cache {
145 compatible = " 129 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 130 next-level-cache = <&L3_0>;
149 }; 131 };
150 }; 132 };
151 133
152 CPU4: cpu@400 { 134 CPU4: cpu@400 {
153 device_type = "cpu"; 135 device_type = "cpu";
154 compatible = "qcom,kry 136 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 137 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 138 enable-method = "psci";
158 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 140 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 141 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 143 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 146 power-domains = <&CPU_PD4>;
166 power-domain-names = " 147 power-domain-names = "psci";
167 #cooling-cells = <2>; 148 #cooling-cells = <2>;
168 L2_400: l2-cache { 149 L2_400: l2-cache {
169 compatible = " 150 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 151 next-level-cache = <&L3_0>;
173 }; 152 };
174 }; 153 };
175 154
176 CPU5: cpu@500 { 155 CPU5: cpu@500 {
177 device_type = "cpu"; 156 device_type = "cpu";
178 compatible = "qcom,kry 157 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 158 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 159 enable-method = "psci";
182 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 161 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 162 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 163 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 164 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 167 power-domains = <&CPU_PD5>;
190 power-domain-names = " 168 power-domain-names = "psci";
191 #cooling-cells = <2>; 169 #cooling-cells = <2>;
192 L2_500: l2-cache { 170 L2_500: l2-cache {
193 compatible = " 171 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 172 next-level-cache = <&L3_0>;
197 }; 173 };
198 }; 174 };
199 175
200 CPU6: cpu@600 { 176 CPU6: cpu@600 {
201 device_type = "cpu"; 177 device_type = "cpu";
202 compatible = "qcom,kry 178 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 179 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 180 enable-method = "psci";
206 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 182 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 183 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 185 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 188 power-domains = <&CPU_PD6>;
214 power-domain-names = " 189 power-domain-names = "psci";
215 #cooling-cells = <2>; 190 #cooling-cells = <2>;
216 L2_600: l2-cache { 191 L2_600: l2-cache {
217 compatible = " 192 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 193 next-level-cache = <&L3_0>;
221 }; 194 };
222 }; 195 };
223 196
224 CPU7: cpu@700 { 197 CPU7: cpu@700 {
225 device_type = "cpu"; 198 device_type = "cpu";
226 compatible = "qcom,kry 199 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 200 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 201 enable-method = "psci";
230 capacity-dmips-mhz = < 202 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 203 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 204 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 205 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 206 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 209 power-domains = <&CPU_PD7>;
238 power-domain-names = " 210 power-domain-names = "psci";
239 #cooling-cells = <2>; 211 #cooling-cells = <2>;
240 L2_700: l2-cache { 212 L2_700: l2-cache {
241 compatible = " 213 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 214 next-level-cache = <&L3_0>;
245 }; 215 };
246 }; 216 };
247 217
248 cpu-map { 218 cpu-map {
249 cluster0 { 219 cluster0 {
250 core0 { 220 core0 {
251 cpu = 221 cpu = <&CPU0>;
252 }; 222 };
253 223
254 core1 { 224 core1 {
255 cpu = 225 cpu = <&CPU1>;
256 }; 226 };
257 227
258 core2 { 228 core2 {
259 cpu = 229 cpu = <&CPU2>;
260 }; 230 };
261 231
262 core3 { 232 core3 {
263 cpu = 233 cpu = <&CPU3>;
264 }; 234 };
265 235
266 core4 { 236 core4 {
267 cpu = 237 cpu = <&CPU4>;
268 }; 238 };
269 239
270 core5 { 240 core5 {
271 cpu = 241 cpu = <&CPU5>;
272 }; 242 };
273 243
274 core6 { 244 core6 {
275 cpu = 245 cpu = <&CPU6>;
276 }; 246 };
277 247
278 core7 { 248 core7 {
279 cpu = 249 cpu = <&CPU7>;
280 }; 250 };
281 }; 251 };
282 }; 252 };
283 253
284 idle-states { 254 idle-states {
285 entry-method = "psci"; 255 entry-method = "psci";
286 256
287 LITTLE_CPU_SLEEP_0: cp 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 258 compatible = "arm,idle-state";
289 idle-state-nam 259 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 260 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 261 entry-latency-us = <355>;
292 exit-latency-u 262 exit-latency-us = <909>;
293 min-residency- 263 min-residency-us = <3934>;
294 local-timer-st 264 local-timer-stop;
295 }; 265 };
296 266
297 BIG_CPU_SLEEP_0: cpu-s 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 268 compatible = "arm,idle-state";
299 idle-state-nam 269 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 270 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 271 entry-latency-us = <241>;
302 exit-latency-u 272 exit-latency-us = <1461>;
303 min-residency- 273 min-residency-us = <4488>;
304 local-timer-st 274 local-timer-stop;
305 }; 275 };
306 }; 276 };
307 277
308 domain-idle-states { 278 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 279 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 280 compatible = "domain-idle-state";
>> 281 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 282 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 283 entry-latency-us = <3263>;
313 exit-latency-u 284 exit-latency-us = <6562>;
314 min-residency- 285 min-residency-us = <9987>;
>> 286 local-timer-stop;
315 }; 287 };
316 }; 288 };
317 }; 289 };
318 290
319 cpu0_opp_table: opp-table-cpu0 { !! 291 cpu0_opp_table: cpu0_opp_table {
320 compatible = "operating-points 292 compatible = "operating-points-v2";
321 opp-shared; 293 opp-shared;
322 294
323 cpu0_opp1: opp-300000000 { 295 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 296 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 297 opp-peak-kBps = <800000 9600000>;
326 }; 298 };
327 299
328 cpu0_opp2: opp-403200000 { 300 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 301 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 302 opp-peak-kBps = <800000 9600000>;
331 }; 303 };
332 304
333 cpu0_opp3: opp-499200000 { 305 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 306 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 307 opp-peak-kBps = <800000 12902400>;
336 }; 308 };
337 309
338 cpu0_opp4: opp-576000000 { 310 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 311 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 312 opp-peak-kBps = <800000 12902400>;
341 }; 313 };
342 314
343 cpu0_opp5: opp-672000000 { 315 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 316 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 317 opp-peak-kBps = <800000 15974400>;
346 }; 318 };
347 319
348 cpu0_opp6: opp-768000000 { 320 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 321 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 322 opp-peak-kBps = <1804000 19660800>;
351 }; 323 };
352 324
353 cpu0_opp7: opp-844800000 { 325 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 326 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 327 opp-peak-kBps = <1804000 19660800>;
356 }; 328 };
357 329
358 cpu0_opp8: opp-940800000 { 330 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 331 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 332 opp-peak-kBps = <1804000 22732800>;
361 }; 333 };
362 334
363 cpu0_opp9: opp-1036800000 { 335 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 336 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 337 opp-peak-kBps = <1804000 22732800>;
366 }; 338 };
367 339
368 cpu0_opp10: opp-1113600000 { 340 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 341 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 342 opp-peak-kBps = <2188000 25804800>;
371 }; 343 };
372 344
373 cpu0_opp11: opp-1209600000 { 345 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 346 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 347 opp-peak-kBps = <2188000 31948800>;
376 }; 348 };
377 349
378 cpu0_opp12: opp-1305600000 { 350 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 351 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 352 opp-peak-kBps = <3072000 31948800>;
381 }; 353 };
382 354
383 cpu0_opp13: opp-1382400000 { 355 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 356 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 357 opp-peak-kBps = <3072000 31948800>;
386 }; 358 };
387 359
388 cpu0_opp14: opp-1478400000 { 360 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 361 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 362 opp-peak-kBps = <3072000 31948800>;
391 }; 363 };
392 364
393 cpu0_opp15: opp-1555200000 { 365 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 366 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 367 opp-peak-kBps = <3072000 40550400>;
396 }; 368 };
397 369
398 cpu0_opp16: opp-1632000000 { 370 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 371 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 372 opp-peak-kBps = <3072000 40550400>;
401 }; 373 };
402 374
403 cpu0_opp17: opp-1708800000 { 375 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 376 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 377 opp-peak-kBps = <3072000 43008000>;
406 }; 378 };
407 379
408 cpu0_opp18: opp-1785600000 { 380 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 381 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 382 opp-peak-kBps = <3072000 43008000>;
411 }; 383 };
412 }; 384 };
413 385
414 cpu4_opp_table: opp-table-cpu4 { !! 386 cpu4_opp_table: cpu4_opp_table {
415 compatible = "operating-points 387 compatible = "operating-points-v2";
416 opp-shared; 388 opp-shared;
417 389
418 cpu4_opp1: opp-710400000 { 390 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 391 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 392 opp-peak-kBps = <1804000 15974400>;
421 }; 393 };
422 394
423 cpu4_opp2: opp-825600000 { 395 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 396 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 397 opp-peak-kBps = <2188000 19660800>;
426 }; 398 };
427 399
428 cpu4_opp3: opp-940800000 { 400 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 401 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 402 opp-peak-kBps = <2188000 22732800>;
431 }; 403 };
432 404
433 cpu4_opp4: opp-1056000000 { 405 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 406 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 407 opp-peak-kBps = <3072000 25804800>;
436 }; 408 };
437 409
438 cpu4_opp5: opp-1171200000 { 410 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 411 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 412 opp-peak-kBps = <3072000 31948800>;
441 }; 413 };
442 414
443 cpu4_opp6: opp-1286400000 { 415 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 416 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 417 opp-peak-kBps = <4068000 31948800>;
446 }; 418 };
447 419
448 cpu4_opp7: opp-1401600000 { 420 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 421 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 422 opp-peak-kBps = <4068000 31948800>;
451 }; 423 };
452 424
453 cpu4_opp8: opp-1497600000 { 425 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 426 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 427 opp-peak-kBps = <4068000 40550400>;
456 }; 428 };
457 429
458 cpu4_opp9: opp-1612800000 { 430 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 431 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 432 opp-peak-kBps = <4068000 40550400>;
461 }; 433 };
462 434
463 cpu4_opp10: opp-1708800000 { 435 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 436 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 437 opp-peak-kBps = <4068000 43008000>;
466 }; 438 };
467 439
468 cpu4_opp11: opp-1804800000 { 440 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 441 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 442 opp-peak-kBps = <6220000 43008000>;
471 }; 443 };
472 444
473 cpu4_opp12: opp-1920000000 { 445 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 446 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 447 opp-peak-kBps = <6220000 49152000>;
476 }; 448 };
477 449
478 cpu4_opp13: opp-2016000000 { 450 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 451 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 452 opp-peak-kBps = <7216000 49152000>;
481 }; 453 };
482 454
483 cpu4_opp14: opp-2131200000 { 455 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 456 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 457 opp-peak-kBps = <8368000 49152000>;
486 }; 458 };
487 459
488 cpu4_opp15: opp-2227200000 { 460 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 461 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 462 opp-peak-kBps = <8368000 51609600>;
491 }; 463 };
492 464
493 cpu4_opp16: opp-2323200000 { 465 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 466 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 467 opp-peak-kBps = <8368000 51609600>;
496 }; 468 };
497 469
498 cpu4_opp17: opp-2419200000 { 470 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 471 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 472 opp-peak-kBps = <8368000 51609600>;
501 }; 473 };
502 }; 474 };
503 475
504 cpu7_opp_table: opp-table-cpu7 { !! 476 cpu7_opp_table: cpu7_opp_table {
505 compatible = "operating-points 477 compatible = "operating-points-v2";
506 opp-shared; 478 opp-shared;
507 479
508 cpu7_opp1: opp-825600000 { 480 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 481 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 19660800>;
511 }; 483 };
512 484
513 cpu7_opp2: opp-940800000 { 485 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 486 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 487 opp-peak-kBps = <2188000 22732800>;
516 }; 488 };
517 489
518 cpu7_opp3: opp-1056000000 { 490 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 491 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 25804800>;
521 }; 493 };
522 494
523 cpu7_opp4: opp-1171200000 { 495 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 496 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 497 opp-peak-kBps = <3072000 31948800>;
526 }; 498 };
527 499
528 cpu7_opp5: opp-1286400000 { 500 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 501 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 31948800>;
531 }; 503 };
532 504
533 cpu7_opp6: opp-1401600000 { 505 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 506 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 31948800>;
536 }; 508 };
537 509
538 cpu7_opp7: opp-1497600000 { 510 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 511 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 40550400>;
541 }; 513 };
542 514
543 cpu7_opp8: opp-1612800000 { 515 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 516 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 517 opp-peak-kBps = <4068000 40550400>;
546 }; 518 };
547 519
548 cpu7_opp9: opp-1708800000 { 520 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 521 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 522 opp-peak-kBps = <4068000 43008000>;
551 }; 523 };
552 524
553 cpu7_opp10: opp-1804800000 { 525 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 526 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 527 opp-peak-kBps = <6220000 43008000>;
556 }; 528 };
557 529
558 cpu7_opp11: opp-1920000000 { 530 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 531 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 532 opp-peak-kBps = <6220000 49152000>;
561 }; 533 };
562 534
563 cpu7_opp12: opp-2016000000 { 535 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 536 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 537 opp-peak-kBps = <7216000 49152000>;
566 }; 538 };
567 539
568 cpu7_opp13: opp-2131200000 { 540 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 541 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 542 opp-peak-kBps = <8368000 49152000>;
571 }; 543 };
572 544
573 cpu7_opp14: opp-2227200000 { 545 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 546 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 547 opp-peak-kBps = <8368000 51609600>;
576 }; 548 };
577 549
578 cpu7_opp15: opp-2323200000 { 550 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 551 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 552 opp-peak-kBps = <8368000 51609600>;
581 }; 553 };
582 554
583 cpu7_opp16: opp-2419200000 { 555 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 556 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
586 }; 558 };
587 559
588 cpu7_opp17: opp-2534400000 { 560 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 561 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
591 }; 563 };
592 564
593 cpu7_opp18: opp-2649600000 { 565 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 566 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 567 opp-peak-kBps = <8368000 51609600>;
596 }; 568 };
597 569
598 cpu7_opp19: opp-2745600000 { 570 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 571 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 572 opp-peak-kBps = <8368000 51609600>;
601 }; 573 };
602 574
603 cpu7_opp20: opp-2841600000 { 575 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 576 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 577 opp-peak-kBps = <8368000 51609600>;
606 }; 578 };
607 }; 579 };
608 580
609 firmware { 581 firmware {
610 scm: scm { 582 scm: scm {
611 compatible = "qcom,scm 583 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 584 #reset-cells = <1>;
613 }; 585 };
614 }; 586 };
615 587
>> 588 tcsr_mutex: hwlock {
>> 589 compatible = "qcom,tcsr-mutex";
>> 590 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 591 #hwlock-cells = <1>;
>> 592 };
>> 593
616 memory@80000000 { 594 memory@80000000 {
617 device_type = "memory"; 595 device_type = "memory";
618 /* We expect the bootloader to 596 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 597 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 598 };
621 599
622 pmu { 600 pmu {
623 compatible = "arm,armv8-pmuv3" 601 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 602 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 603 };
626 604
627 psci { 605 psci {
628 compatible = "arm,psci-1.0"; 606 compatible = "arm,psci-1.0";
629 method = "smc"; 607 method = "smc";
630 608
631 CPU_PD0: power-domain-cpu0 { !! 609 CPU_PD0: cpu0 {
632 #power-domain-cells = 610 #power-domain-cells = <0>;
633 power-domains = <&CLUS 611 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 613 };
636 614
637 CPU_PD1: power-domain-cpu1 { !! 615 CPU_PD1: cpu1 {
638 #power-domain-cells = 616 #power-domain-cells = <0>;
639 power-domains = <&CLUS 617 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 619 };
642 620
643 CPU_PD2: power-domain-cpu2 { !! 621 CPU_PD2: cpu2 {
644 #power-domain-cells = 622 #power-domain-cells = <0>;
645 power-domains = <&CLUS 623 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 625 };
648 626
649 CPU_PD3: power-domain-cpu3 { !! 627 CPU_PD3: cpu3 {
650 #power-domain-cells = 628 #power-domain-cells = <0>;
651 power-domains = <&CLUS 629 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 631 };
654 632
655 CPU_PD4: power-domain-cpu4 { !! 633 CPU_PD4: cpu4 {
656 #power-domain-cells = 634 #power-domain-cells = <0>;
657 power-domains = <&CLUS 635 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 636 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 637 };
660 638
661 CPU_PD5: power-domain-cpu5 { !! 639 CPU_PD5: cpu5 {
662 #power-domain-cells = 640 #power-domain-cells = <0>;
663 power-domains = <&CLUS 641 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 642 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 643 };
666 644
667 CPU_PD6: power-domain-cpu6 { !! 645 CPU_PD6: cpu6 {
668 #power-domain-cells = 646 #power-domain-cells = <0>;
669 power-domains = <&CLUS 647 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 648 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 649 };
672 650
673 CPU_PD7: power-domain-cpu7 { !! 651 CPU_PD7: cpu7 {
674 #power-domain-cells = 652 #power-domain-cells = <0>;
675 power-domains = <&CLUS 653 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 654 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 655 };
678 656
679 CLUSTER_PD: power-domain-cpu-c !! 657 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 658 #power-domain-cells = <0>;
681 domain-idle-states = < 659 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 660 };
683 }; 661 };
684 662
685 reserved-memory { 663 reserved-memory {
686 #address-cells = <2>; 664 #address-cells = <2>;
687 #size-cells = <2>; 665 #size-cells = <2>;
688 ranges; 666 ranges;
689 667
690 hyp_mem: memory@85700000 { 668 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 669 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 670 no-map;
693 }; 671 };
694 672
695 xbl_mem: memory@85d00000 { 673 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 674 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 675 no-map;
698 }; 676 };
699 677
700 aop_mem: memory@85f00000 { 678 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 679 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 680 no-map;
703 }; 681 };
704 682
705 aop_cmd_db: memory@85f20000 { 683 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 684 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 685 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 686 no-map;
709 }; 687 };
710 688
711 smem_mem: memory@86000000 { 689 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 690 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 691 no-map;
714 }; 692 };
715 693
716 tz_mem: memory@86200000 { 694 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 695 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 696 no-map;
719 }; 697 };
720 698
721 rmtfs_mem: memory@89b00000 { 699 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 700 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 701 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 702 no-map;
725 703
726 qcom,client-id = <1>; 704 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 705 qcom,vmid = <15>;
728 }; 706 };
729 707
730 camera_mem: memory@8b700000 { 708 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 709 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 710 no-map;
733 }; 711 };
734 712
735 wlan_mem: memory@8bc00000 { 713 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 714 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 715 no-map;
738 }; 716 };
739 717
740 npu_mem: memory@8bd80000 { 718 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 719 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 720 no-map;
743 }; 721 };
744 722
745 adsp_mem: memory@8be00000 { 723 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 724 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 725 no-map;
748 }; 726 };
749 727
750 mpss_mem: memory@8d800000 { 728 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 729 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 730 no-map;
753 }; 731 };
754 732
755 venus_mem: memory@96e00000 { 733 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 734 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 735 no-map;
758 }; 736 };
759 737
760 slpi_mem: memory@97300000 { 738 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 739 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 740 no-map;
763 }; 741 };
764 742
765 ipa_fw_mem: memory@98700000 { 743 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 744 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 745 no-map;
768 }; 746 };
769 747
770 ipa_gsi_mem: memory@98710000 { 748 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 749 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 750 no-map;
773 }; 751 };
774 752
775 gpu_mem: memory@98715000 { 753 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 754 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 755 no-map;
778 }; 756 };
779 757
780 spss_mem: memory@98800000 { 758 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 759 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 760 no-map;
783 }; 761 };
784 762
785 cdsp_mem: memory@98900000 { 763 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 764 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 765 no-map;
788 }; 766 };
789 767
790 qseecom_mem: memory@9e400000 { 768 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 769 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 770 no-map;
793 }; 771 };
794 }; 772 };
795 773
796 smem { 774 smem {
797 compatible = "qcom,smem"; 775 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 776 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 777 hwlocks = <&tcsr_mutex 3>;
800 }; 778 };
801 779
802 smp2p-cdsp { 780 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 781 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 782 qcom,smem = <94>, <432>;
805 783
806 interrupts = <GIC_SPI 576 IRQ_ 784 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 785
808 mboxes = <&apss_shared 6>; 786 mboxes = <&apss_shared 6>;
809 787
810 qcom,local-pid = <0>; 788 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 789 qcom,remote-pid = <5>;
812 790
813 cdsp_smp2p_out: master-kernel 791 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 792 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 793 #qcom,smem-state-cells = <1>;
816 }; 794 };
817 795
818 cdsp_smp2p_in: slave-kernel { 796 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 797 qcom,entry-name = "slave-kernel";
820 798
821 interrupt-controller; 799 interrupt-controller;
822 #interrupt-cells = <2> 800 #interrupt-cells = <2>;
823 }; 801 };
824 }; 802 };
825 803
826 smp2p-lpass { 804 smp2p-lpass {
827 compatible = "qcom,smp2p"; 805 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 806 qcom,smem = <443>, <429>;
829 807
830 interrupts = <GIC_SPI 158 IRQ_ 808 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 809
832 mboxes = <&apss_shared 10>; 810 mboxes = <&apss_shared 10>;
833 811
834 qcom,local-pid = <0>; 812 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 813 qcom,remote-pid = <2>;
836 814
837 adsp_smp2p_out: master-kernel 815 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 816 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 817 #qcom,smem-state-cells = <1>;
840 }; 818 };
841 819
842 adsp_smp2p_in: slave-kernel { 820 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 821 qcom,entry-name = "slave-kernel";
844 822
845 interrupt-controller; 823 interrupt-controller;
846 #interrupt-cells = <2> 824 #interrupt-cells = <2>;
847 }; 825 };
848 }; 826 };
849 827
850 smp2p-mpss { 828 smp2p-mpss {
851 compatible = "qcom,smp2p"; 829 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 830 qcom,smem = <435>, <428>;
853 831
854 interrupts = <GIC_SPI 451 IRQ_ 832 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 833
856 mboxes = <&apss_shared 14>; 834 mboxes = <&apss_shared 14>;
857 835
858 qcom,local-pid = <0>; 836 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 837 qcom,remote-pid = <1>;
860 838
861 modem_smp2p_out: master-kernel 839 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 840 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 841 #qcom,smem-state-cells = <1>;
864 }; 842 };
865 843
866 modem_smp2p_in: slave-kernel { 844 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 845 qcom,entry-name = "slave-kernel";
868 846
869 interrupt-controller; 847 interrupt-controller;
870 #interrupt-cells = <2> 848 #interrupt-cells = <2>;
871 }; 849 };
872 }; 850 };
873 851
874 smp2p-slpi { 852 smp2p-slpi {
875 compatible = "qcom,smp2p"; 853 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 854 qcom,smem = <481>, <430>;
877 855
878 interrupts = <GIC_SPI 172 IRQ_ 856 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 857
880 mboxes = <&apss_shared 26>; 858 mboxes = <&apss_shared 26>;
881 859
882 qcom,local-pid = <0>; 860 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 861 qcom,remote-pid = <3>;
884 862
885 slpi_smp2p_out: master-kernel 863 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 864 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 865 #qcom,smem-state-cells = <1>;
888 }; 866 };
889 867
890 slpi_smp2p_in: slave-kernel { 868 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 869 qcom,entry-name = "slave-kernel";
892 870
893 interrupt-controller; 871 interrupt-controller;
894 #interrupt-cells = <2> 872 #interrupt-cells = <2>;
895 }; 873 };
896 }; 874 };
897 875
898 soc: soc@0 { 876 soc: soc@0 {
899 #address-cells = <2>; 877 #address-cells = <2>;
900 #size-cells = <2>; 878 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 879 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 880 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 881 compatible = "simple-bus";
904 882
905 gcc: clock-controller@100000 { 883 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 884 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 885 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 886 #clock-cells = <1>;
909 #reset-cells = <1>; 887 #reset-cells = <1>;
910 #power-domain-cells = 888 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 889 clock-names = "bi_tcxo",
912 "sleep_c 890 "sleep_clk";
913 clocks = <&rpmhcc RPMH 891 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 892 <&sleep_clk>;
915 }; 893 };
916 894
917 gpi_dma0: dma-controller@80000 895 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 !! 896 compatible = "qcom,sm8150-gpi-dma";
919 reg = <0 0x00800000 0 !! 897 reg = <0 0x800000 0 0x60000>;
920 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 910 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 911 dma-channels = <13>;
934 dma-channel-mask = <0x 912 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 913 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 914 #dma-cells = <3>;
937 status = "disabled"; 915 status = "disabled";
938 }; 916 };
939 917
940 ethernet: ethernet@20000 { <<
941 compatible = "qcom,sm8 <<
942 reg = <0x0 0x00020000 <<
943 <0x0 0x00036000 <<
944 reg-names = "stmmaceth <<
945 clock-names = "stmmace <<
946 clocks = <&gcc GCC_EMA <<
947 <&gcc GCC_EMAC <<
948 <&gcc GCC_EMAC <<
949 <&gcc GCC_EMAC <<
950 interrupts = <GIC_SPI <<
951 <GIC_SPI <<
952 interrupt-names = "mac <<
953 <<
954 power-domains = <&gcc <<
955 resets = <&gcc GCC_EMA <<
956 <<
957 iommus = <&apps_smmu 0 <<
958 <<
959 snps,tso; <<
960 rx-fifo-depth = <4096> <<
961 tx-fifo-depth = <4096> <<
962 <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 <<
978 qupv3_id_0: geniqup@8c0000 { 918 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 919 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 920 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 921 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 922 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 923 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 924 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 925 #address-cells = <2>;
986 #size-cells = <2>; 926 #size-cells = <2>;
987 ranges; 927 ranges;
988 status = "disabled"; 928 status = "disabled";
989 929
990 i2c0: i2c@880000 { 930 i2c0: i2c@880000 {
991 compatible = " 931 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 932 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 933 clock-names = "se";
994 clocks = <&gcc 934 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d <<
996 <&gpi_d <<
997 dma-names = "t <<
998 pinctrl-names 935 pinctrl-names = "default";
999 pinctrl-0 = <& 936 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 937 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 938 #address-cells = <1>;
1002 #size-cells = 939 #size-cells = <0>;
1003 status = "dis 940 status = "disabled";
1004 }; 941 };
1005 942
1006 spi0: spi@880000 { 943 spi0: spi@880000 {
1007 compatible = 944 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 !! 945 reg = <0 0x880000 0 0x4000>;
1009 reg-names = " 946 reg-names = "se";
1010 clock-names = 947 clock-names = "se";
1011 clocks = <&gc 948 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ <<
1013 <&gpi_ <<
1014 dma-names = " <<
1015 pinctrl-names 949 pinctrl-names = "default";
1016 pinctrl-0 = < 950 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 951 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 952 spi-max-frequency = <50000000>;
1019 #address-cell 953 #address-cells = <1>;
1020 #size-cells = 954 #size-cells = <0>;
1021 status = "dis 955 status = "disabled";
1022 }; 956 };
1023 957
1024 i2c1: i2c@884000 { 958 i2c1: i2c@884000 {
1025 compatible = 959 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 960 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 961 clock-names = "se";
1028 clocks = <&gc 962 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 pinctrl-names 963 pinctrl-names = "default";
1033 pinctrl-0 = < 964 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 965 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 966 #address-cells = <1>;
1036 #size-cells = 967 #size-cells = <0>;
1037 status = "dis 968 status = "disabled";
1038 }; 969 };
1039 970
1040 spi1: spi@884000 { 971 spi1: spi@884000 {
1041 compatible = 972 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 !! 973 reg = <0 0x884000 0 0x4000>;
1043 reg-names = " 974 reg-names = "se";
1044 clock-names = 975 clock-names = "se";
1045 clocks = <&gc 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ <<
1047 <&gpi_ <<
1048 dma-names = " <<
1049 pinctrl-names 977 pinctrl-names = "default";
1050 pinctrl-0 = < 978 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 980 spi-max-frequency = <50000000>;
1053 #address-cell 981 #address-cells = <1>;
1054 #size-cells = 982 #size-cells = <0>;
1055 status = "dis 983 status = "disabled";
1056 }; 984 };
1057 985
1058 i2c2: i2c@888000 { 986 i2c2: i2c@888000 {
1059 compatible = 987 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 988 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 989 clock-names = "se";
1062 clocks = <&gc 990 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ <<
1064 <&gpi_ <<
1065 dma-names = " <<
1066 pinctrl-names 991 pinctrl-names = "default";
1067 pinctrl-0 = < 992 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 993 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 994 #address-cells = <1>;
1070 #size-cells = 995 #size-cells = <0>;
1071 status = "dis 996 status = "disabled";
1072 }; 997 };
1073 998
1074 spi2: spi@888000 { 999 spi2: spi@888000 {
1075 compatible = 1000 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 !! 1001 reg = <0 0x888000 0 0x4000>;
1077 reg-names = " 1002 reg-names = "se";
1078 clock-names = 1003 clock-names = "se";
1079 clocks = <&gc 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ <<
1081 <&gpi_ <<
1082 dma-names = " <<
1083 pinctrl-names 1005 pinctrl-names = "default";
1084 pinctrl-0 = < 1006 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1007 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1008 spi-max-frequency = <50000000>;
1087 #address-cell 1009 #address-cells = <1>;
1088 #size-cells = 1010 #size-cells = <0>;
1089 status = "dis 1011 status = "disabled";
1090 }; 1012 };
1091 1013
1092 i2c3: i2c@88c000 { 1014 i2c3: i2c@88c000 {
1093 compatible = 1015 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1016 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1017 clock-names = "se";
1096 clocks = <&gc 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ <<
1098 <&gpi_ <<
1099 dma-names = " <<
1100 pinctrl-names 1019 pinctrl-names = "default";
1101 pinctrl-0 = < 1020 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1021 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1022 #address-cells = <1>;
1104 #size-cells = 1023 #size-cells = <0>;
1105 status = "dis 1024 status = "disabled";
1106 }; 1025 };
1107 1026
1108 spi3: spi@88c000 { 1027 spi3: spi@88c000 {
1109 compatible = 1028 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 !! 1029 reg = <0 0x88c000 0 0x4000>;
1111 reg-names = " 1030 reg-names = "se";
1112 clock-names = 1031 clock-names = "se";
1113 clocks = <&gc 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ <<
1115 <&gpi_ <<
1116 dma-names = " <<
1117 pinctrl-names 1033 pinctrl-names = "default";
1118 pinctrl-0 = < 1034 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1035 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1036 spi-max-frequency = <50000000>;
1121 #address-cell 1037 #address-cells = <1>;
1122 #size-cells = 1038 #size-cells = <0>;
1123 status = "dis 1039 status = "disabled";
1124 }; 1040 };
1125 1041
1126 i2c4: i2c@890000 { 1042 i2c4: i2c@890000 {
1127 compatible = 1043 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1044 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1045 clock-names = "se";
1130 clocks = <&gc 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ <<
1132 <&gpi_ <<
1133 dma-names = " <<
1134 pinctrl-names 1047 pinctrl-names = "default";
1135 pinctrl-0 = < 1048 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1049 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1050 #address-cells = <1>;
1138 #size-cells = 1051 #size-cells = <0>;
1139 status = "dis 1052 status = "disabled";
1140 }; 1053 };
1141 1054
1142 spi4: spi@890000 { 1055 spi4: spi@890000 {
1143 compatible = 1056 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 !! 1057 reg = <0 0x890000 0 0x4000>;
1145 reg-names = " 1058 reg-names = "se";
1146 clock-names = 1059 clock-names = "se";
1147 clocks = <&gc 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ <<
1149 <&gpi_ <<
1150 dma-names = " <<
1151 pinctrl-names 1061 pinctrl-names = "default";
1152 pinctrl-0 = < 1062 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1063 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1064 spi-max-frequency = <50000000>;
1155 #address-cell 1065 #address-cells = <1>;
1156 #size-cells = 1066 #size-cells = <0>;
1157 status = "dis 1067 status = "disabled";
1158 }; 1068 };
1159 1069
1160 i2c5: i2c@894000 { 1070 i2c5: i2c@894000 {
1161 compatible = 1071 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1072 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1073 clock-names = "se";
1164 clocks = <&gc 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ <<
1166 <&gpi_ <<
1167 dma-names = " <<
1168 pinctrl-names 1075 pinctrl-names = "default";
1169 pinctrl-0 = < 1076 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1077 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1078 #address-cells = <1>;
1172 #size-cells = 1079 #size-cells = <0>;
1173 status = "dis 1080 status = "disabled";
1174 }; 1081 };
1175 1082
1176 spi5: spi@894000 { 1083 spi5: spi@894000 {
1177 compatible = 1084 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 !! 1085 reg = <0 0x894000 0 0x4000>;
1179 reg-names = " 1086 reg-names = "se";
1180 clock-names = 1087 clock-names = "se";
1181 clocks = <&gc 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ <<
1183 <&gpi_ <<
1184 dma-names = " <<
1185 pinctrl-names 1089 pinctrl-names = "default";
1186 pinctrl-0 = < 1090 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1091 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1092 spi-max-frequency = <50000000>;
1189 #address-cell 1093 #address-cells = <1>;
1190 #size-cells = 1094 #size-cells = <0>;
1191 status = "dis 1095 status = "disabled";
1192 }; 1096 };
1193 1097
1194 i2c6: i2c@898000 { 1098 i2c6: i2c@898000 {
1195 compatible = 1099 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1100 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1101 clock-names = "se";
1198 clocks = <&gc 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ <<
1200 <&gpi_ <<
1201 dma-names = " <<
1202 pinctrl-names 1103 pinctrl-names = "default";
1203 pinctrl-0 = < 1104 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1105 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1106 #address-cells = <1>;
1206 #size-cells = 1107 #size-cells = <0>;
1207 status = "dis 1108 status = "disabled";
1208 }; 1109 };
1209 1110
1210 spi6: spi@898000 { 1111 spi6: spi@898000 {
1211 compatible = 1112 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 !! 1113 reg = <0 0x898000 0 0x4000>;
1213 reg-names = " 1114 reg-names = "se";
1214 clock-names = 1115 clock-names = "se";
1215 clocks = <&gc 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ <<
1217 <&gpi_ <<
1218 dma-names = " <<
1219 pinctrl-names 1117 pinctrl-names = "default";
1220 pinctrl-0 = < 1118 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1119 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1120 spi-max-frequency = <50000000>;
1223 #address-cell 1121 #address-cells = <1>;
1224 #size-cells = 1122 #size-cells = <0>;
1225 status = "dis 1123 status = "disabled";
1226 }; 1124 };
1227 1125
1228 i2c7: i2c@89c000 { 1126 i2c7: i2c@89c000 {
1229 compatible = 1127 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1128 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1129 clock-names = "se";
1232 clocks = <&gc 1130 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ <<
1234 <&gpi_ <<
1235 dma-names = " <<
1236 pinctrl-names 1131 pinctrl-names = "default";
1237 pinctrl-0 = < 1132 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = !! 1133 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1134 #address-cells = <1>;
1240 #size-cells = 1135 #size-cells = <0>;
1241 status = "dis 1136 status = "disabled";
1242 }; 1137 };
1243 1138
1244 spi7: spi@89c000 { 1139 spi7: spi@89c000 {
1245 compatible = 1140 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 !! 1141 reg = <0 0x89c000 0 0x4000>;
1247 reg-names = " 1142 reg-names = "se";
1248 clock-names = 1143 clock-names = "se";
1249 clocks = <&gc 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ <<
1251 <&gpi_ <<
1252 dma-names = " <<
1253 pinctrl-names 1145 pinctrl-names = "default";
1254 pinctrl-0 = < 1146 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1147 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1148 spi-max-frequency = <50000000>;
1257 #address-cell 1149 #address-cells = <1>;
1258 #size-cells = 1150 #size-cells = <0>;
1259 status = "dis 1151 status = "disabled";
1260 }; 1152 };
1261 }; 1153 };
1262 1154
1263 gpi_dma1: dma-controller@a000 1155 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm !! 1156 compatible = "qcom,sm8150-gpi-dma";
1265 reg = <0 0x00a00000 0 !! 1157 reg = <0 0xa00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1158 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1159 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1160 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1161 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1162 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1163 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1164 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1165 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1166 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1167 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1168 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1169 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1170 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1171 dma-channels = <13>;
1280 dma-channel-mask = <0 1172 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1173 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1174 #dma-cells = <3>;
1283 status = "disabled"; 1175 status = "disabled";
1284 }; 1176 };
1285 1177
1286 qupv3_id_1: geniqup@ac0000 { 1178 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1179 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1180 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1181 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1182 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1183 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1184 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1185 #address-cells = <2>;
1294 #size-cells = <2>; 1186 #size-cells = <2>;
1295 ranges; 1187 ranges;
1296 status = "disabled"; 1188 status = "disabled";
1297 1189
1298 i2c8: i2c@a80000 { 1190 i2c8: i2c@a80000 {
1299 compatible = 1191 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1192 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1193 clock-names = "se";
1302 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ <<
1304 <&gpi_ <<
1305 dma-names = " <<
1306 pinctrl-names 1195 pinctrl-names = "default";
1307 pinctrl-0 = < 1196 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1197 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1198 #address-cells = <1>;
1310 #size-cells = 1199 #size-cells = <0>;
1311 status = "dis 1200 status = "disabled";
1312 }; 1201 };
1313 1202
1314 spi8: spi@a80000 { 1203 spi8: spi@a80000 {
1315 compatible = 1204 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 !! 1205 reg = <0 0xa80000 0 0x4000>;
1317 reg-names = " 1206 reg-names = "se";
1318 clock-names = 1207 clock-names = "se";
1319 clocks = <&gc 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ <<
1321 <&gpi_ <<
1322 dma-names = " <<
1323 pinctrl-names 1209 pinctrl-names = "default";
1324 pinctrl-0 = < 1210 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1211 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1212 spi-max-frequency = <50000000>;
1327 #address-cell 1213 #address-cells = <1>;
1328 #size-cells = 1214 #size-cells = <0>;
1329 status = "dis 1215 status = "disabled";
1330 }; 1216 };
1331 1217
1332 i2c9: i2c@a84000 { 1218 i2c9: i2c@a84000 {
1333 compatible = 1219 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1220 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1221 clock-names = "se";
1336 clocks = <&gc 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ <<
1338 <&gpi_ <<
1339 dma-names = " <<
1340 pinctrl-names 1223 pinctrl-names = "default";
1341 pinctrl-0 = < 1224 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1225 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1226 #address-cells = <1>;
1344 #size-cells = 1227 #size-cells = <0>;
1345 status = "dis 1228 status = "disabled";
1346 }; 1229 };
1347 1230
1348 spi9: spi@a84000 { 1231 spi9: spi@a84000 {
1349 compatible = 1232 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 !! 1233 reg = <0 0xa84000 0 0x4000>;
1351 reg-names = " 1234 reg-names = "se";
1352 clock-names = 1235 clock-names = "se";
1353 clocks = <&gc 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ <<
1355 <&gpi_ <<
1356 dma-names = " <<
1357 pinctrl-names 1237 pinctrl-names = "default";
1358 pinctrl-0 = < 1238 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1239 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1240 spi-max-frequency = <50000000>;
1361 #address-cell 1241 #address-cells = <1>;
1362 #size-cells = 1242 #size-cells = <0>;
1363 status = "dis 1243 status = "disabled";
1364 }; 1244 };
1365 1245
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 1246 i2c10: i2c@a88000 {
1378 compatible = 1247 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1248 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1249 clock-names = "se";
1381 clocks = <&gc 1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ <<
1383 <&gpi_ <<
1384 dma-names = " <<
1385 pinctrl-names 1251 pinctrl-names = "default";
1386 pinctrl-0 = < 1252 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1253 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1254 #address-cells = <1>;
1389 #size-cells = 1255 #size-cells = <0>;
1390 status = "dis 1256 status = "disabled";
1391 }; 1257 };
1392 1258
1393 spi10: spi@a88000 { 1259 spi10: spi@a88000 {
1394 compatible = 1260 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 !! 1261 reg = <0 0xa88000 0 0x4000>;
1396 reg-names = " 1262 reg-names = "se";
1397 clock-names = 1263 clock-names = "se";
1398 clocks = <&gc 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ <<
1400 <&gpi_ <<
1401 dma-names = " <<
1402 pinctrl-names 1265 pinctrl-names = "default";
1403 pinctrl-0 = < 1266 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1267 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1268 spi-max-frequency = <50000000>;
1406 #address-cell 1269 #address-cells = <1>;
1407 #size-cells = 1270 #size-cells = <0>;
1408 status = "dis 1271 status = "disabled";
1409 }; 1272 };
1410 1273
1411 i2c11: i2c@a8c000 { 1274 i2c11: i2c@a8c000 {
1412 compatible = 1275 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1276 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1277 clock-names = "se";
1415 clocks = <&gc 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ <<
1417 <&gpi_ <<
1418 dma-names = " <<
1419 pinctrl-names 1279 pinctrl-names = "default";
1420 pinctrl-0 = < 1280 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1282 #address-cells = <1>;
1423 #size-cells = 1283 #size-cells = <0>;
1424 status = "dis 1284 status = "disabled";
1425 }; 1285 };
1426 1286
1427 spi11: spi@a8c000 { 1287 spi11: spi@a8c000 {
1428 compatible = 1288 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 !! 1289 reg = <0 0xa8c000 0 0x4000>;
1430 reg-names = " 1290 reg-names = "se";
1431 clock-names = 1291 clock-names = "se";
1432 clocks = <&gc 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ <<
1434 <&gpi_ <<
1435 dma-names = " <<
1436 pinctrl-names 1293 pinctrl-names = "default";
1437 pinctrl-0 = < 1294 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1295 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1296 spi-max-frequency = <50000000>;
1440 #address-cell 1297 #address-cells = <1>;
1441 #size-cells = 1298 #size-cells = <0>;
1442 status = "dis 1299 status = "disabled";
1443 }; 1300 };
1444 1301
1445 uart2: serial@a90000 1302 uart2: serial@a90000 {
1446 compatible = 1303 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1304 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1305 clock-names = "se";
1449 clocks = <&gc 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1307 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1308 status = "disabled";
1452 }; 1309 };
1453 1310
1454 i2c12: i2c@a90000 { 1311 i2c12: i2c@a90000 {
1455 compatible = 1312 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1313 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1314 clock-names = "se";
1458 clocks = <&gc 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 pinctrl-names 1316 pinctrl-names = "default";
1463 pinctrl-0 = < 1317 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1319 #address-cells = <1>;
1466 #size-cells = 1320 #size-cells = <0>;
1467 status = "dis 1321 status = "disabled";
1468 }; 1322 };
1469 1323
1470 spi12: spi@a90000 { 1324 spi12: spi@a90000 {
1471 compatible = 1325 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 !! 1326 reg = <0 0xa90000 0 0x4000>;
1473 reg-names = " 1327 reg-names = "se";
1474 clock-names = 1328 clock-names = "se";
1475 clocks = <&gc 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ <<
1477 <&gpi_ <<
1478 dma-names = " <<
1479 pinctrl-names 1330 pinctrl-names = "default";
1480 pinctrl-0 = < 1331 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1332 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1333 spi-max-frequency = <50000000>;
1483 #address-cell 1334 #address-cells = <1>;
1484 #size-cells = 1335 #size-cells = <0>;
1485 status = "dis 1336 status = "disabled";
1486 }; 1337 };
1487 1338
1488 i2c16: i2c@94000 { 1339 i2c16: i2c@94000 {
1489 compatible = 1340 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 !! 1341 reg = <0 0x0094000 0 0x4000>;
1491 clock-names = 1342 clock-names = "se";
1492 clocks = <&gc 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ <<
1494 <&gpi_ <<
1495 dma-names = " <<
1496 pinctrl-names 1344 pinctrl-names = "default";
1497 pinctrl-0 = < 1345 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1346 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1347 #address-cells = <1>;
1500 #size-cells = 1348 #size-cells = <0>;
1501 status = "dis 1349 status = "disabled";
1502 }; 1350 };
1503 1351
1504 spi16: spi@a94000 { 1352 spi16: spi@a94000 {
1505 compatible = 1353 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 !! 1354 reg = <0 0xa94000 0 0x4000>;
1507 reg-names = " 1355 reg-names = "se";
1508 clock-names = 1356 clock-names = "se";
1509 clocks = <&gc 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ <<
1511 <&gpi_ <<
1512 dma-names = " <<
1513 pinctrl-names 1358 pinctrl-names = "default";
1514 pinctrl-0 = < 1359 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1361 spi-max-frequency = <50000000>;
1517 #address-cell 1362 #address-cells = <1>;
1518 #size-cells = 1363 #size-cells = <0>;
1519 status = "dis 1364 status = "disabled";
1520 }; 1365 };
1521 }; 1366 };
1522 1367
1523 gpi_dma2: dma-controller@c000 1368 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm !! 1369 compatible = "qcom,sm8150-gpi-dma";
1525 reg = <0 0x00c00000 0 !! 1370 reg = <0 0xc00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1371 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1372 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1373 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1374 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1375 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1376 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1377 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1378 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1379 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1380 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1381 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1382 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1383 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1384 dma-channels = <13>;
1540 dma-channel-mask = <0 1385 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1386 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1387 #dma-cells = <3>;
1543 status = "disabled"; 1388 status = "disabled";
1544 }; 1389 };
1545 1390
1546 qupv3_id_2: geniqup@cc0000 { 1391 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1392 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1393 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1394
1550 clock-names = "m-ahb" 1395 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1396 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1397 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1398 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1399 #address-cells = <2>;
1555 #size-cells = <2>; 1400 #size-cells = <2>;
1556 ranges; 1401 ranges;
1557 status = "disabled"; 1402 status = "disabled";
1558 1403
1559 i2c17: i2c@c80000 { 1404 i2c17: i2c@c80000 {
1560 compatible = 1405 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1406 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1407 clock-names = "se";
1563 clocks = <&gc 1408 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ <<
1565 <&gpi_ <<
1566 dma-names = " <<
1567 pinctrl-names 1409 pinctrl-names = "default";
1568 pinctrl-0 = < 1410 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1411 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1412 #address-cells = <1>;
1571 #size-cells = 1413 #size-cells = <0>;
1572 status = "dis 1414 status = "disabled";
1573 }; 1415 };
1574 1416
1575 spi17: spi@c80000 { 1417 spi17: spi@c80000 {
1576 compatible = 1418 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 !! 1419 reg = <0 0xc80000 0 0x4000>;
1578 reg-names = " 1420 reg-names = "se";
1579 clock-names = 1421 clock-names = "se";
1580 clocks = <&gc 1422 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ <<
1582 <&gpi_ <<
1583 dma-names = " <<
1584 pinctrl-names 1423 pinctrl-names = "default";
1585 pinctrl-0 = < 1424 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1425 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1426 spi-max-frequency = <50000000>;
1588 #address-cell 1427 #address-cells = <1>;
1589 #size-cells = 1428 #size-cells = <0>;
1590 status = "dis 1429 status = "disabled";
1591 }; 1430 };
1592 1431
1593 i2c18: i2c@c84000 { 1432 i2c18: i2c@c84000 {
1594 compatible = 1433 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1434 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1435 clock-names = "se";
1597 clocks = <&gc 1436 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ <<
1599 <&gpi_ <<
1600 dma-names = " <<
1601 pinctrl-names 1437 pinctrl-names = "default";
1602 pinctrl-0 = < 1438 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1439 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1440 #address-cells = <1>;
1605 #size-cells = 1441 #size-cells = <0>;
1606 status = "dis 1442 status = "disabled";
1607 }; 1443 };
1608 1444
1609 spi18: spi@c84000 { 1445 spi18: spi@c84000 {
1610 compatible = 1446 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 !! 1447 reg = <0 0xc84000 0 0x4000>;
1612 reg-names = " 1448 reg-names = "se";
1613 clock-names = 1449 clock-names = "se";
1614 clocks = <&gc 1450 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ <<
1616 <&gpi_ <<
1617 dma-names = " <<
1618 pinctrl-names 1451 pinctrl-names = "default";
1619 pinctrl-0 = < 1452 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1453 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1454 spi-max-frequency = <50000000>;
1622 #address-cell 1455 #address-cells = <1>;
1623 #size-cells = 1456 #size-cells = <0>;
1624 status = "dis 1457 status = "disabled";
1625 }; 1458 };
1626 1459
1627 i2c19: i2c@c88000 { 1460 i2c19: i2c@c88000 {
1628 compatible = 1461 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1462 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1463 clock-names = "se";
1631 clocks = <&gc 1464 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 pinctrl-names 1465 pinctrl-names = "default";
1636 pinctrl-0 = < 1466 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1467 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1468 #address-cells = <1>;
1639 #size-cells = 1469 #size-cells = <0>;
1640 status = "dis 1470 status = "disabled";
1641 }; 1471 };
1642 1472
1643 spi19: spi@c88000 { 1473 spi19: spi@c88000 {
1644 compatible = 1474 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 !! 1475 reg = <0 0xc88000 0 0x4000>;
1646 reg-names = " 1476 reg-names = "se";
1647 clock-names = 1477 clock-names = "se";
1648 clocks = <&gc 1478 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ <<
1650 <&gpi_ <<
1651 dma-names = " <<
1652 pinctrl-names 1479 pinctrl-names = "default";
1653 pinctrl-0 = < 1480 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1481 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1482 spi-max-frequency = <50000000>;
1656 #address-cell 1483 #address-cells = <1>;
1657 #size-cells = 1484 #size-cells = <0>;
1658 status = "dis 1485 status = "disabled";
1659 }; 1486 };
1660 1487
1661 i2c13: i2c@c8c000 { 1488 i2c13: i2c@c8c000 {
1662 compatible = 1489 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1490 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1491 clock-names = "se";
1665 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ <<
1667 <&gpi_ <<
1668 dma-names = " <<
1669 pinctrl-names 1493 pinctrl-names = "default";
1670 pinctrl-0 = < 1494 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1495 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1496 #address-cells = <1>;
1673 #size-cells = 1497 #size-cells = <0>;
1674 status = "dis 1498 status = "disabled";
1675 }; 1499 };
1676 1500
1677 spi13: spi@c8c000 { 1501 spi13: spi@c8c000 {
1678 compatible = 1502 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 !! 1503 reg = <0 0xc8c000 0 0x4000>;
1680 reg-names = " 1504 reg-names = "se";
1681 clock-names = 1505 clock-names = "se";
1682 clocks = <&gc 1506 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ <<
1684 <&gpi_ <<
1685 dma-names = " <<
1686 pinctrl-names 1507 pinctrl-names = "default";
1687 pinctrl-0 = < 1508 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1509 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1510 spi-max-frequency = <50000000>;
1690 #address-cell 1511 #address-cells = <1>;
1691 #size-cells = 1512 #size-cells = <0>;
1692 status = "dis 1513 status = "disabled";
1693 }; 1514 };
1694 1515
1695 i2c14: i2c@c90000 { 1516 i2c14: i2c@c90000 {
1696 compatible = 1517 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1518 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1519 clock-names = "se";
1699 clocks = <&gc 1520 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ <<
1701 <&gpi_ <<
1702 dma-names = " <<
1703 pinctrl-names 1521 pinctrl-names = "default";
1704 pinctrl-0 = < 1522 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1523 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1524 #address-cells = <1>;
1707 #size-cells = 1525 #size-cells = <0>;
1708 status = "dis 1526 status = "disabled";
1709 }; 1527 };
1710 1528
1711 spi14: spi@c90000 { 1529 spi14: spi@c90000 {
1712 compatible = 1530 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 !! 1531 reg = <0 0xc90000 0 0x4000>;
1714 reg-names = " 1532 reg-names = "se";
1715 clock-names = 1533 clock-names = "se";
1716 clocks = <&gc 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ <<
1718 <&gpi_ <<
1719 dma-names = " <<
1720 pinctrl-names 1535 pinctrl-names = "default";
1721 pinctrl-0 = < 1536 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1537 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1538 spi-max-frequency = <50000000>;
1724 #address-cell 1539 #address-cells = <1>;
1725 #size-cells = 1540 #size-cells = <0>;
1726 status = "dis 1541 status = "disabled";
1727 }; 1542 };
1728 1543
1729 i2c15: i2c@c94000 { 1544 i2c15: i2c@c94000 {
1730 compatible = 1545 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1546 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1547 clock-names = "se";
1733 clocks = <&gc 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ <<
1735 <&gpi_ <<
1736 dma-names = " <<
1737 pinctrl-names 1549 pinctrl-names = "default";
1738 pinctrl-0 = < 1550 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1551 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1552 #address-cells = <1>;
1741 #size-cells = 1553 #size-cells = <0>;
1742 status = "dis 1554 status = "disabled";
1743 }; 1555 };
1744 1556
1745 spi15: spi@c94000 { 1557 spi15: spi@c94000 {
1746 compatible = 1558 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 !! 1559 reg = <0 0xc94000 0 0x4000>;
1748 reg-names = " 1560 reg-names = "se";
1749 clock-names = 1561 clock-names = "se";
1750 clocks = <&gc 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ <<
1752 <&gpi_ <<
1753 dma-names = " <<
1754 pinctrl-names 1563 pinctrl-names = "default";
1755 pinctrl-0 = < 1564 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1565 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1566 spi-max-frequency = <50000000>;
1758 #address-cell 1567 #address-cells = <1>;
1759 #size-cells = 1568 #size-cells = <0>;
1760 status = "dis 1569 status = "disabled";
1761 }; 1570 };
1762 }; 1571 };
1763 1572
1764 config_noc: interconnect@1500 1573 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1574 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1575 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1576 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1577 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1578 };
1770 1579
1771 system_noc: interconnect@1620 1580 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1581 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1582 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1583 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1584 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1585 };
1777 1586
1778 mc_virt: interconnect@163a000 1587 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1588 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1589 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1590 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1591 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1592 };
1784 1593
1785 aggre1_noc: interconnect@16e0 1594 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1595 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1596 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1597 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1598 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1599 };
1791 1600
1792 aggre2_noc: interconnect@1700 1601 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1602 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1603 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1604 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1605 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1606 };
1798 1607
1799 compute_noc: interconnect@172 1608 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1609 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1610 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1611 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1612 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1613 };
1805 1614
1806 mmss_noc: interconnect@174000 1615 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1616 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1617 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1618 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1619 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1620 };
1812 1621
1813 system-cache-controller@92000 1622 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1623 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 1624 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 1625 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 1626 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1627 };
1822 1628
1823 dma@10a2000 { <<
1824 compatible = "qcom,sm <<
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 <<
1832 <0 0x60000000 0 <<
1833 <0 0x60000f20 0 <<
1834 <0 0x60001000 0 <<
1835 <0 0x60100000 0 <<
1836 reg-names = "parf", " <<
1837 device_type = "pci"; <<
1838 linux,pci-domain = <0 <<
1839 bus-range = <0x00 0xf <<
1840 num-lanes = <1>; <<
1841 <<
1842 #address-cells = <3>; <<
1843 #size-cells = <2>; <<
1844 <<
1845 ranges = <0x01000000 <<
1846 <0x02000000 <<
1847 <<
1848 interrupts = <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 <<
1865 interrupt-map-mask = <<
1866 interrupt-map = <0 0 <<
1867 <0 0 <<
1868 <0 0 <<
1869 <0 0 <<
1870 <<
1871 clocks = <&gcc GCC_PC <<
1872 <&gcc GCC_PC <<
1873 <&gcc GCC_PC <<
1874 <&gcc GCC_PC <<
1875 <&gcc GCC_PC <<
1876 <&gcc GCC_PC <<
1877 <&gcc GCC_AG <<
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", <<
1880 "aux", <<
1881 "cfg", <<
1882 "bus_ma <<
1883 "bus_sl <<
1884 "slave_ <<
1885 "tbu", <<
1886 "ref"; <<
1887 <<
1888 iommu-map = <0x0 &a <<
1889 <0x100 &a <<
1890 <<
1891 resets = <&gcc GCC_PC <<
1892 reset-names = "pci"; <<
1893 <<
1894 power-domains = <&gcc <<
1895 <<
1896 phys = <&pcie0_phy>; <<
1897 phy-names = "pciephy" <<
1898 <<
1899 perst-gpios = <&tlmm <<
1900 wake-gpios = <&tlmm 3 <<
1901 <<
1902 pinctrl-names = "defa <<
1903 pinctrl-0 = <&pcie0_d <<
1904 <<
1905 status = "disabled"; <<
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; <<
1917 <<
1918 pcie0_phy: phy@1c06000 { <<
1919 compatible = "qcom,sm <<
1920 reg = <0 0x01c06000 0 <<
1921 clocks = <&gcc GCC_PC <<
1922 <&gcc GCC_PC <<
1923 <&gcc GCC_PC <<
1924 <&gcc GCC_PC <<
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 <<
1937 resets = <&gcc GCC_PC <<
1938 reset-names = "phy"; <<
1939 <<
1940 assigned-clocks = <&g <<
1941 assigned-clock-rates <<
1942 <<
1943 status = "disabled"; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@1c08000 { <<
1947 compatible = "qcom,pc <<
1948 reg = <0 0x01c08000 0 <<
1949 <0 0x40000000 0 <<
1950 <0 0x40000f20 0 <<
1951 <0 0x40001000 0 <<
1952 <0 0x40100000 0 <<
1953 reg-names = "parf", " <<
1954 device_type = "pci"; <<
1955 linux,pci-domain = <1 <<
1956 bus-range = <0x00 0xf <<
1957 num-lanes = <2>; <<
1958 <<
1959 #address-cells = <3>; <<
1960 #size-cells = <2>; <<
1961 <<
1962 ranges = <0x01000000 <<
1963 <0x02000000 <<
1964 <<
1965 interrupts = <GIC_SPI <<
1966 <GIC_SPI <<
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 <<
1982 interrupt-map-mask = <<
1983 interrupt-map = <0 0 <<
1984 <0 0 <<
1985 <0 0 <<
1986 <0 0 <<
1987 <<
1988 clocks = <&gcc GCC_PC <<
1989 <&gcc GCC_PC <<
1990 <&gcc GCC_PC <<
1991 <&gcc GCC_PC <<
1992 <&gcc GCC_PC <<
1993 <&gcc GCC_PC <<
1994 <&gcc GCC_AG <<
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", <<
1997 "aux", <<
1998 "cfg", <<
1999 "bus_ma <<
2000 "bus_sl <<
2001 "slave_ <<
2002 "tbu", <<
2003 "ref"; <<
2004 <<
2005 assigned-clocks = <&g <<
2006 assigned-clock-rates <<
2007 <<
2008 iommu-map = <0x0 &a <<
2009 <0x100 &a <<
2010 <<
2011 resets = <&gcc GCC_PC <<
2012 reset-names = "pci"; <<
2013 <<
2014 power-domains = <&gcc <<
2015 <<
2016 phys = <&pcie1_phy>; <<
2017 phy-names = "pciephy" <<
2018 <<
2019 perst-gpios = <&tlmm <<
2020 enable-gpio = <&tlmm <<
2021 <<
2022 pinctrl-names = "defa <<
2023 pinctrl-0 = <&pcie1_d <<
2024 <<
2025 status = "disabled"; <<
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; <<
2037 <<
2038 pcie1_phy: phy@1c0e000 { <<
2039 compatible = "qcom,sm <<
2040 reg = <0 0x01c0e000 0 <<
2041 clocks = <&gcc GCC_PC <<
2042 <&gcc GCC_PC <<
2043 <&gcc GCC_PC <<
2044 <&gcc GCC_PC <<
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 <<
2057 resets = <&gcc GCC_PC <<
2058 reset-names = "phy"; <<
2059 <<
2060 assigned-clocks = <&g <<
2061 assigned-clock-rates <<
2062 <<
2063 status = "disabled"; <<
2064 }; <<
2065 <<
2066 ufs_mem_hc: ufshc@1d84000 { 1629 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 1630 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 1631 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 1632 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 1633 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 1634 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 1635 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 1636 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 1637 phy-names = "ufsphy";
2075 lanes-per-direction = 1638 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 1639 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 1640 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 1641 reset-names = "rst";
2079 1642
2080 iommus = <&apps_smmu 1643 iommus = <&apps_smmu 0x300 0>;
2081 1644
2082 clock-names = 1645 clock-names =
2083 "core_clk", 1646 "core_clk",
2084 "bus_aggr_clk 1647 "bus_aggr_clk",
2085 "iface_clk", 1648 "iface_clk",
2086 "core_clk_uni 1649 "core_clk_unipro",
2087 "ref_clk", 1650 "ref_clk",
2088 "tx_lane0_syn 1651 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 1652 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 1653 "rx_lane1_sync_clk",
2091 "ice_core_clk 1654 "ice_core_clk";
2092 clocks = 1655 clocks =
2093 <&gcc GCC_UFS 1656 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 1657 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 1658 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 1659 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 1660 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 1661 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 1662 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1663 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 1664 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 1665 freq-table-hz =
2103 <37500000 300 1666 <37500000 300000000>,
2104 <0 0>, 1667 <0 0>,
2105 <0 0>, 1668 <0 0>,
2106 <37500000 300 1669 <37500000 300000000>,
2107 <0 0>, 1670 <0 0>,
2108 <0 0>, 1671 <0 0>,
2109 <0 0>, 1672 <0 0>,
2110 <0 0>, 1673 <0 0>,
2111 <0 300000000> 1674 <0 300000000>;
2112 1675
2113 status = "disabled"; 1676 status = "disabled";
2114 }; 1677 };
2115 1678
2116 ufs_mem_phy: phy@1d87000 { 1679 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 1680 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 1681 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 1682 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 1683 #size-cells = <2>;
2121 <&gcc GCC_UF !! 1684 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 1685 clock-names = "ref",
2124 "ref_au !! 1686 "ref_aux";
2125 "qref"; !! 1687 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2126 !! 1688 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2127 power-domains = <&gcc <<
2128 1689
2129 resets = <&ufs_mem_hc 1690 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 1691 reset-names = "ufsphy";
>> 1692 status = "disabled";
2131 1693
2132 #phy-cells = <0>; !! 1694 ufs_mem_phy_lanes: phy@1d87400 {
>> 1695 reg = <0 0x01d87400 0 0x108>,
>> 1696 <0 0x01d87600 0 0x1e0>,
>> 1697 <0 0x01d87c00 0 0x1dc>,
>> 1698 <0 0x01d87800 0 0x108>,
>> 1699 <0 0x01d87a00 0 0x1e0>;
>> 1700 #phy-cells = <0>;
>> 1701 };
>> 1702 };
2133 1703
2134 status = "disabled"; !! 1704 ipa_virt: interconnect@1e00000 {
>> 1705 compatible = "qcom,sm8150-ipa-virt";
>> 1706 reg = <0 0x01e00000 0 0x1000>;
>> 1707 #interconnect-cells = <1>;
>> 1708 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 1709 };
2136 1710
2137 cryptobam: dma-controller@1dc !! 1711 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 1712 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 1713 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 1714 };
2177 1715
2178 remoteproc_slpi: remoteproc@2 1716 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 1717 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 1718 reg = <0x0 0x02400000 0x0 0x4040>;
2181 1719
2182 interrupts-extended = 1720 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 1721 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 1722 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 1723 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 1724 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 1725 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 1726 "handover", "stop-ack";
2189 1727
2190 clocks = <&rpmhcc RPM 1728 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 1729 clock-names = "xo";
2192 1730
2193 power-domains = <&rpm !! 1731 power-domains = <&rpmhpd 3>,
2194 <&rpm !! 1732 <&rpmhpd 2>;
2195 power-domain-names = 1733 power-domain-names = "lcx", "lmx";
2196 1734
2197 memory-region = <&slp 1735 memory-region = <&slpi_mem>;
2198 1736
2199 qcom,qmp = <&aoss_qmp 1737 qcom,qmp = <&aoss_qmp>;
2200 1738
2201 qcom,smem-states = <& 1739 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 1740 qcom,smem-state-names = "stop";
2203 1741
2204 status = "disabled"; 1742 status = "disabled";
2205 1743
2206 glink-edge { 1744 glink-edge {
2207 interrupts = 1745 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 1746 label = "dsps";
2209 qcom,remote-p 1747 qcom,remote-pid = <3>;
2210 mboxes = <&ap 1748 mboxes = <&apss_shared 24>;
2211 1749
2212 fastrpc { 1750 fastrpc {
2213 compa 1751 compatible = "qcom,fastrpc";
2214 qcom, 1752 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 1753 label = "sdsp";
2216 qcom, <<
2217 #addr 1754 #address-cells = <1>;
2218 #size 1755 #size-cells = <0>;
2219 1756
2220 compu 1757 compute-cb@1 {
2221 1758 compatible = "qcom,fastrpc-compute-cb";
2222 1759 reg = <1>;
2223 1760 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 1761 };
2225 1762
2226 compu 1763 compute-cb@2 {
2227 1764 compatible = "qcom,fastrpc-compute-cb";
2228 1765 reg = <2>;
2229 1766 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 1767 };
2231 1768
2232 compu 1769 compute-cb@3 {
2233 1770 compatible = "qcom,fastrpc-compute-cb";
2234 1771 reg = <3>;
2235 1772 iommus = <&apps_smmu 0x05a3 0x0>;
2236 1773 /* note: shared-cb = <4> in downstream */
2237 }; 1774 };
2238 }; 1775 };
2239 }; 1776 };
2240 }; 1777 };
2241 1778
2242 gpu: gpu@2c00000 { 1779 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 1780 /*
>> 1781 * note: the amd,imageon compatible makes it possible
>> 1782 * to use the drm/msm driver without the display node,
>> 1783 * make sure to remove it when display node is added
>> 1784 */
>> 1785 compatible = "qcom,adreno-640.1",
>> 1786 "qcom,adreno",
>> 1787 "amd,imageon";
>> 1788
2244 reg = <0 0x02c00000 0 1789 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 1790 reg-names = "kgsl_3d0_reg_memory";
2246 1791
2247 interrupts = <GIC_SPI 1792 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 1793
2249 iommus = <&adreno_smm 1794 iommus = <&adreno_smmu 0 0x401>;
2250 1795
2251 operating-points-v2 = 1796 operating-points-v2 = <&gpu_opp_table>;
2252 1797
2253 qcom,gmu = <&gmu>; 1798 qcom,gmu = <&gmu>;
2254 1799
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 1800 status = "disabled";
2260 1801
2261 zap-shader { 1802 zap-shader {
2262 memory-region 1803 memory-region = <&gpu_mem>;
2263 }; 1804 };
2264 1805
>> 1806 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 1807 gpu_opp_table: opp-table {
2266 compatible = 1808 compatible = "operating-points-v2";
2267 1809
2268 opp-675000000 1810 opp-675000000 {
2269 opp-h 1811 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 1812 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 1813 };
2273 1814
2274 opp-585000000 1815 opp-585000000 {
2275 opp-h 1816 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 1817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 1818 };
2279 1819
2280 opp-499200000 1820 opp-499200000 {
2281 opp-h 1821 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 1822 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 1823 };
2285 1824
2286 opp-427000000 1825 opp-427000000 {
2287 opp-h 1826 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 1827 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 1828 };
2291 1829
2292 opp-345000000 1830 opp-345000000 {
2293 opp-h 1831 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 1832 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 1833 };
2297 1834
2298 opp-257000000 1835 opp-257000000 {
2299 opp-h 1836 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 1837 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 1838 };
2303 }; 1839 };
2304 }; 1840 };
2305 1841
2306 gmu: gmu@2c6a000 { 1842 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 1843 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 1844
2309 reg = <0 0x02c6a000 0 1845 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 1846 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 1847 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 1848 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 1849
2314 interrupts = <GIC_SPI 1850 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1851 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 1852 interrupt-names = "hfi", "gmu";
2317 1853
2318 clocks = <&gpucc GPU_ 1854 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 1855 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 1856 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 1857 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 1858 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 1859 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 1860
2325 power-domains = <&gpu 1861 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 1862 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 1863 power-domain-names = "cx", "gx";
2328 1864
2329 iommus = <&adreno_smm 1865 iommus = <&adreno_smmu 5 0x400>;
2330 1866
2331 operating-points-v2 = 1867 operating-points-v2 = <&gmu_opp_table>;
2332 1868
2333 status = "disabled"; 1869 status = "disabled";
2334 1870
2335 gmu_opp_table: opp-ta 1871 gmu_opp_table: opp-table {
2336 compatible = 1872 compatible = "operating-points-v2";
2337 1873
2338 opp-200000000 1874 opp-200000000 {
2339 opp-h 1875 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 1876 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 1877 };
2342 }; 1878 };
2343 }; 1879 };
2344 1880
2345 gpucc: clock-controller@2c900 1881 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 1882 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 1883 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 1884 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 1885 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 1886 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 1887 clock-names = "bi_tcxo",
2352 "gcc_gp 1888 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 1889 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 1890 #clock-cells = <1>;
2355 #reset-cells = <1>; 1891 #reset-cells = <1>;
2356 #power-domain-cells = 1892 #power-domain-cells = <1>;
2357 }; 1893 };
2358 1894
2359 adreno_smmu: iommu@2ca0000 { 1895 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 1896 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 1897 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 1898 #iommu-cells = <2>;
2364 #global-interrupts = 1899 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 1900 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 1901 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 1902 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 1903 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 1904 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 1905 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 1906 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 1907 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 1908 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 1909 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 1910 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 1911 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 1912 clock-names = "ahb", "bus", "iface";
2378 1913
2379 power-domains = <&gpu 1914 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 1915 };
2381 1916
2382 tlmm: pinctrl@3100000 { 1917 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 1918 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 1919 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 1920 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 1921 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 1922 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 1923 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 1924 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 1925 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 1926 gpio-controller;
2392 #gpio-cells = <2>; 1927 #gpio-cells = <2>;
2393 interrupt-controller; 1928 interrupt-controller;
2394 #interrupt-cells = <2 1929 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc <<
2396 1930
2397 qup_i2c0_default: qup !! 1931 qup_i2c0_default: qup-i2c0-default {
2398 pins = "gpio0 !! 1932 mux {
2399 function = "q !! 1933 pins = "gpio0", "gpio1";
2400 drive-strengt !! 1934 function = "qup0";
2401 bias-disable; !! 1935 };
>> 1936
>> 1937 config {
>> 1938 pins = "gpio0", "gpio1";
>> 1939 drive-strength = <0x02>;
>> 1940 bias-disable;
>> 1941 };
2402 }; 1942 };
2403 1943
2404 qup_spi0_default: qup !! 1944 qup_spi0_default: qup-spi0-default {
2405 pins = "gpio0 1945 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 1946 function = "qup0";
2407 drive-strengt 1947 drive-strength = <6>;
2408 bias-disable; 1948 bias-disable;
2409 }; 1949 };
2410 1950
2411 qup_i2c1_default: qup !! 1951 qup_i2c1_default: qup-i2c1-default {
2412 pins = "gpio1 !! 1952 mux {
2413 function = "q !! 1953 pins = "gpio114", "gpio115";
2414 drive-strengt !! 1954 function = "qup1";
2415 bias-disable; !! 1955 };
>> 1956
>> 1957 config {
>> 1958 pins = "gpio114", "gpio115";
>> 1959 drive-strength = <0x02>;
>> 1960 bias-disable;
>> 1961 };
2416 }; 1962 };
2417 1963
2418 qup_spi1_default: qup !! 1964 qup_spi1_default: qup-spi1-default {
2419 pins = "gpio1 1965 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 1966 function = "qup1";
2421 drive-strengt 1967 drive-strength = <6>;
2422 bias-disable; 1968 bias-disable;
2423 }; 1969 };
2424 1970
2425 qup_i2c2_default: qup !! 1971 qup_i2c2_default: qup-i2c2-default {
2426 pins = "gpio1 !! 1972 mux {
2427 function = "q !! 1973 pins = "gpio126", "gpio127";
2428 drive-strengt !! 1974 function = "qup2";
2429 bias-disable; !! 1975 };
>> 1976
>> 1977 config {
>> 1978 pins = "gpio126", "gpio127";
>> 1979 drive-strength = <0x02>;
>> 1980 bias-disable;
>> 1981 };
2430 }; 1982 };
2431 1983
2432 qup_spi2_default: qup !! 1984 qup_spi2_default: qup-spi2-default {
2433 pins = "gpio1 1985 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 1986 function = "qup2";
2435 drive-strengt 1987 drive-strength = <6>;
2436 bias-disable; 1988 bias-disable;
2437 }; 1989 };
2438 1990
2439 qup_i2c3_default: qup !! 1991 qup_i2c3_default: qup-i2c3-default {
2440 pins = "gpio1 !! 1992 mux {
2441 function = "q !! 1993 pins = "gpio144", "gpio145";
2442 drive-strengt !! 1994 function = "qup3";
2443 bias-disable; !! 1995 };
>> 1996
>> 1997 config {
>> 1998 pins = "gpio144", "gpio145";
>> 1999 drive-strength = <0x02>;
>> 2000 bias-disable;
>> 2001 };
2444 }; 2002 };
2445 2003
2446 qup_spi3_default: qup !! 2004 qup_spi3_default: qup-spi3-default {
2447 pins = "gpio1 2005 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2006 function = "qup3";
2449 drive-strengt 2007 drive-strength = <6>;
2450 bias-disable; 2008 bias-disable;
2451 }; 2009 };
2452 2010
2453 qup_i2c4_default: qup !! 2011 qup_i2c4_default: qup-i2c4-default {
2454 pins = "gpio5 !! 2012 mux {
2455 function = "q !! 2013 pins = "gpio51", "gpio52";
2456 drive-strengt !! 2014 function = "qup4";
2457 bias-disable; !! 2015 };
>> 2016
>> 2017 config {
>> 2018 pins = "gpio51", "gpio52";
>> 2019 drive-strength = <0x02>;
>> 2020 bias-disable;
>> 2021 };
2458 }; 2022 };
2459 2023
2460 qup_spi4_default: qup !! 2024 qup_spi4_default: qup-spi4-default {
2461 pins = "gpio5 2025 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2026 function = "qup4";
2463 drive-strengt 2027 drive-strength = <6>;
2464 bias-disable; 2028 bias-disable;
2465 }; 2029 };
2466 2030
2467 qup_i2c5_default: qup !! 2031 qup_i2c5_default: qup-i2c5-default {
2468 pins = "gpio1 !! 2032 mux {
2469 function = "q !! 2033 pins = "gpio121", "gpio122";
2470 drive-strengt !! 2034 function = "qup5";
2471 bias-disable; !! 2035 };
>> 2036
>> 2037 config {
>> 2038 pins = "gpio121", "gpio122";
>> 2039 drive-strength = <0x02>;
>> 2040 bias-disable;
>> 2041 };
2472 }; 2042 };
2473 2043
2474 qup_spi5_default: qup !! 2044 qup_spi5_default: qup-spi5-default {
2475 pins = "gpio1 2045 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2046 function = "qup5";
2477 drive-strengt 2047 drive-strength = <6>;
2478 bias-disable; 2048 bias-disable;
2479 }; 2049 };
2480 2050
2481 qup_i2c6_default: qup !! 2051 qup_i2c6_default: qup-i2c6-default {
2482 pins = "gpio6 !! 2052 mux {
2483 function = "q !! 2053 pins = "gpio6", "gpio7";
2484 drive-strengt !! 2054 function = "qup6";
2485 bias-disable; !! 2055 };
>> 2056
>> 2057 config {
>> 2058 pins = "gpio6", "gpio7";
>> 2059 drive-strength = <0x02>;
>> 2060 bias-disable;
>> 2061 };
2486 }; 2062 };
2487 2063
2488 qup_spi6_default: qup !! 2064 qup_spi6_default: qup-spi6_default {
2489 pins = "gpio4 2065 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2066 function = "qup6";
2491 drive-strengt 2067 drive-strength = <6>;
2492 bias-disable; 2068 bias-disable;
2493 }; 2069 };
2494 2070
2495 qup_i2c7_default: qup !! 2071 qup_i2c7_default: qup-i2c7-default {
2496 pins = "gpio9 !! 2072 mux {
2497 function = "q !! 2073 pins = "gpio98", "gpio99";
2498 drive-strengt !! 2074 function = "qup7";
2499 bias-disable; !! 2075 };
>> 2076
>> 2077 config {
>> 2078 pins = "gpio98", "gpio99";
>> 2079 drive-strength = <0x02>;
>> 2080 bias-disable;
>> 2081 };
2500 }; 2082 };
2501 2083
2502 qup_spi7_default: qup !! 2084 qup_spi7_default: qup-spi7_default {
2503 pins = "gpio9 2085 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2086 function = "qup7";
2505 drive-strengt 2087 drive-strength = <6>;
2506 bias-disable; 2088 bias-disable;
2507 }; 2089 };
2508 2090
2509 qup_i2c8_default: qup !! 2091 qup_i2c8_default: qup-i2c8-default {
2510 pins = "gpio8 !! 2092 mux {
2511 function = "q !! 2093 pins = "gpio88", "gpio89";
2512 drive-strengt !! 2094 function = "qup8";
2513 bias-disable; !! 2095 };
>> 2096
>> 2097 config {
>> 2098 pins = "gpio88", "gpio89";
>> 2099 drive-strength = <0x02>;
>> 2100 bias-disable;
>> 2101 };
2514 }; 2102 };
2515 2103
2516 qup_spi8_default: qup !! 2104 qup_spi8_default: qup-spi8-default {
2517 pins = "gpio8 2105 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2106 function = "qup8";
2519 drive-strengt 2107 drive-strength = <6>;
2520 bias-disable; 2108 bias-disable;
2521 }; 2109 };
2522 2110
2523 qup_i2c9_default: qup !! 2111 qup_i2c9_default: qup-i2c9-default {
2524 pins = "gpio3 !! 2112 mux {
2525 function = "q !! 2113 pins = "gpio39", "gpio40";
2526 drive-strengt !! 2114 function = "qup9";
2527 bias-disable; !! 2115 };
>> 2116
>> 2117 config {
>> 2118 pins = "gpio39", "gpio40";
>> 2119 drive-strength = <0x02>;
>> 2120 bias-disable;
>> 2121 };
2528 }; 2122 };
2529 2123
2530 qup_spi9_default: qup !! 2124 qup_spi9_default: qup-spi9-default {
2531 pins = "gpio3 2125 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2126 function = "qup9";
2533 drive-strengt 2127 drive-strength = <6>;
2534 bias-disable; 2128 bias-disable;
2535 }; 2129 };
2536 2130
2537 qup_uart9_default: qu !! 2131 qup_i2c10_default: qup-i2c10-default {
2538 pins = "gpio4 !! 2132 mux {
2539 function = "q !! 2133 pins = "gpio9", "gpio10";
2540 drive-strengt !! 2134 function = "qup10";
2541 bias-disable; !! 2135 };
2542 }; <<
2543 2136
2544 qup_i2c10_default: qu !! 2137 config {
2545 pins = "gpio9 !! 2138 pins = "gpio9", "gpio10";
2546 function = "q !! 2139 drive-strength = <0x02>;
2547 drive-strengt !! 2140 bias-disable;
2548 bias-disable; !! 2141 };
2549 }; 2142 };
2550 2143
2551 qup_spi10_default: qu !! 2144 qup_spi10_default: qup-spi10-default {
2552 pins = "gpio9 2145 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2146 function = "qup10";
2554 drive-strengt 2147 drive-strength = <6>;
2555 bias-disable; 2148 bias-disable;
2556 }; 2149 };
2557 2150
2558 qup_i2c11_default: qu !! 2151 qup_i2c11_default: qup-i2c11-default {
2559 pins = "gpio9 !! 2152 mux {
2560 function = "q !! 2153 pins = "gpio94", "gpio95";
2561 drive-strengt !! 2154 function = "qup11";
2562 bias-disable; !! 2155 };
>> 2156
>> 2157 config {
>> 2158 pins = "gpio94", "gpio95";
>> 2159 drive-strength = <0x02>;
>> 2160 bias-disable;
>> 2161 };
2563 }; 2162 };
2564 2163
2565 qup_spi11_default: qu !! 2164 qup_spi11_default: qup-spi11-default {
2566 pins = "gpio9 2165 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2166 function = "qup11";
2568 drive-strengt 2167 drive-strength = <6>;
2569 bias-disable; 2168 bias-disable;
2570 }; 2169 };
2571 2170
2572 qup_i2c12_default: qu !! 2171 qup_i2c12_default: qup-i2c12-default {
2573 pins = "gpio8 !! 2172 mux {
2574 function = "q !! 2173 pins = "gpio83", "gpio84";
2575 drive-strengt !! 2174 function = "qup12";
2576 bias-disable; !! 2175 };
>> 2176
>> 2177 config {
>> 2178 pins = "gpio83", "gpio84";
>> 2179 drive-strength = <0x02>;
>> 2180 bias-disable;
>> 2181 };
2577 }; 2182 };
2578 2183
2579 qup_spi12_default: qu !! 2184 qup_spi12_default: qup-spi12-default {
2580 pins = "gpio8 2185 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2186 function = "qup12";
2582 drive-strengt 2187 drive-strength = <6>;
2583 bias-disable; 2188 bias-disable;
2584 }; 2189 };
2585 2190
2586 qup_i2c13_default: qu !! 2191 qup_i2c13_default: qup-i2c13-default {
2587 pins = "gpio4 !! 2192 mux {
2588 function = "q !! 2193 pins = "gpio43", "gpio44";
2589 drive-strengt !! 2194 function = "qup13";
2590 bias-disable; !! 2195 };
>> 2196
>> 2197 config {
>> 2198 pins = "gpio43", "gpio44";
>> 2199 drive-strength = <0x02>;
>> 2200 bias-disable;
>> 2201 };
2591 }; 2202 };
2592 2203
2593 qup_spi13_default: qu !! 2204 qup_spi13_default: qup-spi13-default {
2594 pins = "gpio4 2205 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2206 function = "qup13";
2596 drive-strengt 2207 drive-strength = <6>;
2597 bias-disable; 2208 bias-disable;
2598 }; 2209 };
2599 2210
2600 qup_i2c14_default: qu !! 2211 qup_i2c14_default: qup-i2c14-default {
2601 pins = "gpio4 !! 2212 mux {
2602 function = "q !! 2213 pins = "gpio47", "gpio48";
2603 drive-strengt !! 2214 function = "qup14";
2604 bias-disable; !! 2215 };
>> 2216
>> 2217 config {
>> 2218 pins = "gpio47", "gpio48";
>> 2219 drive-strength = <0x02>;
>> 2220 bias-disable;
>> 2221 };
2605 }; 2222 };
2606 2223
2607 qup_spi14_default: qu !! 2224 qup_spi14_default: qup-spi14-default {
2608 pins = "gpio4 2225 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2226 function = "qup14";
2610 drive-strengt 2227 drive-strength = <6>;
2611 bias-disable; 2228 bias-disable;
2612 }; 2229 };
2613 2230
2614 qup_i2c15_default: qu !! 2231 qup_i2c15_default: qup-i2c15-default {
2615 pins = "gpio2 !! 2232 mux {
2616 function = "q !! 2233 pins = "gpio27", "gpio28";
2617 drive-strengt !! 2234 function = "qup15";
2618 bias-disable; !! 2235 };
>> 2236
>> 2237 config {
>> 2238 pins = "gpio27", "gpio28";
>> 2239 drive-strength = <0x02>;
>> 2240 bias-disable;
>> 2241 };
2619 }; 2242 };
2620 2243
2621 qup_spi15_default: qu !! 2244 qup_spi15_default: qup-spi15-default {
2622 pins = "gpio2 2245 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2246 function = "qup15";
2624 drive-strengt 2247 drive-strength = <6>;
2625 bias-disable; 2248 bias-disable;
2626 }; 2249 };
2627 2250
2628 qup_i2c16_default: qu !! 2251 qup_i2c16_default: qup-i2c16-default {
2629 pins = "gpio8 !! 2252 mux {
2630 function = "q !! 2253 pins = "gpio86", "gpio85";
2631 drive-strengt !! 2254 function = "qup16";
2632 bias-disable; !! 2255 };
>> 2256
>> 2257 config {
>> 2258 pins = "gpio86", "gpio85";
>> 2259 drive-strength = <0x02>;
>> 2260 bias-disable;
>> 2261 };
2633 }; 2262 };
2634 2263
2635 qup_spi16_default: qu !! 2264 qup_spi16_default: qup-spi16-default {
2636 pins = "gpio8 2265 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2266 function = "qup16";
2638 drive-strengt 2267 drive-strength = <6>;
2639 bias-disable; 2268 bias-disable;
2640 }; 2269 };
2641 2270
2642 qup_i2c17_default: qu !! 2271 qup_i2c17_default: qup-i2c17-default {
2643 pins = "gpio5 !! 2272 mux {
2644 function = "q !! 2273 pins = "gpio55", "gpio56";
2645 drive-strengt !! 2274 function = "qup17";
2646 bias-disable; !! 2275 };
>> 2276
>> 2277 config {
>> 2278 pins = "gpio55", "gpio56";
>> 2279 drive-strength = <0x02>;
>> 2280 bias-disable;
>> 2281 };
2647 }; 2282 };
2648 2283
2649 qup_spi17_default: qu !! 2284 qup_spi17_default: qup-spi17-default {
2650 pins = "gpio5 2285 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2286 function = "qup17";
2652 drive-strengt 2287 drive-strength = <6>;
2653 bias-disable; 2288 bias-disable;
2654 }; 2289 };
2655 2290
2656 qup_i2c18_default: qu !! 2291 qup_i2c18_default: qup-i2c18-default {
2657 pins = "gpio2 !! 2292 mux {
2658 function = "q !! 2293 pins = "gpio23", "gpio24";
2659 drive-strengt !! 2294 function = "qup18";
2660 bias-disable; !! 2295 };
>> 2296
>> 2297 config {
>> 2298 pins = "gpio23", "gpio24";
>> 2299 drive-strength = <0x02>;
>> 2300 bias-disable;
>> 2301 };
2661 }; 2302 };
2662 2303
2663 qup_spi18_default: qu !! 2304 qup_spi18_default: qup-spi18-default {
2664 pins = "gpio2 2305 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2306 function = "qup18";
2666 drive-strengt 2307 drive-strength = <6>;
2667 bias-disable; 2308 bias-disable;
2668 }; 2309 };
2669 2310
2670 qup_i2c19_default: qu !! 2311 qup_i2c19_default: qup-i2c19-default {
2671 pins = "gpio5 !! 2312 mux {
2672 function = "q !! 2313 pins = "gpio57", "gpio58";
2673 drive-strengt !! 2314 function = "qup19";
2674 bias-disable; !! 2315 };
>> 2316
>> 2317 config {
>> 2318 pins = "gpio57", "gpio58";
>> 2319 drive-strength = <0x02>;
>> 2320 bias-disable;
>> 2321 };
2675 }; 2322 };
2676 2323
2677 qup_spi19_default: qu !! 2324 qup_spi19_default: qup-spi19-default {
2678 pins = "gpio5 2325 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2326 function = "qup19";
2680 drive-strengt 2327 drive-strength = <6>;
2681 bias-disable; 2328 bias-disable;
2682 }; 2329 };
2683 <<
2684 pcie0_default_state: <<
2685 perst-pins { <<
2686 pins <<
2687 funct <<
2688 drive <<
2689 bias- <<
2690 }; <<
2691 <<
2692 clkreq-pins { <<
2693 pins <<
2694 funct <<
2695 drive <<
2696 bias- <<
2697 }; <<
2698 <<
2699 wake-pins { <<
2700 pins <<
2701 funct <<
2702 drive <<
2703 bias- <<
2704 }; <<
2705 }; <<
2706 <<
2707 pcie1_default_state: <<
2708 perst-pins { <<
2709 pins <<
2710 funct <<
2711 drive <<
2712 bias- <<
2713 }; <<
2714 <<
2715 clkreq-pins { <<
2716 pins <<
2717 funct <<
2718 drive <<
2719 bias- <<
2720 }; <<
2721 <<
2722 wake-pins { <<
2723 pins <<
2724 funct <<
2725 drive <<
2726 bias- <<
2727 }; <<
2728 }; <<
2729 }; 2330 };
2730 2331
2731 remoteproc_mpss: remoteproc@4 2332 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2333 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2334 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2335
2735 interrupts-extended = 2336 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2337 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2338 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2339 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2340 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2341 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2342 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2343 "stop-ack", "shutdown-ack";
2743 2344
2744 clocks = <&rpmhcc RPM 2345 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2346 clock-names = "xo";
2746 2347
2747 power-domains = <&rpm !! 2348 power-domains = <&rpmhpd 7>,
2748 <&rpm !! 2349 <&rpmhpd 0>;
2749 power-domain-names = 2350 power-domain-names = "cx", "mss";
2750 2351
2751 memory-region = <&mps 2352 memory-region = <&mpss_mem>;
2752 2353
2753 qcom,qmp = <&aoss_qmp 2354 qcom,qmp = <&aoss_qmp>;
2754 2355
2755 qcom,smem-states = <& 2356 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2357 qcom,smem-state-names = "stop";
2757 2358
2758 status = "disabled"; 2359 status = "disabled";
2759 2360
2760 glink-edge { 2361 glink-edge {
2761 interrupts = 2362 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2363 label = "modem";
2763 qcom,remote-p 2364 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2365 mboxes = <&apss_shared 12>;
2765 }; 2366 };
2766 }; 2367 };
2767 2368
2768 stm@6002000 { 2369 stm@6002000 {
2769 compatible = "arm,cor 2370 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2371 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2372 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2373 reg-names = "stm-base", "stm-stimulus-base";
2773 2374
2774 clocks = <&aoss_qmp>; 2375 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2376 clock-names = "apb_pclk";
2776 2377
2777 out-ports { 2378 out-ports {
2778 port { 2379 port {
2779 stm_o 2380 stm_out: endpoint {
2780 2381 remote-endpoint = <&funnel0_in7>;
2781 }; 2382 };
2782 }; 2383 };
2783 }; 2384 };
2784 }; 2385 };
2785 2386
2786 funnel@6041000 { 2387 funnel@6041000 {
2787 compatible = "arm,cor 2388 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2389 reg = <0 0x06041000 0 0x1000>;
2789 2390
2790 clocks = <&aoss_qmp>; 2391 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2392 clock-names = "apb_pclk";
2792 2393
2793 out-ports { 2394 out-ports {
2794 port { 2395 port {
2795 funne 2396 funnel0_out: endpoint {
2796 2397 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2398 };
2798 }; 2399 };
2799 }; 2400 };
2800 2401
2801 in-ports { 2402 in-ports {
2802 #address-cell 2403 #address-cells = <1>;
2803 #size-cells = 2404 #size-cells = <0>;
2804 2405
2805 port@7 { 2406 port@7 {
2806 reg = 2407 reg = <7>;
2807 funne 2408 funnel0_in7: endpoint {
2808 2409 remote-endpoint = <&stm_out>;
2809 }; 2410 };
2810 }; 2411 };
2811 }; 2412 };
2812 }; 2413 };
2813 2414
2814 funnel@6042000 { 2415 funnel@6042000 {
2815 compatible = "arm,cor 2416 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2417 reg = <0 0x06042000 0 0x1000>;
2817 2418
2818 clocks = <&aoss_qmp>; 2419 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2420 clock-names = "apb_pclk";
2820 2421
2821 out-ports { 2422 out-ports {
2822 port { 2423 port {
2823 funne 2424 funnel1_out: endpoint {
2824 2425 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2426 };
2826 }; 2427 };
2827 }; 2428 };
2828 2429
2829 in-ports { 2430 in-ports {
2830 #address-cell 2431 #address-cells = <1>;
2831 #size-cells = 2432 #size-cells = <0>;
2832 2433
2833 port@4 { 2434 port@4 {
2834 reg = 2435 reg = <4>;
2835 funne 2436 funnel1_in4: endpoint {
2836 2437 remote-endpoint = <&swao_replicator_out>;
2837 }; 2438 };
2838 }; 2439 };
2839 }; 2440 };
2840 }; 2441 };
2841 2442
2842 funnel@6043000 { 2443 funnel@6043000 {
2843 compatible = "arm,cor 2444 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2445 reg = <0 0x06043000 0 0x1000>;
2845 2446
2846 clocks = <&aoss_qmp>; 2447 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2448 clock-names = "apb_pclk";
2848 2449
2849 out-ports { 2450 out-ports {
2850 port { 2451 port {
2851 funne 2452 funnel2_out: endpoint {
2852 2453 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2454 };
2854 }; 2455 };
2855 }; 2456 };
2856 2457
2857 in-ports { 2458 in-ports {
2858 #address-cell 2459 #address-cells = <1>;
2859 #size-cells = 2460 #size-cells = <0>;
2860 2461
2861 port@2 { 2462 port@2 {
2862 reg = 2463 reg = <2>;
2863 funne 2464 funnel2_in2: endpoint {
2864 2465 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2466 };
2866 }; 2467 };
2867 }; 2468 };
2868 }; 2469 };
2869 2470
2870 funnel@6045000 { 2471 funnel@6045000 {
2871 compatible = "arm,cor 2472 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2473 reg = <0 0x06045000 0 0x1000>;
2873 2474
2874 clocks = <&aoss_qmp>; 2475 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2476 clock-names = "apb_pclk";
2876 2477
2877 out-ports { 2478 out-ports {
2878 port { 2479 port {
2879 merge 2480 merge_funnel_out: endpoint {
2880 2481 remote-endpoint = <&etf_in>;
2881 }; 2482 };
2882 }; 2483 };
2883 }; 2484 };
2884 2485
2885 in-ports { 2486 in-ports {
2886 #address-cell 2487 #address-cells = <1>;
2887 #size-cells = 2488 #size-cells = <0>;
2888 2489
2889 port@0 { 2490 port@0 {
2890 reg = 2491 reg = <0>;
2891 merge 2492 merge_funnel_in0: endpoint {
2892 2493 remote-endpoint = <&funnel0_out>;
2893 }; 2494 };
2894 }; 2495 };
2895 2496
2896 port@1 { 2497 port@1 {
2897 reg = 2498 reg = <1>;
2898 merge 2499 merge_funnel_in1: endpoint {
2899 2500 remote-endpoint = <&funnel1_out>;
2900 }; 2501 };
2901 }; 2502 };
2902 2503
2903 port@2 { 2504 port@2 {
2904 reg = 2505 reg = <2>;
2905 merge 2506 merge_funnel_in2: endpoint {
2906 2507 remote-endpoint = <&funnel2_out>;
2907 }; 2508 };
2908 }; 2509 };
2909 }; 2510 };
2910 }; 2511 };
2911 2512
2912 replicator@6046000 { 2513 replicator@6046000 {
2913 compatible = "arm,cor 2514 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2515 reg = <0 0x06046000 0 0x1000>;
2915 2516
2916 clocks = <&aoss_qmp>; 2517 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2518 clock-names = "apb_pclk";
2918 2519
2919 out-ports { 2520 out-ports {
2920 #address-cell 2521 #address-cells = <1>;
2921 #size-cells = 2522 #size-cells = <0>;
2922 2523
2923 port@0 { 2524 port@0 {
2924 reg = 2525 reg = <0>;
2925 repli 2526 replicator_out0: endpoint {
2926 2527 remote-endpoint = <&etr_in>;
2927 }; 2528 };
2928 }; 2529 };
2929 2530
2930 port@1 { 2531 port@1 {
2931 reg = 2532 reg = <1>;
2932 repli 2533 replicator_out1: endpoint {
2933 2534 remote-endpoint = <&replicator1_in>;
2934 }; 2535 };
2935 }; 2536 };
2936 }; 2537 };
2937 2538
2938 in-ports { 2539 in-ports {
2939 port { 2540 port {
2940 repli 2541 replicator_in0: endpoint {
2941 2542 remote-endpoint = <&etf_out>;
2942 }; 2543 };
2943 }; 2544 };
2944 }; 2545 };
2945 }; 2546 };
2946 2547
2947 etf@6047000 { 2548 etf@6047000 {
2948 compatible = "arm,cor 2549 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2550 reg = <0 0x06047000 0 0x1000>;
2950 2551
2951 clocks = <&aoss_qmp>; 2552 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2553 clock-names = "apb_pclk";
2953 2554
2954 out-ports { 2555 out-ports {
2955 port { 2556 port {
2956 etf_o 2557 etf_out: endpoint {
2957 2558 remote-endpoint = <&replicator_in0>;
2958 }; 2559 };
2959 }; 2560 };
2960 }; 2561 };
2961 2562
2962 in-ports { 2563 in-ports {
2963 port { 2564 port {
2964 etf_i 2565 etf_in: endpoint {
2965 2566 remote-endpoint = <&merge_funnel_out>;
2966 }; 2567 };
2967 }; 2568 };
2968 }; 2569 };
2969 }; 2570 };
2970 2571
2971 etr@6048000 { 2572 etr@6048000 {
2972 compatible = "arm,cor 2573 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2574 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2575 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2576
2976 clocks = <&aoss_qmp>; 2577 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2578 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2579 arm,scatter-gather;
2979 2580
2980 in-ports { 2581 in-ports {
2981 port { 2582 port {
2982 etr_i 2583 etr_in: endpoint {
2983 2584 remote-endpoint = <&replicator_out0>;
2984 }; 2585 };
2985 }; 2586 };
2986 }; 2587 };
2987 }; 2588 };
2988 2589
2989 replicator@604a000 { 2590 replicator@604a000 {
2990 compatible = "arm,cor 2591 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2592 reg = <0 0x0604a000 0 0x1000>;
2992 2593
2993 clocks = <&aoss_qmp>; 2594 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2595 clock-names = "apb_pclk";
2995 2596
2996 out-ports { 2597 out-ports {
2997 #address-cell 2598 #address-cells = <1>;
2998 #size-cells = 2599 #size-cells = <0>;
2999 2600
3000 port@1 { 2601 port@1 {
3001 reg = 2602 reg = <1>;
3002 repli 2603 replicator1_out: endpoint {
3003 2604 remote-endpoint = <&swao_funnel_in>;
3004 }; 2605 };
3005 }; 2606 };
3006 }; 2607 };
3007 2608
3008 in-ports { 2609 in-ports {
>> 2610 #address-cells = <1>;
>> 2611 #size-cells = <0>;
3009 2612
3010 port { !! 2613 port@1 {
>> 2614 reg = <1>;
3011 repli 2615 replicator1_in: endpoint {
3012 2616 remote-endpoint = <&replicator_out1>;
3013 }; 2617 };
3014 }; 2618 };
3015 }; 2619 };
3016 }; 2620 };
3017 2621
3018 funnel@6b08000 { 2622 funnel@6b08000 {
3019 compatible = "arm,cor 2623 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2624 reg = <0 0x06b08000 0 0x1000>;
3021 2625
3022 clocks = <&aoss_qmp>; 2626 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2627 clock-names = "apb_pclk";
3024 2628
3025 out-ports { 2629 out-ports {
3026 port { 2630 port {
3027 swao_ 2631 swao_funnel_out: endpoint {
3028 2632 remote-endpoint = <&swao_etf_in>;
3029 }; 2633 };
3030 }; 2634 };
3031 }; 2635 };
3032 2636
3033 in-ports { 2637 in-ports {
3034 #address-cell 2638 #address-cells = <1>;
3035 #size-cells = 2639 #size-cells = <0>;
3036 2640
3037 port@6 { 2641 port@6 {
3038 reg = 2642 reg = <6>;
3039 swao_ 2643 swao_funnel_in: endpoint {
3040 2644 remote-endpoint = <&replicator1_out>;
3041 }; 2645 };
3042 }; 2646 };
3043 }; 2647 };
3044 }; 2648 };
3045 2649
3046 etf@6b09000 { 2650 etf@6b09000 {
3047 compatible = "arm,cor 2651 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2652 reg = <0 0x06b09000 0 0x1000>;
3049 2653
3050 clocks = <&aoss_qmp>; 2654 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2655 clock-names = "apb_pclk";
3052 2656
3053 out-ports { 2657 out-ports {
3054 port { 2658 port {
3055 swao_ 2659 swao_etf_out: endpoint {
3056 2660 remote-endpoint = <&swao_replicator_in>;
3057 }; 2661 };
3058 }; 2662 };
3059 }; 2663 };
3060 2664
3061 in-ports { 2665 in-ports {
3062 port { 2666 port {
3063 swao_ 2667 swao_etf_in: endpoint {
3064 2668 remote-endpoint = <&swao_funnel_out>;
3065 }; 2669 };
3066 }; 2670 };
3067 }; 2671 };
3068 }; 2672 };
3069 2673
3070 replicator@6b0a000 { 2674 replicator@6b0a000 {
3071 compatible = "arm,cor 2675 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 2676 reg = <0 0x06b0a000 0 0x1000>;
3073 2677
3074 clocks = <&aoss_qmp>; 2678 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 2679 clock-names = "apb_pclk";
3076 qcom,replicator-loses 2680 qcom,replicator-loses-context;
3077 2681
3078 out-ports { 2682 out-ports {
3079 port { 2683 port {
3080 swao_ 2684 swao_replicator_out: endpoint {
3081 2685 remote-endpoint = <&funnel1_in4>;
3082 }; 2686 };
3083 }; 2687 };
3084 }; 2688 };
3085 2689
3086 in-ports { 2690 in-ports {
3087 port { 2691 port {
3088 swao_ 2692 swao_replicator_in: endpoint {
3089 2693 remote-endpoint = <&swao_etf_out>;
3090 }; 2694 };
3091 }; 2695 };
3092 }; 2696 };
3093 }; 2697 };
3094 2698
3095 etm@7040000 { 2699 etm@7040000 {
3096 compatible = "arm,cor 2700 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 2701 reg = <0 0x07040000 0 0x1000>;
3098 2702
3099 cpu = <&CPU0>; 2703 cpu = <&CPU0>;
3100 2704
3101 clocks = <&aoss_qmp>; 2705 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 2706 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 2707 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 2708 qcom,skip-power-up;
3105 2709
3106 out-ports { 2710 out-ports {
3107 port { 2711 port {
3108 etm0_ 2712 etm0_out: endpoint {
3109 2713 remote-endpoint = <&apss_funnel_in0>;
3110 }; 2714 };
3111 }; 2715 };
3112 }; 2716 };
3113 }; 2717 };
3114 2718
3115 etm@7140000 { 2719 etm@7140000 {
3116 compatible = "arm,cor 2720 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 2721 reg = <0 0x07140000 0 0x1000>;
3118 2722
3119 cpu = <&CPU1>; 2723 cpu = <&CPU1>;
3120 2724
3121 clocks = <&aoss_qmp>; 2725 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 2726 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 2727 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 2728 qcom,skip-power-up;
3125 2729
3126 out-ports { 2730 out-ports {
3127 port { 2731 port {
3128 etm1_ 2732 etm1_out: endpoint {
3129 2733 remote-endpoint = <&apss_funnel_in1>;
3130 }; 2734 };
3131 }; 2735 };
3132 }; 2736 };
3133 }; 2737 };
3134 2738
3135 etm@7240000 { 2739 etm@7240000 {
3136 compatible = "arm,cor 2740 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 2741 reg = <0 0x07240000 0 0x1000>;
3138 2742
3139 cpu = <&CPU2>; 2743 cpu = <&CPU2>;
3140 2744
3141 clocks = <&aoss_qmp>; 2745 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 2746 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 2747 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 2748 qcom,skip-power-up;
3145 2749
3146 out-ports { 2750 out-ports {
3147 port { 2751 port {
3148 etm2_ 2752 etm2_out: endpoint {
3149 2753 remote-endpoint = <&apss_funnel_in2>;
3150 }; 2754 };
3151 }; 2755 };
3152 }; 2756 };
3153 }; 2757 };
3154 2758
3155 etm@7340000 { 2759 etm@7340000 {
3156 compatible = "arm,cor 2760 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 2761 reg = <0 0x07340000 0 0x1000>;
3158 2762
3159 cpu = <&CPU3>; 2763 cpu = <&CPU3>;
3160 2764
3161 clocks = <&aoss_qmp>; 2765 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 2766 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 2767 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 2768 qcom,skip-power-up;
3165 2769
3166 out-ports { 2770 out-ports {
3167 port { 2771 port {
3168 etm3_ 2772 etm3_out: endpoint {
3169 2773 remote-endpoint = <&apss_funnel_in3>;
3170 }; 2774 };
3171 }; 2775 };
3172 }; 2776 };
3173 }; 2777 };
3174 2778
3175 etm@7440000 { 2779 etm@7440000 {
3176 compatible = "arm,cor 2780 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 2781 reg = <0 0x07440000 0 0x1000>;
3178 2782
3179 cpu = <&CPU4>; 2783 cpu = <&CPU4>;
3180 2784
3181 clocks = <&aoss_qmp>; 2785 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 2786 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 2787 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 2788 qcom,skip-power-up;
3185 2789
3186 out-ports { 2790 out-ports {
3187 port { 2791 port {
3188 etm4_ 2792 etm4_out: endpoint {
3189 2793 remote-endpoint = <&apss_funnel_in4>;
3190 }; 2794 };
3191 }; 2795 };
3192 }; 2796 };
3193 }; 2797 };
3194 2798
3195 etm@7540000 { 2799 etm@7540000 {
3196 compatible = "arm,cor 2800 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 2801 reg = <0 0x07540000 0 0x1000>;
3198 2802
3199 cpu = <&CPU5>; 2803 cpu = <&CPU5>;
3200 2804
3201 clocks = <&aoss_qmp>; 2805 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 2806 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 2807 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 2808 qcom,skip-power-up;
3205 2809
3206 out-ports { 2810 out-ports {
3207 port { 2811 port {
3208 etm5_ 2812 etm5_out: endpoint {
3209 2813 remote-endpoint = <&apss_funnel_in5>;
3210 }; 2814 };
3211 }; 2815 };
3212 }; 2816 };
3213 }; 2817 };
3214 2818
3215 etm@7640000 { 2819 etm@7640000 {
3216 compatible = "arm,cor 2820 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 2821 reg = <0 0x07640000 0 0x1000>;
3218 2822
3219 cpu = <&CPU6>; 2823 cpu = <&CPU6>;
3220 2824
3221 clocks = <&aoss_qmp>; 2825 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 2826 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 2827 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 2828 qcom,skip-power-up;
3225 2829
3226 out-ports { 2830 out-ports {
3227 port { 2831 port {
3228 etm6_ 2832 etm6_out: endpoint {
3229 2833 remote-endpoint = <&apss_funnel_in6>;
3230 }; 2834 };
3231 }; 2835 };
3232 }; 2836 };
3233 }; 2837 };
3234 2838
3235 etm@7740000 { 2839 etm@7740000 {
3236 compatible = "arm,cor 2840 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 2841 reg = <0 0x07740000 0 0x1000>;
3238 2842
3239 cpu = <&CPU7>; 2843 cpu = <&CPU7>;
3240 2844
3241 clocks = <&aoss_qmp>; 2845 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 2846 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 2847 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 2848 qcom,skip-power-up;
3245 2849
3246 out-ports { 2850 out-ports {
3247 port { 2851 port {
3248 etm7_ 2852 etm7_out: endpoint {
3249 2853 remote-endpoint = <&apss_funnel_in7>;
3250 }; 2854 };
3251 }; 2855 };
3252 }; 2856 };
3253 }; 2857 };
3254 2858
3255 funnel@7800000 { /* APSS Funn 2859 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 2860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 2861 reg = <0 0x07800000 0 0x1000>;
3258 2862
3259 clocks = <&aoss_qmp>; 2863 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 2864 clock-names = "apb_pclk";
3261 2865
3262 out-ports { 2866 out-ports {
3263 port { 2867 port {
3264 apss_ 2868 apss_funnel_out: endpoint {
3265 2869 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 2870 };
3267 }; 2871 };
3268 }; 2872 };
3269 2873
3270 in-ports { 2874 in-ports {
3271 #address-cell 2875 #address-cells = <1>;
3272 #size-cells = 2876 #size-cells = <0>;
3273 2877
3274 port@0 { 2878 port@0 {
3275 reg = 2879 reg = <0>;
3276 apss_ 2880 apss_funnel_in0: endpoint {
3277 2881 remote-endpoint = <&etm0_out>;
3278 }; 2882 };
3279 }; 2883 };
3280 2884
3281 port@1 { 2885 port@1 {
3282 reg = 2886 reg = <1>;
3283 apss_ 2887 apss_funnel_in1: endpoint {
3284 2888 remote-endpoint = <&etm1_out>;
3285 }; 2889 };
3286 }; 2890 };
3287 2891
3288 port@2 { 2892 port@2 {
3289 reg = 2893 reg = <2>;
3290 apss_ 2894 apss_funnel_in2: endpoint {
3291 2895 remote-endpoint = <&etm2_out>;
3292 }; 2896 };
3293 }; 2897 };
3294 2898
3295 port@3 { 2899 port@3 {
3296 reg = 2900 reg = <3>;
3297 apss_ 2901 apss_funnel_in3: endpoint {
3298 2902 remote-endpoint = <&etm3_out>;
3299 }; 2903 };
3300 }; 2904 };
3301 2905
3302 port@4 { 2906 port@4 {
3303 reg = 2907 reg = <4>;
3304 apss_ 2908 apss_funnel_in4: endpoint {
3305 2909 remote-endpoint = <&etm4_out>;
3306 }; 2910 };
3307 }; 2911 };
3308 2912
3309 port@5 { 2913 port@5 {
3310 reg = 2914 reg = <5>;
3311 apss_ 2915 apss_funnel_in5: endpoint {
3312 2916 remote-endpoint = <&etm5_out>;
3313 }; 2917 };
3314 }; 2918 };
3315 2919
3316 port@6 { 2920 port@6 {
3317 reg = 2921 reg = <6>;
3318 apss_ 2922 apss_funnel_in6: endpoint {
3319 2923 remote-endpoint = <&etm6_out>;
3320 }; 2924 };
3321 }; 2925 };
3322 2926
3323 port@7 { 2927 port@7 {
3324 reg = 2928 reg = <7>;
3325 apss_ 2929 apss_funnel_in7: endpoint {
3326 2930 remote-endpoint = <&etm7_out>;
3327 }; 2931 };
3328 }; 2932 };
3329 }; 2933 };
3330 }; 2934 };
3331 2935
3332 funnel@7810000 { 2936 funnel@7810000 {
3333 compatible = "arm,cor 2937 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 2938 reg = <0 0x07810000 0 0x1000>;
3335 2939
3336 clocks = <&aoss_qmp>; 2940 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 2941 clock-names = "apb_pclk";
3338 2942
3339 out-ports { 2943 out-ports {
3340 port { 2944 port {
3341 apss_ 2945 apss_merge_funnel_out: endpoint {
3342 2946 remote-endpoint = <&funnel2_in2>;
3343 }; 2947 };
3344 }; 2948 };
3345 }; 2949 };
3346 2950
3347 in-ports { 2951 in-ports {
3348 port { 2952 port {
3349 apss_ 2953 apss_merge_funnel_in: endpoint {
3350 2954 remote-endpoint = <&apss_funnel_out>;
3351 }; 2955 };
3352 }; 2956 };
3353 }; 2957 };
3354 }; 2958 };
3355 2959
3356 remoteproc_cdsp: remoteproc@8 2960 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 2961 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 2962 reg = <0x0 0x08300000 0x0 0x4040>;
3359 2963
3360 interrupts-extended = 2964 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 2965 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 2966 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 2967 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 2968 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 2969 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 2970 "handover", "stop-ack";
3367 2971
3368 clocks = <&rpmhcc RPM 2972 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 2973 clock-names = "xo";
3370 2974
3371 power-domains = <&rpm !! 2975 power-domains = <&rpmhpd 7>;
3372 2976
3373 memory-region = <&cds 2977 memory-region = <&cdsp_mem>;
3374 2978
3375 qcom,qmp = <&aoss_qmp 2979 qcom,qmp = <&aoss_qmp>;
3376 2980
3377 qcom,smem-states = <& 2981 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 2982 qcom,smem-state-names = "stop";
3379 2983
3380 status = "disabled"; 2984 status = "disabled";
3381 2985
3382 glink-edge { 2986 glink-edge {
3383 interrupts = 2987 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 2988 label = "cdsp";
3385 qcom,remote-p 2989 qcom,remote-pid = <5>;
3386 mboxes = <&ap 2990 mboxes = <&apss_shared 4>;
3387 2991
3388 fastrpc { 2992 fastrpc {
3389 compa 2993 compatible = "qcom,fastrpc";
3390 qcom, 2994 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 2995 label = "cdsp";
3392 qcom, <<
3393 #addr 2996 #address-cells = <1>;
3394 #size 2997 #size-cells = <0>;
3395 2998
3396 compu 2999 compute-cb@1 {
3397 3000 compatible = "qcom,fastrpc-compute-cb";
3398 3001 reg = <1>;
3399 !! 3002 iommus = <&apps_smmu 0x1401 0x2040>,
>> 3003 <&apps_smmu 0x1421 0x0>,
>> 3004 <&apps_smmu 0x2001 0x420>,
>> 3005 <&apps_smmu 0x2041 0x0>;
3400 }; 3006 };
3401 3007
3402 compu 3008 compute-cb@2 {
3403 3009 compatible = "qcom,fastrpc-compute-cb";
3404 3010 reg = <2>;
3405 !! 3011 iommus = <&apps_smmu 0x2 0x3440>,
>> 3012 <&apps_smmu 0x22 0x3400>;
3406 }; 3013 };
3407 3014
3408 compu 3015 compute-cb@3 {
3409 3016 compatible = "qcom,fastrpc-compute-cb";
3410 3017 reg = <3>;
3411 !! 3018 iommus = <&apps_smmu 0x3 0x3440>,
>> 3019 <&apps_smmu 0x1423 0x0>,
>> 3020 <&apps_smmu 0x2023 0x0>;
3412 }; 3021 };
3413 3022
3414 compu 3023 compute-cb@4 {
3415 3024 compatible = "qcom,fastrpc-compute-cb";
3416 3025 reg = <4>;
3417 !! 3026 iommus = <&apps_smmu 0x4 0x3440>,
>> 3027 <&apps_smmu 0x24 0x3400>;
3418 }; 3028 };
3419 3029
3420 compu 3030 compute-cb@5 {
3421 3031 compatible = "qcom,fastrpc-compute-cb";
3422 3032 reg = <5>;
3423 !! 3033 iommus = <&apps_smmu 0x5 0x3440>,
>> 3034 <&apps_smmu 0x25 0x3400>;
3424 }; 3035 };
3425 3036
3426 compu 3037 compute-cb@6 {
3427 3038 compatible = "qcom,fastrpc-compute-cb";
3428 3039 reg = <6>;
3429 !! 3040 iommus = <&apps_smmu 0x6 0x3460>;
3430 }; 3041 };
3431 3042
3432 compu 3043 compute-cb@7 {
3433 3044 compatible = "qcom,fastrpc-compute-cb";
3434 3045 reg = <7>;
3435 !! 3046 iommus = <&apps_smmu 0x7 0x3460>;
3436 }; 3047 };
3437 3048
3438 compu 3049 compute-cb@8 {
3439 3050 compatible = "qcom,fastrpc-compute-cb";
3440 3051 reg = <8>;
3441 !! 3052 iommus = <&apps_smmu 0x8 0x3460>;
3442 }; 3053 };
3443 3054
3444 /* no 3055 /* note: secure cb9 in downstream */
3445 }; 3056 };
3446 }; 3057 };
3447 }; 3058 };
3448 3059
3449 usb_1_hsphy: phy@88e2000 { 3060 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3061 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3062 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3063 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3064 status = "disabled";
3454 #phy-cells = <0>; 3065 #phy-cells = <0>;
3455 3066
3456 clocks = <&rpmhcc RPM 3067 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3068 clock-names = "ref";
3458 3069
3459 resets = <&gcc GCC_QU 3070 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3071 };
3461 3072
3462 usb_2_hsphy: phy@88e3000 { 3073 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3074 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3075 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3076 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3077 status = "disabled";
3467 #phy-cells = <0>; 3078 #phy-cells = <0>;
3468 3079
3469 clocks = <&rpmhcc RPM 3080 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3081 clock-names = "ref";
3471 3082
3472 resets = <&gcc GCC_QU 3083 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3084 };
3474 3085
3475 usb_1_qmpphy: phy@88e8000 { !! 3086 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 3087 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 3088 reg = <0 0x088e9000 0 0x18c>,
>> 3089 <0 0x088e8000 0 0x10>;
>> 3090 status = "disabled";
>> 3091 #address-cells = <2>;
>> 3092 #size-cells = <2>;
>> 3093 ranges;
3478 3094
3479 clocks = <&gcc GCC_US 3095 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3096 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3097 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3098 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3099 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3100
3488 resets = <&gcc GCC_US 3101 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3102 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3103 reset-names = "phy", "common";
3491 3104
3492 #clock-cells = <1>; !! 3105 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3106 reg = <0 0x088e9200 0 0x200>,
3494 !! 3107 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3108 <0 0x088e9c00 0 0x218>,
3496 !! 3109 <0 0x088e9600 0 0x200>,
3497 ports { !! 3110 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3111 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3112 #clock-cells = <0>;
3500 !! 3113 #phy-cells = <0>;
3501 port@0 { !! 3114 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3115 clock-names = "pipe0";
3503 !! 3116 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3117 };
3524 }; 3118 };
3525 3119
3526 usb_2_qmpphy: phy@88eb000 { 3120 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3121 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3122 reg = <0 0x088eb000 0 0x200>;
>> 3123 status = "disabled";
>> 3124 #address-cells = <2>;
>> 3125 #size-cells = <2>;
>> 3126 ranges;
3529 3127
3530 clocks = <&gcc GCC_US 3128 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3129 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3130 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3131 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3132 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 <<
3542 resets = <&gcc GCC_US <<
3543 <&gcc GCC_US <<
3544 reset-names = "phy", <<
3545 "phy_ph <<
3546 <<
3547 status = "disabled"; <<
3548 }; <<
3549 <<
3550 sdhc_2: mmc@8804000 { <<
3551 compatible = "qcom,sm <<
3552 reg = <0 0x08804000 0 <<
3553 <<
3554 interrupts = <GIC_SPI <<
3555 <GIC_SPI <<
3556 interrupt-names = "hc <<
3557 <<
3558 clocks = <&gcc GCC_SD <<
3559 <&gcc GCC_SD <<
3560 <&rpmhcc RPM <<
3561 clock-names = "iface" <<
3562 iommus = <&apps_smmu <<
3563 qcom,dll-config = <0x <<
3564 qcom,ddr-config = <0x <<
3565 power-domains = <&rpm <<
3566 operating-points-v2 = <<
3567 <<
3568 status = "disabled"; <<
3569 <<
3570 sdhc2_opp_table: opp- <<
3571 compatible = <<
3572 <<
3573 opp-19200000 <<
3574 opp-h <<
3575 requi <<
3576 }; <<
3577 <<
3578 opp-50000000 <<
3579 opp-h <<
3580 requi <<
3581 }; <<
3582 3133
3583 opp-100000000 !! 3134 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3584 opp-h !! 3135 <&gcc GCC_USB3_PHY_SEC_BCR>;
3585 requi !! 3136 reset-names = "phy", "common";
3586 }; <<
3587 3137
3588 opp-202000000 !! 3138 usb_2_ssphy: phy@88eb200 {
3589 opp-h !! 3139 reg = <0 0x088eb200 0 0x200>,
3590 requi !! 3140 <0 0x088eb400 0 0x200>,
3591 }; !! 3141 <0 0x088eb800 0 0x800>,
>> 3142 <0 0x088eb600 0 0x200>;
>> 3143 #clock-cells = <0>;
>> 3144 #phy-cells = <0>;
>> 3145 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3146 clock-names = "pipe0";
>> 3147 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3592 }; 3148 };
3593 }; 3149 };
3594 3150
3595 dc_noc: interconnect@9160000 3151 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3152 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3153 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3154 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3155 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3156 };
3601 3157
3602 gem_noc: interconnect@9680000 3158 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3159 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3160 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3161 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3162 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3163 };
3608 3164
3609 usb_1: usb@a6f8800 { 3165 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3166 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3167 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3168 status = "disabled";
3613 #address-cells = <2>; 3169 #address-cells = <2>;
3614 #size-cells = <2>; 3170 #size-cells = <2>;
3615 ranges; 3171 ranges;
3616 dma-ranges; 3172 dma-ranges;
3617 3173
3618 clocks = <&gcc GCC_CF 3174 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3175 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3176 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US <<
3622 <&gcc GCC_US 3177 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 3178 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3623 <&gcc GCC_US 3179 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no !! 3180 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3625 "core", !! 3181 "sleep", "xo";
3626 "iface" <<
3627 "sleep" <<
3628 "mock_u <<
3629 "xo"; <<
3630 3182
3631 assigned-clocks = <&g 3183 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3184 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3185 assigned-clock-rates = <19200000>, <200000000>;
3634 3186
3635 interrupts-extended = !! 3187 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3188 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3189 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 3190 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 3191 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3192 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3193
3646 power-domains = <&gcc 3194 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3195
3648 resets = <&gcc GCC_US 3196 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3197
3650 interconnects = <&agg !! 3198 usb_1_dwc3: dwc3@a600000 {
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 <<
3655 compatible = 3199 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3200 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3201 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3202 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3203 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3204 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3205 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3206 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3207 };
3684 }; 3208 };
3685 3209
3686 usb_2: usb@a8f8800 { 3210 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3211 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3212 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3213 status = "disabled";
3690 #address-cells = <2>; 3214 #address-cells = <2>;
3691 #size-cells = <2>; 3215 #size-cells = <2>;
3692 ranges; 3216 ranges;
3693 dma-ranges; 3217 dma-ranges;
3694 3218
3695 clocks = <&gcc GCC_CF 3219 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3220 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3221 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US <<
3699 <&gcc GCC_US 3222 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 3223 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3700 <&gcc GCC_US 3224 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no !! 3225 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3702 "core", !! 3226 "sleep", "xo";
3703 "iface" <<
3704 "sleep" <<
3705 "mock_u <<
3706 "xo"; <<
3707 3227
3708 assigned-clocks = <&g 3228 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3229 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3230 assigned-clock-rates = <19200000>, <200000000>;
3711 3231
3712 interrupts-extended = !! 3232 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3233 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3234 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 3235 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 3236 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3237 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3238
3723 power-domains = <&gcc 3239 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3240
3725 resets = <&gcc GCC_US 3241 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3242
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3243 usb_2_dwc3: usb@a800000 {
3732 compatible = 3244 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3245 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3246 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3247 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3248 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3249 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3250 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3251 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3252 };
3741 }; 3253 };
3742 3254
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3255 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3256 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3257 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3258 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3259 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3260 };
3762 3261
3763 camcc: clock-controller@ad000 !! 3262 aoss_qmp: power-controller@c300000 {
3764 compatible = "qcom,sm !! 3263 compatible = "qcom,sm8150-aoss-qmp";
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 <<
4150 compatible = "qcom,sm <<
4151 reg = <0 0x0b220000 0 <<
4152 qcom,pdc-ranges = <0 <<
4153 <12 <<
4154 #interrupt-cells = <2 <<
4155 interrupt-parent = <& <<
4156 interrupt-controller; <<
4157 }; <<
4158 <<
4159 aoss_qmp: power-management@c3 <<
4160 compatible = "qcom,sm <<
4161 reg = <0x0 0x0c300000 3264 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 3265 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3266 mboxes = <&apss_shared 0>;
4164 3267
4165 #clock-cells = <0>; 3268 #clock-cells = <0>;
4166 }; 3269 };
4167 3270
4168 sram@c3f0000 { 3271 sram@c3f0000 {
4169 compatible = "qcom,rp 3272 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 3273 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 3274 };
4172 3275
4173 tsens0: thermal-sensor@c26300 3276 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3277 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3278 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3279 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3280 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3281 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3282 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3283 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3284 #thermal-sensor-cells = <1>;
4182 }; 3285 };
4183 3286
4184 tsens1: thermal-sensor@c26500 3287 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3288 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3289 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3290 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3291 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3292 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3293 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3294 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3295 #thermal-sensor-cells = <1>;
4193 }; 3296 };
4194 3297
4195 spmi_bus: spmi@c440000 { 3298 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3299 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3300 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3301 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3302 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3303 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3304 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3305 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3306 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3307 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3308 qcom,ee = <0>;
4206 qcom,channel = <0>; 3309 qcom,channel = <0>;
4207 #address-cells = <2>; 3310 #address-cells = <2>;
4208 #size-cells = <0>; 3311 #size-cells = <0>;
4209 interrupt-controller; 3312 interrupt-controller;
4210 #interrupt-cells = <4 3313 #interrupt-cells = <4>;
>> 3314 cell-index = <0>;
4211 }; 3315 };
4212 3316
4213 apps_smmu: iommu@15000000 { 3317 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3318 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3319 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3320 #iommu-cells = <2>;
4217 #global-interrupts = 3321 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3322 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3323 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3324 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3325 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3326 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3327 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3328 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3329 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3330 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3331 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3332 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3333 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3334 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3335 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3336 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3339 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3340 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3341 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3342 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3344 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3345 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3346 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3347 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3348 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3349 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3350 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3351 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3352 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3353 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3354 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3355 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3356 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3357 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3358 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3359 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3360 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3361 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3362 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3363 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 3364 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 3365 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 3366 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 3367 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 3368 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 3369 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 3370 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 3371 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 3372 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 3373 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 3374 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 3375 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 3376 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 3377 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 3378 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 3379 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 3380 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 3381 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 3382 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 3383 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 3384 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 3385 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 3386 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 3387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 3388 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 3389 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 3390 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 3391 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 3392 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 3393 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 3394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 3395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 3396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 3397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 3398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 3399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 3400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 3401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 3402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 3403 };
4300 3404
4301 remoteproc_adsp: remoteproc@1 3405 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 3406 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 3407 reg = <0x0 0x17300000 0x0 0x4040>;
4304 3408
4305 interrupts-extended = 3409 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 3410 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 3411 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 3412 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 3413 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 3414 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 3415 "handover", "stop-ack";
4312 3416
4313 clocks = <&rpmhcc RPM 3417 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 3418 clock-names = "xo";
4315 3419
4316 power-domains = <&rpm !! 3420 power-domains = <&rpmhpd 7>;
4317 3421
4318 memory-region = <&ads 3422 memory-region = <&adsp_mem>;
4319 3423
4320 qcom,qmp = <&aoss_qmp 3424 qcom,qmp = <&aoss_qmp>;
4321 3425
4322 qcom,smem-states = <& 3426 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 3427 qcom,smem-state-names = "stop";
4324 3428
4325 status = "disabled"; 3429 status = "disabled";
4326 3430
4327 glink-edge { 3431 glink-edge {
4328 interrupts = 3432 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 3433 label = "lpass";
4330 qcom,remote-p 3434 qcom,remote-pid = <2>;
4331 mboxes = <&ap 3435 mboxes = <&apss_shared 8>;
4332 3436
4333 fastrpc { 3437 fastrpc {
4334 compa 3438 compatible = "qcom,fastrpc";
4335 qcom, 3439 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 3440 label = "adsp";
4337 qcom, <<
4338 #addr 3441 #address-cells = <1>;
4339 #size 3442 #size-cells = <0>;
4340 3443
4341 compu 3444 compute-cb@3 {
4342 3445 compatible = "qcom,fastrpc-compute-cb";
4343 3446 reg = <3>;
4344 3447 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 3448 };
4346 3449
4347 compu 3450 compute-cb@4 {
4348 3451 compatible = "qcom,fastrpc-compute-cb";
4349 3452 reg = <4>;
4350 3453 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 3454 };
4352 3455
4353 compu 3456 compute-cb@5 {
4354 3457 compatible = "qcom,fastrpc-compute-cb";
4355 3458 reg = <5>;
4356 3459 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 3460 };
4358 }; 3461 };
4359 }; 3462 };
4360 }; 3463 };
4361 3464
4362 intc: interrupt-controller@17 3465 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 3466 compatible = "arm,gic-v3";
4364 interrupt-controller; 3467 interrupt-controller;
4365 #interrupt-cells = <3 3468 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 3469 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 3470 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 3471 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 3472 };
4370 3473
4371 apss_shared: mailbox@17c00000 3474 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 3475 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 3476 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 3477 #mbox-cells = <1>;
4376 }; 3478 };
4377 3479
4378 watchdog@17c10000 { 3480 watchdog@17c10000 {
4379 compatible = "qcom,ap 3481 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 3482 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 3483 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 3484 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 3485 };
4384 3486
4385 timer@17c20000 { 3487 timer@17c20000 {
4386 #address-cells = <1>; !! 3488 #address-cells = <2>;
4387 #size-cells = <1>; !! 3489 #size-cells = <2>;
4388 ranges = <0 0 0 0x200 !! 3490 ranges;
4389 compatible = "arm,arm 3491 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 3492 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 3493 clock-frequency = <19200000>;
4392 3494
4393 frame@17c21000 { !! 3495 frame@17c21000{
4394 frame-number 3496 frame-number = <0>;
4395 interrupts = 3497 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 3498 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 !! 3499 reg = <0x0 0x17c21000 0x0 0x1000>,
4398 <0x17c2 !! 3500 <0x0 0x17c22000 0x0 0x1000>;
4399 }; 3501 };
4400 3502
4401 frame@17c23000 { 3503 frame@17c23000 {
4402 frame-number 3504 frame-number = <1>;
4403 interrupts = 3505 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 !! 3506 reg = <0x0 0x17c23000 0x0 0x1000>;
4405 status = "dis 3507 status = "disabled";
4406 }; 3508 };
4407 3509
4408 frame@17c25000 { 3510 frame@17c25000 {
4409 frame-number 3511 frame-number = <2>;
4410 interrupts = 3512 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 !! 3513 reg = <0x0 0x17c25000 0x0 0x1000>;
4412 status = "dis 3514 status = "disabled";
4413 }; 3515 };
4414 3516
4415 frame@17c27000 { 3517 frame@17c27000 {
4416 frame-number 3518 frame-number = <3>;
4417 interrupts = 3519 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 !! 3520 reg = <0x0 0x17c26000 0x0 0x1000>;
4419 status = "dis 3521 status = "disabled";
4420 }; 3522 };
4421 3523
4422 frame@17c29000 { 3524 frame@17c29000 {
4423 frame-number 3525 frame-number = <4>;
4424 interrupts = 3526 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 !! 3527 reg = <0x0 0x17c29000 0x0 0x1000>;
4426 status = "dis 3528 status = "disabled";
4427 }; 3529 };
4428 3530
4429 frame@17c2b000 { 3531 frame@17c2b000 {
4430 frame-number 3532 frame-number = <5>;
4431 interrupts = 3533 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 !! 3534 reg = <0x0 0x17c2b000 0x0 0x1000>;
4433 status = "dis 3535 status = "disabled";
4434 }; 3536 };
4435 3537
4436 frame@17c2d000 { 3538 frame@17c2d000 {
4437 frame-number 3539 frame-number = <6>;
4438 interrupts = 3540 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 !! 3541 reg = <0x0 0x17c2d000 0x0 0x1000>;
4440 status = "dis 3542 status = "disabled";
4441 }; 3543 };
4442 }; 3544 };
4443 3545
4444 apps_rsc: rsc@18200000 { 3546 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 3547 label = "apps_rsc";
4446 compatible = "qcom,rp 3548 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 3549 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 3550 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 3551 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 3552 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 3553 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 3554 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 3555 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 3556 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 3557 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 3558 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 3559 <SLEEP_TCS 3>,
4458 <WA 3560 <WAKE_TCS 3>,
4459 <CO 3561 <CONTROL_TCS 1>;
4460 power-domains = <&CLU <<
4461 3562
4462 rpmhcc: clock-control 3563 rpmhcc: clock-controller {
4463 compatible = 3564 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 3565 #clock-cells = <1>;
4465 clock-names = 3566 clock-names = "xo";
4466 clocks = <&xo 3567 clocks = <&xo_board>;
4467 }; 3568 };
4468 3569
4469 rpmhpd: power-control 3570 rpmhpd: power-controller {
4470 compatible = 3571 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 3572 #power-domain-cells = <1>;
4472 operating-poi 3573 operating-points-v2 = <&rpmhpd_opp_table>;
4473 3574
4474 rpmhpd_opp_ta 3575 rpmhpd_opp_table: opp-table {
4475 compa 3576 compatible = "operating-points-v2";
4476 3577
4477 rpmhp 3578 rpmhpd_opp_ret: opp1 {
4478 3579 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 3580 };
4480 3581
4481 rpmhp 3582 rpmhpd_opp_min_svs: opp2 {
4482 3583 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 3584 };
4484 3585
4485 rpmhp 3586 rpmhpd_opp_low_svs: opp3 {
4486 3587 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 3588 };
4488 3589
4489 rpmhp 3590 rpmhpd_opp_svs: opp4 {
4490 3591 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 3592 };
4492 3593
4493 rpmhp 3594 rpmhpd_opp_svs_l1: opp5 {
4494 3595 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 3596 };
4496 3597
4497 rpmhp 3598 rpmhpd_opp_svs_l2: opp6 {
4498 3599 opp-level = <224>;
4499 }; 3600 };
4500 3601
4501 rpmhp 3602 rpmhpd_opp_nom: opp7 {
4502 3603 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 3604 };
4504 3605
4505 rpmhp 3606 rpmhpd_opp_nom_l1: opp8 {
4506 3607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 3608 };
4508 3609
4509 rpmhp 3610 rpmhpd_opp_nom_l2: opp9 {
4510 3611 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 3612 };
4512 3613
4513 rpmhp 3614 rpmhpd_opp_turbo: opp10 {
4514 3615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 3616 };
4516 3617
4517 rpmhp 3618 rpmhpd_opp_turbo_l1: opp11 {
4518 3619 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 3620 };
4520 }; 3621 };
4521 }; 3622 };
4522 3623
4523 apps_bcm_voter: bcm-v !! 3624 apps_bcm_voter: bcm_voter {
4524 compatible = 3625 compatible = "qcom,bcm-voter";
4525 }; 3626 };
4526 }; 3627 };
4527 3628
4528 osm_l3: interconnect@18321000 3629 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 3630 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 3631 reg = <0 0x18321000 0 0x1400>;
4531 3632
4532 clocks = <&rpmhcc RPM 3633 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 3634 clock-names = "xo", "alternate";
4534 3635
4535 #interconnect-cells = 3636 #interconnect-cells = <1>;
4536 }; 3637 };
4537 3638
4538 cpufreq_hw: cpufreq@18323000 3639 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 3640 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 3641 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 3642 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 3643 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 3644 "freq-domain2";
4544 3645
4545 clocks = <&rpmhcc RPM 3646 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 3647 clock-names = "xo", "alternate";
4547 3648
4548 #freq-domain-cells = 3649 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; <<
4551 <<
4552 lmh_cluster1: lmh@18350800 { <<
4553 compatible = "qcom,sm <<
4554 reg = <0 0x18350800 0 <<
4555 interrupts = <GIC_SPI <<
4556 cpus = <&CPU4>; <<
4557 qcom,lmh-temp-arm-mil <<
4558 qcom,lmh-temp-low-mil <<
4559 qcom,lmh-temp-high-mi <<
4560 interrupt-controller; <<
4561 #interrupt-cells = <1 <<
4562 }; <<
4563 <<
4564 lmh_cluster0: lmh@18358800 { <<
4565 compatible = "qcom,sm <<
4566 reg = <0 0x18358800 0 <<
4567 interrupts = <GIC_SPI <<
4568 cpus = <&CPU0>; <<
4569 qcom,lmh-temp-arm-mil <<
4570 qcom,lmh-temp-low-mil <<
4571 qcom,lmh-temp-high-mi <<
4572 interrupt-controller; <<
4573 #interrupt-cells = <1 <<
4574 }; 3650 };
4575 3651
4576 wifi: wifi@18800000 { 3652 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 3653 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 3654 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 3655 reg-names = "membase";
4580 memory-region = <&wla 3656 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 3657 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 3658 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 3659 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 3660 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 3661 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 3662 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 3663 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 3664 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 3665 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 3666 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 3667 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 3668 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 3669 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 3670 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 3671 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 3672 status = "disabled";
4597 }; 3673 };
4598 }; 3674 };
4599 3675
4600 timer { 3676 timer {
4601 compatible = "arm,armv8-timer 3677 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 3678 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 3679 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 3680 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 3681 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 3682 };
4607 3683
4608 thermal-zones { 3684 thermal-zones {
4609 cpu0-thermal { 3685 cpu0-thermal {
4610 polling-delay-passive 3686 polling-delay-passive = <250>;
>> 3687 polling-delay = <1000>;
4611 3688
4612 thermal-sensors = <&t 3689 thermal-sensors = <&tsens0 1>;
4613 3690
4614 trips { 3691 trips {
4615 cpu0_alert0: 3692 cpu0_alert0: trip-point0 {
4616 tempe 3693 temperature = <90000>;
4617 hyste 3694 hysteresis = <2000>;
4618 type 3695 type = "passive";
4619 }; 3696 };
4620 3697
4621 cpu0_alert1: 3698 cpu0_alert1: trip-point1 {
4622 tempe 3699 temperature = <95000>;
4623 hyste 3700 hysteresis = <2000>;
4624 type 3701 type = "passive";
4625 }; 3702 };
4626 3703
4627 cpu0_crit: cp !! 3704 cpu0_crit: cpu_crit {
4628 tempe 3705 temperature = <110000>;
4629 hyste 3706 hysteresis = <1000>;
4630 type 3707 type = "critical";
4631 }; 3708 };
4632 }; 3709 };
4633 3710
4634 cooling-maps { 3711 cooling-maps {
4635 map0 { 3712 map0 {
4636 trip 3713 trip = <&cpu0_alert0>;
4637 cooli 3714 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 3715 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 3716 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 3717 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 3718 };
4642 map1 { 3719 map1 {
4643 trip 3720 trip = <&cpu0_alert1>;
4644 cooli 3721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 3722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 3723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 3724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 3725 };
4649 }; 3726 };
4650 }; 3727 };
4651 3728
4652 cpu1-thermal { 3729 cpu1-thermal {
4653 polling-delay-passive 3730 polling-delay-passive = <250>;
>> 3731 polling-delay = <1000>;
4654 3732
4655 thermal-sensors = <&t 3733 thermal-sensors = <&tsens0 2>;
4656 3734
4657 trips { 3735 trips {
4658 cpu1_alert0: 3736 cpu1_alert0: trip-point0 {
4659 tempe 3737 temperature = <90000>;
4660 hyste 3738 hysteresis = <2000>;
4661 type 3739 type = "passive";
4662 }; 3740 };
4663 3741
4664 cpu1_alert1: 3742 cpu1_alert1: trip-point1 {
4665 tempe 3743 temperature = <95000>;
4666 hyste 3744 hysteresis = <2000>;
4667 type 3745 type = "passive";
4668 }; 3746 };
4669 3747
4670 cpu1_crit: cp !! 3748 cpu1_crit: cpu_crit {
4671 tempe 3749 temperature = <110000>;
4672 hyste 3750 hysteresis = <1000>;
4673 type 3751 type = "critical";
4674 }; 3752 };
4675 }; 3753 };
4676 3754
4677 cooling-maps { 3755 cooling-maps {
4678 map0 { 3756 map0 {
4679 trip 3757 trip = <&cpu1_alert0>;
4680 cooli 3758 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 3759 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 3760 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 3761 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 3762 };
4685 map1 { 3763 map1 {
4686 trip 3764 trip = <&cpu1_alert1>;
4687 cooli 3765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 3766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 3767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 3768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 3769 };
4692 }; 3770 };
4693 }; 3771 };
4694 3772
4695 cpu2-thermal { 3773 cpu2-thermal {
4696 polling-delay-passive 3774 polling-delay-passive = <250>;
>> 3775 polling-delay = <1000>;
4697 3776
4698 thermal-sensors = <&t 3777 thermal-sensors = <&tsens0 3>;
4699 3778
4700 trips { 3779 trips {
4701 cpu2_alert0: 3780 cpu2_alert0: trip-point0 {
4702 tempe 3781 temperature = <90000>;
4703 hyste 3782 hysteresis = <2000>;
4704 type 3783 type = "passive";
4705 }; 3784 };
4706 3785
4707 cpu2_alert1: 3786 cpu2_alert1: trip-point1 {
4708 tempe 3787 temperature = <95000>;
4709 hyste 3788 hysteresis = <2000>;
4710 type 3789 type = "passive";
4711 }; 3790 };
4712 3791
4713 cpu2_crit: cp !! 3792 cpu2_crit: cpu_crit {
4714 tempe 3793 temperature = <110000>;
4715 hyste 3794 hysteresis = <1000>;
4716 type 3795 type = "critical";
4717 }; 3796 };
4718 }; 3797 };
4719 3798
4720 cooling-maps { 3799 cooling-maps {
4721 map0 { 3800 map0 {
4722 trip 3801 trip = <&cpu2_alert0>;
4723 cooli 3802 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 3803 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 3804 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 3805 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 3806 };
4728 map1 { 3807 map1 {
4729 trip 3808 trip = <&cpu2_alert1>;
4730 cooli 3809 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 3810 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 3811 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 3812 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 3813 };
4735 }; 3814 };
4736 }; 3815 };
4737 3816
4738 cpu3-thermal { 3817 cpu3-thermal {
4739 polling-delay-passive 3818 polling-delay-passive = <250>;
>> 3819 polling-delay = <1000>;
4740 3820
4741 thermal-sensors = <&t 3821 thermal-sensors = <&tsens0 4>;
4742 3822
4743 trips { 3823 trips {
4744 cpu3_alert0: 3824 cpu3_alert0: trip-point0 {
4745 tempe 3825 temperature = <90000>;
4746 hyste 3826 hysteresis = <2000>;
4747 type 3827 type = "passive";
4748 }; 3828 };
4749 3829
4750 cpu3_alert1: 3830 cpu3_alert1: trip-point1 {
4751 tempe 3831 temperature = <95000>;
4752 hyste 3832 hysteresis = <2000>;
4753 type 3833 type = "passive";
4754 }; 3834 };
4755 3835
4756 cpu3_crit: cp !! 3836 cpu3_crit: cpu_crit {
4757 tempe 3837 temperature = <110000>;
4758 hyste 3838 hysteresis = <1000>;
4759 type 3839 type = "critical";
4760 }; 3840 };
4761 }; 3841 };
4762 3842
4763 cooling-maps { 3843 cooling-maps {
4764 map0 { 3844 map0 {
4765 trip 3845 trip = <&cpu3_alert0>;
4766 cooli 3846 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 3847 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 3848 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 3849 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 3850 };
4771 map1 { 3851 map1 {
4772 trip 3852 trip = <&cpu3_alert1>;
4773 cooli 3853 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 3854 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 3855 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 3856 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 3857 };
4778 }; 3858 };
4779 }; 3859 };
4780 3860
4781 cpu4-top-thermal { 3861 cpu4-top-thermal {
4782 polling-delay-passive 3862 polling-delay-passive = <250>;
>> 3863 polling-delay = <1000>;
4783 3864
4784 thermal-sensors = <&t 3865 thermal-sensors = <&tsens0 7>;
4785 3866
4786 trips { 3867 trips {
4787 cpu4_top_aler 3868 cpu4_top_alert0: trip-point0 {
4788 tempe 3869 temperature = <90000>;
4789 hyste 3870 hysteresis = <2000>;
4790 type 3871 type = "passive";
4791 }; 3872 };
4792 3873
4793 cpu4_top_aler 3874 cpu4_top_alert1: trip-point1 {
4794 tempe 3875 temperature = <95000>;
4795 hyste 3876 hysteresis = <2000>;
4796 type 3877 type = "passive";
4797 }; 3878 };
4798 3879
4799 cpu4_top_crit !! 3880 cpu4_top_crit: cpu_crit {
4800 tempe 3881 temperature = <110000>;
4801 hyste 3882 hysteresis = <1000>;
4802 type 3883 type = "critical";
4803 }; 3884 };
4804 }; 3885 };
4805 3886
4806 cooling-maps { 3887 cooling-maps {
4807 map0 { 3888 map0 {
4808 trip 3889 trip = <&cpu4_top_alert0>;
4809 cooli 3890 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 3891 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 3892 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 3893 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 3894 };
4814 map1 { 3895 map1 {
4815 trip 3896 trip = <&cpu4_top_alert1>;
4816 cooli 3897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 3898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 3899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 3900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 3901 };
4821 }; 3902 };
4822 }; 3903 };
4823 3904
4824 cpu5-top-thermal { 3905 cpu5-top-thermal {
4825 polling-delay-passive 3906 polling-delay-passive = <250>;
>> 3907 polling-delay = <1000>;
4826 3908
4827 thermal-sensors = <&t 3909 thermal-sensors = <&tsens0 8>;
4828 3910
4829 trips { 3911 trips {
4830 cpu5_top_aler 3912 cpu5_top_alert0: trip-point0 {
4831 tempe 3913 temperature = <90000>;
4832 hyste 3914 hysteresis = <2000>;
4833 type 3915 type = "passive";
4834 }; 3916 };
4835 3917
4836 cpu5_top_aler 3918 cpu5_top_alert1: trip-point1 {
4837 tempe 3919 temperature = <95000>;
4838 hyste 3920 hysteresis = <2000>;
4839 type 3921 type = "passive";
4840 }; 3922 };
4841 3923
4842 cpu5_top_crit !! 3924 cpu5_top_crit: cpu_crit {
4843 tempe 3925 temperature = <110000>;
4844 hyste 3926 hysteresis = <1000>;
4845 type 3927 type = "critical";
4846 }; 3928 };
4847 }; 3929 };
4848 3930
4849 cooling-maps { 3931 cooling-maps {
4850 map0 { 3932 map0 {
4851 trip 3933 trip = <&cpu5_top_alert0>;
4852 cooli 3934 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 3935 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 3936 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 3937 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 3938 };
4857 map1 { 3939 map1 {
4858 trip 3940 trip = <&cpu5_top_alert1>;
4859 cooli 3941 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 3942 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 3943 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 3944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 3945 };
4864 }; 3946 };
4865 }; 3947 };
4866 3948
4867 cpu6-top-thermal { 3949 cpu6-top-thermal {
4868 polling-delay-passive 3950 polling-delay-passive = <250>;
>> 3951 polling-delay = <1000>;
4869 3952
4870 thermal-sensors = <&t 3953 thermal-sensors = <&tsens0 9>;
4871 3954
4872 trips { 3955 trips {
4873 cpu6_top_aler 3956 cpu6_top_alert0: trip-point0 {
4874 tempe 3957 temperature = <90000>;
4875 hyste 3958 hysteresis = <2000>;
4876 type 3959 type = "passive";
4877 }; 3960 };
4878 3961
4879 cpu6_top_aler 3962 cpu6_top_alert1: trip-point1 {
4880 tempe 3963 temperature = <95000>;
4881 hyste 3964 hysteresis = <2000>;
4882 type 3965 type = "passive";
4883 }; 3966 };
4884 3967
4885 cpu6_top_crit !! 3968 cpu6_top_crit: cpu_crit {
4886 tempe 3969 temperature = <110000>;
4887 hyste 3970 hysteresis = <1000>;
4888 type 3971 type = "critical";
4889 }; 3972 };
4890 }; 3973 };
4891 3974
4892 cooling-maps { 3975 cooling-maps {
4893 map0 { 3976 map0 {
4894 trip 3977 trip = <&cpu6_top_alert0>;
4895 cooli 3978 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 3979 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 3980 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 3981 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 3982 };
4900 map1 { 3983 map1 {
4901 trip 3984 trip = <&cpu6_top_alert1>;
4902 cooli 3985 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 3986 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 3987 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 3988 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 3989 };
4907 }; 3990 };
4908 }; 3991 };
4909 3992
4910 cpu7-top-thermal { 3993 cpu7-top-thermal {
4911 polling-delay-passive 3994 polling-delay-passive = <250>;
>> 3995 polling-delay = <1000>;
4912 3996
4913 thermal-sensors = <&t 3997 thermal-sensors = <&tsens0 10>;
4914 3998
4915 trips { 3999 trips {
4916 cpu7_top_aler 4000 cpu7_top_alert0: trip-point0 {
4917 tempe 4001 temperature = <90000>;
4918 hyste 4002 hysteresis = <2000>;
4919 type 4003 type = "passive";
4920 }; 4004 };
4921 4005
4922 cpu7_top_aler 4006 cpu7_top_alert1: trip-point1 {
4923 tempe 4007 temperature = <95000>;
4924 hyste 4008 hysteresis = <2000>;
4925 type 4009 type = "passive";
4926 }; 4010 };
4927 4011
4928 cpu7_top_crit !! 4012 cpu7_top_crit: cpu_crit {
4929 tempe 4013 temperature = <110000>;
4930 hyste 4014 hysteresis = <1000>;
4931 type 4015 type = "critical";
4932 }; 4016 };
4933 }; 4017 };
4934 4018
4935 cooling-maps { 4019 cooling-maps {
4936 map0 { 4020 map0 {
4937 trip 4021 trip = <&cpu7_top_alert0>;
4938 cooli 4022 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4023 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4024 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4025 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4026 };
4943 map1 { 4027 map1 {
4944 trip 4028 trip = <&cpu7_top_alert1>;
4945 cooli 4029 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4030 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4031 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4032 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4033 };
4950 }; 4034 };
4951 }; 4035 };
4952 4036
4953 cpu4-bottom-thermal { 4037 cpu4-bottom-thermal {
4954 polling-delay-passive 4038 polling-delay-passive = <250>;
>> 4039 polling-delay = <1000>;
4955 4040
4956 thermal-sensors = <&t 4041 thermal-sensors = <&tsens0 11>;
4957 4042
4958 trips { 4043 trips {
4959 cpu4_bottom_a 4044 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4045 temperature = <90000>;
4961 hyste 4046 hysteresis = <2000>;
4962 type 4047 type = "passive";
4963 }; 4048 };
4964 4049
4965 cpu4_bottom_a 4050 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4051 temperature = <95000>;
4967 hyste 4052 hysteresis = <2000>;
4968 type 4053 type = "passive";
4969 }; 4054 };
4970 4055
4971 cpu4_bottom_c !! 4056 cpu4_bottom_crit: cpu_crit {
4972 tempe 4057 temperature = <110000>;
4973 hyste 4058 hysteresis = <1000>;
4974 type 4059 type = "critical";
4975 }; 4060 };
4976 }; 4061 };
4977 4062
4978 cooling-maps { 4063 cooling-maps {
4979 map0 { 4064 map0 {
4980 trip 4065 trip = <&cpu4_bottom_alert0>;
4981 cooli 4066 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4067 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4068 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4069 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4070 };
4986 map1 { 4071 map1 {
4987 trip 4072 trip = <&cpu4_bottom_alert1>;
4988 cooli 4073 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4074 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4075 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4076 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4077 };
4993 }; 4078 };
4994 }; 4079 };
4995 4080
4996 cpu5-bottom-thermal { 4081 cpu5-bottom-thermal {
4997 polling-delay-passive 4082 polling-delay-passive = <250>;
>> 4083 polling-delay = <1000>;
4998 4084
4999 thermal-sensors = <&t 4085 thermal-sensors = <&tsens0 12>;
5000 4086
5001 trips { 4087 trips {
5002 cpu5_bottom_a 4088 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4089 temperature = <90000>;
5004 hyste 4090 hysteresis = <2000>;
5005 type 4091 type = "passive";
5006 }; 4092 };
5007 4093
5008 cpu5_bottom_a 4094 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4095 temperature = <95000>;
5010 hyste 4096 hysteresis = <2000>;
5011 type 4097 type = "passive";
5012 }; 4098 };
5013 4099
5014 cpu5_bottom_c !! 4100 cpu5_bottom_crit: cpu_crit {
5015 tempe 4101 temperature = <110000>;
5016 hyste 4102 hysteresis = <1000>;
5017 type 4103 type = "critical";
5018 }; 4104 };
5019 }; 4105 };
5020 4106
5021 cooling-maps { 4107 cooling-maps {
5022 map0 { 4108 map0 {
5023 trip 4109 trip = <&cpu5_bottom_alert0>;
5024 cooli 4110 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4111 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4112 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4113 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4114 };
5029 map1 { 4115 map1 {
5030 trip 4116 trip = <&cpu5_bottom_alert1>;
5031 cooli 4117 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4118 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4119 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4120 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4121 };
5036 }; 4122 };
5037 }; 4123 };
5038 4124
5039 cpu6-bottom-thermal { 4125 cpu6-bottom-thermal {
5040 polling-delay-passive 4126 polling-delay-passive = <250>;
>> 4127 polling-delay = <1000>;
5041 4128
5042 thermal-sensors = <&t 4129 thermal-sensors = <&tsens0 13>;
5043 4130
5044 trips { 4131 trips {
5045 cpu6_bottom_a 4132 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4133 temperature = <90000>;
5047 hyste 4134 hysteresis = <2000>;
5048 type 4135 type = "passive";
5049 }; 4136 };
5050 4137
5051 cpu6_bottom_a 4138 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4139 temperature = <95000>;
5053 hyste 4140 hysteresis = <2000>;
5054 type 4141 type = "passive";
5055 }; 4142 };
5056 4143
5057 cpu6_bottom_c !! 4144 cpu6_bottom_crit: cpu_crit {
5058 tempe 4145 temperature = <110000>;
5059 hyste 4146 hysteresis = <1000>;
5060 type 4147 type = "critical";
5061 }; 4148 };
5062 }; 4149 };
5063 4150
5064 cooling-maps { 4151 cooling-maps {
5065 map0 { 4152 map0 {
5066 trip 4153 trip = <&cpu6_bottom_alert0>;
5067 cooli 4154 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4155 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4156 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4157 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4158 };
5072 map1 { 4159 map1 {
5073 trip 4160 trip = <&cpu6_bottom_alert1>;
5074 cooli 4161 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4162 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4163 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4164 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4165 };
5079 }; 4166 };
5080 }; 4167 };
5081 4168
5082 cpu7-bottom-thermal { 4169 cpu7-bottom-thermal {
5083 polling-delay-passive 4170 polling-delay-passive = <250>;
>> 4171 polling-delay = <1000>;
5084 4172
5085 thermal-sensors = <&t 4173 thermal-sensors = <&tsens0 14>;
5086 4174
5087 trips { 4175 trips {
5088 cpu7_bottom_a 4176 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4177 temperature = <90000>;
5090 hyste 4178 hysteresis = <2000>;
5091 type 4179 type = "passive";
5092 }; 4180 };
5093 4181
5094 cpu7_bottom_a 4182 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4183 temperature = <95000>;
5096 hyste 4184 hysteresis = <2000>;
5097 type 4185 type = "passive";
5098 }; 4186 };
5099 4187
5100 cpu7_bottom_c !! 4188 cpu7_bottom_crit: cpu_crit {
5101 tempe 4189 temperature = <110000>;
5102 hyste 4190 hysteresis = <1000>;
5103 type 4191 type = "critical";
5104 }; 4192 };
5105 }; 4193 };
5106 4194
5107 cooling-maps { 4195 cooling-maps {
5108 map0 { 4196 map0 {
5109 trip 4197 trip = <&cpu7_bottom_alert0>;
5110 cooli 4198 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4199 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4200 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4201 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4202 };
5115 map1 { 4203 map1 {
5116 trip 4204 trip = <&cpu7_bottom_alert1>;
5117 cooli 4205 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4206 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4207 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4208 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4209 };
5122 }; 4210 };
5123 }; 4211 };
5124 4212
5125 aoss0-thermal { 4213 aoss0-thermal {
5126 polling-delay-passive 4214 polling-delay-passive = <250>;
>> 4215 polling-delay = <1000>;
5127 4216
5128 thermal-sensors = <&t 4217 thermal-sensors = <&tsens0 0>;
5129 4218
5130 trips { 4219 trips {
5131 aoss0_alert0: 4220 aoss0_alert0: trip-point0 {
5132 tempe 4221 temperature = <90000>;
5133 hyste 4222 hysteresis = <2000>;
5134 type 4223 type = "hot";
5135 }; 4224 };
5136 }; 4225 };
5137 }; 4226 };
5138 4227
5139 cluster0-thermal { 4228 cluster0-thermal {
5140 polling-delay-passive 4229 polling-delay-passive = <250>;
>> 4230 polling-delay = <1000>;
5141 4231
5142 thermal-sensors = <&t 4232 thermal-sensors = <&tsens0 5>;
5143 4233
5144 trips { 4234 trips {
5145 cluster0_aler 4235 cluster0_alert0: trip-point0 {
5146 tempe 4236 temperature = <90000>;
5147 hyste 4237 hysteresis = <2000>;
5148 type 4238 type = "hot";
5149 }; 4239 };
5150 cluster0_crit !! 4240 cluster0_crit: cluster0_crit {
5151 tempe 4241 temperature = <110000>;
5152 hyste 4242 hysteresis = <2000>;
5153 type 4243 type = "critical";
5154 }; 4244 };
5155 }; 4245 };
5156 }; 4246 };
5157 4247
5158 cluster1-thermal { 4248 cluster1-thermal {
5159 polling-delay-passive 4249 polling-delay-passive = <250>;
>> 4250 polling-delay = <1000>;
5160 4251
5161 thermal-sensors = <&t 4252 thermal-sensors = <&tsens0 6>;
5162 4253
5163 trips { 4254 trips {
5164 cluster1_aler 4255 cluster1_alert0: trip-point0 {
5165 tempe 4256 temperature = <90000>;
5166 hyste 4257 hysteresis = <2000>;
5167 type 4258 type = "hot";
5168 }; 4259 };
5169 cluster1_crit !! 4260 cluster1_crit: cluster1_crit {
5170 tempe 4261 temperature = <110000>;
5171 hyste 4262 hysteresis = <2000>;
5172 type 4263 type = "critical";
5173 }; 4264 };
5174 }; 4265 };
5175 }; 4266 };
5176 4267
5177 gpu-top-thermal { !! 4268 gpu-thermal-top {
5178 polling-delay-passive 4269 polling-delay-passive = <250>;
>> 4270 polling-delay = <1000>;
5179 4271
5180 thermal-sensors = <&t 4272 thermal-sensors = <&tsens0 15>;
5181 4273
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4274 trips {
5190 gpu_top_alert !! 4275 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4276 temperature = <90000>;
5198 hyste !! 4277 hysteresis = <2000>;
5199 type 4278 type = "hot";
5200 }; 4279 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4280 };
5208 }; 4281 };
5209 4282
5210 aoss1-thermal { 4283 aoss1-thermal {
5211 polling-delay-passive 4284 polling-delay-passive = <250>;
>> 4285 polling-delay = <1000>;
5212 4286
5213 thermal-sensors = <&t 4287 thermal-sensors = <&tsens1 0>;
5214 4288
5215 trips { 4289 trips {
5216 aoss1_alert0: 4290 aoss1_alert0: trip-point0 {
5217 tempe 4291 temperature = <90000>;
5218 hyste 4292 hysteresis = <2000>;
5219 type 4293 type = "hot";
5220 }; 4294 };
5221 }; 4295 };
5222 }; 4296 };
5223 4297
5224 wlan-thermal { 4298 wlan-thermal {
5225 polling-delay-passive 4299 polling-delay-passive = <250>;
>> 4300 polling-delay = <1000>;
5226 4301
5227 thermal-sensors = <&t 4302 thermal-sensors = <&tsens1 1>;
5228 4303
5229 trips { 4304 trips {
5230 wlan_alert0: 4305 wlan_alert0: trip-point0 {
5231 tempe 4306 temperature = <90000>;
5232 hyste 4307 hysteresis = <2000>;
5233 type 4308 type = "hot";
5234 }; 4309 };
5235 }; 4310 };
5236 }; 4311 };
5237 4312
5238 video-thermal { 4313 video-thermal {
5239 polling-delay-passive 4314 polling-delay-passive = <250>;
>> 4315 polling-delay = <1000>;
5240 4316
5241 thermal-sensors = <&t 4317 thermal-sensors = <&tsens1 2>;
5242 4318
5243 trips { 4319 trips {
5244 video_alert0: 4320 video_alert0: trip-point0 {
5245 tempe 4321 temperature = <90000>;
5246 hyste 4322 hysteresis = <2000>;
5247 type 4323 type = "hot";
5248 }; 4324 };
5249 }; 4325 };
5250 }; 4326 };
5251 4327
5252 mem-thermal { 4328 mem-thermal {
5253 polling-delay-passive 4329 polling-delay-passive = <250>;
>> 4330 polling-delay = <1000>;
5254 4331
5255 thermal-sensors = <&t 4332 thermal-sensors = <&tsens1 3>;
5256 4333
5257 trips { 4334 trips {
5258 mem_alert0: t 4335 mem_alert0: trip-point0 {
5259 tempe 4336 temperature = <90000>;
5260 hyste 4337 hysteresis = <2000>;
5261 type 4338 type = "hot";
5262 }; 4339 };
5263 }; 4340 };
5264 }; 4341 };
5265 4342
5266 q6-hvx-thermal { 4343 q6-hvx-thermal {
5267 polling-delay-passive 4344 polling-delay-passive = <250>;
>> 4345 polling-delay = <1000>;
5268 4346
5269 thermal-sensors = <&t 4347 thermal-sensors = <&tsens1 4>;
5270 4348
5271 trips { 4349 trips {
5272 q6_hvx_alert0 4350 q6_hvx_alert0: trip-point0 {
5273 tempe 4351 temperature = <90000>;
5274 hyste 4352 hysteresis = <2000>;
5275 type 4353 type = "hot";
5276 }; 4354 };
5277 }; 4355 };
5278 }; 4356 };
5279 4357
5280 camera-thermal { 4358 camera-thermal {
5281 polling-delay-passive 4359 polling-delay-passive = <250>;
>> 4360 polling-delay = <1000>;
5282 4361
5283 thermal-sensors = <&t 4362 thermal-sensors = <&tsens1 5>;
5284 4363
5285 trips { 4364 trips {
5286 camera_alert0 4365 camera_alert0: trip-point0 {
5287 tempe 4366 temperature = <90000>;
5288 hyste 4367 hysteresis = <2000>;
5289 type 4368 type = "hot";
5290 }; 4369 };
5291 }; 4370 };
5292 }; 4371 };
5293 4372
5294 compute-thermal { 4373 compute-thermal {
5295 polling-delay-passive 4374 polling-delay-passive = <250>;
>> 4375 polling-delay = <1000>;
5296 4376
5297 thermal-sensors = <&t 4377 thermal-sensors = <&tsens1 6>;
5298 4378
5299 trips { 4379 trips {
5300 compute_alert 4380 compute_alert0: trip-point0 {
5301 tempe 4381 temperature = <90000>;
5302 hyste 4382 hysteresis = <2000>;
5303 type 4383 type = "hot";
5304 }; 4384 };
5305 }; 4385 };
5306 }; 4386 };
5307 4387
5308 modem-thermal { 4388 modem-thermal {
5309 polling-delay-passive 4389 polling-delay-passive = <250>;
>> 4390 polling-delay = <1000>;
5310 4391
5311 thermal-sensors = <&t 4392 thermal-sensors = <&tsens1 7>;
5312 4393
5313 trips { 4394 trips {
5314 modem_alert0: 4395 modem_alert0: trip-point0 {
5315 tempe 4396 temperature = <90000>;
5316 hyste 4397 hysteresis = <2000>;
5317 type 4398 type = "hot";
5318 }; 4399 };
5319 }; 4400 };
5320 }; 4401 };
5321 4402
5322 npu-thermal { 4403 npu-thermal {
5323 polling-delay-passive 4404 polling-delay-passive = <250>;
>> 4405 polling-delay = <1000>;
5324 4406
5325 thermal-sensors = <&t 4407 thermal-sensors = <&tsens1 8>;
5326 4408
5327 trips { 4409 trips {
5328 npu_alert0: t 4410 npu_alert0: trip-point0 {
5329 tempe 4411 temperature = <90000>;
5330 hyste 4412 hysteresis = <2000>;
5331 type 4413 type = "hot";
5332 }; 4414 };
5333 }; 4415 };
5334 }; 4416 };
5335 4417
5336 modem-vec-thermal { 4418 modem-vec-thermal {
5337 polling-delay-passive 4419 polling-delay-passive = <250>;
>> 4420 polling-delay = <1000>;
5338 4421
5339 thermal-sensors = <&t 4422 thermal-sensors = <&tsens1 9>;
5340 4423
5341 trips { 4424 trips {
5342 modem_vec_ale 4425 modem_vec_alert0: trip-point0 {
5343 tempe 4426 temperature = <90000>;
5344 hyste 4427 hysteresis = <2000>;
5345 type 4428 type = "hot";
5346 }; 4429 };
5347 }; 4430 };
5348 }; 4431 };
5349 4432
5350 modem-scl-thermal { 4433 modem-scl-thermal {
5351 polling-delay-passive 4434 polling-delay-passive = <250>;
>> 4435 polling-delay = <1000>;
5352 4436
5353 thermal-sensors = <&t 4437 thermal-sensors = <&tsens1 10>;
5354 4438
5355 trips { 4439 trips {
5356 modem_scl_ale 4440 modem_scl_alert0: trip-point0 {
5357 tempe 4441 temperature = <90000>;
5358 hyste 4442 hysteresis = <2000>;
5359 type 4443 type = "hot";
5360 }; 4444 };
5361 }; 4445 };
5362 }; 4446 };
5363 4447
5364 gpu-bottom-thermal { !! 4448 gpu-thermal-bottom {
5365 polling-delay-passive 4449 polling-delay-passive = <250>;
>> 4450 polling-delay = <1000>;
5366 4451
5367 thermal-sensors = <&t 4452 thermal-sensors = <&tsens1 11>;
5368 4453
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 4454 trips {
5377 gpu_bottom_al !! 4455 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 4456 temperature = <90000>;
5385 hyste !! 4457 hysteresis = <2000>;
5386 type 4458 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 4459 };
5394 }; 4460 };
5395 }; 4461 };
5396 }; 4462 };
5397 }; 4463 };
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