1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 15 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
22 17
23 / { 18 / {
24 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
25 20
26 #address-cells = <2>; 21 #address-cells = <2>;
27 #size-cells = <2>; 22 #size-cells = <2>;
28 23
29 chosen { }; 24 chosen { };
30 25
31 clocks { 26 clocks {
32 xo_board: xo-board { 27 xo_board: xo-board {
33 compatible = "fixed-cl 28 compatible = "fixed-clock";
34 #clock-cells = <0>; 29 #clock-cells = <0>;
35 clock-frequency = <384 30 clock-frequency = <38400000>;
36 clock-output-names = " 31 clock-output-names = "xo_board";
37 }; 32 };
38 33
39 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 35 compatible = "fixed-clock";
41 #clock-cells = <0>; 36 #clock-cells = <0>;
42 clock-frequency = <327 37 clock-frequency = <32764>;
43 clock-output-names = " 38 clock-output-names = "sleep_clk";
44 }; 39 };
45 }; 40 };
46 41
47 cpus { 42 cpus {
48 #address-cells = <2>; 43 #address-cells = <2>;
49 #size-cells = <0>; 44 #size-cells = <0>;
50 45
51 CPU0: cpu@0 { 46 CPU0: cpu@0 {
52 device_type = "cpu"; 47 device_type = "cpu";
53 compatible = "qcom,kry 48 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 50 enable-method = "psci";
57 capacity-dmips-mhz = < 51 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 52 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 53 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 54 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 55 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 58 power-domains = <&CPU_PD0>;
65 power-domain-names = " 59 power-domain-names = "psci";
66 #cooling-cells = <2>; 60 #cooling-cells = <2>;
67 L2_0: l2-cache { 61 L2_0: l2-cache {
68 compatible = " 62 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 63 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 64 L3_0: l3-cache {
73 compat !! 65 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 66 };
77 }; 67 };
78 }; 68 };
79 69
80 CPU1: cpu@100 { 70 CPU1: cpu@100 {
81 device_type = "cpu"; 71 device_type = "cpu";
82 compatible = "qcom,kry 72 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 73 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 74 enable-method = "psci";
86 capacity-dmips-mhz = < 75 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 76 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 77 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 79 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 82 power-domains = <&CPU_PD1>;
94 power-domain-names = " 83 power-domain-names = "psci";
95 #cooling-cells = <2>; 84 #cooling-cells = <2>;
96 L2_100: l2-cache { 85 L2_100: l2-cache {
97 compatible = " 86 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 87 next-level-cache = <&L3_0>;
101 }; 88 };
>> 89
102 }; 90 };
103 91
104 CPU2: cpu@200 { 92 CPU2: cpu@200 {
105 device_type = "cpu"; 93 device_type = "cpu";
106 compatible = "qcom,kry 94 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 95 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 96 enable-method = "psci";
110 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 98 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 99 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 101 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 104 power-domains = <&CPU_PD2>;
118 power-domain-names = " 105 power-domain-names = "psci";
119 #cooling-cells = <2>; 106 #cooling-cells = <2>;
120 L2_200: l2-cache { 107 L2_200: l2-cache {
121 compatible = " 108 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 109 next-level-cache = <&L3_0>;
125 }; 110 };
126 }; 111 };
127 112
128 CPU3: cpu@300 { 113 CPU3: cpu@300 {
129 device_type = "cpu"; 114 device_type = "cpu";
130 compatible = "qcom,kry 115 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 116 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 117 enable-method = "psci";
134 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 119 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 120 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 122 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 125 power-domains = <&CPU_PD3>;
142 power-domain-names = " 126 power-domain-names = "psci";
143 #cooling-cells = <2>; 127 #cooling-cells = <2>;
144 L2_300: l2-cache { 128 L2_300: l2-cache {
145 compatible = " 129 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 130 next-level-cache = <&L3_0>;
149 }; 131 };
150 }; 132 };
151 133
152 CPU4: cpu@400 { 134 CPU4: cpu@400 {
153 device_type = "cpu"; 135 device_type = "cpu";
154 compatible = "qcom,kry 136 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 137 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 138 enable-method = "psci";
158 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 140 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 141 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 143 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 146 power-domains = <&CPU_PD4>;
166 power-domain-names = " 147 power-domain-names = "psci";
167 #cooling-cells = <2>; 148 #cooling-cells = <2>;
168 L2_400: l2-cache { 149 L2_400: l2-cache {
169 compatible = " 150 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 151 next-level-cache = <&L3_0>;
173 }; 152 };
174 }; 153 };
175 154
176 CPU5: cpu@500 { 155 CPU5: cpu@500 {
177 device_type = "cpu"; 156 device_type = "cpu";
178 compatible = "qcom,kry 157 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 158 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 159 enable-method = "psci";
182 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 161 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 162 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 163 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 164 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 167 power-domains = <&CPU_PD5>;
190 power-domain-names = " 168 power-domain-names = "psci";
191 #cooling-cells = <2>; 169 #cooling-cells = <2>;
192 L2_500: l2-cache { 170 L2_500: l2-cache {
193 compatible = " 171 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 172 next-level-cache = <&L3_0>;
197 }; 173 };
198 }; 174 };
199 175
200 CPU6: cpu@600 { 176 CPU6: cpu@600 {
201 device_type = "cpu"; 177 device_type = "cpu";
202 compatible = "qcom,kry 178 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 179 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 180 enable-method = "psci";
206 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 182 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 183 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 185 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 188 power-domains = <&CPU_PD6>;
214 power-domain-names = " 189 power-domain-names = "psci";
215 #cooling-cells = <2>; 190 #cooling-cells = <2>;
216 L2_600: l2-cache { 191 L2_600: l2-cache {
217 compatible = " 192 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 193 next-level-cache = <&L3_0>;
221 }; 194 };
222 }; 195 };
223 196
224 CPU7: cpu@700 { 197 CPU7: cpu@700 {
225 device_type = "cpu"; 198 device_type = "cpu";
226 compatible = "qcom,kry 199 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 200 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 201 enable-method = "psci";
230 capacity-dmips-mhz = < 202 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 203 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 204 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 205 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 206 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 209 power-domains = <&CPU_PD7>;
238 power-domain-names = " 210 power-domain-names = "psci";
239 #cooling-cells = <2>; 211 #cooling-cells = <2>;
240 L2_700: l2-cache { 212 L2_700: l2-cache {
241 compatible = " 213 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 214 next-level-cache = <&L3_0>;
245 }; 215 };
246 }; 216 };
247 217
248 cpu-map { 218 cpu-map {
249 cluster0 { 219 cluster0 {
250 core0 { 220 core0 {
251 cpu = 221 cpu = <&CPU0>;
252 }; 222 };
253 223
254 core1 { 224 core1 {
255 cpu = 225 cpu = <&CPU1>;
256 }; 226 };
257 227
258 core2 { 228 core2 {
259 cpu = 229 cpu = <&CPU2>;
260 }; 230 };
261 231
262 core3 { 232 core3 {
263 cpu = 233 cpu = <&CPU3>;
264 }; 234 };
265 235
266 core4 { 236 core4 {
267 cpu = 237 cpu = <&CPU4>;
268 }; 238 };
269 239
270 core5 { 240 core5 {
271 cpu = 241 cpu = <&CPU5>;
272 }; 242 };
273 243
274 core6 { 244 core6 {
275 cpu = 245 cpu = <&CPU6>;
276 }; 246 };
277 247
278 core7 { 248 core7 {
279 cpu = 249 cpu = <&CPU7>;
280 }; 250 };
281 }; 251 };
282 }; 252 };
283 253
284 idle-states { 254 idle-states {
285 entry-method = "psci"; 255 entry-method = "psci";
286 256
287 LITTLE_CPU_SLEEP_0: cp 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 258 compatible = "arm,idle-state";
289 idle-state-nam 259 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 260 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 261 entry-latency-us = <355>;
292 exit-latency-u 262 exit-latency-us = <909>;
293 min-residency- 263 min-residency-us = <3934>;
294 local-timer-st 264 local-timer-stop;
295 }; 265 };
296 266
297 BIG_CPU_SLEEP_0: cpu-s 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 268 compatible = "arm,idle-state";
299 idle-state-nam 269 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 270 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 271 entry-latency-us = <241>;
302 exit-latency-u 272 exit-latency-us = <1461>;
303 min-residency- 273 min-residency-us = <4488>;
304 local-timer-st 274 local-timer-stop;
305 }; 275 };
306 }; 276 };
307 277
308 domain-idle-states { 278 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 279 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 280 compatible = "domain-idle-state";
>> 281 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 282 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 283 entry-latency-us = <3263>;
313 exit-latency-u 284 exit-latency-us = <6562>;
314 min-residency- 285 min-residency-us = <9987>;
>> 286 local-timer-stop;
315 }; 287 };
316 }; 288 };
317 }; 289 };
318 290
319 cpu0_opp_table: opp-table-cpu0 { !! 291 cpu0_opp_table: cpu0_opp_table {
320 compatible = "operating-points 292 compatible = "operating-points-v2";
321 opp-shared; 293 opp-shared;
322 294
323 cpu0_opp1: opp-300000000 { 295 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 296 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 297 opp-peak-kBps = <800000 9600000>;
326 }; 298 };
327 299
328 cpu0_opp2: opp-403200000 { 300 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 301 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 302 opp-peak-kBps = <800000 9600000>;
331 }; 303 };
332 304
333 cpu0_opp3: opp-499200000 { 305 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 306 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 307 opp-peak-kBps = <800000 12902400>;
336 }; 308 };
337 309
338 cpu0_opp4: opp-576000000 { 310 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 311 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 312 opp-peak-kBps = <800000 12902400>;
341 }; 313 };
342 314
343 cpu0_opp5: opp-672000000 { 315 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 316 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 317 opp-peak-kBps = <800000 15974400>;
346 }; 318 };
347 319
348 cpu0_opp6: opp-768000000 { 320 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 321 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 322 opp-peak-kBps = <1804000 19660800>;
351 }; 323 };
352 324
353 cpu0_opp7: opp-844800000 { 325 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 326 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 327 opp-peak-kBps = <1804000 19660800>;
356 }; 328 };
357 329
358 cpu0_opp8: opp-940800000 { 330 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 331 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 332 opp-peak-kBps = <1804000 22732800>;
361 }; 333 };
362 334
363 cpu0_opp9: opp-1036800000 { 335 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 336 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 337 opp-peak-kBps = <1804000 22732800>;
366 }; 338 };
367 339
368 cpu0_opp10: opp-1113600000 { 340 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 341 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 342 opp-peak-kBps = <2188000 25804800>;
371 }; 343 };
372 344
373 cpu0_opp11: opp-1209600000 { 345 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 346 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 347 opp-peak-kBps = <2188000 31948800>;
376 }; 348 };
377 349
378 cpu0_opp12: opp-1305600000 { 350 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 351 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 352 opp-peak-kBps = <3072000 31948800>;
381 }; 353 };
382 354
383 cpu0_opp13: opp-1382400000 { 355 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 356 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 357 opp-peak-kBps = <3072000 31948800>;
386 }; 358 };
387 359
388 cpu0_opp14: opp-1478400000 { 360 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 361 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 362 opp-peak-kBps = <3072000 31948800>;
391 }; 363 };
392 364
393 cpu0_opp15: opp-1555200000 { 365 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 366 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 367 opp-peak-kBps = <3072000 40550400>;
396 }; 368 };
397 369
398 cpu0_opp16: opp-1632000000 { 370 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 371 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 372 opp-peak-kBps = <3072000 40550400>;
401 }; 373 };
402 374
403 cpu0_opp17: opp-1708800000 { 375 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 376 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 377 opp-peak-kBps = <3072000 43008000>;
406 }; 378 };
407 379
408 cpu0_opp18: opp-1785600000 { 380 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 381 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 382 opp-peak-kBps = <3072000 43008000>;
411 }; 383 };
412 }; 384 };
413 385
414 cpu4_opp_table: opp-table-cpu4 { !! 386 cpu4_opp_table: cpu4_opp_table {
415 compatible = "operating-points 387 compatible = "operating-points-v2";
416 opp-shared; 388 opp-shared;
417 389
418 cpu4_opp1: opp-710400000 { 390 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 391 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 392 opp-peak-kBps = <1804000 15974400>;
421 }; 393 };
422 394
423 cpu4_opp2: opp-825600000 { 395 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 396 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 397 opp-peak-kBps = <2188000 19660800>;
426 }; 398 };
427 399
428 cpu4_opp3: opp-940800000 { 400 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 401 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 402 opp-peak-kBps = <2188000 22732800>;
431 }; 403 };
432 404
433 cpu4_opp4: opp-1056000000 { 405 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 406 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 407 opp-peak-kBps = <3072000 25804800>;
436 }; 408 };
437 409
438 cpu4_opp5: opp-1171200000 { 410 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 411 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 412 opp-peak-kBps = <3072000 31948800>;
441 }; 413 };
442 414
443 cpu4_opp6: opp-1286400000 { 415 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 416 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 417 opp-peak-kBps = <4068000 31948800>;
446 }; 418 };
447 419
448 cpu4_opp7: opp-1401600000 { 420 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 421 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 422 opp-peak-kBps = <4068000 31948800>;
451 }; 423 };
452 424
453 cpu4_opp8: opp-1497600000 { 425 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 426 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 427 opp-peak-kBps = <4068000 40550400>;
456 }; 428 };
457 429
458 cpu4_opp9: opp-1612800000 { 430 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 431 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 432 opp-peak-kBps = <4068000 40550400>;
461 }; 433 };
462 434
463 cpu4_opp10: opp-1708800000 { 435 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 436 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 437 opp-peak-kBps = <4068000 43008000>;
466 }; 438 };
467 439
468 cpu4_opp11: opp-1804800000 { 440 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 441 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 442 opp-peak-kBps = <6220000 43008000>;
471 }; 443 };
472 444
473 cpu4_opp12: opp-1920000000 { 445 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 446 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 447 opp-peak-kBps = <6220000 49152000>;
476 }; 448 };
477 449
478 cpu4_opp13: opp-2016000000 { 450 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 451 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 452 opp-peak-kBps = <7216000 49152000>;
481 }; 453 };
482 454
483 cpu4_opp14: opp-2131200000 { 455 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 456 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 457 opp-peak-kBps = <8368000 49152000>;
486 }; 458 };
487 459
488 cpu4_opp15: opp-2227200000 { 460 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 461 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 462 opp-peak-kBps = <8368000 51609600>;
491 }; 463 };
492 464
493 cpu4_opp16: opp-2323200000 { 465 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 466 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 467 opp-peak-kBps = <8368000 51609600>;
496 }; 468 };
497 469
498 cpu4_opp17: opp-2419200000 { 470 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 471 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 472 opp-peak-kBps = <8368000 51609600>;
501 }; 473 };
502 }; 474 };
503 475
504 cpu7_opp_table: opp-table-cpu7 { !! 476 cpu7_opp_table: cpu7_opp_table {
505 compatible = "operating-points 477 compatible = "operating-points-v2";
506 opp-shared; 478 opp-shared;
507 479
508 cpu7_opp1: opp-825600000 { 480 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 481 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 19660800>;
511 }; 483 };
512 484
513 cpu7_opp2: opp-940800000 { 485 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 486 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 487 opp-peak-kBps = <2188000 22732800>;
516 }; 488 };
517 489
518 cpu7_opp3: opp-1056000000 { 490 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 491 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 25804800>;
521 }; 493 };
522 494
523 cpu7_opp4: opp-1171200000 { 495 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 496 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 497 opp-peak-kBps = <3072000 31948800>;
526 }; 498 };
527 499
528 cpu7_opp5: opp-1286400000 { 500 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 501 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 31948800>;
531 }; 503 };
532 504
533 cpu7_opp6: opp-1401600000 { 505 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 506 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 31948800>;
536 }; 508 };
537 509
538 cpu7_opp7: opp-1497600000 { 510 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 511 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 40550400>;
541 }; 513 };
542 514
543 cpu7_opp8: opp-1612800000 { 515 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 516 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 517 opp-peak-kBps = <4068000 40550400>;
546 }; 518 };
547 519
548 cpu7_opp9: opp-1708800000 { 520 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 521 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 522 opp-peak-kBps = <4068000 43008000>;
551 }; 523 };
552 524
553 cpu7_opp10: opp-1804800000 { 525 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 526 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 527 opp-peak-kBps = <6220000 43008000>;
556 }; 528 };
557 529
558 cpu7_opp11: opp-1920000000 { 530 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 531 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 532 opp-peak-kBps = <6220000 49152000>;
561 }; 533 };
562 534
563 cpu7_opp12: opp-2016000000 { 535 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 536 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 537 opp-peak-kBps = <7216000 49152000>;
566 }; 538 };
567 539
568 cpu7_opp13: opp-2131200000 { 540 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 541 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 542 opp-peak-kBps = <8368000 49152000>;
571 }; 543 };
572 544
573 cpu7_opp14: opp-2227200000 { 545 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 546 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 547 opp-peak-kBps = <8368000 51609600>;
576 }; 548 };
577 549
578 cpu7_opp15: opp-2323200000 { 550 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 551 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 552 opp-peak-kBps = <8368000 51609600>;
581 }; 553 };
582 554
583 cpu7_opp16: opp-2419200000 { 555 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 556 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
586 }; 558 };
587 559
588 cpu7_opp17: opp-2534400000 { 560 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 561 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
591 }; 563 };
592 564
593 cpu7_opp18: opp-2649600000 { 565 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 566 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 567 opp-peak-kBps = <8368000 51609600>;
596 }; 568 };
597 569
598 cpu7_opp19: opp-2745600000 { 570 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 571 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 572 opp-peak-kBps = <8368000 51609600>;
601 }; 573 };
602 574
603 cpu7_opp20: opp-2841600000 { 575 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 576 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 577 opp-peak-kBps = <8368000 51609600>;
606 }; 578 };
607 }; 579 };
608 580
609 firmware { 581 firmware {
610 scm: scm { 582 scm: scm {
611 compatible = "qcom,scm 583 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 584 #reset-cells = <1>;
613 }; 585 };
614 }; 586 };
615 587
>> 588 tcsr_mutex: hwlock {
>> 589 compatible = "qcom,tcsr-mutex";
>> 590 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 591 #hwlock-cells = <1>;
>> 592 };
>> 593
616 memory@80000000 { 594 memory@80000000 {
617 device_type = "memory"; 595 device_type = "memory";
618 /* We expect the bootloader to 596 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 597 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 598 };
621 599
622 pmu { 600 pmu {
623 compatible = "arm,armv8-pmuv3" 601 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 602 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 603 };
626 604
627 psci { 605 psci {
628 compatible = "arm,psci-1.0"; 606 compatible = "arm,psci-1.0";
629 method = "smc"; 607 method = "smc";
630 608
631 CPU_PD0: power-domain-cpu0 { !! 609 CPU_PD0: cpu0 {
632 #power-domain-cells = 610 #power-domain-cells = <0>;
633 power-domains = <&CLUS 611 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 613 };
636 614
637 CPU_PD1: power-domain-cpu1 { !! 615 CPU_PD1: cpu1 {
638 #power-domain-cells = 616 #power-domain-cells = <0>;
639 power-domains = <&CLUS 617 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 619 };
642 620
643 CPU_PD2: power-domain-cpu2 { !! 621 CPU_PD2: cpu2 {
644 #power-domain-cells = 622 #power-domain-cells = <0>;
645 power-domains = <&CLUS 623 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 625 };
648 626
649 CPU_PD3: power-domain-cpu3 { !! 627 CPU_PD3: cpu3 {
650 #power-domain-cells = 628 #power-domain-cells = <0>;
651 power-domains = <&CLUS 629 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 631 };
654 632
655 CPU_PD4: power-domain-cpu4 { !! 633 CPU_PD4: cpu4 {
656 #power-domain-cells = 634 #power-domain-cells = <0>;
657 power-domains = <&CLUS 635 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 636 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 637 };
660 638
661 CPU_PD5: power-domain-cpu5 { !! 639 CPU_PD5: cpu5 {
662 #power-domain-cells = 640 #power-domain-cells = <0>;
663 power-domains = <&CLUS 641 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 642 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 643 };
666 644
667 CPU_PD6: power-domain-cpu6 { !! 645 CPU_PD6: cpu6 {
668 #power-domain-cells = 646 #power-domain-cells = <0>;
669 power-domains = <&CLUS 647 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 648 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 649 };
672 650
673 CPU_PD7: power-domain-cpu7 { !! 651 CPU_PD7: cpu7 {
674 #power-domain-cells = 652 #power-domain-cells = <0>;
675 power-domains = <&CLUS 653 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 654 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 655 };
678 656
679 CLUSTER_PD: power-domain-cpu-c !! 657 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 658 #power-domain-cells = <0>;
681 domain-idle-states = < 659 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 660 };
683 }; 661 };
684 662
685 reserved-memory { 663 reserved-memory {
686 #address-cells = <2>; 664 #address-cells = <2>;
687 #size-cells = <2>; 665 #size-cells = <2>;
688 ranges; 666 ranges;
689 667
690 hyp_mem: memory@85700000 { 668 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 669 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 670 no-map;
693 }; 671 };
694 672
695 xbl_mem: memory@85d00000 { 673 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 674 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 675 no-map;
698 }; 676 };
699 677
700 aop_mem: memory@85f00000 { 678 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 679 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 680 no-map;
703 }; 681 };
704 682
705 aop_cmd_db: memory@85f20000 { 683 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 684 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 685 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 686 no-map;
709 }; 687 };
710 688
711 smem_mem: memory@86000000 { 689 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 690 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 691 no-map;
714 }; 692 };
715 693
716 tz_mem: memory@86200000 { 694 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 695 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 696 no-map;
719 }; 697 };
720 698
721 rmtfs_mem: memory@89b00000 { 699 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 700 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 701 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 702 no-map;
725 703
726 qcom,client-id = <1>; 704 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 705 qcom,vmid = <15>;
728 }; 706 };
729 707
730 camera_mem: memory@8b700000 { 708 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 709 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 710 no-map;
733 }; 711 };
734 712
735 wlan_mem: memory@8bc00000 { 713 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 714 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 715 no-map;
738 }; 716 };
739 717
740 npu_mem: memory@8bd80000 { 718 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 719 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 720 no-map;
743 }; 721 };
744 722
745 adsp_mem: memory@8be00000 { 723 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 724 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 725 no-map;
748 }; 726 };
749 727
750 mpss_mem: memory@8d800000 { 728 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 729 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 730 no-map;
753 }; 731 };
754 732
755 venus_mem: memory@96e00000 { 733 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 734 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 735 no-map;
758 }; 736 };
759 737
760 slpi_mem: memory@97300000 { 738 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 739 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 740 no-map;
763 }; 741 };
764 742
765 ipa_fw_mem: memory@98700000 { 743 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 744 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 745 no-map;
768 }; 746 };
769 747
770 ipa_gsi_mem: memory@98710000 { 748 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 749 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 750 no-map;
773 }; 751 };
774 752
775 gpu_mem: memory@98715000 { 753 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 754 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 755 no-map;
778 }; 756 };
779 757
780 spss_mem: memory@98800000 { 758 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 759 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 760 no-map;
783 }; 761 };
784 762
785 cdsp_mem: memory@98900000 { 763 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 764 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 765 no-map;
788 }; 766 };
789 767
790 qseecom_mem: memory@9e400000 { 768 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 769 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 770 no-map;
793 }; 771 };
794 }; 772 };
795 773
796 smem { 774 smem {
797 compatible = "qcom,smem"; 775 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 776 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 777 hwlocks = <&tcsr_mutex 3>;
800 }; 778 };
801 779
802 smp2p-cdsp { 780 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 781 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 782 qcom,smem = <94>, <432>;
805 783
806 interrupts = <GIC_SPI 576 IRQ_ 784 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 785
808 mboxes = <&apss_shared 6>; 786 mboxes = <&apss_shared 6>;
809 787
810 qcom,local-pid = <0>; 788 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 789 qcom,remote-pid = <5>;
812 790
813 cdsp_smp2p_out: master-kernel 791 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 792 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 793 #qcom,smem-state-cells = <1>;
816 }; 794 };
817 795
818 cdsp_smp2p_in: slave-kernel { 796 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 797 qcom,entry-name = "slave-kernel";
820 798
821 interrupt-controller; 799 interrupt-controller;
822 #interrupt-cells = <2> 800 #interrupt-cells = <2>;
823 }; 801 };
824 }; 802 };
825 803
826 smp2p-lpass { 804 smp2p-lpass {
827 compatible = "qcom,smp2p"; 805 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 806 qcom,smem = <443>, <429>;
829 807
830 interrupts = <GIC_SPI 158 IRQ_ 808 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 809
832 mboxes = <&apss_shared 10>; 810 mboxes = <&apss_shared 10>;
833 811
834 qcom,local-pid = <0>; 812 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 813 qcom,remote-pid = <2>;
836 814
837 adsp_smp2p_out: master-kernel 815 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 816 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 817 #qcom,smem-state-cells = <1>;
840 }; 818 };
841 819
842 adsp_smp2p_in: slave-kernel { 820 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 821 qcom,entry-name = "slave-kernel";
844 822
845 interrupt-controller; 823 interrupt-controller;
846 #interrupt-cells = <2> 824 #interrupt-cells = <2>;
847 }; 825 };
848 }; 826 };
849 827
850 smp2p-mpss { 828 smp2p-mpss {
851 compatible = "qcom,smp2p"; 829 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 830 qcom,smem = <435>, <428>;
853 831
854 interrupts = <GIC_SPI 451 IRQ_ 832 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 833
856 mboxes = <&apss_shared 14>; 834 mboxes = <&apss_shared 14>;
857 835
858 qcom,local-pid = <0>; 836 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 837 qcom,remote-pid = <1>;
860 838
861 modem_smp2p_out: master-kernel 839 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 840 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 841 #qcom,smem-state-cells = <1>;
864 }; 842 };
865 843
866 modem_smp2p_in: slave-kernel { 844 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 845 qcom,entry-name = "slave-kernel";
868 846
869 interrupt-controller; 847 interrupt-controller;
870 #interrupt-cells = <2> 848 #interrupt-cells = <2>;
871 }; 849 };
872 }; 850 };
873 851
874 smp2p-slpi { 852 smp2p-slpi {
875 compatible = "qcom,smp2p"; 853 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 854 qcom,smem = <481>, <430>;
877 855
878 interrupts = <GIC_SPI 172 IRQ_ 856 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 857
880 mboxes = <&apss_shared 26>; 858 mboxes = <&apss_shared 26>;
881 859
882 qcom,local-pid = <0>; 860 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 861 qcom,remote-pid = <3>;
884 862
885 slpi_smp2p_out: master-kernel 863 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 864 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 865 #qcom,smem-state-cells = <1>;
888 }; 866 };
889 867
890 slpi_smp2p_in: slave-kernel { 868 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 869 qcom,entry-name = "slave-kernel";
892 870
893 interrupt-controller; 871 interrupt-controller;
894 #interrupt-cells = <2> 872 #interrupt-cells = <2>;
895 }; 873 };
896 }; 874 };
897 875
898 soc: soc@0 { 876 soc: soc@0 {
899 #address-cells = <2>; 877 #address-cells = <2>;
900 #size-cells = <2>; 878 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 879 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 880 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 881 compatible = "simple-bus";
904 882
905 gcc: clock-controller@100000 { 883 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 884 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 885 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 886 #clock-cells = <1>;
909 #reset-cells = <1>; 887 #reset-cells = <1>;
910 #power-domain-cells = 888 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 889 clock-names = "bi_tcxo",
912 "sleep_c 890 "sleep_clk";
913 clocks = <&rpmhcc RPMH 891 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 892 <&sleep_clk>;
915 }; 893 };
916 894
917 gpi_dma0: dma-controller@80000 895 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 !! 896 compatible = "qcom,sm8150-gpi-dma";
919 reg = <0 0x00800000 0 !! 897 reg = <0 0x800000 0 0x60000>;
920 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 910 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 911 dma-channels = <13>;
934 dma-channel-mask = <0x 912 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 913 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 914 #dma-cells = <3>;
937 status = "disabled"; 915 status = "disabled";
938 }; 916 };
939 917
940 ethernet: ethernet@20000 { <<
941 compatible = "qcom,sm8 <<
942 reg = <0x0 0x00020000 <<
943 <0x0 0x00036000 <<
944 reg-names = "stmmaceth <<
945 clock-names = "stmmace <<
946 clocks = <&gcc GCC_EMA <<
947 <&gcc GCC_EMAC <<
948 <&gcc GCC_EMAC <<
949 <&gcc GCC_EMAC <<
950 interrupts = <GIC_SPI <<
951 <GIC_SPI <<
952 interrupt-names = "mac <<
953 <<
954 power-domains = <&gcc <<
955 resets = <&gcc GCC_EMA <<
956 <<
957 iommus = <&apps_smmu 0 <<
958 <<
959 snps,tso; <<
960 rx-fifo-depth = <4096> <<
961 tx-fifo-depth = <4096> <<
962 <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 <<
978 qupv3_id_0: geniqup@8c0000 { 918 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 919 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 920 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 921 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 922 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 923 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 924 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 925 #address-cells = <2>;
986 #size-cells = <2>; 926 #size-cells = <2>;
987 ranges; 927 ranges;
988 status = "disabled"; 928 status = "disabled";
989 929
990 i2c0: i2c@880000 { 930 i2c0: i2c@880000 {
991 compatible = " 931 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 932 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 933 clock-names = "se";
994 clocks = <&gcc 934 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 935 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 936 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 937 dma-names = "tx", "rx";
998 pinctrl-names 938 pinctrl-names = "default";
999 pinctrl-0 = <& 939 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 940 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 941 #address-cells = <1>;
1002 #size-cells = 942 #size-cells = <0>;
1003 status = "dis 943 status = "disabled";
1004 }; 944 };
1005 945
1006 spi0: spi@880000 { 946 spi0: spi@880000 {
1007 compatible = 947 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 !! 948 reg = <0 0x880000 0 0x4000>;
1009 reg-names = " 949 reg-names = "se";
1010 clock-names = 950 clock-names = "se";
1011 clocks = <&gc 951 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 952 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 953 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 954 dma-names = "tx", "rx";
1015 pinctrl-names 955 pinctrl-names = "default";
1016 pinctrl-0 = < 956 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 957 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 958 spi-max-frequency = <50000000>;
1019 #address-cell 959 #address-cells = <1>;
1020 #size-cells = 960 #size-cells = <0>;
1021 status = "dis 961 status = "disabled";
1022 }; 962 };
1023 963
1024 i2c1: i2c@884000 { 964 i2c1: i2c@884000 {
1025 compatible = 965 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 966 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 967 clock-names = "se";
1028 clocks = <&gc 968 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 969 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 970 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 971 dma-names = "tx", "rx";
1032 pinctrl-names 972 pinctrl-names = "default";
1033 pinctrl-0 = < 973 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 974 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 975 #address-cells = <1>;
1036 #size-cells = 976 #size-cells = <0>;
1037 status = "dis 977 status = "disabled";
1038 }; 978 };
1039 979
1040 spi1: spi@884000 { 980 spi1: spi@884000 {
1041 compatible = 981 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 !! 982 reg = <0 0x884000 0 0x4000>;
1043 reg-names = " 983 reg-names = "se";
1044 clock-names = 984 clock-names = "se";
1045 clocks = <&gc 985 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 986 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 987 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 988 dma-names = "tx", "rx";
1049 pinctrl-names 989 pinctrl-names = "default";
1050 pinctrl-0 = < 990 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 991 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 992 spi-max-frequency = <50000000>;
1053 #address-cell 993 #address-cells = <1>;
1054 #size-cells = 994 #size-cells = <0>;
1055 status = "dis 995 status = "disabled";
1056 }; 996 };
1057 997
1058 i2c2: i2c@888000 { 998 i2c2: i2c@888000 {
1059 compatible = 999 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1000 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1001 clock-names = "se";
1062 clocks = <&gc 1002 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1003 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1004 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1005 dma-names = "tx", "rx";
1066 pinctrl-names 1006 pinctrl-names = "default";
1067 pinctrl-0 = < 1007 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1008 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1009 #address-cells = <1>;
1070 #size-cells = 1010 #size-cells = <0>;
1071 status = "dis 1011 status = "disabled";
1072 }; 1012 };
1073 1013
1074 spi2: spi@888000 { 1014 spi2: spi@888000 {
1075 compatible = 1015 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 !! 1016 reg = <0 0x888000 0 0x4000>;
1077 reg-names = " 1017 reg-names = "se";
1078 clock-names = 1018 clock-names = "se";
1079 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1020 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1021 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1022 dma-names = "tx", "rx";
1083 pinctrl-names 1023 pinctrl-names = "default";
1084 pinctrl-0 = < 1024 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1025 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1026 spi-max-frequency = <50000000>;
1087 #address-cell 1027 #address-cells = <1>;
1088 #size-cells = 1028 #size-cells = <0>;
1089 status = "dis 1029 status = "disabled";
1090 }; 1030 };
1091 1031
1092 i2c3: i2c@88c000 { 1032 i2c3: i2c@88c000 {
1093 compatible = 1033 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1034 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1035 clock-names = "se";
1096 clocks = <&gc 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1037 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1038 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1039 dma-names = "tx", "rx";
1100 pinctrl-names 1040 pinctrl-names = "default";
1101 pinctrl-0 = < 1041 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1042 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1043 #address-cells = <1>;
1104 #size-cells = 1044 #size-cells = <0>;
1105 status = "dis 1045 status = "disabled";
1106 }; 1046 };
1107 1047
1108 spi3: spi@88c000 { 1048 spi3: spi@88c000 {
1109 compatible = 1049 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 !! 1050 reg = <0 0x88c000 0 0x4000>;
1111 reg-names = " 1051 reg-names = "se";
1112 clock-names = 1052 clock-names = "se";
1113 clocks = <&gc 1053 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1054 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1055 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1056 dma-names = "tx", "rx";
1117 pinctrl-names 1057 pinctrl-names = "default";
1118 pinctrl-0 = < 1058 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1059 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1060 spi-max-frequency = <50000000>;
1121 #address-cell 1061 #address-cells = <1>;
1122 #size-cells = 1062 #size-cells = <0>;
1123 status = "dis 1063 status = "disabled";
1124 }; 1064 };
1125 1065
1126 i2c4: i2c@890000 { 1066 i2c4: i2c@890000 {
1127 compatible = 1067 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1068 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1069 clock-names = "se";
1130 clocks = <&gc 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1071 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1072 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1073 dma-names = "tx", "rx";
1134 pinctrl-names 1074 pinctrl-names = "default";
1135 pinctrl-0 = < 1075 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1076 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1077 #address-cells = <1>;
1138 #size-cells = 1078 #size-cells = <0>;
1139 status = "dis 1079 status = "disabled";
1140 }; 1080 };
1141 1081
1142 spi4: spi@890000 { 1082 spi4: spi@890000 {
1143 compatible = 1083 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 !! 1084 reg = <0 0x890000 0 0x4000>;
1145 reg-names = " 1085 reg-names = "se";
1146 clock-names = 1086 clock-names = "se";
1147 clocks = <&gc 1087 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1088 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1089 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1090 dma-names = "tx", "rx";
1151 pinctrl-names 1091 pinctrl-names = "default";
1152 pinctrl-0 = < 1092 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1093 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1094 spi-max-frequency = <50000000>;
1155 #address-cell 1095 #address-cells = <1>;
1156 #size-cells = 1096 #size-cells = <0>;
1157 status = "dis 1097 status = "disabled";
1158 }; 1098 };
1159 1099
1160 i2c5: i2c@894000 { 1100 i2c5: i2c@894000 {
1161 compatible = 1101 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1102 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1103 clock-names = "se";
1164 clocks = <&gc 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1105 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1106 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1107 dma-names = "tx", "rx";
1168 pinctrl-names 1108 pinctrl-names = "default";
1169 pinctrl-0 = < 1109 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1110 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1111 #address-cells = <1>;
1172 #size-cells = 1112 #size-cells = <0>;
1173 status = "dis 1113 status = "disabled";
1174 }; 1114 };
1175 1115
1176 spi5: spi@894000 { 1116 spi5: spi@894000 {
1177 compatible = 1117 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 !! 1118 reg = <0 0x894000 0 0x4000>;
1179 reg-names = " 1119 reg-names = "se";
1180 clock-names = 1120 clock-names = "se";
1181 clocks = <&gc 1121 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1122 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1123 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1124 dma-names = "tx", "rx";
1185 pinctrl-names 1125 pinctrl-names = "default";
1186 pinctrl-0 = < 1126 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1127 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1128 spi-max-frequency = <50000000>;
1189 #address-cell 1129 #address-cells = <1>;
1190 #size-cells = 1130 #size-cells = <0>;
1191 status = "dis 1131 status = "disabled";
1192 }; 1132 };
1193 1133
1194 i2c6: i2c@898000 { 1134 i2c6: i2c@898000 {
1195 compatible = 1135 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1136 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1137 clock-names = "se";
1198 clocks = <&gc 1138 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1139 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1140 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1141 dma-names = "tx", "rx";
1202 pinctrl-names 1142 pinctrl-names = "default";
1203 pinctrl-0 = < 1143 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1144 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1145 #address-cells = <1>;
1206 #size-cells = 1146 #size-cells = <0>;
1207 status = "dis 1147 status = "disabled";
1208 }; 1148 };
1209 1149
1210 spi6: spi@898000 { 1150 spi6: spi@898000 {
1211 compatible = 1151 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 !! 1152 reg = <0 0x898000 0 0x4000>;
1213 reg-names = " 1153 reg-names = "se";
1214 clock-names = 1154 clock-names = "se";
1215 clocks = <&gc 1155 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1156 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1157 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1158 dma-names = "tx", "rx";
1219 pinctrl-names 1159 pinctrl-names = "default";
1220 pinctrl-0 = < 1160 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1161 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1162 spi-max-frequency = <50000000>;
1223 #address-cell 1163 #address-cells = <1>;
1224 #size-cells = 1164 #size-cells = <0>;
1225 status = "dis 1165 status = "disabled";
1226 }; 1166 };
1227 1167
1228 i2c7: i2c@89c000 { 1168 i2c7: i2c@89c000 {
1229 compatible = 1169 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1170 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1171 clock-names = "se";
1232 clocks = <&gc 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1173 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1174 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1175 dma-names = "tx", "rx";
1236 pinctrl-names 1176 pinctrl-names = "default";
1237 pinctrl-0 = < 1177 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = !! 1178 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1179 #address-cells = <1>;
1240 #size-cells = 1180 #size-cells = <0>;
1241 status = "dis 1181 status = "disabled";
1242 }; 1182 };
1243 1183
1244 spi7: spi@89c000 { 1184 spi7: spi@89c000 {
1245 compatible = 1185 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 !! 1186 reg = <0 0x89c000 0 0x4000>;
1247 reg-names = " 1187 reg-names = "se";
1248 clock-names = 1188 clock-names = "se";
1249 clocks = <&gc 1189 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1190 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1191 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1192 dma-names = "tx", "rx";
1253 pinctrl-names 1193 pinctrl-names = "default";
1254 pinctrl-0 = < 1194 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1195 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1196 spi-max-frequency = <50000000>;
1257 #address-cell 1197 #address-cells = <1>;
1258 #size-cells = 1198 #size-cells = <0>;
1259 status = "dis 1199 status = "disabled";
1260 }; 1200 };
1261 }; 1201 };
1262 1202
1263 gpi_dma1: dma-controller@a000 1203 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm !! 1204 compatible = "qcom,sm8150-gpi-dma";
1265 reg = <0 0x00a00000 0 !! 1205 reg = <0 0xa00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1206 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1207 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1208 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1209 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1210 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1211 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1212 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1213 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1214 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1215 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1216 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1217 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1218 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1219 dma-channels = <13>;
1280 dma-channel-mask = <0 1220 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1221 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1222 #dma-cells = <3>;
1283 status = "disabled"; 1223 status = "disabled";
1284 }; 1224 };
1285 1225
1286 qupv3_id_1: geniqup@ac0000 { 1226 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1227 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1228 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1229 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1230 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1231 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1232 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1233 #address-cells = <2>;
1294 #size-cells = <2>; 1234 #size-cells = <2>;
1295 ranges; 1235 ranges;
1296 status = "disabled"; 1236 status = "disabled";
1297 1237
1298 i2c8: i2c@a80000 { 1238 i2c8: i2c@a80000 {
1299 compatible = 1239 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1240 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1241 clock-names = "se";
1302 clocks = <&gc 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1243 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1244 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1245 dma-names = "tx", "rx";
1306 pinctrl-names 1246 pinctrl-names = "default";
1307 pinctrl-0 = < 1247 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1248 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1249 #address-cells = <1>;
1310 #size-cells = 1250 #size-cells = <0>;
1311 status = "dis 1251 status = "disabled";
1312 }; 1252 };
1313 1253
1314 spi8: spi@a80000 { 1254 spi8: spi@a80000 {
1315 compatible = 1255 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 !! 1256 reg = <0 0xa80000 0 0x4000>;
1317 reg-names = " 1257 reg-names = "se";
1318 clock-names = 1258 clock-names = "se";
1319 clocks = <&gc 1259 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1260 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1261 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1262 dma-names = "tx", "rx";
1323 pinctrl-names 1263 pinctrl-names = "default";
1324 pinctrl-0 = < 1264 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1265 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1266 spi-max-frequency = <50000000>;
1327 #address-cell 1267 #address-cells = <1>;
1328 #size-cells = 1268 #size-cells = <0>;
1329 status = "dis 1269 status = "disabled";
1330 }; 1270 };
1331 1271
1332 i2c9: i2c@a84000 { 1272 i2c9: i2c@a84000 {
1333 compatible = 1273 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1274 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1275 clock-names = "se";
1336 clocks = <&gc 1276 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1277 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1278 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1279 dma-names = "tx", "rx";
1340 pinctrl-names 1280 pinctrl-names = "default";
1341 pinctrl-0 = < 1281 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1282 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1283 #address-cells = <1>;
1344 #size-cells = 1284 #size-cells = <0>;
1345 status = "dis 1285 status = "disabled";
1346 }; 1286 };
1347 1287
1348 spi9: spi@a84000 { 1288 spi9: spi@a84000 {
1349 compatible = 1289 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 !! 1290 reg = <0 0xa84000 0 0x4000>;
1351 reg-names = " 1291 reg-names = "se";
1352 clock-names = 1292 clock-names = "se";
1353 clocks = <&gc 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1294 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1295 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1296 dma-names = "tx", "rx";
1357 pinctrl-names 1297 pinctrl-names = "default";
1358 pinctrl-0 = < 1298 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1300 spi-max-frequency = <50000000>;
1361 #address-cell 1301 #address-cells = <1>;
1362 #size-cells = 1302 #size-cells = <0>;
1363 status = "dis 1303 status = "disabled";
1364 }; 1304 };
1365 1305
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 1306 i2c10: i2c@a88000 {
1378 compatible = 1307 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1308 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1309 clock-names = "se";
1381 clocks = <&gc 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1311 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1312 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1313 dma-names = "tx", "rx";
1385 pinctrl-names 1314 pinctrl-names = "default";
1386 pinctrl-0 = < 1315 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1316 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1317 #address-cells = <1>;
1389 #size-cells = 1318 #size-cells = <0>;
1390 status = "dis 1319 status = "disabled";
1391 }; 1320 };
1392 1321
1393 spi10: spi@a88000 { 1322 spi10: spi@a88000 {
1394 compatible = 1323 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 !! 1324 reg = <0 0xa88000 0 0x4000>;
1396 reg-names = " 1325 reg-names = "se";
1397 clock-names = 1326 clock-names = "se";
1398 clocks = <&gc 1327 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1328 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1329 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1330 dma-names = "tx", "rx";
1402 pinctrl-names 1331 pinctrl-names = "default";
1403 pinctrl-0 = < 1332 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1333 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1334 spi-max-frequency = <50000000>;
1406 #address-cell 1335 #address-cells = <1>;
1407 #size-cells = 1336 #size-cells = <0>;
1408 status = "dis 1337 status = "disabled";
1409 }; 1338 };
1410 1339
1411 i2c11: i2c@a8c000 { 1340 i2c11: i2c@a8c000 {
1412 compatible = 1341 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1342 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1343 clock-names = "se";
1415 clocks = <&gc 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1345 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1346 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1347 dma-names = "tx", "rx";
1419 pinctrl-names 1348 pinctrl-names = "default";
1420 pinctrl-0 = < 1349 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1350 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1351 #address-cells = <1>;
1423 #size-cells = 1352 #size-cells = <0>;
1424 status = "dis 1353 status = "disabled";
1425 }; 1354 };
1426 1355
1427 spi11: spi@a8c000 { 1356 spi11: spi@a8c000 {
1428 compatible = 1357 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 !! 1358 reg = <0 0xa8c000 0 0x4000>;
1430 reg-names = " 1359 reg-names = "se";
1431 clock-names = 1360 clock-names = "se";
1432 clocks = <&gc 1361 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1362 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1363 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1364 dma-names = "tx", "rx";
1436 pinctrl-names 1365 pinctrl-names = "default";
1437 pinctrl-0 = < 1366 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1367 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1368 spi-max-frequency = <50000000>;
1440 #address-cell 1369 #address-cells = <1>;
1441 #size-cells = 1370 #size-cells = <0>;
1442 status = "dis 1371 status = "disabled";
1443 }; 1372 };
1444 1373
1445 uart2: serial@a90000 1374 uart2: serial@a90000 {
1446 compatible = 1375 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1376 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1377 clock-names = "se";
1449 clocks = <&gc 1378 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1379 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1380 status = "disabled";
1452 }; 1381 };
1453 1382
1454 i2c12: i2c@a90000 { 1383 i2c12: i2c@a90000 {
1455 compatible = 1384 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1385 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1386 clock-names = "se";
1458 clocks = <&gc 1387 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1388 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1389 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1390 dma-names = "tx", "rx";
1462 pinctrl-names 1391 pinctrl-names = "default";
1463 pinctrl-0 = < 1392 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1393 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1394 #address-cells = <1>;
1466 #size-cells = 1395 #size-cells = <0>;
1467 status = "dis 1396 status = "disabled";
1468 }; 1397 };
1469 1398
1470 spi12: spi@a90000 { 1399 spi12: spi@a90000 {
1471 compatible = 1400 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 !! 1401 reg = <0 0xa90000 0 0x4000>;
1473 reg-names = " 1402 reg-names = "se";
1474 clock-names = 1403 clock-names = "se";
1475 clocks = <&gc 1404 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1405 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1406 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1407 dma-names = "tx", "rx";
1479 pinctrl-names 1408 pinctrl-names = "default";
1480 pinctrl-0 = < 1409 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1410 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1411 spi-max-frequency = <50000000>;
1483 #address-cell 1412 #address-cells = <1>;
1484 #size-cells = 1413 #size-cells = <0>;
1485 status = "dis 1414 status = "disabled";
1486 }; 1415 };
1487 1416
1488 i2c16: i2c@94000 { 1417 i2c16: i2c@94000 {
1489 compatible = 1418 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 !! 1419 reg = <0 0x0094000 0 0x4000>;
1491 clock-names = 1420 clock-names = "se";
1492 clocks = <&gc 1421 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1422 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1423 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1424 dma-names = "tx", "rx";
1496 pinctrl-names 1425 pinctrl-names = "default";
1497 pinctrl-0 = < 1426 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1427 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1428 #address-cells = <1>;
1500 #size-cells = 1429 #size-cells = <0>;
1501 status = "dis 1430 status = "disabled";
1502 }; 1431 };
1503 1432
1504 spi16: spi@a94000 { 1433 spi16: spi@a94000 {
1505 compatible = 1434 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 !! 1435 reg = <0 0xa94000 0 0x4000>;
1507 reg-names = " 1436 reg-names = "se";
1508 clock-names = 1437 clock-names = "se";
1509 clocks = <&gc 1438 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1439 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1440 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1441 dma-names = "tx", "rx";
1513 pinctrl-names 1442 pinctrl-names = "default";
1514 pinctrl-0 = < 1443 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1444 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1445 spi-max-frequency = <50000000>;
1517 #address-cell 1446 #address-cells = <1>;
1518 #size-cells = 1447 #size-cells = <0>;
1519 status = "dis 1448 status = "disabled";
1520 }; 1449 };
1521 }; 1450 };
1522 1451
1523 gpi_dma2: dma-controller@c000 1452 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm !! 1453 compatible = "qcom,sm8150-gpi-dma";
1525 reg = <0 0x00c00000 0 !! 1454 reg = <0 0xc00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1455 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1456 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1457 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1458 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1459 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1460 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1461 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1462 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1463 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1464 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1465 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1466 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1467 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1468 dma-channels = <13>;
1540 dma-channel-mask = <0 1469 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1470 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1471 #dma-cells = <3>;
1543 status = "disabled"; 1472 status = "disabled";
1544 }; 1473 };
1545 1474
1546 qupv3_id_2: geniqup@cc0000 { 1475 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1476 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1477 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1478
1550 clock-names = "m-ahb" 1479 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1480 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1481 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1482 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1483 #address-cells = <2>;
1555 #size-cells = <2>; 1484 #size-cells = <2>;
1556 ranges; 1485 ranges;
1557 status = "disabled"; 1486 status = "disabled";
1558 1487
1559 i2c17: i2c@c80000 { 1488 i2c17: i2c@c80000 {
1560 compatible = 1489 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1490 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1491 clock-names = "se";
1563 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1493 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1494 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1495 dma-names = "tx", "rx";
1567 pinctrl-names 1496 pinctrl-names = "default";
1568 pinctrl-0 = < 1497 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1498 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1499 #address-cells = <1>;
1571 #size-cells = 1500 #size-cells = <0>;
1572 status = "dis 1501 status = "disabled";
1573 }; 1502 };
1574 1503
1575 spi17: spi@c80000 { 1504 spi17: spi@c80000 {
1576 compatible = 1505 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 !! 1506 reg = <0 0xc80000 0 0x4000>;
1578 reg-names = " 1507 reg-names = "se";
1579 clock-names = 1508 clock-names = "se";
1580 clocks = <&gc 1509 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1510 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1511 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1512 dma-names = "tx", "rx";
1584 pinctrl-names 1513 pinctrl-names = "default";
1585 pinctrl-0 = < 1514 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1515 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1516 spi-max-frequency = <50000000>;
1588 #address-cell 1517 #address-cells = <1>;
1589 #size-cells = 1518 #size-cells = <0>;
1590 status = "dis 1519 status = "disabled";
1591 }; 1520 };
1592 1521
1593 i2c18: i2c@c84000 { 1522 i2c18: i2c@c84000 {
1594 compatible = 1523 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1524 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1525 clock-names = "se";
1597 clocks = <&gc 1526 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1527 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1528 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1529 dma-names = "tx", "rx";
1601 pinctrl-names 1530 pinctrl-names = "default";
1602 pinctrl-0 = < 1531 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1532 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1533 #address-cells = <1>;
1605 #size-cells = 1534 #size-cells = <0>;
1606 status = "dis 1535 status = "disabled";
1607 }; 1536 };
1608 1537
1609 spi18: spi@c84000 { 1538 spi18: spi@c84000 {
1610 compatible = 1539 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 !! 1540 reg = <0 0xc84000 0 0x4000>;
1612 reg-names = " 1541 reg-names = "se";
1613 clock-names = 1542 clock-names = "se";
1614 clocks = <&gc 1543 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1544 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1545 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1546 dma-names = "tx", "rx";
1618 pinctrl-names 1547 pinctrl-names = "default";
1619 pinctrl-0 = < 1548 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1549 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1550 spi-max-frequency = <50000000>;
1622 #address-cell 1551 #address-cells = <1>;
1623 #size-cells = 1552 #size-cells = <0>;
1624 status = "dis 1553 status = "disabled";
1625 }; 1554 };
1626 1555
1627 i2c19: i2c@c88000 { 1556 i2c19: i2c@c88000 {
1628 compatible = 1557 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1558 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1559 clock-names = "se";
1631 clocks = <&gc 1560 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1561 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1562 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1563 dma-names = "tx", "rx";
1635 pinctrl-names 1564 pinctrl-names = "default";
1636 pinctrl-0 = < 1565 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1566 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1567 #address-cells = <1>;
1639 #size-cells = 1568 #size-cells = <0>;
1640 status = "dis 1569 status = "disabled";
1641 }; 1570 };
1642 1571
1643 spi19: spi@c88000 { 1572 spi19: spi@c88000 {
1644 compatible = 1573 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 !! 1574 reg = <0 0xc88000 0 0x4000>;
1646 reg-names = " 1575 reg-names = "se";
1647 clock-names = 1576 clock-names = "se";
1648 clocks = <&gc 1577 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1578 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1579 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1580 dma-names = "tx", "rx";
1652 pinctrl-names 1581 pinctrl-names = "default";
1653 pinctrl-0 = < 1582 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1583 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1584 spi-max-frequency = <50000000>;
1656 #address-cell 1585 #address-cells = <1>;
1657 #size-cells = 1586 #size-cells = <0>;
1658 status = "dis 1587 status = "disabled";
1659 }; 1588 };
1660 1589
1661 i2c13: i2c@c8c000 { 1590 i2c13: i2c@c8c000 {
1662 compatible = 1591 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1592 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1593 clock-names = "se";
1665 clocks = <&gc 1594 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1595 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1596 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1597 dma-names = "tx", "rx";
1669 pinctrl-names 1598 pinctrl-names = "default";
1670 pinctrl-0 = < 1599 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1600 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1601 #address-cells = <1>;
1673 #size-cells = 1602 #size-cells = <0>;
1674 status = "dis 1603 status = "disabled";
1675 }; 1604 };
1676 1605
1677 spi13: spi@c8c000 { 1606 spi13: spi@c8c000 {
1678 compatible = 1607 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 !! 1608 reg = <0 0xc8c000 0 0x4000>;
1680 reg-names = " 1609 reg-names = "se";
1681 clock-names = 1610 clock-names = "se";
1682 clocks = <&gc 1611 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1612 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1613 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1614 dma-names = "tx", "rx";
1686 pinctrl-names 1615 pinctrl-names = "default";
1687 pinctrl-0 = < 1616 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1617 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1618 spi-max-frequency = <50000000>;
1690 #address-cell 1619 #address-cells = <1>;
1691 #size-cells = 1620 #size-cells = <0>;
1692 status = "dis 1621 status = "disabled";
1693 }; 1622 };
1694 1623
1695 i2c14: i2c@c90000 { 1624 i2c14: i2c@c90000 {
1696 compatible = 1625 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1626 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1627 clock-names = "se";
1699 clocks = <&gc 1628 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1629 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1630 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1631 dma-names = "tx", "rx";
1703 pinctrl-names 1632 pinctrl-names = "default";
1704 pinctrl-0 = < 1633 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1634 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1635 #address-cells = <1>;
1707 #size-cells = 1636 #size-cells = <0>;
1708 status = "dis 1637 status = "disabled";
1709 }; 1638 };
1710 1639
1711 spi14: spi@c90000 { 1640 spi14: spi@c90000 {
1712 compatible = 1641 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 !! 1642 reg = <0 0xc90000 0 0x4000>;
1714 reg-names = " 1643 reg-names = "se";
1715 clock-names = 1644 clock-names = "se";
1716 clocks = <&gc 1645 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1646 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1647 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1648 dma-names = "tx", "rx";
1720 pinctrl-names 1649 pinctrl-names = "default";
1721 pinctrl-0 = < 1650 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1651 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1652 spi-max-frequency = <50000000>;
1724 #address-cell 1653 #address-cells = <1>;
1725 #size-cells = 1654 #size-cells = <0>;
1726 status = "dis 1655 status = "disabled";
1727 }; 1656 };
1728 1657
1729 i2c15: i2c@c94000 { 1658 i2c15: i2c@c94000 {
1730 compatible = 1659 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1660 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1661 clock-names = "se";
1733 clocks = <&gc 1662 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1663 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1664 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1665 dma-names = "tx", "rx";
1737 pinctrl-names 1666 pinctrl-names = "default";
1738 pinctrl-0 = < 1667 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1668 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1669 #address-cells = <1>;
1741 #size-cells = 1670 #size-cells = <0>;
1742 status = "dis 1671 status = "disabled";
1743 }; 1672 };
1744 1673
1745 spi15: spi@c94000 { 1674 spi15: spi@c94000 {
1746 compatible = 1675 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 !! 1676 reg = <0 0xc94000 0 0x4000>;
1748 reg-names = " 1677 reg-names = "se";
1749 clock-names = 1678 clock-names = "se";
1750 clocks = <&gc 1679 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1680 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1681 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1682 dma-names = "tx", "rx";
1754 pinctrl-names 1683 pinctrl-names = "default";
1755 pinctrl-0 = < 1684 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1685 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1686 spi-max-frequency = <50000000>;
1758 #address-cell 1687 #address-cells = <1>;
1759 #size-cells = 1688 #size-cells = <0>;
1760 status = "dis 1689 status = "disabled";
1761 }; 1690 };
1762 }; 1691 };
1763 1692
1764 config_noc: interconnect@1500 1693 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1694 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1695 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1696 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1697 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1698 };
1770 1699
1771 system_noc: interconnect@1620 1700 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1701 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1702 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1703 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1704 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1705 };
1777 1706
1778 mc_virt: interconnect@163a000 1707 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1708 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1709 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1710 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1711 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1712 };
1784 1713
1785 aggre1_noc: interconnect@16e0 1714 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1715 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1716 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1717 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1718 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1719 };
1791 1720
1792 aggre2_noc: interconnect@1700 1721 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1722 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1723 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1724 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1725 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1726 };
1798 1727
1799 compute_noc: interconnect@172 1728 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1729 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1730 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1731 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1732 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1733 };
1805 1734
1806 mmss_noc: interconnect@174000 1735 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1736 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1737 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1738 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1739 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1740 };
1812 1741
1813 system-cache-controller@92000 1742 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1743 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 1744 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 1745 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 1746 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1747 };
1822 1748
1823 dma@10a2000 { <<
1824 compatible = "qcom,sm <<
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 <<
1832 <0 0x60000000 0 <<
1833 <0 0x60000f20 0 <<
1834 <0 0x60001000 0 <<
1835 <0 0x60100000 0 <<
1836 reg-names = "parf", " <<
1837 device_type = "pci"; <<
1838 linux,pci-domain = <0 <<
1839 bus-range = <0x00 0xf <<
1840 num-lanes = <1>; <<
1841 <<
1842 #address-cells = <3>; <<
1843 #size-cells = <2>; <<
1844 <<
1845 ranges = <0x01000000 <<
1846 <0x02000000 <<
1847 <<
1848 interrupts = <GIC_SPI <<
1849 <GIC_SPI <<
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 <<
1865 interrupt-map-mask = <<
1866 interrupt-map = <0 0 <<
1867 <0 0 <<
1868 <0 0 <<
1869 <0 0 <<
1870 <<
1871 clocks = <&gcc GCC_PC <<
1872 <&gcc GCC_PC <<
1873 <&gcc GCC_PC <<
1874 <&gcc GCC_PC <<
1875 <&gcc GCC_PC <<
1876 <&gcc GCC_PC <<
1877 <&gcc GCC_AG <<
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", <<
1880 "aux", <<
1881 "cfg", <<
1882 "bus_ma <<
1883 "bus_sl <<
1884 "slave_ <<
1885 "tbu", <<
1886 "ref"; <<
1887 <<
1888 iommu-map = <0x0 &a <<
1889 <0x100 &a <<
1890 <<
1891 resets = <&gcc GCC_PC <<
1892 reset-names = "pci"; <<
1893 <<
1894 power-domains = <&gcc <<
1895 <<
1896 phys = <&pcie0_phy>; <<
1897 phy-names = "pciephy" <<
1898 <<
1899 perst-gpios = <&tlmm <<
1900 wake-gpios = <&tlmm 3 <<
1901 <<
1902 pinctrl-names = "defa <<
1903 pinctrl-0 = <&pcie0_d <<
1904 <<
1905 status = "disabled"; <<
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; <<
1917 <<
1918 pcie0_phy: phy@1c06000 { <<
1919 compatible = "qcom,sm <<
1920 reg = <0 0x01c06000 0 <<
1921 clocks = <&gcc GCC_PC <<
1922 <&gcc GCC_PC <<
1923 <&gcc GCC_PC <<
1924 <&gcc GCC_PC <<
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 <<
1937 resets = <&gcc GCC_PC <<
1938 reset-names = "phy"; <<
1939 <<
1940 assigned-clocks = <&g <<
1941 assigned-clock-rates <<
1942 <<
1943 status = "disabled"; <<
1944 }; <<
1945 <<
1946 pcie1: pcie@1c08000 { <<
1947 compatible = "qcom,pc <<
1948 reg = <0 0x01c08000 0 <<
1949 <0 0x40000000 0 <<
1950 <0 0x40000f20 0 <<
1951 <0 0x40001000 0 <<
1952 <0 0x40100000 0 <<
1953 reg-names = "parf", " <<
1954 device_type = "pci"; <<
1955 linux,pci-domain = <1 <<
1956 bus-range = <0x00 0xf <<
1957 num-lanes = <2>; <<
1958 <<
1959 #address-cells = <3>; <<
1960 #size-cells = <2>; <<
1961 <<
1962 ranges = <0x01000000 <<
1963 <0x02000000 <<
1964 <<
1965 interrupts = <GIC_SPI <<
1966 <GIC_SPI <<
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 <<
1982 interrupt-map-mask = <<
1983 interrupt-map = <0 0 <<
1984 <0 0 <<
1985 <0 0 <<
1986 <0 0 <<
1987 <<
1988 clocks = <&gcc GCC_PC <<
1989 <&gcc GCC_PC <<
1990 <&gcc GCC_PC <<
1991 <&gcc GCC_PC <<
1992 <&gcc GCC_PC <<
1993 <&gcc GCC_PC <<
1994 <&gcc GCC_AG <<
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", <<
1997 "aux", <<
1998 "cfg", <<
1999 "bus_ma <<
2000 "bus_sl <<
2001 "slave_ <<
2002 "tbu", <<
2003 "ref"; <<
2004 <<
2005 assigned-clocks = <&g <<
2006 assigned-clock-rates <<
2007 <<
2008 iommu-map = <0x0 &a <<
2009 <0x100 &a <<
2010 <<
2011 resets = <&gcc GCC_PC <<
2012 reset-names = "pci"; <<
2013 <<
2014 power-domains = <&gcc <<
2015 <<
2016 phys = <&pcie1_phy>; <<
2017 phy-names = "pciephy" <<
2018 <<
2019 perst-gpios = <&tlmm <<
2020 enable-gpio = <&tlmm <<
2021 <<
2022 pinctrl-names = "defa <<
2023 pinctrl-0 = <&pcie1_d <<
2024 <<
2025 status = "disabled"; <<
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; <<
2037 <<
2038 pcie1_phy: phy@1c0e000 { <<
2039 compatible = "qcom,sm <<
2040 reg = <0 0x01c0e000 0 <<
2041 clocks = <&gcc GCC_PC <<
2042 <&gcc GCC_PC <<
2043 <&gcc GCC_PC <<
2044 <&gcc GCC_PC <<
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 <<
2057 resets = <&gcc GCC_PC <<
2058 reset-names = "phy"; <<
2059 <<
2060 assigned-clocks = <&g <<
2061 assigned-clock-rates <<
2062 <<
2063 status = "disabled"; <<
2064 }; <<
2065 <<
2066 ufs_mem_hc: ufshc@1d84000 { 1749 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 1750 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 1751 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 1752 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 1753 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 1754 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 1755 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 1756 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 1757 phy-names = "ufsphy";
2075 lanes-per-direction = 1758 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 1759 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 1760 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 1761 reset-names = "rst";
2079 1762
2080 iommus = <&apps_smmu 1763 iommus = <&apps_smmu 0x300 0>;
2081 1764
2082 clock-names = 1765 clock-names =
2083 "core_clk", 1766 "core_clk",
2084 "bus_aggr_clk 1767 "bus_aggr_clk",
2085 "iface_clk", 1768 "iface_clk",
2086 "core_clk_uni 1769 "core_clk_unipro",
2087 "ref_clk", 1770 "ref_clk",
2088 "tx_lane0_syn 1771 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 1772 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 1773 "rx_lane1_sync_clk",
2091 "ice_core_clk 1774 "ice_core_clk";
2092 clocks = 1775 clocks =
2093 <&gcc GCC_UFS 1776 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 1777 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 1778 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 1779 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 1780 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 1781 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 1782 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 1783 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 1784 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 1785 freq-table-hz =
2103 <37500000 300 1786 <37500000 300000000>,
2104 <0 0>, 1787 <0 0>,
2105 <0 0>, 1788 <0 0>,
2106 <37500000 300 1789 <37500000 300000000>,
2107 <0 0>, 1790 <0 0>,
2108 <0 0>, 1791 <0 0>,
2109 <0 0>, 1792 <0 0>,
2110 <0 0>, 1793 <0 0>,
2111 <0 300000000> 1794 <0 300000000>;
2112 1795
2113 status = "disabled"; 1796 status = "disabled";
2114 }; 1797 };
2115 1798
2116 ufs_mem_phy: phy@1d87000 { 1799 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 1800 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 1801 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 1802 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 1803 #size-cells = <2>;
2121 <&gcc GCC_UF !! 1804 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 1805 clock-names = "ref",
2124 "ref_au !! 1806 "ref_aux";
2125 "qref"; !! 1807 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
2126 !! 1808 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2127 power-domains = <&gcc <<
2128 1809
2129 resets = <&ufs_mem_hc 1810 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 1811 reset-names = "ufsphy";
>> 1812 status = "disabled";
2131 1813
2132 #phy-cells = <0>; !! 1814 ufs_mem_phy_lanes: phy@1d87400 {
>> 1815 reg = <0 0x01d87400 0 0x108>,
>> 1816 <0 0x01d87600 0 0x1e0>,
>> 1817 <0 0x01d87c00 0 0x1dc>,
>> 1818 <0 0x01d87800 0 0x108>,
>> 1819 <0 0x01d87a00 0 0x1e0>;
>> 1820 #phy-cells = <0>;
>> 1821 };
>> 1822 };
2133 1823
2134 status = "disabled"; !! 1824 ipa_virt: interconnect@1e00000 {
>> 1825 compatible = "qcom,sm8150-ipa-virt";
>> 1826 reg = <0 0x01e00000 0 0x1000>;
>> 1827 #interconnect-cells = <1>;
>> 1828 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 1829 };
2136 1830
2137 cryptobam: dma-controller@1dc !! 1831 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 1832 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 1833 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 1834 };
2177 1835
2178 remoteproc_slpi: remoteproc@2 1836 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 1837 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 1838 reg = <0x0 0x02400000 0x0 0x4040>;
2181 1839
2182 interrupts-extended = 1840 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 1841 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 1842 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 1843 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 1844 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 1845 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 1846 "handover", "stop-ack";
2189 1847
2190 clocks = <&rpmhcc RPM 1848 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 1849 clock-names = "xo";
2192 1850
2193 power-domains = <&rpm !! 1851 power-domains = <&rpmhpd 3>,
2194 <&rpm !! 1852 <&rpmhpd 2>;
2195 power-domain-names = 1853 power-domain-names = "lcx", "lmx";
2196 1854
2197 memory-region = <&slp 1855 memory-region = <&slpi_mem>;
2198 1856
2199 qcom,qmp = <&aoss_qmp 1857 qcom,qmp = <&aoss_qmp>;
2200 1858
2201 qcom,smem-states = <& 1859 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 1860 qcom,smem-state-names = "stop";
2203 1861
2204 status = "disabled"; 1862 status = "disabled";
2205 1863
2206 glink-edge { 1864 glink-edge {
2207 interrupts = 1865 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 1866 label = "dsps";
2209 qcom,remote-p 1867 qcom,remote-pid = <3>;
2210 mboxes = <&ap 1868 mboxes = <&apss_shared 24>;
2211 1869
2212 fastrpc { 1870 fastrpc {
2213 compa 1871 compatible = "qcom,fastrpc";
2214 qcom, 1872 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 1873 label = "sdsp";
2216 qcom, 1874 qcom,non-secure-domain;
2217 #addr 1875 #address-cells = <1>;
2218 #size 1876 #size-cells = <0>;
2219 1877
2220 compu 1878 compute-cb@1 {
2221 1879 compatible = "qcom,fastrpc-compute-cb";
2222 1880 reg = <1>;
2223 1881 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 1882 };
2225 1883
2226 compu 1884 compute-cb@2 {
2227 1885 compatible = "qcom,fastrpc-compute-cb";
2228 1886 reg = <2>;
2229 1887 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 1888 };
2231 1889
2232 compu 1890 compute-cb@3 {
2233 1891 compatible = "qcom,fastrpc-compute-cb";
2234 1892 reg = <3>;
2235 1893 iommus = <&apps_smmu 0x05a3 0x0>;
2236 1894 /* note: shared-cb = <4> in downstream */
2237 }; 1895 };
2238 }; 1896 };
2239 }; 1897 };
2240 }; 1898 };
2241 1899
2242 gpu: gpu@2c00000 { 1900 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 1901 /*
>> 1902 * note: the amd,imageon compatible makes it possible
>> 1903 * to use the drm/msm driver without the display node,
>> 1904 * make sure to remove it when display node is added
>> 1905 */
>> 1906 compatible = "qcom,adreno-640.1",
>> 1907 "qcom,adreno",
>> 1908 "amd,imageon";
>> 1909
2244 reg = <0 0x02c00000 0 1910 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 1911 reg-names = "kgsl_3d0_reg_memory";
2246 1912
2247 interrupts = <GIC_SPI 1913 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 1914
2249 iommus = <&adreno_smm 1915 iommus = <&adreno_smmu 0 0x401>;
2250 1916
2251 operating-points-v2 = 1917 operating-points-v2 = <&gpu_opp_table>;
2252 1918
2253 qcom,gmu = <&gmu>; 1919 qcom,gmu = <&gmu>;
2254 1920
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 1921 status = "disabled";
2260 1922
2261 zap-shader { 1923 zap-shader {
2262 memory-region 1924 memory-region = <&gpu_mem>;
2263 }; 1925 };
2264 1926
>> 1927 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 1928 gpu_opp_table: opp-table {
2266 compatible = 1929 compatible = "operating-points-v2";
2267 1930
2268 opp-675000000 1931 opp-675000000 {
2269 opp-h 1932 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 1933 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 1934 };
2273 1935
2274 opp-585000000 1936 opp-585000000 {
2275 opp-h 1937 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 1938 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 1939 };
2279 1940
2280 opp-499200000 1941 opp-499200000 {
2281 opp-h 1942 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 1943 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 1944 };
2285 1945
2286 opp-427000000 1946 opp-427000000 {
2287 opp-h 1947 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 1948 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 1949 };
2291 1950
2292 opp-345000000 1951 opp-345000000 {
2293 opp-h 1952 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 1953 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 1954 };
2297 1955
2298 opp-257000000 1956 opp-257000000 {
2299 opp-h 1957 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 1958 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 1959 };
2303 }; 1960 };
2304 }; 1961 };
2305 1962
2306 gmu: gmu@2c6a000 { 1963 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 1964 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 1965
2309 reg = <0 0x02c6a000 0 1966 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 1967 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 1968 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 1969 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 1970
2314 interrupts = <GIC_SPI 1971 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 1972 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 1973 interrupt-names = "hfi", "gmu";
2317 1974
2318 clocks = <&gpucc GPU_ 1975 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 1976 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 1977 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 1978 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 1979 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 1980 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 1981
2325 power-domains = <&gpu 1982 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 1983 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 1984 power-domain-names = "cx", "gx";
2328 1985
2329 iommus = <&adreno_smm 1986 iommus = <&adreno_smmu 5 0x400>;
2330 1987
2331 operating-points-v2 = 1988 operating-points-v2 = <&gmu_opp_table>;
2332 1989
2333 status = "disabled"; 1990 status = "disabled";
2334 1991
2335 gmu_opp_table: opp-ta 1992 gmu_opp_table: opp-table {
2336 compatible = 1993 compatible = "operating-points-v2";
2337 1994
2338 opp-200000000 1995 opp-200000000 {
2339 opp-h 1996 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 1997 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 1998 };
2342 }; 1999 };
2343 }; 2000 };
2344 2001
2345 gpucc: clock-controller@2c900 2002 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2003 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2004 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2005 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2006 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2007 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2008 clock-names = "bi_tcxo",
2352 "gcc_gp 2009 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2010 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2011 #clock-cells = <1>;
2355 #reset-cells = <1>; 2012 #reset-cells = <1>;
2356 #power-domain-cells = 2013 #power-domain-cells = <1>;
2357 }; 2014 };
2358 2015
2359 adreno_smmu: iommu@2ca0000 { 2016 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 2017 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 2018 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2019 #iommu-cells = <2>;
2364 #global-interrupts = 2020 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2021 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2022 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2023 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2024 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2025 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2026 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2027 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2028 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2029 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2030 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2031 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2032 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2033 clock-names = "ahb", "bus", "iface";
2378 2034
2379 power-domains = <&gpu 2035 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2036 };
2381 2037
2382 tlmm: pinctrl@3100000 { 2038 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2039 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2040 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2041 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2042 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2043 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2044 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2045 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2046 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2047 gpio-controller;
2392 #gpio-cells = <2>; 2048 #gpio-cells = <2>;
2393 interrupt-controller; 2049 interrupt-controller;
2394 #interrupt-cells = <2 2050 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc <<
2396 2051
2397 qup_i2c0_default: qup !! 2052 qup_i2c0_default: qup-i2c0-default {
2398 pins = "gpio0 !! 2053 mux {
2399 function = "q !! 2054 pins = "gpio0", "gpio1";
2400 drive-strengt !! 2055 function = "qup0";
2401 bias-disable; !! 2056 };
>> 2057
>> 2058 config {
>> 2059 pins = "gpio0", "gpio1";
>> 2060 drive-strength = <0x02>;
>> 2061 bias-disable;
>> 2062 };
2402 }; 2063 };
2403 2064
2404 qup_spi0_default: qup !! 2065 qup_spi0_default: qup-spi0-default {
2405 pins = "gpio0 2066 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2067 function = "qup0";
2407 drive-strengt 2068 drive-strength = <6>;
2408 bias-disable; 2069 bias-disable;
2409 }; 2070 };
2410 2071
2411 qup_i2c1_default: qup !! 2072 qup_i2c1_default: qup-i2c1-default {
2412 pins = "gpio1 !! 2073 mux {
2413 function = "q !! 2074 pins = "gpio114", "gpio115";
2414 drive-strengt !! 2075 function = "qup1";
2415 bias-disable; !! 2076 };
>> 2077
>> 2078 config {
>> 2079 pins = "gpio114", "gpio115";
>> 2080 drive-strength = <0x02>;
>> 2081 bias-disable;
>> 2082 };
2416 }; 2083 };
2417 2084
2418 qup_spi1_default: qup !! 2085 qup_spi1_default: qup-spi1-default {
2419 pins = "gpio1 2086 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2087 function = "qup1";
2421 drive-strengt 2088 drive-strength = <6>;
2422 bias-disable; 2089 bias-disable;
2423 }; 2090 };
2424 2091
2425 qup_i2c2_default: qup !! 2092 qup_i2c2_default: qup-i2c2-default {
2426 pins = "gpio1 !! 2093 mux {
2427 function = "q !! 2094 pins = "gpio126", "gpio127";
2428 drive-strengt !! 2095 function = "qup2";
2429 bias-disable; !! 2096 };
>> 2097
>> 2098 config {
>> 2099 pins = "gpio126", "gpio127";
>> 2100 drive-strength = <0x02>;
>> 2101 bias-disable;
>> 2102 };
2430 }; 2103 };
2431 2104
2432 qup_spi2_default: qup !! 2105 qup_spi2_default: qup-spi2-default {
2433 pins = "gpio1 2106 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2107 function = "qup2";
2435 drive-strengt 2108 drive-strength = <6>;
2436 bias-disable; 2109 bias-disable;
2437 }; 2110 };
2438 2111
2439 qup_i2c3_default: qup !! 2112 qup_i2c3_default: qup-i2c3-default {
2440 pins = "gpio1 !! 2113 mux {
2441 function = "q !! 2114 pins = "gpio144", "gpio145";
2442 drive-strengt !! 2115 function = "qup3";
2443 bias-disable; !! 2116 };
>> 2117
>> 2118 config {
>> 2119 pins = "gpio144", "gpio145";
>> 2120 drive-strength = <0x02>;
>> 2121 bias-disable;
>> 2122 };
2444 }; 2123 };
2445 2124
2446 qup_spi3_default: qup !! 2125 qup_spi3_default: qup-spi3-default {
2447 pins = "gpio1 2126 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2127 function = "qup3";
2449 drive-strengt 2128 drive-strength = <6>;
2450 bias-disable; 2129 bias-disable;
2451 }; 2130 };
2452 2131
2453 qup_i2c4_default: qup !! 2132 qup_i2c4_default: qup-i2c4-default {
2454 pins = "gpio5 !! 2133 mux {
2455 function = "q !! 2134 pins = "gpio51", "gpio52";
2456 drive-strengt !! 2135 function = "qup4";
2457 bias-disable; !! 2136 };
>> 2137
>> 2138 config {
>> 2139 pins = "gpio51", "gpio52";
>> 2140 drive-strength = <0x02>;
>> 2141 bias-disable;
>> 2142 };
2458 }; 2143 };
2459 2144
2460 qup_spi4_default: qup !! 2145 qup_spi4_default: qup-spi4-default {
2461 pins = "gpio5 2146 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2147 function = "qup4";
2463 drive-strengt 2148 drive-strength = <6>;
2464 bias-disable; 2149 bias-disable;
2465 }; 2150 };
2466 2151
2467 qup_i2c5_default: qup !! 2152 qup_i2c5_default: qup-i2c5-default {
2468 pins = "gpio1 !! 2153 mux {
2469 function = "q !! 2154 pins = "gpio121", "gpio122";
2470 drive-strengt !! 2155 function = "qup5";
2471 bias-disable; !! 2156 };
>> 2157
>> 2158 config {
>> 2159 pins = "gpio121", "gpio122";
>> 2160 drive-strength = <0x02>;
>> 2161 bias-disable;
>> 2162 };
2472 }; 2163 };
2473 2164
2474 qup_spi5_default: qup !! 2165 qup_spi5_default: qup-spi5-default {
2475 pins = "gpio1 2166 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2167 function = "qup5";
2477 drive-strengt 2168 drive-strength = <6>;
2478 bias-disable; 2169 bias-disable;
2479 }; 2170 };
2480 2171
2481 qup_i2c6_default: qup !! 2172 qup_i2c6_default: qup-i2c6-default {
2482 pins = "gpio6 !! 2173 mux {
2483 function = "q !! 2174 pins = "gpio6", "gpio7";
2484 drive-strengt !! 2175 function = "qup6";
2485 bias-disable; !! 2176 };
>> 2177
>> 2178 config {
>> 2179 pins = "gpio6", "gpio7";
>> 2180 drive-strength = <0x02>;
>> 2181 bias-disable;
>> 2182 };
2486 }; 2183 };
2487 2184
2488 qup_spi6_default: qup !! 2185 qup_spi6_default: qup-spi6_default {
2489 pins = "gpio4 2186 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2187 function = "qup6";
2491 drive-strengt 2188 drive-strength = <6>;
2492 bias-disable; 2189 bias-disable;
2493 }; 2190 };
2494 2191
2495 qup_i2c7_default: qup !! 2192 qup_i2c7_default: qup-i2c7-default {
2496 pins = "gpio9 !! 2193 mux {
2497 function = "q !! 2194 pins = "gpio98", "gpio99";
2498 drive-strengt !! 2195 function = "qup7";
2499 bias-disable; !! 2196 };
>> 2197
>> 2198 config {
>> 2199 pins = "gpio98", "gpio99";
>> 2200 drive-strength = <0x02>;
>> 2201 bias-disable;
>> 2202 };
2500 }; 2203 };
2501 2204
2502 qup_spi7_default: qup !! 2205 qup_spi7_default: qup-spi7_default {
2503 pins = "gpio9 2206 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2207 function = "qup7";
2505 drive-strengt 2208 drive-strength = <6>;
2506 bias-disable; 2209 bias-disable;
2507 }; 2210 };
2508 2211
2509 qup_i2c8_default: qup !! 2212 qup_i2c8_default: qup-i2c8-default {
2510 pins = "gpio8 !! 2213 mux {
2511 function = "q !! 2214 pins = "gpio88", "gpio89";
2512 drive-strengt !! 2215 function = "qup8";
2513 bias-disable; !! 2216 };
>> 2217
>> 2218 config {
>> 2219 pins = "gpio88", "gpio89";
>> 2220 drive-strength = <0x02>;
>> 2221 bias-disable;
>> 2222 };
2514 }; 2223 };
2515 2224
2516 qup_spi8_default: qup !! 2225 qup_spi8_default: qup-spi8-default {
2517 pins = "gpio8 2226 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2227 function = "qup8";
2519 drive-strengt 2228 drive-strength = <6>;
2520 bias-disable; 2229 bias-disable;
2521 }; 2230 };
2522 2231
2523 qup_i2c9_default: qup !! 2232 qup_i2c9_default: qup-i2c9-default {
2524 pins = "gpio3 !! 2233 mux {
2525 function = "q !! 2234 pins = "gpio39", "gpio40";
2526 drive-strengt !! 2235 function = "qup9";
2527 bias-disable; !! 2236 };
>> 2237
>> 2238 config {
>> 2239 pins = "gpio39", "gpio40";
>> 2240 drive-strength = <0x02>;
>> 2241 bias-disable;
>> 2242 };
2528 }; 2243 };
2529 2244
2530 qup_spi9_default: qup !! 2245 qup_spi9_default: qup-spi9-default {
2531 pins = "gpio3 2246 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2247 function = "qup9";
2533 drive-strengt 2248 drive-strength = <6>;
2534 bias-disable; 2249 bias-disable;
2535 }; 2250 };
2536 2251
2537 qup_uart9_default: qu !! 2252 qup_i2c10_default: qup-i2c10-default {
2538 pins = "gpio4 !! 2253 mux {
2539 function = "q !! 2254 pins = "gpio9", "gpio10";
2540 drive-strengt !! 2255 function = "qup10";
2541 bias-disable; !! 2256 };
2542 }; <<
2543 2257
2544 qup_i2c10_default: qu !! 2258 config {
2545 pins = "gpio9 !! 2259 pins = "gpio9", "gpio10";
2546 function = "q !! 2260 drive-strength = <0x02>;
2547 drive-strengt !! 2261 bias-disable;
2548 bias-disable; !! 2262 };
2549 }; 2263 };
2550 2264
2551 qup_spi10_default: qu !! 2265 qup_spi10_default: qup-spi10-default {
2552 pins = "gpio9 2266 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2267 function = "qup10";
2554 drive-strengt 2268 drive-strength = <6>;
2555 bias-disable; 2269 bias-disable;
2556 }; 2270 };
2557 2271
2558 qup_i2c11_default: qu !! 2272 qup_i2c11_default: qup-i2c11-default {
2559 pins = "gpio9 !! 2273 mux {
2560 function = "q !! 2274 pins = "gpio94", "gpio95";
2561 drive-strengt !! 2275 function = "qup11";
2562 bias-disable; !! 2276 };
>> 2277
>> 2278 config {
>> 2279 pins = "gpio94", "gpio95";
>> 2280 drive-strength = <0x02>;
>> 2281 bias-disable;
>> 2282 };
2563 }; 2283 };
2564 2284
2565 qup_spi11_default: qu !! 2285 qup_spi11_default: qup-spi11-default {
2566 pins = "gpio9 2286 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2287 function = "qup11";
2568 drive-strengt 2288 drive-strength = <6>;
2569 bias-disable; 2289 bias-disable;
2570 }; 2290 };
2571 2291
2572 qup_i2c12_default: qu !! 2292 qup_i2c12_default: qup-i2c12-default {
2573 pins = "gpio8 !! 2293 mux {
2574 function = "q !! 2294 pins = "gpio83", "gpio84";
2575 drive-strengt !! 2295 function = "qup12";
2576 bias-disable; !! 2296 };
>> 2297
>> 2298 config {
>> 2299 pins = "gpio83", "gpio84";
>> 2300 drive-strength = <0x02>;
>> 2301 bias-disable;
>> 2302 };
2577 }; 2303 };
2578 2304
2579 qup_spi12_default: qu !! 2305 qup_spi12_default: qup-spi12-default {
2580 pins = "gpio8 2306 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2307 function = "qup12";
2582 drive-strengt 2308 drive-strength = <6>;
2583 bias-disable; 2309 bias-disable;
2584 }; 2310 };
2585 2311
2586 qup_i2c13_default: qu !! 2312 qup_i2c13_default: qup-i2c13-default {
2587 pins = "gpio4 !! 2313 mux {
2588 function = "q !! 2314 pins = "gpio43", "gpio44";
2589 drive-strengt !! 2315 function = "qup13";
2590 bias-disable; !! 2316 };
>> 2317
>> 2318 config {
>> 2319 pins = "gpio43", "gpio44";
>> 2320 drive-strength = <0x02>;
>> 2321 bias-disable;
>> 2322 };
2591 }; 2323 };
2592 2324
2593 qup_spi13_default: qu !! 2325 qup_spi13_default: qup-spi13-default {
2594 pins = "gpio4 2326 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2327 function = "qup13";
2596 drive-strengt 2328 drive-strength = <6>;
2597 bias-disable; 2329 bias-disable;
2598 }; 2330 };
2599 2331
2600 qup_i2c14_default: qu !! 2332 qup_i2c14_default: qup-i2c14-default {
2601 pins = "gpio4 !! 2333 mux {
2602 function = "q !! 2334 pins = "gpio47", "gpio48";
2603 drive-strengt !! 2335 function = "qup14";
2604 bias-disable; !! 2336 };
>> 2337
>> 2338 config {
>> 2339 pins = "gpio47", "gpio48";
>> 2340 drive-strength = <0x02>;
>> 2341 bias-disable;
>> 2342 };
2605 }; 2343 };
2606 2344
2607 qup_spi14_default: qu !! 2345 qup_spi14_default: qup-spi14-default {
2608 pins = "gpio4 2346 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2347 function = "qup14";
2610 drive-strengt 2348 drive-strength = <6>;
2611 bias-disable; 2349 bias-disable;
2612 }; 2350 };
2613 2351
2614 qup_i2c15_default: qu !! 2352 qup_i2c15_default: qup-i2c15-default {
2615 pins = "gpio2 !! 2353 mux {
2616 function = "q !! 2354 pins = "gpio27", "gpio28";
2617 drive-strengt !! 2355 function = "qup15";
2618 bias-disable; !! 2356 };
>> 2357
>> 2358 config {
>> 2359 pins = "gpio27", "gpio28";
>> 2360 drive-strength = <0x02>;
>> 2361 bias-disable;
>> 2362 };
2619 }; 2363 };
2620 2364
2621 qup_spi15_default: qu !! 2365 qup_spi15_default: qup-spi15-default {
2622 pins = "gpio2 2366 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2367 function = "qup15";
2624 drive-strengt 2368 drive-strength = <6>;
2625 bias-disable; 2369 bias-disable;
2626 }; 2370 };
2627 2371
2628 qup_i2c16_default: qu !! 2372 qup_i2c16_default: qup-i2c16-default {
2629 pins = "gpio8 !! 2373 mux {
2630 function = "q !! 2374 pins = "gpio86", "gpio85";
2631 drive-strengt !! 2375 function = "qup16";
2632 bias-disable; !! 2376 };
>> 2377
>> 2378 config {
>> 2379 pins = "gpio86", "gpio85";
>> 2380 drive-strength = <0x02>;
>> 2381 bias-disable;
>> 2382 };
2633 }; 2383 };
2634 2384
2635 qup_spi16_default: qu !! 2385 qup_spi16_default: qup-spi16-default {
2636 pins = "gpio8 2386 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2387 function = "qup16";
2638 drive-strengt 2388 drive-strength = <6>;
2639 bias-disable; 2389 bias-disable;
2640 }; 2390 };
2641 2391
2642 qup_i2c17_default: qu !! 2392 qup_i2c17_default: qup-i2c17-default {
2643 pins = "gpio5 !! 2393 mux {
2644 function = "q !! 2394 pins = "gpio55", "gpio56";
2645 drive-strengt !! 2395 function = "qup17";
2646 bias-disable; !! 2396 };
>> 2397
>> 2398 config {
>> 2399 pins = "gpio55", "gpio56";
>> 2400 drive-strength = <0x02>;
>> 2401 bias-disable;
>> 2402 };
2647 }; 2403 };
2648 2404
2649 qup_spi17_default: qu !! 2405 qup_spi17_default: qup-spi17-default {
2650 pins = "gpio5 2406 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2407 function = "qup17";
2652 drive-strengt 2408 drive-strength = <6>;
2653 bias-disable; 2409 bias-disable;
2654 }; 2410 };
2655 2411
2656 qup_i2c18_default: qu !! 2412 qup_i2c18_default: qup-i2c18-default {
2657 pins = "gpio2 !! 2413 mux {
2658 function = "q !! 2414 pins = "gpio23", "gpio24";
2659 drive-strengt !! 2415 function = "qup18";
2660 bias-disable; !! 2416 };
>> 2417
>> 2418 config {
>> 2419 pins = "gpio23", "gpio24";
>> 2420 drive-strength = <0x02>;
>> 2421 bias-disable;
>> 2422 };
2661 }; 2423 };
2662 2424
2663 qup_spi18_default: qu !! 2425 qup_spi18_default: qup-spi18-default {
2664 pins = "gpio2 2426 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2427 function = "qup18";
2666 drive-strengt 2428 drive-strength = <6>;
2667 bias-disable; 2429 bias-disable;
2668 }; 2430 };
2669 2431
2670 qup_i2c19_default: qu !! 2432 qup_i2c19_default: qup-i2c19-default {
2671 pins = "gpio5 !! 2433 mux {
2672 function = "q !! 2434 pins = "gpio57", "gpio58";
2673 drive-strengt !! 2435 function = "qup19";
2674 bias-disable; !! 2436 };
>> 2437
>> 2438 config {
>> 2439 pins = "gpio57", "gpio58";
>> 2440 drive-strength = <0x02>;
>> 2441 bias-disable;
>> 2442 };
2675 }; 2443 };
2676 2444
2677 qup_spi19_default: qu !! 2445 qup_spi19_default: qup-spi19-default {
2678 pins = "gpio5 2446 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2447 function = "qup19";
2680 drive-strengt 2448 drive-strength = <6>;
2681 bias-disable; 2449 bias-disable;
2682 }; 2450 };
2683 <<
2684 pcie0_default_state: <<
2685 perst-pins { <<
2686 pins <<
2687 funct <<
2688 drive <<
2689 bias- <<
2690 }; <<
2691 <<
2692 clkreq-pins { <<
2693 pins <<
2694 funct <<
2695 drive <<
2696 bias- <<
2697 }; <<
2698 <<
2699 wake-pins { <<
2700 pins <<
2701 funct <<
2702 drive <<
2703 bias- <<
2704 }; <<
2705 }; <<
2706 <<
2707 pcie1_default_state: <<
2708 perst-pins { <<
2709 pins <<
2710 funct <<
2711 drive <<
2712 bias- <<
2713 }; <<
2714 <<
2715 clkreq-pins { <<
2716 pins <<
2717 funct <<
2718 drive <<
2719 bias- <<
2720 }; <<
2721 <<
2722 wake-pins { <<
2723 pins <<
2724 funct <<
2725 drive <<
2726 bias- <<
2727 }; <<
2728 }; <<
2729 }; 2451 };
2730 2452
2731 remoteproc_mpss: remoteproc@4 2453 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2454 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2455 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2456
2735 interrupts-extended = 2457 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2458 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2459 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2460 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2461 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2462 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2463 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2464 "stop-ack", "shutdown-ack";
2743 2465
2744 clocks = <&rpmhcc RPM 2466 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2467 clock-names = "xo";
2746 2468
2747 power-domains = <&rpm !! 2469 power-domains = <&rpmhpd 7>,
2748 <&rpm !! 2470 <&rpmhpd 0>;
2749 power-domain-names = 2471 power-domain-names = "cx", "mss";
2750 2472
2751 memory-region = <&mps 2473 memory-region = <&mpss_mem>;
2752 2474
2753 qcom,qmp = <&aoss_qmp 2475 qcom,qmp = <&aoss_qmp>;
2754 2476
2755 qcom,smem-states = <& 2477 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2478 qcom,smem-state-names = "stop";
2757 2479
2758 status = "disabled"; 2480 status = "disabled";
2759 2481
2760 glink-edge { 2482 glink-edge {
2761 interrupts = 2483 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2484 label = "modem";
2763 qcom,remote-p 2485 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2486 mboxes = <&apss_shared 12>;
2765 }; 2487 };
2766 }; 2488 };
2767 2489
2768 stm@6002000 { 2490 stm@6002000 {
2769 compatible = "arm,cor 2491 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2492 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2493 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2494 reg-names = "stm-base", "stm-stimulus-base";
2773 2495
2774 clocks = <&aoss_qmp>; 2496 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2497 clock-names = "apb_pclk";
2776 2498
2777 out-ports { 2499 out-ports {
2778 port { 2500 port {
2779 stm_o 2501 stm_out: endpoint {
2780 2502 remote-endpoint = <&funnel0_in7>;
2781 }; 2503 };
2782 }; 2504 };
2783 }; 2505 };
2784 }; 2506 };
2785 2507
2786 funnel@6041000 { 2508 funnel@6041000 {
2787 compatible = "arm,cor 2509 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2510 reg = <0 0x06041000 0 0x1000>;
2789 2511
2790 clocks = <&aoss_qmp>; 2512 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2513 clock-names = "apb_pclk";
2792 2514
2793 out-ports { 2515 out-ports {
2794 port { 2516 port {
2795 funne 2517 funnel0_out: endpoint {
2796 2518 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2519 };
2798 }; 2520 };
2799 }; 2521 };
2800 2522
2801 in-ports { 2523 in-ports {
2802 #address-cell 2524 #address-cells = <1>;
2803 #size-cells = 2525 #size-cells = <0>;
2804 2526
2805 port@7 { 2527 port@7 {
2806 reg = 2528 reg = <7>;
2807 funne 2529 funnel0_in7: endpoint {
2808 2530 remote-endpoint = <&stm_out>;
2809 }; 2531 };
2810 }; 2532 };
2811 }; 2533 };
2812 }; 2534 };
2813 2535
2814 funnel@6042000 { 2536 funnel@6042000 {
2815 compatible = "arm,cor 2537 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2538 reg = <0 0x06042000 0 0x1000>;
2817 2539
2818 clocks = <&aoss_qmp>; 2540 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2541 clock-names = "apb_pclk";
2820 2542
2821 out-ports { 2543 out-ports {
2822 port { 2544 port {
2823 funne 2545 funnel1_out: endpoint {
2824 2546 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2547 };
2826 }; 2548 };
2827 }; 2549 };
2828 2550
2829 in-ports { 2551 in-ports {
2830 #address-cell 2552 #address-cells = <1>;
2831 #size-cells = 2553 #size-cells = <0>;
2832 2554
2833 port@4 { 2555 port@4 {
2834 reg = 2556 reg = <4>;
2835 funne 2557 funnel1_in4: endpoint {
2836 2558 remote-endpoint = <&swao_replicator_out>;
2837 }; 2559 };
2838 }; 2560 };
2839 }; 2561 };
2840 }; 2562 };
2841 2563
2842 funnel@6043000 { 2564 funnel@6043000 {
2843 compatible = "arm,cor 2565 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2566 reg = <0 0x06043000 0 0x1000>;
2845 2567
2846 clocks = <&aoss_qmp>; 2568 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2569 clock-names = "apb_pclk";
2848 2570
2849 out-ports { 2571 out-ports {
2850 port { 2572 port {
2851 funne 2573 funnel2_out: endpoint {
2852 2574 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2575 };
2854 }; 2576 };
2855 }; 2577 };
2856 2578
2857 in-ports { 2579 in-ports {
2858 #address-cell 2580 #address-cells = <1>;
2859 #size-cells = 2581 #size-cells = <0>;
2860 2582
2861 port@2 { 2583 port@2 {
2862 reg = 2584 reg = <2>;
2863 funne 2585 funnel2_in2: endpoint {
2864 2586 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2587 };
2866 }; 2588 };
2867 }; 2589 };
2868 }; 2590 };
2869 2591
2870 funnel@6045000 { 2592 funnel@6045000 {
2871 compatible = "arm,cor 2593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2594 reg = <0 0x06045000 0 0x1000>;
2873 2595
2874 clocks = <&aoss_qmp>; 2596 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2597 clock-names = "apb_pclk";
2876 2598
2877 out-ports { 2599 out-ports {
2878 port { 2600 port {
2879 merge 2601 merge_funnel_out: endpoint {
2880 2602 remote-endpoint = <&etf_in>;
2881 }; 2603 };
2882 }; 2604 };
2883 }; 2605 };
2884 2606
2885 in-ports { 2607 in-ports {
2886 #address-cell 2608 #address-cells = <1>;
2887 #size-cells = 2609 #size-cells = <0>;
2888 2610
2889 port@0 { 2611 port@0 {
2890 reg = 2612 reg = <0>;
2891 merge 2613 merge_funnel_in0: endpoint {
2892 2614 remote-endpoint = <&funnel0_out>;
2893 }; 2615 };
2894 }; 2616 };
2895 2617
2896 port@1 { 2618 port@1 {
2897 reg = 2619 reg = <1>;
2898 merge 2620 merge_funnel_in1: endpoint {
2899 2621 remote-endpoint = <&funnel1_out>;
2900 }; 2622 };
2901 }; 2623 };
2902 2624
2903 port@2 { 2625 port@2 {
2904 reg = 2626 reg = <2>;
2905 merge 2627 merge_funnel_in2: endpoint {
2906 2628 remote-endpoint = <&funnel2_out>;
2907 }; 2629 };
2908 }; 2630 };
2909 }; 2631 };
2910 }; 2632 };
2911 2633
2912 replicator@6046000 { 2634 replicator@6046000 {
2913 compatible = "arm,cor 2635 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2636 reg = <0 0x06046000 0 0x1000>;
2915 2637
2916 clocks = <&aoss_qmp>; 2638 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2639 clock-names = "apb_pclk";
2918 2640
2919 out-ports { 2641 out-ports {
2920 #address-cell 2642 #address-cells = <1>;
2921 #size-cells = 2643 #size-cells = <0>;
2922 2644
2923 port@0 { 2645 port@0 {
2924 reg = 2646 reg = <0>;
2925 repli 2647 replicator_out0: endpoint {
2926 2648 remote-endpoint = <&etr_in>;
2927 }; 2649 };
2928 }; 2650 };
2929 2651
2930 port@1 { 2652 port@1 {
2931 reg = 2653 reg = <1>;
2932 repli 2654 replicator_out1: endpoint {
2933 2655 remote-endpoint = <&replicator1_in>;
2934 }; 2656 };
2935 }; 2657 };
2936 }; 2658 };
2937 2659
2938 in-ports { 2660 in-ports {
2939 port { 2661 port {
2940 repli 2662 replicator_in0: endpoint {
2941 2663 remote-endpoint = <&etf_out>;
2942 }; 2664 };
2943 }; 2665 };
2944 }; 2666 };
2945 }; 2667 };
2946 2668
2947 etf@6047000 { 2669 etf@6047000 {
2948 compatible = "arm,cor 2670 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2671 reg = <0 0x06047000 0 0x1000>;
2950 2672
2951 clocks = <&aoss_qmp>; 2673 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2674 clock-names = "apb_pclk";
2953 2675
2954 out-ports { 2676 out-ports {
2955 port { 2677 port {
2956 etf_o 2678 etf_out: endpoint {
2957 2679 remote-endpoint = <&replicator_in0>;
2958 }; 2680 };
2959 }; 2681 };
2960 }; 2682 };
2961 2683
2962 in-ports { 2684 in-ports {
2963 port { 2685 port {
2964 etf_i 2686 etf_in: endpoint {
2965 2687 remote-endpoint = <&merge_funnel_out>;
2966 }; 2688 };
2967 }; 2689 };
2968 }; 2690 };
2969 }; 2691 };
2970 2692
2971 etr@6048000 { 2693 etr@6048000 {
2972 compatible = "arm,cor 2694 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2695 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2696 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2697
2976 clocks = <&aoss_qmp>; 2698 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2699 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2700 arm,scatter-gather;
2979 2701
2980 in-ports { 2702 in-ports {
2981 port { 2703 port {
2982 etr_i 2704 etr_in: endpoint {
2983 2705 remote-endpoint = <&replicator_out0>;
2984 }; 2706 };
2985 }; 2707 };
2986 }; 2708 };
2987 }; 2709 };
2988 2710
2989 replicator@604a000 { 2711 replicator@604a000 {
2990 compatible = "arm,cor 2712 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2713 reg = <0 0x0604a000 0 0x1000>;
2992 2714
2993 clocks = <&aoss_qmp>; 2715 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2716 clock-names = "apb_pclk";
2995 2717
2996 out-ports { 2718 out-ports {
2997 #address-cell 2719 #address-cells = <1>;
2998 #size-cells = 2720 #size-cells = <0>;
2999 2721
3000 port@1 { 2722 port@1 {
3001 reg = 2723 reg = <1>;
3002 repli 2724 replicator1_out: endpoint {
3003 2725 remote-endpoint = <&swao_funnel_in>;
3004 }; 2726 };
3005 }; 2727 };
3006 }; 2728 };
3007 2729
3008 in-ports { 2730 in-ports {
>> 2731 #address-cells = <1>;
>> 2732 #size-cells = <0>;
3009 2733
3010 port { !! 2734 port@1 {
>> 2735 reg = <1>;
3011 repli 2736 replicator1_in: endpoint {
3012 2737 remote-endpoint = <&replicator_out1>;
3013 }; 2738 };
3014 }; 2739 };
3015 }; 2740 };
3016 }; 2741 };
3017 2742
3018 funnel@6b08000 { 2743 funnel@6b08000 {
3019 compatible = "arm,cor 2744 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2745 reg = <0 0x06b08000 0 0x1000>;
3021 2746
3022 clocks = <&aoss_qmp>; 2747 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2748 clock-names = "apb_pclk";
3024 2749
3025 out-ports { 2750 out-ports {
3026 port { 2751 port {
3027 swao_ 2752 swao_funnel_out: endpoint {
3028 2753 remote-endpoint = <&swao_etf_in>;
3029 }; 2754 };
3030 }; 2755 };
3031 }; 2756 };
3032 2757
3033 in-ports { 2758 in-ports {
3034 #address-cell 2759 #address-cells = <1>;
3035 #size-cells = 2760 #size-cells = <0>;
3036 2761
3037 port@6 { 2762 port@6 {
3038 reg = 2763 reg = <6>;
3039 swao_ 2764 swao_funnel_in: endpoint {
3040 2765 remote-endpoint = <&replicator1_out>;
3041 }; 2766 };
3042 }; 2767 };
3043 }; 2768 };
3044 }; 2769 };
3045 2770
3046 etf@6b09000 { 2771 etf@6b09000 {
3047 compatible = "arm,cor 2772 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2773 reg = <0 0x06b09000 0 0x1000>;
3049 2774
3050 clocks = <&aoss_qmp>; 2775 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2776 clock-names = "apb_pclk";
3052 2777
3053 out-ports { 2778 out-ports {
3054 port { 2779 port {
3055 swao_ 2780 swao_etf_out: endpoint {
3056 2781 remote-endpoint = <&swao_replicator_in>;
3057 }; 2782 };
3058 }; 2783 };
3059 }; 2784 };
3060 2785
3061 in-ports { 2786 in-ports {
3062 port { 2787 port {
3063 swao_ 2788 swao_etf_in: endpoint {
3064 2789 remote-endpoint = <&swao_funnel_out>;
3065 }; 2790 };
3066 }; 2791 };
3067 }; 2792 };
3068 }; 2793 };
3069 2794
3070 replicator@6b0a000 { 2795 replicator@6b0a000 {
3071 compatible = "arm,cor 2796 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 2797 reg = <0 0x06b0a000 0 0x1000>;
3073 2798
3074 clocks = <&aoss_qmp>; 2799 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 2800 clock-names = "apb_pclk";
3076 qcom,replicator-loses 2801 qcom,replicator-loses-context;
3077 2802
3078 out-ports { 2803 out-ports {
3079 port { 2804 port {
3080 swao_ 2805 swao_replicator_out: endpoint {
3081 2806 remote-endpoint = <&funnel1_in4>;
3082 }; 2807 };
3083 }; 2808 };
3084 }; 2809 };
3085 2810
3086 in-ports { 2811 in-ports {
3087 port { 2812 port {
3088 swao_ 2813 swao_replicator_in: endpoint {
3089 2814 remote-endpoint = <&swao_etf_out>;
3090 }; 2815 };
3091 }; 2816 };
3092 }; 2817 };
3093 }; 2818 };
3094 2819
3095 etm@7040000 { 2820 etm@7040000 {
3096 compatible = "arm,cor 2821 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 2822 reg = <0 0x07040000 0 0x1000>;
3098 2823
3099 cpu = <&CPU0>; 2824 cpu = <&CPU0>;
3100 2825
3101 clocks = <&aoss_qmp>; 2826 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 2827 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 2828 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 2829 qcom,skip-power-up;
3105 2830
3106 out-ports { 2831 out-ports {
3107 port { 2832 port {
3108 etm0_ 2833 etm0_out: endpoint {
3109 2834 remote-endpoint = <&apss_funnel_in0>;
3110 }; 2835 };
3111 }; 2836 };
3112 }; 2837 };
3113 }; 2838 };
3114 2839
3115 etm@7140000 { 2840 etm@7140000 {
3116 compatible = "arm,cor 2841 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 2842 reg = <0 0x07140000 0 0x1000>;
3118 2843
3119 cpu = <&CPU1>; 2844 cpu = <&CPU1>;
3120 2845
3121 clocks = <&aoss_qmp>; 2846 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 2847 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 2848 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 2849 qcom,skip-power-up;
3125 2850
3126 out-ports { 2851 out-ports {
3127 port { 2852 port {
3128 etm1_ 2853 etm1_out: endpoint {
3129 2854 remote-endpoint = <&apss_funnel_in1>;
3130 }; 2855 };
3131 }; 2856 };
3132 }; 2857 };
3133 }; 2858 };
3134 2859
3135 etm@7240000 { 2860 etm@7240000 {
3136 compatible = "arm,cor 2861 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 2862 reg = <0 0x07240000 0 0x1000>;
3138 2863
3139 cpu = <&CPU2>; 2864 cpu = <&CPU2>;
3140 2865
3141 clocks = <&aoss_qmp>; 2866 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 2867 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 2868 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 2869 qcom,skip-power-up;
3145 2870
3146 out-ports { 2871 out-ports {
3147 port { 2872 port {
3148 etm2_ 2873 etm2_out: endpoint {
3149 2874 remote-endpoint = <&apss_funnel_in2>;
3150 }; 2875 };
3151 }; 2876 };
3152 }; 2877 };
3153 }; 2878 };
3154 2879
3155 etm@7340000 { 2880 etm@7340000 {
3156 compatible = "arm,cor 2881 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 2882 reg = <0 0x07340000 0 0x1000>;
3158 2883
3159 cpu = <&CPU3>; 2884 cpu = <&CPU3>;
3160 2885
3161 clocks = <&aoss_qmp>; 2886 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 2887 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 2888 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 2889 qcom,skip-power-up;
3165 2890
3166 out-ports { 2891 out-ports {
3167 port { 2892 port {
3168 etm3_ 2893 etm3_out: endpoint {
3169 2894 remote-endpoint = <&apss_funnel_in3>;
3170 }; 2895 };
3171 }; 2896 };
3172 }; 2897 };
3173 }; 2898 };
3174 2899
3175 etm@7440000 { 2900 etm@7440000 {
3176 compatible = "arm,cor 2901 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 2902 reg = <0 0x07440000 0 0x1000>;
3178 2903
3179 cpu = <&CPU4>; 2904 cpu = <&CPU4>;
3180 2905
3181 clocks = <&aoss_qmp>; 2906 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 2907 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 2908 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 2909 qcom,skip-power-up;
3185 2910
3186 out-ports { 2911 out-ports {
3187 port { 2912 port {
3188 etm4_ 2913 etm4_out: endpoint {
3189 2914 remote-endpoint = <&apss_funnel_in4>;
3190 }; 2915 };
3191 }; 2916 };
3192 }; 2917 };
3193 }; 2918 };
3194 2919
3195 etm@7540000 { 2920 etm@7540000 {
3196 compatible = "arm,cor 2921 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 2922 reg = <0 0x07540000 0 0x1000>;
3198 2923
3199 cpu = <&CPU5>; 2924 cpu = <&CPU5>;
3200 2925
3201 clocks = <&aoss_qmp>; 2926 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 2927 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 2928 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 2929 qcom,skip-power-up;
3205 2930
3206 out-ports { 2931 out-ports {
3207 port { 2932 port {
3208 etm5_ 2933 etm5_out: endpoint {
3209 2934 remote-endpoint = <&apss_funnel_in5>;
3210 }; 2935 };
3211 }; 2936 };
3212 }; 2937 };
3213 }; 2938 };
3214 2939
3215 etm@7640000 { 2940 etm@7640000 {
3216 compatible = "arm,cor 2941 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 2942 reg = <0 0x07640000 0 0x1000>;
3218 2943
3219 cpu = <&CPU6>; 2944 cpu = <&CPU6>;
3220 2945
3221 clocks = <&aoss_qmp>; 2946 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 2947 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 2948 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 2949 qcom,skip-power-up;
3225 2950
3226 out-ports { 2951 out-ports {
3227 port { 2952 port {
3228 etm6_ 2953 etm6_out: endpoint {
3229 2954 remote-endpoint = <&apss_funnel_in6>;
3230 }; 2955 };
3231 }; 2956 };
3232 }; 2957 };
3233 }; 2958 };
3234 2959
3235 etm@7740000 { 2960 etm@7740000 {
3236 compatible = "arm,cor 2961 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 2962 reg = <0 0x07740000 0 0x1000>;
3238 2963
3239 cpu = <&CPU7>; 2964 cpu = <&CPU7>;
3240 2965
3241 clocks = <&aoss_qmp>; 2966 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 2967 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 2968 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 2969 qcom,skip-power-up;
3245 2970
3246 out-ports { 2971 out-ports {
3247 port { 2972 port {
3248 etm7_ 2973 etm7_out: endpoint {
3249 2974 remote-endpoint = <&apss_funnel_in7>;
3250 }; 2975 };
3251 }; 2976 };
3252 }; 2977 };
3253 }; 2978 };
3254 2979
3255 funnel@7800000 { /* APSS Funn 2980 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 2981 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 2982 reg = <0 0x07800000 0 0x1000>;
3258 2983
3259 clocks = <&aoss_qmp>; 2984 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 2985 clock-names = "apb_pclk";
3261 2986
3262 out-ports { 2987 out-ports {
3263 port { 2988 port {
3264 apss_ 2989 apss_funnel_out: endpoint {
3265 2990 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 2991 };
3267 }; 2992 };
3268 }; 2993 };
3269 2994
3270 in-ports { 2995 in-ports {
3271 #address-cell 2996 #address-cells = <1>;
3272 #size-cells = 2997 #size-cells = <0>;
3273 2998
3274 port@0 { 2999 port@0 {
3275 reg = 3000 reg = <0>;
3276 apss_ 3001 apss_funnel_in0: endpoint {
3277 3002 remote-endpoint = <&etm0_out>;
3278 }; 3003 };
3279 }; 3004 };
3280 3005
3281 port@1 { 3006 port@1 {
3282 reg = 3007 reg = <1>;
3283 apss_ 3008 apss_funnel_in1: endpoint {
3284 3009 remote-endpoint = <&etm1_out>;
3285 }; 3010 };
3286 }; 3011 };
3287 3012
3288 port@2 { 3013 port@2 {
3289 reg = 3014 reg = <2>;
3290 apss_ 3015 apss_funnel_in2: endpoint {
3291 3016 remote-endpoint = <&etm2_out>;
3292 }; 3017 };
3293 }; 3018 };
3294 3019
3295 port@3 { 3020 port@3 {
3296 reg = 3021 reg = <3>;
3297 apss_ 3022 apss_funnel_in3: endpoint {
3298 3023 remote-endpoint = <&etm3_out>;
3299 }; 3024 };
3300 }; 3025 };
3301 3026
3302 port@4 { 3027 port@4 {
3303 reg = 3028 reg = <4>;
3304 apss_ 3029 apss_funnel_in4: endpoint {
3305 3030 remote-endpoint = <&etm4_out>;
3306 }; 3031 };
3307 }; 3032 };
3308 3033
3309 port@5 { 3034 port@5 {
3310 reg = 3035 reg = <5>;
3311 apss_ 3036 apss_funnel_in5: endpoint {
3312 3037 remote-endpoint = <&etm5_out>;
3313 }; 3038 };
3314 }; 3039 };
3315 3040
3316 port@6 { 3041 port@6 {
3317 reg = 3042 reg = <6>;
3318 apss_ 3043 apss_funnel_in6: endpoint {
3319 3044 remote-endpoint = <&etm6_out>;
3320 }; 3045 };
3321 }; 3046 };
3322 3047
3323 port@7 { 3048 port@7 {
3324 reg = 3049 reg = <7>;
3325 apss_ 3050 apss_funnel_in7: endpoint {
3326 3051 remote-endpoint = <&etm7_out>;
3327 }; 3052 };
3328 }; 3053 };
3329 }; 3054 };
3330 }; 3055 };
3331 3056
3332 funnel@7810000 { 3057 funnel@7810000 {
3333 compatible = "arm,cor 3058 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3059 reg = <0 0x07810000 0 0x1000>;
3335 3060
3336 clocks = <&aoss_qmp>; 3061 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3062 clock-names = "apb_pclk";
3338 3063
3339 out-ports { 3064 out-ports {
3340 port { 3065 port {
3341 apss_ 3066 apss_merge_funnel_out: endpoint {
3342 3067 remote-endpoint = <&funnel2_in2>;
3343 }; 3068 };
3344 }; 3069 };
3345 }; 3070 };
3346 3071
3347 in-ports { 3072 in-ports {
3348 port { 3073 port {
3349 apss_ 3074 apss_merge_funnel_in: endpoint {
3350 3075 remote-endpoint = <&apss_funnel_out>;
3351 }; 3076 };
3352 }; 3077 };
3353 }; 3078 };
3354 }; 3079 };
3355 3080
3356 remoteproc_cdsp: remoteproc@8 3081 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3082 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3083 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3084
3360 interrupts-extended = 3085 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3086 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3087 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3088 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3089 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3090 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3091 "handover", "stop-ack";
3367 3092
3368 clocks = <&rpmhcc RPM 3093 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3094 clock-names = "xo";
3370 3095
3371 power-domains = <&rpm !! 3096 power-domains = <&rpmhpd 7>;
3372 3097
3373 memory-region = <&cds 3098 memory-region = <&cdsp_mem>;
3374 3099
3375 qcom,qmp = <&aoss_qmp 3100 qcom,qmp = <&aoss_qmp>;
3376 3101
3377 qcom,smem-states = <& 3102 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3103 qcom,smem-state-names = "stop";
3379 3104
3380 status = "disabled"; 3105 status = "disabled";
3381 3106
3382 glink-edge { 3107 glink-edge {
3383 interrupts = 3108 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3109 label = "cdsp";
3385 qcom,remote-p 3110 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3111 mboxes = <&apss_shared 4>;
3387 3112
3388 fastrpc { 3113 fastrpc {
3389 compa 3114 compatible = "qcom,fastrpc";
3390 qcom, 3115 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3116 label = "cdsp";
3392 qcom, 3117 qcom,non-secure-domain;
3393 #addr 3118 #address-cells = <1>;
3394 #size 3119 #size-cells = <0>;
3395 3120
3396 compu 3121 compute-cb@1 {
3397 3122 compatible = "qcom,fastrpc-compute-cb";
3398 3123 reg = <1>;
3399 !! 3124 iommus = <&apps_smmu 0x1401 0x2040>,
>> 3125 <&apps_smmu 0x1421 0x0>,
>> 3126 <&apps_smmu 0x2001 0x420>,
>> 3127 <&apps_smmu 0x2041 0x0>;
3400 }; 3128 };
3401 3129
3402 compu 3130 compute-cb@2 {
3403 3131 compatible = "qcom,fastrpc-compute-cb";
3404 3132 reg = <2>;
3405 !! 3133 iommus = <&apps_smmu 0x2 0x3440>,
>> 3134 <&apps_smmu 0x22 0x3400>;
3406 }; 3135 };
3407 3136
3408 compu 3137 compute-cb@3 {
3409 3138 compatible = "qcom,fastrpc-compute-cb";
3410 3139 reg = <3>;
3411 !! 3140 iommus = <&apps_smmu 0x3 0x3440>,
>> 3141 <&apps_smmu 0x1423 0x0>,
>> 3142 <&apps_smmu 0x2023 0x0>;
3412 }; 3143 };
3413 3144
3414 compu 3145 compute-cb@4 {
3415 3146 compatible = "qcom,fastrpc-compute-cb";
3416 3147 reg = <4>;
3417 !! 3148 iommus = <&apps_smmu 0x4 0x3440>,
>> 3149 <&apps_smmu 0x24 0x3400>;
3418 }; 3150 };
3419 3151
3420 compu 3152 compute-cb@5 {
3421 3153 compatible = "qcom,fastrpc-compute-cb";
3422 3154 reg = <5>;
3423 !! 3155 iommus = <&apps_smmu 0x5 0x3440>,
>> 3156 <&apps_smmu 0x25 0x3400>;
3424 }; 3157 };
3425 3158
3426 compu 3159 compute-cb@6 {
3427 3160 compatible = "qcom,fastrpc-compute-cb";
3428 3161 reg = <6>;
3429 !! 3162 iommus = <&apps_smmu 0x6 0x3460>;
3430 }; 3163 };
3431 3164
3432 compu 3165 compute-cb@7 {
3433 3166 compatible = "qcom,fastrpc-compute-cb";
3434 3167 reg = <7>;
3435 !! 3168 iommus = <&apps_smmu 0x7 0x3460>;
3436 }; 3169 };
3437 3170
3438 compu 3171 compute-cb@8 {
3439 3172 compatible = "qcom,fastrpc-compute-cb";
3440 3173 reg = <8>;
3441 !! 3174 iommus = <&apps_smmu 0x8 0x3460>;
3442 }; 3175 };
3443 3176
3444 /* no 3177 /* note: secure cb9 in downstream */
3445 }; 3178 };
3446 }; 3179 };
3447 }; 3180 };
3448 3181
3449 usb_1_hsphy: phy@88e2000 { 3182 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3183 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3184 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3185 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3186 status = "disabled";
3454 #phy-cells = <0>; 3187 #phy-cells = <0>;
3455 3188
3456 clocks = <&rpmhcc RPM 3189 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3190 clock-names = "ref";
3458 3191
3459 resets = <&gcc GCC_QU 3192 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3193 };
3461 3194
3462 usb_2_hsphy: phy@88e3000 { 3195 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3196 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3197 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3198 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3199 status = "disabled";
3467 #phy-cells = <0>; 3200 #phy-cells = <0>;
3468 3201
3469 clocks = <&rpmhcc RPM 3202 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3203 clock-names = "ref";
3471 3204
3472 resets = <&gcc GCC_QU 3205 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3206 };
3474 3207
3475 usb_1_qmpphy: phy@88e8000 { !! 3208 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 3209 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 3210 reg = <0 0x088e9000 0 0x18c>,
>> 3211 <0 0x088e8000 0 0x10>;
>> 3212 status = "disabled";
>> 3213 #address-cells = <2>;
>> 3214 #size-cells = <2>;
>> 3215 ranges;
3478 3216
3479 clocks = <&gcc GCC_US 3217 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3218 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3219 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3220 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3221 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3222
3488 resets = <&gcc GCC_US 3223 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3224 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3225 reset-names = "phy", "common";
3491 3226
3492 #clock-cells = <1>; !! 3227 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3228 reg = <0 0x088e9200 0 0x200>,
3494 !! 3229 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3230 <0 0x088e9c00 0 0x218>,
3496 !! 3231 <0 0x088e9600 0 0x200>,
3497 ports { !! 3232 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3233 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3234 #clock-cells = <0>;
3500 !! 3235 #phy-cells = <0>;
3501 port@0 { !! 3236 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3237 clock-names = "pipe0";
3503 !! 3238 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3239 };
3524 }; 3240 };
3525 3241
3526 usb_2_qmpphy: phy@88eb000 { 3242 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3243 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3244 reg = <0 0x088eb000 0 0x200>;
>> 3245 status = "disabled";
>> 3246 #address-cells = <2>;
>> 3247 #size-cells = <2>;
>> 3248 ranges;
3529 3249
3530 clocks = <&gcc GCC_US 3250 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3251 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3252 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3253 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3254 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 <<
3542 resets = <&gcc GCC_US <<
3543 <&gcc GCC_US <<
3544 reset-names = "phy", <<
3545 "phy_ph <<
3546 <<
3547 status = "disabled"; <<
3548 }; <<
3549 <<
3550 sdhc_2: mmc@8804000 { <<
3551 compatible = "qcom,sm <<
3552 reg = <0 0x08804000 0 <<
3553 <<
3554 interrupts = <GIC_SPI <<
3555 <GIC_SPI <<
3556 interrupt-names = "hc <<
3557 <<
3558 clocks = <&gcc GCC_SD <<
3559 <&gcc GCC_SD <<
3560 <&rpmhcc RPM <<
3561 clock-names = "iface" <<
3562 iommus = <&apps_smmu <<
3563 qcom,dll-config = <0x <<
3564 qcom,ddr-config = <0x <<
3565 power-domains = <&rpm <<
3566 operating-points-v2 = <<
3567 <<
3568 status = "disabled"; <<
3569 <<
3570 sdhc2_opp_table: opp- <<
3571 compatible = <<
3572 <<
3573 opp-19200000 <<
3574 opp-h <<
3575 requi <<
3576 }; <<
3577 3255
3578 opp-50000000 !! 3256 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3579 opp-h !! 3257 <&gcc GCC_USB3_PHY_SEC_BCR>;
3580 requi !! 3258 reset-names = "phy", "common";
3581 }; <<
3582 <<
3583 opp-100000000 <<
3584 opp-h <<
3585 requi <<
3586 }; <<
3587 3259
3588 opp-202000000 !! 3260 usb_2_ssphy: phy@88eb200 {
3589 opp-h !! 3261 reg = <0 0x088eb200 0 0x200>,
3590 requi !! 3262 <0 0x088eb400 0 0x200>,
3591 }; !! 3263 <0 0x088eb800 0 0x800>,
>> 3264 <0 0x088eb600 0 0x200>;
>> 3265 #clock-cells = <0>;
>> 3266 #phy-cells = <0>;
>> 3267 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3268 clock-names = "pipe0";
>> 3269 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3592 }; 3270 };
3593 }; 3271 };
3594 3272
3595 dc_noc: interconnect@9160000 3273 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3274 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3275 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3276 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3277 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3278 };
3601 3279
3602 gem_noc: interconnect@9680000 3280 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3281 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3282 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3283 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3284 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3285 };
3608 3286
3609 usb_1: usb@a6f8800 { 3287 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3288 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3289 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3290 status = "disabled";
3613 #address-cells = <2>; 3291 #address-cells = <2>;
3614 #size-cells = <2>; 3292 #size-cells = <2>;
3615 ranges; 3293 ranges;
3616 dma-ranges; 3294 dma-ranges;
3617 3295
3618 clocks = <&gcc GCC_CF 3296 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3297 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3298 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US <<
3622 <&gcc GCC_US 3299 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 3300 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3623 <&gcc GCC_US 3301 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no !! 3302 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3625 "core", !! 3303 "sleep", "xo";
3626 "iface" <<
3627 "sleep" <<
3628 "mock_u <<
3629 "xo"; <<
3630 3304
3631 assigned-clocks = <&g 3305 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3306 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3307 assigned-clock-rates = <19200000>, <200000000>;
3634 3308
3635 interrupts-extended = !! 3309 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3310 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3311 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 3312 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 3313 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3314 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3315
3646 power-domains = <&gcc 3316 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3317
3648 resets = <&gcc GCC_US 3318 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3319
3650 interconnects = <&agg !! 3320 usb_1_dwc3: dwc3@a600000 {
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 <<
3655 compatible = 3321 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3322 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3323 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3324 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3325 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3326 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3327 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3328 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3329 };
3684 }; 3330 };
3685 3331
3686 usb_2: usb@a8f8800 { 3332 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3333 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3334 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3335 status = "disabled";
3690 #address-cells = <2>; 3336 #address-cells = <2>;
3691 #size-cells = <2>; 3337 #size-cells = <2>;
3692 ranges; 3338 ranges;
3693 dma-ranges; 3339 dma-ranges;
3694 3340
3695 clocks = <&gcc GCC_CF 3341 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3342 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3343 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US <<
3699 <&gcc GCC_US 3344 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 3345 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3700 <&gcc GCC_US 3346 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no !! 3347 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3702 "core", !! 3348 "sleep", "xo";
3703 "iface" <<
3704 "sleep" <<
3705 "mock_u <<
3706 "xo"; <<
3707 3349
3708 assigned-clocks = <&g 3350 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3351 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3352 assigned-clock-rates = <19200000>, <200000000>;
3711 3353
3712 interrupts-extended = !! 3354 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3355 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3356 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 3357 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 3358 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3359 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3360
3723 power-domains = <&gcc 3361 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3362
3725 resets = <&gcc GCC_US 3363 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3364
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3365 usb_2_dwc3: usb@a800000 {
3732 compatible = 3366 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3367 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3368 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3369 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3370 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3371 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3372 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3373 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3374 };
3741 }; 3375 };
3742 3376
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3377 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3378 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3379 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3380 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3381 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3382 };
3762 3383
3763 camcc: clock-controller@ad000 !! 3384 aoss_qmp: power-controller@c300000 {
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 <<
4150 compatible = "qcom,sm <<
4151 reg = <0 0x0b220000 0 <<
4152 qcom,pdc-ranges = <0 <<
4153 <12 <<
4154 #interrupt-cells = <2 <<
4155 interrupt-parent = <& <<
4156 interrupt-controller; <<
4157 }; <<
4158 <<
4159 aoss_qmp: power-management@c3 <<
4160 compatible = "qcom,sm 3385 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 3386 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 3387 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3388 mboxes = <&apss_shared 0>;
4164 3389
4165 #clock-cells = <0>; 3390 #clock-cells = <0>;
4166 }; 3391 };
4167 3392
4168 sram@c3f0000 { 3393 sram@c3f0000 {
4169 compatible = "qcom,rp 3394 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 3395 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 3396 };
4172 3397
4173 tsens0: thermal-sensor@c26300 3398 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3399 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3400 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3401 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3402 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3403 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3404 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3405 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3406 #thermal-sensor-cells = <1>;
4182 }; 3407 };
4183 3408
4184 tsens1: thermal-sensor@c26500 3409 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3410 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3411 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3412 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3413 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3414 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3415 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3416 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3417 #thermal-sensor-cells = <1>;
4193 }; 3418 };
4194 3419
4195 spmi_bus: spmi@c440000 { 3420 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3421 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3422 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3423 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3424 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3425 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3426 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3427 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3428 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3429 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3430 qcom,ee = <0>;
4206 qcom,channel = <0>; 3431 qcom,channel = <0>;
4207 #address-cells = <2>; 3432 #address-cells = <2>;
4208 #size-cells = <0>; 3433 #size-cells = <0>;
4209 interrupt-controller; 3434 interrupt-controller;
4210 #interrupt-cells = <4 3435 #interrupt-cells = <4>;
>> 3436 cell-index = <0>;
4211 }; 3437 };
4212 3438
4213 apps_smmu: iommu@15000000 { 3439 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3440 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3441 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3442 #iommu-cells = <2>;
4217 #global-interrupts = 3443 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3444 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3445 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3446 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3447 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3448 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3449 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3450 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3451 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3452 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3453 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3454 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3455 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3456 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3457 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3458 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3459 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3460 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3461 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3462 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3463 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3464 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3465 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3466 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3467 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3468 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3469 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3470 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3471 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3472 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3473 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3474 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3475 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3476 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3477 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3478 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3479 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3480 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3481 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3482 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3483 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3484 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3485 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 3486 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 3487 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 3488 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 3489 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 3490 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 3491 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 3492 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 3493 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 3494 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 3495 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 3496 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 3497 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 3498 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 3499 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 3500 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 3501 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 3502 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 3503 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 3504 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 3505 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 3506 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 3507 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 3508 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 3509 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 3510 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 3511 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 3512 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 3513 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 3514 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 3515 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 3516 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 3517 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 3518 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 3519 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 3520 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 3521 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 3522 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 3523 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 3524 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 3525 };
4300 3526
4301 remoteproc_adsp: remoteproc@1 3527 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 3528 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 3529 reg = <0x0 0x17300000 0x0 0x4040>;
4304 3530
4305 interrupts-extended = 3531 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 3532 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 3533 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 3534 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 3535 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 3536 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 3537 "handover", "stop-ack";
4312 3538
4313 clocks = <&rpmhcc RPM 3539 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 3540 clock-names = "xo";
4315 3541
4316 power-domains = <&rpm !! 3542 power-domains = <&rpmhpd 7>;
4317 3543
4318 memory-region = <&ads 3544 memory-region = <&adsp_mem>;
4319 3545
4320 qcom,qmp = <&aoss_qmp 3546 qcom,qmp = <&aoss_qmp>;
4321 3547
4322 qcom,smem-states = <& 3548 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 3549 qcom,smem-state-names = "stop";
4324 3550
4325 status = "disabled"; 3551 status = "disabled";
4326 3552
4327 glink-edge { 3553 glink-edge {
4328 interrupts = 3554 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 3555 label = "lpass";
4330 qcom,remote-p 3556 qcom,remote-pid = <2>;
4331 mboxes = <&ap 3557 mboxes = <&apss_shared 8>;
4332 3558
4333 fastrpc { 3559 fastrpc {
4334 compa 3560 compatible = "qcom,fastrpc";
4335 qcom, 3561 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 3562 label = "adsp";
4337 qcom, 3563 qcom,non-secure-domain;
4338 #addr 3564 #address-cells = <1>;
4339 #size 3565 #size-cells = <0>;
4340 3566
4341 compu 3567 compute-cb@3 {
4342 3568 compatible = "qcom,fastrpc-compute-cb";
4343 3569 reg = <3>;
4344 3570 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 3571 };
4346 3572
4347 compu 3573 compute-cb@4 {
4348 3574 compatible = "qcom,fastrpc-compute-cb";
4349 3575 reg = <4>;
4350 3576 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 3577 };
4352 3578
4353 compu 3579 compute-cb@5 {
4354 3580 compatible = "qcom,fastrpc-compute-cb";
4355 3581 reg = <5>;
4356 3582 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 3583 };
4358 }; 3584 };
4359 }; 3585 };
4360 }; 3586 };
4361 3587
4362 intc: interrupt-controller@17 3588 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 3589 compatible = "arm,gic-v3";
4364 interrupt-controller; 3590 interrupt-controller;
4365 #interrupt-cells = <3 3591 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 3592 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 3593 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 3594 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 3595 };
4370 3596
4371 apss_shared: mailbox@17c00000 3597 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 3598 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 3599 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 3600 #mbox-cells = <1>;
4376 }; 3601 };
4377 3602
4378 watchdog@17c10000 { 3603 watchdog@17c10000 {
4379 compatible = "qcom,ap 3604 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 3605 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 3606 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 3607 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 3608 };
4384 3609
4385 timer@17c20000 { 3610 timer@17c20000 {
4386 #address-cells = <1>; 3611 #address-cells = <1>;
4387 #size-cells = <1>; 3612 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 3613 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 3614 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 3615 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 3616 clock-frequency = <19200000>;
4392 3617
4393 frame@17c21000 { !! 3618 frame@17c21000{
4394 frame-number 3619 frame-number = <0>;
4395 interrupts = 3620 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 3621 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 3622 reg = <0x17c21000 0x1000>,
4398 <0x17c2 3623 <0x17c22000 0x1000>;
4399 }; 3624 };
4400 3625
4401 frame@17c23000 { 3626 frame@17c23000 {
4402 frame-number 3627 frame-number = <1>;
4403 interrupts = 3628 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 3629 reg = <0x17c23000 0x1000>;
4405 status = "dis 3630 status = "disabled";
4406 }; 3631 };
4407 3632
4408 frame@17c25000 { 3633 frame@17c25000 {
4409 frame-number 3634 frame-number = <2>;
4410 interrupts = 3635 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 3636 reg = <0x17c25000 0x1000>;
4412 status = "dis 3637 status = "disabled";
4413 }; 3638 };
4414 3639
4415 frame@17c27000 { 3640 frame@17c27000 {
4416 frame-number 3641 frame-number = <3>;
4417 interrupts = 3642 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 3643 reg = <0x17c26000 0x1000>;
4419 status = "dis 3644 status = "disabled";
4420 }; 3645 };
4421 3646
4422 frame@17c29000 { 3647 frame@17c29000 {
4423 frame-number 3648 frame-number = <4>;
4424 interrupts = 3649 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 3650 reg = <0x17c29000 0x1000>;
4426 status = "dis 3651 status = "disabled";
4427 }; 3652 };
4428 3653
4429 frame@17c2b000 { 3654 frame@17c2b000 {
4430 frame-number 3655 frame-number = <5>;
4431 interrupts = 3656 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 3657 reg = <0x17c2b000 0x1000>;
4433 status = "dis 3658 status = "disabled";
4434 }; 3659 };
4435 3660
4436 frame@17c2d000 { 3661 frame@17c2d000 {
4437 frame-number 3662 frame-number = <6>;
4438 interrupts = 3663 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 3664 reg = <0x17c2d000 0x1000>;
4440 status = "dis 3665 status = "disabled";
4441 }; 3666 };
4442 }; 3667 };
4443 3668
4444 apps_rsc: rsc@18200000 { 3669 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 3670 label = "apps_rsc";
4446 compatible = "qcom,rp 3671 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 3672 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 3673 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 3674 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 3675 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 3676 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 3677 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 3678 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 3679 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 3680 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 3681 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 3682 <SLEEP_TCS 3>,
4458 <WA 3683 <WAKE_TCS 3>,
4459 <CO 3684 <CONTROL_TCS 1>;
4460 power-domains = <&CLU <<
4461 3685
4462 rpmhcc: clock-control 3686 rpmhcc: clock-controller {
4463 compatible = 3687 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 3688 #clock-cells = <1>;
4465 clock-names = 3689 clock-names = "xo";
4466 clocks = <&xo 3690 clocks = <&xo_board>;
4467 }; 3691 };
4468 3692
4469 rpmhpd: power-control 3693 rpmhpd: power-controller {
4470 compatible = 3694 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 3695 #power-domain-cells = <1>;
4472 operating-poi 3696 operating-points-v2 = <&rpmhpd_opp_table>;
4473 3697
4474 rpmhpd_opp_ta 3698 rpmhpd_opp_table: opp-table {
4475 compa 3699 compatible = "operating-points-v2";
4476 3700
4477 rpmhp 3701 rpmhpd_opp_ret: opp1 {
4478 3702 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 3703 };
4480 3704
4481 rpmhp 3705 rpmhpd_opp_min_svs: opp2 {
4482 3706 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 3707 };
4484 3708
4485 rpmhp 3709 rpmhpd_opp_low_svs: opp3 {
4486 3710 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 3711 };
4488 3712
4489 rpmhp 3713 rpmhpd_opp_svs: opp4 {
4490 3714 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 3715 };
4492 3716
4493 rpmhp 3717 rpmhpd_opp_svs_l1: opp5 {
4494 3718 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 3719 };
4496 3720
4497 rpmhp 3721 rpmhpd_opp_svs_l2: opp6 {
4498 3722 opp-level = <224>;
4499 }; 3723 };
4500 3724
4501 rpmhp 3725 rpmhpd_opp_nom: opp7 {
4502 3726 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 3727 };
4504 3728
4505 rpmhp 3729 rpmhpd_opp_nom_l1: opp8 {
4506 3730 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 3731 };
4508 3732
4509 rpmhp 3733 rpmhpd_opp_nom_l2: opp9 {
4510 3734 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 3735 };
4512 3736
4513 rpmhp 3737 rpmhpd_opp_turbo: opp10 {
4514 3738 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 3739 };
4516 3740
4517 rpmhp 3741 rpmhpd_opp_turbo_l1: opp11 {
4518 3742 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 3743 };
4520 }; 3744 };
4521 }; 3745 };
4522 3746
4523 apps_bcm_voter: bcm-v !! 3747 apps_bcm_voter: bcm_voter {
4524 compatible = 3748 compatible = "qcom,bcm-voter";
4525 }; 3749 };
4526 }; 3750 };
4527 3751
4528 osm_l3: interconnect@18321000 3752 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 3753 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 3754 reg = <0 0x18321000 0 0x1400>;
4531 3755
4532 clocks = <&rpmhcc RPM 3756 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 3757 clock-names = "xo", "alternate";
4534 3758
4535 #interconnect-cells = 3759 #interconnect-cells = <1>;
4536 }; 3760 };
4537 3761
4538 cpufreq_hw: cpufreq@18323000 3762 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 3763 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 3764 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 3765 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 3766 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 3767 "freq-domain2";
4544 3768
4545 clocks = <&rpmhcc RPM 3769 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 3770 clock-names = "xo", "alternate";
4547 3771
4548 #freq-domain-cells = 3772 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; 3773 };
4551 3774
4552 lmh_cluster1: lmh@18350800 { 3775 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 3776 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 3777 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 3778 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 3779 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 3780 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 3781 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 3782 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 3783 interrupt-controller;
4561 #interrupt-cells = <1 3784 #interrupt-cells = <1>;
4562 }; 3785 };
4563 3786
4564 lmh_cluster0: lmh@18358800 { 3787 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 3788 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 3789 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 3790 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 3791 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 3792 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 3793 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 3794 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 3795 interrupt-controller;
4573 #interrupt-cells = <1 3796 #interrupt-cells = <1>;
4574 }; 3797 };
4575 3798
4576 wifi: wifi@18800000 { 3799 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 3800 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 3801 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 3802 reg-names = "membase";
4580 memory-region = <&wla 3803 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 3804 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 3805 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 3806 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 3807 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 3808 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 3809 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 3810 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 3811 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 3812 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 3813 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 3814 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 3815 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 3816 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 3817 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 3818 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 3819 status = "disabled";
4597 }; 3820 };
4598 }; 3821 };
4599 3822
4600 timer { 3823 timer {
4601 compatible = "arm,armv8-timer 3824 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 3825 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 3826 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 3827 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 3828 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 3829 };
4607 3830
4608 thermal-zones { 3831 thermal-zones {
4609 cpu0-thermal { 3832 cpu0-thermal {
4610 polling-delay-passive 3833 polling-delay-passive = <250>;
>> 3834 polling-delay = <1000>;
4611 3835
4612 thermal-sensors = <&t 3836 thermal-sensors = <&tsens0 1>;
4613 3837
4614 trips { 3838 trips {
4615 cpu0_alert0: 3839 cpu0_alert0: trip-point0 {
4616 tempe 3840 temperature = <90000>;
4617 hyste 3841 hysteresis = <2000>;
4618 type 3842 type = "passive";
4619 }; 3843 };
4620 3844
4621 cpu0_alert1: 3845 cpu0_alert1: trip-point1 {
4622 tempe 3846 temperature = <95000>;
4623 hyste 3847 hysteresis = <2000>;
4624 type 3848 type = "passive";
4625 }; 3849 };
4626 3850
4627 cpu0_crit: cp !! 3851 cpu0_crit: cpu_crit {
4628 tempe 3852 temperature = <110000>;
4629 hyste 3853 hysteresis = <1000>;
4630 type 3854 type = "critical";
4631 }; 3855 };
4632 }; 3856 };
4633 3857
4634 cooling-maps { 3858 cooling-maps {
4635 map0 { 3859 map0 {
4636 trip 3860 trip = <&cpu0_alert0>;
4637 cooli 3861 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 3862 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 3863 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 3864 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 3865 };
4642 map1 { 3866 map1 {
4643 trip 3867 trip = <&cpu0_alert1>;
4644 cooli 3868 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 3869 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 3870 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 3871 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 3872 };
4649 }; 3873 };
4650 }; 3874 };
4651 3875
4652 cpu1-thermal { 3876 cpu1-thermal {
4653 polling-delay-passive 3877 polling-delay-passive = <250>;
>> 3878 polling-delay = <1000>;
4654 3879
4655 thermal-sensors = <&t 3880 thermal-sensors = <&tsens0 2>;
4656 3881
4657 trips { 3882 trips {
4658 cpu1_alert0: 3883 cpu1_alert0: trip-point0 {
4659 tempe 3884 temperature = <90000>;
4660 hyste 3885 hysteresis = <2000>;
4661 type 3886 type = "passive";
4662 }; 3887 };
4663 3888
4664 cpu1_alert1: 3889 cpu1_alert1: trip-point1 {
4665 tempe 3890 temperature = <95000>;
4666 hyste 3891 hysteresis = <2000>;
4667 type 3892 type = "passive";
4668 }; 3893 };
4669 3894
4670 cpu1_crit: cp !! 3895 cpu1_crit: cpu_crit {
4671 tempe 3896 temperature = <110000>;
4672 hyste 3897 hysteresis = <1000>;
4673 type 3898 type = "critical";
4674 }; 3899 };
4675 }; 3900 };
4676 3901
4677 cooling-maps { 3902 cooling-maps {
4678 map0 { 3903 map0 {
4679 trip 3904 trip = <&cpu1_alert0>;
4680 cooli 3905 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 3906 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 3907 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 3908 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 3909 };
4685 map1 { 3910 map1 {
4686 trip 3911 trip = <&cpu1_alert1>;
4687 cooli 3912 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 3913 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 3914 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 3915 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 3916 };
4692 }; 3917 };
4693 }; 3918 };
4694 3919
4695 cpu2-thermal { 3920 cpu2-thermal {
4696 polling-delay-passive 3921 polling-delay-passive = <250>;
>> 3922 polling-delay = <1000>;
4697 3923
4698 thermal-sensors = <&t 3924 thermal-sensors = <&tsens0 3>;
4699 3925
4700 trips { 3926 trips {
4701 cpu2_alert0: 3927 cpu2_alert0: trip-point0 {
4702 tempe 3928 temperature = <90000>;
4703 hyste 3929 hysteresis = <2000>;
4704 type 3930 type = "passive";
4705 }; 3931 };
4706 3932
4707 cpu2_alert1: 3933 cpu2_alert1: trip-point1 {
4708 tempe 3934 temperature = <95000>;
4709 hyste 3935 hysteresis = <2000>;
4710 type 3936 type = "passive";
4711 }; 3937 };
4712 3938
4713 cpu2_crit: cp !! 3939 cpu2_crit: cpu_crit {
4714 tempe 3940 temperature = <110000>;
4715 hyste 3941 hysteresis = <1000>;
4716 type 3942 type = "critical";
4717 }; 3943 };
4718 }; 3944 };
4719 3945
4720 cooling-maps { 3946 cooling-maps {
4721 map0 { 3947 map0 {
4722 trip 3948 trip = <&cpu2_alert0>;
4723 cooli 3949 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 3950 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 3951 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 3952 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 3953 };
4728 map1 { 3954 map1 {
4729 trip 3955 trip = <&cpu2_alert1>;
4730 cooli 3956 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 3957 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 3958 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 3959 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 3960 };
4735 }; 3961 };
4736 }; 3962 };
4737 3963
4738 cpu3-thermal { 3964 cpu3-thermal {
4739 polling-delay-passive 3965 polling-delay-passive = <250>;
>> 3966 polling-delay = <1000>;
4740 3967
4741 thermal-sensors = <&t 3968 thermal-sensors = <&tsens0 4>;
4742 3969
4743 trips { 3970 trips {
4744 cpu3_alert0: 3971 cpu3_alert0: trip-point0 {
4745 tempe 3972 temperature = <90000>;
4746 hyste 3973 hysteresis = <2000>;
4747 type 3974 type = "passive";
4748 }; 3975 };
4749 3976
4750 cpu3_alert1: 3977 cpu3_alert1: trip-point1 {
4751 tempe 3978 temperature = <95000>;
4752 hyste 3979 hysteresis = <2000>;
4753 type 3980 type = "passive";
4754 }; 3981 };
4755 3982
4756 cpu3_crit: cp !! 3983 cpu3_crit: cpu_crit {
4757 tempe 3984 temperature = <110000>;
4758 hyste 3985 hysteresis = <1000>;
4759 type 3986 type = "critical";
4760 }; 3987 };
4761 }; 3988 };
4762 3989
4763 cooling-maps { 3990 cooling-maps {
4764 map0 { 3991 map0 {
4765 trip 3992 trip = <&cpu3_alert0>;
4766 cooli 3993 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 3994 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 3995 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 3996 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 3997 };
4771 map1 { 3998 map1 {
4772 trip 3999 trip = <&cpu3_alert1>;
4773 cooli 4000 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4001 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4002 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4003 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4004 };
4778 }; 4005 };
4779 }; 4006 };
4780 4007
4781 cpu4-top-thermal { 4008 cpu4-top-thermal {
4782 polling-delay-passive 4009 polling-delay-passive = <250>;
>> 4010 polling-delay = <1000>;
4783 4011
4784 thermal-sensors = <&t 4012 thermal-sensors = <&tsens0 7>;
4785 4013
4786 trips { 4014 trips {
4787 cpu4_top_aler 4015 cpu4_top_alert0: trip-point0 {
4788 tempe 4016 temperature = <90000>;
4789 hyste 4017 hysteresis = <2000>;
4790 type 4018 type = "passive";
4791 }; 4019 };
4792 4020
4793 cpu4_top_aler 4021 cpu4_top_alert1: trip-point1 {
4794 tempe 4022 temperature = <95000>;
4795 hyste 4023 hysteresis = <2000>;
4796 type 4024 type = "passive";
4797 }; 4025 };
4798 4026
4799 cpu4_top_crit !! 4027 cpu4_top_crit: cpu_crit {
4800 tempe 4028 temperature = <110000>;
4801 hyste 4029 hysteresis = <1000>;
4802 type 4030 type = "critical";
4803 }; 4031 };
4804 }; 4032 };
4805 4033
4806 cooling-maps { 4034 cooling-maps {
4807 map0 { 4035 map0 {
4808 trip 4036 trip = <&cpu4_top_alert0>;
4809 cooli 4037 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4038 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4039 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4040 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4041 };
4814 map1 { 4042 map1 {
4815 trip 4043 trip = <&cpu4_top_alert1>;
4816 cooli 4044 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4045 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4046 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4047 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4048 };
4821 }; 4049 };
4822 }; 4050 };
4823 4051
4824 cpu5-top-thermal { 4052 cpu5-top-thermal {
4825 polling-delay-passive 4053 polling-delay-passive = <250>;
>> 4054 polling-delay = <1000>;
4826 4055
4827 thermal-sensors = <&t 4056 thermal-sensors = <&tsens0 8>;
4828 4057
4829 trips { 4058 trips {
4830 cpu5_top_aler 4059 cpu5_top_alert0: trip-point0 {
4831 tempe 4060 temperature = <90000>;
4832 hyste 4061 hysteresis = <2000>;
4833 type 4062 type = "passive";
4834 }; 4063 };
4835 4064
4836 cpu5_top_aler 4065 cpu5_top_alert1: trip-point1 {
4837 tempe 4066 temperature = <95000>;
4838 hyste 4067 hysteresis = <2000>;
4839 type 4068 type = "passive";
4840 }; 4069 };
4841 4070
4842 cpu5_top_crit !! 4071 cpu5_top_crit: cpu_crit {
4843 tempe 4072 temperature = <110000>;
4844 hyste 4073 hysteresis = <1000>;
4845 type 4074 type = "critical";
4846 }; 4075 };
4847 }; 4076 };
4848 4077
4849 cooling-maps { 4078 cooling-maps {
4850 map0 { 4079 map0 {
4851 trip 4080 trip = <&cpu5_top_alert0>;
4852 cooli 4081 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4082 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4083 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4084 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4085 };
4857 map1 { 4086 map1 {
4858 trip 4087 trip = <&cpu5_top_alert1>;
4859 cooli 4088 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4089 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4090 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4091 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4092 };
4864 }; 4093 };
4865 }; 4094 };
4866 4095
4867 cpu6-top-thermal { 4096 cpu6-top-thermal {
4868 polling-delay-passive 4097 polling-delay-passive = <250>;
>> 4098 polling-delay = <1000>;
4869 4099
4870 thermal-sensors = <&t 4100 thermal-sensors = <&tsens0 9>;
4871 4101
4872 trips { 4102 trips {
4873 cpu6_top_aler 4103 cpu6_top_alert0: trip-point0 {
4874 tempe 4104 temperature = <90000>;
4875 hyste 4105 hysteresis = <2000>;
4876 type 4106 type = "passive";
4877 }; 4107 };
4878 4108
4879 cpu6_top_aler 4109 cpu6_top_alert1: trip-point1 {
4880 tempe 4110 temperature = <95000>;
4881 hyste 4111 hysteresis = <2000>;
4882 type 4112 type = "passive";
4883 }; 4113 };
4884 4114
4885 cpu6_top_crit !! 4115 cpu6_top_crit: cpu_crit {
4886 tempe 4116 temperature = <110000>;
4887 hyste 4117 hysteresis = <1000>;
4888 type 4118 type = "critical";
4889 }; 4119 };
4890 }; 4120 };
4891 4121
4892 cooling-maps { 4122 cooling-maps {
4893 map0 { 4123 map0 {
4894 trip 4124 trip = <&cpu6_top_alert0>;
4895 cooli 4125 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4126 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4127 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4128 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4129 };
4900 map1 { 4130 map1 {
4901 trip 4131 trip = <&cpu6_top_alert1>;
4902 cooli 4132 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4133 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4134 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4135 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4136 };
4907 }; 4137 };
4908 }; 4138 };
4909 4139
4910 cpu7-top-thermal { 4140 cpu7-top-thermal {
4911 polling-delay-passive 4141 polling-delay-passive = <250>;
>> 4142 polling-delay = <1000>;
4912 4143
4913 thermal-sensors = <&t 4144 thermal-sensors = <&tsens0 10>;
4914 4145
4915 trips { 4146 trips {
4916 cpu7_top_aler 4147 cpu7_top_alert0: trip-point0 {
4917 tempe 4148 temperature = <90000>;
4918 hyste 4149 hysteresis = <2000>;
4919 type 4150 type = "passive";
4920 }; 4151 };
4921 4152
4922 cpu7_top_aler 4153 cpu7_top_alert1: trip-point1 {
4923 tempe 4154 temperature = <95000>;
4924 hyste 4155 hysteresis = <2000>;
4925 type 4156 type = "passive";
4926 }; 4157 };
4927 4158
4928 cpu7_top_crit !! 4159 cpu7_top_crit: cpu_crit {
4929 tempe 4160 temperature = <110000>;
4930 hyste 4161 hysteresis = <1000>;
4931 type 4162 type = "critical";
4932 }; 4163 };
4933 }; 4164 };
4934 4165
4935 cooling-maps { 4166 cooling-maps {
4936 map0 { 4167 map0 {
4937 trip 4168 trip = <&cpu7_top_alert0>;
4938 cooli 4169 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4170 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4171 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4172 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4173 };
4943 map1 { 4174 map1 {
4944 trip 4175 trip = <&cpu7_top_alert1>;
4945 cooli 4176 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4177 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4178 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4179 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4180 };
4950 }; 4181 };
4951 }; 4182 };
4952 4183
4953 cpu4-bottom-thermal { 4184 cpu4-bottom-thermal {
4954 polling-delay-passive 4185 polling-delay-passive = <250>;
>> 4186 polling-delay = <1000>;
4955 4187
4956 thermal-sensors = <&t 4188 thermal-sensors = <&tsens0 11>;
4957 4189
4958 trips { 4190 trips {
4959 cpu4_bottom_a 4191 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4192 temperature = <90000>;
4961 hyste 4193 hysteresis = <2000>;
4962 type 4194 type = "passive";
4963 }; 4195 };
4964 4196
4965 cpu4_bottom_a 4197 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4198 temperature = <95000>;
4967 hyste 4199 hysteresis = <2000>;
4968 type 4200 type = "passive";
4969 }; 4201 };
4970 4202
4971 cpu4_bottom_c !! 4203 cpu4_bottom_crit: cpu_crit {
4972 tempe 4204 temperature = <110000>;
4973 hyste 4205 hysteresis = <1000>;
4974 type 4206 type = "critical";
4975 }; 4207 };
4976 }; 4208 };
4977 4209
4978 cooling-maps { 4210 cooling-maps {
4979 map0 { 4211 map0 {
4980 trip 4212 trip = <&cpu4_bottom_alert0>;
4981 cooli 4213 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4214 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4215 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4216 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4217 };
4986 map1 { 4218 map1 {
4987 trip 4219 trip = <&cpu4_bottom_alert1>;
4988 cooli 4220 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4221 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4222 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4223 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4224 };
4993 }; 4225 };
4994 }; 4226 };
4995 4227
4996 cpu5-bottom-thermal { 4228 cpu5-bottom-thermal {
4997 polling-delay-passive 4229 polling-delay-passive = <250>;
>> 4230 polling-delay = <1000>;
4998 4231
4999 thermal-sensors = <&t 4232 thermal-sensors = <&tsens0 12>;
5000 4233
5001 trips { 4234 trips {
5002 cpu5_bottom_a 4235 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4236 temperature = <90000>;
5004 hyste 4237 hysteresis = <2000>;
5005 type 4238 type = "passive";
5006 }; 4239 };
5007 4240
5008 cpu5_bottom_a 4241 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4242 temperature = <95000>;
5010 hyste 4243 hysteresis = <2000>;
5011 type 4244 type = "passive";
5012 }; 4245 };
5013 4246
5014 cpu5_bottom_c !! 4247 cpu5_bottom_crit: cpu_crit {
5015 tempe 4248 temperature = <110000>;
5016 hyste 4249 hysteresis = <1000>;
5017 type 4250 type = "critical";
5018 }; 4251 };
5019 }; 4252 };
5020 4253
5021 cooling-maps { 4254 cooling-maps {
5022 map0 { 4255 map0 {
5023 trip 4256 trip = <&cpu5_bottom_alert0>;
5024 cooli 4257 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4258 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4259 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4260 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4261 };
5029 map1 { 4262 map1 {
5030 trip 4263 trip = <&cpu5_bottom_alert1>;
5031 cooli 4264 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4265 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4266 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4267 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4268 };
5036 }; 4269 };
5037 }; 4270 };
5038 4271
5039 cpu6-bottom-thermal { 4272 cpu6-bottom-thermal {
5040 polling-delay-passive 4273 polling-delay-passive = <250>;
>> 4274 polling-delay = <1000>;
5041 4275
5042 thermal-sensors = <&t 4276 thermal-sensors = <&tsens0 13>;
5043 4277
5044 trips { 4278 trips {
5045 cpu6_bottom_a 4279 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4280 temperature = <90000>;
5047 hyste 4281 hysteresis = <2000>;
5048 type 4282 type = "passive";
5049 }; 4283 };
5050 4284
5051 cpu6_bottom_a 4285 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4286 temperature = <95000>;
5053 hyste 4287 hysteresis = <2000>;
5054 type 4288 type = "passive";
5055 }; 4289 };
5056 4290
5057 cpu6_bottom_c !! 4291 cpu6_bottom_crit: cpu_crit {
5058 tempe 4292 temperature = <110000>;
5059 hyste 4293 hysteresis = <1000>;
5060 type 4294 type = "critical";
5061 }; 4295 };
5062 }; 4296 };
5063 4297
5064 cooling-maps { 4298 cooling-maps {
5065 map0 { 4299 map0 {
5066 trip 4300 trip = <&cpu6_bottom_alert0>;
5067 cooli 4301 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4302 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4303 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4304 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4305 };
5072 map1 { 4306 map1 {
5073 trip 4307 trip = <&cpu6_bottom_alert1>;
5074 cooli 4308 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4309 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4310 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4311 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4312 };
5079 }; 4313 };
5080 }; 4314 };
5081 4315
5082 cpu7-bottom-thermal { 4316 cpu7-bottom-thermal {
5083 polling-delay-passive 4317 polling-delay-passive = <250>;
>> 4318 polling-delay = <1000>;
5084 4319
5085 thermal-sensors = <&t 4320 thermal-sensors = <&tsens0 14>;
5086 4321
5087 trips { 4322 trips {
5088 cpu7_bottom_a 4323 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4324 temperature = <90000>;
5090 hyste 4325 hysteresis = <2000>;
5091 type 4326 type = "passive";
5092 }; 4327 };
5093 4328
5094 cpu7_bottom_a 4329 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4330 temperature = <95000>;
5096 hyste 4331 hysteresis = <2000>;
5097 type 4332 type = "passive";
5098 }; 4333 };
5099 4334
5100 cpu7_bottom_c !! 4335 cpu7_bottom_crit: cpu_crit {
5101 tempe 4336 temperature = <110000>;
5102 hyste 4337 hysteresis = <1000>;
5103 type 4338 type = "critical";
5104 }; 4339 };
5105 }; 4340 };
5106 4341
5107 cooling-maps { 4342 cooling-maps {
5108 map0 { 4343 map0 {
5109 trip 4344 trip = <&cpu7_bottom_alert0>;
5110 cooli 4345 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4346 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4347 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4348 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4349 };
5115 map1 { 4350 map1 {
5116 trip 4351 trip = <&cpu7_bottom_alert1>;
5117 cooli 4352 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4353 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4354 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4355 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4356 };
5122 }; 4357 };
5123 }; 4358 };
5124 4359
5125 aoss0-thermal { 4360 aoss0-thermal {
5126 polling-delay-passive 4361 polling-delay-passive = <250>;
>> 4362 polling-delay = <1000>;
5127 4363
5128 thermal-sensors = <&t 4364 thermal-sensors = <&tsens0 0>;
5129 4365
5130 trips { 4366 trips {
5131 aoss0_alert0: 4367 aoss0_alert0: trip-point0 {
5132 tempe 4368 temperature = <90000>;
5133 hyste 4369 hysteresis = <2000>;
5134 type 4370 type = "hot";
5135 }; 4371 };
5136 }; 4372 };
5137 }; 4373 };
5138 4374
5139 cluster0-thermal { 4375 cluster0-thermal {
5140 polling-delay-passive 4376 polling-delay-passive = <250>;
>> 4377 polling-delay = <1000>;
5141 4378
5142 thermal-sensors = <&t 4379 thermal-sensors = <&tsens0 5>;
5143 4380
5144 trips { 4381 trips {
5145 cluster0_aler 4382 cluster0_alert0: trip-point0 {
5146 tempe 4383 temperature = <90000>;
5147 hyste 4384 hysteresis = <2000>;
5148 type 4385 type = "hot";
5149 }; 4386 };
5150 cluster0_crit !! 4387 cluster0_crit: cluster0_crit {
5151 tempe 4388 temperature = <110000>;
5152 hyste 4389 hysteresis = <2000>;
5153 type 4390 type = "critical";
5154 }; 4391 };
5155 }; 4392 };
5156 }; 4393 };
5157 4394
5158 cluster1-thermal { 4395 cluster1-thermal {
5159 polling-delay-passive 4396 polling-delay-passive = <250>;
>> 4397 polling-delay = <1000>;
5160 4398
5161 thermal-sensors = <&t 4399 thermal-sensors = <&tsens0 6>;
5162 4400
5163 trips { 4401 trips {
5164 cluster1_aler 4402 cluster1_alert0: trip-point0 {
5165 tempe 4403 temperature = <90000>;
5166 hyste 4404 hysteresis = <2000>;
5167 type 4405 type = "hot";
5168 }; 4406 };
5169 cluster1_crit !! 4407 cluster1_crit: cluster1_crit {
5170 tempe 4408 temperature = <110000>;
5171 hyste 4409 hysteresis = <2000>;
5172 type 4410 type = "critical";
5173 }; 4411 };
5174 }; 4412 };
5175 }; 4413 };
5176 4414
5177 gpu-top-thermal { 4415 gpu-top-thermal {
5178 polling-delay-passive 4416 polling-delay-passive = <250>;
>> 4417 polling-delay = <1000>;
5179 4418
5180 thermal-sensors = <&t 4419 thermal-sensors = <&tsens0 15>;
5181 4420
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4421 trips {
5190 gpu_top_alert !! 4422 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4423 temperature = <90000>;
5198 hyste !! 4424 hysteresis = <2000>;
5199 type 4425 type = "hot";
5200 }; 4426 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4427 };
5208 }; 4428 };
5209 4429
5210 aoss1-thermal { 4430 aoss1-thermal {
5211 polling-delay-passive 4431 polling-delay-passive = <250>;
>> 4432 polling-delay = <1000>;
5212 4433
5213 thermal-sensors = <&t 4434 thermal-sensors = <&tsens1 0>;
5214 4435
5215 trips { 4436 trips {
5216 aoss1_alert0: 4437 aoss1_alert0: trip-point0 {
5217 tempe 4438 temperature = <90000>;
5218 hyste 4439 hysteresis = <2000>;
5219 type 4440 type = "hot";
5220 }; 4441 };
5221 }; 4442 };
5222 }; 4443 };
5223 4444
5224 wlan-thermal { 4445 wlan-thermal {
5225 polling-delay-passive 4446 polling-delay-passive = <250>;
>> 4447 polling-delay = <1000>;
5226 4448
5227 thermal-sensors = <&t 4449 thermal-sensors = <&tsens1 1>;
5228 4450
5229 trips { 4451 trips {
5230 wlan_alert0: 4452 wlan_alert0: trip-point0 {
5231 tempe 4453 temperature = <90000>;
5232 hyste 4454 hysteresis = <2000>;
5233 type 4455 type = "hot";
5234 }; 4456 };
5235 }; 4457 };
5236 }; 4458 };
5237 4459
5238 video-thermal { 4460 video-thermal {
5239 polling-delay-passive 4461 polling-delay-passive = <250>;
>> 4462 polling-delay = <1000>;
5240 4463
5241 thermal-sensors = <&t 4464 thermal-sensors = <&tsens1 2>;
5242 4465
5243 trips { 4466 trips {
5244 video_alert0: 4467 video_alert0: trip-point0 {
5245 tempe 4468 temperature = <90000>;
5246 hyste 4469 hysteresis = <2000>;
5247 type 4470 type = "hot";
5248 }; 4471 };
5249 }; 4472 };
5250 }; 4473 };
5251 4474
5252 mem-thermal { 4475 mem-thermal {
5253 polling-delay-passive 4476 polling-delay-passive = <250>;
>> 4477 polling-delay = <1000>;
5254 4478
5255 thermal-sensors = <&t 4479 thermal-sensors = <&tsens1 3>;
5256 4480
5257 trips { 4481 trips {
5258 mem_alert0: t 4482 mem_alert0: trip-point0 {
5259 tempe 4483 temperature = <90000>;
5260 hyste 4484 hysteresis = <2000>;
5261 type 4485 type = "hot";
5262 }; 4486 };
5263 }; 4487 };
5264 }; 4488 };
5265 4489
5266 q6-hvx-thermal { 4490 q6-hvx-thermal {
5267 polling-delay-passive 4491 polling-delay-passive = <250>;
>> 4492 polling-delay = <1000>;
5268 4493
5269 thermal-sensors = <&t 4494 thermal-sensors = <&tsens1 4>;
5270 4495
5271 trips { 4496 trips {
5272 q6_hvx_alert0 4497 q6_hvx_alert0: trip-point0 {
5273 tempe 4498 temperature = <90000>;
5274 hyste 4499 hysteresis = <2000>;
5275 type 4500 type = "hot";
5276 }; 4501 };
5277 }; 4502 };
5278 }; 4503 };
5279 4504
5280 camera-thermal { 4505 camera-thermal {
5281 polling-delay-passive 4506 polling-delay-passive = <250>;
>> 4507 polling-delay = <1000>;
5282 4508
5283 thermal-sensors = <&t 4509 thermal-sensors = <&tsens1 5>;
5284 4510
5285 trips { 4511 trips {
5286 camera_alert0 4512 camera_alert0: trip-point0 {
5287 tempe 4513 temperature = <90000>;
5288 hyste 4514 hysteresis = <2000>;
5289 type 4515 type = "hot";
5290 }; 4516 };
5291 }; 4517 };
5292 }; 4518 };
5293 4519
5294 compute-thermal { 4520 compute-thermal {
5295 polling-delay-passive 4521 polling-delay-passive = <250>;
>> 4522 polling-delay = <1000>;
5296 4523
5297 thermal-sensors = <&t 4524 thermal-sensors = <&tsens1 6>;
5298 4525
5299 trips { 4526 trips {
5300 compute_alert 4527 compute_alert0: trip-point0 {
5301 tempe 4528 temperature = <90000>;
5302 hyste 4529 hysteresis = <2000>;
5303 type 4530 type = "hot";
5304 }; 4531 };
5305 }; 4532 };
5306 }; 4533 };
5307 4534
5308 modem-thermal { 4535 modem-thermal {
5309 polling-delay-passive 4536 polling-delay-passive = <250>;
>> 4537 polling-delay = <1000>;
5310 4538
5311 thermal-sensors = <&t 4539 thermal-sensors = <&tsens1 7>;
5312 4540
5313 trips { 4541 trips {
5314 modem_alert0: 4542 modem_alert0: trip-point0 {
5315 tempe 4543 temperature = <90000>;
5316 hyste 4544 hysteresis = <2000>;
5317 type 4545 type = "hot";
5318 }; 4546 };
5319 }; 4547 };
5320 }; 4548 };
5321 4549
5322 npu-thermal { 4550 npu-thermal {
5323 polling-delay-passive 4551 polling-delay-passive = <250>;
>> 4552 polling-delay = <1000>;
5324 4553
5325 thermal-sensors = <&t 4554 thermal-sensors = <&tsens1 8>;
5326 4555
5327 trips { 4556 trips {
5328 npu_alert0: t 4557 npu_alert0: trip-point0 {
5329 tempe 4558 temperature = <90000>;
5330 hyste 4559 hysteresis = <2000>;
5331 type 4560 type = "hot";
5332 }; 4561 };
5333 }; 4562 };
5334 }; 4563 };
5335 4564
5336 modem-vec-thermal { 4565 modem-vec-thermal {
5337 polling-delay-passive 4566 polling-delay-passive = <250>;
>> 4567 polling-delay = <1000>;
5338 4568
5339 thermal-sensors = <&t 4569 thermal-sensors = <&tsens1 9>;
5340 4570
5341 trips { 4571 trips {
5342 modem_vec_ale 4572 modem_vec_alert0: trip-point0 {
5343 tempe 4573 temperature = <90000>;
5344 hyste 4574 hysteresis = <2000>;
5345 type 4575 type = "hot";
5346 }; 4576 };
5347 }; 4577 };
5348 }; 4578 };
5349 4579
5350 modem-scl-thermal { 4580 modem-scl-thermal {
5351 polling-delay-passive 4581 polling-delay-passive = <250>;
>> 4582 polling-delay = <1000>;
5352 4583
5353 thermal-sensors = <&t 4584 thermal-sensors = <&tsens1 10>;
5354 4585
5355 trips { 4586 trips {
5356 modem_scl_ale 4587 modem_scl_alert0: trip-point0 {
5357 tempe 4588 temperature = <90000>;
5358 hyste 4589 hysteresis = <2000>;
5359 type 4590 type = "hot";
5360 }; 4591 };
5361 }; 4592 };
5362 }; 4593 };
5363 4594
5364 gpu-bottom-thermal { 4595 gpu-bottom-thermal {
5365 polling-delay-passive 4596 polling-delay-passive = <250>;
>> 4597 polling-delay = <1000>;
5366 4598
5367 thermal-sensors = <&t 4599 thermal-sensors = <&tsens1 11>;
5368 4600
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 4601 trips {
5377 gpu_bottom_al !! 4602 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 4603 temperature = <90000>;
5385 hyste !! 4604 hysteresis = <2000>;
5386 type 4605 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 4606 };
5394 }; 4607 };
5395 }; 4608 };
5396 }; 4609 };
5397 }; 4610 };
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