1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 15 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
22 17
23 / { 18 / {
24 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
25 20
26 #address-cells = <2>; 21 #address-cells = <2>;
27 #size-cells = <2>; 22 #size-cells = <2>;
28 23
29 chosen { }; 24 chosen { };
30 25
31 clocks { 26 clocks {
32 xo_board: xo-board { 27 xo_board: xo-board {
33 compatible = "fixed-cl 28 compatible = "fixed-clock";
34 #clock-cells = <0>; 29 #clock-cells = <0>;
35 clock-frequency = <384 30 clock-frequency = <38400000>;
36 clock-output-names = " 31 clock-output-names = "xo_board";
37 }; 32 };
38 33
39 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 35 compatible = "fixed-clock";
41 #clock-cells = <0>; 36 #clock-cells = <0>;
42 clock-frequency = <327 37 clock-frequency = <32764>;
43 clock-output-names = " 38 clock-output-names = "sleep_clk";
44 }; 39 };
45 }; 40 };
46 41
47 cpus { 42 cpus {
48 #address-cells = <2>; 43 #address-cells = <2>;
49 #size-cells = <0>; 44 #size-cells = <0>;
50 45
51 CPU0: cpu@0 { 46 CPU0: cpu@0 {
52 device_type = "cpu"; 47 device_type = "cpu";
53 compatible = "qcom,kry 48 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 50 enable-method = "psci";
57 capacity-dmips-mhz = < 51 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 52 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 53 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 54 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 55 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 58 power-domains = <&CPU_PD0>;
65 power-domain-names = " 59 power-domain-names = "psci";
66 #cooling-cells = <2>; 60 #cooling-cells = <2>;
67 L2_0: l2-cache { 61 L2_0: l2-cache {
68 compatible = " 62 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 63 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 64 L3_0: l3-cache {
73 compat !! 65 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 66 };
77 }; 67 };
78 }; 68 };
79 69
80 CPU1: cpu@100 { 70 CPU1: cpu@100 {
81 device_type = "cpu"; 71 device_type = "cpu";
82 compatible = "qcom,kry 72 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 73 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 74 enable-method = "psci";
86 capacity-dmips-mhz = < 75 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 76 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 77 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 79 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 82 power-domains = <&CPU_PD1>;
94 power-domain-names = " 83 power-domain-names = "psci";
95 #cooling-cells = <2>; 84 #cooling-cells = <2>;
96 L2_100: l2-cache { 85 L2_100: l2-cache {
97 compatible = " 86 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 87 next-level-cache = <&L3_0>;
101 }; 88 };
>> 89
102 }; 90 };
103 91
104 CPU2: cpu@200 { 92 CPU2: cpu@200 {
105 device_type = "cpu"; 93 device_type = "cpu";
106 compatible = "qcom,kry 94 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 95 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 96 enable-method = "psci";
110 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 98 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 99 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 101 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 104 power-domains = <&CPU_PD2>;
118 power-domain-names = " 105 power-domain-names = "psci";
119 #cooling-cells = <2>; 106 #cooling-cells = <2>;
120 L2_200: l2-cache { 107 L2_200: l2-cache {
121 compatible = " 108 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 109 next-level-cache = <&L3_0>;
125 }; 110 };
126 }; 111 };
127 112
128 CPU3: cpu@300 { 113 CPU3: cpu@300 {
129 device_type = "cpu"; 114 device_type = "cpu";
130 compatible = "qcom,kry 115 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 116 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 117 enable-method = "psci";
134 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 119 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 120 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 122 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 125 power-domains = <&CPU_PD3>;
142 power-domain-names = " 126 power-domain-names = "psci";
143 #cooling-cells = <2>; 127 #cooling-cells = <2>;
144 L2_300: l2-cache { 128 L2_300: l2-cache {
145 compatible = " 129 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 130 next-level-cache = <&L3_0>;
149 }; 131 };
150 }; 132 };
151 133
152 CPU4: cpu@400 { 134 CPU4: cpu@400 {
153 device_type = "cpu"; 135 device_type = "cpu";
154 compatible = "qcom,kry 136 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 137 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 138 enable-method = "psci";
158 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 140 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 141 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 143 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 146 power-domains = <&CPU_PD4>;
166 power-domain-names = " 147 power-domain-names = "psci";
167 #cooling-cells = <2>; 148 #cooling-cells = <2>;
168 L2_400: l2-cache { 149 L2_400: l2-cache {
169 compatible = " 150 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 151 next-level-cache = <&L3_0>;
173 }; 152 };
174 }; 153 };
175 154
176 CPU5: cpu@500 { 155 CPU5: cpu@500 {
177 device_type = "cpu"; 156 device_type = "cpu";
178 compatible = "qcom,kry 157 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 158 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 159 enable-method = "psci";
182 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 161 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 162 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 163 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 164 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 167 power-domains = <&CPU_PD5>;
190 power-domain-names = " 168 power-domain-names = "psci";
191 #cooling-cells = <2>; 169 #cooling-cells = <2>;
192 L2_500: l2-cache { 170 L2_500: l2-cache {
193 compatible = " 171 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 172 next-level-cache = <&L3_0>;
197 }; 173 };
198 }; 174 };
199 175
200 CPU6: cpu@600 { 176 CPU6: cpu@600 {
201 device_type = "cpu"; 177 device_type = "cpu";
202 compatible = "qcom,kry 178 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 179 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 180 enable-method = "psci";
206 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 182 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 183 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 185 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 188 power-domains = <&CPU_PD6>;
214 power-domain-names = " 189 power-domain-names = "psci";
215 #cooling-cells = <2>; 190 #cooling-cells = <2>;
216 L2_600: l2-cache { 191 L2_600: l2-cache {
217 compatible = " 192 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 193 next-level-cache = <&L3_0>;
221 }; 194 };
222 }; 195 };
223 196
224 CPU7: cpu@700 { 197 CPU7: cpu@700 {
225 device_type = "cpu"; 198 device_type = "cpu";
226 compatible = "qcom,kry 199 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 200 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 201 enable-method = "psci";
230 capacity-dmips-mhz = < 202 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 203 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 204 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 205 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 206 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 209 power-domains = <&CPU_PD7>;
238 power-domain-names = " 210 power-domain-names = "psci";
239 #cooling-cells = <2>; 211 #cooling-cells = <2>;
240 L2_700: l2-cache { 212 L2_700: l2-cache {
241 compatible = " 213 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 214 next-level-cache = <&L3_0>;
245 }; 215 };
246 }; 216 };
247 217
248 cpu-map { 218 cpu-map {
249 cluster0 { 219 cluster0 {
250 core0 { 220 core0 {
251 cpu = 221 cpu = <&CPU0>;
252 }; 222 };
253 223
254 core1 { 224 core1 {
255 cpu = 225 cpu = <&CPU1>;
256 }; 226 };
257 227
258 core2 { 228 core2 {
259 cpu = 229 cpu = <&CPU2>;
260 }; 230 };
261 231
262 core3 { 232 core3 {
263 cpu = 233 cpu = <&CPU3>;
264 }; 234 };
265 235
266 core4 { 236 core4 {
267 cpu = 237 cpu = <&CPU4>;
268 }; 238 };
269 239
270 core5 { 240 core5 {
271 cpu = 241 cpu = <&CPU5>;
272 }; 242 };
273 243
274 core6 { 244 core6 {
275 cpu = 245 cpu = <&CPU6>;
276 }; 246 };
277 247
278 core7 { 248 core7 {
279 cpu = 249 cpu = <&CPU7>;
280 }; 250 };
281 }; 251 };
282 }; 252 };
283 253
284 idle-states { 254 idle-states {
285 entry-method = "psci"; 255 entry-method = "psci";
286 256
287 LITTLE_CPU_SLEEP_0: cp 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 258 compatible = "arm,idle-state";
289 idle-state-nam 259 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 260 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 261 entry-latency-us = <355>;
292 exit-latency-u 262 exit-latency-us = <909>;
293 min-residency- 263 min-residency-us = <3934>;
294 local-timer-st 264 local-timer-stop;
295 }; 265 };
296 266
297 BIG_CPU_SLEEP_0: cpu-s 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 268 compatible = "arm,idle-state";
299 idle-state-nam 269 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 270 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 271 entry-latency-us = <241>;
302 exit-latency-u 272 exit-latency-us = <1461>;
303 min-residency- 273 min-residency-us = <4488>;
304 local-timer-st 274 local-timer-stop;
305 }; 275 };
306 }; 276 };
307 277
308 domain-idle-states { 278 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 279 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 280 compatible = "domain-idle-state";
>> 281 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 282 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 283 entry-latency-us = <3263>;
313 exit-latency-u 284 exit-latency-us = <6562>;
314 min-residency- 285 min-residency-us = <9987>;
>> 286 local-timer-stop;
315 }; 287 };
316 }; 288 };
317 }; 289 };
318 290
319 cpu0_opp_table: opp-table-cpu0 { !! 291 cpu0_opp_table: cpu0_opp_table {
320 compatible = "operating-points 292 compatible = "operating-points-v2";
321 opp-shared; 293 opp-shared;
322 294
323 cpu0_opp1: opp-300000000 { 295 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 296 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 297 opp-peak-kBps = <800000 9600000>;
326 }; 298 };
327 299
328 cpu0_opp2: opp-403200000 { 300 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 301 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 302 opp-peak-kBps = <800000 9600000>;
331 }; 303 };
332 304
333 cpu0_opp3: opp-499200000 { 305 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 306 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 307 opp-peak-kBps = <800000 12902400>;
336 }; 308 };
337 309
338 cpu0_opp4: opp-576000000 { 310 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 311 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 312 opp-peak-kBps = <800000 12902400>;
341 }; 313 };
342 314
343 cpu0_opp5: opp-672000000 { 315 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 316 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 317 opp-peak-kBps = <800000 15974400>;
346 }; 318 };
347 319
348 cpu0_opp6: opp-768000000 { 320 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 321 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 322 opp-peak-kBps = <1804000 19660800>;
351 }; 323 };
352 324
353 cpu0_opp7: opp-844800000 { 325 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 326 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 327 opp-peak-kBps = <1804000 19660800>;
356 }; 328 };
357 329
358 cpu0_opp8: opp-940800000 { 330 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 331 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 332 opp-peak-kBps = <1804000 22732800>;
361 }; 333 };
362 334
363 cpu0_opp9: opp-1036800000 { 335 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 336 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 337 opp-peak-kBps = <1804000 22732800>;
366 }; 338 };
367 339
368 cpu0_opp10: opp-1113600000 { 340 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 341 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 342 opp-peak-kBps = <2188000 25804800>;
371 }; 343 };
372 344
373 cpu0_opp11: opp-1209600000 { 345 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 346 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 347 opp-peak-kBps = <2188000 31948800>;
376 }; 348 };
377 349
378 cpu0_opp12: opp-1305600000 { 350 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 351 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 352 opp-peak-kBps = <3072000 31948800>;
381 }; 353 };
382 354
383 cpu0_opp13: opp-1382400000 { 355 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 356 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 357 opp-peak-kBps = <3072000 31948800>;
386 }; 358 };
387 359
388 cpu0_opp14: opp-1478400000 { 360 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 361 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 362 opp-peak-kBps = <3072000 31948800>;
391 }; 363 };
392 364
393 cpu0_opp15: opp-1555200000 { 365 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 366 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 367 opp-peak-kBps = <3072000 40550400>;
396 }; 368 };
397 369
398 cpu0_opp16: opp-1632000000 { 370 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 371 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 372 opp-peak-kBps = <3072000 40550400>;
401 }; 373 };
402 374
403 cpu0_opp17: opp-1708800000 { 375 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 376 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 377 opp-peak-kBps = <3072000 43008000>;
406 }; 378 };
407 379
408 cpu0_opp18: opp-1785600000 { 380 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 381 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 382 opp-peak-kBps = <3072000 43008000>;
411 }; 383 };
412 }; 384 };
413 385
414 cpu4_opp_table: opp-table-cpu4 { !! 386 cpu4_opp_table: cpu4_opp_table {
415 compatible = "operating-points 387 compatible = "operating-points-v2";
416 opp-shared; 388 opp-shared;
417 389
418 cpu4_opp1: opp-710400000 { 390 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 391 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 392 opp-peak-kBps = <1804000 15974400>;
421 }; 393 };
422 394
423 cpu4_opp2: opp-825600000 { 395 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 396 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 397 opp-peak-kBps = <2188000 19660800>;
426 }; 398 };
427 399
428 cpu4_opp3: opp-940800000 { 400 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 401 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 402 opp-peak-kBps = <2188000 22732800>;
431 }; 403 };
432 404
433 cpu4_opp4: opp-1056000000 { 405 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 406 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 407 opp-peak-kBps = <3072000 25804800>;
436 }; 408 };
437 409
438 cpu4_opp5: opp-1171200000 { 410 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 411 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 412 opp-peak-kBps = <3072000 31948800>;
441 }; 413 };
442 414
443 cpu4_opp6: opp-1286400000 { 415 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 416 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 417 opp-peak-kBps = <4068000 31948800>;
446 }; 418 };
447 419
448 cpu4_opp7: opp-1401600000 { 420 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 421 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 422 opp-peak-kBps = <4068000 31948800>;
451 }; 423 };
452 424
453 cpu4_opp8: opp-1497600000 { 425 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 426 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 427 opp-peak-kBps = <4068000 40550400>;
456 }; 428 };
457 429
458 cpu4_opp9: opp-1612800000 { 430 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 431 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 432 opp-peak-kBps = <4068000 40550400>;
461 }; 433 };
462 434
463 cpu4_opp10: opp-1708800000 { 435 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 436 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 437 opp-peak-kBps = <4068000 43008000>;
466 }; 438 };
467 439
468 cpu4_opp11: opp-1804800000 { 440 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 441 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 442 opp-peak-kBps = <6220000 43008000>;
471 }; 443 };
472 444
473 cpu4_opp12: opp-1920000000 { 445 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 446 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 447 opp-peak-kBps = <6220000 49152000>;
476 }; 448 };
477 449
478 cpu4_opp13: opp-2016000000 { 450 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 451 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 452 opp-peak-kBps = <7216000 49152000>;
481 }; 453 };
482 454
483 cpu4_opp14: opp-2131200000 { 455 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 456 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 457 opp-peak-kBps = <8368000 49152000>;
486 }; 458 };
487 459
488 cpu4_opp15: opp-2227200000 { 460 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 461 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 462 opp-peak-kBps = <8368000 51609600>;
491 }; 463 };
492 464
493 cpu4_opp16: opp-2323200000 { 465 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 466 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 467 opp-peak-kBps = <8368000 51609600>;
496 }; 468 };
497 469
498 cpu4_opp17: opp-2419200000 { 470 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 471 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 472 opp-peak-kBps = <8368000 51609600>;
501 }; 473 };
502 }; 474 };
503 475
504 cpu7_opp_table: opp-table-cpu7 { !! 476 cpu7_opp_table: cpu7_opp_table {
505 compatible = "operating-points 477 compatible = "operating-points-v2";
506 opp-shared; 478 opp-shared;
507 479
508 cpu7_opp1: opp-825600000 { 480 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 481 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 19660800>;
511 }; 483 };
512 484
513 cpu7_opp2: opp-940800000 { 485 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 486 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 487 opp-peak-kBps = <2188000 22732800>;
516 }; 488 };
517 489
518 cpu7_opp3: opp-1056000000 { 490 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 491 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 25804800>;
521 }; 493 };
522 494
523 cpu7_opp4: opp-1171200000 { 495 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 496 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 497 opp-peak-kBps = <3072000 31948800>;
526 }; 498 };
527 499
528 cpu7_opp5: opp-1286400000 { 500 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 501 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 31948800>;
531 }; 503 };
532 504
533 cpu7_opp6: opp-1401600000 { 505 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 506 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 31948800>;
536 }; 508 };
537 509
538 cpu7_opp7: opp-1497600000 { 510 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 511 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 40550400>;
541 }; 513 };
542 514
543 cpu7_opp8: opp-1612800000 { 515 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 516 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 517 opp-peak-kBps = <4068000 40550400>;
546 }; 518 };
547 519
548 cpu7_opp9: opp-1708800000 { 520 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 521 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 522 opp-peak-kBps = <4068000 43008000>;
551 }; 523 };
552 524
553 cpu7_opp10: opp-1804800000 { 525 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 526 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 527 opp-peak-kBps = <6220000 43008000>;
556 }; 528 };
557 529
558 cpu7_opp11: opp-1920000000 { 530 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 531 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 532 opp-peak-kBps = <6220000 49152000>;
561 }; 533 };
562 534
563 cpu7_opp12: opp-2016000000 { 535 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 536 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 537 opp-peak-kBps = <7216000 49152000>;
566 }; 538 };
567 539
568 cpu7_opp13: opp-2131200000 { 540 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 541 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 542 opp-peak-kBps = <8368000 49152000>;
571 }; 543 };
572 544
573 cpu7_opp14: opp-2227200000 { 545 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 546 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 547 opp-peak-kBps = <8368000 51609600>;
576 }; 548 };
577 549
578 cpu7_opp15: opp-2323200000 { 550 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 551 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 552 opp-peak-kBps = <8368000 51609600>;
581 }; 553 };
582 554
583 cpu7_opp16: opp-2419200000 { 555 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 556 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
586 }; 558 };
587 559
588 cpu7_opp17: opp-2534400000 { 560 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 561 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
591 }; 563 };
592 564
593 cpu7_opp18: opp-2649600000 { 565 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 566 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 567 opp-peak-kBps = <8368000 51609600>;
596 }; 568 };
597 569
598 cpu7_opp19: opp-2745600000 { 570 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 571 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 572 opp-peak-kBps = <8368000 51609600>;
601 }; 573 };
602 574
603 cpu7_opp20: opp-2841600000 { 575 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 576 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 577 opp-peak-kBps = <8368000 51609600>;
606 }; 578 };
607 }; 579 };
608 580
609 firmware { 581 firmware {
610 scm: scm { 582 scm: scm {
611 compatible = "qcom,scm 583 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 584 #reset-cells = <1>;
613 }; 585 };
614 }; 586 };
615 587
>> 588 tcsr_mutex: hwlock {
>> 589 compatible = "qcom,tcsr-mutex";
>> 590 syscon = <&tcsr_mutex_regs 0 0x1000>;
>> 591 #hwlock-cells = <1>;
>> 592 };
>> 593
616 memory@80000000 { 594 memory@80000000 {
617 device_type = "memory"; 595 device_type = "memory";
618 /* We expect the bootloader to 596 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 597 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 598 };
621 599
622 pmu { 600 pmu {
623 compatible = "arm,armv8-pmuv3" 601 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 602 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 603 };
626 604
627 psci { 605 psci {
628 compatible = "arm,psci-1.0"; 606 compatible = "arm,psci-1.0";
629 method = "smc"; 607 method = "smc";
630 608
631 CPU_PD0: power-domain-cpu0 { !! 609 CPU_PD0: cpu0 {
632 #power-domain-cells = 610 #power-domain-cells = <0>;
633 power-domains = <&CLUS 611 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 613 };
636 614
637 CPU_PD1: power-domain-cpu1 { !! 615 CPU_PD1: cpu1 {
638 #power-domain-cells = 616 #power-domain-cells = <0>;
639 power-domains = <&CLUS 617 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 619 };
642 620
643 CPU_PD2: power-domain-cpu2 { !! 621 CPU_PD2: cpu2 {
644 #power-domain-cells = 622 #power-domain-cells = <0>;
645 power-domains = <&CLUS 623 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 625 };
648 626
649 CPU_PD3: power-domain-cpu3 { !! 627 CPU_PD3: cpu3 {
650 #power-domain-cells = 628 #power-domain-cells = <0>;
651 power-domains = <&CLUS 629 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 631 };
654 632
655 CPU_PD4: power-domain-cpu4 { !! 633 CPU_PD4: cpu4 {
656 #power-domain-cells = 634 #power-domain-cells = <0>;
657 power-domains = <&CLUS 635 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 636 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 637 };
660 638
661 CPU_PD5: power-domain-cpu5 { !! 639 CPU_PD5: cpu5 {
662 #power-domain-cells = 640 #power-domain-cells = <0>;
663 power-domains = <&CLUS 641 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 642 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 643 };
666 644
667 CPU_PD6: power-domain-cpu6 { !! 645 CPU_PD6: cpu6 {
668 #power-domain-cells = 646 #power-domain-cells = <0>;
669 power-domains = <&CLUS 647 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 648 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 649 };
672 650
673 CPU_PD7: power-domain-cpu7 { !! 651 CPU_PD7: cpu7 {
674 #power-domain-cells = 652 #power-domain-cells = <0>;
675 power-domains = <&CLUS 653 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 654 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 655 };
678 656
679 CLUSTER_PD: power-domain-cpu-c !! 657 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 658 #power-domain-cells = <0>;
681 domain-idle-states = < 659 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 660 };
683 }; 661 };
684 662
685 reserved-memory { 663 reserved-memory {
686 #address-cells = <2>; 664 #address-cells = <2>;
687 #size-cells = <2>; 665 #size-cells = <2>;
688 ranges; 666 ranges;
689 667
690 hyp_mem: memory@85700000 { 668 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 669 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 670 no-map;
693 }; 671 };
694 672
695 xbl_mem: memory@85d00000 { 673 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 674 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 675 no-map;
698 }; 676 };
699 677
700 aop_mem: memory@85f00000 { 678 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 679 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 680 no-map;
703 }; 681 };
704 682
705 aop_cmd_db: memory@85f20000 { 683 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 684 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 685 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 686 no-map;
709 }; 687 };
710 688
711 smem_mem: memory@86000000 { 689 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 690 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 691 no-map;
714 }; 692 };
715 693
716 tz_mem: memory@86200000 { 694 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 695 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 696 no-map;
719 }; 697 };
720 698
721 rmtfs_mem: memory@89b00000 { 699 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 700 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 701 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 702 no-map;
725 703
726 qcom,client-id = <1>; 704 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 705 qcom,vmid = <15>;
728 }; 706 };
729 707
730 camera_mem: memory@8b700000 { 708 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 709 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 710 no-map;
733 }; 711 };
734 712
735 wlan_mem: memory@8bc00000 { 713 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 714 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 715 no-map;
738 }; 716 };
739 717
740 npu_mem: memory@8bd80000 { 718 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 719 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 720 no-map;
743 }; 721 };
744 722
745 adsp_mem: memory@8be00000 { 723 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 724 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 725 no-map;
748 }; 726 };
749 727
750 mpss_mem: memory@8d800000 { 728 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 729 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 730 no-map;
753 }; 731 };
754 732
755 venus_mem: memory@96e00000 { 733 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 734 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 735 no-map;
758 }; 736 };
759 737
760 slpi_mem: memory@97300000 { 738 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 739 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 740 no-map;
763 }; 741 };
764 742
765 ipa_fw_mem: memory@98700000 { 743 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 744 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 745 no-map;
768 }; 746 };
769 747
770 ipa_gsi_mem: memory@98710000 { 748 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 749 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 750 no-map;
773 }; 751 };
774 752
775 gpu_mem: memory@98715000 { 753 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 754 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 755 no-map;
778 }; 756 };
779 757
780 spss_mem: memory@98800000 { 758 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 759 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 760 no-map;
783 }; 761 };
784 762
785 cdsp_mem: memory@98900000 { 763 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 764 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 765 no-map;
788 }; 766 };
789 767
790 qseecom_mem: memory@9e400000 { 768 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 769 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 770 no-map;
793 }; 771 };
794 }; 772 };
795 773
796 smem { 774 smem {
797 compatible = "qcom,smem"; 775 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 776 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 777 hwlocks = <&tcsr_mutex 3>;
800 }; 778 };
801 779
802 smp2p-cdsp { 780 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 781 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 782 qcom,smem = <94>, <432>;
805 783
806 interrupts = <GIC_SPI 576 IRQ_ 784 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 785
808 mboxes = <&apss_shared 6>; 786 mboxes = <&apss_shared 6>;
809 787
810 qcom,local-pid = <0>; 788 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 789 qcom,remote-pid = <5>;
812 790
813 cdsp_smp2p_out: master-kernel 791 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 792 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 793 #qcom,smem-state-cells = <1>;
816 }; 794 };
817 795
818 cdsp_smp2p_in: slave-kernel { 796 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 797 qcom,entry-name = "slave-kernel";
820 798
821 interrupt-controller; 799 interrupt-controller;
822 #interrupt-cells = <2> 800 #interrupt-cells = <2>;
823 }; 801 };
824 }; 802 };
825 803
826 smp2p-lpass { 804 smp2p-lpass {
827 compatible = "qcom,smp2p"; 805 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 806 qcom,smem = <443>, <429>;
829 807
830 interrupts = <GIC_SPI 158 IRQ_ 808 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 809
832 mboxes = <&apss_shared 10>; 810 mboxes = <&apss_shared 10>;
833 811
834 qcom,local-pid = <0>; 812 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 813 qcom,remote-pid = <2>;
836 814
837 adsp_smp2p_out: master-kernel 815 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 816 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 817 #qcom,smem-state-cells = <1>;
840 }; 818 };
841 819
842 adsp_smp2p_in: slave-kernel { 820 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 821 qcom,entry-name = "slave-kernel";
844 822
845 interrupt-controller; 823 interrupt-controller;
846 #interrupt-cells = <2> 824 #interrupt-cells = <2>;
847 }; 825 };
848 }; 826 };
849 827
850 smp2p-mpss { 828 smp2p-mpss {
851 compatible = "qcom,smp2p"; 829 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 830 qcom,smem = <435>, <428>;
853 831
854 interrupts = <GIC_SPI 451 IRQ_ 832 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 833
856 mboxes = <&apss_shared 14>; 834 mboxes = <&apss_shared 14>;
857 835
858 qcom,local-pid = <0>; 836 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 837 qcom,remote-pid = <1>;
860 838
861 modem_smp2p_out: master-kernel 839 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 840 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 841 #qcom,smem-state-cells = <1>;
864 }; 842 };
865 843
866 modem_smp2p_in: slave-kernel { 844 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 845 qcom,entry-name = "slave-kernel";
868 846
869 interrupt-controller; 847 interrupt-controller;
870 #interrupt-cells = <2> 848 #interrupt-cells = <2>;
871 }; 849 };
872 }; 850 };
873 851
874 smp2p-slpi { 852 smp2p-slpi {
875 compatible = "qcom,smp2p"; 853 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 854 qcom,smem = <481>, <430>;
877 855
878 interrupts = <GIC_SPI 172 IRQ_ 856 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 857
880 mboxes = <&apss_shared 26>; 858 mboxes = <&apss_shared 26>;
881 859
882 qcom,local-pid = <0>; 860 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 861 qcom,remote-pid = <3>;
884 862
885 slpi_smp2p_out: master-kernel 863 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 864 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 865 #qcom,smem-state-cells = <1>;
888 }; 866 };
889 867
890 slpi_smp2p_in: slave-kernel { 868 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 869 qcom,entry-name = "slave-kernel";
892 870
893 interrupt-controller; 871 interrupt-controller;
894 #interrupt-cells = <2> 872 #interrupt-cells = <2>;
895 }; 873 };
896 }; 874 };
897 875
898 soc: soc@0 { 876 soc: soc@0 {
899 #address-cells = <2>; 877 #address-cells = <2>;
900 #size-cells = <2>; 878 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 879 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 880 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 881 compatible = "simple-bus";
904 882
905 gcc: clock-controller@100000 { 883 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 884 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 885 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 886 #clock-cells = <1>;
909 #reset-cells = <1>; 887 #reset-cells = <1>;
910 #power-domain-cells = 888 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 889 clock-names = "bi_tcxo",
912 "sleep_c 890 "sleep_clk";
913 clocks = <&rpmhcc RPMH 891 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 892 <&sleep_clk>;
915 }; 893 };
916 894
917 gpi_dma0: dma-controller@80000 895 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 !! 896 compatible = "qcom,sm8150-gpi-dma";
919 reg = <0 0x00800000 0 !! 897 reg = <0 0x800000 0 0x60000>;
920 interrupts = <GIC_SPI 898 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 899 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 900 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 901 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 902 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 903 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 904 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 905 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 906 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 907 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 908 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 909 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 910 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 911 dma-channels = <13>;
934 dma-channel-mask = <0x 912 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 913 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 914 #dma-cells = <3>;
937 status = "disabled"; 915 status = "disabled";
938 }; 916 };
939 917
940 ethernet: ethernet@20000 { 918 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 919 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 920 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 921 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 922 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 923 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 924 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 925 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 926 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 927 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 928 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 929 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 930 interrupt-names = "macirq", "eth_lpi";
953 931
954 power-domains = <&gcc 932 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 933 resets = <&gcc GCC_EMAC_BCR>;
956 934
957 iommus = <&apps_smmu 0 !! 935 iommus = <&apps_smmu 0x3C0 0x0>;
958 936
959 snps,tso; 937 snps,tso;
960 rx-fifo-depth = <4096> 938 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 939 tx-fifo-depth = <4096>;
962 940
963 status = "disabled"; 941 status = "disabled";
964 }; 942 };
965 943
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 944
978 qupv3_id_0: geniqup@8c0000 { 945 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 946 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 947 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 948 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 949 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 950 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 951 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 952 #address-cells = <2>;
986 #size-cells = <2>; 953 #size-cells = <2>;
987 ranges; 954 ranges;
988 status = "disabled"; 955 status = "disabled";
989 956
990 i2c0: i2c@880000 { 957 i2c0: i2c@880000 {
991 compatible = " 958 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 959 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 960 clock-names = "se";
994 clocks = <&gcc 961 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 962 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 963 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 964 dma-names = "tx", "rx";
998 pinctrl-names 965 pinctrl-names = "default";
999 pinctrl-0 = <& 966 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 967 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 968 #address-cells = <1>;
1002 #size-cells = 969 #size-cells = <0>;
1003 status = "dis 970 status = "disabled";
1004 }; 971 };
1005 972
1006 spi0: spi@880000 { 973 spi0: spi@880000 {
1007 compatible = 974 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 !! 975 reg = <0 0x880000 0 0x4000>;
1009 reg-names = " 976 reg-names = "se";
1010 clock-names = 977 clock-names = "se";
1011 clocks = <&gc 978 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 979 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 980 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 981 dma-names = "tx", "rx";
1015 pinctrl-names 982 pinctrl-names = "default";
1016 pinctrl-0 = < 983 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 984 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 985 spi-max-frequency = <50000000>;
1019 #address-cell 986 #address-cells = <1>;
1020 #size-cells = 987 #size-cells = <0>;
1021 status = "dis 988 status = "disabled";
1022 }; 989 };
1023 990
1024 i2c1: i2c@884000 { 991 i2c1: i2c@884000 {
1025 compatible = 992 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 993 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 994 clock-names = "se";
1028 clocks = <&gc 995 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 996 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 997 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 998 dma-names = "tx", "rx";
1032 pinctrl-names 999 pinctrl-names = "default";
1033 pinctrl-0 = < 1000 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 1001 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 1002 #address-cells = <1>;
1036 #size-cells = 1003 #size-cells = <0>;
1037 status = "dis 1004 status = "disabled";
1038 }; 1005 };
1039 1006
1040 spi1: spi@884000 { 1007 spi1: spi@884000 {
1041 compatible = 1008 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 !! 1009 reg = <0 0x884000 0 0x4000>;
1043 reg-names = " 1010 reg-names = "se";
1044 clock-names = 1011 clock-names = "se";
1045 clocks = <&gc 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1013 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1014 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1015 dma-names = "tx", "rx";
1049 pinctrl-names 1016 pinctrl-names = "default";
1050 pinctrl-0 = < 1017 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1018 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1019 spi-max-frequency = <50000000>;
1053 #address-cell 1020 #address-cells = <1>;
1054 #size-cells = 1021 #size-cells = <0>;
1055 status = "dis 1022 status = "disabled";
1056 }; 1023 };
1057 1024
1058 i2c2: i2c@888000 { 1025 i2c2: i2c@888000 {
1059 compatible = 1026 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1027 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1028 clock-names = "se";
1062 clocks = <&gc 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1030 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1031 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1032 dma-names = "tx", "rx";
1066 pinctrl-names 1033 pinctrl-names = "default";
1067 pinctrl-0 = < 1034 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1035 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1036 #address-cells = <1>;
1070 #size-cells = 1037 #size-cells = <0>;
1071 status = "dis 1038 status = "disabled";
1072 }; 1039 };
1073 1040
1074 spi2: spi@888000 { 1041 spi2: spi@888000 {
1075 compatible = 1042 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 !! 1043 reg = <0 0x888000 0 0x4000>;
1077 reg-names = " 1044 reg-names = "se";
1078 clock-names = 1045 clock-names = "se";
1079 clocks = <&gc 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1047 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1048 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1049 dma-names = "tx", "rx";
1083 pinctrl-names 1050 pinctrl-names = "default";
1084 pinctrl-0 = < 1051 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1052 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1053 spi-max-frequency = <50000000>;
1087 #address-cell 1054 #address-cells = <1>;
1088 #size-cells = 1055 #size-cells = <0>;
1089 status = "dis 1056 status = "disabled";
1090 }; 1057 };
1091 1058
1092 i2c3: i2c@88c000 { 1059 i2c3: i2c@88c000 {
1093 compatible = 1060 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1061 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1062 clock-names = "se";
1096 clocks = <&gc 1063 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1064 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1065 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1066 dma-names = "tx", "rx";
1100 pinctrl-names 1067 pinctrl-names = "default";
1101 pinctrl-0 = < 1068 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1069 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1070 #address-cells = <1>;
1104 #size-cells = 1071 #size-cells = <0>;
1105 status = "dis 1072 status = "disabled";
1106 }; 1073 };
1107 1074
1108 spi3: spi@88c000 { 1075 spi3: spi@88c000 {
1109 compatible = 1076 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 !! 1077 reg = <0 0x88c000 0 0x4000>;
1111 reg-names = " 1078 reg-names = "se";
1112 clock-names = 1079 clock-names = "se";
1113 clocks = <&gc 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1081 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1082 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1083 dma-names = "tx", "rx";
1117 pinctrl-names 1084 pinctrl-names = "default";
1118 pinctrl-0 = < 1085 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1086 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1087 spi-max-frequency = <50000000>;
1121 #address-cell 1088 #address-cells = <1>;
1122 #size-cells = 1089 #size-cells = <0>;
1123 status = "dis 1090 status = "disabled";
1124 }; 1091 };
1125 1092
1126 i2c4: i2c@890000 { 1093 i2c4: i2c@890000 {
1127 compatible = 1094 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1095 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1096 clock-names = "se";
1130 clocks = <&gc 1097 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1098 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1099 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1100 dma-names = "tx", "rx";
1134 pinctrl-names 1101 pinctrl-names = "default";
1135 pinctrl-0 = < 1102 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1103 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1104 #address-cells = <1>;
1138 #size-cells = 1105 #size-cells = <0>;
1139 status = "dis 1106 status = "disabled";
1140 }; 1107 };
1141 1108
1142 spi4: spi@890000 { 1109 spi4: spi@890000 {
1143 compatible = 1110 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 !! 1111 reg = <0 0x890000 0 0x4000>;
1145 reg-names = " 1112 reg-names = "se";
1146 clock-names = 1113 clock-names = "se";
1147 clocks = <&gc 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1115 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1116 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1117 dma-names = "tx", "rx";
1151 pinctrl-names 1118 pinctrl-names = "default";
1152 pinctrl-0 = < 1119 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1120 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1121 spi-max-frequency = <50000000>;
1155 #address-cell 1122 #address-cells = <1>;
1156 #size-cells = 1123 #size-cells = <0>;
1157 status = "dis 1124 status = "disabled";
1158 }; 1125 };
1159 1126
1160 i2c5: i2c@894000 { 1127 i2c5: i2c@894000 {
1161 compatible = 1128 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1129 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1130 clock-names = "se";
1164 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1132 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1133 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1134 dma-names = "tx", "rx";
1168 pinctrl-names 1135 pinctrl-names = "default";
1169 pinctrl-0 = < 1136 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1137 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1138 #address-cells = <1>;
1172 #size-cells = 1139 #size-cells = <0>;
1173 status = "dis 1140 status = "disabled";
1174 }; 1141 };
1175 1142
1176 spi5: spi@894000 { 1143 spi5: spi@894000 {
1177 compatible = 1144 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 !! 1145 reg = <0 0x894000 0 0x4000>;
1179 reg-names = " 1146 reg-names = "se";
1180 clock-names = 1147 clock-names = "se";
1181 clocks = <&gc 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1149 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1150 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1151 dma-names = "tx", "rx";
1185 pinctrl-names 1152 pinctrl-names = "default";
1186 pinctrl-0 = < 1153 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1154 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1155 spi-max-frequency = <50000000>;
1189 #address-cell 1156 #address-cells = <1>;
1190 #size-cells = 1157 #size-cells = <0>;
1191 status = "dis 1158 status = "disabled";
1192 }; 1159 };
1193 1160
1194 i2c6: i2c@898000 { 1161 i2c6: i2c@898000 {
1195 compatible = 1162 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1163 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1164 clock-names = "se";
1198 clocks = <&gc 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1166 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1167 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1168 dma-names = "tx", "rx";
1202 pinctrl-names 1169 pinctrl-names = "default";
1203 pinctrl-0 = < 1170 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1171 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1172 #address-cells = <1>;
1206 #size-cells = 1173 #size-cells = <0>;
1207 status = "dis 1174 status = "disabled";
1208 }; 1175 };
1209 1176
1210 spi6: spi@898000 { 1177 spi6: spi@898000 {
1211 compatible = 1178 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 !! 1179 reg = <0 0x898000 0 0x4000>;
1213 reg-names = " 1180 reg-names = "se";
1214 clock-names = 1181 clock-names = "se";
1215 clocks = <&gc 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1183 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1184 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1185 dma-names = "tx", "rx";
1219 pinctrl-names 1186 pinctrl-names = "default";
1220 pinctrl-0 = < 1187 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1188 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1189 spi-max-frequency = <50000000>;
1223 #address-cell 1190 #address-cells = <1>;
1224 #size-cells = 1191 #size-cells = <0>;
1225 status = "dis 1192 status = "disabled";
1226 }; 1193 };
1227 1194
1228 i2c7: i2c@89c000 { 1195 i2c7: i2c@89c000 {
1229 compatible = 1196 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1197 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1198 clock-names = "se";
1232 clocks = <&gc 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1200 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1201 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1202 dma-names = "tx", "rx";
1236 pinctrl-names 1203 pinctrl-names = "default";
1237 pinctrl-0 = < 1204 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = !! 1205 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1206 #address-cells = <1>;
1240 #size-cells = 1207 #size-cells = <0>;
1241 status = "dis 1208 status = "disabled";
1242 }; 1209 };
1243 1210
1244 spi7: spi@89c000 { 1211 spi7: spi@89c000 {
1245 compatible = 1212 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 !! 1213 reg = <0 0x89c000 0 0x4000>;
1247 reg-names = " 1214 reg-names = "se";
1248 clock-names = 1215 clock-names = "se";
1249 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1217 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1218 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1219 dma-names = "tx", "rx";
1253 pinctrl-names 1220 pinctrl-names = "default";
1254 pinctrl-0 = < 1221 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1222 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1223 spi-max-frequency = <50000000>;
1257 #address-cell 1224 #address-cells = <1>;
1258 #size-cells = 1225 #size-cells = <0>;
1259 status = "dis 1226 status = "disabled";
1260 }; 1227 };
1261 }; 1228 };
1262 1229
1263 gpi_dma1: dma-controller@a000 1230 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm !! 1231 compatible = "qcom,sm8150-gpi-dma";
1265 reg = <0 0x00a00000 0 !! 1232 reg = <0 0xa00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1233 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1234 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1235 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1236 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1237 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1238 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1239 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1240 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1241 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1242 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1243 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1244 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1245 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1246 dma-channels = <13>;
1280 dma-channel-mask = <0 1247 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1248 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1249 #dma-cells = <3>;
1283 status = "disabled"; 1250 status = "disabled";
1284 }; 1251 };
1285 1252
1286 qupv3_id_1: geniqup@ac0000 { 1253 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1254 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1255 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1256 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1257 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1258 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1259 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1260 #address-cells = <2>;
1294 #size-cells = <2>; 1261 #size-cells = <2>;
1295 ranges; 1262 ranges;
1296 status = "disabled"; 1263 status = "disabled";
1297 1264
1298 i2c8: i2c@a80000 { 1265 i2c8: i2c@a80000 {
1299 compatible = 1266 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1267 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1268 clock-names = "se";
1302 clocks = <&gc 1269 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1270 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1271 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1272 dma-names = "tx", "rx";
1306 pinctrl-names 1273 pinctrl-names = "default";
1307 pinctrl-0 = < 1274 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1275 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1276 #address-cells = <1>;
1310 #size-cells = 1277 #size-cells = <0>;
1311 status = "dis 1278 status = "disabled";
1312 }; 1279 };
1313 1280
1314 spi8: spi@a80000 { 1281 spi8: spi@a80000 {
1315 compatible = 1282 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 !! 1283 reg = <0 0xa80000 0 0x4000>;
1317 reg-names = " 1284 reg-names = "se";
1318 clock-names = 1285 clock-names = "se";
1319 clocks = <&gc 1286 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1287 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1288 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1289 dma-names = "tx", "rx";
1323 pinctrl-names 1290 pinctrl-names = "default";
1324 pinctrl-0 = < 1291 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1292 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1293 spi-max-frequency = <50000000>;
1327 #address-cell 1294 #address-cells = <1>;
1328 #size-cells = 1295 #size-cells = <0>;
1329 status = "dis 1296 status = "disabled";
1330 }; 1297 };
1331 1298
1332 i2c9: i2c@a84000 { 1299 i2c9: i2c@a84000 {
1333 compatible = 1300 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1301 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1302 clock-names = "se";
1336 clocks = <&gc 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1304 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1305 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1306 dma-names = "tx", "rx";
1340 pinctrl-names 1307 pinctrl-names = "default";
1341 pinctrl-0 = < 1308 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1309 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1310 #address-cells = <1>;
1344 #size-cells = 1311 #size-cells = <0>;
1345 status = "dis 1312 status = "disabled";
1346 }; 1313 };
1347 1314
1348 spi9: spi@a84000 { 1315 spi9: spi@a84000 {
1349 compatible = 1316 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 !! 1317 reg = <0 0xa84000 0 0x4000>;
1351 reg-names = " 1318 reg-names = "se";
1352 clock-names = 1319 clock-names = "se";
1353 clocks = <&gc 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1321 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1322 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1323 dma-names = "tx", "rx";
1357 pinctrl-names 1324 pinctrl-names = "default";
1358 pinctrl-0 = < 1325 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1326 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1327 spi-max-frequency = <50000000>;
1361 #address-cell 1328 #address-cells = <1>;
1362 #size-cells = 1329 #size-cells = <0>;
1363 status = "dis 1330 status = "disabled";
1364 }; 1331 };
1365 1332
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 1333 i2c10: i2c@a88000 {
1378 compatible = 1334 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1335 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1336 clock-names = "se";
1381 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1338 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1339 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1340 dma-names = "tx", "rx";
1385 pinctrl-names 1341 pinctrl-names = "default";
1386 pinctrl-0 = < 1342 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1343 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1344 #address-cells = <1>;
1389 #size-cells = 1345 #size-cells = <0>;
1390 status = "dis 1346 status = "disabled";
1391 }; 1347 };
1392 1348
1393 spi10: spi@a88000 { 1349 spi10: spi@a88000 {
1394 compatible = 1350 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 !! 1351 reg = <0 0xa88000 0 0x4000>;
1396 reg-names = " 1352 reg-names = "se";
1397 clock-names = 1353 clock-names = "se";
1398 clocks = <&gc 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1355 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1356 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1357 dma-names = "tx", "rx";
1402 pinctrl-names 1358 pinctrl-names = "default";
1403 pinctrl-0 = < 1359 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1360 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1361 spi-max-frequency = <50000000>;
1406 #address-cell 1362 #address-cells = <1>;
1407 #size-cells = 1363 #size-cells = <0>;
1408 status = "dis 1364 status = "disabled";
1409 }; 1365 };
1410 1366
1411 i2c11: i2c@a8c000 { 1367 i2c11: i2c@a8c000 {
1412 compatible = 1368 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1369 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1370 clock-names = "se";
1415 clocks = <&gc 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1372 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1373 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1374 dma-names = "tx", "rx";
1419 pinctrl-names 1375 pinctrl-names = "default";
1420 pinctrl-0 = < 1376 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1377 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1378 #address-cells = <1>;
1423 #size-cells = 1379 #size-cells = <0>;
1424 status = "dis 1380 status = "disabled";
1425 }; 1381 };
1426 1382
1427 spi11: spi@a8c000 { 1383 spi11: spi@a8c000 {
1428 compatible = 1384 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 !! 1385 reg = <0 0xa8c000 0 0x4000>;
1430 reg-names = " 1386 reg-names = "se";
1431 clock-names = 1387 clock-names = "se";
1432 clocks = <&gc 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1389 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1390 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1391 dma-names = "tx", "rx";
1436 pinctrl-names 1392 pinctrl-names = "default";
1437 pinctrl-0 = < 1393 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1394 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1395 spi-max-frequency = <50000000>;
1440 #address-cell 1396 #address-cells = <1>;
1441 #size-cells = 1397 #size-cells = <0>;
1442 status = "dis 1398 status = "disabled";
1443 }; 1399 };
1444 1400
1445 uart2: serial@a90000 1401 uart2: serial@a90000 {
1446 compatible = 1402 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1403 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1404 clock-names = "se";
1449 clocks = <&gc 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1406 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1407 status = "disabled";
1452 }; 1408 };
1453 1409
1454 i2c12: i2c@a90000 { 1410 i2c12: i2c@a90000 {
1455 compatible = 1411 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1412 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1413 clock-names = "se";
1458 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1415 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1416 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1417 dma-names = "tx", "rx";
1462 pinctrl-names 1418 pinctrl-names = "default";
1463 pinctrl-0 = < 1419 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1420 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1421 #address-cells = <1>;
1466 #size-cells = 1422 #size-cells = <0>;
1467 status = "dis 1423 status = "disabled";
1468 }; 1424 };
1469 1425
1470 spi12: spi@a90000 { 1426 spi12: spi@a90000 {
1471 compatible = 1427 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 !! 1428 reg = <0 0xa90000 0 0x4000>;
1473 reg-names = " 1429 reg-names = "se";
1474 clock-names = 1430 clock-names = "se";
1475 clocks = <&gc 1431 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1432 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1433 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1434 dma-names = "tx", "rx";
1479 pinctrl-names 1435 pinctrl-names = "default";
1480 pinctrl-0 = < 1436 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1437 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1438 spi-max-frequency = <50000000>;
1483 #address-cell 1439 #address-cells = <1>;
1484 #size-cells = 1440 #size-cells = <0>;
1485 status = "dis 1441 status = "disabled";
1486 }; 1442 };
1487 1443
1488 i2c16: i2c@94000 { 1444 i2c16: i2c@94000 {
1489 compatible = 1445 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 !! 1446 reg = <0 0x0094000 0 0x4000>;
1491 clock-names = 1447 clock-names = "se";
1492 clocks = <&gc 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1449 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1450 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1451 dma-names = "tx", "rx";
1496 pinctrl-names 1452 pinctrl-names = "default";
1497 pinctrl-0 = < 1453 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1454 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1455 #address-cells = <1>;
1500 #size-cells = 1456 #size-cells = <0>;
1501 status = "dis 1457 status = "disabled";
1502 }; 1458 };
1503 1459
1504 spi16: spi@a94000 { 1460 spi16: spi@a94000 {
1505 compatible = 1461 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 !! 1462 reg = <0 0xa94000 0 0x4000>;
1507 reg-names = " 1463 reg-names = "se";
1508 clock-names = 1464 clock-names = "se";
1509 clocks = <&gc 1465 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1466 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1467 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1468 dma-names = "tx", "rx";
1513 pinctrl-names 1469 pinctrl-names = "default";
1514 pinctrl-0 = < 1470 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1471 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1472 spi-max-frequency = <50000000>;
1517 #address-cell 1473 #address-cells = <1>;
1518 #size-cells = 1474 #size-cells = <0>;
1519 status = "dis 1475 status = "disabled";
1520 }; 1476 };
1521 }; 1477 };
1522 1478
1523 gpi_dma2: dma-controller@c000 1479 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm !! 1480 compatible = "qcom,sm8150-gpi-dma";
1525 reg = <0 0x00c00000 0 !! 1481 reg = <0 0xc00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1482 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1483 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1484 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1485 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1486 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1487 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1488 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1489 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1490 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1491 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1492 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1493 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1494 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1495 dma-channels = <13>;
1540 dma-channel-mask = <0 1496 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1497 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1498 #dma-cells = <3>;
1543 status = "disabled"; 1499 status = "disabled";
1544 }; 1500 };
1545 1501
1546 qupv3_id_2: geniqup@cc0000 { 1502 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1503 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1504 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1505
1550 clock-names = "m-ahb" 1506 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1507 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1508 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1509 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1510 #address-cells = <2>;
1555 #size-cells = <2>; 1511 #size-cells = <2>;
1556 ranges; 1512 ranges;
1557 status = "disabled"; 1513 status = "disabled";
1558 1514
1559 i2c17: i2c@c80000 { 1515 i2c17: i2c@c80000 {
1560 compatible = 1516 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1517 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1518 clock-names = "se";
1563 clocks = <&gc 1519 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1520 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1521 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1522 dma-names = "tx", "rx";
1567 pinctrl-names 1523 pinctrl-names = "default";
1568 pinctrl-0 = < 1524 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1525 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1526 #address-cells = <1>;
1571 #size-cells = 1527 #size-cells = <0>;
1572 status = "dis 1528 status = "disabled";
1573 }; 1529 };
1574 1530
1575 spi17: spi@c80000 { 1531 spi17: spi@c80000 {
1576 compatible = 1532 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 !! 1533 reg = <0 0xc80000 0 0x4000>;
1578 reg-names = " 1534 reg-names = "se";
1579 clock-names = 1535 clock-names = "se";
1580 clocks = <&gc 1536 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1537 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1538 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1539 dma-names = "tx", "rx";
1584 pinctrl-names 1540 pinctrl-names = "default";
1585 pinctrl-0 = < 1541 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1542 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1543 spi-max-frequency = <50000000>;
1588 #address-cell 1544 #address-cells = <1>;
1589 #size-cells = 1545 #size-cells = <0>;
1590 status = "dis 1546 status = "disabled";
1591 }; 1547 };
1592 1548
1593 i2c18: i2c@c84000 { 1549 i2c18: i2c@c84000 {
1594 compatible = 1550 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1551 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1552 clock-names = "se";
1597 clocks = <&gc 1553 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1554 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1555 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1556 dma-names = "tx", "rx";
1601 pinctrl-names 1557 pinctrl-names = "default";
1602 pinctrl-0 = < 1558 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1559 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1560 #address-cells = <1>;
1605 #size-cells = 1561 #size-cells = <0>;
1606 status = "dis 1562 status = "disabled";
1607 }; 1563 };
1608 1564
1609 spi18: spi@c84000 { 1565 spi18: spi@c84000 {
1610 compatible = 1566 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 !! 1567 reg = <0 0xc84000 0 0x4000>;
1612 reg-names = " 1568 reg-names = "se";
1613 clock-names = 1569 clock-names = "se";
1614 clocks = <&gc 1570 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1571 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1572 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1573 dma-names = "tx", "rx";
1618 pinctrl-names 1574 pinctrl-names = "default";
1619 pinctrl-0 = < 1575 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1576 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1577 spi-max-frequency = <50000000>;
1622 #address-cell 1578 #address-cells = <1>;
1623 #size-cells = 1579 #size-cells = <0>;
1624 status = "dis 1580 status = "disabled";
1625 }; 1581 };
1626 1582
1627 i2c19: i2c@c88000 { 1583 i2c19: i2c@c88000 {
1628 compatible = 1584 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1585 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1586 clock-names = "se";
1631 clocks = <&gc 1587 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1588 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1589 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1590 dma-names = "tx", "rx";
1635 pinctrl-names 1591 pinctrl-names = "default";
1636 pinctrl-0 = < 1592 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1593 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1594 #address-cells = <1>;
1639 #size-cells = 1595 #size-cells = <0>;
1640 status = "dis 1596 status = "disabled";
1641 }; 1597 };
1642 1598
1643 spi19: spi@c88000 { 1599 spi19: spi@c88000 {
1644 compatible = 1600 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 !! 1601 reg = <0 0xc88000 0 0x4000>;
1646 reg-names = " 1602 reg-names = "se";
1647 clock-names = 1603 clock-names = "se";
1648 clocks = <&gc 1604 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1605 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1606 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1607 dma-names = "tx", "rx";
1652 pinctrl-names 1608 pinctrl-names = "default";
1653 pinctrl-0 = < 1609 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1610 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1611 spi-max-frequency = <50000000>;
1656 #address-cell 1612 #address-cells = <1>;
1657 #size-cells = 1613 #size-cells = <0>;
1658 status = "dis 1614 status = "disabled";
1659 }; 1615 };
1660 1616
1661 i2c13: i2c@c8c000 { 1617 i2c13: i2c@c8c000 {
1662 compatible = 1618 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1619 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1620 clock-names = "se";
1665 clocks = <&gc 1621 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1622 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1623 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1624 dma-names = "tx", "rx";
1669 pinctrl-names 1625 pinctrl-names = "default";
1670 pinctrl-0 = < 1626 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1627 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1628 #address-cells = <1>;
1673 #size-cells = 1629 #size-cells = <0>;
1674 status = "dis 1630 status = "disabled";
1675 }; 1631 };
1676 1632
1677 spi13: spi@c8c000 { 1633 spi13: spi@c8c000 {
1678 compatible = 1634 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 !! 1635 reg = <0 0xc8c000 0 0x4000>;
1680 reg-names = " 1636 reg-names = "se";
1681 clock-names = 1637 clock-names = "se";
1682 clocks = <&gc 1638 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1639 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1640 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1641 dma-names = "tx", "rx";
1686 pinctrl-names 1642 pinctrl-names = "default";
1687 pinctrl-0 = < 1643 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1644 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1645 spi-max-frequency = <50000000>;
1690 #address-cell 1646 #address-cells = <1>;
1691 #size-cells = 1647 #size-cells = <0>;
1692 status = "dis 1648 status = "disabled";
1693 }; 1649 };
1694 1650
1695 i2c14: i2c@c90000 { 1651 i2c14: i2c@c90000 {
1696 compatible = 1652 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1653 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1654 clock-names = "se";
1699 clocks = <&gc 1655 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1656 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1657 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1658 dma-names = "tx", "rx";
1703 pinctrl-names 1659 pinctrl-names = "default";
1704 pinctrl-0 = < 1660 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1661 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1662 #address-cells = <1>;
1707 #size-cells = 1663 #size-cells = <0>;
1708 status = "dis 1664 status = "disabled";
1709 }; 1665 };
1710 1666
1711 spi14: spi@c90000 { 1667 spi14: spi@c90000 {
1712 compatible = 1668 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 !! 1669 reg = <0 0xc90000 0 0x4000>;
1714 reg-names = " 1670 reg-names = "se";
1715 clock-names = 1671 clock-names = "se";
1716 clocks = <&gc 1672 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1673 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1674 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1675 dma-names = "tx", "rx";
1720 pinctrl-names 1676 pinctrl-names = "default";
1721 pinctrl-0 = < 1677 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1678 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1679 spi-max-frequency = <50000000>;
1724 #address-cell 1680 #address-cells = <1>;
1725 #size-cells = 1681 #size-cells = <0>;
1726 status = "dis 1682 status = "disabled";
1727 }; 1683 };
1728 1684
1729 i2c15: i2c@c94000 { 1685 i2c15: i2c@c94000 {
1730 compatible = 1686 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1687 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1688 clock-names = "se";
1733 clocks = <&gc 1689 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1690 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1691 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1692 dma-names = "tx", "rx";
1737 pinctrl-names 1693 pinctrl-names = "default";
1738 pinctrl-0 = < 1694 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1695 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1696 #address-cells = <1>;
1741 #size-cells = 1697 #size-cells = <0>;
1742 status = "dis 1698 status = "disabled";
1743 }; 1699 };
1744 1700
1745 spi15: spi@c94000 { 1701 spi15: spi@c94000 {
1746 compatible = 1702 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 !! 1703 reg = <0 0xc94000 0 0x4000>;
1748 reg-names = " 1704 reg-names = "se";
1749 clock-names = 1705 clock-names = "se";
1750 clocks = <&gc 1706 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1707 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1708 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1709 dma-names = "tx", "rx";
1754 pinctrl-names 1710 pinctrl-names = "default";
1755 pinctrl-0 = < 1711 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1712 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1713 spi-max-frequency = <50000000>;
1758 #address-cell 1714 #address-cells = <1>;
1759 #size-cells = 1715 #size-cells = <0>;
1760 status = "dis 1716 status = "disabled";
1761 }; 1717 };
1762 }; 1718 };
1763 1719
1764 config_noc: interconnect@1500 1720 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1721 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1722 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1723 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1724 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1725 };
1770 1726
1771 system_noc: interconnect@1620 1727 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1728 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1729 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1730 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1731 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1732 };
1777 1733
1778 mc_virt: interconnect@163a000 1734 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1735 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1736 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1737 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1738 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1739 };
1784 1740
1785 aggre1_noc: interconnect@16e0 1741 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1742 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1743 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1744 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1745 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1746 };
1791 1747
1792 aggre2_noc: interconnect@1700 1748 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1749 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1750 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1751 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1752 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1753 };
1798 1754
1799 compute_noc: interconnect@172 1755 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1756 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1757 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1758 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1759 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1760 };
1805 1761
1806 mmss_noc: interconnect@174000 1762 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1763 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1764 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1765 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1766 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1767 };
1812 1768
1813 system-cache-controller@92000 1769 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1770 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 1771 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 1772 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 1773 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1774 };
1822 1775
1823 dma@10a2000 { !! 1776 pcie0: pci@1c00000 {
1824 compatible = "qcom,sm !! 1777 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 1778 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1779 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1780 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1781 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1782 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1783 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1784 device_type = "pci";
1838 linux,pci-domain = <0 1785 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1786 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1787 num-lanes = <1>;
1841 1788
1842 #address-cells = <3>; 1789 #address-cells = <3>;
1843 #size-cells = <2>; 1790 #size-cells = <2>;
1844 1791
1845 ranges = <0x01000000 !! 1792 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
1846 <0x02000000 !! 1793 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
1847 1794
1848 interrupts = <GIC_SPI !! 1795 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1849 <GIC_SPI !! 1796 interrupt-names = "msi";
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 1797 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1798 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1799 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1800 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1801 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1802 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1803
1871 clocks = <&gcc GCC_PC 1804 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1805 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1806 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1807 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1808 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1809 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG !! 1810 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", 1811 clock-names = "pipe",
1880 "aux", 1812 "aux",
1881 "cfg", 1813 "cfg",
1882 "bus_ma 1814 "bus_master",
1883 "bus_sl 1815 "bus_slave",
1884 "slave_ 1816 "slave_q2a",
1885 "tbu", !! 1817 "tbu";
1886 "ref"; <<
1887 1818
>> 1819 iommus = <&apps_smmu 0x1d80 0x7f>;
1888 iommu-map = <0x0 &a 1820 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1821 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1822
1891 resets = <&gcc GCC_PC 1823 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1824 reset-names = "pci";
1893 1825
1894 power-domains = <&gcc 1826 power-domains = <&gcc PCIE_0_GDSC>;
1895 1827
1896 phys = <&pcie0_phy>; !! 1828 phys = <&pcie0_lane>;
1897 phy-names = "pciephy" 1829 phy-names = "pciephy";
1898 1830
1899 perst-gpios = <&tlmm !! 1831 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 !! 1832 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1833
1902 pinctrl-names = "defa 1834 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1835 pinctrl-0 = <&pcie0_default_state>;
1904 1836
1905 status = "disabled"; 1837 status = "disabled";
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; 1838 };
1917 1839
1918 pcie0_phy: phy@1c06000 { 1840 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1841 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 !! 1842 reg = <0 0x01c06000 0 0x1c0>;
>> 1843 #address-cells = <2>;
>> 1844 #size-cells = <2>;
>> 1845 ranges;
1921 clocks = <&gcc GCC_PC 1846 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1847 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC !! 1848 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1924 <&gcc GCC_PC !! 1849 clock-names = "aux", "cfg_ahb", "refgen";
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 1850
1937 resets = <&gcc GCC_PC 1851 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1852 reset-names = "phy";
1939 1853
1940 assigned-clocks = <&g 1854 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1855 assigned-clock-rates = <100000000>;
1942 1856
1943 status = "disabled"; 1857 status = "disabled";
>> 1858
>> 1859 pcie0_lane: phy@1c06200 {
>> 1860 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1861 <0 0x1c06400 0 0x200>, /* rx */
>> 1862 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1863 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1864 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1865 clock-names = "pipe0";
>> 1866
>> 1867 #phy-cells = <0>;
>> 1868 clock-output-names = "pcie_0_pipe_clk";
>> 1869 };
1944 }; 1870 };
1945 1871
1946 pcie1: pcie@1c08000 { !! 1872 pcie1: pci@1c08000 {
1947 compatible = "qcom,pc !! 1873 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1948 reg = <0 0x01c08000 0 1874 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1875 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1876 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1877 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1878 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1879 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1880 device_type = "pci";
1955 linux,pci-domain = <1 1881 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1882 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1883 num-lanes = <2>;
1958 1884
1959 #address-cells = <3>; 1885 #address-cells = <3>;
1960 #size-cells = <2>; 1886 #size-cells = <2>;
1961 1887
1962 ranges = <0x01000000 !! 1888 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1889 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1890
1965 interrupts = <GIC_SPI !! 1891 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1966 <GIC_SPI !! 1892 interrupt-names = "msi";
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 1893 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1894 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1895 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1896 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1897 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1898 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1899
1988 clocks = <&gcc GCC_PC 1900 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1901 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1902 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1903 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1904 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1905 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG !! 1906 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", 1907 clock-names = "pipe",
1997 "aux", 1908 "aux",
1998 "cfg", 1909 "cfg",
1999 "bus_ma 1910 "bus_master",
2000 "bus_sl 1911 "bus_slave",
2001 "slave_ 1912 "slave_q2a",
2002 "tbu", !! 1913 "tbu";
2003 "ref"; <<
2004 1914
2005 assigned-clocks = <&g 1915 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 1916 assigned-clock-rates = <19200000>;
2007 1917
>> 1918 iommus = <&apps_smmu 0x1e00 0x7f>;
2008 iommu-map = <0x0 &a 1919 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 1920 <0x100 &apps_smmu 0x1e01 0x1>;
2010 1921
2011 resets = <&gcc GCC_PC 1922 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 1923 reset-names = "pci";
2013 1924
2014 power-domains = <&gcc 1925 power-domains = <&gcc PCIE_1_GDSC>;
2015 1926
2016 phys = <&pcie1_phy>; !! 1927 phys = <&pcie1_lane>;
2017 phy-names = "pciephy" 1928 phy-names = "pciephy";
2018 1929
2019 perst-gpios = <&tlmm !! 1930 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 1931 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 1932
2022 pinctrl-names = "defa 1933 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 1934 pinctrl-0 = <&pcie1_default_state>;
2024 1935
2025 status = "disabled"; 1936 status = "disabled";
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; 1937 };
2037 1938
2038 pcie1_phy: phy@1c0e000 { 1939 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 1940 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 !! 1941 reg = <0 0x01c0e000 0 0x1c0>;
>> 1942 #address-cells = <2>;
>> 1943 #size-cells = <2>;
>> 1944 ranges;
2041 clocks = <&gcc GCC_PC 1945 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 1946 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC !! 1947 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2044 <&gcc GCC_PC !! 1948 clock-names = "aux", "cfg_ahb", "refgen";
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 1949
2057 resets = <&gcc GCC_PC 1950 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 1951 reset-names = "phy";
2059 1952
2060 assigned-clocks = <&g 1953 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 1954 assigned-clock-rates = <100000000>;
2062 1955
2063 status = "disabled"; 1956 status = "disabled";
>> 1957
>> 1958 pcie1_lane: phy@1c0e200 {
>> 1959 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1960 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1961 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1962 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1963 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1964 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1965 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1966 clock-names = "pipe0";
>> 1967
>> 1968 #phy-cells = <0>;
>> 1969 clock-output-names = "pcie_1_pipe_clk";
>> 1970 };
2064 }; 1971 };
2065 1972
2066 ufs_mem_hc: ufshc@1d84000 { 1973 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 1974 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 1975 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 1976 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 1977 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 1978 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 1979 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 1980 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 1981 phy-names = "ufsphy";
2075 lanes-per-direction = 1982 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 1983 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 1984 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 1985 reset-names = "rst";
2079 1986
2080 iommus = <&apps_smmu 1987 iommus = <&apps_smmu 0x300 0>;
2081 1988
2082 clock-names = 1989 clock-names =
2083 "core_clk", 1990 "core_clk",
2084 "bus_aggr_clk 1991 "bus_aggr_clk",
2085 "iface_clk", 1992 "iface_clk",
2086 "core_clk_uni 1993 "core_clk_unipro",
2087 "ref_clk", 1994 "ref_clk",
2088 "tx_lane0_syn 1995 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 1996 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 1997 "rx_lane1_sync_clk",
2091 "ice_core_clk 1998 "ice_core_clk";
2092 clocks = 1999 clocks =
2093 <&gcc GCC_UFS 2000 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 2001 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 2002 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 2003 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 2004 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 2005 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2006 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2007 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2008 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2009 freq-table-hz =
2103 <37500000 300 2010 <37500000 300000000>,
2104 <0 0>, 2011 <0 0>,
2105 <0 0>, 2012 <0 0>,
2106 <37500000 300 2013 <37500000 300000000>,
2107 <0 0>, 2014 <0 0>,
2108 <0 0>, 2015 <0 0>,
2109 <0 0>, 2016 <0 0>,
2110 <0 0>, 2017 <0 0>,
2111 <0 300000000> 2018 <0 300000000>;
2112 2019
2113 status = "disabled"; 2020 status = "disabled";
2114 }; 2021 };
2115 2022
2116 ufs_mem_phy: phy@1d87000 { 2023 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2024 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 2025 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 2026 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 2027 #size-cells = <2>;
2121 <&gcc GCC_UF !! 2028 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 2029 clock-names = "ref",
2124 "ref_au !! 2030 "ref_aux";
2125 "qref"; !! 2031 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>> 2032 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2126 2033
2127 power-domains = <&gcc 2034 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2035
2129 resets = <&ufs_mem_hc 2036 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2037 reset-names = "ufsphy";
>> 2038 status = "disabled";
2131 2039
2132 #phy-cells = <0>; !! 2040 ufs_mem_phy_lanes: phy@1d87400 {
>> 2041 reg = <0 0x01d87400 0 0x108>,
>> 2042 <0 0x01d87600 0 0x1e0>,
>> 2043 <0 0x01d87c00 0 0x1dc>,
>> 2044 <0 0x01d87800 0 0x108>,
>> 2045 <0 0x01d87a00 0 0x1e0>;
>> 2046 #phy-cells = <0>;
>> 2047 };
>> 2048 };
2133 2049
2134 status = "disabled"; !! 2050 ipa_virt: interconnect@1e00000 {
>> 2051 compatible = "qcom,sm8150-ipa-virt";
>> 2052 reg = <0 0x01e00000 0 0x1000>;
>> 2053 #interconnect-cells = <1>;
>> 2054 qcom,bcm-voters = <&apps_bcm_voter>;
2135 }; 2055 };
2136 2056
2137 cryptobam: dma-controller@1dc !! 2057 tcsr_mutex_regs: syscon@1f40000 {
2138 compatible = "qcom,ba !! 2058 compatible = "syscon";
2139 reg = <0 0x01dc4000 0 !! 2059 reg = <0x0 0x01f40000 0x0 0x40000>;
2140 interrupts = <GIC_SPI <<
2141 #dma-cells = <1>; <<
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; <<
2166 <<
2167 tcsr_mutex: hwlock@1f40000 { <<
2168 compatible = "qcom,tc <<
2169 reg = <0x0 0x01f40000 <<
2170 #hwlock-cells = <1>; <<
2171 }; <<
2172 <<
2173 tcsr_regs_1: syscon@1f60000 { <<
2174 compatible = "qcom,sm <<
2175 reg = <0x0 0x01f60000 <<
2176 }; 2060 };
2177 2061
2178 remoteproc_slpi: remoteproc@2 2062 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2063 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2064 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2065
2182 interrupts-extended = 2066 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2067 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2068 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2069 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2070 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2071 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2072 "handover", "stop-ack";
2189 2073
2190 clocks = <&rpmhcc RPM 2074 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2075 clock-names = "xo";
2192 2076
2193 power-domains = <&rpm !! 2077 power-domains = <&rpmhpd 3>,
2194 <&rpm !! 2078 <&rpmhpd 2>;
2195 power-domain-names = 2079 power-domain-names = "lcx", "lmx";
2196 2080
2197 memory-region = <&slp 2081 memory-region = <&slpi_mem>;
2198 2082
2199 qcom,qmp = <&aoss_qmp 2083 qcom,qmp = <&aoss_qmp>;
2200 2084
2201 qcom,smem-states = <& 2085 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2086 qcom,smem-state-names = "stop";
2203 2087
2204 status = "disabled"; 2088 status = "disabled";
2205 2089
2206 glink-edge { 2090 glink-edge {
2207 interrupts = 2091 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2092 label = "dsps";
2209 qcom,remote-p 2093 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2094 mboxes = <&apss_shared 24>;
2211 2095
2212 fastrpc { 2096 fastrpc {
2213 compa 2097 compatible = "qcom,fastrpc";
2214 qcom, 2098 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2099 label = "sdsp";
2216 qcom, 2100 qcom,non-secure-domain;
2217 #addr 2101 #address-cells = <1>;
2218 #size 2102 #size-cells = <0>;
2219 2103
2220 compu 2104 compute-cb@1 {
2221 2105 compatible = "qcom,fastrpc-compute-cb";
2222 2106 reg = <1>;
2223 2107 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2108 };
2225 2109
2226 compu 2110 compute-cb@2 {
2227 2111 compatible = "qcom,fastrpc-compute-cb";
2228 2112 reg = <2>;
2229 2113 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2114 };
2231 2115
2232 compu 2116 compute-cb@3 {
2233 2117 compatible = "qcom,fastrpc-compute-cb";
2234 2118 reg = <3>;
2235 2119 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2120 /* note: shared-cb = <4> in downstream */
2237 }; 2121 };
2238 }; 2122 };
2239 }; 2123 };
2240 }; 2124 };
2241 2125
2242 gpu: gpu@2c00000 { 2126 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 2127 /*
>> 2128 * note: the amd,imageon compatible makes it possible
>> 2129 * to use the drm/msm driver without the display node,
>> 2130 * make sure to remove it when display node is added
>> 2131 */
>> 2132 compatible = "qcom,adreno-640.1",
>> 2133 "qcom,adreno",
>> 2134 "amd,imageon";
>> 2135
2244 reg = <0 0x02c00000 0 2136 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2137 reg-names = "kgsl_3d0_reg_memory";
2246 2138
2247 interrupts = <GIC_SPI 2139 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2140
2249 iommus = <&adreno_smm 2141 iommus = <&adreno_smmu 0 0x401>;
2250 2142
2251 operating-points-v2 = 2143 operating-points-v2 = <&gpu_opp_table>;
2252 2144
2253 qcom,gmu = <&gmu>; 2145 qcom,gmu = <&gmu>;
2254 2146
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 2147 status = "disabled";
2260 2148
2261 zap-shader { 2149 zap-shader {
2262 memory-region 2150 memory-region = <&gpu_mem>;
2263 }; 2151 };
2264 2152
>> 2153 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 2154 gpu_opp_table: opp-table {
2266 compatible = 2155 compatible = "operating-points-v2";
2267 2156
2268 opp-675000000 2157 opp-675000000 {
2269 opp-h 2158 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2159 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 2160 };
2273 2161
2274 opp-585000000 2162 opp-585000000 {
2275 opp-h 2163 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2164 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 2165 };
2279 2166
2280 opp-499200000 2167 opp-499200000 {
2281 opp-h 2168 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2169 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 2170 };
2285 2171
2286 opp-427000000 2172 opp-427000000 {
2287 opp-h 2173 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2174 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 2175 };
2291 2176
2292 opp-345000000 2177 opp-345000000 {
2293 opp-h 2178 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2179 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 2180 };
2297 2181
2298 opp-257000000 2182 opp-257000000 {
2299 opp-h 2183 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2184 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 2185 };
2303 }; 2186 };
2304 }; 2187 };
2305 2188
2306 gmu: gmu@2c6a000 { 2189 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad !! 2190 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2191
2309 reg = <0 0x02c6a000 0 2192 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2193 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2194 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2196
2314 interrupts = <GIC_SPI 2197 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2198 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2199 interrupt-names = "hfi", "gmu";
2317 2200
2318 clocks = <&gpucc GPU_ 2201 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2202 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2203 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2204 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2205 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2207
2325 power-domains = <&gpu 2208 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2209 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2210 power-domain-names = "cx", "gx";
2328 2211
2329 iommus = <&adreno_smm 2212 iommus = <&adreno_smmu 5 0x400>;
2330 2213
2331 operating-points-v2 = 2214 operating-points-v2 = <&gmu_opp_table>;
2332 2215
2333 status = "disabled"; 2216 status = "disabled";
2334 2217
2335 gmu_opp_table: opp-ta 2218 gmu_opp_table: opp-table {
2336 compatible = 2219 compatible = "operating-points-v2";
2337 2220
2338 opp-200000000 2221 opp-200000000 {
2339 opp-h 2222 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2223 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2224 };
2342 }; 2225 };
2343 }; 2226 };
2344 2227
2345 gpucc: clock-controller@2c900 2228 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2229 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2230 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2231 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2232 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2233 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2234 clock-names = "bi_tcxo",
2352 "gcc_gp 2235 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2236 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2237 #clock-cells = <1>;
2355 #reset-cells = <1>; 2238 #reset-cells = <1>;
2356 #power-domain-cells = 2239 #power-domain-cells = <1>;
2357 }; 2240 };
2358 2241
2359 adreno_smmu: iommu@2ca0000 { 2242 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 2243 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 2244 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2245 #iommu-cells = <2>;
2364 #global-interrupts = 2246 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2247 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2248 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2249 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2250 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2251 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2252 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2253 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2254 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2255 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2256 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2257 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2258 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2259 clock-names = "ahb", "bus", "iface";
2378 2260
2379 power-domains = <&gpu 2261 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2262 };
2381 2263
2382 tlmm: pinctrl@3100000 { 2264 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2265 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2266 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2267 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2268 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2269 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2270 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2271 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2272 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2273 gpio-controller;
2392 #gpio-cells = <2>; 2274 #gpio-cells = <2>;
2393 interrupt-controller; 2275 interrupt-controller;
2394 #interrupt-cells = <2 2276 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2277 wakeup-parent = <&pdc>;
2396 2278
2397 qup_i2c0_default: qup !! 2279 qup_i2c0_default: qup-i2c0-default {
2398 pins = "gpio0 !! 2280 mux {
2399 function = "q !! 2281 pins = "gpio0", "gpio1";
2400 drive-strengt !! 2282 function = "qup0";
2401 bias-disable; !! 2283 };
>> 2284
>> 2285 config {
>> 2286 pins = "gpio0", "gpio1";
>> 2287 drive-strength = <0x02>;
>> 2288 bias-disable;
>> 2289 };
2402 }; 2290 };
2403 2291
2404 qup_spi0_default: qup !! 2292 qup_spi0_default: qup-spi0-default {
2405 pins = "gpio0 2293 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2294 function = "qup0";
2407 drive-strengt 2295 drive-strength = <6>;
2408 bias-disable; 2296 bias-disable;
2409 }; 2297 };
2410 2298
2411 qup_i2c1_default: qup !! 2299 qup_i2c1_default: qup-i2c1-default {
2412 pins = "gpio1 !! 2300 mux {
2413 function = "q !! 2301 pins = "gpio114", "gpio115";
2414 drive-strengt !! 2302 function = "qup1";
2415 bias-disable; !! 2303 };
>> 2304
>> 2305 config {
>> 2306 pins = "gpio114", "gpio115";
>> 2307 drive-strength = <0x02>;
>> 2308 bias-disable;
>> 2309 };
2416 }; 2310 };
2417 2311
2418 qup_spi1_default: qup !! 2312 qup_spi1_default: qup-spi1-default {
2419 pins = "gpio1 2313 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2314 function = "qup1";
2421 drive-strengt 2315 drive-strength = <6>;
2422 bias-disable; 2316 bias-disable;
2423 }; 2317 };
2424 2318
2425 qup_i2c2_default: qup !! 2319 qup_i2c2_default: qup-i2c2-default {
2426 pins = "gpio1 !! 2320 mux {
2427 function = "q !! 2321 pins = "gpio126", "gpio127";
2428 drive-strengt !! 2322 function = "qup2";
2429 bias-disable; !! 2323 };
>> 2324
>> 2325 config {
>> 2326 pins = "gpio126", "gpio127";
>> 2327 drive-strength = <0x02>;
>> 2328 bias-disable;
>> 2329 };
2430 }; 2330 };
2431 2331
2432 qup_spi2_default: qup !! 2332 qup_spi2_default: qup-spi2-default {
2433 pins = "gpio1 2333 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2334 function = "qup2";
2435 drive-strengt 2335 drive-strength = <6>;
2436 bias-disable; 2336 bias-disable;
2437 }; 2337 };
2438 2338
2439 qup_i2c3_default: qup !! 2339 qup_i2c3_default: qup-i2c3-default {
2440 pins = "gpio1 !! 2340 mux {
2441 function = "q !! 2341 pins = "gpio144", "gpio145";
2442 drive-strengt !! 2342 function = "qup3";
2443 bias-disable; !! 2343 };
>> 2344
>> 2345 config {
>> 2346 pins = "gpio144", "gpio145";
>> 2347 drive-strength = <0x02>;
>> 2348 bias-disable;
>> 2349 };
2444 }; 2350 };
2445 2351
2446 qup_spi3_default: qup !! 2352 qup_spi3_default: qup-spi3-default {
2447 pins = "gpio1 2353 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2354 function = "qup3";
2449 drive-strengt 2355 drive-strength = <6>;
2450 bias-disable; 2356 bias-disable;
2451 }; 2357 };
2452 2358
2453 qup_i2c4_default: qup !! 2359 qup_i2c4_default: qup-i2c4-default {
2454 pins = "gpio5 !! 2360 mux {
2455 function = "q !! 2361 pins = "gpio51", "gpio52";
2456 drive-strengt !! 2362 function = "qup4";
2457 bias-disable; !! 2363 };
>> 2364
>> 2365 config {
>> 2366 pins = "gpio51", "gpio52";
>> 2367 drive-strength = <0x02>;
>> 2368 bias-disable;
>> 2369 };
2458 }; 2370 };
2459 2371
2460 qup_spi4_default: qup !! 2372 qup_spi4_default: qup-spi4-default {
2461 pins = "gpio5 2373 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2374 function = "qup4";
2463 drive-strengt 2375 drive-strength = <6>;
2464 bias-disable; 2376 bias-disable;
2465 }; 2377 };
2466 2378
2467 qup_i2c5_default: qup !! 2379 qup_i2c5_default: qup-i2c5-default {
2468 pins = "gpio1 !! 2380 mux {
2469 function = "q !! 2381 pins = "gpio121", "gpio122";
2470 drive-strengt !! 2382 function = "qup5";
2471 bias-disable; !! 2383 };
>> 2384
>> 2385 config {
>> 2386 pins = "gpio121", "gpio122";
>> 2387 drive-strength = <0x02>;
>> 2388 bias-disable;
>> 2389 };
2472 }; 2390 };
2473 2391
2474 qup_spi5_default: qup !! 2392 qup_spi5_default: qup-spi5-default {
2475 pins = "gpio1 2393 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2394 function = "qup5";
2477 drive-strengt 2395 drive-strength = <6>;
2478 bias-disable; 2396 bias-disable;
2479 }; 2397 };
2480 2398
2481 qup_i2c6_default: qup !! 2399 qup_i2c6_default: qup-i2c6-default {
2482 pins = "gpio6 !! 2400 mux {
2483 function = "q !! 2401 pins = "gpio6", "gpio7";
2484 drive-strengt !! 2402 function = "qup6";
2485 bias-disable; !! 2403 };
>> 2404
>> 2405 config {
>> 2406 pins = "gpio6", "gpio7";
>> 2407 drive-strength = <0x02>;
>> 2408 bias-disable;
>> 2409 };
2486 }; 2410 };
2487 2411
2488 qup_spi6_default: qup !! 2412 qup_spi6_default: qup-spi6_default {
2489 pins = "gpio4 2413 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2414 function = "qup6";
2491 drive-strengt 2415 drive-strength = <6>;
2492 bias-disable; 2416 bias-disable;
2493 }; 2417 };
2494 2418
2495 qup_i2c7_default: qup !! 2419 qup_i2c7_default: qup-i2c7-default {
2496 pins = "gpio9 !! 2420 mux {
2497 function = "q !! 2421 pins = "gpio98", "gpio99";
2498 drive-strengt !! 2422 function = "qup7";
2499 bias-disable; !! 2423 };
>> 2424
>> 2425 config {
>> 2426 pins = "gpio98", "gpio99";
>> 2427 drive-strength = <0x02>;
>> 2428 bias-disable;
>> 2429 };
2500 }; 2430 };
2501 2431
2502 qup_spi7_default: qup !! 2432 qup_spi7_default: qup-spi7_default {
2503 pins = "gpio9 2433 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2434 function = "qup7";
2505 drive-strengt 2435 drive-strength = <6>;
2506 bias-disable; 2436 bias-disable;
2507 }; 2437 };
2508 2438
2509 qup_i2c8_default: qup !! 2439 qup_i2c8_default: qup-i2c8-default {
2510 pins = "gpio8 !! 2440 mux {
2511 function = "q !! 2441 pins = "gpio88", "gpio89";
2512 drive-strengt !! 2442 function = "qup8";
2513 bias-disable; !! 2443 };
>> 2444
>> 2445 config {
>> 2446 pins = "gpio88", "gpio89";
>> 2447 drive-strength = <0x02>;
>> 2448 bias-disable;
>> 2449 };
2514 }; 2450 };
2515 2451
2516 qup_spi8_default: qup !! 2452 qup_spi8_default: qup-spi8-default {
2517 pins = "gpio8 2453 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2454 function = "qup8";
2519 drive-strengt 2455 drive-strength = <6>;
2520 bias-disable; 2456 bias-disable;
2521 }; 2457 };
2522 2458
2523 qup_i2c9_default: qup !! 2459 qup_i2c9_default: qup-i2c9-default {
2524 pins = "gpio3 !! 2460 mux {
2525 function = "q !! 2461 pins = "gpio39", "gpio40";
2526 drive-strengt !! 2462 function = "qup9";
2527 bias-disable; !! 2463 };
>> 2464
>> 2465 config {
>> 2466 pins = "gpio39", "gpio40";
>> 2467 drive-strength = <0x02>;
>> 2468 bias-disable;
>> 2469 };
2528 }; 2470 };
2529 2471
2530 qup_spi9_default: qup !! 2472 qup_spi9_default: qup-spi9-default {
2531 pins = "gpio3 2473 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2474 function = "qup9";
2533 drive-strengt 2475 drive-strength = <6>;
2534 bias-disable; 2476 bias-disable;
2535 }; 2477 };
2536 2478
2537 qup_uart9_default: qu !! 2479 qup_i2c10_default: qup-i2c10-default {
2538 pins = "gpio4 !! 2480 mux {
2539 function = "q !! 2481 pins = "gpio9", "gpio10";
2540 drive-strengt !! 2482 function = "qup10";
2541 bias-disable; !! 2483 };
2542 }; <<
2543 2484
2544 qup_i2c10_default: qu !! 2485 config {
2545 pins = "gpio9 !! 2486 pins = "gpio9", "gpio10";
2546 function = "q !! 2487 drive-strength = <0x02>;
2547 drive-strengt !! 2488 bias-disable;
2548 bias-disable; !! 2489 };
2549 }; 2490 };
2550 2491
2551 qup_spi10_default: qu !! 2492 qup_spi10_default: qup-spi10-default {
2552 pins = "gpio9 2493 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2494 function = "qup10";
2554 drive-strengt 2495 drive-strength = <6>;
2555 bias-disable; 2496 bias-disable;
2556 }; 2497 };
2557 2498
2558 qup_i2c11_default: qu !! 2499 qup_i2c11_default: qup-i2c11-default {
2559 pins = "gpio9 !! 2500 mux {
2560 function = "q !! 2501 pins = "gpio94", "gpio95";
2561 drive-strengt !! 2502 function = "qup11";
2562 bias-disable; !! 2503 };
>> 2504
>> 2505 config {
>> 2506 pins = "gpio94", "gpio95";
>> 2507 drive-strength = <0x02>;
>> 2508 bias-disable;
>> 2509 };
2563 }; 2510 };
2564 2511
2565 qup_spi11_default: qu !! 2512 qup_spi11_default: qup-spi11-default {
2566 pins = "gpio9 2513 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2514 function = "qup11";
2568 drive-strengt 2515 drive-strength = <6>;
2569 bias-disable; 2516 bias-disable;
2570 }; 2517 };
2571 2518
2572 qup_i2c12_default: qu !! 2519 qup_i2c12_default: qup-i2c12-default {
2573 pins = "gpio8 !! 2520 mux {
2574 function = "q !! 2521 pins = "gpio83", "gpio84";
2575 drive-strengt !! 2522 function = "qup12";
2576 bias-disable; !! 2523 };
>> 2524
>> 2525 config {
>> 2526 pins = "gpio83", "gpio84";
>> 2527 drive-strength = <0x02>;
>> 2528 bias-disable;
>> 2529 };
2577 }; 2530 };
2578 2531
2579 qup_spi12_default: qu !! 2532 qup_spi12_default: qup-spi12-default {
2580 pins = "gpio8 2533 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2534 function = "qup12";
2582 drive-strengt 2535 drive-strength = <6>;
2583 bias-disable; 2536 bias-disable;
2584 }; 2537 };
2585 2538
2586 qup_i2c13_default: qu !! 2539 qup_i2c13_default: qup-i2c13-default {
2587 pins = "gpio4 !! 2540 mux {
2588 function = "q !! 2541 pins = "gpio43", "gpio44";
2589 drive-strengt !! 2542 function = "qup13";
2590 bias-disable; !! 2543 };
>> 2544
>> 2545 config {
>> 2546 pins = "gpio43", "gpio44";
>> 2547 drive-strength = <0x02>;
>> 2548 bias-disable;
>> 2549 };
2591 }; 2550 };
2592 2551
2593 qup_spi13_default: qu !! 2552 qup_spi13_default: qup-spi13-default {
2594 pins = "gpio4 2553 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2554 function = "qup13";
2596 drive-strengt 2555 drive-strength = <6>;
2597 bias-disable; 2556 bias-disable;
2598 }; 2557 };
2599 2558
2600 qup_i2c14_default: qu !! 2559 qup_i2c14_default: qup-i2c14-default {
2601 pins = "gpio4 !! 2560 mux {
2602 function = "q !! 2561 pins = "gpio47", "gpio48";
2603 drive-strengt !! 2562 function = "qup14";
2604 bias-disable; !! 2563 };
>> 2564
>> 2565 config {
>> 2566 pins = "gpio47", "gpio48";
>> 2567 drive-strength = <0x02>;
>> 2568 bias-disable;
>> 2569 };
2605 }; 2570 };
2606 2571
2607 qup_spi14_default: qu !! 2572 qup_spi14_default: qup-spi14-default {
2608 pins = "gpio4 2573 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2574 function = "qup14";
2610 drive-strengt 2575 drive-strength = <6>;
2611 bias-disable; 2576 bias-disable;
2612 }; 2577 };
2613 2578
2614 qup_i2c15_default: qu !! 2579 qup_i2c15_default: qup-i2c15-default {
2615 pins = "gpio2 !! 2580 mux {
2616 function = "q !! 2581 pins = "gpio27", "gpio28";
2617 drive-strengt !! 2582 function = "qup15";
2618 bias-disable; !! 2583 };
>> 2584
>> 2585 config {
>> 2586 pins = "gpio27", "gpio28";
>> 2587 drive-strength = <0x02>;
>> 2588 bias-disable;
>> 2589 };
2619 }; 2590 };
2620 2591
2621 qup_spi15_default: qu !! 2592 qup_spi15_default: qup-spi15-default {
2622 pins = "gpio2 2593 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2594 function = "qup15";
2624 drive-strengt 2595 drive-strength = <6>;
2625 bias-disable; 2596 bias-disable;
2626 }; 2597 };
2627 2598
2628 qup_i2c16_default: qu !! 2599 qup_i2c16_default: qup-i2c16-default {
2629 pins = "gpio8 !! 2600 mux {
2630 function = "q !! 2601 pins = "gpio86", "gpio85";
2631 drive-strengt !! 2602 function = "qup16";
2632 bias-disable; !! 2603 };
>> 2604
>> 2605 config {
>> 2606 pins = "gpio86", "gpio85";
>> 2607 drive-strength = <0x02>;
>> 2608 bias-disable;
>> 2609 };
2633 }; 2610 };
2634 2611
2635 qup_spi16_default: qu !! 2612 qup_spi16_default: qup-spi16-default {
2636 pins = "gpio8 2613 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2614 function = "qup16";
2638 drive-strengt 2615 drive-strength = <6>;
2639 bias-disable; 2616 bias-disable;
2640 }; 2617 };
2641 2618
2642 qup_i2c17_default: qu !! 2619 qup_i2c17_default: qup-i2c17-default {
2643 pins = "gpio5 !! 2620 mux {
2644 function = "q !! 2621 pins = "gpio55", "gpio56";
2645 drive-strengt !! 2622 function = "qup17";
2646 bias-disable; !! 2623 };
>> 2624
>> 2625 config {
>> 2626 pins = "gpio55", "gpio56";
>> 2627 drive-strength = <0x02>;
>> 2628 bias-disable;
>> 2629 };
2647 }; 2630 };
2648 2631
2649 qup_spi17_default: qu !! 2632 qup_spi17_default: qup-spi17-default {
2650 pins = "gpio5 2633 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2634 function = "qup17";
2652 drive-strengt 2635 drive-strength = <6>;
2653 bias-disable; 2636 bias-disable;
2654 }; 2637 };
2655 2638
2656 qup_i2c18_default: qu !! 2639 qup_i2c18_default: qup-i2c18-default {
2657 pins = "gpio2 !! 2640 mux {
2658 function = "q !! 2641 pins = "gpio23", "gpio24";
2659 drive-strengt !! 2642 function = "qup18";
2660 bias-disable; !! 2643 };
>> 2644
>> 2645 config {
>> 2646 pins = "gpio23", "gpio24";
>> 2647 drive-strength = <0x02>;
>> 2648 bias-disable;
>> 2649 };
2661 }; 2650 };
2662 2651
2663 qup_spi18_default: qu !! 2652 qup_spi18_default: qup-spi18-default {
2664 pins = "gpio2 2653 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2654 function = "qup18";
2666 drive-strengt 2655 drive-strength = <6>;
2667 bias-disable; 2656 bias-disable;
2668 }; 2657 };
2669 2658
2670 qup_i2c19_default: qu !! 2659 qup_i2c19_default: qup-i2c19-default {
2671 pins = "gpio5 !! 2660 mux {
2672 function = "q !! 2661 pins = "gpio57", "gpio58";
2673 drive-strengt !! 2662 function = "qup19";
2674 bias-disable; !! 2663 };
>> 2664
>> 2665 config {
>> 2666 pins = "gpio57", "gpio58";
>> 2667 drive-strength = <0x02>;
>> 2668 bias-disable;
>> 2669 };
2675 }; 2670 };
2676 2671
2677 qup_spi19_default: qu !! 2672 qup_spi19_default: qup-spi19-default {
2678 pins = "gpio5 2673 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2674 function = "qup19";
2680 drive-strengt 2675 drive-strength = <6>;
2681 bias-disable; 2676 bias-disable;
2682 }; 2677 };
2683 2678
2684 pcie0_default_state: !! 2679 pcie0_default_state: pcie0-default {
2685 perst-pins { !! 2680 perst {
2686 pins 2681 pins = "gpio35";
2687 funct 2682 function = "gpio";
2688 drive 2683 drive-strength = <2>;
2689 bias- 2684 bias-pull-down;
2690 }; 2685 };
2691 2686
2692 clkreq-pins { !! 2687 clkreq {
2693 pins 2688 pins = "gpio36";
2694 funct 2689 function = "pci_e0";
2695 drive 2690 drive-strength = <2>;
2696 bias- 2691 bias-pull-up;
2697 }; 2692 };
2698 2693
2699 wake-pins { !! 2694 wake {
2700 pins 2695 pins = "gpio37";
2701 funct 2696 function = "gpio";
2702 drive 2697 drive-strength = <2>;
2703 bias- 2698 bias-pull-up;
2704 }; 2699 };
2705 }; 2700 };
2706 2701
2707 pcie1_default_state: !! 2702 pcie1_default_state: pcie1-default {
2708 perst-pins { !! 2703 perst {
2709 pins 2704 pins = "gpio102";
2710 funct 2705 function = "gpio";
2711 drive 2706 drive-strength = <2>;
2712 bias- 2707 bias-pull-down;
2713 }; 2708 };
2714 2709
2715 clkreq-pins { !! 2710 clkreq {
2716 pins 2711 pins = "gpio103";
2717 funct 2712 function = "pci_e1";
2718 drive 2713 drive-strength = <2>;
2719 bias- 2714 bias-pull-up;
2720 }; 2715 };
2721 2716
2722 wake-pins { !! 2717 wake {
2723 pins 2718 pins = "gpio104";
2724 funct 2719 function = "gpio";
2725 drive 2720 drive-strength = <2>;
2726 bias- 2721 bias-pull-up;
2727 }; 2722 };
2728 }; 2723 };
2729 }; 2724 };
2730 2725
2731 remoteproc_mpss: remoteproc@4 2726 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2727 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2728 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2729
2735 interrupts-extended = 2730 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2731 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2732 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2733 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2734 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2735 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2736 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2737 "stop-ack", "shutdown-ack";
2743 2738
2744 clocks = <&rpmhcc RPM 2739 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2740 clock-names = "xo";
2746 2741
2747 power-domains = <&rpm !! 2742 power-domains = <&rpmhpd 7>,
2748 <&rpm !! 2743 <&rpmhpd 0>;
2749 power-domain-names = 2744 power-domain-names = "cx", "mss";
2750 2745
2751 memory-region = <&mps 2746 memory-region = <&mpss_mem>;
2752 2747
2753 qcom,qmp = <&aoss_qmp 2748 qcom,qmp = <&aoss_qmp>;
2754 2749
2755 qcom,smem-states = <& 2750 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2751 qcom,smem-state-names = "stop";
2757 2752
2758 status = "disabled"; 2753 status = "disabled";
2759 2754
2760 glink-edge { 2755 glink-edge {
2761 interrupts = 2756 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2757 label = "modem";
2763 qcom,remote-p 2758 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2759 mboxes = <&apss_shared 12>;
2765 }; 2760 };
2766 }; 2761 };
2767 2762
2768 stm@6002000 { 2763 stm@6002000 {
2769 compatible = "arm,cor 2764 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2765 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2766 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2767 reg-names = "stm-base", "stm-stimulus-base";
2773 2768
2774 clocks = <&aoss_qmp>; 2769 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2770 clock-names = "apb_pclk";
2776 2771
2777 out-ports { 2772 out-ports {
2778 port { 2773 port {
2779 stm_o 2774 stm_out: endpoint {
2780 2775 remote-endpoint = <&funnel0_in7>;
2781 }; 2776 };
2782 }; 2777 };
2783 }; 2778 };
2784 }; 2779 };
2785 2780
2786 funnel@6041000 { 2781 funnel@6041000 {
2787 compatible = "arm,cor 2782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2783 reg = <0 0x06041000 0 0x1000>;
2789 2784
2790 clocks = <&aoss_qmp>; 2785 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2786 clock-names = "apb_pclk";
2792 2787
2793 out-ports { 2788 out-ports {
2794 port { 2789 port {
2795 funne 2790 funnel0_out: endpoint {
2796 2791 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2792 };
2798 }; 2793 };
2799 }; 2794 };
2800 2795
2801 in-ports { 2796 in-ports {
2802 #address-cell 2797 #address-cells = <1>;
2803 #size-cells = 2798 #size-cells = <0>;
2804 2799
2805 port@7 { 2800 port@7 {
2806 reg = 2801 reg = <7>;
2807 funne 2802 funnel0_in7: endpoint {
2808 2803 remote-endpoint = <&stm_out>;
2809 }; 2804 };
2810 }; 2805 };
2811 }; 2806 };
2812 }; 2807 };
2813 2808
2814 funnel@6042000 { 2809 funnel@6042000 {
2815 compatible = "arm,cor 2810 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2811 reg = <0 0x06042000 0 0x1000>;
2817 2812
2818 clocks = <&aoss_qmp>; 2813 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2814 clock-names = "apb_pclk";
2820 2815
2821 out-ports { 2816 out-ports {
2822 port { 2817 port {
2823 funne 2818 funnel1_out: endpoint {
2824 2819 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2820 };
2826 }; 2821 };
2827 }; 2822 };
2828 2823
2829 in-ports { 2824 in-ports {
2830 #address-cell 2825 #address-cells = <1>;
2831 #size-cells = 2826 #size-cells = <0>;
2832 2827
2833 port@4 { 2828 port@4 {
2834 reg = 2829 reg = <4>;
2835 funne 2830 funnel1_in4: endpoint {
2836 2831 remote-endpoint = <&swao_replicator_out>;
2837 }; 2832 };
2838 }; 2833 };
2839 }; 2834 };
2840 }; 2835 };
2841 2836
2842 funnel@6043000 { 2837 funnel@6043000 {
2843 compatible = "arm,cor 2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2839 reg = <0 0x06043000 0 0x1000>;
2845 2840
2846 clocks = <&aoss_qmp>; 2841 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2842 clock-names = "apb_pclk";
2848 2843
2849 out-ports { 2844 out-ports {
2850 port { 2845 port {
2851 funne 2846 funnel2_out: endpoint {
2852 2847 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2848 };
2854 }; 2849 };
2855 }; 2850 };
2856 2851
2857 in-ports { 2852 in-ports {
2858 #address-cell 2853 #address-cells = <1>;
2859 #size-cells = 2854 #size-cells = <0>;
2860 2855
2861 port@2 { 2856 port@2 {
2862 reg = 2857 reg = <2>;
2863 funne 2858 funnel2_in2: endpoint {
2864 2859 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2860 };
2866 }; 2861 };
2867 }; 2862 };
2868 }; 2863 };
2869 2864
2870 funnel@6045000 { 2865 funnel@6045000 {
2871 compatible = "arm,cor 2866 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2867 reg = <0 0x06045000 0 0x1000>;
2873 2868
2874 clocks = <&aoss_qmp>; 2869 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2870 clock-names = "apb_pclk";
2876 2871
2877 out-ports { 2872 out-ports {
2878 port { 2873 port {
2879 merge 2874 merge_funnel_out: endpoint {
2880 2875 remote-endpoint = <&etf_in>;
2881 }; 2876 };
2882 }; 2877 };
2883 }; 2878 };
2884 2879
2885 in-ports { 2880 in-ports {
2886 #address-cell 2881 #address-cells = <1>;
2887 #size-cells = 2882 #size-cells = <0>;
2888 2883
2889 port@0 { 2884 port@0 {
2890 reg = 2885 reg = <0>;
2891 merge 2886 merge_funnel_in0: endpoint {
2892 2887 remote-endpoint = <&funnel0_out>;
2893 }; 2888 };
2894 }; 2889 };
2895 2890
2896 port@1 { 2891 port@1 {
2897 reg = 2892 reg = <1>;
2898 merge 2893 merge_funnel_in1: endpoint {
2899 2894 remote-endpoint = <&funnel1_out>;
2900 }; 2895 };
2901 }; 2896 };
2902 2897
2903 port@2 { 2898 port@2 {
2904 reg = 2899 reg = <2>;
2905 merge 2900 merge_funnel_in2: endpoint {
2906 2901 remote-endpoint = <&funnel2_out>;
2907 }; 2902 };
2908 }; 2903 };
2909 }; 2904 };
2910 }; 2905 };
2911 2906
2912 replicator@6046000 { 2907 replicator@6046000 {
2913 compatible = "arm,cor 2908 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2909 reg = <0 0x06046000 0 0x1000>;
2915 2910
2916 clocks = <&aoss_qmp>; 2911 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2912 clock-names = "apb_pclk";
2918 2913
2919 out-ports { 2914 out-ports {
2920 #address-cell 2915 #address-cells = <1>;
2921 #size-cells = 2916 #size-cells = <0>;
2922 2917
2923 port@0 { 2918 port@0 {
2924 reg = 2919 reg = <0>;
2925 repli 2920 replicator_out0: endpoint {
2926 2921 remote-endpoint = <&etr_in>;
2927 }; 2922 };
2928 }; 2923 };
2929 2924
2930 port@1 { 2925 port@1 {
2931 reg = 2926 reg = <1>;
2932 repli 2927 replicator_out1: endpoint {
2933 2928 remote-endpoint = <&replicator1_in>;
2934 }; 2929 };
2935 }; 2930 };
2936 }; 2931 };
2937 2932
2938 in-ports { 2933 in-ports {
2939 port { 2934 port {
2940 repli 2935 replicator_in0: endpoint {
2941 2936 remote-endpoint = <&etf_out>;
2942 }; 2937 };
2943 }; 2938 };
2944 }; 2939 };
2945 }; 2940 };
2946 2941
2947 etf@6047000 { 2942 etf@6047000 {
2948 compatible = "arm,cor 2943 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2944 reg = <0 0x06047000 0 0x1000>;
2950 2945
2951 clocks = <&aoss_qmp>; 2946 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2947 clock-names = "apb_pclk";
2953 2948
2954 out-ports { 2949 out-ports {
2955 port { 2950 port {
2956 etf_o 2951 etf_out: endpoint {
2957 2952 remote-endpoint = <&replicator_in0>;
2958 }; 2953 };
2959 }; 2954 };
2960 }; 2955 };
2961 2956
2962 in-ports { 2957 in-ports {
2963 port { 2958 port {
2964 etf_i 2959 etf_in: endpoint {
2965 2960 remote-endpoint = <&merge_funnel_out>;
2966 }; 2961 };
2967 }; 2962 };
2968 }; 2963 };
2969 }; 2964 };
2970 2965
2971 etr@6048000 { 2966 etr@6048000 {
2972 compatible = "arm,cor 2967 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2968 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2969 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2970
2976 clocks = <&aoss_qmp>; 2971 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2972 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2973 arm,scatter-gather;
2979 2974
2980 in-ports { 2975 in-ports {
2981 port { 2976 port {
2982 etr_i 2977 etr_in: endpoint {
2983 2978 remote-endpoint = <&replicator_out0>;
2984 }; 2979 };
2985 }; 2980 };
2986 }; 2981 };
2987 }; 2982 };
2988 2983
2989 replicator@604a000 { 2984 replicator@604a000 {
2990 compatible = "arm,cor 2985 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2986 reg = <0 0x0604a000 0 0x1000>;
2992 2987
2993 clocks = <&aoss_qmp>; 2988 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2989 clock-names = "apb_pclk";
2995 2990
2996 out-ports { 2991 out-ports {
2997 #address-cell 2992 #address-cells = <1>;
2998 #size-cells = 2993 #size-cells = <0>;
2999 2994
3000 port@1 { 2995 port@1 {
3001 reg = 2996 reg = <1>;
3002 repli 2997 replicator1_out: endpoint {
3003 2998 remote-endpoint = <&swao_funnel_in>;
3004 }; 2999 };
3005 }; 3000 };
3006 }; 3001 };
3007 3002
3008 in-ports { 3003 in-ports {
>> 3004 #address-cells = <1>;
>> 3005 #size-cells = <0>;
3009 3006
3010 port { !! 3007 port@1 {
>> 3008 reg = <1>;
3011 repli 3009 replicator1_in: endpoint {
3012 3010 remote-endpoint = <&replicator_out1>;
3013 }; 3011 };
3014 }; 3012 };
3015 }; 3013 };
3016 }; 3014 };
3017 3015
3018 funnel@6b08000 { 3016 funnel@6b08000 {
3019 compatible = "arm,cor 3017 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 3018 reg = <0 0x06b08000 0 0x1000>;
3021 3019
3022 clocks = <&aoss_qmp>; 3020 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 3021 clock-names = "apb_pclk";
3024 3022
3025 out-ports { 3023 out-ports {
3026 port { 3024 port {
3027 swao_ 3025 swao_funnel_out: endpoint {
3028 3026 remote-endpoint = <&swao_etf_in>;
3029 }; 3027 };
3030 }; 3028 };
3031 }; 3029 };
3032 3030
3033 in-ports { 3031 in-ports {
3034 #address-cell 3032 #address-cells = <1>;
3035 #size-cells = 3033 #size-cells = <0>;
3036 3034
3037 port@6 { 3035 port@6 {
3038 reg = 3036 reg = <6>;
3039 swao_ 3037 swao_funnel_in: endpoint {
3040 3038 remote-endpoint = <&replicator1_out>;
3041 }; 3039 };
3042 }; 3040 };
3043 }; 3041 };
3044 }; 3042 };
3045 3043
3046 etf@6b09000 { 3044 etf@6b09000 {
3047 compatible = "arm,cor 3045 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 3046 reg = <0 0x06b09000 0 0x1000>;
3049 3047
3050 clocks = <&aoss_qmp>; 3048 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 3049 clock-names = "apb_pclk";
3052 3050
3053 out-ports { 3051 out-ports {
3054 port { 3052 port {
3055 swao_ 3053 swao_etf_out: endpoint {
3056 3054 remote-endpoint = <&swao_replicator_in>;
3057 }; 3055 };
3058 }; 3056 };
3059 }; 3057 };
3060 3058
3061 in-ports { 3059 in-ports {
3062 port { 3060 port {
3063 swao_ 3061 swao_etf_in: endpoint {
3064 3062 remote-endpoint = <&swao_funnel_out>;
3065 }; 3063 };
3066 }; 3064 };
3067 }; 3065 };
3068 }; 3066 };
3069 3067
3070 replicator@6b0a000 { 3068 replicator@6b0a000 {
3071 compatible = "arm,cor 3069 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 3070 reg = <0 0x06b0a000 0 0x1000>;
3073 3071
3074 clocks = <&aoss_qmp>; 3072 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 3073 clock-names = "apb_pclk";
3076 qcom,replicator-loses 3074 qcom,replicator-loses-context;
3077 3075
3078 out-ports { 3076 out-ports {
3079 port { 3077 port {
3080 swao_ 3078 swao_replicator_out: endpoint {
3081 3079 remote-endpoint = <&funnel1_in4>;
3082 }; 3080 };
3083 }; 3081 };
3084 }; 3082 };
3085 3083
3086 in-ports { 3084 in-ports {
3087 port { 3085 port {
3088 swao_ 3086 swao_replicator_in: endpoint {
3089 3087 remote-endpoint = <&swao_etf_out>;
3090 }; 3088 };
3091 }; 3089 };
3092 }; 3090 };
3093 }; 3091 };
3094 3092
3095 etm@7040000 { 3093 etm@7040000 {
3096 compatible = "arm,cor 3094 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 3095 reg = <0 0x07040000 0 0x1000>;
3098 3096
3099 cpu = <&CPU0>; 3097 cpu = <&CPU0>;
3100 3098
3101 clocks = <&aoss_qmp>; 3099 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 3100 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 3101 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 3102 qcom,skip-power-up;
3105 3103
3106 out-ports { 3104 out-ports {
3107 port { 3105 port {
3108 etm0_ 3106 etm0_out: endpoint {
3109 3107 remote-endpoint = <&apss_funnel_in0>;
3110 }; 3108 };
3111 }; 3109 };
3112 }; 3110 };
3113 }; 3111 };
3114 3112
3115 etm@7140000 { 3113 etm@7140000 {
3116 compatible = "arm,cor 3114 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 3115 reg = <0 0x07140000 0 0x1000>;
3118 3116
3119 cpu = <&CPU1>; 3117 cpu = <&CPU1>;
3120 3118
3121 clocks = <&aoss_qmp>; 3119 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3120 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3121 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3122 qcom,skip-power-up;
3125 3123
3126 out-ports { 3124 out-ports {
3127 port { 3125 port {
3128 etm1_ 3126 etm1_out: endpoint {
3129 3127 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3128 };
3131 }; 3129 };
3132 }; 3130 };
3133 }; 3131 };
3134 3132
3135 etm@7240000 { 3133 etm@7240000 {
3136 compatible = "arm,cor 3134 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3135 reg = <0 0x07240000 0 0x1000>;
3138 3136
3139 cpu = <&CPU2>; 3137 cpu = <&CPU2>;
3140 3138
3141 clocks = <&aoss_qmp>; 3139 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3140 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3141 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3142 qcom,skip-power-up;
3145 3143
3146 out-ports { 3144 out-ports {
3147 port { 3145 port {
3148 etm2_ 3146 etm2_out: endpoint {
3149 3147 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3148 };
3151 }; 3149 };
3152 }; 3150 };
3153 }; 3151 };
3154 3152
3155 etm@7340000 { 3153 etm@7340000 {
3156 compatible = "arm,cor 3154 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3155 reg = <0 0x07340000 0 0x1000>;
3158 3156
3159 cpu = <&CPU3>; 3157 cpu = <&CPU3>;
3160 3158
3161 clocks = <&aoss_qmp>; 3159 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3160 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3161 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3162 qcom,skip-power-up;
3165 3163
3166 out-ports { 3164 out-ports {
3167 port { 3165 port {
3168 etm3_ 3166 etm3_out: endpoint {
3169 3167 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3168 };
3171 }; 3169 };
3172 }; 3170 };
3173 }; 3171 };
3174 3172
3175 etm@7440000 { 3173 etm@7440000 {
3176 compatible = "arm,cor 3174 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3175 reg = <0 0x07440000 0 0x1000>;
3178 3176
3179 cpu = <&CPU4>; 3177 cpu = <&CPU4>;
3180 3178
3181 clocks = <&aoss_qmp>; 3179 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3180 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3181 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3182 qcom,skip-power-up;
3185 3183
3186 out-ports { 3184 out-ports {
3187 port { 3185 port {
3188 etm4_ 3186 etm4_out: endpoint {
3189 3187 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3188 };
3191 }; 3189 };
3192 }; 3190 };
3193 }; 3191 };
3194 3192
3195 etm@7540000 { 3193 etm@7540000 {
3196 compatible = "arm,cor 3194 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3195 reg = <0 0x07540000 0 0x1000>;
3198 3196
3199 cpu = <&CPU5>; 3197 cpu = <&CPU5>;
3200 3198
3201 clocks = <&aoss_qmp>; 3199 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3200 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3201 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3202 qcom,skip-power-up;
3205 3203
3206 out-ports { 3204 out-ports {
3207 port { 3205 port {
3208 etm5_ 3206 etm5_out: endpoint {
3209 3207 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3208 };
3211 }; 3209 };
3212 }; 3210 };
3213 }; 3211 };
3214 3212
3215 etm@7640000 { 3213 etm@7640000 {
3216 compatible = "arm,cor 3214 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3215 reg = <0 0x07640000 0 0x1000>;
3218 3216
3219 cpu = <&CPU6>; 3217 cpu = <&CPU6>;
3220 3218
3221 clocks = <&aoss_qmp>; 3219 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3220 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3221 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3222 qcom,skip-power-up;
3225 3223
3226 out-ports { 3224 out-ports {
3227 port { 3225 port {
3228 etm6_ 3226 etm6_out: endpoint {
3229 3227 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3228 };
3231 }; 3229 };
3232 }; 3230 };
3233 }; 3231 };
3234 3232
3235 etm@7740000 { 3233 etm@7740000 {
3236 compatible = "arm,cor 3234 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3235 reg = <0 0x07740000 0 0x1000>;
3238 3236
3239 cpu = <&CPU7>; 3237 cpu = <&CPU7>;
3240 3238
3241 clocks = <&aoss_qmp>; 3239 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3240 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3241 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3242 qcom,skip-power-up;
3245 3243
3246 out-ports { 3244 out-ports {
3247 port { 3245 port {
3248 etm7_ 3246 etm7_out: endpoint {
3249 3247 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3248 };
3251 }; 3249 };
3252 }; 3250 };
3253 }; 3251 };
3254 3252
3255 funnel@7800000 { /* APSS Funn 3253 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3255 reg = <0 0x07800000 0 0x1000>;
3258 3256
3259 clocks = <&aoss_qmp>; 3257 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3258 clock-names = "apb_pclk";
3261 3259
3262 out-ports { 3260 out-ports {
3263 port { 3261 port {
3264 apss_ 3262 apss_funnel_out: endpoint {
3265 3263 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3264 };
3267 }; 3265 };
3268 }; 3266 };
3269 3267
3270 in-ports { 3268 in-ports {
3271 #address-cell 3269 #address-cells = <1>;
3272 #size-cells = 3270 #size-cells = <0>;
3273 3271
3274 port@0 { 3272 port@0 {
3275 reg = 3273 reg = <0>;
3276 apss_ 3274 apss_funnel_in0: endpoint {
3277 3275 remote-endpoint = <&etm0_out>;
3278 }; 3276 };
3279 }; 3277 };
3280 3278
3281 port@1 { 3279 port@1 {
3282 reg = 3280 reg = <1>;
3283 apss_ 3281 apss_funnel_in1: endpoint {
3284 3282 remote-endpoint = <&etm1_out>;
3285 }; 3283 };
3286 }; 3284 };
3287 3285
3288 port@2 { 3286 port@2 {
3289 reg = 3287 reg = <2>;
3290 apss_ 3288 apss_funnel_in2: endpoint {
3291 3289 remote-endpoint = <&etm2_out>;
3292 }; 3290 };
3293 }; 3291 };
3294 3292
3295 port@3 { 3293 port@3 {
3296 reg = 3294 reg = <3>;
3297 apss_ 3295 apss_funnel_in3: endpoint {
3298 3296 remote-endpoint = <&etm3_out>;
3299 }; 3297 };
3300 }; 3298 };
3301 3299
3302 port@4 { 3300 port@4 {
3303 reg = 3301 reg = <4>;
3304 apss_ 3302 apss_funnel_in4: endpoint {
3305 3303 remote-endpoint = <&etm4_out>;
3306 }; 3304 };
3307 }; 3305 };
3308 3306
3309 port@5 { 3307 port@5 {
3310 reg = 3308 reg = <5>;
3311 apss_ 3309 apss_funnel_in5: endpoint {
3312 3310 remote-endpoint = <&etm5_out>;
3313 }; 3311 };
3314 }; 3312 };
3315 3313
3316 port@6 { 3314 port@6 {
3317 reg = 3315 reg = <6>;
3318 apss_ 3316 apss_funnel_in6: endpoint {
3319 3317 remote-endpoint = <&etm6_out>;
3320 }; 3318 };
3321 }; 3319 };
3322 3320
3323 port@7 { 3321 port@7 {
3324 reg = 3322 reg = <7>;
3325 apss_ 3323 apss_funnel_in7: endpoint {
3326 3324 remote-endpoint = <&etm7_out>;
3327 }; 3325 };
3328 }; 3326 };
3329 }; 3327 };
3330 }; 3328 };
3331 3329
3332 funnel@7810000 { 3330 funnel@7810000 {
3333 compatible = "arm,cor 3331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3332 reg = <0 0x07810000 0 0x1000>;
3335 3333
3336 clocks = <&aoss_qmp>; 3334 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3335 clock-names = "apb_pclk";
3338 3336
3339 out-ports { 3337 out-ports {
3340 port { 3338 port {
3341 apss_ 3339 apss_merge_funnel_out: endpoint {
3342 3340 remote-endpoint = <&funnel2_in2>;
3343 }; 3341 };
3344 }; 3342 };
3345 }; 3343 };
3346 3344
3347 in-ports { 3345 in-ports {
3348 port { 3346 port {
3349 apss_ 3347 apss_merge_funnel_in: endpoint {
3350 3348 remote-endpoint = <&apss_funnel_out>;
3351 }; 3349 };
3352 }; 3350 };
3353 }; 3351 };
3354 }; 3352 };
3355 3353
3356 remoteproc_cdsp: remoteproc@8 3354 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3355 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3356 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3357
3360 interrupts-extended = 3358 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3359 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3360 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3361 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3362 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3363 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3364 "handover", "stop-ack";
3367 3365
3368 clocks = <&rpmhcc RPM 3366 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3367 clock-names = "xo";
3370 3368
3371 power-domains = <&rpm !! 3369 power-domains = <&rpmhpd 7>;
3372 3370
3373 memory-region = <&cds 3371 memory-region = <&cdsp_mem>;
3374 3372
3375 qcom,qmp = <&aoss_qmp 3373 qcom,qmp = <&aoss_qmp>;
3376 3374
3377 qcom,smem-states = <& 3375 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3376 qcom,smem-state-names = "stop";
3379 3377
3380 status = "disabled"; 3378 status = "disabled";
3381 3379
3382 glink-edge { 3380 glink-edge {
3383 interrupts = 3381 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3382 label = "cdsp";
3385 qcom,remote-p 3383 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3384 mboxes = <&apss_shared 4>;
3387 3385
3388 fastrpc { 3386 fastrpc {
3389 compa 3387 compatible = "qcom,fastrpc";
3390 qcom, 3388 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3389 label = "cdsp";
3392 qcom, 3390 qcom,non-secure-domain;
3393 #addr 3391 #address-cells = <1>;
3394 #size 3392 #size-cells = <0>;
3395 3393
3396 compu 3394 compute-cb@1 {
3397 3395 compatible = "qcom,fastrpc-compute-cb";
3398 3396 reg = <1>;
3399 !! 3397 iommus = <&apps_smmu 0x1401 0x2040>,
>> 3398 <&apps_smmu 0x1421 0x0>,
>> 3399 <&apps_smmu 0x2001 0x420>,
>> 3400 <&apps_smmu 0x2041 0x0>;
3400 }; 3401 };
3401 3402
3402 compu 3403 compute-cb@2 {
3403 3404 compatible = "qcom,fastrpc-compute-cb";
3404 3405 reg = <2>;
3405 !! 3406 iommus = <&apps_smmu 0x2 0x3440>,
>> 3407 <&apps_smmu 0x22 0x3400>;
3406 }; 3408 };
3407 3409
3408 compu 3410 compute-cb@3 {
3409 3411 compatible = "qcom,fastrpc-compute-cb";
3410 3412 reg = <3>;
3411 !! 3413 iommus = <&apps_smmu 0x3 0x3440>,
>> 3414 <&apps_smmu 0x1423 0x0>,
>> 3415 <&apps_smmu 0x2023 0x0>;
3412 }; 3416 };
3413 3417
3414 compu 3418 compute-cb@4 {
3415 3419 compatible = "qcom,fastrpc-compute-cb";
3416 3420 reg = <4>;
3417 !! 3421 iommus = <&apps_smmu 0x4 0x3440>,
>> 3422 <&apps_smmu 0x24 0x3400>;
3418 }; 3423 };
3419 3424
3420 compu 3425 compute-cb@5 {
3421 3426 compatible = "qcom,fastrpc-compute-cb";
3422 3427 reg = <5>;
3423 !! 3428 iommus = <&apps_smmu 0x5 0x3440>,
>> 3429 <&apps_smmu 0x25 0x3400>;
3424 }; 3430 };
3425 3431
3426 compu 3432 compute-cb@6 {
3427 3433 compatible = "qcom,fastrpc-compute-cb";
3428 3434 reg = <6>;
3429 !! 3435 iommus = <&apps_smmu 0x6 0x3460>;
3430 }; 3436 };
3431 3437
3432 compu 3438 compute-cb@7 {
3433 3439 compatible = "qcom,fastrpc-compute-cb";
3434 3440 reg = <7>;
3435 !! 3441 iommus = <&apps_smmu 0x7 0x3460>;
3436 }; 3442 };
3437 3443
3438 compu 3444 compute-cb@8 {
3439 3445 compatible = "qcom,fastrpc-compute-cb";
3440 3446 reg = <8>;
3441 !! 3447 iommus = <&apps_smmu 0x8 0x3460>;
3442 }; 3448 };
3443 3449
3444 /* no 3450 /* note: secure cb9 in downstream */
3445 }; 3451 };
3446 }; 3452 };
3447 }; 3453 };
3448 3454
3449 usb_1_hsphy: phy@88e2000 { 3455 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3456 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3457 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3458 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3459 status = "disabled";
3454 #phy-cells = <0>; 3460 #phy-cells = <0>;
3455 3461
3456 clocks = <&rpmhcc RPM 3462 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3463 clock-names = "ref";
3458 3464
3459 resets = <&gcc GCC_QU 3465 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3466 };
3461 3467
3462 usb_2_hsphy: phy@88e3000 { 3468 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3469 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3470 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3471 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3472 status = "disabled";
3467 #phy-cells = <0>; 3473 #phy-cells = <0>;
3468 3474
3469 clocks = <&rpmhcc RPM 3475 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3476 clock-names = "ref";
3471 3477
3472 resets = <&gcc GCC_QU 3478 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3479 };
3474 3480
3475 usb_1_qmpphy: phy@88e8000 { !! 3481 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 3482 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 3483 reg = <0 0x088e9000 0 0x18c>,
>> 3484 <0 0x088e8000 0 0x10>;
>> 3485 status = "disabled";
>> 3486 #address-cells = <2>;
>> 3487 #size-cells = <2>;
>> 3488 ranges;
3478 3489
3479 clocks = <&gcc GCC_US 3490 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3491 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3492 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3493 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3494 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3495
3488 resets = <&gcc GCC_US 3496 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3497 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3498 reset-names = "phy", "common";
3491 3499
3492 #clock-cells = <1>; !! 3500 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3501 reg = <0 0x088e9200 0 0x200>,
3494 !! 3502 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3503 <0 0x088e9c00 0 0x218>,
3496 !! 3504 <0 0x088e9600 0 0x200>,
3497 ports { !! 3505 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3506 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3507 #clock-cells = <0>;
3500 !! 3508 #phy-cells = <0>;
3501 port@0 { !! 3509 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3510 clock-names = "pipe0";
3503 !! 3511 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3512 };
3524 }; 3513 };
3525 3514
3526 usb_2_qmpphy: phy@88eb000 { 3515 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3516 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3517 reg = <0 0x088eb000 0 0x200>;
>> 3518 status = "disabled";
>> 3519 #address-cells = <2>;
>> 3520 #size-cells = <2>;
>> 3521 ranges;
3529 3522
3530 clocks = <&gcc GCC_US 3523 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3524 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3525 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3526 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3527 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 3528
3542 resets = <&gcc GCC_US !! 3529 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3543 <&gcc GCC_US !! 3530 <&gcc GCC_USB3_PHY_SEC_BCR>;
3544 reset-names = "phy", !! 3531 reset-names = "phy", "common";
3545 "phy_ph <<
3546 3532
3547 status = "disabled"; !! 3533 usb_2_ssphy: phy@88eb200 {
>> 3534 reg = <0 0x088eb200 0 0x200>,
>> 3535 <0 0x088eb400 0 0x200>,
>> 3536 <0 0x088eb800 0 0x800>,
>> 3537 <0 0x088eb600 0 0x200>;
>> 3538 #clock-cells = <0>;
>> 3539 #phy-cells = <0>;
>> 3540 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3541 clock-names = "pipe0";
>> 3542 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3543 };
3548 }; 3544 };
3549 3545
3550 sdhc_2: mmc@8804000 { !! 3546 sdhc_2: sdhci@8804000 {
3551 compatible = "qcom,sm 3547 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3548 reg = <0 0x08804000 0 0x1000>;
3553 3549
3554 interrupts = <GIC_SPI 3550 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3551 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3552 interrupt-names = "hc_irq", "pwr_irq";
3557 3553
3558 clocks = <&gcc GCC_SD 3554 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3555 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3556 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3557 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3558 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3559 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3560 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3561 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3562 operating-points-v2 = <&sdhc2_opp_table>;
3567 3563
3568 status = "disabled"; 3564 status = "disabled";
3569 3565
3570 sdhc2_opp_table: opp- !! 3566 sdhc2_opp_table: sdhc2-opp-table {
3571 compatible = 3567 compatible = "operating-points-v2";
3572 3568
3573 opp-19200000 3569 opp-19200000 {
3574 opp-h 3570 opp-hz = /bits/ 64 <19200000>;
3575 requi 3571 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3572 };
3577 3573
3578 opp-50000000 3574 opp-50000000 {
3579 opp-h 3575 opp-hz = /bits/ 64 <50000000>;
3580 requi 3576 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3577 };
3582 3578
3583 opp-100000000 3579 opp-100000000 {
3584 opp-h 3580 opp-hz = /bits/ 64 <100000000>;
3585 requi 3581 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3582 };
3587 3583
3588 opp-202000000 3584 opp-202000000 {
3589 opp-h 3585 opp-hz = /bits/ 64 <202000000>;
3590 requi 3586 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3587 };
3592 }; 3588 };
3593 }; 3589 };
3594 3590
3595 dc_noc: interconnect@9160000 3591 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3592 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3593 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3594 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3595 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3596 };
3601 3597
3602 gem_noc: interconnect@9680000 3598 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3599 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3600 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3601 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3602 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3603 };
3608 3604
3609 usb_1: usb@a6f8800 { 3605 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3606 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3607 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3608 status = "disabled";
3613 #address-cells = <2>; 3609 #address-cells = <2>;
3614 #size-cells = <2>; 3610 #size-cells = <2>;
3615 ranges; 3611 ranges;
3616 dma-ranges; 3612 dma-ranges;
3617 3613
3618 clocks = <&gcc GCC_CF 3614 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3615 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3616 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3617 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3618 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3619 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3620 clock-names = "cfg_noc",
3625 "core", 3621 "core",
3626 "iface" 3622 "iface",
3627 "sleep" 3623 "sleep",
3628 "mock_u 3624 "mock_utmi",
3629 "xo"; 3625 "xo";
3630 3626
3631 assigned-clocks = <&g 3627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3628 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3629 assigned-clock-rates = <19200000>, <200000000>;
3634 3630
3635 interrupts-extended = !! 3631 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3632 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3633 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 3634 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 3635 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3636 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3637
3646 power-domains = <&gcc 3638 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3639
3648 resets = <&gcc GCC_US 3640 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3641
3650 interconnects = <&agg <<
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 3642 usb_1_dwc3: usb@a600000 {
3655 compatible = 3643 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3644 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3645 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3646 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3647 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3648 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3649 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3650 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3651 };
3684 }; 3652 };
3685 3653
3686 usb_2: usb@a8f8800 { 3654 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3655 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3656 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3657 status = "disabled";
3690 #address-cells = <2>; 3658 #address-cells = <2>;
3691 #size-cells = <2>; 3659 #size-cells = <2>;
3692 ranges; 3660 ranges;
3693 dma-ranges; 3661 dma-ranges;
3694 3662
3695 clocks = <&gcc GCC_CF 3663 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3664 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3665 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3666 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3667 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3668 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3669 clock-names = "cfg_noc",
3702 "core", 3670 "core",
3703 "iface" 3671 "iface",
3704 "sleep" 3672 "sleep",
3705 "mock_u 3673 "mock_utmi",
3706 "xo"; 3674 "xo";
3707 3675
3708 assigned-clocks = <&g 3676 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3677 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3678 assigned-clock-rates = <19200000>, <200000000>;
3711 3679
3712 interrupts-extended = !! 3680 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3681 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3682 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 3683 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 3684 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3685 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3686
3723 power-domains = <&gcc 3687 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3688
3725 resets = <&gcc GCC_US 3689 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3690
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3691 usb_2_dwc3: usb@a800000 {
3732 compatible = 3692 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3693 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3694 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3695 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3696 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3697 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3698 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3699 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3700 };
3741 }; 3701 };
3742 3702
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3703 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3704 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3705 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3706 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3707 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3708 };
3762 3709
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 3710 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 3711 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 !! 3712 reg = <0 0x0b220000 0 0x400>;
4152 qcom,pdc-ranges = <0 3713 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 3714 <125 63 1>;
4154 #interrupt-cells = <2 3715 #interrupt-cells = <2>;
4155 interrupt-parent = <& 3716 interrupt-parent = <&intc>;
4156 interrupt-controller; 3717 interrupt-controller;
4157 }; 3718 };
4158 3719
4159 aoss_qmp: power-management@c3 !! 3720 aoss_qmp: power-controller@c300000 {
4160 compatible = "qcom,sm 3721 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 3722 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 3723 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3724 mboxes = <&apss_shared 0>;
4164 3725
4165 #clock-cells = <0>; 3726 #clock-cells = <0>;
4166 }; 3727 };
4167 3728
4168 sram@c3f0000 { 3729 sram@c3f0000 {
4169 compatible = "qcom,rp 3730 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 3731 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 3732 };
4172 3733
4173 tsens0: thermal-sensor@c26300 3734 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3735 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3736 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3737 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3738 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3739 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3740 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3741 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3742 #thermal-sensor-cells = <1>;
4182 }; 3743 };
4183 3744
4184 tsens1: thermal-sensor@c26500 3745 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3746 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3747 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3748 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3749 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3750 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3751 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3752 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3753 #thermal-sensor-cells = <1>;
4193 }; 3754 };
4194 3755
4195 spmi_bus: spmi@c440000 { 3756 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3757 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3758 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3759 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3760 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3761 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3762 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3763 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3764 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3765 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3766 qcom,ee = <0>;
4206 qcom,channel = <0>; 3767 qcom,channel = <0>;
4207 #address-cells = <2>; 3768 #address-cells = <2>;
4208 #size-cells = <0>; 3769 #size-cells = <0>;
4209 interrupt-controller; 3770 interrupt-controller;
4210 #interrupt-cells = <4 3771 #interrupt-cells = <4>;
>> 3772 cell-index = <0>;
4211 }; 3773 };
4212 3774
4213 apps_smmu: iommu@15000000 { 3775 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3776 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3777 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3778 #iommu-cells = <2>;
4217 #global-interrupts = 3779 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3780 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3781 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3782 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3783 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3784 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3785 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3786 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3787 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3788 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3789 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3790 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3791 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3792 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3793 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3794 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3795 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3796 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3797 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3798 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3799 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3800 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3801 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3802 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3803 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3804 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3805 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3806 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3807 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3808 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3809 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3810 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3811 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3812 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3813 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3814 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3815 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3816 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3817 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3818 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3819 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3820 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3821 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 3822 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 3823 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 3824 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 3825 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 3826 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 3827 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 3828 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 3829 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 3830 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 3831 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 3832 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 3833 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 3834 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 3835 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 3836 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 3837 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 3838 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 3839 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 3840 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 3841 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 3842 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 3843 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 3844 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 3845 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 3846 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 3847 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 3848 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 3849 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 3850 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 3851 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 3852 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 3853 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 3854 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 3855 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 3856 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 3857 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 3858 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 3859 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 3860 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 3861 };
4300 3862
4301 remoteproc_adsp: remoteproc@1 3863 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 3864 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 3865 reg = <0x0 0x17300000 0x0 0x4040>;
4304 3866
4305 interrupts-extended = 3867 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 3868 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 3869 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 3870 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 3871 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 3872 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 3873 "handover", "stop-ack";
4312 3874
4313 clocks = <&rpmhcc RPM 3875 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 3876 clock-names = "xo";
4315 3877
4316 power-domains = <&rpm !! 3878 power-domains = <&rpmhpd 7>;
4317 3879
4318 memory-region = <&ads 3880 memory-region = <&adsp_mem>;
4319 3881
4320 qcom,qmp = <&aoss_qmp 3882 qcom,qmp = <&aoss_qmp>;
4321 3883
4322 qcom,smem-states = <& 3884 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 3885 qcom,smem-state-names = "stop";
4324 3886
4325 status = "disabled"; 3887 status = "disabled";
4326 3888
4327 glink-edge { 3889 glink-edge {
4328 interrupts = 3890 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 3891 label = "lpass";
4330 qcom,remote-p 3892 qcom,remote-pid = <2>;
4331 mboxes = <&ap 3893 mboxes = <&apss_shared 8>;
4332 3894
4333 fastrpc { 3895 fastrpc {
4334 compa 3896 compatible = "qcom,fastrpc";
4335 qcom, 3897 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 3898 label = "adsp";
4337 qcom, 3899 qcom,non-secure-domain;
4338 #addr 3900 #address-cells = <1>;
4339 #size 3901 #size-cells = <0>;
4340 3902
4341 compu 3903 compute-cb@3 {
4342 3904 compatible = "qcom,fastrpc-compute-cb";
4343 3905 reg = <3>;
4344 3906 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 3907 };
4346 3908
4347 compu 3909 compute-cb@4 {
4348 3910 compatible = "qcom,fastrpc-compute-cb";
4349 3911 reg = <4>;
4350 3912 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 3913 };
4352 3914
4353 compu 3915 compute-cb@5 {
4354 3916 compatible = "qcom,fastrpc-compute-cb";
4355 3917 reg = <5>;
4356 3918 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 3919 };
4358 }; 3920 };
4359 }; 3921 };
4360 }; 3922 };
4361 3923
4362 intc: interrupt-controller@17 3924 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 3925 compatible = "arm,gic-v3";
4364 interrupt-controller; 3926 interrupt-controller;
4365 #interrupt-cells = <3 3927 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 3928 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 3929 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 3930 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 3931 };
4370 3932
4371 apss_shared: mailbox@17c00000 3933 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 3934 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 3935 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 3936 #mbox-cells = <1>;
4376 }; 3937 };
4377 3938
4378 watchdog@17c10000 { 3939 watchdog@17c10000 {
4379 compatible = "qcom,ap 3940 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 3941 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 3942 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 3943 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 3944 };
4384 3945
4385 timer@17c20000 { 3946 timer@17c20000 {
4386 #address-cells = <1>; 3947 #address-cells = <1>;
4387 #size-cells = <1>; 3948 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 3949 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 3950 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 3951 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 3952 clock-frequency = <19200000>;
4392 3953
4393 frame@17c21000 { !! 3954 frame@17c21000{
4394 frame-number 3955 frame-number = <0>;
4395 interrupts = 3956 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 3957 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 3958 reg = <0x17c21000 0x1000>,
4398 <0x17c2 3959 <0x17c22000 0x1000>;
4399 }; 3960 };
4400 3961
4401 frame@17c23000 { 3962 frame@17c23000 {
4402 frame-number 3963 frame-number = <1>;
4403 interrupts = 3964 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 3965 reg = <0x17c23000 0x1000>;
4405 status = "dis 3966 status = "disabled";
4406 }; 3967 };
4407 3968
4408 frame@17c25000 { 3969 frame@17c25000 {
4409 frame-number 3970 frame-number = <2>;
4410 interrupts = 3971 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 3972 reg = <0x17c25000 0x1000>;
4412 status = "dis 3973 status = "disabled";
4413 }; 3974 };
4414 3975
4415 frame@17c27000 { 3976 frame@17c27000 {
4416 frame-number 3977 frame-number = <3>;
4417 interrupts = 3978 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 3979 reg = <0x17c26000 0x1000>;
4419 status = "dis 3980 status = "disabled";
4420 }; 3981 };
4421 3982
4422 frame@17c29000 { 3983 frame@17c29000 {
4423 frame-number 3984 frame-number = <4>;
4424 interrupts = 3985 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 3986 reg = <0x17c29000 0x1000>;
4426 status = "dis 3987 status = "disabled";
4427 }; 3988 };
4428 3989
4429 frame@17c2b000 { 3990 frame@17c2b000 {
4430 frame-number 3991 frame-number = <5>;
4431 interrupts = 3992 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 3993 reg = <0x17c2b000 0x1000>;
4433 status = "dis 3994 status = "disabled";
4434 }; 3995 };
4435 3996
4436 frame@17c2d000 { 3997 frame@17c2d000 {
4437 frame-number 3998 frame-number = <6>;
4438 interrupts = 3999 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 4000 reg = <0x17c2d000 0x1000>;
4440 status = "dis 4001 status = "disabled";
4441 }; 4002 };
4442 }; 4003 };
4443 4004
4444 apps_rsc: rsc@18200000 { 4005 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 4006 label = "apps_rsc";
4446 compatible = "qcom,rp 4007 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 4008 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 4009 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 4010 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 4011 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 4012 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4013 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 4014 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 4015 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 4016 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 4017 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 4018 <SLEEP_TCS 3>,
4458 <WA 4019 <WAKE_TCS 3>,
4459 <CO 4020 <CONTROL_TCS 1>;
4460 power-domains = <&CLU <<
4461 4021
4462 rpmhcc: clock-control 4022 rpmhcc: clock-controller {
4463 compatible = 4023 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 4024 #clock-cells = <1>;
4465 clock-names = 4025 clock-names = "xo";
4466 clocks = <&xo 4026 clocks = <&xo_board>;
4467 }; 4027 };
4468 4028
4469 rpmhpd: power-control 4029 rpmhpd: power-controller {
4470 compatible = 4030 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 4031 #power-domain-cells = <1>;
4472 operating-poi 4032 operating-points-v2 = <&rpmhpd_opp_table>;
4473 4033
4474 rpmhpd_opp_ta 4034 rpmhpd_opp_table: opp-table {
4475 compa 4035 compatible = "operating-points-v2";
4476 4036
4477 rpmhp 4037 rpmhpd_opp_ret: opp1 {
4478 4038 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 4039 };
4480 4040
4481 rpmhp 4041 rpmhpd_opp_min_svs: opp2 {
4482 4042 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 4043 };
4484 4044
4485 rpmhp 4045 rpmhpd_opp_low_svs: opp3 {
4486 4046 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 4047 };
4488 4048
4489 rpmhp 4049 rpmhpd_opp_svs: opp4 {
4490 4050 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 4051 };
4492 4052
4493 rpmhp 4053 rpmhpd_opp_svs_l1: opp5 {
4494 4054 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 4055 };
4496 4056
4497 rpmhp 4057 rpmhpd_opp_svs_l2: opp6 {
4498 4058 opp-level = <224>;
4499 }; 4059 };
4500 4060
4501 rpmhp 4061 rpmhpd_opp_nom: opp7 {
4502 4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 4063 };
4504 4064
4505 rpmhp 4065 rpmhpd_opp_nom_l1: opp8 {
4506 4066 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 4067 };
4508 4068
4509 rpmhp 4069 rpmhpd_opp_nom_l2: opp9 {
4510 4070 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 4071 };
4512 4072
4513 rpmhp 4073 rpmhpd_opp_turbo: opp10 {
4514 4074 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 4075 };
4516 4076
4517 rpmhp 4077 rpmhpd_opp_turbo_l1: opp11 {
4518 4078 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 4079 };
4520 }; 4080 };
4521 }; 4081 };
4522 4082
4523 apps_bcm_voter: bcm-v 4083 apps_bcm_voter: bcm-voter {
4524 compatible = 4084 compatible = "qcom,bcm-voter";
4525 }; 4085 };
4526 }; 4086 };
4527 4087
4528 osm_l3: interconnect@18321000 4088 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm !! 4089 compatible = "qcom,sm8150-osm-l3";
4530 reg = <0 0x18321000 0 4090 reg = <0 0x18321000 0 0x1400>;
4531 4091
4532 clocks = <&rpmhcc RPM 4092 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 4093 clock-names = "xo", "alternate";
4534 4094
4535 #interconnect-cells = 4095 #interconnect-cells = <1>;
4536 }; 4096 };
4537 4097
4538 cpufreq_hw: cpufreq@18323000 4098 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 4099 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 4100 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 4101 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 4102 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 4103 "freq-domain2";
4544 4104
4545 clocks = <&rpmhcc RPM 4105 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 4106 clock-names = "xo", "alternate";
4547 4107
4548 #freq-domain-cells = 4108 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; 4109 };
4551 4110
4552 lmh_cluster1: lmh@18350800 { 4111 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 4112 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 4113 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 4114 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 4115 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 4116 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 4117 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 4118 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 4119 interrupt-controller;
4561 #interrupt-cells = <1 4120 #interrupt-cells = <1>;
4562 }; 4121 };
4563 4122
4564 lmh_cluster0: lmh@18358800 { 4123 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 4124 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 4125 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 4126 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4127 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4128 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4129 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4130 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4131 interrupt-controller;
4573 #interrupt-cells = <1 4132 #interrupt-cells = <1>;
4574 }; 4133 };
4575 4134
4576 wifi: wifi@18800000 { 4135 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4136 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4137 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4138 reg-names = "membase";
4580 memory-region = <&wla 4139 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4140 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4141 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4142 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4143 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4144 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4145 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4146 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4147 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4148 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4149 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4150 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4151 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4152 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4153 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4154 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4155 status = "disabled";
4597 }; 4156 };
4598 }; 4157 };
4599 4158
4600 timer { 4159 timer {
4601 compatible = "arm,armv8-timer 4160 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4161 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4162 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4163 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4164 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4165 };
4607 4166
4608 thermal-zones { 4167 thermal-zones {
4609 cpu0-thermal { 4168 cpu0-thermal {
4610 polling-delay-passive 4169 polling-delay-passive = <250>;
>> 4170 polling-delay = <1000>;
4611 4171
4612 thermal-sensors = <&t 4172 thermal-sensors = <&tsens0 1>;
4613 4173
4614 trips { 4174 trips {
4615 cpu0_alert0: 4175 cpu0_alert0: trip-point0 {
4616 tempe 4176 temperature = <90000>;
4617 hyste 4177 hysteresis = <2000>;
4618 type 4178 type = "passive";
4619 }; 4179 };
4620 4180
4621 cpu0_alert1: 4181 cpu0_alert1: trip-point1 {
4622 tempe 4182 temperature = <95000>;
4623 hyste 4183 hysteresis = <2000>;
4624 type 4184 type = "passive";
4625 }; 4185 };
4626 4186
4627 cpu0_crit: cp !! 4187 cpu0_crit: cpu_crit {
4628 tempe 4188 temperature = <110000>;
4629 hyste 4189 hysteresis = <1000>;
4630 type 4190 type = "critical";
4631 }; 4191 };
4632 }; 4192 };
4633 4193
4634 cooling-maps { 4194 cooling-maps {
4635 map0 { 4195 map0 {
4636 trip 4196 trip = <&cpu0_alert0>;
4637 cooli 4197 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4198 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4199 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4200 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4201 };
4642 map1 { 4202 map1 {
4643 trip 4203 trip = <&cpu0_alert1>;
4644 cooli 4204 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4205 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4206 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4207 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4208 };
4649 }; 4209 };
4650 }; 4210 };
4651 4211
4652 cpu1-thermal { 4212 cpu1-thermal {
4653 polling-delay-passive 4213 polling-delay-passive = <250>;
>> 4214 polling-delay = <1000>;
4654 4215
4655 thermal-sensors = <&t 4216 thermal-sensors = <&tsens0 2>;
4656 4217
4657 trips { 4218 trips {
4658 cpu1_alert0: 4219 cpu1_alert0: trip-point0 {
4659 tempe 4220 temperature = <90000>;
4660 hyste 4221 hysteresis = <2000>;
4661 type 4222 type = "passive";
4662 }; 4223 };
4663 4224
4664 cpu1_alert1: 4225 cpu1_alert1: trip-point1 {
4665 tempe 4226 temperature = <95000>;
4666 hyste 4227 hysteresis = <2000>;
4667 type 4228 type = "passive";
4668 }; 4229 };
4669 4230
4670 cpu1_crit: cp !! 4231 cpu1_crit: cpu_crit {
4671 tempe 4232 temperature = <110000>;
4672 hyste 4233 hysteresis = <1000>;
4673 type 4234 type = "critical";
4674 }; 4235 };
4675 }; 4236 };
4676 4237
4677 cooling-maps { 4238 cooling-maps {
4678 map0 { 4239 map0 {
4679 trip 4240 trip = <&cpu1_alert0>;
4680 cooli 4241 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4242 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4243 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4244 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4245 };
4685 map1 { 4246 map1 {
4686 trip 4247 trip = <&cpu1_alert1>;
4687 cooli 4248 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4249 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4250 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4251 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4252 };
4692 }; 4253 };
4693 }; 4254 };
4694 4255
4695 cpu2-thermal { 4256 cpu2-thermal {
4696 polling-delay-passive 4257 polling-delay-passive = <250>;
>> 4258 polling-delay = <1000>;
4697 4259
4698 thermal-sensors = <&t 4260 thermal-sensors = <&tsens0 3>;
4699 4261
4700 trips { 4262 trips {
4701 cpu2_alert0: 4263 cpu2_alert0: trip-point0 {
4702 tempe 4264 temperature = <90000>;
4703 hyste 4265 hysteresis = <2000>;
4704 type 4266 type = "passive";
4705 }; 4267 };
4706 4268
4707 cpu2_alert1: 4269 cpu2_alert1: trip-point1 {
4708 tempe 4270 temperature = <95000>;
4709 hyste 4271 hysteresis = <2000>;
4710 type 4272 type = "passive";
4711 }; 4273 };
4712 4274
4713 cpu2_crit: cp !! 4275 cpu2_crit: cpu_crit {
4714 tempe 4276 temperature = <110000>;
4715 hyste 4277 hysteresis = <1000>;
4716 type 4278 type = "critical";
4717 }; 4279 };
4718 }; 4280 };
4719 4281
4720 cooling-maps { 4282 cooling-maps {
4721 map0 { 4283 map0 {
4722 trip 4284 trip = <&cpu2_alert0>;
4723 cooli 4285 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4286 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4287 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4288 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4289 };
4728 map1 { 4290 map1 {
4729 trip 4291 trip = <&cpu2_alert1>;
4730 cooli 4292 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4293 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4294 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4295 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4296 };
4735 }; 4297 };
4736 }; 4298 };
4737 4299
4738 cpu3-thermal { 4300 cpu3-thermal {
4739 polling-delay-passive 4301 polling-delay-passive = <250>;
>> 4302 polling-delay = <1000>;
4740 4303
4741 thermal-sensors = <&t 4304 thermal-sensors = <&tsens0 4>;
4742 4305
4743 trips { 4306 trips {
4744 cpu3_alert0: 4307 cpu3_alert0: trip-point0 {
4745 tempe 4308 temperature = <90000>;
4746 hyste 4309 hysteresis = <2000>;
4747 type 4310 type = "passive";
4748 }; 4311 };
4749 4312
4750 cpu3_alert1: 4313 cpu3_alert1: trip-point1 {
4751 tempe 4314 temperature = <95000>;
4752 hyste 4315 hysteresis = <2000>;
4753 type 4316 type = "passive";
4754 }; 4317 };
4755 4318
4756 cpu3_crit: cp !! 4319 cpu3_crit: cpu_crit {
4757 tempe 4320 temperature = <110000>;
4758 hyste 4321 hysteresis = <1000>;
4759 type 4322 type = "critical";
4760 }; 4323 };
4761 }; 4324 };
4762 4325
4763 cooling-maps { 4326 cooling-maps {
4764 map0 { 4327 map0 {
4765 trip 4328 trip = <&cpu3_alert0>;
4766 cooli 4329 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4330 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4331 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4332 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4333 };
4771 map1 { 4334 map1 {
4772 trip 4335 trip = <&cpu3_alert1>;
4773 cooli 4336 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4337 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4338 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4339 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4340 };
4778 }; 4341 };
4779 }; 4342 };
4780 4343
4781 cpu4-top-thermal { 4344 cpu4-top-thermal {
4782 polling-delay-passive 4345 polling-delay-passive = <250>;
>> 4346 polling-delay = <1000>;
4783 4347
4784 thermal-sensors = <&t 4348 thermal-sensors = <&tsens0 7>;
4785 4349
4786 trips { 4350 trips {
4787 cpu4_top_aler 4351 cpu4_top_alert0: trip-point0 {
4788 tempe 4352 temperature = <90000>;
4789 hyste 4353 hysteresis = <2000>;
4790 type 4354 type = "passive";
4791 }; 4355 };
4792 4356
4793 cpu4_top_aler 4357 cpu4_top_alert1: trip-point1 {
4794 tempe 4358 temperature = <95000>;
4795 hyste 4359 hysteresis = <2000>;
4796 type 4360 type = "passive";
4797 }; 4361 };
4798 4362
4799 cpu4_top_crit !! 4363 cpu4_top_crit: cpu_crit {
4800 tempe 4364 temperature = <110000>;
4801 hyste 4365 hysteresis = <1000>;
4802 type 4366 type = "critical";
4803 }; 4367 };
4804 }; 4368 };
4805 4369
4806 cooling-maps { 4370 cooling-maps {
4807 map0 { 4371 map0 {
4808 trip 4372 trip = <&cpu4_top_alert0>;
4809 cooli 4373 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4374 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4375 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4376 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4377 };
4814 map1 { 4378 map1 {
4815 trip 4379 trip = <&cpu4_top_alert1>;
4816 cooli 4380 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4381 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4382 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4383 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4384 };
4821 }; 4385 };
4822 }; 4386 };
4823 4387
4824 cpu5-top-thermal { 4388 cpu5-top-thermal {
4825 polling-delay-passive 4389 polling-delay-passive = <250>;
>> 4390 polling-delay = <1000>;
4826 4391
4827 thermal-sensors = <&t 4392 thermal-sensors = <&tsens0 8>;
4828 4393
4829 trips { 4394 trips {
4830 cpu5_top_aler 4395 cpu5_top_alert0: trip-point0 {
4831 tempe 4396 temperature = <90000>;
4832 hyste 4397 hysteresis = <2000>;
4833 type 4398 type = "passive";
4834 }; 4399 };
4835 4400
4836 cpu5_top_aler 4401 cpu5_top_alert1: trip-point1 {
4837 tempe 4402 temperature = <95000>;
4838 hyste 4403 hysteresis = <2000>;
4839 type 4404 type = "passive";
4840 }; 4405 };
4841 4406
4842 cpu5_top_crit !! 4407 cpu5_top_crit: cpu_crit {
4843 tempe 4408 temperature = <110000>;
4844 hyste 4409 hysteresis = <1000>;
4845 type 4410 type = "critical";
4846 }; 4411 };
4847 }; 4412 };
4848 4413
4849 cooling-maps { 4414 cooling-maps {
4850 map0 { 4415 map0 {
4851 trip 4416 trip = <&cpu5_top_alert0>;
4852 cooli 4417 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4418 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4419 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4420 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4421 };
4857 map1 { 4422 map1 {
4858 trip 4423 trip = <&cpu5_top_alert1>;
4859 cooli 4424 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4425 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4426 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4427 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4428 };
4864 }; 4429 };
4865 }; 4430 };
4866 4431
4867 cpu6-top-thermal { 4432 cpu6-top-thermal {
4868 polling-delay-passive 4433 polling-delay-passive = <250>;
>> 4434 polling-delay = <1000>;
4869 4435
4870 thermal-sensors = <&t 4436 thermal-sensors = <&tsens0 9>;
4871 4437
4872 trips { 4438 trips {
4873 cpu6_top_aler 4439 cpu6_top_alert0: trip-point0 {
4874 tempe 4440 temperature = <90000>;
4875 hyste 4441 hysteresis = <2000>;
4876 type 4442 type = "passive";
4877 }; 4443 };
4878 4444
4879 cpu6_top_aler 4445 cpu6_top_alert1: trip-point1 {
4880 tempe 4446 temperature = <95000>;
4881 hyste 4447 hysteresis = <2000>;
4882 type 4448 type = "passive";
4883 }; 4449 };
4884 4450
4885 cpu6_top_crit !! 4451 cpu6_top_crit: cpu_crit {
4886 tempe 4452 temperature = <110000>;
4887 hyste 4453 hysteresis = <1000>;
4888 type 4454 type = "critical";
4889 }; 4455 };
4890 }; 4456 };
4891 4457
4892 cooling-maps { 4458 cooling-maps {
4893 map0 { 4459 map0 {
4894 trip 4460 trip = <&cpu6_top_alert0>;
4895 cooli 4461 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4462 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4463 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4464 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4465 };
4900 map1 { 4466 map1 {
4901 trip 4467 trip = <&cpu6_top_alert1>;
4902 cooli 4468 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4469 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4470 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4471 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4472 };
4907 }; 4473 };
4908 }; 4474 };
4909 4475
4910 cpu7-top-thermal { 4476 cpu7-top-thermal {
4911 polling-delay-passive 4477 polling-delay-passive = <250>;
>> 4478 polling-delay = <1000>;
4912 4479
4913 thermal-sensors = <&t 4480 thermal-sensors = <&tsens0 10>;
4914 4481
4915 trips { 4482 trips {
4916 cpu7_top_aler 4483 cpu7_top_alert0: trip-point0 {
4917 tempe 4484 temperature = <90000>;
4918 hyste 4485 hysteresis = <2000>;
4919 type 4486 type = "passive";
4920 }; 4487 };
4921 4488
4922 cpu7_top_aler 4489 cpu7_top_alert1: trip-point1 {
4923 tempe 4490 temperature = <95000>;
4924 hyste 4491 hysteresis = <2000>;
4925 type 4492 type = "passive";
4926 }; 4493 };
4927 4494
4928 cpu7_top_crit !! 4495 cpu7_top_crit: cpu_crit {
4929 tempe 4496 temperature = <110000>;
4930 hyste 4497 hysteresis = <1000>;
4931 type 4498 type = "critical";
4932 }; 4499 };
4933 }; 4500 };
4934 4501
4935 cooling-maps { 4502 cooling-maps {
4936 map0 { 4503 map0 {
4937 trip 4504 trip = <&cpu7_top_alert0>;
4938 cooli 4505 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4506 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4507 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4508 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4509 };
4943 map1 { 4510 map1 {
4944 trip 4511 trip = <&cpu7_top_alert1>;
4945 cooli 4512 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4513 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4514 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4515 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4516 };
4950 }; 4517 };
4951 }; 4518 };
4952 4519
4953 cpu4-bottom-thermal { 4520 cpu4-bottom-thermal {
4954 polling-delay-passive 4521 polling-delay-passive = <250>;
>> 4522 polling-delay = <1000>;
4955 4523
4956 thermal-sensors = <&t 4524 thermal-sensors = <&tsens0 11>;
4957 4525
4958 trips { 4526 trips {
4959 cpu4_bottom_a 4527 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4528 temperature = <90000>;
4961 hyste 4529 hysteresis = <2000>;
4962 type 4530 type = "passive";
4963 }; 4531 };
4964 4532
4965 cpu4_bottom_a 4533 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4534 temperature = <95000>;
4967 hyste 4535 hysteresis = <2000>;
4968 type 4536 type = "passive";
4969 }; 4537 };
4970 4538
4971 cpu4_bottom_c !! 4539 cpu4_bottom_crit: cpu_crit {
4972 tempe 4540 temperature = <110000>;
4973 hyste 4541 hysteresis = <1000>;
4974 type 4542 type = "critical";
4975 }; 4543 };
4976 }; 4544 };
4977 4545
4978 cooling-maps { 4546 cooling-maps {
4979 map0 { 4547 map0 {
4980 trip 4548 trip = <&cpu4_bottom_alert0>;
4981 cooli 4549 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4550 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4551 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4552 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4553 };
4986 map1 { 4554 map1 {
4987 trip 4555 trip = <&cpu4_bottom_alert1>;
4988 cooli 4556 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4557 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4558 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4559 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4560 };
4993 }; 4561 };
4994 }; 4562 };
4995 4563
4996 cpu5-bottom-thermal { 4564 cpu5-bottom-thermal {
4997 polling-delay-passive 4565 polling-delay-passive = <250>;
>> 4566 polling-delay = <1000>;
4998 4567
4999 thermal-sensors = <&t 4568 thermal-sensors = <&tsens0 12>;
5000 4569
5001 trips { 4570 trips {
5002 cpu5_bottom_a 4571 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4572 temperature = <90000>;
5004 hyste 4573 hysteresis = <2000>;
5005 type 4574 type = "passive";
5006 }; 4575 };
5007 4576
5008 cpu5_bottom_a 4577 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4578 temperature = <95000>;
5010 hyste 4579 hysteresis = <2000>;
5011 type 4580 type = "passive";
5012 }; 4581 };
5013 4582
5014 cpu5_bottom_c !! 4583 cpu5_bottom_crit: cpu_crit {
5015 tempe 4584 temperature = <110000>;
5016 hyste 4585 hysteresis = <1000>;
5017 type 4586 type = "critical";
5018 }; 4587 };
5019 }; 4588 };
5020 4589
5021 cooling-maps { 4590 cooling-maps {
5022 map0 { 4591 map0 {
5023 trip 4592 trip = <&cpu5_bottom_alert0>;
5024 cooli 4593 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4594 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4595 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4596 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4597 };
5029 map1 { 4598 map1 {
5030 trip 4599 trip = <&cpu5_bottom_alert1>;
5031 cooli 4600 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4601 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4602 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4603 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4604 };
5036 }; 4605 };
5037 }; 4606 };
5038 4607
5039 cpu6-bottom-thermal { 4608 cpu6-bottom-thermal {
5040 polling-delay-passive 4609 polling-delay-passive = <250>;
>> 4610 polling-delay = <1000>;
5041 4611
5042 thermal-sensors = <&t 4612 thermal-sensors = <&tsens0 13>;
5043 4613
5044 trips { 4614 trips {
5045 cpu6_bottom_a 4615 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4616 temperature = <90000>;
5047 hyste 4617 hysteresis = <2000>;
5048 type 4618 type = "passive";
5049 }; 4619 };
5050 4620
5051 cpu6_bottom_a 4621 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4622 temperature = <95000>;
5053 hyste 4623 hysteresis = <2000>;
5054 type 4624 type = "passive";
5055 }; 4625 };
5056 4626
5057 cpu6_bottom_c !! 4627 cpu6_bottom_crit: cpu_crit {
5058 tempe 4628 temperature = <110000>;
5059 hyste 4629 hysteresis = <1000>;
5060 type 4630 type = "critical";
5061 }; 4631 };
5062 }; 4632 };
5063 4633
5064 cooling-maps { 4634 cooling-maps {
5065 map0 { 4635 map0 {
5066 trip 4636 trip = <&cpu6_bottom_alert0>;
5067 cooli 4637 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4638 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4639 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4640 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4641 };
5072 map1 { 4642 map1 {
5073 trip 4643 trip = <&cpu6_bottom_alert1>;
5074 cooli 4644 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4645 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4646 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4647 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4648 };
5079 }; 4649 };
5080 }; 4650 };
5081 4651
5082 cpu7-bottom-thermal { 4652 cpu7-bottom-thermal {
5083 polling-delay-passive 4653 polling-delay-passive = <250>;
>> 4654 polling-delay = <1000>;
5084 4655
5085 thermal-sensors = <&t 4656 thermal-sensors = <&tsens0 14>;
5086 4657
5087 trips { 4658 trips {
5088 cpu7_bottom_a 4659 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4660 temperature = <90000>;
5090 hyste 4661 hysteresis = <2000>;
5091 type 4662 type = "passive";
5092 }; 4663 };
5093 4664
5094 cpu7_bottom_a 4665 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4666 temperature = <95000>;
5096 hyste 4667 hysteresis = <2000>;
5097 type 4668 type = "passive";
5098 }; 4669 };
5099 4670
5100 cpu7_bottom_c !! 4671 cpu7_bottom_crit: cpu_crit {
5101 tempe 4672 temperature = <110000>;
5102 hyste 4673 hysteresis = <1000>;
5103 type 4674 type = "critical";
5104 }; 4675 };
5105 }; 4676 };
5106 4677
5107 cooling-maps { 4678 cooling-maps {
5108 map0 { 4679 map0 {
5109 trip 4680 trip = <&cpu7_bottom_alert0>;
5110 cooli 4681 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4682 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4683 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4684 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4685 };
5115 map1 { 4686 map1 {
5116 trip 4687 trip = <&cpu7_bottom_alert1>;
5117 cooli 4688 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4689 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4690 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4691 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4692 };
5122 }; 4693 };
5123 }; 4694 };
5124 4695
5125 aoss0-thermal { 4696 aoss0-thermal {
5126 polling-delay-passive 4697 polling-delay-passive = <250>;
>> 4698 polling-delay = <1000>;
5127 4699
5128 thermal-sensors = <&t 4700 thermal-sensors = <&tsens0 0>;
5129 4701
5130 trips { 4702 trips {
5131 aoss0_alert0: 4703 aoss0_alert0: trip-point0 {
5132 tempe 4704 temperature = <90000>;
5133 hyste 4705 hysteresis = <2000>;
5134 type 4706 type = "hot";
5135 }; 4707 };
5136 }; 4708 };
5137 }; 4709 };
5138 4710
5139 cluster0-thermal { 4711 cluster0-thermal {
5140 polling-delay-passive 4712 polling-delay-passive = <250>;
>> 4713 polling-delay = <1000>;
5141 4714
5142 thermal-sensors = <&t 4715 thermal-sensors = <&tsens0 5>;
5143 4716
5144 trips { 4717 trips {
5145 cluster0_aler 4718 cluster0_alert0: trip-point0 {
5146 tempe 4719 temperature = <90000>;
5147 hyste 4720 hysteresis = <2000>;
5148 type 4721 type = "hot";
5149 }; 4722 };
5150 cluster0_crit !! 4723 cluster0_crit: cluster0_crit {
5151 tempe 4724 temperature = <110000>;
5152 hyste 4725 hysteresis = <2000>;
5153 type 4726 type = "critical";
5154 }; 4727 };
5155 }; 4728 };
5156 }; 4729 };
5157 4730
5158 cluster1-thermal { 4731 cluster1-thermal {
5159 polling-delay-passive 4732 polling-delay-passive = <250>;
>> 4733 polling-delay = <1000>;
5160 4734
5161 thermal-sensors = <&t 4735 thermal-sensors = <&tsens0 6>;
5162 4736
5163 trips { 4737 trips {
5164 cluster1_aler 4738 cluster1_alert0: trip-point0 {
5165 tempe 4739 temperature = <90000>;
5166 hyste 4740 hysteresis = <2000>;
5167 type 4741 type = "hot";
5168 }; 4742 };
5169 cluster1_crit !! 4743 cluster1_crit: cluster1_crit {
5170 tempe 4744 temperature = <110000>;
5171 hyste 4745 hysteresis = <2000>;
5172 type 4746 type = "critical";
5173 }; 4747 };
5174 }; 4748 };
5175 }; 4749 };
5176 4750
5177 gpu-top-thermal { 4751 gpu-top-thermal {
5178 polling-delay-passive 4752 polling-delay-passive = <250>;
>> 4753 polling-delay = <1000>;
5179 4754
5180 thermal-sensors = <&t 4755 thermal-sensors = <&tsens0 15>;
5181 4756
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4757 trips {
5190 gpu_top_alert !! 4758 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4759 temperature = <90000>;
5198 hyste !! 4760 hysteresis = <2000>;
5199 type 4761 type = "hot";
5200 }; 4762 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4763 };
5208 }; 4764 };
5209 4765
5210 aoss1-thermal { 4766 aoss1-thermal {
5211 polling-delay-passive 4767 polling-delay-passive = <250>;
>> 4768 polling-delay = <1000>;
5212 4769
5213 thermal-sensors = <&t 4770 thermal-sensors = <&tsens1 0>;
5214 4771
5215 trips { 4772 trips {
5216 aoss1_alert0: 4773 aoss1_alert0: trip-point0 {
5217 tempe 4774 temperature = <90000>;
5218 hyste 4775 hysteresis = <2000>;
5219 type 4776 type = "hot";
5220 }; 4777 };
5221 }; 4778 };
5222 }; 4779 };
5223 4780
5224 wlan-thermal { 4781 wlan-thermal {
5225 polling-delay-passive 4782 polling-delay-passive = <250>;
>> 4783 polling-delay = <1000>;
5226 4784
5227 thermal-sensors = <&t 4785 thermal-sensors = <&tsens1 1>;
5228 4786
5229 trips { 4787 trips {
5230 wlan_alert0: 4788 wlan_alert0: trip-point0 {
5231 tempe 4789 temperature = <90000>;
5232 hyste 4790 hysteresis = <2000>;
5233 type 4791 type = "hot";
5234 }; 4792 };
5235 }; 4793 };
5236 }; 4794 };
5237 4795
5238 video-thermal { 4796 video-thermal {
5239 polling-delay-passive 4797 polling-delay-passive = <250>;
>> 4798 polling-delay = <1000>;
5240 4799
5241 thermal-sensors = <&t 4800 thermal-sensors = <&tsens1 2>;
5242 4801
5243 trips { 4802 trips {
5244 video_alert0: 4803 video_alert0: trip-point0 {
5245 tempe 4804 temperature = <90000>;
5246 hyste 4805 hysteresis = <2000>;
5247 type 4806 type = "hot";
5248 }; 4807 };
5249 }; 4808 };
5250 }; 4809 };
5251 4810
5252 mem-thermal { 4811 mem-thermal {
5253 polling-delay-passive 4812 polling-delay-passive = <250>;
>> 4813 polling-delay = <1000>;
5254 4814
5255 thermal-sensors = <&t 4815 thermal-sensors = <&tsens1 3>;
5256 4816
5257 trips { 4817 trips {
5258 mem_alert0: t 4818 mem_alert0: trip-point0 {
5259 tempe 4819 temperature = <90000>;
5260 hyste 4820 hysteresis = <2000>;
5261 type 4821 type = "hot";
5262 }; 4822 };
5263 }; 4823 };
5264 }; 4824 };
5265 4825
5266 q6-hvx-thermal { 4826 q6-hvx-thermal {
5267 polling-delay-passive 4827 polling-delay-passive = <250>;
>> 4828 polling-delay = <1000>;
5268 4829
5269 thermal-sensors = <&t 4830 thermal-sensors = <&tsens1 4>;
5270 4831
5271 trips { 4832 trips {
5272 q6_hvx_alert0 4833 q6_hvx_alert0: trip-point0 {
5273 tempe 4834 temperature = <90000>;
5274 hyste 4835 hysteresis = <2000>;
5275 type 4836 type = "hot";
5276 }; 4837 };
5277 }; 4838 };
5278 }; 4839 };
5279 4840
5280 camera-thermal { 4841 camera-thermal {
5281 polling-delay-passive 4842 polling-delay-passive = <250>;
>> 4843 polling-delay = <1000>;
5282 4844
5283 thermal-sensors = <&t 4845 thermal-sensors = <&tsens1 5>;
5284 4846
5285 trips { 4847 trips {
5286 camera_alert0 4848 camera_alert0: trip-point0 {
5287 tempe 4849 temperature = <90000>;
5288 hyste 4850 hysteresis = <2000>;
5289 type 4851 type = "hot";
5290 }; 4852 };
5291 }; 4853 };
5292 }; 4854 };
5293 4855
5294 compute-thermal { 4856 compute-thermal {
5295 polling-delay-passive 4857 polling-delay-passive = <250>;
>> 4858 polling-delay = <1000>;
5296 4859
5297 thermal-sensors = <&t 4860 thermal-sensors = <&tsens1 6>;
5298 4861
5299 trips { 4862 trips {
5300 compute_alert 4863 compute_alert0: trip-point0 {
5301 tempe 4864 temperature = <90000>;
5302 hyste 4865 hysteresis = <2000>;
5303 type 4866 type = "hot";
5304 }; 4867 };
5305 }; 4868 };
5306 }; 4869 };
5307 4870
5308 modem-thermal { 4871 modem-thermal {
5309 polling-delay-passive 4872 polling-delay-passive = <250>;
>> 4873 polling-delay = <1000>;
5310 4874
5311 thermal-sensors = <&t 4875 thermal-sensors = <&tsens1 7>;
5312 4876
5313 trips { 4877 trips {
5314 modem_alert0: 4878 modem_alert0: trip-point0 {
5315 tempe 4879 temperature = <90000>;
5316 hyste 4880 hysteresis = <2000>;
5317 type 4881 type = "hot";
5318 }; 4882 };
5319 }; 4883 };
5320 }; 4884 };
5321 4885
5322 npu-thermal { 4886 npu-thermal {
5323 polling-delay-passive 4887 polling-delay-passive = <250>;
>> 4888 polling-delay = <1000>;
5324 4889
5325 thermal-sensors = <&t 4890 thermal-sensors = <&tsens1 8>;
5326 4891
5327 trips { 4892 trips {
5328 npu_alert0: t 4893 npu_alert0: trip-point0 {
5329 tempe 4894 temperature = <90000>;
5330 hyste 4895 hysteresis = <2000>;
5331 type 4896 type = "hot";
5332 }; 4897 };
5333 }; 4898 };
5334 }; 4899 };
5335 4900
5336 modem-vec-thermal { 4901 modem-vec-thermal {
5337 polling-delay-passive 4902 polling-delay-passive = <250>;
>> 4903 polling-delay = <1000>;
5338 4904
5339 thermal-sensors = <&t 4905 thermal-sensors = <&tsens1 9>;
5340 4906
5341 trips { 4907 trips {
5342 modem_vec_ale 4908 modem_vec_alert0: trip-point0 {
5343 tempe 4909 temperature = <90000>;
5344 hyste 4910 hysteresis = <2000>;
5345 type 4911 type = "hot";
5346 }; 4912 };
5347 }; 4913 };
5348 }; 4914 };
5349 4915
5350 modem-scl-thermal { 4916 modem-scl-thermal {
5351 polling-delay-passive 4917 polling-delay-passive = <250>;
>> 4918 polling-delay = <1000>;
5352 4919
5353 thermal-sensors = <&t 4920 thermal-sensors = <&tsens1 10>;
5354 4921
5355 trips { 4922 trips {
5356 modem_scl_ale 4923 modem_scl_alert0: trip-point0 {
5357 tempe 4924 temperature = <90000>;
5358 hyste 4925 hysteresis = <2000>;
5359 type 4926 type = "hot";
5360 }; 4927 };
5361 }; 4928 };
5362 }; 4929 };
5363 4930
5364 gpu-bottom-thermal { 4931 gpu-bottom-thermal {
5365 polling-delay-passive 4932 polling-delay-passive = <250>;
>> 4933 polling-delay = <1000>;
5366 4934
5367 thermal-sensors = <&t 4935 thermal-sensors = <&tsens1 11>;
5368 4936
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 4937 trips {
5377 gpu_bottom_al !! 4938 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 4939 temperature = <90000>;
5385 hyste !! 4940 hysteresis = <2000>;
5386 type 4941 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 4942 };
5394 }; 4943 };
5395 }; 4944 };
5396 }; 4945 };
5397 }; 4946 };
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