1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> 8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> 10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 18 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 19 #include <dt-bindings/thermal/thermal.h>
22 20
23 / { 21 / {
24 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
25 23
26 #address-cells = <2>; 24 #address-cells = <2>;
27 #size-cells = <2>; 25 #size-cells = <2>;
28 26
29 chosen { }; 27 chosen { };
30 28
31 clocks { 29 clocks {
32 xo_board: xo-board { 30 xo_board: xo-board {
33 compatible = "fixed-cl 31 compatible = "fixed-clock";
34 #clock-cells = <0>; 32 #clock-cells = <0>;
35 clock-frequency = <384 33 clock-frequency = <38400000>;
36 clock-output-names = " 34 clock-output-names = "xo_board";
37 }; 35 };
38 36
39 sleep_clk: sleep-clk { 37 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 38 compatible = "fixed-clock";
41 #clock-cells = <0>; 39 #clock-cells = <0>;
42 clock-frequency = <327 40 clock-frequency = <32764>;
43 clock-output-names = " 41 clock-output-names = "sleep_clk";
44 }; 42 };
45 }; 43 };
46 44
47 cpus { 45 cpus {
48 #address-cells = <2>; 46 #address-cells = <2>;
49 #size-cells = <0>; 47 #size-cells = <0>;
50 48
51 CPU0: cpu@0 { 49 CPU0: cpu@0 {
52 device_type = "cpu"; 50 device_type = "cpu";
53 compatible = "qcom,kry 51 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 52 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 53 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci" 54 enable-method = "psci";
57 capacity-dmips-mhz = < 55 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 56 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 57 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 58 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 59 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ 60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
63 <&osm_ 61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 62 power-domains = <&CPU_PD0>;
65 power-domain-names = " 63 power-domain-names = "psci";
66 #cooling-cells = <2>; 64 #cooling-cells = <2>;
67 L2_0: l2-cache { 65 L2_0: l2-cache {
68 compatible = " 66 compatible = "cache";
69 cache-level = 67 cache-level = <2>;
70 cache-unified; 68 cache-unified;
71 next-level-cac 69 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 70 L3_0: l3-cache {
73 compat 71 compatible = "cache";
74 cache- 72 cache-level = <3>;
75 cache- 73 cache-unified;
76 }; 74 };
77 }; 75 };
78 }; 76 };
79 77
80 CPU1: cpu@100 { 78 CPU1: cpu@100 {
81 device_type = "cpu"; 79 device_type = "cpu";
82 compatible = "qcom,kry 80 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 81 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 82 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci" 83 enable-method = "psci";
86 capacity-dmips-mhz = < 84 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 85 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 86 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 87 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 88 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 89 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
92 <&osm_ 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 91 power-domains = <&CPU_PD1>;
94 power-domain-names = " 92 power-domain-names = "psci";
95 #cooling-cells = <2>; 93 #cooling-cells = <2>;
96 L2_100: l2-cache { 94 L2_100: l2-cache {
97 compatible = " 95 compatible = "cache";
98 cache-level = 96 cache-level = <2>;
99 cache-unified; 97 cache-unified;
100 next-level-cac 98 next-level-cache = <&L3_0>;
101 }; 99 };
102 }; 100 };
103 101
104 CPU2: cpu@200 { 102 CPU2: cpu@200 {
105 device_type = "cpu"; 103 device_type = "cpu";
106 compatible = "qcom,kry 104 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 105 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw 106 clocks = <&cpufreq_hw 0>;
109 enable-method = "psci" 107 enable-method = "psci";
110 capacity-dmips-mhz = < 108 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 109 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 110 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 111 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 112 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ 113 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 <&osm_ 114 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 115 power-domains = <&CPU_PD2>;
118 power-domain-names = " 116 power-domain-names = "psci";
119 #cooling-cells = <2>; 117 #cooling-cells = <2>;
120 L2_200: l2-cache { 118 L2_200: l2-cache {
121 compatible = " 119 compatible = "cache";
122 cache-level = 120 cache-level = <2>;
123 cache-unified; 121 cache-unified;
124 next-level-cac 122 next-level-cache = <&L3_0>;
125 }; 123 };
126 }; 124 };
127 125
128 CPU3: cpu@300 { 126 CPU3: cpu@300 {
129 device_type = "cpu"; 127 device_type = "cpu";
130 compatible = "qcom,kry 128 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 129 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 130 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci" 131 enable-method = "psci";
134 capacity-dmips-mhz = < 132 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 133 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 134 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 135 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 136 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ 137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
140 <&osm_ 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 139 power-domains = <&CPU_PD3>;
142 power-domain-names = " 140 power-domain-names = "psci";
143 #cooling-cells = <2>; 141 #cooling-cells = <2>;
144 L2_300: l2-cache { 142 L2_300: l2-cache {
145 compatible = " 143 compatible = "cache";
146 cache-level = 144 cache-level = <2>;
147 cache-unified; 145 cache-unified;
148 next-level-cac 146 next-level-cache = <&L3_0>;
149 }; 147 };
150 }; 148 };
151 149
152 CPU4: cpu@400 { 150 CPU4: cpu@400 {
153 device_type = "cpu"; 151 device_type = "cpu";
154 compatible = "qcom,kry 152 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 153 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw 154 clocks = <&cpufreq_hw 1>;
157 enable-method = "psci" 155 enable-method = "psci";
158 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 157 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 158 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 159 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 160 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ 161 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
164 <&osm_ 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 163 power-domains = <&CPU_PD4>;
166 power-domain-names = " 164 power-domain-names = "psci";
167 #cooling-cells = <2>; 165 #cooling-cells = <2>;
168 L2_400: l2-cache { 166 L2_400: l2-cache {
169 compatible = " 167 compatible = "cache";
170 cache-level = 168 cache-level = <2>;
171 cache-unified; 169 cache-unified;
172 next-level-cac 170 next-level-cache = <&L3_0>;
173 }; 171 };
174 }; 172 };
175 173
176 CPU5: cpu@500 { 174 CPU5: cpu@500 {
177 device_type = "cpu"; 175 device_type = "cpu";
178 compatible = "qcom,kry 176 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 177 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw 178 clocks = <&cpufreq_hw 1>;
181 enable-method = "psci" 179 enable-method = "psci";
182 capacity-dmips-mhz = < 180 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 181 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 182 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 183 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 184 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ 185 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
188 <&osm_ 186 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 187 power-domains = <&CPU_PD5>;
190 power-domain-names = " 188 power-domain-names = "psci";
191 #cooling-cells = <2>; 189 #cooling-cells = <2>;
192 L2_500: l2-cache { 190 L2_500: l2-cache {
193 compatible = " 191 compatible = "cache";
194 cache-level = 192 cache-level = <2>;
195 cache-unified; 193 cache-unified;
196 next-level-cac 194 next-level-cache = <&L3_0>;
197 }; 195 };
198 }; 196 };
199 197
200 CPU6: cpu@600 { 198 CPU6: cpu@600 {
201 device_type = "cpu"; 199 device_type = "cpu";
202 compatible = "qcom,kry 200 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 201 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw 202 clocks = <&cpufreq_hw 1>;
205 enable-method = "psci" 203 enable-method = "psci";
206 capacity-dmips-mhz = < 204 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 205 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 206 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 207 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 208 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ 209 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
212 <&osm_ 210 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 211 power-domains = <&CPU_PD6>;
214 power-domain-names = " 212 power-domain-names = "psci";
215 #cooling-cells = <2>; 213 #cooling-cells = <2>;
216 L2_600: l2-cache { 214 L2_600: l2-cache {
217 compatible = " 215 compatible = "cache";
218 cache-level = 216 cache-level = <2>;
219 cache-unified; 217 cache-unified;
220 next-level-cac 218 next-level-cache = <&L3_0>;
221 }; 219 };
222 }; 220 };
223 221
224 CPU7: cpu@700 { 222 CPU7: cpu@700 {
225 device_type = "cpu"; 223 device_type = "cpu";
226 compatible = "qcom,kry 224 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 225 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw 226 clocks = <&cpufreq_hw 2>;
229 enable-method = "psci" 227 enable-method = "psci";
230 capacity-dmips-mhz = < 228 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 229 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 230 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 231 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 232 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ 233 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
236 <&osm_ 234 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 235 power-domains = <&CPU_PD7>;
238 power-domain-names = " 236 power-domain-names = "psci";
239 #cooling-cells = <2>; 237 #cooling-cells = <2>;
240 L2_700: l2-cache { 238 L2_700: l2-cache {
241 compatible = " 239 compatible = "cache";
242 cache-level = 240 cache-level = <2>;
243 cache-unified; 241 cache-unified;
244 next-level-cac 242 next-level-cache = <&L3_0>;
245 }; 243 };
246 }; 244 };
247 245
248 cpu-map { 246 cpu-map {
249 cluster0 { 247 cluster0 {
250 core0 { 248 core0 {
251 cpu = 249 cpu = <&CPU0>;
252 }; 250 };
253 251
254 core1 { 252 core1 {
255 cpu = 253 cpu = <&CPU1>;
256 }; 254 };
257 255
258 core2 { 256 core2 {
259 cpu = 257 cpu = <&CPU2>;
260 }; 258 };
261 259
262 core3 { 260 core3 {
263 cpu = 261 cpu = <&CPU3>;
264 }; 262 };
265 263
266 core4 { 264 core4 {
267 cpu = 265 cpu = <&CPU4>;
268 }; 266 };
269 267
270 core5 { 268 core5 {
271 cpu = 269 cpu = <&CPU5>;
272 }; 270 };
273 271
274 core6 { 272 core6 {
275 cpu = 273 cpu = <&CPU6>;
276 }; 274 };
277 275
278 core7 { 276 core7 {
279 cpu = 277 cpu = <&CPU7>;
280 }; 278 };
281 }; 279 };
282 }; 280 };
283 281
284 idle-states { 282 idle-states {
285 entry-method = "psci"; 283 entry-method = "psci";
286 284
287 LITTLE_CPU_SLEEP_0: cp 285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 286 compatible = "arm,idle-state";
289 idle-state-nam 287 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 288 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 289 entry-latency-us = <355>;
292 exit-latency-u 290 exit-latency-us = <909>;
293 min-residency- 291 min-residency-us = <3934>;
294 local-timer-st 292 local-timer-stop;
295 }; 293 };
296 294
297 BIG_CPU_SLEEP_0: cpu-s 295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 296 compatible = "arm,idle-state";
299 idle-state-nam 297 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 298 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 299 entry-latency-us = <241>;
302 exit-latency-u 300 exit-latency-us = <1461>;
303 min-residency- 301 min-residency-us = <4488>;
304 local-timer-st 302 local-timer-stop;
305 }; 303 };
306 }; 304 };
307 305
308 domain-idle-states { 306 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 307 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 308 compatible = "domain-idle-state";
311 arm,psci-suspe 309 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 310 entry-latency-us = <3263>;
313 exit-latency-u 311 exit-latency-us = <6562>;
314 min-residency- 312 min-residency-us = <9987>;
315 }; 313 };
316 }; 314 };
317 }; 315 };
318 316
319 cpu0_opp_table: opp-table-cpu0 { 317 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points 318 compatible = "operating-points-v2";
321 opp-shared; 319 opp-shared;
322 320
323 cpu0_opp1: opp-300000000 { 321 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 322 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 323 opp-peak-kBps = <800000 9600000>;
326 }; 324 };
327 325
328 cpu0_opp2: opp-403200000 { 326 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 327 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 328 opp-peak-kBps = <800000 9600000>;
331 }; 329 };
332 330
333 cpu0_opp3: opp-499200000 { 331 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 332 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 333 opp-peak-kBps = <800000 12902400>;
336 }; 334 };
337 335
338 cpu0_opp4: opp-576000000 { 336 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 337 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 338 opp-peak-kBps = <800000 12902400>;
341 }; 339 };
342 340
343 cpu0_opp5: opp-672000000 { 341 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 342 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 343 opp-peak-kBps = <800000 15974400>;
346 }; 344 };
347 345
348 cpu0_opp6: opp-768000000 { 346 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 347 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 348 opp-peak-kBps = <1804000 19660800>;
351 }; 349 };
352 350
353 cpu0_opp7: opp-844800000 { 351 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 352 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 353 opp-peak-kBps = <1804000 19660800>;
356 }; 354 };
357 355
358 cpu0_opp8: opp-940800000 { 356 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 357 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 358 opp-peak-kBps = <1804000 22732800>;
361 }; 359 };
362 360
363 cpu0_opp9: opp-1036800000 { 361 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 362 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 363 opp-peak-kBps = <1804000 22732800>;
366 }; 364 };
367 365
368 cpu0_opp10: opp-1113600000 { 366 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 367 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 368 opp-peak-kBps = <2188000 25804800>;
371 }; 369 };
372 370
373 cpu0_opp11: opp-1209600000 { 371 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 372 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 373 opp-peak-kBps = <2188000 31948800>;
376 }; 374 };
377 375
378 cpu0_opp12: opp-1305600000 { 376 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 377 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 378 opp-peak-kBps = <3072000 31948800>;
381 }; 379 };
382 380
383 cpu0_opp13: opp-1382400000 { 381 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 382 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 383 opp-peak-kBps = <3072000 31948800>;
386 }; 384 };
387 385
388 cpu0_opp14: opp-1478400000 { 386 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 387 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 388 opp-peak-kBps = <3072000 31948800>;
391 }; 389 };
392 390
393 cpu0_opp15: opp-1555200000 { 391 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 392 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 393 opp-peak-kBps = <3072000 40550400>;
396 }; 394 };
397 395
398 cpu0_opp16: opp-1632000000 { 396 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 397 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 398 opp-peak-kBps = <3072000 40550400>;
401 }; 399 };
402 400
403 cpu0_opp17: opp-1708800000 { 401 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 402 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 403 opp-peak-kBps = <3072000 43008000>;
406 }; 404 };
407 405
408 cpu0_opp18: opp-1785600000 { 406 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 407 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 408 opp-peak-kBps = <3072000 43008000>;
411 }; 409 };
412 }; 410 };
413 411
414 cpu4_opp_table: opp-table-cpu4 { 412 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points 413 compatible = "operating-points-v2";
416 opp-shared; 414 opp-shared;
417 415
418 cpu4_opp1: opp-710400000 { 416 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 417 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 418 opp-peak-kBps = <1804000 15974400>;
421 }; 419 };
422 420
423 cpu4_opp2: opp-825600000 { 421 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 422 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 423 opp-peak-kBps = <2188000 19660800>;
426 }; 424 };
427 425
428 cpu4_opp3: opp-940800000 { 426 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 427 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 428 opp-peak-kBps = <2188000 22732800>;
431 }; 429 };
432 430
433 cpu4_opp4: opp-1056000000 { 431 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 432 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 433 opp-peak-kBps = <3072000 25804800>;
436 }; 434 };
437 435
438 cpu4_opp5: opp-1171200000 { 436 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 437 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 438 opp-peak-kBps = <3072000 31948800>;
441 }; 439 };
442 440
443 cpu4_opp6: opp-1286400000 { 441 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 442 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 443 opp-peak-kBps = <4068000 31948800>;
446 }; 444 };
447 445
448 cpu4_opp7: opp-1401600000 { 446 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 447 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 448 opp-peak-kBps = <4068000 31948800>;
451 }; 449 };
452 450
453 cpu4_opp8: opp-1497600000 { 451 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 452 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 453 opp-peak-kBps = <4068000 40550400>;
456 }; 454 };
457 455
458 cpu4_opp9: opp-1612800000 { 456 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 457 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 458 opp-peak-kBps = <4068000 40550400>;
461 }; 459 };
462 460
463 cpu4_opp10: opp-1708800000 { 461 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 462 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 463 opp-peak-kBps = <4068000 43008000>;
466 }; 464 };
467 465
468 cpu4_opp11: opp-1804800000 { 466 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 467 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 468 opp-peak-kBps = <6220000 43008000>;
471 }; 469 };
472 470
473 cpu4_opp12: opp-1920000000 { 471 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 472 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 473 opp-peak-kBps = <6220000 49152000>;
476 }; 474 };
477 475
478 cpu4_opp13: opp-2016000000 { 476 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 477 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 478 opp-peak-kBps = <7216000 49152000>;
481 }; 479 };
482 480
483 cpu4_opp14: opp-2131200000 { 481 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 482 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 483 opp-peak-kBps = <8368000 49152000>;
486 }; 484 };
487 485
488 cpu4_opp15: opp-2227200000 { 486 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 487 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 488 opp-peak-kBps = <8368000 51609600>;
491 }; 489 };
492 490
493 cpu4_opp16: opp-2323200000 { 491 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 492 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 493 opp-peak-kBps = <8368000 51609600>;
496 }; 494 };
497 495
498 cpu4_opp17: opp-2419200000 { 496 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 497 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 498 opp-peak-kBps = <8368000 51609600>;
501 }; 499 };
502 }; 500 };
503 501
504 cpu7_opp_table: opp-table-cpu7 { 502 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points 503 compatible = "operating-points-v2";
506 opp-shared; 504 opp-shared;
507 505
508 cpu7_opp1: opp-825600000 { 506 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 507 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 508 opp-peak-kBps = <2188000 19660800>;
511 }; 509 };
512 510
513 cpu7_opp2: opp-940800000 { 511 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 512 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 513 opp-peak-kBps = <2188000 22732800>;
516 }; 514 };
517 515
518 cpu7_opp3: opp-1056000000 { 516 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 517 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 518 opp-peak-kBps = <3072000 25804800>;
521 }; 519 };
522 520
523 cpu7_opp4: opp-1171200000 { 521 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 522 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 523 opp-peak-kBps = <3072000 31948800>;
526 }; 524 };
527 525
528 cpu7_opp5: opp-1286400000 { 526 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 527 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 528 opp-peak-kBps = <4068000 31948800>;
531 }; 529 };
532 530
533 cpu7_opp6: opp-1401600000 { 531 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 532 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 533 opp-peak-kBps = <4068000 31948800>;
536 }; 534 };
537 535
538 cpu7_opp7: opp-1497600000 { 536 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 537 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 538 opp-peak-kBps = <4068000 40550400>;
541 }; 539 };
542 540
543 cpu7_opp8: opp-1612800000 { 541 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 542 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 543 opp-peak-kBps = <4068000 40550400>;
546 }; 544 };
547 545
548 cpu7_opp9: opp-1708800000 { 546 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 547 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 548 opp-peak-kBps = <4068000 43008000>;
551 }; 549 };
552 550
553 cpu7_opp10: opp-1804800000 { 551 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 552 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 553 opp-peak-kBps = <6220000 43008000>;
556 }; 554 };
557 555
558 cpu7_opp11: opp-1920000000 { 556 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 557 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 558 opp-peak-kBps = <6220000 49152000>;
561 }; 559 };
562 560
563 cpu7_opp12: opp-2016000000 { 561 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 562 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 563 opp-peak-kBps = <7216000 49152000>;
566 }; 564 };
567 565
568 cpu7_opp13: opp-2131200000 { 566 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 567 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 568 opp-peak-kBps = <8368000 49152000>;
571 }; 569 };
572 570
573 cpu7_opp14: opp-2227200000 { 571 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 572 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 573 opp-peak-kBps = <8368000 51609600>;
576 }; 574 };
577 575
578 cpu7_opp15: opp-2323200000 { 576 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 577 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 578 opp-peak-kBps = <8368000 51609600>;
581 }; 579 };
582 580
583 cpu7_opp16: opp-2419200000 { 581 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 582 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 583 opp-peak-kBps = <8368000 51609600>;
586 }; 584 };
587 585
588 cpu7_opp17: opp-2534400000 { 586 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 587 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 588 opp-peak-kBps = <8368000 51609600>;
591 }; 589 };
592 590
593 cpu7_opp18: opp-2649600000 { 591 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 592 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 593 opp-peak-kBps = <8368000 51609600>;
596 }; 594 };
597 595
598 cpu7_opp19: opp-2745600000 { 596 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 597 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 598 opp-peak-kBps = <8368000 51609600>;
601 }; 599 };
602 600
603 cpu7_opp20: opp-2841600000 { 601 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 602 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 603 opp-peak-kBps = <8368000 51609600>;
606 }; 604 };
607 }; 605 };
608 606
609 firmware { 607 firmware {
610 scm: scm { 608 scm: scm {
611 compatible = "qcom,scm 609 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 610 #reset-cells = <1>;
613 }; 611 };
614 }; 612 };
615 613
616 memory@80000000 { 614 memory@80000000 {
617 device_type = "memory"; 615 device_type = "memory";
618 /* We expect the bootloader to 616 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 617 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 618 };
621 619
622 pmu { 620 pmu {
623 compatible = "arm,armv8-pmuv3" 621 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 622 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 623 };
626 624
627 psci { 625 psci {
628 compatible = "arm,psci-1.0"; 626 compatible = "arm,psci-1.0";
629 method = "smc"; 627 method = "smc";
630 628
631 CPU_PD0: power-domain-cpu0 { 629 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells = 630 #power-domain-cells = <0>;
633 power-domains = <&CLUS 631 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 632 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 633 };
636 634
637 CPU_PD1: power-domain-cpu1 { 635 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells = 636 #power-domain-cells = <0>;
639 power-domains = <&CLUS 637 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 638 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 639 };
642 640
643 CPU_PD2: power-domain-cpu2 { 641 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells = 642 #power-domain-cells = <0>;
645 power-domains = <&CLUS 643 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 644 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 645 };
648 646
649 CPU_PD3: power-domain-cpu3 { 647 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells = 648 #power-domain-cells = <0>;
651 power-domains = <&CLUS 649 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 650 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 651 };
654 652
655 CPU_PD4: power-domain-cpu4 { 653 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells = 654 #power-domain-cells = <0>;
657 power-domains = <&CLUS 655 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 656 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 657 };
660 658
661 CPU_PD5: power-domain-cpu5 { 659 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells = 660 #power-domain-cells = <0>;
663 power-domains = <&CLUS 661 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 662 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 663 };
666 664
667 CPU_PD6: power-domain-cpu6 { 665 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells = 666 #power-domain-cells = <0>;
669 power-domains = <&CLUS 667 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 668 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 669 };
672 670
673 CPU_PD7: power-domain-cpu7 { 671 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells = 672 #power-domain-cells = <0>;
675 power-domains = <&CLUS 673 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 674 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 675 };
678 676
679 CLUSTER_PD: power-domain-cpu-c 677 CLUSTER_PD: power-domain-cpu-cluster0 {
680 #power-domain-cells = 678 #power-domain-cells = <0>;
681 domain-idle-states = < 679 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 680 };
683 }; 681 };
684 682
685 reserved-memory { 683 reserved-memory {
686 #address-cells = <2>; 684 #address-cells = <2>;
687 #size-cells = <2>; 685 #size-cells = <2>;
688 ranges; 686 ranges;
689 687
690 hyp_mem: memory@85700000 { 688 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 689 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 690 no-map;
693 }; 691 };
694 692
695 xbl_mem: memory@85d00000 { 693 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 694 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 695 no-map;
698 }; 696 };
699 697
700 aop_mem: memory@85f00000 { 698 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 699 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 700 no-map;
703 }; 701 };
704 702
705 aop_cmd_db: memory@85f20000 { 703 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 704 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 705 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 706 no-map;
709 }; 707 };
710 708
711 smem_mem: memory@86000000 { 709 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 710 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 711 no-map;
714 }; 712 };
715 713
716 tz_mem: memory@86200000 { 714 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 715 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 716 no-map;
719 }; 717 };
720 718
721 rmtfs_mem: memory@89b00000 { 719 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 720 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 721 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 722 no-map;
725 723
726 qcom,client-id = <1>; 724 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ 725 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
728 }; 726 };
729 727
730 camera_mem: memory@8b700000 { 728 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 729 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 730 no-map;
733 }; 731 };
734 732
735 wlan_mem: memory@8bc00000 { 733 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 734 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 735 no-map;
738 }; 736 };
739 737
740 npu_mem: memory@8bd80000 { 738 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 739 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 740 no-map;
743 }; 741 };
744 742
745 adsp_mem: memory@8be00000 { 743 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 744 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 745 no-map;
748 }; 746 };
749 747
750 mpss_mem: memory@8d800000 { 748 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 749 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 750 no-map;
753 }; 751 };
754 752
755 venus_mem: memory@96e00000 { 753 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 754 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 755 no-map;
758 }; 756 };
759 757
760 slpi_mem: memory@97300000 { 758 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 759 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 760 no-map;
763 }; 761 };
764 762
765 ipa_fw_mem: memory@98700000 { 763 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 764 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 765 no-map;
768 }; 766 };
769 767
770 ipa_gsi_mem: memory@98710000 { 768 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 769 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 770 no-map;
773 }; 771 };
774 772
775 gpu_mem: memory@98715000 { 773 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 774 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 775 no-map;
778 }; 776 };
779 777
780 spss_mem: memory@98800000 { 778 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 779 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 780 no-map;
783 }; 781 };
784 782
785 cdsp_mem: memory@98900000 { 783 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 784 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 785 no-map;
788 }; 786 };
789 787
790 qseecom_mem: memory@9e400000 { 788 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 789 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 790 no-map;
793 }; 791 };
794 }; 792 };
795 793
796 smem { 794 smem {
797 compatible = "qcom,smem"; 795 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 796 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 797 hwlocks = <&tcsr_mutex 3>;
800 }; 798 };
801 799
802 smp2p-cdsp { 800 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 801 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 802 qcom,smem = <94>, <432>;
805 803
806 interrupts = <GIC_SPI 576 IRQ_ 804 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 805
808 mboxes = <&apss_shared 6>; 806 mboxes = <&apss_shared 6>;
809 807
810 qcom,local-pid = <0>; 808 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 809 qcom,remote-pid = <5>;
812 810
813 cdsp_smp2p_out: master-kernel 811 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 812 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 813 #qcom,smem-state-cells = <1>;
816 }; 814 };
817 815
818 cdsp_smp2p_in: slave-kernel { 816 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 817 qcom,entry-name = "slave-kernel";
820 818
821 interrupt-controller; 819 interrupt-controller;
822 #interrupt-cells = <2> 820 #interrupt-cells = <2>;
823 }; 821 };
824 }; 822 };
825 823
826 smp2p-lpass { 824 smp2p-lpass {
827 compatible = "qcom,smp2p"; 825 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 826 qcom,smem = <443>, <429>;
829 827
830 interrupts = <GIC_SPI 158 IRQ_ 828 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 829
832 mboxes = <&apss_shared 10>; 830 mboxes = <&apss_shared 10>;
833 831
834 qcom,local-pid = <0>; 832 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 833 qcom,remote-pid = <2>;
836 834
837 adsp_smp2p_out: master-kernel 835 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 836 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 837 #qcom,smem-state-cells = <1>;
840 }; 838 };
841 839
842 adsp_smp2p_in: slave-kernel { 840 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 841 qcom,entry-name = "slave-kernel";
844 842
845 interrupt-controller; 843 interrupt-controller;
846 #interrupt-cells = <2> 844 #interrupt-cells = <2>;
847 }; 845 };
848 }; 846 };
849 847
850 smp2p-mpss { 848 smp2p-mpss {
851 compatible = "qcom,smp2p"; 849 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 850 qcom,smem = <435>, <428>;
853 851
854 interrupts = <GIC_SPI 451 IRQ_ 852 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 853
856 mboxes = <&apss_shared 14>; 854 mboxes = <&apss_shared 14>;
857 855
858 qcom,local-pid = <0>; 856 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 857 qcom,remote-pid = <1>;
860 858
861 modem_smp2p_out: master-kernel 859 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 860 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 861 #qcom,smem-state-cells = <1>;
864 }; 862 };
865 863
866 modem_smp2p_in: slave-kernel { 864 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 865 qcom,entry-name = "slave-kernel";
868 866
869 interrupt-controller; 867 interrupt-controller;
870 #interrupt-cells = <2> 868 #interrupt-cells = <2>;
871 }; 869 };
872 }; 870 };
873 871
874 smp2p-slpi { 872 smp2p-slpi {
875 compatible = "qcom,smp2p"; 873 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 874 qcom,smem = <481>, <430>;
877 875
878 interrupts = <GIC_SPI 172 IRQ_ 876 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 877
880 mboxes = <&apss_shared 26>; 878 mboxes = <&apss_shared 26>;
881 879
882 qcom,local-pid = <0>; 880 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 881 qcom,remote-pid = <3>;
884 882
885 slpi_smp2p_out: master-kernel 883 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 884 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 885 #qcom,smem-state-cells = <1>;
888 }; 886 };
889 887
890 slpi_smp2p_in: slave-kernel { 888 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 889 qcom,entry-name = "slave-kernel";
892 890
893 interrupt-controller; 891 interrupt-controller;
894 #interrupt-cells = <2> 892 #interrupt-cells = <2>;
895 }; 893 };
896 }; 894 };
897 895
898 soc: soc@0 { 896 soc: soc@0 {
899 #address-cells = <2>; 897 #address-cells = <2>;
900 #size-cells = <2>; 898 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 899 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 900 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 901 compatible = "simple-bus";
904 902
905 gcc: clock-controller@100000 { 903 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 904 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 905 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 906 #clock-cells = <1>;
909 #reset-cells = <1>; 907 #reset-cells = <1>;
910 #power-domain-cells = 908 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 909 clock-names = "bi_tcxo",
912 "sleep_c 910 "sleep_clk";
913 clocks = <&rpmhcc RPMH 911 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 912 <&sleep_clk>;
915 }; 913 };
916 914
917 gpi_dma0: dma-controller@80000 915 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 916 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 917 reg = <0 0x00800000 0 0x60000>;
920 interrupts = <GIC_SPI 918 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 919 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 920 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 921 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 922 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 923 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 924 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 925 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 926 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 927 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 928 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 929 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 930 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 931 dma-channels = <13>;
934 dma-channel-mask = <0x 932 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 933 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 934 #dma-cells = <3>;
937 status = "disabled"; 935 status = "disabled";
938 }; 936 };
939 937
940 ethernet: ethernet@20000 { 938 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 939 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 940 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 941 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 942 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 943 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 944 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 945 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 946 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 947 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 948 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 949 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 950 interrupt-names = "macirq", "eth_lpi";
953 951
954 power-domains = <&gcc 952 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 953 resets = <&gcc GCC_EMAC_BCR>;
956 954
957 iommus = <&apps_smmu 0 955 iommus = <&apps_smmu 0x3c0 0x0>;
958 956
959 snps,tso; 957 snps,tso;
960 rx-fifo-depth = <4096> 958 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 959 tx-fifo-depth = <4096>;
962 960
963 status = "disabled"; 961 status = "disabled";
964 }; 962 };
965 963
966 qfprom: efuse@784000 { 964 qfprom: efuse@784000 {
967 compatible = "qcom,sm8 965 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
968 reg = <0 0x00784000 0 966 reg = <0 0x00784000 0 0x8ff>;
969 #address-cells = <1>; 967 #address-cells = <1>;
970 #size-cells = <1>; 968 #size-cells = <1>;
971 969
972 gpu_speed_bin: gpu-spe 970 gpu_speed_bin: gpu-speed-bin@133 {
973 reg = <0x133 0 971 reg = <0x133 0x1>;
974 bits = <5 3>; 972 bits = <5 3>;
975 }; 973 };
976 }; 974 };
977 975
978 qupv3_id_0: geniqup@8c0000 { 976 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 977 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 978 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 979 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 982 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 983 #address-cells = <2>;
986 #size-cells = <2>; 984 #size-cells = <2>;
987 ranges; 985 ranges;
988 status = "disabled"; 986 status = "disabled";
989 987
990 i2c0: i2c@880000 { 988 i2c0: i2c@880000 {
991 compatible = " 989 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 990 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 991 clock-names = "se";
994 clocks = <&gcc 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 993 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 994 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 995 dma-names = "tx", "rx";
998 pinctrl-names 996 pinctrl-names = "default";
999 pinctrl-0 = <& 997 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 998 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 999 #address-cells = <1>;
1002 #size-cells = 1000 #size-cells = <0>;
1003 status = "dis 1001 status = "disabled";
1004 }; 1002 };
1005 1003
1006 spi0: spi@880000 { 1004 spi0: spi@880000 {
1007 compatible = 1005 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 1006 reg = <0 0x00880000 0 0x4000>;
1009 reg-names = " 1007 reg-names = "se";
1010 clock-names = 1008 clock-names = "se";
1011 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 1012 dma-names = "tx", "rx";
1015 pinctrl-names 1013 pinctrl-names = "default";
1016 pinctrl-0 = < 1014 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 1015 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 1016 spi-max-frequency = <50000000>;
1019 #address-cell 1017 #address-cells = <1>;
1020 #size-cells = 1018 #size-cells = <0>;
1021 status = "dis 1019 status = "disabled";
1022 }; 1020 };
1023 1021
1024 i2c1: i2c@884000 { 1022 i2c1: i2c@884000 {
1025 compatible = 1023 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 1024 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 1025 clock-names = "se";
1028 clocks = <&gc 1026 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 1029 dma-names = "tx", "rx";
1032 pinctrl-names 1030 pinctrl-names = "default";
1033 pinctrl-0 = < 1031 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 1032 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 1033 #address-cells = <1>;
1036 #size-cells = 1034 #size-cells = <0>;
1037 status = "dis 1035 status = "disabled";
1038 }; 1036 };
1039 1037
1040 spi1: spi@884000 { 1038 spi1: spi@884000 {
1041 compatible = 1039 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1040 reg = <0 0x00884000 0 0x4000>;
1043 reg-names = " 1041 reg-names = "se";
1044 clock-names = 1042 clock-names = "se";
1045 clocks = <&gc 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1045 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1046 dma-names = "tx", "rx";
1049 pinctrl-names 1047 pinctrl-names = "default";
1050 pinctrl-0 = < 1048 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1050 spi-max-frequency = <50000000>;
1053 #address-cell 1051 #address-cells = <1>;
1054 #size-cells = 1052 #size-cells = <0>;
1055 status = "dis 1053 status = "disabled";
1056 }; 1054 };
1057 1055
1058 i2c2: i2c@888000 { 1056 i2c2: i2c@888000 {
1059 compatible = 1057 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1058 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1059 clock-names = "se";
1062 clocks = <&gc 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1061 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1062 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1063 dma-names = "tx", "rx";
1066 pinctrl-names 1064 pinctrl-names = "default";
1067 pinctrl-0 = < 1065 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1066 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1067 #address-cells = <1>;
1070 #size-cells = 1068 #size-cells = <0>;
1071 status = "dis 1069 status = "disabled";
1072 }; 1070 };
1073 1071
1074 spi2: spi@888000 { 1072 spi2: spi@888000 {
1075 compatible = 1073 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 1074 reg = <0 0x00888000 0 0x4000>;
1077 reg-names = " 1075 reg-names = "se";
1078 clock-names = 1076 clock-names = "se";
1079 clocks = <&gc 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1078 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1079 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1080 dma-names = "tx", "rx";
1083 pinctrl-names 1081 pinctrl-names = "default";
1084 pinctrl-0 = < 1082 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1083 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1084 spi-max-frequency = <50000000>;
1087 #address-cell 1085 #address-cells = <1>;
1088 #size-cells = 1086 #size-cells = <0>;
1089 status = "dis 1087 status = "disabled";
1090 }; 1088 };
1091 1089
1092 i2c3: i2c@88c000 { 1090 i2c3: i2c@88c000 {
1093 compatible = 1091 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1092 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1093 clock-names = "se";
1096 clocks = <&gc 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1095 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1096 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1097 dma-names = "tx", "rx";
1100 pinctrl-names 1098 pinctrl-names = "default";
1101 pinctrl-0 = < 1099 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1100 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1101 #address-cells = <1>;
1104 #size-cells = 1102 #size-cells = <0>;
1105 status = "dis 1103 status = "disabled";
1106 }; 1104 };
1107 1105
1108 spi3: spi@88c000 { 1106 spi3: spi@88c000 {
1109 compatible = 1107 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 1108 reg = <0 0x0088c000 0 0x4000>;
1111 reg-names = " 1109 reg-names = "se";
1112 clock-names = 1110 clock-names = "se";
1113 clocks = <&gc 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1112 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1113 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1114 dma-names = "tx", "rx";
1117 pinctrl-names 1115 pinctrl-names = "default";
1118 pinctrl-0 = < 1116 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1117 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1118 spi-max-frequency = <50000000>;
1121 #address-cell 1119 #address-cells = <1>;
1122 #size-cells = 1120 #size-cells = <0>;
1123 status = "dis 1121 status = "disabled";
1124 }; 1122 };
1125 1123
1126 i2c4: i2c@890000 { 1124 i2c4: i2c@890000 {
1127 compatible = 1125 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1126 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1127 clock-names = "se";
1130 clocks = <&gc 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1129 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1130 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1131 dma-names = "tx", "rx";
1134 pinctrl-names 1132 pinctrl-names = "default";
1135 pinctrl-0 = < 1133 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1134 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1135 #address-cells = <1>;
1138 #size-cells = 1136 #size-cells = <0>;
1139 status = "dis 1137 status = "disabled";
1140 }; 1138 };
1141 1139
1142 spi4: spi@890000 { 1140 spi4: spi@890000 {
1143 compatible = 1141 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 1142 reg = <0 0x00890000 0 0x4000>;
1145 reg-names = " 1143 reg-names = "se";
1146 clock-names = 1144 clock-names = "se";
1147 clocks = <&gc 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1146 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1147 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1148 dma-names = "tx", "rx";
1151 pinctrl-names 1149 pinctrl-names = "default";
1152 pinctrl-0 = < 1150 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1151 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1152 spi-max-frequency = <50000000>;
1155 #address-cell 1153 #address-cells = <1>;
1156 #size-cells = 1154 #size-cells = <0>;
1157 status = "dis 1155 status = "disabled";
1158 }; 1156 };
1159 1157
1160 i2c5: i2c@894000 { 1158 i2c5: i2c@894000 {
1161 compatible = 1159 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1160 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1161 clock-names = "se";
1164 clocks = <&gc 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1163 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1164 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1165 dma-names = "tx", "rx";
1168 pinctrl-names 1166 pinctrl-names = "default";
1169 pinctrl-0 = < 1167 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1168 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1169 #address-cells = <1>;
1172 #size-cells = 1170 #size-cells = <0>;
1173 status = "dis 1171 status = "disabled";
1174 }; 1172 };
1175 1173
1176 spi5: spi@894000 { 1174 spi5: spi@894000 {
1177 compatible = 1175 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 1176 reg = <0 0x00894000 0 0x4000>;
1179 reg-names = " 1177 reg-names = "se";
1180 clock-names = 1178 clock-names = "se";
1181 clocks = <&gc 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1180 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1181 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1182 dma-names = "tx", "rx";
1185 pinctrl-names 1183 pinctrl-names = "default";
1186 pinctrl-0 = < 1184 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1185 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1186 spi-max-frequency = <50000000>;
1189 #address-cell 1187 #address-cells = <1>;
1190 #size-cells = 1188 #size-cells = <0>;
1191 status = "dis 1189 status = "disabled";
1192 }; 1190 };
1193 1191
1194 i2c6: i2c@898000 { 1192 i2c6: i2c@898000 {
1195 compatible = 1193 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1194 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1195 clock-names = "se";
1198 clocks = <&gc 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1197 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1198 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1199 dma-names = "tx", "rx";
1202 pinctrl-names 1200 pinctrl-names = "default";
1203 pinctrl-0 = < 1201 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1202 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1203 #address-cells = <1>;
1206 #size-cells = 1204 #size-cells = <0>;
1207 status = "dis 1205 status = "disabled";
1208 }; 1206 };
1209 1207
1210 spi6: spi@898000 { 1208 spi6: spi@898000 {
1211 compatible = 1209 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1210 reg = <0 0x00898000 0 0x4000>;
1213 reg-names = " 1211 reg-names = "se";
1214 clock-names = 1212 clock-names = "se";
1215 clocks = <&gc 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1214 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1215 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1216 dma-names = "tx", "rx";
1219 pinctrl-names 1217 pinctrl-names = "default";
1220 pinctrl-0 = < 1218 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1219 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1220 spi-max-frequency = <50000000>;
1223 #address-cell 1221 #address-cells = <1>;
1224 #size-cells = 1222 #size-cells = <0>;
1225 status = "dis 1223 status = "disabled";
1226 }; 1224 };
1227 1225
1228 i2c7: i2c@89c000 { 1226 i2c7: i2c@89c000 {
1229 compatible = 1227 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1228 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1229 clock-names = "se";
1232 clocks = <&gc 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1231 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1232 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1233 dma-names = "tx", "rx";
1236 pinctrl-names 1234 pinctrl-names = "default";
1237 pinctrl-0 = < 1235 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = 1236 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1237 #address-cells = <1>;
1240 #size-cells = 1238 #size-cells = <0>;
1241 status = "dis 1239 status = "disabled";
1242 }; 1240 };
1243 1241
1244 spi7: spi@89c000 { 1242 spi7: spi@89c000 {
1245 compatible = 1243 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 1244 reg = <0 0x0089c000 0 0x4000>;
1247 reg-names = " 1245 reg-names = "se";
1248 clock-names = 1246 clock-names = "se";
1249 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1248 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1249 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1250 dma-names = "tx", "rx";
1253 pinctrl-names 1251 pinctrl-names = "default";
1254 pinctrl-0 = < 1252 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1253 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1254 spi-max-frequency = <50000000>;
1257 #address-cell 1255 #address-cells = <1>;
1258 #size-cells = 1256 #size-cells = <0>;
1259 status = "dis 1257 status = "disabled";
1260 }; 1258 };
1261 }; 1259 };
1262 1260
1263 gpi_dma1: dma-controller@a000 1261 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm 1262 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 1263 reg = <0 0x00a00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1276 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1277 dma-channels = <13>;
1280 dma-channel-mask = <0 1278 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1279 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1280 #dma-cells = <3>;
1283 status = "disabled"; 1281 status = "disabled";
1284 }; 1282 };
1285 1283
1286 qupv3_id_1: geniqup@ac0000 { 1284 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1285 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1286 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1287 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1288 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1289 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1290 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1291 #address-cells = <2>;
1294 #size-cells = <2>; 1292 #size-cells = <2>;
1295 ranges; 1293 ranges;
1296 status = "disabled"; 1294 status = "disabled";
1297 1295
1298 i2c8: i2c@a80000 { 1296 i2c8: i2c@a80000 {
1299 compatible = 1297 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1298 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1299 clock-names = "se";
1302 clocks = <&gc 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1301 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1303 dma-names = "tx", "rx";
1306 pinctrl-names 1304 pinctrl-names = "default";
1307 pinctrl-0 = < 1305 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1306 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1307 #address-cells = <1>;
1310 #size-cells = 1308 #size-cells = <0>;
1311 status = "dis 1309 status = "disabled";
1312 }; 1310 };
1313 1311
1314 spi8: spi@a80000 { 1312 spi8: spi@a80000 {
1315 compatible = 1313 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 1314 reg = <0 0x00a80000 0 0x4000>;
1317 reg-names = " 1315 reg-names = "se";
1318 clock-names = 1316 clock-names = "se";
1319 clocks = <&gc 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1318 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1320 dma-names = "tx", "rx";
1323 pinctrl-names 1321 pinctrl-names = "default";
1324 pinctrl-0 = < 1322 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1323 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1324 spi-max-frequency = <50000000>;
1327 #address-cell 1325 #address-cells = <1>;
1328 #size-cells = 1326 #size-cells = <0>;
1329 status = "dis 1327 status = "disabled";
1330 }; 1328 };
1331 1329
1332 i2c9: i2c@a84000 { 1330 i2c9: i2c@a84000 {
1333 compatible = 1331 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1332 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1333 clock-names = "se";
1336 clocks = <&gc 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1336 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1337 dma-names = "tx", "rx";
1340 pinctrl-names 1338 pinctrl-names = "default";
1341 pinctrl-0 = < 1339 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1340 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1341 #address-cells = <1>;
1344 #size-cells = 1342 #size-cells = <0>;
1345 status = "dis 1343 status = "disabled";
1346 }; 1344 };
1347 1345
1348 spi9: spi@a84000 { 1346 spi9: spi@a84000 {
1349 compatible = 1347 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 1348 reg = <0 0x00a84000 0 0x4000>;
1351 reg-names = " 1349 reg-names = "se";
1352 clock-names = 1350 clock-names = "se";
1353 clocks = <&gc 1351 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1353 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1354 dma-names = "tx", "rx";
1357 pinctrl-names 1355 pinctrl-names = "default";
1358 pinctrl-0 = < 1356 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1357 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1358 spi-max-frequency = <50000000>;
1361 #address-cell 1359 #address-cells = <1>;
1362 #size-cells = 1360 #size-cells = <0>;
1363 status = "dis 1361 status = "disabled";
1364 }; 1362 };
1365 1363
1366 uart9: serial@a84000 1364 uart9: serial@a84000 {
1367 compatible = 1365 compatible = "qcom,geni-uart";
1368 reg = <0x0 0x 1366 reg = <0x0 0x00a84000 0x0 0x4000>;
1369 clocks = <&gc 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1370 clock-names = 1368 clock-names = "se";
1371 pinctrl-0 = < 1369 pinctrl-0 = <&qup_uart9_default>;
1372 pinctrl-names 1370 pinctrl-names = "default";
1373 interrupts = 1371 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1374 status = "dis 1372 status = "disabled";
1375 }; 1373 };
1376 1374
1377 i2c10: i2c@a88000 { 1375 i2c10: i2c@a88000 {
1378 compatible = 1376 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1377 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1378 clock-names = "se";
1381 clocks = <&gc 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1380 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1381 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1382 dma-names = "tx", "rx";
1385 pinctrl-names 1383 pinctrl-names = "default";
1386 pinctrl-0 = < 1384 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1385 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1386 #address-cells = <1>;
1389 #size-cells = 1387 #size-cells = <0>;
1390 status = "dis 1388 status = "disabled";
1391 }; 1389 };
1392 1390
1393 spi10: spi@a88000 { 1391 spi10: spi@a88000 {
1394 compatible = 1392 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 1393 reg = <0 0x00a88000 0 0x4000>;
1396 reg-names = " 1394 reg-names = "se";
1397 clock-names = 1395 clock-names = "se";
1398 clocks = <&gc 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1398 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1399 dma-names = "tx", "rx";
1402 pinctrl-names 1400 pinctrl-names = "default";
1403 pinctrl-0 = < 1401 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1402 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1403 spi-max-frequency = <50000000>;
1406 #address-cell 1404 #address-cells = <1>;
1407 #size-cells = 1405 #size-cells = <0>;
1408 status = "dis 1406 status = "disabled";
1409 }; 1407 };
1410 1408
1411 i2c11: i2c@a8c000 { 1409 i2c11: i2c@a8c000 {
1412 compatible = 1410 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1411 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1412 clock-names = "se";
1415 clocks = <&gc 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1414 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1415 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1416 dma-names = "tx", "rx";
1419 pinctrl-names 1417 pinctrl-names = "default";
1420 pinctrl-0 = < 1418 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1419 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1420 #address-cells = <1>;
1423 #size-cells = 1421 #size-cells = <0>;
1424 status = "dis 1422 status = "disabled";
1425 }; 1423 };
1426 1424
1427 spi11: spi@a8c000 { 1425 spi11: spi@a8c000 {
1428 compatible = 1426 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 1427 reg = <0 0x00a8c000 0 0x4000>;
1430 reg-names = " 1428 reg-names = "se";
1431 clock-names = 1429 clock-names = "se";
1432 clocks = <&gc 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1431 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1432 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1433 dma-names = "tx", "rx";
1436 pinctrl-names 1434 pinctrl-names = "default";
1437 pinctrl-0 = < 1435 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1436 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1437 spi-max-frequency = <50000000>;
1440 #address-cell 1438 #address-cells = <1>;
1441 #size-cells = 1439 #size-cells = <0>;
1442 status = "dis 1440 status = "disabled";
1443 }; 1441 };
1444 1442
1445 uart2: serial@a90000 1443 uart2: serial@a90000 {
1446 compatible = 1444 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1445 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1446 clock-names = "se";
1449 clocks = <&gc 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1449 status = "disabled";
1452 }; 1450 };
1453 1451
1454 i2c12: i2c@a90000 { 1452 i2c12: i2c@a90000 {
1455 compatible = 1453 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1454 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1455 clock-names = "se";
1458 clocks = <&gc 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1457 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1458 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1459 dma-names = "tx", "rx";
1462 pinctrl-names 1460 pinctrl-names = "default";
1463 pinctrl-0 = < 1461 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1462 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1463 #address-cells = <1>;
1466 #size-cells = 1464 #size-cells = <0>;
1467 status = "dis 1465 status = "disabled";
1468 }; 1466 };
1469 1467
1470 spi12: spi@a90000 { 1468 spi12: spi@a90000 {
1471 compatible = 1469 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 1470 reg = <0 0x00a90000 0 0x4000>;
1473 reg-names = " 1471 reg-names = "se";
1474 clock-names = 1472 clock-names = "se";
1475 clocks = <&gc 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1474 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1475 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1476 dma-names = "tx", "rx";
1479 pinctrl-names 1477 pinctrl-names = "default";
1480 pinctrl-0 = < 1478 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1479 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1480 spi-max-frequency = <50000000>;
1483 #address-cell 1481 #address-cells = <1>;
1484 #size-cells = 1482 #size-cells = <0>;
1485 status = "dis 1483 status = "disabled";
1486 }; 1484 };
1487 1485
1488 i2c16: i2c@94000 { 1486 i2c16: i2c@94000 {
1489 compatible = 1487 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 1488 reg = <0 0x00094000 0 0x4000>;
1491 clock-names = 1489 clock-names = "se";
1492 clocks = <&gc 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1491 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1492 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1493 dma-names = "tx", "rx";
1496 pinctrl-names 1494 pinctrl-names = "default";
1497 pinctrl-0 = < 1495 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1496 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1497 #address-cells = <1>;
1500 #size-cells = 1498 #size-cells = <0>;
1501 status = "dis 1499 status = "disabled";
1502 }; 1500 };
1503 1501
1504 spi16: spi@a94000 { 1502 spi16: spi@a94000 {
1505 compatible = 1503 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 1504 reg = <0 0x00a94000 0 0x4000>;
1507 reg-names = " 1505 reg-names = "se";
1508 clock-names = 1506 clock-names = "se";
1509 clocks = <&gc 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1508 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1509 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1510 dma-names = "tx", "rx";
1513 pinctrl-names 1511 pinctrl-names = "default";
1514 pinctrl-0 = < 1512 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1513 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1514 spi-max-frequency = <50000000>;
1517 #address-cell 1515 #address-cells = <1>;
1518 #size-cells = 1516 #size-cells = <0>;
1519 status = "dis 1517 status = "disabled";
1520 }; 1518 };
1521 }; 1519 };
1522 1520
1523 gpi_dma2: dma-controller@c000 1521 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm 1522 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 1523 reg = <0 0x00c00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1524 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1525 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1526 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1527 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1528 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1529 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1530 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1531 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1532 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1533 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1534 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1535 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1536 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1537 dma-channels = <13>;
1540 dma-channel-mask = <0 1538 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1539 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1540 #dma-cells = <3>;
1543 status = "disabled"; 1541 status = "disabled";
1544 }; 1542 };
1545 1543
1546 qupv3_id_2: geniqup@cc0000 { 1544 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1545 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1546 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1547
1550 clock-names = "m-ahb" 1548 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1549 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1550 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1551 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1552 #address-cells = <2>;
1555 #size-cells = <2>; 1553 #size-cells = <2>;
1556 ranges; 1554 ranges;
1557 status = "disabled"; 1555 status = "disabled";
1558 1556
1559 i2c17: i2c@c80000 { 1557 i2c17: i2c@c80000 {
1560 compatible = 1558 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1559 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1560 clock-names = "se";
1563 clocks = <&gc 1561 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1562 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1564 dma-names = "tx", "rx";
1567 pinctrl-names 1565 pinctrl-names = "default";
1568 pinctrl-0 = < 1566 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1567 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1568 #address-cells = <1>;
1571 #size-cells = 1569 #size-cells = <0>;
1572 status = "dis 1570 status = "disabled";
1573 }; 1571 };
1574 1572
1575 spi17: spi@c80000 { 1573 spi17: spi@c80000 {
1576 compatible = 1574 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1575 reg = <0 0x00c80000 0 0x4000>;
1578 reg-names = " 1576 reg-names = "se";
1579 clock-names = 1577 clock-names = "se";
1580 clocks = <&gc 1578 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1579 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1581 dma-names = "tx", "rx";
1584 pinctrl-names 1582 pinctrl-names = "default";
1585 pinctrl-0 = < 1583 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1584 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1585 spi-max-frequency = <50000000>;
1588 #address-cell 1586 #address-cells = <1>;
1589 #size-cells = 1587 #size-cells = <0>;
1590 status = "dis 1588 status = "disabled";
1591 }; 1589 };
1592 1590
1593 i2c18: i2c@c84000 { 1591 i2c18: i2c@c84000 {
1594 compatible = 1592 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1593 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1594 clock-names = "se";
1597 clocks = <&gc 1595 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1597 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1598 dma-names = "tx", "rx";
1601 pinctrl-names 1599 pinctrl-names = "default";
1602 pinctrl-0 = < 1600 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1602 #address-cells = <1>;
1605 #size-cells = 1603 #size-cells = <0>;
1606 status = "dis 1604 status = "disabled";
1607 }; 1605 };
1608 1606
1609 spi18: spi@c84000 { 1607 spi18: spi@c84000 {
1610 compatible = 1608 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 1609 reg = <0 0x00c84000 0 0x4000>;
1612 reg-names = " 1610 reg-names = "se";
1613 clock-names = 1611 clock-names = "se";
1614 clocks = <&gc 1612 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1614 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1615 dma-names = "tx", "rx";
1618 pinctrl-names 1616 pinctrl-names = "default";
1619 pinctrl-0 = < 1617 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1618 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1619 spi-max-frequency = <50000000>;
1622 #address-cell 1620 #address-cells = <1>;
1623 #size-cells = 1621 #size-cells = <0>;
1624 status = "dis 1622 status = "disabled";
1625 }; 1623 };
1626 1624
1627 i2c19: i2c@c88000 { 1625 i2c19: i2c@c88000 {
1628 compatible = 1626 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1627 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1628 clock-names = "se";
1631 clocks = <&gc 1629 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1630 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1631 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1632 dma-names = "tx", "rx";
1635 pinctrl-names 1633 pinctrl-names = "default";
1636 pinctrl-0 = < 1634 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1635 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1636 #address-cells = <1>;
1639 #size-cells = 1637 #size-cells = <0>;
1640 status = "dis 1638 status = "disabled";
1641 }; 1639 };
1642 1640
1643 spi19: spi@c88000 { 1641 spi19: spi@c88000 {
1644 compatible = 1642 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 1643 reg = <0 0x00c88000 0 0x4000>;
1646 reg-names = " 1644 reg-names = "se";
1647 clock-names = 1645 clock-names = "se";
1648 clocks = <&gc 1646 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1647 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1648 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1649 dma-names = "tx", "rx";
1652 pinctrl-names 1650 pinctrl-names = "default";
1653 pinctrl-0 = < 1651 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1652 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1653 spi-max-frequency = <50000000>;
1656 #address-cell 1654 #address-cells = <1>;
1657 #size-cells = 1655 #size-cells = <0>;
1658 status = "dis 1656 status = "disabled";
1659 }; 1657 };
1660 1658
1661 i2c13: i2c@c8c000 { 1659 i2c13: i2c@c8c000 {
1662 compatible = 1660 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1661 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1662 clock-names = "se";
1665 clocks = <&gc 1663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1664 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1665 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1666 dma-names = "tx", "rx";
1669 pinctrl-names 1667 pinctrl-names = "default";
1670 pinctrl-0 = < 1668 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1669 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1670 #address-cells = <1>;
1673 #size-cells = 1671 #size-cells = <0>;
1674 status = "dis 1672 status = "disabled";
1675 }; 1673 };
1676 1674
1677 spi13: spi@c8c000 { 1675 spi13: spi@c8c000 {
1678 compatible = 1676 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 1677 reg = <0 0x00c8c000 0 0x4000>;
1680 reg-names = " 1678 reg-names = "se";
1681 clock-names = 1679 clock-names = "se";
1682 clocks = <&gc 1680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1681 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1682 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1683 dma-names = "tx", "rx";
1686 pinctrl-names 1684 pinctrl-names = "default";
1687 pinctrl-0 = < 1685 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1686 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1687 spi-max-frequency = <50000000>;
1690 #address-cell 1688 #address-cells = <1>;
1691 #size-cells = 1689 #size-cells = <0>;
1692 status = "dis 1690 status = "disabled";
1693 }; 1691 };
1694 1692
1695 i2c14: i2c@c90000 { 1693 i2c14: i2c@c90000 {
1696 compatible = 1694 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1695 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1696 clock-names = "se";
1699 clocks = <&gc 1697 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1698 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1699 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1700 dma-names = "tx", "rx";
1703 pinctrl-names 1701 pinctrl-names = "default";
1704 pinctrl-0 = < 1702 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1703 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1704 #address-cells = <1>;
1707 #size-cells = 1705 #size-cells = <0>;
1708 status = "dis 1706 status = "disabled";
1709 }; 1707 };
1710 1708
1711 spi14: spi@c90000 { 1709 spi14: spi@c90000 {
1712 compatible = 1710 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 1711 reg = <0 0x00c90000 0 0x4000>;
1714 reg-names = " 1712 reg-names = "se";
1715 clock-names = 1713 clock-names = "se";
1716 clocks = <&gc 1714 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1715 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1716 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1717 dma-names = "tx", "rx";
1720 pinctrl-names 1718 pinctrl-names = "default";
1721 pinctrl-0 = < 1719 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1720 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1721 spi-max-frequency = <50000000>;
1724 #address-cell 1722 #address-cells = <1>;
1725 #size-cells = 1723 #size-cells = <0>;
1726 status = "dis 1724 status = "disabled";
1727 }; 1725 };
1728 1726
1729 i2c15: i2c@c94000 { 1727 i2c15: i2c@c94000 {
1730 compatible = 1728 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1729 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1730 clock-names = "se";
1733 clocks = <&gc 1731 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1732 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1733 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1734 dma-names = "tx", "rx";
1737 pinctrl-names 1735 pinctrl-names = "default";
1738 pinctrl-0 = < 1736 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1737 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1738 #address-cells = <1>;
1741 #size-cells = 1739 #size-cells = <0>;
1742 status = "dis 1740 status = "disabled";
1743 }; 1741 };
1744 1742
1745 spi15: spi@c94000 { 1743 spi15: spi@c94000 {
1746 compatible = 1744 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 1745 reg = <0 0x00c94000 0 0x4000>;
1748 reg-names = " 1746 reg-names = "se";
1749 clock-names = 1747 clock-names = "se";
1750 clocks = <&gc 1748 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1749 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1750 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1751 dma-names = "tx", "rx";
1754 pinctrl-names 1752 pinctrl-names = "default";
1755 pinctrl-0 = < 1753 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1754 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1755 spi-max-frequency = <50000000>;
1758 #address-cell 1756 #address-cells = <1>;
1759 #size-cells = 1757 #size-cells = <0>;
1760 status = "dis 1758 status = "disabled";
1761 }; 1759 };
1762 }; 1760 };
1763 1761
1764 config_noc: interconnect@1500 1762 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1763 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1764 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = 1765 #interconnect-cells = <2>;
1768 qcom,bcm-voters = <&a 1766 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1767 };
1770 1768
1771 system_noc: interconnect@1620 1769 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1770 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1771 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = 1772 #interconnect-cells = <2>;
1775 qcom,bcm-voters = <&a 1773 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1774 };
1777 1775
1778 mc_virt: interconnect@163a000 1776 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1777 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1778 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = 1779 #interconnect-cells = <2>;
1782 qcom,bcm-voters = <&a 1780 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1781 };
1784 1782
1785 aggre1_noc: interconnect@16e0 1783 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1784 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1785 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = 1786 #interconnect-cells = <2>;
1789 qcom,bcm-voters = <&a 1787 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1788 };
1791 1789
1792 aggre2_noc: interconnect@1700 1790 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1791 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1792 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = 1793 #interconnect-cells = <2>;
1796 qcom,bcm-voters = <&a 1794 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1795 };
1798 1796
1799 compute_noc: interconnect@172 1797 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1798 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1799 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = 1800 #interconnect-cells = <2>;
1803 qcom,bcm-voters = <&a 1801 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1802 };
1805 1803
1806 mmss_noc: interconnect@174000 1804 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1805 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1806 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = 1807 #interconnect-cells = <2>;
1810 qcom,bcm-voters = <&a 1808 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1809 };
1812 1810
1813 system-cache-controller@92000 1811 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1812 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 1813 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1816 <0 0x09300000 0 1814 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1817 <0 0x09600000 0 1815 <0 0x09600000 0 0x50000>;
1818 reg-names = "llcc0_ba 1816 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1819 "llcc3_ba 1817 "llcc3_base", "llcc_broadcast_base";
1820 interrupts = <GIC_SPI 1818 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1819 };
1822 1820
1823 dma@10a2000 { 1821 dma@10a2000 {
1824 compatible = "qcom,sm 1822 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1825 reg = <0x0 0x010a2000 1823 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 1824 <0x0 0x010ad000 0x0 0x3000>;
1827 }; 1825 };
1828 1826
1829 pcie0: pcie@1c00000 { 1827 pcie0: pcie@1c00000 {
1830 compatible = "qcom,pc 1828 compatible = "qcom,pcie-sm8150";
1831 reg = <0 0x01c00000 0 1829 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1830 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1831 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1832 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1833 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1834 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1835 device_type = "pci";
1838 linux,pci-domain = <0 1836 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1837 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1838 num-lanes = <1>;
1841 1839
1842 #address-cells = <3>; 1840 #address-cells = <3>;
1843 #size-cells = <2>; 1841 #size-cells = <2>;
1844 1842
1845 ranges = <0x01000000 1843 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 1844 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 1845
1848 interrupts = <GIC_SPI 1846 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 1847 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 1848 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 1849 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 1850 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 1851 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 1852 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 1853 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1856 interrupt-names = "ms 1854 interrupt-names = "msi0",
1857 "ms 1855 "msi1",
1858 "ms 1856 "msi2",
1859 "ms 1857 "msi3",
1860 "ms 1858 "msi4",
1861 "ms 1859 "msi5",
1862 "ms 1860 "msi6",
1863 "ms 1861 "msi7";
1864 #interrupt-cells = <1 1862 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1863 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1864 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1865 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1866 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1867 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1868
1871 clocks = <&gcc GCC_PC 1869 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1870 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1871 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1872 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1873 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1874 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG 1875 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1878 <&rpmhcc RPM 1876 <&rpmhcc RPMH_CXO_CLK>;
1879 clock-names = "pipe", 1877 clock-names = "pipe",
1880 "aux", 1878 "aux",
1881 "cfg", 1879 "cfg",
1882 "bus_ma 1880 "bus_master",
1883 "bus_sl 1881 "bus_slave",
1884 "slave_ 1882 "slave_q2a",
1885 "tbu", 1883 "tbu",
1886 "ref"; 1884 "ref";
1887 1885
1888 iommu-map = <0x0 &a 1886 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1887 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1888
1891 resets = <&gcc GCC_PC 1889 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1890 reset-names = "pci";
1893 1891
1894 power-domains = <&gcc 1892 power-domains = <&gcc PCIE_0_GDSC>;
1895 1893
1896 phys = <&pcie0_phy>; 1894 phys = <&pcie0_phy>;
1897 phy-names = "pciephy" 1895 phy-names = "pciephy";
1898 1896
1899 perst-gpios = <&tlmm 1897 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 1898 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1899
1902 pinctrl-names = "defa 1900 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1901 pinctrl-0 = <&pcie0_default_state>;
1904 1902
1905 status = "disabled"; 1903 status = "disabled";
1906 1904
1907 pcie@0 { 1905 pcie@0 {
1908 device_type = 1906 device_type = "pci";
1909 reg = <0x0 0x 1907 reg = <0x0 0x0 0x0 0x0 0x0>;
1910 bus-range = < 1908 bus-range = <0x01 0xff>;
1911 1909
1912 #address-cell 1910 #address-cells = <3>;
1913 #size-cells = 1911 #size-cells = <2>;
1914 ranges; 1912 ranges;
1915 }; 1913 };
1916 }; 1914 };
1917 1915
1918 pcie0_phy: phy@1c06000 { 1916 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1917 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 1918 reg = <0 0x01c06000 0 0x1000>;
1921 clocks = <&gcc GCC_PC 1919 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1920 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC 1921 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1924 <&gcc GCC_PC 1922 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1925 <&gcc GCC_PC 1923 <&gcc GCC_PCIE_0_PIPE_CLK>;
1926 clock-names = "aux", 1924 clock-names = "aux",
1927 "cfg_ah 1925 "cfg_ahb",
1928 "ref", 1926 "ref",
1929 "refgen 1927 "refgen",
1930 "pipe"; 1928 "pipe";
1931 1929
1932 clock-output-names = 1930 clock-output-names = "pcie_0_pipe_clk";
1933 #clock-cells = <0>; 1931 #clock-cells = <0>;
1934 1932
1935 #phy-cells = <0>; 1933 #phy-cells = <0>;
1936 1934
1937 resets = <&gcc GCC_PC 1935 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1936 reset-names = "phy";
1939 1937
1940 assigned-clocks = <&g 1938 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1939 assigned-clock-rates = <100000000>;
1942 1940
1943 status = "disabled"; 1941 status = "disabled";
1944 }; 1942 };
1945 1943
1946 pcie1: pcie@1c08000 { 1944 pcie1: pcie@1c08000 {
1947 compatible = "qcom,pc 1945 compatible = "qcom,pcie-sm8150";
1948 reg = <0 0x01c08000 0 1946 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1947 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1948 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1949 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1950 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1951 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1952 device_type = "pci";
1955 linux,pci-domain = <1 1953 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1954 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1955 num-lanes = <2>;
1958 1956
1959 #address-cells = <3>; 1957 #address-cells = <3>;
1960 #size-cells = <2>; 1958 #size-cells = <2>;
1961 1959
1962 ranges = <0x01000000 1960 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1961 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1962
1965 interrupts = <GIC_SPI 1963 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 1964 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 1965 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 1966 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 1967 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 1968 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 1969 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 1970 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1973 interrupt-names = "ms 1971 interrupt-names = "msi0",
1974 "ms 1972 "msi1",
1975 "ms 1973 "msi2",
1976 "ms 1974 "msi3",
1977 "ms 1975 "msi4",
1978 "ms 1976 "msi5",
1979 "ms 1977 "msi6",
1980 "ms 1978 "msi7";
1981 #interrupt-cells = <1 1979 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1980 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1981 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1982 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1983 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1984 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1985
1988 clocks = <&gcc GCC_PC 1986 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1987 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1989 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1990 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1991 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG 1992 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1995 <&rpmhcc RPM 1993 <&rpmhcc RPMH_CXO_CLK>;
1996 clock-names = "pipe", 1994 clock-names = "pipe",
1997 "aux", 1995 "aux",
1998 "cfg", 1996 "cfg",
1999 "bus_ma 1997 "bus_master",
2000 "bus_sl 1998 "bus_slave",
2001 "slave_ 1999 "slave_q2a",
2002 "tbu", 2000 "tbu",
2003 "ref"; 2001 "ref";
2004 2002
2005 assigned-clocks = <&g 2003 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 2004 assigned-clock-rates = <19200000>;
2007 2005
2008 iommu-map = <0x0 &a 2006 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 2007 <0x100 &apps_smmu 0x1e01 0x1>;
2010 2008
2011 resets = <&gcc GCC_PC 2009 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 2010 reset-names = "pci";
2013 2011
2014 power-domains = <&gcc 2012 power-domains = <&gcc PCIE_1_GDSC>;
2015 2013
2016 phys = <&pcie1_phy>; 2014 phys = <&pcie1_phy>;
2017 phy-names = "pciephy" 2015 phy-names = "pciephy";
2018 2016
2019 perst-gpios = <&tlmm 2017 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 2018 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 2019
2022 pinctrl-names = "defa 2020 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 2021 pinctrl-0 = <&pcie1_default_state>;
2024 2022
2025 status = "disabled"; 2023 status = "disabled";
2026 2024
2027 pcie@0 { 2025 pcie@0 {
2028 device_type = 2026 device_type = "pci";
2029 reg = <0x0 0x 2027 reg = <0x0 0x0 0x0 0x0 0x0>;
2030 bus-range = < 2028 bus-range = <0x01 0xff>;
2031 2029
2032 #address-cell 2030 #address-cells = <3>;
2033 #size-cells = 2031 #size-cells = <2>;
2034 ranges; 2032 ranges;
2035 }; 2033 };
2036 }; 2034 };
2037 2035
2038 pcie1_phy: phy@1c0e000 { 2036 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 2037 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 2038 reg = <0 0x01c0e000 0 0x1000>;
2041 clocks = <&gcc GCC_PC 2039 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 2040 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC 2041 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2044 <&gcc GCC_PC 2042 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2045 <&gcc GCC_PC 2043 <&gcc GCC_PCIE_1_PIPE_CLK>;
2046 clock-names = "aux", 2044 clock-names = "aux",
2047 "cfg_ah 2045 "cfg_ahb",
2048 "ref", 2046 "ref",
2049 "refgen 2047 "refgen",
2050 "pipe"; 2048 "pipe";
2051 2049
2052 clock-output-names = 2050 clock-output-names = "pcie_1_pipe_clk";
2053 #clock-cells = <0>; 2051 #clock-cells = <0>;
2054 2052
2055 #phy-cells = <0>; 2053 #phy-cells = <0>;
2056 2054
2057 resets = <&gcc GCC_PC 2055 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 2056 reset-names = "phy";
2059 2057
2060 assigned-clocks = <&g 2058 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 2059 assigned-clock-rates = <100000000>;
2062 2060
2063 status = "disabled"; 2061 status = "disabled";
2064 }; 2062 };
2065 2063
2066 ufs_mem_hc: ufshc@1d84000 { 2064 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 2065 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 2066 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 2067 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 2068 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 2069 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 2070 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> 2071 phys = <&ufs_mem_phy>;
2074 phy-names = "ufsphy"; 2072 phy-names = "ufsphy";
2075 lanes-per-direction = 2073 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 2074 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 2075 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 2076 reset-names = "rst";
2079 2077
2080 iommus = <&apps_smmu 2078 iommus = <&apps_smmu 0x300 0>;
2081 2079
2082 clock-names = 2080 clock-names =
2083 "core_clk", 2081 "core_clk",
2084 "bus_aggr_clk 2082 "bus_aggr_clk",
2085 "iface_clk", 2083 "iface_clk",
2086 "core_clk_uni 2084 "core_clk_unipro",
2087 "ref_clk", 2085 "ref_clk",
2088 "tx_lane0_syn 2086 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 2087 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 2088 "rx_lane1_sync_clk",
2091 "ice_core_clk 2089 "ice_core_clk";
2092 clocks = 2090 clocks =
2093 <&gcc GCC_UFS 2091 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 2092 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 2093 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 2094 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 2095 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 2096 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2097 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2098 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2099 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2100 freq-table-hz =
2103 <37500000 300 2101 <37500000 300000000>,
2104 <0 0>, 2102 <0 0>,
2105 <0 0>, 2103 <0 0>,
2106 <37500000 300 2104 <37500000 300000000>,
2107 <0 0>, 2105 <0 0>,
2108 <0 0>, 2106 <0 0>,
2109 <0 0>, 2107 <0 0>,
2110 <0 0>, 2108 <0 0>,
2111 <0 300000000> 2109 <0 300000000>;
2112 2110
2113 status = "disabled"; 2111 status = "disabled";
2114 }; 2112 };
2115 2113
2116 ufs_mem_phy: phy@1d87000 { 2114 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2115 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 2116 reg = <0 0x01d87000 0 0x1000>;
2119 2117
2120 clocks = <&rpmhcc RPM 2118 clocks = <&rpmhcc RPMH_CXO_CLK>,
2121 <&gcc GCC_UF 2119 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2122 <&gcc GCC_UF 2120 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
2123 clock-names = "ref", 2121 clock-names = "ref",
2124 "ref_au 2122 "ref_aux",
2125 "qref"; 2123 "qref";
2126 2124
2127 power-domains = <&gcc 2125 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2126
2129 resets = <&ufs_mem_hc 2127 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2128 reset-names = "ufsphy";
2131 2129
2132 #phy-cells = <0>; 2130 #phy-cells = <0>;
2133 2131
2134 status = "disabled"; 2132 status = "disabled";
2135 }; 2133 };
2136 2134
2137 cryptobam: dma-controller@1dc 2135 cryptobam: dma-controller@1dc4000 {
2138 compatible = "qcom,ba 2136 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2139 reg = <0 0x01dc4000 0 2137 reg = <0 0x01dc4000 0 0x24000>;
2140 interrupts = <GIC_SPI 2138 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2141 #dma-cells = <1>; 2139 #dma-cells = <1>;
2142 qcom,ee = <0>; 2140 qcom,ee = <0>;
2143 qcom,controlled-remot 2141 qcom,controlled-remotely;
2144 num-channels = <8>; 2142 num-channels = <8>;
2145 qcom,num-ees = <2>; 2143 qcom,num-ees = <2>;
2146 iommus = <&apps_smmu 2144 iommus = <&apps_smmu 0x502 0x0641>,
2147 <&apps_smmu 2145 <&apps_smmu 0x504 0x0011>,
2148 <&apps_smmu 2146 <&apps_smmu 0x506 0x0011>,
2149 <&apps_smmu 2147 <&apps_smmu 0x508 0x0011>,
2150 <&apps_smmu 2148 <&apps_smmu 0x512 0x0000>;
2151 }; 2149 };
2152 2150
2153 crypto: crypto@1dfa000 { 2151 crypto: crypto@1dfa000 {
2154 compatible = "qcom,sm 2152 compatible = "qcom,sm8150-qce", "qcom,qce";
2155 reg = <0 0x01dfa000 0 2153 reg = <0 0x01dfa000 0 0x6000>;
2156 dmas = <&cryptobam 4> 2154 dmas = <&cryptobam 4>, <&cryptobam 5>;
2157 dma-names = "rx", "tx 2155 dma-names = "rx", "tx";
2158 iommus = <&apps_smmu 2156 iommus = <&apps_smmu 0x502 0x0641>,
2159 <&apps_smmu 2157 <&apps_smmu 0x504 0x0011>,
2160 <&apps_smmu 2158 <&apps_smmu 0x506 0x0011>,
2161 <&apps_smmu 2159 <&apps_smmu 0x508 0x0011>,
2162 <&apps_smmu 2160 <&apps_smmu 0x512 0x0000>;
2163 interconnects = <&agg 2161 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2164 interconnect-names = 2162 interconnect-names = "memory";
2165 }; 2163 };
2166 2164
2167 tcsr_mutex: hwlock@1f40000 { 2165 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc 2166 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 2167 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>; 2168 #hwlock-cells = <1>;
2171 }; 2169 };
2172 2170
2173 tcsr_regs_1: syscon@1f60000 { 2171 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm 2172 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 2173 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 }; 2174 };
2177 2175
2178 remoteproc_slpi: remoteproc@2 2176 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2177 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2178 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2179
2182 interrupts-extended = 2180 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2181 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2182 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2183 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2184 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2185 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2186 "handover", "stop-ack";
2189 2187
2190 clocks = <&rpmhcc RPM 2188 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2189 clock-names = "xo";
2192 2190
2193 power-domains = <&rpm 2191 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpm 2192 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = 2193 power-domain-names = "lcx", "lmx";
2196 2194
2197 memory-region = <&slp 2195 memory-region = <&slpi_mem>;
2198 2196
2199 qcom,qmp = <&aoss_qmp 2197 qcom,qmp = <&aoss_qmp>;
2200 2198
2201 qcom,smem-states = <& 2199 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2200 qcom,smem-state-names = "stop";
2203 2201
2204 status = "disabled"; 2202 status = "disabled";
2205 2203
2206 glink-edge { 2204 glink-edge {
2207 interrupts = 2205 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2206 label = "dsps";
2209 qcom,remote-p 2207 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2208 mboxes = <&apss_shared 24>;
2211 2209
2212 fastrpc { 2210 fastrpc {
2213 compa 2211 compatible = "qcom,fastrpc";
2214 qcom, 2212 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2213 label = "sdsp";
2216 qcom, 2214 qcom,non-secure-domain;
2217 #addr 2215 #address-cells = <1>;
2218 #size 2216 #size-cells = <0>;
2219 2217
2220 compu 2218 compute-cb@1 {
2221 2219 compatible = "qcom,fastrpc-compute-cb";
2222 2220 reg = <1>;
2223 2221 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2222 };
2225 2223
2226 compu 2224 compute-cb@2 {
2227 2225 compatible = "qcom,fastrpc-compute-cb";
2228 2226 reg = <2>;
2229 2227 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2228 };
2231 2229
2232 compu 2230 compute-cb@3 {
2233 2231 compatible = "qcom,fastrpc-compute-cb";
2234 2232 reg = <3>;
2235 2233 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2234 /* note: shared-cb = <4> in downstream */
2237 }; 2235 };
2238 }; 2236 };
2239 }; 2237 };
2240 }; 2238 };
2241 2239
2242 gpu: gpu@2c00000 { 2240 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad 2241 compatible = "qcom,adreno-640.1", "qcom,adreno";
2244 reg = <0 0x02c00000 0 2242 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2243 reg-names = "kgsl_3d0_reg_memory";
2246 2244
2247 interrupts = <GIC_SPI 2245 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2246
2249 iommus = <&adreno_smm 2247 iommus = <&adreno_smmu 0 0x401>;
2250 2248
2251 operating-points-v2 = 2249 operating-points-v2 = <&gpu_opp_table>;
2252 2250
2253 qcom,gmu = <&gmu>; 2251 qcom,gmu = <&gmu>;
2254 2252
2255 nvmem-cells = <&gpu_s 2253 nvmem-cells = <&gpu_speed_bin>;
2256 nvmem-cell-names = "s 2254 nvmem-cell-names = "speed_bin";
2257 #cooling-cells = <2>; 2255 #cooling-cells = <2>;
2258 2256
2259 status = "disabled"; 2257 status = "disabled";
2260 2258
2261 zap-shader { 2259 zap-shader {
2262 memory-region 2260 memory-region = <&gpu_mem>;
2263 }; 2261 };
2264 2262
2265 gpu_opp_table: opp-ta 2263 gpu_opp_table: opp-table {
2266 compatible = 2264 compatible = "operating-points-v2";
2267 2265
2268 opp-675000000 2266 opp-675000000 {
2269 opp-h 2267 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s 2269 opp-supported-hw = <0x2>;
2272 }; 2270 };
2273 2271
2274 opp-585000000 2272 opp-585000000 {
2275 opp-h 2273 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2274 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s 2275 opp-supported-hw = <0x3>;
2278 }; 2276 };
2279 2277
2280 opp-499200000 2278 opp-499200000 {
2281 opp-h 2279 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2280 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s 2281 opp-supported-hw = <0x3>;
2284 }; 2282 };
2285 2283
2286 opp-427000000 2284 opp-427000000 {
2287 opp-h 2285 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2286 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s 2287 opp-supported-hw = <0x3>;
2290 }; 2288 };
2291 2289
2292 opp-345000000 2290 opp-345000000 {
2293 opp-h 2291 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2292 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s 2293 opp-supported-hw = <0x3>;
2296 }; 2294 };
2297 2295
2298 opp-257000000 2296 opp-257000000 {
2299 opp-h 2297 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2298 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s 2299 opp-supported-hw = <0x3>;
2302 }; 2300 };
2303 }; 2301 };
2304 }; 2302 };
2305 2303
2306 gmu: gmu@2c6a000 { 2304 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad 2305 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2306
2309 reg = <0 0x02c6a000 0 2307 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2308 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2309 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2310 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2311
2314 interrupts = <GIC_SPI 2312 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2313 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2314 interrupt-names = "hfi", "gmu";
2317 2315
2318 clocks = <&gpucc GPU_ 2316 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2317 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2318 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2319 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2320 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2321 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2322
2325 power-domains = <&gpu 2323 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2324 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2325 power-domain-names = "cx", "gx";
2328 2326
2329 iommus = <&adreno_smm 2327 iommus = <&adreno_smmu 5 0x400>;
2330 2328
2331 operating-points-v2 = 2329 operating-points-v2 = <&gmu_opp_table>;
2332 2330
2333 status = "disabled"; 2331 status = "disabled";
2334 2332
2335 gmu_opp_table: opp-ta 2333 gmu_opp_table: opp-table {
2336 compatible = 2334 compatible = "operating-points-v2";
2337 2335
2338 opp-200000000 2336 opp-200000000 {
2339 opp-h 2337 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2338 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2339 };
2342 }; 2340 };
2343 }; 2341 };
2344 2342
2345 gpucc: clock-controller@2c900 2343 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2344 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2345 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2346 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2347 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2348 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2349 clock-names = "bi_tcxo",
2352 "gcc_gp 2350 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2351 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2352 #clock-cells = <1>;
2355 #reset-cells = <1>; 2353 #reset-cells = <1>;
2356 #power-domain-cells = 2354 #power-domain-cells = <1>;
2357 }; 2355 };
2358 2356
2359 adreno_smmu: iommu@2ca0000 { 2357 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm 2358 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2361 "qcom,sm 2359 "qcom,smmu-500", "arm,mmu-500";
2362 reg = <0 0x02ca0000 0 2360 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2361 #iommu-cells = <2>;
2364 #global-interrupts = 2362 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2363 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2364 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2365 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2366 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2367 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2368 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2369 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2370 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2371 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2372 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2373 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2374 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2375 clock-names = "ahb", "bus", "iface";
2378 2376
2379 power-domains = <&gpu 2377 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2378 };
2381 2379
2382 tlmm: pinctrl@3100000 { 2380 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2381 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2382 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2383 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2384 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2385 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2386 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2387 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2388 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2389 gpio-controller;
2392 #gpio-cells = <2>; 2390 #gpio-cells = <2>;
2393 interrupt-controller; 2391 interrupt-controller;
2394 #interrupt-cells = <2 2392 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2393 wakeup-parent = <&pdc>;
2396 2394
2397 qup_i2c0_default: qup 2395 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0 2396 pins = "gpio0", "gpio1";
2399 function = "q 2397 function = "qup0";
2400 drive-strengt 2398 drive-strength = <0x02>;
2401 bias-disable; 2399 bias-disable;
2402 }; 2400 };
2403 2401
2404 qup_spi0_default: qup 2402 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0 2403 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2404 function = "qup0";
2407 drive-strengt 2405 drive-strength = <6>;
2408 bias-disable; 2406 bias-disable;
2409 }; 2407 };
2410 2408
2411 qup_i2c1_default: qup 2409 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio1 2410 pins = "gpio114", "gpio115";
2413 function = "q 2411 function = "qup1";
2414 drive-strengt 2412 drive-strength = <2>;
2415 bias-disable; 2413 bias-disable;
2416 }; 2414 };
2417 2415
2418 qup_spi1_default: qup 2416 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio1 2417 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2418 function = "qup1";
2421 drive-strengt 2419 drive-strength = <6>;
2422 bias-disable; 2420 bias-disable;
2423 }; 2421 };
2424 2422
2425 qup_i2c2_default: qup 2423 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio1 2424 pins = "gpio126", "gpio127";
2427 function = "q 2425 function = "qup2";
2428 drive-strengt 2426 drive-strength = <2>;
2429 bias-disable; 2427 bias-disable;
2430 }; 2428 };
2431 2429
2432 qup_spi2_default: qup 2430 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio1 2431 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2432 function = "qup2";
2435 drive-strengt 2433 drive-strength = <6>;
2436 bias-disable; 2434 bias-disable;
2437 }; 2435 };
2438 2436
2439 qup_i2c3_default: qup 2437 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio1 2438 pins = "gpio144", "gpio145";
2441 function = "q 2439 function = "qup3";
2442 drive-strengt 2440 drive-strength = <2>;
2443 bias-disable; 2441 bias-disable;
2444 }; 2442 };
2445 2443
2446 qup_spi3_default: qup 2444 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio1 2445 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2446 function = "qup3";
2449 drive-strengt 2447 drive-strength = <6>;
2450 bias-disable; 2448 bias-disable;
2451 }; 2449 };
2452 2450
2453 qup_i2c4_default: qup 2451 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio5 2452 pins = "gpio51", "gpio52";
2455 function = "q 2453 function = "qup4";
2456 drive-strengt 2454 drive-strength = <2>;
2457 bias-disable; 2455 bias-disable;
2458 }; 2456 };
2459 2457
2460 qup_spi4_default: qup 2458 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio5 2459 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2460 function = "qup4";
2463 drive-strengt 2461 drive-strength = <6>;
2464 bias-disable; 2462 bias-disable;
2465 }; 2463 };
2466 2464
2467 qup_i2c5_default: qup 2465 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio1 2466 pins = "gpio121", "gpio122";
2469 function = "q 2467 function = "qup5";
2470 drive-strengt 2468 drive-strength = <2>;
2471 bias-disable; 2469 bias-disable;
2472 }; 2470 };
2473 2471
2474 qup_spi5_default: qup 2472 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio1 2473 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2474 function = "qup5";
2477 drive-strengt 2475 drive-strength = <6>;
2478 bias-disable; 2476 bias-disable;
2479 }; 2477 };
2480 2478
2481 qup_i2c6_default: qup 2479 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6 2480 pins = "gpio6", "gpio7";
2483 function = "q 2481 function = "qup6";
2484 drive-strengt 2482 drive-strength = <2>;
2485 bias-disable; 2483 bias-disable;
2486 }; 2484 };
2487 2485
2488 qup_spi6_default: qup 2486 qup_spi6_default: qup-spi6-default-state {
2489 pins = "gpio4 2487 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2488 function = "qup6";
2491 drive-strengt 2489 drive-strength = <6>;
2492 bias-disable; 2490 bias-disable;
2493 }; 2491 };
2494 2492
2495 qup_i2c7_default: qup 2493 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio9 2494 pins = "gpio98", "gpio99";
2497 function = "q 2495 function = "qup7";
2498 drive-strengt 2496 drive-strength = <2>;
2499 bias-disable; 2497 bias-disable;
2500 }; 2498 };
2501 2499
2502 qup_spi7_default: qup 2500 qup_spi7_default: qup-spi7-default-state {
2503 pins = "gpio9 2501 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2502 function = "qup7";
2505 drive-strengt 2503 drive-strength = <6>;
2506 bias-disable; 2504 bias-disable;
2507 }; 2505 };
2508 2506
2509 qup_i2c8_default: qup 2507 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio8 2508 pins = "gpio88", "gpio89";
2511 function = "q 2509 function = "qup8";
2512 drive-strengt 2510 drive-strength = <2>;
2513 bias-disable; 2511 bias-disable;
2514 }; 2512 };
2515 2513
2516 qup_spi8_default: qup 2514 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio8 2515 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2516 function = "qup8";
2519 drive-strengt 2517 drive-strength = <6>;
2520 bias-disable; 2518 bias-disable;
2521 }; 2519 };
2522 2520
2523 qup_i2c9_default: qup 2521 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio3 2522 pins = "gpio39", "gpio40";
2525 function = "q 2523 function = "qup9";
2526 drive-strengt 2524 drive-strength = <2>;
2527 bias-disable; 2525 bias-disable;
2528 }; 2526 };
2529 2527
2530 qup_spi9_default: qup 2528 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio3 2529 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2530 function = "qup9";
2533 drive-strengt 2531 drive-strength = <6>;
2534 bias-disable; 2532 bias-disable;
2535 }; 2533 };
2536 2534
2537 qup_uart9_default: qu 2535 qup_uart9_default: qup-uart9-default-state {
2538 pins = "gpio4 2536 pins = "gpio41", "gpio42";
2539 function = "q 2537 function = "qup9";
2540 drive-strengt 2538 drive-strength = <2>;
2541 bias-disable; 2539 bias-disable;
2542 }; 2540 };
2543 2541
2544 qup_i2c10_default: qu 2542 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9 2543 pins = "gpio9", "gpio10";
2546 function = "q 2544 function = "qup10";
2547 drive-strengt 2545 drive-strength = <2>;
2548 bias-disable; 2546 bias-disable;
2549 }; 2547 };
2550 2548
2551 qup_spi10_default: qu 2549 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9 2550 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2551 function = "qup10";
2554 drive-strengt 2552 drive-strength = <6>;
2555 bias-disable; 2553 bias-disable;
2556 }; 2554 };
2557 2555
2558 qup_i2c11_default: qu 2556 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio9 2557 pins = "gpio94", "gpio95";
2560 function = "q 2558 function = "qup11";
2561 drive-strengt 2559 drive-strength = <2>;
2562 bias-disable; 2560 bias-disable;
2563 }; 2561 };
2564 2562
2565 qup_spi11_default: qu 2563 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio9 2564 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2565 function = "qup11";
2568 drive-strengt 2566 drive-strength = <6>;
2569 bias-disable; 2567 bias-disable;
2570 }; 2568 };
2571 2569
2572 qup_i2c12_default: qu 2570 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio8 2571 pins = "gpio83", "gpio84";
2574 function = "q 2572 function = "qup12";
2575 drive-strengt 2573 drive-strength = <2>;
2576 bias-disable; 2574 bias-disable;
2577 }; 2575 };
2578 2576
2579 qup_spi12_default: qu 2577 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio8 2578 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2579 function = "qup12";
2582 drive-strengt 2580 drive-strength = <6>;
2583 bias-disable; 2581 bias-disable;
2584 }; 2582 };
2585 2583
2586 qup_i2c13_default: qu 2584 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio4 2585 pins = "gpio43", "gpio44";
2588 function = "q 2586 function = "qup13";
2589 drive-strengt 2587 drive-strength = <2>;
2590 bias-disable; 2588 bias-disable;
2591 }; 2589 };
2592 2590
2593 qup_spi13_default: qu 2591 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio4 2592 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2593 function = "qup13";
2596 drive-strengt 2594 drive-strength = <6>;
2597 bias-disable; 2595 bias-disable;
2598 }; 2596 };
2599 2597
2600 qup_i2c14_default: qu 2598 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio4 2599 pins = "gpio47", "gpio48";
2602 function = "q 2600 function = "qup14";
2603 drive-strengt 2601 drive-strength = <2>;
2604 bias-disable; 2602 bias-disable;
2605 }; 2603 };
2606 2604
2607 qup_spi14_default: qu 2605 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio4 2606 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2607 function = "qup14";
2610 drive-strengt 2608 drive-strength = <6>;
2611 bias-disable; 2609 bias-disable;
2612 }; 2610 };
2613 2611
2614 qup_i2c15_default: qu 2612 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio2 2613 pins = "gpio27", "gpio28";
2616 function = "q 2614 function = "qup15";
2617 drive-strengt 2615 drive-strength = <2>;
2618 bias-disable; 2616 bias-disable;
2619 }; 2617 };
2620 2618
2621 qup_spi15_default: qu 2619 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio2 2620 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2621 function = "qup15";
2624 drive-strengt 2622 drive-strength = <6>;
2625 bias-disable; 2623 bias-disable;
2626 }; 2624 };
2627 2625
2628 qup_i2c16_default: qu 2626 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio8 2627 pins = "gpio86", "gpio85";
2630 function = "q 2628 function = "qup16";
2631 drive-strengt 2629 drive-strength = <2>;
2632 bias-disable; 2630 bias-disable;
2633 }; 2631 };
2634 2632
2635 qup_spi16_default: qu 2633 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio8 2634 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2635 function = "qup16";
2638 drive-strengt 2636 drive-strength = <6>;
2639 bias-disable; 2637 bias-disable;
2640 }; 2638 };
2641 2639
2642 qup_i2c17_default: qu 2640 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio5 2641 pins = "gpio55", "gpio56";
2644 function = "q 2642 function = "qup17";
2645 drive-strengt 2643 drive-strength = <2>;
2646 bias-disable; 2644 bias-disable;
2647 }; 2645 };
2648 2646
2649 qup_spi17_default: qu 2647 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio5 2648 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2649 function = "qup17";
2652 drive-strengt 2650 drive-strength = <6>;
2653 bias-disable; 2651 bias-disable;
2654 }; 2652 };
2655 2653
2656 qup_i2c18_default: qu 2654 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio2 2655 pins = "gpio23", "gpio24";
2658 function = "q 2656 function = "qup18";
2659 drive-strengt 2657 drive-strength = <2>;
2660 bias-disable; 2658 bias-disable;
2661 }; 2659 };
2662 2660
2663 qup_spi18_default: qu 2661 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio2 2662 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2663 function = "qup18";
2666 drive-strengt 2664 drive-strength = <6>;
2667 bias-disable; 2665 bias-disable;
2668 }; 2666 };
2669 2667
2670 qup_i2c19_default: qu 2668 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio5 2669 pins = "gpio57", "gpio58";
2672 function = "q 2670 function = "qup19";
2673 drive-strengt 2671 drive-strength = <2>;
2674 bias-disable; 2672 bias-disable;
2675 }; 2673 };
2676 2674
2677 qup_spi19_default: qu 2675 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio5 2676 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2677 function = "qup19";
2680 drive-strengt 2678 drive-strength = <6>;
2681 bias-disable; 2679 bias-disable;
2682 }; 2680 };
2683 2681
2684 pcie0_default_state: 2682 pcie0_default_state: pcie0-default-state {
2685 perst-pins { 2683 perst-pins {
2686 pins 2684 pins = "gpio35";
2687 funct 2685 function = "gpio";
2688 drive 2686 drive-strength = <2>;
2689 bias- 2687 bias-pull-down;
2690 }; 2688 };
2691 2689
2692 clkreq-pins { 2690 clkreq-pins {
2693 pins 2691 pins = "gpio36";
2694 funct 2692 function = "pci_e0";
2695 drive 2693 drive-strength = <2>;
2696 bias- 2694 bias-pull-up;
2697 }; 2695 };
2698 2696
2699 wake-pins { 2697 wake-pins {
2700 pins 2698 pins = "gpio37";
2701 funct 2699 function = "gpio";
2702 drive 2700 drive-strength = <2>;
2703 bias- 2701 bias-pull-up;
2704 }; 2702 };
2705 }; 2703 };
2706 2704
2707 pcie1_default_state: 2705 pcie1_default_state: pcie1-default-state {
2708 perst-pins { 2706 perst-pins {
2709 pins 2707 pins = "gpio102";
2710 funct 2708 function = "gpio";
2711 drive 2709 drive-strength = <2>;
2712 bias- 2710 bias-pull-down;
2713 }; 2711 };
2714 2712
2715 clkreq-pins { 2713 clkreq-pins {
2716 pins 2714 pins = "gpio103";
2717 funct 2715 function = "pci_e1";
2718 drive 2716 drive-strength = <2>;
2719 bias- 2717 bias-pull-up;
2720 }; 2718 };
2721 2719
2722 wake-pins { 2720 wake-pins {
2723 pins 2721 pins = "gpio104";
2724 funct 2722 function = "gpio";
2725 drive 2723 drive-strength = <2>;
2726 bias- 2724 bias-pull-up;
2727 }; 2725 };
2728 }; 2726 };
2729 }; 2727 };
2730 2728
2731 remoteproc_mpss: remoteproc@4 2729 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2730 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2731 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2732
2735 interrupts-extended = 2733 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2734 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2735 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2736 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2737 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2738 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2739 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2740 "stop-ack", "shutdown-ack";
2743 2741
2744 clocks = <&rpmhcc RPM 2742 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2743 clock-names = "xo";
2746 2744
2747 power-domains = <&rpm 2745 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpm 2746 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = 2747 power-domain-names = "cx", "mss";
2750 2748
2751 memory-region = <&mps 2749 memory-region = <&mpss_mem>;
2752 2750
2753 qcom,qmp = <&aoss_qmp 2751 qcom,qmp = <&aoss_qmp>;
2754 2752
2755 qcom,smem-states = <& 2753 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2754 qcom,smem-state-names = "stop";
2757 2755
2758 status = "disabled"; 2756 status = "disabled";
2759 2757
2760 glink-edge { 2758 glink-edge {
2761 interrupts = 2759 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2760 label = "modem";
2763 qcom,remote-p 2761 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2762 mboxes = <&apss_shared 12>;
2765 }; 2763 };
2766 }; 2764 };
2767 2765
2768 stm@6002000 { 2766 stm@6002000 {
2769 compatible = "arm,cor 2767 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2768 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2769 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2770 reg-names = "stm-base", "stm-stimulus-base";
2773 2771
2774 clocks = <&aoss_qmp>; 2772 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2773 clock-names = "apb_pclk";
2776 2774
2777 out-ports { 2775 out-ports {
2778 port { 2776 port {
2779 stm_o 2777 stm_out: endpoint {
2780 2778 remote-endpoint = <&funnel0_in7>;
2781 }; 2779 };
2782 }; 2780 };
2783 }; 2781 };
2784 }; 2782 };
2785 2783
2786 funnel@6041000 { 2784 funnel@6041000 {
2787 compatible = "arm,cor 2785 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2786 reg = <0 0x06041000 0 0x1000>;
2789 2787
2790 clocks = <&aoss_qmp>; 2788 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2789 clock-names = "apb_pclk";
2792 2790
2793 out-ports { 2791 out-ports {
2794 port { 2792 port {
2795 funne 2793 funnel0_out: endpoint {
2796 2794 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2795 };
2798 }; 2796 };
2799 }; 2797 };
2800 2798
2801 in-ports { 2799 in-ports {
2802 #address-cell 2800 #address-cells = <1>;
2803 #size-cells = 2801 #size-cells = <0>;
2804 2802
2805 port@7 { 2803 port@7 {
2806 reg = 2804 reg = <7>;
2807 funne 2805 funnel0_in7: endpoint {
2808 2806 remote-endpoint = <&stm_out>;
2809 }; 2807 };
2810 }; 2808 };
2811 }; 2809 };
2812 }; 2810 };
2813 2811
2814 funnel@6042000 { 2812 funnel@6042000 {
2815 compatible = "arm,cor 2813 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2814 reg = <0 0x06042000 0 0x1000>;
2817 2815
2818 clocks = <&aoss_qmp>; 2816 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2817 clock-names = "apb_pclk";
2820 2818
2821 out-ports { 2819 out-ports {
2822 port { 2820 port {
2823 funne 2821 funnel1_out: endpoint {
2824 2822 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2823 };
2826 }; 2824 };
2827 }; 2825 };
2828 2826
2829 in-ports { 2827 in-ports {
2830 #address-cell 2828 #address-cells = <1>;
2831 #size-cells = 2829 #size-cells = <0>;
2832 2830
2833 port@4 { 2831 port@4 {
2834 reg = 2832 reg = <4>;
2835 funne 2833 funnel1_in4: endpoint {
2836 2834 remote-endpoint = <&swao_replicator_out>;
2837 }; 2835 };
2838 }; 2836 };
2839 }; 2837 };
2840 }; 2838 };
2841 2839
2842 funnel@6043000 { 2840 funnel@6043000 {
2843 compatible = "arm,cor 2841 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2842 reg = <0 0x06043000 0 0x1000>;
2845 2843
2846 clocks = <&aoss_qmp>; 2844 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2845 clock-names = "apb_pclk";
2848 2846
2849 out-ports { 2847 out-ports {
2850 port { 2848 port {
2851 funne 2849 funnel2_out: endpoint {
2852 2850 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2851 };
2854 }; 2852 };
2855 }; 2853 };
2856 2854
2857 in-ports { 2855 in-ports {
2858 #address-cell 2856 #address-cells = <1>;
2859 #size-cells = 2857 #size-cells = <0>;
2860 2858
2861 port@2 { 2859 port@2 {
2862 reg = 2860 reg = <2>;
2863 funne 2861 funnel2_in2: endpoint {
2864 2862 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2863 };
2866 }; 2864 };
2867 }; 2865 };
2868 }; 2866 };
2869 2867
2870 funnel@6045000 { 2868 funnel@6045000 {
2871 compatible = "arm,cor 2869 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2870 reg = <0 0x06045000 0 0x1000>;
2873 2871
2874 clocks = <&aoss_qmp>; 2872 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2873 clock-names = "apb_pclk";
2876 2874
2877 out-ports { 2875 out-ports {
2878 port { 2876 port {
2879 merge 2877 merge_funnel_out: endpoint {
2880 2878 remote-endpoint = <&etf_in>;
2881 }; 2879 };
2882 }; 2880 };
2883 }; 2881 };
2884 2882
2885 in-ports { 2883 in-ports {
2886 #address-cell 2884 #address-cells = <1>;
2887 #size-cells = 2885 #size-cells = <0>;
2888 2886
2889 port@0 { 2887 port@0 {
2890 reg = 2888 reg = <0>;
2891 merge 2889 merge_funnel_in0: endpoint {
2892 2890 remote-endpoint = <&funnel0_out>;
2893 }; 2891 };
2894 }; 2892 };
2895 2893
2896 port@1 { 2894 port@1 {
2897 reg = 2895 reg = <1>;
2898 merge 2896 merge_funnel_in1: endpoint {
2899 2897 remote-endpoint = <&funnel1_out>;
2900 }; 2898 };
2901 }; 2899 };
2902 2900
2903 port@2 { 2901 port@2 {
2904 reg = 2902 reg = <2>;
2905 merge 2903 merge_funnel_in2: endpoint {
2906 2904 remote-endpoint = <&funnel2_out>;
2907 }; 2905 };
2908 }; 2906 };
2909 }; 2907 };
2910 }; 2908 };
2911 2909
2912 replicator@6046000 { 2910 replicator@6046000 {
2913 compatible = "arm,cor 2911 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2912 reg = <0 0x06046000 0 0x1000>;
2915 2913
2916 clocks = <&aoss_qmp>; 2914 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2915 clock-names = "apb_pclk";
2918 2916
2919 out-ports { 2917 out-ports {
2920 #address-cell 2918 #address-cells = <1>;
2921 #size-cells = 2919 #size-cells = <0>;
2922 2920
2923 port@0 { 2921 port@0 {
2924 reg = 2922 reg = <0>;
2925 repli 2923 replicator_out0: endpoint {
2926 2924 remote-endpoint = <&etr_in>;
2927 }; 2925 };
2928 }; 2926 };
2929 2927
2930 port@1 { 2928 port@1 {
2931 reg = 2929 reg = <1>;
2932 repli 2930 replicator_out1: endpoint {
2933 2931 remote-endpoint = <&replicator1_in>;
2934 }; 2932 };
2935 }; 2933 };
2936 }; 2934 };
2937 2935
2938 in-ports { 2936 in-ports {
2939 port { 2937 port {
2940 repli 2938 replicator_in0: endpoint {
2941 2939 remote-endpoint = <&etf_out>;
2942 }; 2940 };
2943 }; 2941 };
2944 }; 2942 };
2945 }; 2943 };
2946 2944
2947 etf@6047000 { 2945 etf@6047000 {
2948 compatible = "arm,cor 2946 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2947 reg = <0 0x06047000 0 0x1000>;
2950 2948
2951 clocks = <&aoss_qmp>; 2949 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2950 clock-names = "apb_pclk";
2953 2951
2954 out-ports { 2952 out-ports {
2955 port { 2953 port {
2956 etf_o 2954 etf_out: endpoint {
2957 2955 remote-endpoint = <&replicator_in0>;
2958 }; 2956 };
2959 }; 2957 };
2960 }; 2958 };
2961 2959
2962 in-ports { 2960 in-ports {
2963 port { 2961 port {
2964 etf_i 2962 etf_in: endpoint {
2965 2963 remote-endpoint = <&merge_funnel_out>;
2966 }; 2964 };
2967 }; 2965 };
2968 }; 2966 };
2969 }; 2967 };
2970 2968
2971 etr@6048000 { 2969 etr@6048000 {
2972 compatible = "arm,cor 2970 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2971 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2972 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2973
2976 clocks = <&aoss_qmp>; 2974 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2975 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2976 arm,scatter-gather;
2979 2977
2980 in-ports { 2978 in-ports {
2981 port { 2979 port {
2982 etr_i 2980 etr_in: endpoint {
2983 2981 remote-endpoint = <&replicator_out0>;
2984 }; 2982 };
2985 }; 2983 };
2986 }; 2984 };
2987 }; 2985 };
2988 2986
2989 replicator@604a000 { 2987 replicator@604a000 {
2990 compatible = "arm,cor 2988 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2989 reg = <0 0x0604a000 0 0x1000>;
2992 2990
2993 clocks = <&aoss_qmp>; 2991 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2992 clock-names = "apb_pclk";
2995 2993
2996 out-ports { 2994 out-ports {
2997 #address-cell 2995 #address-cells = <1>;
2998 #size-cells = 2996 #size-cells = <0>;
2999 2997
3000 port@1 { 2998 port@1 {
3001 reg = 2999 reg = <1>;
3002 repli 3000 replicator1_out: endpoint {
3003 3001 remote-endpoint = <&swao_funnel_in>;
3004 }; 3002 };
3005 }; 3003 };
3006 }; 3004 };
3007 3005
3008 in-ports { 3006 in-ports {
3009 3007
3010 port { 3008 port {
3011 repli 3009 replicator1_in: endpoint {
3012 3010 remote-endpoint = <&replicator_out1>;
3013 }; 3011 };
3014 }; 3012 };
3015 }; 3013 };
3016 }; 3014 };
3017 3015
3018 funnel@6b08000 { 3016 funnel@6b08000 {
3019 compatible = "arm,cor 3017 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 3018 reg = <0 0x06b08000 0 0x1000>;
3021 3019
3022 clocks = <&aoss_qmp>; 3020 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 3021 clock-names = "apb_pclk";
3024 3022
3025 out-ports { 3023 out-ports {
3026 port { 3024 port {
3027 swao_ 3025 swao_funnel_out: endpoint {
3028 3026 remote-endpoint = <&swao_etf_in>;
3029 }; 3027 };
3030 }; 3028 };
3031 }; 3029 };
3032 3030
3033 in-ports { 3031 in-ports {
3034 #address-cell 3032 #address-cells = <1>;
3035 #size-cells = 3033 #size-cells = <0>;
3036 3034
3037 port@6 { 3035 port@6 {
3038 reg = 3036 reg = <6>;
3039 swao_ 3037 swao_funnel_in: endpoint {
3040 3038 remote-endpoint = <&replicator1_out>;
3041 }; 3039 };
3042 }; 3040 };
3043 }; 3041 };
3044 }; 3042 };
3045 3043
3046 etf@6b09000 { 3044 etf@6b09000 {
3047 compatible = "arm,cor 3045 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 3046 reg = <0 0x06b09000 0 0x1000>;
3049 3047
3050 clocks = <&aoss_qmp>; 3048 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 3049 clock-names = "apb_pclk";
3052 3050
3053 out-ports { 3051 out-ports {
3054 port { 3052 port {
3055 swao_ 3053 swao_etf_out: endpoint {
3056 3054 remote-endpoint = <&swao_replicator_in>;
3057 }; 3055 };
3058 }; 3056 };
3059 }; 3057 };
3060 3058
3061 in-ports { 3059 in-ports {
3062 port { 3060 port {
3063 swao_ 3061 swao_etf_in: endpoint {
3064 3062 remote-endpoint = <&swao_funnel_out>;
3065 }; 3063 };
3066 }; 3064 };
3067 }; 3065 };
3068 }; 3066 };
3069 3067
3070 replicator@6b0a000 { 3068 replicator@6b0a000 {
3071 compatible = "arm,cor 3069 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 3070 reg = <0 0x06b0a000 0 0x1000>;
3073 3071
3074 clocks = <&aoss_qmp>; 3072 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 3073 clock-names = "apb_pclk";
3076 qcom,replicator-loses 3074 qcom,replicator-loses-context;
3077 3075
3078 out-ports { 3076 out-ports {
3079 port { 3077 port {
3080 swao_ 3078 swao_replicator_out: endpoint {
3081 3079 remote-endpoint = <&funnel1_in4>;
3082 }; 3080 };
3083 }; 3081 };
3084 }; 3082 };
3085 3083
3086 in-ports { 3084 in-ports {
3087 port { 3085 port {
3088 swao_ 3086 swao_replicator_in: endpoint {
3089 3087 remote-endpoint = <&swao_etf_out>;
3090 }; 3088 };
3091 }; 3089 };
3092 }; 3090 };
3093 }; 3091 };
3094 3092
3095 etm@7040000 { 3093 etm@7040000 {
3096 compatible = "arm,cor 3094 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 3095 reg = <0 0x07040000 0 0x1000>;
3098 3096
3099 cpu = <&CPU0>; 3097 cpu = <&CPU0>;
3100 3098
3101 clocks = <&aoss_qmp>; 3099 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 3100 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 3101 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 3102 qcom,skip-power-up;
3105 3103
3106 out-ports { 3104 out-ports {
3107 port { 3105 port {
3108 etm0_ 3106 etm0_out: endpoint {
3109 3107 remote-endpoint = <&apss_funnel_in0>;
3110 }; 3108 };
3111 }; 3109 };
3112 }; 3110 };
3113 }; 3111 };
3114 3112
3115 etm@7140000 { 3113 etm@7140000 {
3116 compatible = "arm,cor 3114 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 3115 reg = <0 0x07140000 0 0x1000>;
3118 3116
3119 cpu = <&CPU1>; 3117 cpu = <&CPU1>;
3120 3118
3121 clocks = <&aoss_qmp>; 3119 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3120 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3121 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3122 qcom,skip-power-up;
3125 3123
3126 out-ports { 3124 out-ports {
3127 port { 3125 port {
3128 etm1_ 3126 etm1_out: endpoint {
3129 3127 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3128 };
3131 }; 3129 };
3132 }; 3130 };
3133 }; 3131 };
3134 3132
3135 etm@7240000 { 3133 etm@7240000 {
3136 compatible = "arm,cor 3134 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3135 reg = <0 0x07240000 0 0x1000>;
3138 3136
3139 cpu = <&CPU2>; 3137 cpu = <&CPU2>;
3140 3138
3141 clocks = <&aoss_qmp>; 3139 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3140 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3141 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3142 qcom,skip-power-up;
3145 3143
3146 out-ports { 3144 out-ports {
3147 port { 3145 port {
3148 etm2_ 3146 etm2_out: endpoint {
3149 3147 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3148 };
3151 }; 3149 };
3152 }; 3150 };
3153 }; 3151 };
3154 3152
3155 etm@7340000 { 3153 etm@7340000 {
3156 compatible = "arm,cor 3154 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3155 reg = <0 0x07340000 0 0x1000>;
3158 3156
3159 cpu = <&CPU3>; 3157 cpu = <&CPU3>;
3160 3158
3161 clocks = <&aoss_qmp>; 3159 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3160 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3161 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3162 qcom,skip-power-up;
3165 3163
3166 out-ports { 3164 out-ports {
3167 port { 3165 port {
3168 etm3_ 3166 etm3_out: endpoint {
3169 3167 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3168 };
3171 }; 3169 };
3172 }; 3170 };
3173 }; 3171 };
3174 3172
3175 etm@7440000 { 3173 etm@7440000 {
3176 compatible = "arm,cor 3174 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3175 reg = <0 0x07440000 0 0x1000>;
3178 3176
3179 cpu = <&CPU4>; 3177 cpu = <&CPU4>;
3180 3178
3181 clocks = <&aoss_qmp>; 3179 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3180 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3181 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3182 qcom,skip-power-up;
3185 3183
3186 out-ports { 3184 out-ports {
3187 port { 3185 port {
3188 etm4_ 3186 etm4_out: endpoint {
3189 3187 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3188 };
3191 }; 3189 };
3192 }; 3190 };
3193 }; 3191 };
3194 3192
3195 etm@7540000 { 3193 etm@7540000 {
3196 compatible = "arm,cor 3194 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3195 reg = <0 0x07540000 0 0x1000>;
3198 3196
3199 cpu = <&CPU5>; 3197 cpu = <&CPU5>;
3200 3198
3201 clocks = <&aoss_qmp>; 3199 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3200 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3201 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3202 qcom,skip-power-up;
3205 3203
3206 out-ports { 3204 out-ports {
3207 port { 3205 port {
3208 etm5_ 3206 etm5_out: endpoint {
3209 3207 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3208 };
3211 }; 3209 };
3212 }; 3210 };
3213 }; 3211 };
3214 3212
3215 etm@7640000 { 3213 etm@7640000 {
3216 compatible = "arm,cor 3214 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3215 reg = <0 0x07640000 0 0x1000>;
3218 3216
3219 cpu = <&CPU6>; 3217 cpu = <&CPU6>;
3220 3218
3221 clocks = <&aoss_qmp>; 3219 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3220 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3221 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3222 qcom,skip-power-up;
3225 3223
3226 out-ports { 3224 out-ports {
3227 port { 3225 port {
3228 etm6_ 3226 etm6_out: endpoint {
3229 3227 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3228 };
3231 }; 3229 };
3232 }; 3230 };
3233 }; 3231 };
3234 3232
3235 etm@7740000 { 3233 etm@7740000 {
3236 compatible = "arm,cor 3234 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3235 reg = <0 0x07740000 0 0x1000>;
3238 3236
3239 cpu = <&CPU7>; 3237 cpu = <&CPU7>;
3240 3238
3241 clocks = <&aoss_qmp>; 3239 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3240 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3241 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3242 qcom,skip-power-up;
3245 3243
3246 out-ports { 3244 out-ports {
3247 port { 3245 port {
3248 etm7_ 3246 etm7_out: endpoint {
3249 3247 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3248 };
3251 }; 3249 };
3252 }; 3250 };
3253 }; 3251 };
3254 3252
3255 funnel@7800000 { /* APSS Funn 3253 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3255 reg = <0 0x07800000 0 0x1000>;
3258 3256
3259 clocks = <&aoss_qmp>; 3257 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3258 clock-names = "apb_pclk";
3261 3259
3262 out-ports { 3260 out-ports {
3263 port { 3261 port {
3264 apss_ 3262 apss_funnel_out: endpoint {
3265 3263 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3264 };
3267 }; 3265 };
3268 }; 3266 };
3269 3267
3270 in-ports { 3268 in-ports {
3271 #address-cell 3269 #address-cells = <1>;
3272 #size-cells = 3270 #size-cells = <0>;
3273 3271
3274 port@0 { 3272 port@0 {
3275 reg = 3273 reg = <0>;
3276 apss_ 3274 apss_funnel_in0: endpoint {
3277 3275 remote-endpoint = <&etm0_out>;
3278 }; 3276 };
3279 }; 3277 };
3280 3278
3281 port@1 { 3279 port@1 {
3282 reg = 3280 reg = <1>;
3283 apss_ 3281 apss_funnel_in1: endpoint {
3284 3282 remote-endpoint = <&etm1_out>;
3285 }; 3283 };
3286 }; 3284 };
3287 3285
3288 port@2 { 3286 port@2 {
3289 reg = 3287 reg = <2>;
3290 apss_ 3288 apss_funnel_in2: endpoint {
3291 3289 remote-endpoint = <&etm2_out>;
3292 }; 3290 };
3293 }; 3291 };
3294 3292
3295 port@3 { 3293 port@3 {
3296 reg = 3294 reg = <3>;
3297 apss_ 3295 apss_funnel_in3: endpoint {
3298 3296 remote-endpoint = <&etm3_out>;
3299 }; 3297 };
3300 }; 3298 };
3301 3299
3302 port@4 { 3300 port@4 {
3303 reg = 3301 reg = <4>;
3304 apss_ 3302 apss_funnel_in4: endpoint {
3305 3303 remote-endpoint = <&etm4_out>;
3306 }; 3304 };
3307 }; 3305 };
3308 3306
3309 port@5 { 3307 port@5 {
3310 reg = 3308 reg = <5>;
3311 apss_ 3309 apss_funnel_in5: endpoint {
3312 3310 remote-endpoint = <&etm5_out>;
3313 }; 3311 };
3314 }; 3312 };
3315 3313
3316 port@6 { 3314 port@6 {
3317 reg = 3315 reg = <6>;
3318 apss_ 3316 apss_funnel_in6: endpoint {
3319 3317 remote-endpoint = <&etm6_out>;
3320 }; 3318 };
3321 }; 3319 };
3322 3320
3323 port@7 { 3321 port@7 {
3324 reg = 3322 reg = <7>;
3325 apss_ 3323 apss_funnel_in7: endpoint {
3326 3324 remote-endpoint = <&etm7_out>;
3327 }; 3325 };
3328 }; 3326 };
3329 }; 3327 };
3330 }; 3328 };
3331 3329
3332 funnel@7810000 { 3330 funnel@7810000 {
3333 compatible = "arm,cor 3331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3332 reg = <0 0x07810000 0 0x1000>;
3335 3333
3336 clocks = <&aoss_qmp>; 3334 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3335 clock-names = "apb_pclk";
3338 3336
3339 out-ports { 3337 out-ports {
3340 port { 3338 port {
3341 apss_ 3339 apss_merge_funnel_out: endpoint {
3342 3340 remote-endpoint = <&funnel2_in2>;
3343 }; 3341 };
3344 }; 3342 };
3345 }; 3343 };
3346 3344
3347 in-ports { 3345 in-ports {
3348 port { 3346 port {
3349 apss_ 3347 apss_merge_funnel_in: endpoint {
3350 3348 remote-endpoint = <&apss_funnel_out>;
3351 }; 3349 };
3352 }; 3350 };
3353 }; 3351 };
3354 }; 3352 };
3355 3353
3356 remoteproc_cdsp: remoteproc@8 3354 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3355 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3356 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3357
3360 interrupts-extended = 3358 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3359 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3360 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3361 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3362 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3363 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3364 "handover", "stop-ack";
3367 3365
3368 clocks = <&rpmhcc RPM 3366 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3367 clock-names = "xo";
3370 3368
3371 power-domains = <&rpm 3369 power-domains = <&rpmhpd SM8150_CX>;
3372 3370
3373 memory-region = <&cds 3371 memory-region = <&cdsp_mem>;
3374 3372
3375 qcom,qmp = <&aoss_qmp 3373 qcom,qmp = <&aoss_qmp>;
3376 3374
3377 qcom,smem-states = <& 3375 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3376 qcom,smem-state-names = "stop";
3379 3377
3380 status = "disabled"; 3378 status = "disabled";
3381 3379
3382 glink-edge { 3380 glink-edge {
3383 interrupts = 3381 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3382 label = "cdsp";
3385 qcom,remote-p 3383 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3384 mboxes = <&apss_shared 4>;
3387 3385
3388 fastrpc { 3386 fastrpc {
3389 compa 3387 compatible = "qcom,fastrpc";
3390 qcom, 3388 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3389 label = "cdsp";
3392 qcom, 3390 qcom,non-secure-domain;
3393 #addr 3391 #address-cells = <1>;
3394 #size 3392 #size-cells = <0>;
3395 3393
3396 compu 3394 compute-cb@1 {
3397 3395 compatible = "qcom,fastrpc-compute-cb";
3398 3396 reg = <1>;
3399 3397 iommus = <&apps_smmu 0x1001 0x0460>;
3400 }; 3398 };
3401 3399
3402 compu 3400 compute-cb@2 {
3403 3401 compatible = "qcom,fastrpc-compute-cb";
3404 3402 reg = <2>;
3405 3403 iommus = <&apps_smmu 0x1002 0x0460>;
3406 }; 3404 };
3407 3405
3408 compu 3406 compute-cb@3 {
3409 3407 compatible = "qcom,fastrpc-compute-cb";
3410 3408 reg = <3>;
3411 3409 iommus = <&apps_smmu 0x1003 0x0460>;
3412 }; 3410 };
3413 3411
3414 compu 3412 compute-cb@4 {
3415 3413 compatible = "qcom,fastrpc-compute-cb";
3416 3414 reg = <4>;
3417 3415 iommus = <&apps_smmu 0x1004 0x0460>;
3418 }; 3416 };
3419 3417
3420 compu 3418 compute-cb@5 {
3421 3419 compatible = "qcom,fastrpc-compute-cb";
3422 3420 reg = <5>;
3423 3421 iommus = <&apps_smmu 0x1005 0x0460>;
3424 }; 3422 };
3425 3423
3426 compu 3424 compute-cb@6 {
3427 3425 compatible = "qcom,fastrpc-compute-cb";
3428 3426 reg = <6>;
3429 3427 iommus = <&apps_smmu 0x1006 0x0460>;
3430 }; 3428 };
3431 3429
3432 compu 3430 compute-cb@7 {
3433 3431 compatible = "qcom,fastrpc-compute-cb";
3434 3432 reg = <7>;
3435 3433 iommus = <&apps_smmu 0x1007 0x0460>;
3436 }; 3434 };
3437 3435
3438 compu 3436 compute-cb@8 {
3439 3437 compatible = "qcom,fastrpc-compute-cb";
3440 3438 reg = <8>;
3441 3439 iommus = <&apps_smmu 0x1008 0x0460>;
3442 }; 3440 };
3443 3441
3444 /* no 3442 /* note: secure cb9 in downstream */
3445 }; 3443 };
3446 }; 3444 };
3447 }; 3445 };
3448 3446
3449 usb_1_hsphy: phy@88e2000 { 3447 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3448 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3449 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3450 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3451 status = "disabled";
3454 #phy-cells = <0>; 3452 #phy-cells = <0>;
3455 3453
3456 clocks = <&rpmhcc RPM 3454 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3455 clock-names = "ref";
3458 3456
3459 resets = <&gcc GCC_QU 3457 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3458 };
3461 3459
3462 usb_2_hsphy: phy@88e3000 { 3460 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3461 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3462 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3463 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3464 status = "disabled";
3467 #phy-cells = <0>; 3465 #phy-cells = <0>;
3468 3466
3469 clocks = <&rpmhcc RPM 3467 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3468 clock-names = "ref";
3471 3469
3472 resets = <&gcc GCC_QU 3470 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3471 };
3474 3472
3475 usb_1_qmpphy: phy@88e8000 { 3473 usb_1_qmpphy: phy@88e8000 {
3476 compatible = "qcom,sm 3474 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3477 reg = <0 0x088e8000 0 3475 reg = <0 0x088e8000 0 0x3000>;
3478 3476
3479 clocks = <&gcc GCC_US 3477 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3480 <&gcc GCC_US 3478 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US 3479 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3482 <&gcc GCC_US 3480 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3483 clock-names = "aux", 3481 clock-names = "aux",
3484 "ref", 3482 "ref",
3485 "com_au 3483 "com_aux",
3486 "usb3_p 3484 "usb3_pipe";
3487 3485
3488 resets = <&gcc GCC_US 3486 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3487 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3488 reset-names = "phy", "common";
3491 3489
3492 #clock-cells = <1>; 3490 #clock-cells = <1>;
3493 #phy-cells = <1>; 3491 #phy-cells = <1>;
3494 3492
3495 status = "disabled"; 3493 status = "disabled";
3496 3494
3497 ports { 3495 ports {
3498 #address-cell 3496 #address-cells = <1>;
3499 #size-cells = 3497 #size-cells = <0>;
3500 3498
3501 port@0 { 3499 port@0 {
3502 reg = 3500 reg = <0>;
3503 3501
3504 usb_1 3502 usb_1_qmpphy_out: endpoint {
3505 }; 3503 };
3506 }; 3504 };
3507 3505
3508 port@1 { 3506 port@1 {
3509 reg = 3507 reg = <1>;
3510 3508
3511 usb_1 3509 usb_1_qmpphy_usb_ss_in: endpoint {
3512 <<
3513 }; 3510 };
3514 }; 3511 };
3515 3512
3516 port@2 { 3513 port@2 {
3517 reg = 3514 reg = <2>;
3518 3515
3519 usb_1 3516 usb_1_qmpphy_dp_in: endpoint {
3520 <<
3521 }; 3517 };
3522 }; 3518 };
3523 }; 3519 };
3524 }; 3520 };
3525 3521
3526 usb_2_qmpphy: phy@88eb000 { 3522 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3523 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 3524 reg = <0 0x088eb000 0 0x1000>;
3529 3525
3530 clocks = <&gcc GCC_US 3526 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3531 <&gcc GCC_US 3527 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US 3528 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3533 <&gcc GCC_US 3529 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3534 clock-names = "aux", 3530 clock-names = "aux",
3535 "ref", 3531 "ref",
3536 "com_au 3532 "com_aux",
3537 "pipe"; 3533 "pipe";
3538 clock-output-names = 3534 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3539 #clock-cells = <0>; 3535 #clock-cells = <0>;
3540 #phy-cells = <0>; 3536 #phy-cells = <0>;
3541 3537
3542 resets = <&gcc GCC_US 3538 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3543 <&gcc GCC_US 3539 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3544 reset-names = "phy", 3540 reset-names = "phy",
3545 "phy_ph 3541 "phy_phy";
3546 3542
3547 status = "disabled"; 3543 status = "disabled";
3548 }; 3544 };
3549 3545
3550 sdhc_2: mmc@8804000 { 3546 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm 3547 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3548 reg = <0 0x08804000 0 0x1000>;
3553 3549
3554 interrupts = <GIC_SPI 3550 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3551 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3552 interrupt-names = "hc_irq", "pwr_irq";
3557 3553
3558 clocks = <&gcc GCC_SD 3554 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3555 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3556 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3557 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3558 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3559 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3560 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3561 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3562 operating-points-v2 = <&sdhc2_opp_table>;
3567 3563
3568 status = "disabled"; 3564 status = "disabled";
3569 3565
3570 sdhc2_opp_table: opp- 3566 sdhc2_opp_table: opp-table {
3571 compatible = 3567 compatible = "operating-points-v2";
3572 3568
3573 opp-19200000 3569 opp-19200000 {
3574 opp-h 3570 opp-hz = /bits/ 64 <19200000>;
3575 requi 3571 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3572 };
3577 3573
3578 opp-50000000 3574 opp-50000000 {
3579 opp-h 3575 opp-hz = /bits/ 64 <50000000>;
3580 requi 3576 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3577 };
3582 3578
3583 opp-100000000 3579 opp-100000000 {
3584 opp-h 3580 opp-hz = /bits/ 64 <100000000>;
3585 requi 3581 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3582 };
3587 3583
3588 opp-202000000 3584 opp-202000000 {
3589 opp-h 3585 opp-hz = /bits/ 64 <202000000>;
3590 requi 3586 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3587 };
3592 }; 3588 };
3593 }; 3589 };
3594 3590
3595 dc_noc: interconnect@9160000 3591 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3592 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3593 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = 3594 #interconnect-cells = <2>;
3599 qcom,bcm-voters = <&a 3595 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3596 };
3601 3597
3602 gem_noc: interconnect@9680000 3598 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3599 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3600 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = 3601 #interconnect-cells = <2>;
3606 qcom,bcm-voters = <&a 3602 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3603 };
3608 3604
3609 usb_1: usb@a6f8800 { 3605 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3606 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3607 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3608 status = "disabled";
3613 #address-cells = <2>; 3609 #address-cells = <2>;
3614 #size-cells = <2>; 3610 #size-cells = <2>;
3615 ranges; 3611 ranges;
3616 dma-ranges; 3612 dma-ranges;
3617 3613
3618 clocks = <&gcc GCC_CF 3614 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3615 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3616 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3617 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3618 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3619 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3620 clock-names = "cfg_noc",
3625 "core", 3621 "core",
3626 "iface" 3622 "iface",
3627 "sleep" 3623 "sleep",
3628 "mock_u 3624 "mock_utmi",
3629 "xo"; 3625 "xo";
3630 3626
3631 assigned-clocks = <&g 3627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3628 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3629 assigned-clock-rates = <19200000>, <200000000>;
3634 3630
3635 interrupts-extended = 3631 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3636 3632 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3637 3633 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3638 3634 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3639 3635 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3640 interrupt-names = "pw 3636 interrupt-names = "pwr_event",
3641 "hs 3637 "hs_phy_irq",
3642 "dp 3638 "dp_hs_phy_irq",
3643 "dm 3639 "dm_hs_phy_irq",
3644 "ss 3640 "ss_phy_irq";
3645 3641
3646 power-domains = <&gcc 3642 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3643
3648 resets = <&gcc GCC_US 3644 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3645
3650 interconnects = <&agg 3646 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3651 <&gem 3647 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3652 interconnect-names = 3648 interconnect-names = "usb-ddr", "apps-usb";
3653 3649
3654 usb_1_dwc3: usb@a6000 3650 usb_1_dwc3: usb@a600000 {
3655 compatible = 3651 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3652 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3653 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3654 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3655 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3656 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ 3657 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3662 phy-names = " 3658 phy-names = "usb2-phy", "usb3-phy";
3663 3659
3664 ports { 3660 ports {
3665 #addr 3661 #address-cells = <1>;
3666 #size 3662 #size-cells = <0>;
3667 3663
3668 port@ 3664 port@0 {
3669 3665 reg = <0>;
3670 3666
3671 3667 usb_1_dwc3_hs: endpoint {
3672 3668 };
3673 }; 3669 };
3674 3670
3675 port@ 3671 port@1 {
3676 3672 reg = <1>;
3677 3673
3678 3674 usb_1_dwc3_ss: endpoint {
3679 <<
3680 3675 };
3681 }; 3676 };
3682 }; 3677 };
3683 }; 3678 };
3684 }; 3679 };
3685 3680
3686 usb_2: usb@a8f8800 { 3681 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3682 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3683 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3684 status = "disabled";
3690 #address-cells = <2>; 3685 #address-cells = <2>;
3691 #size-cells = <2>; 3686 #size-cells = <2>;
3692 ranges; 3687 ranges;
3693 dma-ranges; 3688 dma-ranges;
3694 3689
3695 clocks = <&gcc GCC_CF 3690 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3691 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3692 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3693 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3694 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3695 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3696 clock-names = "cfg_noc",
3702 "core", 3697 "core",
3703 "iface" 3698 "iface",
3704 "sleep" 3699 "sleep",
3705 "mock_u 3700 "mock_utmi",
3706 "xo"; 3701 "xo";
3707 3702
3708 assigned-clocks = <&g 3703 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3704 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3705 assigned-clock-rates = <19200000>, <200000000>;
3711 3706
3712 interrupts-extended = 3707 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3713 3708 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3714 3709 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
3715 3710 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3716 3711 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>;
3717 interrupt-names = "pw 3712 interrupt-names = "pwr_event",
3718 "hs 3713 "hs_phy_irq",
3719 "dp 3714 "dp_hs_phy_irq",
3720 "dm 3715 "dm_hs_phy_irq",
3721 "ss 3716 "ss_phy_irq";
3722 3717
3723 power-domains = <&gcc 3718 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3719
3725 resets = <&gcc GCC_US 3720 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3721
3727 interconnects = <&agg 3722 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3728 <&gem 3723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3729 interconnect-names = 3724 interconnect-names = "usb-ddr", "apps-usb";
3730 3725
3731 usb_2_dwc3: usb@a8000 3726 usb_2_dwc3: usb@a800000 {
3732 compatible = 3727 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3728 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3729 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3730 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3731 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3732 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ 3733 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
3739 phy-names = " 3734 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3735 };
3741 }; 3736 };
3742 3737
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3738 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3739 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3740 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = 3741 #interconnect-cells = <2>;
3760 qcom,bcm-voters = <&a 3742 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3743 };
3762 3744
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 3745 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm 3746 compatible = "qcom,sm8150-mdss";
3777 reg = <0 0x0ae00000 0 3747 reg = <0 0x0ae00000 0 0x1000>;
3778 reg-names = "mdss"; 3748 reg-names = "mdss";
3779 3749
3780 interconnects = <&mms 3750 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3781 <&mms 3751 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3782 interconnect-names = 3752 interconnect-names = "mdp0-mem", "mdp1-mem";
3783 3753
3784 power-domains = <&dis 3754 power-domains = <&dispcc MDSS_GDSC>;
3785 3755
3786 clocks = <&dispcc DIS 3756 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 <&gcc GCC_DI 3757 <&gcc GCC_DISP_HF_AXI_CLK>,
3788 <&gcc GCC_DI 3758 <&gcc GCC_DISP_SF_AXI_CLK>,
3789 <&dispcc DIS 3759 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3790 clock-names = "iface" 3760 clock-names = "iface", "bus", "nrt_bus", "core";
3791 3761
3792 interrupts = <GIC_SPI 3762 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller; 3763 interrupt-controller;
3794 #interrupt-cells = <1 3764 #interrupt-cells = <1>;
3795 3765
3796 iommus = <&apps_smmu 3766 iommus = <&apps_smmu 0x800 0x420>;
3797 3767
3798 status = "disabled"; 3768 status = "disabled";
3799 3769
3800 #address-cells = <2>; 3770 #address-cells = <2>;
3801 #size-cells = <2>; 3771 #size-cells = <2>;
3802 ranges; 3772 ranges;
3803 3773
3804 mdss_mdp: display-con 3774 mdss_mdp: display-controller@ae01000 {
3805 compatible = 3775 compatible = "qcom,sm8150-dpu";
3806 reg = <0 0x0a 3776 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0a 3777 <0 0x0aeb0000 0 0x2008>;
3808 reg-names = " 3778 reg-names = "mdp", "vbif";
3809 3779
3810 clocks = <&di 3780 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3811 <&gc 3781 <&gcc GCC_DISP_HF_AXI_CLK>,
3812 <&di 3782 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3813 <&di 3783 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3814 clock-names = 3784 clock-names = "iface", "bus", "core", "vsync";
3815 3785
3816 assigned-cloc 3786 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-cloc 3787 assigned-clock-rates = <19200000>;
3818 3788
3819 operating-poi 3789 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains 3790 power-domains = <&rpmhpd SM8150_MMCX>;
3821 3791
3822 interrupt-par 3792 interrupt-parent = <&mdss>;
3823 interrupts = 3793 interrupts = <0>;
3824 3794
3825 ports { 3795 ports {
3826 #addr 3796 #address-cells = <1>;
3827 #size 3797 #size-cells = <0>;
3828 3798
3829 port@ 3799 port@0 {
3830 3800 reg = <0>;
3831 3801 dpu_intf1_out: endpoint {
3832 3802 remote-endpoint = <&mdss_dsi0_in>;
3833 3803 };
3834 }; 3804 };
3835 3805
3836 port@ 3806 port@1 {
3837 3807 reg = <1>;
3838 3808 dpu_intf2_out: endpoint {
3839 3809 remote-endpoint = <&mdss_dsi1_in>;
3840 3810 };
3841 }; 3811 };
3842 3812
3843 port@ 3813 port@2 {
3844 3814 reg = <2>;
3845 3815 dpu_intf0_out: endpoint {
3846 3816 remote-endpoint = <&mdss_dp_in>;
3847 3817 };
3848 }; 3818 };
3849 }; 3819 };
3850 3820
3851 mdp_opp_table 3821 mdp_opp_table: opp-table {
3852 compa 3822 compatible = "operating-points-v2";
3853 3823
3854 opp-1 3824 opp-171428571 {
3855 3825 opp-hz = /bits/ 64 <171428571>;
3856 3826 required-opps = <&rpmhpd_opp_low_svs>;
3857 }; 3827 };
3858 3828
3859 opp-3 3829 opp-300000000 {
3860 3830 opp-hz = /bits/ 64 <300000000>;
3861 3831 required-opps = <&rpmhpd_opp_svs>;
3862 }; 3832 };
3863 3833
3864 opp-3 3834 opp-345000000 {
3865 3835 opp-hz = /bits/ 64 <345000000>;
3866 3836 required-opps = <&rpmhpd_opp_svs_l1>;
3867 }; 3837 };
3868 3838
3869 opp-4 3839 opp-460000000 {
3870 3840 opp-hz = /bits/ 64 <460000000>;
3871 3841 required-opps = <&rpmhpd_opp_nom>;
3872 }; 3842 };
3873 }; 3843 };
3874 }; 3844 };
3875 3845
3876 mdss_dp: displayport- 3846 mdss_dp: displayport-controller@ae90000 {
3877 compatible = 3847 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3878 reg = <0 0xae 3848 reg = <0 0xae90000 0 0x200>,
3879 <0 0xae 3849 <0 0xae90200 0 0x200>,
3880 <0 0xae 3850 <0 0xae90400 0 0x600>,
3881 <0 0x0a 3851 <0 0x0ae90a00 0 0x600>,
3882 <0 0x0a 3852 <0 0x0ae91000 0 0x600>;
3883 3853
3884 interrupt-par 3854 interrupt-parent = <&mdss>;
3885 interrupts = 3855 interrupts = <12>;
3886 clocks = <&di 3856 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3887 <&di 3857 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3888 <&di 3858 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3889 <&di 3859 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3890 <&di 3860 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3891 clock-names = 3861 clock-names = "core_iface",
3892 3862 "core_aux",
3893 3863 "ctrl_link",
3894 3864 "ctrl_link_iface",
3895 3865 "stream_pixel";
3896 3866
3897 assigned-cloc 3867 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3898 3868 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3899 assigned-cloc 3869 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3900 3870 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3901 3871
3902 phys = <&usb_ 3872 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3903 phy-names = " 3873 phy-names = "dp";
3904 3874
3905 #sound-dai-ce 3875 #sound-dai-cells = <0>;
3906 3876
3907 operating-poi 3877 operating-points-v2 = <&dp_opp_table>;
3908 power-domains 3878 power-domains = <&rpmhpd SM8250_MMCX>;
3909 3879
3910 status = "dis 3880 status = "disabled";
3911 3881
3912 ports { 3882 ports {
3913 #addr 3883 #address-cells = <1>;
3914 #size 3884 #size-cells = <0>;
3915 3885
3916 port@ 3886 port@0 {
3917 3887 reg = <0>;
3918 3888 mdss_dp_in: endpoint {
3919 3889 remote-endpoint = <&dpu_intf0_out>;
3920 3890 };
3921 }; 3891 };
3922 3892
3923 port@ 3893 port@1 {
3924 3894 reg = <1>;
3925 3895
3926 3896 mdss_dp_out: endpoint {
3927 <<
3928 3897 };
3929 }; 3898 };
3930 }; 3899 };
3931 3900
3932 dp_opp_table: 3901 dp_opp_table: opp-table {
3933 compa 3902 compatible = "operating-points-v2";
3934 3903
3935 opp-1 3904 opp-160000000 {
3936 3905 opp-hz = /bits/ 64 <160000000>;
3937 3906 required-opps = <&rpmhpd_opp_low_svs>;
3938 }; 3907 };
3939 3908
3940 opp-2 3909 opp-270000000 {
3941 3910 opp-hz = /bits/ 64 <270000000>;
3942 3911 required-opps = <&rpmhpd_opp_svs>;
3943 }; 3912 };
3944 3913
3945 opp-5 3914 opp-540000000 {
3946 3915 opp-hz = /bits/ 64 <540000000>;
3947 3916 required-opps = <&rpmhpd_opp_svs_l1>;
3948 }; 3917 };
3949 3918
3950 opp-8 3919 opp-810000000 {
3951 3920 opp-hz = /bits/ 64 <810000000>;
3952 3921 required-opps = <&rpmhpd_opp_nom>;
3953 }; 3922 };
3954 }; 3923 };
3955 }; 3924 };
3956 3925
3957 mdss_dsi0: dsi@ae9400 3926 mdss_dsi0: dsi@ae94000 {
3958 compatible = 3927 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg = <0 0x0a 3928 reg = <0 0x0ae94000 0 0x400>;
3960 reg-names = " 3929 reg-names = "dsi_ctrl";
3961 3930
3962 interrupt-par 3931 interrupt-parent = <&mdss>;
3963 interrupts = 3932 interrupts = <4>;
3964 3933
3965 clocks = <&di 3934 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3966 <&di 3935 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3967 <&di 3936 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3968 <&di 3937 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3969 <&di 3938 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3970 <&gc 3939 <&gcc GCC_DISP_HF_AXI_CLK>;
3971 clock-names = 3940 clock-names = "byte",
3972 3941 "byte_intf",
3973 3942 "pixel",
3974 3943 "core",
3975 3944 "iface",
3976 3945 "bus";
3977 3946
3978 assigned-cloc 3947 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3979 3948 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3980 assigned-cloc 3949 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3981 3950 <&mdss_dsi0_phy 1>;
3982 3951
3983 operating-poi 3952 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains 3953 power-domains = <&rpmhpd SM8150_MMCX>;
3985 3954
3986 phys = <&mdss 3955 phys = <&mdss_dsi0_phy>;
3987 3956
3988 status = "dis 3957 status = "disabled";
3989 3958
3990 #address-cell 3959 #address-cells = <1>;
3991 #size-cells = 3960 #size-cells = <0>;
3992 3961
3993 ports { 3962 ports {
3994 #addr 3963 #address-cells = <1>;
3995 #size 3964 #size-cells = <0>;
3996 3965
3997 port@ 3966 port@0 {
3998 3967 reg = <0>;
3999 3968 mdss_dsi0_in: endpoint {
4000 3969 remote-endpoint = <&dpu_intf1_out>;
4001 3970 };
4002 }; 3971 };
4003 3972
4004 port@ 3973 port@1 {
4005 3974 reg = <1>;
4006 3975 mdss_dsi0_out: endpoint {
4007 3976 };
4008 }; 3977 };
4009 }; 3978 };
4010 3979
4011 dsi_opp_table 3980 dsi_opp_table: opp-table {
4012 compa 3981 compatible = "operating-points-v2";
4013 3982
4014 opp-1 3983 opp-187500000 {
4015 3984 opp-hz = /bits/ 64 <187500000>;
4016 3985 required-opps = <&rpmhpd_opp_low_svs>;
4017 }; 3986 };
4018 3987
4019 opp-3 3988 opp-300000000 {
4020 3989 opp-hz = /bits/ 64 <300000000>;
4021 3990 required-opps = <&rpmhpd_opp_svs>;
4022 }; 3991 };
4023 3992
4024 opp-3 3993 opp-358000000 {
4025 3994 opp-hz = /bits/ 64 <358000000>;
4026 3995 required-opps = <&rpmhpd_opp_svs_l1>;
4027 }; 3996 };
4028 }; 3997 };
4029 }; 3998 };
4030 3999
4031 mdss_dsi0_phy: phy@ae 4000 mdss_dsi0_phy: phy@ae94400 {
4032 compatible = 4001 compatible = "qcom,dsi-phy-7nm-8150";
4033 reg = <0 0x0a 4002 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0a 4003 <0 0x0ae94600 0 0x280>,
4035 <0 0x0a 4004 <0 0x0ae94900 0 0x260>;
4036 reg-names = " 4005 reg-names = "dsi_phy",
4037 " 4006 "dsi_phy_lane",
4038 " 4007 "dsi_pll";
4039 4008
4040 #clock-cells 4009 #clock-cells = <1>;
4041 #phy-cells = 4010 #phy-cells = <0>;
4042 4011
4043 clocks = <&di 4012 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4044 <&rp 4013 <&rpmhcc RPMH_CXO_CLK>;
4045 clock-names = 4014 clock-names = "iface", "ref";
4046 4015
4047 status = "dis 4016 status = "disabled";
4048 }; 4017 };
4049 4018
4050 mdss_dsi1: dsi@ae9600 4019 mdss_dsi1: dsi@ae96000 {
4051 compatible = 4020 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4052 reg = <0 0x0a 4021 reg = <0 0x0ae96000 0 0x400>;
4053 reg-names = " 4022 reg-names = "dsi_ctrl";
4054 4023
4055 interrupt-par 4024 interrupt-parent = <&mdss>;
4056 interrupts = 4025 interrupts = <5>;
4057 4026
4058 clocks = <&di 4027 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4059 <&di 4028 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4060 <&di 4029 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4061 <&di 4030 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4062 <&di 4031 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4063 <&gc 4032 <&gcc GCC_DISP_HF_AXI_CLK>;
4064 clock-names = 4033 clock-names = "byte",
4065 4034 "byte_intf",
4066 4035 "pixel",
4067 4036 "core",
4068 4037 "iface",
4069 4038 "bus";
4070 4039
4071 assigned-cloc 4040 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4072 4041 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4073 assigned-cloc 4042 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4074 4043 <&mdss_dsi1_phy 1>;
4075 4044
4076 operating-poi 4045 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains 4046 power-domains = <&rpmhpd SM8150_MMCX>;
4078 4047
4079 phys = <&mdss 4048 phys = <&mdss_dsi1_phy>;
4080 4049
4081 status = "dis 4050 status = "disabled";
4082 4051
4083 #address-cell 4052 #address-cells = <1>;
4084 #size-cells = 4053 #size-cells = <0>;
4085 4054
4086 ports { 4055 ports {
4087 #addr 4056 #address-cells = <1>;
4088 #size 4057 #size-cells = <0>;
4089 4058
4090 port@ 4059 port@0 {
4091 4060 reg = <0>;
4092 4061 mdss_dsi1_in: endpoint {
4093 4062 remote-endpoint = <&dpu_intf2_out>;
4094 4063 };
4095 }; 4064 };
4096 4065
4097 port@ 4066 port@1 {
4098 4067 reg = <1>;
4099 4068 mdss_dsi1_out: endpoint {
4100 4069 };
4101 }; 4070 };
4102 }; 4071 };
4103 }; 4072 };
4104 4073
4105 mdss_dsi1_phy: phy@ae 4074 mdss_dsi1_phy: phy@ae96400 {
4106 compatible = 4075 compatible = "qcom,dsi-phy-7nm-8150";
4107 reg = <0 0x0a 4076 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0a 4077 <0 0x0ae96600 0 0x280>,
4109 <0 0x0a 4078 <0 0x0ae96900 0 0x260>;
4110 reg-names = " 4079 reg-names = "dsi_phy",
4111 " 4080 "dsi_phy_lane",
4112 " 4081 "dsi_pll";
4113 4082
4114 #clock-cells 4083 #clock-cells = <1>;
4115 #phy-cells = 4084 #phy-cells = <0>;
4116 4085
4117 clocks = <&di 4086 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4118 <&rp 4087 <&rpmhcc RPMH_CXO_CLK>;
4119 clock-names = 4088 clock-names = "iface", "ref";
4120 4089
4121 status = "dis 4090 status = "disabled";
4122 }; 4091 };
4123 }; 4092 };
4124 4093
4125 dispcc: clock-controller@af00 4094 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm 4095 compatible = "qcom,sm8150-dispcc";
4127 reg = <0 0x0af00000 0 4096 reg = <0 0x0af00000 0 0x10000>;
4128 clocks = <&rpmhcc RPM 4097 clocks = <&rpmhcc RPMH_CXO_CLK>,
4129 <&mdss_dsi0_ 4098 <&mdss_dsi0_phy 0>,
4130 <&mdss_dsi0_ 4099 <&mdss_dsi0_phy 1>,
4131 <&mdss_dsi1_ 4100 <&mdss_dsi1_phy 0>,
4132 <&mdss_dsi1_ 4101 <&mdss_dsi1_phy 1>,
4133 <&usb_1_qmpp 4102 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4134 <&usb_1_qmpp 4103 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4135 clock-names = "bi_tcx 4104 clock-names = "bi_tcxo",
4136 "dsi0_p 4105 "dsi0_phy_pll_out_byteclk",
4137 "dsi0_p 4106 "dsi0_phy_pll_out_dsiclk",
4138 "dsi1_p 4107 "dsi1_phy_pll_out_byteclk",
4139 "dsi1_p 4108 "dsi1_phy_pll_out_dsiclk",
4140 "dp_phy 4109 "dp_phy_pll_link_clk",
4141 "dp_phy 4110 "dp_phy_pll_vco_div_clk";
4142 power-domains = <&rpm 4111 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpm 4112 required-opps = <&rpmhpd_opp_low_svs>;
4144 #clock-cells = <1>; 4113 #clock-cells = <1>;
4145 #reset-cells = <1>; 4114 #reset-cells = <1>;
4146 #power-domain-cells = 4115 #power-domain-cells = <1>;
4147 }; 4116 };
4148 4117
4149 pdc: interrupt-controller@b22 4118 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 4119 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 4120 reg = <0 0x0b220000 0 0x30000>;
4152 qcom,pdc-ranges = <0 4121 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 4122 <125 63 1>;
4154 #interrupt-cells = <2 4123 #interrupt-cells = <2>;
4155 interrupt-parent = <& 4124 interrupt-parent = <&intc>;
4156 interrupt-controller; 4125 interrupt-controller;
4157 }; 4126 };
4158 4127
4159 aoss_qmp: power-management@c3 4128 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm 4129 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 4130 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 4131 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 4132 mboxes = <&apss_shared 0>;
4164 4133
4165 #clock-cells = <0>; 4134 #clock-cells = <0>;
4166 }; 4135 };
4167 4136
4168 sram@c3f0000 { 4137 sram@c3f0000 {
4169 compatible = "qcom,rp 4138 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 4139 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 4140 };
4172 4141
4173 tsens0: thermal-sensor@c26300 4142 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 4143 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 4144 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 4145 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 4146 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 4147 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 4148 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 4149 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 4150 #thermal-sensor-cells = <1>;
4182 }; 4151 };
4183 4152
4184 tsens1: thermal-sensor@c26500 4153 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 4154 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 4155 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 4156 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 4157 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 4158 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 4159 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 4160 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 4161 #thermal-sensor-cells = <1>;
4193 }; 4162 };
4194 4163
4195 spmi_bus: spmi@c440000 { 4164 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 4165 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 4166 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 4167 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 4168 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 4169 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 4170 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 4171 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 4172 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 4173 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 4174 qcom,ee = <0>;
4206 qcom,channel = <0>; 4175 qcom,channel = <0>;
4207 #address-cells = <2>; 4176 #address-cells = <2>;
4208 #size-cells = <0>; 4177 #size-cells = <0>;
4209 interrupt-controller; 4178 interrupt-controller;
4210 #interrupt-cells = <4 4179 #interrupt-cells = <4>;
4211 }; 4180 };
4212 4181
4213 apps_smmu: iommu@15000000 { 4182 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm 4183 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 4184 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 4185 #iommu-cells = <2>;
4217 #global-interrupts = 4186 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 4187 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 4188 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 4189 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 4190 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 4191 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 4192 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 4193 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 4194 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 4195 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 4196 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 4197 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4198 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 4199 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 4200 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 4201 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 4202 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 4203 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 4204 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 4205 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4206 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 4207 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 4208 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 4209 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 4210 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 4211 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 4212 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 4213 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 4214 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 4215 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 4216 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 4217 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 4218 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 4219 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 4220 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 4221 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 4222 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 4223 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 4224 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 4225 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 4226 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 4227 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 4228 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 4229 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 4230 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 4231 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 4232 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 4233 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 4234 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 4235 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 4236 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 4237 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 4238 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 4239 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 4240 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 4241 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 4242 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 4243 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 4244 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 4245 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 4246 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 4247 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 4248 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 4249 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 4250 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 4251 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 4252 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 4253 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 4254 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 4255 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 4256 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 4257 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 4258 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 4259 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 4260 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 4261 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 4262 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 4263 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 4264 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 4265 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 4266 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 4267 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 4268 };
4300 4269
4301 remoteproc_adsp: remoteproc@1 4270 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 4271 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 4272 reg = <0x0 0x17300000 0x0 0x4040>;
4304 4273
4305 interrupts-extended = 4274 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 4275 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 4276 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 4277 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 4278 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 4279 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 4280 "handover", "stop-ack";
4312 4281
4313 clocks = <&rpmhcc RPM 4282 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 4283 clock-names = "xo";
4315 4284
4316 power-domains = <&rpm 4285 power-domains = <&rpmhpd SM8150_CX>;
4317 4286
4318 memory-region = <&ads 4287 memory-region = <&adsp_mem>;
4319 4288
4320 qcom,qmp = <&aoss_qmp 4289 qcom,qmp = <&aoss_qmp>;
4321 4290
4322 qcom,smem-states = <& 4291 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 4292 qcom,smem-state-names = "stop";
4324 4293
4325 status = "disabled"; 4294 status = "disabled";
4326 4295
4327 glink-edge { 4296 glink-edge {
4328 interrupts = 4297 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 4298 label = "lpass";
4330 qcom,remote-p 4299 qcom,remote-pid = <2>;
4331 mboxes = <&ap 4300 mboxes = <&apss_shared 8>;
4332 4301
4333 fastrpc { 4302 fastrpc {
4334 compa 4303 compatible = "qcom,fastrpc";
4335 qcom, 4304 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 4305 label = "adsp";
4337 qcom, 4306 qcom,non-secure-domain;
4338 #addr 4307 #address-cells = <1>;
4339 #size 4308 #size-cells = <0>;
4340 4309
4341 compu 4310 compute-cb@3 {
4342 4311 compatible = "qcom,fastrpc-compute-cb";
4343 4312 reg = <3>;
4344 4313 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 4314 };
4346 4315
4347 compu 4316 compute-cb@4 {
4348 4317 compatible = "qcom,fastrpc-compute-cb";
4349 4318 reg = <4>;
4350 4319 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 4320 };
4352 4321
4353 compu 4322 compute-cb@5 {
4354 4323 compatible = "qcom,fastrpc-compute-cb";
4355 4324 reg = <5>;
4356 4325 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 4326 };
4358 }; 4327 };
4359 }; 4328 };
4360 }; 4329 };
4361 4330
4362 intc: interrupt-controller@17 4331 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 4332 compatible = "arm,gic-v3";
4364 interrupt-controller; 4333 interrupt-controller;
4365 #interrupt-cells = <3 4334 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 4335 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 4336 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 4337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 4338 };
4370 4339
4371 apss_shared: mailbox@17c00000 4340 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm 4341 compatible = "qcom,sm8150-apss-shared",
4373 "qcom,sd 4342 "qcom,sdm845-apss-shared";
4374 reg = <0x0 0x17c00000 4343 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 4344 #mbox-cells = <1>;
4376 }; 4345 };
4377 4346
4378 watchdog@17c10000 { 4347 watchdog@17c10000 {
4379 compatible = "qcom,ap 4348 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 4349 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 4350 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI 4351 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4383 }; 4352 };
4384 4353
4385 timer@17c20000 { 4354 timer@17c20000 {
4386 #address-cells = <1>; 4355 #address-cells = <1>;
4387 #size-cells = <1>; 4356 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 4357 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 4358 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 4359 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 4360 clock-frequency = <19200000>;
4392 4361
4393 frame@17c21000 { 4362 frame@17c21000 {
4394 frame-number 4363 frame-number = <0>;
4395 interrupts = 4364 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 4365 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 4366 reg = <0x17c21000 0x1000>,
4398 <0x17c2 4367 <0x17c22000 0x1000>;
4399 }; 4368 };
4400 4369
4401 frame@17c23000 { 4370 frame@17c23000 {
4402 frame-number 4371 frame-number = <1>;
4403 interrupts = 4372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 4373 reg = <0x17c23000 0x1000>;
4405 status = "dis 4374 status = "disabled";
4406 }; 4375 };
4407 4376
4408 frame@17c25000 { 4377 frame@17c25000 {
4409 frame-number 4378 frame-number = <2>;
4410 interrupts = 4379 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 4380 reg = <0x17c25000 0x1000>;
4412 status = "dis 4381 status = "disabled";
4413 }; 4382 };
4414 4383
4415 frame@17c27000 { 4384 frame@17c27000 {
4416 frame-number 4385 frame-number = <3>;
4417 interrupts = 4386 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 4387 reg = <0x17c26000 0x1000>;
4419 status = "dis 4388 status = "disabled";
4420 }; 4389 };
4421 4390
4422 frame@17c29000 { 4391 frame@17c29000 {
4423 frame-number 4392 frame-number = <4>;
4424 interrupts = 4393 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 4394 reg = <0x17c29000 0x1000>;
4426 status = "dis 4395 status = "disabled";
4427 }; 4396 };
4428 4397
4429 frame@17c2b000 { 4398 frame@17c2b000 {
4430 frame-number 4399 frame-number = <5>;
4431 interrupts = 4400 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 4401 reg = <0x17c2b000 0x1000>;
4433 status = "dis 4402 status = "disabled";
4434 }; 4403 };
4435 4404
4436 frame@17c2d000 { 4405 frame@17c2d000 {
4437 frame-number 4406 frame-number = <6>;
4438 interrupts = 4407 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 4408 reg = <0x17c2d000 0x1000>;
4440 status = "dis 4409 status = "disabled";
4441 }; 4410 };
4442 }; 4411 };
4443 4412
4444 apps_rsc: rsc@18200000 { 4413 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 4414 label = "apps_rsc";
4446 compatible = "qcom,rp 4415 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 4416 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 4417 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 4418 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 4419 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 4420 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4421 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 4422 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 4423 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 4424 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 4425 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 4426 <SLEEP_TCS 3>,
4458 <WA 4427 <WAKE_TCS 3>,
4459 <CO 4428 <CONTROL_TCS 1>;
4460 power-domains = <&CLU 4429 power-domains = <&CLUSTER_PD>;
4461 4430
4462 rpmhcc: clock-control 4431 rpmhcc: clock-controller {
4463 compatible = 4432 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 4433 #clock-cells = <1>;
4465 clock-names = 4434 clock-names = "xo";
4466 clocks = <&xo 4435 clocks = <&xo_board>;
4467 }; 4436 };
4468 4437
4469 rpmhpd: power-control 4438 rpmhpd: power-controller {
4470 compatible = 4439 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 4440 #power-domain-cells = <1>;
4472 operating-poi 4441 operating-points-v2 = <&rpmhpd_opp_table>;
4473 4442
4474 rpmhpd_opp_ta 4443 rpmhpd_opp_table: opp-table {
4475 compa 4444 compatible = "operating-points-v2";
4476 4445
4477 rpmhp 4446 rpmhpd_opp_ret: opp1 {
4478 4447 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 4448 };
4480 4449
4481 rpmhp 4450 rpmhpd_opp_min_svs: opp2 {
4482 4451 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 4452 };
4484 4453
4485 rpmhp 4454 rpmhpd_opp_low_svs: opp3 {
4486 4455 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 4456 };
4488 4457
4489 rpmhp 4458 rpmhpd_opp_svs: opp4 {
4490 4459 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 4460 };
4492 4461
4493 rpmhp 4462 rpmhpd_opp_svs_l1: opp5 {
4494 4463 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 4464 };
4496 4465
4497 rpmhp 4466 rpmhpd_opp_svs_l2: opp6 {
4498 4467 opp-level = <224>;
4499 }; 4468 };
4500 4469
4501 rpmhp 4470 rpmhpd_opp_nom: opp7 {
4502 4471 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 4472 };
4504 4473
4505 rpmhp 4474 rpmhpd_opp_nom_l1: opp8 {
4506 4475 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 4476 };
4508 4477
4509 rpmhp 4478 rpmhpd_opp_nom_l2: opp9 {
4510 4479 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 4480 };
4512 4481
4513 rpmhp 4482 rpmhpd_opp_turbo: opp10 {
4514 4483 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 4484 };
4516 4485
4517 rpmhp 4486 rpmhpd_opp_turbo_l1: opp11 {
4518 4487 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 4488 };
4520 }; 4489 };
4521 }; 4490 };
4522 4491
4523 apps_bcm_voter: bcm-v 4492 apps_bcm_voter: bcm-voter {
4524 compatible = 4493 compatible = "qcom,bcm-voter";
4525 }; 4494 };
4526 }; 4495 };
4527 4496
4528 osm_l3: interconnect@18321000 4497 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm 4498 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 4499 reg = <0 0x18321000 0 0x1400>;
4531 4500
4532 clocks = <&rpmhcc RPM 4501 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 4502 clock-names = "xo", "alternate";
4534 4503
4535 #interconnect-cells = 4504 #interconnect-cells = <1>;
4536 }; 4505 };
4537 4506
4538 cpufreq_hw: cpufreq@18323000 4507 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm 4508 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 4509 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 4510 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 4511 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 4512 "freq-domain2";
4544 4513
4545 clocks = <&rpmhcc RPM 4514 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 4515 clock-names = "xo", "alternate";
4547 4516
4548 #freq-domain-cells = 4517 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; 4518 #clock-cells = <1>;
4550 }; 4519 };
4551 4520
4552 lmh_cluster1: lmh@18350800 { 4521 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 4522 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 4523 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 4524 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 4525 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 4526 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 4527 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 4528 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 4529 interrupt-controller;
4561 #interrupt-cells = <1 4530 #interrupt-cells = <1>;
4562 }; 4531 };
4563 4532
4564 lmh_cluster0: lmh@18358800 { 4533 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 4534 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 4535 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 4536 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4537 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4538 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4539 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4540 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4541 interrupt-controller;
4573 #interrupt-cells = <1 4542 #interrupt-cells = <1>;
4574 }; 4543 };
4575 4544
4576 wifi: wifi@18800000 { 4545 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4546 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4547 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4548 reg-names = "membase";
4580 memory-region = <&wla 4549 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4550 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4551 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4552 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4553 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4554 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4555 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4556 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4557 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4558 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4559 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4560 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4561 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4562 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4563 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4564 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4565 status = "disabled";
4597 }; 4566 };
4598 }; 4567 };
4599 4568
4600 timer { 4569 timer {
4601 compatible = "arm,armv8-timer 4570 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4571 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4572 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4573 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4574 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4575 };
4607 4576
4608 thermal-zones { 4577 thermal-zones {
4609 cpu0-thermal { 4578 cpu0-thermal {
4610 polling-delay-passive 4579 polling-delay-passive = <250>;
>> 4580 polling-delay = <1000>;
4611 4581
4612 thermal-sensors = <&t 4582 thermal-sensors = <&tsens0 1>;
4613 4583
4614 trips { 4584 trips {
4615 cpu0_alert0: 4585 cpu0_alert0: trip-point0 {
4616 tempe 4586 temperature = <90000>;
4617 hyste 4587 hysteresis = <2000>;
4618 type 4588 type = "passive";
4619 }; 4589 };
4620 4590
4621 cpu0_alert1: 4591 cpu0_alert1: trip-point1 {
4622 tempe 4592 temperature = <95000>;
4623 hyste 4593 hysteresis = <2000>;
4624 type 4594 type = "passive";
4625 }; 4595 };
4626 4596
4627 cpu0_crit: cp 4597 cpu0_crit: cpu-crit {
4628 tempe 4598 temperature = <110000>;
4629 hyste 4599 hysteresis = <1000>;
4630 type 4600 type = "critical";
4631 }; 4601 };
4632 }; 4602 };
4633 4603
4634 cooling-maps { 4604 cooling-maps {
4635 map0 { 4605 map0 {
4636 trip 4606 trip = <&cpu0_alert0>;
4637 cooli 4607 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4608 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4609 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4610 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4611 };
4642 map1 { 4612 map1 {
4643 trip 4613 trip = <&cpu0_alert1>;
4644 cooli 4614 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4615 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4616 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4617 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4618 };
4649 }; 4619 };
4650 }; 4620 };
4651 4621
4652 cpu1-thermal { 4622 cpu1-thermal {
4653 polling-delay-passive 4623 polling-delay-passive = <250>;
>> 4624 polling-delay = <1000>;
4654 4625
4655 thermal-sensors = <&t 4626 thermal-sensors = <&tsens0 2>;
4656 4627
4657 trips { 4628 trips {
4658 cpu1_alert0: 4629 cpu1_alert0: trip-point0 {
4659 tempe 4630 temperature = <90000>;
4660 hyste 4631 hysteresis = <2000>;
4661 type 4632 type = "passive";
4662 }; 4633 };
4663 4634
4664 cpu1_alert1: 4635 cpu1_alert1: trip-point1 {
4665 tempe 4636 temperature = <95000>;
4666 hyste 4637 hysteresis = <2000>;
4667 type 4638 type = "passive";
4668 }; 4639 };
4669 4640
4670 cpu1_crit: cp 4641 cpu1_crit: cpu-crit {
4671 tempe 4642 temperature = <110000>;
4672 hyste 4643 hysteresis = <1000>;
4673 type 4644 type = "critical";
4674 }; 4645 };
4675 }; 4646 };
4676 4647
4677 cooling-maps { 4648 cooling-maps {
4678 map0 { 4649 map0 {
4679 trip 4650 trip = <&cpu1_alert0>;
4680 cooli 4651 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4652 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4653 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4654 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4655 };
4685 map1 { 4656 map1 {
4686 trip 4657 trip = <&cpu1_alert1>;
4687 cooli 4658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4659 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4660 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4661 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4662 };
4692 }; 4663 };
4693 }; 4664 };
4694 4665
4695 cpu2-thermal { 4666 cpu2-thermal {
4696 polling-delay-passive 4667 polling-delay-passive = <250>;
>> 4668 polling-delay = <1000>;
4697 4669
4698 thermal-sensors = <&t 4670 thermal-sensors = <&tsens0 3>;
4699 4671
4700 trips { 4672 trips {
4701 cpu2_alert0: 4673 cpu2_alert0: trip-point0 {
4702 tempe 4674 temperature = <90000>;
4703 hyste 4675 hysteresis = <2000>;
4704 type 4676 type = "passive";
4705 }; 4677 };
4706 4678
4707 cpu2_alert1: 4679 cpu2_alert1: trip-point1 {
4708 tempe 4680 temperature = <95000>;
4709 hyste 4681 hysteresis = <2000>;
4710 type 4682 type = "passive";
4711 }; 4683 };
4712 4684
4713 cpu2_crit: cp 4685 cpu2_crit: cpu-crit {
4714 tempe 4686 temperature = <110000>;
4715 hyste 4687 hysteresis = <1000>;
4716 type 4688 type = "critical";
4717 }; 4689 };
4718 }; 4690 };
4719 4691
4720 cooling-maps { 4692 cooling-maps {
4721 map0 { 4693 map0 {
4722 trip 4694 trip = <&cpu2_alert0>;
4723 cooli 4695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4699 };
4728 map1 { 4700 map1 {
4729 trip 4701 trip = <&cpu2_alert1>;
4730 cooli 4702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4703 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4704 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4705 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4706 };
4735 }; 4707 };
4736 }; 4708 };
4737 4709
4738 cpu3-thermal { 4710 cpu3-thermal {
4739 polling-delay-passive 4711 polling-delay-passive = <250>;
>> 4712 polling-delay = <1000>;
4740 4713
4741 thermal-sensors = <&t 4714 thermal-sensors = <&tsens0 4>;
4742 4715
4743 trips { 4716 trips {
4744 cpu3_alert0: 4717 cpu3_alert0: trip-point0 {
4745 tempe 4718 temperature = <90000>;
4746 hyste 4719 hysteresis = <2000>;
4747 type 4720 type = "passive";
4748 }; 4721 };
4749 4722
4750 cpu3_alert1: 4723 cpu3_alert1: trip-point1 {
4751 tempe 4724 temperature = <95000>;
4752 hyste 4725 hysteresis = <2000>;
4753 type 4726 type = "passive";
4754 }; 4727 };
4755 4728
4756 cpu3_crit: cp 4729 cpu3_crit: cpu-crit {
4757 tempe 4730 temperature = <110000>;
4758 hyste 4731 hysteresis = <1000>;
4759 type 4732 type = "critical";
4760 }; 4733 };
4761 }; 4734 };
4762 4735
4763 cooling-maps { 4736 cooling-maps {
4764 map0 { 4737 map0 {
4765 trip 4738 trip = <&cpu3_alert0>;
4766 cooli 4739 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4740 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4741 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4742 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4743 };
4771 map1 { 4744 map1 {
4772 trip 4745 trip = <&cpu3_alert1>;
4773 cooli 4746 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4747 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4748 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4749 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4750 };
4778 }; 4751 };
4779 }; 4752 };
4780 4753
4781 cpu4-top-thermal { 4754 cpu4-top-thermal {
4782 polling-delay-passive 4755 polling-delay-passive = <250>;
>> 4756 polling-delay = <1000>;
4783 4757
4784 thermal-sensors = <&t 4758 thermal-sensors = <&tsens0 7>;
4785 4759
4786 trips { 4760 trips {
4787 cpu4_top_aler 4761 cpu4_top_alert0: trip-point0 {
4788 tempe 4762 temperature = <90000>;
4789 hyste 4763 hysteresis = <2000>;
4790 type 4764 type = "passive";
4791 }; 4765 };
4792 4766
4793 cpu4_top_aler 4767 cpu4_top_alert1: trip-point1 {
4794 tempe 4768 temperature = <95000>;
4795 hyste 4769 hysteresis = <2000>;
4796 type 4770 type = "passive";
4797 }; 4771 };
4798 4772
4799 cpu4_top_crit 4773 cpu4_top_crit: cpu-crit {
4800 tempe 4774 temperature = <110000>;
4801 hyste 4775 hysteresis = <1000>;
4802 type 4776 type = "critical";
4803 }; 4777 };
4804 }; 4778 };
4805 4779
4806 cooling-maps { 4780 cooling-maps {
4807 map0 { 4781 map0 {
4808 trip 4782 trip = <&cpu4_top_alert0>;
4809 cooli 4783 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4784 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4785 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4786 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4787 };
4814 map1 { 4788 map1 {
4815 trip 4789 trip = <&cpu4_top_alert1>;
4816 cooli 4790 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4791 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4792 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4793 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4794 };
4821 }; 4795 };
4822 }; 4796 };
4823 4797
4824 cpu5-top-thermal { 4798 cpu5-top-thermal {
4825 polling-delay-passive 4799 polling-delay-passive = <250>;
>> 4800 polling-delay = <1000>;
4826 4801
4827 thermal-sensors = <&t 4802 thermal-sensors = <&tsens0 8>;
4828 4803
4829 trips { 4804 trips {
4830 cpu5_top_aler 4805 cpu5_top_alert0: trip-point0 {
4831 tempe 4806 temperature = <90000>;
4832 hyste 4807 hysteresis = <2000>;
4833 type 4808 type = "passive";
4834 }; 4809 };
4835 4810
4836 cpu5_top_aler 4811 cpu5_top_alert1: trip-point1 {
4837 tempe 4812 temperature = <95000>;
4838 hyste 4813 hysteresis = <2000>;
4839 type 4814 type = "passive";
4840 }; 4815 };
4841 4816
4842 cpu5_top_crit 4817 cpu5_top_crit: cpu-crit {
4843 tempe 4818 temperature = <110000>;
4844 hyste 4819 hysteresis = <1000>;
4845 type 4820 type = "critical";
4846 }; 4821 };
4847 }; 4822 };
4848 4823
4849 cooling-maps { 4824 cooling-maps {
4850 map0 { 4825 map0 {
4851 trip 4826 trip = <&cpu5_top_alert0>;
4852 cooli 4827 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4828 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4829 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4830 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4831 };
4857 map1 { 4832 map1 {
4858 trip 4833 trip = <&cpu5_top_alert1>;
4859 cooli 4834 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4835 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4836 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4837 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4838 };
4864 }; 4839 };
4865 }; 4840 };
4866 4841
4867 cpu6-top-thermal { 4842 cpu6-top-thermal {
4868 polling-delay-passive 4843 polling-delay-passive = <250>;
>> 4844 polling-delay = <1000>;
4869 4845
4870 thermal-sensors = <&t 4846 thermal-sensors = <&tsens0 9>;
4871 4847
4872 trips { 4848 trips {
4873 cpu6_top_aler 4849 cpu6_top_alert0: trip-point0 {
4874 tempe 4850 temperature = <90000>;
4875 hyste 4851 hysteresis = <2000>;
4876 type 4852 type = "passive";
4877 }; 4853 };
4878 4854
4879 cpu6_top_aler 4855 cpu6_top_alert1: trip-point1 {
4880 tempe 4856 temperature = <95000>;
4881 hyste 4857 hysteresis = <2000>;
4882 type 4858 type = "passive";
4883 }; 4859 };
4884 4860
4885 cpu6_top_crit 4861 cpu6_top_crit: cpu-crit {
4886 tempe 4862 temperature = <110000>;
4887 hyste 4863 hysteresis = <1000>;
4888 type 4864 type = "critical";
4889 }; 4865 };
4890 }; 4866 };
4891 4867
4892 cooling-maps { 4868 cooling-maps {
4893 map0 { 4869 map0 {
4894 trip 4870 trip = <&cpu6_top_alert0>;
4895 cooli 4871 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4873 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4874 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4875 };
4900 map1 { 4876 map1 {
4901 trip 4877 trip = <&cpu6_top_alert1>;
4902 cooli 4878 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4880 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4881 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4882 };
4907 }; 4883 };
4908 }; 4884 };
4909 4885
4910 cpu7-top-thermal { 4886 cpu7-top-thermal {
4911 polling-delay-passive 4887 polling-delay-passive = <250>;
>> 4888 polling-delay = <1000>;
4912 4889
4913 thermal-sensors = <&t 4890 thermal-sensors = <&tsens0 10>;
4914 4891
4915 trips { 4892 trips {
4916 cpu7_top_aler 4893 cpu7_top_alert0: trip-point0 {
4917 tempe 4894 temperature = <90000>;
4918 hyste 4895 hysteresis = <2000>;
4919 type 4896 type = "passive";
4920 }; 4897 };
4921 4898
4922 cpu7_top_aler 4899 cpu7_top_alert1: trip-point1 {
4923 tempe 4900 temperature = <95000>;
4924 hyste 4901 hysteresis = <2000>;
4925 type 4902 type = "passive";
4926 }; 4903 };
4927 4904
4928 cpu7_top_crit 4905 cpu7_top_crit: cpu-crit {
4929 tempe 4906 temperature = <110000>;
4930 hyste 4907 hysteresis = <1000>;
4931 type 4908 type = "critical";
4932 }; 4909 };
4933 }; 4910 };
4934 4911
4935 cooling-maps { 4912 cooling-maps {
4936 map0 { 4913 map0 {
4937 trip 4914 trip = <&cpu7_top_alert0>;
4938 cooli 4915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4919 };
4943 map1 { 4920 map1 {
4944 trip 4921 trip = <&cpu7_top_alert1>;
4945 cooli 4922 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4923 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4924 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4925 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4926 };
4950 }; 4927 };
4951 }; 4928 };
4952 4929
4953 cpu4-bottom-thermal { 4930 cpu4-bottom-thermal {
4954 polling-delay-passive 4931 polling-delay-passive = <250>;
>> 4932 polling-delay = <1000>;
4955 4933
4956 thermal-sensors = <&t 4934 thermal-sensors = <&tsens0 11>;
4957 4935
4958 trips { 4936 trips {
4959 cpu4_bottom_a 4937 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4938 temperature = <90000>;
4961 hyste 4939 hysteresis = <2000>;
4962 type 4940 type = "passive";
4963 }; 4941 };
4964 4942
4965 cpu4_bottom_a 4943 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4944 temperature = <95000>;
4967 hyste 4945 hysteresis = <2000>;
4968 type 4946 type = "passive";
4969 }; 4947 };
4970 4948
4971 cpu4_bottom_c 4949 cpu4_bottom_crit: cpu-crit {
4972 tempe 4950 temperature = <110000>;
4973 hyste 4951 hysteresis = <1000>;
4974 type 4952 type = "critical";
4975 }; 4953 };
4976 }; 4954 };
4977 4955
4978 cooling-maps { 4956 cooling-maps {
4979 map0 { 4957 map0 {
4980 trip 4958 trip = <&cpu4_bottom_alert0>;
4981 cooli 4959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4963 };
4986 map1 { 4964 map1 {
4987 trip 4965 trip = <&cpu4_bottom_alert1>;
4988 cooli 4966 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4967 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4968 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4969 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4970 };
4993 }; 4971 };
4994 }; 4972 };
4995 4973
4996 cpu5-bottom-thermal { 4974 cpu5-bottom-thermal {
4997 polling-delay-passive 4975 polling-delay-passive = <250>;
>> 4976 polling-delay = <1000>;
4998 4977
4999 thermal-sensors = <&t 4978 thermal-sensors = <&tsens0 12>;
5000 4979
5001 trips { 4980 trips {
5002 cpu5_bottom_a 4981 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4982 temperature = <90000>;
5004 hyste 4983 hysteresis = <2000>;
5005 type 4984 type = "passive";
5006 }; 4985 };
5007 4986
5008 cpu5_bottom_a 4987 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4988 temperature = <95000>;
5010 hyste 4989 hysteresis = <2000>;
5011 type 4990 type = "passive";
5012 }; 4991 };
5013 4992
5014 cpu5_bottom_c 4993 cpu5_bottom_crit: cpu-crit {
5015 tempe 4994 temperature = <110000>;
5016 hyste 4995 hysteresis = <1000>;
5017 type 4996 type = "critical";
5018 }; 4997 };
5019 }; 4998 };
5020 4999
5021 cooling-maps { 5000 cooling-maps {
5022 map0 { 5001 map0 {
5023 trip 5002 trip = <&cpu5_bottom_alert0>;
5024 cooli 5003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 5004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 5005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 5006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 5007 };
5029 map1 { 5008 map1 {
5030 trip 5009 trip = <&cpu5_bottom_alert1>;
5031 cooli 5010 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 5011 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 5012 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 5013 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 5014 };
5036 }; 5015 };
5037 }; 5016 };
5038 5017
5039 cpu6-bottom-thermal { 5018 cpu6-bottom-thermal {
5040 polling-delay-passive 5019 polling-delay-passive = <250>;
>> 5020 polling-delay = <1000>;
5041 5021
5042 thermal-sensors = <&t 5022 thermal-sensors = <&tsens0 13>;
5043 5023
5044 trips { 5024 trips {
5045 cpu6_bottom_a 5025 cpu6_bottom_alert0: trip-point0 {
5046 tempe 5026 temperature = <90000>;
5047 hyste 5027 hysteresis = <2000>;
5048 type 5028 type = "passive";
5049 }; 5029 };
5050 5030
5051 cpu6_bottom_a 5031 cpu6_bottom_alert1: trip-point1 {
5052 tempe 5032 temperature = <95000>;
5053 hyste 5033 hysteresis = <2000>;
5054 type 5034 type = "passive";
5055 }; 5035 };
5056 5036
5057 cpu6_bottom_c 5037 cpu6_bottom_crit: cpu-crit {
5058 tempe 5038 temperature = <110000>;
5059 hyste 5039 hysteresis = <1000>;
5060 type 5040 type = "critical";
5061 }; 5041 };
5062 }; 5042 };
5063 5043
5064 cooling-maps { 5044 cooling-maps {
5065 map0 { 5045 map0 {
5066 trip 5046 trip = <&cpu6_bottom_alert0>;
5067 cooli 5047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 5048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 5049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 5050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 5051 };
5072 map1 { 5052 map1 {
5073 trip 5053 trip = <&cpu6_bottom_alert1>;
5074 cooli 5054 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 5055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 5056 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 5057 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 5058 };
5079 }; 5059 };
5080 }; 5060 };
5081 5061
5082 cpu7-bottom-thermal { 5062 cpu7-bottom-thermal {
5083 polling-delay-passive 5063 polling-delay-passive = <250>;
>> 5064 polling-delay = <1000>;
5084 5065
5085 thermal-sensors = <&t 5066 thermal-sensors = <&tsens0 14>;
5086 5067
5087 trips { 5068 trips {
5088 cpu7_bottom_a 5069 cpu7_bottom_alert0: trip-point0 {
5089 tempe 5070 temperature = <90000>;
5090 hyste 5071 hysteresis = <2000>;
5091 type 5072 type = "passive";
5092 }; 5073 };
5093 5074
5094 cpu7_bottom_a 5075 cpu7_bottom_alert1: trip-point1 {
5095 tempe 5076 temperature = <95000>;
5096 hyste 5077 hysteresis = <2000>;
5097 type 5078 type = "passive";
5098 }; 5079 };
5099 5080
5100 cpu7_bottom_c 5081 cpu7_bottom_crit: cpu-crit {
5101 tempe 5082 temperature = <110000>;
5102 hyste 5083 hysteresis = <1000>;
5103 type 5084 type = "critical";
5104 }; 5085 };
5105 }; 5086 };
5106 5087
5107 cooling-maps { 5088 cooling-maps {
5108 map0 { 5089 map0 {
5109 trip 5090 trip = <&cpu7_bottom_alert0>;
5110 cooli 5091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 5092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 5093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 5094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 5095 };
5115 map1 { 5096 map1 {
5116 trip 5097 trip = <&cpu7_bottom_alert1>;
5117 cooli 5098 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 5099 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 5100 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 5101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 5102 };
5122 }; 5103 };
5123 }; 5104 };
5124 5105
5125 aoss0-thermal { 5106 aoss0-thermal {
5126 polling-delay-passive 5107 polling-delay-passive = <250>;
>> 5108 polling-delay = <1000>;
5127 5109
5128 thermal-sensors = <&t 5110 thermal-sensors = <&tsens0 0>;
5129 5111
5130 trips { 5112 trips {
5131 aoss0_alert0: 5113 aoss0_alert0: trip-point0 {
5132 tempe 5114 temperature = <90000>;
5133 hyste 5115 hysteresis = <2000>;
5134 type 5116 type = "hot";
5135 }; 5117 };
5136 }; 5118 };
5137 }; 5119 };
5138 5120
5139 cluster0-thermal { 5121 cluster0-thermal {
5140 polling-delay-passive 5122 polling-delay-passive = <250>;
>> 5123 polling-delay = <1000>;
5141 5124
5142 thermal-sensors = <&t 5125 thermal-sensors = <&tsens0 5>;
5143 5126
5144 trips { 5127 trips {
5145 cluster0_aler 5128 cluster0_alert0: trip-point0 {
5146 tempe 5129 temperature = <90000>;
5147 hyste 5130 hysteresis = <2000>;
5148 type 5131 type = "hot";
5149 }; 5132 };
5150 cluster0_crit 5133 cluster0_crit: cluster0-crit {
5151 tempe 5134 temperature = <110000>;
5152 hyste 5135 hysteresis = <2000>;
5153 type 5136 type = "critical";
5154 }; 5137 };
5155 }; 5138 };
5156 }; 5139 };
5157 5140
5158 cluster1-thermal { 5141 cluster1-thermal {
5159 polling-delay-passive 5142 polling-delay-passive = <250>;
>> 5143 polling-delay = <1000>;
5160 5144
5161 thermal-sensors = <&t 5145 thermal-sensors = <&tsens0 6>;
5162 5146
5163 trips { 5147 trips {
5164 cluster1_aler 5148 cluster1_alert0: trip-point0 {
5165 tempe 5149 temperature = <90000>;
5166 hyste 5150 hysteresis = <2000>;
5167 type 5151 type = "hot";
5168 }; 5152 };
5169 cluster1_crit 5153 cluster1_crit: cluster1-crit {
5170 tempe 5154 temperature = <110000>;
5171 hyste 5155 hysteresis = <2000>;
5172 type 5156 type = "critical";
5173 }; 5157 };
5174 }; 5158 };
5175 }; 5159 };
5176 5160
5177 gpu-top-thermal { 5161 gpu-top-thermal {
5178 polling-delay-passive 5162 polling-delay-passive = <250>;
>> 5163 polling-delay = <1000>;
5179 5164
5180 thermal-sensors = <&t 5165 thermal-sensors = <&tsens0 15>;
5181 5166
5182 cooling-maps { 5167 cooling-maps {
5183 map0 { 5168 map0 {
5184 trip 5169 trip = <&gpu_top_alert0>;
5185 cooli 5170 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5186 }; 5171 };
5187 }; 5172 };
5188 5173
5189 trips { 5174 trips {
5190 gpu_top_alert 5175 gpu_top_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 5176 temperature = <90000>;
5198 hyste !! 5177 hysteresis = <2000>;
5199 type 5178 type = "hot";
5200 }; 5179 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 5180 };
5208 }; 5181 };
5209 5182
5210 aoss1-thermal { 5183 aoss1-thermal {
5211 polling-delay-passive 5184 polling-delay-passive = <250>;
>> 5185 polling-delay = <1000>;
5212 5186
5213 thermal-sensors = <&t 5187 thermal-sensors = <&tsens1 0>;
5214 5188
5215 trips { 5189 trips {
5216 aoss1_alert0: 5190 aoss1_alert0: trip-point0 {
5217 tempe 5191 temperature = <90000>;
5218 hyste 5192 hysteresis = <2000>;
5219 type 5193 type = "hot";
5220 }; 5194 };
5221 }; 5195 };
5222 }; 5196 };
5223 5197
5224 wlan-thermal { 5198 wlan-thermal {
5225 polling-delay-passive 5199 polling-delay-passive = <250>;
>> 5200 polling-delay = <1000>;
5226 5201
5227 thermal-sensors = <&t 5202 thermal-sensors = <&tsens1 1>;
5228 5203
5229 trips { 5204 trips {
5230 wlan_alert0: 5205 wlan_alert0: trip-point0 {
5231 tempe 5206 temperature = <90000>;
5232 hyste 5207 hysteresis = <2000>;
5233 type 5208 type = "hot";
5234 }; 5209 };
5235 }; 5210 };
5236 }; 5211 };
5237 5212
5238 video-thermal { 5213 video-thermal {
5239 polling-delay-passive 5214 polling-delay-passive = <250>;
>> 5215 polling-delay = <1000>;
5240 5216
5241 thermal-sensors = <&t 5217 thermal-sensors = <&tsens1 2>;
5242 5218
5243 trips { 5219 trips {
5244 video_alert0: 5220 video_alert0: trip-point0 {
5245 tempe 5221 temperature = <90000>;
5246 hyste 5222 hysteresis = <2000>;
5247 type 5223 type = "hot";
5248 }; 5224 };
5249 }; 5225 };
5250 }; 5226 };
5251 5227
5252 mem-thermal { 5228 mem-thermal {
5253 polling-delay-passive 5229 polling-delay-passive = <250>;
>> 5230 polling-delay = <1000>;
5254 5231
5255 thermal-sensors = <&t 5232 thermal-sensors = <&tsens1 3>;
5256 5233
5257 trips { 5234 trips {
5258 mem_alert0: t 5235 mem_alert0: trip-point0 {
5259 tempe 5236 temperature = <90000>;
5260 hyste 5237 hysteresis = <2000>;
5261 type 5238 type = "hot";
5262 }; 5239 };
5263 }; 5240 };
5264 }; 5241 };
5265 5242
5266 q6-hvx-thermal { 5243 q6-hvx-thermal {
5267 polling-delay-passive 5244 polling-delay-passive = <250>;
>> 5245 polling-delay = <1000>;
5268 5246
5269 thermal-sensors = <&t 5247 thermal-sensors = <&tsens1 4>;
5270 5248
5271 trips { 5249 trips {
5272 q6_hvx_alert0 5250 q6_hvx_alert0: trip-point0 {
5273 tempe 5251 temperature = <90000>;
5274 hyste 5252 hysteresis = <2000>;
5275 type 5253 type = "hot";
5276 }; 5254 };
5277 }; 5255 };
5278 }; 5256 };
5279 5257
5280 camera-thermal { 5258 camera-thermal {
5281 polling-delay-passive 5259 polling-delay-passive = <250>;
>> 5260 polling-delay = <1000>;
5282 5261
5283 thermal-sensors = <&t 5262 thermal-sensors = <&tsens1 5>;
5284 5263
5285 trips { 5264 trips {
5286 camera_alert0 5265 camera_alert0: trip-point0 {
5287 tempe 5266 temperature = <90000>;
5288 hyste 5267 hysteresis = <2000>;
5289 type 5268 type = "hot";
5290 }; 5269 };
5291 }; 5270 };
5292 }; 5271 };
5293 5272
5294 compute-thermal { 5273 compute-thermal {
5295 polling-delay-passive 5274 polling-delay-passive = <250>;
>> 5275 polling-delay = <1000>;
5296 5276
5297 thermal-sensors = <&t 5277 thermal-sensors = <&tsens1 6>;
5298 5278
5299 trips { 5279 trips {
5300 compute_alert 5280 compute_alert0: trip-point0 {
5301 tempe 5281 temperature = <90000>;
5302 hyste 5282 hysteresis = <2000>;
5303 type 5283 type = "hot";
5304 }; 5284 };
5305 }; 5285 };
5306 }; 5286 };
5307 5287
5308 modem-thermal { 5288 modem-thermal {
5309 polling-delay-passive 5289 polling-delay-passive = <250>;
>> 5290 polling-delay = <1000>;
5310 5291
5311 thermal-sensors = <&t 5292 thermal-sensors = <&tsens1 7>;
5312 5293
5313 trips { 5294 trips {
5314 modem_alert0: 5295 modem_alert0: trip-point0 {
5315 tempe 5296 temperature = <90000>;
5316 hyste 5297 hysteresis = <2000>;
5317 type 5298 type = "hot";
5318 }; 5299 };
5319 }; 5300 };
5320 }; 5301 };
5321 5302
5322 npu-thermal { 5303 npu-thermal {
5323 polling-delay-passive 5304 polling-delay-passive = <250>;
>> 5305 polling-delay = <1000>;
5324 5306
5325 thermal-sensors = <&t 5307 thermal-sensors = <&tsens1 8>;
5326 5308
5327 trips { 5309 trips {
5328 npu_alert0: t 5310 npu_alert0: trip-point0 {
5329 tempe 5311 temperature = <90000>;
5330 hyste 5312 hysteresis = <2000>;
5331 type 5313 type = "hot";
5332 }; 5314 };
5333 }; 5315 };
5334 }; 5316 };
5335 5317
5336 modem-vec-thermal { 5318 modem-vec-thermal {
5337 polling-delay-passive 5319 polling-delay-passive = <250>;
>> 5320 polling-delay = <1000>;
5338 5321
5339 thermal-sensors = <&t 5322 thermal-sensors = <&tsens1 9>;
5340 5323
5341 trips { 5324 trips {
5342 modem_vec_ale 5325 modem_vec_alert0: trip-point0 {
5343 tempe 5326 temperature = <90000>;
5344 hyste 5327 hysteresis = <2000>;
5345 type 5328 type = "hot";
5346 }; 5329 };
5347 }; 5330 };
5348 }; 5331 };
5349 5332
5350 modem-scl-thermal { 5333 modem-scl-thermal {
5351 polling-delay-passive 5334 polling-delay-passive = <250>;
>> 5335 polling-delay = <1000>;
5352 5336
5353 thermal-sensors = <&t 5337 thermal-sensors = <&tsens1 10>;
5354 5338
5355 trips { 5339 trips {
5356 modem_scl_ale 5340 modem_scl_alert0: trip-point0 {
5357 tempe 5341 temperature = <90000>;
5358 hyste 5342 hysteresis = <2000>;
5359 type 5343 type = "hot";
5360 }; 5344 };
5361 }; 5345 };
5362 }; 5346 };
5363 5347
5364 gpu-bottom-thermal { 5348 gpu-bottom-thermal {
5365 polling-delay-passive 5349 polling-delay-passive = <250>;
>> 5350 polling-delay = <1000>;
5366 5351
5367 thermal-sensors = <&t 5352 thermal-sensors = <&tsens1 11>;
5368 5353
5369 cooling-maps { 5354 cooling-maps {
5370 map0 { 5355 map0 {
5371 trip 5356 trip = <&gpu_bottom_alert0>;
5372 cooli 5357 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5373 }; 5358 };
5374 }; 5359 };
5375 5360
5376 trips { 5361 trips {
5377 gpu_bottom_al 5362 gpu_bottom_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 5363 temperature = <90000>;
5385 hyste !! 5364 hysteresis = <2000>;
5386 type 5365 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 5366 };
5394 }; 5367 };
5395 }; 5368 };
5396 }; 5369 };
5397 }; 5370 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.