1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> 8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> 10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 17 #include <dt-bindings/clock/qcom,videocc-sm8150.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3 18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 19 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 20 #include <dt-bindings/thermal/thermal.h>
22 21
23 / { 22 / {
24 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
25 24
26 #address-cells = <2>; 25 #address-cells = <2>;
27 #size-cells = <2>; 26 #size-cells = <2>;
28 27
29 chosen { }; 28 chosen { };
30 29
31 clocks { 30 clocks {
32 xo_board: xo-board { 31 xo_board: xo-board {
33 compatible = "fixed-cl 32 compatible = "fixed-clock";
34 #clock-cells = <0>; 33 #clock-cells = <0>;
35 clock-frequency = <384 34 clock-frequency = <38400000>;
36 clock-output-names = " 35 clock-output-names = "xo_board";
37 }; 36 };
38 37
39 sleep_clk: sleep-clk { 38 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 39 compatible = "fixed-clock";
41 #clock-cells = <0>; 40 #clock-cells = <0>;
42 clock-frequency = <327 41 clock-frequency = <32764>;
43 clock-output-names = " 42 clock-output-names = "sleep_clk";
44 }; 43 };
45 }; 44 };
46 45
47 cpus { 46 cpus {
48 #address-cells = <2>; 47 #address-cells = <2>;
49 #size-cells = <0>; 48 #size-cells = <0>;
50 49
51 CPU0: cpu@0 { 50 CPU0: cpu@0 {
52 device_type = "cpu"; 51 device_type = "cpu";
53 compatible = "qcom,kry 52 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 53 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 54 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci" 55 enable-method = "psci";
57 capacity-dmips-mhz = < 56 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 57 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 58 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 59 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 60 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ 61 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
63 <&osm_ 62 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 63 power-domains = <&CPU_PD0>;
65 power-domain-names = " 64 power-domain-names = "psci";
66 #cooling-cells = <2>; 65 #cooling-cells = <2>;
67 L2_0: l2-cache { 66 L2_0: l2-cache {
68 compatible = " 67 compatible = "cache";
69 cache-level = 68 cache-level = <2>;
70 cache-unified; 69 cache-unified;
71 next-level-cac 70 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 71 L3_0: l3-cache {
73 compat 72 compatible = "cache";
74 cache- 73 cache-level = <3>;
75 cache- 74 cache-unified;
76 }; 75 };
77 }; 76 };
78 }; 77 };
79 78
80 CPU1: cpu@100 { 79 CPU1: cpu@100 {
81 device_type = "cpu"; 80 device_type = "cpu";
82 compatible = "qcom,kry 81 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 82 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 83 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci" 84 enable-method = "psci";
86 capacity-dmips-mhz = < 85 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 86 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 87 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 88 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 89 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 90 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
92 <&osm_ 91 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 92 power-domains = <&CPU_PD1>;
94 power-domain-names = " 93 power-domain-names = "psci";
95 #cooling-cells = <2>; 94 #cooling-cells = <2>;
96 L2_100: l2-cache { 95 L2_100: l2-cache {
97 compatible = " 96 compatible = "cache";
98 cache-level = 97 cache-level = <2>;
99 cache-unified; 98 cache-unified;
100 next-level-cac 99 next-level-cache = <&L3_0>;
101 }; 100 };
102 }; 101 };
103 102
104 CPU2: cpu@200 { 103 CPU2: cpu@200 {
105 device_type = "cpu"; 104 device_type = "cpu";
106 compatible = "qcom,kry 105 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 106 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw 107 clocks = <&cpufreq_hw 0>;
109 enable-method = "psci" 108 enable-method = "psci";
110 capacity-dmips-mhz = < 109 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 110 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 111 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 112 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 113 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ 114 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 <&osm_ 115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 116 power-domains = <&CPU_PD2>;
118 power-domain-names = " 117 power-domain-names = "psci";
119 #cooling-cells = <2>; 118 #cooling-cells = <2>;
120 L2_200: l2-cache { 119 L2_200: l2-cache {
121 compatible = " 120 compatible = "cache";
122 cache-level = 121 cache-level = <2>;
123 cache-unified; 122 cache-unified;
124 next-level-cac 123 next-level-cache = <&L3_0>;
125 }; 124 };
126 }; 125 };
127 126
128 CPU3: cpu@300 { 127 CPU3: cpu@300 {
129 device_type = "cpu"; 128 device_type = "cpu";
130 compatible = "qcom,kry 129 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 130 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 131 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci" 132 enable-method = "psci";
134 capacity-dmips-mhz = < 133 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 134 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 135 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 136 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 137 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ 138 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
140 <&osm_ 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 140 power-domains = <&CPU_PD3>;
142 power-domain-names = " 141 power-domain-names = "psci";
143 #cooling-cells = <2>; 142 #cooling-cells = <2>;
144 L2_300: l2-cache { 143 L2_300: l2-cache {
145 compatible = " 144 compatible = "cache";
146 cache-level = 145 cache-level = <2>;
147 cache-unified; 146 cache-unified;
148 next-level-cac 147 next-level-cache = <&L3_0>;
149 }; 148 };
150 }; 149 };
151 150
152 CPU4: cpu@400 { 151 CPU4: cpu@400 {
153 device_type = "cpu"; 152 device_type = "cpu";
154 compatible = "qcom,kry 153 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 154 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw 155 clocks = <&cpufreq_hw 1>;
157 enable-method = "psci" 156 enable-method = "psci";
158 capacity-dmips-mhz = < 157 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 158 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 159 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 160 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 161 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ 162 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
164 <&osm_ 163 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 164 power-domains = <&CPU_PD4>;
166 power-domain-names = " 165 power-domain-names = "psci";
167 #cooling-cells = <2>; 166 #cooling-cells = <2>;
168 L2_400: l2-cache { 167 L2_400: l2-cache {
169 compatible = " 168 compatible = "cache";
170 cache-level = 169 cache-level = <2>;
171 cache-unified; 170 cache-unified;
172 next-level-cac 171 next-level-cache = <&L3_0>;
173 }; 172 };
174 }; 173 };
175 174
176 CPU5: cpu@500 { 175 CPU5: cpu@500 {
177 device_type = "cpu"; 176 device_type = "cpu";
178 compatible = "qcom,kry 177 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 178 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw 179 clocks = <&cpufreq_hw 1>;
181 enable-method = "psci" 180 enable-method = "psci";
182 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 182 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 183 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 185 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ 186 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
188 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 188 power-domains = <&CPU_PD5>;
190 power-domain-names = " 189 power-domain-names = "psci";
191 #cooling-cells = <2>; 190 #cooling-cells = <2>;
192 L2_500: l2-cache { 191 L2_500: l2-cache {
193 compatible = " 192 compatible = "cache";
194 cache-level = 193 cache-level = <2>;
195 cache-unified; 194 cache-unified;
196 next-level-cac 195 next-level-cache = <&L3_0>;
197 }; 196 };
198 }; 197 };
199 198
200 CPU6: cpu@600 { 199 CPU6: cpu@600 {
201 device_type = "cpu"; 200 device_type = "cpu";
202 compatible = "qcom,kry 201 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 202 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw 203 clocks = <&cpufreq_hw 1>;
205 enable-method = "psci" 204 enable-method = "psci";
206 capacity-dmips-mhz = < 205 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 206 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 207 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 208 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 209 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ 210 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
212 <&osm_ 211 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 212 power-domains = <&CPU_PD6>;
214 power-domain-names = " 213 power-domain-names = "psci";
215 #cooling-cells = <2>; 214 #cooling-cells = <2>;
216 L2_600: l2-cache { 215 L2_600: l2-cache {
217 compatible = " 216 compatible = "cache";
218 cache-level = 217 cache-level = <2>;
219 cache-unified; 218 cache-unified;
220 next-level-cac 219 next-level-cache = <&L3_0>;
221 }; 220 };
222 }; 221 };
223 222
224 CPU7: cpu@700 { 223 CPU7: cpu@700 {
225 device_type = "cpu"; 224 device_type = "cpu";
226 compatible = "qcom,kry 225 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 226 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw 227 clocks = <&cpufreq_hw 2>;
229 enable-method = "psci" 228 enable-method = "psci";
230 capacity-dmips-mhz = < 229 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 230 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 231 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 232 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 233 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ 234 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
236 <&osm_ 235 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 236 power-domains = <&CPU_PD7>;
238 power-domain-names = " 237 power-domain-names = "psci";
239 #cooling-cells = <2>; 238 #cooling-cells = <2>;
240 L2_700: l2-cache { 239 L2_700: l2-cache {
241 compatible = " 240 compatible = "cache";
242 cache-level = 241 cache-level = <2>;
243 cache-unified; 242 cache-unified;
244 next-level-cac 243 next-level-cache = <&L3_0>;
245 }; 244 };
246 }; 245 };
247 246
248 cpu-map { 247 cpu-map {
249 cluster0 { 248 cluster0 {
250 core0 { 249 core0 {
251 cpu = 250 cpu = <&CPU0>;
252 }; 251 };
253 252
254 core1 { 253 core1 {
255 cpu = 254 cpu = <&CPU1>;
256 }; 255 };
257 256
258 core2 { 257 core2 {
259 cpu = 258 cpu = <&CPU2>;
260 }; 259 };
261 260
262 core3 { 261 core3 {
263 cpu = 262 cpu = <&CPU3>;
264 }; 263 };
265 264
266 core4 { 265 core4 {
267 cpu = 266 cpu = <&CPU4>;
268 }; 267 };
269 268
270 core5 { 269 core5 {
271 cpu = 270 cpu = <&CPU5>;
272 }; 271 };
273 272
274 core6 { 273 core6 {
275 cpu = 274 cpu = <&CPU6>;
276 }; 275 };
277 276
278 core7 { 277 core7 {
279 cpu = 278 cpu = <&CPU7>;
280 }; 279 };
281 }; 280 };
282 }; 281 };
283 282
284 idle-states { 283 idle-states {
285 entry-method = "psci"; 284 entry-method = "psci";
286 285
287 LITTLE_CPU_SLEEP_0: cp 286 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 287 compatible = "arm,idle-state";
289 idle-state-nam 288 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 289 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 290 entry-latency-us = <355>;
292 exit-latency-u 291 exit-latency-us = <909>;
293 min-residency- 292 min-residency-us = <3934>;
294 local-timer-st 293 local-timer-stop;
295 }; 294 };
296 295
297 BIG_CPU_SLEEP_0: cpu-s 296 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 297 compatible = "arm,idle-state";
299 idle-state-nam 298 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 299 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 300 entry-latency-us = <241>;
302 exit-latency-u 301 exit-latency-us = <1461>;
303 min-residency- 302 min-residency-us = <4488>;
304 local-timer-st 303 local-timer-stop;
305 }; 304 };
306 }; 305 };
307 306
308 domain-idle-states { 307 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 308 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 309 compatible = "domain-idle-state";
311 arm,psci-suspe 310 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 311 entry-latency-us = <3263>;
313 exit-latency-u 312 exit-latency-us = <6562>;
314 min-residency- 313 min-residency-us = <9987>;
315 }; 314 };
316 }; 315 };
317 }; 316 };
318 317
319 cpu0_opp_table: opp-table-cpu0 { 318 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points 319 compatible = "operating-points-v2";
321 opp-shared; 320 opp-shared;
322 321
323 cpu0_opp1: opp-300000000 { 322 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 323 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 324 opp-peak-kBps = <800000 9600000>;
326 }; 325 };
327 326
328 cpu0_opp2: opp-403200000 { 327 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 328 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 329 opp-peak-kBps = <800000 9600000>;
331 }; 330 };
332 331
333 cpu0_opp3: opp-499200000 { 332 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 333 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 334 opp-peak-kBps = <800000 12902400>;
336 }; 335 };
337 336
338 cpu0_opp4: opp-576000000 { 337 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 338 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 339 opp-peak-kBps = <800000 12902400>;
341 }; 340 };
342 341
343 cpu0_opp5: opp-672000000 { 342 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 343 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 344 opp-peak-kBps = <800000 15974400>;
346 }; 345 };
347 346
348 cpu0_opp6: opp-768000000 { 347 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 348 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 349 opp-peak-kBps = <1804000 19660800>;
351 }; 350 };
352 351
353 cpu0_opp7: opp-844800000 { 352 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 353 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 354 opp-peak-kBps = <1804000 19660800>;
356 }; 355 };
357 356
358 cpu0_opp8: opp-940800000 { 357 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 358 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 359 opp-peak-kBps = <1804000 22732800>;
361 }; 360 };
362 361
363 cpu0_opp9: opp-1036800000 { 362 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 363 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 364 opp-peak-kBps = <1804000 22732800>;
366 }; 365 };
367 366
368 cpu0_opp10: opp-1113600000 { 367 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 368 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 369 opp-peak-kBps = <2188000 25804800>;
371 }; 370 };
372 371
373 cpu0_opp11: opp-1209600000 { 372 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 373 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 374 opp-peak-kBps = <2188000 31948800>;
376 }; 375 };
377 376
378 cpu0_opp12: opp-1305600000 { 377 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 378 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 379 opp-peak-kBps = <3072000 31948800>;
381 }; 380 };
382 381
383 cpu0_opp13: opp-1382400000 { 382 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 383 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 384 opp-peak-kBps = <3072000 31948800>;
386 }; 385 };
387 386
388 cpu0_opp14: opp-1478400000 { 387 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 388 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 389 opp-peak-kBps = <3072000 31948800>;
391 }; 390 };
392 391
393 cpu0_opp15: opp-1555200000 { 392 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 393 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 394 opp-peak-kBps = <3072000 40550400>;
396 }; 395 };
397 396
398 cpu0_opp16: opp-1632000000 { 397 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 398 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 399 opp-peak-kBps = <3072000 40550400>;
401 }; 400 };
402 401
403 cpu0_opp17: opp-1708800000 { 402 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 403 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 404 opp-peak-kBps = <3072000 43008000>;
406 }; 405 };
407 406
408 cpu0_opp18: opp-1785600000 { 407 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 408 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 409 opp-peak-kBps = <3072000 43008000>;
411 }; 410 };
412 }; 411 };
413 412
414 cpu4_opp_table: opp-table-cpu4 { 413 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points 414 compatible = "operating-points-v2";
416 opp-shared; 415 opp-shared;
417 416
418 cpu4_opp1: opp-710400000 { 417 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 418 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 419 opp-peak-kBps = <1804000 15974400>;
421 }; 420 };
422 421
423 cpu4_opp2: opp-825600000 { 422 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 423 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 424 opp-peak-kBps = <2188000 19660800>;
426 }; 425 };
427 426
428 cpu4_opp3: opp-940800000 { 427 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 428 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 429 opp-peak-kBps = <2188000 22732800>;
431 }; 430 };
432 431
433 cpu4_opp4: opp-1056000000 { 432 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 433 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 434 opp-peak-kBps = <3072000 25804800>;
436 }; 435 };
437 436
438 cpu4_opp5: opp-1171200000 { 437 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 438 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 439 opp-peak-kBps = <3072000 31948800>;
441 }; 440 };
442 441
443 cpu4_opp6: opp-1286400000 { 442 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 443 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 444 opp-peak-kBps = <4068000 31948800>;
446 }; 445 };
447 446
448 cpu4_opp7: opp-1401600000 { 447 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 448 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 449 opp-peak-kBps = <4068000 31948800>;
451 }; 450 };
452 451
453 cpu4_opp8: opp-1497600000 { 452 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 453 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 454 opp-peak-kBps = <4068000 40550400>;
456 }; 455 };
457 456
458 cpu4_opp9: opp-1612800000 { 457 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 458 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 459 opp-peak-kBps = <4068000 40550400>;
461 }; 460 };
462 461
463 cpu4_opp10: opp-1708800000 { 462 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 463 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 464 opp-peak-kBps = <4068000 43008000>;
466 }; 465 };
467 466
468 cpu4_opp11: opp-1804800000 { 467 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 468 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 469 opp-peak-kBps = <6220000 43008000>;
471 }; 470 };
472 471
473 cpu4_opp12: opp-1920000000 { 472 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 473 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 474 opp-peak-kBps = <6220000 49152000>;
476 }; 475 };
477 476
478 cpu4_opp13: opp-2016000000 { 477 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 478 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 479 opp-peak-kBps = <7216000 49152000>;
481 }; 480 };
482 481
483 cpu4_opp14: opp-2131200000 { 482 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 483 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 484 opp-peak-kBps = <8368000 49152000>;
486 }; 485 };
487 486
488 cpu4_opp15: opp-2227200000 { 487 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 488 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 489 opp-peak-kBps = <8368000 51609600>;
491 }; 490 };
492 491
493 cpu4_opp16: opp-2323200000 { 492 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 493 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 494 opp-peak-kBps = <8368000 51609600>;
496 }; 495 };
497 496
498 cpu4_opp17: opp-2419200000 { 497 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 498 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 499 opp-peak-kBps = <8368000 51609600>;
501 }; 500 };
502 }; 501 };
503 502
504 cpu7_opp_table: opp-table-cpu7 { 503 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points 504 compatible = "operating-points-v2";
506 opp-shared; 505 opp-shared;
507 506
508 cpu7_opp1: opp-825600000 { 507 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 508 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 509 opp-peak-kBps = <2188000 19660800>;
511 }; 510 };
512 511
513 cpu7_opp2: opp-940800000 { 512 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 513 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 514 opp-peak-kBps = <2188000 22732800>;
516 }; 515 };
517 516
518 cpu7_opp3: opp-1056000000 { 517 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 518 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 519 opp-peak-kBps = <3072000 25804800>;
521 }; 520 };
522 521
523 cpu7_opp4: opp-1171200000 { 522 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 523 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 524 opp-peak-kBps = <3072000 31948800>;
526 }; 525 };
527 526
528 cpu7_opp5: opp-1286400000 { 527 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 528 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 529 opp-peak-kBps = <4068000 31948800>;
531 }; 530 };
532 531
533 cpu7_opp6: opp-1401600000 { 532 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 533 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 534 opp-peak-kBps = <4068000 31948800>;
536 }; 535 };
537 536
538 cpu7_opp7: opp-1497600000 { 537 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 538 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 539 opp-peak-kBps = <4068000 40550400>;
541 }; 540 };
542 541
543 cpu7_opp8: opp-1612800000 { 542 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 543 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 544 opp-peak-kBps = <4068000 40550400>;
546 }; 545 };
547 546
548 cpu7_opp9: opp-1708800000 { 547 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 548 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 549 opp-peak-kBps = <4068000 43008000>;
551 }; 550 };
552 551
553 cpu7_opp10: opp-1804800000 { 552 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 553 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 554 opp-peak-kBps = <6220000 43008000>;
556 }; 555 };
557 556
558 cpu7_opp11: opp-1920000000 { 557 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 558 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 559 opp-peak-kBps = <6220000 49152000>;
561 }; 560 };
562 561
563 cpu7_opp12: opp-2016000000 { 562 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 563 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 564 opp-peak-kBps = <7216000 49152000>;
566 }; 565 };
567 566
568 cpu7_opp13: opp-2131200000 { 567 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 568 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 569 opp-peak-kBps = <8368000 49152000>;
571 }; 570 };
572 571
573 cpu7_opp14: opp-2227200000 { 572 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 573 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 574 opp-peak-kBps = <8368000 51609600>;
576 }; 575 };
577 576
578 cpu7_opp15: opp-2323200000 { 577 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 578 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 579 opp-peak-kBps = <8368000 51609600>;
581 }; 580 };
582 581
583 cpu7_opp16: opp-2419200000 { 582 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 583 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 584 opp-peak-kBps = <8368000 51609600>;
586 }; 585 };
587 586
588 cpu7_opp17: opp-2534400000 { 587 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 588 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 589 opp-peak-kBps = <8368000 51609600>;
591 }; 590 };
592 591
593 cpu7_opp18: opp-2649600000 { 592 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 593 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 594 opp-peak-kBps = <8368000 51609600>;
596 }; 595 };
597 596
598 cpu7_opp19: opp-2745600000 { 597 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 598 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 599 opp-peak-kBps = <8368000 51609600>;
601 }; 600 };
602 601
603 cpu7_opp20: opp-2841600000 { 602 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 603 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 604 opp-peak-kBps = <8368000 51609600>;
606 }; 605 };
607 }; 606 };
608 607
609 firmware { 608 firmware {
610 scm: scm { 609 scm: scm {
611 compatible = "qcom,scm 610 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 611 #reset-cells = <1>;
613 }; 612 };
614 }; 613 };
615 614
616 memory@80000000 { 615 memory@80000000 {
617 device_type = "memory"; 616 device_type = "memory";
618 /* We expect the bootloader to 617 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 618 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 619 };
621 620
622 pmu { 621 pmu {
623 compatible = "arm,armv8-pmuv3" 622 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 623 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 624 };
626 625
627 psci { 626 psci {
628 compatible = "arm,psci-1.0"; 627 compatible = "arm,psci-1.0";
629 method = "smc"; 628 method = "smc";
630 629
631 CPU_PD0: power-domain-cpu0 { 630 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells = 631 #power-domain-cells = <0>;
633 power-domains = <&CLUS 632 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 633 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 634 };
636 635
637 CPU_PD1: power-domain-cpu1 { 636 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells = 637 #power-domain-cells = <0>;
639 power-domains = <&CLUS 638 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 639 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 640 };
642 641
643 CPU_PD2: power-domain-cpu2 { 642 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells = 643 #power-domain-cells = <0>;
645 power-domains = <&CLUS 644 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 645 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 646 };
648 647
649 CPU_PD3: power-domain-cpu3 { 648 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells = 649 #power-domain-cells = <0>;
651 power-domains = <&CLUS 650 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 651 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 652 };
654 653
655 CPU_PD4: power-domain-cpu4 { 654 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells = 655 #power-domain-cells = <0>;
657 power-domains = <&CLUS 656 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 657 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 658 };
660 659
661 CPU_PD5: power-domain-cpu5 { 660 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells = 661 #power-domain-cells = <0>;
663 power-domains = <&CLUS 662 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 663 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 664 };
666 665
667 CPU_PD6: power-domain-cpu6 { 666 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells = 667 #power-domain-cells = <0>;
669 power-domains = <&CLUS 668 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 669 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 670 };
672 671
673 CPU_PD7: power-domain-cpu7 { 672 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells = 673 #power-domain-cells = <0>;
675 power-domains = <&CLUS 674 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 675 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 676 };
678 677
679 CLUSTER_PD: power-domain-cpu-c 678 CLUSTER_PD: power-domain-cpu-cluster0 {
680 #power-domain-cells = 679 #power-domain-cells = <0>;
681 domain-idle-states = < 680 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 681 };
683 }; 682 };
684 683
685 reserved-memory { 684 reserved-memory {
686 #address-cells = <2>; 685 #address-cells = <2>;
687 #size-cells = <2>; 686 #size-cells = <2>;
688 ranges; 687 ranges;
689 688
690 hyp_mem: memory@85700000 { 689 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 690 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 691 no-map;
693 }; 692 };
694 693
695 xbl_mem: memory@85d00000 { 694 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 695 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 696 no-map;
698 }; 697 };
699 698
700 aop_mem: memory@85f00000 { 699 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 700 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 701 no-map;
703 }; 702 };
704 703
705 aop_cmd_db: memory@85f20000 { 704 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 705 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 706 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 707 no-map;
709 }; 708 };
710 709
711 smem_mem: memory@86000000 { 710 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 711 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 712 no-map;
714 }; 713 };
715 714
716 tz_mem: memory@86200000 { 715 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 716 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 717 no-map;
719 }; 718 };
720 719
721 rmtfs_mem: memory@89b00000 { 720 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 721 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 722 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 723 no-map;
725 724
726 qcom,client-id = <1>; 725 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ 726 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
728 }; 727 };
729 728
730 camera_mem: memory@8b700000 { 729 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 730 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 731 no-map;
733 }; 732 };
734 733
735 wlan_mem: memory@8bc00000 { 734 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 735 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 736 no-map;
738 }; 737 };
739 738
740 npu_mem: memory@8bd80000 { 739 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 740 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 741 no-map;
743 }; 742 };
744 743
745 adsp_mem: memory@8be00000 { 744 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 745 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 746 no-map;
748 }; 747 };
749 748
750 mpss_mem: memory@8d800000 { 749 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 750 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 751 no-map;
753 }; 752 };
754 753
755 venus_mem: memory@96e00000 { 754 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 755 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 756 no-map;
758 }; 757 };
759 758
760 slpi_mem: memory@97300000 { 759 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 760 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 761 no-map;
763 }; 762 };
764 763
765 ipa_fw_mem: memory@98700000 { 764 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 765 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 766 no-map;
768 }; 767 };
769 768
770 ipa_gsi_mem: memory@98710000 { 769 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 770 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 771 no-map;
773 }; 772 };
774 773
775 gpu_mem: memory@98715000 { 774 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 775 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 776 no-map;
778 }; 777 };
779 778
780 spss_mem: memory@98800000 { 779 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 780 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 781 no-map;
783 }; 782 };
784 783
785 cdsp_mem: memory@98900000 { 784 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 785 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 786 no-map;
788 }; 787 };
789 788
790 qseecom_mem: memory@9e400000 { 789 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 790 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 791 no-map;
793 }; 792 };
794 }; 793 };
795 794
796 smem { 795 smem {
797 compatible = "qcom,smem"; 796 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 797 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 798 hwlocks = <&tcsr_mutex 3>;
800 }; 799 };
801 800
802 smp2p-cdsp { 801 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 802 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 803 qcom,smem = <94>, <432>;
805 804
806 interrupts = <GIC_SPI 576 IRQ_ 805 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 806
808 mboxes = <&apss_shared 6>; 807 mboxes = <&apss_shared 6>;
809 808
810 qcom,local-pid = <0>; 809 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 810 qcom,remote-pid = <5>;
812 811
813 cdsp_smp2p_out: master-kernel 812 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 813 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 814 #qcom,smem-state-cells = <1>;
816 }; 815 };
817 816
818 cdsp_smp2p_in: slave-kernel { 817 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 818 qcom,entry-name = "slave-kernel";
820 819
821 interrupt-controller; 820 interrupt-controller;
822 #interrupt-cells = <2> 821 #interrupt-cells = <2>;
823 }; 822 };
824 }; 823 };
825 824
826 smp2p-lpass { 825 smp2p-lpass {
827 compatible = "qcom,smp2p"; 826 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 827 qcom,smem = <443>, <429>;
829 828
830 interrupts = <GIC_SPI 158 IRQ_ 829 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 830
832 mboxes = <&apss_shared 10>; 831 mboxes = <&apss_shared 10>;
833 832
834 qcom,local-pid = <0>; 833 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 834 qcom,remote-pid = <2>;
836 835
837 adsp_smp2p_out: master-kernel 836 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 837 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 838 #qcom,smem-state-cells = <1>;
840 }; 839 };
841 840
842 adsp_smp2p_in: slave-kernel { 841 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 842 qcom,entry-name = "slave-kernel";
844 843
845 interrupt-controller; 844 interrupt-controller;
846 #interrupt-cells = <2> 845 #interrupt-cells = <2>;
847 }; 846 };
848 }; 847 };
849 848
850 smp2p-mpss { 849 smp2p-mpss {
851 compatible = "qcom,smp2p"; 850 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 851 qcom,smem = <435>, <428>;
853 852
854 interrupts = <GIC_SPI 451 IRQ_ 853 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 854
856 mboxes = <&apss_shared 14>; 855 mboxes = <&apss_shared 14>;
857 856
858 qcom,local-pid = <0>; 857 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 858 qcom,remote-pid = <1>;
860 859
861 modem_smp2p_out: master-kernel 860 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 861 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 862 #qcom,smem-state-cells = <1>;
864 }; 863 };
865 864
866 modem_smp2p_in: slave-kernel { 865 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 866 qcom,entry-name = "slave-kernel";
868 867
869 interrupt-controller; 868 interrupt-controller;
870 #interrupt-cells = <2> 869 #interrupt-cells = <2>;
871 }; 870 };
872 }; 871 };
873 872
874 smp2p-slpi { 873 smp2p-slpi {
875 compatible = "qcom,smp2p"; 874 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 875 qcom,smem = <481>, <430>;
877 876
878 interrupts = <GIC_SPI 172 IRQ_ 877 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 878
880 mboxes = <&apss_shared 26>; 879 mboxes = <&apss_shared 26>;
881 880
882 qcom,local-pid = <0>; 881 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 882 qcom,remote-pid = <3>;
884 883
885 slpi_smp2p_out: master-kernel 884 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 885 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 886 #qcom,smem-state-cells = <1>;
888 }; 887 };
889 888
890 slpi_smp2p_in: slave-kernel { 889 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 890 qcom,entry-name = "slave-kernel";
892 891
893 interrupt-controller; 892 interrupt-controller;
894 #interrupt-cells = <2> 893 #interrupt-cells = <2>;
895 }; 894 };
896 }; 895 };
897 896
898 soc: soc@0 { 897 soc: soc@0 {
899 #address-cells = <2>; 898 #address-cells = <2>;
900 #size-cells = <2>; 899 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 900 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 901 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 902 compatible = "simple-bus";
904 903
905 gcc: clock-controller@100000 { 904 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 905 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 906 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 907 #clock-cells = <1>;
909 #reset-cells = <1>; 908 #reset-cells = <1>;
910 #power-domain-cells = 909 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 910 clock-names = "bi_tcxo",
912 "sleep_c 911 "sleep_clk";
913 clocks = <&rpmhcc RPMH 912 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 913 <&sleep_clk>;
915 }; 914 };
916 915
917 gpi_dma0: dma-controller@80000 916 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 917 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 918 reg = <0 0x00800000 0 0x60000>;
920 interrupts = <GIC_SPI 919 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 920 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 921 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 922 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 923 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 924 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 925 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 926 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 927 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 928 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 929 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 930 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 931 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 932 dma-channels = <13>;
934 dma-channel-mask = <0x 933 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 934 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 935 #dma-cells = <3>;
937 status = "disabled"; 936 status = "disabled";
938 }; 937 };
939 938
940 ethernet: ethernet@20000 { 939 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 940 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 941 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 942 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 943 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 944 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 945 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 946 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 947 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 948 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 949 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 950 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 951 interrupt-names = "macirq", "eth_lpi";
953 952
954 power-domains = <&gcc 953 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 954 resets = <&gcc GCC_EMAC_BCR>;
956 955
957 iommus = <&apps_smmu 0 956 iommus = <&apps_smmu 0x3c0 0x0>;
958 957
959 snps,tso; 958 snps,tso;
960 rx-fifo-depth = <4096> 959 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 960 tx-fifo-depth = <4096>;
962 961
963 status = "disabled"; 962 status = "disabled";
964 }; 963 };
965 964
966 qfprom: efuse@784000 { 965 qfprom: efuse@784000 {
967 compatible = "qcom,sm8 966 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
968 reg = <0 0x00784000 0 967 reg = <0 0x00784000 0 0x8ff>;
969 #address-cells = <1>; 968 #address-cells = <1>;
970 #size-cells = <1>; 969 #size-cells = <1>;
971 970
972 gpu_speed_bin: gpu-spe 971 gpu_speed_bin: gpu-speed-bin@133 {
973 reg = <0x133 0 972 reg = <0x133 0x1>;
974 bits = <5 3>; 973 bits = <5 3>;
975 }; 974 };
976 }; 975 };
977 976
978 qupv3_id_0: geniqup@8c0000 { 977 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 978 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 979 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 980 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 981 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 982 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 983 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 984 #address-cells = <2>;
986 #size-cells = <2>; 985 #size-cells = <2>;
987 ranges; 986 ranges;
988 status = "disabled"; 987 status = "disabled";
989 988
990 i2c0: i2c@880000 { 989 i2c0: i2c@880000 {
991 compatible = " 990 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 991 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 992 clock-names = "se";
994 clocks = <&gcc 993 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 994 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 995 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 996 dma-names = "tx", "rx";
998 pinctrl-names 997 pinctrl-names = "default";
999 pinctrl-0 = <& 998 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 999 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 1000 #address-cells = <1>;
1002 #size-cells = 1001 #size-cells = <0>;
1003 status = "dis 1002 status = "disabled";
1004 }; 1003 };
1005 1004
1006 spi0: spi@880000 { 1005 spi0: spi@880000 {
1007 compatible = 1006 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 1007 reg = <0 0x00880000 0 0x4000>;
1009 reg-names = " 1008 reg-names = "se";
1010 clock-names = 1009 clock-names = "se";
1011 clocks = <&gc 1010 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 1012 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 1013 dma-names = "tx", "rx";
1015 pinctrl-names 1014 pinctrl-names = "default";
1016 pinctrl-0 = < 1015 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 1016 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 1017 spi-max-frequency = <50000000>;
1019 #address-cell 1018 #address-cells = <1>;
1020 #size-cells = 1019 #size-cells = <0>;
1021 status = "dis 1020 status = "disabled";
1022 }; 1021 };
1023 1022
1024 i2c1: i2c@884000 { 1023 i2c1: i2c@884000 {
1025 compatible = 1024 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 1025 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 1026 clock-names = "se";
1028 clocks = <&gc 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 1028 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 1029 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 1030 dma-names = "tx", "rx";
1032 pinctrl-names 1031 pinctrl-names = "default";
1033 pinctrl-0 = < 1032 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 1033 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 1034 #address-cells = <1>;
1036 #size-cells = 1035 #size-cells = <0>;
1037 status = "dis 1036 status = "disabled";
1038 }; 1037 };
1039 1038
1040 spi1: spi@884000 { 1039 spi1: spi@884000 {
1041 compatible = 1040 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1041 reg = <0 0x00884000 0 0x4000>;
1043 reg-names = " 1042 reg-names = "se";
1044 clock-names = 1043 clock-names = "se";
1045 clocks = <&gc 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1045 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1046 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1047 dma-names = "tx", "rx";
1049 pinctrl-names 1048 pinctrl-names = "default";
1050 pinctrl-0 = < 1049 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1050 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1051 spi-max-frequency = <50000000>;
1053 #address-cell 1052 #address-cells = <1>;
1054 #size-cells = 1053 #size-cells = <0>;
1055 status = "dis 1054 status = "disabled";
1056 }; 1055 };
1057 1056
1058 i2c2: i2c@888000 { 1057 i2c2: i2c@888000 {
1059 compatible = 1058 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1059 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1060 clock-names = "se";
1062 clocks = <&gc 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1062 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1063 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1064 dma-names = "tx", "rx";
1066 pinctrl-names 1065 pinctrl-names = "default";
1067 pinctrl-0 = < 1066 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1067 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1068 #address-cells = <1>;
1070 #size-cells = 1069 #size-cells = <0>;
1071 status = "dis 1070 status = "disabled";
1072 }; 1071 };
1073 1072
1074 spi2: spi@888000 { 1073 spi2: spi@888000 {
1075 compatible = 1074 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 1075 reg = <0 0x00888000 0 0x4000>;
1077 reg-names = " 1076 reg-names = "se";
1078 clock-names = 1077 clock-names = "se";
1079 clocks = <&gc 1078 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1079 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1080 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1081 dma-names = "tx", "rx";
1083 pinctrl-names 1082 pinctrl-names = "default";
1084 pinctrl-0 = < 1083 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1084 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1085 spi-max-frequency = <50000000>;
1087 #address-cell 1086 #address-cells = <1>;
1088 #size-cells = 1087 #size-cells = <0>;
1089 status = "dis 1088 status = "disabled";
1090 }; 1089 };
1091 1090
1092 i2c3: i2c@88c000 { 1091 i2c3: i2c@88c000 {
1093 compatible = 1092 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1093 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1094 clock-names = "se";
1096 clocks = <&gc 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1096 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1097 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1098 dma-names = "tx", "rx";
1100 pinctrl-names 1099 pinctrl-names = "default";
1101 pinctrl-0 = < 1100 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1101 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1102 #address-cells = <1>;
1104 #size-cells = 1103 #size-cells = <0>;
1105 status = "dis 1104 status = "disabled";
1106 }; 1105 };
1107 1106
1108 spi3: spi@88c000 { 1107 spi3: spi@88c000 {
1109 compatible = 1108 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 1109 reg = <0 0x0088c000 0 0x4000>;
1111 reg-names = " 1110 reg-names = "se";
1112 clock-names = 1111 clock-names = "se";
1113 clocks = <&gc 1112 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1113 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1114 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1115 dma-names = "tx", "rx";
1117 pinctrl-names 1116 pinctrl-names = "default";
1118 pinctrl-0 = < 1117 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1118 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1119 spi-max-frequency = <50000000>;
1121 #address-cell 1120 #address-cells = <1>;
1122 #size-cells = 1121 #size-cells = <0>;
1123 status = "dis 1122 status = "disabled";
1124 }; 1123 };
1125 1124
1126 i2c4: i2c@890000 { 1125 i2c4: i2c@890000 {
1127 compatible = 1126 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1127 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1128 clock-names = "se";
1130 clocks = <&gc 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1130 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1131 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1132 dma-names = "tx", "rx";
1134 pinctrl-names 1133 pinctrl-names = "default";
1135 pinctrl-0 = < 1134 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1135 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1136 #address-cells = <1>;
1138 #size-cells = 1137 #size-cells = <0>;
1139 status = "dis 1138 status = "disabled";
1140 }; 1139 };
1141 1140
1142 spi4: spi@890000 { 1141 spi4: spi@890000 {
1143 compatible = 1142 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 1143 reg = <0 0x00890000 0 0x4000>;
1145 reg-names = " 1144 reg-names = "se";
1146 clock-names = 1145 clock-names = "se";
1147 clocks = <&gc 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1147 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1148 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1149 dma-names = "tx", "rx";
1151 pinctrl-names 1150 pinctrl-names = "default";
1152 pinctrl-0 = < 1151 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1152 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1153 spi-max-frequency = <50000000>;
1155 #address-cell 1154 #address-cells = <1>;
1156 #size-cells = 1155 #size-cells = <0>;
1157 status = "dis 1156 status = "disabled";
1158 }; 1157 };
1159 1158
1160 i2c5: i2c@894000 { 1159 i2c5: i2c@894000 {
1161 compatible = 1160 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1161 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1162 clock-names = "se";
1164 clocks = <&gc 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1164 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1165 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1166 dma-names = "tx", "rx";
1168 pinctrl-names 1167 pinctrl-names = "default";
1169 pinctrl-0 = < 1168 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1169 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1170 #address-cells = <1>;
1172 #size-cells = 1171 #size-cells = <0>;
1173 status = "dis 1172 status = "disabled";
1174 }; 1173 };
1175 1174
1176 spi5: spi@894000 { 1175 spi5: spi@894000 {
1177 compatible = 1176 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 1177 reg = <0 0x00894000 0 0x4000>;
1179 reg-names = " 1178 reg-names = "se";
1180 clock-names = 1179 clock-names = "se";
1181 clocks = <&gc 1180 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1181 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1182 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1183 dma-names = "tx", "rx";
1185 pinctrl-names 1184 pinctrl-names = "default";
1186 pinctrl-0 = < 1185 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1186 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1187 spi-max-frequency = <50000000>;
1189 #address-cell 1188 #address-cells = <1>;
1190 #size-cells = 1189 #size-cells = <0>;
1191 status = "dis 1190 status = "disabled";
1192 }; 1191 };
1193 1192
1194 i2c6: i2c@898000 { 1193 i2c6: i2c@898000 {
1195 compatible = 1194 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1195 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1196 clock-names = "se";
1198 clocks = <&gc 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1198 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1199 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1200 dma-names = "tx", "rx";
1202 pinctrl-names 1201 pinctrl-names = "default";
1203 pinctrl-0 = < 1202 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1203 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1204 #address-cells = <1>;
1206 #size-cells = 1205 #size-cells = <0>;
1207 status = "dis 1206 status = "disabled";
1208 }; 1207 };
1209 1208
1210 spi6: spi@898000 { 1209 spi6: spi@898000 {
1211 compatible = 1210 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1211 reg = <0 0x00898000 0 0x4000>;
1213 reg-names = " 1212 reg-names = "se";
1214 clock-names = 1213 clock-names = "se";
1215 clocks = <&gc 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1215 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1216 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1217 dma-names = "tx", "rx";
1219 pinctrl-names 1218 pinctrl-names = "default";
1220 pinctrl-0 = < 1219 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1220 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1221 spi-max-frequency = <50000000>;
1223 #address-cell 1222 #address-cells = <1>;
1224 #size-cells = 1223 #size-cells = <0>;
1225 status = "dis 1224 status = "disabled";
1226 }; 1225 };
1227 1226
1228 i2c7: i2c@89c000 { 1227 i2c7: i2c@89c000 {
1229 compatible = 1228 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1229 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1230 clock-names = "se";
1232 clocks = <&gc 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1232 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1233 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1234 dma-names = "tx", "rx";
1236 pinctrl-names 1235 pinctrl-names = "default";
1237 pinctrl-0 = < 1236 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = 1237 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1238 #address-cells = <1>;
1240 #size-cells = 1239 #size-cells = <0>;
1241 status = "dis 1240 status = "disabled";
1242 }; 1241 };
1243 1242
1244 spi7: spi@89c000 { 1243 spi7: spi@89c000 {
1245 compatible = 1244 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 1245 reg = <0 0x0089c000 0 0x4000>;
1247 reg-names = " 1246 reg-names = "se";
1248 clock-names = 1247 clock-names = "se";
1249 clocks = <&gc 1248 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1249 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1250 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1251 dma-names = "tx", "rx";
1253 pinctrl-names 1252 pinctrl-names = "default";
1254 pinctrl-0 = < 1253 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1254 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1255 spi-max-frequency = <50000000>;
1257 #address-cell 1256 #address-cells = <1>;
1258 #size-cells = 1257 #size-cells = <0>;
1259 status = "dis 1258 status = "disabled";
1260 }; 1259 };
1261 }; 1260 };
1262 1261
1263 gpi_dma1: dma-controller@a000 1262 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm 1263 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 1264 reg = <0 0x00a00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1265 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1266 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1267 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1268 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1269 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1270 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1271 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1272 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1273 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1274 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1275 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1276 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1277 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1278 dma-channels = <13>;
1280 dma-channel-mask = <0 1279 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1280 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1281 #dma-cells = <3>;
1283 status = "disabled"; 1282 status = "disabled";
1284 }; 1283 };
1285 1284
1286 qupv3_id_1: geniqup@ac0000 { 1285 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1286 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1287 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1288 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1289 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1290 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1291 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1292 #address-cells = <2>;
1294 #size-cells = <2>; 1293 #size-cells = <2>;
1295 ranges; 1294 ranges;
1296 status = "disabled"; 1295 status = "disabled";
1297 1296
1298 i2c8: i2c@a80000 { 1297 i2c8: i2c@a80000 {
1299 compatible = 1298 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1299 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1300 clock-names = "se";
1302 clocks = <&gc 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1302 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1303 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1304 dma-names = "tx", "rx";
1306 pinctrl-names 1305 pinctrl-names = "default";
1307 pinctrl-0 = < 1306 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1307 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1308 #address-cells = <1>;
1310 #size-cells = 1309 #size-cells = <0>;
1311 status = "dis 1310 status = "disabled";
1312 }; 1311 };
1313 1312
1314 spi8: spi@a80000 { 1313 spi8: spi@a80000 {
1315 compatible = 1314 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 1315 reg = <0 0x00a80000 0 0x4000>;
1317 reg-names = " 1316 reg-names = "se";
1318 clock-names = 1317 clock-names = "se";
1319 clocks = <&gc 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1319 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1320 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1321 dma-names = "tx", "rx";
1323 pinctrl-names 1322 pinctrl-names = "default";
1324 pinctrl-0 = < 1323 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1324 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1325 spi-max-frequency = <50000000>;
1327 #address-cell 1326 #address-cells = <1>;
1328 #size-cells = 1327 #size-cells = <0>;
1329 status = "dis 1328 status = "disabled";
1330 }; 1329 };
1331 1330
1332 i2c9: i2c@a84000 { 1331 i2c9: i2c@a84000 {
1333 compatible = 1332 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1333 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1334 clock-names = "se";
1336 clocks = <&gc 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1336 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1337 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1338 dma-names = "tx", "rx";
1340 pinctrl-names 1339 pinctrl-names = "default";
1341 pinctrl-0 = < 1340 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1341 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1342 #address-cells = <1>;
1344 #size-cells = 1343 #size-cells = <0>;
1345 status = "dis 1344 status = "disabled";
1346 }; 1345 };
1347 1346
1348 spi9: spi@a84000 { 1347 spi9: spi@a84000 {
1349 compatible = 1348 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 1349 reg = <0 0x00a84000 0 0x4000>;
1351 reg-names = " 1350 reg-names = "se";
1352 clock-names = 1351 clock-names = "se";
1353 clocks = <&gc 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1353 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1354 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1355 dma-names = "tx", "rx";
1357 pinctrl-names 1356 pinctrl-names = "default";
1358 pinctrl-0 = < 1357 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1358 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1359 spi-max-frequency = <50000000>;
1361 #address-cell 1360 #address-cells = <1>;
1362 #size-cells = 1361 #size-cells = <0>;
1363 status = "dis 1362 status = "disabled";
1364 }; 1363 };
1365 1364
1366 uart9: serial@a84000 1365 uart9: serial@a84000 {
1367 compatible = 1366 compatible = "qcom,geni-uart";
1368 reg = <0x0 0x 1367 reg = <0x0 0x00a84000 0x0 0x4000>;
1369 clocks = <&gc 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1370 clock-names = 1369 clock-names = "se";
1371 pinctrl-0 = < 1370 pinctrl-0 = <&qup_uart9_default>;
1372 pinctrl-names 1371 pinctrl-names = "default";
1373 interrupts = 1372 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1374 status = "dis 1373 status = "disabled";
1375 }; 1374 };
1376 1375
1377 i2c10: i2c@a88000 { 1376 i2c10: i2c@a88000 {
1378 compatible = 1377 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1378 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1379 clock-names = "se";
1381 clocks = <&gc 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1381 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1382 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1383 dma-names = "tx", "rx";
1385 pinctrl-names 1384 pinctrl-names = "default";
1386 pinctrl-0 = < 1385 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1386 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1387 #address-cells = <1>;
1389 #size-cells = 1388 #size-cells = <0>;
1390 status = "dis 1389 status = "disabled";
1391 }; 1390 };
1392 1391
1393 spi10: spi@a88000 { 1392 spi10: spi@a88000 {
1394 compatible = 1393 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 1394 reg = <0 0x00a88000 0 0x4000>;
1396 reg-names = " 1395 reg-names = "se";
1397 clock-names = 1396 clock-names = "se";
1398 clocks = <&gc 1397 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1398 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1399 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1400 dma-names = "tx", "rx";
1402 pinctrl-names 1401 pinctrl-names = "default";
1403 pinctrl-0 = < 1402 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1403 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1404 spi-max-frequency = <50000000>;
1406 #address-cell 1405 #address-cells = <1>;
1407 #size-cells = 1406 #size-cells = <0>;
1408 status = "dis 1407 status = "disabled";
1409 }; 1408 };
1410 1409
1411 i2c11: i2c@a8c000 { 1410 i2c11: i2c@a8c000 {
1412 compatible = 1411 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1412 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1413 clock-names = "se";
1415 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1415 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1416 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1417 dma-names = "tx", "rx";
1419 pinctrl-names 1418 pinctrl-names = "default";
1420 pinctrl-0 = < 1419 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1420 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1421 #address-cells = <1>;
1423 #size-cells = 1422 #size-cells = <0>;
1424 status = "dis 1423 status = "disabled";
1425 }; 1424 };
1426 1425
1427 spi11: spi@a8c000 { 1426 spi11: spi@a8c000 {
1428 compatible = 1427 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 1428 reg = <0 0x00a8c000 0 0x4000>;
1430 reg-names = " 1429 reg-names = "se";
1431 clock-names = 1430 clock-names = "se";
1432 clocks = <&gc 1431 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1432 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1433 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1434 dma-names = "tx", "rx";
1436 pinctrl-names 1435 pinctrl-names = "default";
1437 pinctrl-0 = < 1436 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1437 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1438 spi-max-frequency = <50000000>;
1440 #address-cell 1439 #address-cells = <1>;
1441 #size-cells = 1440 #size-cells = <0>;
1442 status = "dis 1441 status = "disabled";
1443 }; 1442 };
1444 1443
1445 uart2: serial@a90000 1444 uart2: serial@a90000 {
1446 compatible = 1445 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1446 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1447 clock-names = "se";
1449 clocks = <&gc 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1449 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1450 status = "disabled";
1452 }; 1451 };
1453 1452
1454 i2c12: i2c@a90000 { 1453 i2c12: i2c@a90000 {
1455 compatible = 1454 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1455 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1456 clock-names = "se";
1458 clocks = <&gc 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1458 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1459 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1460 dma-names = "tx", "rx";
1462 pinctrl-names 1461 pinctrl-names = "default";
1463 pinctrl-0 = < 1462 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1463 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1464 #address-cells = <1>;
1466 #size-cells = 1465 #size-cells = <0>;
1467 status = "dis 1466 status = "disabled";
1468 }; 1467 };
1469 1468
1470 spi12: spi@a90000 { 1469 spi12: spi@a90000 {
1471 compatible = 1470 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 1471 reg = <0 0x00a90000 0 0x4000>;
1473 reg-names = " 1472 reg-names = "se";
1474 clock-names = 1473 clock-names = "se";
1475 clocks = <&gc 1474 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1475 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1476 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1477 dma-names = "tx", "rx";
1479 pinctrl-names 1478 pinctrl-names = "default";
1480 pinctrl-0 = < 1479 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1480 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1481 spi-max-frequency = <50000000>;
1483 #address-cell 1482 #address-cells = <1>;
1484 #size-cells = 1483 #size-cells = <0>;
1485 status = "dis 1484 status = "disabled";
1486 }; 1485 };
1487 1486
1488 i2c16: i2c@94000 { 1487 i2c16: i2c@94000 {
1489 compatible = 1488 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 1489 reg = <0 0x00094000 0 0x4000>;
1491 clock-names = 1490 clock-names = "se";
1492 clocks = <&gc 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1492 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1493 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1494 dma-names = "tx", "rx";
1496 pinctrl-names 1495 pinctrl-names = "default";
1497 pinctrl-0 = < 1496 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1497 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1498 #address-cells = <1>;
1500 #size-cells = 1499 #size-cells = <0>;
1501 status = "dis 1500 status = "disabled";
1502 }; 1501 };
1503 1502
1504 spi16: spi@a94000 { 1503 spi16: spi@a94000 {
1505 compatible = 1504 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 1505 reg = <0 0x00a94000 0 0x4000>;
1507 reg-names = " 1506 reg-names = "se";
1508 clock-names = 1507 clock-names = "se";
1509 clocks = <&gc 1508 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1509 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1510 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1511 dma-names = "tx", "rx";
1513 pinctrl-names 1512 pinctrl-names = "default";
1514 pinctrl-0 = < 1513 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1514 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1515 spi-max-frequency = <50000000>;
1517 #address-cell 1516 #address-cells = <1>;
1518 #size-cells = 1517 #size-cells = <0>;
1519 status = "dis 1518 status = "disabled";
1520 }; 1519 };
1521 }; 1520 };
1522 1521
1523 gpi_dma2: dma-controller@c000 1522 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm 1523 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 1524 reg = <0 0x00c00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1525 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1526 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1527 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1528 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1529 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1530 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1531 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1532 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1533 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1534 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1535 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1536 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1537 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1538 dma-channels = <13>;
1540 dma-channel-mask = <0 1539 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1540 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1541 #dma-cells = <3>;
1543 status = "disabled"; 1542 status = "disabled";
1544 }; 1543 };
1545 1544
1546 qupv3_id_2: geniqup@cc0000 { 1545 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1546 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1547 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1548
1550 clock-names = "m-ahb" 1549 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1550 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1551 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1552 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1553 #address-cells = <2>;
1555 #size-cells = <2>; 1554 #size-cells = <2>;
1556 ranges; 1555 ranges;
1557 status = "disabled"; 1556 status = "disabled";
1558 1557
1559 i2c17: i2c@c80000 { 1558 i2c17: i2c@c80000 {
1560 compatible = 1559 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1560 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1561 clock-names = "se";
1563 clocks = <&gc 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1563 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1564 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1565 dma-names = "tx", "rx";
1567 pinctrl-names 1566 pinctrl-names = "default";
1568 pinctrl-0 = < 1567 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1568 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1569 #address-cells = <1>;
1571 #size-cells = 1570 #size-cells = <0>;
1572 status = "dis 1571 status = "disabled";
1573 }; 1572 };
1574 1573
1575 spi17: spi@c80000 { 1574 spi17: spi@c80000 {
1576 compatible = 1575 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1576 reg = <0 0x00c80000 0 0x4000>;
1578 reg-names = " 1577 reg-names = "se";
1579 clock-names = 1578 clock-names = "se";
1580 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1580 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1581 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1582 dma-names = "tx", "rx";
1584 pinctrl-names 1583 pinctrl-names = "default";
1585 pinctrl-0 = < 1584 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1585 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1586 spi-max-frequency = <50000000>;
1588 #address-cell 1587 #address-cells = <1>;
1589 #size-cells = 1588 #size-cells = <0>;
1590 status = "dis 1589 status = "disabled";
1591 }; 1590 };
1592 1591
1593 i2c18: i2c@c84000 { 1592 i2c18: i2c@c84000 {
1594 compatible = 1593 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1594 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1595 clock-names = "se";
1597 clocks = <&gc 1596 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1597 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1598 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1599 dma-names = "tx", "rx";
1601 pinctrl-names 1600 pinctrl-names = "default";
1602 pinctrl-0 = < 1601 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1602 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1603 #address-cells = <1>;
1605 #size-cells = 1604 #size-cells = <0>;
1606 status = "dis 1605 status = "disabled";
1607 }; 1606 };
1608 1607
1609 spi18: spi@c84000 { 1608 spi18: spi@c84000 {
1610 compatible = 1609 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 1610 reg = <0 0x00c84000 0 0x4000>;
1612 reg-names = " 1611 reg-names = "se";
1613 clock-names = 1612 clock-names = "se";
1614 clocks = <&gc 1613 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1614 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1615 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1616 dma-names = "tx", "rx";
1618 pinctrl-names 1617 pinctrl-names = "default";
1619 pinctrl-0 = < 1618 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1619 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1620 spi-max-frequency = <50000000>;
1622 #address-cell 1621 #address-cells = <1>;
1623 #size-cells = 1622 #size-cells = <0>;
1624 status = "dis 1623 status = "disabled";
1625 }; 1624 };
1626 1625
1627 i2c19: i2c@c88000 { 1626 i2c19: i2c@c88000 {
1628 compatible = 1627 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1628 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1629 clock-names = "se";
1631 clocks = <&gc 1630 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1631 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1632 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1633 dma-names = "tx", "rx";
1635 pinctrl-names 1634 pinctrl-names = "default";
1636 pinctrl-0 = < 1635 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1636 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1637 #address-cells = <1>;
1639 #size-cells = 1638 #size-cells = <0>;
1640 status = "dis 1639 status = "disabled";
1641 }; 1640 };
1642 1641
1643 spi19: spi@c88000 { 1642 spi19: spi@c88000 {
1644 compatible = 1643 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 1644 reg = <0 0x00c88000 0 0x4000>;
1646 reg-names = " 1645 reg-names = "se";
1647 clock-names = 1646 clock-names = "se";
1648 clocks = <&gc 1647 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1648 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1649 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1650 dma-names = "tx", "rx";
1652 pinctrl-names 1651 pinctrl-names = "default";
1653 pinctrl-0 = < 1652 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1653 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1654 spi-max-frequency = <50000000>;
1656 #address-cell 1655 #address-cells = <1>;
1657 #size-cells = 1656 #size-cells = <0>;
1658 status = "dis 1657 status = "disabled";
1659 }; 1658 };
1660 1659
1661 i2c13: i2c@c8c000 { 1660 i2c13: i2c@c8c000 {
1662 compatible = 1661 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1662 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1663 clock-names = "se";
1665 clocks = <&gc 1664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1665 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1666 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1667 dma-names = "tx", "rx";
1669 pinctrl-names 1668 pinctrl-names = "default";
1670 pinctrl-0 = < 1669 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1670 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1671 #address-cells = <1>;
1673 #size-cells = 1672 #size-cells = <0>;
1674 status = "dis 1673 status = "disabled";
1675 }; 1674 };
1676 1675
1677 spi13: spi@c8c000 { 1676 spi13: spi@c8c000 {
1678 compatible = 1677 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 1678 reg = <0 0x00c8c000 0 0x4000>;
1680 reg-names = " 1679 reg-names = "se";
1681 clock-names = 1680 clock-names = "se";
1682 clocks = <&gc 1681 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1682 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1683 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1684 dma-names = "tx", "rx";
1686 pinctrl-names 1685 pinctrl-names = "default";
1687 pinctrl-0 = < 1686 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1687 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1688 spi-max-frequency = <50000000>;
1690 #address-cell 1689 #address-cells = <1>;
1691 #size-cells = 1690 #size-cells = <0>;
1692 status = "dis 1691 status = "disabled";
1693 }; 1692 };
1694 1693
1695 i2c14: i2c@c90000 { 1694 i2c14: i2c@c90000 {
1696 compatible = 1695 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1696 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1697 clock-names = "se";
1699 clocks = <&gc 1698 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1699 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1700 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1701 dma-names = "tx", "rx";
1703 pinctrl-names 1702 pinctrl-names = "default";
1704 pinctrl-0 = < 1703 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1705 #address-cells = <1>;
1707 #size-cells = 1706 #size-cells = <0>;
1708 status = "dis 1707 status = "disabled";
1709 }; 1708 };
1710 1709
1711 spi14: spi@c90000 { 1710 spi14: spi@c90000 {
1712 compatible = 1711 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 1712 reg = <0 0x00c90000 0 0x4000>;
1714 reg-names = " 1713 reg-names = "se";
1715 clock-names = 1714 clock-names = "se";
1716 clocks = <&gc 1715 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1716 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1717 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1718 dma-names = "tx", "rx";
1720 pinctrl-names 1719 pinctrl-names = "default";
1721 pinctrl-0 = < 1720 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1721 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1722 spi-max-frequency = <50000000>;
1724 #address-cell 1723 #address-cells = <1>;
1725 #size-cells = 1724 #size-cells = <0>;
1726 status = "dis 1725 status = "disabled";
1727 }; 1726 };
1728 1727
1729 i2c15: i2c@c94000 { 1728 i2c15: i2c@c94000 {
1730 compatible = 1729 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1730 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1731 clock-names = "se";
1733 clocks = <&gc 1732 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1733 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1734 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1735 dma-names = "tx", "rx";
1737 pinctrl-names 1736 pinctrl-names = "default";
1738 pinctrl-0 = < 1737 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1738 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1739 #address-cells = <1>;
1741 #size-cells = 1740 #size-cells = <0>;
1742 status = "dis 1741 status = "disabled";
1743 }; 1742 };
1744 1743
1745 spi15: spi@c94000 { 1744 spi15: spi@c94000 {
1746 compatible = 1745 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 1746 reg = <0 0x00c94000 0 0x4000>;
1748 reg-names = " 1747 reg-names = "se";
1749 clock-names = 1748 clock-names = "se";
1750 clocks = <&gc 1749 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1750 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1751 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1752 dma-names = "tx", "rx";
1754 pinctrl-names 1753 pinctrl-names = "default";
1755 pinctrl-0 = < 1754 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1755 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1756 spi-max-frequency = <50000000>;
1758 #address-cell 1757 #address-cells = <1>;
1759 #size-cells = 1758 #size-cells = <0>;
1760 status = "dis 1759 status = "disabled";
1761 }; 1760 };
1762 }; 1761 };
1763 1762
1764 config_noc: interconnect@1500 1763 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1764 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1765 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = 1766 #interconnect-cells = <2>;
1768 qcom,bcm-voters = <&a 1767 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1768 };
1770 1769
1771 system_noc: interconnect@1620 1770 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1771 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1772 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = 1773 #interconnect-cells = <2>;
1775 qcom,bcm-voters = <&a 1774 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1775 };
1777 1776
1778 mc_virt: interconnect@163a000 1777 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1778 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1779 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = 1780 #interconnect-cells = <2>;
1782 qcom,bcm-voters = <&a 1781 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1782 };
1784 1783
1785 aggre1_noc: interconnect@16e0 1784 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1785 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1786 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = 1787 #interconnect-cells = <2>;
1789 qcom,bcm-voters = <&a 1788 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1789 };
1791 1790
1792 aggre2_noc: interconnect@1700 1791 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1792 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1793 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = 1794 #interconnect-cells = <2>;
1796 qcom,bcm-voters = <&a 1795 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1796 };
1798 1797
1799 compute_noc: interconnect@172 1798 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1799 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1800 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = 1801 #interconnect-cells = <2>;
1803 qcom,bcm-voters = <&a 1802 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1803 };
1805 1804
1806 mmss_noc: interconnect@174000 1805 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1806 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1807 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = 1808 #interconnect-cells = <2>;
1810 qcom,bcm-voters = <&a 1809 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1810 };
1812 1811
1813 system-cache-controller@92000 1812 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1813 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 1814 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1816 <0 0x09300000 0 1815 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1817 <0 0x09600000 0 1816 <0 0x09600000 0 0x50000>;
1818 reg-names = "llcc0_ba 1817 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1819 "llcc3_ba 1818 "llcc3_base", "llcc_broadcast_base";
1820 interrupts = <GIC_SPI 1819 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1820 };
1822 1821
1823 dma@10a2000 { 1822 dma@10a2000 {
1824 compatible = "qcom,sm 1823 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1825 reg = <0x0 0x010a2000 1824 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 1825 <0x0 0x010ad000 0x0 0x3000>;
1827 }; 1826 };
1828 1827
1829 pcie0: pcie@1c00000 { 1828 pcie0: pcie@1c00000 {
1830 compatible = "qcom,pc 1829 compatible = "qcom,pcie-sm8150";
1831 reg = <0 0x01c00000 0 1830 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1831 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1832 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1833 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1834 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1835 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1836 device_type = "pci";
1838 linux,pci-domain = <0 1837 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1838 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1839 num-lanes = <1>;
1841 1840
1842 #address-cells = <3>; 1841 #address-cells = <3>;
1843 #size-cells = <2>; 1842 #size-cells = <2>;
1844 1843
1845 ranges = <0x01000000 1844 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 1845 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 1846
1848 interrupts = <GIC_SPI 1847 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 1848 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 1849 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 1850 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 1851 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 1852 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 1853 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 1854 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1856 interrupt-names = "ms 1855 interrupt-names = "msi0",
1857 "ms 1856 "msi1",
1858 "ms 1857 "msi2",
1859 "ms 1858 "msi3",
1860 "ms 1859 "msi4",
1861 "ms 1860 "msi5",
1862 "ms 1861 "msi6",
1863 "ms 1862 "msi7";
1864 #interrupt-cells = <1 1863 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1864 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1865 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1866 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1867 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1868 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1869
1871 clocks = <&gcc GCC_PC 1870 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1871 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1872 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1873 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1874 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1875 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG 1876 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1878 <&rpmhcc RPM 1877 <&rpmhcc RPMH_CXO_CLK>;
1879 clock-names = "pipe", 1878 clock-names = "pipe",
1880 "aux", 1879 "aux",
1881 "cfg", 1880 "cfg",
1882 "bus_ma 1881 "bus_master",
1883 "bus_sl 1882 "bus_slave",
1884 "slave_ 1883 "slave_q2a",
1885 "tbu", 1884 "tbu",
1886 "ref"; 1885 "ref";
1887 1886
1888 iommu-map = <0x0 &a 1887 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1888 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1889
1891 resets = <&gcc GCC_PC 1890 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1891 reset-names = "pci";
1893 1892
1894 power-domains = <&gcc 1893 power-domains = <&gcc PCIE_0_GDSC>;
1895 1894
1896 phys = <&pcie0_phy>; 1895 phys = <&pcie0_phy>;
1897 phy-names = "pciephy" 1896 phy-names = "pciephy";
1898 1897
1899 perst-gpios = <&tlmm 1898 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 1899 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1900
1902 pinctrl-names = "defa 1901 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1902 pinctrl-0 = <&pcie0_default_state>;
1904 1903
1905 status = "disabled"; 1904 status = "disabled";
1906 1905
1907 pcie@0 { 1906 pcie@0 {
1908 device_type = 1907 device_type = "pci";
1909 reg = <0x0 0x 1908 reg = <0x0 0x0 0x0 0x0 0x0>;
1910 bus-range = < 1909 bus-range = <0x01 0xff>;
1911 1910
1912 #address-cell 1911 #address-cells = <3>;
1913 #size-cells = 1912 #size-cells = <2>;
1914 ranges; 1913 ranges;
1915 }; 1914 };
1916 }; 1915 };
1917 1916
1918 pcie0_phy: phy@1c06000 { 1917 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1918 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 1919 reg = <0 0x01c06000 0 0x1000>;
1921 clocks = <&gcc GCC_PC 1920 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1921 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC 1922 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1924 <&gcc GCC_PC 1923 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1925 <&gcc GCC_PC 1924 <&gcc GCC_PCIE_0_PIPE_CLK>;
1926 clock-names = "aux", 1925 clock-names = "aux",
1927 "cfg_ah 1926 "cfg_ahb",
1928 "ref", 1927 "ref",
1929 "refgen 1928 "refgen",
1930 "pipe"; 1929 "pipe";
1931 1930
1932 clock-output-names = 1931 clock-output-names = "pcie_0_pipe_clk";
1933 #clock-cells = <0>; 1932 #clock-cells = <0>;
1934 1933
1935 #phy-cells = <0>; 1934 #phy-cells = <0>;
1936 1935
1937 resets = <&gcc GCC_PC 1936 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1937 reset-names = "phy";
1939 1938
1940 assigned-clocks = <&g 1939 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1940 assigned-clock-rates = <100000000>;
1942 1941
1943 status = "disabled"; 1942 status = "disabled";
1944 }; 1943 };
1945 1944
1946 pcie1: pcie@1c08000 { 1945 pcie1: pcie@1c08000 {
1947 compatible = "qcom,pc 1946 compatible = "qcom,pcie-sm8150";
1948 reg = <0 0x01c08000 0 1947 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1948 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1949 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1950 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1951 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1952 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1953 device_type = "pci";
1955 linux,pci-domain = <1 1954 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1955 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1956 num-lanes = <2>;
1958 1957
1959 #address-cells = <3>; 1958 #address-cells = <3>;
1960 #size-cells = <2>; 1959 #size-cells = <2>;
1961 1960
1962 ranges = <0x01000000 1961 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1962 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1963
1965 interrupts = <GIC_SPI 1964 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 1965 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 1966 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 1967 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 1968 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 1969 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 1970 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 1971 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1973 interrupt-names = "ms 1972 interrupt-names = "msi0",
1974 "ms 1973 "msi1",
1975 "ms 1974 "msi2",
1976 "ms 1975 "msi3",
1977 "ms 1976 "msi4",
1978 "ms 1977 "msi5",
1979 "ms 1978 "msi6",
1980 "ms 1979 "msi7";
1981 #interrupt-cells = <1 1980 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1981 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1982 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1983 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1984 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1985 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1986
1988 clocks = <&gcc GCC_PC 1987 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1988 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1989 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1990 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1991 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1992 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG 1993 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
1995 <&rpmhcc RPM 1994 <&rpmhcc RPMH_CXO_CLK>;
1996 clock-names = "pipe", 1995 clock-names = "pipe",
1997 "aux", 1996 "aux",
1998 "cfg", 1997 "cfg",
1999 "bus_ma 1998 "bus_master",
2000 "bus_sl 1999 "bus_slave",
2001 "slave_ 2000 "slave_q2a",
2002 "tbu", 2001 "tbu",
2003 "ref"; 2002 "ref";
2004 2003
2005 assigned-clocks = <&g 2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 2005 assigned-clock-rates = <19200000>;
2007 2006
2008 iommu-map = <0x0 &a 2007 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 2008 <0x100 &apps_smmu 0x1e01 0x1>;
2010 2009
2011 resets = <&gcc GCC_PC 2010 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 2011 reset-names = "pci";
2013 2012
2014 power-domains = <&gcc 2013 power-domains = <&gcc PCIE_1_GDSC>;
2015 2014
2016 phys = <&pcie1_phy>; 2015 phys = <&pcie1_phy>;
2017 phy-names = "pciephy" 2016 phy-names = "pciephy";
2018 2017
2019 perst-gpios = <&tlmm 2018 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 2019 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 2020
2022 pinctrl-names = "defa 2021 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 2022 pinctrl-0 = <&pcie1_default_state>;
2024 2023
2025 status = "disabled"; 2024 status = "disabled";
2026 2025
2027 pcie@0 { 2026 pcie@0 {
2028 device_type = 2027 device_type = "pci";
2029 reg = <0x0 0x 2028 reg = <0x0 0x0 0x0 0x0 0x0>;
2030 bus-range = < 2029 bus-range = <0x01 0xff>;
2031 2030
2032 #address-cell 2031 #address-cells = <3>;
2033 #size-cells = 2032 #size-cells = <2>;
2034 ranges; 2033 ranges;
2035 }; 2034 };
2036 }; 2035 };
2037 2036
2038 pcie1_phy: phy@1c0e000 { 2037 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 2038 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 2039 reg = <0 0x01c0e000 0 0x1000>;
2041 clocks = <&gcc GCC_PC 2040 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC 2042 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2044 <&gcc GCC_PC 2043 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2045 <&gcc GCC_PC 2044 <&gcc GCC_PCIE_1_PIPE_CLK>;
2046 clock-names = "aux", 2045 clock-names = "aux",
2047 "cfg_ah 2046 "cfg_ahb",
2048 "ref", 2047 "ref",
2049 "refgen 2048 "refgen",
2050 "pipe"; 2049 "pipe";
2051 2050
2052 clock-output-names = 2051 clock-output-names = "pcie_1_pipe_clk";
2053 #clock-cells = <0>; 2052 #clock-cells = <0>;
2054 2053
2055 #phy-cells = <0>; 2054 #phy-cells = <0>;
2056 2055
2057 resets = <&gcc GCC_PC 2056 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 2057 reset-names = "phy";
2059 2058
2060 assigned-clocks = <&g 2059 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 2060 assigned-clock-rates = <100000000>;
2062 2061
2063 status = "disabled"; 2062 status = "disabled";
2064 }; 2063 };
2065 2064
2066 ufs_mem_hc: ufshc@1d84000 { 2065 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 2066 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 2067 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 2068 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 2069 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 2070 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 2071 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> 2072 phys = <&ufs_mem_phy>;
2074 phy-names = "ufsphy"; 2073 phy-names = "ufsphy";
2075 lanes-per-direction = 2074 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 2075 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 2076 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 2077 reset-names = "rst";
2079 2078
2080 iommus = <&apps_smmu 2079 iommus = <&apps_smmu 0x300 0>;
2081 2080
2082 clock-names = 2081 clock-names =
2083 "core_clk", 2082 "core_clk",
2084 "bus_aggr_clk 2083 "bus_aggr_clk",
2085 "iface_clk", 2084 "iface_clk",
2086 "core_clk_uni 2085 "core_clk_unipro",
2087 "ref_clk", 2086 "ref_clk",
2088 "tx_lane0_syn 2087 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 2088 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 2089 "rx_lane1_sync_clk",
2091 "ice_core_clk 2090 "ice_core_clk";
2092 clocks = 2091 clocks =
2093 <&gcc GCC_UFS 2092 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 2093 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 2094 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 2095 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 2096 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 2097 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2098 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2100 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2101 freq-table-hz =
2103 <37500000 300 2102 <37500000 300000000>,
2104 <0 0>, 2103 <0 0>,
2105 <0 0>, 2104 <0 0>,
2106 <37500000 300 2105 <37500000 300000000>,
2107 <0 0>, 2106 <0 0>,
2108 <0 0>, 2107 <0 0>,
2109 <0 0>, 2108 <0 0>,
2110 <0 0>, 2109 <0 0>,
2111 <0 300000000> 2110 <0 300000000>;
2112 2111
2113 status = "disabled"; 2112 status = "disabled";
2114 }; 2113 };
2115 2114
2116 ufs_mem_phy: phy@1d87000 { 2115 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2116 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 2117 reg = <0 0x01d87000 0 0x1000>;
2119 2118
2120 clocks = <&rpmhcc RPM 2119 clocks = <&rpmhcc RPMH_CXO_CLK>,
2121 <&gcc GCC_UF 2120 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2122 <&gcc GCC_UF 2121 <&gcc GCC_UFS_MEM_CLKREF_CLK>;
2123 clock-names = "ref", 2122 clock-names = "ref",
2124 "ref_au 2123 "ref_aux",
2125 "qref"; 2124 "qref";
2126 2125
2127 power-domains = <&gcc 2126 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2127
2129 resets = <&ufs_mem_hc 2128 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2129 reset-names = "ufsphy";
2131 2130
2132 #phy-cells = <0>; 2131 #phy-cells = <0>;
2133 2132
2134 status = "disabled"; 2133 status = "disabled";
2135 }; 2134 };
2136 2135
2137 cryptobam: dma-controller@1dc 2136 cryptobam: dma-controller@1dc4000 {
2138 compatible = "qcom,ba 2137 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2139 reg = <0 0x01dc4000 0 2138 reg = <0 0x01dc4000 0 0x24000>;
2140 interrupts = <GIC_SPI 2139 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2141 #dma-cells = <1>; 2140 #dma-cells = <1>;
2142 qcom,ee = <0>; 2141 qcom,ee = <0>;
2143 qcom,controlled-remot 2142 qcom,controlled-remotely;
2144 num-channels = <8>; 2143 num-channels = <8>;
2145 qcom,num-ees = <2>; 2144 qcom,num-ees = <2>;
2146 iommus = <&apps_smmu 2145 iommus = <&apps_smmu 0x502 0x0641>,
2147 <&apps_smmu 2146 <&apps_smmu 0x504 0x0011>,
2148 <&apps_smmu 2147 <&apps_smmu 0x506 0x0011>,
2149 <&apps_smmu 2148 <&apps_smmu 0x508 0x0011>,
2150 <&apps_smmu 2149 <&apps_smmu 0x512 0x0000>;
2151 }; 2150 };
2152 2151
2153 crypto: crypto@1dfa000 { 2152 crypto: crypto@1dfa000 {
2154 compatible = "qcom,sm 2153 compatible = "qcom,sm8150-qce", "qcom,qce";
2155 reg = <0 0x01dfa000 0 2154 reg = <0 0x01dfa000 0 0x6000>;
2156 dmas = <&cryptobam 4> 2155 dmas = <&cryptobam 4>, <&cryptobam 5>;
2157 dma-names = "rx", "tx 2156 dma-names = "rx", "tx";
2158 iommus = <&apps_smmu 2157 iommus = <&apps_smmu 0x502 0x0641>,
2159 <&apps_smmu 2158 <&apps_smmu 0x504 0x0011>,
2160 <&apps_smmu 2159 <&apps_smmu 0x506 0x0011>,
2161 <&apps_smmu 2160 <&apps_smmu 0x508 0x0011>,
2162 <&apps_smmu 2161 <&apps_smmu 0x512 0x0000>;
2163 interconnects = <&agg 2162 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2164 interconnect-names = 2163 interconnect-names = "memory";
2165 }; 2164 };
2166 2165
2167 tcsr_mutex: hwlock@1f40000 { 2166 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc 2167 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 2168 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>; 2169 #hwlock-cells = <1>;
2171 }; 2170 };
2172 2171
2173 tcsr_regs_1: syscon@1f60000 { 2172 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm 2173 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 2174 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 }; 2175 };
2177 2176
2178 remoteproc_slpi: remoteproc@2 2177 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2178 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2179 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2180
2182 interrupts-extended = 2181 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2182 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2183 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2184 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2185 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2186 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2187 "handover", "stop-ack";
2189 2188
2190 clocks = <&rpmhcc RPM 2189 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2190 clock-names = "xo";
2192 2191
2193 power-domains = <&rpm 2192 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpm 2193 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = 2194 power-domain-names = "lcx", "lmx";
2196 2195
2197 memory-region = <&slp 2196 memory-region = <&slpi_mem>;
2198 2197
2199 qcom,qmp = <&aoss_qmp 2198 qcom,qmp = <&aoss_qmp>;
2200 2199
2201 qcom,smem-states = <& 2200 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2201 qcom,smem-state-names = "stop";
2203 2202
2204 status = "disabled"; 2203 status = "disabled";
2205 2204
2206 glink-edge { 2205 glink-edge {
2207 interrupts = 2206 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2207 label = "dsps";
2209 qcom,remote-p 2208 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2209 mboxes = <&apss_shared 24>;
2211 2210
2212 fastrpc { 2211 fastrpc {
2213 compa 2212 compatible = "qcom,fastrpc";
2214 qcom, 2213 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2214 label = "sdsp";
2216 qcom, 2215 qcom,non-secure-domain;
2217 #addr 2216 #address-cells = <1>;
2218 #size 2217 #size-cells = <0>;
2219 2218
2220 compu 2219 compute-cb@1 {
2221 2220 compatible = "qcom,fastrpc-compute-cb";
2222 2221 reg = <1>;
2223 2222 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2223 };
2225 2224
2226 compu 2225 compute-cb@2 {
2227 2226 compatible = "qcom,fastrpc-compute-cb";
2228 2227 reg = <2>;
2229 2228 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2229 };
2231 2230
2232 compu 2231 compute-cb@3 {
2233 2232 compatible = "qcom,fastrpc-compute-cb";
2234 2233 reg = <3>;
2235 2234 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2235 /* note: shared-cb = <4> in downstream */
2237 }; 2236 };
2238 }; 2237 };
2239 }; 2238 };
2240 }; 2239 };
2241 2240
2242 gpu: gpu@2c00000 { 2241 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad 2242 compatible = "qcom,adreno-640.1", "qcom,adreno";
2244 reg = <0 0x02c00000 0 2243 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2244 reg-names = "kgsl_3d0_reg_memory";
2246 2245
2247 interrupts = <GIC_SPI 2246 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2247
2249 iommus = <&adreno_smm 2248 iommus = <&adreno_smmu 0 0x401>;
2250 2249
2251 operating-points-v2 = 2250 operating-points-v2 = <&gpu_opp_table>;
2252 2251
2253 qcom,gmu = <&gmu>; 2252 qcom,gmu = <&gmu>;
2254 2253
2255 nvmem-cells = <&gpu_s 2254 nvmem-cells = <&gpu_speed_bin>;
2256 nvmem-cell-names = "s 2255 nvmem-cell-names = "speed_bin";
2257 #cooling-cells = <2>; 2256 #cooling-cells = <2>;
2258 2257
2259 status = "disabled"; 2258 status = "disabled";
2260 2259
2261 zap-shader { 2260 zap-shader {
2262 memory-region 2261 memory-region = <&gpu_mem>;
2263 }; 2262 };
2264 2263
2265 gpu_opp_table: opp-ta 2264 gpu_opp_table: opp-table {
2266 compatible = 2265 compatible = "operating-points-v2";
2267 2266
2268 opp-675000000 2267 opp-675000000 {
2269 opp-h 2268 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2269 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s 2270 opp-supported-hw = <0x2>;
2272 }; 2271 };
2273 2272
2274 opp-585000000 2273 opp-585000000 {
2275 opp-h 2274 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2275 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s 2276 opp-supported-hw = <0x3>;
2278 }; 2277 };
2279 2278
2280 opp-499200000 2279 opp-499200000 {
2281 opp-h 2280 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2281 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s 2282 opp-supported-hw = <0x3>;
2284 }; 2283 };
2285 2284
2286 opp-427000000 2285 opp-427000000 {
2287 opp-h 2286 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2287 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s 2288 opp-supported-hw = <0x3>;
2290 }; 2289 };
2291 2290
2292 opp-345000000 2291 opp-345000000 {
2293 opp-h 2292 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2293 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s 2294 opp-supported-hw = <0x3>;
2296 }; 2295 };
2297 2296
2298 opp-257000000 2297 opp-257000000 {
2299 opp-h 2298 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2299 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s 2300 opp-supported-hw = <0x3>;
2302 }; 2301 };
2303 }; 2302 };
2304 }; 2303 };
2305 2304
2306 gmu: gmu@2c6a000 { 2305 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad 2306 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2307
2309 reg = <0 0x02c6a000 0 2308 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2309 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2310 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2311 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2312
2314 interrupts = <GIC_SPI 2313 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2314 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2315 interrupt-names = "hfi", "gmu";
2317 2316
2318 clocks = <&gpucc GPU_ 2317 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2318 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2319 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2320 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2321 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2322 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2323
2325 power-domains = <&gpu 2324 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2325 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2326 power-domain-names = "cx", "gx";
2328 2327
2329 iommus = <&adreno_smm 2328 iommus = <&adreno_smmu 5 0x400>;
2330 2329
2331 operating-points-v2 = 2330 operating-points-v2 = <&gmu_opp_table>;
2332 2331
2333 status = "disabled"; 2332 status = "disabled";
2334 2333
2335 gmu_opp_table: opp-ta 2334 gmu_opp_table: opp-table {
2336 compatible = 2335 compatible = "operating-points-v2";
2337 2336
2338 opp-200000000 2337 opp-200000000 {
2339 opp-h 2338 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2339 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2340 };
2342 }; 2341 };
2343 }; 2342 };
2344 2343
2345 gpucc: clock-controller@2c900 2344 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2345 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2346 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2347 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2348 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2349 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2350 clock-names = "bi_tcxo",
2352 "gcc_gp 2351 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2352 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2353 #clock-cells = <1>;
2355 #reset-cells = <1>; 2354 #reset-cells = <1>;
2356 #power-domain-cells = 2355 #power-domain-cells = <1>;
2357 }; 2356 };
2358 2357
2359 adreno_smmu: iommu@2ca0000 { 2358 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm 2359 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2361 "qcom,sm 2360 "qcom,smmu-500", "arm,mmu-500";
2362 reg = <0 0x02ca0000 0 2361 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2362 #iommu-cells = <2>;
2364 #global-interrupts = 2363 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2364 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2365 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2366 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2367 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2368 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2369 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2370 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2371 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2372 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2373 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2374 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2375 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2376 clock-names = "ahb", "bus", "iface";
2378 2377
2379 power-domains = <&gpu 2378 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2379 };
2381 2380
2382 tlmm: pinctrl@3100000 { 2381 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2382 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2383 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2384 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2385 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2386 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2387 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2388 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2389 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2390 gpio-controller;
2392 #gpio-cells = <2>; 2391 #gpio-cells = <2>;
2393 interrupt-controller; 2392 interrupt-controller;
2394 #interrupt-cells = <2 2393 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2394 wakeup-parent = <&pdc>;
2396 2395
2397 qup_i2c0_default: qup 2396 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0 2397 pins = "gpio0", "gpio1";
2399 function = "q 2398 function = "qup0";
2400 drive-strengt 2399 drive-strength = <0x02>;
2401 bias-disable; 2400 bias-disable;
2402 }; 2401 };
2403 2402
2404 qup_spi0_default: qup 2403 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0 2404 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2405 function = "qup0";
2407 drive-strengt 2406 drive-strength = <6>;
2408 bias-disable; 2407 bias-disable;
2409 }; 2408 };
2410 2409
2411 qup_i2c1_default: qup 2410 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio1 2411 pins = "gpio114", "gpio115";
2413 function = "q 2412 function = "qup1";
2414 drive-strengt 2413 drive-strength = <2>;
2415 bias-disable; 2414 bias-disable;
2416 }; 2415 };
2417 2416
2418 qup_spi1_default: qup 2417 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio1 2418 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2419 function = "qup1";
2421 drive-strengt 2420 drive-strength = <6>;
2422 bias-disable; 2421 bias-disable;
2423 }; 2422 };
2424 2423
2425 qup_i2c2_default: qup 2424 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio1 2425 pins = "gpio126", "gpio127";
2427 function = "q 2426 function = "qup2";
2428 drive-strengt 2427 drive-strength = <2>;
2429 bias-disable; 2428 bias-disable;
2430 }; 2429 };
2431 2430
2432 qup_spi2_default: qup 2431 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio1 2432 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2433 function = "qup2";
2435 drive-strengt 2434 drive-strength = <6>;
2436 bias-disable; 2435 bias-disable;
2437 }; 2436 };
2438 2437
2439 qup_i2c3_default: qup 2438 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio1 2439 pins = "gpio144", "gpio145";
2441 function = "q 2440 function = "qup3";
2442 drive-strengt 2441 drive-strength = <2>;
2443 bias-disable; 2442 bias-disable;
2444 }; 2443 };
2445 2444
2446 qup_spi3_default: qup 2445 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio1 2446 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2447 function = "qup3";
2449 drive-strengt 2448 drive-strength = <6>;
2450 bias-disable; 2449 bias-disable;
2451 }; 2450 };
2452 2451
2453 qup_i2c4_default: qup 2452 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio5 2453 pins = "gpio51", "gpio52";
2455 function = "q 2454 function = "qup4";
2456 drive-strengt 2455 drive-strength = <2>;
2457 bias-disable; 2456 bias-disable;
2458 }; 2457 };
2459 2458
2460 qup_spi4_default: qup 2459 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio5 2460 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2461 function = "qup4";
2463 drive-strengt 2462 drive-strength = <6>;
2464 bias-disable; 2463 bias-disable;
2465 }; 2464 };
2466 2465
2467 qup_i2c5_default: qup 2466 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio1 2467 pins = "gpio121", "gpio122";
2469 function = "q 2468 function = "qup5";
2470 drive-strengt 2469 drive-strength = <2>;
2471 bias-disable; 2470 bias-disable;
2472 }; 2471 };
2473 2472
2474 qup_spi5_default: qup 2473 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio1 2474 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2475 function = "qup5";
2477 drive-strengt 2476 drive-strength = <6>;
2478 bias-disable; 2477 bias-disable;
2479 }; 2478 };
2480 2479
2481 qup_i2c6_default: qup 2480 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6 2481 pins = "gpio6", "gpio7";
2483 function = "q 2482 function = "qup6";
2484 drive-strengt 2483 drive-strength = <2>;
2485 bias-disable; 2484 bias-disable;
2486 }; 2485 };
2487 2486
2488 qup_spi6_default: qup 2487 qup_spi6_default: qup-spi6-default-state {
2489 pins = "gpio4 2488 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2489 function = "qup6";
2491 drive-strengt 2490 drive-strength = <6>;
2492 bias-disable; 2491 bias-disable;
2493 }; 2492 };
2494 2493
2495 qup_i2c7_default: qup 2494 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio9 2495 pins = "gpio98", "gpio99";
2497 function = "q 2496 function = "qup7";
2498 drive-strengt 2497 drive-strength = <2>;
2499 bias-disable; 2498 bias-disable;
2500 }; 2499 };
2501 2500
2502 qup_spi7_default: qup 2501 qup_spi7_default: qup-spi7-default-state {
2503 pins = "gpio9 2502 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2503 function = "qup7";
2505 drive-strengt 2504 drive-strength = <6>;
2506 bias-disable; 2505 bias-disable;
2507 }; 2506 };
2508 2507
2509 qup_i2c8_default: qup 2508 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio8 2509 pins = "gpio88", "gpio89";
2511 function = "q 2510 function = "qup8";
2512 drive-strengt 2511 drive-strength = <2>;
2513 bias-disable; 2512 bias-disable;
2514 }; 2513 };
2515 2514
2516 qup_spi8_default: qup 2515 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio8 2516 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2517 function = "qup8";
2519 drive-strengt 2518 drive-strength = <6>;
2520 bias-disable; 2519 bias-disable;
2521 }; 2520 };
2522 2521
2523 qup_i2c9_default: qup 2522 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio3 2523 pins = "gpio39", "gpio40";
2525 function = "q 2524 function = "qup9";
2526 drive-strengt 2525 drive-strength = <2>;
2527 bias-disable; 2526 bias-disable;
2528 }; 2527 };
2529 2528
2530 qup_spi9_default: qup 2529 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio3 2530 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2531 function = "qup9";
2533 drive-strengt 2532 drive-strength = <6>;
2534 bias-disable; 2533 bias-disable;
2535 }; 2534 };
2536 2535
2537 qup_uart9_default: qu 2536 qup_uart9_default: qup-uart9-default-state {
2538 pins = "gpio4 2537 pins = "gpio41", "gpio42";
2539 function = "q 2538 function = "qup9";
2540 drive-strengt 2539 drive-strength = <2>;
2541 bias-disable; 2540 bias-disable;
2542 }; 2541 };
2543 2542
2544 qup_i2c10_default: qu 2543 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9 2544 pins = "gpio9", "gpio10";
2546 function = "q 2545 function = "qup10";
2547 drive-strengt 2546 drive-strength = <2>;
2548 bias-disable; 2547 bias-disable;
2549 }; 2548 };
2550 2549
2551 qup_spi10_default: qu 2550 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9 2551 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2552 function = "qup10";
2554 drive-strengt 2553 drive-strength = <6>;
2555 bias-disable; 2554 bias-disable;
2556 }; 2555 };
2557 2556
2558 qup_i2c11_default: qu 2557 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio9 2558 pins = "gpio94", "gpio95";
2560 function = "q 2559 function = "qup11";
2561 drive-strengt 2560 drive-strength = <2>;
2562 bias-disable; 2561 bias-disable;
2563 }; 2562 };
2564 2563
2565 qup_spi11_default: qu 2564 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio9 2565 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2566 function = "qup11";
2568 drive-strengt 2567 drive-strength = <6>;
2569 bias-disable; 2568 bias-disable;
2570 }; 2569 };
2571 2570
2572 qup_i2c12_default: qu 2571 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio8 2572 pins = "gpio83", "gpio84";
2574 function = "q 2573 function = "qup12";
2575 drive-strengt 2574 drive-strength = <2>;
2576 bias-disable; 2575 bias-disable;
2577 }; 2576 };
2578 2577
2579 qup_spi12_default: qu 2578 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio8 2579 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2580 function = "qup12";
2582 drive-strengt 2581 drive-strength = <6>;
2583 bias-disable; 2582 bias-disable;
2584 }; 2583 };
2585 2584
2586 qup_i2c13_default: qu 2585 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio4 2586 pins = "gpio43", "gpio44";
2588 function = "q 2587 function = "qup13";
2589 drive-strengt 2588 drive-strength = <2>;
2590 bias-disable; 2589 bias-disable;
2591 }; 2590 };
2592 2591
2593 qup_spi13_default: qu 2592 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio4 2593 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2594 function = "qup13";
2596 drive-strengt 2595 drive-strength = <6>;
2597 bias-disable; 2596 bias-disable;
2598 }; 2597 };
2599 2598
2600 qup_i2c14_default: qu 2599 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio4 2600 pins = "gpio47", "gpio48";
2602 function = "q 2601 function = "qup14";
2603 drive-strengt 2602 drive-strength = <2>;
2604 bias-disable; 2603 bias-disable;
2605 }; 2604 };
2606 2605
2607 qup_spi14_default: qu 2606 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio4 2607 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2608 function = "qup14";
2610 drive-strengt 2609 drive-strength = <6>;
2611 bias-disable; 2610 bias-disable;
2612 }; 2611 };
2613 2612
2614 qup_i2c15_default: qu 2613 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio2 2614 pins = "gpio27", "gpio28";
2616 function = "q 2615 function = "qup15";
2617 drive-strengt 2616 drive-strength = <2>;
2618 bias-disable; 2617 bias-disable;
2619 }; 2618 };
2620 2619
2621 qup_spi15_default: qu 2620 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio2 2621 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2622 function = "qup15";
2624 drive-strengt 2623 drive-strength = <6>;
2625 bias-disable; 2624 bias-disable;
2626 }; 2625 };
2627 2626
2628 qup_i2c16_default: qu 2627 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio8 2628 pins = "gpio86", "gpio85";
2630 function = "q 2629 function = "qup16";
2631 drive-strengt 2630 drive-strength = <2>;
2632 bias-disable; 2631 bias-disable;
2633 }; 2632 };
2634 2633
2635 qup_spi16_default: qu 2634 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio8 2635 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2636 function = "qup16";
2638 drive-strengt 2637 drive-strength = <6>;
2639 bias-disable; 2638 bias-disable;
2640 }; 2639 };
2641 2640
2642 qup_i2c17_default: qu 2641 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio5 2642 pins = "gpio55", "gpio56";
2644 function = "q 2643 function = "qup17";
2645 drive-strengt 2644 drive-strength = <2>;
2646 bias-disable; 2645 bias-disable;
2647 }; 2646 };
2648 2647
2649 qup_spi17_default: qu 2648 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio5 2649 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2650 function = "qup17";
2652 drive-strengt 2651 drive-strength = <6>;
2653 bias-disable; 2652 bias-disable;
2654 }; 2653 };
2655 2654
2656 qup_i2c18_default: qu 2655 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio2 2656 pins = "gpio23", "gpio24";
2658 function = "q 2657 function = "qup18";
2659 drive-strengt 2658 drive-strength = <2>;
2660 bias-disable; 2659 bias-disable;
2661 }; 2660 };
2662 2661
2663 qup_spi18_default: qu 2662 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio2 2663 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2664 function = "qup18";
2666 drive-strengt 2665 drive-strength = <6>;
2667 bias-disable; 2666 bias-disable;
2668 }; 2667 };
2669 2668
2670 qup_i2c19_default: qu 2669 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio5 2670 pins = "gpio57", "gpio58";
2672 function = "q 2671 function = "qup19";
2673 drive-strengt 2672 drive-strength = <2>;
2674 bias-disable; 2673 bias-disable;
2675 }; 2674 };
2676 2675
2677 qup_spi19_default: qu 2676 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio5 2677 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2678 function = "qup19";
2680 drive-strengt 2679 drive-strength = <6>;
2681 bias-disable; 2680 bias-disable;
2682 }; 2681 };
2683 2682
2684 pcie0_default_state: 2683 pcie0_default_state: pcie0-default-state {
2685 perst-pins { 2684 perst-pins {
2686 pins 2685 pins = "gpio35";
2687 funct 2686 function = "gpio";
2688 drive 2687 drive-strength = <2>;
2689 bias- 2688 bias-pull-down;
2690 }; 2689 };
2691 2690
2692 clkreq-pins { 2691 clkreq-pins {
2693 pins 2692 pins = "gpio36";
2694 funct 2693 function = "pci_e0";
2695 drive 2694 drive-strength = <2>;
2696 bias- 2695 bias-pull-up;
2697 }; 2696 };
2698 2697
2699 wake-pins { 2698 wake-pins {
2700 pins 2699 pins = "gpio37";
2701 funct 2700 function = "gpio";
2702 drive 2701 drive-strength = <2>;
2703 bias- 2702 bias-pull-up;
2704 }; 2703 };
2705 }; 2704 };
2706 2705
2707 pcie1_default_state: 2706 pcie1_default_state: pcie1-default-state {
2708 perst-pins { 2707 perst-pins {
2709 pins 2708 pins = "gpio102";
2710 funct 2709 function = "gpio";
2711 drive 2710 drive-strength = <2>;
2712 bias- 2711 bias-pull-down;
2713 }; 2712 };
2714 2713
2715 clkreq-pins { 2714 clkreq-pins {
2716 pins 2715 pins = "gpio103";
2717 funct 2716 function = "pci_e1";
2718 drive 2717 drive-strength = <2>;
2719 bias- 2718 bias-pull-up;
2720 }; 2719 };
2721 2720
2722 wake-pins { 2721 wake-pins {
2723 pins 2722 pins = "gpio104";
2724 funct 2723 function = "gpio";
2725 drive 2724 drive-strength = <2>;
2726 bias- 2725 bias-pull-up;
2727 }; 2726 };
2728 }; 2727 };
2729 }; 2728 };
2730 2729
2731 remoteproc_mpss: remoteproc@4 2730 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2731 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2732 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2733
2735 interrupts-extended = 2734 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2735 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2736 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2737 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2738 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2739 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2740 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2741 "stop-ack", "shutdown-ack";
2743 2742
2744 clocks = <&rpmhcc RPM 2743 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2744 clock-names = "xo";
2746 2745
2747 power-domains = <&rpm 2746 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpm 2747 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = 2748 power-domain-names = "cx", "mss";
2750 2749
2751 memory-region = <&mps 2750 memory-region = <&mpss_mem>;
2752 2751
2753 qcom,qmp = <&aoss_qmp 2752 qcom,qmp = <&aoss_qmp>;
2754 2753
2755 qcom,smem-states = <& 2754 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2755 qcom,smem-state-names = "stop";
2757 2756
2758 status = "disabled"; 2757 status = "disabled";
2759 2758
2760 glink-edge { 2759 glink-edge {
2761 interrupts = 2760 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2761 label = "modem";
2763 qcom,remote-p 2762 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2763 mboxes = <&apss_shared 12>;
2765 }; 2764 };
2766 }; 2765 };
2767 2766
2768 stm@6002000 { 2767 stm@6002000 {
2769 compatible = "arm,cor 2768 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2769 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2770 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2771 reg-names = "stm-base", "stm-stimulus-base";
2773 2772
2774 clocks = <&aoss_qmp>; 2773 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2774 clock-names = "apb_pclk";
2776 2775
2777 out-ports { 2776 out-ports {
2778 port { 2777 port {
2779 stm_o 2778 stm_out: endpoint {
2780 2779 remote-endpoint = <&funnel0_in7>;
2781 }; 2780 };
2782 }; 2781 };
2783 }; 2782 };
2784 }; 2783 };
2785 2784
2786 funnel@6041000 { 2785 funnel@6041000 {
2787 compatible = "arm,cor 2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2787 reg = <0 0x06041000 0 0x1000>;
2789 2788
2790 clocks = <&aoss_qmp>; 2789 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2790 clock-names = "apb_pclk";
2792 2791
2793 out-ports { 2792 out-ports {
2794 port { 2793 port {
2795 funne 2794 funnel0_out: endpoint {
2796 2795 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2796 };
2798 }; 2797 };
2799 }; 2798 };
2800 2799
2801 in-ports { 2800 in-ports {
2802 #address-cell 2801 #address-cells = <1>;
2803 #size-cells = 2802 #size-cells = <0>;
2804 2803
2805 port@7 { 2804 port@7 {
2806 reg = 2805 reg = <7>;
2807 funne 2806 funnel0_in7: endpoint {
2808 2807 remote-endpoint = <&stm_out>;
2809 }; 2808 };
2810 }; 2809 };
2811 }; 2810 };
2812 }; 2811 };
2813 2812
2814 funnel@6042000 { 2813 funnel@6042000 {
2815 compatible = "arm,cor 2814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2815 reg = <0 0x06042000 0 0x1000>;
2817 2816
2818 clocks = <&aoss_qmp>; 2817 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2818 clock-names = "apb_pclk";
2820 2819
2821 out-ports { 2820 out-ports {
2822 port { 2821 port {
2823 funne 2822 funnel1_out: endpoint {
2824 2823 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2824 };
2826 }; 2825 };
2827 }; 2826 };
2828 2827
2829 in-ports { 2828 in-ports {
2830 #address-cell 2829 #address-cells = <1>;
2831 #size-cells = 2830 #size-cells = <0>;
2832 2831
2833 port@4 { 2832 port@4 {
2834 reg = 2833 reg = <4>;
2835 funne 2834 funnel1_in4: endpoint {
2836 2835 remote-endpoint = <&swao_replicator_out>;
2837 }; 2836 };
2838 }; 2837 };
2839 }; 2838 };
2840 }; 2839 };
2841 2840
2842 funnel@6043000 { 2841 funnel@6043000 {
2843 compatible = "arm,cor 2842 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2843 reg = <0 0x06043000 0 0x1000>;
2845 2844
2846 clocks = <&aoss_qmp>; 2845 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2846 clock-names = "apb_pclk";
2848 2847
2849 out-ports { 2848 out-ports {
2850 port { 2849 port {
2851 funne 2850 funnel2_out: endpoint {
2852 2851 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2852 };
2854 }; 2853 };
2855 }; 2854 };
2856 2855
2857 in-ports { 2856 in-ports {
2858 #address-cell 2857 #address-cells = <1>;
2859 #size-cells = 2858 #size-cells = <0>;
2860 2859
2861 port@2 { 2860 port@2 {
2862 reg = 2861 reg = <2>;
2863 funne 2862 funnel2_in2: endpoint {
2864 2863 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2864 };
2866 }; 2865 };
2867 }; 2866 };
2868 }; 2867 };
2869 2868
2870 funnel@6045000 { 2869 funnel@6045000 {
2871 compatible = "arm,cor 2870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2871 reg = <0 0x06045000 0 0x1000>;
2873 2872
2874 clocks = <&aoss_qmp>; 2873 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2874 clock-names = "apb_pclk";
2876 2875
2877 out-ports { 2876 out-ports {
2878 port { 2877 port {
2879 merge 2878 merge_funnel_out: endpoint {
2880 2879 remote-endpoint = <&etf_in>;
2881 }; 2880 };
2882 }; 2881 };
2883 }; 2882 };
2884 2883
2885 in-ports { 2884 in-ports {
2886 #address-cell 2885 #address-cells = <1>;
2887 #size-cells = 2886 #size-cells = <0>;
2888 2887
2889 port@0 { 2888 port@0 {
2890 reg = 2889 reg = <0>;
2891 merge 2890 merge_funnel_in0: endpoint {
2892 2891 remote-endpoint = <&funnel0_out>;
2893 }; 2892 };
2894 }; 2893 };
2895 2894
2896 port@1 { 2895 port@1 {
2897 reg = 2896 reg = <1>;
2898 merge 2897 merge_funnel_in1: endpoint {
2899 2898 remote-endpoint = <&funnel1_out>;
2900 }; 2899 };
2901 }; 2900 };
2902 2901
2903 port@2 { 2902 port@2 {
2904 reg = 2903 reg = <2>;
2905 merge 2904 merge_funnel_in2: endpoint {
2906 2905 remote-endpoint = <&funnel2_out>;
2907 }; 2906 };
2908 }; 2907 };
2909 }; 2908 };
2910 }; 2909 };
2911 2910
2912 replicator@6046000 { 2911 replicator@6046000 {
2913 compatible = "arm,cor 2912 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2913 reg = <0 0x06046000 0 0x1000>;
2915 2914
2916 clocks = <&aoss_qmp>; 2915 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2916 clock-names = "apb_pclk";
2918 2917
2919 out-ports { 2918 out-ports {
2920 #address-cell 2919 #address-cells = <1>;
2921 #size-cells = 2920 #size-cells = <0>;
2922 2921
2923 port@0 { 2922 port@0 {
2924 reg = 2923 reg = <0>;
2925 repli 2924 replicator_out0: endpoint {
2926 2925 remote-endpoint = <&etr_in>;
2927 }; 2926 };
2928 }; 2927 };
2929 2928
2930 port@1 { 2929 port@1 {
2931 reg = 2930 reg = <1>;
2932 repli 2931 replicator_out1: endpoint {
2933 2932 remote-endpoint = <&replicator1_in>;
2934 }; 2933 };
2935 }; 2934 };
2936 }; 2935 };
2937 2936
2938 in-ports { 2937 in-ports {
2939 port { 2938 port {
2940 repli 2939 replicator_in0: endpoint {
2941 2940 remote-endpoint = <&etf_out>;
2942 }; 2941 };
2943 }; 2942 };
2944 }; 2943 };
2945 }; 2944 };
2946 2945
2947 etf@6047000 { 2946 etf@6047000 {
2948 compatible = "arm,cor 2947 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2948 reg = <0 0x06047000 0 0x1000>;
2950 2949
2951 clocks = <&aoss_qmp>; 2950 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2951 clock-names = "apb_pclk";
2953 2952
2954 out-ports { 2953 out-ports {
2955 port { 2954 port {
2956 etf_o 2955 etf_out: endpoint {
2957 2956 remote-endpoint = <&replicator_in0>;
2958 }; 2957 };
2959 }; 2958 };
2960 }; 2959 };
2961 2960
2962 in-ports { 2961 in-ports {
2963 port { 2962 port {
2964 etf_i 2963 etf_in: endpoint {
2965 2964 remote-endpoint = <&merge_funnel_out>;
2966 }; 2965 };
2967 }; 2966 };
2968 }; 2967 };
2969 }; 2968 };
2970 2969
2971 etr@6048000 { 2970 etr@6048000 {
2972 compatible = "arm,cor 2971 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2972 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2973 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2974
2976 clocks = <&aoss_qmp>; 2975 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2976 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2977 arm,scatter-gather;
2979 2978
2980 in-ports { 2979 in-ports {
2981 port { 2980 port {
2982 etr_i 2981 etr_in: endpoint {
2983 2982 remote-endpoint = <&replicator_out0>;
2984 }; 2983 };
2985 }; 2984 };
2986 }; 2985 };
2987 }; 2986 };
2988 2987
2989 replicator@604a000 { 2988 replicator@604a000 {
2990 compatible = "arm,cor 2989 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2990 reg = <0 0x0604a000 0 0x1000>;
2992 2991
2993 clocks = <&aoss_qmp>; 2992 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2993 clock-names = "apb_pclk";
2995 2994
2996 out-ports { 2995 out-ports {
2997 #address-cell 2996 #address-cells = <1>;
2998 #size-cells = 2997 #size-cells = <0>;
2999 2998
3000 port@1 { 2999 port@1 {
3001 reg = 3000 reg = <1>;
3002 repli 3001 replicator1_out: endpoint {
3003 3002 remote-endpoint = <&swao_funnel_in>;
3004 }; 3003 };
3005 }; 3004 };
3006 }; 3005 };
3007 3006
3008 in-ports { 3007 in-ports {
3009 3008
3010 port { 3009 port {
3011 repli 3010 replicator1_in: endpoint {
3012 3011 remote-endpoint = <&replicator_out1>;
3013 }; 3012 };
3014 }; 3013 };
3015 }; 3014 };
3016 }; 3015 };
3017 3016
3018 funnel@6b08000 { 3017 funnel@6b08000 {
3019 compatible = "arm,cor 3018 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 3019 reg = <0 0x06b08000 0 0x1000>;
3021 3020
3022 clocks = <&aoss_qmp>; 3021 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 3022 clock-names = "apb_pclk";
3024 3023
3025 out-ports { 3024 out-ports {
3026 port { 3025 port {
3027 swao_ 3026 swao_funnel_out: endpoint {
3028 3027 remote-endpoint = <&swao_etf_in>;
3029 }; 3028 };
3030 }; 3029 };
3031 }; 3030 };
3032 3031
3033 in-ports { 3032 in-ports {
3034 #address-cell 3033 #address-cells = <1>;
3035 #size-cells = 3034 #size-cells = <0>;
3036 3035
3037 port@6 { 3036 port@6 {
3038 reg = 3037 reg = <6>;
3039 swao_ 3038 swao_funnel_in: endpoint {
3040 3039 remote-endpoint = <&replicator1_out>;
3041 }; 3040 };
3042 }; 3041 };
3043 }; 3042 };
3044 }; 3043 };
3045 3044
3046 etf@6b09000 { 3045 etf@6b09000 {
3047 compatible = "arm,cor 3046 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 3047 reg = <0 0x06b09000 0 0x1000>;
3049 3048
3050 clocks = <&aoss_qmp>; 3049 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 3050 clock-names = "apb_pclk";
3052 3051
3053 out-ports { 3052 out-ports {
3054 port { 3053 port {
3055 swao_ 3054 swao_etf_out: endpoint {
3056 3055 remote-endpoint = <&swao_replicator_in>;
3057 }; 3056 };
3058 }; 3057 };
3059 }; 3058 };
3060 3059
3061 in-ports { 3060 in-ports {
3062 port { 3061 port {
3063 swao_ 3062 swao_etf_in: endpoint {
3064 3063 remote-endpoint = <&swao_funnel_out>;
3065 }; 3064 };
3066 }; 3065 };
3067 }; 3066 };
3068 }; 3067 };
3069 3068
3070 replicator@6b0a000 { 3069 replicator@6b0a000 {
3071 compatible = "arm,cor 3070 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 3071 reg = <0 0x06b0a000 0 0x1000>;
3073 3072
3074 clocks = <&aoss_qmp>; 3073 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 3074 clock-names = "apb_pclk";
3076 qcom,replicator-loses 3075 qcom,replicator-loses-context;
3077 3076
3078 out-ports { 3077 out-ports {
3079 port { 3078 port {
3080 swao_ 3079 swao_replicator_out: endpoint {
3081 3080 remote-endpoint = <&funnel1_in4>;
3082 }; 3081 };
3083 }; 3082 };
3084 }; 3083 };
3085 3084
3086 in-ports { 3085 in-ports {
3087 port { 3086 port {
3088 swao_ 3087 swao_replicator_in: endpoint {
3089 3088 remote-endpoint = <&swao_etf_out>;
3090 }; 3089 };
3091 }; 3090 };
3092 }; 3091 };
3093 }; 3092 };
3094 3093
3095 etm@7040000 { 3094 etm@7040000 {
3096 compatible = "arm,cor 3095 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 3096 reg = <0 0x07040000 0 0x1000>;
3098 3097
3099 cpu = <&CPU0>; 3098 cpu = <&CPU0>;
3100 3099
3101 clocks = <&aoss_qmp>; 3100 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 3101 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 3102 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 3103 qcom,skip-power-up;
3105 3104
3106 out-ports { 3105 out-ports {
3107 port { 3106 port {
3108 etm0_ 3107 etm0_out: endpoint {
3109 3108 remote-endpoint = <&apss_funnel_in0>;
3110 }; 3109 };
3111 }; 3110 };
3112 }; 3111 };
3113 }; 3112 };
3114 3113
3115 etm@7140000 { 3114 etm@7140000 {
3116 compatible = "arm,cor 3115 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 3116 reg = <0 0x07140000 0 0x1000>;
3118 3117
3119 cpu = <&CPU1>; 3118 cpu = <&CPU1>;
3120 3119
3121 clocks = <&aoss_qmp>; 3120 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3121 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3122 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3123 qcom,skip-power-up;
3125 3124
3126 out-ports { 3125 out-ports {
3127 port { 3126 port {
3128 etm1_ 3127 etm1_out: endpoint {
3129 3128 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3129 };
3131 }; 3130 };
3132 }; 3131 };
3133 }; 3132 };
3134 3133
3135 etm@7240000 { 3134 etm@7240000 {
3136 compatible = "arm,cor 3135 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3136 reg = <0 0x07240000 0 0x1000>;
3138 3137
3139 cpu = <&CPU2>; 3138 cpu = <&CPU2>;
3140 3139
3141 clocks = <&aoss_qmp>; 3140 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3141 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3142 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3143 qcom,skip-power-up;
3145 3144
3146 out-ports { 3145 out-ports {
3147 port { 3146 port {
3148 etm2_ 3147 etm2_out: endpoint {
3149 3148 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3149 };
3151 }; 3150 };
3152 }; 3151 };
3153 }; 3152 };
3154 3153
3155 etm@7340000 { 3154 etm@7340000 {
3156 compatible = "arm,cor 3155 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3156 reg = <0 0x07340000 0 0x1000>;
3158 3157
3159 cpu = <&CPU3>; 3158 cpu = <&CPU3>;
3160 3159
3161 clocks = <&aoss_qmp>; 3160 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3161 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3162 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3163 qcom,skip-power-up;
3165 3164
3166 out-ports { 3165 out-ports {
3167 port { 3166 port {
3168 etm3_ 3167 etm3_out: endpoint {
3169 3168 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3169 };
3171 }; 3170 };
3172 }; 3171 };
3173 }; 3172 };
3174 3173
3175 etm@7440000 { 3174 etm@7440000 {
3176 compatible = "arm,cor 3175 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3176 reg = <0 0x07440000 0 0x1000>;
3178 3177
3179 cpu = <&CPU4>; 3178 cpu = <&CPU4>;
3180 3179
3181 clocks = <&aoss_qmp>; 3180 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3181 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3182 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3183 qcom,skip-power-up;
3185 3184
3186 out-ports { 3185 out-ports {
3187 port { 3186 port {
3188 etm4_ 3187 etm4_out: endpoint {
3189 3188 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3189 };
3191 }; 3190 };
3192 }; 3191 };
3193 }; 3192 };
3194 3193
3195 etm@7540000 { 3194 etm@7540000 {
3196 compatible = "arm,cor 3195 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3196 reg = <0 0x07540000 0 0x1000>;
3198 3197
3199 cpu = <&CPU5>; 3198 cpu = <&CPU5>;
3200 3199
3201 clocks = <&aoss_qmp>; 3200 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3201 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3202 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3203 qcom,skip-power-up;
3205 3204
3206 out-ports { 3205 out-ports {
3207 port { 3206 port {
3208 etm5_ 3207 etm5_out: endpoint {
3209 3208 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3209 };
3211 }; 3210 };
3212 }; 3211 };
3213 }; 3212 };
3214 3213
3215 etm@7640000 { 3214 etm@7640000 {
3216 compatible = "arm,cor 3215 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3216 reg = <0 0x07640000 0 0x1000>;
3218 3217
3219 cpu = <&CPU6>; 3218 cpu = <&CPU6>;
3220 3219
3221 clocks = <&aoss_qmp>; 3220 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3221 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3222 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3223 qcom,skip-power-up;
3225 3224
3226 out-ports { 3225 out-ports {
3227 port { 3226 port {
3228 etm6_ 3227 etm6_out: endpoint {
3229 3228 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3229 };
3231 }; 3230 };
3232 }; 3231 };
3233 }; 3232 };
3234 3233
3235 etm@7740000 { 3234 etm@7740000 {
3236 compatible = "arm,cor 3235 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3236 reg = <0 0x07740000 0 0x1000>;
3238 3237
3239 cpu = <&CPU7>; 3238 cpu = <&CPU7>;
3240 3239
3241 clocks = <&aoss_qmp>; 3240 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3241 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3242 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3243 qcom,skip-power-up;
3245 3244
3246 out-ports { 3245 out-ports {
3247 port { 3246 port {
3248 etm7_ 3247 etm7_out: endpoint {
3249 3248 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3249 };
3251 }; 3250 };
3252 }; 3251 };
3253 }; 3252 };
3254 3253
3255 funnel@7800000 { /* APSS Funn 3254 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3256 reg = <0 0x07800000 0 0x1000>;
3258 3257
3259 clocks = <&aoss_qmp>; 3258 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3259 clock-names = "apb_pclk";
3261 3260
3262 out-ports { 3261 out-ports {
3263 port { 3262 port {
3264 apss_ 3263 apss_funnel_out: endpoint {
3265 3264 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3265 };
3267 }; 3266 };
3268 }; 3267 };
3269 3268
3270 in-ports { 3269 in-ports {
3271 #address-cell 3270 #address-cells = <1>;
3272 #size-cells = 3271 #size-cells = <0>;
3273 3272
3274 port@0 { 3273 port@0 {
3275 reg = 3274 reg = <0>;
3276 apss_ 3275 apss_funnel_in0: endpoint {
3277 3276 remote-endpoint = <&etm0_out>;
3278 }; 3277 };
3279 }; 3278 };
3280 3279
3281 port@1 { 3280 port@1 {
3282 reg = 3281 reg = <1>;
3283 apss_ 3282 apss_funnel_in1: endpoint {
3284 3283 remote-endpoint = <&etm1_out>;
3285 }; 3284 };
3286 }; 3285 };
3287 3286
3288 port@2 { 3287 port@2 {
3289 reg = 3288 reg = <2>;
3290 apss_ 3289 apss_funnel_in2: endpoint {
3291 3290 remote-endpoint = <&etm2_out>;
3292 }; 3291 };
3293 }; 3292 };
3294 3293
3295 port@3 { 3294 port@3 {
3296 reg = 3295 reg = <3>;
3297 apss_ 3296 apss_funnel_in3: endpoint {
3298 3297 remote-endpoint = <&etm3_out>;
3299 }; 3298 };
3300 }; 3299 };
3301 3300
3302 port@4 { 3301 port@4 {
3303 reg = 3302 reg = <4>;
3304 apss_ 3303 apss_funnel_in4: endpoint {
3305 3304 remote-endpoint = <&etm4_out>;
3306 }; 3305 };
3307 }; 3306 };
3308 3307
3309 port@5 { 3308 port@5 {
3310 reg = 3309 reg = <5>;
3311 apss_ 3310 apss_funnel_in5: endpoint {
3312 3311 remote-endpoint = <&etm5_out>;
3313 }; 3312 };
3314 }; 3313 };
3315 3314
3316 port@6 { 3315 port@6 {
3317 reg = 3316 reg = <6>;
3318 apss_ 3317 apss_funnel_in6: endpoint {
3319 3318 remote-endpoint = <&etm6_out>;
3320 }; 3319 };
3321 }; 3320 };
3322 3321
3323 port@7 { 3322 port@7 {
3324 reg = 3323 reg = <7>;
3325 apss_ 3324 apss_funnel_in7: endpoint {
3326 3325 remote-endpoint = <&etm7_out>;
3327 }; 3326 };
3328 }; 3327 };
3329 }; 3328 };
3330 }; 3329 };
3331 3330
3332 funnel@7810000 { 3331 funnel@7810000 {
3333 compatible = "arm,cor 3332 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3333 reg = <0 0x07810000 0 0x1000>;
3335 3334
3336 clocks = <&aoss_qmp>; 3335 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3336 clock-names = "apb_pclk";
3338 3337
3339 out-ports { 3338 out-ports {
3340 port { 3339 port {
3341 apss_ 3340 apss_merge_funnel_out: endpoint {
3342 3341 remote-endpoint = <&funnel2_in2>;
3343 }; 3342 };
3344 }; 3343 };
3345 }; 3344 };
3346 3345
3347 in-ports { 3346 in-ports {
3348 port { 3347 port {
3349 apss_ 3348 apss_merge_funnel_in: endpoint {
3350 3349 remote-endpoint = <&apss_funnel_out>;
3351 }; 3350 };
3352 }; 3351 };
3353 }; 3352 };
3354 }; 3353 };
3355 3354
3356 remoteproc_cdsp: remoteproc@8 3355 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3356 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3357 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3358
3360 interrupts-extended = 3359 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3360 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3361 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3362 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3363 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3364 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3365 "handover", "stop-ack";
3367 3366
3368 clocks = <&rpmhcc RPM 3367 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3368 clock-names = "xo";
3370 3369
3371 power-domains = <&rpm 3370 power-domains = <&rpmhpd SM8150_CX>;
3372 3371
3373 memory-region = <&cds 3372 memory-region = <&cdsp_mem>;
3374 3373
3375 qcom,qmp = <&aoss_qmp 3374 qcom,qmp = <&aoss_qmp>;
3376 3375
3377 qcom,smem-states = <& 3376 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3377 qcom,smem-state-names = "stop";
3379 3378
3380 status = "disabled"; 3379 status = "disabled";
3381 3380
3382 glink-edge { 3381 glink-edge {
3383 interrupts = 3382 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3383 label = "cdsp";
3385 qcom,remote-p 3384 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3385 mboxes = <&apss_shared 4>;
3387 3386
3388 fastrpc { 3387 fastrpc {
3389 compa 3388 compatible = "qcom,fastrpc";
3390 qcom, 3389 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3390 label = "cdsp";
3392 qcom, 3391 qcom,non-secure-domain;
3393 #addr 3392 #address-cells = <1>;
3394 #size 3393 #size-cells = <0>;
3395 3394
3396 compu 3395 compute-cb@1 {
3397 3396 compatible = "qcom,fastrpc-compute-cb";
3398 3397 reg = <1>;
3399 3398 iommus = <&apps_smmu 0x1001 0x0460>;
3400 }; 3399 };
3401 3400
3402 compu 3401 compute-cb@2 {
3403 3402 compatible = "qcom,fastrpc-compute-cb";
3404 3403 reg = <2>;
3405 3404 iommus = <&apps_smmu 0x1002 0x0460>;
3406 }; 3405 };
3407 3406
3408 compu 3407 compute-cb@3 {
3409 3408 compatible = "qcom,fastrpc-compute-cb";
3410 3409 reg = <3>;
3411 3410 iommus = <&apps_smmu 0x1003 0x0460>;
3412 }; 3411 };
3413 3412
3414 compu 3413 compute-cb@4 {
3415 3414 compatible = "qcom,fastrpc-compute-cb";
3416 3415 reg = <4>;
3417 3416 iommus = <&apps_smmu 0x1004 0x0460>;
3418 }; 3417 };
3419 3418
3420 compu 3419 compute-cb@5 {
3421 3420 compatible = "qcom,fastrpc-compute-cb";
3422 3421 reg = <5>;
3423 3422 iommus = <&apps_smmu 0x1005 0x0460>;
3424 }; 3423 };
3425 3424
3426 compu 3425 compute-cb@6 {
3427 3426 compatible = "qcom,fastrpc-compute-cb";
3428 3427 reg = <6>;
3429 3428 iommus = <&apps_smmu 0x1006 0x0460>;
3430 }; 3429 };
3431 3430
3432 compu 3431 compute-cb@7 {
3433 3432 compatible = "qcom,fastrpc-compute-cb";
3434 3433 reg = <7>;
3435 3434 iommus = <&apps_smmu 0x1007 0x0460>;
3436 }; 3435 };
3437 3436
3438 compu 3437 compute-cb@8 {
3439 3438 compatible = "qcom,fastrpc-compute-cb";
3440 3439 reg = <8>;
3441 3440 iommus = <&apps_smmu 0x1008 0x0460>;
3442 }; 3441 };
3443 3442
3444 /* no 3443 /* note: secure cb9 in downstream */
3445 }; 3444 };
3446 }; 3445 };
3447 }; 3446 };
3448 3447
3449 usb_1_hsphy: phy@88e2000 { 3448 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3449 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3450 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3451 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3452 status = "disabled";
3454 #phy-cells = <0>; 3453 #phy-cells = <0>;
3455 3454
3456 clocks = <&rpmhcc RPM 3455 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3456 clock-names = "ref";
3458 3457
3459 resets = <&gcc GCC_QU 3458 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3459 };
3461 3460
3462 usb_2_hsphy: phy@88e3000 { 3461 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3462 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3463 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3464 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3465 status = "disabled";
3467 #phy-cells = <0>; 3466 #phy-cells = <0>;
3468 3467
3469 clocks = <&rpmhcc RPM 3468 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3469 clock-names = "ref";
3471 3470
3472 resets = <&gcc GCC_QU 3471 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3472 };
3474 3473
3475 usb_1_qmpphy: phy@88e8000 { 3474 usb_1_qmpphy: phy@88e8000 {
3476 compatible = "qcom,sm 3475 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3477 reg = <0 0x088e8000 0 3476 reg = <0 0x088e8000 0 0x3000>;
3478 3477
3479 clocks = <&gcc GCC_US 3478 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3480 <&gcc GCC_US 3479 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US 3480 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3482 <&gcc GCC_US 3481 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3483 clock-names = "aux", 3482 clock-names = "aux",
3484 "ref", 3483 "ref",
3485 "com_au 3484 "com_aux",
3486 "usb3_p 3485 "usb3_pipe";
3487 3486
3488 resets = <&gcc GCC_US 3487 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3488 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3489 reset-names = "phy", "common";
3491 3490
3492 #clock-cells = <1>; 3491 #clock-cells = <1>;
3493 #phy-cells = <1>; 3492 #phy-cells = <1>;
3494 3493
3495 status = "disabled"; 3494 status = "disabled";
3496 3495
3497 ports { 3496 ports {
3498 #address-cell 3497 #address-cells = <1>;
3499 #size-cells = 3498 #size-cells = <0>;
3500 3499
3501 port@0 { 3500 port@0 {
3502 reg = 3501 reg = <0>;
3503 3502
3504 usb_1 3503 usb_1_qmpphy_out: endpoint {
3505 }; 3504 };
3506 }; 3505 };
3507 3506
3508 port@1 { 3507 port@1 {
3509 reg = 3508 reg = <1>;
3510 3509
3511 usb_1 3510 usb_1_qmpphy_usb_ss_in: endpoint {
3512 3511 remote-endpoint = <&usb_1_dwc3_ss>;
3513 }; 3512 };
3514 }; 3513 };
3515 3514
3516 port@2 { 3515 port@2 {
3517 reg = 3516 reg = <2>;
3518 3517
3519 usb_1 3518 usb_1_qmpphy_dp_in: endpoint {
3520 3519 remote-endpoint = <&mdss_dp_out>;
3521 }; 3520 };
3522 }; 3521 };
3523 }; 3522 };
3524 }; 3523 };
3525 3524
3526 usb_2_qmpphy: phy@88eb000 { 3525 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3526 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 3527 reg = <0 0x088eb000 0 0x1000>;
3529 3528
3530 clocks = <&gcc GCC_US 3529 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3531 <&gcc GCC_US 3530 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US 3531 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3533 <&gcc GCC_US 3532 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3534 clock-names = "aux", 3533 clock-names = "aux",
3535 "ref", 3534 "ref",
3536 "com_au 3535 "com_aux",
3537 "pipe"; 3536 "pipe";
3538 clock-output-names = 3537 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3539 #clock-cells = <0>; 3538 #clock-cells = <0>;
3540 #phy-cells = <0>; 3539 #phy-cells = <0>;
3541 3540
3542 resets = <&gcc GCC_US 3541 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3543 <&gcc GCC_US 3542 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3544 reset-names = "phy", 3543 reset-names = "phy",
3545 "phy_ph 3544 "phy_phy";
3546 3545
3547 status = "disabled"; 3546 status = "disabled";
3548 }; 3547 };
3549 3548
3550 sdhc_2: mmc@8804000 { 3549 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm 3550 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3551 reg = <0 0x08804000 0 0x1000>;
3553 3552
3554 interrupts = <GIC_SPI 3553 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3554 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3555 interrupt-names = "hc_irq", "pwr_irq";
3557 3556
3558 clocks = <&gcc GCC_SD 3557 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3558 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3559 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3560 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3561 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3562 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3563 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3564 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3565 operating-points-v2 = <&sdhc2_opp_table>;
3567 3566
3568 status = "disabled"; 3567 status = "disabled";
3569 3568
3570 sdhc2_opp_table: opp- 3569 sdhc2_opp_table: opp-table {
3571 compatible = 3570 compatible = "operating-points-v2";
3572 3571
3573 opp-19200000 3572 opp-19200000 {
3574 opp-h 3573 opp-hz = /bits/ 64 <19200000>;
3575 requi 3574 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3575 };
3577 3576
3578 opp-50000000 3577 opp-50000000 {
3579 opp-h 3578 opp-hz = /bits/ 64 <50000000>;
3580 requi 3579 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3580 };
3582 3581
3583 opp-100000000 3582 opp-100000000 {
3584 opp-h 3583 opp-hz = /bits/ 64 <100000000>;
3585 requi 3584 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3585 };
3587 3586
3588 opp-202000000 3587 opp-202000000 {
3589 opp-h 3588 opp-hz = /bits/ 64 <202000000>;
3590 requi 3589 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3590 };
3592 }; 3591 };
3593 }; 3592 };
3594 3593
3595 dc_noc: interconnect@9160000 3594 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3595 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3596 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = 3597 #interconnect-cells = <2>;
3599 qcom,bcm-voters = <&a 3598 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3599 };
3601 3600
3602 gem_noc: interconnect@9680000 3601 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3602 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3603 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = 3604 #interconnect-cells = <2>;
3606 qcom,bcm-voters = <&a 3605 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3606 };
3608 3607
3609 usb_1: usb@a6f8800 { 3608 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3609 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3610 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3611 status = "disabled";
3613 #address-cells = <2>; 3612 #address-cells = <2>;
3614 #size-cells = <2>; 3613 #size-cells = <2>;
3615 ranges; 3614 ranges;
3616 dma-ranges; 3615 dma-ranges;
3617 3616
3618 clocks = <&gcc GCC_CF 3617 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3618 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3619 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3620 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3621 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3622 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3623 clock-names = "cfg_noc",
3625 "core", 3624 "core",
3626 "iface" 3625 "iface",
3627 "sleep" 3626 "sleep",
3628 "mock_u 3627 "mock_utmi",
3629 "xo"; 3628 "xo";
3630 3629
3631 assigned-clocks = <&g 3630 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3631 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3632 assigned-clock-rates = <19200000>, <200000000>;
3634 3633
3635 interrupts-extended = 3634 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3636 3635 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3637 3636 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
3638 3637 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3639 3638 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
3640 interrupt-names = "pw 3639 interrupt-names = "pwr_event",
3641 "hs 3640 "hs_phy_irq",
3642 "dp 3641 "dp_hs_phy_irq",
3643 "dm 3642 "dm_hs_phy_irq",
3644 "ss 3643 "ss_phy_irq";
3645 3644
3646 power-domains = <&gcc 3645 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3646
3648 resets = <&gcc GCC_US 3647 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3648
3650 interconnects = <&agg 3649 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3651 <&gem 3650 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3652 interconnect-names = 3651 interconnect-names = "usb-ddr", "apps-usb";
3653 3652
3654 usb_1_dwc3: usb@a6000 3653 usb_1_dwc3: usb@a600000 {
3655 compatible = 3654 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3655 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3656 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3657 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3658 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3659 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ 3660 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3662 phy-names = " 3661 phy-names = "usb2-phy", "usb3-phy";
3663 3662
3664 ports { 3663 ports {
3665 #addr 3664 #address-cells = <1>;
3666 #size 3665 #size-cells = <0>;
3667 3666
3668 port@ 3667 port@0 {
3669 3668 reg = <0>;
3670 3669
3671 3670 usb_1_dwc3_hs: endpoint {
3672 3671 };
3673 }; 3672 };
3674 3673
3675 port@ 3674 port@1 {
3676 3675 reg = <1>;
3677 3676
3678 3677 usb_1_dwc3_ss: endpoint {
3679 3678 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
3680 3679 };
3681 }; 3680 };
3682 }; 3681 };
3683 }; 3682 };
3684 }; 3683 };
3685 3684
3686 usb_2: usb@a8f8800 { 3685 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3686 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3687 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3688 status = "disabled";
3690 #address-cells = <2>; 3689 #address-cells = <2>;
3691 #size-cells = <2>; 3690 #size-cells = <2>;
3692 ranges; 3691 ranges;
3693 dma-ranges; 3692 dma-ranges;
3694 3693
3695 clocks = <&gcc GCC_CF 3694 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3695 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3696 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3697 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3698 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3699 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3700 clock-names = "cfg_noc",
3702 "core", 3701 "core",
3703 "iface" 3702 "iface",
3704 "sleep" 3703 "sleep",
3705 "mock_u 3704 "mock_utmi",
3706 "xo"; 3705 "xo";
3707 3706
3708 assigned-clocks = <&g 3707 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3708 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3709 assigned-clock-rates = <19200000>, <200000000>;
3711 3710
3712 interrupts-extended = 3711 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
3713 3712 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3714 3713 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
3715 3714 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3716 3715 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>;
3717 interrupt-names = "pw 3716 interrupt-names = "pwr_event",
3718 "hs 3717 "hs_phy_irq",
3719 "dp 3718 "dp_hs_phy_irq",
3720 "dm 3719 "dm_hs_phy_irq",
3721 "ss 3720 "ss_phy_irq";
3722 3721
3723 power-domains = <&gcc 3722 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3723
3725 resets = <&gcc GCC_US 3724 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3725
3727 interconnects = <&agg 3726 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3728 <&gem 3727 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3729 interconnect-names = 3728 interconnect-names = "usb-ddr", "apps-usb";
3730 3729
3731 usb_2_dwc3: usb@a8000 3730 usb_2_dwc3: usb@a800000 {
3732 compatible = 3731 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3732 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3733 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3734 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3735 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3736 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ 3737 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
3739 phy-names = " 3738 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3739 };
3741 }; 3740 };
3742 3741
3743 videocc: clock-controller@ab0 3742 videocc: clock-controller@ab00000 {
3744 compatible = "qcom,sm 3743 compatible = "qcom,sm8150-videocc";
3745 reg = <0 0x0ab00000 0 3744 reg = <0 0x0ab00000 0 0x10000>;
3746 clocks = <&gcc GCC_VI 3745 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
3747 <&rpmhcc RPM 3746 <&rpmhcc RPMH_CXO_CLK>;
3748 clock-names = "iface" 3747 clock-names = "iface", "bi_tcxo";
3749 power-domains = <&rpm 3748 power-domains = <&rpmhpd SM8150_MMCX>;
3750 required-opps = <&rpm 3749 required-opps = <&rpmhpd_opp_low_svs>;
3751 #clock-cells = <1>; 3750 #clock-cells = <1>;
3752 #reset-cells = <1>; 3751 #reset-cells = <1>;
3753 #power-domain-cells = 3752 #power-domain-cells = <1>;
3754 }; 3753 };
3755 3754
3756 camnoc_virt: interconnect@ac0 3755 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3756 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3757 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = 3758 #interconnect-cells = <2>;
3760 qcom,bcm-voters = <&a 3759 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; <<
3762 <<
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; 3760 };
3774 3761
3775 mdss: display-subsystem@ae000 3762 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm 3763 compatible = "qcom,sm8150-mdss";
3777 reg = <0 0x0ae00000 0 3764 reg = <0 0x0ae00000 0 0x1000>;
3778 reg-names = "mdss"; 3765 reg-names = "mdss";
3779 3766
3780 interconnects = <&mms 3767 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3781 <&mms 3768 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3782 interconnect-names = 3769 interconnect-names = "mdp0-mem", "mdp1-mem";
3783 3770
3784 power-domains = <&dis 3771 power-domains = <&dispcc MDSS_GDSC>;
3785 3772
3786 clocks = <&dispcc DIS 3773 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 <&gcc GCC_DI 3774 <&gcc GCC_DISP_HF_AXI_CLK>,
3788 <&gcc GCC_DI 3775 <&gcc GCC_DISP_SF_AXI_CLK>,
3789 <&dispcc DIS 3776 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3790 clock-names = "iface" 3777 clock-names = "iface", "bus", "nrt_bus", "core";
3791 3778
3792 interrupts = <GIC_SPI 3779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller; 3780 interrupt-controller;
3794 #interrupt-cells = <1 3781 #interrupt-cells = <1>;
3795 3782
3796 iommus = <&apps_smmu 3783 iommus = <&apps_smmu 0x800 0x420>;
3797 3784
3798 status = "disabled"; 3785 status = "disabled";
3799 3786
3800 #address-cells = <2>; 3787 #address-cells = <2>;
3801 #size-cells = <2>; 3788 #size-cells = <2>;
3802 ranges; 3789 ranges;
3803 3790
3804 mdss_mdp: display-con 3791 mdss_mdp: display-controller@ae01000 {
3805 compatible = 3792 compatible = "qcom,sm8150-dpu";
3806 reg = <0 0x0a 3793 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0a 3794 <0 0x0aeb0000 0 0x2008>;
3808 reg-names = " 3795 reg-names = "mdp", "vbif";
3809 3796
3810 clocks = <&di 3797 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3811 <&gc 3798 <&gcc GCC_DISP_HF_AXI_CLK>,
3812 <&di 3799 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3813 <&di 3800 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3814 clock-names = 3801 clock-names = "iface", "bus", "core", "vsync";
3815 3802
3816 assigned-cloc 3803 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-cloc 3804 assigned-clock-rates = <19200000>;
3818 3805
3819 operating-poi 3806 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains 3807 power-domains = <&rpmhpd SM8150_MMCX>;
3821 3808
3822 interrupt-par 3809 interrupt-parent = <&mdss>;
3823 interrupts = 3810 interrupts = <0>;
3824 3811
3825 ports { 3812 ports {
3826 #addr 3813 #address-cells = <1>;
3827 #size 3814 #size-cells = <0>;
3828 3815
3829 port@ 3816 port@0 {
3830 3817 reg = <0>;
3831 3818 dpu_intf1_out: endpoint {
3832 3819 remote-endpoint = <&mdss_dsi0_in>;
3833 3820 };
3834 }; 3821 };
3835 3822
3836 port@ 3823 port@1 {
3837 3824 reg = <1>;
3838 3825 dpu_intf2_out: endpoint {
3839 3826 remote-endpoint = <&mdss_dsi1_in>;
3840 3827 };
3841 }; 3828 };
3842 3829
3843 port@ 3830 port@2 {
3844 3831 reg = <2>;
3845 3832 dpu_intf0_out: endpoint {
3846 3833 remote-endpoint = <&mdss_dp_in>;
3847 3834 };
3848 }; 3835 };
3849 }; 3836 };
3850 3837
3851 mdp_opp_table 3838 mdp_opp_table: opp-table {
3852 compa 3839 compatible = "operating-points-v2";
3853 3840
3854 opp-1 3841 opp-171428571 {
3855 3842 opp-hz = /bits/ 64 <171428571>;
3856 3843 required-opps = <&rpmhpd_opp_low_svs>;
3857 }; 3844 };
3858 3845
3859 opp-3 3846 opp-300000000 {
3860 3847 opp-hz = /bits/ 64 <300000000>;
3861 3848 required-opps = <&rpmhpd_opp_svs>;
3862 }; 3849 };
3863 3850
3864 opp-3 3851 opp-345000000 {
3865 3852 opp-hz = /bits/ 64 <345000000>;
3866 3853 required-opps = <&rpmhpd_opp_svs_l1>;
3867 }; 3854 };
3868 3855
3869 opp-4 3856 opp-460000000 {
3870 3857 opp-hz = /bits/ 64 <460000000>;
3871 3858 required-opps = <&rpmhpd_opp_nom>;
3872 }; 3859 };
3873 }; 3860 };
3874 }; 3861 };
3875 3862
3876 mdss_dp: displayport- 3863 mdss_dp: displayport-controller@ae90000 {
3877 compatible = 3864 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3878 reg = <0 0xae 3865 reg = <0 0xae90000 0 0x200>,
3879 <0 0xae 3866 <0 0xae90200 0 0x200>,
3880 <0 0xae 3867 <0 0xae90400 0 0x600>,
3881 <0 0x0a 3868 <0 0x0ae90a00 0 0x600>,
3882 <0 0x0a 3869 <0 0x0ae91000 0 0x600>;
3883 3870
3884 interrupt-par 3871 interrupt-parent = <&mdss>;
3885 interrupts = 3872 interrupts = <12>;
3886 clocks = <&di 3873 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3887 <&di 3874 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3888 <&di 3875 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3889 <&di 3876 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3890 <&di 3877 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3891 clock-names = 3878 clock-names = "core_iface",
3892 3879 "core_aux",
3893 3880 "ctrl_link",
3894 3881 "ctrl_link_iface",
3895 3882 "stream_pixel";
3896 3883
3897 assigned-cloc 3884 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3898 3885 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3899 assigned-cloc 3886 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3900 3887 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3901 3888
3902 phys = <&usb_ 3889 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3903 phy-names = " 3890 phy-names = "dp";
3904 3891
3905 #sound-dai-ce 3892 #sound-dai-cells = <0>;
3906 3893
3907 operating-poi 3894 operating-points-v2 = <&dp_opp_table>;
3908 power-domains 3895 power-domains = <&rpmhpd SM8250_MMCX>;
3909 3896
3910 status = "dis 3897 status = "disabled";
3911 3898
3912 ports { 3899 ports {
3913 #addr 3900 #address-cells = <1>;
3914 #size 3901 #size-cells = <0>;
3915 3902
3916 port@ 3903 port@0 {
3917 3904 reg = <0>;
3918 3905 mdss_dp_in: endpoint {
3919 3906 remote-endpoint = <&dpu_intf0_out>;
3920 3907 };
3921 }; 3908 };
3922 3909
3923 port@ 3910 port@1 {
3924 3911 reg = <1>;
3925 3912
3926 3913 mdss_dp_out: endpoint {
3927 3914 remote-endpoint = <&usb_1_qmpphy_dp_in>;
3928 3915 };
3929 }; 3916 };
3930 }; 3917 };
3931 3918
3932 dp_opp_table: 3919 dp_opp_table: opp-table {
3933 compa 3920 compatible = "operating-points-v2";
3934 3921
3935 opp-1 3922 opp-160000000 {
3936 3923 opp-hz = /bits/ 64 <160000000>;
3937 3924 required-opps = <&rpmhpd_opp_low_svs>;
3938 }; 3925 };
3939 3926
3940 opp-2 3927 opp-270000000 {
3941 3928 opp-hz = /bits/ 64 <270000000>;
3942 3929 required-opps = <&rpmhpd_opp_svs>;
3943 }; 3930 };
3944 3931
3945 opp-5 3932 opp-540000000 {
3946 3933 opp-hz = /bits/ 64 <540000000>;
3947 3934 required-opps = <&rpmhpd_opp_svs_l1>;
3948 }; 3935 };
3949 3936
3950 opp-8 3937 opp-810000000 {
3951 3938 opp-hz = /bits/ 64 <810000000>;
3952 3939 required-opps = <&rpmhpd_opp_nom>;
3953 }; 3940 };
3954 }; 3941 };
3955 }; 3942 };
3956 3943
3957 mdss_dsi0: dsi@ae9400 3944 mdss_dsi0: dsi@ae94000 {
3958 compatible = 3945 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg = <0 0x0a 3946 reg = <0 0x0ae94000 0 0x400>;
3960 reg-names = " 3947 reg-names = "dsi_ctrl";
3961 3948
3962 interrupt-par 3949 interrupt-parent = <&mdss>;
3963 interrupts = 3950 interrupts = <4>;
3964 3951
3965 clocks = <&di 3952 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3966 <&di 3953 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3967 <&di 3954 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3968 <&di 3955 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3969 <&di 3956 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3970 <&gc 3957 <&gcc GCC_DISP_HF_AXI_CLK>;
3971 clock-names = 3958 clock-names = "byte",
3972 3959 "byte_intf",
3973 3960 "pixel",
3974 3961 "core",
3975 3962 "iface",
3976 3963 "bus";
3977 3964
3978 assigned-cloc 3965 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3979 3966 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3980 assigned-cloc 3967 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3981 3968 <&mdss_dsi0_phy 1>;
3982 3969
3983 operating-poi 3970 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains 3971 power-domains = <&rpmhpd SM8150_MMCX>;
3985 3972
3986 phys = <&mdss 3973 phys = <&mdss_dsi0_phy>;
3987 3974
3988 status = "dis 3975 status = "disabled";
3989 3976
3990 #address-cell 3977 #address-cells = <1>;
3991 #size-cells = 3978 #size-cells = <0>;
3992 3979
3993 ports { 3980 ports {
3994 #addr 3981 #address-cells = <1>;
3995 #size 3982 #size-cells = <0>;
3996 3983
3997 port@ 3984 port@0 {
3998 3985 reg = <0>;
3999 3986 mdss_dsi0_in: endpoint {
4000 3987 remote-endpoint = <&dpu_intf1_out>;
4001 3988 };
4002 }; 3989 };
4003 3990
4004 port@ 3991 port@1 {
4005 3992 reg = <1>;
4006 3993 mdss_dsi0_out: endpoint {
4007 3994 };
4008 }; 3995 };
4009 }; 3996 };
4010 3997
4011 dsi_opp_table 3998 dsi_opp_table: opp-table {
4012 compa 3999 compatible = "operating-points-v2";
4013 4000
4014 opp-1 4001 opp-187500000 {
4015 4002 opp-hz = /bits/ 64 <187500000>;
4016 4003 required-opps = <&rpmhpd_opp_low_svs>;
4017 }; 4004 };
4018 4005
4019 opp-3 4006 opp-300000000 {
4020 4007 opp-hz = /bits/ 64 <300000000>;
4021 4008 required-opps = <&rpmhpd_opp_svs>;
4022 }; 4009 };
4023 4010
4024 opp-3 4011 opp-358000000 {
4025 4012 opp-hz = /bits/ 64 <358000000>;
4026 4013 required-opps = <&rpmhpd_opp_svs_l1>;
4027 }; 4014 };
4028 }; 4015 };
4029 }; 4016 };
4030 4017
4031 mdss_dsi0_phy: phy@ae 4018 mdss_dsi0_phy: phy@ae94400 {
4032 compatible = 4019 compatible = "qcom,dsi-phy-7nm-8150";
4033 reg = <0 0x0a 4020 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0a 4021 <0 0x0ae94600 0 0x280>,
4035 <0 0x0a 4022 <0 0x0ae94900 0 0x260>;
4036 reg-names = " 4023 reg-names = "dsi_phy",
4037 " 4024 "dsi_phy_lane",
4038 " 4025 "dsi_pll";
4039 4026
4040 #clock-cells 4027 #clock-cells = <1>;
4041 #phy-cells = 4028 #phy-cells = <0>;
4042 4029
4043 clocks = <&di 4030 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4044 <&rp 4031 <&rpmhcc RPMH_CXO_CLK>;
4045 clock-names = 4032 clock-names = "iface", "ref";
4046 4033
4047 status = "dis 4034 status = "disabled";
4048 }; 4035 };
4049 4036
4050 mdss_dsi1: dsi@ae9600 4037 mdss_dsi1: dsi@ae96000 {
4051 compatible = 4038 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4052 reg = <0 0x0a 4039 reg = <0 0x0ae96000 0 0x400>;
4053 reg-names = " 4040 reg-names = "dsi_ctrl";
4054 4041
4055 interrupt-par 4042 interrupt-parent = <&mdss>;
4056 interrupts = 4043 interrupts = <5>;
4057 4044
4058 clocks = <&di 4045 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4059 <&di 4046 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4060 <&di 4047 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4061 <&di 4048 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4062 <&di 4049 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4063 <&gc 4050 <&gcc GCC_DISP_HF_AXI_CLK>;
4064 clock-names = 4051 clock-names = "byte",
4065 4052 "byte_intf",
4066 4053 "pixel",
4067 4054 "core",
4068 4055 "iface",
4069 4056 "bus";
4070 4057
4071 assigned-cloc 4058 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4072 4059 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4073 assigned-cloc 4060 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4074 4061 <&mdss_dsi1_phy 1>;
4075 4062
4076 operating-poi 4063 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains 4064 power-domains = <&rpmhpd SM8150_MMCX>;
4078 4065
4079 phys = <&mdss 4066 phys = <&mdss_dsi1_phy>;
4080 4067
4081 status = "dis 4068 status = "disabled";
4082 4069
4083 #address-cell 4070 #address-cells = <1>;
4084 #size-cells = 4071 #size-cells = <0>;
4085 4072
4086 ports { 4073 ports {
4087 #addr 4074 #address-cells = <1>;
4088 #size 4075 #size-cells = <0>;
4089 4076
4090 port@ 4077 port@0 {
4091 4078 reg = <0>;
4092 4079 mdss_dsi1_in: endpoint {
4093 4080 remote-endpoint = <&dpu_intf2_out>;
4094 4081 };
4095 }; 4082 };
4096 4083
4097 port@ 4084 port@1 {
4098 4085 reg = <1>;
4099 4086 mdss_dsi1_out: endpoint {
4100 4087 };
4101 }; 4088 };
4102 }; 4089 };
4103 }; 4090 };
4104 4091
4105 mdss_dsi1_phy: phy@ae 4092 mdss_dsi1_phy: phy@ae96400 {
4106 compatible = 4093 compatible = "qcom,dsi-phy-7nm-8150";
4107 reg = <0 0x0a 4094 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0a 4095 <0 0x0ae96600 0 0x280>,
4109 <0 0x0a 4096 <0 0x0ae96900 0 0x260>;
4110 reg-names = " 4097 reg-names = "dsi_phy",
4111 " 4098 "dsi_phy_lane",
4112 " 4099 "dsi_pll";
4113 4100
4114 #clock-cells 4101 #clock-cells = <1>;
4115 #phy-cells = 4102 #phy-cells = <0>;
4116 4103
4117 clocks = <&di 4104 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4118 <&rp 4105 <&rpmhcc RPMH_CXO_CLK>;
4119 clock-names = 4106 clock-names = "iface", "ref";
4120 4107
4121 status = "dis 4108 status = "disabled";
4122 }; 4109 };
4123 }; 4110 };
4124 4111
4125 dispcc: clock-controller@af00 4112 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm 4113 compatible = "qcom,sm8150-dispcc";
4127 reg = <0 0x0af00000 0 4114 reg = <0 0x0af00000 0 0x10000>;
4128 clocks = <&rpmhcc RPM 4115 clocks = <&rpmhcc RPMH_CXO_CLK>,
4129 <&mdss_dsi0_ 4116 <&mdss_dsi0_phy 0>,
4130 <&mdss_dsi0_ 4117 <&mdss_dsi0_phy 1>,
4131 <&mdss_dsi1_ 4118 <&mdss_dsi1_phy 0>,
4132 <&mdss_dsi1_ 4119 <&mdss_dsi1_phy 1>,
4133 <&usb_1_qmpp 4120 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4134 <&usb_1_qmpp 4121 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4135 clock-names = "bi_tcx 4122 clock-names = "bi_tcxo",
4136 "dsi0_p 4123 "dsi0_phy_pll_out_byteclk",
4137 "dsi0_p 4124 "dsi0_phy_pll_out_dsiclk",
4138 "dsi1_p 4125 "dsi1_phy_pll_out_byteclk",
4139 "dsi1_p 4126 "dsi1_phy_pll_out_dsiclk",
4140 "dp_phy 4127 "dp_phy_pll_link_clk",
4141 "dp_phy 4128 "dp_phy_pll_vco_div_clk";
4142 power-domains = <&rpm 4129 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpm 4130 required-opps = <&rpmhpd_opp_low_svs>;
4144 #clock-cells = <1>; 4131 #clock-cells = <1>;
4145 #reset-cells = <1>; 4132 #reset-cells = <1>;
4146 #power-domain-cells = 4133 #power-domain-cells = <1>;
4147 }; 4134 };
4148 4135
4149 pdc: interrupt-controller@b22 4136 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 4137 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 4138 reg = <0 0x0b220000 0 0x30000>;
4152 qcom,pdc-ranges = <0 4139 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 4140 <125 63 1>;
4154 #interrupt-cells = <2 4141 #interrupt-cells = <2>;
4155 interrupt-parent = <& 4142 interrupt-parent = <&intc>;
4156 interrupt-controller; 4143 interrupt-controller;
4157 }; 4144 };
4158 4145
4159 aoss_qmp: power-management@c3 4146 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm 4147 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 4148 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 4149 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 4150 mboxes = <&apss_shared 0>;
4164 4151
4165 #clock-cells = <0>; 4152 #clock-cells = <0>;
4166 }; 4153 };
4167 4154
4168 sram@c3f0000 { 4155 sram@c3f0000 {
4169 compatible = "qcom,rp 4156 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 4157 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 4158 };
4172 4159
4173 tsens0: thermal-sensor@c26300 4160 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 4161 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 4162 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 4163 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 4164 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 4165 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 4166 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 4167 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 4168 #thermal-sensor-cells = <1>;
4182 }; 4169 };
4183 4170
4184 tsens1: thermal-sensor@c26500 4171 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 4172 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 4173 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 4174 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 4175 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 4176 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 4177 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 4178 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 4179 #thermal-sensor-cells = <1>;
4193 }; 4180 };
4194 4181
4195 spmi_bus: spmi@c440000 { 4182 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 4183 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 4184 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 4185 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 4186 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 4187 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 4188 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 4189 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 4190 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 4191 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 4192 qcom,ee = <0>;
4206 qcom,channel = <0>; 4193 qcom,channel = <0>;
4207 #address-cells = <2>; 4194 #address-cells = <2>;
4208 #size-cells = <0>; 4195 #size-cells = <0>;
4209 interrupt-controller; 4196 interrupt-controller;
4210 #interrupt-cells = <4 4197 #interrupt-cells = <4>;
4211 }; 4198 };
4212 4199
4213 apps_smmu: iommu@15000000 { 4200 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm 4201 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 4202 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 4203 #iommu-cells = <2>;
4217 #global-interrupts = 4204 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 4205 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 4206 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 4207 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 4208 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 4209 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 4210 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 4211 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 4212 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 4213 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 4214 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 4215 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4216 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 4217 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 4218 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 4219 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 4220 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 4221 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 4222 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 4223 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4224 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 4225 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 4226 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 4227 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 4228 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 4229 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 4230 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 4231 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 4232 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 4233 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 4234 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 4235 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 4236 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 4237 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 4238 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 4239 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 4240 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 4241 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 4242 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 4243 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 4244 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 4245 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 4246 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 4247 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 4248 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 4249 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 4250 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 4251 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 4252 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 4253 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 4254 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 4255 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 4256 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 4257 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 4258 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 4259 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 4260 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 4261 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 4262 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 4263 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 4264 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 4265 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 4266 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 4267 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 4268 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 4269 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 4270 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 4271 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 4272 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 4273 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 4274 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 4275 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 4276 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 4277 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 4278 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 4279 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 4280 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 4281 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 4282 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 4283 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 4284 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 4285 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 4286 };
4300 4287
4301 remoteproc_adsp: remoteproc@1 4288 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 4289 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 4290 reg = <0x0 0x17300000 0x0 0x4040>;
4304 4291
4305 interrupts-extended = 4292 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 4293 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 4294 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 4295 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 4296 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 4297 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 4298 "handover", "stop-ack";
4312 4299
4313 clocks = <&rpmhcc RPM 4300 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 4301 clock-names = "xo";
4315 4302
4316 power-domains = <&rpm 4303 power-domains = <&rpmhpd SM8150_CX>;
4317 4304
4318 memory-region = <&ads 4305 memory-region = <&adsp_mem>;
4319 4306
4320 qcom,qmp = <&aoss_qmp 4307 qcom,qmp = <&aoss_qmp>;
4321 4308
4322 qcom,smem-states = <& 4309 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 4310 qcom,smem-state-names = "stop";
4324 4311
4325 status = "disabled"; 4312 status = "disabled";
4326 4313
4327 glink-edge { 4314 glink-edge {
4328 interrupts = 4315 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 4316 label = "lpass";
4330 qcom,remote-p 4317 qcom,remote-pid = <2>;
4331 mboxes = <&ap 4318 mboxes = <&apss_shared 8>;
4332 4319
4333 fastrpc { 4320 fastrpc {
4334 compa 4321 compatible = "qcom,fastrpc";
4335 qcom, 4322 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 4323 label = "adsp";
4337 qcom, 4324 qcom,non-secure-domain;
4338 #addr 4325 #address-cells = <1>;
4339 #size 4326 #size-cells = <0>;
4340 4327
4341 compu 4328 compute-cb@3 {
4342 4329 compatible = "qcom,fastrpc-compute-cb";
4343 4330 reg = <3>;
4344 4331 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 4332 };
4346 4333
4347 compu 4334 compute-cb@4 {
4348 4335 compatible = "qcom,fastrpc-compute-cb";
4349 4336 reg = <4>;
4350 4337 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 4338 };
4352 4339
4353 compu 4340 compute-cb@5 {
4354 4341 compatible = "qcom,fastrpc-compute-cb";
4355 4342 reg = <5>;
4356 4343 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 4344 };
4358 }; 4345 };
4359 }; 4346 };
4360 }; 4347 };
4361 4348
4362 intc: interrupt-controller@17 4349 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 4350 compatible = "arm,gic-v3";
4364 interrupt-controller; 4351 interrupt-controller;
4365 #interrupt-cells = <3 4352 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 4353 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 4354 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 4355 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 4356 };
4370 4357
4371 apss_shared: mailbox@17c00000 4358 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm 4359 compatible = "qcom,sm8150-apss-shared",
4373 "qcom,sd 4360 "qcom,sdm845-apss-shared";
4374 reg = <0x0 0x17c00000 4361 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 4362 #mbox-cells = <1>;
4376 }; 4363 };
4377 4364
4378 watchdog@17c10000 { 4365 watchdog@17c10000 {
4379 compatible = "qcom,ap 4366 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 4367 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 4368 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI 4369 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4383 }; 4370 };
4384 4371
4385 timer@17c20000 { 4372 timer@17c20000 {
4386 #address-cells = <1>; 4373 #address-cells = <1>;
4387 #size-cells = <1>; 4374 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 4375 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 4376 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 4377 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 4378 clock-frequency = <19200000>;
4392 4379
4393 frame@17c21000 { 4380 frame@17c21000 {
4394 frame-number 4381 frame-number = <0>;
4395 interrupts = 4382 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 4383 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 4384 reg = <0x17c21000 0x1000>,
4398 <0x17c2 4385 <0x17c22000 0x1000>;
4399 }; 4386 };
4400 4387
4401 frame@17c23000 { 4388 frame@17c23000 {
4402 frame-number 4389 frame-number = <1>;
4403 interrupts = 4390 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 4391 reg = <0x17c23000 0x1000>;
4405 status = "dis 4392 status = "disabled";
4406 }; 4393 };
4407 4394
4408 frame@17c25000 { 4395 frame@17c25000 {
4409 frame-number 4396 frame-number = <2>;
4410 interrupts = 4397 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 4398 reg = <0x17c25000 0x1000>;
4412 status = "dis 4399 status = "disabled";
4413 }; 4400 };
4414 4401
4415 frame@17c27000 { 4402 frame@17c27000 {
4416 frame-number 4403 frame-number = <3>;
4417 interrupts = 4404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 4405 reg = <0x17c26000 0x1000>;
4419 status = "dis 4406 status = "disabled";
4420 }; 4407 };
4421 4408
4422 frame@17c29000 { 4409 frame@17c29000 {
4423 frame-number 4410 frame-number = <4>;
4424 interrupts = 4411 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 4412 reg = <0x17c29000 0x1000>;
4426 status = "dis 4413 status = "disabled";
4427 }; 4414 };
4428 4415
4429 frame@17c2b000 { 4416 frame@17c2b000 {
4430 frame-number 4417 frame-number = <5>;
4431 interrupts = 4418 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 4419 reg = <0x17c2b000 0x1000>;
4433 status = "dis 4420 status = "disabled";
4434 }; 4421 };
4435 4422
4436 frame@17c2d000 { 4423 frame@17c2d000 {
4437 frame-number 4424 frame-number = <6>;
4438 interrupts = 4425 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 4426 reg = <0x17c2d000 0x1000>;
4440 status = "dis 4427 status = "disabled";
4441 }; 4428 };
4442 }; 4429 };
4443 4430
4444 apps_rsc: rsc@18200000 { 4431 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 4432 label = "apps_rsc";
4446 compatible = "qcom,rp 4433 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 4434 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 4435 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 4436 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 4437 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 4438 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4439 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 4440 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 4441 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 4442 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 4443 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 4444 <SLEEP_TCS 3>,
4458 <WA 4445 <WAKE_TCS 3>,
4459 <CO 4446 <CONTROL_TCS 1>;
4460 power-domains = <&CLU 4447 power-domains = <&CLUSTER_PD>;
4461 4448
4462 rpmhcc: clock-control 4449 rpmhcc: clock-controller {
4463 compatible = 4450 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 4451 #clock-cells = <1>;
4465 clock-names = 4452 clock-names = "xo";
4466 clocks = <&xo 4453 clocks = <&xo_board>;
4467 }; 4454 };
4468 4455
4469 rpmhpd: power-control 4456 rpmhpd: power-controller {
4470 compatible = 4457 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 4458 #power-domain-cells = <1>;
4472 operating-poi 4459 operating-points-v2 = <&rpmhpd_opp_table>;
4473 4460
4474 rpmhpd_opp_ta 4461 rpmhpd_opp_table: opp-table {
4475 compa 4462 compatible = "operating-points-v2";
4476 4463
4477 rpmhp 4464 rpmhpd_opp_ret: opp1 {
4478 4465 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 4466 };
4480 4467
4481 rpmhp 4468 rpmhpd_opp_min_svs: opp2 {
4482 4469 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 4470 };
4484 4471
4485 rpmhp 4472 rpmhpd_opp_low_svs: opp3 {
4486 4473 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 4474 };
4488 4475
4489 rpmhp 4476 rpmhpd_opp_svs: opp4 {
4490 4477 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 4478 };
4492 4479
4493 rpmhp 4480 rpmhpd_opp_svs_l1: opp5 {
4494 4481 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 4482 };
4496 4483
4497 rpmhp 4484 rpmhpd_opp_svs_l2: opp6 {
4498 4485 opp-level = <224>;
4499 }; 4486 };
4500 4487
4501 rpmhp 4488 rpmhpd_opp_nom: opp7 {
4502 4489 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 4490 };
4504 4491
4505 rpmhp 4492 rpmhpd_opp_nom_l1: opp8 {
4506 4493 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 4494 };
4508 4495
4509 rpmhp 4496 rpmhpd_opp_nom_l2: opp9 {
4510 4497 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 4498 };
4512 4499
4513 rpmhp 4500 rpmhpd_opp_turbo: opp10 {
4514 4501 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 4502 };
4516 4503
4517 rpmhp 4504 rpmhpd_opp_turbo_l1: opp11 {
4518 4505 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 4506 };
4520 }; 4507 };
4521 }; 4508 };
4522 4509
4523 apps_bcm_voter: bcm-v 4510 apps_bcm_voter: bcm-voter {
4524 compatible = 4511 compatible = "qcom,bcm-voter";
4525 }; 4512 };
4526 }; 4513 };
4527 4514
4528 osm_l3: interconnect@18321000 4515 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm 4516 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 4517 reg = <0 0x18321000 0 0x1400>;
4531 4518
4532 clocks = <&rpmhcc RPM 4519 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 4520 clock-names = "xo", "alternate";
4534 4521
4535 #interconnect-cells = 4522 #interconnect-cells = <1>;
4536 }; 4523 };
4537 4524
4538 cpufreq_hw: cpufreq@18323000 4525 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm 4526 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 4527 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 4528 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 4529 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 4530 "freq-domain2";
4544 4531
4545 clocks = <&rpmhcc RPM 4532 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 4533 clock-names = "xo", "alternate";
4547 4534
4548 #freq-domain-cells = 4535 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; 4536 #clock-cells = <1>;
4550 }; 4537 };
4551 4538
4552 lmh_cluster1: lmh@18350800 { 4539 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 4540 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 4541 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 4542 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 4543 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 4544 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 4545 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 4546 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 4547 interrupt-controller;
4561 #interrupt-cells = <1 4548 #interrupt-cells = <1>;
4562 }; 4549 };
4563 4550
4564 lmh_cluster0: lmh@18358800 { 4551 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 4552 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 4553 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 4554 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4555 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4556 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4557 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4558 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4559 interrupt-controller;
4573 #interrupt-cells = <1 4560 #interrupt-cells = <1>;
4574 }; 4561 };
4575 4562
4576 wifi: wifi@18800000 { 4563 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4564 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4565 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4566 reg-names = "membase";
4580 memory-region = <&wla 4567 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4568 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4569 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4570 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4571 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4572 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4573 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4574 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4575 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4576 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4577 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4578 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4579 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4580 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4581 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4582 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4583 status = "disabled";
4597 }; 4584 };
4598 }; 4585 };
4599 4586
4600 timer { 4587 timer {
4601 compatible = "arm,armv8-timer 4588 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4589 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4590 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4591 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4592 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4593 };
4607 4594
4608 thermal-zones { 4595 thermal-zones {
4609 cpu0-thermal { 4596 cpu0-thermal {
4610 polling-delay-passive 4597 polling-delay-passive = <250>;
4611 4598
4612 thermal-sensors = <&t 4599 thermal-sensors = <&tsens0 1>;
4613 4600
4614 trips { 4601 trips {
4615 cpu0_alert0: 4602 cpu0_alert0: trip-point0 {
4616 tempe 4603 temperature = <90000>;
4617 hyste 4604 hysteresis = <2000>;
4618 type 4605 type = "passive";
4619 }; 4606 };
4620 4607
4621 cpu0_alert1: 4608 cpu0_alert1: trip-point1 {
4622 tempe 4609 temperature = <95000>;
4623 hyste 4610 hysteresis = <2000>;
4624 type 4611 type = "passive";
4625 }; 4612 };
4626 4613
4627 cpu0_crit: cp 4614 cpu0_crit: cpu-crit {
4628 tempe 4615 temperature = <110000>;
4629 hyste 4616 hysteresis = <1000>;
4630 type 4617 type = "critical";
4631 }; 4618 };
4632 }; 4619 };
4633 4620
4634 cooling-maps { 4621 cooling-maps {
4635 map0 { 4622 map0 {
4636 trip 4623 trip = <&cpu0_alert0>;
4637 cooli 4624 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4625 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4626 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4627 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4628 };
4642 map1 { 4629 map1 {
4643 trip 4630 trip = <&cpu0_alert1>;
4644 cooli 4631 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4632 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4633 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4634 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4635 };
4649 }; 4636 };
4650 }; 4637 };
4651 4638
4652 cpu1-thermal { 4639 cpu1-thermal {
4653 polling-delay-passive 4640 polling-delay-passive = <250>;
4654 4641
4655 thermal-sensors = <&t 4642 thermal-sensors = <&tsens0 2>;
4656 4643
4657 trips { 4644 trips {
4658 cpu1_alert0: 4645 cpu1_alert0: trip-point0 {
4659 tempe 4646 temperature = <90000>;
4660 hyste 4647 hysteresis = <2000>;
4661 type 4648 type = "passive";
4662 }; 4649 };
4663 4650
4664 cpu1_alert1: 4651 cpu1_alert1: trip-point1 {
4665 tempe 4652 temperature = <95000>;
4666 hyste 4653 hysteresis = <2000>;
4667 type 4654 type = "passive";
4668 }; 4655 };
4669 4656
4670 cpu1_crit: cp 4657 cpu1_crit: cpu-crit {
4671 tempe 4658 temperature = <110000>;
4672 hyste 4659 hysteresis = <1000>;
4673 type 4660 type = "critical";
4674 }; 4661 };
4675 }; 4662 };
4676 4663
4677 cooling-maps { 4664 cooling-maps {
4678 map0 { 4665 map0 {
4679 trip 4666 trip = <&cpu1_alert0>;
4680 cooli 4667 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4668 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4669 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4670 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4671 };
4685 map1 { 4672 map1 {
4686 trip 4673 trip = <&cpu1_alert1>;
4687 cooli 4674 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4675 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4676 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4677 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4678 };
4692 }; 4679 };
4693 }; 4680 };
4694 4681
4695 cpu2-thermal { 4682 cpu2-thermal {
4696 polling-delay-passive 4683 polling-delay-passive = <250>;
4697 4684
4698 thermal-sensors = <&t 4685 thermal-sensors = <&tsens0 3>;
4699 4686
4700 trips { 4687 trips {
4701 cpu2_alert0: 4688 cpu2_alert0: trip-point0 {
4702 tempe 4689 temperature = <90000>;
4703 hyste 4690 hysteresis = <2000>;
4704 type 4691 type = "passive";
4705 }; 4692 };
4706 4693
4707 cpu2_alert1: 4694 cpu2_alert1: trip-point1 {
4708 tempe 4695 temperature = <95000>;
4709 hyste 4696 hysteresis = <2000>;
4710 type 4697 type = "passive";
4711 }; 4698 };
4712 4699
4713 cpu2_crit: cp 4700 cpu2_crit: cpu-crit {
4714 tempe 4701 temperature = <110000>;
4715 hyste 4702 hysteresis = <1000>;
4716 type 4703 type = "critical";
4717 }; 4704 };
4718 }; 4705 };
4719 4706
4720 cooling-maps { 4707 cooling-maps {
4721 map0 { 4708 map0 {
4722 trip 4709 trip = <&cpu2_alert0>;
4723 cooli 4710 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4711 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4712 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4713 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4714 };
4728 map1 { 4715 map1 {
4729 trip 4716 trip = <&cpu2_alert1>;
4730 cooli 4717 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4718 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4719 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4720 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4721 };
4735 }; 4722 };
4736 }; 4723 };
4737 4724
4738 cpu3-thermal { 4725 cpu3-thermal {
4739 polling-delay-passive 4726 polling-delay-passive = <250>;
4740 4727
4741 thermal-sensors = <&t 4728 thermal-sensors = <&tsens0 4>;
4742 4729
4743 trips { 4730 trips {
4744 cpu3_alert0: 4731 cpu3_alert0: trip-point0 {
4745 tempe 4732 temperature = <90000>;
4746 hyste 4733 hysteresis = <2000>;
4747 type 4734 type = "passive";
4748 }; 4735 };
4749 4736
4750 cpu3_alert1: 4737 cpu3_alert1: trip-point1 {
4751 tempe 4738 temperature = <95000>;
4752 hyste 4739 hysteresis = <2000>;
4753 type 4740 type = "passive";
4754 }; 4741 };
4755 4742
4756 cpu3_crit: cp 4743 cpu3_crit: cpu-crit {
4757 tempe 4744 temperature = <110000>;
4758 hyste 4745 hysteresis = <1000>;
4759 type 4746 type = "critical";
4760 }; 4747 };
4761 }; 4748 };
4762 4749
4763 cooling-maps { 4750 cooling-maps {
4764 map0 { 4751 map0 {
4765 trip 4752 trip = <&cpu3_alert0>;
4766 cooli 4753 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4754 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4755 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4756 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4757 };
4771 map1 { 4758 map1 {
4772 trip 4759 trip = <&cpu3_alert1>;
4773 cooli 4760 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4761 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4762 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4763 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4764 };
4778 }; 4765 };
4779 }; 4766 };
4780 4767
4781 cpu4-top-thermal { 4768 cpu4-top-thermal {
4782 polling-delay-passive 4769 polling-delay-passive = <250>;
4783 4770
4784 thermal-sensors = <&t 4771 thermal-sensors = <&tsens0 7>;
4785 4772
4786 trips { 4773 trips {
4787 cpu4_top_aler 4774 cpu4_top_alert0: trip-point0 {
4788 tempe 4775 temperature = <90000>;
4789 hyste 4776 hysteresis = <2000>;
4790 type 4777 type = "passive";
4791 }; 4778 };
4792 4779
4793 cpu4_top_aler 4780 cpu4_top_alert1: trip-point1 {
4794 tempe 4781 temperature = <95000>;
4795 hyste 4782 hysteresis = <2000>;
4796 type 4783 type = "passive";
4797 }; 4784 };
4798 4785
4799 cpu4_top_crit 4786 cpu4_top_crit: cpu-crit {
4800 tempe 4787 temperature = <110000>;
4801 hyste 4788 hysteresis = <1000>;
4802 type 4789 type = "critical";
4803 }; 4790 };
4804 }; 4791 };
4805 4792
4806 cooling-maps { 4793 cooling-maps {
4807 map0 { 4794 map0 {
4808 trip 4795 trip = <&cpu4_top_alert0>;
4809 cooli 4796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4800 };
4814 map1 { 4801 map1 {
4815 trip 4802 trip = <&cpu4_top_alert1>;
4816 cooli 4803 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4804 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4805 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4806 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4807 };
4821 }; 4808 };
4822 }; 4809 };
4823 4810
4824 cpu5-top-thermal { 4811 cpu5-top-thermal {
4825 polling-delay-passive 4812 polling-delay-passive = <250>;
4826 4813
4827 thermal-sensors = <&t 4814 thermal-sensors = <&tsens0 8>;
4828 4815
4829 trips { 4816 trips {
4830 cpu5_top_aler 4817 cpu5_top_alert0: trip-point0 {
4831 tempe 4818 temperature = <90000>;
4832 hyste 4819 hysteresis = <2000>;
4833 type 4820 type = "passive";
4834 }; 4821 };
4835 4822
4836 cpu5_top_aler 4823 cpu5_top_alert1: trip-point1 {
4837 tempe 4824 temperature = <95000>;
4838 hyste 4825 hysteresis = <2000>;
4839 type 4826 type = "passive";
4840 }; 4827 };
4841 4828
4842 cpu5_top_crit 4829 cpu5_top_crit: cpu-crit {
4843 tempe 4830 temperature = <110000>;
4844 hyste 4831 hysteresis = <1000>;
4845 type 4832 type = "critical";
4846 }; 4833 };
4847 }; 4834 };
4848 4835
4849 cooling-maps { 4836 cooling-maps {
4850 map0 { 4837 map0 {
4851 trip 4838 trip = <&cpu5_top_alert0>;
4852 cooli 4839 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4840 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4841 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4842 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4843 };
4857 map1 { 4844 map1 {
4858 trip 4845 trip = <&cpu5_top_alert1>;
4859 cooli 4846 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4847 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4848 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4849 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4850 };
4864 }; 4851 };
4865 }; 4852 };
4866 4853
4867 cpu6-top-thermal { 4854 cpu6-top-thermal {
4868 polling-delay-passive 4855 polling-delay-passive = <250>;
4869 4856
4870 thermal-sensors = <&t 4857 thermal-sensors = <&tsens0 9>;
4871 4858
4872 trips { 4859 trips {
4873 cpu6_top_aler 4860 cpu6_top_alert0: trip-point0 {
4874 tempe 4861 temperature = <90000>;
4875 hyste 4862 hysteresis = <2000>;
4876 type 4863 type = "passive";
4877 }; 4864 };
4878 4865
4879 cpu6_top_aler 4866 cpu6_top_alert1: trip-point1 {
4880 tempe 4867 temperature = <95000>;
4881 hyste 4868 hysteresis = <2000>;
4882 type 4869 type = "passive";
4883 }; 4870 };
4884 4871
4885 cpu6_top_crit 4872 cpu6_top_crit: cpu-crit {
4886 tempe 4873 temperature = <110000>;
4887 hyste 4874 hysteresis = <1000>;
4888 type 4875 type = "critical";
4889 }; 4876 };
4890 }; 4877 };
4891 4878
4892 cooling-maps { 4879 cooling-maps {
4893 map0 { 4880 map0 {
4894 trip 4881 trip = <&cpu6_top_alert0>;
4895 cooli 4882 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4883 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4884 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4885 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4886 };
4900 map1 { 4887 map1 {
4901 trip 4888 trip = <&cpu6_top_alert1>;
4902 cooli 4889 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4891 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4892 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4893 };
4907 }; 4894 };
4908 }; 4895 };
4909 4896
4910 cpu7-top-thermal { 4897 cpu7-top-thermal {
4911 polling-delay-passive 4898 polling-delay-passive = <250>;
4912 4899
4913 thermal-sensors = <&t 4900 thermal-sensors = <&tsens0 10>;
4914 4901
4915 trips { 4902 trips {
4916 cpu7_top_aler 4903 cpu7_top_alert0: trip-point0 {
4917 tempe 4904 temperature = <90000>;
4918 hyste 4905 hysteresis = <2000>;
4919 type 4906 type = "passive";
4920 }; 4907 };
4921 4908
4922 cpu7_top_aler 4909 cpu7_top_alert1: trip-point1 {
4923 tempe 4910 temperature = <95000>;
4924 hyste 4911 hysteresis = <2000>;
4925 type 4912 type = "passive";
4926 }; 4913 };
4927 4914
4928 cpu7_top_crit 4915 cpu7_top_crit: cpu-crit {
4929 tempe 4916 temperature = <110000>;
4930 hyste 4917 hysteresis = <1000>;
4931 type 4918 type = "critical";
4932 }; 4919 };
4933 }; 4920 };
4934 4921
4935 cooling-maps { 4922 cooling-maps {
4936 map0 { 4923 map0 {
4937 trip 4924 trip = <&cpu7_top_alert0>;
4938 cooli 4925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4926 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4927 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4928 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4929 };
4943 map1 { 4930 map1 {
4944 trip 4931 trip = <&cpu7_top_alert1>;
4945 cooli 4932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4933 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4934 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4935 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4936 };
4950 }; 4937 };
4951 }; 4938 };
4952 4939
4953 cpu4-bottom-thermal { 4940 cpu4-bottom-thermal {
4954 polling-delay-passive 4941 polling-delay-passive = <250>;
4955 4942
4956 thermal-sensors = <&t 4943 thermal-sensors = <&tsens0 11>;
4957 4944
4958 trips { 4945 trips {
4959 cpu4_bottom_a 4946 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4947 temperature = <90000>;
4961 hyste 4948 hysteresis = <2000>;
4962 type 4949 type = "passive";
4963 }; 4950 };
4964 4951
4965 cpu4_bottom_a 4952 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4953 temperature = <95000>;
4967 hyste 4954 hysteresis = <2000>;
4968 type 4955 type = "passive";
4969 }; 4956 };
4970 4957
4971 cpu4_bottom_c 4958 cpu4_bottom_crit: cpu-crit {
4972 tempe 4959 temperature = <110000>;
4973 hyste 4960 hysteresis = <1000>;
4974 type 4961 type = "critical";
4975 }; 4962 };
4976 }; 4963 };
4977 4964
4978 cooling-maps { 4965 cooling-maps {
4979 map0 { 4966 map0 {
4980 trip 4967 trip = <&cpu4_bottom_alert0>;
4981 cooli 4968 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4969 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4970 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4971 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4972 };
4986 map1 { 4973 map1 {
4987 trip 4974 trip = <&cpu4_bottom_alert1>;
4988 cooli 4975 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4976 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4977 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4978 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4979 };
4993 }; 4980 };
4994 }; 4981 };
4995 4982
4996 cpu5-bottom-thermal { 4983 cpu5-bottom-thermal {
4997 polling-delay-passive 4984 polling-delay-passive = <250>;
4998 4985
4999 thermal-sensors = <&t 4986 thermal-sensors = <&tsens0 12>;
5000 4987
5001 trips { 4988 trips {
5002 cpu5_bottom_a 4989 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4990 temperature = <90000>;
5004 hyste 4991 hysteresis = <2000>;
5005 type 4992 type = "passive";
5006 }; 4993 };
5007 4994
5008 cpu5_bottom_a 4995 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4996 temperature = <95000>;
5010 hyste 4997 hysteresis = <2000>;
5011 type 4998 type = "passive";
5012 }; 4999 };
5013 5000
5014 cpu5_bottom_c 5001 cpu5_bottom_crit: cpu-crit {
5015 tempe 5002 temperature = <110000>;
5016 hyste 5003 hysteresis = <1000>;
5017 type 5004 type = "critical";
5018 }; 5005 };
5019 }; 5006 };
5020 5007
5021 cooling-maps { 5008 cooling-maps {
5022 map0 { 5009 map0 {
5023 trip 5010 trip = <&cpu5_bottom_alert0>;
5024 cooli 5011 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 5012 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 5013 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 5014 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 5015 };
5029 map1 { 5016 map1 {
5030 trip 5017 trip = <&cpu5_bottom_alert1>;
5031 cooli 5018 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 5019 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 5020 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 5021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 5022 };
5036 }; 5023 };
5037 }; 5024 };
5038 5025
5039 cpu6-bottom-thermal { 5026 cpu6-bottom-thermal {
5040 polling-delay-passive 5027 polling-delay-passive = <250>;
5041 5028
5042 thermal-sensors = <&t 5029 thermal-sensors = <&tsens0 13>;
5043 5030
5044 trips { 5031 trips {
5045 cpu6_bottom_a 5032 cpu6_bottom_alert0: trip-point0 {
5046 tempe 5033 temperature = <90000>;
5047 hyste 5034 hysteresis = <2000>;
5048 type 5035 type = "passive";
5049 }; 5036 };
5050 5037
5051 cpu6_bottom_a 5038 cpu6_bottom_alert1: trip-point1 {
5052 tempe 5039 temperature = <95000>;
5053 hyste 5040 hysteresis = <2000>;
5054 type 5041 type = "passive";
5055 }; 5042 };
5056 5043
5057 cpu6_bottom_c 5044 cpu6_bottom_crit: cpu-crit {
5058 tempe 5045 temperature = <110000>;
5059 hyste 5046 hysteresis = <1000>;
5060 type 5047 type = "critical";
5061 }; 5048 };
5062 }; 5049 };
5063 5050
5064 cooling-maps { 5051 cooling-maps {
5065 map0 { 5052 map0 {
5066 trip 5053 trip = <&cpu6_bottom_alert0>;
5067 cooli 5054 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 5055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 5056 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 5057 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 5058 };
5072 map1 { 5059 map1 {
5073 trip 5060 trip = <&cpu6_bottom_alert1>;
5074 cooli 5061 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 5062 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 5063 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 5064 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 5065 };
5079 }; 5066 };
5080 }; 5067 };
5081 5068
5082 cpu7-bottom-thermal { 5069 cpu7-bottom-thermal {
5083 polling-delay-passive 5070 polling-delay-passive = <250>;
5084 5071
5085 thermal-sensors = <&t 5072 thermal-sensors = <&tsens0 14>;
5086 5073
5087 trips { 5074 trips {
5088 cpu7_bottom_a 5075 cpu7_bottom_alert0: trip-point0 {
5089 tempe 5076 temperature = <90000>;
5090 hyste 5077 hysteresis = <2000>;
5091 type 5078 type = "passive";
5092 }; 5079 };
5093 5080
5094 cpu7_bottom_a 5081 cpu7_bottom_alert1: trip-point1 {
5095 tempe 5082 temperature = <95000>;
5096 hyste 5083 hysteresis = <2000>;
5097 type 5084 type = "passive";
5098 }; 5085 };
5099 5086
5100 cpu7_bottom_c 5087 cpu7_bottom_crit: cpu-crit {
5101 tempe 5088 temperature = <110000>;
5102 hyste 5089 hysteresis = <1000>;
5103 type 5090 type = "critical";
5104 }; 5091 };
5105 }; 5092 };
5106 5093
5107 cooling-maps { 5094 cooling-maps {
5108 map0 { 5095 map0 {
5109 trip 5096 trip = <&cpu7_bottom_alert0>;
5110 cooli 5097 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 5098 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 5099 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 5100 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 5101 };
5115 map1 { 5102 map1 {
5116 trip 5103 trip = <&cpu7_bottom_alert1>;
5117 cooli 5104 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 5105 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 5106 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 5107 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 5108 };
5122 }; 5109 };
5123 }; 5110 };
5124 5111
5125 aoss0-thermal { 5112 aoss0-thermal {
5126 polling-delay-passive 5113 polling-delay-passive = <250>;
5127 5114
5128 thermal-sensors = <&t 5115 thermal-sensors = <&tsens0 0>;
5129 5116
5130 trips { 5117 trips {
5131 aoss0_alert0: 5118 aoss0_alert0: trip-point0 {
5132 tempe 5119 temperature = <90000>;
5133 hyste 5120 hysteresis = <2000>;
5134 type 5121 type = "hot";
5135 }; 5122 };
5136 }; 5123 };
5137 }; 5124 };
5138 5125
5139 cluster0-thermal { 5126 cluster0-thermal {
5140 polling-delay-passive 5127 polling-delay-passive = <250>;
5141 5128
5142 thermal-sensors = <&t 5129 thermal-sensors = <&tsens0 5>;
5143 5130
5144 trips { 5131 trips {
5145 cluster0_aler 5132 cluster0_alert0: trip-point0 {
5146 tempe 5133 temperature = <90000>;
5147 hyste 5134 hysteresis = <2000>;
5148 type 5135 type = "hot";
5149 }; 5136 };
5150 cluster0_crit 5137 cluster0_crit: cluster0-crit {
5151 tempe 5138 temperature = <110000>;
5152 hyste 5139 hysteresis = <2000>;
5153 type 5140 type = "critical";
5154 }; 5141 };
5155 }; 5142 };
5156 }; 5143 };
5157 5144
5158 cluster1-thermal { 5145 cluster1-thermal {
5159 polling-delay-passive 5146 polling-delay-passive = <250>;
5160 5147
5161 thermal-sensors = <&t 5148 thermal-sensors = <&tsens0 6>;
5162 5149
5163 trips { 5150 trips {
5164 cluster1_aler 5151 cluster1_alert0: trip-point0 {
5165 tempe 5152 temperature = <90000>;
5166 hyste 5153 hysteresis = <2000>;
5167 type 5154 type = "hot";
5168 }; 5155 };
5169 cluster1_crit 5156 cluster1_crit: cluster1-crit {
5170 tempe 5157 temperature = <110000>;
5171 hyste 5158 hysteresis = <2000>;
5172 type 5159 type = "critical";
5173 }; 5160 };
5174 }; 5161 };
5175 }; 5162 };
5176 5163
5177 gpu-top-thermal { 5164 gpu-top-thermal {
5178 polling-delay-passive 5165 polling-delay-passive = <250>;
5179 5166
5180 thermal-sensors = <&t 5167 thermal-sensors = <&tsens0 15>;
5181 5168
5182 cooling-maps { 5169 cooling-maps {
5183 map0 { 5170 map0 {
5184 trip 5171 trip = <&gpu_top_alert0>;
5185 cooli 5172 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5186 }; 5173 };
5187 }; 5174 };
5188 5175
5189 trips { 5176 trips {
5190 gpu_top_alert 5177 gpu_top_alert0: trip-point0 {
5191 tempe 5178 temperature = <85000>;
5192 hyste 5179 hysteresis = <1000>;
5193 type 5180 type = "passive";
5194 }; 5181 };
5195 5182
5196 trip-point1 { 5183 trip-point1 {
5197 tempe 5184 temperature = <90000>;
5198 hyste 5185 hysteresis = <1000>;
5199 type 5186 type = "hot";
5200 }; 5187 };
5201 5188
5202 trip-point2 { 5189 trip-point2 {
5203 tempe 5190 temperature = <110000>;
5204 hyste 5191 hysteresis = <1000>;
5205 type 5192 type = "critical";
5206 }; 5193 };
5207 }; 5194 };
5208 }; 5195 };
5209 5196
5210 aoss1-thermal { 5197 aoss1-thermal {
5211 polling-delay-passive 5198 polling-delay-passive = <250>;
5212 5199
5213 thermal-sensors = <&t 5200 thermal-sensors = <&tsens1 0>;
5214 5201
5215 trips { 5202 trips {
5216 aoss1_alert0: 5203 aoss1_alert0: trip-point0 {
5217 tempe 5204 temperature = <90000>;
5218 hyste 5205 hysteresis = <2000>;
5219 type 5206 type = "hot";
5220 }; 5207 };
5221 }; 5208 };
5222 }; 5209 };
5223 5210
5224 wlan-thermal { 5211 wlan-thermal {
5225 polling-delay-passive 5212 polling-delay-passive = <250>;
5226 5213
5227 thermal-sensors = <&t 5214 thermal-sensors = <&tsens1 1>;
5228 5215
5229 trips { 5216 trips {
5230 wlan_alert0: 5217 wlan_alert0: trip-point0 {
5231 tempe 5218 temperature = <90000>;
5232 hyste 5219 hysteresis = <2000>;
5233 type 5220 type = "hot";
5234 }; 5221 };
5235 }; 5222 };
5236 }; 5223 };
5237 5224
5238 video-thermal { 5225 video-thermal {
5239 polling-delay-passive 5226 polling-delay-passive = <250>;
5240 5227
5241 thermal-sensors = <&t 5228 thermal-sensors = <&tsens1 2>;
5242 5229
5243 trips { 5230 trips {
5244 video_alert0: 5231 video_alert0: trip-point0 {
5245 tempe 5232 temperature = <90000>;
5246 hyste 5233 hysteresis = <2000>;
5247 type 5234 type = "hot";
5248 }; 5235 };
5249 }; 5236 };
5250 }; 5237 };
5251 5238
5252 mem-thermal { 5239 mem-thermal {
5253 polling-delay-passive 5240 polling-delay-passive = <250>;
5254 5241
5255 thermal-sensors = <&t 5242 thermal-sensors = <&tsens1 3>;
5256 5243
5257 trips { 5244 trips {
5258 mem_alert0: t 5245 mem_alert0: trip-point0 {
5259 tempe 5246 temperature = <90000>;
5260 hyste 5247 hysteresis = <2000>;
5261 type 5248 type = "hot";
5262 }; 5249 };
5263 }; 5250 };
5264 }; 5251 };
5265 5252
5266 q6-hvx-thermal { 5253 q6-hvx-thermal {
5267 polling-delay-passive 5254 polling-delay-passive = <250>;
5268 5255
5269 thermal-sensors = <&t 5256 thermal-sensors = <&tsens1 4>;
5270 5257
5271 trips { 5258 trips {
5272 q6_hvx_alert0 5259 q6_hvx_alert0: trip-point0 {
5273 tempe 5260 temperature = <90000>;
5274 hyste 5261 hysteresis = <2000>;
5275 type 5262 type = "hot";
5276 }; 5263 };
5277 }; 5264 };
5278 }; 5265 };
5279 5266
5280 camera-thermal { 5267 camera-thermal {
5281 polling-delay-passive 5268 polling-delay-passive = <250>;
5282 5269
5283 thermal-sensors = <&t 5270 thermal-sensors = <&tsens1 5>;
5284 5271
5285 trips { 5272 trips {
5286 camera_alert0 5273 camera_alert0: trip-point0 {
5287 tempe 5274 temperature = <90000>;
5288 hyste 5275 hysteresis = <2000>;
5289 type 5276 type = "hot";
5290 }; 5277 };
5291 }; 5278 };
5292 }; 5279 };
5293 5280
5294 compute-thermal { 5281 compute-thermal {
5295 polling-delay-passive 5282 polling-delay-passive = <250>;
5296 5283
5297 thermal-sensors = <&t 5284 thermal-sensors = <&tsens1 6>;
5298 5285
5299 trips { 5286 trips {
5300 compute_alert 5287 compute_alert0: trip-point0 {
5301 tempe 5288 temperature = <90000>;
5302 hyste 5289 hysteresis = <2000>;
5303 type 5290 type = "hot";
5304 }; 5291 };
5305 }; 5292 };
5306 }; 5293 };
5307 5294
5308 modem-thermal { 5295 modem-thermal {
5309 polling-delay-passive 5296 polling-delay-passive = <250>;
5310 5297
5311 thermal-sensors = <&t 5298 thermal-sensors = <&tsens1 7>;
5312 5299
5313 trips { 5300 trips {
5314 modem_alert0: 5301 modem_alert0: trip-point0 {
5315 tempe 5302 temperature = <90000>;
5316 hyste 5303 hysteresis = <2000>;
5317 type 5304 type = "hot";
5318 }; 5305 };
5319 }; 5306 };
5320 }; 5307 };
5321 5308
5322 npu-thermal { 5309 npu-thermal {
5323 polling-delay-passive 5310 polling-delay-passive = <250>;
5324 5311
5325 thermal-sensors = <&t 5312 thermal-sensors = <&tsens1 8>;
5326 5313
5327 trips { 5314 trips {
5328 npu_alert0: t 5315 npu_alert0: trip-point0 {
5329 tempe 5316 temperature = <90000>;
5330 hyste 5317 hysteresis = <2000>;
5331 type 5318 type = "hot";
5332 }; 5319 };
5333 }; 5320 };
5334 }; 5321 };
5335 5322
5336 modem-vec-thermal { 5323 modem-vec-thermal {
5337 polling-delay-passive 5324 polling-delay-passive = <250>;
5338 5325
5339 thermal-sensors = <&t 5326 thermal-sensors = <&tsens1 9>;
5340 5327
5341 trips { 5328 trips {
5342 modem_vec_ale 5329 modem_vec_alert0: trip-point0 {
5343 tempe 5330 temperature = <90000>;
5344 hyste 5331 hysteresis = <2000>;
5345 type 5332 type = "hot";
5346 }; 5333 };
5347 }; 5334 };
5348 }; 5335 };
5349 5336
5350 modem-scl-thermal { 5337 modem-scl-thermal {
5351 polling-delay-passive 5338 polling-delay-passive = <250>;
5352 5339
5353 thermal-sensors = <&t 5340 thermal-sensors = <&tsens1 10>;
5354 5341
5355 trips { 5342 trips {
5356 modem_scl_ale 5343 modem_scl_alert0: trip-point0 {
5357 tempe 5344 temperature = <90000>;
5358 hyste 5345 hysteresis = <2000>;
5359 type 5346 type = "hot";
5360 }; 5347 };
5361 }; 5348 };
5362 }; 5349 };
5363 5350
5364 gpu-bottom-thermal { 5351 gpu-bottom-thermal {
5365 polling-delay-passive 5352 polling-delay-passive = <250>;
5366 5353
5367 thermal-sensors = <&t 5354 thermal-sensors = <&tsens1 11>;
5368 5355
5369 cooling-maps { 5356 cooling-maps {
5370 map0 { 5357 map0 {
5371 trip 5358 trip = <&gpu_bottom_alert0>;
5372 cooli 5359 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5373 }; 5360 };
5374 }; 5361 };
5375 5362
5376 trips { 5363 trips {
5377 gpu_bottom_al 5364 gpu_bottom_alert0: trip-point0 {
5378 tempe 5365 temperature = <85000>;
5379 hyste 5366 hysteresis = <1000>;
5380 type 5367 type = "passive";
5381 }; 5368 };
5382 5369
5383 trip-point1 { 5370 trip-point1 {
5384 tempe 5371 temperature = <90000>;
5385 hyste 5372 hysteresis = <1000>;
5386 type 5373 type = "hot";
5387 }; 5374 };
5388 5375
5389 trip-point2 { 5376 trip-point2 {
5390 tempe 5377 temperature = <110000>;
5391 hyste 5378 hysteresis = <1000>;
5392 type 5379 type = "critical";
5393 }; 5380 };
5394 }; 5381 };
5395 }; 5382 };
5396 }; 5383 };
5397 }; 5384 };
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