1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 <<
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 15 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 16 #include <dt-bindings/thermal/thermal.h>
22 17
23 / { 18 / {
24 interrupt-parent = <&intc>; 19 interrupt-parent = <&intc>;
25 20
26 #address-cells = <2>; 21 #address-cells = <2>;
27 #size-cells = <2>; 22 #size-cells = <2>;
28 23
29 chosen { }; 24 chosen { };
30 25
31 clocks { 26 clocks {
32 xo_board: xo-board { 27 xo_board: xo-board {
33 compatible = "fixed-cl 28 compatible = "fixed-clock";
34 #clock-cells = <0>; 29 #clock-cells = <0>;
35 clock-frequency = <384 30 clock-frequency = <38400000>;
36 clock-output-names = " 31 clock-output-names = "xo_board";
37 }; 32 };
38 33
39 sleep_clk: sleep-clk { 34 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 35 compatible = "fixed-clock";
41 #clock-cells = <0>; 36 #clock-cells = <0>;
42 clock-frequency = <327 37 clock-frequency = <32764>;
43 clock-output-names = " 38 clock-output-names = "sleep_clk";
44 }; 39 };
45 }; 40 };
46 41
47 cpus { 42 cpus {
48 #address-cells = <2>; 43 #address-cells = <2>;
49 #size-cells = <0>; 44 #size-cells = <0>;
50 45
51 CPU0: cpu@0 { 46 CPU0: cpu@0 {
52 device_type = "cpu"; 47 device_type = "cpu";
53 compatible = "qcom,kry 48 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 50 enable-method = "psci";
57 capacity-dmips-mhz = < 51 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 52 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 53 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 54 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 55 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 56 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 57 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 58 power-domains = <&CPU_PD0>;
65 power-domain-names = " 59 power-domain-names = "psci";
66 #cooling-cells = <2>; 60 #cooling-cells = <2>;
67 L2_0: l2-cache { 61 L2_0: l2-cache {
68 compatible = " 62 compatible = "cache";
69 cache-level = <<
70 cache-unified; <<
71 next-level-cac 63 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 64 L3_0: l3-cache {
73 compat !! 65 compatible = "cache";
74 cache- <<
75 cache- <<
76 }; 66 };
77 }; 67 };
78 }; 68 };
79 69
80 CPU1: cpu@100 { 70 CPU1: cpu@100 {
81 device_type = "cpu"; 71 device_type = "cpu";
82 compatible = "qcom,kry 72 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 73 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 74 enable-method = "psci";
86 capacity-dmips-mhz = < 75 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 76 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 77 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 78 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 79 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 80 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 81 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 82 power-domains = <&CPU_PD1>;
94 power-domain-names = " 83 power-domain-names = "psci";
95 #cooling-cells = <2>; 84 #cooling-cells = <2>;
96 L2_100: l2-cache { 85 L2_100: l2-cache {
97 compatible = " 86 compatible = "cache";
98 cache-level = <<
99 cache-unified; <<
100 next-level-cac 87 next-level-cache = <&L3_0>;
101 }; 88 };
>> 89
102 }; 90 };
103 91
104 CPU2: cpu@200 { 92 CPU2: cpu@200 {
105 device_type = "cpu"; 93 device_type = "cpu";
106 compatible = "qcom,kry 94 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 95 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 96 enable-method = "psci";
110 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 98 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 99 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 101 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 102 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 103 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 104 power-domains = <&CPU_PD2>;
118 power-domain-names = " 105 power-domain-names = "psci";
119 #cooling-cells = <2>; 106 #cooling-cells = <2>;
120 L2_200: l2-cache { 107 L2_200: l2-cache {
121 compatible = " 108 compatible = "cache";
122 cache-level = <<
123 cache-unified; <<
124 next-level-cac 109 next-level-cache = <&L3_0>;
125 }; 110 };
126 }; 111 };
127 112
128 CPU3: cpu@300 { 113 CPU3: cpu@300 {
129 device_type = "cpu"; 114 device_type = "cpu";
130 compatible = "qcom,kry 115 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 116 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 117 enable-method = "psci";
134 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 119 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 120 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 122 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 123 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 124 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 125 power-domains = <&CPU_PD3>;
142 power-domain-names = " 126 power-domain-names = "psci";
143 #cooling-cells = <2>; 127 #cooling-cells = <2>;
144 L2_300: l2-cache { 128 L2_300: l2-cache {
145 compatible = " 129 compatible = "cache";
146 cache-level = <<
147 cache-unified; <<
148 next-level-cac 130 next-level-cache = <&L3_0>;
149 }; 131 };
150 }; 132 };
151 133
152 CPU4: cpu@400 { 134 CPU4: cpu@400 {
153 device_type = "cpu"; 135 device_type = "cpu";
154 compatible = "qcom,kry 136 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 137 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 138 enable-method = "psci";
158 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 140 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 141 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 143 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 145 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 146 power-domains = <&CPU_PD4>;
166 power-domain-names = " 147 power-domain-names = "psci";
167 #cooling-cells = <2>; 148 #cooling-cells = <2>;
168 L2_400: l2-cache { 149 L2_400: l2-cache {
169 compatible = " 150 compatible = "cache";
170 cache-level = <<
171 cache-unified; <<
172 next-level-cac 151 next-level-cache = <&L3_0>;
173 }; 152 };
174 }; 153 };
175 154
176 CPU5: cpu@500 { 155 CPU5: cpu@500 {
177 device_type = "cpu"; 156 device_type = "cpu";
178 compatible = "qcom,kry 157 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 158 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 159 enable-method = "psci";
182 capacity-dmips-mhz = < 160 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 161 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 162 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 163 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 164 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 165 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 167 power-domains = <&CPU_PD5>;
190 power-domain-names = " 168 power-domain-names = "psci";
191 #cooling-cells = <2>; 169 #cooling-cells = <2>;
192 L2_500: l2-cache { 170 L2_500: l2-cache {
193 compatible = " 171 compatible = "cache";
194 cache-level = <<
195 cache-unified; <<
196 next-level-cac 172 next-level-cache = <&L3_0>;
197 }; 173 };
198 }; 174 };
199 175
200 CPU6: cpu@600 { 176 CPU6: cpu@600 {
201 device_type = "cpu"; 177 device_type = "cpu";
202 compatible = "qcom,kry 178 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 179 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 180 enable-method = "psci";
206 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 182 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 183 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 185 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 188 power-domains = <&CPU_PD6>;
214 power-domain-names = " 189 power-domain-names = "psci";
215 #cooling-cells = <2>; 190 #cooling-cells = <2>;
216 L2_600: l2-cache { 191 L2_600: l2-cache {
217 compatible = " 192 compatible = "cache";
218 cache-level = <<
219 cache-unified; <<
220 next-level-cac 193 next-level-cache = <&L3_0>;
221 }; 194 };
222 }; 195 };
223 196
224 CPU7: cpu@700 { 197 CPU7: cpu@700 {
225 device_type = "cpu"; 198 device_type = "cpu";
226 compatible = "qcom,kry 199 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 200 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 201 enable-method = "psci";
230 capacity-dmips-mhz = < 202 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 203 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 204 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 205 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 206 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 209 power-domains = <&CPU_PD7>;
238 power-domain-names = " 210 power-domain-names = "psci";
239 #cooling-cells = <2>; 211 #cooling-cells = <2>;
240 L2_700: l2-cache { 212 L2_700: l2-cache {
241 compatible = " 213 compatible = "cache";
242 cache-level = <<
243 cache-unified; <<
244 next-level-cac 214 next-level-cache = <&L3_0>;
245 }; 215 };
246 }; 216 };
247 217
248 cpu-map { 218 cpu-map {
249 cluster0 { 219 cluster0 {
250 core0 { 220 core0 {
251 cpu = 221 cpu = <&CPU0>;
252 }; 222 };
253 223
254 core1 { 224 core1 {
255 cpu = 225 cpu = <&CPU1>;
256 }; 226 };
257 227
258 core2 { 228 core2 {
259 cpu = 229 cpu = <&CPU2>;
260 }; 230 };
261 231
262 core3 { 232 core3 {
263 cpu = 233 cpu = <&CPU3>;
264 }; 234 };
265 235
266 core4 { 236 core4 {
267 cpu = 237 cpu = <&CPU4>;
268 }; 238 };
269 239
270 core5 { 240 core5 {
271 cpu = 241 cpu = <&CPU5>;
272 }; 242 };
273 243
274 core6 { 244 core6 {
275 cpu = 245 cpu = <&CPU6>;
276 }; 246 };
277 247
278 core7 { 248 core7 {
279 cpu = 249 cpu = <&CPU7>;
280 }; 250 };
281 }; 251 };
282 }; 252 };
283 253
284 idle-states { 254 idle-states {
285 entry-method = "psci"; 255 entry-method = "psci";
286 256
287 LITTLE_CPU_SLEEP_0: cp 257 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 258 compatible = "arm,idle-state";
289 idle-state-nam 259 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 260 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 261 entry-latency-us = <355>;
292 exit-latency-u 262 exit-latency-us = <909>;
293 min-residency- 263 min-residency-us = <3934>;
294 local-timer-st 264 local-timer-stop;
295 }; 265 };
296 266
297 BIG_CPU_SLEEP_0: cpu-s 267 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 268 compatible = "arm,idle-state";
299 idle-state-nam 269 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 270 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 271 entry-latency-us = <241>;
302 exit-latency-u 272 exit-latency-us = <1461>;
303 min-residency- 273 min-residency-us = <4488>;
304 local-timer-st 274 local-timer-stop;
305 }; 275 };
306 }; 276 };
307 277
308 domain-idle-states { 278 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 279 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 280 compatible = "domain-idle-state";
>> 281 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 282 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 283 entry-latency-us = <3263>;
313 exit-latency-u 284 exit-latency-us = <6562>;
314 min-residency- 285 min-residency-us = <9987>;
>> 286 local-timer-stop;
315 }; 287 };
316 }; 288 };
317 }; 289 };
318 290
319 cpu0_opp_table: opp-table-cpu0 { 291 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points 292 compatible = "operating-points-v2";
321 opp-shared; 293 opp-shared;
322 294
323 cpu0_opp1: opp-300000000 { 295 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 296 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 297 opp-peak-kBps = <800000 9600000>;
326 }; 298 };
327 299
328 cpu0_opp2: opp-403200000 { 300 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 301 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 302 opp-peak-kBps = <800000 9600000>;
331 }; 303 };
332 304
333 cpu0_opp3: opp-499200000 { 305 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 306 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 307 opp-peak-kBps = <800000 12902400>;
336 }; 308 };
337 309
338 cpu0_opp4: opp-576000000 { 310 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 311 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 312 opp-peak-kBps = <800000 12902400>;
341 }; 313 };
342 314
343 cpu0_opp5: opp-672000000 { 315 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 316 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 317 opp-peak-kBps = <800000 15974400>;
346 }; 318 };
347 319
348 cpu0_opp6: opp-768000000 { 320 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 321 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 322 opp-peak-kBps = <1804000 19660800>;
351 }; 323 };
352 324
353 cpu0_opp7: opp-844800000 { 325 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 326 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 327 opp-peak-kBps = <1804000 19660800>;
356 }; 328 };
357 329
358 cpu0_opp8: opp-940800000 { 330 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 331 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 332 opp-peak-kBps = <1804000 22732800>;
361 }; 333 };
362 334
363 cpu0_opp9: opp-1036800000 { 335 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 336 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 337 opp-peak-kBps = <1804000 22732800>;
366 }; 338 };
367 339
368 cpu0_opp10: opp-1113600000 { 340 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 341 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 342 opp-peak-kBps = <2188000 25804800>;
371 }; 343 };
372 344
373 cpu0_opp11: opp-1209600000 { 345 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 346 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 347 opp-peak-kBps = <2188000 31948800>;
376 }; 348 };
377 349
378 cpu0_opp12: opp-1305600000 { 350 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 351 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 352 opp-peak-kBps = <3072000 31948800>;
381 }; 353 };
382 354
383 cpu0_opp13: opp-1382400000 { 355 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 356 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 357 opp-peak-kBps = <3072000 31948800>;
386 }; 358 };
387 359
388 cpu0_opp14: opp-1478400000 { 360 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 361 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 362 opp-peak-kBps = <3072000 31948800>;
391 }; 363 };
392 364
393 cpu0_opp15: opp-1555200000 { 365 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 366 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 367 opp-peak-kBps = <3072000 40550400>;
396 }; 368 };
397 369
398 cpu0_opp16: opp-1632000000 { 370 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 371 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 372 opp-peak-kBps = <3072000 40550400>;
401 }; 373 };
402 374
403 cpu0_opp17: opp-1708800000 { 375 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 376 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 377 opp-peak-kBps = <3072000 43008000>;
406 }; 378 };
407 379
408 cpu0_opp18: opp-1785600000 { 380 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 381 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 382 opp-peak-kBps = <3072000 43008000>;
411 }; 383 };
412 }; 384 };
413 385
414 cpu4_opp_table: opp-table-cpu4 { 386 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points 387 compatible = "operating-points-v2";
416 opp-shared; 388 opp-shared;
417 389
418 cpu4_opp1: opp-710400000 { 390 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 391 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 392 opp-peak-kBps = <1804000 15974400>;
421 }; 393 };
422 394
423 cpu4_opp2: opp-825600000 { 395 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 396 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 397 opp-peak-kBps = <2188000 19660800>;
426 }; 398 };
427 399
428 cpu4_opp3: opp-940800000 { 400 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 401 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 402 opp-peak-kBps = <2188000 22732800>;
431 }; 403 };
432 404
433 cpu4_opp4: opp-1056000000 { 405 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 406 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 407 opp-peak-kBps = <3072000 25804800>;
436 }; 408 };
437 409
438 cpu4_opp5: opp-1171200000 { 410 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 411 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 412 opp-peak-kBps = <3072000 31948800>;
441 }; 413 };
442 414
443 cpu4_opp6: opp-1286400000 { 415 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 416 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 417 opp-peak-kBps = <4068000 31948800>;
446 }; 418 };
447 419
448 cpu4_opp7: opp-1401600000 { 420 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 421 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 422 opp-peak-kBps = <4068000 31948800>;
451 }; 423 };
452 424
453 cpu4_opp8: opp-1497600000 { 425 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 426 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 427 opp-peak-kBps = <4068000 40550400>;
456 }; 428 };
457 429
458 cpu4_opp9: opp-1612800000 { 430 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 431 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 432 opp-peak-kBps = <4068000 40550400>;
461 }; 433 };
462 434
463 cpu4_opp10: opp-1708800000 { 435 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 436 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 437 opp-peak-kBps = <4068000 43008000>;
466 }; 438 };
467 439
468 cpu4_opp11: opp-1804800000 { 440 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 441 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 442 opp-peak-kBps = <6220000 43008000>;
471 }; 443 };
472 444
473 cpu4_opp12: opp-1920000000 { 445 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 446 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 447 opp-peak-kBps = <6220000 49152000>;
476 }; 448 };
477 449
478 cpu4_opp13: opp-2016000000 { 450 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 451 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 452 opp-peak-kBps = <7216000 49152000>;
481 }; 453 };
482 454
483 cpu4_opp14: opp-2131200000 { 455 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 456 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 457 opp-peak-kBps = <8368000 49152000>;
486 }; 458 };
487 459
488 cpu4_opp15: opp-2227200000 { 460 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 461 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 462 opp-peak-kBps = <8368000 51609600>;
491 }; 463 };
492 464
493 cpu4_opp16: opp-2323200000 { 465 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 466 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 467 opp-peak-kBps = <8368000 51609600>;
496 }; 468 };
497 469
498 cpu4_opp17: opp-2419200000 { 470 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 471 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 472 opp-peak-kBps = <8368000 51609600>;
501 }; 473 };
502 }; 474 };
503 475
504 cpu7_opp_table: opp-table-cpu7 { 476 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points 477 compatible = "operating-points-v2";
506 opp-shared; 478 opp-shared;
507 479
508 cpu7_opp1: opp-825600000 { 480 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 481 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 19660800>;
511 }; 483 };
512 484
513 cpu7_opp2: opp-940800000 { 485 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 486 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 487 opp-peak-kBps = <2188000 22732800>;
516 }; 488 };
517 489
518 cpu7_opp3: opp-1056000000 { 490 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 491 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 25804800>;
521 }; 493 };
522 494
523 cpu7_opp4: opp-1171200000 { 495 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 496 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 497 opp-peak-kBps = <3072000 31948800>;
526 }; 498 };
527 499
528 cpu7_opp5: opp-1286400000 { 500 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 501 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 31948800>;
531 }; 503 };
532 504
533 cpu7_opp6: opp-1401600000 { 505 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 506 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 31948800>;
536 }; 508 };
537 509
538 cpu7_opp7: opp-1497600000 { 510 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 511 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 40550400>;
541 }; 513 };
542 514
543 cpu7_opp8: opp-1612800000 { 515 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 516 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 517 opp-peak-kBps = <4068000 40550400>;
546 }; 518 };
547 519
548 cpu7_opp9: opp-1708800000 { 520 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 521 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 522 opp-peak-kBps = <4068000 43008000>;
551 }; 523 };
552 524
553 cpu7_opp10: opp-1804800000 { 525 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 526 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 527 opp-peak-kBps = <6220000 43008000>;
556 }; 528 };
557 529
558 cpu7_opp11: opp-1920000000 { 530 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 531 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 532 opp-peak-kBps = <6220000 49152000>;
561 }; 533 };
562 534
563 cpu7_opp12: opp-2016000000 { 535 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 536 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 537 opp-peak-kBps = <7216000 49152000>;
566 }; 538 };
567 539
568 cpu7_opp13: opp-2131200000 { 540 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 541 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 542 opp-peak-kBps = <8368000 49152000>;
571 }; 543 };
572 544
573 cpu7_opp14: opp-2227200000 { 545 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 546 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 547 opp-peak-kBps = <8368000 51609600>;
576 }; 548 };
577 549
578 cpu7_opp15: opp-2323200000 { 550 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 551 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 552 opp-peak-kBps = <8368000 51609600>;
581 }; 553 };
582 554
583 cpu7_opp16: opp-2419200000 { 555 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 556 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
586 }; 558 };
587 559
588 cpu7_opp17: opp-2534400000 { 560 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 561 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
591 }; 563 };
592 564
593 cpu7_opp18: opp-2649600000 { 565 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 566 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 567 opp-peak-kBps = <8368000 51609600>;
596 }; 568 };
597 569
598 cpu7_opp19: opp-2745600000 { 570 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 571 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 572 opp-peak-kBps = <8368000 51609600>;
601 }; 573 };
602 574
603 cpu7_opp20: opp-2841600000 { 575 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 576 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 577 opp-peak-kBps = <8368000 51609600>;
606 }; 578 };
607 }; 579 };
608 580
609 firmware { 581 firmware {
610 scm: scm { 582 scm: scm {
611 compatible = "qcom,scm 583 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 584 #reset-cells = <1>;
613 }; 585 };
614 }; 586 };
615 587
616 memory@80000000 { 588 memory@80000000 {
617 device_type = "memory"; 589 device_type = "memory";
618 /* We expect the bootloader to 590 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 591 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 592 };
621 593
622 pmu { 594 pmu {
623 compatible = "arm,armv8-pmuv3" 595 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 596 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 597 };
626 598
627 psci { 599 psci {
628 compatible = "arm,psci-1.0"; 600 compatible = "arm,psci-1.0";
629 method = "smc"; 601 method = "smc";
630 602
631 CPU_PD0: power-domain-cpu0 { !! 603 CPU_PD0: cpu0 {
632 #power-domain-cells = 604 #power-domain-cells = <0>;
633 power-domains = <&CLUS 605 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 606 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 607 };
636 608
637 CPU_PD1: power-domain-cpu1 { !! 609 CPU_PD1: cpu1 {
638 #power-domain-cells = 610 #power-domain-cells = <0>;
639 power-domains = <&CLUS 611 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 612 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 613 };
642 614
643 CPU_PD2: power-domain-cpu2 { !! 615 CPU_PD2: cpu2 {
644 #power-domain-cells = 616 #power-domain-cells = <0>;
645 power-domains = <&CLUS 617 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 618 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 619 };
648 620
649 CPU_PD3: power-domain-cpu3 { !! 621 CPU_PD3: cpu3 {
650 #power-domain-cells = 622 #power-domain-cells = <0>;
651 power-domains = <&CLUS 623 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 624 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 625 };
654 626
655 CPU_PD4: power-domain-cpu4 { !! 627 CPU_PD4: cpu4 {
656 #power-domain-cells = 628 #power-domain-cells = <0>;
657 power-domains = <&CLUS 629 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 630 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 631 };
660 632
661 CPU_PD5: power-domain-cpu5 { !! 633 CPU_PD5: cpu5 {
662 #power-domain-cells = 634 #power-domain-cells = <0>;
663 power-domains = <&CLUS 635 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 636 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 637 };
666 638
667 CPU_PD6: power-domain-cpu6 { !! 639 CPU_PD6: cpu6 {
668 #power-domain-cells = 640 #power-domain-cells = <0>;
669 power-domains = <&CLUS 641 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 642 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 643 };
672 644
673 CPU_PD7: power-domain-cpu7 { !! 645 CPU_PD7: cpu7 {
674 #power-domain-cells = 646 #power-domain-cells = <0>;
675 power-domains = <&CLUS 647 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 648 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 649 };
678 650
679 CLUSTER_PD: power-domain-cpu-c !! 651 CLUSTER_PD: cpu-cluster0 {
680 #power-domain-cells = 652 #power-domain-cells = <0>;
681 domain-idle-states = < 653 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 654 };
683 }; 655 };
684 656
685 reserved-memory { 657 reserved-memory {
686 #address-cells = <2>; 658 #address-cells = <2>;
687 #size-cells = <2>; 659 #size-cells = <2>;
688 ranges; 660 ranges;
689 661
690 hyp_mem: memory@85700000 { 662 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 663 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 664 no-map;
693 }; 665 };
694 666
695 xbl_mem: memory@85d00000 { 667 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 668 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 669 no-map;
698 }; 670 };
699 671
700 aop_mem: memory@85f00000 { 672 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 673 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 674 no-map;
703 }; 675 };
704 676
705 aop_cmd_db: memory@85f20000 { 677 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 678 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 679 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 680 no-map;
709 }; 681 };
710 682
711 smem_mem: memory@86000000 { 683 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 684 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 685 no-map;
714 }; 686 };
715 687
716 tz_mem: memory@86200000 { 688 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 689 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 690 no-map;
719 }; 691 };
720 692
721 rmtfs_mem: memory@89b00000 { 693 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 694 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 695 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 696 no-map;
725 697
726 qcom,client-id = <1>; 698 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 699 qcom,vmid = <15>;
728 }; 700 };
729 701
730 camera_mem: memory@8b700000 { 702 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 703 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 704 no-map;
733 }; 705 };
734 706
735 wlan_mem: memory@8bc00000 { 707 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 708 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 709 no-map;
738 }; 710 };
739 711
740 npu_mem: memory@8bd80000 { 712 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 713 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 714 no-map;
743 }; 715 };
744 716
745 adsp_mem: memory@8be00000 { 717 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 718 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 719 no-map;
748 }; 720 };
749 721
750 mpss_mem: memory@8d800000 { 722 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 723 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 724 no-map;
753 }; 725 };
754 726
755 venus_mem: memory@96e00000 { 727 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 728 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 729 no-map;
758 }; 730 };
759 731
760 slpi_mem: memory@97300000 { 732 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 733 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 734 no-map;
763 }; 735 };
764 736
765 ipa_fw_mem: memory@98700000 { 737 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 738 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 739 no-map;
768 }; 740 };
769 741
770 ipa_gsi_mem: memory@98710000 { 742 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 743 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 744 no-map;
773 }; 745 };
774 746
775 gpu_mem: memory@98715000 { 747 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 748 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 749 no-map;
778 }; 750 };
779 751
780 spss_mem: memory@98800000 { 752 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 753 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 754 no-map;
783 }; 755 };
784 756
785 cdsp_mem: memory@98900000 { 757 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 758 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 759 no-map;
788 }; 760 };
789 761
790 qseecom_mem: memory@9e400000 { 762 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 763 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 764 no-map;
793 }; 765 };
794 }; 766 };
795 767
796 smem { 768 smem {
797 compatible = "qcom,smem"; 769 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 770 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 771 hwlocks = <&tcsr_mutex 3>;
800 }; 772 };
801 773
802 smp2p-cdsp { 774 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 775 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 776 qcom,smem = <94>, <432>;
805 777
806 interrupts = <GIC_SPI 576 IRQ_ 778 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 779
808 mboxes = <&apss_shared 6>; 780 mboxes = <&apss_shared 6>;
809 781
810 qcom,local-pid = <0>; 782 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 783 qcom,remote-pid = <5>;
812 784
813 cdsp_smp2p_out: master-kernel 785 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 786 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 787 #qcom,smem-state-cells = <1>;
816 }; 788 };
817 789
818 cdsp_smp2p_in: slave-kernel { 790 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 791 qcom,entry-name = "slave-kernel";
820 792
821 interrupt-controller; 793 interrupt-controller;
822 #interrupt-cells = <2> 794 #interrupt-cells = <2>;
823 }; 795 };
824 }; 796 };
825 797
826 smp2p-lpass { 798 smp2p-lpass {
827 compatible = "qcom,smp2p"; 799 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 800 qcom,smem = <443>, <429>;
829 801
830 interrupts = <GIC_SPI 158 IRQ_ 802 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 803
832 mboxes = <&apss_shared 10>; 804 mboxes = <&apss_shared 10>;
833 805
834 qcom,local-pid = <0>; 806 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 807 qcom,remote-pid = <2>;
836 808
837 adsp_smp2p_out: master-kernel 809 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 810 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 811 #qcom,smem-state-cells = <1>;
840 }; 812 };
841 813
842 adsp_smp2p_in: slave-kernel { 814 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 815 qcom,entry-name = "slave-kernel";
844 816
845 interrupt-controller; 817 interrupt-controller;
846 #interrupt-cells = <2> 818 #interrupt-cells = <2>;
847 }; 819 };
848 }; 820 };
849 821
850 smp2p-mpss { 822 smp2p-mpss {
851 compatible = "qcom,smp2p"; 823 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 824 qcom,smem = <435>, <428>;
853 825
854 interrupts = <GIC_SPI 451 IRQ_ 826 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 827
856 mboxes = <&apss_shared 14>; 828 mboxes = <&apss_shared 14>;
857 829
858 qcom,local-pid = <0>; 830 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 831 qcom,remote-pid = <1>;
860 832
861 modem_smp2p_out: master-kernel 833 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 834 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 835 #qcom,smem-state-cells = <1>;
864 }; 836 };
865 837
866 modem_smp2p_in: slave-kernel { 838 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 839 qcom,entry-name = "slave-kernel";
868 840
869 interrupt-controller; 841 interrupt-controller;
870 #interrupt-cells = <2> 842 #interrupt-cells = <2>;
871 }; 843 };
872 }; 844 };
873 845
874 smp2p-slpi { 846 smp2p-slpi {
875 compatible = "qcom,smp2p"; 847 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 848 qcom,smem = <481>, <430>;
877 849
878 interrupts = <GIC_SPI 172 IRQ_ 850 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 851
880 mboxes = <&apss_shared 26>; 852 mboxes = <&apss_shared 26>;
881 853
882 qcom,local-pid = <0>; 854 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 855 qcom,remote-pid = <3>;
884 856
885 slpi_smp2p_out: master-kernel 857 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 858 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 859 #qcom,smem-state-cells = <1>;
888 }; 860 };
889 861
890 slpi_smp2p_in: slave-kernel { 862 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 863 qcom,entry-name = "slave-kernel";
892 864
893 interrupt-controller; 865 interrupt-controller;
894 #interrupt-cells = <2> 866 #interrupt-cells = <2>;
895 }; 867 };
896 }; 868 };
897 869
898 soc: soc@0 { 870 soc: soc@0 {
899 #address-cells = <2>; 871 #address-cells = <2>;
900 #size-cells = <2>; 872 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 873 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 874 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 875 compatible = "simple-bus";
904 876
905 gcc: clock-controller@100000 { 877 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 878 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 879 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 880 #clock-cells = <1>;
909 #reset-cells = <1>; 881 #reset-cells = <1>;
910 #power-domain-cells = 882 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 883 clock-names = "bi_tcxo",
912 "sleep_c 884 "sleep_clk";
913 clocks = <&rpmhcc RPMH 885 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 886 <&sleep_clk>;
915 }; 887 };
916 888
917 gpi_dma0: dma-controller@80000 889 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 890 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 !! 891 reg = <0 0x800000 0 0x60000>;
920 interrupts = <GIC_SPI 892 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 893 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 894 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 895 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 896 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 897 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 898 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 899 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 900 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 901 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 902 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 903 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 904 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 905 dma-channels = <13>;
934 dma-channel-mask = <0x 906 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 907 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 908 #dma-cells = <3>;
937 status = "disabled"; 909 status = "disabled";
938 }; 910 };
939 911
940 ethernet: ethernet@20000 { 912 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 913 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 914 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 915 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 916 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 917 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 918 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 919 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 920 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 921 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 922 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 923 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 924 interrupt-names = "macirq", "eth_lpi";
953 925
954 power-domains = <&gcc 926 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 927 resets = <&gcc GCC_EMAC_BCR>;
956 928
957 iommus = <&apps_smmu 0 !! 929 iommus = <&apps_smmu 0x3C0 0x0>;
958 930
959 snps,tso; 931 snps,tso;
960 rx-fifo-depth = <4096> 932 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 933 tx-fifo-depth = <4096>;
962 934
963 status = "disabled"; 935 status = "disabled";
964 }; 936 };
965 937
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 938
978 qupv3_id_0: geniqup@8c0000 { 939 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 940 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 941 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 942 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 943 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 944 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 945 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 946 #address-cells = <2>;
986 #size-cells = <2>; 947 #size-cells = <2>;
987 ranges; 948 ranges;
988 status = "disabled"; 949 status = "disabled";
989 950
990 i2c0: i2c@880000 { 951 i2c0: i2c@880000 {
991 compatible = " 952 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 953 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 954 clock-names = "se";
994 clocks = <&gcc 955 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 956 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 957 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 958 dma-names = "tx", "rx";
998 pinctrl-names 959 pinctrl-names = "default";
999 pinctrl-0 = <& 960 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 962 #address-cells = <1>;
1002 #size-cells = 963 #size-cells = <0>;
1003 status = "dis 964 status = "disabled";
1004 }; 965 };
1005 966
1006 spi0: spi@880000 { 967 spi0: spi@880000 {
1007 compatible = 968 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 !! 969 reg = <0 0x880000 0 0x4000>;
1009 reg-names = " 970 reg-names = "se";
1010 clock-names = 971 clock-names = "se";
1011 clocks = <&gc 972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 973 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 974 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 975 dma-names = "tx", "rx";
1015 pinctrl-names 976 pinctrl-names = "default";
1016 pinctrl-0 = < 977 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 978 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 979 spi-max-frequency = <50000000>;
1019 #address-cell 980 #address-cells = <1>;
1020 #size-cells = 981 #size-cells = <0>;
1021 status = "dis 982 status = "disabled";
1022 }; 983 };
1023 984
1024 i2c1: i2c@884000 { 985 i2c1: i2c@884000 {
1025 compatible = 986 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 987 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 988 clock-names = "se";
1028 clocks = <&gc 989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 990 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 991 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 992 dma-names = "tx", "rx";
1032 pinctrl-names 993 pinctrl-names = "default";
1033 pinctrl-0 = < 994 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 995 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 996 #address-cells = <1>;
1036 #size-cells = 997 #size-cells = <0>;
1037 status = "dis 998 status = "disabled";
1038 }; 999 };
1039 1000
1040 spi1: spi@884000 { 1001 spi1: spi@884000 {
1041 compatible = 1002 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 !! 1003 reg = <0 0x884000 0 0x4000>;
1043 reg-names = " 1004 reg-names = "se";
1044 clock-names = 1005 clock-names = "se";
1045 clocks = <&gc 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1007 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1008 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1009 dma-names = "tx", "rx";
1049 pinctrl-names 1010 pinctrl-names = "default";
1050 pinctrl-0 = < 1011 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1012 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1013 spi-max-frequency = <50000000>;
1053 #address-cell 1014 #address-cells = <1>;
1054 #size-cells = 1015 #size-cells = <0>;
1055 status = "dis 1016 status = "disabled";
1056 }; 1017 };
1057 1018
1058 i2c2: i2c@888000 { 1019 i2c2: i2c@888000 {
1059 compatible = 1020 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1021 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1022 clock-names = "se";
1062 clocks = <&gc 1023 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1024 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1025 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1026 dma-names = "tx", "rx";
1066 pinctrl-names 1027 pinctrl-names = "default";
1067 pinctrl-0 = < 1028 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1029 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1030 #address-cells = <1>;
1070 #size-cells = 1031 #size-cells = <0>;
1071 status = "dis 1032 status = "disabled";
1072 }; 1033 };
1073 1034
1074 spi2: spi@888000 { 1035 spi2: spi@888000 {
1075 compatible = 1036 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 !! 1037 reg = <0 0x888000 0 0x4000>;
1077 reg-names = " 1038 reg-names = "se";
1078 clock-names = 1039 clock-names = "se";
1079 clocks = <&gc 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1041 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1042 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1043 dma-names = "tx", "rx";
1083 pinctrl-names 1044 pinctrl-names = "default";
1084 pinctrl-0 = < 1045 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1046 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1047 spi-max-frequency = <50000000>;
1087 #address-cell 1048 #address-cells = <1>;
1088 #size-cells = 1049 #size-cells = <0>;
1089 status = "dis 1050 status = "disabled";
1090 }; 1051 };
1091 1052
1092 i2c3: i2c@88c000 { 1053 i2c3: i2c@88c000 {
1093 compatible = 1054 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1055 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1056 clock-names = "se";
1096 clocks = <&gc 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1058 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1059 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1060 dma-names = "tx", "rx";
1100 pinctrl-names 1061 pinctrl-names = "default";
1101 pinctrl-0 = < 1062 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1063 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1064 #address-cells = <1>;
1104 #size-cells = 1065 #size-cells = <0>;
1105 status = "dis 1066 status = "disabled";
1106 }; 1067 };
1107 1068
1108 spi3: spi@88c000 { 1069 spi3: spi@88c000 {
1109 compatible = 1070 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 !! 1071 reg = <0 0x88c000 0 0x4000>;
1111 reg-names = " 1072 reg-names = "se";
1112 clock-names = 1073 clock-names = "se";
1113 clocks = <&gc 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1075 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1076 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1077 dma-names = "tx", "rx";
1117 pinctrl-names 1078 pinctrl-names = "default";
1118 pinctrl-0 = < 1079 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1080 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1081 spi-max-frequency = <50000000>;
1121 #address-cell 1082 #address-cells = <1>;
1122 #size-cells = 1083 #size-cells = <0>;
1123 status = "dis 1084 status = "disabled";
1124 }; 1085 };
1125 1086
1126 i2c4: i2c@890000 { 1087 i2c4: i2c@890000 {
1127 compatible = 1088 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1089 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1090 clock-names = "se";
1130 clocks = <&gc 1091 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1094 dma-names = "tx", "rx";
1134 pinctrl-names 1095 pinctrl-names = "default";
1135 pinctrl-0 = < 1096 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1097 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1098 #address-cells = <1>;
1138 #size-cells = 1099 #size-cells = <0>;
1139 status = "dis 1100 status = "disabled";
1140 }; 1101 };
1141 1102
1142 spi4: spi@890000 { 1103 spi4: spi@890000 {
1143 compatible = 1104 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 !! 1105 reg = <0 0x890000 0 0x4000>;
1145 reg-names = " 1106 reg-names = "se";
1146 clock-names = 1107 clock-names = "se";
1147 clocks = <&gc 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1109 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1110 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1111 dma-names = "tx", "rx";
1151 pinctrl-names 1112 pinctrl-names = "default";
1152 pinctrl-0 = < 1113 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1114 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1115 spi-max-frequency = <50000000>;
1155 #address-cell 1116 #address-cells = <1>;
1156 #size-cells = 1117 #size-cells = <0>;
1157 status = "dis 1118 status = "disabled";
1158 }; 1119 };
1159 1120
1160 i2c5: i2c@894000 { 1121 i2c5: i2c@894000 {
1161 compatible = 1122 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1123 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1124 clock-names = "se";
1164 clocks = <&gc 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1126 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1127 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1128 dma-names = "tx", "rx";
1168 pinctrl-names 1129 pinctrl-names = "default";
1169 pinctrl-0 = < 1130 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1131 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1132 #address-cells = <1>;
1172 #size-cells = 1133 #size-cells = <0>;
1173 status = "dis 1134 status = "disabled";
1174 }; 1135 };
1175 1136
1176 spi5: spi@894000 { 1137 spi5: spi@894000 {
1177 compatible = 1138 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 !! 1139 reg = <0 0x894000 0 0x4000>;
1179 reg-names = " 1140 reg-names = "se";
1180 clock-names = 1141 clock-names = "se";
1181 clocks = <&gc 1142 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1143 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1144 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1145 dma-names = "tx", "rx";
1185 pinctrl-names 1146 pinctrl-names = "default";
1186 pinctrl-0 = < 1147 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1149 spi-max-frequency = <50000000>;
1189 #address-cell 1150 #address-cells = <1>;
1190 #size-cells = 1151 #size-cells = <0>;
1191 status = "dis 1152 status = "disabled";
1192 }; 1153 };
1193 1154
1194 i2c6: i2c@898000 { 1155 i2c6: i2c@898000 {
1195 compatible = 1156 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1157 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1158 clock-names = "se";
1198 clocks = <&gc 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1160 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1161 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1162 dma-names = "tx", "rx";
1202 pinctrl-names 1163 pinctrl-names = "default";
1203 pinctrl-0 = < 1164 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1165 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1166 #address-cells = <1>;
1206 #size-cells = 1167 #size-cells = <0>;
1207 status = "dis 1168 status = "disabled";
1208 }; 1169 };
1209 1170
1210 spi6: spi@898000 { 1171 spi6: spi@898000 {
1211 compatible = 1172 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 !! 1173 reg = <0 0x898000 0 0x4000>;
1213 reg-names = " 1174 reg-names = "se";
1214 clock-names = 1175 clock-names = "se";
1215 clocks = <&gc 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1177 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1178 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1179 dma-names = "tx", "rx";
1219 pinctrl-names 1180 pinctrl-names = "default";
1220 pinctrl-0 = < 1181 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1182 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1183 spi-max-frequency = <50000000>;
1223 #address-cell 1184 #address-cells = <1>;
1224 #size-cells = 1185 #size-cells = <0>;
1225 status = "dis 1186 status = "disabled";
1226 }; 1187 };
1227 1188
1228 i2c7: i2c@89c000 { 1189 i2c7: i2c@89c000 {
1229 compatible = 1190 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1191 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1192 clock-names = "se";
1232 clocks = <&gc 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1194 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1195 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1196 dma-names = "tx", "rx";
1236 pinctrl-names 1197 pinctrl-names = "default";
1237 pinctrl-0 = < 1198 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = !! 1199 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1200 #address-cells = <1>;
1240 #size-cells = 1201 #size-cells = <0>;
1241 status = "dis 1202 status = "disabled";
1242 }; 1203 };
1243 1204
1244 spi7: spi@89c000 { 1205 spi7: spi@89c000 {
1245 compatible = 1206 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 !! 1207 reg = <0 0x89c000 0 0x4000>;
1247 reg-names = " 1208 reg-names = "se";
1248 clock-names = 1209 clock-names = "se";
1249 clocks = <&gc 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1211 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1212 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1213 dma-names = "tx", "rx";
1253 pinctrl-names 1214 pinctrl-names = "default";
1254 pinctrl-0 = < 1215 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1216 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1217 spi-max-frequency = <50000000>;
1257 #address-cell 1218 #address-cells = <1>;
1258 #size-cells = 1219 #size-cells = <0>;
1259 status = "dis 1220 status = "disabled";
1260 }; 1221 };
1261 }; 1222 };
1262 1223
1263 gpi_dma1: dma-controller@a000 1224 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm 1225 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 !! 1226 reg = <0 0xa00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1227 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1228 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1229 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1230 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1231 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1232 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1233 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1234 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1235 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1236 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1237 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1238 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1239 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1240 dma-channels = <13>;
1280 dma-channel-mask = <0 1241 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1242 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1243 #dma-cells = <3>;
1283 status = "disabled"; 1244 status = "disabled";
1284 }; 1245 };
1285 1246
1286 qupv3_id_1: geniqup@ac0000 { 1247 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1248 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1249 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1250 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1251 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1252 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1253 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1254 #address-cells = <2>;
1294 #size-cells = <2>; 1255 #size-cells = <2>;
1295 ranges; 1256 ranges;
1296 status = "disabled"; 1257 status = "disabled";
1297 1258
1298 i2c8: i2c@a80000 { 1259 i2c8: i2c@a80000 {
1299 compatible = 1260 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1261 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1262 clock-names = "se";
1302 clocks = <&gc 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1264 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1265 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1266 dma-names = "tx", "rx";
1306 pinctrl-names 1267 pinctrl-names = "default";
1307 pinctrl-0 = < 1268 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1269 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1270 #address-cells = <1>;
1310 #size-cells = 1271 #size-cells = <0>;
1311 status = "dis 1272 status = "disabled";
1312 }; 1273 };
1313 1274
1314 spi8: spi@a80000 { 1275 spi8: spi@a80000 {
1315 compatible = 1276 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 !! 1277 reg = <0 0xa80000 0 0x4000>;
1317 reg-names = " 1278 reg-names = "se";
1318 clock-names = 1279 clock-names = "se";
1319 clocks = <&gc 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1282 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1283 dma-names = "tx", "rx";
1323 pinctrl-names 1284 pinctrl-names = "default";
1324 pinctrl-0 = < 1285 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1286 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1287 spi-max-frequency = <50000000>;
1327 #address-cell 1288 #address-cells = <1>;
1328 #size-cells = 1289 #size-cells = <0>;
1329 status = "dis 1290 status = "disabled";
1330 }; 1291 };
1331 1292
1332 i2c9: i2c@a84000 { 1293 i2c9: i2c@a84000 {
1333 compatible = 1294 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1295 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1296 clock-names = "se";
1336 clocks = <&gc 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1298 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1299 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1300 dma-names = "tx", "rx";
1340 pinctrl-names 1301 pinctrl-names = "default";
1341 pinctrl-0 = < 1302 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1303 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1304 #address-cells = <1>;
1344 #size-cells = 1305 #size-cells = <0>;
1345 status = "dis 1306 status = "disabled";
1346 }; 1307 };
1347 1308
1348 spi9: spi@a84000 { 1309 spi9: spi@a84000 {
1349 compatible = 1310 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 !! 1311 reg = <0 0xa84000 0 0x4000>;
1351 reg-names = " 1312 reg-names = "se";
1352 clock-names = 1313 clock-names = "se";
1353 clocks = <&gc 1314 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1315 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1316 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1317 dma-names = "tx", "rx";
1357 pinctrl-names 1318 pinctrl-names = "default";
1358 pinctrl-0 = < 1319 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1320 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1321 spi-max-frequency = <50000000>;
1361 #address-cell 1322 #address-cells = <1>;
1362 #size-cells = 1323 #size-cells = <0>;
1363 status = "dis 1324 status = "disabled";
1364 }; 1325 };
1365 1326
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 1327 i2c10: i2c@a88000 {
1378 compatible = 1328 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1329 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1330 clock-names = "se";
1381 clocks = <&gc 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1334 dma-names = "tx", "rx";
1385 pinctrl-names 1335 pinctrl-names = "default";
1386 pinctrl-0 = < 1336 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1337 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1338 #address-cells = <1>;
1389 #size-cells = 1339 #size-cells = <0>;
1390 status = "dis 1340 status = "disabled";
1391 }; 1341 };
1392 1342
1393 spi10: spi@a88000 { 1343 spi10: spi@a88000 {
1394 compatible = 1344 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 !! 1345 reg = <0 0xa88000 0 0x4000>;
1396 reg-names = " 1346 reg-names = "se";
1397 clock-names = 1347 clock-names = "se";
1398 clocks = <&gc 1348 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1349 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1350 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1351 dma-names = "tx", "rx";
1402 pinctrl-names 1352 pinctrl-names = "default";
1403 pinctrl-0 = < 1353 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1354 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1355 spi-max-frequency = <50000000>;
1406 #address-cell 1356 #address-cells = <1>;
1407 #size-cells = 1357 #size-cells = <0>;
1408 status = "dis 1358 status = "disabled";
1409 }; 1359 };
1410 1360
1411 i2c11: i2c@a8c000 { 1361 i2c11: i2c@a8c000 {
1412 compatible = 1362 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1363 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1364 clock-names = "se";
1415 clocks = <&gc 1365 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1366 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1367 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1368 dma-names = "tx", "rx";
1419 pinctrl-names 1369 pinctrl-names = "default";
1420 pinctrl-0 = < 1370 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1371 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1372 #address-cells = <1>;
1423 #size-cells = 1373 #size-cells = <0>;
1424 status = "dis 1374 status = "disabled";
1425 }; 1375 };
1426 1376
1427 spi11: spi@a8c000 { 1377 spi11: spi@a8c000 {
1428 compatible = 1378 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 !! 1379 reg = <0 0xa8c000 0 0x4000>;
1430 reg-names = " 1380 reg-names = "se";
1431 clock-names = 1381 clock-names = "se";
1432 clocks = <&gc 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1383 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1384 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1385 dma-names = "tx", "rx";
1436 pinctrl-names 1386 pinctrl-names = "default";
1437 pinctrl-0 = < 1387 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1389 spi-max-frequency = <50000000>;
1440 #address-cell 1390 #address-cells = <1>;
1441 #size-cells = 1391 #size-cells = <0>;
1442 status = "dis 1392 status = "disabled";
1443 }; 1393 };
1444 1394
1445 uart2: serial@a90000 1395 uart2: serial@a90000 {
1446 compatible = 1396 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1397 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1398 clock-names = "se";
1449 clocks = <&gc 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1400 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1401 status = "disabled";
1452 }; 1402 };
1453 1403
1454 i2c12: i2c@a90000 { 1404 i2c12: i2c@a90000 {
1455 compatible = 1405 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1406 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1407 clock-names = "se";
1458 clocks = <&gc 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1411 dma-names = "tx", "rx";
1462 pinctrl-names 1412 pinctrl-names = "default";
1463 pinctrl-0 = < 1413 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1414 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1415 #address-cells = <1>;
1466 #size-cells = 1416 #size-cells = <0>;
1467 status = "dis 1417 status = "disabled";
1468 }; 1418 };
1469 1419
1470 spi12: spi@a90000 { 1420 spi12: spi@a90000 {
1471 compatible = 1421 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 !! 1422 reg = <0 0xa90000 0 0x4000>;
1473 reg-names = " 1423 reg-names = "se";
1474 clock-names = 1424 clock-names = "se";
1475 clocks = <&gc 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1426 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1427 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1428 dma-names = "tx", "rx";
1479 pinctrl-names 1429 pinctrl-names = "default";
1480 pinctrl-0 = < 1430 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1431 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1432 spi-max-frequency = <50000000>;
1483 #address-cell 1433 #address-cells = <1>;
1484 #size-cells = 1434 #size-cells = <0>;
1485 status = "dis 1435 status = "disabled";
1486 }; 1436 };
1487 1437
1488 i2c16: i2c@94000 { 1438 i2c16: i2c@94000 {
1489 compatible = 1439 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 !! 1440 reg = <0 0x0094000 0 0x4000>;
1491 clock-names = 1441 clock-names = "se";
1492 clocks = <&gc 1442 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1443 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1444 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1445 dma-names = "tx", "rx";
1496 pinctrl-names 1446 pinctrl-names = "default";
1497 pinctrl-0 = < 1447 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1448 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1449 #address-cells = <1>;
1500 #size-cells = 1450 #size-cells = <0>;
1501 status = "dis 1451 status = "disabled";
1502 }; 1452 };
1503 1453
1504 spi16: spi@a94000 { 1454 spi16: spi@a94000 {
1505 compatible = 1455 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 !! 1456 reg = <0 0xa94000 0 0x4000>;
1507 reg-names = " 1457 reg-names = "se";
1508 clock-names = 1458 clock-names = "se";
1509 clocks = <&gc 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1460 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1461 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1462 dma-names = "tx", "rx";
1513 pinctrl-names 1463 pinctrl-names = "default";
1514 pinctrl-0 = < 1464 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1465 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1466 spi-max-frequency = <50000000>;
1517 #address-cell 1467 #address-cells = <1>;
1518 #size-cells = 1468 #size-cells = <0>;
1519 status = "dis 1469 status = "disabled";
1520 }; 1470 };
1521 }; 1471 };
1522 1472
1523 gpi_dma2: dma-controller@c000 1473 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm 1474 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 !! 1475 reg = <0 0xc00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1476 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1477 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1478 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1479 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1480 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1481 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1482 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1483 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1484 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1485 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1486 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1487 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1488 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1489 dma-channels = <13>;
1540 dma-channel-mask = <0 1490 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1491 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1492 #dma-cells = <3>;
1543 status = "disabled"; 1493 status = "disabled";
1544 }; 1494 };
1545 1495
1546 qupv3_id_2: geniqup@cc0000 { 1496 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1497 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1498 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1499
1550 clock-names = "m-ahb" 1500 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1501 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1502 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1503 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1504 #address-cells = <2>;
1555 #size-cells = <2>; 1505 #size-cells = <2>;
1556 ranges; 1506 ranges;
1557 status = "disabled"; 1507 status = "disabled";
1558 1508
1559 i2c17: i2c@c80000 { 1509 i2c17: i2c@c80000 {
1560 compatible = 1510 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1511 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1512 clock-names = "se";
1563 clocks = <&gc 1513 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1514 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1515 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1516 dma-names = "tx", "rx";
1567 pinctrl-names 1517 pinctrl-names = "default";
1568 pinctrl-0 = < 1518 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1519 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1520 #address-cells = <1>;
1571 #size-cells = 1521 #size-cells = <0>;
1572 status = "dis 1522 status = "disabled";
1573 }; 1523 };
1574 1524
1575 spi17: spi@c80000 { 1525 spi17: spi@c80000 {
1576 compatible = 1526 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 !! 1527 reg = <0 0xc80000 0 0x4000>;
1578 reg-names = " 1528 reg-names = "se";
1579 clock-names = 1529 clock-names = "se";
1580 clocks = <&gc 1530 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1531 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1532 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1533 dma-names = "tx", "rx";
1584 pinctrl-names 1534 pinctrl-names = "default";
1585 pinctrl-0 = < 1535 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1536 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1537 spi-max-frequency = <50000000>;
1588 #address-cell 1538 #address-cells = <1>;
1589 #size-cells = 1539 #size-cells = <0>;
1590 status = "dis 1540 status = "disabled";
1591 }; 1541 };
1592 1542
1593 i2c18: i2c@c84000 { 1543 i2c18: i2c@c84000 {
1594 compatible = 1544 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1545 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1546 clock-names = "se";
1597 clocks = <&gc 1547 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1548 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1549 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1550 dma-names = "tx", "rx";
1601 pinctrl-names 1551 pinctrl-names = "default";
1602 pinctrl-0 = < 1552 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1553 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1554 #address-cells = <1>;
1605 #size-cells = 1555 #size-cells = <0>;
1606 status = "dis 1556 status = "disabled";
1607 }; 1557 };
1608 1558
1609 spi18: spi@c84000 { 1559 spi18: spi@c84000 {
1610 compatible = 1560 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 !! 1561 reg = <0 0xc84000 0 0x4000>;
1612 reg-names = " 1562 reg-names = "se";
1613 clock-names = 1563 clock-names = "se";
1614 clocks = <&gc 1564 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1565 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1566 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1567 dma-names = "tx", "rx";
1618 pinctrl-names 1568 pinctrl-names = "default";
1619 pinctrl-0 = < 1569 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1570 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1571 spi-max-frequency = <50000000>;
1622 #address-cell 1572 #address-cells = <1>;
1623 #size-cells = 1573 #size-cells = <0>;
1624 status = "dis 1574 status = "disabled";
1625 }; 1575 };
1626 1576
1627 i2c19: i2c@c88000 { 1577 i2c19: i2c@c88000 {
1628 compatible = 1578 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1579 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1580 clock-names = "se";
1631 clocks = <&gc 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1582 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1583 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1584 dma-names = "tx", "rx";
1635 pinctrl-names 1585 pinctrl-names = "default";
1636 pinctrl-0 = < 1586 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1587 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1588 #address-cells = <1>;
1639 #size-cells = 1589 #size-cells = <0>;
1640 status = "dis 1590 status = "disabled";
1641 }; 1591 };
1642 1592
1643 spi19: spi@c88000 { 1593 spi19: spi@c88000 {
1644 compatible = 1594 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 !! 1595 reg = <0 0xc88000 0 0x4000>;
1646 reg-names = " 1596 reg-names = "se";
1647 clock-names = 1597 clock-names = "se";
1648 clocks = <&gc 1598 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1599 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1600 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1601 dma-names = "tx", "rx";
1652 pinctrl-names 1602 pinctrl-names = "default";
1653 pinctrl-0 = < 1603 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1604 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1605 spi-max-frequency = <50000000>;
1656 #address-cell 1606 #address-cells = <1>;
1657 #size-cells = 1607 #size-cells = <0>;
1658 status = "dis 1608 status = "disabled";
1659 }; 1609 };
1660 1610
1661 i2c13: i2c@c8c000 { 1611 i2c13: i2c@c8c000 {
1662 compatible = 1612 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1613 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1614 clock-names = "se";
1665 clocks = <&gc 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1616 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1617 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1618 dma-names = "tx", "rx";
1669 pinctrl-names 1619 pinctrl-names = "default";
1670 pinctrl-0 = < 1620 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1621 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1622 #address-cells = <1>;
1673 #size-cells = 1623 #size-cells = <0>;
1674 status = "dis 1624 status = "disabled";
1675 }; 1625 };
1676 1626
1677 spi13: spi@c8c000 { 1627 spi13: spi@c8c000 {
1678 compatible = 1628 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 !! 1629 reg = <0 0xc8c000 0 0x4000>;
1680 reg-names = " 1630 reg-names = "se";
1681 clock-names = 1631 clock-names = "se";
1682 clocks = <&gc 1632 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1633 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1634 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1635 dma-names = "tx", "rx";
1686 pinctrl-names 1636 pinctrl-names = "default";
1687 pinctrl-0 = < 1637 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1638 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1639 spi-max-frequency = <50000000>;
1690 #address-cell 1640 #address-cells = <1>;
1691 #size-cells = 1641 #size-cells = <0>;
1692 status = "dis 1642 status = "disabled";
1693 }; 1643 };
1694 1644
1695 i2c14: i2c@c90000 { 1645 i2c14: i2c@c90000 {
1696 compatible = 1646 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1647 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1648 clock-names = "se";
1699 clocks = <&gc 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1650 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1651 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1652 dma-names = "tx", "rx";
1703 pinctrl-names 1653 pinctrl-names = "default";
1704 pinctrl-0 = < 1654 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1655 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1656 #address-cells = <1>;
1707 #size-cells = 1657 #size-cells = <0>;
1708 status = "dis 1658 status = "disabled";
1709 }; 1659 };
1710 1660
1711 spi14: spi@c90000 { 1661 spi14: spi@c90000 {
1712 compatible = 1662 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 !! 1663 reg = <0 0xc90000 0 0x4000>;
1714 reg-names = " 1664 reg-names = "se";
1715 clock-names = 1665 clock-names = "se";
1716 clocks = <&gc 1666 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1667 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1668 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1669 dma-names = "tx", "rx";
1720 pinctrl-names 1670 pinctrl-names = "default";
1721 pinctrl-0 = < 1671 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1672 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1673 spi-max-frequency = <50000000>;
1724 #address-cell 1674 #address-cells = <1>;
1725 #size-cells = 1675 #size-cells = <0>;
1726 status = "dis 1676 status = "disabled";
1727 }; 1677 };
1728 1678
1729 i2c15: i2c@c94000 { 1679 i2c15: i2c@c94000 {
1730 compatible = 1680 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1681 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1682 clock-names = "se";
1733 clocks = <&gc 1683 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1684 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1685 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1686 dma-names = "tx", "rx";
1737 pinctrl-names 1687 pinctrl-names = "default";
1738 pinctrl-0 = < 1688 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1689 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1690 #address-cells = <1>;
1741 #size-cells = 1691 #size-cells = <0>;
1742 status = "dis 1692 status = "disabled";
1743 }; 1693 };
1744 1694
1745 spi15: spi@c94000 { 1695 spi15: spi@c94000 {
1746 compatible = 1696 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 !! 1697 reg = <0 0xc94000 0 0x4000>;
1748 reg-names = " 1698 reg-names = "se";
1749 clock-names = 1699 clock-names = "se";
1750 clocks = <&gc 1700 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1701 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1702 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1703 dma-names = "tx", "rx";
1754 pinctrl-names 1704 pinctrl-names = "default";
1755 pinctrl-0 = < 1705 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1706 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1707 spi-max-frequency = <50000000>;
1758 #address-cell 1708 #address-cells = <1>;
1759 #size-cells = 1709 #size-cells = <0>;
1760 status = "dis 1710 status = "disabled";
1761 }; 1711 };
1762 }; 1712 };
1763 1713
1764 config_noc: interconnect@1500 1714 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1715 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1716 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1717 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1718 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1719 };
1770 1720
1771 system_noc: interconnect@1620 1721 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1722 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1723 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1724 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1725 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1726 };
1777 1727
1778 mc_virt: interconnect@163a000 1728 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1729 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1730 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1731 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1732 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1733 };
1784 1734
1785 aggre1_noc: interconnect@16e0 1735 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1736 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1737 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1738 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1739 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1740 };
1791 1741
1792 aggre2_noc: interconnect@1700 1742 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1743 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1744 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1745 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1746 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1747 };
1798 1748
1799 compute_noc: interconnect@172 1749 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1750 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1751 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1752 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1753 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1754 };
1805 1755
1806 mmss_noc: interconnect@174000 1756 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1757 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1758 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1759 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1760 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1761 };
1812 1762
1813 system-cache-controller@92000 1763 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1764 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 1765 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 1766 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 1767 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1768 };
1822 1769
1823 dma@10a2000 { !! 1770 pcie0: pci@1c00000 {
1824 compatible = "qcom,sm !! 1771 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1825 reg = <0x0 0x010a2000 <<
1826 <0x0 0x010ad000 <<
1827 }; <<
1828 <<
1829 pcie0: pcie@1c00000 { <<
1830 compatible = "qcom,pc <<
1831 reg = <0 0x01c00000 0 1772 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1773 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1774 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1775 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1776 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1777 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1778 device_type = "pci";
1838 linux,pci-domain = <0 1779 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1780 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1781 num-lanes = <1>;
1841 1782
1842 #address-cells = <3>; 1783 #address-cells = <3>;
1843 #size-cells = <2>; 1784 #size-cells = <2>;
1844 1785
1845 ranges = <0x01000000 1786 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 1787 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 1788
1848 interrupts = <GIC_SPI !! 1789 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1849 <GIC_SPI !! 1790 interrupt-names = "msi";
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 1791 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1792 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1793 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1794 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1795 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1796 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1797
1871 clocks = <&gcc GCC_PC 1798 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1799 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1800 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1801 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1802 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1803 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG !! 1804 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", 1805 clock-names = "pipe",
1880 "aux", 1806 "aux",
1881 "cfg", 1807 "cfg",
1882 "bus_ma 1808 "bus_master",
1883 "bus_sl 1809 "bus_slave",
1884 "slave_ 1810 "slave_q2a",
1885 "tbu", !! 1811 "tbu";
1886 "ref"; <<
1887 1812
>> 1813 iommus = <&apps_smmu 0x1d80 0x3f>;
1888 iommu-map = <0x0 &a 1814 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1815 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1816
1891 resets = <&gcc GCC_PC 1817 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1818 reset-names = "pci";
1893 1819
1894 power-domains = <&gcc 1820 power-domains = <&gcc PCIE_0_GDSC>;
1895 1821
1896 phys = <&pcie0_phy>; !! 1822 phys = <&pcie0_lane>;
1897 phy-names = "pciephy" 1823 phy-names = "pciephy";
1898 1824
1899 perst-gpios = <&tlmm !! 1825 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 !! 1826 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1827
1902 pinctrl-names = "defa 1828 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1829 pinctrl-0 = <&pcie0_default_state>;
1904 1830
1905 status = "disabled"; 1831 status = "disabled";
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; 1832 };
1917 1833
1918 pcie0_phy: phy@1c06000 { 1834 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1835 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 !! 1836 reg = <0 0x01c06000 0 0x1c0>;
>> 1837 #address-cells = <2>;
>> 1838 #size-cells = <2>;
>> 1839 ranges;
1921 clocks = <&gcc GCC_PC 1840 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1841 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC !! 1842 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1924 <&gcc GCC_PC !! 1843 clock-names = "aux", "cfg_ahb", "refgen";
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 1844
1937 resets = <&gcc GCC_PC 1845 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1846 reset-names = "phy";
1939 1847
1940 assigned-clocks = <&g 1848 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1849 assigned-clock-rates = <100000000>;
1942 1850
1943 status = "disabled"; 1851 status = "disabled";
>> 1852
>> 1853 pcie0_lane: phy@1c06200 {
>> 1854 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1855 <0 0x1c06400 0 0x200>, /* rx */
>> 1856 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1857 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1858 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1859 clock-names = "pipe0";
>> 1860
>> 1861 #phy-cells = <0>;
>> 1862 clock-output-names = "pcie_0_pipe_clk";
>> 1863 };
1944 }; 1864 };
1945 1865
1946 pcie1: pcie@1c08000 { !! 1866 pcie1: pci@1c08000 {
1947 compatible = "qcom,pc !! 1867 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1948 reg = <0 0x01c08000 0 1868 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1869 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1870 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1871 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1872 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1873 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1874 device_type = "pci";
1955 linux,pci-domain = <1 1875 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1876 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1877 num-lanes = <2>;
1958 1878
1959 #address-cells = <3>; 1879 #address-cells = <3>;
1960 #size-cells = <2>; 1880 #size-cells = <2>;
1961 1881
1962 ranges = <0x01000000 1882 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1883 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1884
1965 interrupts = <GIC_SPI !! 1885 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1966 <GIC_SPI !! 1886 interrupt-names = "msi";
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 1887 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1888 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1889 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1890 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1891 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1892 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1893
1988 clocks = <&gcc GCC_PC 1894 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1895 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1896 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1897 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1898 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1899 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG !! 1900 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", 1901 clock-names = "pipe",
1997 "aux", 1902 "aux",
1998 "cfg", 1903 "cfg",
1999 "bus_ma 1904 "bus_master",
2000 "bus_sl 1905 "bus_slave",
2001 "slave_ 1906 "slave_q2a",
2002 "tbu", !! 1907 "tbu";
2003 "ref"; <<
2004 1908
2005 assigned-clocks = <&g 1909 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 1910 assigned-clock-rates = <19200000>;
2007 1911
>> 1912 iommus = <&apps_smmu 0x1e00 0x3f>;
2008 iommu-map = <0x0 &a 1913 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 1914 <0x100 &apps_smmu 0x1e01 0x1>;
2010 1915
2011 resets = <&gcc GCC_PC 1916 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 1917 reset-names = "pci";
2013 1918
2014 power-domains = <&gcc 1919 power-domains = <&gcc PCIE_1_GDSC>;
2015 1920
2016 phys = <&pcie1_phy>; !! 1921 phys = <&pcie1_lane>;
2017 phy-names = "pciephy" 1922 phy-names = "pciephy";
2018 1923
2019 perst-gpios = <&tlmm !! 1924 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 1925 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 1926
2022 pinctrl-names = "defa 1927 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 1928 pinctrl-0 = <&pcie1_default_state>;
2024 1929
2025 status = "disabled"; 1930 status = "disabled";
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; 1931 };
2037 1932
2038 pcie1_phy: phy@1c0e000 { 1933 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 1934 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 !! 1935 reg = <0 0x01c0e000 0 0x1c0>;
>> 1936 #address-cells = <2>;
>> 1937 #size-cells = <2>;
>> 1938 ranges;
2041 clocks = <&gcc GCC_PC 1939 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 1940 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC !! 1941 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2044 <&gcc GCC_PC !! 1942 clock-names = "aux", "cfg_ahb", "refgen";
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 1943
2057 resets = <&gcc GCC_PC 1944 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 1945 reset-names = "phy";
2059 1946
2060 assigned-clocks = <&g 1947 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 1948 assigned-clock-rates = <100000000>;
2062 1949
2063 status = "disabled"; 1950 status = "disabled";
>> 1951
>> 1952 pcie1_lane: phy@1c0e200 {
>> 1953 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1954 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1955 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1956 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1957 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1958 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1959 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1960 clock-names = "pipe0";
>> 1961
>> 1962 #phy-cells = <0>;
>> 1963 clock-output-names = "pcie_1_pipe_clk";
>> 1964 };
2064 }; 1965 };
2065 1966
2066 ufs_mem_hc: ufshc@1d84000 { 1967 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 1968 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 1969 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 1970 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 1971 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 1972 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 1973 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 1974 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 1975 phy-names = "ufsphy";
2075 lanes-per-direction = 1976 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 1977 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 1978 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 1979 reset-names = "rst";
2079 1980
2080 iommus = <&apps_smmu 1981 iommus = <&apps_smmu 0x300 0>;
2081 1982
2082 clock-names = 1983 clock-names =
2083 "core_clk", 1984 "core_clk",
2084 "bus_aggr_clk 1985 "bus_aggr_clk",
2085 "iface_clk", 1986 "iface_clk",
2086 "core_clk_uni 1987 "core_clk_unipro",
2087 "ref_clk", 1988 "ref_clk",
2088 "tx_lane0_syn 1989 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 1990 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 1991 "rx_lane1_sync_clk",
2091 "ice_core_clk 1992 "ice_core_clk";
2092 clocks = 1993 clocks =
2093 <&gcc GCC_UFS 1994 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 1995 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 1996 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 1997 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 1998 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 1999 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2000 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2001 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2002 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2003 freq-table-hz =
2103 <37500000 300 2004 <37500000 300000000>,
2104 <0 0>, 2005 <0 0>,
2105 <0 0>, 2006 <0 0>,
2106 <37500000 300 2007 <37500000 300000000>,
2107 <0 0>, 2008 <0 0>,
2108 <0 0>, 2009 <0 0>,
2109 <0 0>, 2010 <0 0>,
2110 <0 0>, 2011 <0 0>,
2111 <0 300000000> 2012 <0 300000000>;
2112 2013
2113 status = "disabled"; 2014 status = "disabled";
2114 }; 2015 };
2115 2016
2116 ufs_mem_phy: phy@1d87000 { 2017 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2018 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 2019 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 2020 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 2021 #size-cells = <2>;
2121 <&gcc GCC_UF !! 2022 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 2023 clock-names = "ref",
2124 "ref_au !! 2024 "ref_aux";
2125 "qref"; !! 2025 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>> 2026 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2126 2027
2127 power-domains = <&gcc 2028 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2029
2129 resets = <&ufs_mem_hc 2030 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2031 reset-names = "ufsphy";
2131 <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 2032 status = "disabled";
>> 2033
>> 2034 ufs_mem_phy_lanes: phy@1d87400 {
>> 2035 reg = <0 0x01d87400 0 0x16c>,
>> 2036 <0 0x01d87600 0 0x200>,
>> 2037 <0 0x01d87c00 0 0x200>,
>> 2038 <0 0x01d87800 0 0x16c>,
>> 2039 <0 0x01d87a00 0 0x200>;
>> 2040 #phy-cells = <0>;
>> 2041 };
2135 }; 2042 };
2136 2043
2137 cryptobam: dma-controller@1dc !! 2044 ipa_virt: interconnect@1e00000 {
2138 compatible = "qcom,ba !! 2045 compatible = "qcom,sm8150-ipa-virt";
2139 reg = <0 0x01dc4000 0 !! 2046 reg = <0 0x01e00000 0 0x1000>;
2140 interrupts = <GIC_SPI !! 2047 #interconnect-cells = <1>;
2141 #dma-cells = <1>; !! 2048 qcom,bcm-voters = <&apps_bcm_voter>;
2142 qcom,ee = <0>; <<
2143 qcom,controlled-remot <<
2144 num-channels = <8>; <<
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; 2049 };
2166 2050
2167 tcsr_mutex: hwlock@1f40000 { 2051 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc 2052 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 2053 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>; 2054 #hwlock-cells = <1>;
2171 }; 2055 };
2172 2056
2173 tcsr_regs_1: syscon@1f60000 { 2057 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm 2058 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 2059 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 }; 2060 };
2177 2061
2178 remoteproc_slpi: remoteproc@2 2062 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2063 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2064 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2065
2182 interrupts-extended = 2066 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2067 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2068 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2069 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2070 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2071 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2072 "handover", "stop-ack";
2189 2073
2190 clocks = <&rpmhcc RPM 2074 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2075 clock-names = "xo";
2192 2076
2193 power-domains = <&rpm 2077 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpm 2078 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = 2079 power-domain-names = "lcx", "lmx";
2196 2080
2197 memory-region = <&slp 2081 memory-region = <&slpi_mem>;
2198 2082
2199 qcom,qmp = <&aoss_qmp 2083 qcom,qmp = <&aoss_qmp>;
2200 2084
2201 qcom,smem-states = <& 2085 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2086 qcom,smem-state-names = "stop";
2203 2087
2204 status = "disabled"; 2088 status = "disabled";
2205 2089
2206 glink-edge { 2090 glink-edge {
2207 interrupts = 2091 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2092 label = "dsps";
2209 qcom,remote-p 2093 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2094 mboxes = <&apss_shared 24>;
2211 2095
2212 fastrpc { 2096 fastrpc {
2213 compa 2097 compatible = "qcom,fastrpc";
2214 qcom, 2098 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2099 label = "sdsp";
2216 qcom, 2100 qcom,non-secure-domain;
2217 #addr 2101 #address-cells = <1>;
2218 #size 2102 #size-cells = <0>;
2219 2103
2220 compu 2104 compute-cb@1 {
2221 2105 compatible = "qcom,fastrpc-compute-cb";
2222 2106 reg = <1>;
2223 2107 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2108 };
2225 2109
2226 compu 2110 compute-cb@2 {
2227 2111 compatible = "qcom,fastrpc-compute-cb";
2228 2112 reg = <2>;
2229 2113 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2114 };
2231 2115
2232 compu 2116 compute-cb@3 {
2233 2117 compatible = "qcom,fastrpc-compute-cb";
2234 2118 reg = <3>;
2235 2119 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2120 /* note: shared-cb = <4> in downstream */
2237 }; 2121 };
2238 }; 2122 };
2239 }; 2123 };
2240 }; 2124 };
2241 2125
2242 gpu: gpu@2c00000 { 2126 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 2127 /*
>> 2128 * note: the amd,imageon compatible makes it possible
>> 2129 * to use the drm/msm driver without the display node,
>> 2130 * make sure to remove it when display node is added
>> 2131 */
>> 2132 compatible = "qcom,adreno-640.1",
>> 2133 "qcom,adreno",
>> 2134 "amd,imageon";
>> 2135
2244 reg = <0 0x02c00000 0 2136 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2137 reg-names = "kgsl_3d0_reg_memory";
2246 2138
2247 interrupts = <GIC_SPI 2139 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2140
2249 iommus = <&adreno_smm 2141 iommus = <&adreno_smmu 0 0x401>;
2250 2142
2251 operating-points-v2 = 2143 operating-points-v2 = <&gpu_opp_table>;
2252 2144
2253 qcom,gmu = <&gmu>; 2145 qcom,gmu = <&gmu>;
2254 2146
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 2147 status = "disabled";
2260 2148
2261 zap-shader { 2149 zap-shader {
2262 memory-region 2150 memory-region = <&gpu_mem>;
2263 }; 2151 };
2264 2152
>> 2153 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 2154 gpu_opp_table: opp-table {
2266 compatible = 2155 compatible = "operating-points-v2";
2267 2156
2268 opp-675000000 2157 opp-675000000 {
2269 opp-h 2158 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2159 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 2160 };
2273 2161
2274 opp-585000000 2162 opp-585000000 {
2275 opp-h 2163 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2164 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 2165 };
2279 2166
2280 opp-499200000 2167 opp-499200000 {
2281 opp-h 2168 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2169 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 2170 };
2285 2171
2286 opp-427000000 2172 opp-427000000 {
2287 opp-h 2173 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2174 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 2175 };
2291 2176
2292 opp-345000000 2177 opp-345000000 {
2293 opp-h 2178 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2179 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 2180 };
2297 2181
2298 opp-257000000 2182 opp-257000000 {
2299 opp-h 2183 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2184 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 2185 };
2303 }; 2186 };
2304 }; 2187 };
2305 2188
2306 gmu: gmu@2c6a000 { 2189 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad 2190 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2191
2309 reg = <0 0x02c6a000 0 2192 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2193 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2194 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2195 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2196
2314 interrupts = <GIC_SPI 2197 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2198 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2199 interrupt-names = "hfi", "gmu";
2317 2200
2318 clocks = <&gpucc GPU_ 2201 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2202 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2203 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2204 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2205 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2206 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2207
2325 power-domains = <&gpu 2208 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2209 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2210 power-domain-names = "cx", "gx";
2328 2211
2329 iommus = <&adreno_smm 2212 iommus = <&adreno_smmu 5 0x400>;
2330 2213
2331 operating-points-v2 = 2214 operating-points-v2 = <&gmu_opp_table>;
2332 2215
2333 status = "disabled"; 2216 status = "disabled";
2334 2217
2335 gmu_opp_table: opp-ta 2218 gmu_opp_table: opp-table {
2336 compatible = 2219 compatible = "operating-points-v2";
2337 2220
2338 opp-200000000 2221 opp-200000000 {
2339 opp-h 2222 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2223 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2224 };
2342 }; 2225 };
2343 }; 2226 };
2344 2227
2345 gpucc: clock-controller@2c900 2228 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2229 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2230 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2231 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2232 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2233 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2234 clock-names = "bi_tcxo",
2352 "gcc_gp 2235 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2236 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2237 #clock-cells = <1>;
2355 #reset-cells = <1>; 2238 #reset-cells = <1>;
2356 #power-domain-cells = 2239 #power-domain-cells = <1>;
2357 }; 2240 };
2358 2241
2359 adreno_smmu: iommu@2ca0000 { 2242 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 2243 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 2244 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2245 #iommu-cells = <2>;
2364 #global-interrupts = 2246 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2247 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2248 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2249 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2250 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2251 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2252 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2253 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2254 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2255 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2256 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2257 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2258 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2259 clock-names = "ahb", "bus", "iface";
2378 2260
2379 power-domains = <&gpu 2261 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2262 };
2381 2263
2382 tlmm: pinctrl@3100000 { 2264 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2265 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2266 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2267 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2268 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2269 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2270 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2271 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2272 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2273 gpio-controller;
2392 #gpio-cells = <2>; 2274 #gpio-cells = <2>;
2393 interrupt-controller; 2275 interrupt-controller;
2394 #interrupt-cells = <2 2276 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2277 wakeup-parent = <&pdc>;
2396 2278
2397 qup_i2c0_default: qup 2279 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0 2280 pins = "gpio0", "gpio1";
2399 function = "q 2281 function = "qup0";
2400 drive-strengt 2282 drive-strength = <0x02>;
2401 bias-disable; 2283 bias-disable;
2402 }; 2284 };
2403 2285
2404 qup_spi0_default: qup 2286 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0 2287 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2288 function = "qup0";
2407 drive-strengt 2289 drive-strength = <6>;
2408 bias-disable; 2290 bias-disable;
2409 }; 2291 };
2410 2292
2411 qup_i2c1_default: qup 2293 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio1 2294 pins = "gpio114", "gpio115";
2413 function = "q 2295 function = "qup1";
2414 drive-strengt 2296 drive-strength = <2>;
2415 bias-disable; 2297 bias-disable;
2416 }; 2298 };
2417 2299
2418 qup_spi1_default: qup 2300 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio1 2301 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2302 function = "qup1";
2421 drive-strengt 2303 drive-strength = <6>;
2422 bias-disable; 2304 bias-disable;
2423 }; 2305 };
2424 2306
2425 qup_i2c2_default: qup 2307 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio1 2308 pins = "gpio126", "gpio127";
2427 function = "q 2309 function = "qup2";
2428 drive-strengt 2310 drive-strength = <2>;
2429 bias-disable; 2311 bias-disable;
2430 }; 2312 };
2431 2313
2432 qup_spi2_default: qup 2314 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio1 2315 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2316 function = "qup2";
2435 drive-strengt 2317 drive-strength = <6>;
2436 bias-disable; 2318 bias-disable;
2437 }; 2319 };
2438 2320
2439 qup_i2c3_default: qup 2321 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio1 2322 pins = "gpio144", "gpio145";
2441 function = "q 2323 function = "qup3";
2442 drive-strengt 2324 drive-strength = <2>;
2443 bias-disable; 2325 bias-disable;
2444 }; 2326 };
2445 2327
2446 qup_spi3_default: qup 2328 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio1 2329 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2330 function = "qup3";
2449 drive-strengt 2331 drive-strength = <6>;
2450 bias-disable; 2332 bias-disable;
2451 }; 2333 };
2452 2334
2453 qup_i2c4_default: qup 2335 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio5 2336 pins = "gpio51", "gpio52";
2455 function = "q 2337 function = "qup4";
2456 drive-strengt 2338 drive-strength = <2>;
2457 bias-disable; 2339 bias-disable;
2458 }; 2340 };
2459 2341
2460 qup_spi4_default: qup 2342 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio5 2343 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2344 function = "qup4";
2463 drive-strengt 2345 drive-strength = <6>;
2464 bias-disable; 2346 bias-disable;
2465 }; 2347 };
2466 2348
2467 qup_i2c5_default: qup 2349 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio1 2350 pins = "gpio121", "gpio122";
2469 function = "q 2351 function = "qup5";
2470 drive-strengt 2352 drive-strength = <2>;
2471 bias-disable; 2353 bias-disable;
2472 }; 2354 };
2473 2355
2474 qup_spi5_default: qup 2356 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio1 2357 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2358 function = "qup5";
2477 drive-strengt 2359 drive-strength = <6>;
2478 bias-disable; 2360 bias-disable;
2479 }; 2361 };
2480 2362
2481 qup_i2c6_default: qup 2363 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6 2364 pins = "gpio6", "gpio7";
2483 function = "q 2365 function = "qup6";
2484 drive-strengt 2366 drive-strength = <2>;
2485 bias-disable; 2367 bias-disable;
2486 }; 2368 };
2487 2369
2488 qup_spi6_default: qup !! 2370 qup_spi6_default: qup-spi6_default-state {
2489 pins = "gpio4 2371 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2372 function = "qup6";
2491 drive-strengt 2373 drive-strength = <6>;
2492 bias-disable; 2374 bias-disable;
2493 }; 2375 };
2494 2376
2495 qup_i2c7_default: qup 2377 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio9 2378 pins = "gpio98", "gpio99";
2497 function = "q 2379 function = "qup7";
2498 drive-strengt 2380 drive-strength = <2>;
2499 bias-disable; 2381 bias-disable;
2500 }; 2382 };
2501 2383
2502 qup_spi7_default: qup !! 2384 qup_spi7_default: qup-spi7_default-state {
2503 pins = "gpio9 2385 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2386 function = "qup7";
2505 drive-strengt 2387 drive-strength = <6>;
2506 bias-disable; 2388 bias-disable;
2507 }; 2389 };
2508 2390
2509 qup_i2c8_default: qup 2391 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio8 2392 pins = "gpio88", "gpio89";
2511 function = "q 2393 function = "qup8";
2512 drive-strengt 2394 drive-strength = <2>;
2513 bias-disable; 2395 bias-disable;
2514 }; 2396 };
2515 2397
2516 qup_spi8_default: qup 2398 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio8 2399 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2400 function = "qup8";
2519 drive-strengt 2401 drive-strength = <6>;
2520 bias-disable; 2402 bias-disable;
2521 }; 2403 };
2522 2404
2523 qup_i2c9_default: qup 2405 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio3 2406 pins = "gpio39", "gpio40";
2525 function = "q 2407 function = "qup9";
2526 drive-strengt 2408 drive-strength = <2>;
2527 bias-disable; 2409 bias-disable;
2528 }; 2410 };
2529 2411
2530 qup_spi9_default: qup 2412 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio3 2413 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2414 function = "qup9";
2533 drive-strengt 2415 drive-strength = <6>;
2534 bias-disable; 2416 bias-disable;
2535 }; 2417 };
2536 2418
2537 qup_uart9_default: qu <<
2538 pins = "gpio4 <<
2539 function = "q <<
2540 drive-strengt <<
2541 bias-disable; <<
2542 }; <<
2543 <<
2544 qup_i2c10_default: qu 2419 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9 2420 pins = "gpio9", "gpio10";
2546 function = "q 2421 function = "qup10";
2547 drive-strengt 2422 drive-strength = <2>;
2548 bias-disable; 2423 bias-disable;
2549 }; 2424 };
2550 2425
2551 qup_spi10_default: qu 2426 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9 2427 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2428 function = "qup10";
2554 drive-strengt 2429 drive-strength = <6>;
2555 bias-disable; 2430 bias-disable;
2556 }; 2431 };
2557 2432
2558 qup_i2c11_default: qu 2433 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio9 2434 pins = "gpio94", "gpio95";
2560 function = "q 2435 function = "qup11";
2561 drive-strengt 2436 drive-strength = <2>;
2562 bias-disable; 2437 bias-disable;
2563 }; 2438 };
2564 2439
2565 qup_spi11_default: qu 2440 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio9 2441 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2442 function = "qup11";
2568 drive-strengt 2443 drive-strength = <6>;
2569 bias-disable; 2444 bias-disable;
2570 }; 2445 };
2571 2446
2572 qup_i2c12_default: qu 2447 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio8 2448 pins = "gpio83", "gpio84";
2574 function = "q 2449 function = "qup12";
2575 drive-strengt 2450 drive-strength = <2>;
2576 bias-disable; 2451 bias-disable;
2577 }; 2452 };
2578 2453
2579 qup_spi12_default: qu 2454 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio8 2455 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2456 function = "qup12";
2582 drive-strengt 2457 drive-strength = <6>;
2583 bias-disable; 2458 bias-disable;
2584 }; 2459 };
2585 2460
2586 qup_i2c13_default: qu 2461 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio4 2462 pins = "gpio43", "gpio44";
2588 function = "q 2463 function = "qup13";
2589 drive-strengt 2464 drive-strength = <2>;
2590 bias-disable; 2465 bias-disable;
2591 }; 2466 };
2592 2467
2593 qup_spi13_default: qu 2468 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio4 2469 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2470 function = "qup13";
2596 drive-strengt 2471 drive-strength = <6>;
2597 bias-disable; 2472 bias-disable;
2598 }; 2473 };
2599 2474
2600 qup_i2c14_default: qu 2475 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio4 2476 pins = "gpio47", "gpio48";
2602 function = "q 2477 function = "qup14";
2603 drive-strengt 2478 drive-strength = <2>;
2604 bias-disable; 2479 bias-disable;
2605 }; 2480 };
2606 2481
2607 qup_spi14_default: qu 2482 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio4 2483 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2484 function = "qup14";
2610 drive-strengt 2485 drive-strength = <6>;
2611 bias-disable; 2486 bias-disable;
2612 }; 2487 };
2613 2488
2614 qup_i2c15_default: qu 2489 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio2 2490 pins = "gpio27", "gpio28";
2616 function = "q 2491 function = "qup15";
2617 drive-strengt 2492 drive-strength = <2>;
2618 bias-disable; 2493 bias-disable;
2619 }; 2494 };
2620 2495
2621 qup_spi15_default: qu 2496 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio2 2497 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2498 function = "qup15";
2624 drive-strengt 2499 drive-strength = <6>;
2625 bias-disable; 2500 bias-disable;
2626 }; 2501 };
2627 2502
2628 qup_i2c16_default: qu 2503 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio8 2504 pins = "gpio86", "gpio85";
2630 function = "q 2505 function = "qup16";
2631 drive-strengt 2506 drive-strength = <2>;
2632 bias-disable; 2507 bias-disable;
2633 }; 2508 };
2634 2509
2635 qup_spi16_default: qu 2510 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio8 2511 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2512 function = "qup16";
2638 drive-strengt 2513 drive-strength = <6>;
2639 bias-disable; 2514 bias-disable;
2640 }; 2515 };
2641 2516
2642 qup_i2c17_default: qu 2517 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio5 2518 pins = "gpio55", "gpio56";
2644 function = "q 2519 function = "qup17";
2645 drive-strengt 2520 drive-strength = <2>;
2646 bias-disable; 2521 bias-disable;
2647 }; 2522 };
2648 2523
2649 qup_spi17_default: qu 2524 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio5 2525 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2526 function = "qup17";
2652 drive-strengt 2527 drive-strength = <6>;
2653 bias-disable; 2528 bias-disable;
2654 }; 2529 };
2655 2530
2656 qup_i2c18_default: qu 2531 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio2 2532 pins = "gpio23", "gpio24";
2658 function = "q 2533 function = "qup18";
2659 drive-strengt 2534 drive-strength = <2>;
2660 bias-disable; 2535 bias-disable;
2661 }; 2536 };
2662 2537
2663 qup_spi18_default: qu 2538 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio2 2539 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2540 function = "qup18";
2666 drive-strengt 2541 drive-strength = <6>;
2667 bias-disable; 2542 bias-disable;
2668 }; 2543 };
2669 2544
2670 qup_i2c19_default: qu 2545 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio5 2546 pins = "gpio57", "gpio58";
2672 function = "q 2547 function = "qup19";
2673 drive-strengt 2548 drive-strength = <2>;
2674 bias-disable; 2549 bias-disable;
2675 }; 2550 };
2676 2551
2677 qup_spi19_default: qu 2552 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio5 2553 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2554 function = "qup19";
2680 drive-strengt 2555 drive-strength = <6>;
2681 bias-disable; 2556 bias-disable;
2682 }; 2557 };
2683 2558
2684 pcie0_default_state: 2559 pcie0_default_state: pcie0-default-state {
2685 perst-pins { 2560 perst-pins {
2686 pins 2561 pins = "gpio35";
2687 funct 2562 function = "gpio";
2688 drive 2563 drive-strength = <2>;
2689 bias- 2564 bias-pull-down;
2690 }; 2565 };
2691 2566
2692 clkreq-pins { 2567 clkreq-pins {
2693 pins 2568 pins = "gpio36";
2694 funct 2569 function = "pci_e0";
2695 drive 2570 drive-strength = <2>;
2696 bias- 2571 bias-pull-up;
2697 }; 2572 };
2698 2573
2699 wake-pins { 2574 wake-pins {
2700 pins 2575 pins = "gpio37";
2701 funct 2576 function = "gpio";
2702 drive 2577 drive-strength = <2>;
2703 bias- 2578 bias-pull-up;
2704 }; 2579 };
2705 }; 2580 };
2706 2581
2707 pcie1_default_state: 2582 pcie1_default_state: pcie1-default-state {
2708 perst-pins { 2583 perst-pins {
2709 pins 2584 pins = "gpio102";
2710 funct 2585 function = "gpio";
2711 drive 2586 drive-strength = <2>;
2712 bias- 2587 bias-pull-down;
2713 }; 2588 };
2714 2589
2715 clkreq-pins { 2590 clkreq-pins {
2716 pins 2591 pins = "gpio103";
2717 funct 2592 function = "pci_e1";
2718 drive 2593 drive-strength = <2>;
2719 bias- 2594 bias-pull-up;
2720 }; 2595 };
2721 2596
2722 wake-pins { 2597 wake-pins {
2723 pins 2598 pins = "gpio104";
2724 funct 2599 function = "gpio";
2725 drive 2600 drive-strength = <2>;
2726 bias- 2601 bias-pull-up;
2727 }; 2602 };
2728 }; 2603 };
2729 }; 2604 };
2730 2605
2731 remoteproc_mpss: remoteproc@4 2606 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2607 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2608 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2609
2735 interrupts-extended = 2610 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2611 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2612 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2613 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2614 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2615 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2616 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2617 "stop-ack", "shutdown-ack";
2743 2618
2744 clocks = <&rpmhcc RPM 2619 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2620 clock-names = "xo";
2746 2621
2747 power-domains = <&rpm 2622 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpm 2623 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = 2624 power-domain-names = "cx", "mss";
2750 2625
2751 memory-region = <&mps 2626 memory-region = <&mpss_mem>;
2752 2627
2753 qcom,qmp = <&aoss_qmp 2628 qcom,qmp = <&aoss_qmp>;
2754 2629
2755 qcom,smem-states = <& 2630 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2631 qcom,smem-state-names = "stop";
2757 2632
2758 status = "disabled"; 2633 status = "disabled";
2759 2634
2760 glink-edge { 2635 glink-edge {
2761 interrupts = 2636 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2637 label = "modem";
2763 qcom,remote-p 2638 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2639 mboxes = <&apss_shared 12>;
2765 }; 2640 };
2766 }; 2641 };
2767 2642
2768 stm@6002000 { 2643 stm@6002000 {
2769 compatible = "arm,cor 2644 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2645 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2646 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2647 reg-names = "stm-base", "stm-stimulus-base";
2773 2648
2774 clocks = <&aoss_qmp>; 2649 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2650 clock-names = "apb_pclk";
2776 2651
2777 out-ports { 2652 out-ports {
2778 port { 2653 port {
2779 stm_o 2654 stm_out: endpoint {
2780 2655 remote-endpoint = <&funnel0_in7>;
2781 }; 2656 };
2782 }; 2657 };
2783 }; 2658 };
2784 }; 2659 };
2785 2660
2786 funnel@6041000 { 2661 funnel@6041000 {
2787 compatible = "arm,cor 2662 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2663 reg = <0 0x06041000 0 0x1000>;
2789 2664
2790 clocks = <&aoss_qmp>; 2665 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2666 clock-names = "apb_pclk";
2792 2667
2793 out-ports { 2668 out-ports {
2794 port { 2669 port {
2795 funne 2670 funnel0_out: endpoint {
2796 2671 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2672 };
2798 }; 2673 };
2799 }; 2674 };
2800 2675
2801 in-ports { 2676 in-ports {
2802 #address-cell 2677 #address-cells = <1>;
2803 #size-cells = 2678 #size-cells = <0>;
2804 2679
2805 port@7 { 2680 port@7 {
2806 reg = 2681 reg = <7>;
2807 funne 2682 funnel0_in7: endpoint {
2808 2683 remote-endpoint = <&stm_out>;
2809 }; 2684 };
2810 }; 2685 };
2811 }; 2686 };
2812 }; 2687 };
2813 2688
2814 funnel@6042000 { 2689 funnel@6042000 {
2815 compatible = "arm,cor 2690 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2691 reg = <0 0x06042000 0 0x1000>;
2817 2692
2818 clocks = <&aoss_qmp>; 2693 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2694 clock-names = "apb_pclk";
2820 2695
2821 out-ports { 2696 out-ports {
2822 port { 2697 port {
2823 funne 2698 funnel1_out: endpoint {
2824 2699 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2700 };
2826 }; 2701 };
2827 }; 2702 };
2828 2703
2829 in-ports { 2704 in-ports {
2830 #address-cell 2705 #address-cells = <1>;
2831 #size-cells = 2706 #size-cells = <0>;
2832 2707
2833 port@4 { 2708 port@4 {
2834 reg = 2709 reg = <4>;
2835 funne 2710 funnel1_in4: endpoint {
2836 2711 remote-endpoint = <&swao_replicator_out>;
2837 }; 2712 };
2838 }; 2713 };
2839 }; 2714 };
2840 }; 2715 };
2841 2716
2842 funnel@6043000 { 2717 funnel@6043000 {
2843 compatible = "arm,cor 2718 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2719 reg = <0 0x06043000 0 0x1000>;
2845 2720
2846 clocks = <&aoss_qmp>; 2721 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2722 clock-names = "apb_pclk";
2848 2723
2849 out-ports { 2724 out-ports {
2850 port { 2725 port {
2851 funne 2726 funnel2_out: endpoint {
2852 2727 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2728 };
2854 }; 2729 };
2855 }; 2730 };
2856 2731
2857 in-ports { 2732 in-ports {
2858 #address-cell 2733 #address-cells = <1>;
2859 #size-cells = 2734 #size-cells = <0>;
2860 2735
2861 port@2 { 2736 port@2 {
2862 reg = 2737 reg = <2>;
2863 funne 2738 funnel2_in2: endpoint {
2864 2739 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2740 };
2866 }; 2741 };
2867 }; 2742 };
2868 }; 2743 };
2869 2744
2870 funnel@6045000 { 2745 funnel@6045000 {
2871 compatible = "arm,cor 2746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2747 reg = <0 0x06045000 0 0x1000>;
2873 2748
2874 clocks = <&aoss_qmp>; 2749 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2750 clock-names = "apb_pclk";
2876 2751
2877 out-ports { 2752 out-ports {
2878 port { 2753 port {
2879 merge 2754 merge_funnel_out: endpoint {
2880 2755 remote-endpoint = <&etf_in>;
2881 }; 2756 };
2882 }; 2757 };
2883 }; 2758 };
2884 2759
2885 in-ports { 2760 in-ports {
2886 #address-cell 2761 #address-cells = <1>;
2887 #size-cells = 2762 #size-cells = <0>;
2888 2763
2889 port@0 { 2764 port@0 {
2890 reg = 2765 reg = <0>;
2891 merge 2766 merge_funnel_in0: endpoint {
2892 2767 remote-endpoint = <&funnel0_out>;
2893 }; 2768 };
2894 }; 2769 };
2895 2770
2896 port@1 { 2771 port@1 {
2897 reg = 2772 reg = <1>;
2898 merge 2773 merge_funnel_in1: endpoint {
2899 2774 remote-endpoint = <&funnel1_out>;
2900 }; 2775 };
2901 }; 2776 };
2902 2777
2903 port@2 { 2778 port@2 {
2904 reg = 2779 reg = <2>;
2905 merge 2780 merge_funnel_in2: endpoint {
2906 2781 remote-endpoint = <&funnel2_out>;
2907 }; 2782 };
2908 }; 2783 };
2909 }; 2784 };
2910 }; 2785 };
2911 2786
2912 replicator@6046000 { 2787 replicator@6046000 {
2913 compatible = "arm,cor 2788 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2789 reg = <0 0x06046000 0 0x1000>;
2915 2790
2916 clocks = <&aoss_qmp>; 2791 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2792 clock-names = "apb_pclk";
2918 2793
2919 out-ports { 2794 out-ports {
2920 #address-cell 2795 #address-cells = <1>;
2921 #size-cells = 2796 #size-cells = <0>;
2922 2797
2923 port@0 { 2798 port@0 {
2924 reg = 2799 reg = <0>;
2925 repli 2800 replicator_out0: endpoint {
2926 2801 remote-endpoint = <&etr_in>;
2927 }; 2802 };
2928 }; 2803 };
2929 2804
2930 port@1 { 2805 port@1 {
2931 reg = 2806 reg = <1>;
2932 repli 2807 replicator_out1: endpoint {
2933 2808 remote-endpoint = <&replicator1_in>;
2934 }; 2809 };
2935 }; 2810 };
2936 }; 2811 };
2937 2812
2938 in-ports { 2813 in-ports {
2939 port { 2814 port {
2940 repli 2815 replicator_in0: endpoint {
2941 2816 remote-endpoint = <&etf_out>;
2942 }; 2817 };
2943 }; 2818 };
2944 }; 2819 };
2945 }; 2820 };
2946 2821
2947 etf@6047000 { 2822 etf@6047000 {
2948 compatible = "arm,cor 2823 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2824 reg = <0 0x06047000 0 0x1000>;
2950 2825
2951 clocks = <&aoss_qmp>; 2826 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2827 clock-names = "apb_pclk";
2953 2828
2954 out-ports { 2829 out-ports {
2955 port { 2830 port {
2956 etf_o 2831 etf_out: endpoint {
2957 2832 remote-endpoint = <&replicator_in0>;
2958 }; 2833 };
2959 }; 2834 };
2960 }; 2835 };
2961 2836
2962 in-ports { 2837 in-ports {
2963 port { 2838 port {
2964 etf_i 2839 etf_in: endpoint {
2965 2840 remote-endpoint = <&merge_funnel_out>;
2966 }; 2841 };
2967 }; 2842 };
2968 }; 2843 };
2969 }; 2844 };
2970 2845
2971 etr@6048000 { 2846 etr@6048000 {
2972 compatible = "arm,cor 2847 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2848 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2849 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2850
2976 clocks = <&aoss_qmp>; 2851 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2852 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2853 arm,scatter-gather;
2979 2854
2980 in-ports { 2855 in-ports {
2981 port { 2856 port {
2982 etr_i 2857 etr_in: endpoint {
2983 2858 remote-endpoint = <&replicator_out0>;
2984 }; 2859 };
2985 }; 2860 };
2986 }; 2861 };
2987 }; 2862 };
2988 2863
2989 replicator@604a000 { 2864 replicator@604a000 {
2990 compatible = "arm,cor 2865 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2866 reg = <0 0x0604a000 0 0x1000>;
2992 2867
2993 clocks = <&aoss_qmp>; 2868 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2869 clock-names = "apb_pclk";
2995 2870
2996 out-ports { 2871 out-ports {
2997 #address-cell 2872 #address-cells = <1>;
2998 #size-cells = 2873 #size-cells = <0>;
2999 2874
3000 port@1 { 2875 port@1 {
3001 reg = 2876 reg = <1>;
3002 repli 2877 replicator1_out: endpoint {
3003 2878 remote-endpoint = <&swao_funnel_in>;
3004 }; 2879 };
3005 }; 2880 };
3006 }; 2881 };
3007 2882
3008 in-ports { 2883 in-ports {
>> 2884 #address-cells = <1>;
>> 2885 #size-cells = <0>;
3009 2886
3010 port { !! 2887 port@1 {
>> 2888 reg = <1>;
3011 repli 2889 replicator1_in: endpoint {
3012 2890 remote-endpoint = <&replicator_out1>;
3013 }; 2891 };
3014 }; 2892 };
3015 }; 2893 };
3016 }; 2894 };
3017 2895
3018 funnel@6b08000 { 2896 funnel@6b08000 {
3019 compatible = "arm,cor 2897 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2898 reg = <0 0x06b08000 0 0x1000>;
3021 2899
3022 clocks = <&aoss_qmp>; 2900 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2901 clock-names = "apb_pclk";
3024 2902
3025 out-ports { 2903 out-ports {
3026 port { 2904 port {
3027 swao_ 2905 swao_funnel_out: endpoint {
3028 2906 remote-endpoint = <&swao_etf_in>;
3029 }; 2907 };
3030 }; 2908 };
3031 }; 2909 };
3032 2910
3033 in-ports { 2911 in-ports {
3034 #address-cell 2912 #address-cells = <1>;
3035 #size-cells = 2913 #size-cells = <0>;
3036 2914
3037 port@6 { 2915 port@6 {
3038 reg = 2916 reg = <6>;
3039 swao_ 2917 swao_funnel_in: endpoint {
3040 2918 remote-endpoint = <&replicator1_out>;
3041 }; 2919 };
3042 }; 2920 };
3043 }; 2921 };
3044 }; 2922 };
3045 2923
3046 etf@6b09000 { 2924 etf@6b09000 {
3047 compatible = "arm,cor 2925 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2926 reg = <0 0x06b09000 0 0x1000>;
3049 2927
3050 clocks = <&aoss_qmp>; 2928 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2929 clock-names = "apb_pclk";
3052 2930
3053 out-ports { 2931 out-ports {
3054 port { 2932 port {
3055 swao_ 2933 swao_etf_out: endpoint {
3056 2934 remote-endpoint = <&swao_replicator_in>;
3057 }; 2935 };
3058 }; 2936 };
3059 }; 2937 };
3060 2938
3061 in-ports { 2939 in-ports {
3062 port { 2940 port {
3063 swao_ 2941 swao_etf_in: endpoint {
3064 2942 remote-endpoint = <&swao_funnel_out>;
3065 }; 2943 };
3066 }; 2944 };
3067 }; 2945 };
3068 }; 2946 };
3069 2947
3070 replicator@6b0a000 { 2948 replicator@6b0a000 {
3071 compatible = "arm,cor 2949 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 2950 reg = <0 0x06b0a000 0 0x1000>;
3073 2951
3074 clocks = <&aoss_qmp>; 2952 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 2953 clock-names = "apb_pclk";
3076 qcom,replicator-loses 2954 qcom,replicator-loses-context;
3077 2955
3078 out-ports { 2956 out-ports {
3079 port { 2957 port {
3080 swao_ 2958 swao_replicator_out: endpoint {
3081 2959 remote-endpoint = <&funnel1_in4>;
3082 }; 2960 };
3083 }; 2961 };
3084 }; 2962 };
3085 2963
3086 in-ports { 2964 in-ports {
3087 port { 2965 port {
3088 swao_ 2966 swao_replicator_in: endpoint {
3089 2967 remote-endpoint = <&swao_etf_out>;
3090 }; 2968 };
3091 }; 2969 };
3092 }; 2970 };
3093 }; 2971 };
3094 2972
3095 etm@7040000 { 2973 etm@7040000 {
3096 compatible = "arm,cor 2974 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 2975 reg = <0 0x07040000 0 0x1000>;
3098 2976
3099 cpu = <&CPU0>; 2977 cpu = <&CPU0>;
3100 2978
3101 clocks = <&aoss_qmp>; 2979 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 2980 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 2981 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 2982 qcom,skip-power-up;
3105 2983
3106 out-ports { 2984 out-ports {
3107 port { 2985 port {
3108 etm0_ 2986 etm0_out: endpoint {
3109 2987 remote-endpoint = <&apss_funnel_in0>;
3110 }; 2988 };
3111 }; 2989 };
3112 }; 2990 };
3113 }; 2991 };
3114 2992
3115 etm@7140000 { 2993 etm@7140000 {
3116 compatible = "arm,cor 2994 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 2995 reg = <0 0x07140000 0 0x1000>;
3118 2996
3119 cpu = <&CPU1>; 2997 cpu = <&CPU1>;
3120 2998
3121 clocks = <&aoss_qmp>; 2999 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3000 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3001 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3002 qcom,skip-power-up;
3125 3003
3126 out-ports { 3004 out-ports {
3127 port { 3005 port {
3128 etm1_ 3006 etm1_out: endpoint {
3129 3007 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3008 };
3131 }; 3009 };
3132 }; 3010 };
3133 }; 3011 };
3134 3012
3135 etm@7240000 { 3013 etm@7240000 {
3136 compatible = "arm,cor 3014 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3015 reg = <0 0x07240000 0 0x1000>;
3138 3016
3139 cpu = <&CPU2>; 3017 cpu = <&CPU2>;
3140 3018
3141 clocks = <&aoss_qmp>; 3019 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3020 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3021 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3022 qcom,skip-power-up;
3145 3023
3146 out-ports { 3024 out-ports {
3147 port { 3025 port {
3148 etm2_ 3026 etm2_out: endpoint {
3149 3027 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3028 };
3151 }; 3029 };
3152 }; 3030 };
3153 }; 3031 };
3154 3032
3155 etm@7340000 { 3033 etm@7340000 {
3156 compatible = "arm,cor 3034 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3035 reg = <0 0x07340000 0 0x1000>;
3158 3036
3159 cpu = <&CPU3>; 3037 cpu = <&CPU3>;
3160 3038
3161 clocks = <&aoss_qmp>; 3039 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3040 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3041 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3042 qcom,skip-power-up;
3165 3043
3166 out-ports { 3044 out-ports {
3167 port { 3045 port {
3168 etm3_ 3046 etm3_out: endpoint {
3169 3047 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3048 };
3171 }; 3049 };
3172 }; 3050 };
3173 }; 3051 };
3174 3052
3175 etm@7440000 { 3053 etm@7440000 {
3176 compatible = "arm,cor 3054 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3055 reg = <0 0x07440000 0 0x1000>;
3178 3056
3179 cpu = <&CPU4>; 3057 cpu = <&CPU4>;
3180 3058
3181 clocks = <&aoss_qmp>; 3059 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3060 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3061 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3062 qcom,skip-power-up;
3185 3063
3186 out-ports { 3064 out-ports {
3187 port { 3065 port {
3188 etm4_ 3066 etm4_out: endpoint {
3189 3067 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3068 };
3191 }; 3069 };
3192 }; 3070 };
3193 }; 3071 };
3194 3072
3195 etm@7540000 { 3073 etm@7540000 {
3196 compatible = "arm,cor 3074 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3075 reg = <0 0x07540000 0 0x1000>;
3198 3076
3199 cpu = <&CPU5>; 3077 cpu = <&CPU5>;
3200 3078
3201 clocks = <&aoss_qmp>; 3079 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3080 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3081 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3082 qcom,skip-power-up;
3205 3083
3206 out-ports { 3084 out-ports {
3207 port { 3085 port {
3208 etm5_ 3086 etm5_out: endpoint {
3209 3087 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3088 };
3211 }; 3089 };
3212 }; 3090 };
3213 }; 3091 };
3214 3092
3215 etm@7640000 { 3093 etm@7640000 {
3216 compatible = "arm,cor 3094 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3095 reg = <0 0x07640000 0 0x1000>;
3218 3096
3219 cpu = <&CPU6>; 3097 cpu = <&CPU6>;
3220 3098
3221 clocks = <&aoss_qmp>; 3099 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3100 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3101 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3102 qcom,skip-power-up;
3225 3103
3226 out-ports { 3104 out-ports {
3227 port { 3105 port {
3228 etm6_ 3106 etm6_out: endpoint {
3229 3107 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3108 };
3231 }; 3109 };
3232 }; 3110 };
3233 }; 3111 };
3234 3112
3235 etm@7740000 { 3113 etm@7740000 {
3236 compatible = "arm,cor 3114 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3115 reg = <0 0x07740000 0 0x1000>;
3238 3116
3239 cpu = <&CPU7>; 3117 cpu = <&CPU7>;
3240 3118
3241 clocks = <&aoss_qmp>; 3119 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3120 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3121 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3122 qcom,skip-power-up;
3245 3123
3246 out-ports { 3124 out-ports {
3247 port { 3125 port {
3248 etm7_ 3126 etm7_out: endpoint {
3249 3127 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3128 };
3251 }; 3129 };
3252 }; 3130 };
3253 }; 3131 };
3254 3132
3255 funnel@7800000 { /* APSS Funn 3133 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3134 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3135 reg = <0 0x07800000 0 0x1000>;
3258 3136
3259 clocks = <&aoss_qmp>; 3137 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3138 clock-names = "apb_pclk";
3261 3139
3262 out-ports { 3140 out-ports {
3263 port { 3141 port {
3264 apss_ 3142 apss_funnel_out: endpoint {
3265 3143 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3144 };
3267 }; 3145 };
3268 }; 3146 };
3269 3147
3270 in-ports { 3148 in-ports {
3271 #address-cell 3149 #address-cells = <1>;
3272 #size-cells = 3150 #size-cells = <0>;
3273 3151
3274 port@0 { 3152 port@0 {
3275 reg = 3153 reg = <0>;
3276 apss_ 3154 apss_funnel_in0: endpoint {
3277 3155 remote-endpoint = <&etm0_out>;
3278 }; 3156 };
3279 }; 3157 };
3280 3158
3281 port@1 { 3159 port@1 {
3282 reg = 3160 reg = <1>;
3283 apss_ 3161 apss_funnel_in1: endpoint {
3284 3162 remote-endpoint = <&etm1_out>;
3285 }; 3163 };
3286 }; 3164 };
3287 3165
3288 port@2 { 3166 port@2 {
3289 reg = 3167 reg = <2>;
3290 apss_ 3168 apss_funnel_in2: endpoint {
3291 3169 remote-endpoint = <&etm2_out>;
3292 }; 3170 };
3293 }; 3171 };
3294 3172
3295 port@3 { 3173 port@3 {
3296 reg = 3174 reg = <3>;
3297 apss_ 3175 apss_funnel_in3: endpoint {
3298 3176 remote-endpoint = <&etm3_out>;
3299 }; 3177 };
3300 }; 3178 };
3301 3179
3302 port@4 { 3180 port@4 {
3303 reg = 3181 reg = <4>;
3304 apss_ 3182 apss_funnel_in4: endpoint {
3305 3183 remote-endpoint = <&etm4_out>;
3306 }; 3184 };
3307 }; 3185 };
3308 3186
3309 port@5 { 3187 port@5 {
3310 reg = 3188 reg = <5>;
3311 apss_ 3189 apss_funnel_in5: endpoint {
3312 3190 remote-endpoint = <&etm5_out>;
3313 }; 3191 };
3314 }; 3192 };
3315 3193
3316 port@6 { 3194 port@6 {
3317 reg = 3195 reg = <6>;
3318 apss_ 3196 apss_funnel_in6: endpoint {
3319 3197 remote-endpoint = <&etm6_out>;
3320 }; 3198 };
3321 }; 3199 };
3322 3200
3323 port@7 { 3201 port@7 {
3324 reg = 3202 reg = <7>;
3325 apss_ 3203 apss_funnel_in7: endpoint {
3326 3204 remote-endpoint = <&etm7_out>;
3327 }; 3205 };
3328 }; 3206 };
3329 }; 3207 };
3330 }; 3208 };
3331 3209
3332 funnel@7810000 { 3210 funnel@7810000 {
3333 compatible = "arm,cor 3211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3212 reg = <0 0x07810000 0 0x1000>;
3335 3213
3336 clocks = <&aoss_qmp>; 3214 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3215 clock-names = "apb_pclk";
3338 3216
3339 out-ports { 3217 out-ports {
3340 port { 3218 port {
3341 apss_ 3219 apss_merge_funnel_out: endpoint {
3342 3220 remote-endpoint = <&funnel2_in2>;
3343 }; 3221 };
3344 }; 3222 };
3345 }; 3223 };
3346 3224
3347 in-ports { 3225 in-ports {
3348 port { 3226 port {
3349 apss_ 3227 apss_merge_funnel_in: endpoint {
3350 3228 remote-endpoint = <&apss_funnel_out>;
3351 }; 3229 };
3352 }; 3230 };
3353 }; 3231 };
3354 }; 3232 };
3355 3233
3356 remoteproc_cdsp: remoteproc@8 3234 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3235 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3236 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3237
3360 interrupts-extended = 3238 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3239 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3240 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3241 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3242 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3243 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3244 "handover", "stop-ack";
3367 3245
3368 clocks = <&rpmhcc RPM 3246 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3247 clock-names = "xo";
3370 3248
3371 power-domains = <&rpm 3249 power-domains = <&rpmhpd SM8150_CX>;
3372 3250
3373 memory-region = <&cds 3251 memory-region = <&cdsp_mem>;
3374 3252
3375 qcom,qmp = <&aoss_qmp 3253 qcom,qmp = <&aoss_qmp>;
3376 3254
3377 qcom,smem-states = <& 3255 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3256 qcom,smem-state-names = "stop";
3379 3257
3380 status = "disabled"; 3258 status = "disabled";
3381 3259
3382 glink-edge { 3260 glink-edge {
3383 interrupts = 3261 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3262 label = "cdsp";
3385 qcom,remote-p 3263 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3264 mboxes = <&apss_shared 4>;
3387 3265
3388 fastrpc { 3266 fastrpc {
3389 compa 3267 compatible = "qcom,fastrpc";
3390 qcom, 3268 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3269 label = "cdsp";
3392 qcom, 3270 qcom,non-secure-domain;
3393 #addr 3271 #address-cells = <1>;
3394 #size 3272 #size-cells = <0>;
3395 3273
3396 compu 3274 compute-cb@1 {
3397 3275 compatible = "qcom,fastrpc-compute-cb";
3398 3276 reg = <1>;
3399 3277 iommus = <&apps_smmu 0x1001 0x0460>;
3400 }; 3278 };
3401 3279
3402 compu 3280 compute-cb@2 {
3403 3281 compatible = "qcom,fastrpc-compute-cb";
3404 3282 reg = <2>;
3405 3283 iommus = <&apps_smmu 0x1002 0x0460>;
3406 }; 3284 };
3407 3285
3408 compu 3286 compute-cb@3 {
3409 3287 compatible = "qcom,fastrpc-compute-cb";
3410 3288 reg = <3>;
3411 3289 iommus = <&apps_smmu 0x1003 0x0460>;
3412 }; 3290 };
3413 3291
3414 compu 3292 compute-cb@4 {
3415 3293 compatible = "qcom,fastrpc-compute-cb";
3416 3294 reg = <4>;
3417 3295 iommus = <&apps_smmu 0x1004 0x0460>;
3418 }; 3296 };
3419 3297
3420 compu 3298 compute-cb@5 {
3421 3299 compatible = "qcom,fastrpc-compute-cb";
3422 3300 reg = <5>;
3423 3301 iommus = <&apps_smmu 0x1005 0x0460>;
3424 }; 3302 };
3425 3303
3426 compu 3304 compute-cb@6 {
3427 3305 compatible = "qcom,fastrpc-compute-cb";
3428 3306 reg = <6>;
3429 3307 iommus = <&apps_smmu 0x1006 0x0460>;
3430 }; 3308 };
3431 3309
3432 compu 3310 compute-cb@7 {
3433 3311 compatible = "qcom,fastrpc-compute-cb";
3434 3312 reg = <7>;
3435 3313 iommus = <&apps_smmu 0x1007 0x0460>;
3436 }; 3314 };
3437 3315
3438 compu 3316 compute-cb@8 {
3439 3317 compatible = "qcom,fastrpc-compute-cb";
3440 3318 reg = <8>;
3441 3319 iommus = <&apps_smmu 0x1008 0x0460>;
3442 }; 3320 };
3443 3321
3444 /* no 3322 /* note: secure cb9 in downstream */
3445 }; 3323 };
3446 }; 3324 };
3447 }; 3325 };
3448 3326
3449 usb_1_hsphy: phy@88e2000 { 3327 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3328 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3329 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3330 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3331 status = "disabled";
3454 #phy-cells = <0>; 3332 #phy-cells = <0>;
3455 3333
3456 clocks = <&rpmhcc RPM 3334 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3335 clock-names = "ref";
3458 3336
3459 resets = <&gcc GCC_QU 3337 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3338 };
3461 3339
3462 usb_2_hsphy: phy@88e3000 { 3340 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3341 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3342 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3343 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3344 status = "disabled";
3467 #phy-cells = <0>; 3345 #phy-cells = <0>;
3468 3346
3469 clocks = <&rpmhcc RPM 3347 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3348 clock-names = "ref";
3471 3349
3472 resets = <&gcc GCC_QU 3350 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3351 };
3474 3352
3475 usb_1_qmpphy: phy@88e8000 { !! 3353 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 3354 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 3355 reg = <0 0x088e9000 0 0x18c>,
>> 3356 <0 0x088e8000 0 0x10>;
>> 3357 status = "disabled";
>> 3358 #address-cells = <2>;
>> 3359 #size-cells = <2>;
>> 3360 ranges;
3478 3361
3479 clocks = <&gcc GCC_US 3362 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3363 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3364 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3365 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3366 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3367
3488 resets = <&gcc GCC_US 3368 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3369 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3370 reset-names = "phy", "common";
3491 3371
3492 #clock-cells = <1>; !! 3372 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3373 reg = <0 0x088e9200 0 0x200>,
3494 !! 3374 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3375 <0 0x088e9c00 0 0x218>,
3496 !! 3376 <0 0x088e9600 0 0x200>,
3497 ports { !! 3377 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3378 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3379 #clock-cells = <0>;
3500 !! 3380 #phy-cells = <0>;
3501 port@0 { !! 3381 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3382 clock-names = "pipe0";
3503 !! 3383 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3384 };
3524 }; 3385 };
3525 3386
3526 usb_2_qmpphy: phy@88eb000 { 3387 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3388 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3389 reg = <0 0x088eb000 0 0x200>;
>> 3390 status = "disabled";
>> 3391 #address-cells = <2>;
>> 3392 #size-cells = <2>;
>> 3393 ranges;
3529 3394
3530 clocks = <&gcc GCC_US 3395 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3396 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3397 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3398 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3399 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 3400
3542 resets = <&gcc GCC_US !! 3401 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3543 <&gcc GCC_US !! 3402 <&gcc GCC_USB3_PHY_SEC_BCR>;
3544 reset-names = "phy", !! 3403 reset-names = "phy", "common";
3545 "phy_ph <<
3546 3404
3547 status = "disabled"; !! 3405 usb_2_ssphy: phy@88eb200 {
>> 3406 reg = <0 0x088eb200 0 0x200>,
>> 3407 <0 0x088eb400 0 0x200>,
>> 3408 <0 0x088eb800 0 0x800>,
>> 3409 <0 0x088eb600 0 0x200>;
>> 3410 #clock-cells = <0>;
>> 3411 #phy-cells = <0>;
>> 3412 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3413 clock-names = "pipe0";
>> 3414 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3415 };
3548 }; 3416 };
3549 3417
3550 sdhc_2: mmc@8804000 { 3418 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm 3419 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3420 reg = <0 0x08804000 0 0x1000>;
3553 3421
3554 interrupts = <GIC_SPI 3422 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3423 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3424 interrupt-names = "hc_irq", "pwr_irq";
3557 3425
3558 clocks = <&gcc GCC_SD 3426 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3427 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3428 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3429 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3430 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3431 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3432 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3433 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3434 operating-points-v2 = <&sdhc2_opp_table>;
3567 3435
3568 status = "disabled"; 3436 status = "disabled";
3569 3437
3570 sdhc2_opp_table: opp- 3438 sdhc2_opp_table: opp-table {
3571 compatible = 3439 compatible = "operating-points-v2";
3572 3440
3573 opp-19200000 3441 opp-19200000 {
3574 opp-h 3442 opp-hz = /bits/ 64 <19200000>;
3575 requi 3443 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3444 };
3577 3445
3578 opp-50000000 3446 opp-50000000 {
3579 opp-h 3447 opp-hz = /bits/ 64 <50000000>;
3580 requi 3448 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3449 };
3582 3450
3583 opp-100000000 3451 opp-100000000 {
3584 opp-h 3452 opp-hz = /bits/ 64 <100000000>;
3585 requi 3453 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3454 };
3587 3455
3588 opp-202000000 3456 opp-202000000 {
3589 opp-h 3457 opp-hz = /bits/ 64 <202000000>;
3590 requi 3458 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3459 };
3592 }; 3460 };
3593 }; 3461 };
3594 3462
3595 dc_noc: interconnect@9160000 3463 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3464 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3465 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3466 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3467 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3468 };
3601 3469
3602 gem_noc: interconnect@9680000 3470 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3471 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3472 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3473 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3474 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3475 };
3608 3476
3609 usb_1: usb@a6f8800 { 3477 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3478 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3479 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3480 status = "disabled";
3613 #address-cells = <2>; 3481 #address-cells = <2>;
3614 #size-cells = <2>; 3482 #size-cells = <2>;
3615 ranges; 3483 ranges;
3616 dma-ranges; 3484 dma-ranges;
3617 3485
3618 clocks = <&gcc GCC_CF 3486 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3487 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3488 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3489 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3490 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3491 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3492 clock-names = "cfg_noc",
3625 "core", 3493 "core",
3626 "iface" 3494 "iface",
3627 "sleep" 3495 "sleep",
3628 "mock_u 3496 "mock_utmi",
3629 "xo"; 3497 "xo";
3630 3498
3631 assigned-clocks = <&g 3499 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3500 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3501 assigned-clock-rates = <19200000>, <200000000>;
3634 3502
3635 interrupts-extended = !! 3503 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3504 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3505 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 3506 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 3507 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3508 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3509
3646 power-domains = <&gcc 3510 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3511
3648 resets = <&gcc GCC_US 3512 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3513
3650 interconnects = <&agg <<
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 3514 usb_1_dwc3: usb@a600000 {
3655 compatible = 3515 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3516 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3517 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3518 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3519 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3520 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3521 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3522 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3523 };
3684 }; 3524 };
3685 3525
3686 usb_2: usb@a8f8800 { 3526 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3527 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3528 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3529 status = "disabled";
3690 #address-cells = <2>; 3530 #address-cells = <2>;
3691 #size-cells = <2>; 3531 #size-cells = <2>;
3692 ranges; 3532 ranges;
3693 dma-ranges; 3533 dma-ranges;
3694 3534
3695 clocks = <&gcc GCC_CF 3535 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3536 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3537 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3538 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3539 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3540 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3541 clock-names = "cfg_noc",
3702 "core", 3542 "core",
3703 "iface" 3543 "iface",
3704 "sleep" 3544 "sleep",
3705 "mock_u 3545 "mock_utmi",
3706 "xo"; 3546 "xo";
3707 3547
3708 assigned-clocks = <&g 3548 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3549 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3550 assigned-clock-rates = <19200000>, <200000000>;
3711 3551
3712 interrupts-extended = !! 3552 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3553 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3554 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 3555 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 3556 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3557 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3558
3723 power-domains = <&gcc 3559 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3560
3725 resets = <&gcc GCC_US 3561 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3562
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3563 usb_2_dwc3: usb@a800000 {
3732 compatible = 3564 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3565 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3566 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3567 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3568 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3569 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3570 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3571 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3572 };
3741 }; 3573 };
3742 3574
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3575 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3576 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3577 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3578 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3579 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3580 };
3762 3581
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 <<
3776 compatible = "qcom,sm <<
3777 reg = <0 0x0ae00000 0 <<
3778 reg-names = "mdss"; <<
3779 <<
3780 interconnects = <&mms <<
3781 <&mms <<
3782 interconnect-names = <<
3783 <<
3784 power-domains = <&dis <<
3785 <<
3786 clocks = <&dispcc DIS <<
3787 <&gcc GCC_DI <<
3788 <&gcc GCC_DI <<
3789 <&dispcc DIS <<
3790 clock-names = "iface" <<
3791 <<
3792 interrupts = <GIC_SPI <<
3793 interrupt-controller; <<
3794 #interrupt-cells = <1 <<
3795 <<
3796 iommus = <&apps_smmu <<
3797 <<
3798 status = "disabled"; <<
3799 <<
3800 #address-cells = <2>; <<
3801 #size-cells = <2>; <<
3802 ranges; <<
3803 <<
3804 mdss_mdp: display-con <<
3805 compatible = <<
3806 reg = <0 0x0a <<
3807 <0 0x0a <<
3808 reg-names = " <<
3809 <<
3810 clocks = <&di <<
3811 <&gc <<
3812 <&di <<
3813 <&di <<
3814 clock-names = <<
3815 <<
3816 assigned-cloc <<
3817 assigned-cloc <<
3818 <<
3819 operating-poi <<
3820 power-domains <<
3821 <<
3822 interrupt-par <<
3823 interrupts = <<
3824 <<
3825 ports { <<
3826 #addr <<
3827 #size <<
3828 <<
3829 port@ <<
3830 <<
3831 <<
3832 <<
3833 <<
3834 }; <<
3835 <<
3836 port@ <<
3837 <<
3838 <<
3839 <<
3840 <<
3841 }; <<
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; <<
3850 <<
3851 mdp_opp_table <<
3852 compa <<
3853 <<
3854 opp-1 <<
3855 <<
3856 <<
3857 }; <<
3858 <<
3859 opp-3 <<
3860 <<
3861 <<
3862 }; <<
3863 <<
3864 opp-3 <<
3865 <<
3866 <<
3867 }; <<
3868 <<
3869 opp-4 <<
3870 <<
3871 <<
3872 }; <<
3873 }; <<
3874 }; <<
3875 <<
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 <<
3958 compatible = <<
3959 reg = <0 0x0a <<
3960 reg-names = " <<
3961 <<
3962 interrupt-par <<
3963 interrupts = <<
3964 <<
3965 clocks = <&di <<
3966 <&di <<
3967 <&di <<
3968 <&di <<
3969 <&di <<
3970 <&gc <<
3971 clock-names = <<
3972 <<
3973 <<
3974 <<
3975 <<
3976 <<
3977 <<
3978 assigned-cloc <<
3979 <<
3980 assigned-cloc <<
3981 <<
3982 <<
3983 operating-poi <<
3984 power-domains <<
3985 <<
3986 phys = <&mdss <<
3987 <<
3988 status = "dis <<
3989 <<
3990 #address-cell <<
3991 #size-cells = <<
3992 <<
3993 ports { <<
3994 #addr <<
3995 #size <<
3996 <<
3997 port@ <<
3998 <<
3999 <<
4000 <<
4001 <<
4002 }; <<
4003 <<
4004 port@ <<
4005 <<
4006 <<
4007 <<
4008 }; <<
4009 }; <<
4010 <<
4011 dsi_opp_table <<
4012 compa <<
4013 <<
4014 opp-1 <<
4015 <<
4016 <<
4017 }; <<
4018 <<
4019 opp-3 <<
4020 <<
4021 <<
4022 }; <<
4023 <<
4024 opp-3 <<
4025 <<
4026 <<
4027 }; <<
4028 }; <<
4029 }; <<
4030 <<
4031 mdss_dsi0_phy: phy@ae <<
4032 compatible = <<
4033 reg = <0 0x0a <<
4034 <0 0x0a <<
4035 <0 0x0a <<
4036 reg-names = " <<
4037 " <<
4038 " <<
4039 <<
4040 #clock-cells <<
4041 #phy-cells = <<
4042 <<
4043 clocks = <&di <<
4044 <&rp <<
4045 clock-names = <<
4046 <<
4047 status = "dis <<
4048 }; <<
4049 <<
4050 mdss_dsi1: dsi@ae9600 <<
4051 compatible = <<
4052 reg = <0 0x0a <<
4053 reg-names = " <<
4054 <<
4055 interrupt-par <<
4056 interrupts = <<
4057 <<
4058 clocks = <&di <<
4059 <&di <<
4060 <&di <<
4061 <&di <<
4062 <&di <<
4063 <&gc <<
4064 clock-names = <<
4065 <<
4066 <<
4067 <<
4068 <<
4069 <<
4070 <<
4071 assigned-cloc <<
4072 <<
4073 assigned-cloc <<
4074 <<
4075 <<
4076 operating-poi <<
4077 power-domains <<
4078 <<
4079 phys = <&mdss <<
4080 <<
4081 status = "dis <<
4082 <<
4083 #address-cell <<
4084 #size-cells = <<
4085 <<
4086 ports { <<
4087 #addr <<
4088 #size <<
4089 <<
4090 port@ <<
4091 <<
4092 <<
4093 <<
4094 <<
4095 }; <<
4096 <<
4097 port@ <<
4098 <<
4099 <<
4100 <<
4101 }; <<
4102 }; <<
4103 }; <<
4104 <<
4105 mdss_dsi1_phy: phy@ae <<
4106 compatible = <<
4107 reg = <0 0x0a <<
4108 <0 0x0a <<
4109 <0 0x0a <<
4110 reg-names = " <<
4111 " <<
4112 " <<
4113 <<
4114 #clock-cells <<
4115 #phy-cells = <<
4116 <<
4117 clocks = <&di <<
4118 <&rp <<
4119 clock-names = <<
4120 <<
4121 status = "dis <<
4122 }; <<
4123 }; <<
4124 <<
4125 dispcc: clock-controller@af00 <<
4126 compatible = "qcom,sm <<
4127 reg = <0 0x0af00000 0 <<
4128 clocks = <&rpmhcc RPM <<
4129 <&mdss_dsi0_ <<
4130 <&mdss_dsi0_ <<
4131 <&mdss_dsi1_ <<
4132 <&mdss_dsi1_ <<
4133 <&usb_1_qmpp <<
4134 <&usb_1_qmpp <<
4135 clock-names = "bi_tcx <<
4136 "dsi0_p <<
4137 "dsi0_p <<
4138 "dsi1_p <<
4139 "dsi1_p <<
4140 "dp_phy <<
4141 "dp_phy <<
4142 power-domains = <&rpm <<
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; <<
4145 #reset-cells = <1>; <<
4146 #power-domain-cells = <<
4147 }; <<
4148 <<
4149 pdc: interrupt-controller@b22 3582 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 3583 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 !! 3584 reg = <0 0x0b220000 0 0x400>;
4152 qcom,pdc-ranges = <0 3585 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 3586 <125 63 1>;
4154 #interrupt-cells = <2 3587 #interrupt-cells = <2>;
4155 interrupt-parent = <& 3588 interrupt-parent = <&intc>;
4156 interrupt-controller; 3589 interrupt-controller;
4157 }; 3590 };
4158 3591
4159 aoss_qmp: power-management@c3 !! 3592 aoss_qmp: power-controller@c300000 {
4160 compatible = "qcom,sm 3593 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 3594 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 3595 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3596 mboxes = <&apss_shared 0>;
4164 3597
4165 #clock-cells = <0>; 3598 #clock-cells = <0>;
4166 }; 3599 };
4167 3600
4168 sram@c3f0000 { 3601 sram@c3f0000 {
4169 compatible = "qcom,rp 3602 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 3603 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 3604 };
4172 3605
4173 tsens0: thermal-sensor@c26300 3606 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3607 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3608 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3609 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3610 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3611 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3612 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3613 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3614 #thermal-sensor-cells = <1>;
4182 }; 3615 };
4183 3616
4184 tsens1: thermal-sensor@c26500 3617 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3618 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3619 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3620 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3621 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3622 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3623 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3624 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3625 #thermal-sensor-cells = <1>;
4193 }; 3626 };
4194 3627
4195 spmi_bus: spmi@c440000 { 3628 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3629 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3630 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3631 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3632 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3633 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3634 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3635 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3636 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3637 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3638 qcom,ee = <0>;
4206 qcom,channel = <0>; 3639 qcom,channel = <0>;
4207 #address-cells = <2>; 3640 #address-cells = <2>;
4208 #size-cells = <0>; 3641 #size-cells = <0>;
4209 interrupt-controller; 3642 interrupt-controller;
4210 #interrupt-cells = <4 3643 #interrupt-cells = <4>;
>> 3644 cell-index = <0>;
4211 }; 3645 };
4212 3646
4213 apps_smmu: iommu@15000000 { 3647 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3648 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3649 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3650 #iommu-cells = <2>;
4217 #global-interrupts = 3651 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3652 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3653 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3654 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3655 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3656 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3657 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3658 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3659 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3660 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3661 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3662 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3663 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3664 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3665 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3666 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3667 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3668 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3669 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3670 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3671 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3672 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3673 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3674 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3675 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3676 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3677 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3678 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3679 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3680 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3681 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3682 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3683 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3684 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3685 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3686 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3687 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3688 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3689 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3690 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3691 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3692 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3693 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 3694 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 3695 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 3696 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 3697 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 3698 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 3699 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 3700 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 3701 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 3702 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 3703 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 3704 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 3705 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 3706 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 3707 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 3708 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 3709 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 3710 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 3711 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 3712 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 3713 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 3714 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 3715 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 3716 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 3717 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 3718 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 3719 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 3720 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 3721 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 3722 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 3723 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 3724 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 3725 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 3726 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 3727 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 3728 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 3729 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 3730 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 3731 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 3732 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 3733 };
4300 3734
4301 remoteproc_adsp: remoteproc@1 3735 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 3736 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 3737 reg = <0x0 0x17300000 0x0 0x4040>;
4304 3738
4305 interrupts-extended = 3739 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 3740 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 3741 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 3742 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 3743 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 3744 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 3745 "handover", "stop-ack";
4312 3746
4313 clocks = <&rpmhcc RPM 3747 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 3748 clock-names = "xo";
4315 3749
4316 power-domains = <&rpm 3750 power-domains = <&rpmhpd SM8150_CX>;
4317 3751
4318 memory-region = <&ads 3752 memory-region = <&adsp_mem>;
4319 3753
4320 qcom,qmp = <&aoss_qmp 3754 qcom,qmp = <&aoss_qmp>;
4321 3755
4322 qcom,smem-states = <& 3756 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 3757 qcom,smem-state-names = "stop";
4324 3758
4325 status = "disabled"; 3759 status = "disabled";
4326 3760
4327 glink-edge { 3761 glink-edge {
4328 interrupts = 3762 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 3763 label = "lpass";
4330 qcom,remote-p 3764 qcom,remote-pid = <2>;
4331 mboxes = <&ap 3765 mboxes = <&apss_shared 8>;
4332 3766
4333 fastrpc { 3767 fastrpc {
4334 compa 3768 compatible = "qcom,fastrpc";
4335 qcom, 3769 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 3770 label = "adsp";
4337 qcom, 3771 qcom,non-secure-domain;
4338 #addr 3772 #address-cells = <1>;
4339 #size 3773 #size-cells = <0>;
4340 3774
4341 compu 3775 compute-cb@3 {
4342 3776 compatible = "qcom,fastrpc-compute-cb";
4343 3777 reg = <3>;
4344 3778 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 3779 };
4346 3780
4347 compu 3781 compute-cb@4 {
4348 3782 compatible = "qcom,fastrpc-compute-cb";
4349 3783 reg = <4>;
4350 3784 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 3785 };
4352 3786
4353 compu 3787 compute-cb@5 {
4354 3788 compatible = "qcom,fastrpc-compute-cb";
4355 3789 reg = <5>;
4356 3790 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 3791 };
4358 }; 3792 };
4359 }; 3793 };
4360 }; 3794 };
4361 3795
4362 intc: interrupt-controller@17 3796 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 3797 compatible = "arm,gic-v3";
4364 interrupt-controller; 3798 interrupt-controller;
4365 #interrupt-cells = <3 3799 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 3800 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 3801 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 3802 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 3803 };
4370 3804
4371 apss_shared: mailbox@17c00000 3805 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 3806 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 3807 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 3808 #mbox-cells = <1>;
4376 }; 3809 };
4377 3810
4378 watchdog@17c10000 { 3811 watchdog@17c10000 {
4379 compatible = "qcom,ap 3812 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 3813 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 3814 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 3815 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 3816 };
4384 3817
4385 timer@17c20000 { 3818 timer@17c20000 {
4386 #address-cells = <1>; 3819 #address-cells = <1>;
4387 #size-cells = <1>; 3820 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 3821 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 3822 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 3823 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 3824 clock-frequency = <19200000>;
4392 3825
4393 frame@17c21000 { !! 3826 frame@17c21000{
4394 frame-number 3827 frame-number = <0>;
4395 interrupts = 3828 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 3829 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 3830 reg = <0x17c21000 0x1000>,
4398 <0x17c2 3831 <0x17c22000 0x1000>;
4399 }; 3832 };
4400 3833
4401 frame@17c23000 { 3834 frame@17c23000 {
4402 frame-number 3835 frame-number = <1>;
4403 interrupts = 3836 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 3837 reg = <0x17c23000 0x1000>;
4405 status = "dis 3838 status = "disabled";
4406 }; 3839 };
4407 3840
4408 frame@17c25000 { 3841 frame@17c25000 {
4409 frame-number 3842 frame-number = <2>;
4410 interrupts = 3843 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 3844 reg = <0x17c25000 0x1000>;
4412 status = "dis 3845 status = "disabled";
4413 }; 3846 };
4414 3847
4415 frame@17c27000 { 3848 frame@17c27000 {
4416 frame-number 3849 frame-number = <3>;
4417 interrupts = 3850 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 3851 reg = <0x17c26000 0x1000>;
4419 status = "dis 3852 status = "disabled";
4420 }; 3853 };
4421 3854
4422 frame@17c29000 { 3855 frame@17c29000 {
4423 frame-number 3856 frame-number = <4>;
4424 interrupts = 3857 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 3858 reg = <0x17c29000 0x1000>;
4426 status = "dis 3859 status = "disabled";
4427 }; 3860 };
4428 3861
4429 frame@17c2b000 { 3862 frame@17c2b000 {
4430 frame-number 3863 frame-number = <5>;
4431 interrupts = 3864 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 3865 reg = <0x17c2b000 0x1000>;
4433 status = "dis 3866 status = "disabled";
4434 }; 3867 };
4435 3868
4436 frame@17c2d000 { 3869 frame@17c2d000 {
4437 frame-number 3870 frame-number = <6>;
4438 interrupts = 3871 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 3872 reg = <0x17c2d000 0x1000>;
4440 status = "dis 3873 status = "disabled";
4441 }; 3874 };
4442 }; 3875 };
4443 3876
4444 apps_rsc: rsc@18200000 { 3877 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 3878 label = "apps_rsc";
4446 compatible = "qcom,rp 3879 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 3880 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 3881 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 3882 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 3883 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 3884 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 3885 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 3886 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 3887 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 3888 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 3889 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 3890 <SLEEP_TCS 3>,
4458 <WA 3891 <WAKE_TCS 3>,
4459 <CO 3892 <CONTROL_TCS 1>;
4460 power-domains = <&CLU 3893 power-domains = <&CLUSTER_PD>;
4461 3894
4462 rpmhcc: clock-control 3895 rpmhcc: clock-controller {
4463 compatible = 3896 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 3897 #clock-cells = <1>;
4465 clock-names = 3898 clock-names = "xo";
4466 clocks = <&xo 3899 clocks = <&xo_board>;
4467 }; 3900 };
4468 3901
4469 rpmhpd: power-control 3902 rpmhpd: power-controller {
4470 compatible = 3903 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 3904 #power-domain-cells = <1>;
4472 operating-poi 3905 operating-points-v2 = <&rpmhpd_opp_table>;
4473 3906
4474 rpmhpd_opp_ta 3907 rpmhpd_opp_table: opp-table {
4475 compa 3908 compatible = "operating-points-v2";
4476 3909
4477 rpmhp 3910 rpmhpd_opp_ret: opp1 {
4478 3911 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 3912 };
4480 3913
4481 rpmhp 3914 rpmhpd_opp_min_svs: opp2 {
4482 3915 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 3916 };
4484 3917
4485 rpmhp 3918 rpmhpd_opp_low_svs: opp3 {
4486 3919 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 3920 };
4488 3921
4489 rpmhp 3922 rpmhpd_opp_svs: opp4 {
4490 3923 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 3924 };
4492 3925
4493 rpmhp 3926 rpmhpd_opp_svs_l1: opp5 {
4494 3927 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 3928 };
4496 3929
4497 rpmhp 3930 rpmhpd_opp_svs_l2: opp6 {
4498 3931 opp-level = <224>;
4499 }; 3932 };
4500 3933
4501 rpmhp 3934 rpmhpd_opp_nom: opp7 {
4502 3935 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 3936 };
4504 3937
4505 rpmhp 3938 rpmhpd_opp_nom_l1: opp8 {
4506 3939 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 3940 };
4508 3941
4509 rpmhp 3942 rpmhpd_opp_nom_l2: opp9 {
4510 3943 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 3944 };
4512 3945
4513 rpmhp 3946 rpmhpd_opp_turbo: opp10 {
4514 3947 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 3948 };
4516 3949
4517 rpmhp 3950 rpmhpd_opp_turbo_l1: opp11 {
4518 3951 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 3952 };
4520 }; 3953 };
4521 }; 3954 };
4522 3955
4523 apps_bcm_voter: bcm-v 3956 apps_bcm_voter: bcm-voter {
4524 compatible = 3957 compatible = "qcom,bcm-voter";
4525 }; 3958 };
4526 }; 3959 };
4527 3960
4528 osm_l3: interconnect@18321000 3961 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm 3962 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 3963 reg = <0 0x18321000 0 0x1400>;
4531 3964
4532 clocks = <&rpmhcc RPM 3965 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 3966 clock-names = "xo", "alternate";
4534 3967
4535 #interconnect-cells = 3968 #interconnect-cells = <1>;
4536 }; 3969 };
4537 3970
4538 cpufreq_hw: cpufreq@18323000 3971 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 3972 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 3973 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 3974 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 3975 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 3976 "freq-domain2";
4544 3977
4545 clocks = <&rpmhcc RPM 3978 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 3979 clock-names = "xo", "alternate";
4547 3980
4548 #freq-domain-cells = 3981 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; 3982 };
4551 3983
4552 lmh_cluster1: lmh@18350800 { 3984 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 3985 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 3986 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 3987 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 3988 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 3989 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 3990 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 3991 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 3992 interrupt-controller;
4561 #interrupt-cells = <1 3993 #interrupt-cells = <1>;
4562 }; 3994 };
4563 3995
4564 lmh_cluster0: lmh@18358800 { 3996 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 3997 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 3998 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 3999 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4000 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4001 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4002 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4003 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4004 interrupt-controller;
4573 #interrupt-cells = <1 4005 #interrupt-cells = <1>;
4574 }; 4006 };
4575 4007
4576 wifi: wifi@18800000 { 4008 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4009 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4010 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4011 reg-names = "membase";
4580 memory-region = <&wla 4012 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4013 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4014 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4015 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4016 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4017 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4018 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4019 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4020 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4021 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4022 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4023 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4024 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4025 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4026 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4027 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4028 status = "disabled";
4597 }; 4029 };
4598 }; 4030 };
4599 4031
4600 timer { 4032 timer {
4601 compatible = "arm,armv8-timer 4033 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4034 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4035 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4036 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4037 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4038 };
4607 4039
4608 thermal-zones { 4040 thermal-zones {
4609 cpu0-thermal { 4041 cpu0-thermal {
4610 polling-delay-passive 4042 polling-delay-passive = <250>;
>> 4043 polling-delay = <1000>;
4611 4044
4612 thermal-sensors = <&t 4045 thermal-sensors = <&tsens0 1>;
4613 4046
4614 trips { 4047 trips {
4615 cpu0_alert0: 4048 cpu0_alert0: trip-point0 {
4616 tempe 4049 temperature = <90000>;
4617 hyste 4050 hysteresis = <2000>;
4618 type 4051 type = "passive";
4619 }; 4052 };
4620 4053
4621 cpu0_alert1: 4054 cpu0_alert1: trip-point1 {
4622 tempe 4055 temperature = <95000>;
4623 hyste 4056 hysteresis = <2000>;
4624 type 4057 type = "passive";
4625 }; 4058 };
4626 4059
4627 cpu0_crit: cp !! 4060 cpu0_crit: cpu_crit {
4628 tempe 4061 temperature = <110000>;
4629 hyste 4062 hysteresis = <1000>;
4630 type 4063 type = "critical";
4631 }; 4064 };
4632 }; 4065 };
4633 4066
4634 cooling-maps { 4067 cooling-maps {
4635 map0 { 4068 map0 {
4636 trip 4069 trip = <&cpu0_alert0>;
4637 cooli 4070 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4071 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4072 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4073 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4074 };
4642 map1 { 4075 map1 {
4643 trip 4076 trip = <&cpu0_alert1>;
4644 cooli 4077 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4078 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4079 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4080 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4081 };
4649 }; 4082 };
4650 }; 4083 };
4651 4084
4652 cpu1-thermal { 4085 cpu1-thermal {
4653 polling-delay-passive 4086 polling-delay-passive = <250>;
>> 4087 polling-delay = <1000>;
4654 4088
4655 thermal-sensors = <&t 4089 thermal-sensors = <&tsens0 2>;
4656 4090
4657 trips { 4091 trips {
4658 cpu1_alert0: 4092 cpu1_alert0: trip-point0 {
4659 tempe 4093 temperature = <90000>;
4660 hyste 4094 hysteresis = <2000>;
4661 type 4095 type = "passive";
4662 }; 4096 };
4663 4097
4664 cpu1_alert1: 4098 cpu1_alert1: trip-point1 {
4665 tempe 4099 temperature = <95000>;
4666 hyste 4100 hysteresis = <2000>;
4667 type 4101 type = "passive";
4668 }; 4102 };
4669 4103
4670 cpu1_crit: cp !! 4104 cpu1_crit: cpu_crit {
4671 tempe 4105 temperature = <110000>;
4672 hyste 4106 hysteresis = <1000>;
4673 type 4107 type = "critical";
4674 }; 4108 };
4675 }; 4109 };
4676 4110
4677 cooling-maps { 4111 cooling-maps {
4678 map0 { 4112 map0 {
4679 trip 4113 trip = <&cpu1_alert0>;
4680 cooli 4114 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4115 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4116 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4117 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4118 };
4685 map1 { 4119 map1 {
4686 trip 4120 trip = <&cpu1_alert1>;
4687 cooli 4121 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4122 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4123 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4124 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4125 };
4692 }; 4126 };
4693 }; 4127 };
4694 4128
4695 cpu2-thermal { 4129 cpu2-thermal {
4696 polling-delay-passive 4130 polling-delay-passive = <250>;
>> 4131 polling-delay = <1000>;
4697 4132
4698 thermal-sensors = <&t 4133 thermal-sensors = <&tsens0 3>;
4699 4134
4700 trips { 4135 trips {
4701 cpu2_alert0: 4136 cpu2_alert0: trip-point0 {
4702 tempe 4137 temperature = <90000>;
4703 hyste 4138 hysteresis = <2000>;
4704 type 4139 type = "passive";
4705 }; 4140 };
4706 4141
4707 cpu2_alert1: 4142 cpu2_alert1: trip-point1 {
4708 tempe 4143 temperature = <95000>;
4709 hyste 4144 hysteresis = <2000>;
4710 type 4145 type = "passive";
4711 }; 4146 };
4712 4147
4713 cpu2_crit: cp !! 4148 cpu2_crit: cpu_crit {
4714 tempe 4149 temperature = <110000>;
4715 hyste 4150 hysteresis = <1000>;
4716 type 4151 type = "critical";
4717 }; 4152 };
4718 }; 4153 };
4719 4154
4720 cooling-maps { 4155 cooling-maps {
4721 map0 { 4156 map0 {
4722 trip 4157 trip = <&cpu2_alert0>;
4723 cooli 4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4159 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4160 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4161 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4162 };
4728 map1 { 4163 map1 {
4729 trip 4164 trip = <&cpu2_alert1>;
4730 cooli 4165 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4166 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4167 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4168 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4169 };
4735 }; 4170 };
4736 }; 4171 };
4737 4172
4738 cpu3-thermal { 4173 cpu3-thermal {
4739 polling-delay-passive 4174 polling-delay-passive = <250>;
>> 4175 polling-delay = <1000>;
4740 4176
4741 thermal-sensors = <&t 4177 thermal-sensors = <&tsens0 4>;
4742 4178
4743 trips { 4179 trips {
4744 cpu3_alert0: 4180 cpu3_alert0: trip-point0 {
4745 tempe 4181 temperature = <90000>;
4746 hyste 4182 hysteresis = <2000>;
4747 type 4183 type = "passive";
4748 }; 4184 };
4749 4185
4750 cpu3_alert1: 4186 cpu3_alert1: trip-point1 {
4751 tempe 4187 temperature = <95000>;
4752 hyste 4188 hysteresis = <2000>;
4753 type 4189 type = "passive";
4754 }; 4190 };
4755 4191
4756 cpu3_crit: cp !! 4192 cpu3_crit: cpu_crit {
4757 tempe 4193 temperature = <110000>;
4758 hyste 4194 hysteresis = <1000>;
4759 type 4195 type = "critical";
4760 }; 4196 };
4761 }; 4197 };
4762 4198
4763 cooling-maps { 4199 cooling-maps {
4764 map0 { 4200 map0 {
4765 trip 4201 trip = <&cpu3_alert0>;
4766 cooli 4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4203 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4204 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4205 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4206 };
4771 map1 { 4207 map1 {
4772 trip 4208 trip = <&cpu3_alert1>;
4773 cooli 4209 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4210 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4211 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4212 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4213 };
4778 }; 4214 };
4779 }; 4215 };
4780 4216
4781 cpu4-top-thermal { 4217 cpu4-top-thermal {
4782 polling-delay-passive 4218 polling-delay-passive = <250>;
>> 4219 polling-delay = <1000>;
4783 4220
4784 thermal-sensors = <&t 4221 thermal-sensors = <&tsens0 7>;
4785 4222
4786 trips { 4223 trips {
4787 cpu4_top_aler 4224 cpu4_top_alert0: trip-point0 {
4788 tempe 4225 temperature = <90000>;
4789 hyste 4226 hysteresis = <2000>;
4790 type 4227 type = "passive";
4791 }; 4228 };
4792 4229
4793 cpu4_top_aler 4230 cpu4_top_alert1: trip-point1 {
4794 tempe 4231 temperature = <95000>;
4795 hyste 4232 hysteresis = <2000>;
4796 type 4233 type = "passive";
4797 }; 4234 };
4798 4235
4799 cpu4_top_crit !! 4236 cpu4_top_crit: cpu_crit {
4800 tempe 4237 temperature = <110000>;
4801 hyste 4238 hysteresis = <1000>;
4802 type 4239 type = "critical";
4803 }; 4240 };
4804 }; 4241 };
4805 4242
4806 cooling-maps { 4243 cooling-maps {
4807 map0 { 4244 map0 {
4808 trip 4245 trip = <&cpu4_top_alert0>;
4809 cooli 4246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4250 };
4814 map1 { 4251 map1 {
4815 trip 4252 trip = <&cpu4_top_alert1>;
4816 cooli 4253 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4254 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4255 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4256 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4257 };
4821 }; 4258 };
4822 }; 4259 };
4823 4260
4824 cpu5-top-thermal { 4261 cpu5-top-thermal {
4825 polling-delay-passive 4262 polling-delay-passive = <250>;
>> 4263 polling-delay = <1000>;
4826 4264
4827 thermal-sensors = <&t 4265 thermal-sensors = <&tsens0 8>;
4828 4266
4829 trips { 4267 trips {
4830 cpu5_top_aler 4268 cpu5_top_alert0: trip-point0 {
4831 tempe 4269 temperature = <90000>;
4832 hyste 4270 hysteresis = <2000>;
4833 type 4271 type = "passive";
4834 }; 4272 };
4835 4273
4836 cpu5_top_aler 4274 cpu5_top_alert1: trip-point1 {
4837 tempe 4275 temperature = <95000>;
4838 hyste 4276 hysteresis = <2000>;
4839 type 4277 type = "passive";
4840 }; 4278 };
4841 4279
4842 cpu5_top_crit !! 4280 cpu5_top_crit: cpu_crit {
4843 tempe 4281 temperature = <110000>;
4844 hyste 4282 hysteresis = <1000>;
4845 type 4283 type = "critical";
4846 }; 4284 };
4847 }; 4285 };
4848 4286
4849 cooling-maps { 4287 cooling-maps {
4850 map0 { 4288 map0 {
4851 trip 4289 trip = <&cpu5_top_alert0>;
4852 cooli 4290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4294 };
4857 map1 { 4295 map1 {
4858 trip 4296 trip = <&cpu5_top_alert1>;
4859 cooli 4297 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4298 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4299 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4300 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4301 };
4864 }; 4302 };
4865 }; 4303 };
4866 4304
4867 cpu6-top-thermal { 4305 cpu6-top-thermal {
4868 polling-delay-passive 4306 polling-delay-passive = <250>;
>> 4307 polling-delay = <1000>;
4869 4308
4870 thermal-sensors = <&t 4309 thermal-sensors = <&tsens0 9>;
4871 4310
4872 trips { 4311 trips {
4873 cpu6_top_aler 4312 cpu6_top_alert0: trip-point0 {
4874 tempe 4313 temperature = <90000>;
4875 hyste 4314 hysteresis = <2000>;
4876 type 4315 type = "passive";
4877 }; 4316 };
4878 4317
4879 cpu6_top_aler 4318 cpu6_top_alert1: trip-point1 {
4880 tempe 4319 temperature = <95000>;
4881 hyste 4320 hysteresis = <2000>;
4882 type 4321 type = "passive";
4883 }; 4322 };
4884 4323
4885 cpu6_top_crit !! 4324 cpu6_top_crit: cpu_crit {
4886 tempe 4325 temperature = <110000>;
4887 hyste 4326 hysteresis = <1000>;
4888 type 4327 type = "critical";
4889 }; 4328 };
4890 }; 4329 };
4891 4330
4892 cooling-maps { 4331 cooling-maps {
4893 map0 { 4332 map0 {
4894 trip 4333 trip = <&cpu6_top_alert0>;
4895 cooli 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4338 };
4900 map1 { 4339 map1 {
4901 trip 4340 trip = <&cpu6_top_alert1>;
4902 cooli 4341 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4342 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4343 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4344 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4345 };
4907 }; 4346 };
4908 }; 4347 };
4909 4348
4910 cpu7-top-thermal { 4349 cpu7-top-thermal {
4911 polling-delay-passive 4350 polling-delay-passive = <250>;
>> 4351 polling-delay = <1000>;
4912 4352
4913 thermal-sensors = <&t 4353 thermal-sensors = <&tsens0 10>;
4914 4354
4915 trips { 4355 trips {
4916 cpu7_top_aler 4356 cpu7_top_alert0: trip-point0 {
4917 tempe 4357 temperature = <90000>;
4918 hyste 4358 hysteresis = <2000>;
4919 type 4359 type = "passive";
4920 }; 4360 };
4921 4361
4922 cpu7_top_aler 4362 cpu7_top_alert1: trip-point1 {
4923 tempe 4363 temperature = <95000>;
4924 hyste 4364 hysteresis = <2000>;
4925 type 4365 type = "passive";
4926 }; 4366 };
4927 4367
4928 cpu7_top_crit !! 4368 cpu7_top_crit: cpu_crit {
4929 tempe 4369 temperature = <110000>;
4930 hyste 4370 hysteresis = <1000>;
4931 type 4371 type = "critical";
4932 }; 4372 };
4933 }; 4373 };
4934 4374
4935 cooling-maps { 4375 cooling-maps {
4936 map0 { 4376 map0 {
4937 trip 4377 trip = <&cpu7_top_alert0>;
4938 cooli 4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4379 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4380 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4381 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4382 };
4943 map1 { 4383 map1 {
4944 trip 4384 trip = <&cpu7_top_alert1>;
4945 cooli 4385 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4386 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4387 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4388 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4389 };
4950 }; 4390 };
4951 }; 4391 };
4952 4392
4953 cpu4-bottom-thermal { 4393 cpu4-bottom-thermal {
4954 polling-delay-passive 4394 polling-delay-passive = <250>;
>> 4395 polling-delay = <1000>;
4955 4396
4956 thermal-sensors = <&t 4397 thermal-sensors = <&tsens0 11>;
4957 4398
4958 trips { 4399 trips {
4959 cpu4_bottom_a 4400 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4401 temperature = <90000>;
4961 hyste 4402 hysteresis = <2000>;
4962 type 4403 type = "passive";
4963 }; 4404 };
4964 4405
4965 cpu4_bottom_a 4406 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4407 temperature = <95000>;
4967 hyste 4408 hysteresis = <2000>;
4968 type 4409 type = "passive";
4969 }; 4410 };
4970 4411
4971 cpu4_bottom_c !! 4412 cpu4_bottom_crit: cpu_crit {
4972 tempe 4413 temperature = <110000>;
4973 hyste 4414 hysteresis = <1000>;
4974 type 4415 type = "critical";
4975 }; 4416 };
4976 }; 4417 };
4977 4418
4978 cooling-maps { 4419 cooling-maps {
4979 map0 { 4420 map0 {
4980 trip 4421 trip = <&cpu4_bottom_alert0>;
4981 cooli 4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4423 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4424 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4425 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4426 };
4986 map1 { 4427 map1 {
4987 trip 4428 trip = <&cpu4_bottom_alert1>;
4988 cooli 4429 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4430 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4431 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4432 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4433 };
4993 }; 4434 };
4994 }; 4435 };
4995 4436
4996 cpu5-bottom-thermal { 4437 cpu5-bottom-thermal {
4997 polling-delay-passive 4438 polling-delay-passive = <250>;
>> 4439 polling-delay = <1000>;
4998 4440
4999 thermal-sensors = <&t 4441 thermal-sensors = <&tsens0 12>;
5000 4442
5001 trips { 4443 trips {
5002 cpu5_bottom_a 4444 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4445 temperature = <90000>;
5004 hyste 4446 hysteresis = <2000>;
5005 type 4447 type = "passive";
5006 }; 4448 };
5007 4449
5008 cpu5_bottom_a 4450 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4451 temperature = <95000>;
5010 hyste 4452 hysteresis = <2000>;
5011 type 4453 type = "passive";
5012 }; 4454 };
5013 4455
5014 cpu5_bottom_c !! 4456 cpu5_bottom_crit: cpu_crit {
5015 tempe 4457 temperature = <110000>;
5016 hyste 4458 hysteresis = <1000>;
5017 type 4459 type = "critical";
5018 }; 4460 };
5019 }; 4461 };
5020 4462
5021 cooling-maps { 4463 cooling-maps {
5022 map0 { 4464 map0 {
5023 trip 4465 trip = <&cpu5_bottom_alert0>;
5024 cooli 4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4467 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4468 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4469 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4470 };
5029 map1 { 4471 map1 {
5030 trip 4472 trip = <&cpu5_bottom_alert1>;
5031 cooli 4473 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4474 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4475 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4476 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4477 };
5036 }; 4478 };
5037 }; 4479 };
5038 4480
5039 cpu6-bottom-thermal { 4481 cpu6-bottom-thermal {
5040 polling-delay-passive 4482 polling-delay-passive = <250>;
>> 4483 polling-delay = <1000>;
5041 4484
5042 thermal-sensors = <&t 4485 thermal-sensors = <&tsens0 13>;
5043 4486
5044 trips { 4487 trips {
5045 cpu6_bottom_a 4488 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4489 temperature = <90000>;
5047 hyste 4490 hysteresis = <2000>;
5048 type 4491 type = "passive";
5049 }; 4492 };
5050 4493
5051 cpu6_bottom_a 4494 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4495 temperature = <95000>;
5053 hyste 4496 hysteresis = <2000>;
5054 type 4497 type = "passive";
5055 }; 4498 };
5056 4499
5057 cpu6_bottom_c !! 4500 cpu6_bottom_crit: cpu_crit {
5058 tempe 4501 temperature = <110000>;
5059 hyste 4502 hysteresis = <1000>;
5060 type 4503 type = "critical";
5061 }; 4504 };
5062 }; 4505 };
5063 4506
5064 cooling-maps { 4507 cooling-maps {
5065 map0 { 4508 map0 {
5066 trip 4509 trip = <&cpu6_bottom_alert0>;
5067 cooli 4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4514 };
5072 map1 { 4515 map1 {
5073 trip 4516 trip = <&cpu6_bottom_alert1>;
5074 cooli 4517 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4518 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4519 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4520 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4521 };
5079 }; 4522 };
5080 }; 4523 };
5081 4524
5082 cpu7-bottom-thermal { 4525 cpu7-bottom-thermal {
5083 polling-delay-passive 4526 polling-delay-passive = <250>;
>> 4527 polling-delay = <1000>;
5084 4528
5085 thermal-sensors = <&t 4529 thermal-sensors = <&tsens0 14>;
5086 4530
5087 trips { 4531 trips {
5088 cpu7_bottom_a 4532 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4533 temperature = <90000>;
5090 hyste 4534 hysteresis = <2000>;
5091 type 4535 type = "passive";
5092 }; 4536 };
5093 4537
5094 cpu7_bottom_a 4538 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4539 temperature = <95000>;
5096 hyste 4540 hysteresis = <2000>;
5097 type 4541 type = "passive";
5098 }; 4542 };
5099 4543
5100 cpu7_bottom_c !! 4544 cpu7_bottom_crit: cpu_crit {
5101 tempe 4545 temperature = <110000>;
5102 hyste 4546 hysteresis = <1000>;
5103 type 4547 type = "critical";
5104 }; 4548 };
5105 }; 4549 };
5106 4550
5107 cooling-maps { 4551 cooling-maps {
5108 map0 { 4552 map0 {
5109 trip 4553 trip = <&cpu7_bottom_alert0>;
5110 cooli 4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4558 };
5115 map1 { 4559 map1 {
5116 trip 4560 trip = <&cpu7_bottom_alert1>;
5117 cooli 4561 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4562 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4563 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4564 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4565 };
5122 }; 4566 };
5123 }; 4567 };
5124 4568
5125 aoss0-thermal { 4569 aoss0-thermal {
5126 polling-delay-passive 4570 polling-delay-passive = <250>;
>> 4571 polling-delay = <1000>;
5127 4572
5128 thermal-sensors = <&t 4573 thermal-sensors = <&tsens0 0>;
5129 4574
5130 trips { 4575 trips {
5131 aoss0_alert0: 4576 aoss0_alert0: trip-point0 {
5132 tempe 4577 temperature = <90000>;
5133 hyste 4578 hysteresis = <2000>;
5134 type 4579 type = "hot";
5135 }; 4580 };
5136 }; 4581 };
5137 }; 4582 };
5138 4583
5139 cluster0-thermal { 4584 cluster0-thermal {
5140 polling-delay-passive 4585 polling-delay-passive = <250>;
>> 4586 polling-delay = <1000>;
5141 4587
5142 thermal-sensors = <&t 4588 thermal-sensors = <&tsens0 5>;
5143 4589
5144 trips { 4590 trips {
5145 cluster0_aler 4591 cluster0_alert0: trip-point0 {
5146 tempe 4592 temperature = <90000>;
5147 hyste 4593 hysteresis = <2000>;
5148 type 4594 type = "hot";
5149 }; 4595 };
5150 cluster0_crit !! 4596 cluster0_crit: cluster0_crit {
5151 tempe 4597 temperature = <110000>;
5152 hyste 4598 hysteresis = <2000>;
5153 type 4599 type = "critical";
5154 }; 4600 };
5155 }; 4601 };
5156 }; 4602 };
5157 4603
5158 cluster1-thermal { 4604 cluster1-thermal {
5159 polling-delay-passive 4605 polling-delay-passive = <250>;
>> 4606 polling-delay = <1000>;
5160 4607
5161 thermal-sensors = <&t 4608 thermal-sensors = <&tsens0 6>;
5162 4609
5163 trips { 4610 trips {
5164 cluster1_aler 4611 cluster1_alert0: trip-point0 {
5165 tempe 4612 temperature = <90000>;
5166 hyste 4613 hysteresis = <2000>;
5167 type 4614 type = "hot";
5168 }; 4615 };
5169 cluster1_crit !! 4616 cluster1_crit: cluster1_crit {
5170 tempe 4617 temperature = <110000>;
5171 hyste 4618 hysteresis = <2000>;
5172 type 4619 type = "critical";
5173 }; 4620 };
5174 }; 4621 };
5175 }; 4622 };
5176 4623
5177 gpu-top-thermal { 4624 gpu-top-thermal {
5178 polling-delay-passive 4625 polling-delay-passive = <250>;
>> 4626 polling-delay = <1000>;
5179 4627
5180 thermal-sensors = <&t 4628 thermal-sensors = <&tsens0 15>;
5181 4629
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4630 trips {
5190 gpu_top_alert !! 4631 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4632 temperature = <90000>;
5198 hyste !! 4633 hysteresis = <2000>;
5199 type 4634 type = "hot";
5200 }; 4635 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4636 };
5208 }; 4637 };
5209 4638
5210 aoss1-thermal { 4639 aoss1-thermal {
5211 polling-delay-passive 4640 polling-delay-passive = <250>;
>> 4641 polling-delay = <1000>;
5212 4642
5213 thermal-sensors = <&t 4643 thermal-sensors = <&tsens1 0>;
5214 4644
5215 trips { 4645 trips {
5216 aoss1_alert0: 4646 aoss1_alert0: trip-point0 {
5217 tempe 4647 temperature = <90000>;
5218 hyste 4648 hysteresis = <2000>;
5219 type 4649 type = "hot";
5220 }; 4650 };
5221 }; 4651 };
5222 }; 4652 };
5223 4653
5224 wlan-thermal { 4654 wlan-thermal {
5225 polling-delay-passive 4655 polling-delay-passive = <250>;
>> 4656 polling-delay = <1000>;
5226 4657
5227 thermal-sensors = <&t 4658 thermal-sensors = <&tsens1 1>;
5228 4659
5229 trips { 4660 trips {
5230 wlan_alert0: 4661 wlan_alert0: trip-point0 {
5231 tempe 4662 temperature = <90000>;
5232 hyste 4663 hysteresis = <2000>;
5233 type 4664 type = "hot";
5234 }; 4665 };
5235 }; 4666 };
5236 }; 4667 };
5237 4668
5238 video-thermal { 4669 video-thermal {
5239 polling-delay-passive 4670 polling-delay-passive = <250>;
>> 4671 polling-delay = <1000>;
5240 4672
5241 thermal-sensors = <&t 4673 thermal-sensors = <&tsens1 2>;
5242 4674
5243 trips { 4675 trips {
5244 video_alert0: 4676 video_alert0: trip-point0 {
5245 tempe 4677 temperature = <90000>;
5246 hyste 4678 hysteresis = <2000>;
5247 type 4679 type = "hot";
5248 }; 4680 };
5249 }; 4681 };
5250 }; 4682 };
5251 4683
5252 mem-thermal { 4684 mem-thermal {
5253 polling-delay-passive 4685 polling-delay-passive = <250>;
>> 4686 polling-delay = <1000>;
5254 4687
5255 thermal-sensors = <&t 4688 thermal-sensors = <&tsens1 3>;
5256 4689
5257 trips { 4690 trips {
5258 mem_alert0: t 4691 mem_alert0: trip-point0 {
5259 tempe 4692 temperature = <90000>;
5260 hyste 4693 hysteresis = <2000>;
5261 type 4694 type = "hot";
5262 }; 4695 };
5263 }; 4696 };
5264 }; 4697 };
5265 4698
5266 q6-hvx-thermal { 4699 q6-hvx-thermal {
5267 polling-delay-passive 4700 polling-delay-passive = <250>;
>> 4701 polling-delay = <1000>;
5268 4702
5269 thermal-sensors = <&t 4703 thermal-sensors = <&tsens1 4>;
5270 4704
5271 trips { 4705 trips {
5272 q6_hvx_alert0 4706 q6_hvx_alert0: trip-point0 {
5273 tempe 4707 temperature = <90000>;
5274 hyste 4708 hysteresis = <2000>;
5275 type 4709 type = "hot";
5276 }; 4710 };
5277 }; 4711 };
5278 }; 4712 };
5279 4713
5280 camera-thermal { 4714 camera-thermal {
5281 polling-delay-passive 4715 polling-delay-passive = <250>;
>> 4716 polling-delay = <1000>;
5282 4717
5283 thermal-sensors = <&t 4718 thermal-sensors = <&tsens1 5>;
5284 4719
5285 trips { 4720 trips {
5286 camera_alert0 4721 camera_alert0: trip-point0 {
5287 tempe 4722 temperature = <90000>;
5288 hyste 4723 hysteresis = <2000>;
5289 type 4724 type = "hot";
5290 }; 4725 };
5291 }; 4726 };
5292 }; 4727 };
5293 4728
5294 compute-thermal { 4729 compute-thermal {
5295 polling-delay-passive 4730 polling-delay-passive = <250>;
>> 4731 polling-delay = <1000>;
5296 4732
5297 thermal-sensors = <&t 4733 thermal-sensors = <&tsens1 6>;
5298 4734
5299 trips { 4735 trips {
5300 compute_alert 4736 compute_alert0: trip-point0 {
5301 tempe 4737 temperature = <90000>;
5302 hyste 4738 hysteresis = <2000>;
5303 type 4739 type = "hot";
5304 }; 4740 };
5305 }; 4741 };
5306 }; 4742 };
5307 4743
5308 modem-thermal { 4744 modem-thermal {
5309 polling-delay-passive 4745 polling-delay-passive = <250>;
>> 4746 polling-delay = <1000>;
5310 4747
5311 thermal-sensors = <&t 4748 thermal-sensors = <&tsens1 7>;
5312 4749
5313 trips { 4750 trips {
5314 modem_alert0: 4751 modem_alert0: trip-point0 {
5315 tempe 4752 temperature = <90000>;
5316 hyste 4753 hysteresis = <2000>;
5317 type 4754 type = "hot";
5318 }; 4755 };
5319 }; 4756 };
5320 }; 4757 };
5321 4758
5322 npu-thermal { 4759 npu-thermal {
5323 polling-delay-passive 4760 polling-delay-passive = <250>;
>> 4761 polling-delay = <1000>;
5324 4762
5325 thermal-sensors = <&t 4763 thermal-sensors = <&tsens1 8>;
5326 4764
5327 trips { 4765 trips {
5328 npu_alert0: t 4766 npu_alert0: trip-point0 {
5329 tempe 4767 temperature = <90000>;
5330 hyste 4768 hysteresis = <2000>;
5331 type 4769 type = "hot";
5332 }; 4770 };
5333 }; 4771 };
5334 }; 4772 };
5335 4773
5336 modem-vec-thermal { 4774 modem-vec-thermal {
5337 polling-delay-passive 4775 polling-delay-passive = <250>;
>> 4776 polling-delay = <1000>;
5338 4777
5339 thermal-sensors = <&t 4778 thermal-sensors = <&tsens1 9>;
5340 4779
5341 trips { 4780 trips {
5342 modem_vec_ale 4781 modem_vec_alert0: trip-point0 {
5343 tempe 4782 temperature = <90000>;
5344 hyste 4783 hysteresis = <2000>;
5345 type 4784 type = "hot";
5346 }; 4785 };
5347 }; 4786 };
5348 }; 4787 };
5349 4788
5350 modem-scl-thermal { 4789 modem-scl-thermal {
5351 polling-delay-passive 4790 polling-delay-passive = <250>;
>> 4791 polling-delay = <1000>;
5352 4792
5353 thermal-sensors = <&t 4793 thermal-sensors = <&tsens1 10>;
5354 4794
5355 trips { 4795 trips {
5356 modem_scl_ale 4796 modem_scl_alert0: trip-point0 {
5357 tempe 4797 temperature = <90000>;
5358 hyste 4798 hysteresis = <2000>;
5359 type 4799 type = "hot";
5360 }; 4800 };
5361 }; 4801 };
5362 }; 4802 };
5363 4803
5364 gpu-bottom-thermal { 4804 gpu-bottom-thermal {
5365 polling-delay-passive 4805 polling-delay-passive = <250>;
>> 4806 polling-delay = <1000>;
5366 4807
5367 thermal-sensors = <&t 4808 thermal-sensors = <&tsens1 11>;
5368 4809
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 4810 trips {
5377 gpu_bottom_al !! 4811 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 4812 temperature = <90000>;
5385 hyste !! 4813 hysteresis = <2000>;
5386 type 4814 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 4815 };
5394 }; 4816 };
5395 }; 4817 };
5396 }; 4818 };
5397 }; 4819 };
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