1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 12 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 16 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 17 #include <dt-bindings/thermal/thermal.h>
22 18
23 / { 19 / {
24 interrupt-parent = <&intc>; 20 interrupt-parent = <&intc>;
25 21
26 #address-cells = <2>; 22 #address-cells = <2>;
27 #size-cells = <2>; 23 #size-cells = <2>;
28 24
29 chosen { }; 25 chosen { };
30 26
31 clocks { 27 clocks {
32 xo_board: xo-board { 28 xo_board: xo-board {
33 compatible = "fixed-cl 29 compatible = "fixed-clock";
34 #clock-cells = <0>; 30 #clock-cells = <0>;
35 clock-frequency = <384 31 clock-frequency = <38400000>;
36 clock-output-names = " 32 clock-output-names = "xo_board";
37 }; 33 };
38 34
39 sleep_clk: sleep-clk { 35 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 36 compatible = "fixed-clock";
41 #clock-cells = <0>; 37 #clock-cells = <0>;
42 clock-frequency = <327 38 clock-frequency = <32764>;
43 clock-output-names = " 39 clock-output-names = "sleep_clk";
44 }; 40 };
45 }; 41 };
46 42
47 cpus { 43 cpus {
48 #address-cells = <2>; 44 #address-cells = <2>;
49 #size-cells = <0>; 45 #size-cells = <0>;
50 46
51 CPU0: cpu@0 { 47 CPU0: cpu@0 {
52 device_type = "cpu"; 48 device_type = "cpu";
53 compatible = "qcom,kry 49 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 50 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw <<
56 enable-method = "psci" 51 enable-method = "psci";
57 capacity-dmips-mhz = < 52 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 53 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 54 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 55 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 56 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 57 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 59 power-domains = <&CPU_PD0>;
65 power-domain-names = " 60 power-domain-names = "psci";
66 #cooling-cells = <2>; 61 #cooling-cells = <2>;
67 L2_0: l2-cache { 62 L2_0: l2-cache {
68 compatible = " 63 compatible = "cache";
69 cache-level = 64 cache-level = <2>;
70 cache-unified; <<
71 next-level-cac 65 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 66 L3_0: l3-cache {
73 compat !! 67 compatible = "cache";
74 cache- !! 68 cache-level = <3>;
75 cache- <<
76 }; 69 };
77 }; 70 };
78 }; 71 };
79 72
80 CPU1: cpu@100 { 73 CPU1: cpu@100 {
81 device_type = "cpu"; 74 device_type = "cpu";
82 compatible = "qcom,kry 75 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 76 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw <<
85 enable-method = "psci" 77 enable-method = "psci";
86 capacity-dmips-mhz = < 78 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 79 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 80 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 81 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 82 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 83 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 84 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 85 power-domains = <&CPU_PD1>;
94 power-domain-names = " 86 power-domain-names = "psci";
95 #cooling-cells = <2>; 87 #cooling-cells = <2>;
96 L2_100: l2-cache { 88 L2_100: l2-cache {
97 compatible = " 89 compatible = "cache";
98 cache-level = 90 cache-level = <2>;
99 cache-unified; <<
100 next-level-cac 91 next-level-cache = <&L3_0>;
101 }; 92 };
>> 93
102 }; 94 };
103 95
104 CPU2: cpu@200 { 96 CPU2: cpu@200 {
105 device_type = "cpu"; 97 device_type = "cpu";
106 compatible = "qcom,kry 98 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 99 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw <<
109 enable-method = "psci" 100 enable-method = "psci";
110 capacity-dmips-mhz = < 101 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 102 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 103 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 104 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 105 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 106 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 107 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 108 power-domains = <&CPU_PD2>;
118 power-domain-names = " 109 power-domain-names = "psci";
119 #cooling-cells = <2>; 110 #cooling-cells = <2>;
120 L2_200: l2-cache { 111 L2_200: l2-cache {
121 compatible = " 112 compatible = "cache";
122 cache-level = 113 cache-level = <2>;
123 cache-unified; <<
124 next-level-cac 114 next-level-cache = <&L3_0>;
125 }; 115 };
126 }; 116 };
127 117
128 CPU3: cpu@300 { 118 CPU3: cpu@300 {
129 device_type = "cpu"; 119 device_type = "cpu";
130 compatible = "qcom,kry 120 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 121 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw <<
133 enable-method = "psci" 122 enable-method = "psci";
134 capacity-dmips-mhz = < 123 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 124 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 125 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 126 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 127 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 128 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 129 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 130 power-domains = <&CPU_PD3>;
142 power-domain-names = " 131 power-domain-names = "psci";
143 #cooling-cells = <2>; 132 #cooling-cells = <2>;
144 L2_300: l2-cache { 133 L2_300: l2-cache {
145 compatible = " 134 compatible = "cache";
146 cache-level = 135 cache-level = <2>;
147 cache-unified; <<
148 next-level-cac 136 next-level-cache = <&L3_0>;
149 }; 137 };
150 }; 138 };
151 139
152 CPU4: cpu@400 { 140 CPU4: cpu@400 {
153 device_type = "cpu"; 141 device_type = "cpu";
154 compatible = "qcom,kry 142 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 143 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 144 enable-method = "psci";
158 capacity-dmips-mhz = < 145 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 146 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 147 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 148 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 149 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 150 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 151 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 152 power-domains = <&CPU_PD4>;
166 power-domain-names = " 153 power-domain-names = "psci";
167 #cooling-cells = <2>; 154 #cooling-cells = <2>;
168 L2_400: l2-cache { 155 L2_400: l2-cache {
169 compatible = " 156 compatible = "cache";
170 cache-level = 157 cache-level = <2>;
171 cache-unified; <<
172 next-level-cac 158 next-level-cache = <&L3_0>;
173 }; 159 };
174 }; 160 };
175 161
176 CPU5: cpu@500 { 162 CPU5: cpu@500 {
177 device_type = "cpu"; 163 device_type = "cpu";
178 compatible = "qcom,kry 164 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 165 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw <<
181 enable-method = "psci" 166 enable-method = "psci";
182 capacity-dmips-mhz = < 167 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 168 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 169 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 170 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 171 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 172 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 173 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 174 power-domains = <&CPU_PD5>;
190 power-domain-names = " 175 power-domain-names = "psci";
191 #cooling-cells = <2>; 176 #cooling-cells = <2>;
192 L2_500: l2-cache { 177 L2_500: l2-cache {
193 compatible = " 178 compatible = "cache";
194 cache-level = 179 cache-level = <2>;
195 cache-unified; <<
196 next-level-cac 180 next-level-cache = <&L3_0>;
197 }; 181 };
198 }; 182 };
199 183
200 CPU6: cpu@600 { 184 CPU6: cpu@600 {
201 device_type = "cpu"; 185 device_type = "cpu";
202 compatible = "qcom,kry 186 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 187 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw <<
205 enable-method = "psci" 188 enable-method = "psci";
206 capacity-dmips-mhz = < 189 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 190 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 191 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 192 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 193 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 194 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 195 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 196 power-domains = <&CPU_PD6>;
214 power-domain-names = " 197 power-domain-names = "psci";
215 #cooling-cells = <2>; 198 #cooling-cells = <2>;
216 L2_600: l2-cache { 199 L2_600: l2-cache {
217 compatible = " 200 compatible = "cache";
218 cache-level = 201 cache-level = <2>;
219 cache-unified; <<
220 next-level-cac 202 next-level-cache = <&L3_0>;
221 }; 203 };
222 }; 204 };
223 205
224 CPU7: cpu@700 { 206 CPU7: cpu@700 {
225 device_type = "cpu"; 207 device_type = "cpu";
226 compatible = "qcom,kry 208 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 209 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw <<
229 enable-method = "psci" 210 enable-method = "psci";
230 capacity-dmips-mhz = < 211 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 212 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 213 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 214 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 215 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 216 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 217 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 218 power-domains = <&CPU_PD7>;
238 power-domain-names = " 219 power-domain-names = "psci";
239 #cooling-cells = <2>; 220 #cooling-cells = <2>;
240 L2_700: l2-cache { 221 L2_700: l2-cache {
241 compatible = " 222 compatible = "cache";
242 cache-level = 223 cache-level = <2>;
243 cache-unified; <<
244 next-level-cac 224 next-level-cache = <&L3_0>;
245 }; 225 };
246 }; 226 };
247 227
248 cpu-map { 228 cpu-map {
249 cluster0 { 229 cluster0 {
250 core0 { 230 core0 {
251 cpu = 231 cpu = <&CPU0>;
252 }; 232 };
253 233
254 core1 { 234 core1 {
255 cpu = 235 cpu = <&CPU1>;
256 }; 236 };
257 237
258 core2 { 238 core2 {
259 cpu = 239 cpu = <&CPU2>;
260 }; 240 };
261 241
262 core3 { 242 core3 {
263 cpu = 243 cpu = <&CPU3>;
264 }; 244 };
265 245
266 core4 { 246 core4 {
267 cpu = 247 cpu = <&CPU4>;
268 }; 248 };
269 249
270 core5 { 250 core5 {
271 cpu = 251 cpu = <&CPU5>;
272 }; 252 };
273 253
274 core6 { 254 core6 {
275 cpu = 255 cpu = <&CPU6>;
276 }; 256 };
277 257
278 core7 { 258 core7 {
279 cpu = 259 cpu = <&CPU7>;
280 }; 260 };
281 }; 261 };
282 }; 262 };
283 263
284 idle-states { 264 idle-states {
285 entry-method = "psci"; 265 entry-method = "psci";
286 266
287 LITTLE_CPU_SLEEP_0: cp 267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 268 compatible = "arm,idle-state";
289 idle-state-nam 269 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 270 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 271 entry-latency-us = <355>;
292 exit-latency-u 272 exit-latency-us = <909>;
293 min-residency- 273 min-residency-us = <3934>;
294 local-timer-st 274 local-timer-stop;
295 }; 275 };
296 276
297 BIG_CPU_SLEEP_0: cpu-s 277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 278 compatible = "arm,idle-state";
299 idle-state-nam 279 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 280 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 281 entry-latency-us = <241>;
302 exit-latency-u 282 exit-latency-us = <1461>;
303 min-residency- 283 min-residency-us = <4488>;
304 local-timer-st 284 local-timer-stop;
305 }; 285 };
306 }; 286 };
307 287
308 domain-idle-states { 288 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 289 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 290 compatible = "domain-idle-state";
>> 291 idle-state-name = "cluster-power-collapse";
311 arm,psci-suspe 292 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 293 entry-latency-us = <3263>;
313 exit-latency-u 294 exit-latency-us = <6562>;
314 min-residency- 295 min-residency-us = <9987>;
>> 296 local-timer-stop;
315 }; 297 };
316 }; 298 };
317 }; 299 };
318 300
319 cpu0_opp_table: opp-table-cpu0 { 301 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points 302 compatible = "operating-points-v2";
321 opp-shared; 303 opp-shared;
322 304
323 cpu0_opp1: opp-300000000 { 305 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 306 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 307 opp-peak-kBps = <800000 9600000>;
326 }; 308 };
327 309
328 cpu0_opp2: opp-403200000 { 310 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 311 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 312 opp-peak-kBps = <800000 9600000>;
331 }; 313 };
332 314
333 cpu0_opp3: opp-499200000 { 315 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 316 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 317 opp-peak-kBps = <800000 12902400>;
336 }; 318 };
337 319
338 cpu0_opp4: opp-576000000 { 320 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 321 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 322 opp-peak-kBps = <800000 12902400>;
341 }; 323 };
342 324
343 cpu0_opp5: opp-672000000 { 325 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 326 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 327 opp-peak-kBps = <800000 15974400>;
346 }; 328 };
347 329
348 cpu0_opp6: opp-768000000 { 330 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 331 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 332 opp-peak-kBps = <1804000 19660800>;
351 }; 333 };
352 334
353 cpu0_opp7: opp-844800000 { 335 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 336 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 337 opp-peak-kBps = <1804000 19660800>;
356 }; 338 };
357 339
358 cpu0_opp8: opp-940800000 { 340 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 341 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 342 opp-peak-kBps = <1804000 22732800>;
361 }; 343 };
362 344
363 cpu0_opp9: opp-1036800000 { 345 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 346 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 347 opp-peak-kBps = <1804000 22732800>;
366 }; 348 };
367 349
368 cpu0_opp10: opp-1113600000 { 350 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 351 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 352 opp-peak-kBps = <2188000 25804800>;
371 }; 353 };
372 354
373 cpu0_opp11: opp-1209600000 { 355 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 356 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 357 opp-peak-kBps = <2188000 31948800>;
376 }; 358 };
377 359
378 cpu0_opp12: opp-1305600000 { 360 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 361 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 362 opp-peak-kBps = <3072000 31948800>;
381 }; 363 };
382 364
383 cpu0_opp13: opp-1382400000 { 365 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 366 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 367 opp-peak-kBps = <3072000 31948800>;
386 }; 368 };
387 369
388 cpu0_opp14: opp-1478400000 { 370 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 371 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 372 opp-peak-kBps = <3072000 31948800>;
391 }; 373 };
392 374
393 cpu0_opp15: opp-1555200000 { 375 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 376 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 377 opp-peak-kBps = <3072000 40550400>;
396 }; 378 };
397 379
398 cpu0_opp16: opp-1632000000 { 380 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 381 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 382 opp-peak-kBps = <3072000 40550400>;
401 }; 383 };
402 384
403 cpu0_opp17: opp-1708800000 { 385 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 386 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 387 opp-peak-kBps = <3072000 43008000>;
406 }; 388 };
407 389
408 cpu0_opp18: opp-1785600000 { 390 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 391 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 392 opp-peak-kBps = <3072000 43008000>;
411 }; 393 };
412 }; 394 };
413 395
414 cpu4_opp_table: opp-table-cpu4 { 396 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points 397 compatible = "operating-points-v2";
416 opp-shared; 398 opp-shared;
417 399
418 cpu4_opp1: opp-710400000 { 400 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 401 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 402 opp-peak-kBps = <1804000 15974400>;
421 }; 403 };
422 404
423 cpu4_opp2: opp-825600000 { 405 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 406 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 407 opp-peak-kBps = <2188000 19660800>;
426 }; 408 };
427 409
428 cpu4_opp3: opp-940800000 { 410 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 411 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 412 opp-peak-kBps = <2188000 22732800>;
431 }; 413 };
432 414
433 cpu4_opp4: opp-1056000000 { 415 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 416 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 417 opp-peak-kBps = <3072000 25804800>;
436 }; 418 };
437 419
438 cpu4_opp5: opp-1171200000 { 420 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 421 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 422 opp-peak-kBps = <3072000 31948800>;
441 }; 423 };
442 424
443 cpu4_opp6: opp-1286400000 { 425 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 426 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 427 opp-peak-kBps = <4068000 31948800>;
446 }; 428 };
447 429
448 cpu4_opp7: opp-1401600000 { 430 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 431 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 432 opp-peak-kBps = <4068000 31948800>;
451 }; 433 };
452 434
453 cpu4_opp8: opp-1497600000 { 435 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 436 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 437 opp-peak-kBps = <4068000 40550400>;
456 }; 438 };
457 439
458 cpu4_opp9: opp-1612800000 { 440 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 441 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 442 opp-peak-kBps = <4068000 40550400>;
461 }; 443 };
462 444
463 cpu4_opp10: opp-1708800000 { 445 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 446 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 447 opp-peak-kBps = <4068000 43008000>;
466 }; 448 };
467 449
468 cpu4_opp11: opp-1804800000 { 450 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 451 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 452 opp-peak-kBps = <6220000 43008000>;
471 }; 453 };
472 454
473 cpu4_opp12: opp-1920000000 { 455 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 456 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 457 opp-peak-kBps = <6220000 49152000>;
476 }; 458 };
477 459
478 cpu4_opp13: opp-2016000000 { 460 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 461 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 462 opp-peak-kBps = <7216000 49152000>;
481 }; 463 };
482 464
483 cpu4_opp14: opp-2131200000 { 465 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 466 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 467 opp-peak-kBps = <8368000 49152000>;
486 }; 468 };
487 469
488 cpu4_opp15: opp-2227200000 { 470 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 471 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 472 opp-peak-kBps = <8368000 51609600>;
491 }; 473 };
492 474
493 cpu4_opp16: opp-2323200000 { 475 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 476 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 477 opp-peak-kBps = <8368000 51609600>;
496 }; 478 };
497 479
498 cpu4_opp17: opp-2419200000 { 480 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 481 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 482 opp-peak-kBps = <8368000 51609600>;
501 }; 483 };
502 }; 484 };
503 485
504 cpu7_opp_table: opp-table-cpu7 { 486 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points 487 compatible = "operating-points-v2";
506 opp-shared; 488 opp-shared;
507 489
508 cpu7_opp1: opp-825600000 { 490 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 491 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 492 opp-peak-kBps = <2188000 19660800>;
511 }; 493 };
512 494
513 cpu7_opp2: opp-940800000 { 495 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 496 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 497 opp-peak-kBps = <2188000 22732800>;
516 }; 498 };
517 499
518 cpu7_opp3: opp-1056000000 { 500 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 501 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 502 opp-peak-kBps = <3072000 25804800>;
521 }; 503 };
522 504
523 cpu7_opp4: opp-1171200000 { 505 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 506 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 507 opp-peak-kBps = <3072000 31948800>;
526 }; 508 };
527 509
528 cpu7_opp5: opp-1286400000 { 510 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 511 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 512 opp-peak-kBps = <4068000 31948800>;
531 }; 513 };
532 514
533 cpu7_opp6: opp-1401600000 { 515 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 516 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 517 opp-peak-kBps = <4068000 31948800>;
536 }; 518 };
537 519
538 cpu7_opp7: opp-1497600000 { 520 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 521 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 522 opp-peak-kBps = <4068000 40550400>;
541 }; 523 };
542 524
543 cpu7_opp8: opp-1612800000 { 525 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 526 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 527 opp-peak-kBps = <4068000 40550400>;
546 }; 528 };
547 529
548 cpu7_opp9: opp-1708800000 { 530 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 531 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 532 opp-peak-kBps = <4068000 43008000>;
551 }; 533 };
552 534
553 cpu7_opp10: opp-1804800000 { 535 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 536 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 537 opp-peak-kBps = <6220000 43008000>;
556 }; 538 };
557 539
558 cpu7_opp11: opp-1920000000 { 540 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 541 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 542 opp-peak-kBps = <6220000 49152000>;
561 }; 543 };
562 544
563 cpu7_opp12: opp-2016000000 { 545 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 546 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 547 opp-peak-kBps = <7216000 49152000>;
566 }; 548 };
567 549
568 cpu7_opp13: opp-2131200000 { 550 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 551 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 552 opp-peak-kBps = <8368000 49152000>;
571 }; 553 };
572 554
573 cpu7_opp14: opp-2227200000 { 555 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 556 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
576 }; 558 };
577 559
578 cpu7_opp15: opp-2323200000 { 560 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 561 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
581 }; 563 };
582 564
583 cpu7_opp16: opp-2419200000 { 565 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 566 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 567 opp-peak-kBps = <8368000 51609600>;
586 }; 568 };
587 569
588 cpu7_opp17: opp-2534400000 { 570 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 571 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 572 opp-peak-kBps = <8368000 51609600>;
591 }; 573 };
592 574
593 cpu7_opp18: opp-2649600000 { 575 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 576 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 577 opp-peak-kBps = <8368000 51609600>;
596 }; 578 };
597 579
598 cpu7_opp19: opp-2745600000 { 580 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 581 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 582 opp-peak-kBps = <8368000 51609600>;
601 }; 583 };
602 584
603 cpu7_opp20: opp-2841600000 { 585 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 586 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 587 opp-peak-kBps = <8368000 51609600>;
606 }; 588 };
607 }; 589 };
608 590
609 firmware { 591 firmware {
610 scm: scm { 592 scm: scm {
611 compatible = "qcom,scm 593 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 594 #reset-cells = <1>;
613 }; 595 };
614 }; 596 };
615 597
616 memory@80000000 { 598 memory@80000000 {
617 device_type = "memory"; 599 device_type = "memory";
618 /* We expect the bootloader to 600 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 601 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 602 };
621 603
622 pmu { 604 pmu {
623 compatible = "arm,armv8-pmuv3" 605 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 606 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 607 };
626 608
627 psci { 609 psci {
628 compatible = "arm,psci-1.0"; 610 compatible = "arm,psci-1.0";
629 method = "smc"; 611 method = "smc";
630 612
631 CPU_PD0: power-domain-cpu0 { 613 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells = 614 #power-domain-cells = <0>;
633 power-domains = <&CLUS 615 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 616 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 617 };
636 618
637 CPU_PD1: power-domain-cpu1 { 619 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells = 620 #power-domain-cells = <0>;
639 power-domains = <&CLUS 621 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 622 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 623 };
642 624
643 CPU_PD2: power-domain-cpu2 { 625 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells = 626 #power-domain-cells = <0>;
645 power-domains = <&CLUS 627 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 628 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 629 };
648 630
649 CPU_PD3: power-domain-cpu3 { 631 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells = 632 #power-domain-cells = <0>;
651 power-domains = <&CLUS 633 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 634 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 635 };
654 636
655 CPU_PD4: power-domain-cpu4 { 637 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells = 638 #power-domain-cells = <0>;
657 power-domains = <&CLUS 639 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 640 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 641 };
660 642
661 CPU_PD5: power-domain-cpu5 { 643 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells = 644 #power-domain-cells = <0>;
663 power-domains = <&CLUS 645 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 646 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 647 };
666 648
667 CPU_PD6: power-domain-cpu6 { 649 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells = 650 #power-domain-cells = <0>;
669 power-domains = <&CLUS 651 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 652 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 653 };
672 654
673 CPU_PD7: power-domain-cpu7 { 655 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells = 656 #power-domain-cells = <0>;
675 power-domains = <&CLUS 657 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 658 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 659 };
678 660
679 CLUSTER_PD: power-domain-cpu-c 661 CLUSTER_PD: power-domain-cpu-cluster0 {
680 #power-domain-cells = 662 #power-domain-cells = <0>;
681 domain-idle-states = < 663 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 664 };
683 }; 665 };
684 666
685 reserved-memory { 667 reserved-memory {
686 #address-cells = <2>; 668 #address-cells = <2>;
687 #size-cells = <2>; 669 #size-cells = <2>;
688 ranges; 670 ranges;
689 671
690 hyp_mem: memory@85700000 { 672 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 673 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 674 no-map;
693 }; 675 };
694 676
695 xbl_mem: memory@85d00000 { 677 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 678 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 679 no-map;
698 }; 680 };
699 681
700 aop_mem: memory@85f00000 { 682 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 683 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 684 no-map;
703 }; 685 };
704 686
705 aop_cmd_db: memory@85f20000 { 687 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 688 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 689 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 690 no-map;
709 }; 691 };
710 692
711 smem_mem: memory@86000000 { 693 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 694 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 695 no-map;
714 }; 696 };
715 697
716 tz_mem: memory@86200000 { 698 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 699 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 700 no-map;
719 }; 701 };
720 702
721 rmtfs_mem: memory@89b00000 { 703 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 704 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 705 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 706 no-map;
725 707
726 qcom,client-id = <1>; 708 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 709 qcom,vmid = <15>;
728 }; 710 };
729 711
730 camera_mem: memory@8b700000 { 712 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 713 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 714 no-map;
733 }; 715 };
734 716
735 wlan_mem: memory@8bc00000 { 717 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 718 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 719 no-map;
738 }; 720 };
739 721
740 npu_mem: memory@8bd80000 { 722 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 723 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 724 no-map;
743 }; 725 };
744 726
745 adsp_mem: memory@8be00000 { 727 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 728 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 729 no-map;
748 }; 730 };
749 731
750 mpss_mem: memory@8d800000 { 732 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 733 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 734 no-map;
753 }; 735 };
754 736
755 venus_mem: memory@96e00000 { 737 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 738 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 739 no-map;
758 }; 740 };
759 741
760 slpi_mem: memory@97300000 { 742 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 743 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 744 no-map;
763 }; 745 };
764 746
765 ipa_fw_mem: memory@98700000 { 747 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 748 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 749 no-map;
768 }; 750 };
769 751
770 ipa_gsi_mem: memory@98710000 { 752 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 753 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 754 no-map;
773 }; 755 };
774 756
775 gpu_mem: memory@98715000 { 757 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 758 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 759 no-map;
778 }; 760 };
779 761
780 spss_mem: memory@98800000 { 762 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 763 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 764 no-map;
783 }; 765 };
784 766
785 cdsp_mem: memory@98900000 { 767 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 768 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 769 no-map;
788 }; 770 };
789 771
790 qseecom_mem: memory@9e400000 { 772 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 773 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 774 no-map;
793 }; 775 };
794 }; 776 };
795 777
796 smem { 778 smem {
797 compatible = "qcom,smem"; 779 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 780 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 781 hwlocks = <&tcsr_mutex 3>;
800 }; 782 };
801 783
802 smp2p-cdsp { 784 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 785 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 786 qcom,smem = <94>, <432>;
805 787
806 interrupts = <GIC_SPI 576 IRQ_ 788 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 789
808 mboxes = <&apss_shared 6>; 790 mboxes = <&apss_shared 6>;
809 791
810 qcom,local-pid = <0>; 792 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 793 qcom,remote-pid = <5>;
812 794
813 cdsp_smp2p_out: master-kernel 795 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 796 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 797 #qcom,smem-state-cells = <1>;
816 }; 798 };
817 799
818 cdsp_smp2p_in: slave-kernel { 800 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 801 qcom,entry-name = "slave-kernel";
820 802
821 interrupt-controller; 803 interrupt-controller;
822 #interrupt-cells = <2> 804 #interrupt-cells = <2>;
823 }; 805 };
824 }; 806 };
825 807
826 smp2p-lpass { 808 smp2p-lpass {
827 compatible = "qcom,smp2p"; 809 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 810 qcom,smem = <443>, <429>;
829 811
830 interrupts = <GIC_SPI 158 IRQ_ 812 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 813
832 mboxes = <&apss_shared 10>; 814 mboxes = <&apss_shared 10>;
833 815
834 qcom,local-pid = <0>; 816 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 817 qcom,remote-pid = <2>;
836 818
837 adsp_smp2p_out: master-kernel 819 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 820 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 821 #qcom,smem-state-cells = <1>;
840 }; 822 };
841 823
842 adsp_smp2p_in: slave-kernel { 824 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 825 qcom,entry-name = "slave-kernel";
844 826
845 interrupt-controller; 827 interrupt-controller;
846 #interrupt-cells = <2> 828 #interrupt-cells = <2>;
847 }; 829 };
848 }; 830 };
849 831
850 smp2p-mpss { 832 smp2p-mpss {
851 compatible = "qcom,smp2p"; 833 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 834 qcom,smem = <435>, <428>;
853 835
854 interrupts = <GIC_SPI 451 IRQ_ 836 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 837
856 mboxes = <&apss_shared 14>; 838 mboxes = <&apss_shared 14>;
857 839
858 qcom,local-pid = <0>; 840 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 841 qcom,remote-pid = <1>;
860 842
861 modem_smp2p_out: master-kernel 843 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 844 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 845 #qcom,smem-state-cells = <1>;
864 }; 846 };
865 847
866 modem_smp2p_in: slave-kernel { 848 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 849 qcom,entry-name = "slave-kernel";
868 850
869 interrupt-controller; 851 interrupt-controller;
870 #interrupt-cells = <2> 852 #interrupt-cells = <2>;
871 }; 853 };
872 }; 854 };
873 855
874 smp2p-slpi { 856 smp2p-slpi {
875 compatible = "qcom,smp2p"; 857 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 858 qcom,smem = <481>, <430>;
877 859
878 interrupts = <GIC_SPI 172 IRQ_ 860 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 861
880 mboxes = <&apss_shared 26>; 862 mboxes = <&apss_shared 26>;
881 863
882 qcom,local-pid = <0>; 864 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 865 qcom,remote-pid = <3>;
884 866
885 slpi_smp2p_out: master-kernel 867 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 868 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 869 #qcom,smem-state-cells = <1>;
888 }; 870 };
889 871
890 slpi_smp2p_in: slave-kernel { 872 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 873 qcom,entry-name = "slave-kernel";
892 874
893 interrupt-controller; 875 interrupt-controller;
894 #interrupt-cells = <2> 876 #interrupt-cells = <2>;
895 }; 877 };
896 }; 878 };
897 879
898 soc: soc@0 { 880 soc: soc@0 {
899 #address-cells = <2>; 881 #address-cells = <2>;
900 #size-cells = <2>; 882 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 883 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 884 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 885 compatible = "simple-bus";
904 886
905 gcc: clock-controller@100000 { 887 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 888 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 889 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 890 #clock-cells = <1>;
909 #reset-cells = <1>; 891 #reset-cells = <1>;
910 #power-domain-cells = 892 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 893 clock-names = "bi_tcxo",
912 "sleep_c 894 "sleep_clk";
913 clocks = <&rpmhcc RPMH 895 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 896 <&sleep_clk>;
915 }; 897 };
916 898
917 gpi_dma0: dma-controller@80000 899 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 900 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 901 reg = <0 0x00800000 0 0x60000>;
920 interrupts = <GIC_SPI 902 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 903 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 904 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 905 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 906 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 907 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 908 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 909 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 910 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 911 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 912 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 913 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 914 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 915 dma-channels = <13>;
934 dma-channel-mask = <0x 916 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 917 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 918 #dma-cells = <3>;
937 status = "disabled"; 919 status = "disabled";
938 }; 920 };
939 921
940 ethernet: ethernet@20000 { 922 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 923 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 924 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 925 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 926 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 927 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 928 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 929 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 930 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 931 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 932 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 933 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 934 interrupt-names = "macirq", "eth_lpi";
953 935
954 power-domains = <&gcc 936 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 937 resets = <&gcc GCC_EMAC_BCR>;
956 938
957 iommus = <&apps_smmu 0 939 iommus = <&apps_smmu 0x3c0 0x0>;
958 940
959 snps,tso; 941 snps,tso;
960 rx-fifo-depth = <4096> 942 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 943 tx-fifo-depth = <4096>;
962 944
963 status = "disabled"; 945 status = "disabled";
964 }; 946 };
965 947
966 qfprom: efuse@784000 { <<
967 compatible = "qcom,sm8 <<
968 reg = <0 0x00784000 0 <<
969 #address-cells = <1>; <<
970 #size-cells = <1>; <<
971 <<
972 gpu_speed_bin: gpu-spe <<
973 reg = <0x133 0 <<
974 bits = <5 3>; <<
975 }; <<
976 }; <<
977 948
978 qupv3_id_0: geniqup@8c0000 { 949 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 950 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 951 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 952 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 953 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 954 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 955 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 956 #address-cells = <2>;
986 #size-cells = <2>; 957 #size-cells = <2>;
987 ranges; 958 ranges;
988 status = "disabled"; 959 status = "disabled";
989 960
990 i2c0: i2c@880000 { 961 i2c0: i2c@880000 {
991 compatible = " 962 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 963 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 964 clock-names = "se";
994 clocks = <&gcc 965 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 966 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 967 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 968 dma-names = "tx", "rx";
998 pinctrl-names 969 pinctrl-names = "default";
999 pinctrl-0 = <& 970 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 971 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 972 #address-cells = <1>;
1002 #size-cells = 973 #size-cells = <0>;
1003 status = "dis 974 status = "disabled";
1004 }; 975 };
1005 976
1006 spi0: spi@880000 { 977 spi0: spi@880000 {
1007 compatible = 978 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 979 reg = <0 0x00880000 0 0x4000>;
1009 reg-names = " 980 reg-names = "se";
1010 clock-names = 981 clock-names = "se";
1011 clocks = <&gc 982 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 983 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 984 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 985 dma-names = "tx", "rx";
1015 pinctrl-names 986 pinctrl-names = "default";
1016 pinctrl-0 = < 987 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 988 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 989 spi-max-frequency = <50000000>;
1019 #address-cell 990 #address-cells = <1>;
1020 #size-cells = 991 #size-cells = <0>;
1021 status = "dis 992 status = "disabled";
1022 }; 993 };
1023 994
1024 i2c1: i2c@884000 { 995 i2c1: i2c@884000 {
1025 compatible = 996 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 997 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 998 clock-names = "se";
1028 clocks = <&gc 999 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 1000 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 1001 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 1002 dma-names = "tx", "rx";
1032 pinctrl-names 1003 pinctrl-names = "default";
1033 pinctrl-0 = < 1004 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 1005 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 1006 #address-cells = <1>;
1036 #size-cells = 1007 #size-cells = <0>;
1037 status = "dis 1008 status = "disabled";
1038 }; 1009 };
1039 1010
1040 spi1: spi@884000 { 1011 spi1: spi@884000 {
1041 compatible = 1012 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1013 reg = <0 0x00884000 0 0x4000>;
1043 reg-names = " 1014 reg-names = "se";
1044 clock-names = 1015 clock-names = "se";
1045 clocks = <&gc 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1017 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1018 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1019 dma-names = "tx", "rx";
1049 pinctrl-names 1020 pinctrl-names = "default";
1050 pinctrl-0 = < 1021 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1022 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1023 spi-max-frequency = <50000000>;
1053 #address-cell 1024 #address-cells = <1>;
1054 #size-cells = 1025 #size-cells = <0>;
1055 status = "dis 1026 status = "disabled";
1056 }; 1027 };
1057 1028
1058 i2c2: i2c@888000 { 1029 i2c2: i2c@888000 {
1059 compatible = 1030 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1031 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1032 clock-names = "se";
1062 clocks = <&gc 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1034 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1035 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1036 dma-names = "tx", "rx";
1066 pinctrl-names 1037 pinctrl-names = "default";
1067 pinctrl-0 = < 1038 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1039 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1040 #address-cells = <1>;
1070 #size-cells = 1041 #size-cells = <0>;
1071 status = "dis 1042 status = "disabled";
1072 }; 1043 };
1073 1044
1074 spi2: spi@888000 { 1045 spi2: spi@888000 {
1075 compatible = 1046 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 1047 reg = <0 0x00888000 0 0x4000>;
1077 reg-names = " 1048 reg-names = "se";
1078 clock-names = 1049 clock-names = "se";
1079 clocks = <&gc 1050 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1051 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1052 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1053 dma-names = "tx", "rx";
1083 pinctrl-names 1054 pinctrl-names = "default";
1084 pinctrl-0 = < 1055 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1056 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1057 spi-max-frequency = <50000000>;
1087 #address-cell 1058 #address-cells = <1>;
1088 #size-cells = 1059 #size-cells = <0>;
1089 status = "dis 1060 status = "disabled";
1090 }; 1061 };
1091 1062
1092 i2c3: i2c@88c000 { 1063 i2c3: i2c@88c000 {
1093 compatible = 1064 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1065 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1066 clock-names = "se";
1096 clocks = <&gc 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1068 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1069 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1070 dma-names = "tx", "rx";
1100 pinctrl-names 1071 pinctrl-names = "default";
1101 pinctrl-0 = < 1072 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1074 #address-cells = <1>;
1104 #size-cells = 1075 #size-cells = <0>;
1105 status = "dis 1076 status = "disabled";
1106 }; 1077 };
1107 1078
1108 spi3: spi@88c000 { 1079 spi3: spi@88c000 {
1109 compatible = 1080 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 1081 reg = <0 0x0088c000 0 0x4000>;
1111 reg-names = " 1082 reg-names = "se";
1112 clock-names = 1083 clock-names = "se";
1113 clocks = <&gc 1084 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1085 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1086 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1087 dma-names = "tx", "rx";
1117 pinctrl-names 1088 pinctrl-names = "default";
1118 pinctrl-0 = < 1089 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1090 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1091 spi-max-frequency = <50000000>;
1121 #address-cell 1092 #address-cells = <1>;
1122 #size-cells = 1093 #size-cells = <0>;
1123 status = "dis 1094 status = "disabled";
1124 }; 1095 };
1125 1096
1126 i2c4: i2c@890000 { 1097 i2c4: i2c@890000 {
1127 compatible = 1098 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1099 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1100 clock-names = "se";
1130 clocks = <&gc 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1102 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1103 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1104 dma-names = "tx", "rx";
1134 pinctrl-names 1105 pinctrl-names = "default";
1135 pinctrl-0 = < 1106 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1107 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1108 #address-cells = <1>;
1138 #size-cells = 1109 #size-cells = <0>;
1139 status = "dis 1110 status = "disabled";
1140 }; 1111 };
1141 1112
1142 spi4: spi@890000 { 1113 spi4: spi@890000 {
1143 compatible = 1114 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 1115 reg = <0 0x00890000 0 0x4000>;
1145 reg-names = " 1116 reg-names = "se";
1146 clock-names = 1117 clock-names = "se";
1147 clocks = <&gc 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1121 dma-names = "tx", "rx";
1151 pinctrl-names 1122 pinctrl-names = "default";
1152 pinctrl-0 = < 1123 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1124 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1125 spi-max-frequency = <50000000>;
1155 #address-cell 1126 #address-cells = <1>;
1156 #size-cells = 1127 #size-cells = <0>;
1157 status = "dis 1128 status = "disabled";
1158 }; 1129 };
1159 1130
1160 i2c5: i2c@894000 { 1131 i2c5: i2c@894000 {
1161 compatible = 1132 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1133 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1134 clock-names = "se";
1164 clocks = <&gc 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1136 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1137 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1138 dma-names = "tx", "rx";
1168 pinctrl-names 1139 pinctrl-names = "default";
1169 pinctrl-0 = < 1140 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1141 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1142 #address-cells = <1>;
1172 #size-cells = 1143 #size-cells = <0>;
1173 status = "dis 1144 status = "disabled";
1174 }; 1145 };
1175 1146
1176 spi5: spi@894000 { 1147 spi5: spi@894000 {
1177 compatible = 1148 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 1149 reg = <0 0x00894000 0 0x4000>;
1179 reg-names = " 1150 reg-names = "se";
1180 clock-names = 1151 clock-names = "se";
1181 clocks = <&gc 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1153 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1154 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1155 dma-names = "tx", "rx";
1185 pinctrl-names 1156 pinctrl-names = "default";
1186 pinctrl-0 = < 1157 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1158 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1159 spi-max-frequency = <50000000>;
1189 #address-cell 1160 #address-cells = <1>;
1190 #size-cells = 1161 #size-cells = <0>;
1191 status = "dis 1162 status = "disabled";
1192 }; 1163 };
1193 1164
1194 i2c6: i2c@898000 { 1165 i2c6: i2c@898000 {
1195 compatible = 1166 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1167 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1168 clock-names = "se";
1198 clocks = <&gc 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1170 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1171 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1172 dma-names = "tx", "rx";
1202 pinctrl-names 1173 pinctrl-names = "default";
1203 pinctrl-0 = < 1174 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1175 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1176 #address-cells = <1>;
1206 #size-cells = 1177 #size-cells = <0>;
1207 status = "dis 1178 status = "disabled";
1208 }; 1179 };
1209 1180
1210 spi6: spi@898000 { 1181 spi6: spi@898000 {
1211 compatible = 1182 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1183 reg = <0 0x00898000 0 0x4000>;
1213 reg-names = " 1184 reg-names = "se";
1214 clock-names = 1185 clock-names = "se";
1215 clocks = <&gc 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1187 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1188 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1189 dma-names = "tx", "rx";
1219 pinctrl-names 1190 pinctrl-names = "default";
1220 pinctrl-0 = < 1191 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1192 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1193 spi-max-frequency = <50000000>;
1223 #address-cell 1194 #address-cells = <1>;
1224 #size-cells = 1195 #size-cells = <0>;
1225 status = "dis 1196 status = "disabled";
1226 }; 1197 };
1227 1198
1228 i2c7: i2c@89c000 { 1199 i2c7: i2c@89c000 {
1229 compatible = 1200 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1201 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1202 clock-names = "se";
1232 clocks = <&gc 1203 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1204 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1205 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1206 dma-names = "tx", "rx";
1236 pinctrl-names 1207 pinctrl-names = "default";
1237 pinctrl-0 = < 1208 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = !! 1209 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1210 #address-cells = <1>;
1240 #size-cells = 1211 #size-cells = <0>;
1241 status = "dis 1212 status = "disabled";
1242 }; 1213 };
1243 1214
1244 spi7: spi@89c000 { 1215 spi7: spi@89c000 {
1245 compatible = 1216 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 1217 reg = <0 0x0089c000 0 0x4000>;
1247 reg-names = " 1218 reg-names = "se";
1248 clock-names = 1219 clock-names = "se";
1249 clocks = <&gc 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1221 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1222 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1223 dma-names = "tx", "rx";
1253 pinctrl-names 1224 pinctrl-names = "default";
1254 pinctrl-0 = < 1225 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1226 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1227 spi-max-frequency = <50000000>;
1257 #address-cell 1228 #address-cells = <1>;
1258 #size-cells = 1229 #size-cells = <0>;
1259 status = "dis 1230 status = "disabled";
1260 }; 1231 };
1261 }; 1232 };
1262 1233
1263 gpi_dma1: dma-controller@a000 1234 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm 1235 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 1236 reg = <0 0x00a00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1237 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1238 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1239 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1240 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1241 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1242 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1243 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1244 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1245 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1246 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1247 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1248 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1249 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1250 dma-channels = <13>;
1280 dma-channel-mask = <0 1251 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1252 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1253 #dma-cells = <3>;
1283 status = "disabled"; 1254 status = "disabled";
1284 }; 1255 };
1285 1256
1286 qupv3_id_1: geniqup@ac0000 { 1257 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1258 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1259 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1260 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1261 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1262 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1263 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1264 #address-cells = <2>;
1294 #size-cells = <2>; 1265 #size-cells = <2>;
1295 ranges; 1266 ranges;
1296 status = "disabled"; 1267 status = "disabled";
1297 1268
1298 i2c8: i2c@a80000 { 1269 i2c8: i2c@a80000 {
1299 compatible = 1270 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1271 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1272 clock-names = "se";
1302 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1274 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1275 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1276 dma-names = "tx", "rx";
1306 pinctrl-names 1277 pinctrl-names = "default";
1307 pinctrl-0 = < 1278 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1279 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1280 #address-cells = <1>;
1310 #size-cells = 1281 #size-cells = <0>;
1311 status = "dis 1282 status = "disabled";
1312 }; 1283 };
1313 1284
1314 spi8: spi@a80000 { 1285 spi8: spi@a80000 {
1315 compatible = 1286 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 1287 reg = <0 0x00a80000 0 0x4000>;
1317 reg-names = " 1288 reg-names = "se";
1318 clock-names = 1289 clock-names = "se";
1319 clocks = <&gc 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1291 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1292 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1293 dma-names = "tx", "rx";
1323 pinctrl-names 1294 pinctrl-names = "default";
1324 pinctrl-0 = < 1295 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1296 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1297 spi-max-frequency = <50000000>;
1327 #address-cell 1298 #address-cells = <1>;
1328 #size-cells = 1299 #size-cells = <0>;
1329 status = "dis 1300 status = "disabled";
1330 }; 1301 };
1331 1302
1332 i2c9: i2c@a84000 { 1303 i2c9: i2c@a84000 {
1333 compatible = 1304 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1305 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1306 clock-names = "se";
1336 clocks = <&gc 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1308 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1309 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1310 dma-names = "tx", "rx";
1340 pinctrl-names 1311 pinctrl-names = "default";
1341 pinctrl-0 = < 1312 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1313 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1314 #address-cells = <1>;
1344 #size-cells = 1315 #size-cells = <0>;
1345 status = "dis 1316 status = "disabled";
1346 }; 1317 };
1347 1318
1348 spi9: spi@a84000 { 1319 spi9: spi@a84000 {
1349 compatible = 1320 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 1321 reg = <0 0x00a84000 0 0x4000>;
1351 reg-names = " 1322 reg-names = "se";
1352 clock-names = 1323 clock-names = "se";
1353 clocks = <&gc 1324 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1325 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1326 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1327 dma-names = "tx", "rx";
1357 pinctrl-names 1328 pinctrl-names = "default";
1358 pinctrl-0 = < 1329 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1330 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1331 spi-max-frequency = <50000000>;
1361 #address-cell 1332 #address-cells = <1>;
1362 #size-cells = 1333 #size-cells = <0>;
1363 status = "dis 1334 status = "disabled";
1364 }; 1335 };
1365 1336
1366 uart9: serial@a84000 <<
1367 compatible = <<
1368 reg = <0x0 0x <<
1369 clocks = <&gc <<
1370 clock-names = <<
1371 pinctrl-0 = < <<
1372 pinctrl-names <<
1373 interrupts = <<
1374 status = "dis <<
1375 }; <<
1376 <<
1377 i2c10: i2c@a88000 { 1337 i2c10: i2c@a88000 {
1378 compatible = 1338 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1339 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1340 clock-names = "se";
1381 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1342 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1343 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1344 dma-names = "tx", "rx";
1385 pinctrl-names 1345 pinctrl-names = "default";
1386 pinctrl-0 = < 1346 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1347 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1348 #address-cells = <1>;
1389 #size-cells = 1349 #size-cells = <0>;
1390 status = "dis 1350 status = "disabled";
1391 }; 1351 };
1392 1352
1393 spi10: spi@a88000 { 1353 spi10: spi@a88000 {
1394 compatible = 1354 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 1355 reg = <0 0x00a88000 0 0x4000>;
1396 reg-names = " 1356 reg-names = "se";
1397 clock-names = 1357 clock-names = "se";
1398 clocks = <&gc 1358 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1361 dma-names = "tx", "rx";
1402 pinctrl-names 1362 pinctrl-names = "default";
1403 pinctrl-0 = < 1363 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1364 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1365 spi-max-frequency = <50000000>;
1406 #address-cell 1366 #address-cells = <1>;
1407 #size-cells = 1367 #size-cells = <0>;
1408 status = "dis 1368 status = "disabled";
1409 }; 1369 };
1410 1370
1411 i2c11: i2c@a8c000 { 1371 i2c11: i2c@a8c000 {
1412 compatible = 1372 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1373 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1374 clock-names = "se";
1415 clocks = <&gc 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1376 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1377 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1378 dma-names = "tx", "rx";
1419 pinctrl-names 1379 pinctrl-names = "default";
1420 pinctrl-0 = < 1380 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1381 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1382 #address-cells = <1>;
1423 #size-cells = 1383 #size-cells = <0>;
1424 status = "dis 1384 status = "disabled";
1425 }; 1385 };
1426 1386
1427 spi11: spi@a8c000 { 1387 spi11: spi@a8c000 {
1428 compatible = 1388 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 1389 reg = <0 0x00a8c000 0 0x4000>;
1430 reg-names = " 1390 reg-names = "se";
1431 clock-names = 1391 clock-names = "se";
1432 clocks = <&gc 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1393 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1394 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1395 dma-names = "tx", "rx";
1436 pinctrl-names 1396 pinctrl-names = "default";
1437 pinctrl-0 = < 1397 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1398 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1399 spi-max-frequency = <50000000>;
1440 #address-cell 1400 #address-cells = <1>;
1441 #size-cells = 1401 #size-cells = <0>;
1442 status = "dis 1402 status = "disabled";
1443 }; 1403 };
1444 1404
1445 uart2: serial@a90000 1405 uart2: serial@a90000 {
1446 compatible = 1406 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1407 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1408 clock-names = "se";
1449 clocks = <&gc 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1410 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1411 status = "disabled";
1452 }; 1412 };
1453 1413
1454 i2c12: i2c@a90000 { 1414 i2c12: i2c@a90000 {
1455 compatible = 1415 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1416 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1417 clock-names = "se";
1458 clocks = <&gc 1418 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1419 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1420 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1421 dma-names = "tx", "rx";
1462 pinctrl-names 1422 pinctrl-names = "default";
1463 pinctrl-0 = < 1423 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1424 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1425 #address-cells = <1>;
1466 #size-cells = 1426 #size-cells = <0>;
1467 status = "dis 1427 status = "disabled";
1468 }; 1428 };
1469 1429
1470 spi12: spi@a90000 { 1430 spi12: spi@a90000 {
1471 compatible = 1431 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 1432 reg = <0 0x00a90000 0 0x4000>;
1473 reg-names = " 1433 reg-names = "se";
1474 clock-names = 1434 clock-names = "se";
1475 clocks = <&gc 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1436 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1437 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1438 dma-names = "tx", "rx";
1479 pinctrl-names 1439 pinctrl-names = "default";
1480 pinctrl-0 = < 1440 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1441 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1442 spi-max-frequency = <50000000>;
1483 #address-cell 1443 #address-cells = <1>;
1484 #size-cells = 1444 #size-cells = <0>;
1485 status = "dis 1445 status = "disabled";
1486 }; 1446 };
1487 1447
1488 i2c16: i2c@94000 { 1448 i2c16: i2c@94000 {
1489 compatible = 1449 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 1450 reg = <0 0x00094000 0 0x4000>;
1491 clock-names = 1451 clock-names = "se";
1492 clocks = <&gc 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1453 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1454 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1455 dma-names = "tx", "rx";
1496 pinctrl-names 1456 pinctrl-names = "default";
1497 pinctrl-0 = < 1457 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1458 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1459 #address-cells = <1>;
1500 #size-cells = 1460 #size-cells = <0>;
1501 status = "dis 1461 status = "disabled";
1502 }; 1462 };
1503 1463
1504 spi16: spi@a94000 { 1464 spi16: spi@a94000 {
1505 compatible = 1465 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 1466 reg = <0 0x00a94000 0 0x4000>;
1507 reg-names = " 1467 reg-names = "se";
1508 clock-names = 1468 clock-names = "se";
1509 clocks = <&gc 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1470 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1471 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1472 dma-names = "tx", "rx";
1513 pinctrl-names 1473 pinctrl-names = "default";
1514 pinctrl-0 = < 1474 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1475 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1476 spi-max-frequency = <50000000>;
1517 #address-cell 1477 #address-cells = <1>;
1518 #size-cells = 1478 #size-cells = <0>;
1519 status = "dis 1479 status = "disabled";
1520 }; 1480 };
1521 }; 1481 };
1522 1482
1523 gpi_dma2: dma-controller@c000 1483 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm 1484 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 1485 reg = <0 0x00c00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1486 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1487 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1488 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1489 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1490 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1491 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1492 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1493 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1494 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1495 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1496 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1497 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1498 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1499 dma-channels = <13>;
1540 dma-channel-mask = <0 1500 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1501 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1502 #dma-cells = <3>;
1543 status = "disabled"; 1503 status = "disabled";
1544 }; 1504 };
1545 1505
1546 qupv3_id_2: geniqup@cc0000 { 1506 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1507 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1508 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1509
1550 clock-names = "m-ahb" 1510 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1511 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1512 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1513 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1514 #address-cells = <2>;
1555 #size-cells = <2>; 1515 #size-cells = <2>;
1556 ranges; 1516 ranges;
1557 status = "disabled"; 1517 status = "disabled";
1558 1518
1559 i2c17: i2c@c80000 { 1519 i2c17: i2c@c80000 {
1560 compatible = 1520 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1521 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1522 clock-names = "se";
1563 clocks = <&gc 1523 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1524 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1525 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1526 dma-names = "tx", "rx";
1567 pinctrl-names 1527 pinctrl-names = "default";
1568 pinctrl-0 = < 1528 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1529 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1530 #address-cells = <1>;
1571 #size-cells = 1531 #size-cells = <0>;
1572 status = "dis 1532 status = "disabled";
1573 }; 1533 };
1574 1534
1575 spi17: spi@c80000 { 1535 spi17: spi@c80000 {
1576 compatible = 1536 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1537 reg = <0 0x00c80000 0 0x4000>;
1578 reg-names = " 1538 reg-names = "se";
1579 clock-names = 1539 clock-names = "se";
1580 clocks = <&gc 1540 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1541 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1542 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1543 dma-names = "tx", "rx";
1584 pinctrl-names 1544 pinctrl-names = "default";
1585 pinctrl-0 = < 1545 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1546 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1547 spi-max-frequency = <50000000>;
1588 #address-cell 1548 #address-cells = <1>;
1589 #size-cells = 1549 #size-cells = <0>;
1590 status = "dis 1550 status = "disabled";
1591 }; 1551 };
1592 1552
1593 i2c18: i2c@c84000 { 1553 i2c18: i2c@c84000 {
1594 compatible = 1554 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1555 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1556 clock-names = "se";
1597 clocks = <&gc 1557 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1558 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1559 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1560 dma-names = "tx", "rx";
1601 pinctrl-names 1561 pinctrl-names = "default";
1602 pinctrl-0 = < 1562 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1563 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1564 #address-cells = <1>;
1605 #size-cells = 1565 #size-cells = <0>;
1606 status = "dis 1566 status = "disabled";
1607 }; 1567 };
1608 1568
1609 spi18: spi@c84000 { 1569 spi18: spi@c84000 {
1610 compatible = 1570 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 1571 reg = <0 0x00c84000 0 0x4000>;
1612 reg-names = " 1572 reg-names = "se";
1613 clock-names = 1573 clock-names = "se";
1614 clocks = <&gc 1574 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1575 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1576 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1577 dma-names = "tx", "rx";
1618 pinctrl-names 1578 pinctrl-names = "default";
1619 pinctrl-0 = < 1579 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1580 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1581 spi-max-frequency = <50000000>;
1622 #address-cell 1582 #address-cells = <1>;
1623 #size-cells = 1583 #size-cells = <0>;
1624 status = "dis 1584 status = "disabled";
1625 }; 1585 };
1626 1586
1627 i2c19: i2c@c88000 { 1587 i2c19: i2c@c88000 {
1628 compatible = 1588 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1589 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1590 clock-names = "se";
1631 clocks = <&gc 1591 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1592 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1593 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1594 dma-names = "tx", "rx";
1635 pinctrl-names 1595 pinctrl-names = "default";
1636 pinctrl-0 = < 1596 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1597 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1598 #address-cells = <1>;
1639 #size-cells = 1599 #size-cells = <0>;
1640 status = "dis 1600 status = "disabled";
1641 }; 1601 };
1642 1602
1643 spi19: spi@c88000 { 1603 spi19: spi@c88000 {
1644 compatible = 1604 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 1605 reg = <0 0x00c88000 0 0x4000>;
1646 reg-names = " 1606 reg-names = "se";
1647 clock-names = 1607 clock-names = "se";
1648 clocks = <&gc 1608 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1609 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1610 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1611 dma-names = "tx", "rx";
1652 pinctrl-names 1612 pinctrl-names = "default";
1653 pinctrl-0 = < 1613 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1614 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1615 spi-max-frequency = <50000000>;
1656 #address-cell 1616 #address-cells = <1>;
1657 #size-cells = 1617 #size-cells = <0>;
1658 status = "dis 1618 status = "disabled";
1659 }; 1619 };
1660 1620
1661 i2c13: i2c@c8c000 { 1621 i2c13: i2c@c8c000 {
1662 compatible = 1622 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1623 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1624 clock-names = "se";
1665 clocks = <&gc 1625 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1626 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1627 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1628 dma-names = "tx", "rx";
1669 pinctrl-names 1629 pinctrl-names = "default";
1670 pinctrl-0 = < 1630 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1631 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1632 #address-cells = <1>;
1673 #size-cells = 1633 #size-cells = <0>;
1674 status = "dis 1634 status = "disabled";
1675 }; 1635 };
1676 1636
1677 spi13: spi@c8c000 { 1637 spi13: spi@c8c000 {
1678 compatible = 1638 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 1639 reg = <0 0x00c8c000 0 0x4000>;
1680 reg-names = " 1640 reg-names = "se";
1681 clock-names = 1641 clock-names = "se";
1682 clocks = <&gc 1642 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1643 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1644 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1645 dma-names = "tx", "rx";
1686 pinctrl-names 1646 pinctrl-names = "default";
1687 pinctrl-0 = < 1647 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1648 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1649 spi-max-frequency = <50000000>;
1690 #address-cell 1650 #address-cells = <1>;
1691 #size-cells = 1651 #size-cells = <0>;
1692 status = "dis 1652 status = "disabled";
1693 }; 1653 };
1694 1654
1695 i2c14: i2c@c90000 { 1655 i2c14: i2c@c90000 {
1696 compatible = 1656 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1657 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1658 clock-names = "se";
1699 clocks = <&gc 1659 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1660 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1661 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1662 dma-names = "tx", "rx";
1703 pinctrl-names 1663 pinctrl-names = "default";
1704 pinctrl-0 = < 1664 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1665 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1666 #address-cells = <1>;
1707 #size-cells = 1667 #size-cells = <0>;
1708 status = "dis 1668 status = "disabled";
1709 }; 1669 };
1710 1670
1711 spi14: spi@c90000 { 1671 spi14: spi@c90000 {
1712 compatible = 1672 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 1673 reg = <0 0x00c90000 0 0x4000>;
1714 reg-names = " 1674 reg-names = "se";
1715 clock-names = 1675 clock-names = "se";
1716 clocks = <&gc 1676 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1677 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1678 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1679 dma-names = "tx", "rx";
1720 pinctrl-names 1680 pinctrl-names = "default";
1721 pinctrl-0 = < 1681 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1682 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1683 spi-max-frequency = <50000000>;
1724 #address-cell 1684 #address-cells = <1>;
1725 #size-cells = 1685 #size-cells = <0>;
1726 status = "dis 1686 status = "disabled";
1727 }; 1687 };
1728 1688
1729 i2c15: i2c@c94000 { 1689 i2c15: i2c@c94000 {
1730 compatible = 1690 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1691 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1692 clock-names = "se";
1733 clocks = <&gc 1693 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1694 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1695 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1696 dma-names = "tx", "rx";
1737 pinctrl-names 1697 pinctrl-names = "default";
1738 pinctrl-0 = < 1698 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1699 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1700 #address-cells = <1>;
1741 #size-cells = 1701 #size-cells = <0>;
1742 status = "dis 1702 status = "disabled";
1743 }; 1703 };
1744 1704
1745 spi15: spi@c94000 { 1705 spi15: spi@c94000 {
1746 compatible = 1706 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 1707 reg = <0 0x00c94000 0 0x4000>;
1748 reg-names = " 1708 reg-names = "se";
1749 clock-names = 1709 clock-names = "se";
1750 clocks = <&gc 1710 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1711 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1712 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1713 dma-names = "tx", "rx";
1754 pinctrl-names 1714 pinctrl-names = "default";
1755 pinctrl-0 = < 1715 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1716 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1717 spi-max-frequency = <50000000>;
1758 #address-cell 1718 #address-cells = <1>;
1759 #size-cells = 1719 #size-cells = <0>;
1760 status = "dis 1720 status = "disabled";
1761 }; 1721 };
1762 }; 1722 };
1763 1723
1764 config_noc: interconnect@1500 1724 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1725 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1726 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1727 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1728 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1729 };
1770 1730
1771 system_noc: interconnect@1620 1731 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1732 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1733 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1734 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1735 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1736 };
1777 1737
1778 mc_virt: interconnect@163a000 1738 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1739 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1740 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1741 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1742 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1743 };
1784 1744
1785 aggre1_noc: interconnect@16e0 1745 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1746 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1747 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1748 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1749 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1750 };
1791 1751
1792 aggre2_noc: interconnect@1700 1752 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1753 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1754 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1755 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1756 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1757 };
1798 1758
1799 compute_noc: interconnect@172 1759 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1760 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1761 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1762 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1763 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1764 };
1805 1765
1806 mmss_noc: interconnect@174000 1766 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1767 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1768 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1769 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1770 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1771 };
1812 1772
1813 system-cache-controller@92000 1773 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1774 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 !! 1775 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1816 <0 0x09300000 0 !! 1776 reg-names = "llcc_base", "llcc_broadcast_base";
1817 <0 0x09600000 0 <<
1818 reg-names = "llcc0_ba <<
1819 "llcc3_ba <<
1820 interrupts = <GIC_SPI 1777 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1778 };
1822 1779
1823 dma@10a2000 { 1780 dma@10a2000 {
1824 compatible = "qcom,sm 1781 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1825 reg = <0x0 0x010a2000 1782 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 1783 <0x0 0x010ad000 0x0 0x3000>;
1827 }; 1784 };
1828 1785
1829 pcie0: pcie@1c00000 { !! 1786 pcie0: pci@1c00000 {
1830 compatible = "qcom,pc !! 1787 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1831 reg = <0 0x01c00000 0 1788 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1789 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1790 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1791 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1792 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1793 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1794 device_type = "pci";
1838 linux,pci-domain = <0 1795 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1796 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1797 num-lanes = <1>;
1841 1798
1842 #address-cells = <3>; 1799 #address-cells = <3>;
1843 #size-cells = <2>; 1800 #size-cells = <2>;
1844 1801
1845 ranges = <0x01000000 1802 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 1803 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 1804
1848 interrupts = <GIC_SPI !! 1805 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1849 <GIC_SPI !! 1806 interrupt-names = "msi";
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 1807 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1808 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1809 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1810 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1811 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1812 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1813
1871 clocks = <&gcc GCC_PC 1814 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1815 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1816 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1817 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1818 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1819 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG !! 1820 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", 1821 clock-names = "pipe",
1880 "aux", 1822 "aux",
1881 "cfg", 1823 "cfg",
1882 "bus_ma 1824 "bus_master",
1883 "bus_sl 1825 "bus_slave",
1884 "slave_ 1826 "slave_q2a",
1885 "tbu", !! 1827 "tbu";
1886 "ref"; <<
1887 1828
>> 1829 iommus = <&apps_smmu 0x1d80 0x3f>;
1888 iommu-map = <0x0 &a 1830 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1831 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1832
1891 resets = <&gcc GCC_PC 1833 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1834 reset-names = "pci";
1893 1835
1894 power-domains = <&gcc 1836 power-domains = <&gcc PCIE_0_GDSC>;
1895 1837
1896 phys = <&pcie0_phy>; !! 1838 phys = <&pcie0_lane>;
1897 phy-names = "pciephy" 1839 phy-names = "pciephy";
1898 1840
1899 perst-gpios = <&tlmm !! 1841 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 !! 1842 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1843
1902 pinctrl-names = "defa 1844 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1845 pinctrl-0 = <&pcie0_default_state>;
1904 1846
1905 status = "disabled"; 1847 status = "disabled";
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; 1848 };
1917 1849
1918 pcie0_phy: phy@1c06000 { 1850 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1851 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 !! 1852 reg = <0 0x01c06000 0 0x1c0>;
>> 1853 #address-cells = <2>;
>> 1854 #size-cells = <2>;
>> 1855 ranges;
1921 clocks = <&gcc GCC_PC 1856 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1857 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC !! 1858 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1924 <&gcc GCC_PC !! 1859 clock-names = "aux", "cfg_ahb", "refgen";
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 1860
1937 resets = <&gcc GCC_PC 1861 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1862 reset-names = "phy";
1939 1863
1940 assigned-clocks = <&g 1864 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1865 assigned-clock-rates = <100000000>;
1942 1866
1943 status = "disabled"; 1867 status = "disabled";
>> 1868
>> 1869 pcie0_lane: phy@1c06200 {
>> 1870 reg = <0 0x01c06200 0 0x170>, /* tx */
>> 1871 <0 0x01c06400 0 0x200>, /* rx */
>> 1872 <0 0x01c06800 0 0x1f0>, /* pcs */
>> 1873 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1874 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1875 clock-names = "pipe0";
>> 1876
>> 1877 #phy-cells = <0>;
>> 1878 clock-output-names = "pcie_0_pipe_clk";
>> 1879 };
1944 }; 1880 };
1945 1881
1946 pcie1: pcie@1c08000 { !! 1882 pcie1: pci@1c08000 {
1947 compatible = "qcom,pc !! 1883 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1948 reg = <0 0x01c08000 0 1884 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1885 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1886 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1887 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1888 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1889 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1890 device_type = "pci";
1955 linux,pci-domain = <1 1891 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1892 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1893 num-lanes = <2>;
1958 1894
1959 #address-cells = <3>; 1895 #address-cells = <3>;
1960 #size-cells = <2>; 1896 #size-cells = <2>;
1961 1897
1962 ranges = <0x01000000 1898 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1899 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1900
1965 interrupts = <GIC_SPI !! 1901 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1966 <GIC_SPI !! 1902 interrupt-names = "msi";
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 1903 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1904 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1905 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1906 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1907 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1908 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1909
1988 clocks = <&gcc GCC_PC 1910 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1911 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1912 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1913 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1914 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1915 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG !! 1916 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", 1917 clock-names = "pipe",
1997 "aux", 1918 "aux",
1998 "cfg", 1919 "cfg",
1999 "bus_ma 1920 "bus_master",
2000 "bus_sl 1921 "bus_slave",
2001 "slave_ 1922 "slave_q2a",
2002 "tbu", !! 1923 "tbu";
2003 "ref"; <<
2004 1924
2005 assigned-clocks = <&g 1925 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 1926 assigned-clock-rates = <19200000>;
2007 1927
>> 1928 iommus = <&apps_smmu 0x1e00 0x3f>;
2008 iommu-map = <0x0 &a 1929 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 1930 <0x100 &apps_smmu 0x1e01 0x1>;
2010 1931
2011 resets = <&gcc GCC_PC 1932 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 1933 reset-names = "pci";
2013 1934
2014 power-domains = <&gcc 1935 power-domains = <&gcc PCIE_1_GDSC>;
2015 1936
2016 phys = <&pcie1_phy>; !! 1937 phys = <&pcie1_lane>;
2017 phy-names = "pciephy" 1938 phy-names = "pciephy";
2018 1939
2019 perst-gpios = <&tlmm !! 1940 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 1941 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 1942
2022 pinctrl-names = "defa 1943 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 1944 pinctrl-0 = <&pcie1_default_state>;
2024 1945
2025 status = "disabled"; 1946 status = "disabled";
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; 1947 };
2037 1948
2038 pcie1_phy: phy@1c0e000 { 1949 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 1950 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 !! 1951 reg = <0 0x01c0e000 0 0x1c0>;
>> 1952 #address-cells = <2>;
>> 1953 #size-cells = <2>;
>> 1954 ranges;
2041 clocks = <&gcc GCC_PC 1955 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 1956 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC !! 1957 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2044 <&gcc GCC_PC !! 1958 clock-names = "aux", "cfg_ahb", "refgen";
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 1959
2057 resets = <&gcc GCC_PC 1960 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 1961 reset-names = "phy";
2059 1962
2060 assigned-clocks = <&g 1963 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 1964 assigned-clock-rates = <100000000>;
2062 1965
2063 status = "disabled"; 1966 status = "disabled";
>> 1967
>> 1968 pcie1_lane: phy@1c0e200 {
>> 1969 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
>> 1970 <0 0x01c0e400 0 0x200>, /* rx0 */
>> 1971 <0 0x01c0ea00 0 0x1f0>, /* pcs */
>> 1972 <0 0x01c0e600 0 0x170>, /* tx1 */
>> 1973 <0 0x01c0e800 0 0x200>, /* rx1 */
>> 1974 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1975 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1976 clock-names = "pipe0";
>> 1977
>> 1978 #phy-cells = <0>;
>> 1979 clock-output-names = "pcie_1_pipe_clk";
>> 1980 };
2064 }; 1981 };
2065 1982
2066 ufs_mem_hc: ufshc@1d84000 { 1983 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 1984 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 1985 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 1986 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 1987 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 1988 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 1989 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 1990 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 1991 phy-names = "ufsphy";
2075 lanes-per-direction = 1992 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 1993 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 1994 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 1995 reset-names = "rst";
2079 1996
2080 iommus = <&apps_smmu 1997 iommus = <&apps_smmu 0x300 0>;
2081 1998
2082 clock-names = 1999 clock-names =
2083 "core_clk", 2000 "core_clk",
2084 "bus_aggr_clk 2001 "bus_aggr_clk",
2085 "iface_clk", 2002 "iface_clk",
2086 "core_clk_uni 2003 "core_clk_unipro",
2087 "ref_clk", 2004 "ref_clk",
2088 "tx_lane0_syn 2005 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 2006 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 2007 "rx_lane1_sync_clk",
2091 "ice_core_clk 2008 "ice_core_clk";
2092 clocks = 2009 clocks =
2093 <&gcc GCC_UFS 2010 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 2011 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 2012 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 2013 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 2014 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 2015 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2016 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2017 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2018 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2019 freq-table-hz =
2103 <37500000 300 2020 <37500000 300000000>,
2104 <0 0>, 2021 <0 0>,
2105 <0 0>, 2022 <0 0>,
2106 <37500000 300 2023 <37500000 300000000>,
2107 <0 0>, 2024 <0 0>,
2108 <0 0>, 2025 <0 0>,
2109 <0 0>, 2026 <0 0>,
2110 <0 0>, 2027 <0 0>,
2111 <0 300000000> 2028 <0 300000000>;
2112 2029
2113 status = "disabled"; 2030 status = "disabled";
2114 }; 2031 };
2115 2032
2116 ufs_mem_phy: phy@1d87000 { 2033 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2034 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 2035 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 2036 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 2037 #size-cells = <2>;
2121 <&gcc GCC_UF !! 2038 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 2039 clock-names = "ref",
2124 "ref_au !! 2040 "ref_aux";
2125 "qref"; !! 2041 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>> 2042 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2126 2043
2127 power-domains = <&gcc 2044 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2045
2129 resets = <&ufs_mem_hc 2046 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2047 reset-names = "ufsphy";
2131 <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 2048 status = "disabled";
2135 }; <<
2136 2049
2137 cryptobam: dma-controller@1dc !! 2050 ufs_mem_phy_lanes: phy@1d87400 {
2138 compatible = "qcom,ba !! 2051 reg = <0 0x01d87400 0 0x16c>,
2139 reg = <0 0x01dc4000 0 !! 2052 <0 0x01d87600 0 0x200>,
2140 interrupts = <GIC_SPI !! 2053 <0 0x01d87c00 0 0x200>,
2141 #dma-cells = <1>; !! 2054 <0 0x01d87800 0 0x16c>,
2142 qcom,ee = <0>; !! 2055 <0 0x01d87a00 0 0x200>;
2143 qcom,controlled-remot !! 2056 #phy-cells = <0>;
2144 num-channels = <8>; !! 2057 };
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; 2058 };
2166 2059
2167 tcsr_mutex: hwlock@1f40000 { 2060 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc 2061 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 2062 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>; 2063 #hwlock-cells = <1>;
2171 }; 2064 };
2172 2065
2173 tcsr_regs_1: syscon@1f60000 { 2066 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm 2067 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 2068 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 }; 2069 };
2177 2070
2178 remoteproc_slpi: remoteproc@2 2071 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2072 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2073 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2074
2182 interrupts-extended = 2075 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2076 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2077 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2078 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2079 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2080 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2081 "handover", "stop-ack";
2189 2082
2190 clocks = <&rpmhcc RPM 2083 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2084 clock-names = "xo";
2192 2085
2193 power-domains = <&rpm 2086 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpm 2087 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = 2088 power-domain-names = "lcx", "lmx";
2196 2089
2197 memory-region = <&slp 2090 memory-region = <&slpi_mem>;
2198 2091
2199 qcom,qmp = <&aoss_qmp 2092 qcom,qmp = <&aoss_qmp>;
2200 2093
2201 qcom,smem-states = <& 2094 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2095 qcom,smem-state-names = "stop";
2203 2096
2204 status = "disabled"; 2097 status = "disabled";
2205 2098
2206 glink-edge { 2099 glink-edge {
2207 interrupts = 2100 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2101 label = "dsps";
2209 qcom,remote-p 2102 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2103 mboxes = <&apss_shared 24>;
2211 2104
2212 fastrpc { 2105 fastrpc {
2213 compa 2106 compatible = "qcom,fastrpc";
2214 qcom, 2107 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2108 label = "sdsp";
2216 qcom, 2109 qcom,non-secure-domain;
2217 #addr 2110 #address-cells = <1>;
2218 #size 2111 #size-cells = <0>;
2219 2112
2220 compu 2113 compute-cb@1 {
2221 2114 compatible = "qcom,fastrpc-compute-cb";
2222 2115 reg = <1>;
2223 2116 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2117 };
2225 2118
2226 compu 2119 compute-cb@2 {
2227 2120 compatible = "qcom,fastrpc-compute-cb";
2228 2121 reg = <2>;
2229 2122 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2123 };
2231 2124
2232 compu 2125 compute-cb@3 {
2233 2126 compatible = "qcom,fastrpc-compute-cb";
2234 2127 reg = <3>;
2235 2128 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2129 /* note: shared-cb = <4> in downstream */
2237 }; 2130 };
2238 }; 2131 };
2239 }; 2132 };
2240 }; 2133 };
2241 2134
2242 gpu: gpu@2c00000 { 2135 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad !! 2136 /*
>> 2137 * note: the amd,imageon compatible makes it possible
>> 2138 * to use the drm/msm driver without the display node,
>> 2139 * make sure to remove it when display node is added
>> 2140 */
>> 2141 compatible = "qcom,adreno-640.1",
>> 2142 "qcom,adreno",
>> 2143 "amd,imageon";
>> 2144
2244 reg = <0 0x02c00000 0 2145 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2146 reg-names = "kgsl_3d0_reg_memory";
2246 2147
2247 interrupts = <GIC_SPI 2148 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2149
2249 iommus = <&adreno_smm 2150 iommus = <&adreno_smmu 0 0x401>;
2250 2151
2251 operating-points-v2 = 2152 operating-points-v2 = <&gpu_opp_table>;
2252 2153
2253 qcom,gmu = <&gmu>; 2154 qcom,gmu = <&gmu>;
2254 2155
2255 nvmem-cells = <&gpu_s <<
2256 nvmem-cell-names = "s <<
2257 #cooling-cells = <2>; <<
2258 <<
2259 status = "disabled"; 2156 status = "disabled";
2260 2157
2261 zap-shader { 2158 zap-shader {
2262 memory-region 2159 memory-region = <&gpu_mem>;
2263 }; 2160 };
2264 2161
>> 2162 /* note: downstream checks gpu binning for 675 Mhz */
2265 gpu_opp_table: opp-ta 2163 gpu_opp_table: opp-table {
2266 compatible = 2164 compatible = "operating-points-v2";
2267 2165
2268 opp-675000000 2166 opp-675000000 {
2269 opp-h 2167 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2168 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s <<
2272 }; 2169 };
2273 2170
2274 opp-585000000 2171 opp-585000000 {
2275 opp-h 2172 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2173 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s <<
2278 }; 2174 };
2279 2175
2280 opp-499200000 2176 opp-499200000 {
2281 opp-h 2177 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2178 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s <<
2284 }; 2179 };
2285 2180
2286 opp-427000000 2181 opp-427000000 {
2287 opp-h 2182 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2183 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s <<
2290 }; 2184 };
2291 2185
2292 opp-345000000 2186 opp-345000000 {
2293 opp-h 2187 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2188 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s <<
2296 }; 2189 };
2297 2190
2298 opp-257000000 2191 opp-257000000 {
2299 opp-h 2192 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s <<
2302 }; 2194 };
2303 }; 2195 };
2304 }; 2196 };
2305 2197
2306 gmu: gmu@2c6a000 { 2198 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad 2199 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2200
2309 reg = <0 0x02c6a000 0 2201 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2202 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2203 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2204 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2205
2314 interrupts = <GIC_SPI 2206 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2207 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2208 interrupt-names = "hfi", "gmu";
2317 2209
2318 clocks = <&gpucc GPU_ 2210 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2211 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2212 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2213 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2214 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2215 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2216
2325 power-domains = <&gpu 2217 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2218 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2219 power-domain-names = "cx", "gx";
2328 2220
2329 iommus = <&adreno_smm 2221 iommus = <&adreno_smmu 5 0x400>;
2330 2222
2331 operating-points-v2 = 2223 operating-points-v2 = <&gmu_opp_table>;
2332 2224
2333 status = "disabled"; 2225 status = "disabled";
2334 2226
2335 gmu_opp_table: opp-ta 2227 gmu_opp_table: opp-table {
2336 compatible = 2228 compatible = "operating-points-v2";
2337 2229
2338 opp-200000000 2230 opp-200000000 {
2339 opp-h 2231 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2232 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2233 };
2342 }; 2234 };
2343 }; 2235 };
2344 2236
2345 gpucc: clock-controller@2c900 2237 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2238 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2239 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2240 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2241 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2242 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2243 clock-names = "bi_tcxo",
2352 "gcc_gp 2244 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2245 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2246 #clock-cells = <1>;
2355 #reset-cells = <1>; 2247 #reset-cells = <1>;
2356 #power-domain-cells = 2248 #power-domain-cells = <1>;
2357 }; 2249 };
2358 2250
2359 adreno_smmu: iommu@2ca0000 { 2251 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm !! 2252 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2361 "qcom,sm <<
2362 reg = <0 0x02ca0000 0 2253 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2254 #iommu-cells = <2>;
2364 #global-interrupts = 2255 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2256 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2257 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2258 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2259 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2260 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2261 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2262 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2263 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2264 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2265 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2266 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2267 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2268 clock-names = "ahb", "bus", "iface";
2378 2269
2379 power-domains = <&gpu 2270 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2271 };
2381 2272
2382 tlmm: pinctrl@3100000 { 2273 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2274 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2275 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2276 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2277 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2278 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2279 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2281 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2282 gpio-controller;
2392 #gpio-cells = <2>; 2283 #gpio-cells = <2>;
2393 interrupt-controller; 2284 interrupt-controller;
2394 #interrupt-cells = <2 2285 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2286 wakeup-parent = <&pdc>;
2396 2287
2397 qup_i2c0_default: qup 2288 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0 2289 pins = "gpio0", "gpio1";
2399 function = "q 2290 function = "qup0";
2400 drive-strengt 2291 drive-strength = <0x02>;
2401 bias-disable; 2292 bias-disable;
2402 }; 2293 };
2403 2294
2404 qup_spi0_default: qup 2295 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0 2296 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2297 function = "qup0";
2407 drive-strengt 2298 drive-strength = <6>;
2408 bias-disable; 2299 bias-disable;
2409 }; 2300 };
2410 2301
2411 qup_i2c1_default: qup 2302 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio1 2303 pins = "gpio114", "gpio115";
2413 function = "q 2304 function = "qup1";
2414 drive-strengt 2305 drive-strength = <2>;
2415 bias-disable; 2306 bias-disable;
2416 }; 2307 };
2417 2308
2418 qup_spi1_default: qup 2309 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio1 2310 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2311 function = "qup1";
2421 drive-strengt 2312 drive-strength = <6>;
2422 bias-disable; 2313 bias-disable;
2423 }; 2314 };
2424 2315
2425 qup_i2c2_default: qup 2316 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio1 2317 pins = "gpio126", "gpio127";
2427 function = "q 2318 function = "qup2";
2428 drive-strengt 2319 drive-strength = <2>;
2429 bias-disable; 2320 bias-disable;
2430 }; 2321 };
2431 2322
2432 qup_spi2_default: qup 2323 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio1 2324 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2325 function = "qup2";
2435 drive-strengt 2326 drive-strength = <6>;
2436 bias-disable; 2327 bias-disable;
2437 }; 2328 };
2438 2329
2439 qup_i2c3_default: qup 2330 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio1 2331 pins = "gpio144", "gpio145";
2441 function = "q 2332 function = "qup3";
2442 drive-strengt 2333 drive-strength = <2>;
2443 bias-disable; 2334 bias-disable;
2444 }; 2335 };
2445 2336
2446 qup_spi3_default: qup 2337 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio1 2338 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2339 function = "qup3";
2449 drive-strengt 2340 drive-strength = <6>;
2450 bias-disable; 2341 bias-disable;
2451 }; 2342 };
2452 2343
2453 qup_i2c4_default: qup 2344 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio5 2345 pins = "gpio51", "gpio52";
2455 function = "q 2346 function = "qup4";
2456 drive-strengt 2347 drive-strength = <2>;
2457 bias-disable; 2348 bias-disable;
2458 }; 2349 };
2459 2350
2460 qup_spi4_default: qup 2351 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio5 2352 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2353 function = "qup4";
2463 drive-strengt 2354 drive-strength = <6>;
2464 bias-disable; 2355 bias-disable;
2465 }; 2356 };
2466 2357
2467 qup_i2c5_default: qup 2358 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio1 2359 pins = "gpio121", "gpio122";
2469 function = "q 2360 function = "qup5";
2470 drive-strengt 2361 drive-strength = <2>;
2471 bias-disable; 2362 bias-disable;
2472 }; 2363 };
2473 2364
2474 qup_spi5_default: qup 2365 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio1 2366 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2367 function = "qup5";
2477 drive-strengt 2368 drive-strength = <6>;
2478 bias-disable; 2369 bias-disable;
2479 }; 2370 };
2480 2371
2481 qup_i2c6_default: qup 2372 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6 2373 pins = "gpio6", "gpio7";
2483 function = "q 2374 function = "qup6";
2484 drive-strengt 2375 drive-strength = <2>;
2485 bias-disable; 2376 bias-disable;
2486 }; 2377 };
2487 2378
2488 qup_spi6_default: qup !! 2379 qup_spi6_default: qup-spi6_default-state {
2489 pins = "gpio4 2380 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2381 function = "qup6";
2491 drive-strengt 2382 drive-strength = <6>;
2492 bias-disable; 2383 bias-disable;
2493 }; 2384 };
2494 2385
2495 qup_i2c7_default: qup 2386 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio9 2387 pins = "gpio98", "gpio99";
2497 function = "q 2388 function = "qup7";
2498 drive-strengt 2389 drive-strength = <2>;
2499 bias-disable; 2390 bias-disable;
2500 }; 2391 };
2501 2392
2502 qup_spi7_default: qup !! 2393 qup_spi7_default: qup-spi7_default-state {
2503 pins = "gpio9 2394 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2395 function = "qup7";
2505 drive-strengt 2396 drive-strength = <6>;
2506 bias-disable; 2397 bias-disable;
2507 }; 2398 };
2508 2399
2509 qup_i2c8_default: qup 2400 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio8 2401 pins = "gpio88", "gpio89";
2511 function = "q 2402 function = "qup8";
2512 drive-strengt 2403 drive-strength = <2>;
2513 bias-disable; 2404 bias-disable;
2514 }; 2405 };
2515 2406
2516 qup_spi8_default: qup 2407 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio8 2408 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2409 function = "qup8";
2519 drive-strengt 2410 drive-strength = <6>;
2520 bias-disable; 2411 bias-disable;
2521 }; 2412 };
2522 2413
2523 qup_i2c9_default: qup 2414 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio3 2415 pins = "gpio39", "gpio40";
2525 function = "q 2416 function = "qup9";
2526 drive-strengt 2417 drive-strength = <2>;
2527 bias-disable; 2418 bias-disable;
2528 }; 2419 };
2529 2420
2530 qup_spi9_default: qup 2421 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio3 2422 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2423 function = "qup9";
2533 drive-strengt 2424 drive-strength = <6>;
2534 bias-disable; 2425 bias-disable;
2535 }; 2426 };
2536 2427
2537 qup_uart9_default: qu <<
2538 pins = "gpio4 <<
2539 function = "q <<
2540 drive-strengt <<
2541 bias-disable; <<
2542 }; <<
2543 <<
2544 qup_i2c10_default: qu 2428 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9 2429 pins = "gpio9", "gpio10";
2546 function = "q 2430 function = "qup10";
2547 drive-strengt 2431 drive-strength = <2>;
2548 bias-disable; 2432 bias-disable;
2549 }; 2433 };
2550 2434
2551 qup_spi10_default: qu 2435 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9 2436 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2437 function = "qup10";
2554 drive-strengt 2438 drive-strength = <6>;
2555 bias-disable; 2439 bias-disable;
2556 }; 2440 };
2557 2441
2558 qup_i2c11_default: qu 2442 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio9 2443 pins = "gpio94", "gpio95";
2560 function = "q 2444 function = "qup11";
2561 drive-strengt 2445 drive-strength = <2>;
2562 bias-disable; 2446 bias-disable;
2563 }; 2447 };
2564 2448
2565 qup_spi11_default: qu 2449 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio9 2450 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2451 function = "qup11";
2568 drive-strengt 2452 drive-strength = <6>;
2569 bias-disable; 2453 bias-disable;
2570 }; 2454 };
2571 2455
2572 qup_i2c12_default: qu 2456 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio8 2457 pins = "gpio83", "gpio84";
2574 function = "q 2458 function = "qup12";
2575 drive-strengt 2459 drive-strength = <2>;
2576 bias-disable; 2460 bias-disable;
2577 }; 2461 };
2578 2462
2579 qup_spi12_default: qu 2463 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio8 2464 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2465 function = "qup12";
2582 drive-strengt 2466 drive-strength = <6>;
2583 bias-disable; 2467 bias-disable;
2584 }; 2468 };
2585 2469
2586 qup_i2c13_default: qu 2470 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio4 2471 pins = "gpio43", "gpio44";
2588 function = "q 2472 function = "qup13";
2589 drive-strengt 2473 drive-strength = <2>;
2590 bias-disable; 2474 bias-disable;
2591 }; 2475 };
2592 2476
2593 qup_spi13_default: qu 2477 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio4 2478 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2479 function = "qup13";
2596 drive-strengt 2480 drive-strength = <6>;
2597 bias-disable; 2481 bias-disable;
2598 }; 2482 };
2599 2483
2600 qup_i2c14_default: qu 2484 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio4 2485 pins = "gpio47", "gpio48";
2602 function = "q 2486 function = "qup14";
2603 drive-strengt 2487 drive-strength = <2>;
2604 bias-disable; 2488 bias-disable;
2605 }; 2489 };
2606 2490
2607 qup_spi14_default: qu 2491 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio4 2492 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2493 function = "qup14";
2610 drive-strengt 2494 drive-strength = <6>;
2611 bias-disable; 2495 bias-disable;
2612 }; 2496 };
2613 2497
2614 qup_i2c15_default: qu 2498 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio2 2499 pins = "gpio27", "gpio28";
2616 function = "q 2500 function = "qup15";
2617 drive-strengt 2501 drive-strength = <2>;
2618 bias-disable; 2502 bias-disable;
2619 }; 2503 };
2620 2504
2621 qup_spi15_default: qu 2505 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio2 2506 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2507 function = "qup15";
2624 drive-strengt 2508 drive-strength = <6>;
2625 bias-disable; 2509 bias-disable;
2626 }; 2510 };
2627 2511
2628 qup_i2c16_default: qu 2512 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio8 2513 pins = "gpio86", "gpio85";
2630 function = "q 2514 function = "qup16";
2631 drive-strengt 2515 drive-strength = <2>;
2632 bias-disable; 2516 bias-disable;
2633 }; 2517 };
2634 2518
2635 qup_spi16_default: qu 2519 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio8 2520 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2521 function = "qup16";
2638 drive-strengt 2522 drive-strength = <6>;
2639 bias-disable; 2523 bias-disable;
2640 }; 2524 };
2641 2525
2642 qup_i2c17_default: qu 2526 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio5 2527 pins = "gpio55", "gpio56";
2644 function = "q 2528 function = "qup17";
2645 drive-strengt 2529 drive-strength = <2>;
2646 bias-disable; 2530 bias-disable;
2647 }; 2531 };
2648 2532
2649 qup_spi17_default: qu 2533 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio5 2534 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2535 function = "qup17";
2652 drive-strengt 2536 drive-strength = <6>;
2653 bias-disable; 2537 bias-disable;
2654 }; 2538 };
2655 2539
2656 qup_i2c18_default: qu 2540 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio2 2541 pins = "gpio23", "gpio24";
2658 function = "q 2542 function = "qup18";
2659 drive-strengt 2543 drive-strength = <2>;
2660 bias-disable; 2544 bias-disable;
2661 }; 2545 };
2662 2546
2663 qup_spi18_default: qu 2547 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio2 2548 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2549 function = "qup18";
2666 drive-strengt 2550 drive-strength = <6>;
2667 bias-disable; 2551 bias-disable;
2668 }; 2552 };
2669 2553
2670 qup_i2c19_default: qu 2554 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio5 2555 pins = "gpio57", "gpio58";
2672 function = "q 2556 function = "qup19";
2673 drive-strengt 2557 drive-strength = <2>;
2674 bias-disable; 2558 bias-disable;
2675 }; 2559 };
2676 2560
2677 qup_spi19_default: qu 2561 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio5 2562 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2563 function = "qup19";
2680 drive-strengt 2564 drive-strength = <6>;
2681 bias-disable; 2565 bias-disable;
2682 }; 2566 };
2683 2567
2684 pcie0_default_state: 2568 pcie0_default_state: pcie0-default-state {
2685 perst-pins { 2569 perst-pins {
2686 pins 2570 pins = "gpio35";
2687 funct 2571 function = "gpio";
2688 drive 2572 drive-strength = <2>;
2689 bias- 2573 bias-pull-down;
2690 }; 2574 };
2691 2575
2692 clkreq-pins { 2576 clkreq-pins {
2693 pins 2577 pins = "gpio36";
2694 funct 2578 function = "pci_e0";
2695 drive 2579 drive-strength = <2>;
2696 bias- 2580 bias-pull-up;
2697 }; 2581 };
2698 2582
2699 wake-pins { 2583 wake-pins {
2700 pins 2584 pins = "gpio37";
2701 funct 2585 function = "gpio";
2702 drive 2586 drive-strength = <2>;
2703 bias- 2587 bias-pull-up;
2704 }; 2588 };
2705 }; 2589 };
2706 2590
2707 pcie1_default_state: 2591 pcie1_default_state: pcie1-default-state {
2708 perst-pins { 2592 perst-pins {
2709 pins 2593 pins = "gpio102";
2710 funct 2594 function = "gpio";
2711 drive 2595 drive-strength = <2>;
2712 bias- 2596 bias-pull-down;
2713 }; 2597 };
2714 2598
2715 clkreq-pins { 2599 clkreq-pins {
2716 pins 2600 pins = "gpio103";
2717 funct 2601 function = "pci_e1";
2718 drive 2602 drive-strength = <2>;
2719 bias- 2603 bias-pull-up;
2720 }; 2604 };
2721 2605
2722 wake-pins { 2606 wake-pins {
2723 pins 2607 pins = "gpio104";
2724 funct 2608 function = "gpio";
2725 drive 2609 drive-strength = <2>;
2726 bias- 2610 bias-pull-up;
2727 }; 2611 };
2728 }; 2612 };
2729 }; 2613 };
2730 2614
2731 remoteproc_mpss: remoteproc@4 2615 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2616 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2617 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2618
2735 interrupts-extended = 2619 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2620 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2621 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2622 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2623 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2624 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2625 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2626 "stop-ack", "shutdown-ack";
2743 2627
2744 clocks = <&rpmhcc RPM 2628 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2629 clock-names = "xo";
2746 2630
2747 power-domains = <&rpm 2631 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpm 2632 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = 2633 power-domain-names = "cx", "mss";
2750 2634
2751 memory-region = <&mps 2635 memory-region = <&mpss_mem>;
2752 2636
2753 qcom,qmp = <&aoss_qmp 2637 qcom,qmp = <&aoss_qmp>;
2754 2638
2755 qcom,smem-states = <& 2639 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2640 qcom,smem-state-names = "stop";
2757 2641
2758 status = "disabled"; 2642 status = "disabled";
2759 2643
2760 glink-edge { 2644 glink-edge {
2761 interrupts = 2645 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2646 label = "modem";
2763 qcom,remote-p 2647 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2648 mboxes = <&apss_shared 12>;
2765 }; 2649 };
2766 }; 2650 };
2767 2651
2768 stm@6002000 { 2652 stm@6002000 {
2769 compatible = "arm,cor 2653 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2654 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2655 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2656 reg-names = "stm-base", "stm-stimulus-base";
2773 2657
2774 clocks = <&aoss_qmp>; 2658 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2659 clock-names = "apb_pclk";
2776 2660
2777 out-ports { 2661 out-ports {
2778 port { 2662 port {
2779 stm_o 2663 stm_out: endpoint {
2780 2664 remote-endpoint = <&funnel0_in7>;
2781 }; 2665 };
2782 }; 2666 };
2783 }; 2667 };
2784 }; 2668 };
2785 2669
2786 funnel@6041000 { 2670 funnel@6041000 {
2787 compatible = "arm,cor 2671 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2672 reg = <0 0x06041000 0 0x1000>;
2789 2673
2790 clocks = <&aoss_qmp>; 2674 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2675 clock-names = "apb_pclk";
2792 2676
2793 out-ports { 2677 out-ports {
2794 port { 2678 port {
2795 funne 2679 funnel0_out: endpoint {
2796 2680 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2681 };
2798 }; 2682 };
2799 }; 2683 };
2800 2684
2801 in-ports { 2685 in-ports {
2802 #address-cell 2686 #address-cells = <1>;
2803 #size-cells = 2687 #size-cells = <0>;
2804 2688
2805 port@7 { 2689 port@7 {
2806 reg = 2690 reg = <7>;
2807 funne 2691 funnel0_in7: endpoint {
2808 2692 remote-endpoint = <&stm_out>;
2809 }; 2693 };
2810 }; 2694 };
2811 }; 2695 };
2812 }; 2696 };
2813 2697
2814 funnel@6042000 { 2698 funnel@6042000 {
2815 compatible = "arm,cor 2699 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2700 reg = <0 0x06042000 0 0x1000>;
2817 2701
2818 clocks = <&aoss_qmp>; 2702 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2703 clock-names = "apb_pclk";
2820 2704
2821 out-ports { 2705 out-ports {
2822 port { 2706 port {
2823 funne 2707 funnel1_out: endpoint {
2824 2708 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2709 };
2826 }; 2710 };
2827 }; 2711 };
2828 2712
2829 in-ports { 2713 in-ports {
2830 #address-cell 2714 #address-cells = <1>;
2831 #size-cells = 2715 #size-cells = <0>;
2832 2716
2833 port@4 { 2717 port@4 {
2834 reg = 2718 reg = <4>;
2835 funne 2719 funnel1_in4: endpoint {
2836 2720 remote-endpoint = <&swao_replicator_out>;
2837 }; 2721 };
2838 }; 2722 };
2839 }; 2723 };
2840 }; 2724 };
2841 2725
2842 funnel@6043000 { 2726 funnel@6043000 {
2843 compatible = "arm,cor 2727 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2728 reg = <0 0x06043000 0 0x1000>;
2845 2729
2846 clocks = <&aoss_qmp>; 2730 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2731 clock-names = "apb_pclk";
2848 2732
2849 out-ports { 2733 out-ports {
2850 port { 2734 port {
2851 funne 2735 funnel2_out: endpoint {
2852 2736 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2737 };
2854 }; 2738 };
2855 }; 2739 };
2856 2740
2857 in-ports { 2741 in-ports {
2858 #address-cell 2742 #address-cells = <1>;
2859 #size-cells = 2743 #size-cells = <0>;
2860 2744
2861 port@2 { 2745 port@2 {
2862 reg = 2746 reg = <2>;
2863 funne 2747 funnel2_in2: endpoint {
2864 2748 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2749 };
2866 }; 2750 };
2867 }; 2751 };
2868 }; 2752 };
2869 2753
2870 funnel@6045000 { 2754 funnel@6045000 {
2871 compatible = "arm,cor 2755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2756 reg = <0 0x06045000 0 0x1000>;
2873 2757
2874 clocks = <&aoss_qmp>; 2758 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2759 clock-names = "apb_pclk";
2876 2760
2877 out-ports { 2761 out-ports {
2878 port { 2762 port {
2879 merge 2763 merge_funnel_out: endpoint {
2880 2764 remote-endpoint = <&etf_in>;
2881 }; 2765 };
2882 }; 2766 };
2883 }; 2767 };
2884 2768
2885 in-ports { 2769 in-ports {
2886 #address-cell 2770 #address-cells = <1>;
2887 #size-cells = 2771 #size-cells = <0>;
2888 2772
2889 port@0 { 2773 port@0 {
2890 reg = 2774 reg = <0>;
2891 merge 2775 merge_funnel_in0: endpoint {
2892 2776 remote-endpoint = <&funnel0_out>;
2893 }; 2777 };
2894 }; 2778 };
2895 2779
2896 port@1 { 2780 port@1 {
2897 reg = 2781 reg = <1>;
2898 merge 2782 merge_funnel_in1: endpoint {
2899 2783 remote-endpoint = <&funnel1_out>;
2900 }; 2784 };
2901 }; 2785 };
2902 2786
2903 port@2 { 2787 port@2 {
2904 reg = 2788 reg = <2>;
2905 merge 2789 merge_funnel_in2: endpoint {
2906 2790 remote-endpoint = <&funnel2_out>;
2907 }; 2791 };
2908 }; 2792 };
2909 }; 2793 };
2910 }; 2794 };
2911 2795
2912 replicator@6046000 { 2796 replicator@6046000 {
2913 compatible = "arm,cor 2797 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2798 reg = <0 0x06046000 0 0x1000>;
2915 2799
2916 clocks = <&aoss_qmp>; 2800 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2801 clock-names = "apb_pclk";
2918 2802
2919 out-ports { 2803 out-ports {
2920 #address-cell 2804 #address-cells = <1>;
2921 #size-cells = 2805 #size-cells = <0>;
2922 2806
2923 port@0 { 2807 port@0 {
2924 reg = 2808 reg = <0>;
2925 repli 2809 replicator_out0: endpoint {
2926 2810 remote-endpoint = <&etr_in>;
2927 }; 2811 };
2928 }; 2812 };
2929 2813
2930 port@1 { 2814 port@1 {
2931 reg = 2815 reg = <1>;
2932 repli 2816 replicator_out1: endpoint {
2933 2817 remote-endpoint = <&replicator1_in>;
2934 }; 2818 };
2935 }; 2819 };
2936 }; 2820 };
2937 2821
2938 in-ports { 2822 in-ports {
2939 port { 2823 port {
2940 repli 2824 replicator_in0: endpoint {
2941 2825 remote-endpoint = <&etf_out>;
2942 }; 2826 };
2943 }; 2827 };
2944 }; 2828 };
2945 }; 2829 };
2946 2830
2947 etf@6047000 { 2831 etf@6047000 {
2948 compatible = "arm,cor 2832 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2833 reg = <0 0x06047000 0 0x1000>;
2950 2834
2951 clocks = <&aoss_qmp>; 2835 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2836 clock-names = "apb_pclk";
2953 2837
2954 out-ports { 2838 out-ports {
2955 port { 2839 port {
2956 etf_o 2840 etf_out: endpoint {
2957 2841 remote-endpoint = <&replicator_in0>;
2958 }; 2842 };
2959 }; 2843 };
2960 }; 2844 };
2961 2845
2962 in-ports { 2846 in-ports {
2963 port { 2847 port {
2964 etf_i 2848 etf_in: endpoint {
2965 2849 remote-endpoint = <&merge_funnel_out>;
2966 }; 2850 };
2967 }; 2851 };
2968 }; 2852 };
2969 }; 2853 };
2970 2854
2971 etr@6048000 { 2855 etr@6048000 {
2972 compatible = "arm,cor 2856 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2857 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2858 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2859
2976 clocks = <&aoss_qmp>; 2860 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2861 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2862 arm,scatter-gather;
2979 2863
2980 in-ports { 2864 in-ports {
2981 port { 2865 port {
2982 etr_i 2866 etr_in: endpoint {
2983 2867 remote-endpoint = <&replicator_out0>;
2984 }; 2868 };
2985 }; 2869 };
2986 }; 2870 };
2987 }; 2871 };
2988 2872
2989 replicator@604a000 { 2873 replicator@604a000 {
2990 compatible = "arm,cor 2874 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2875 reg = <0 0x0604a000 0 0x1000>;
2992 2876
2993 clocks = <&aoss_qmp>; 2877 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2878 clock-names = "apb_pclk";
2995 2879
2996 out-ports { 2880 out-ports {
2997 #address-cell 2881 #address-cells = <1>;
2998 #size-cells = 2882 #size-cells = <0>;
2999 2883
3000 port@1 { 2884 port@1 {
3001 reg = 2885 reg = <1>;
3002 repli 2886 replicator1_out: endpoint {
3003 2887 remote-endpoint = <&swao_funnel_in>;
3004 }; 2888 };
3005 }; 2889 };
3006 }; 2890 };
3007 2891
3008 in-ports { 2892 in-ports {
>> 2893 #address-cells = <1>;
>> 2894 #size-cells = <0>;
3009 2895
3010 port { !! 2896 port@1 {
>> 2897 reg = <1>;
3011 repli 2898 replicator1_in: endpoint {
3012 2899 remote-endpoint = <&replicator_out1>;
3013 }; 2900 };
3014 }; 2901 };
3015 }; 2902 };
3016 }; 2903 };
3017 2904
3018 funnel@6b08000 { 2905 funnel@6b08000 {
3019 compatible = "arm,cor 2906 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2907 reg = <0 0x06b08000 0 0x1000>;
3021 2908
3022 clocks = <&aoss_qmp>; 2909 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2910 clock-names = "apb_pclk";
3024 2911
3025 out-ports { 2912 out-ports {
3026 port { 2913 port {
3027 swao_ 2914 swao_funnel_out: endpoint {
3028 2915 remote-endpoint = <&swao_etf_in>;
3029 }; 2916 };
3030 }; 2917 };
3031 }; 2918 };
3032 2919
3033 in-ports { 2920 in-ports {
3034 #address-cell 2921 #address-cells = <1>;
3035 #size-cells = 2922 #size-cells = <0>;
3036 2923
3037 port@6 { 2924 port@6 {
3038 reg = 2925 reg = <6>;
3039 swao_ 2926 swao_funnel_in: endpoint {
3040 2927 remote-endpoint = <&replicator1_out>;
3041 }; 2928 };
3042 }; 2929 };
3043 }; 2930 };
3044 }; 2931 };
3045 2932
3046 etf@6b09000 { 2933 etf@6b09000 {
3047 compatible = "arm,cor 2934 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2935 reg = <0 0x06b09000 0 0x1000>;
3049 2936
3050 clocks = <&aoss_qmp>; 2937 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2938 clock-names = "apb_pclk";
3052 2939
3053 out-ports { 2940 out-ports {
3054 port { 2941 port {
3055 swao_ 2942 swao_etf_out: endpoint {
3056 2943 remote-endpoint = <&swao_replicator_in>;
3057 }; 2944 };
3058 }; 2945 };
3059 }; 2946 };
3060 2947
3061 in-ports { 2948 in-ports {
3062 port { 2949 port {
3063 swao_ 2950 swao_etf_in: endpoint {
3064 2951 remote-endpoint = <&swao_funnel_out>;
3065 }; 2952 };
3066 }; 2953 };
3067 }; 2954 };
3068 }; 2955 };
3069 2956
3070 replicator@6b0a000 { 2957 replicator@6b0a000 {
3071 compatible = "arm,cor 2958 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 2959 reg = <0 0x06b0a000 0 0x1000>;
3073 2960
3074 clocks = <&aoss_qmp>; 2961 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 2962 clock-names = "apb_pclk";
3076 qcom,replicator-loses 2963 qcom,replicator-loses-context;
3077 2964
3078 out-ports { 2965 out-ports {
3079 port { 2966 port {
3080 swao_ 2967 swao_replicator_out: endpoint {
3081 2968 remote-endpoint = <&funnel1_in4>;
3082 }; 2969 };
3083 }; 2970 };
3084 }; 2971 };
3085 2972
3086 in-ports { 2973 in-ports {
3087 port { 2974 port {
3088 swao_ 2975 swao_replicator_in: endpoint {
3089 2976 remote-endpoint = <&swao_etf_out>;
3090 }; 2977 };
3091 }; 2978 };
3092 }; 2979 };
3093 }; 2980 };
3094 2981
3095 etm@7040000 { 2982 etm@7040000 {
3096 compatible = "arm,cor 2983 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 2984 reg = <0 0x07040000 0 0x1000>;
3098 2985
3099 cpu = <&CPU0>; 2986 cpu = <&CPU0>;
3100 2987
3101 clocks = <&aoss_qmp>; 2988 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 2989 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 2990 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 2991 qcom,skip-power-up;
3105 2992
3106 out-ports { 2993 out-ports {
3107 port { 2994 port {
3108 etm0_ 2995 etm0_out: endpoint {
3109 2996 remote-endpoint = <&apss_funnel_in0>;
3110 }; 2997 };
3111 }; 2998 };
3112 }; 2999 };
3113 }; 3000 };
3114 3001
3115 etm@7140000 { 3002 etm@7140000 {
3116 compatible = "arm,cor 3003 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 3004 reg = <0 0x07140000 0 0x1000>;
3118 3005
3119 cpu = <&CPU1>; 3006 cpu = <&CPU1>;
3120 3007
3121 clocks = <&aoss_qmp>; 3008 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3009 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3010 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3011 qcom,skip-power-up;
3125 3012
3126 out-ports { 3013 out-ports {
3127 port { 3014 port {
3128 etm1_ 3015 etm1_out: endpoint {
3129 3016 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3017 };
3131 }; 3018 };
3132 }; 3019 };
3133 }; 3020 };
3134 3021
3135 etm@7240000 { 3022 etm@7240000 {
3136 compatible = "arm,cor 3023 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3024 reg = <0 0x07240000 0 0x1000>;
3138 3025
3139 cpu = <&CPU2>; 3026 cpu = <&CPU2>;
3140 3027
3141 clocks = <&aoss_qmp>; 3028 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3029 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3030 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3031 qcom,skip-power-up;
3145 3032
3146 out-ports { 3033 out-ports {
3147 port { 3034 port {
3148 etm2_ 3035 etm2_out: endpoint {
3149 3036 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3037 };
3151 }; 3038 };
3152 }; 3039 };
3153 }; 3040 };
3154 3041
3155 etm@7340000 { 3042 etm@7340000 {
3156 compatible = "arm,cor 3043 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3044 reg = <0 0x07340000 0 0x1000>;
3158 3045
3159 cpu = <&CPU3>; 3046 cpu = <&CPU3>;
3160 3047
3161 clocks = <&aoss_qmp>; 3048 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3049 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3050 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3051 qcom,skip-power-up;
3165 3052
3166 out-ports { 3053 out-ports {
3167 port { 3054 port {
3168 etm3_ 3055 etm3_out: endpoint {
3169 3056 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3057 };
3171 }; 3058 };
3172 }; 3059 };
3173 }; 3060 };
3174 3061
3175 etm@7440000 { 3062 etm@7440000 {
3176 compatible = "arm,cor 3063 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3064 reg = <0 0x07440000 0 0x1000>;
3178 3065
3179 cpu = <&CPU4>; 3066 cpu = <&CPU4>;
3180 3067
3181 clocks = <&aoss_qmp>; 3068 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3069 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3070 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3071 qcom,skip-power-up;
3185 3072
3186 out-ports { 3073 out-ports {
3187 port { 3074 port {
3188 etm4_ 3075 etm4_out: endpoint {
3189 3076 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3077 };
3191 }; 3078 };
3192 }; 3079 };
3193 }; 3080 };
3194 3081
3195 etm@7540000 { 3082 etm@7540000 {
3196 compatible = "arm,cor 3083 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3084 reg = <0 0x07540000 0 0x1000>;
3198 3085
3199 cpu = <&CPU5>; 3086 cpu = <&CPU5>;
3200 3087
3201 clocks = <&aoss_qmp>; 3088 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3089 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3090 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3091 qcom,skip-power-up;
3205 3092
3206 out-ports { 3093 out-ports {
3207 port { 3094 port {
3208 etm5_ 3095 etm5_out: endpoint {
3209 3096 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3097 };
3211 }; 3098 };
3212 }; 3099 };
3213 }; 3100 };
3214 3101
3215 etm@7640000 { 3102 etm@7640000 {
3216 compatible = "arm,cor 3103 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3104 reg = <0 0x07640000 0 0x1000>;
3218 3105
3219 cpu = <&CPU6>; 3106 cpu = <&CPU6>;
3220 3107
3221 clocks = <&aoss_qmp>; 3108 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3109 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3110 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3111 qcom,skip-power-up;
3225 3112
3226 out-ports { 3113 out-ports {
3227 port { 3114 port {
3228 etm6_ 3115 etm6_out: endpoint {
3229 3116 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3117 };
3231 }; 3118 };
3232 }; 3119 };
3233 }; 3120 };
3234 3121
3235 etm@7740000 { 3122 etm@7740000 {
3236 compatible = "arm,cor 3123 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3124 reg = <0 0x07740000 0 0x1000>;
3238 3125
3239 cpu = <&CPU7>; 3126 cpu = <&CPU7>;
3240 3127
3241 clocks = <&aoss_qmp>; 3128 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3129 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3130 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3131 qcom,skip-power-up;
3245 3132
3246 out-ports { 3133 out-ports {
3247 port { 3134 port {
3248 etm7_ 3135 etm7_out: endpoint {
3249 3136 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3137 };
3251 }; 3138 };
3252 }; 3139 };
3253 }; 3140 };
3254 3141
3255 funnel@7800000 { /* APSS Funn 3142 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3143 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3144 reg = <0 0x07800000 0 0x1000>;
3258 3145
3259 clocks = <&aoss_qmp>; 3146 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3147 clock-names = "apb_pclk";
3261 3148
3262 out-ports { 3149 out-ports {
3263 port { 3150 port {
3264 apss_ 3151 apss_funnel_out: endpoint {
3265 3152 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3153 };
3267 }; 3154 };
3268 }; 3155 };
3269 3156
3270 in-ports { 3157 in-ports {
3271 #address-cell 3158 #address-cells = <1>;
3272 #size-cells = 3159 #size-cells = <0>;
3273 3160
3274 port@0 { 3161 port@0 {
3275 reg = 3162 reg = <0>;
3276 apss_ 3163 apss_funnel_in0: endpoint {
3277 3164 remote-endpoint = <&etm0_out>;
3278 }; 3165 };
3279 }; 3166 };
3280 3167
3281 port@1 { 3168 port@1 {
3282 reg = 3169 reg = <1>;
3283 apss_ 3170 apss_funnel_in1: endpoint {
3284 3171 remote-endpoint = <&etm1_out>;
3285 }; 3172 };
3286 }; 3173 };
3287 3174
3288 port@2 { 3175 port@2 {
3289 reg = 3176 reg = <2>;
3290 apss_ 3177 apss_funnel_in2: endpoint {
3291 3178 remote-endpoint = <&etm2_out>;
3292 }; 3179 };
3293 }; 3180 };
3294 3181
3295 port@3 { 3182 port@3 {
3296 reg = 3183 reg = <3>;
3297 apss_ 3184 apss_funnel_in3: endpoint {
3298 3185 remote-endpoint = <&etm3_out>;
3299 }; 3186 };
3300 }; 3187 };
3301 3188
3302 port@4 { 3189 port@4 {
3303 reg = 3190 reg = <4>;
3304 apss_ 3191 apss_funnel_in4: endpoint {
3305 3192 remote-endpoint = <&etm4_out>;
3306 }; 3193 };
3307 }; 3194 };
3308 3195
3309 port@5 { 3196 port@5 {
3310 reg = 3197 reg = <5>;
3311 apss_ 3198 apss_funnel_in5: endpoint {
3312 3199 remote-endpoint = <&etm5_out>;
3313 }; 3200 };
3314 }; 3201 };
3315 3202
3316 port@6 { 3203 port@6 {
3317 reg = 3204 reg = <6>;
3318 apss_ 3205 apss_funnel_in6: endpoint {
3319 3206 remote-endpoint = <&etm6_out>;
3320 }; 3207 };
3321 }; 3208 };
3322 3209
3323 port@7 { 3210 port@7 {
3324 reg = 3211 reg = <7>;
3325 apss_ 3212 apss_funnel_in7: endpoint {
3326 3213 remote-endpoint = <&etm7_out>;
3327 }; 3214 };
3328 }; 3215 };
3329 }; 3216 };
3330 }; 3217 };
3331 3218
3332 funnel@7810000 { 3219 funnel@7810000 {
3333 compatible = "arm,cor 3220 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3221 reg = <0 0x07810000 0 0x1000>;
3335 3222
3336 clocks = <&aoss_qmp>; 3223 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3224 clock-names = "apb_pclk";
3338 3225
3339 out-ports { 3226 out-ports {
3340 port { 3227 port {
3341 apss_ 3228 apss_merge_funnel_out: endpoint {
3342 3229 remote-endpoint = <&funnel2_in2>;
3343 }; 3230 };
3344 }; 3231 };
3345 }; 3232 };
3346 3233
3347 in-ports { 3234 in-ports {
3348 port { 3235 port {
3349 apss_ 3236 apss_merge_funnel_in: endpoint {
3350 3237 remote-endpoint = <&apss_funnel_out>;
3351 }; 3238 };
3352 }; 3239 };
3353 }; 3240 };
3354 }; 3241 };
3355 3242
3356 remoteproc_cdsp: remoteproc@8 3243 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3244 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3245 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3246
3360 interrupts-extended = 3247 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3248 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3249 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3250 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3251 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3252 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3253 "handover", "stop-ack";
3367 3254
3368 clocks = <&rpmhcc RPM 3255 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3256 clock-names = "xo";
3370 3257
3371 power-domains = <&rpm 3258 power-domains = <&rpmhpd SM8150_CX>;
3372 3259
3373 memory-region = <&cds 3260 memory-region = <&cdsp_mem>;
3374 3261
3375 qcom,qmp = <&aoss_qmp 3262 qcom,qmp = <&aoss_qmp>;
3376 3263
3377 qcom,smem-states = <& 3264 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3265 qcom,smem-state-names = "stop";
3379 3266
3380 status = "disabled"; 3267 status = "disabled";
3381 3268
3382 glink-edge { 3269 glink-edge {
3383 interrupts = 3270 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3271 label = "cdsp";
3385 qcom,remote-p 3272 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3273 mboxes = <&apss_shared 4>;
3387 3274
3388 fastrpc { 3275 fastrpc {
3389 compa 3276 compatible = "qcom,fastrpc";
3390 qcom, 3277 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3278 label = "cdsp";
3392 qcom, 3279 qcom,non-secure-domain;
3393 #addr 3280 #address-cells = <1>;
3394 #size 3281 #size-cells = <0>;
3395 3282
3396 compu 3283 compute-cb@1 {
3397 3284 compatible = "qcom,fastrpc-compute-cb";
3398 3285 reg = <1>;
3399 3286 iommus = <&apps_smmu 0x1001 0x0460>;
3400 }; 3287 };
3401 3288
3402 compu 3289 compute-cb@2 {
3403 3290 compatible = "qcom,fastrpc-compute-cb";
3404 3291 reg = <2>;
3405 3292 iommus = <&apps_smmu 0x1002 0x0460>;
3406 }; 3293 };
3407 3294
3408 compu 3295 compute-cb@3 {
3409 3296 compatible = "qcom,fastrpc-compute-cb";
3410 3297 reg = <3>;
3411 3298 iommus = <&apps_smmu 0x1003 0x0460>;
3412 }; 3299 };
3413 3300
3414 compu 3301 compute-cb@4 {
3415 3302 compatible = "qcom,fastrpc-compute-cb";
3416 3303 reg = <4>;
3417 3304 iommus = <&apps_smmu 0x1004 0x0460>;
3418 }; 3305 };
3419 3306
3420 compu 3307 compute-cb@5 {
3421 3308 compatible = "qcom,fastrpc-compute-cb";
3422 3309 reg = <5>;
3423 3310 iommus = <&apps_smmu 0x1005 0x0460>;
3424 }; 3311 };
3425 3312
3426 compu 3313 compute-cb@6 {
3427 3314 compatible = "qcom,fastrpc-compute-cb";
3428 3315 reg = <6>;
3429 3316 iommus = <&apps_smmu 0x1006 0x0460>;
3430 }; 3317 };
3431 3318
3432 compu 3319 compute-cb@7 {
3433 3320 compatible = "qcom,fastrpc-compute-cb";
3434 3321 reg = <7>;
3435 3322 iommus = <&apps_smmu 0x1007 0x0460>;
3436 }; 3323 };
3437 3324
3438 compu 3325 compute-cb@8 {
3439 3326 compatible = "qcom,fastrpc-compute-cb";
3440 3327 reg = <8>;
3441 3328 iommus = <&apps_smmu 0x1008 0x0460>;
3442 }; 3329 };
3443 3330
3444 /* no 3331 /* note: secure cb9 in downstream */
3445 }; 3332 };
3446 }; 3333 };
3447 }; 3334 };
3448 3335
3449 usb_1_hsphy: phy@88e2000 { 3336 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3337 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3338 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3339 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3340 status = "disabled";
3454 #phy-cells = <0>; 3341 #phy-cells = <0>;
3455 3342
3456 clocks = <&rpmhcc RPM 3343 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3344 clock-names = "ref";
3458 3345
3459 resets = <&gcc GCC_QU 3346 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3347 };
3461 3348
3462 usb_2_hsphy: phy@88e3000 { 3349 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3350 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3351 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3352 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3353 status = "disabled";
3467 #phy-cells = <0>; 3354 #phy-cells = <0>;
3468 3355
3469 clocks = <&rpmhcc RPM 3356 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3357 clock-names = "ref";
3471 3358
3472 resets = <&gcc GCC_QU 3359 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3360 };
3474 3361
3475 usb_1_qmpphy: phy@88e8000 { !! 3362 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 3363 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 3364 reg = <0 0x088e9000 0 0x18c>,
>> 3365 <0 0x088e8000 0 0x10>;
>> 3366 status = "disabled";
>> 3367 #address-cells = <2>;
>> 3368 #size-cells = <2>;
>> 3369 ranges;
3478 3370
3479 clocks = <&gcc GCC_US 3371 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3372 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3373 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3374 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3375 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3376
3488 resets = <&gcc GCC_US 3377 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3378 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3379 reset-names = "phy", "common";
3491 3380
3492 #clock-cells = <1>; !! 3381 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3382 reg = <0 0x088e9200 0 0x200>,
3494 !! 3383 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3384 <0 0x088e9c00 0 0x218>,
3496 !! 3385 <0 0x088e9600 0 0x200>,
3497 ports { !! 3386 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3387 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3388 #clock-cells = <0>;
3500 !! 3389 #phy-cells = <0>;
3501 port@0 { !! 3390 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3391 clock-names = "pipe0";
3503 !! 3392 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3393 };
3524 }; 3394 };
3525 3395
3526 usb_2_qmpphy: phy@88eb000 { 3396 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3397 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3398 reg = <0 0x088eb000 0 0x200>;
>> 3399 status = "disabled";
>> 3400 #address-cells = <2>;
>> 3401 #size-cells = <2>;
>> 3402 ranges;
3529 3403
3530 clocks = <&gcc GCC_US 3404 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3405 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3406 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3407 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3408 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 3409
3542 resets = <&gcc GCC_US !! 3410 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3543 <&gcc GCC_US !! 3411 <&gcc GCC_USB3_PHY_SEC_BCR>;
3544 reset-names = "phy", !! 3412 reset-names = "phy", "common";
3545 "phy_ph <<
3546 3413
3547 status = "disabled"; !! 3414 usb_2_ssphy: phy@88eb200 {
>> 3415 reg = <0 0x088eb200 0 0x200>,
>> 3416 <0 0x088eb400 0 0x200>,
>> 3417 <0 0x088eb800 0 0x800>,
>> 3418 <0 0x088eb600 0 0x200>;
>> 3419 #clock-cells = <0>;
>> 3420 #phy-cells = <0>;
>> 3421 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3422 clock-names = "pipe0";
>> 3423 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3424 };
3548 }; 3425 };
3549 3426
3550 sdhc_2: mmc@8804000 { 3427 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm 3428 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3429 reg = <0 0x08804000 0 0x1000>;
3553 3430
3554 interrupts = <GIC_SPI 3431 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3432 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3433 interrupt-names = "hc_irq", "pwr_irq";
3557 3434
3558 clocks = <&gcc GCC_SD 3435 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3436 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3437 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3438 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3439 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3440 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3441 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3442 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3443 operating-points-v2 = <&sdhc2_opp_table>;
3567 3444
3568 status = "disabled"; 3445 status = "disabled";
3569 3446
3570 sdhc2_opp_table: opp- 3447 sdhc2_opp_table: opp-table {
3571 compatible = 3448 compatible = "operating-points-v2";
3572 3449
3573 opp-19200000 3450 opp-19200000 {
3574 opp-h 3451 opp-hz = /bits/ 64 <19200000>;
3575 requi 3452 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3453 };
3577 3454
3578 opp-50000000 3455 opp-50000000 {
3579 opp-h 3456 opp-hz = /bits/ 64 <50000000>;
3580 requi 3457 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3458 };
3582 3459
3583 opp-100000000 3460 opp-100000000 {
3584 opp-h 3461 opp-hz = /bits/ 64 <100000000>;
3585 requi 3462 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3463 };
3587 3464
3588 opp-202000000 3465 opp-202000000 {
3589 opp-h 3466 opp-hz = /bits/ 64 <202000000>;
3590 requi 3467 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3468 };
3592 }; 3469 };
3593 }; 3470 };
3594 3471
3595 dc_noc: interconnect@9160000 3472 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3473 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3474 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3475 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3476 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3477 };
3601 3478
3602 gem_noc: interconnect@9680000 3479 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3480 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3481 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3482 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3483 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3484 };
3608 3485
3609 usb_1: usb@a6f8800 { 3486 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3487 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3488 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3489 status = "disabled";
3613 #address-cells = <2>; 3490 #address-cells = <2>;
3614 #size-cells = <2>; 3491 #size-cells = <2>;
3615 ranges; 3492 ranges;
3616 dma-ranges; 3493 dma-ranges;
3617 3494
3618 clocks = <&gcc GCC_CF 3495 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3496 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3497 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3498 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3499 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3500 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3501 clock-names = "cfg_noc",
3625 "core", 3502 "core",
3626 "iface" 3503 "iface",
3627 "sleep" 3504 "sleep",
3628 "mock_u 3505 "mock_utmi",
3629 "xo"; 3506 "xo";
3630 3507
3631 assigned-clocks = <&g 3508 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3509 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3510 assigned-clock-rates = <19200000>, <200000000>;
3634 3511
3635 interrupts-extended = !! 3512 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3513 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3514 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 3515 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 3516 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3517 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3518
3646 power-domains = <&gcc 3519 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3520
3648 resets = <&gcc GCC_US 3521 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3522
3650 interconnects = <&agg <<
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 3523 usb_1_dwc3: usb@a600000 {
3655 compatible = 3524 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3525 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3526 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3527 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3528 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3529 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3530 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3531 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3532 };
3684 }; 3533 };
3685 3534
3686 usb_2: usb@a8f8800 { 3535 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3536 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3537 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3538 status = "disabled";
3690 #address-cells = <2>; 3539 #address-cells = <2>;
3691 #size-cells = <2>; 3540 #size-cells = <2>;
3692 ranges; 3541 ranges;
3693 dma-ranges; 3542 dma-ranges;
3694 3543
3695 clocks = <&gcc GCC_CF 3544 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3545 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3546 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3547 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3548 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3549 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3550 clock-names = "cfg_noc",
3702 "core", 3551 "core",
3703 "iface" 3552 "iface",
3704 "sleep" 3553 "sleep",
3705 "mock_u 3554 "mock_utmi",
3706 "xo"; 3555 "xo";
3707 3556
3708 assigned-clocks = <&g 3557 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3558 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3559 assigned-clock-rates = <19200000>, <200000000>;
3711 3560
3712 interrupts-extended = !! 3561 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3562 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3563 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 3564 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 3565 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3566 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3567
3723 power-domains = <&gcc 3568 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3569
3725 resets = <&gcc GCC_US 3570 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3571
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3572 usb_2_dwc3: usb@a800000 {
3732 compatible = 3573 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3574 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3575 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3576 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3577 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3578 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3579 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3580 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3581 };
3741 }; 3582 };
3742 3583
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3584 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3585 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3586 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3587 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3588 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3589 };
3762 3590
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 3591 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm 3592 compatible = "qcom,sm8150-mdss";
3777 reg = <0 0x0ae00000 0 3593 reg = <0 0x0ae00000 0 0x1000>;
3778 reg-names = "mdss"; 3594 reg-names = "mdss";
3779 3595
3780 interconnects = <&mms !! 3596 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3781 <&mms !! 3597 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3782 interconnect-names = 3598 interconnect-names = "mdp0-mem", "mdp1-mem";
3783 3599
3784 power-domains = <&dis 3600 power-domains = <&dispcc MDSS_GDSC>;
3785 3601
3786 clocks = <&dispcc DIS 3602 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 <&gcc GCC_DI 3603 <&gcc GCC_DISP_HF_AXI_CLK>,
3788 <&gcc GCC_DI 3604 <&gcc GCC_DISP_SF_AXI_CLK>,
3789 <&dispcc DIS 3605 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3790 clock-names = "iface" 3606 clock-names = "iface", "bus", "nrt_bus", "core";
3791 3607
3792 interrupts = <GIC_SPI 3608 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller; 3609 interrupt-controller;
3794 #interrupt-cells = <1 3610 #interrupt-cells = <1>;
3795 3611
3796 iommus = <&apps_smmu 3612 iommus = <&apps_smmu 0x800 0x420>;
3797 3613
3798 status = "disabled"; 3614 status = "disabled";
3799 3615
3800 #address-cells = <2>; 3616 #address-cells = <2>;
3801 #size-cells = <2>; 3617 #size-cells = <2>;
3802 ranges; 3618 ranges;
3803 3619
3804 mdss_mdp: display-con 3620 mdss_mdp: display-controller@ae01000 {
3805 compatible = 3621 compatible = "qcom,sm8150-dpu";
3806 reg = <0 0x0a 3622 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0a 3623 <0 0x0aeb0000 0 0x2008>;
3808 reg-names = " 3624 reg-names = "mdp", "vbif";
3809 3625
3810 clocks = <&di 3626 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3811 <&gc 3627 <&gcc GCC_DISP_HF_AXI_CLK>,
3812 <&di 3628 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3813 <&di 3629 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3814 clock-names = 3630 clock-names = "iface", "bus", "core", "vsync";
3815 3631
3816 assigned-cloc 3632 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-cloc 3633 assigned-clock-rates = <19200000>;
3818 3634
3819 operating-poi 3635 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains 3636 power-domains = <&rpmhpd SM8150_MMCX>;
3821 3637
3822 interrupt-par 3638 interrupt-parent = <&mdss>;
3823 interrupts = 3639 interrupts = <0>;
3824 3640
3825 ports { 3641 ports {
3826 #addr 3642 #address-cells = <1>;
3827 #size 3643 #size-cells = <0>;
3828 3644
3829 port@ 3645 port@0 {
3830 3646 reg = <0>;
3831 3647 dpu_intf1_out: endpoint {
3832 3648 remote-endpoint = <&mdss_dsi0_in>;
3833 3649 };
3834 }; 3650 };
3835 3651
3836 port@ 3652 port@1 {
3837 3653 reg = <1>;
3838 3654 dpu_intf2_out: endpoint {
3839 3655 remote-endpoint = <&mdss_dsi1_in>;
3840 3656 };
3841 }; 3657 };
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; 3658 };
3850 3659
3851 mdp_opp_table 3660 mdp_opp_table: opp-table {
3852 compa 3661 compatible = "operating-points-v2";
3853 3662
3854 opp-1 3663 opp-171428571 {
3855 3664 opp-hz = /bits/ 64 <171428571>;
3856 3665 required-opps = <&rpmhpd_opp_low_svs>;
3857 }; 3666 };
3858 3667
3859 opp-3 3668 opp-300000000 {
3860 3669 opp-hz = /bits/ 64 <300000000>;
3861 3670 required-opps = <&rpmhpd_opp_svs>;
3862 }; 3671 };
3863 3672
3864 opp-3 3673 opp-345000000 {
3865 3674 opp-hz = /bits/ 64 <345000000>;
3866 3675 required-opps = <&rpmhpd_opp_svs_l1>;
3867 }; 3676 };
3868 3677
3869 opp-4 3678 opp-460000000 {
3870 3679 opp-hz = /bits/ 64 <460000000>;
3871 3680 required-opps = <&rpmhpd_opp_nom>;
3872 }; 3681 };
3873 }; 3682 };
3874 }; 3683 };
3875 3684
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 3685 mdss_dsi0: dsi@ae94000 {
3958 compatible = 3686 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg = <0 0x0a 3687 reg = <0 0x0ae94000 0 0x400>;
3960 reg-names = " 3688 reg-names = "dsi_ctrl";
3961 3689
3962 interrupt-par 3690 interrupt-parent = <&mdss>;
3963 interrupts = 3691 interrupts = <4>;
3964 3692
3965 clocks = <&di 3693 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3966 <&di 3694 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3967 <&di 3695 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3968 <&di 3696 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3969 <&di 3697 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3970 <&gc 3698 <&gcc GCC_DISP_HF_AXI_CLK>;
3971 clock-names = 3699 clock-names = "byte",
3972 3700 "byte_intf",
3973 3701 "pixel",
3974 3702 "core",
3975 3703 "iface",
3976 3704 "bus";
3977 3705
3978 assigned-cloc 3706 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3979 3707 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3980 assigned-cloc 3708 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3981 3709 <&mdss_dsi0_phy 1>;
3982 3710
3983 operating-poi 3711 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains 3712 power-domains = <&rpmhpd SM8150_MMCX>;
3985 3713
3986 phys = <&mdss 3714 phys = <&mdss_dsi0_phy>;
3987 3715
3988 status = "dis 3716 status = "disabled";
3989 3717
3990 #address-cell 3718 #address-cells = <1>;
3991 #size-cells = 3719 #size-cells = <0>;
3992 3720
3993 ports { 3721 ports {
3994 #addr 3722 #address-cells = <1>;
3995 #size 3723 #size-cells = <0>;
3996 3724
3997 port@ 3725 port@0 {
3998 3726 reg = <0>;
3999 3727 mdss_dsi0_in: endpoint {
4000 3728 remote-endpoint = <&dpu_intf1_out>;
4001 3729 };
4002 }; 3730 };
4003 3731
4004 port@ 3732 port@1 {
4005 3733 reg = <1>;
4006 3734 mdss_dsi0_out: endpoint {
4007 3735 };
4008 }; 3736 };
4009 }; 3737 };
4010 3738
4011 dsi_opp_table 3739 dsi_opp_table: opp-table {
4012 compa 3740 compatible = "operating-points-v2";
4013 3741
4014 opp-1 3742 opp-187500000 {
4015 3743 opp-hz = /bits/ 64 <187500000>;
4016 3744 required-opps = <&rpmhpd_opp_low_svs>;
4017 }; 3745 };
4018 3746
4019 opp-3 3747 opp-300000000 {
4020 3748 opp-hz = /bits/ 64 <300000000>;
4021 3749 required-opps = <&rpmhpd_opp_svs>;
4022 }; 3750 };
4023 3751
4024 opp-3 3752 opp-358000000 {
4025 3753 opp-hz = /bits/ 64 <358000000>;
4026 3754 required-opps = <&rpmhpd_opp_svs_l1>;
4027 }; 3755 };
4028 }; 3756 };
4029 }; 3757 };
4030 3758
4031 mdss_dsi0_phy: phy@ae 3759 mdss_dsi0_phy: phy@ae94400 {
4032 compatible = !! 3760 compatible = "qcom,dsi-phy-7nm";
4033 reg = <0 0x0a 3761 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0a 3762 <0 0x0ae94600 0 0x280>,
4035 <0 0x0a 3763 <0 0x0ae94900 0 0x260>;
4036 reg-names = " 3764 reg-names = "dsi_phy",
4037 " 3765 "dsi_phy_lane",
4038 " 3766 "dsi_pll";
4039 3767
4040 #clock-cells 3768 #clock-cells = <1>;
4041 #phy-cells = 3769 #phy-cells = <0>;
4042 3770
4043 clocks = <&di 3771 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4044 <&rp 3772 <&rpmhcc RPMH_CXO_CLK>;
4045 clock-names = 3773 clock-names = "iface", "ref";
4046 3774
4047 status = "dis 3775 status = "disabled";
4048 }; 3776 };
4049 3777
4050 mdss_dsi1: dsi@ae9600 3778 mdss_dsi1: dsi@ae96000 {
4051 compatible = 3779 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4052 reg = <0 0x0a 3780 reg = <0 0x0ae96000 0 0x400>;
4053 reg-names = " 3781 reg-names = "dsi_ctrl";
4054 3782
4055 interrupt-par 3783 interrupt-parent = <&mdss>;
4056 interrupts = 3784 interrupts = <5>;
4057 3785
4058 clocks = <&di 3786 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4059 <&di 3787 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4060 <&di 3788 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4061 <&di 3789 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4062 <&di 3790 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4063 <&gc 3791 <&gcc GCC_DISP_HF_AXI_CLK>;
4064 clock-names = 3792 clock-names = "byte",
4065 3793 "byte_intf",
4066 3794 "pixel",
4067 3795 "core",
4068 3796 "iface",
4069 3797 "bus";
4070 3798
4071 assigned-cloc 3799 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4072 3800 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4073 assigned-cloc 3801 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4074 3802 <&mdss_dsi1_phy 1>;
4075 3803
4076 operating-poi 3804 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains 3805 power-domains = <&rpmhpd SM8150_MMCX>;
4078 3806
4079 phys = <&mdss 3807 phys = <&mdss_dsi1_phy>;
4080 3808
4081 status = "dis 3809 status = "disabled";
4082 3810
4083 #address-cell 3811 #address-cells = <1>;
4084 #size-cells = 3812 #size-cells = <0>;
4085 3813
4086 ports { 3814 ports {
4087 #addr 3815 #address-cells = <1>;
4088 #size 3816 #size-cells = <0>;
4089 3817
4090 port@ 3818 port@0 {
4091 3819 reg = <0>;
4092 3820 mdss_dsi1_in: endpoint {
4093 3821 remote-endpoint = <&dpu_intf2_out>;
4094 3822 };
4095 }; 3823 };
4096 3824
4097 port@ 3825 port@1 {
4098 3826 reg = <1>;
4099 3827 mdss_dsi1_out: endpoint {
4100 3828 };
4101 }; 3829 };
4102 }; 3830 };
4103 }; 3831 };
4104 3832
4105 mdss_dsi1_phy: phy@ae 3833 mdss_dsi1_phy: phy@ae96400 {
4106 compatible = !! 3834 compatible = "qcom,dsi-phy-7nm";
4107 reg = <0 0x0a 3835 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0a 3836 <0 0x0ae96600 0 0x280>,
4109 <0 0x0a 3837 <0 0x0ae96900 0 0x260>;
4110 reg-names = " 3838 reg-names = "dsi_phy",
4111 " 3839 "dsi_phy_lane",
4112 " 3840 "dsi_pll";
4113 3841
4114 #clock-cells 3842 #clock-cells = <1>;
4115 #phy-cells = 3843 #phy-cells = <0>;
4116 3844
4117 clocks = <&di 3845 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4118 <&rp 3846 <&rpmhcc RPMH_CXO_CLK>;
4119 clock-names = 3847 clock-names = "iface", "ref";
4120 3848
4121 status = "dis 3849 status = "disabled";
4122 }; 3850 };
4123 }; 3851 };
4124 3852
4125 dispcc: clock-controller@af00 3853 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm 3854 compatible = "qcom,sm8150-dispcc";
4127 reg = <0 0x0af00000 0 3855 reg = <0 0x0af00000 0 0x10000>;
4128 clocks = <&rpmhcc RPM 3856 clocks = <&rpmhcc RPMH_CXO_CLK>,
4129 <&mdss_dsi0_ 3857 <&mdss_dsi0_phy 0>,
4130 <&mdss_dsi0_ 3858 <&mdss_dsi0_phy 1>,
4131 <&mdss_dsi1_ 3859 <&mdss_dsi1_phy 0>,
4132 <&mdss_dsi1_ 3860 <&mdss_dsi1_phy 1>,
4133 <&usb_1_qmpp !! 3861 <0>,
4134 <&usb_1_qmpp !! 3862 <0>;
4135 clock-names = "bi_tcx 3863 clock-names = "bi_tcxo",
4136 "dsi0_p 3864 "dsi0_phy_pll_out_byteclk",
4137 "dsi0_p 3865 "dsi0_phy_pll_out_dsiclk",
4138 "dsi1_p 3866 "dsi1_phy_pll_out_byteclk",
4139 "dsi1_p 3867 "dsi1_phy_pll_out_dsiclk",
4140 "dp_phy 3868 "dp_phy_pll_link_clk",
4141 "dp_phy 3869 "dp_phy_pll_vco_div_clk";
4142 power-domains = <&rpm 3870 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; 3871 #clock-cells = <1>;
4145 #reset-cells = <1>; 3872 #reset-cells = <1>;
4146 #power-domain-cells = 3873 #power-domain-cells = <1>;
4147 }; 3874 };
4148 3875
4149 pdc: interrupt-controller@b22 3876 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 3877 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 !! 3878 reg = <0 0x0b220000 0 0x400>;
4152 qcom,pdc-ranges = <0 3879 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 3880 <125 63 1>;
4154 #interrupt-cells = <2 3881 #interrupt-cells = <2>;
4155 interrupt-parent = <& 3882 interrupt-parent = <&intc>;
4156 interrupt-controller; 3883 interrupt-controller;
4157 }; 3884 };
4158 3885
4159 aoss_qmp: power-management@c3 3886 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm 3887 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 3888 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 3889 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3890 mboxes = <&apss_shared 0>;
4164 3891
4165 #clock-cells = <0>; 3892 #clock-cells = <0>;
4166 }; 3893 };
4167 3894
4168 sram@c3f0000 { 3895 sram@c3f0000 {
4169 compatible = "qcom,rp 3896 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 3897 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 3898 };
4172 3899
4173 tsens0: thermal-sensor@c26300 3900 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3901 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3902 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3903 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3904 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3905 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3906 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3907 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3908 #thermal-sensor-cells = <1>;
4182 }; 3909 };
4183 3910
4184 tsens1: thermal-sensor@c26500 3911 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3912 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3913 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3914 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3915 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3916 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3917 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3918 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3919 #thermal-sensor-cells = <1>;
4193 }; 3920 };
4194 3921
4195 spmi_bus: spmi@c440000 { 3922 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3923 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3924 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3925 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3926 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3927 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3928 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3929 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3930 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3931 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3932 qcom,ee = <0>;
4206 qcom,channel = <0>; 3933 qcom,channel = <0>;
4207 #address-cells = <2>; 3934 #address-cells = <2>;
4208 #size-cells = <0>; 3935 #size-cells = <0>;
4209 interrupt-controller; 3936 interrupt-controller;
4210 #interrupt-cells = <4 3937 #interrupt-cells = <4>;
>> 3938 cell-index = <0>;
4211 }; 3939 };
4212 3940
4213 apps_smmu: iommu@15000000 { 3941 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3942 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3943 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3944 #iommu-cells = <2>;
4217 #global-interrupts = 3945 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3947 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3948 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3949 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3950 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3951 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3952 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 3953 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 3954 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 3955 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 3956 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 3957 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 3958 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 3959 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 3960 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 3961 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 3962 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 3963 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 3964 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 3965 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 3966 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 3967 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 3968 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 3969 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 3970 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 3971 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 3972 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 3973 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 3974 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 3975 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 3976 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 3977 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 3978 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 3979 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 3980 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 3981 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 3982 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 3983 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 3984 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 3985 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 3986 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 3987 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 3988 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 3989 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 3990 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 3991 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 3992 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 3993 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 3994 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 3995 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 3996 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 3997 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 3998 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 3999 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 4000 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 4001 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 4002 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 4003 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 4004 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 4005 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 4006 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 4007 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 4008 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 4009 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 4010 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 4011 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 4012 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 4013 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 4014 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 4015 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 4016 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 4017 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 4018 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 4019 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 4020 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 4021 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 4022 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 4023 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 4024 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 4025 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 4026 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 4027 };
4300 4028
4301 remoteproc_adsp: remoteproc@1 4029 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 4030 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 4031 reg = <0x0 0x17300000 0x0 0x4040>;
4304 4032
4305 interrupts-extended = 4033 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 4034 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 4035 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 4036 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 4037 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 4038 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 4039 "handover", "stop-ack";
4312 4040
4313 clocks = <&rpmhcc RPM 4041 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 4042 clock-names = "xo";
4315 4043
4316 power-domains = <&rpm 4044 power-domains = <&rpmhpd SM8150_CX>;
4317 4045
4318 memory-region = <&ads 4046 memory-region = <&adsp_mem>;
4319 4047
4320 qcom,qmp = <&aoss_qmp 4048 qcom,qmp = <&aoss_qmp>;
4321 4049
4322 qcom,smem-states = <& 4050 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 4051 qcom,smem-state-names = "stop";
4324 4052
4325 status = "disabled"; 4053 status = "disabled";
4326 4054
4327 glink-edge { 4055 glink-edge {
4328 interrupts = 4056 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 4057 label = "lpass";
4330 qcom,remote-p 4058 qcom,remote-pid = <2>;
4331 mboxes = <&ap 4059 mboxes = <&apss_shared 8>;
4332 4060
4333 fastrpc { 4061 fastrpc {
4334 compa 4062 compatible = "qcom,fastrpc";
4335 qcom, 4063 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 4064 label = "adsp";
4337 qcom, 4065 qcom,non-secure-domain;
4338 #addr 4066 #address-cells = <1>;
4339 #size 4067 #size-cells = <0>;
4340 4068
4341 compu 4069 compute-cb@3 {
4342 4070 compatible = "qcom,fastrpc-compute-cb";
4343 4071 reg = <3>;
4344 4072 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 4073 };
4346 4074
4347 compu 4075 compute-cb@4 {
4348 4076 compatible = "qcom,fastrpc-compute-cb";
4349 4077 reg = <4>;
4350 4078 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 4079 };
4352 4080
4353 compu 4081 compute-cb@5 {
4354 4082 compatible = "qcom,fastrpc-compute-cb";
4355 4083 reg = <5>;
4356 4084 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 4085 };
4358 }; 4086 };
4359 }; 4087 };
4360 }; 4088 };
4361 4089
4362 intc: interrupt-controller@17 4090 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 4091 compatible = "arm,gic-v3";
4364 interrupt-controller; 4092 interrupt-controller;
4365 #interrupt-cells = <3 4093 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 4094 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 4095 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 4096 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 4097 };
4370 4098
4371 apss_shared: mailbox@17c00000 4099 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm !! 4100 compatible = "qcom,sm8150-apss-shared";
4373 "qcom,sd <<
4374 reg = <0x0 0x17c00000 4101 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 4102 #mbox-cells = <1>;
4376 }; 4103 };
4377 4104
4378 watchdog@17c10000 { 4105 watchdog@17c10000 {
4379 compatible = "qcom,ap 4106 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 4107 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 4108 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 4109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 4110 };
4384 4111
4385 timer@17c20000 { 4112 timer@17c20000 {
4386 #address-cells = <1>; 4113 #address-cells = <1>;
4387 #size-cells = <1>; 4114 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 4115 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 4116 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 4117 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 4118 clock-frequency = <19200000>;
4392 4119
4393 frame@17c21000 { 4120 frame@17c21000 {
4394 frame-number 4121 frame-number = <0>;
4395 interrupts = 4122 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 4123 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 4124 reg = <0x17c21000 0x1000>,
4398 <0x17c2 4125 <0x17c22000 0x1000>;
4399 }; 4126 };
4400 4127
4401 frame@17c23000 { 4128 frame@17c23000 {
4402 frame-number 4129 frame-number = <1>;
4403 interrupts = 4130 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 4131 reg = <0x17c23000 0x1000>;
4405 status = "dis 4132 status = "disabled";
4406 }; 4133 };
4407 4134
4408 frame@17c25000 { 4135 frame@17c25000 {
4409 frame-number 4136 frame-number = <2>;
4410 interrupts = 4137 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 4138 reg = <0x17c25000 0x1000>;
4412 status = "dis 4139 status = "disabled";
4413 }; 4140 };
4414 4141
4415 frame@17c27000 { 4142 frame@17c27000 {
4416 frame-number 4143 frame-number = <3>;
4417 interrupts = 4144 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 4145 reg = <0x17c26000 0x1000>;
4419 status = "dis 4146 status = "disabled";
4420 }; 4147 };
4421 4148
4422 frame@17c29000 { 4149 frame@17c29000 {
4423 frame-number 4150 frame-number = <4>;
4424 interrupts = 4151 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 4152 reg = <0x17c29000 0x1000>;
4426 status = "dis 4153 status = "disabled";
4427 }; 4154 };
4428 4155
4429 frame@17c2b000 { 4156 frame@17c2b000 {
4430 frame-number 4157 frame-number = <5>;
4431 interrupts = 4158 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 4159 reg = <0x17c2b000 0x1000>;
4433 status = "dis 4160 status = "disabled";
4434 }; 4161 };
4435 4162
4436 frame@17c2d000 { 4163 frame@17c2d000 {
4437 frame-number 4164 frame-number = <6>;
4438 interrupts = 4165 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 4166 reg = <0x17c2d000 0x1000>;
4440 status = "dis 4167 status = "disabled";
4441 }; 4168 };
4442 }; 4169 };
4443 4170
4444 apps_rsc: rsc@18200000 { 4171 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 4172 label = "apps_rsc";
4446 compatible = "qcom,rp 4173 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 4174 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 4175 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 4176 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 4177 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 4178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 4180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 4181 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 4182 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 4183 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 4184 <SLEEP_TCS 3>,
4458 <WA 4185 <WAKE_TCS 3>,
4459 <CO 4186 <CONTROL_TCS 1>;
4460 power-domains = <&CLU 4187 power-domains = <&CLUSTER_PD>;
4461 4188
4462 rpmhcc: clock-control 4189 rpmhcc: clock-controller {
4463 compatible = 4190 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 4191 #clock-cells = <1>;
4465 clock-names = 4192 clock-names = "xo";
4466 clocks = <&xo 4193 clocks = <&xo_board>;
4467 }; 4194 };
4468 4195
4469 rpmhpd: power-control 4196 rpmhpd: power-controller {
4470 compatible = 4197 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 4198 #power-domain-cells = <1>;
4472 operating-poi 4199 operating-points-v2 = <&rpmhpd_opp_table>;
4473 4200
4474 rpmhpd_opp_ta 4201 rpmhpd_opp_table: opp-table {
4475 compa 4202 compatible = "operating-points-v2";
4476 4203
4477 rpmhp 4204 rpmhpd_opp_ret: opp1 {
4478 4205 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 4206 };
4480 4207
4481 rpmhp 4208 rpmhpd_opp_min_svs: opp2 {
4482 4209 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 4210 };
4484 4211
4485 rpmhp 4212 rpmhpd_opp_low_svs: opp3 {
4486 4213 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 4214 };
4488 4215
4489 rpmhp 4216 rpmhpd_opp_svs: opp4 {
4490 4217 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 4218 };
4492 4219
4493 rpmhp 4220 rpmhpd_opp_svs_l1: opp5 {
4494 4221 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 4222 };
4496 4223
4497 rpmhp 4224 rpmhpd_opp_svs_l2: opp6 {
4498 4225 opp-level = <224>;
4499 }; 4226 };
4500 4227
4501 rpmhp 4228 rpmhpd_opp_nom: opp7 {
4502 4229 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 4230 };
4504 4231
4505 rpmhp 4232 rpmhpd_opp_nom_l1: opp8 {
4506 4233 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 4234 };
4508 4235
4509 rpmhp 4236 rpmhpd_opp_nom_l2: opp9 {
4510 4237 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 4238 };
4512 4239
4513 rpmhp 4240 rpmhpd_opp_turbo: opp10 {
4514 4241 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 4242 };
4516 4243
4517 rpmhp 4244 rpmhpd_opp_turbo_l1: opp11 {
4518 4245 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 4246 };
4520 }; 4247 };
4521 }; 4248 };
4522 4249
4523 apps_bcm_voter: bcm-v 4250 apps_bcm_voter: bcm-voter {
4524 compatible = 4251 compatible = "qcom,bcm-voter";
4525 }; 4252 };
4526 }; 4253 };
4527 4254
4528 osm_l3: interconnect@18321000 4255 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm 4256 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 4257 reg = <0 0x18321000 0 0x1400>;
4531 4258
4532 clocks = <&rpmhcc RPM 4259 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 4260 clock-names = "xo", "alternate";
4534 4261
4535 #interconnect-cells = 4262 #interconnect-cells = <1>;
4536 }; 4263 };
4537 4264
4538 cpufreq_hw: cpufreq@18323000 4265 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm !! 4266 compatible = "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 4267 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 4268 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 4269 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 4270 "freq-domain2";
4544 4271
4545 clocks = <&rpmhcc RPM 4272 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 4273 clock-names = "xo", "alternate";
4547 4274
4548 #freq-domain-cells = 4275 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; <<
4550 }; 4276 };
4551 4277
4552 lmh_cluster1: lmh@18350800 { 4278 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 4279 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 4280 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 4281 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 4282 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 4283 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 4284 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 4285 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 4286 interrupt-controller;
4561 #interrupt-cells = <1 4287 #interrupt-cells = <1>;
4562 }; 4288 };
4563 4289
4564 lmh_cluster0: lmh@18358800 { 4290 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 4291 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 4292 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 4293 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4294 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4295 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4296 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4297 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4298 interrupt-controller;
4573 #interrupt-cells = <1 4299 #interrupt-cells = <1>;
4574 }; 4300 };
4575 4301
4576 wifi: wifi@18800000 { 4302 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4303 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4304 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4305 reg-names = "membase";
4580 memory-region = <&wla 4306 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4307 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4308 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4309 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4310 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4311 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4312 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4313 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4314 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4315 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4316 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4317 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4318 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4319 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4320 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4321 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4322 status = "disabled";
4597 }; 4323 };
4598 }; 4324 };
4599 4325
4600 timer { 4326 timer {
4601 compatible = "arm,armv8-timer 4327 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4328 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4329 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4330 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4331 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4332 };
4607 4333
4608 thermal-zones { 4334 thermal-zones {
4609 cpu0-thermal { 4335 cpu0-thermal {
4610 polling-delay-passive 4336 polling-delay-passive = <250>;
>> 4337 polling-delay = <1000>;
4611 4338
4612 thermal-sensors = <&t 4339 thermal-sensors = <&tsens0 1>;
4613 4340
4614 trips { 4341 trips {
4615 cpu0_alert0: 4342 cpu0_alert0: trip-point0 {
4616 tempe 4343 temperature = <90000>;
4617 hyste 4344 hysteresis = <2000>;
4618 type 4345 type = "passive";
4619 }; 4346 };
4620 4347
4621 cpu0_alert1: 4348 cpu0_alert1: trip-point1 {
4622 tempe 4349 temperature = <95000>;
4623 hyste 4350 hysteresis = <2000>;
4624 type 4351 type = "passive";
4625 }; 4352 };
4626 4353
4627 cpu0_crit: cp 4354 cpu0_crit: cpu-crit {
4628 tempe 4355 temperature = <110000>;
4629 hyste 4356 hysteresis = <1000>;
4630 type 4357 type = "critical";
4631 }; 4358 };
4632 }; 4359 };
4633 4360
4634 cooling-maps { 4361 cooling-maps {
4635 map0 { 4362 map0 {
4636 trip 4363 trip = <&cpu0_alert0>;
4637 cooli 4364 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4365 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4366 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4367 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4368 };
4642 map1 { 4369 map1 {
4643 trip 4370 trip = <&cpu0_alert1>;
4644 cooli 4371 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4372 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4373 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4374 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4375 };
4649 }; 4376 };
4650 }; 4377 };
4651 4378
4652 cpu1-thermal { 4379 cpu1-thermal {
4653 polling-delay-passive 4380 polling-delay-passive = <250>;
>> 4381 polling-delay = <1000>;
4654 4382
4655 thermal-sensors = <&t 4383 thermal-sensors = <&tsens0 2>;
4656 4384
4657 trips { 4385 trips {
4658 cpu1_alert0: 4386 cpu1_alert0: trip-point0 {
4659 tempe 4387 temperature = <90000>;
4660 hyste 4388 hysteresis = <2000>;
4661 type 4389 type = "passive";
4662 }; 4390 };
4663 4391
4664 cpu1_alert1: 4392 cpu1_alert1: trip-point1 {
4665 tempe 4393 temperature = <95000>;
4666 hyste 4394 hysteresis = <2000>;
4667 type 4395 type = "passive";
4668 }; 4396 };
4669 4397
4670 cpu1_crit: cp 4398 cpu1_crit: cpu-crit {
4671 tempe 4399 temperature = <110000>;
4672 hyste 4400 hysteresis = <1000>;
4673 type 4401 type = "critical";
4674 }; 4402 };
4675 }; 4403 };
4676 4404
4677 cooling-maps { 4405 cooling-maps {
4678 map0 { 4406 map0 {
4679 trip 4407 trip = <&cpu1_alert0>;
4680 cooli 4408 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4409 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4410 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4411 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4412 };
4685 map1 { 4413 map1 {
4686 trip 4414 trip = <&cpu1_alert1>;
4687 cooli 4415 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4416 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4417 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4418 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4419 };
4692 }; 4420 };
4693 }; 4421 };
4694 4422
4695 cpu2-thermal { 4423 cpu2-thermal {
4696 polling-delay-passive 4424 polling-delay-passive = <250>;
>> 4425 polling-delay = <1000>;
4697 4426
4698 thermal-sensors = <&t 4427 thermal-sensors = <&tsens0 3>;
4699 4428
4700 trips { 4429 trips {
4701 cpu2_alert0: 4430 cpu2_alert0: trip-point0 {
4702 tempe 4431 temperature = <90000>;
4703 hyste 4432 hysteresis = <2000>;
4704 type 4433 type = "passive";
4705 }; 4434 };
4706 4435
4707 cpu2_alert1: 4436 cpu2_alert1: trip-point1 {
4708 tempe 4437 temperature = <95000>;
4709 hyste 4438 hysteresis = <2000>;
4710 type 4439 type = "passive";
4711 }; 4440 };
4712 4441
4713 cpu2_crit: cp 4442 cpu2_crit: cpu-crit {
4714 tempe 4443 temperature = <110000>;
4715 hyste 4444 hysteresis = <1000>;
4716 type 4445 type = "critical";
4717 }; 4446 };
4718 }; 4447 };
4719 4448
4720 cooling-maps { 4449 cooling-maps {
4721 map0 { 4450 map0 {
4722 trip 4451 trip = <&cpu2_alert0>;
4723 cooli 4452 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4453 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4454 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4455 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4456 };
4728 map1 { 4457 map1 {
4729 trip 4458 trip = <&cpu2_alert1>;
4730 cooli 4459 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4460 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4461 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4462 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4463 };
4735 }; 4464 };
4736 }; 4465 };
4737 4466
4738 cpu3-thermal { 4467 cpu3-thermal {
4739 polling-delay-passive 4468 polling-delay-passive = <250>;
>> 4469 polling-delay = <1000>;
4740 4470
4741 thermal-sensors = <&t 4471 thermal-sensors = <&tsens0 4>;
4742 4472
4743 trips { 4473 trips {
4744 cpu3_alert0: 4474 cpu3_alert0: trip-point0 {
4745 tempe 4475 temperature = <90000>;
4746 hyste 4476 hysteresis = <2000>;
4747 type 4477 type = "passive";
4748 }; 4478 };
4749 4479
4750 cpu3_alert1: 4480 cpu3_alert1: trip-point1 {
4751 tempe 4481 temperature = <95000>;
4752 hyste 4482 hysteresis = <2000>;
4753 type 4483 type = "passive";
4754 }; 4484 };
4755 4485
4756 cpu3_crit: cp 4486 cpu3_crit: cpu-crit {
4757 tempe 4487 temperature = <110000>;
4758 hyste 4488 hysteresis = <1000>;
4759 type 4489 type = "critical";
4760 }; 4490 };
4761 }; 4491 };
4762 4492
4763 cooling-maps { 4493 cooling-maps {
4764 map0 { 4494 map0 {
4765 trip 4495 trip = <&cpu3_alert0>;
4766 cooli 4496 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4497 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4498 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4499 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4500 };
4771 map1 { 4501 map1 {
4772 trip 4502 trip = <&cpu3_alert1>;
4773 cooli 4503 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4504 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4505 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4506 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4507 };
4778 }; 4508 };
4779 }; 4509 };
4780 4510
4781 cpu4-top-thermal { 4511 cpu4-top-thermal {
4782 polling-delay-passive 4512 polling-delay-passive = <250>;
>> 4513 polling-delay = <1000>;
4783 4514
4784 thermal-sensors = <&t 4515 thermal-sensors = <&tsens0 7>;
4785 4516
4786 trips { 4517 trips {
4787 cpu4_top_aler 4518 cpu4_top_alert0: trip-point0 {
4788 tempe 4519 temperature = <90000>;
4789 hyste 4520 hysteresis = <2000>;
4790 type 4521 type = "passive";
4791 }; 4522 };
4792 4523
4793 cpu4_top_aler 4524 cpu4_top_alert1: trip-point1 {
4794 tempe 4525 temperature = <95000>;
4795 hyste 4526 hysteresis = <2000>;
4796 type 4527 type = "passive";
4797 }; 4528 };
4798 4529
4799 cpu4_top_crit 4530 cpu4_top_crit: cpu-crit {
4800 tempe 4531 temperature = <110000>;
4801 hyste 4532 hysteresis = <1000>;
4802 type 4533 type = "critical";
4803 }; 4534 };
4804 }; 4535 };
4805 4536
4806 cooling-maps { 4537 cooling-maps {
4807 map0 { 4538 map0 {
4808 trip 4539 trip = <&cpu4_top_alert0>;
4809 cooli 4540 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4541 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4542 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4543 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4544 };
4814 map1 { 4545 map1 {
4815 trip 4546 trip = <&cpu4_top_alert1>;
4816 cooli 4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4551 };
4821 }; 4552 };
4822 }; 4553 };
4823 4554
4824 cpu5-top-thermal { 4555 cpu5-top-thermal {
4825 polling-delay-passive 4556 polling-delay-passive = <250>;
>> 4557 polling-delay = <1000>;
4826 4558
4827 thermal-sensors = <&t 4559 thermal-sensors = <&tsens0 8>;
4828 4560
4829 trips { 4561 trips {
4830 cpu5_top_aler 4562 cpu5_top_alert0: trip-point0 {
4831 tempe 4563 temperature = <90000>;
4832 hyste 4564 hysteresis = <2000>;
4833 type 4565 type = "passive";
4834 }; 4566 };
4835 4567
4836 cpu5_top_aler 4568 cpu5_top_alert1: trip-point1 {
4837 tempe 4569 temperature = <95000>;
4838 hyste 4570 hysteresis = <2000>;
4839 type 4571 type = "passive";
4840 }; 4572 };
4841 4573
4842 cpu5_top_crit 4574 cpu5_top_crit: cpu-crit {
4843 tempe 4575 temperature = <110000>;
4844 hyste 4576 hysteresis = <1000>;
4845 type 4577 type = "critical";
4846 }; 4578 };
4847 }; 4579 };
4848 4580
4849 cooling-maps { 4581 cooling-maps {
4850 map0 { 4582 map0 {
4851 trip 4583 trip = <&cpu5_top_alert0>;
4852 cooli 4584 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4585 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4586 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4587 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4588 };
4857 map1 { 4589 map1 {
4858 trip 4590 trip = <&cpu5_top_alert1>;
4859 cooli 4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4595 };
4864 }; 4596 };
4865 }; 4597 };
4866 4598
4867 cpu6-top-thermal { 4599 cpu6-top-thermal {
4868 polling-delay-passive 4600 polling-delay-passive = <250>;
>> 4601 polling-delay = <1000>;
4869 4602
4870 thermal-sensors = <&t 4603 thermal-sensors = <&tsens0 9>;
4871 4604
4872 trips { 4605 trips {
4873 cpu6_top_aler 4606 cpu6_top_alert0: trip-point0 {
4874 tempe 4607 temperature = <90000>;
4875 hyste 4608 hysteresis = <2000>;
4876 type 4609 type = "passive";
4877 }; 4610 };
4878 4611
4879 cpu6_top_aler 4612 cpu6_top_alert1: trip-point1 {
4880 tempe 4613 temperature = <95000>;
4881 hyste 4614 hysteresis = <2000>;
4882 type 4615 type = "passive";
4883 }; 4616 };
4884 4617
4885 cpu6_top_crit 4618 cpu6_top_crit: cpu-crit {
4886 tempe 4619 temperature = <110000>;
4887 hyste 4620 hysteresis = <1000>;
4888 type 4621 type = "critical";
4889 }; 4622 };
4890 }; 4623 };
4891 4624
4892 cooling-maps { 4625 cooling-maps {
4893 map0 { 4626 map0 {
4894 trip 4627 trip = <&cpu6_top_alert0>;
4895 cooli 4628 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4629 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4630 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4631 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4632 };
4900 map1 { 4633 map1 {
4901 trip 4634 trip = <&cpu6_top_alert1>;
4902 cooli 4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4639 };
4907 }; 4640 };
4908 }; 4641 };
4909 4642
4910 cpu7-top-thermal { 4643 cpu7-top-thermal {
4911 polling-delay-passive 4644 polling-delay-passive = <250>;
>> 4645 polling-delay = <1000>;
4912 4646
4913 thermal-sensors = <&t 4647 thermal-sensors = <&tsens0 10>;
4914 4648
4915 trips { 4649 trips {
4916 cpu7_top_aler 4650 cpu7_top_alert0: trip-point0 {
4917 tempe 4651 temperature = <90000>;
4918 hyste 4652 hysteresis = <2000>;
4919 type 4653 type = "passive";
4920 }; 4654 };
4921 4655
4922 cpu7_top_aler 4656 cpu7_top_alert1: trip-point1 {
4923 tempe 4657 temperature = <95000>;
4924 hyste 4658 hysteresis = <2000>;
4925 type 4659 type = "passive";
4926 }; 4660 };
4927 4661
4928 cpu7_top_crit 4662 cpu7_top_crit: cpu-crit {
4929 tempe 4663 temperature = <110000>;
4930 hyste 4664 hysteresis = <1000>;
4931 type 4665 type = "critical";
4932 }; 4666 };
4933 }; 4667 };
4934 4668
4935 cooling-maps { 4669 cooling-maps {
4936 map0 { 4670 map0 {
4937 trip 4671 trip = <&cpu7_top_alert0>;
4938 cooli 4672 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4673 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4674 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4675 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4676 };
4943 map1 { 4677 map1 {
4944 trip 4678 trip = <&cpu7_top_alert1>;
4945 cooli 4679 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4680 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4681 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4682 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4683 };
4950 }; 4684 };
4951 }; 4685 };
4952 4686
4953 cpu4-bottom-thermal { 4687 cpu4-bottom-thermal {
4954 polling-delay-passive 4688 polling-delay-passive = <250>;
>> 4689 polling-delay = <1000>;
4955 4690
4956 thermal-sensors = <&t 4691 thermal-sensors = <&tsens0 11>;
4957 4692
4958 trips { 4693 trips {
4959 cpu4_bottom_a 4694 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4695 temperature = <90000>;
4961 hyste 4696 hysteresis = <2000>;
4962 type 4697 type = "passive";
4963 }; 4698 };
4964 4699
4965 cpu4_bottom_a 4700 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4701 temperature = <95000>;
4967 hyste 4702 hysteresis = <2000>;
4968 type 4703 type = "passive";
4969 }; 4704 };
4970 4705
4971 cpu4_bottom_c 4706 cpu4_bottom_crit: cpu-crit {
4972 tempe 4707 temperature = <110000>;
4973 hyste 4708 hysteresis = <1000>;
4974 type 4709 type = "critical";
4975 }; 4710 };
4976 }; 4711 };
4977 4712
4978 cooling-maps { 4713 cooling-maps {
4979 map0 { 4714 map0 {
4980 trip 4715 trip = <&cpu4_bottom_alert0>;
4981 cooli 4716 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4717 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4718 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4719 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4720 };
4986 map1 { 4721 map1 {
4987 trip 4722 trip = <&cpu4_bottom_alert1>;
4988 cooli 4723 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4724 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4725 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4726 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4727 };
4993 }; 4728 };
4994 }; 4729 };
4995 4730
4996 cpu5-bottom-thermal { 4731 cpu5-bottom-thermal {
4997 polling-delay-passive 4732 polling-delay-passive = <250>;
>> 4733 polling-delay = <1000>;
4998 4734
4999 thermal-sensors = <&t 4735 thermal-sensors = <&tsens0 12>;
5000 4736
5001 trips { 4737 trips {
5002 cpu5_bottom_a 4738 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4739 temperature = <90000>;
5004 hyste 4740 hysteresis = <2000>;
5005 type 4741 type = "passive";
5006 }; 4742 };
5007 4743
5008 cpu5_bottom_a 4744 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4745 temperature = <95000>;
5010 hyste 4746 hysteresis = <2000>;
5011 type 4747 type = "passive";
5012 }; 4748 };
5013 4749
5014 cpu5_bottom_c 4750 cpu5_bottom_crit: cpu-crit {
5015 tempe 4751 temperature = <110000>;
5016 hyste 4752 hysteresis = <1000>;
5017 type 4753 type = "critical";
5018 }; 4754 };
5019 }; 4755 };
5020 4756
5021 cooling-maps { 4757 cooling-maps {
5022 map0 { 4758 map0 {
5023 trip 4759 trip = <&cpu5_bottom_alert0>;
5024 cooli 4760 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4761 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4762 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4763 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4764 };
5029 map1 { 4765 map1 {
5030 trip 4766 trip = <&cpu5_bottom_alert1>;
5031 cooli 4767 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4768 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4769 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4770 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4771 };
5036 }; 4772 };
5037 }; 4773 };
5038 4774
5039 cpu6-bottom-thermal { 4775 cpu6-bottom-thermal {
5040 polling-delay-passive 4776 polling-delay-passive = <250>;
>> 4777 polling-delay = <1000>;
5041 4778
5042 thermal-sensors = <&t 4779 thermal-sensors = <&tsens0 13>;
5043 4780
5044 trips { 4781 trips {
5045 cpu6_bottom_a 4782 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4783 temperature = <90000>;
5047 hyste 4784 hysteresis = <2000>;
5048 type 4785 type = "passive";
5049 }; 4786 };
5050 4787
5051 cpu6_bottom_a 4788 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4789 temperature = <95000>;
5053 hyste 4790 hysteresis = <2000>;
5054 type 4791 type = "passive";
5055 }; 4792 };
5056 4793
5057 cpu6_bottom_c 4794 cpu6_bottom_crit: cpu-crit {
5058 tempe 4795 temperature = <110000>;
5059 hyste 4796 hysteresis = <1000>;
5060 type 4797 type = "critical";
5061 }; 4798 };
5062 }; 4799 };
5063 4800
5064 cooling-maps { 4801 cooling-maps {
5065 map0 { 4802 map0 {
5066 trip 4803 trip = <&cpu6_bottom_alert0>;
5067 cooli 4804 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4806 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4807 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4808 };
5072 map1 { 4809 map1 {
5073 trip 4810 trip = <&cpu6_bottom_alert1>;
5074 cooli 4811 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4812 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4813 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4815 };
5079 }; 4816 };
5080 }; 4817 };
5081 4818
5082 cpu7-bottom-thermal { 4819 cpu7-bottom-thermal {
5083 polling-delay-passive 4820 polling-delay-passive = <250>;
>> 4821 polling-delay = <1000>;
5084 4822
5085 thermal-sensors = <&t 4823 thermal-sensors = <&tsens0 14>;
5086 4824
5087 trips { 4825 trips {
5088 cpu7_bottom_a 4826 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4827 temperature = <90000>;
5090 hyste 4828 hysteresis = <2000>;
5091 type 4829 type = "passive";
5092 }; 4830 };
5093 4831
5094 cpu7_bottom_a 4832 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4833 temperature = <95000>;
5096 hyste 4834 hysteresis = <2000>;
5097 type 4835 type = "passive";
5098 }; 4836 };
5099 4837
5100 cpu7_bottom_c 4838 cpu7_bottom_crit: cpu-crit {
5101 tempe 4839 temperature = <110000>;
5102 hyste 4840 hysteresis = <1000>;
5103 type 4841 type = "critical";
5104 }; 4842 };
5105 }; 4843 };
5106 4844
5107 cooling-maps { 4845 cooling-maps {
5108 map0 { 4846 map0 {
5109 trip 4847 trip = <&cpu7_bottom_alert0>;
5110 cooli 4848 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4849 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4850 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4851 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4852 };
5115 map1 { 4853 map1 {
5116 trip 4854 trip = <&cpu7_bottom_alert1>;
5117 cooli 4855 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4856 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4857 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4858 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4859 };
5122 }; 4860 };
5123 }; 4861 };
5124 4862
5125 aoss0-thermal { 4863 aoss0-thermal {
5126 polling-delay-passive 4864 polling-delay-passive = <250>;
>> 4865 polling-delay = <1000>;
5127 4866
5128 thermal-sensors = <&t 4867 thermal-sensors = <&tsens0 0>;
5129 4868
5130 trips { 4869 trips {
5131 aoss0_alert0: 4870 aoss0_alert0: trip-point0 {
5132 tempe 4871 temperature = <90000>;
5133 hyste 4872 hysteresis = <2000>;
5134 type 4873 type = "hot";
5135 }; 4874 };
5136 }; 4875 };
5137 }; 4876 };
5138 4877
5139 cluster0-thermal { 4878 cluster0-thermal {
5140 polling-delay-passive 4879 polling-delay-passive = <250>;
>> 4880 polling-delay = <1000>;
5141 4881
5142 thermal-sensors = <&t 4882 thermal-sensors = <&tsens0 5>;
5143 4883
5144 trips { 4884 trips {
5145 cluster0_aler 4885 cluster0_alert0: trip-point0 {
5146 tempe 4886 temperature = <90000>;
5147 hyste 4887 hysteresis = <2000>;
5148 type 4888 type = "hot";
5149 }; 4889 };
5150 cluster0_crit !! 4890 cluster0_crit: cluster0_crit {
5151 tempe 4891 temperature = <110000>;
5152 hyste 4892 hysteresis = <2000>;
5153 type 4893 type = "critical";
5154 }; 4894 };
5155 }; 4895 };
5156 }; 4896 };
5157 4897
5158 cluster1-thermal { 4898 cluster1-thermal {
5159 polling-delay-passive 4899 polling-delay-passive = <250>;
>> 4900 polling-delay = <1000>;
5160 4901
5161 thermal-sensors = <&t 4902 thermal-sensors = <&tsens0 6>;
5162 4903
5163 trips { 4904 trips {
5164 cluster1_aler 4905 cluster1_alert0: trip-point0 {
5165 tempe 4906 temperature = <90000>;
5166 hyste 4907 hysteresis = <2000>;
5167 type 4908 type = "hot";
5168 }; 4909 };
5169 cluster1_crit !! 4910 cluster1_crit: cluster1_crit {
5170 tempe 4911 temperature = <110000>;
5171 hyste 4912 hysteresis = <2000>;
5172 type 4913 type = "critical";
5173 }; 4914 };
5174 }; 4915 };
5175 }; 4916 };
5176 4917
5177 gpu-top-thermal { 4918 gpu-top-thermal {
5178 polling-delay-passive 4919 polling-delay-passive = <250>;
>> 4920 polling-delay = <1000>;
5179 4921
5180 thermal-sensors = <&t 4922 thermal-sensors = <&tsens0 15>;
5181 4923
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4924 trips {
5190 gpu_top_alert !! 4925 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4926 temperature = <90000>;
5198 hyste !! 4927 hysteresis = <2000>;
5199 type 4928 type = "hot";
5200 }; 4929 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4930 };
5208 }; 4931 };
5209 4932
5210 aoss1-thermal { 4933 aoss1-thermal {
5211 polling-delay-passive 4934 polling-delay-passive = <250>;
>> 4935 polling-delay = <1000>;
5212 4936
5213 thermal-sensors = <&t 4937 thermal-sensors = <&tsens1 0>;
5214 4938
5215 trips { 4939 trips {
5216 aoss1_alert0: 4940 aoss1_alert0: trip-point0 {
5217 tempe 4941 temperature = <90000>;
5218 hyste 4942 hysteresis = <2000>;
5219 type 4943 type = "hot";
5220 }; 4944 };
5221 }; 4945 };
5222 }; 4946 };
5223 4947
5224 wlan-thermal { 4948 wlan-thermal {
5225 polling-delay-passive 4949 polling-delay-passive = <250>;
>> 4950 polling-delay = <1000>;
5226 4951
5227 thermal-sensors = <&t 4952 thermal-sensors = <&tsens1 1>;
5228 4953
5229 trips { 4954 trips {
5230 wlan_alert0: 4955 wlan_alert0: trip-point0 {
5231 tempe 4956 temperature = <90000>;
5232 hyste 4957 hysteresis = <2000>;
5233 type 4958 type = "hot";
5234 }; 4959 };
5235 }; 4960 };
5236 }; 4961 };
5237 4962
5238 video-thermal { 4963 video-thermal {
5239 polling-delay-passive 4964 polling-delay-passive = <250>;
>> 4965 polling-delay = <1000>;
5240 4966
5241 thermal-sensors = <&t 4967 thermal-sensors = <&tsens1 2>;
5242 4968
5243 trips { 4969 trips {
5244 video_alert0: 4970 video_alert0: trip-point0 {
5245 tempe 4971 temperature = <90000>;
5246 hyste 4972 hysteresis = <2000>;
5247 type 4973 type = "hot";
5248 }; 4974 };
5249 }; 4975 };
5250 }; 4976 };
5251 4977
5252 mem-thermal { 4978 mem-thermal {
5253 polling-delay-passive 4979 polling-delay-passive = <250>;
>> 4980 polling-delay = <1000>;
5254 4981
5255 thermal-sensors = <&t 4982 thermal-sensors = <&tsens1 3>;
5256 4983
5257 trips { 4984 trips {
5258 mem_alert0: t 4985 mem_alert0: trip-point0 {
5259 tempe 4986 temperature = <90000>;
5260 hyste 4987 hysteresis = <2000>;
5261 type 4988 type = "hot";
5262 }; 4989 };
5263 }; 4990 };
5264 }; 4991 };
5265 4992
5266 q6-hvx-thermal { 4993 q6-hvx-thermal {
5267 polling-delay-passive 4994 polling-delay-passive = <250>;
>> 4995 polling-delay = <1000>;
5268 4996
5269 thermal-sensors = <&t 4997 thermal-sensors = <&tsens1 4>;
5270 4998
5271 trips { 4999 trips {
5272 q6_hvx_alert0 5000 q6_hvx_alert0: trip-point0 {
5273 tempe 5001 temperature = <90000>;
5274 hyste 5002 hysteresis = <2000>;
5275 type 5003 type = "hot";
5276 }; 5004 };
5277 }; 5005 };
5278 }; 5006 };
5279 5007
5280 camera-thermal { 5008 camera-thermal {
5281 polling-delay-passive 5009 polling-delay-passive = <250>;
>> 5010 polling-delay = <1000>;
5282 5011
5283 thermal-sensors = <&t 5012 thermal-sensors = <&tsens1 5>;
5284 5013
5285 trips { 5014 trips {
5286 camera_alert0 5015 camera_alert0: trip-point0 {
5287 tempe 5016 temperature = <90000>;
5288 hyste 5017 hysteresis = <2000>;
5289 type 5018 type = "hot";
5290 }; 5019 };
5291 }; 5020 };
5292 }; 5021 };
5293 5022
5294 compute-thermal { 5023 compute-thermal {
5295 polling-delay-passive 5024 polling-delay-passive = <250>;
>> 5025 polling-delay = <1000>;
5296 5026
5297 thermal-sensors = <&t 5027 thermal-sensors = <&tsens1 6>;
5298 5028
5299 trips { 5029 trips {
5300 compute_alert 5030 compute_alert0: trip-point0 {
5301 tempe 5031 temperature = <90000>;
5302 hyste 5032 hysteresis = <2000>;
5303 type 5033 type = "hot";
5304 }; 5034 };
5305 }; 5035 };
5306 }; 5036 };
5307 5037
5308 modem-thermal { 5038 modem-thermal {
5309 polling-delay-passive 5039 polling-delay-passive = <250>;
>> 5040 polling-delay = <1000>;
5310 5041
5311 thermal-sensors = <&t 5042 thermal-sensors = <&tsens1 7>;
5312 5043
5313 trips { 5044 trips {
5314 modem_alert0: 5045 modem_alert0: trip-point0 {
5315 tempe 5046 temperature = <90000>;
5316 hyste 5047 hysteresis = <2000>;
5317 type 5048 type = "hot";
5318 }; 5049 };
5319 }; 5050 };
5320 }; 5051 };
5321 5052
5322 npu-thermal { 5053 npu-thermal {
5323 polling-delay-passive 5054 polling-delay-passive = <250>;
>> 5055 polling-delay = <1000>;
5324 5056
5325 thermal-sensors = <&t 5057 thermal-sensors = <&tsens1 8>;
5326 5058
5327 trips { 5059 trips {
5328 npu_alert0: t 5060 npu_alert0: trip-point0 {
5329 tempe 5061 temperature = <90000>;
5330 hyste 5062 hysteresis = <2000>;
5331 type 5063 type = "hot";
5332 }; 5064 };
5333 }; 5065 };
5334 }; 5066 };
5335 5067
5336 modem-vec-thermal { 5068 modem-vec-thermal {
5337 polling-delay-passive 5069 polling-delay-passive = <250>;
>> 5070 polling-delay = <1000>;
5338 5071
5339 thermal-sensors = <&t 5072 thermal-sensors = <&tsens1 9>;
5340 5073
5341 trips { 5074 trips {
5342 modem_vec_ale 5075 modem_vec_alert0: trip-point0 {
5343 tempe 5076 temperature = <90000>;
5344 hyste 5077 hysteresis = <2000>;
5345 type 5078 type = "hot";
5346 }; 5079 };
5347 }; 5080 };
5348 }; 5081 };
5349 5082
5350 modem-scl-thermal { 5083 modem-scl-thermal {
5351 polling-delay-passive 5084 polling-delay-passive = <250>;
>> 5085 polling-delay = <1000>;
5352 5086
5353 thermal-sensors = <&t 5087 thermal-sensors = <&tsens1 10>;
5354 5088
5355 trips { 5089 trips {
5356 modem_scl_ale 5090 modem_scl_alert0: trip-point0 {
5357 tempe 5091 temperature = <90000>;
5358 hyste 5092 hysteresis = <2000>;
5359 type 5093 type = "hot";
5360 }; 5094 };
5361 }; 5095 };
5362 }; 5096 };
5363 5097
5364 gpu-bottom-thermal { 5098 gpu-bottom-thermal {
5365 polling-delay-passive 5099 polling-delay-passive = <250>;
>> 5100 polling-delay = <1000>;
5366 5101
5367 thermal-sensors = <&t 5102 thermal-sensors = <&tsens1 11>;
5368 5103
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 5104 trips {
5377 gpu_bottom_al !! 5105 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 5106 temperature = <90000>;
5385 hyste !! 5107 hysteresis = <2000>;
5386 type 5108 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 5109 };
5394 }; 5110 };
5395 }; 5111 };
5396 }; 5112 };
5397 }; 5113 };
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