1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
11 #include <dt-bindings/power/qcom-rpmpd.h> 9 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 12 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 16 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 17 #include <dt-bindings/thermal/thermal.h>
22 18
23 / { 19 / {
24 interrupt-parent = <&intc>; 20 interrupt-parent = <&intc>;
25 21
26 #address-cells = <2>; 22 #address-cells = <2>;
27 #size-cells = <2>; 23 #size-cells = <2>;
28 24
29 chosen { }; 25 chosen { };
30 26
31 clocks { 27 clocks {
32 xo_board: xo-board { 28 xo_board: xo-board {
33 compatible = "fixed-cl 29 compatible = "fixed-clock";
34 #clock-cells = <0>; 30 #clock-cells = <0>;
35 clock-frequency = <384 31 clock-frequency = <38400000>;
36 clock-output-names = " 32 clock-output-names = "xo_board";
37 }; 33 };
38 34
39 sleep_clk: sleep-clk { 35 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 36 compatible = "fixed-clock";
41 #clock-cells = <0>; 37 #clock-cells = <0>;
42 clock-frequency = <327 38 clock-frequency = <32764>;
43 clock-output-names = " 39 clock-output-names = "sleep_clk";
44 }; 40 };
45 }; 41 };
46 42
47 cpus { 43 cpus {
48 #address-cells = <2>; 44 #address-cells = <2>;
49 #size-cells = <0>; 45 #size-cells = <0>;
50 46
51 CPU0: cpu@0 { 47 CPU0: cpu@0 {
52 device_type = "cpu"; 48 device_type = "cpu";
53 compatible = "qcom,kry 49 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 50 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 51 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci" 52 enable-method = "psci";
57 capacity-dmips-mhz = < 53 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 54 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 55 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 56 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 57 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ !! 58 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
63 <&osm_ 59 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 60 power-domains = <&CPU_PD0>;
65 power-domain-names = " 61 power-domain-names = "psci";
66 #cooling-cells = <2>; 62 #cooling-cells = <2>;
67 L2_0: l2-cache { 63 L2_0: l2-cache {
68 compatible = " 64 compatible = "cache";
69 cache-level = 65 cache-level = <2>;
70 cache-unified; 66 cache-unified;
71 next-level-cac 67 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 68 L3_0: l3-cache {
73 compat 69 compatible = "cache";
74 cache- 70 cache-level = <3>;
75 cache- 71 cache-unified;
76 }; 72 };
77 }; 73 };
78 }; 74 };
79 75
80 CPU1: cpu@100 { 76 CPU1: cpu@100 {
81 device_type = "cpu"; 77 device_type = "cpu";
82 compatible = "qcom,kry 78 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 79 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 80 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci" 81 enable-method = "psci";
86 capacity-dmips-mhz = < 82 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 83 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 84 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 85 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 86 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ !! 87 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
92 <&osm_ 88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 89 power-domains = <&CPU_PD1>;
94 power-domain-names = " 90 power-domain-names = "psci";
95 #cooling-cells = <2>; 91 #cooling-cells = <2>;
96 L2_100: l2-cache { 92 L2_100: l2-cache {
97 compatible = " 93 compatible = "cache";
98 cache-level = 94 cache-level = <2>;
99 cache-unified; 95 cache-unified;
100 next-level-cac 96 next-level-cache = <&L3_0>;
101 }; 97 };
102 }; 98 };
103 99
104 CPU2: cpu@200 { 100 CPU2: cpu@200 {
105 device_type = "cpu"; 101 device_type = "cpu";
106 compatible = "qcom,kry 102 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 103 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw 104 clocks = <&cpufreq_hw 0>;
109 enable-method = "psci" 105 enable-method = "psci";
110 capacity-dmips-mhz = < 106 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 107 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 108 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 109 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 110 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ !! 111 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
116 <&osm_ 112 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 113 power-domains = <&CPU_PD2>;
118 power-domain-names = " 114 power-domain-names = "psci";
119 #cooling-cells = <2>; 115 #cooling-cells = <2>;
120 L2_200: l2-cache { 116 L2_200: l2-cache {
121 compatible = " 117 compatible = "cache";
122 cache-level = 118 cache-level = <2>;
123 cache-unified; 119 cache-unified;
124 next-level-cac 120 next-level-cache = <&L3_0>;
125 }; 121 };
126 }; 122 };
127 123
128 CPU3: cpu@300 { 124 CPU3: cpu@300 {
129 device_type = "cpu"; 125 device_type = "cpu";
130 compatible = "qcom,kry 126 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 127 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 128 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci" 129 enable-method = "psci";
134 capacity-dmips-mhz = < 130 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 131 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 132 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 133 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 134 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ !! 135 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
140 <&osm_ 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 137 power-domains = <&CPU_PD3>;
142 power-domain-names = " 138 power-domain-names = "psci";
143 #cooling-cells = <2>; 139 #cooling-cells = <2>;
144 L2_300: l2-cache { 140 L2_300: l2-cache {
145 compatible = " 141 compatible = "cache";
146 cache-level = 142 cache-level = <2>;
147 cache-unified; 143 cache-unified;
148 next-level-cac 144 next-level-cache = <&L3_0>;
149 }; 145 };
150 }; 146 };
151 147
152 CPU4: cpu@400 { 148 CPU4: cpu@400 {
153 device_type = "cpu"; 149 device_type = "cpu";
154 compatible = "qcom,kry 150 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 151 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw 152 clocks = <&cpufreq_hw 1>;
157 enable-method = "psci" 153 enable-method = "psci";
158 capacity-dmips-mhz = < 154 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 155 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 156 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 157 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 158 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ !! 159 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
164 <&osm_ 160 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 161 power-domains = <&CPU_PD4>;
166 power-domain-names = " 162 power-domain-names = "psci";
167 #cooling-cells = <2>; 163 #cooling-cells = <2>;
168 L2_400: l2-cache { 164 L2_400: l2-cache {
169 compatible = " 165 compatible = "cache";
170 cache-level = 166 cache-level = <2>;
171 cache-unified; 167 cache-unified;
172 next-level-cac 168 next-level-cache = <&L3_0>;
173 }; 169 };
174 }; 170 };
175 171
176 CPU5: cpu@500 { 172 CPU5: cpu@500 {
177 device_type = "cpu"; 173 device_type = "cpu";
178 compatible = "qcom,kry 174 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 175 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw 176 clocks = <&cpufreq_hw 1>;
181 enable-method = "psci" 177 enable-method = "psci";
182 capacity-dmips-mhz = < 178 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 179 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 180 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 181 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 182 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ !! 183 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
188 <&osm_ 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 185 power-domains = <&CPU_PD5>;
190 power-domain-names = " 186 power-domain-names = "psci";
191 #cooling-cells = <2>; 187 #cooling-cells = <2>;
192 L2_500: l2-cache { 188 L2_500: l2-cache {
193 compatible = " 189 compatible = "cache";
194 cache-level = 190 cache-level = <2>;
195 cache-unified; 191 cache-unified;
196 next-level-cac 192 next-level-cache = <&L3_0>;
197 }; 193 };
198 }; 194 };
199 195
200 CPU6: cpu@600 { 196 CPU6: cpu@600 {
201 device_type = "cpu"; 197 device_type = "cpu";
202 compatible = "qcom,kry 198 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 199 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw 200 clocks = <&cpufreq_hw 1>;
205 enable-method = "psci" 201 enable-method = "psci";
206 capacity-dmips-mhz = < 202 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 203 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 204 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 205 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 206 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ !! 207 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
212 <&osm_ 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 209 power-domains = <&CPU_PD6>;
214 power-domain-names = " 210 power-domain-names = "psci";
215 #cooling-cells = <2>; 211 #cooling-cells = <2>;
216 L2_600: l2-cache { 212 L2_600: l2-cache {
217 compatible = " 213 compatible = "cache";
218 cache-level = 214 cache-level = <2>;
219 cache-unified; 215 cache-unified;
220 next-level-cac 216 next-level-cache = <&L3_0>;
221 }; 217 };
222 }; 218 };
223 219
224 CPU7: cpu@700 { 220 CPU7: cpu@700 {
225 device_type = "cpu"; 221 device_type = "cpu";
226 compatible = "qcom,kry 222 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 223 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw 224 clocks = <&cpufreq_hw 2>;
229 enable-method = "psci" 225 enable-method = "psci";
230 capacity-dmips-mhz = < 226 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 227 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 228 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 229 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 230 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ !! 231 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
236 <&osm_ 232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 233 power-domains = <&CPU_PD7>;
238 power-domain-names = " 234 power-domain-names = "psci";
239 #cooling-cells = <2>; 235 #cooling-cells = <2>;
240 L2_700: l2-cache { 236 L2_700: l2-cache {
241 compatible = " 237 compatible = "cache";
242 cache-level = 238 cache-level = <2>;
243 cache-unified; 239 cache-unified;
244 next-level-cac 240 next-level-cache = <&L3_0>;
245 }; 241 };
246 }; 242 };
247 243
248 cpu-map { 244 cpu-map {
249 cluster0 { 245 cluster0 {
250 core0 { 246 core0 {
251 cpu = 247 cpu = <&CPU0>;
252 }; 248 };
253 249
254 core1 { 250 core1 {
255 cpu = 251 cpu = <&CPU1>;
256 }; 252 };
257 253
258 core2 { 254 core2 {
259 cpu = 255 cpu = <&CPU2>;
260 }; 256 };
261 257
262 core3 { 258 core3 {
263 cpu = 259 cpu = <&CPU3>;
264 }; 260 };
265 261
266 core4 { 262 core4 {
267 cpu = 263 cpu = <&CPU4>;
268 }; 264 };
269 265
270 core5 { 266 core5 {
271 cpu = 267 cpu = <&CPU5>;
272 }; 268 };
273 269
274 core6 { 270 core6 {
275 cpu = 271 cpu = <&CPU6>;
276 }; 272 };
277 273
278 core7 { 274 core7 {
279 cpu = 275 cpu = <&CPU7>;
280 }; 276 };
281 }; 277 };
282 }; 278 };
283 279
284 idle-states { 280 idle-states {
285 entry-method = "psci"; 281 entry-method = "psci";
286 282
287 LITTLE_CPU_SLEEP_0: cp 283 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 284 compatible = "arm,idle-state";
289 idle-state-nam 285 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 286 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 287 entry-latency-us = <355>;
292 exit-latency-u 288 exit-latency-us = <909>;
293 min-residency- 289 min-residency-us = <3934>;
294 local-timer-st 290 local-timer-stop;
295 }; 291 };
296 292
297 BIG_CPU_SLEEP_0: cpu-s 293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 294 compatible = "arm,idle-state";
299 idle-state-nam 295 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 296 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 297 entry-latency-us = <241>;
302 exit-latency-u 298 exit-latency-us = <1461>;
303 min-residency- 299 min-residency-us = <4488>;
304 local-timer-st 300 local-timer-stop;
305 }; 301 };
306 }; 302 };
307 303
308 domain-idle-states { 304 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 305 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 306 compatible = "domain-idle-state";
311 arm,psci-suspe 307 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 308 entry-latency-us = <3263>;
313 exit-latency-u 309 exit-latency-us = <6562>;
314 min-residency- 310 min-residency-us = <9987>;
315 }; 311 };
316 }; 312 };
317 }; 313 };
318 314
319 cpu0_opp_table: opp-table-cpu0 { 315 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points 316 compatible = "operating-points-v2";
321 opp-shared; 317 opp-shared;
322 318
323 cpu0_opp1: opp-300000000 { 319 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 320 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 321 opp-peak-kBps = <800000 9600000>;
326 }; 322 };
327 323
328 cpu0_opp2: opp-403200000 { 324 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 325 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 326 opp-peak-kBps = <800000 9600000>;
331 }; 327 };
332 328
333 cpu0_opp3: opp-499200000 { 329 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 330 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 331 opp-peak-kBps = <800000 12902400>;
336 }; 332 };
337 333
338 cpu0_opp4: opp-576000000 { 334 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 335 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 336 opp-peak-kBps = <800000 12902400>;
341 }; 337 };
342 338
343 cpu0_opp5: opp-672000000 { 339 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 340 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 341 opp-peak-kBps = <800000 15974400>;
346 }; 342 };
347 343
348 cpu0_opp6: opp-768000000 { 344 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 345 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 346 opp-peak-kBps = <1804000 19660800>;
351 }; 347 };
352 348
353 cpu0_opp7: opp-844800000 { 349 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 350 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 351 opp-peak-kBps = <1804000 19660800>;
356 }; 352 };
357 353
358 cpu0_opp8: opp-940800000 { 354 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 355 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 356 opp-peak-kBps = <1804000 22732800>;
361 }; 357 };
362 358
363 cpu0_opp9: opp-1036800000 { 359 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 360 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 361 opp-peak-kBps = <1804000 22732800>;
366 }; 362 };
367 363
368 cpu0_opp10: opp-1113600000 { 364 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 365 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 366 opp-peak-kBps = <2188000 25804800>;
371 }; 367 };
372 368
373 cpu0_opp11: opp-1209600000 { 369 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 370 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 371 opp-peak-kBps = <2188000 31948800>;
376 }; 372 };
377 373
378 cpu0_opp12: opp-1305600000 { 374 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 375 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 376 opp-peak-kBps = <3072000 31948800>;
381 }; 377 };
382 378
383 cpu0_opp13: opp-1382400000 { 379 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 380 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 381 opp-peak-kBps = <3072000 31948800>;
386 }; 382 };
387 383
388 cpu0_opp14: opp-1478400000 { 384 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 385 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 386 opp-peak-kBps = <3072000 31948800>;
391 }; 387 };
392 388
393 cpu0_opp15: opp-1555200000 { 389 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 390 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 391 opp-peak-kBps = <3072000 40550400>;
396 }; 392 };
397 393
398 cpu0_opp16: opp-1632000000 { 394 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 395 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 396 opp-peak-kBps = <3072000 40550400>;
401 }; 397 };
402 398
403 cpu0_opp17: opp-1708800000 { 399 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 400 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 401 opp-peak-kBps = <3072000 43008000>;
406 }; 402 };
407 403
408 cpu0_opp18: opp-1785600000 { 404 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 405 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 406 opp-peak-kBps = <3072000 43008000>;
411 }; 407 };
412 }; 408 };
413 409
414 cpu4_opp_table: opp-table-cpu4 { 410 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points 411 compatible = "operating-points-v2";
416 opp-shared; 412 opp-shared;
417 413
418 cpu4_opp1: opp-710400000 { 414 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 415 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 416 opp-peak-kBps = <1804000 15974400>;
421 }; 417 };
422 418
423 cpu4_opp2: opp-825600000 { 419 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 420 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 421 opp-peak-kBps = <2188000 19660800>;
426 }; 422 };
427 423
428 cpu4_opp3: opp-940800000 { 424 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 425 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 426 opp-peak-kBps = <2188000 22732800>;
431 }; 427 };
432 428
433 cpu4_opp4: opp-1056000000 { 429 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 430 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 431 opp-peak-kBps = <3072000 25804800>;
436 }; 432 };
437 433
438 cpu4_opp5: opp-1171200000 { 434 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 435 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 436 opp-peak-kBps = <3072000 31948800>;
441 }; 437 };
442 438
443 cpu4_opp6: opp-1286400000 { 439 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 440 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 441 opp-peak-kBps = <4068000 31948800>;
446 }; 442 };
447 443
448 cpu4_opp7: opp-1401600000 { 444 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 445 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 446 opp-peak-kBps = <4068000 31948800>;
451 }; 447 };
452 448
453 cpu4_opp8: opp-1497600000 { 449 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 450 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 451 opp-peak-kBps = <4068000 40550400>;
456 }; 452 };
457 453
458 cpu4_opp9: opp-1612800000 { 454 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 455 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 456 opp-peak-kBps = <4068000 40550400>;
461 }; 457 };
462 458
463 cpu4_opp10: opp-1708800000 { 459 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 460 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 461 opp-peak-kBps = <4068000 43008000>;
466 }; 462 };
467 463
468 cpu4_opp11: opp-1804800000 { 464 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 465 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 466 opp-peak-kBps = <6220000 43008000>;
471 }; 467 };
472 468
473 cpu4_opp12: opp-1920000000 { 469 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 470 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 471 opp-peak-kBps = <6220000 49152000>;
476 }; 472 };
477 473
478 cpu4_opp13: opp-2016000000 { 474 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 475 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 476 opp-peak-kBps = <7216000 49152000>;
481 }; 477 };
482 478
483 cpu4_opp14: opp-2131200000 { 479 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 480 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 481 opp-peak-kBps = <8368000 49152000>;
486 }; 482 };
487 483
488 cpu4_opp15: opp-2227200000 { 484 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 485 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 486 opp-peak-kBps = <8368000 51609600>;
491 }; 487 };
492 488
493 cpu4_opp16: opp-2323200000 { 489 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 490 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 491 opp-peak-kBps = <8368000 51609600>;
496 }; 492 };
497 493
498 cpu4_opp17: opp-2419200000 { 494 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 495 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 496 opp-peak-kBps = <8368000 51609600>;
501 }; 497 };
502 }; 498 };
503 499
504 cpu7_opp_table: opp-table-cpu7 { 500 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points 501 compatible = "operating-points-v2";
506 opp-shared; 502 opp-shared;
507 503
508 cpu7_opp1: opp-825600000 { 504 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 505 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 506 opp-peak-kBps = <2188000 19660800>;
511 }; 507 };
512 508
513 cpu7_opp2: opp-940800000 { 509 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 510 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 511 opp-peak-kBps = <2188000 22732800>;
516 }; 512 };
517 513
518 cpu7_opp3: opp-1056000000 { 514 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 515 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 516 opp-peak-kBps = <3072000 25804800>;
521 }; 517 };
522 518
523 cpu7_opp4: opp-1171200000 { 519 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 520 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 521 opp-peak-kBps = <3072000 31948800>;
526 }; 522 };
527 523
528 cpu7_opp5: opp-1286400000 { 524 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 525 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 526 opp-peak-kBps = <4068000 31948800>;
531 }; 527 };
532 528
533 cpu7_opp6: opp-1401600000 { 529 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 530 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 531 opp-peak-kBps = <4068000 31948800>;
536 }; 532 };
537 533
538 cpu7_opp7: opp-1497600000 { 534 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 535 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 536 opp-peak-kBps = <4068000 40550400>;
541 }; 537 };
542 538
543 cpu7_opp8: opp-1612800000 { 539 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 540 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 541 opp-peak-kBps = <4068000 40550400>;
546 }; 542 };
547 543
548 cpu7_opp9: opp-1708800000 { 544 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 545 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 546 opp-peak-kBps = <4068000 43008000>;
551 }; 547 };
552 548
553 cpu7_opp10: opp-1804800000 { 549 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 550 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 551 opp-peak-kBps = <6220000 43008000>;
556 }; 552 };
557 553
558 cpu7_opp11: opp-1920000000 { 554 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 555 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 556 opp-peak-kBps = <6220000 49152000>;
561 }; 557 };
562 558
563 cpu7_opp12: opp-2016000000 { 559 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 560 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 561 opp-peak-kBps = <7216000 49152000>;
566 }; 562 };
567 563
568 cpu7_opp13: opp-2131200000 { 564 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 565 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 566 opp-peak-kBps = <8368000 49152000>;
571 }; 567 };
572 568
573 cpu7_opp14: opp-2227200000 { 569 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 570 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 571 opp-peak-kBps = <8368000 51609600>;
576 }; 572 };
577 573
578 cpu7_opp15: opp-2323200000 { 574 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 575 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 576 opp-peak-kBps = <8368000 51609600>;
581 }; 577 };
582 578
583 cpu7_opp16: opp-2419200000 { 579 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 580 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 581 opp-peak-kBps = <8368000 51609600>;
586 }; 582 };
587 583
588 cpu7_opp17: opp-2534400000 { 584 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 585 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 586 opp-peak-kBps = <8368000 51609600>;
591 }; 587 };
592 588
593 cpu7_opp18: opp-2649600000 { 589 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 590 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 591 opp-peak-kBps = <8368000 51609600>;
596 }; 592 };
597 593
598 cpu7_opp19: opp-2745600000 { 594 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 595 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 596 opp-peak-kBps = <8368000 51609600>;
601 }; 597 };
602 598
603 cpu7_opp20: opp-2841600000 { 599 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 600 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 601 opp-peak-kBps = <8368000 51609600>;
606 }; 602 };
607 }; 603 };
608 604
609 firmware { 605 firmware {
610 scm: scm { 606 scm: scm {
611 compatible = "qcom,scm 607 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 608 #reset-cells = <1>;
613 }; 609 };
614 }; 610 };
615 611
616 memory@80000000 { 612 memory@80000000 {
617 device_type = "memory"; 613 device_type = "memory";
618 /* We expect the bootloader to 614 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 615 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 616 };
621 617
622 pmu { 618 pmu {
623 compatible = "arm,armv8-pmuv3" 619 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 620 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 621 };
626 622
627 psci { 623 psci {
628 compatible = "arm,psci-1.0"; 624 compatible = "arm,psci-1.0";
629 method = "smc"; 625 method = "smc";
630 626
631 CPU_PD0: power-domain-cpu0 { 627 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells = 628 #power-domain-cells = <0>;
633 power-domains = <&CLUS 629 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 631 };
636 632
637 CPU_PD1: power-domain-cpu1 { 633 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells = 634 #power-domain-cells = <0>;
639 power-domains = <&CLUS 635 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 636 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 637 };
642 638
643 CPU_PD2: power-domain-cpu2 { 639 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells = 640 #power-domain-cells = <0>;
645 power-domains = <&CLUS 641 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 642 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 643 };
648 644
649 CPU_PD3: power-domain-cpu3 { 645 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells = 646 #power-domain-cells = <0>;
651 power-domains = <&CLUS 647 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 648 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 649 };
654 650
655 CPU_PD4: power-domain-cpu4 { 651 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells = 652 #power-domain-cells = <0>;
657 power-domains = <&CLUS 653 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 654 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 655 };
660 656
661 CPU_PD5: power-domain-cpu5 { 657 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells = 658 #power-domain-cells = <0>;
663 power-domains = <&CLUS 659 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 660 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 661 };
666 662
667 CPU_PD6: power-domain-cpu6 { 663 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells = 664 #power-domain-cells = <0>;
669 power-domains = <&CLUS 665 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 666 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 667 };
672 668
673 CPU_PD7: power-domain-cpu7 { 669 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells = 670 #power-domain-cells = <0>;
675 power-domains = <&CLUS 671 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 672 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 673 };
678 674
679 CLUSTER_PD: power-domain-cpu-c 675 CLUSTER_PD: power-domain-cpu-cluster0 {
680 #power-domain-cells = 676 #power-domain-cells = <0>;
681 domain-idle-states = < 677 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 678 };
683 }; 679 };
684 680
685 reserved-memory { 681 reserved-memory {
686 #address-cells = <2>; 682 #address-cells = <2>;
687 #size-cells = <2>; 683 #size-cells = <2>;
688 ranges; 684 ranges;
689 685
690 hyp_mem: memory@85700000 { 686 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 687 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 688 no-map;
693 }; 689 };
694 690
695 xbl_mem: memory@85d00000 { 691 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 692 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 693 no-map;
698 }; 694 };
699 695
700 aop_mem: memory@85f00000 { 696 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 697 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 698 no-map;
703 }; 699 };
704 700
705 aop_cmd_db: memory@85f20000 { 701 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 702 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 703 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 704 no-map;
709 }; 705 };
710 706
711 smem_mem: memory@86000000 { 707 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 708 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 709 no-map;
714 }; 710 };
715 711
716 tz_mem: memory@86200000 { 712 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 713 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 714 no-map;
719 }; 715 };
720 716
721 rmtfs_mem: memory@89b00000 { 717 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 718 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 719 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 720 no-map;
725 721
726 qcom,client-id = <1>; 722 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ !! 723 qcom,vmid = <15>;
728 }; 724 };
729 725
730 camera_mem: memory@8b700000 { 726 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 727 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 728 no-map;
733 }; 729 };
734 730
735 wlan_mem: memory@8bc00000 { 731 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 732 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 733 no-map;
738 }; 734 };
739 735
740 npu_mem: memory@8bd80000 { 736 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 737 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 738 no-map;
743 }; 739 };
744 740
745 adsp_mem: memory@8be00000 { 741 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 742 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 743 no-map;
748 }; 744 };
749 745
750 mpss_mem: memory@8d800000 { 746 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 747 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 748 no-map;
753 }; 749 };
754 750
755 venus_mem: memory@96e00000 { 751 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 752 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 753 no-map;
758 }; 754 };
759 755
760 slpi_mem: memory@97300000 { 756 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 757 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 758 no-map;
763 }; 759 };
764 760
765 ipa_fw_mem: memory@98700000 { 761 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 762 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 763 no-map;
768 }; 764 };
769 765
770 ipa_gsi_mem: memory@98710000 { 766 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 767 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 768 no-map;
773 }; 769 };
774 770
775 gpu_mem: memory@98715000 { 771 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 772 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 773 no-map;
778 }; 774 };
779 775
780 spss_mem: memory@98800000 { 776 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 777 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 778 no-map;
783 }; 779 };
784 780
785 cdsp_mem: memory@98900000 { 781 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 782 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 783 no-map;
788 }; 784 };
789 785
790 qseecom_mem: memory@9e400000 { 786 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 787 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 788 no-map;
793 }; 789 };
794 }; 790 };
795 791
796 smem { 792 smem {
797 compatible = "qcom,smem"; 793 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 794 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 795 hwlocks = <&tcsr_mutex 3>;
800 }; 796 };
801 797
802 smp2p-cdsp { 798 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 799 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 800 qcom,smem = <94>, <432>;
805 801
806 interrupts = <GIC_SPI 576 IRQ_ 802 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 803
808 mboxes = <&apss_shared 6>; 804 mboxes = <&apss_shared 6>;
809 805
810 qcom,local-pid = <0>; 806 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 807 qcom,remote-pid = <5>;
812 808
813 cdsp_smp2p_out: master-kernel 809 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 810 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 811 #qcom,smem-state-cells = <1>;
816 }; 812 };
817 813
818 cdsp_smp2p_in: slave-kernel { 814 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 815 qcom,entry-name = "slave-kernel";
820 816
821 interrupt-controller; 817 interrupt-controller;
822 #interrupt-cells = <2> 818 #interrupt-cells = <2>;
823 }; 819 };
824 }; 820 };
825 821
826 smp2p-lpass { 822 smp2p-lpass {
827 compatible = "qcom,smp2p"; 823 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 824 qcom,smem = <443>, <429>;
829 825
830 interrupts = <GIC_SPI 158 IRQ_ 826 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 827
832 mboxes = <&apss_shared 10>; 828 mboxes = <&apss_shared 10>;
833 829
834 qcom,local-pid = <0>; 830 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 831 qcom,remote-pid = <2>;
836 832
837 adsp_smp2p_out: master-kernel 833 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 834 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 835 #qcom,smem-state-cells = <1>;
840 }; 836 };
841 837
842 adsp_smp2p_in: slave-kernel { 838 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 839 qcom,entry-name = "slave-kernel";
844 840
845 interrupt-controller; 841 interrupt-controller;
846 #interrupt-cells = <2> 842 #interrupt-cells = <2>;
847 }; 843 };
848 }; 844 };
849 845
850 smp2p-mpss { 846 smp2p-mpss {
851 compatible = "qcom,smp2p"; 847 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 848 qcom,smem = <435>, <428>;
853 849
854 interrupts = <GIC_SPI 451 IRQ_ 850 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 851
856 mboxes = <&apss_shared 14>; 852 mboxes = <&apss_shared 14>;
857 853
858 qcom,local-pid = <0>; 854 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 855 qcom,remote-pid = <1>;
860 856
861 modem_smp2p_out: master-kernel 857 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 858 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 859 #qcom,smem-state-cells = <1>;
864 }; 860 };
865 861
866 modem_smp2p_in: slave-kernel { 862 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 863 qcom,entry-name = "slave-kernel";
868 864
869 interrupt-controller; 865 interrupt-controller;
870 #interrupt-cells = <2> 866 #interrupt-cells = <2>;
871 }; 867 };
872 }; 868 };
873 869
874 smp2p-slpi { 870 smp2p-slpi {
875 compatible = "qcom,smp2p"; 871 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 872 qcom,smem = <481>, <430>;
877 873
878 interrupts = <GIC_SPI 172 IRQ_ 874 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 875
880 mboxes = <&apss_shared 26>; 876 mboxes = <&apss_shared 26>;
881 877
882 qcom,local-pid = <0>; 878 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 879 qcom,remote-pid = <3>;
884 880
885 slpi_smp2p_out: master-kernel 881 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 882 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 883 #qcom,smem-state-cells = <1>;
888 }; 884 };
889 885
890 slpi_smp2p_in: slave-kernel { 886 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 887 qcom,entry-name = "slave-kernel";
892 888
893 interrupt-controller; 889 interrupt-controller;
894 #interrupt-cells = <2> 890 #interrupt-cells = <2>;
895 }; 891 };
896 }; 892 };
897 893
898 soc: soc@0 { 894 soc: soc@0 {
899 #address-cells = <2>; 895 #address-cells = <2>;
900 #size-cells = <2>; 896 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 897 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 898 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 899 compatible = "simple-bus";
904 900
905 gcc: clock-controller@100000 { 901 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 902 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 903 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 904 #clock-cells = <1>;
909 #reset-cells = <1>; 905 #reset-cells = <1>;
910 #power-domain-cells = 906 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 907 clock-names = "bi_tcxo",
912 "sleep_c 908 "sleep_clk";
913 clocks = <&rpmhcc RPMH 909 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 910 <&sleep_clk>;
915 }; 911 };
916 912
917 gpi_dma0: dma-controller@80000 913 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 914 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 915 reg = <0 0x00800000 0 0x60000>;
920 interrupts = <GIC_SPI 916 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 917 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 918 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 919 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 920 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 921 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 922 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 923 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 924 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 925 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 926 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 927 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 928 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 929 dma-channels = <13>;
934 dma-channel-mask = <0x 930 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 931 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 932 #dma-cells = <3>;
937 status = "disabled"; 933 status = "disabled";
938 }; 934 };
939 935
940 ethernet: ethernet@20000 { 936 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 937 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 938 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 939 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 940 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 941 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 942 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 943 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 944 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 945 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 946 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 947 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 948 interrupt-names = "macirq", "eth_lpi";
953 949
954 power-domains = <&gcc 950 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 951 resets = <&gcc GCC_EMAC_BCR>;
956 952
957 iommus = <&apps_smmu 0 953 iommus = <&apps_smmu 0x3c0 0x0>;
958 954
959 snps,tso; 955 snps,tso;
960 rx-fifo-depth = <4096> 956 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 957 tx-fifo-depth = <4096>;
962 958
963 status = "disabled"; 959 status = "disabled";
964 }; 960 };
965 961
966 qfprom: efuse@784000 { 962 qfprom: efuse@784000 {
967 compatible = "qcom,sm8 963 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
968 reg = <0 0x00784000 0 964 reg = <0 0x00784000 0 0x8ff>;
969 #address-cells = <1>; 965 #address-cells = <1>;
970 #size-cells = <1>; 966 #size-cells = <1>;
971 967
972 gpu_speed_bin: gpu-spe !! 968 gpu_speed_bin: gpu_speed_bin@133 {
973 reg = <0x133 0 969 reg = <0x133 0x1>;
974 bits = <5 3>; 970 bits = <5 3>;
975 }; 971 };
976 }; 972 };
977 973
978 qupv3_id_0: geniqup@8c0000 { 974 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 975 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 976 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 977 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 978 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 979 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 980 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 981 #address-cells = <2>;
986 #size-cells = <2>; 982 #size-cells = <2>;
987 ranges; 983 ranges;
988 status = "disabled"; 984 status = "disabled";
989 985
990 i2c0: i2c@880000 { 986 i2c0: i2c@880000 {
991 compatible = " 987 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 988 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 989 clock-names = "se";
994 clocks = <&gcc 990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 991 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 992 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 993 dma-names = "tx", "rx";
998 pinctrl-names 994 pinctrl-names = "default";
999 pinctrl-0 = <& 995 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 996 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 997 #address-cells = <1>;
1002 #size-cells = 998 #size-cells = <0>;
1003 status = "dis 999 status = "disabled";
1004 }; 1000 };
1005 1001
1006 spi0: spi@880000 { 1002 spi0: spi@880000 {
1007 compatible = 1003 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 1004 reg = <0 0x00880000 0 0x4000>;
1009 reg-names = " 1005 reg-names = "se";
1010 clock-names = 1006 clock-names = "se";
1011 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 1008 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 1009 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 1010 dma-names = "tx", "rx";
1015 pinctrl-names 1011 pinctrl-names = "default";
1016 pinctrl-0 = < 1012 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 1013 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 1014 spi-max-frequency = <50000000>;
1019 #address-cell 1015 #address-cells = <1>;
1020 #size-cells = 1016 #size-cells = <0>;
1021 status = "dis 1017 status = "disabled";
1022 }; 1018 };
1023 1019
1024 i2c1: i2c@884000 { 1020 i2c1: i2c@884000 {
1025 compatible = 1021 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 1022 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 1023 clock-names = "se";
1028 clocks = <&gc 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 1025 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 1026 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 1027 dma-names = "tx", "rx";
1032 pinctrl-names 1028 pinctrl-names = "default";
1033 pinctrl-0 = < 1029 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 1030 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 1031 #address-cells = <1>;
1036 #size-cells = 1032 #size-cells = <0>;
1037 status = "dis 1033 status = "disabled";
1038 }; 1034 };
1039 1035
1040 spi1: spi@884000 { 1036 spi1: spi@884000 {
1041 compatible = 1037 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1038 reg = <0 0x00884000 0 0x4000>;
1043 reg-names = " 1039 reg-names = "se";
1044 clock-names = 1040 clock-names = "se";
1045 clocks = <&gc 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1042 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1043 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1044 dma-names = "tx", "rx";
1049 pinctrl-names 1045 pinctrl-names = "default";
1050 pinctrl-0 = < 1046 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1047 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1048 spi-max-frequency = <50000000>;
1053 #address-cell 1049 #address-cells = <1>;
1054 #size-cells = 1050 #size-cells = <0>;
1055 status = "dis 1051 status = "disabled";
1056 }; 1052 };
1057 1053
1058 i2c2: i2c@888000 { 1054 i2c2: i2c@888000 {
1059 compatible = 1055 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1056 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1057 clock-names = "se";
1062 clocks = <&gc 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1059 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1060 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1061 dma-names = "tx", "rx";
1066 pinctrl-names 1062 pinctrl-names = "default";
1067 pinctrl-0 = < 1063 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1064 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1065 #address-cells = <1>;
1070 #size-cells = 1066 #size-cells = <0>;
1071 status = "dis 1067 status = "disabled";
1072 }; 1068 };
1073 1069
1074 spi2: spi@888000 { 1070 spi2: spi@888000 {
1075 compatible = 1071 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 1072 reg = <0 0x00888000 0 0x4000>;
1077 reg-names = " 1073 reg-names = "se";
1078 clock-names = 1074 clock-names = "se";
1079 clocks = <&gc 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1076 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1077 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1078 dma-names = "tx", "rx";
1083 pinctrl-names 1079 pinctrl-names = "default";
1084 pinctrl-0 = < 1080 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1081 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1082 spi-max-frequency = <50000000>;
1087 #address-cell 1083 #address-cells = <1>;
1088 #size-cells = 1084 #size-cells = <0>;
1089 status = "dis 1085 status = "disabled";
1090 }; 1086 };
1091 1087
1092 i2c3: i2c@88c000 { 1088 i2c3: i2c@88c000 {
1093 compatible = 1089 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1090 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1091 clock-names = "se";
1096 clocks = <&gc 1092 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1093 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1094 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1095 dma-names = "tx", "rx";
1100 pinctrl-names 1096 pinctrl-names = "default";
1101 pinctrl-0 = < 1097 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1098 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1099 #address-cells = <1>;
1104 #size-cells = 1100 #size-cells = <0>;
1105 status = "dis 1101 status = "disabled";
1106 }; 1102 };
1107 1103
1108 spi3: spi@88c000 { 1104 spi3: spi@88c000 {
1109 compatible = 1105 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 1106 reg = <0 0x0088c000 0 0x4000>;
1111 reg-names = " 1107 reg-names = "se";
1112 clock-names = 1108 clock-names = "se";
1113 clocks = <&gc 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1110 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1111 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1112 dma-names = "tx", "rx";
1117 pinctrl-names 1113 pinctrl-names = "default";
1118 pinctrl-0 = < 1114 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1115 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1116 spi-max-frequency = <50000000>;
1121 #address-cell 1117 #address-cells = <1>;
1122 #size-cells = 1118 #size-cells = <0>;
1123 status = "dis 1119 status = "disabled";
1124 }; 1120 };
1125 1121
1126 i2c4: i2c@890000 { 1122 i2c4: i2c@890000 {
1127 compatible = 1123 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1124 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1125 clock-names = "se";
1130 clocks = <&gc 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1127 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1128 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1129 dma-names = "tx", "rx";
1134 pinctrl-names 1130 pinctrl-names = "default";
1135 pinctrl-0 = < 1131 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1132 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1133 #address-cells = <1>;
1138 #size-cells = 1134 #size-cells = <0>;
1139 status = "dis 1135 status = "disabled";
1140 }; 1136 };
1141 1137
1142 spi4: spi@890000 { 1138 spi4: spi@890000 {
1143 compatible = 1139 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 1140 reg = <0 0x00890000 0 0x4000>;
1145 reg-names = " 1141 reg-names = "se";
1146 clock-names = 1142 clock-names = "se";
1147 clocks = <&gc 1143 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1144 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1145 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1146 dma-names = "tx", "rx";
1151 pinctrl-names 1147 pinctrl-names = "default";
1152 pinctrl-0 = < 1148 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1149 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1150 spi-max-frequency = <50000000>;
1155 #address-cell 1151 #address-cells = <1>;
1156 #size-cells = 1152 #size-cells = <0>;
1157 status = "dis 1153 status = "disabled";
1158 }; 1154 };
1159 1155
1160 i2c5: i2c@894000 { 1156 i2c5: i2c@894000 {
1161 compatible = 1157 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1158 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1159 clock-names = "se";
1164 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1161 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1162 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1163 dma-names = "tx", "rx";
1168 pinctrl-names 1164 pinctrl-names = "default";
1169 pinctrl-0 = < 1165 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1166 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1167 #address-cells = <1>;
1172 #size-cells = 1168 #size-cells = <0>;
1173 status = "dis 1169 status = "disabled";
1174 }; 1170 };
1175 1171
1176 spi5: spi@894000 { 1172 spi5: spi@894000 {
1177 compatible = 1173 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 1174 reg = <0 0x00894000 0 0x4000>;
1179 reg-names = " 1175 reg-names = "se";
1180 clock-names = 1176 clock-names = "se";
1181 clocks = <&gc 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1178 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1179 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1180 dma-names = "tx", "rx";
1185 pinctrl-names 1181 pinctrl-names = "default";
1186 pinctrl-0 = < 1182 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1183 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1184 spi-max-frequency = <50000000>;
1189 #address-cell 1185 #address-cells = <1>;
1190 #size-cells = 1186 #size-cells = <0>;
1191 status = "dis 1187 status = "disabled";
1192 }; 1188 };
1193 1189
1194 i2c6: i2c@898000 { 1190 i2c6: i2c@898000 {
1195 compatible = 1191 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1192 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1193 clock-names = "se";
1198 clocks = <&gc 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1195 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1196 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1197 dma-names = "tx", "rx";
1202 pinctrl-names 1198 pinctrl-names = "default";
1203 pinctrl-0 = < 1199 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1200 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1201 #address-cells = <1>;
1206 #size-cells = 1202 #size-cells = <0>;
1207 status = "dis 1203 status = "disabled";
1208 }; 1204 };
1209 1205
1210 spi6: spi@898000 { 1206 spi6: spi@898000 {
1211 compatible = 1207 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1208 reg = <0 0x00898000 0 0x4000>;
1213 reg-names = " 1209 reg-names = "se";
1214 clock-names = 1210 clock-names = "se";
1215 clocks = <&gc 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1212 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1213 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1214 dma-names = "tx", "rx";
1219 pinctrl-names 1215 pinctrl-names = "default";
1220 pinctrl-0 = < 1216 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1217 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1218 spi-max-frequency = <50000000>;
1223 #address-cell 1219 #address-cells = <1>;
1224 #size-cells = 1220 #size-cells = <0>;
1225 status = "dis 1221 status = "disabled";
1226 }; 1222 };
1227 1223
1228 i2c7: i2c@89c000 { 1224 i2c7: i2c@89c000 {
1229 compatible = 1225 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1226 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1227 clock-names = "se";
1232 clocks = <&gc 1228 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1229 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1230 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1231 dma-names = "tx", "rx";
1236 pinctrl-names 1232 pinctrl-names = "default";
1237 pinctrl-0 = < 1233 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = 1234 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1235 #address-cells = <1>;
1240 #size-cells = 1236 #size-cells = <0>;
1241 status = "dis 1237 status = "disabled";
1242 }; 1238 };
1243 1239
1244 spi7: spi@89c000 { 1240 spi7: spi@89c000 {
1245 compatible = 1241 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 1242 reg = <0 0x0089c000 0 0x4000>;
1247 reg-names = " 1243 reg-names = "se";
1248 clock-names = 1244 clock-names = "se";
1249 clocks = <&gc 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1246 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1247 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1248 dma-names = "tx", "rx";
1253 pinctrl-names 1249 pinctrl-names = "default";
1254 pinctrl-0 = < 1250 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1251 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1252 spi-max-frequency = <50000000>;
1257 #address-cell 1253 #address-cells = <1>;
1258 #size-cells = 1254 #size-cells = <0>;
1259 status = "dis 1255 status = "disabled";
1260 }; 1256 };
1261 }; 1257 };
1262 1258
1263 gpi_dma1: dma-controller@a000 1259 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm 1260 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 1261 reg = <0 0x00a00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1262 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1263 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1264 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1265 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1266 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1267 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1268 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1269 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1270 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1271 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1272 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1273 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1274 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1275 dma-channels = <13>;
1280 dma-channel-mask = <0 1276 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1277 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1278 #dma-cells = <3>;
1283 status = "disabled"; 1279 status = "disabled";
1284 }; 1280 };
1285 1281
1286 qupv3_id_1: geniqup@ac0000 { 1282 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1283 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1284 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1285 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1286 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1287 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1288 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1289 #address-cells = <2>;
1294 #size-cells = <2>; 1290 #size-cells = <2>;
1295 ranges; 1291 ranges;
1296 status = "disabled"; 1292 status = "disabled";
1297 1293
1298 i2c8: i2c@a80000 { 1294 i2c8: i2c@a80000 {
1299 compatible = 1295 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1296 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1297 clock-names = "se";
1302 clocks = <&gc 1298 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1299 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1300 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1301 dma-names = "tx", "rx";
1306 pinctrl-names 1302 pinctrl-names = "default";
1307 pinctrl-0 = < 1303 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1304 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1305 #address-cells = <1>;
1310 #size-cells = 1306 #size-cells = <0>;
1311 status = "dis 1307 status = "disabled";
1312 }; 1308 };
1313 1309
1314 spi8: spi@a80000 { 1310 spi8: spi@a80000 {
1315 compatible = 1311 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 1312 reg = <0 0x00a80000 0 0x4000>;
1317 reg-names = " 1313 reg-names = "se";
1318 clock-names = 1314 clock-names = "se";
1319 clocks = <&gc 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1316 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1317 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1318 dma-names = "tx", "rx";
1323 pinctrl-names 1319 pinctrl-names = "default";
1324 pinctrl-0 = < 1320 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1321 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1322 spi-max-frequency = <50000000>;
1327 #address-cell 1323 #address-cells = <1>;
1328 #size-cells = 1324 #size-cells = <0>;
1329 status = "dis 1325 status = "disabled";
1330 }; 1326 };
1331 1327
1332 i2c9: i2c@a84000 { 1328 i2c9: i2c@a84000 {
1333 compatible = 1329 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1330 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1331 clock-names = "se";
1336 clocks = <&gc 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1333 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1334 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1335 dma-names = "tx", "rx";
1340 pinctrl-names 1336 pinctrl-names = "default";
1341 pinctrl-0 = < 1337 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1338 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1339 #address-cells = <1>;
1344 #size-cells = 1340 #size-cells = <0>;
1345 status = "dis 1341 status = "disabled";
1346 }; 1342 };
1347 1343
1348 spi9: spi@a84000 { 1344 spi9: spi@a84000 {
1349 compatible = 1345 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 1346 reg = <0 0x00a84000 0 0x4000>;
1351 reg-names = " 1347 reg-names = "se";
1352 clock-names = 1348 clock-names = "se";
1353 clocks = <&gc 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1350 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1351 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1352 dma-names = "tx", "rx";
1357 pinctrl-names 1353 pinctrl-names = "default";
1358 pinctrl-0 = < 1354 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1355 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1356 spi-max-frequency = <50000000>;
1361 #address-cell 1357 #address-cells = <1>;
1362 #size-cells = 1358 #size-cells = <0>;
1363 status = "dis 1359 status = "disabled";
1364 }; 1360 };
1365 1361
1366 uart9: serial@a84000 1362 uart9: serial@a84000 {
1367 compatible = 1363 compatible = "qcom,geni-uart";
1368 reg = <0x0 0x 1364 reg = <0x0 0x00a84000 0x0 0x4000>;
>> 1365 reg-names = "se";
1369 clocks = <&gc 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1370 clock-names = 1367 clock-names = "se";
1371 pinctrl-0 = < 1368 pinctrl-0 = <&qup_uart9_default>;
1372 pinctrl-names 1369 pinctrl-names = "default";
1373 interrupts = 1370 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
>> 1371 #address-cells = <1>;
>> 1372 #size-cells = <0>;
1374 status = "dis 1373 status = "disabled";
1375 }; 1374 };
1376 1375
1377 i2c10: i2c@a88000 { 1376 i2c10: i2c@a88000 {
1378 compatible = 1377 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1378 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1379 clock-names = "se";
1381 clocks = <&gc 1380 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1381 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1382 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1383 dma-names = "tx", "rx";
1385 pinctrl-names 1384 pinctrl-names = "default";
1386 pinctrl-0 = < 1385 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1386 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1387 #address-cells = <1>;
1389 #size-cells = 1388 #size-cells = <0>;
1390 status = "dis 1389 status = "disabled";
1391 }; 1390 };
1392 1391
1393 spi10: spi@a88000 { 1392 spi10: spi@a88000 {
1394 compatible = 1393 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 1394 reg = <0 0x00a88000 0 0x4000>;
1396 reg-names = " 1395 reg-names = "se";
1397 clock-names = 1396 clock-names = "se";
1398 clocks = <&gc 1397 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1398 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1399 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1400 dma-names = "tx", "rx";
1402 pinctrl-names 1401 pinctrl-names = "default";
1403 pinctrl-0 = < 1402 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1403 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1404 spi-max-frequency = <50000000>;
1406 #address-cell 1405 #address-cells = <1>;
1407 #size-cells = 1406 #size-cells = <0>;
1408 status = "dis 1407 status = "disabled";
1409 }; 1408 };
1410 1409
1411 i2c11: i2c@a8c000 { 1410 i2c11: i2c@a8c000 {
1412 compatible = 1411 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1412 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1413 clock-names = "se";
1415 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1415 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1416 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1417 dma-names = "tx", "rx";
1419 pinctrl-names 1418 pinctrl-names = "default";
1420 pinctrl-0 = < 1419 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1420 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1421 #address-cells = <1>;
1423 #size-cells = 1422 #size-cells = <0>;
1424 status = "dis 1423 status = "disabled";
1425 }; 1424 };
1426 1425
1427 spi11: spi@a8c000 { 1426 spi11: spi@a8c000 {
1428 compatible = 1427 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 1428 reg = <0 0x00a8c000 0 0x4000>;
1430 reg-names = " 1429 reg-names = "se";
1431 clock-names = 1430 clock-names = "se";
1432 clocks = <&gc 1431 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1432 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1433 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1434 dma-names = "tx", "rx";
1436 pinctrl-names 1435 pinctrl-names = "default";
1437 pinctrl-0 = < 1436 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1437 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1438 spi-max-frequency = <50000000>;
1440 #address-cell 1439 #address-cells = <1>;
1441 #size-cells = 1440 #size-cells = <0>;
1442 status = "dis 1441 status = "disabled";
1443 }; 1442 };
1444 1443
1445 uart2: serial@a90000 1444 uart2: serial@a90000 {
1446 compatible = 1445 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1446 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1447 clock-names = "se";
1449 clocks = <&gc 1448 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1449 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1450 status = "disabled";
1452 }; 1451 };
1453 1452
1454 i2c12: i2c@a90000 { 1453 i2c12: i2c@a90000 {
1455 compatible = 1454 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1455 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1456 clock-names = "se";
1458 clocks = <&gc 1457 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1458 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1459 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1460 dma-names = "tx", "rx";
1462 pinctrl-names 1461 pinctrl-names = "default";
1463 pinctrl-0 = < 1462 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1463 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1464 #address-cells = <1>;
1466 #size-cells = 1465 #size-cells = <0>;
1467 status = "dis 1466 status = "disabled";
1468 }; 1467 };
1469 1468
1470 spi12: spi@a90000 { 1469 spi12: spi@a90000 {
1471 compatible = 1470 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 1471 reg = <0 0x00a90000 0 0x4000>;
1473 reg-names = " 1472 reg-names = "se";
1474 clock-names = 1473 clock-names = "se";
1475 clocks = <&gc 1474 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1475 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1476 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1477 dma-names = "tx", "rx";
1479 pinctrl-names 1478 pinctrl-names = "default";
1480 pinctrl-0 = < 1479 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1480 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1481 spi-max-frequency = <50000000>;
1483 #address-cell 1482 #address-cells = <1>;
1484 #size-cells = 1483 #size-cells = <0>;
1485 status = "dis 1484 status = "disabled";
1486 }; 1485 };
1487 1486
1488 i2c16: i2c@94000 { 1487 i2c16: i2c@94000 {
1489 compatible = 1488 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 1489 reg = <0 0x00094000 0 0x4000>;
1491 clock-names = 1490 clock-names = "se";
1492 clocks = <&gc 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1492 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1493 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1494 dma-names = "tx", "rx";
1496 pinctrl-names 1495 pinctrl-names = "default";
1497 pinctrl-0 = < 1496 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1497 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1498 #address-cells = <1>;
1500 #size-cells = 1499 #size-cells = <0>;
1501 status = "dis 1500 status = "disabled";
1502 }; 1501 };
1503 1502
1504 spi16: spi@a94000 { 1503 spi16: spi@a94000 {
1505 compatible = 1504 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 1505 reg = <0 0x00a94000 0 0x4000>;
1507 reg-names = " 1506 reg-names = "se";
1508 clock-names = 1507 clock-names = "se";
1509 clocks = <&gc 1508 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1509 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1510 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1511 dma-names = "tx", "rx";
1513 pinctrl-names 1512 pinctrl-names = "default";
1514 pinctrl-0 = < 1513 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1514 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1515 spi-max-frequency = <50000000>;
1517 #address-cell 1516 #address-cells = <1>;
1518 #size-cells = 1517 #size-cells = <0>;
1519 status = "dis 1518 status = "disabled";
1520 }; 1519 };
1521 }; 1520 };
1522 1521
1523 gpi_dma2: dma-controller@c000 1522 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm 1523 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 1524 reg = <0 0x00c00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1525 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1526 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1527 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1528 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1529 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1530 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1531 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1532 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1533 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1534 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1535 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1536 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1537 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1538 dma-channels = <13>;
1540 dma-channel-mask = <0 1539 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1540 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1541 #dma-cells = <3>;
1543 status = "disabled"; 1542 status = "disabled";
1544 }; 1543 };
1545 1544
1546 qupv3_id_2: geniqup@cc0000 { 1545 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1546 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1547 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1548
1550 clock-names = "m-ahb" 1549 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1550 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1551 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1552 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1553 #address-cells = <2>;
1555 #size-cells = <2>; 1554 #size-cells = <2>;
1556 ranges; 1555 ranges;
1557 status = "disabled"; 1556 status = "disabled";
1558 1557
1559 i2c17: i2c@c80000 { 1558 i2c17: i2c@c80000 {
1560 compatible = 1559 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1560 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1561 clock-names = "se";
1563 clocks = <&gc 1562 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1563 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1564 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1565 dma-names = "tx", "rx";
1567 pinctrl-names 1566 pinctrl-names = "default";
1568 pinctrl-0 = < 1567 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1568 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1569 #address-cells = <1>;
1571 #size-cells = 1570 #size-cells = <0>;
1572 status = "dis 1571 status = "disabled";
1573 }; 1572 };
1574 1573
1575 spi17: spi@c80000 { 1574 spi17: spi@c80000 {
1576 compatible = 1575 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1576 reg = <0 0x00c80000 0 0x4000>;
1578 reg-names = " 1577 reg-names = "se";
1579 clock-names = 1578 clock-names = "se";
1580 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1580 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1581 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1582 dma-names = "tx", "rx";
1584 pinctrl-names 1583 pinctrl-names = "default";
1585 pinctrl-0 = < 1584 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1585 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1586 spi-max-frequency = <50000000>;
1588 #address-cell 1587 #address-cells = <1>;
1589 #size-cells = 1588 #size-cells = <0>;
1590 status = "dis 1589 status = "disabled";
1591 }; 1590 };
1592 1591
1593 i2c18: i2c@c84000 { 1592 i2c18: i2c@c84000 {
1594 compatible = 1593 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1594 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1595 clock-names = "se";
1597 clocks = <&gc 1596 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1597 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1598 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1599 dma-names = "tx", "rx";
1601 pinctrl-names 1600 pinctrl-names = "default";
1602 pinctrl-0 = < 1601 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1602 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1603 #address-cells = <1>;
1605 #size-cells = 1604 #size-cells = <0>;
1606 status = "dis 1605 status = "disabled";
1607 }; 1606 };
1608 1607
1609 spi18: spi@c84000 { 1608 spi18: spi@c84000 {
1610 compatible = 1609 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 1610 reg = <0 0x00c84000 0 0x4000>;
1612 reg-names = " 1611 reg-names = "se";
1613 clock-names = 1612 clock-names = "se";
1614 clocks = <&gc 1613 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1614 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1615 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1616 dma-names = "tx", "rx";
1618 pinctrl-names 1617 pinctrl-names = "default";
1619 pinctrl-0 = < 1618 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1619 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1620 spi-max-frequency = <50000000>;
1622 #address-cell 1621 #address-cells = <1>;
1623 #size-cells = 1622 #size-cells = <0>;
1624 status = "dis 1623 status = "disabled";
1625 }; 1624 };
1626 1625
1627 i2c19: i2c@c88000 { 1626 i2c19: i2c@c88000 {
1628 compatible = 1627 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1628 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1629 clock-names = "se";
1631 clocks = <&gc 1630 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1631 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1632 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1633 dma-names = "tx", "rx";
1635 pinctrl-names 1634 pinctrl-names = "default";
1636 pinctrl-0 = < 1635 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1636 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1637 #address-cells = <1>;
1639 #size-cells = 1638 #size-cells = <0>;
1640 status = "dis 1639 status = "disabled";
1641 }; 1640 };
1642 1641
1643 spi19: spi@c88000 { 1642 spi19: spi@c88000 {
1644 compatible = 1643 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 1644 reg = <0 0x00c88000 0 0x4000>;
1646 reg-names = " 1645 reg-names = "se";
1647 clock-names = 1646 clock-names = "se";
1648 clocks = <&gc 1647 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1648 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1649 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1650 dma-names = "tx", "rx";
1652 pinctrl-names 1651 pinctrl-names = "default";
1653 pinctrl-0 = < 1652 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1653 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1654 spi-max-frequency = <50000000>;
1656 #address-cell 1655 #address-cells = <1>;
1657 #size-cells = 1656 #size-cells = <0>;
1658 status = "dis 1657 status = "disabled";
1659 }; 1658 };
1660 1659
1661 i2c13: i2c@c8c000 { 1660 i2c13: i2c@c8c000 {
1662 compatible = 1661 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1662 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1663 clock-names = "se";
1665 clocks = <&gc 1664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1665 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1666 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1667 dma-names = "tx", "rx";
1669 pinctrl-names 1668 pinctrl-names = "default";
1670 pinctrl-0 = < 1669 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1670 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1671 #address-cells = <1>;
1673 #size-cells = 1672 #size-cells = <0>;
1674 status = "dis 1673 status = "disabled";
1675 }; 1674 };
1676 1675
1677 spi13: spi@c8c000 { 1676 spi13: spi@c8c000 {
1678 compatible = 1677 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 1678 reg = <0 0x00c8c000 0 0x4000>;
1680 reg-names = " 1679 reg-names = "se";
1681 clock-names = 1680 clock-names = "se";
1682 clocks = <&gc 1681 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1682 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1683 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1684 dma-names = "tx", "rx";
1686 pinctrl-names 1685 pinctrl-names = "default";
1687 pinctrl-0 = < 1686 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1687 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1688 spi-max-frequency = <50000000>;
1690 #address-cell 1689 #address-cells = <1>;
1691 #size-cells = 1690 #size-cells = <0>;
1692 status = "dis 1691 status = "disabled";
1693 }; 1692 };
1694 1693
1695 i2c14: i2c@c90000 { 1694 i2c14: i2c@c90000 {
1696 compatible = 1695 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1696 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1697 clock-names = "se";
1699 clocks = <&gc 1698 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1699 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1700 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1701 dma-names = "tx", "rx";
1703 pinctrl-names 1702 pinctrl-names = "default";
1704 pinctrl-0 = < 1703 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1705 #address-cells = <1>;
1707 #size-cells = 1706 #size-cells = <0>;
1708 status = "dis 1707 status = "disabled";
1709 }; 1708 };
1710 1709
1711 spi14: spi@c90000 { 1710 spi14: spi@c90000 {
1712 compatible = 1711 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 1712 reg = <0 0x00c90000 0 0x4000>;
1714 reg-names = " 1713 reg-names = "se";
1715 clock-names = 1714 clock-names = "se";
1716 clocks = <&gc 1715 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1716 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1717 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1718 dma-names = "tx", "rx";
1720 pinctrl-names 1719 pinctrl-names = "default";
1721 pinctrl-0 = < 1720 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1721 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1722 spi-max-frequency = <50000000>;
1724 #address-cell 1723 #address-cells = <1>;
1725 #size-cells = 1724 #size-cells = <0>;
1726 status = "dis 1725 status = "disabled";
1727 }; 1726 };
1728 1727
1729 i2c15: i2c@c94000 { 1728 i2c15: i2c@c94000 {
1730 compatible = 1729 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1730 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1731 clock-names = "se";
1733 clocks = <&gc 1732 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1733 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1734 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1735 dma-names = "tx", "rx";
1737 pinctrl-names 1736 pinctrl-names = "default";
1738 pinctrl-0 = < 1737 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1738 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1739 #address-cells = <1>;
1741 #size-cells = 1740 #size-cells = <0>;
1742 status = "dis 1741 status = "disabled";
1743 }; 1742 };
1744 1743
1745 spi15: spi@c94000 { 1744 spi15: spi@c94000 {
1746 compatible = 1745 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 1746 reg = <0 0x00c94000 0 0x4000>;
1748 reg-names = " 1747 reg-names = "se";
1749 clock-names = 1748 clock-names = "se";
1750 clocks = <&gc 1749 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1750 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1751 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1752 dma-names = "tx", "rx";
1754 pinctrl-names 1753 pinctrl-names = "default";
1755 pinctrl-0 = < 1754 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1755 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1756 spi-max-frequency = <50000000>;
1758 #address-cell 1757 #address-cells = <1>;
1759 #size-cells = 1758 #size-cells = <0>;
1760 status = "dis 1759 status = "disabled";
1761 }; 1760 };
1762 }; 1761 };
1763 1762
1764 config_noc: interconnect@1500 1763 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1764 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1765 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = !! 1766 #interconnect-cells = <1>;
1768 qcom,bcm-voters = <&a 1767 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1768 };
1770 1769
1771 system_noc: interconnect@1620 1770 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1771 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1772 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = !! 1773 #interconnect-cells = <1>;
1775 qcom,bcm-voters = <&a 1774 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1775 };
1777 1776
1778 mc_virt: interconnect@163a000 1777 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1778 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1779 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = !! 1780 #interconnect-cells = <1>;
1782 qcom,bcm-voters = <&a 1781 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1782 };
1784 1783
1785 aggre1_noc: interconnect@16e0 1784 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1785 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1786 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = !! 1787 #interconnect-cells = <1>;
1789 qcom,bcm-voters = <&a 1788 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1789 };
1791 1790
1792 aggre2_noc: interconnect@1700 1791 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1792 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1793 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = !! 1794 #interconnect-cells = <1>;
1796 qcom,bcm-voters = <&a 1795 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1796 };
1798 1797
1799 compute_noc: interconnect@172 1798 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1799 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1800 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = !! 1801 #interconnect-cells = <1>;
1803 qcom,bcm-voters = <&a 1802 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1803 };
1805 1804
1806 mmss_noc: interconnect@174000 1805 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1806 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1807 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = !! 1808 #interconnect-cells = <1>;
1810 qcom,bcm-voters = <&a 1809 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1810 };
1812 1811
1813 system-cache-controller@92000 1812 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1813 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 1814 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1816 <0 0x09300000 0 1815 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1817 <0 0x09600000 0 1816 <0 0x09600000 0 0x50000>;
1818 reg-names = "llcc0_ba 1817 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1819 "llcc3_ba 1818 "llcc3_base", "llcc_broadcast_base";
1820 interrupts = <GIC_SPI 1819 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1820 };
1822 1821
1823 dma@10a2000 { 1822 dma@10a2000 {
1824 compatible = "qcom,sm 1823 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1825 reg = <0x0 0x010a2000 1824 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 1825 <0x0 0x010ad000 0x0 0x3000>;
1827 }; 1826 };
1828 1827
1829 pcie0: pcie@1c00000 { !! 1828 pcie0: pci@1c00000 {
1830 compatible = "qcom,pc !! 1829 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1831 reg = <0 0x01c00000 0 1830 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1831 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1832 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1833 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1834 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1835 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1836 device_type = "pci";
1838 linux,pci-domain = <0 1837 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1838 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1839 num-lanes = <1>;
1841 1840
1842 #address-cells = <3>; 1841 #address-cells = <3>;
1843 #size-cells = <2>; 1842 #size-cells = <2>;
1844 1843
1845 ranges = <0x01000000 1844 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 1845 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 1846
1848 interrupts = <GIC_SPI !! 1847 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1849 <GIC_SPI !! 1848 interrupt-names = "msi";
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 1849 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1850 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1851 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1852 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1853 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1854 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1855
1871 clocks = <&gcc GCC_PC 1856 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1857 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1858 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1859 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1860 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1861 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG !! 1862 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", 1863 clock-names = "pipe",
1880 "aux", 1864 "aux",
1881 "cfg", 1865 "cfg",
1882 "bus_ma 1866 "bus_master",
1883 "bus_sl 1867 "bus_slave",
1884 "slave_ 1868 "slave_q2a",
1885 "tbu", !! 1869 "tbu";
1886 "ref"; <<
1887 1870
1888 iommu-map = <0x0 &a 1871 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1872 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1873
1891 resets = <&gcc GCC_PC 1874 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1875 reset-names = "pci";
1893 1876
1894 power-domains = <&gcc 1877 power-domains = <&gcc PCIE_0_GDSC>;
1895 1878
1896 phys = <&pcie0_phy>; !! 1879 phys = <&pcie0_lane>;
1897 phy-names = "pciephy" 1880 phy-names = "pciephy";
1898 1881
1899 perst-gpios = <&tlmm !! 1882 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 !! 1883 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1884
1902 pinctrl-names = "defa 1885 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1886 pinctrl-0 = <&pcie0_default_state>;
1904 1887
1905 status = "disabled"; 1888 status = "disabled";
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; 1889 };
1917 1890
1918 pcie0_phy: phy@1c06000 { 1891 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1892 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 !! 1893 reg = <0 0x01c06000 0 0x1c0>;
>> 1894 #address-cells = <2>;
>> 1895 #size-cells = <2>;
>> 1896 ranges;
1921 clocks = <&gcc GCC_PC 1897 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1898 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC !! 1899 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1924 <&gcc GCC_PC !! 1900 clock-names = "aux", "cfg_ahb", "refgen";
1925 <&gcc GCC_PC <<
1926 clock-names = "aux", <<
1927 "cfg_ah <<
1928 "ref", <<
1929 "refgen <<
1930 "pipe"; <<
1931 <<
1932 clock-output-names = <<
1933 #clock-cells = <0>; <<
1934 <<
1935 #phy-cells = <0>; <<
1936 1901
1937 resets = <&gcc GCC_PC 1902 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1903 reset-names = "phy";
1939 1904
1940 assigned-clocks = <&g 1905 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1906 assigned-clock-rates = <100000000>;
1942 1907
1943 status = "disabled"; 1908 status = "disabled";
>> 1909
>> 1910 pcie0_lane: phy@1c06200 {
>> 1911 reg = <0 0x01c06200 0 0x170>, /* tx */
>> 1912 <0 0x01c06400 0 0x200>, /* rx */
>> 1913 <0 0x01c06800 0 0x1f0>, /* pcs */
>> 1914 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1915 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1916 clock-names = "pipe0";
>> 1917
>> 1918 #phy-cells = <0>;
>> 1919 clock-output-names = "pcie_0_pipe_clk";
>> 1920 };
1944 }; 1921 };
1945 1922
1946 pcie1: pcie@1c08000 { !! 1923 pcie1: pci@1c08000 {
1947 compatible = "qcom,pc !! 1924 compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
1948 reg = <0 0x01c08000 0 1925 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1926 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1927 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1928 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1929 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1930 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1931 device_type = "pci";
1955 linux,pci-domain = <1 1932 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1933 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1934 num-lanes = <2>;
1958 1935
1959 #address-cells = <3>; 1936 #address-cells = <3>;
1960 #size-cells = <2>; 1937 #size-cells = <2>;
1961 1938
1962 ranges = <0x01000000 1939 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1940 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1941
1965 interrupts = <GIC_SPI !! 1942 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1966 <GIC_SPI !! 1943 interrupt-names = "msi";
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 1944 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1945 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1946 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1947 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1948 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1949 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1950
1988 clocks = <&gcc GCC_PC 1951 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1952 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1953 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1954 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1955 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1956 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG !! 1957 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", 1958 clock-names = "pipe",
1997 "aux", 1959 "aux",
1998 "cfg", 1960 "cfg",
1999 "bus_ma 1961 "bus_master",
2000 "bus_sl 1962 "bus_slave",
2001 "slave_ 1963 "slave_q2a",
2002 "tbu", !! 1964 "tbu";
2003 "ref"; <<
2004 1965
2005 assigned-clocks = <&g 1966 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 1967 assigned-clock-rates = <19200000>;
2007 1968
2008 iommu-map = <0x0 &a 1969 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 1970 <0x100 &apps_smmu 0x1e01 0x1>;
2010 1971
2011 resets = <&gcc GCC_PC 1972 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 1973 reset-names = "pci";
2013 1974
2014 power-domains = <&gcc 1975 power-domains = <&gcc PCIE_1_GDSC>;
2015 1976
2016 phys = <&pcie1_phy>; !! 1977 phys = <&pcie1_lane>;
2017 phy-names = "pciephy" 1978 phy-names = "pciephy";
2018 1979
2019 perst-gpios = <&tlmm !! 1980 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 1981 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 1982
2022 pinctrl-names = "defa 1983 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 1984 pinctrl-0 = <&pcie1_default_state>;
2024 1985
2025 status = "disabled"; 1986 status = "disabled";
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; 1987 };
2037 1988
2038 pcie1_phy: phy@1c0e000 { 1989 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 1990 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 !! 1991 reg = <0 0x01c0e000 0 0x1c0>;
>> 1992 #address-cells = <2>;
>> 1993 #size-cells = <2>;
>> 1994 ranges;
2041 clocks = <&gcc GCC_PC 1995 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 1996 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC !! 1997 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2044 <&gcc GCC_PC !! 1998 clock-names = "aux", "cfg_ahb", "refgen";
2045 <&gcc GCC_PC <<
2046 clock-names = "aux", <<
2047 "cfg_ah <<
2048 "ref", <<
2049 "refgen <<
2050 "pipe"; <<
2051 <<
2052 clock-output-names = <<
2053 #clock-cells = <0>; <<
2054 <<
2055 #phy-cells = <0>; <<
2056 1999
2057 resets = <&gcc GCC_PC 2000 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 2001 reset-names = "phy";
2059 2002
2060 assigned-clocks = <&g 2003 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 2004 assigned-clock-rates = <100000000>;
2062 2005
2063 status = "disabled"; 2006 status = "disabled";
>> 2007
>> 2008 pcie1_lane: phy@1c0e200 {
>> 2009 reg = <0 0x01c0e200 0 0x170>, /* tx0 */
>> 2010 <0 0x01c0e400 0 0x200>, /* rx0 */
>> 2011 <0 0x01c0ea00 0 0x1f0>, /* pcs */
>> 2012 <0 0x01c0e600 0 0x170>, /* tx1 */
>> 2013 <0 0x01c0e800 0 0x200>, /* rx1 */
>> 2014 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2015 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2016 clock-names = "pipe0";
>> 2017
>> 2018 #phy-cells = <0>;
>> 2019 clock-output-names = "pcie_1_pipe_clk";
>> 2020 };
2064 }; 2021 };
2065 2022
2066 ufs_mem_hc: ufshc@1d84000 { 2023 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 2024 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 2025 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 2026 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 2027 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 2028 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 2029 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> !! 2030 phys = <&ufs_mem_phy_lanes>;
2074 phy-names = "ufsphy"; 2031 phy-names = "ufsphy";
2075 lanes-per-direction = 2032 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 2033 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 2034 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 2035 reset-names = "rst";
2079 2036
2080 iommus = <&apps_smmu 2037 iommus = <&apps_smmu 0x300 0>;
2081 2038
2082 clock-names = 2039 clock-names =
2083 "core_clk", 2040 "core_clk",
2084 "bus_aggr_clk 2041 "bus_aggr_clk",
2085 "iface_clk", 2042 "iface_clk",
2086 "core_clk_uni 2043 "core_clk_unipro",
2087 "ref_clk", 2044 "ref_clk",
2088 "tx_lane0_syn 2045 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 2046 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 2047 "rx_lane1_sync_clk",
2091 "ice_core_clk 2048 "ice_core_clk";
2092 clocks = 2049 clocks =
2093 <&gcc GCC_UFS 2050 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 2051 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 2052 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 2053 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 2054 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 2055 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2056 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2057 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2058 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2059 freq-table-hz =
2103 <37500000 300 2060 <37500000 300000000>,
2104 <0 0>, 2061 <0 0>,
2105 <0 0>, 2062 <0 0>,
2106 <37500000 300 2063 <37500000 300000000>,
2107 <0 0>, 2064 <0 0>,
2108 <0 0>, 2065 <0 0>,
2109 <0 0>, 2066 <0 0>,
2110 <0 0>, 2067 <0 0>,
2111 <0 300000000> 2068 <0 300000000>;
2112 2069
2113 status = "disabled"; 2070 status = "disabled";
2114 }; 2071 };
2115 2072
2116 ufs_mem_phy: phy@1d87000 { 2073 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2074 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 !! 2075 reg = <0 0x01d87000 0 0x1c0>;
2119 !! 2076 #address-cells = <2>;
2120 clocks = <&rpmhcc RPM !! 2077 #size-cells = <2>;
2121 <&gcc GCC_UF !! 2078 ranges;
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 2079 clock-names = "ref",
2124 "ref_au !! 2080 "ref_aux";
2125 "qref"; !! 2081 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>> 2082 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2126 2083
2127 power-domains = <&gcc 2084 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2085
2129 resets = <&ufs_mem_hc 2086 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2087 reset-names = "ufsphy";
2131 <<
2132 #phy-cells = <0>; <<
2133 <<
2134 status = "disabled"; 2088 status = "disabled";
2135 }; <<
2136 2089
2137 cryptobam: dma-controller@1dc !! 2090 ufs_mem_phy_lanes: phy@1d87400 {
2138 compatible = "qcom,ba !! 2091 reg = <0 0x01d87400 0 0x16c>,
2139 reg = <0 0x01dc4000 0 !! 2092 <0 0x01d87600 0 0x200>,
2140 interrupts = <GIC_SPI !! 2093 <0 0x01d87c00 0 0x200>,
2141 #dma-cells = <1>; !! 2094 <0 0x01d87800 0 0x16c>,
2142 qcom,ee = <0>; !! 2095 <0 0x01d87a00 0 0x200>;
2143 qcom,controlled-remot !! 2096 #phy-cells = <0>;
2144 num-channels = <8>; !! 2097 };
2145 qcom,num-ees = <2>; <<
2146 iommus = <&apps_smmu <<
2147 <&apps_smmu <<
2148 <&apps_smmu <<
2149 <&apps_smmu <<
2150 <&apps_smmu <<
2151 }; <<
2152 <<
2153 crypto: crypto@1dfa000 { <<
2154 compatible = "qcom,sm <<
2155 reg = <0 0x01dfa000 0 <<
2156 dmas = <&cryptobam 4> <<
2157 dma-names = "rx", "tx <<
2158 iommus = <&apps_smmu <<
2159 <&apps_smmu <<
2160 <&apps_smmu <<
2161 <&apps_smmu <<
2162 <&apps_smmu <<
2163 interconnects = <&agg <<
2164 interconnect-names = <<
2165 }; 2098 };
2166 2099
2167 tcsr_mutex: hwlock@1f40000 { 2100 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc 2101 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 2102 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>; 2103 #hwlock-cells = <1>;
2171 }; 2104 };
2172 2105
2173 tcsr_regs_1: syscon@1f60000 { 2106 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm 2107 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 2108 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 }; 2109 };
2177 2110
2178 remoteproc_slpi: remoteproc@2 2111 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2112 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2113 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2114
2182 interrupts-extended = 2115 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2116 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2117 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2118 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2119 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2120 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2121 "handover", "stop-ack";
2189 2122
2190 clocks = <&rpmhcc RPM 2123 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2124 clock-names = "xo";
2192 2125
2193 power-domains = <&rpm 2126 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpm 2127 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = 2128 power-domain-names = "lcx", "lmx";
2196 2129
2197 memory-region = <&slp 2130 memory-region = <&slpi_mem>;
2198 2131
2199 qcom,qmp = <&aoss_qmp 2132 qcom,qmp = <&aoss_qmp>;
2200 2133
2201 qcom,smem-states = <& 2134 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2135 qcom,smem-state-names = "stop";
2203 2136
2204 status = "disabled"; 2137 status = "disabled";
2205 2138
2206 glink-edge { 2139 glink-edge {
2207 interrupts = 2140 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2141 label = "dsps";
2209 qcom,remote-p 2142 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2143 mboxes = <&apss_shared 24>;
2211 2144
2212 fastrpc { 2145 fastrpc {
2213 compa 2146 compatible = "qcom,fastrpc";
2214 qcom, 2147 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2148 label = "sdsp";
2216 qcom, 2149 qcom,non-secure-domain;
2217 #addr 2150 #address-cells = <1>;
2218 #size 2151 #size-cells = <0>;
2219 2152
2220 compu 2153 compute-cb@1 {
2221 2154 compatible = "qcom,fastrpc-compute-cb";
2222 2155 reg = <1>;
2223 2156 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2157 };
2225 2158
2226 compu 2159 compute-cb@2 {
2227 2160 compatible = "qcom,fastrpc-compute-cb";
2228 2161 reg = <2>;
2229 2162 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2163 };
2231 2164
2232 compu 2165 compute-cb@3 {
2233 2166 compatible = "qcom,fastrpc-compute-cb";
2234 2167 reg = <3>;
2235 2168 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2169 /* note: shared-cb = <4> in downstream */
2237 }; 2170 };
2238 }; 2171 };
2239 }; 2172 };
2240 }; 2173 };
2241 2174
2242 gpu: gpu@2c00000 { 2175 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad 2176 compatible = "qcom,adreno-640.1", "qcom,adreno";
2244 reg = <0 0x02c00000 0 2177 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2178 reg-names = "kgsl_3d0_reg_memory";
2246 2179
2247 interrupts = <GIC_SPI 2180 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2181
2249 iommus = <&adreno_smm 2182 iommus = <&adreno_smmu 0 0x401>;
2250 2183
2251 operating-points-v2 = 2184 operating-points-v2 = <&gpu_opp_table>;
2252 2185
2253 qcom,gmu = <&gmu>; 2186 qcom,gmu = <&gmu>;
2254 2187
2255 nvmem-cells = <&gpu_s 2188 nvmem-cells = <&gpu_speed_bin>;
2256 nvmem-cell-names = "s 2189 nvmem-cell-names = "speed_bin";
2257 #cooling-cells = <2>; <<
2258 2190
2259 status = "disabled"; 2191 status = "disabled";
2260 2192
2261 zap-shader { 2193 zap-shader {
2262 memory-region 2194 memory-region = <&gpu_mem>;
2263 }; 2195 };
2264 2196
2265 gpu_opp_table: opp-ta 2197 gpu_opp_table: opp-table {
2266 compatible = 2198 compatible = "operating-points-v2";
2267 2199
2268 opp-675000000 2200 opp-675000000 {
2269 opp-h 2201 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2202 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s 2203 opp-supported-hw = <0x2>;
2272 }; 2204 };
2273 2205
2274 opp-585000000 2206 opp-585000000 {
2275 opp-h 2207 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2208 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s 2209 opp-supported-hw = <0x3>;
2278 }; 2210 };
2279 2211
2280 opp-499200000 2212 opp-499200000 {
2281 opp-h 2213 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2214 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s 2215 opp-supported-hw = <0x3>;
2284 }; 2216 };
2285 2217
2286 opp-427000000 2218 opp-427000000 {
2287 opp-h 2219 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2220 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s 2221 opp-supported-hw = <0x3>;
2290 }; 2222 };
2291 2223
2292 opp-345000000 2224 opp-345000000 {
2293 opp-h 2225 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2226 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s 2227 opp-supported-hw = <0x3>;
2296 }; 2228 };
2297 2229
2298 opp-257000000 2230 opp-257000000 {
2299 opp-h 2231 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2232 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s 2233 opp-supported-hw = <0x3>;
2302 }; 2234 };
2303 }; 2235 };
2304 }; 2236 };
2305 2237
2306 gmu: gmu@2c6a000 { 2238 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad 2239 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2240
2309 reg = <0 0x02c6a000 0 2241 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2242 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2243 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2244 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2245
2314 interrupts = <GIC_SPI 2246 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2247 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2248 interrupt-names = "hfi", "gmu";
2317 2249
2318 clocks = <&gpucc GPU_ 2250 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2251 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2252 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2253 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2254 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2255 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2256
2325 power-domains = <&gpu 2257 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2258 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2259 power-domain-names = "cx", "gx";
2328 2260
2329 iommus = <&adreno_smm 2261 iommus = <&adreno_smmu 5 0x400>;
2330 2262
2331 operating-points-v2 = 2263 operating-points-v2 = <&gmu_opp_table>;
2332 2264
2333 status = "disabled"; 2265 status = "disabled";
2334 2266
2335 gmu_opp_table: opp-ta 2267 gmu_opp_table: opp-table {
2336 compatible = 2268 compatible = "operating-points-v2";
2337 2269
2338 opp-200000000 2270 opp-200000000 {
2339 opp-h 2271 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2272 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2273 };
2342 }; 2274 };
2343 }; 2275 };
2344 2276
2345 gpucc: clock-controller@2c900 2277 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2278 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2279 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2280 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2281 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2282 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2283 clock-names = "bi_tcxo",
2352 "gcc_gp 2284 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2285 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2286 #clock-cells = <1>;
2355 #reset-cells = <1>; 2287 #reset-cells = <1>;
2356 #power-domain-cells = 2288 #power-domain-cells = <1>;
2357 }; 2289 };
2358 2290
2359 adreno_smmu: iommu@2ca0000 { 2291 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm 2292 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2361 "qcom,sm 2293 "qcom,smmu-500", "arm,mmu-500";
2362 reg = <0 0x02ca0000 0 2294 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2295 #iommu-cells = <2>;
2364 #global-interrupts = 2296 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2297 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2298 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2299 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2300 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2301 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2302 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2303 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2304 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2305 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2306 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2307 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2308 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2309 clock-names = "ahb", "bus", "iface";
2378 2310
2379 power-domains = <&gpu 2311 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2312 };
2381 2313
2382 tlmm: pinctrl@3100000 { 2314 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2315 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2316 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2317 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2318 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2319 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2320 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2321 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2322 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2323 gpio-controller;
2392 #gpio-cells = <2>; 2324 #gpio-cells = <2>;
2393 interrupt-controller; 2325 interrupt-controller;
2394 #interrupt-cells = <2 2326 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2327 wakeup-parent = <&pdc>;
2396 2328
2397 qup_i2c0_default: qup 2329 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0 2330 pins = "gpio0", "gpio1";
2399 function = "q 2331 function = "qup0";
2400 drive-strengt 2332 drive-strength = <0x02>;
2401 bias-disable; 2333 bias-disable;
2402 }; 2334 };
2403 2335
2404 qup_spi0_default: qup 2336 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0 2337 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2338 function = "qup0";
2407 drive-strengt 2339 drive-strength = <6>;
2408 bias-disable; 2340 bias-disable;
2409 }; 2341 };
2410 2342
2411 qup_i2c1_default: qup 2343 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio1 2344 pins = "gpio114", "gpio115";
2413 function = "q 2345 function = "qup1";
2414 drive-strengt 2346 drive-strength = <2>;
2415 bias-disable; 2347 bias-disable;
2416 }; 2348 };
2417 2349
2418 qup_spi1_default: qup 2350 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio1 2351 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2352 function = "qup1";
2421 drive-strengt 2353 drive-strength = <6>;
2422 bias-disable; 2354 bias-disable;
2423 }; 2355 };
2424 2356
2425 qup_i2c2_default: qup 2357 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio1 2358 pins = "gpio126", "gpio127";
2427 function = "q 2359 function = "qup2";
2428 drive-strengt 2360 drive-strength = <2>;
2429 bias-disable; 2361 bias-disable;
2430 }; 2362 };
2431 2363
2432 qup_spi2_default: qup 2364 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio1 2365 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2366 function = "qup2";
2435 drive-strengt 2367 drive-strength = <6>;
2436 bias-disable; 2368 bias-disable;
2437 }; 2369 };
2438 2370
2439 qup_i2c3_default: qup 2371 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio1 2372 pins = "gpio144", "gpio145";
2441 function = "q 2373 function = "qup3";
2442 drive-strengt 2374 drive-strength = <2>;
2443 bias-disable; 2375 bias-disable;
2444 }; 2376 };
2445 2377
2446 qup_spi3_default: qup 2378 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio1 2379 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2380 function = "qup3";
2449 drive-strengt 2381 drive-strength = <6>;
2450 bias-disable; 2382 bias-disable;
2451 }; 2383 };
2452 2384
2453 qup_i2c4_default: qup 2385 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio5 2386 pins = "gpio51", "gpio52";
2455 function = "q 2387 function = "qup4";
2456 drive-strengt 2388 drive-strength = <2>;
2457 bias-disable; 2389 bias-disable;
2458 }; 2390 };
2459 2391
2460 qup_spi4_default: qup 2392 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio5 2393 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2394 function = "qup4";
2463 drive-strengt 2395 drive-strength = <6>;
2464 bias-disable; 2396 bias-disable;
2465 }; 2397 };
2466 2398
2467 qup_i2c5_default: qup 2399 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio1 2400 pins = "gpio121", "gpio122";
2469 function = "q 2401 function = "qup5";
2470 drive-strengt 2402 drive-strength = <2>;
2471 bias-disable; 2403 bias-disable;
2472 }; 2404 };
2473 2405
2474 qup_spi5_default: qup 2406 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio1 2407 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2408 function = "qup5";
2477 drive-strengt 2409 drive-strength = <6>;
2478 bias-disable; 2410 bias-disable;
2479 }; 2411 };
2480 2412
2481 qup_i2c6_default: qup 2413 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6 2414 pins = "gpio6", "gpio7";
2483 function = "q 2415 function = "qup6";
2484 drive-strengt 2416 drive-strength = <2>;
2485 bias-disable; 2417 bias-disable;
2486 }; 2418 };
2487 2419
2488 qup_spi6_default: qup !! 2420 qup_spi6_default: qup-spi6_default-state {
2489 pins = "gpio4 2421 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2422 function = "qup6";
2491 drive-strengt 2423 drive-strength = <6>;
2492 bias-disable; 2424 bias-disable;
2493 }; 2425 };
2494 2426
2495 qup_i2c7_default: qup 2427 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio9 2428 pins = "gpio98", "gpio99";
2497 function = "q 2429 function = "qup7";
2498 drive-strengt 2430 drive-strength = <2>;
2499 bias-disable; 2431 bias-disable;
2500 }; 2432 };
2501 2433
2502 qup_spi7_default: qup !! 2434 qup_spi7_default: qup-spi7_default-state {
2503 pins = "gpio9 2435 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2436 function = "qup7";
2505 drive-strengt 2437 drive-strength = <6>;
2506 bias-disable; 2438 bias-disable;
2507 }; 2439 };
2508 2440
2509 qup_i2c8_default: qup 2441 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio8 2442 pins = "gpio88", "gpio89";
2511 function = "q 2443 function = "qup8";
2512 drive-strengt 2444 drive-strength = <2>;
2513 bias-disable; 2445 bias-disable;
2514 }; 2446 };
2515 2447
2516 qup_spi8_default: qup 2448 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio8 2449 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2450 function = "qup8";
2519 drive-strengt 2451 drive-strength = <6>;
2520 bias-disable; 2452 bias-disable;
2521 }; 2453 };
2522 2454
2523 qup_i2c9_default: qup 2455 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio3 2456 pins = "gpio39", "gpio40";
2525 function = "q 2457 function = "qup9";
2526 drive-strengt 2458 drive-strength = <2>;
2527 bias-disable; 2459 bias-disable;
2528 }; 2460 };
2529 2461
2530 qup_spi9_default: qup 2462 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio3 2463 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2464 function = "qup9";
2533 drive-strengt 2465 drive-strength = <6>;
2534 bias-disable; 2466 bias-disable;
2535 }; 2467 };
2536 2468
2537 qup_uart9_default: qu 2469 qup_uart9_default: qup-uart9-default-state {
2538 pins = "gpio4 2470 pins = "gpio41", "gpio42";
2539 function = "q 2471 function = "qup9";
2540 drive-strengt 2472 drive-strength = <2>;
2541 bias-disable; 2473 bias-disable;
2542 }; 2474 };
2543 2475
2544 qup_i2c10_default: qu 2476 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9 2477 pins = "gpio9", "gpio10";
2546 function = "q 2478 function = "qup10";
2547 drive-strengt 2479 drive-strength = <2>;
2548 bias-disable; 2480 bias-disable;
2549 }; 2481 };
2550 2482
2551 qup_spi10_default: qu 2483 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9 2484 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2485 function = "qup10";
2554 drive-strengt 2486 drive-strength = <6>;
2555 bias-disable; 2487 bias-disable;
2556 }; 2488 };
2557 2489
2558 qup_i2c11_default: qu 2490 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio9 2491 pins = "gpio94", "gpio95";
2560 function = "q 2492 function = "qup11";
2561 drive-strengt 2493 drive-strength = <2>;
2562 bias-disable; 2494 bias-disable;
2563 }; 2495 };
2564 2496
2565 qup_spi11_default: qu 2497 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio9 2498 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2499 function = "qup11";
2568 drive-strengt 2500 drive-strength = <6>;
2569 bias-disable; 2501 bias-disable;
2570 }; 2502 };
2571 2503
2572 qup_i2c12_default: qu 2504 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio8 2505 pins = "gpio83", "gpio84";
2574 function = "q 2506 function = "qup12";
2575 drive-strengt 2507 drive-strength = <2>;
2576 bias-disable; 2508 bias-disable;
2577 }; 2509 };
2578 2510
2579 qup_spi12_default: qu 2511 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio8 2512 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2513 function = "qup12";
2582 drive-strengt 2514 drive-strength = <6>;
2583 bias-disable; 2515 bias-disable;
2584 }; 2516 };
2585 2517
2586 qup_i2c13_default: qu 2518 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio4 2519 pins = "gpio43", "gpio44";
2588 function = "q 2520 function = "qup13";
2589 drive-strengt 2521 drive-strength = <2>;
2590 bias-disable; 2522 bias-disable;
2591 }; 2523 };
2592 2524
2593 qup_spi13_default: qu 2525 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio4 2526 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2527 function = "qup13";
2596 drive-strengt 2528 drive-strength = <6>;
2597 bias-disable; 2529 bias-disable;
2598 }; 2530 };
2599 2531
2600 qup_i2c14_default: qu 2532 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio4 2533 pins = "gpio47", "gpio48";
2602 function = "q 2534 function = "qup14";
2603 drive-strengt 2535 drive-strength = <2>;
2604 bias-disable; 2536 bias-disable;
2605 }; 2537 };
2606 2538
2607 qup_spi14_default: qu 2539 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio4 2540 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2541 function = "qup14";
2610 drive-strengt 2542 drive-strength = <6>;
2611 bias-disable; 2543 bias-disable;
2612 }; 2544 };
2613 2545
2614 qup_i2c15_default: qu 2546 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio2 2547 pins = "gpio27", "gpio28";
2616 function = "q 2548 function = "qup15";
2617 drive-strengt 2549 drive-strength = <2>;
2618 bias-disable; 2550 bias-disable;
2619 }; 2551 };
2620 2552
2621 qup_spi15_default: qu 2553 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio2 2554 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2555 function = "qup15";
2624 drive-strengt 2556 drive-strength = <6>;
2625 bias-disable; 2557 bias-disable;
2626 }; 2558 };
2627 2559
2628 qup_i2c16_default: qu 2560 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio8 2561 pins = "gpio86", "gpio85";
2630 function = "q 2562 function = "qup16";
2631 drive-strengt 2563 drive-strength = <2>;
2632 bias-disable; 2564 bias-disable;
2633 }; 2565 };
2634 2566
2635 qup_spi16_default: qu 2567 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio8 2568 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2569 function = "qup16";
2638 drive-strengt 2570 drive-strength = <6>;
2639 bias-disable; 2571 bias-disable;
2640 }; 2572 };
2641 2573
2642 qup_i2c17_default: qu 2574 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio5 2575 pins = "gpio55", "gpio56";
2644 function = "q 2576 function = "qup17";
2645 drive-strengt 2577 drive-strength = <2>;
2646 bias-disable; 2578 bias-disable;
2647 }; 2579 };
2648 2580
2649 qup_spi17_default: qu 2581 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio5 2582 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2583 function = "qup17";
2652 drive-strengt 2584 drive-strength = <6>;
2653 bias-disable; 2585 bias-disable;
2654 }; 2586 };
2655 2587
2656 qup_i2c18_default: qu 2588 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio2 2589 pins = "gpio23", "gpio24";
2658 function = "q 2590 function = "qup18";
2659 drive-strengt 2591 drive-strength = <2>;
2660 bias-disable; 2592 bias-disable;
2661 }; 2593 };
2662 2594
2663 qup_spi18_default: qu 2595 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio2 2596 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2597 function = "qup18";
2666 drive-strengt 2598 drive-strength = <6>;
2667 bias-disable; 2599 bias-disable;
2668 }; 2600 };
2669 2601
2670 qup_i2c19_default: qu 2602 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio5 2603 pins = "gpio57", "gpio58";
2672 function = "q 2604 function = "qup19";
2673 drive-strengt 2605 drive-strength = <2>;
2674 bias-disable; 2606 bias-disable;
2675 }; 2607 };
2676 2608
2677 qup_spi19_default: qu 2609 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio5 2610 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2611 function = "qup19";
2680 drive-strengt 2612 drive-strength = <6>;
2681 bias-disable; 2613 bias-disable;
2682 }; 2614 };
2683 2615
2684 pcie0_default_state: 2616 pcie0_default_state: pcie0-default-state {
2685 perst-pins { 2617 perst-pins {
2686 pins 2618 pins = "gpio35";
2687 funct 2619 function = "gpio";
2688 drive 2620 drive-strength = <2>;
2689 bias- 2621 bias-pull-down;
2690 }; 2622 };
2691 2623
2692 clkreq-pins { 2624 clkreq-pins {
2693 pins 2625 pins = "gpio36";
2694 funct 2626 function = "pci_e0";
2695 drive 2627 drive-strength = <2>;
2696 bias- 2628 bias-pull-up;
2697 }; 2629 };
2698 2630
2699 wake-pins { 2631 wake-pins {
2700 pins 2632 pins = "gpio37";
2701 funct 2633 function = "gpio";
2702 drive 2634 drive-strength = <2>;
2703 bias- 2635 bias-pull-up;
2704 }; 2636 };
2705 }; 2637 };
2706 2638
2707 pcie1_default_state: 2639 pcie1_default_state: pcie1-default-state {
2708 perst-pins { 2640 perst-pins {
2709 pins 2641 pins = "gpio102";
2710 funct 2642 function = "gpio";
2711 drive 2643 drive-strength = <2>;
2712 bias- 2644 bias-pull-down;
2713 }; 2645 };
2714 2646
2715 clkreq-pins { 2647 clkreq-pins {
2716 pins 2648 pins = "gpio103";
2717 funct 2649 function = "pci_e1";
2718 drive 2650 drive-strength = <2>;
2719 bias- 2651 bias-pull-up;
2720 }; 2652 };
2721 2653
2722 wake-pins { 2654 wake-pins {
2723 pins 2655 pins = "gpio104";
2724 funct 2656 function = "gpio";
2725 drive 2657 drive-strength = <2>;
2726 bias- 2658 bias-pull-up;
2727 }; 2659 };
2728 }; 2660 };
2729 }; 2661 };
2730 2662
2731 remoteproc_mpss: remoteproc@4 2663 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2664 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2665 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2666
2735 interrupts-extended = 2667 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2668 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2669 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2670 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2671 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2672 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2673 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2674 "stop-ack", "shutdown-ack";
2743 2675
2744 clocks = <&rpmhcc RPM 2676 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2677 clock-names = "xo";
2746 2678
2747 power-domains = <&rpm 2679 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpm 2680 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = 2681 power-domain-names = "cx", "mss";
2750 2682
2751 memory-region = <&mps 2683 memory-region = <&mpss_mem>;
2752 2684
2753 qcom,qmp = <&aoss_qmp 2685 qcom,qmp = <&aoss_qmp>;
2754 2686
2755 qcom,smem-states = <& 2687 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2688 qcom,smem-state-names = "stop";
2757 2689
2758 status = "disabled"; 2690 status = "disabled";
2759 2691
2760 glink-edge { 2692 glink-edge {
2761 interrupts = 2693 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2694 label = "modem";
2763 qcom,remote-p 2695 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2696 mboxes = <&apss_shared 12>;
2765 }; 2697 };
2766 }; 2698 };
2767 2699
2768 stm@6002000 { 2700 stm@6002000 {
2769 compatible = "arm,cor 2701 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2702 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2703 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2704 reg-names = "stm-base", "stm-stimulus-base";
2773 2705
2774 clocks = <&aoss_qmp>; 2706 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2707 clock-names = "apb_pclk";
2776 2708
2777 out-ports { 2709 out-ports {
2778 port { 2710 port {
2779 stm_o 2711 stm_out: endpoint {
2780 2712 remote-endpoint = <&funnel0_in7>;
2781 }; 2713 };
2782 }; 2714 };
2783 }; 2715 };
2784 }; 2716 };
2785 2717
2786 funnel@6041000 { 2718 funnel@6041000 {
2787 compatible = "arm,cor 2719 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2720 reg = <0 0x06041000 0 0x1000>;
2789 2721
2790 clocks = <&aoss_qmp>; 2722 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2723 clock-names = "apb_pclk";
2792 2724
2793 out-ports { 2725 out-ports {
2794 port { 2726 port {
2795 funne 2727 funnel0_out: endpoint {
2796 2728 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2729 };
2798 }; 2730 };
2799 }; 2731 };
2800 2732
2801 in-ports { 2733 in-ports {
2802 #address-cell 2734 #address-cells = <1>;
2803 #size-cells = 2735 #size-cells = <0>;
2804 2736
2805 port@7 { 2737 port@7 {
2806 reg = 2738 reg = <7>;
2807 funne 2739 funnel0_in7: endpoint {
2808 2740 remote-endpoint = <&stm_out>;
2809 }; 2741 };
2810 }; 2742 };
2811 }; 2743 };
2812 }; 2744 };
2813 2745
2814 funnel@6042000 { 2746 funnel@6042000 {
2815 compatible = "arm,cor 2747 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2748 reg = <0 0x06042000 0 0x1000>;
2817 2749
2818 clocks = <&aoss_qmp>; 2750 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2751 clock-names = "apb_pclk";
2820 2752
2821 out-ports { 2753 out-ports {
2822 port { 2754 port {
2823 funne 2755 funnel1_out: endpoint {
2824 2756 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2757 };
2826 }; 2758 };
2827 }; 2759 };
2828 2760
2829 in-ports { 2761 in-ports {
2830 #address-cell 2762 #address-cells = <1>;
2831 #size-cells = 2763 #size-cells = <0>;
2832 2764
2833 port@4 { 2765 port@4 {
2834 reg = 2766 reg = <4>;
2835 funne 2767 funnel1_in4: endpoint {
2836 2768 remote-endpoint = <&swao_replicator_out>;
2837 }; 2769 };
2838 }; 2770 };
2839 }; 2771 };
2840 }; 2772 };
2841 2773
2842 funnel@6043000 { 2774 funnel@6043000 {
2843 compatible = "arm,cor 2775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2776 reg = <0 0x06043000 0 0x1000>;
2845 2777
2846 clocks = <&aoss_qmp>; 2778 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2779 clock-names = "apb_pclk";
2848 2780
2849 out-ports { 2781 out-ports {
2850 port { 2782 port {
2851 funne 2783 funnel2_out: endpoint {
2852 2784 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2785 };
2854 }; 2786 };
2855 }; 2787 };
2856 2788
2857 in-ports { 2789 in-ports {
2858 #address-cell 2790 #address-cells = <1>;
2859 #size-cells = 2791 #size-cells = <0>;
2860 2792
2861 port@2 { 2793 port@2 {
2862 reg = 2794 reg = <2>;
2863 funne 2795 funnel2_in2: endpoint {
2864 2796 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2797 };
2866 }; 2798 };
2867 }; 2799 };
2868 }; 2800 };
2869 2801
2870 funnel@6045000 { 2802 funnel@6045000 {
2871 compatible = "arm,cor 2803 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2804 reg = <0 0x06045000 0 0x1000>;
2873 2805
2874 clocks = <&aoss_qmp>; 2806 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2807 clock-names = "apb_pclk";
2876 2808
2877 out-ports { 2809 out-ports {
2878 port { 2810 port {
2879 merge 2811 merge_funnel_out: endpoint {
2880 2812 remote-endpoint = <&etf_in>;
2881 }; 2813 };
2882 }; 2814 };
2883 }; 2815 };
2884 2816
2885 in-ports { 2817 in-ports {
2886 #address-cell 2818 #address-cells = <1>;
2887 #size-cells = 2819 #size-cells = <0>;
2888 2820
2889 port@0 { 2821 port@0 {
2890 reg = 2822 reg = <0>;
2891 merge 2823 merge_funnel_in0: endpoint {
2892 2824 remote-endpoint = <&funnel0_out>;
2893 }; 2825 };
2894 }; 2826 };
2895 2827
2896 port@1 { 2828 port@1 {
2897 reg = 2829 reg = <1>;
2898 merge 2830 merge_funnel_in1: endpoint {
2899 2831 remote-endpoint = <&funnel1_out>;
2900 }; 2832 };
2901 }; 2833 };
2902 2834
2903 port@2 { 2835 port@2 {
2904 reg = 2836 reg = <2>;
2905 merge 2837 merge_funnel_in2: endpoint {
2906 2838 remote-endpoint = <&funnel2_out>;
2907 }; 2839 };
2908 }; 2840 };
2909 }; 2841 };
2910 }; 2842 };
2911 2843
2912 replicator@6046000 { 2844 replicator@6046000 {
2913 compatible = "arm,cor 2845 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2846 reg = <0 0x06046000 0 0x1000>;
2915 2847
2916 clocks = <&aoss_qmp>; 2848 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2849 clock-names = "apb_pclk";
2918 2850
2919 out-ports { 2851 out-ports {
2920 #address-cell 2852 #address-cells = <1>;
2921 #size-cells = 2853 #size-cells = <0>;
2922 2854
2923 port@0 { 2855 port@0 {
2924 reg = 2856 reg = <0>;
2925 repli 2857 replicator_out0: endpoint {
2926 2858 remote-endpoint = <&etr_in>;
2927 }; 2859 };
2928 }; 2860 };
2929 2861
2930 port@1 { 2862 port@1 {
2931 reg = 2863 reg = <1>;
2932 repli 2864 replicator_out1: endpoint {
2933 2865 remote-endpoint = <&replicator1_in>;
2934 }; 2866 };
2935 }; 2867 };
2936 }; 2868 };
2937 2869
2938 in-ports { 2870 in-ports {
2939 port { 2871 port {
2940 repli 2872 replicator_in0: endpoint {
2941 2873 remote-endpoint = <&etf_out>;
2942 }; 2874 };
2943 }; 2875 };
2944 }; 2876 };
2945 }; 2877 };
2946 2878
2947 etf@6047000 { 2879 etf@6047000 {
2948 compatible = "arm,cor 2880 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2881 reg = <0 0x06047000 0 0x1000>;
2950 2882
2951 clocks = <&aoss_qmp>; 2883 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2884 clock-names = "apb_pclk";
2953 2885
2954 out-ports { 2886 out-ports {
2955 port { 2887 port {
2956 etf_o 2888 etf_out: endpoint {
2957 2889 remote-endpoint = <&replicator_in0>;
2958 }; 2890 };
2959 }; 2891 };
2960 }; 2892 };
2961 2893
2962 in-ports { 2894 in-ports {
2963 port { 2895 port {
2964 etf_i 2896 etf_in: endpoint {
2965 2897 remote-endpoint = <&merge_funnel_out>;
2966 }; 2898 };
2967 }; 2899 };
2968 }; 2900 };
2969 }; 2901 };
2970 2902
2971 etr@6048000 { 2903 etr@6048000 {
2972 compatible = "arm,cor 2904 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2905 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2906 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2907
2976 clocks = <&aoss_qmp>; 2908 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2909 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2910 arm,scatter-gather;
2979 2911
2980 in-ports { 2912 in-ports {
2981 port { 2913 port {
2982 etr_i 2914 etr_in: endpoint {
2983 2915 remote-endpoint = <&replicator_out0>;
2984 }; 2916 };
2985 }; 2917 };
2986 }; 2918 };
2987 }; 2919 };
2988 2920
2989 replicator@604a000 { 2921 replicator@604a000 {
2990 compatible = "arm,cor 2922 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2923 reg = <0 0x0604a000 0 0x1000>;
2992 2924
2993 clocks = <&aoss_qmp>; 2925 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2926 clock-names = "apb_pclk";
2995 2927
2996 out-ports { 2928 out-ports {
2997 #address-cell 2929 #address-cells = <1>;
2998 #size-cells = 2930 #size-cells = <0>;
2999 2931
3000 port@1 { 2932 port@1 {
3001 reg = 2933 reg = <1>;
3002 repli 2934 replicator1_out: endpoint {
3003 2935 remote-endpoint = <&swao_funnel_in>;
3004 }; 2936 };
3005 }; 2937 };
3006 }; 2938 };
3007 2939
3008 in-ports { 2940 in-ports {
>> 2941 #address-cells = <1>;
>> 2942 #size-cells = <0>;
3009 2943
3010 port { !! 2944 port@1 {
>> 2945 reg = <1>;
3011 repli 2946 replicator1_in: endpoint {
3012 2947 remote-endpoint = <&replicator_out1>;
3013 }; 2948 };
3014 }; 2949 };
3015 }; 2950 };
3016 }; 2951 };
3017 2952
3018 funnel@6b08000 { 2953 funnel@6b08000 {
3019 compatible = "arm,cor 2954 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2955 reg = <0 0x06b08000 0 0x1000>;
3021 2956
3022 clocks = <&aoss_qmp>; 2957 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2958 clock-names = "apb_pclk";
3024 2959
3025 out-ports { 2960 out-ports {
3026 port { 2961 port {
3027 swao_ 2962 swao_funnel_out: endpoint {
3028 2963 remote-endpoint = <&swao_etf_in>;
3029 }; 2964 };
3030 }; 2965 };
3031 }; 2966 };
3032 2967
3033 in-ports { 2968 in-ports {
3034 #address-cell 2969 #address-cells = <1>;
3035 #size-cells = 2970 #size-cells = <0>;
3036 2971
3037 port@6 { 2972 port@6 {
3038 reg = 2973 reg = <6>;
3039 swao_ 2974 swao_funnel_in: endpoint {
3040 2975 remote-endpoint = <&replicator1_out>;
3041 }; 2976 };
3042 }; 2977 };
3043 }; 2978 };
3044 }; 2979 };
3045 2980
3046 etf@6b09000 { 2981 etf@6b09000 {
3047 compatible = "arm,cor 2982 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2983 reg = <0 0x06b09000 0 0x1000>;
3049 2984
3050 clocks = <&aoss_qmp>; 2985 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2986 clock-names = "apb_pclk";
3052 2987
3053 out-ports { 2988 out-ports {
3054 port { 2989 port {
3055 swao_ 2990 swao_etf_out: endpoint {
3056 2991 remote-endpoint = <&swao_replicator_in>;
3057 }; 2992 };
3058 }; 2993 };
3059 }; 2994 };
3060 2995
3061 in-ports { 2996 in-ports {
3062 port { 2997 port {
3063 swao_ 2998 swao_etf_in: endpoint {
3064 2999 remote-endpoint = <&swao_funnel_out>;
3065 }; 3000 };
3066 }; 3001 };
3067 }; 3002 };
3068 }; 3003 };
3069 3004
3070 replicator@6b0a000 { 3005 replicator@6b0a000 {
3071 compatible = "arm,cor 3006 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 3007 reg = <0 0x06b0a000 0 0x1000>;
3073 3008
3074 clocks = <&aoss_qmp>; 3009 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 3010 clock-names = "apb_pclk";
3076 qcom,replicator-loses 3011 qcom,replicator-loses-context;
3077 3012
3078 out-ports { 3013 out-ports {
3079 port { 3014 port {
3080 swao_ 3015 swao_replicator_out: endpoint {
3081 3016 remote-endpoint = <&funnel1_in4>;
3082 }; 3017 };
3083 }; 3018 };
3084 }; 3019 };
3085 3020
3086 in-ports { 3021 in-ports {
3087 port { 3022 port {
3088 swao_ 3023 swao_replicator_in: endpoint {
3089 3024 remote-endpoint = <&swao_etf_out>;
3090 }; 3025 };
3091 }; 3026 };
3092 }; 3027 };
3093 }; 3028 };
3094 3029
3095 etm@7040000 { 3030 etm@7040000 {
3096 compatible = "arm,cor 3031 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 3032 reg = <0 0x07040000 0 0x1000>;
3098 3033
3099 cpu = <&CPU0>; 3034 cpu = <&CPU0>;
3100 3035
3101 clocks = <&aoss_qmp>; 3036 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 3037 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 3038 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 3039 qcom,skip-power-up;
3105 3040
3106 out-ports { 3041 out-ports {
3107 port { 3042 port {
3108 etm0_ 3043 etm0_out: endpoint {
3109 3044 remote-endpoint = <&apss_funnel_in0>;
3110 }; 3045 };
3111 }; 3046 };
3112 }; 3047 };
3113 }; 3048 };
3114 3049
3115 etm@7140000 { 3050 etm@7140000 {
3116 compatible = "arm,cor 3051 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 3052 reg = <0 0x07140000 0 0x1000>;
3118 3053
3119 cpu = <&CPU1>; 3054 cpu = <&CPU1>;
3120 3055
3121 clocks = <&aoss_qmp>; 3056 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3057 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3058 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3059 qcom,skip-power-up;
3125 3060
3126 out-ports { 3061 out-ports {
3127 port { 3062 port {
3128 etm1_ 3063 etm1_out: endpoint {
3129 3064 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3065 };
3131 }; 3066 };
3132 }; 3067 };
3133 }; 3068 };
3134 3069
3135 etm@7240000 { 3070 etm@7240000 {
3136 compatible = "arm,cor 3071 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3072 reg = <0 0x07240000 0 0x1000>;
3138 3073
3139 cpu = <&CPU2>; 3074 cpu = <&CPU2>;
3140 3075
3141 clocks = <&aoss_qmp>; 3076 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3077 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3078 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3079 qcom,skip-power-up;
3145 3080
3146 out-ports { 3081 out-ports {
3147 port { 3082 port {
3148 etm2_ 3083 etm2_out: endpoint {
3149 3084 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3085 };
3151 }; 3086 };
3152 }; 3087 };
3153 }; 3088 };
3154 3089
3155 etm@7340000 { 3090 etm@7340000 {
3156 compatible = "arm,cor 3091 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3092 reg = <0 0x07340000 0 0x1000>;
3158 3093
3159 cpu = <&CPU3>; 3094 cpu = <&CPU3>;
3160 3095
3161 clocks = <&aoss_qmp>; 3096 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3097 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3098 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3099 qcom,skip-power-up;
3165 3100
3166 out-ports { 3101 out-ports {
3167 port { 3102 port {
3168 etm3_ 3103 etm3_out: endpoint {
3169 3104 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3105 };
3171 }; 3106 };
3172 }; 3107 };
3173 }; 3108 };
3174 3109
3175 etm@7440000 { 3110 etm@7440000 {
3176 compatible = "arm,cor 3111 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3112 reg = <0 0x07440000 0 0x1000>;
3178 3113
3179 cpu = <&CPU4>; 3114 cpu = <&CPU4>;
3180 3115
3181 clocks = <&aoss_qmp>; 3116 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3117 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3118 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3119 qcom,skip-power-up;
3185 3120
3186 out-ports { 3121 out-ports {
3187 port { 3122 port {
3188 etm4_ 3123 etm4_out: endpoint {
3189 3124 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3125 };
3191 }; 3126 };
3192 }; 3127 };
3193 }; 3128 };
3194 3129
3195 etm@7540000 { 3130 etm@7540000 {
3196 compatible = "arm,cor 3131 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3132 reg = <0 0x07540000 0 0x1000>;
3198 3133
3199 cpu = <&CPU5>; 3134 cpu = <&CPU5>;
3200 3135
3201 clocks = <&aoss_qmp>; 3136 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3137 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3138 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3139 qcom,skip-power-up;
3205 3140
3206 out-ports { 3141 out-ports {
3207 port { 3142 port {
3208 etm5_ 3143 etm5_out: endpoint {
3209 3144 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3145 };
3211 }; 3146 };
3212 }; 3147 };
3213 }; 3148 };
3214 3149
3215 etm@7640000 { 3150 etm@7640000 {
3216 compatible = "arm,cor 3151 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3152 reg = <0 0x07640000 0 0x1000>;
3218 3153
3219 cpu = <&CPU6>; 3154 cpu = <&CPU6>;
3220 3155
3221 clocks = <&aoss_qmp>; 3156 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3157 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3158 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3159 qcom,skip-power-up;
3225 3160
3226 out-ports { 3161 out-ports {
3227 port { 3162 port {
3228 etm6_ 3163 etm6_out: endpoint {
3229 3164 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3165 };
3231 }; 3166 };
3232 }; 3167 };
3233 }; 3168 };
3234 3169
3235 etm@7740000 { 3170 etm@7740000 {
3236 compatible = "arm,cor 3171 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3172 reg = <0 0x07740000 0 0x1000>;
3238 3173
3239 cpu = <&CPU7>; 3174 cpu = <&CPU7>;
3240 3175
3241 clocks = <&aoss_qmp>; 3176 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3177 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3178 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3179 qcom,skip-power-up;
3245 3180
3246 out-ports { 3181 out-ports {
3247 port { 3182 port {
3248 etm7_ 3183 etm7_out: endpoint {
3249 3184 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3185 };
3251 }; 3186 };
3252 }; 3187 };
3253 }; 3188 };
3254 3189
3255 funnel@7800000 { /* APSS Funn 3190 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3191 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3192 reg = <0 0x07800000 0 0x1000>;
3258 3193
3259 clocks = <&aoss_qmp>; 3194 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3195 clock-names = "apb_pclk";
3261 3196
3262 out-ports { 3197 out-ports {
3263 port { 3198 port {
3264 apss_ 3199 apss_funnel_out: endpoint {
3265 3200 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3201 };
3267 }; 3202 };
3268 }; 3203 };
3269 3204
3270 in-ports { 3205 in-ports {
3271 #address-cell 3206 #address-cells = <1>;
3272 #size-cells = 3207 #size-cells = <0>;
3273 3208
3274 port@0 { 3209 port@0 {
3275 reg = 3210 reg = <0>;
3276 apss_ 3211 apss_funnel_in0: endpoint {
3277 3212 remote-endpoint = <&etm0_out>;
3278 }; 3213 };
3279 }; 3214 };
3280 3215
3281 port@1 { 3216 port@1 {
3282 reg = 3217 reg = <1>;
3283 apss_ 3218 apss_funnel_in1: endpoint {
3284 3219 remote-endpoint = <&etm1_out>;
3285 }; 3220 };
3286 }; 3221 };
3287 3222
3288 port@2 { 3223 port@2 {
3289 reg = 3224 reg = <2>;
3290 apss_ 3225 apss_funnel_in2: endpoint {
3291 3226 remote-endpoint = <&etm2_out>;
3292 }; 3227 };
3293 }; 3228 };
3294 3229
3295 port@3 { 3230 port@3 {
3296 reg = 3231 reg = <3>;
3297 apss_ 3232 apss_funnel_in3: endpoint {
3298 3233 remote-endpoint = <&etm3_out>;
3299 }; 3234 };
3300 }; 3235 };
3301 3236
3302 port@4 { 3237 port@4 {
3303 reg = 3238 reg = <4>;
3304 apss_ 3239 apss_funnel_in4: endpoint {
3305 3240 remote-endpoint = <&etm4_out>;
3306 }; 3241 };
3307 }; 3242 };
3308 3243
3309 port@5 { 3244 port@5 {
3310 reg = 3245 reg = <5>;
3311 apss_ 3246 apss_funnel_in5: endpoint {
3312 3247 remote-endpoint = <&etm5_out>;
3313 }; 3248 };
3314 }; 3249 };
3315 3250
3316 port@6 { 3251 port@6 {
3317 reg = 3252 reg = <6>;
3318 apss_ 3253 apss_funnel_in6: endpoint {
3319 3254 remote-endpoint = <&etm6_out>;
3320 }; 3255 };
3321 }; 3256 };
3322 3257
3323 port@7 { 3258 port@7 {
3324 reg = 3259 reg = <7>;
3325 apss_ 3260 apss_funnel_in7: endpoint {
3326 3261 remote-endpoint = <&etm7_out>;
3327 }; 3262 };
3328 }; 3263 };
3329 }; 3264 };
3330 }; 3265 };
3331 3266
3332 funnel@7810000 { 3267 funnel@7810000 {
3333 compatible = "arm,cor 3268 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3269 reg = <0 0x07810000 0 0x1000>;
3335 3270
3336 clocks = <&aoss_qmp>; 3271 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3272 clock-names = "apb_pclk";
3338 3273
3339 out-ports { 3274 out-ports {
3340 port { 3275 port {
3341 apss_ 3276 apss_merge_funnel_out: endpoint {
3342 3277 remote-endpoint = <&funnel2_in2>;
3343 }; 3278 };
3344 }; 3279 };
3345 }; 3280 };
3346 3281
3347 in-ports { 3282 in-ports {
3348 port { 3283 port {
3349 apss_ 3284 apss_merge_funnel_in: endpoint {
3350 3285 remote-endpoint = <&apss_funnel_out>;
3351 }; 3286 };
3352 }; 3287 };
3353 }; 3288 };
3354 }; 3289 };
3355 3290
3356 remoteproc_cdsp: remoteproc@8 3291 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3292 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3293 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3294
3360 interrupts-extended = 3295 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3296 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3297 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3298 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3299 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3300 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3301 "handover", "stop-ack";
3367 3302
3368 clocks = <&rpmhcc RPM 3303 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3304 clock-names = "xo";
3370 3305
3371 power-domains = <&rpm 3306 power-domains = <&rpmhpd SM8150_CX>;
3372 3307
3373 memory-region = <&cds 3308 memory-region = <&cdsp_mem>;
3374 3309
3375 qcom,qmp = <&aoss_qmp 3310 qcom,qmp = <&aoss_qmp>;
3376 3311
3377 qcom,smem-states = <& 3312 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3313 qcom,smem-state-names = "stop";
3379 3314
3380 status = "disabled"; 3315 status = "disabled";
3381 3316
3382 glink-edge { 3317 glink-edge {
3383 interrupts = 3318 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3319 label = "cdsp";
3385 qcom,remote-p 3320 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3321 mboxes = <&apss_shared 4>;
3387 3322
3388 fastrpc { 3323 fastrpc {
3389 compa 3324 compatible = "qcom,fastrpc";
3390 qcom, 3325 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3326 label = "cdsp";
3392 qcom, 3327 qcom,non-secure-domain;
3393 #addr 3328 #address-cells = <1>;
3394 #size 3329 #size-cells = <0>;
3395 3330
3396 compu 3331 compute-cb@1 {
3397 3332 compatible = "qcom,fastrpc-compute-cb";
3398 3333 reg = <1>;
3399 3334 iommus = <&apps_smmu 0x1001 0x0460>;
3400 }; 3335 };
3401 3336
3402 compu 3337 compute-cb@2 {
3403 3338 compatible = "qcom,fastrpc-compute-cb";
3404 3339 reg = <2>;
3405 3340 iommus = <&apps_smmu 0x1002 0x0460>;
3406 }; 3341 };
3407 3342
3408 compu 3343 compute-cb@3 {
3409 3344 compatible = "qcom,fastrpc-compute-cb";
3410 3345 reg = <3>;
3411 3346 iommus = <&apps_smmu 0x1003 0x0460>;
3412 }; 3347 };
3413 3348
3414 compu 3349 compute-cb@4 {
3415 3350 compatible = "qcom,fastrpc-compute-cb";
3416 3351 reg = <4>;
3417 3352 iommus = <&apps_smmu 0x1004 0x0460>;
3418 }; 3353 };
3419 3354
3420 compu 3355 compute-cb@5 {
3421 3356 compatible = "qcom,fastrpc-compute-cb";
3422 3357 reg = <5>;
3423 3358 iommus = <&apps_smmu 0x1005 0x0460>;
3424 }; 3359 };
3425 3360
3426 compu 3361 compute-cb@6 {
3427 3362 compatible = "qcom,fastrpc-compute-cb";
3428 3363 reg = <6>;
3429 3364 iommus = <&apps_smmu 0x1006 0x0460>;
3430 }; 3365 };
3431 3366
3432 compu 3367 compute-cb@7 {
3433 3368 compatible = "qcom,fastrpc-compute-cb";
3434 3369 reg = <7>;
3435 3370 iommus = <&apps_smmu 0x1007 0x0460>;
3436 }; 3371 };
3437 3372
3438 compu 3373 compute-cb@8 {
3439 3374 compatible = "qcom,fastrpc-compute-cb";
3440 3375 reg = <8>;
3441 3376 iommus = <&apps_smmu 0x1008 0x0460>;
3442 }; 3377 };
3443 3378
3444 /* no 3379 /* note: secure cb9 in downstream */
3445 }; 3380 };
3446 }; 3381 };
3447 }; 3382 };
3448 3383
3449 usb_1_hsphy: phy@88e2000 { 3384 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3385 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3386 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3387 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3388 status = "disabled";
3454 #phy-cells = <0>; 3389 #phy-cells = <0>;
3455 3390
3456 clocks = <&rpmhcc RPM 3391 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3392 clock-names = "ref";
3458 3393
3459 resets = <&gcc GCC_QU 3394 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3395 };
3461 3396
3462 usb_2_hsphy: phy@88e3000 { 3397 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3398 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3399 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3400 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3401 status = "disabled";
3467 #phy-cells = <0>; 3402 #phy-cells = <0>;
3468 3403
3469 clocks = <&rpmhcc RPM 3404 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3405 clock-names = "ref";
3471 3406
3472 resets = <&gcc GCC_QU 3407 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3408 };
3474 3409
3475 usb_1_qmpphy: phy@88e8000 { !! 3410 usb_1_qmpphy: phy@88e9000 {
3476 compatible = "qcom,sm !! 3411 compatible = "qcom,sm8150-qmp-usb3-phy";
3477 reg = <0 0x088e8000 0 !! 3412 reg = <0 0x088e9000 0 0x18c>,
>> 3413 <0 0x088e8000 0 0x10>;
>> 3414 status = "disabled";
>> 3415 #address-cells = <2>;
>> 3416 #size-cells = <2>;
>> 3417 ranges;
3478 3418
3479 clocks = <&gcc GCC_US 3419 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> 3420 <&rpmhcc RPMH_CXO_CLK>,
3480 <&gcc GCC_US 3421 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US !! 3422 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3482 <&gcc GCC_US !! 3423 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3483 clock-names = "aux", <<
3484 "ref", <<
3485 "com_au <<
3486 "usb3_p <<
3487 3424
3488 resets = <&gcc GCC_US 3425 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3426 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3427 reset-names = "phy", "common";
3491 3428
3492 #clock-cells = <1>; !! 3429 usb_1_ssphy: phy@88e9200 {
3493 #phy-cells = <1>; !! 3430 reg = <0 0x088e9200 0 0x200>,
3494 !! 3431 <0 0x088e9400 0 0x200>,
3495 status = "disabled"; !! 3432 <0 0x088e9c00 0 0x218>,
3496 !! 3433 <0 0x088e9600 0 0x200>,
3497 ports { !! 3434 <0 0x088e9800 0 0x200>,
3498 #address-cell !! 3435 <0 0x088e9a00 0 0x100>;
3499 #size-cells = !! 3436 #clock-cells = <0>;
3500 !! 3437 #phy-cells = <0>;
3501 port@0 { !! 3438 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3502 reg = !! 3439 clock-names = "pipe0";
3503 !! 3440 clock-output-names = "usb3_phy_pipe_clk_src";
3504 usb_1 <<
3505 }; <<
3506 }; <<
3507 <<
3508 port@1 { <<
3509 reg = <<
3510 <<
3511 usb_1 <<
3512 <<
3513 }; <<
3514 }; <<
3515 <<
3516 port@2 { <<
3517 reg = <<
3518 <<
3519 usb_1 <<
3520 <<
3521 }; <<
3522 }; <<
3523 }; 3441 };
3524 }; 3442 };
3525 3443
3526 usb_2_qmpphy: phy@88eb000 { 3444 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3445 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 !! 3446 reg = <0 0x088eb000 0 0x200>;
>> 3447 status = "disabled";
>> 3448 #address-cells = <2>;
>> 3449 #size-cells = <2>;
>> 3450 ranges;
3529 3451
3530 clocks = <&gcc GCC_US 3452 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3453 <&rpmhcc RPMH_CXO_CLK>,
3531 <&gcc GCC_US 3454 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US !! 3455 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3533 <&gcc GCC_US !! 3456 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3534 clock-names = "aux", <<
3535 "ref", <<
3536 "com_au <<
3537 "pipe"; <<
3538 clock-output-names = <<
3539 #clock-cells = <0>; <<
3540 #phy-cells = <0>; <<
3541 3457
3542 resets = <&gcc GCC_US !! 3458 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3543 <&gcc GCC_US !! 3459 <&gcc GCC_USB3_PHY_SEC_BCR>;
3544 reset-names = "phy", !! 3460 reset-names = "phy", "common";
3545 "phy_ph <<
3546 3461
3547 status = "disabled"; !! 3462 usb_2_ssphy: phy@88eb200 {
>> 3463 reg = <0 0x088eb200 0 0x200>,
>> 3464 <0 0x088eb400 0 0x200>,
>> 3465 <0 0x088eb800 0 0x800>,
>> 3466 <0 0x088eb600 0 0x200>;
>> 3467 #clock-cells = <0>;
>> 3468 #phy-cells = <0>;
>> 3469 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3470 clock-names = "pipe0";
>> 3471 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3472 };
3548 }; 3473 };
3549 3474
3550 sdhc_2: mmc@8804000 { 3475 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm 3476 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3477 reg = <0 0x08804000 0 0x1000>;
3553 3478
3554 interrupts = <GIC_SPI 3479 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3480 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3481 interrupt-names = "hc_irq", "pwr_irq";
3557 3482
3558 clocks = <&gcc GCC_SD 3483 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3484 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3485 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3486 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3487 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3488 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3489 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3490 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3491 operating-points-v2 = <&sdhc2_opp_table>;
3567 3492
3568 status = "disabled"; 3493 status = "disabled";
3569 3494
3570 sdhc2_opp_table: opp- 3495 sdhc2_opp_table: opp-table {
3571 compatible = 3496 compatible = "operating-points-v2";
3572 3497
3573 opp-19200000 3498 opp-19200000 {
3574 opp-h 3499 opp-hz = /bits/ 64 <19200000>;
3575 requi 3500 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3501 };
3577 3502
3578 opp-50000000 3503 opp-50000000 {
3579 opp-h 3504 opp-hz = /bits/ 64 <50000000>;
3580 requi 3505 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3506 };
3582 3507
3583 opp-100000000 3508 opp-100000000 {
3584 opp-h 3509 opp-hz = /bits/ 64 <100000000>;
3585 requi 3510 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3511 };
3587 3512
3588 opp-202000000 3513 opp-202000000 {
3589 opp-h 3514 opp-hz = /bits/ 64 <202000000>;
3590 requi 3515 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3516 };
3592 }; 3517 };
3593 }; 3518 };
3594 3519
3595 dc_noc: interconnect@9160000 3520 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3521 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3522 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = !! 3523 #interconnect-cells = <1>;
3599 qcom,bcm-voters = <&a 3524 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3525 };
3601 3526
3602 gem_noc: interconnect@9680000 3527 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3528 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3529 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = !! 3530 #interconnect-cells = <1>;
3606 qcom,bcm-voters = <&a 3531 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3532 };
3608 3533
3609 usb_1: usb@a6f8800 { 3534 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3535 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3536 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3537 status = "disabled";
3613 #address-cells = <2>; 3538 #address-cells = <2>;
3614 #size-cells = <2>; 3539 #size-cells = <2>;
3615 ranges; 3540 ranges;
3616 dma-ranges; 3541 dma-ranges;
3617 3542
3618 clocks = <&gcc GCC_CF 3543 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3544 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3545 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3546 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3547 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3548 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3549 clock-names = "cfg_noc",
3625 "core", 3550 "core",
3626 "iface" 3551 "iface",
3627 "sleep" 3552 "sleep",
3628 "mock_u 3553 "mock_utmi",
3629 "xo"; 3554 "xo";
3630 3555
3631 assigned-clocks = <&g 3556 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3557 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3558 assigned-clock-rates = <19200000>, <200000000>;
3634 3559
3635 interrupts-extended = !! 3560 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3561 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3637 !! 3562 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3638 !! 3563 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3639 !! 3564 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3640 interrupt-names = "pw !! 3565 "dm_hs_phy_irq", "dp_hs_phy_irq";
3641 "hs <<
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3566
3646 power-domains = <&gcc 3567 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3568
3648 resets = <&gcc GCC_US 3569 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3570
3650 interconnects = <&agg <<
3651 <&gem <<
3652 interconnect-names = <<
3653 <<
3654 usb_1_dwc3: usb@a6000 3571 usb_1_dwc3: usb@a600000 {
3655 compatible = 3572 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3573 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3574 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3575 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3576 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3577 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ !! 3578 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3662 phy-names = " 3579 phy-names = "usb2-phy", "usb3-phy";
3663 <<
3664 ports { <<
3665 #addr <<
3666 #size <<
3667 <<
3668 port@ <<
3669 <<
3670 <<
3671 <<
3672 <<
3673 }; <<
3674 <<
3675 port@ <<
3676 <<
3677 <<
3678 <<
3679 <<
3680 <<
3681 }; <<
3682 }; <<
3683 }; 3580 };
3684 }; 3581 };
3685 3582
3686 usb_2: usb@a8f8800 { 3583 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3584 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3585 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3586 status = "disabled";
3690 #address-cells = <2>; 3587 #address-cells = <2>;
3691 #size-cells = <2>; 3588 #size-cells = <2>;
3692 ranges; 3589 ranges;
3693 dma-ranges; 3590 dma-ranges;
3694 3591
3695 clocks = <&gcc GCC_CF 3592 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3593 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3594 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3595 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3596 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3597 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3598 clock-names = "cfg_noc",
3702 "core", 3599 "core",
3703 "iface" 3600 "iface",
3704 "sleep" 3601 "sleep",
3705 "mock_u 3602 "mock_utmi",
3706 "xo"; 3603 "xo";
3707 3604
3708 assigned-clocks = <&g 3605 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3606 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3607 assigned-clock-rates = <19200000>, <200000000>;
3711 3608
3712 interrupts-extended = !! 3609 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3610 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3714 !! 3611 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3715 !! 3612 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3716 !! 3613 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3717 interrupt-names = "pw !! 3614 "dm_hs_phy_irq", "dp_hs_phy_irq";
3718 "hs <<
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3615
3723 power-domains = <&gcc 3616 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3617
3725 resets = <&gcc GCC_US 3618 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3619
3727 interconnects = <&agg <<
3728 <&gem <<
3729 interconnect-names = <<
3730 <<
3731 usb_2_dwc3: usb@a8000 3620 usb_2_dwc3: usb@a800000 {
3732 compatible = 3621 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3622 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3623 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3624 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3625 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3626 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ !! 3627 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3739 phy-names = " 3628 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3629 };
3741 }; 3630 };
3742 3631
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3632 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3633 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3634 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = !! 3635 #interconnect-cells = <1>;
3760 qcom,bcm-voters = <&a 3636 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3637 };
3762 3638
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 3639 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm 3640 compatible = "qcom,sm8150-mdss";
3777 reg = <0 0x0ae00000 0 3641 reg = <0 0x0ae00000 0 0x1000>;
3778 reg-names = "mdss"; 3642 reg-names = "mdss";
3779 3643
3780 interconnects = <&mms !! 3644 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
3781 <&mms !! 3645 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
3782 interconnect-names = 3646 interconnect-names = "mdp0-mem", "mdp1-mem";
3783 3647
3784 power-domains = <&dis 3648 power-domains = <&dispcc MDSS_GDSC>;
3785 3649
3786 clocks = <&dispcc DIS 3650 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 <&gcc GCC_DI 3651 <&gcc GCC_DISP_HF_AXI_CLK>,
3788 <&gcc GCC_DI 3652 <&gcc GCC_DISP_SF_AXI_CLK>,
3789 <&dispcc DIS 3653 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3790 clock-names = "iface" 3654 clock-names = "iface", "bus", "nrt_bus", "core";
3791 3655
3792 interrupts = <GIC_SPI 3656 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller; 3657 interrupt-controller;
3794 #interrupt-cells = <1 3658 #interrupt-cells = <1>;
3795 3659
3796 iommus = <&apps_smmu 3660 iommus = <&apps_smmu 0x800 0x420>;
3797 3661
3798 status = "disabled"; 3662 status = "disabled";
3799 3663
3800 #address-cells = <2>; 3664 #address-cells = <2>;
3801 #size-cells = <2>; 3665 #size-cells = <2>;
3802 ranges; 3666 ranges;
3803 3667
3804 mdss_mdp: display-con 3668 mdss_mdp: display-controller@ae01000 {
3805 compatible = 3669 compatible = "qcom,sm8150-dpu";
3806 reg = <0 0x0a 3670 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0a 3671 <0 0x0aeb0000 0 0x2008>;
3808 reg-names = " 3672 reg-names = "mdp", "vbif";
3809 3673
3810 clocks = <&di 3674 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3811 <&gc 3675 <&gcc GCC_DISP_HF_AXI_CLK>,
3812 <&di 3676 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3813 <&di 3677 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3814 clock-names = 3678 clock-names = "iface", "bus", "core", "vsync";
3815 3679
3816 assigned-cloc 3680 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-cloc 3681 assigned-clock-rates = <19200000>;
3818 3682
3819 operating-poi 3683 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains 3684 power-domains = <&rpmhpd SM8150_MMCX>;
3821 3685
3822 interrupt-par 3686 interrupt-parent = <&mdss>;
3823 interrupts = 3687 interrupts = <0>;
3824 3688
3825 ports { 3689 ports {
3826 #addr 3690 #address-cells = <1>;
3827 #size 3691 #size-cells = <0>;
3828 3692
3829 port@ 3693 port@0 {
3830 3694 reg = <0>;
3831 3695 dpu_intf1_out: endpoint {
3832 3696 remote-endpoint = <&mdss_dsi0_in>;
3833 3697 };
3834 }; 3698 };
3835 3699
3836 port@ 3700 port@1 {
3837 3701 reg = <1>;
3838 3702 dpu_intf2_out: endpoint {
3839 3703 remote-endpoint = <&mdss_dsi1_in>;
3840 3704 };
3841 }; 3705 };
3842 <<
3843 port@ <<
3844 <<
3845 <<
3846 <<
3847 <<
3848 }; <<
3849 }; 3706 };
3850 3707
3851 mdp_opp_table 3708 mdp_opp_table: opp-table {
3852 compa 3709 compatible = "operating-points-v2";
3853 3710
3854 opp-1 3711 opp-171428571 {
3855 3712 opp-hz = /bits/ 64 <171428571>;
3856 3713 required-opps = <&rpmhpd_opp_low_svs>;
3857 }; 3714 };
3858 3715
3859 opp-3 3716 opp-300000000 {
3860 3717 opp-hz = /bits/ 64 <300000000>;
3861 3718 required-opps = <&rpmhpd_opp_svs>;
3862 }; 3719 };
3863 3720
3864 opp-3 3721 opp-345000000 {
3865 3722 opp-hz = /bits/ 64 <345000000>;
3866 3723 required-opps = <&rpmhpd_opp_svs_l1>;
3867 }; 3724 };
3868 3725
3869 opp-4 3726 opp-460000000 {
3870 3727 opp-hz = /bits/ 64 <460000000>;
3871 3728 required-opps = <&rpmhpd_opp_nom>;
3872 }; 3729 };
3873 }; 3730 };
3874 }; 3731 };
3875 3732
3876 mdss_dp: displayport- <<
3877 compatible = <<
3878 reg = <0 0xae <<
3879 <0 0xae <<
3880 <0 0xae <<
3881 <0 0x0a <<
3882 <0 0x0a <<
3883 <<
3884 interrupt-par <<
3885 interrupts = <<
3886 clocks = <&di <<
3887 <&di <<
3888 <&di <<
3889 <&di <<
3890 <&di <<
3891 clock-names = <<
3892 <<
3893 <<
3894 <<
3895 <<
3896 <<
3897 assigned-cloc <<
3898 <<
3899 assigned-cloc <<
3900 <<
3901 <<
3902 phys = <&usb_ <<
3903 phy-names = " <<
3904 <<
3905 #sound-dai-ce <<
3906 <<
3907 operating-poi <<
3908 power-domains <<
3909 <<
3910 status = "dis <<
3911 <<
3912 ports { <<
3913 #addr <<
3914 #size <<
3915 <<
3916 port@ <<
3917 <<
3918 <<
3919 <<
3920 <<
3921 }; <<
3922 <<
3923 port@ <<
3924 <<
3925 <<
3926 <<
3927 <<
3928 <<
3929 }; <<
3930 }; <<
3931 <<
3932 dp_opp_table: <<
3933 compa <<
3934 <<
3935 opp-1 <<
3936 <<
3937 <<
3938 }; <<
3939 <<
3940 opp-2 <<
3941 <<
3942 <<
3943 }; <<
3944 <<
3945 opp-5 <<
3946 <<
3947 <<
3948 }; <<
3949 <<
3950 opp-8 <<
3951 <<
3952 <<
3953 }; <<
3954 }; <<
3955 }; <<
3956 <<
3957 mdss_dsi0: dsi@ae9400 3733 mdss_dsi0: dsi@ae94000 {
3958 compatible = 3734 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg = <0 0x0a 3735 reg = <0 0x0ae94000 0 0x400>;
3960 reg-names = " 3736 reg-names = "dsi_ctrl";
3961 3737
3962 interrupt-par 3738 interrupt-parent = <&mdss>;
3963 interrupts = 3739 interrupts = <4>;
3964 3740
3965 clocks = <&di 3741 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3966 <&di 3742 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3967 <&di 3743 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3968 <&di 3744 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3969 <&di 3745 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3970 <&gc 3746 <&gcc GCC_DISP_HF_AXI_CLK>;
3971 clock-names = 3747 clock-names = "byte",
3972 3748 "byte_intf",
3973 3749 "pixel",
3974 3750 "core",
3975 3751 "iface",
3976 3752 "bus";
3977 3753
3978 assigned-cloc 3754 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3979 3755 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3980 assigned-cloc 3756 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3981 3757 <&mdss_dsi0_phy 1>;
3982 3758
3983 operating-poi 3759 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains 3760 power-domains = <&rpmhpd SM8150_MMCX>;
3985 3761
3986 phys = <&mdss 3762 phys = <&mdss_dsi0_phy>;
3987 3763
3988 status = "dis 3764 status = "disabled";
3989 3765
3990 #address-cell 3766 #address-cells = <1>;
3991 #size-cells = 3767 #size-cells = <0>;
3992 3768
3993 ports { 3769 ports {
3994 #addr 3770 #address-cells = <1>;
3995 #size 3771 #size-cells = <0>;
3996 3772
3997 port@ 3773 port@0 {
3998 3774 reg = <0>;
3999 3775 mdss_dsi0_in: endpoint {
4000 3776 remote-endpoint = <&dpu_intf1_out>;
4001 3777 };
4002 }; 3778 };
4003 3779
4004 port@ 3780 port@1 {
4005 3781 reg = <1>;
4006 3782 mdss_dsi0_out: endpoint {
4007 3783 };
4008 }; 3784 };
4009 }; 3785 };
4010 3786
4011 dsi_opp_table 3787 dsi_opp_table: opp-table {
4012 compa 3788 compatible = "operating-points-v2";
4013 3789
4014 opp-1 3790 opp-187500000 {
4015 3791 opp-hz = /bits/ 64 <187500000>;
4016 3792 required-opps = <&rpmhpd_opp_low_svs>;
4017 }; 3793 };
4018 3794
4019 opp-3 3795 opp-300000000 {
4020 3796 opp-hz = /bits/ 64 <300000000>;
4021 3797 required-opps = <&rpmhpd_opp_svs>;
4022 }; 3798 };
4023 3799
4024 opp-3 3800 opp-358000000 {
4025 3801 opp-hz = /bits/ 64 <358000000>;
4026 3802 required-opps = <&rpmhpd_opp_svs_l1>;
4027 }; 3803 };
4028 }; 3804 };
4029 }; 3805 };
4030 3806
4031 mdss_dsi0_phy: phy@ae 3807 mdss_dsi0_phy: phy@ae94400 {
4032 compatible = 3808 compatible = "qcom,dsi-phy-7nm-8150";
4033 reg = <0 0x0a 3809 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0a 3810 <0 0x0ae94600 0 0x280>,
4035 <0 0x0a 3811 <0 0x0ae94900 0 0x260>;
4036 reg-names = " 3812 reg-names = "dsi_phy",
4037 " 3813 "dsi_phy_lane",
4038 " 3814 "dsi_pll";
4039 3815
4040 #clock-cells 3816 #clock-cells = <1>;
4041 #phy-cells = 3817 #phy-cells = <0>;
4042 3818
4043 clocks = <&di 3819 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4044 <&rp 3820 <&rpmhcc RPMH_CXO_CLK>;
4045 clock-names = 3821 clock-names = "iface", "ref";
4046 3822
4047 status = "dis 3823 status = "disabled";
4048 }; 3824 };
4049 3825
4050 mdss_dsi1: dsi@ae9600 3826 mdss_dsi1: dsi@ae96000 {
4051 compatible = 3827 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4052 reg = <0 0x0a 3828 reg = <0 0x0ae96000 0 0x400>;
4053 reg-names = " 3829 reg-names = "dsi_ctrl";
4054 3830
4055 interrupt-par 3831 interrupt-parent = <&mdss>;
4056 interrupts = 3832 interrupts = <5>;
4057 3833
4058 clocks = <&di 3834 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4059 <&di 3835 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4060 <&di 3836 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4061 <&di 3837 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4062 <&di 3838 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4063 <&gc 3839 <&gcc GCC_DISP_HF_AXI_CLK>;
4064 clock-names = 3840 clock-names = "byte",
4065 3841 "byte_intf",
4066 3842 "pixel",
4067 3843 "core",
4068 3844 "iface",
4069 3845 "bus";
4070 3846
4071 assigned-cloc 3847 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4072 3848 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4073 assigned-cloc 3849 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4074 3850 <&mdss_dsi1_phy 1>;
4075 3851
4076 operating-poi 3852 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains 3853 power-domains = <&rpmhpd SM8150_MMCX>;
4078 3854
4079 phys = <&mdss 3855 phys = <&mdss_dsi1_phy>;
4080 3856
4081 status = "dis 3857 status = "disabled";
4082 3858
4083 #address-cell 3859 #address-cells = <1>;
4084 #size-cells = 3860 #size-cells = <0>;
4085 3861
4086 ports { 3862 ports {
4087 #addr 3863 #address-cells = <1>;
4088 #size 3864 #size-cells = <0>;
4089 3865
4090 port@ 3866 port@0 {
4091 3867 reg = <0>;
4092 3868 mdss_dsi1_in: endpoint {
4093 3869 remote-endpoint = <&dpu_intf2_out>;
4094 3870 };
4095 }; 3871 };
4096 3872
4097 port@ 3873 port@1 {
4098 3874 reg = <1>;
4099 3875 mdss_dsi1_out: endpoint {
4100 3876 };
4101 }; 3877 };
4102 }; 3878 };
4103 }; 3879 };
4104 3880
4105 mdss_dsi1_phy: phy@ae 3881 mdss_dsi1_phy: phy@ae96400 {
4106 compatible = 3882 compatible = "qcom,dsi-phy-7nm-8150";
4107 reg = <0 0x0a 3883 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0a 3884 <0 0x0ae96600 0 0x280>,
4109 <0 0x0a 3885 <0 0x0ae96900 0 0x260>;
4110 reg-names = " 3886 reg-names = "dsi_phy",
4111 " 3887 "dsi_phy_lane",
4112 " 3888 "dsi_pll";
4113 3889
4114 #clock-cells 3890 #clock-cells = <1>;
4115 #phy-cells = 3891 #phy-cells = <0>;
4116 3892
4117 clocks = <&di 3893 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4118 <&rp 3894 <&rpmhcc RPMH_CXO_CLK>;
4119 clock-names = 3895 clock-names = "iface", "ref";
4120 3896
4121 status = "dis 3897 status = "disabled";
4122 }; 3898 };
4123 }; 3899 };
4124 3900
4125 dispcc: clock-controller@af00 3901 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm 3902 compatible = "qcom,sm8150-dispcc";
4127 reg = <0 0x0af00000 0 3903 reg = <0 0x0af00000 0 0x10000>;
4128 clocks = <&rpmhcc RPM 3904 clocks = <&rpmhcc RPMH_CXO_CLK>,
4129 <&mdss_dsi0_ 3905 <&mdss_dsi0_phy 0>,
4130 <&mdss_dsi0_ 3906 <&mdss_dsi0_phy 1>,
4131 <&mdss_dsi1_ 3907 <&mdss_dsi1_phy 0>,
4132 <&mdss_dsi1_ 3908 <&mdss_dsi1_phy 1>,
4133 <&usb_1_qmpp !! 3909 <0>,
4134 <&usb_1_qmpp !! 3910 <0>;
4135 clock-names = "bi_tcx 3911 clock-names = "bi_tcxo",
4136 "dsi0_p 3912 "dsi0_phy_pll_out_byteclk",
4137 "dsi0_p 3913 "dsi0_phy_pll_out_dsiclk",
4138 "dsi1_p 3914 "dsi1_phy_pll_out_byteclk",
4139 "dsi1_p 3915 "dsi1_phy_pll_out_dsiclk",
4140 "dp_phy 3916 "dp_phy_pll_link_clk",
4141 "dp_phy 3917 "dp_phy_pll_vco_div_clk";
4142 power-domains = <&rpm 3918 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpm <<
4144 #clock-cells = <1>; 3919 #clock-cells = <1>;
4145 #reset-cells = <1>; 3920 #reset-cells = <1>;
4146 #power-domain-cells = 3921 #power-domain-cells = <1>;
4147 }; 3922 };
4148 3923
4149 pdc: interrupt-controller@b22 3924 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 3925 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 !! 3926 reg = <0 0x0b220000 0 0x400>;
4152 qcom,pdc-ranges = <0 3927 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 3928 <125 63 1>;
4154 #interrupt-cells = <2 3929 #interrupt-cells = <2>;
4155 interrupt-parent = <& 3930 interrupt-parent = <&intc>;
4156 interrupt-controller; 3931 interrupt-controller;
4157 }; 3932 };
4158 3933
4159 aoss_qmp: power-management@c3 3934 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm 3935 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 3936 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 3937 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 3938 mboxes = <&apss_shared 0>;
4164 3939
4165 #clock-cells = <0>; 3940 #clock-cells = <0>;
4166 }; 3941 };
4167 3942
4168 sram@c3f0000 { 3943 sram@c3f0000 {
4169 compatible = "qcom,rp 3944 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 3945 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 3946 };
4172 3947
4173 tsens0: thermal-sensor@c26300 3948 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 3949 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 3950 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 3951 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 3952 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 3953 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 3954 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 3955 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 3956 #thermal-sensor-cells = <1>;
4182 }; 3957 };
4183 3958
4184 tsens1: thermal-sensor@c26500 3959 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 3960 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 3961 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 3962 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 3963 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 3964 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 3965 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 3966 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 3967 #thermal-sensor-cells = <1>;
4193 }; 3968 };
4194 3969
4195 spmi_bus: spmi@c440000 { 3970 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 3971 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 3972 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 3973 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 3974 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 3975 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 3976 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 3977 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 3978 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 3979 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 3980 qcom,ee = <0>;
4206 qcom,channel = <0>; 3981 qcom,channel = <0>;
4207 #address-cells = <2>; 3982 #address-cells = <2>;
4208 #size-cells = <0>; 3983 #size-cells = <0>;
4209 interrupt-controller; 3984 interrupt-controller;
4210 #interrupt-cells = <4 3985 #interrupt-cells = <4>;
4211 }; 3986 };
4212 3987
4213 apps_smmu: iommu@15000000 { 3988 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm !! 3989 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 3990 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 3991 #iommu-cells = <2>;
4217 #global-interrupts = 3992 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 3993 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 3994 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 3995 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 3996 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 3997 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 3998 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 3999 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 4000 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 4001 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 4002 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 4003 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4004 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 4005 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 4006 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 4007 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 4008 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 4009 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 4010 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 4011 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4012 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 4013 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 4014 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 4015 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 4016 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 4017 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 4018 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 4019 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 4020 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 4021 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 4022 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 4023 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 4024 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 4025 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 4026 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 4027 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 4028 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 4029 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 4030 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 4031 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 4032 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 4033 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 4034 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 4035 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 4036 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 4037 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 4038 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 4039 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 4040 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 4041 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 4042 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 4043 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 4044 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 4045 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 4046 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 4047 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 4048 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 4049 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 4050 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 4051 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 4052 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 4053 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 4054 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 4055 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 4056 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 4057 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 4058 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 4059 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 4060 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 4061 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 4062 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 4063 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 4064 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 4065 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 4066 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 4067 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 4068 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 4069 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 4070 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 4071 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 4072 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 4073 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 4074 };
4300 4075
4301 remoteproc_adsp: remoteproc@1 4076 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 4077 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 4078 reg = <0x0 0x17300000 0x0 0x4040>;
4304 4079
4305 interrupts-extended = 4080 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 4081 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 4082 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 4083 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 4084 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 4085 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 4086 "handover", "stop-ack";
4312 4087
4313 clocks = <&rpmhcc RPM 4088 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 4089 clock-names = "xo";
4315 4090
4316 power-domains = <&rpm 4091 power-domains = <&rpmhpd SM8150_CX>;
4317 4092
4318 memory-region = <&ads 4093 memory-region = <&adsp_mem>;
4319 4094
4320 qcom,qmp = <&aoss_qmp 4095 qcom,qmp = <&aoss_qmp>;
4321 4096
4322 qcom,smem-states = <& 4097 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 4098 qcom,smem-state-names = "stop";
4324 4099
4325 status = "disabled"; 4100 status = "disabled";
4326 4101
4327 glink-edge { 4102 glink-edge {
4328 interrupts = 4103 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 4104 label = "lpass";
4330 qcom,remote-p 4105 qcom,remote-pid = <2>;
4331 mboxes = <&ap 4106 mboxes = <&apss_shared 8>;
4332 4107
4333 fastrpc { 4108 fastrpc {
4334 compa 4109 compatible = "qcom,fastrpc";
4335 qcom, 4110 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 4111 label = "adsp";
4337 qcom, 4112 qcom,non-secure-domain;
4338 #addr 4113 #address-cells = <1>;
4339 #size 4114 #size-cells = <0>;
4340 4115
4341 compu 4116 compute-cb@3 {
4342 4117 compatible = "qcom,fastrpc-compute-cb";
4343 4118 reg = <3>;
4344 4119 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 4120 };
4346 4121
4347 compu 4122 compute-cb@4 {
4348 4123 compatible = "qcom,fastrpc-compute-cb";
4349 4124 reg = <4>;
4350 4125 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 4126 };
4352 4127
4353 compu 4128 compute-cb@5 {
4354 4129 compatible = "qcom,fastrpc-compute-cb";
4355 4130 reg = <5>;
4356 4131 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 4132 };
4358 }; 4133 };
4359 }; 4134 };
4360 }; 4135 };
4361 4136
4362 intc: interrupt-controller@17 4137 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 4138 compatible = "arm,gic-v3";
4364 interrupt-controller; 4139 interrupt-controller;
4365 #interrupt-cells = <3 4140 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 4141 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 4142 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 4143 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 4144 };
4370 4145
4371 apss_shared: mailbox@17c00000 4146 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm 4147 compatible = "qcom,sm8150-apss-shared",
4373 "qcom,sd 4148 "qcom,sdm845-apss-shared";
4374 reg = <0x0 0x17c00000 4149 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 4150 #mbox-cells = <1>;
4376 }; 4151 };
4377 4152
4378 watchdog@17c10000 { 4153 watchdog@17c10000 {
4379 compatible = "qcom,ap 4154 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 4155 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 4156 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI !! 4157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4383 }; 4158 };
4384 4159
4385 timer@17c20000 { 4160 timer@17c20000 {
4386 #address-cells = <1>; 4161 #address-cells = <1>;
4387 #size-cells = <1>; 4162 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 4163 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 4164 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 4165 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 4166 clock-frequency = <19200000>;
4392 4167
4393 frame@17c21000 { 4168 frame@17c21000 {
4394 frame-number 4169 frame-number = <0>;
4395 interrupts = 4170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 4171 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 4172 reg = <0x17c21000 0x1000>,
4398 <0x17c2 4173 <0x17c22000 0x1000>;
4399 }; 4174 };
4400 4175
4401 frame@17c23000 { 4176 frame@17c23000 {
4402 frame-number 4177 frame-number = <1>;
4403 interrupts = 4178 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 4179 reg = <0x17c23000 0x1000>;
4405 status = "dis 4180 status = "disabled";
4406 }; 4181 };
4407 4182
4408 frame@17c25000 { 4183 frame@17c25000 {
4409 frame-number 4184 frame-number = <2>;
4410 interrupts = 4185 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 4186 reg = <0x17c25000 0x1000>;
4412 status = "dis 4187 status = "disabled";
4413 }; 4188 };
4414 4189
4415 frame@17c27000 { 4190 frame@17c27000 {
4416 frame-number 4191 frame-number = <3>;
4417 interrupts = 4192 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 4193 reg = <0x17c26000 0x1000>;
4419 status = "dis 4194 status = "disabled";
4420 }; 4195 };
4421 4196
4422 frame@17c29000 { 4197 frame@17c29000 {
4423 frame-number 4198 frame-number = <4>;
4424 interrupts = 4199 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 4200 reg = <0x17c29000 0x1000>;
4426 status = "dis 4201 status = "disabled";
4427 }; 4202 };
4428 4203
4429 frame@17c2b000 { 4204 frame@17c2b000 {
4430 frame-number 4205 frame-number = <5>;
4431 interrupts = 4206 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 4207 reg = <0x17c2b000 0x1000>;
4433 status = "dis 4208 status = "disabled";
4434 }; 4209 };
4435 4210
4436 frame@17c2d000 { 4211 frame@17c2d000 {
4437 frame-number 4212 frame-number = <6>;
4438 interrupts = 4213 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 4214 reg = <0x17c2d000 0x1000>;
4440 status = "dis 4215 status = "disabled";
4441 }; 4216 };
4442 }; 4217 };
4443 4218
4444 apps_rsc: rsc@18200000 { 4219 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 4220 label = "apps_rsc";
4446 compatible = "qcom,rp 4221 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 4222 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 4223 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 4224 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 4225 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 4226 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4227 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 4228 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 4229 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 4230 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 4231 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 4232 <SLEEP_TCS 3>,
4458 <WA 4233 <WAKE_TCS 3>,
4459 <CO 4234 <CONTROL_TCS 1>;
4460 power-domains = <&CLU 4235 power-domains = <&CLUSTER_PD>;
4461 4236
4462 rpmhcc: clock-control 4237 rpmhcc: clock-controller {
4463 compatible = 4238 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 4239 #clock-cells = <1>;
4465 clock-names = 4240 clock-names = "xo";
4466 clocks = <&xo 4241 clocks = <&xo_board>;
4467 }; 4242 };
4468 4243
4469 rpmhpd: power-control 4244 rpmhpd: power-controller {
4470 compatible = 4245 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 4246 #power-domain-cells = <1>;
4472 operating-poi 4247 operating-points-v2 = <&rpmhpd_opp_table>;
4473 4248
4474 rpmhpd_opp_ta 4249 rpmhpd_opp_table: opp-table {
4475 compa 4250 compatible = "operating-points-v2";
4476 4251
4477 rpmhp 4252 rpmhpd_opp_ret: opp1 {
4478 4253 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 4254 };
4480 4255
4481 rpmhp 4256 rpmhpd_opp_min_svs: opp2 {
4482 4257 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 4258 };
4484 4259
4485 rpmhp 4260 rpmhpd_opp_low_svs: opp3 {
4486 4261 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 4262 };
4488 4263
4489 rpmhp 4264 rpmhpd_opp_svs: opp4 {
4490 4265 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 4266 };
4492 4267
4493 rpmhp 4268 rpmhpd_opp_svs_l1: opp5 {
4494 4269 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 4270 };
4496 4271
4497 rpmhp 4272 rpmhpd_opp_svs_l2: opp6 {
4498 4273 opp-level = <224>;
4499 }; 4274 };
4500 4275
4501 rpmhp 4276 rpmhpd_opp_nom: opp7 {
4502 4277 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 4278 };
4504 4279
4505 rpmhp 4280 rpmhpd_opp_nom_l1: opp8 {
4506 4281 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 4282 };
4508 4283
4509 rpmhp 4284 rpmhpd_opp_nom_l2: opp9 {
4510 4285 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 4286 };
4512 4287
4513 rpmhp 4288 rpmhpd_opp_turbo: opp10 {
4514 4289 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 4290 };
4516 4291
4517 rpmhp 4292 rpmhpd_opp_turbo_l1: opp11 {
4518 4293 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 4294 };
4520 }; 4295 };
4521 }; 4296 };
4522 4297
4523 apps_bcm_voter: bcm-v 4298 apps_bcm_voter: bcm-voter {
4524 compatible = 4299 compatible = "qcom,bcm-voter";
4525 }; 4300 };
4526 }; 4301 };
4527 4302
4528 osm_l3: interconnect@18321000 4303 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm 4304 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 4305 reg = <0 0x18321000 0 0x1400>;
4531 4306
4532 clocks = <&rpmhcc RPM 4307 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 4308 clock-names = "xo", "alternate";
4534 4309
4535 #interconnect-cells = 4310 #interconnect-cells = <1>;
4536 }; 4311 };
4537 4312
4538 cpufreq_hw: cpufreq@18323000 4313 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm 4314 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 4315 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 4316 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 4317 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 4318 "freq-domain2";
4544 4319
4545 clocks = <&rpmhcc RPM 4320 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 4321 clock-names = "xo", "alternate";
4547 4322
4548 #freq-domain-cells = 4323 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; 4324 #clock-cells = <1>;
4550 }; 4325 };
4551 4326
4552 lmh_cluster1: lmh@18350800 { 4327 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 4328 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 4329 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 4330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 4331 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 4332 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 4333 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 4334 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 4335 interrupt-controller;
4561 #interrupt-cells = <1 4336 #interrupt-cells = <1>;
4562 }; 4337 };
4563 4338
4564 lmh_cluster0: lmh@18358800 { 4339 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 4340 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 4341 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 4342 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4343 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4344 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4345 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4346 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4347 interrupt-controller;
4573 #interrupt-cells = <1 4348 #interrupt-cells = <1>;
4574 }; 4349 };
4575 4350
4576 wifi: wifi@18800000 { 4351 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4352 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4353 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4354 reg-names = "membase";
4580 memory-region = <&wla 4355 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4356 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4357 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4358 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4359 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4360 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4361 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4362 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4363 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4364 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4365 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4366 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4367 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4368 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4369 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4370 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4371 status = "disabled";
4597 }; 4372 };
4598 }; 4373 };
4599 4374
4600 timer { 4375 timer {
4601 compatible = "arm,armv8-timer 4376 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4377 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4378 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4379 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4380 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4381 };
4607 4382
4608 thermal-zones { 4383 thermal-zones {
4609 cpu0-thermal { 4384 cpu0-thermal {
4610 polling-delay-passive 4385 polling-delay-passive = <250>;
>> 4386 polling-delay = <1000>;
4611 4387
4612 thermal-sensors = <&t 4388 thermal-sensors = <&tsens0 1>;
4613 4389
4614 trips { 4390 trips {
4615 cpu0_alert0: 4391 cpu0_alert0: trip-point0 {
4616 tempe 4392 temperature = <90000>;
4617 hyste 4393 hysteresis = <2000>;
4618 type 4394 type = "passive";
4619 }; 4395 };
4620 4396
4621 cpu0_alert1: 4397 cpu0_alert1: trip-point1 {
4622 tempe 4398 temperature = <95000>;
4623 hyste 4399 hysteresis = <2000>;
4624 type 4400 type = "passive";
4625 }; 4401 };
4626 4402
4627 cpu0_crit: cp 4403 cpu0_crit: cpu-crit {
4628 tempe 4404 temperature = <110000>;
4629 hyste 4405 hysteresis = <1000>;
4630 type 4406 type = "critical";
4631 }; 4407 };
4632 }; 4408 };
4633 4409
4634 cooling-maps { 4410 cooling-maps {
4635 map0 { 4411 map0 {
4636 trip 4412 trip = <&cpu0_alert0>;
4637 cooli 4413 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4414 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4415 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4416 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4417 };
4642 map1 { 4418 map1 {
4643 trip 4419 trip = <&cpu0_alert1>;
4644 cooli 4420 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4421 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4422 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4423 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4424 };
4649 }; 4425 };
4650 }; 4426 };
4651 4427
4652 cpu1-thermal { 4428 cpu1-thermal {
4653 polling-delay-passive 4429 polling-delay-passive = <250>;
>> 4430 polling-delay = <1000>;
4654 4431
4655 thermal-sensors = <&t 4432 thermal-sensors = <&tsens0 2>;
4656 4433
4657 trips { 4434 trips {
4658 cpu1_alert0: 4435 cpu1_alert0: trip-point0 {
4659 tempe 4436 temperature = <90000>;
4660 hyste 4437 hysteresis = <2000>;
4661 type 4438 type = "passive";
4662 }; 4439 };
4663 4440
4664 cpu1_alert1: 4441 cpu1_alert1: trip-point1 {
4665 tempe 4442 temperature = <95000>;
4666 hyste 4443 hysteresis = <2000>;
4667 type 4444 type = "passive";
4668 }; 4445 };
4669 4446
4670 cpu1_crit: cp 4447 cpu1_crit: cpu-crit {
4671 tempe 4448 temperature = <110000>;
4672 hyste 4449 hysteresis = <1000>;
4673 type 4450 type = "critical";
4674 }; 4451 };
4675 }; 4452 };
4676 4453
4677 cooling-maps { 4454 cooling-maps {
4678 map0 { 4455 map0 {
4679 trip 4456 trip = <&cpu1_alert0>;
4680 cooli 4457 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4458 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4459 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4460 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4461 };
4685 map1 { 4462 map1 {
4686 trip 4463 trip = <&cpu1_alert1>;
4687 cooli 4464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4468 };
4692 }; 4469 };
4693 }; 4470 };
4694 4471
4695 cpu2-thermal { 4472 cpu2-thermal {
4696 polling-delay-passive 4473 polling-delay-passive = <250>;
>> 4474 polling-delay = <1000>;
4697 4475
4698 thermal-sensors = <&t 4476 thermal-sensors = <&tsens0 3>;
4699 4477
4700 trips { 4478 trips {
4701 cpu2_alert0: 4479 cpu2_alert0: trip-point0 {
4702 tempe 4480 temperature = <90000>;
4703 hyste 4481 hysteresis = <2000>;
4704 type 4482 type = "passive";
4705 }; 4483 };
4706 4484
4707 cpu2_alert1: 4485 cpu2_alert1: trip-point1 {
4708 tempe 4486 temperature = <95000>;
4709 hyste 4487 hysteresis = <2000>;
4710 type 4488 type = "passive";
4711 }; 4489 };
4712 4490
4713 cpu2_crit: cp 4491 cpu2_crit: cpu-crit {
4714 tempe 4492 temperature = <110000>;
4715 hyste 4493 hysteresis = <1000>;
4716 type 4494 type = "critical";
4717 }; 4495 };
4718 }; 4496 };
4719 4497
4720 cooling-maps { 4498 cooling-maps {
4721 map0 { 4499 map0 {
4722 trip 4500 trip = <&cpu2_alert0>;
4723 cooli 4501 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4502 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4503 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4504 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4505 };
4728 map1 { 4506 map1 {
4729 trip 4507 trip = <&cpu2_alert1>;
4730 cooli 4508 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4509 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4510 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4511 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4512 };
4735 }; 4513 };
4736 }; 4514 };
4737 4515
4738 cpu3-thermal { 4516 cpu3-thermal {
4739 polling-delay-passive 4517 polling-delay-passive = <250>;
>> 4518 polling-delay = <1000>;
4740 4519
4741 thermal-sensors = <&t 4520 thermal-sensors = <&tsens0 4>;
4742 4521
4743 trips { 4522 trips {
4744 cpu3_alert0: 4523 cpu3_alert0: trip-point0 {
4745 tempe 4524 temperature = <90000>;
4746 hyste 4525 hysteresis = <2000>;
4747 type 4526 type = "passive";
4748 }; 4527 };
4749 4528
4750 cpu3_alert1: 4529 cpu3_alert1: trip-point1 {
4751 tempe 4530 temperature = <95000>;
4752 hyste 4531 hysteresis = <2000>;
4753 type 4532 type = "passive";
4754 }; 4533 };
4755 4534
4756 cpu3_crit: cp 4535 cpu3_crit: cpu-crit {
4757 tempe 4536 temperature = <110000>;
4758 hyste 4537 hysteresis = <1000>;
4759 type 4538 type = "critical";
4760 }; 4539 };
4761 }; 4540 };
4762 4541
4763 cooling-maps { 4542 cooling-maps {
4764 map0 { 4543 map0 {
4765 trip 4544 trip = <&cpu3_alert0>;
4766 cooli 4545 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4546 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4547 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4548 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4549 };
4771 map1 { 4550 map1 {
4772 trip 4551 trip = <&cpu3_alert1>;
4773 cooli 4552 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4553 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4554 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4555 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4556 };
4778 }; 4557 };
4779 }; 4558 };
4780 4559
4781 cpu4-top-thermal { 4560 cpu4-top-thermal {
4782 polling-delay-passive 4561 polling-delay-passive = <250>;
>> 4562 polling-delay = <1000>;
4783 4563
4784 thermal-sensors = <&t 4564 thermal-sensors = <&tsens0 7>;
4785 4565
4786 trips { 4566 trips {
4787 cpu4_top_aler 4567 cpu4_top_alert0: trip-point0 {
4788 tempe 4568 temperature = <90000>;
4789 hyste 4569 hysteresis = <2000>;
4790 type 4570 type = "passive";
4791 }; 4571 };
4792 4572
4793 cpu4_top_aler 4573 cpu4_top_alert1: trip-point1 {
4794 tempe 4574 temperature = <95000>;
4795 hyste 4575 hysteresis = <2000>;
4796 type 4576 type = "passive";
4797 }; 4577 };
4798 4578
4799 cpu4_top_crit 4579 cpu4_top_crit: cpu-crit {
4800 tempe 4580 temperature = <110000>;
4801 hyste 4581 hysteresis = <1000>;
4802 type 4582 type = "critical";
4803 }; 4583 };
4804 }; 4584 };
4805 4585
4806 cooling-maps { 4586 cooling-maps {
4807 map0 { 4587 map0 {
4808 trip 4588 trip = <&cpu4_top_alert0>;
4809 cooli 4589 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4590 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4591 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4592 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4593 };
4814 map1 { 4594 map1 {
4815 trip 4595 trip = <&cpu4_top_alert1>;
4816 cooli 4596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4600 };
4821 }; 4601 };
4822 }; 4602 };
4823 4603
4824 cpu5-top-thermal { 4604 cpu5-top-thermal {
4825 polling-delay-passive 4605 polling-delay-passive = <250>;
>> 4606 polling-delay = <1000>;
4826 4607
4827 thermal-sensors = <&t 4608 thermal-sensors = <&tsens0 8>;
4828 4609
4829 trips { 4610 trips {
4830 cpu5_top_aler 4611 cpu5_top_alert0: trip-point0 {
4831 tempe 4612 temperature = <90000>;
4832 hyste 4613 hysteresis = <2000>;
4833 type 4614 type = "passive";
4834 }; 4615 };
4835 4616
4836 cpu5_top_aler 4617 cpu5_top_alert1: trip-point1 {
4837 tempe 4618 temperature = <95000>;
4838 hyste 4619 hysteresis = <2000>;
4839 type 4620 type = "passive";
4840 }; 4621 };
4841 4622
4842 cpu5_top_crit 4623 cpu5_top_crit: cpu-crit {
4843 tempe 4624 temperature = <110000>;
4844 hyste 4625 hysteresis = <1000>;
4845 type 4626 type = "critical";
4846 }; 4627 };
4847 }; 4628 };
4848 4629
4849 cooling-maps { 4630 cooling-maps {
4850 map0 { 4631 map0 {
4851 trip 4632 trip = <&cpu5_top_alert0>;
4852 cooli 4633 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4634 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4635 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4636 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4637 };
4857 map1 { 4638 map1 {
4858 trip 4639 trip = <&cpu5_top_alert1>;
4859 cooli 4640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4644 };
4864 }; 4645 };
4865 }; 4646 };
4866 4647
4867 cpu6-top-thermal { 4648 cpu6-top-thermal {
4868 polling-delay-passive 4649 polling-delay-passive = <250>;
>> 4650 polling-delay = <1000>;
4869 4651
4870 thermal-sensors = <&t 4652 thermal-sensors = <&tsens0 9>;
4871 4653
4872 trips { 4654 trips {
4873 cpu6_top_aler 4655 cpu6_top_alert0: trip-point0 {
4874 tempe 4656 temperature = <90000>;
4875 hyste 4657 hysteresis = <2000>;
4876 type 4658 type = "passive";
4877 }; 4659 };
4878 4660
4879 cpu6_top_aler 4661 cpu6_top_alert1: trip-point1 {
4880 tempe 4662 temperature = <95000>;
4881 hyste 4663 hysteresis = <2000>;
4882 type 4664 type = "passive";
4883 }; 4665 };
4884 4666
4885 cpu6_top_crit 4667 cpu6_top_crit: cpu-crit {
4886 tempe 4668 temperature = <110000>;
4887 hyste 4669 hysteresis = <1000>;
4888 type 4670 type = "critical";
4889 }; 4671 };
4890 }; 4672 };
4891 4673
4892 cooling-maps { 4674 cooling-maps {
4893 map0 { 4675 map0 {
4894 trip 4676 trip = <&cpu6_top_alert0>;
4895 cooli 4677 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4678 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4679 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4680 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4681 };
4900 map1 { 4682 map1 {
4901 trip 4683 trip = <&cpu6_top_alert1>;
4902 cooli 4684 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4686 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4687 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4688 };
4907 }; 4689 };
4908 }; 4690 };
4909 4691
4910 cpu7-top-thermal { 4692 cpu7-top-thermal {
4911 polling-delay-passive 4693 polling-delay-passive = <250>;
>> 4694 polling-delay = <1000>;
4912 4695
4913 thermal-sensors = <&t 4696 thermal-sensors = <&tsens0 10>;
4914 4697
4915 trips { 4698 trips {
4916 cpu7_top_aler 4699 cpu7_top_alert0: trip-point0 {
4917 tempe 4700 temperature = <90000>;
4918 hyste 4701 hysteresis = <2000>;
4919 type 4702 type = "passive";
4920 }; 4703 };
4921 4704
4922 cpu7_top_aler 4705 cpu7_top_alert1: trip-point1 {
4923 tempe 4706 temperature = <95000>;
4924 hyste 4707 hysteresis = <2000>;
4925 type 4708 type = "passive";
4926 }; 4709 };
4927 4710
4928 cpu7_top_crit 4711 cpu7_top_crit: cpu-crit {
4929 tempe 4712 temperature = <110000>;
4930 hyste 4713 hysteresis = <1000>;
4931 type 4714 type = "critical";
4932 }; 4715 };
4933 }; 4716 };
4934 4717
4935 cooling-maps { 4718 cooling-maps {
4936 map0 { 4719 map0 {
4937 trip 4720 trip = <&cpu7_top_alert0>;
4938 cooli 4721 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4722 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4723 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4724 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4725 };
4943 map1 { 4726 map1 {
4944 trip 4727 trip = <&cpu7_top_alert1>;
4945 cooli 4728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4732 };
4950 }; 4733 };
4951 }; 4734 };
4952 4735
4953 cpu4-bottom-thermal { 4736 cpu4-bottom-thermal {
4954 polling-delay-passive 4737 polling-delay-passive = <250>;
>> 4738 polling-delay = <1000>;
4955 4739
4956 thermal-sensors = <&t 4740 thermal-sensors = <&tsens0 11>;
4957 4741
4958 trips { 4742 trips {
4959 cpu4_bottom_a 4743 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4744 temperature = <90000>;
4961 hyste 4745 hysteresis = <2000>;
4962 type 4746 type = "passive";
4963 }; 4747 };
4964 4748
4965 cpu4_bottom_a 4749 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4750 temperature = <95000>;
4967 hyste 4751 hysteresis = <2000>;
4968 type 4752 type = "passive";
4969 }; 4753 };
4970 4754
4971 cpu4_bottom_c 4755 cpu4_bottom_crit: cpu-crit {
4972 tempe 4756 temperature = <110000>;
4973 hyste 4757 hysteresis = <1000>;
4974 type 4758 type = "critical";
4975 }; 4759 };
4976 }; 4760 };
4977 4761
4978 cooling-maps { 4762 cooling-maps {
4979 map0 { 4763 map0 {
4980 trip 4764 trip = <&cpu4_bottom_alert0>;
4981 cooli 4765 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4766 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4767 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4768 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4769 };
4986 map1 { 4770 map1 {
4987 trip 4771 trip = <&cpu4_bottom_alert1>;
4988 cooli 4772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4776 };
4993 }; 4777 };
4994 }; 4778 };
4995 4779
4996 cpu5-bottom-thermal { 4780 cpu5-bottom-thermal {
4997 polling-delay-passive 4781 polling-delay-passive = <250>;
>> 4782 polling-delay = <1000>;
4998 4783
4999 thermal-sensors = <&t 4784 thermal-sensors = <&tsens0 12>;
5000 4785
5001 trips { 4786 trips {
5002 cpu5_bottom_a 4787 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4788 temperature = <90000>;
5004 hyste 4789 hysteresis = <2000>;
5005 type 4790 type = "passive";
5006 }; 4791 };
5007 4792
5008 cpu5_bottom_a 4793 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4794 temperature = <95000>;
5010 hyste 4795 hysteresis = <2000>;
5011 type 4796 type = "passive";
5012 }; 4797 };
5013 4798
5014 cpu5_bottom_c 4799 cpu5_bottom_crit: cpu-crit {
5015 tempe 4800 temperature = <110000>;
5016 hyste 4801 hysteresis = <1000>;
5017 type 4802 type = "critical";
5018 }; 4803 };
5019 }; 4804 };
5020 4805
5021 cooling-maps { 4806 cooling-maps {
5022 map0 { 4807 map0 {
5023 trip 4808 trip = <&cpu5_bottom_alert0>;
5024 cooli 4809 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4810 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4811 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4812 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4813 };
5029 map1 { 4814 map1 {
5030 trip 4815 trip = <&cpu5_bottom_alert1>;
5031 cooli 4816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4820 };
5036 }; 4821 };
5037 }; 4822 };
5038 4823
5039 cpu6-bottom-thermal { 4824 cpu6-bottom-thermal {
5040 polling-delay-passive 4825 polling-delay-passive = <250>;
>> 4826 polling-delay = <1000>;
5041 4827
5042 thermal-sensors = <&t 4828 thermal-sensors = <&tsens0 13>;
5043 4829
5044 trips { 4830 trips {
5045 cpu6_bottom_a 4831 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4832 temperature = <90000>;
5047 hyste 4833 hysteresis = <2000>;
5048 type 4834 type = "passive";
5049 }; 4835 };
5050 4836
5051 cpu6_bottom_a 4837 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4838 temperature = <95000>;
5053 hyste 4839 hysteresis = <2000>;
5054 type 4840 type = "passive";
5055 }; 4841 };
5056 4842
5057 cpu6_bottom_c 4843 cpu6_bottom_crit: cpu-crit {
5058 tempe 4844 temperature = <110000>;
5059 hyste 4845 hysteresis = <1000>;
5060 type 4846 type = "critical";
5061 }; 4847 };
5062 }; 4848 };
5063 4849
5064 cooling-maps { 4850 cooling-maps {
5065 map0 { 4851 map0 {
5066 trip 4852 trip = <&cpu6_bottom_alert0>;
5067 cooli 4853 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4855 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4856 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4857 };
5072 map1 { 4858 map1 {
5073 trip 4859 trip = <&cpu6_bottom_alert1>;
5074 cooli 4860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4864 };
5079 }; 4865 };
5080 }; 4866 };
5081 4867
5082 cpu7-bottom-thermal { 4868 cpu7-bottom-thermal {
5083 polling-delay-passive 4869 polling-delay-passive = <250>;
>> 4870 polling-delay = <1000>;
5084 4871
5085 thermal-sensors = <&t 4872 thermal-sensors = <&tsens0 14>;
5086 4873
5087 trips { 4874 trips {
5088 cpu7_bottom_a 4875 cpu7_bottom_alert0: trip-point0 {
5089 tempe 4876 temperature = <90000>;
5090 hyste 4877 hysteresis = <2000>;
5091 type 4878 type = "passive";
5092 }; 4879 };
5093 4880
5094 cpu7_bottom_a 4881 cpu7_bottom_alert1: trip-point1 {
5095 tempe 4882 temperature = <95000>;
5096 hyste 4883 hysteresis = <2000>;
5097 type 4884 type = "passive";
5098 }; 4885 };
5099 4886
5100 cpu7_bottom_c 4887 cpu7_bottom_crit: cpu-crit {
5101 tempe 4888 temperature = <110000>;
5102 hyste 4889 hysteresis = <1000>;
5103 type 4890 type = "critical";
5104 }; 4891 };
5105 }; 4892 };
5106 4893
5107 cooling-maps { 4894 cooling-maps {
5108 map0 { 4895 map0 {
5109 trip 4896 trip = <&cpu7_bottom_alert0>;
5110 cooli 4897 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 4898 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 4899 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 4900 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 4901 };
5115 map1 { 4902 map1 {
5116 trip 4903 trip = <&cpu7_bottom_alert1>;
5117 cooli 4904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 4905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 4906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 4907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 4908 };
5122 }; 4909 };
5123 }; 4910 };
5124 4911
5125 aoss0-thermal { 4912 aoss0-thermal {
5126 polling-delay-passive 4913 polling-delay-passive = <250>;
>> 4914 polling-delay = <1000>;
5127 4915
5128 thermal-sensors = <&t 4916 thermal-sensors = <&tsens0 0>;
5129 4917
5130 trips { 4918 trips {
5131 aoss0_alert0: 4919 aoss0_alert0: trip-point0 {
5132 tempe 4920 temperature = <90000>;
5133 hyste 4921 hysteresis = <2000>;
5134 type 4922 type = "hot";
5135 }; 4923 };
5136 }; 4924 };
5137 }; 4925 };
5138 4926
5139 cluster0-thermal { 4927 cluster0-thermal {
5140 polling-delay-passive 4928 polling-delay-passive = <250>;
>> 4929 polling-delay = <1000>;
5141 4930
5142 thermal-sensors = <&t 4931 thermal-sensors = <&tsens0 5>;
5143 4932
5144 trips { 4933 trips {
5145 cluster0_aler 4934 cluster0_alert0: trip-point0 {
5146 tempe 4935 temperature = <90000>;
5147 hyste 4936 hysteresis = <2000>;
5148 type 4937 type = "hot";
5149 }; 4938 };
5150 cluster0_crit !! 4939 cluster0_crit: cluster0_crit {
5151 tempe 4940 temperature = <110000>;
5152 hyste 4941 hysteresis = <2000>;
5153 type 4942 type = "critical";
5154 }; 4943 };
5155 }; 4944 };
5156 }; 4945 };
5157 4946
5158 cluster1-thermal { 4947 cluster1-thermal {
5159 polling-delay-passive 4948 polling-delay-passive = <250>;
>> 4949 polling-delay = <1000>;
5160 4950
5161 thermal-sensors = <&t 4951 thermal-sensors = <&tsens0 6>;
5162 4952
5163 trips { 4953 trips {
5164 cluster1_aler 4954 cluster1_alert0: trip-point0 {
5165 tempe 4955 temperature = <90000>;
5166 hyste 4956 hysteresis = <2000>;
5167 type 4957 type = "hot";
5168 }; 4958 };
5169 cluster1_crit !! 4959 cluster1_crit: cluster1_crit {
5170 tempe 4960 temperature = <110000>;
5171 hyste 4961 hysteresis = <2000>;
5172 type 4962 type = "critical";
5173 }; 4963 };
5174 }; 4964 };
5175 }; 4965 };
5176 4966
5177 gpu-top-thermal { 4967 gpu-top-thermal {
5178 polling-delay-passive 4968 polling-delay-passive = <250>;
>> 4969 polling-delay = <1000>;
5179 4970
5180 thermal-sensors = <&t 4971 thermal-sensors = <&tsens0 15>;
5181 4972
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 4973 trips {
5190 gpu_top_alert !! 4974 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 4975 temperature = <90000>;
5198 hyste !! 4976 hysteresis = <2000>;
5199 type 4977 type = "hot";
5200 }; 4978 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 4979 };
5208 }; 4980 };
5209 4981
5210 aoss1-thermal { 4982 aoss1-thermal {
5211 polling-delay-passive 4983 polling-delay-passive = <250>;
>> 4984 polling-delay = <1000>;
5212 4985
5213 thermal-sensors = <&t 4986 thermal-sensors = <&tsens1 0>;
5214 4987
5215 trips { 4988 trips {
5216 aoss1_alert0: 4989 aoss1_alert0: trip-point0 {
5217 tempe 4990 temperature = <90000>;
5218 hyste 4991 hysteresis = <2000>;
5219 type 4992 type = "hot";
5220 }; 4993 };
5221 }; 4994 };
5222 }; 4995 };
5223 4996
5224 wlan-thermal { 4997 wlan-thermal {
5225 polling-delay-passive 4998 polling-delay-passive = <250>;
>> 4999 polling-delay = <1000>;
5226 5000
5227 thermal-sensors = <&t 5001 thermal-sensors = <&tsens1 1>;
5228 5002
5229 trips { 5003 trips {
5230 wlan_alert0: 5004 wlan_alert0: trip-point0 {
5231 tempe 5005 temperature = <90000>;
5232 hyste 5006 hysteresis = <2000>;
5233 type 5007 type = "hot";
5234 }; 5008 };
5235 }; 5009 };
5236 }; 5010 };
5237 5011
5238 video-thermal { 5012 video-thermal {
5239 polling-delay-passive 5013 polling-delay-passive = <250>;
>> 5014 polling-delay = <1000>;
5240 5015
5241 thermal-sensors = <&t 5016 thermal-sensors = <&tsens1 2>;
5242 5017
5243 trips { 5018 trips {
5244 video_alert0: 5019 video_alert0: trip-point0 {
5245 tempe 5020 temperature = <90000>;
5246 hyste 5021 hysteresis = <2000>;
5247 type 5022 type = "hot";
5248 }; 5023 };
5249 }; 5024 };
5250 }; 5025 };
5251 5026
5252 mem-thermal { 5027 mem-thermal {
5253 polling-delay-passive 5028 polling-delay-passive = <250>;
>> 5029 polling-delay = <1000>;
5254 5030
5255 thermal-sensors = <&t 5031 thermal-sensors = <&tsens1 3>;
5256 5032
5257 trips { 5033 trips {
5258 mem_alert0: t 5034 mem_alert0: trip-point0 {
5259 tempe 5035 temperature = <90000>;
5260 hyste 5036 hysteresis = <2000>;
5261 type 5037 type = "hot";
5262 }; 5038 };
5263 }; 5039 };
5264 }; 5040 };
5265 5041
5266 q6-hvx-thermal { 5042 q6-hvx-thermal {
5267 polling-delay-passive 5043 polling-delay-passive = <250>;
>> 5044 polling-delay = <1000>;
5268 5045
5269 thermal-sensors = <&t 5046 thermal-sensors = <&tsens1 4>;
5270 5047
5271 trips { 5048 trips {
5272 q6_hvx_alert0 5049 q6_hvx_alert0: trip-point0 {
5273 tempe 5050 temperature = <90000>;
5274 hyste 5051 hysteresis = <2000>;
5275 type 5052 type = "hot";
5276 }; 5053 };
5277 }; 5054 };
5278 }; 5055 };
5279 5056
5280 camera-thermal { 5057 camera-thermal {
5281 polling-delay-passive 5058 polling-delay-passive = <250>;
>> 5059 polling-delay = <1000>;
5282 5060
5283 thermal-sensors = <&t 5061 thermal-sensors = <&tsens1 5>;
5284 5062
5285 trips { 5063 trips {
5286 camera_alert0 5064 camera_alert0: trip-point0 {
5287 tempe 5065 temperature = <90000>;
5288 hyste 5066 hysteresis = <2000>;
5289 type 5067 type = "hot";
5290 }; 5068 };
5291 }; 5069 };
5292 }; 5070 };
5293 5071
5294 compute-thermal { 5072 compute-thermal {
5295 polling-delay-passive 5073 polling-delay-passive = <250>;
>> 5074 polling-delay = <1000>;
5296 5075
5297 thermal-sensors = <&t 5076 thermal-sensors = <&tsens1 6>;
5298 5077
5299 trips { 5078 trips {
5300 compute_alert 5079 compute_alert0: trip-point0 {
5301 tempe 5080 temperature = <90000>;
5302 hyste 5081 hysteresis = <2000>;
5303 type 5082 type = "hot";
5304 }; 5083 };
5305 }; 5084 };
5306 }; 5085 };
5307 5086
5308 modem-thermal { 5087 modem-thermal {
5309 polling-delay-passive 5088 polling-delay-passive = <250>;
>> 5089 polling-delay = <1000>;
5310 5090
5311 thermal-sensors = <&t 5091 thermal-sensors = <&tsens1 7>;
5312 5092
5313 trips { 5093 trips {
5314 modem_alert0: 5094 modem_alert0: trip-point0 {
5315 tempe 5095 temperature = <90000>;
5316 hyste 5096 hysteresis = <2000>;
5317 type 5097 type = "hot";
5318 }; 5098 };
5319 }; 5099 };
5320 }; 5100 };
5321 5101
5322 npu-thermal { 5102 npu-thermal {
5323 polling-delay-passive 5103 polling-delay-passive = <250>;
>> 5104 polling-delay = <1000>;
5324 5105
5325 thermal-sensors = <&t 5106 thermal-sensors = <&tsens1 8>;
5326 5107
5327 trips { 5108 trips {
5328 npu_alert0: t 5109 npu_alert0: trip-point0 {
5329 tempe 5110 temperature = <90000>;
5330 hyste 5111 hysteresis = <2000>;
5331 type 5112 type = "hot";
5332 }; 5113 };
5333 }; 5114 };
5334 }; 5115 };
5335 5116
5336 modem-vec-thermal { 5117 modem-vec-thermal {
5337 polling-delay-passive 5118 polling-delay-passive = <250>;
>> 5119 polling-delay = <1000>;
5338 5120
5339 thermal-sensors = <&t 5121 thermal-sensors = <&tsens1 9>;
5340 5122
5341 trips { 5123 trips {
5342 modem_vec_ale 5124 modem_vec_alert0: trip-point0 {
5343 tempe 5125 temperature = <90000>;
5344 hyste 5126 hysteresis = <2000>;
5345 type 5127 type = "hot";
5346 }; 5128 };
5347 }; 5129 };
5348 }; 5130 };
5349 5131
5350 modem-scl-thermal { 5132 modem-scl-thermal {
5351 polling-delay-passive 5133 polling-delay-passive = <250>;
>> 5134 polling-delay = <1000>;
5352 5135
5353 thermal-sensors = <&t 5136 thermal-sensors = <&tsens1 10>;
5354 5137
5355 trips { 5138 trips {
5356 modem_scl_ale 5139 modem_scl_alert0: trip-point0 {
5357 tempe 5140 temperature = <90000>;
5358 hyste 5141 hysteresis = <2000>;
5359 type 5142 type = "hot";
5360 }; 5143 };
5361 }; 5144 };
5362 }; 5145 };
5363 5146
5364 gpu-bottom-thermal { 5147 gpu-bottom-thermal {
5365 polling-delay-passive 5148 polling-delay-passive = <250>;
>> 5149 polling-delay = <1000>;
5366 5150
5367 thermal-sensors = <&t 5151 thermal-sensors = <&tsens1 11>;
5368 5152
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 5153 trips {
5377 gpu_bottom_al !! 5154 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 5155 temperature = <90000>;
5385 hyste !! 5156 hysteresis = <2000>;
5386 type 5157 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 5158 };
5394 }; 5159 };
5395 }; 5160 };
5396 }; 5161 };
5397 }; 5162 };
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