1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2017-2019, The Linux Foundati 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2019, Linaro Limited 4 * Copyright (c) 2019, Linaro Limited
5 */ 5 */
6 6
7 #include <dt-bindings/dma/qcom-gpi.h> 7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/firmware/qcom,scm.h> 8 #include <dt-bindings/firmware/qcom,scm.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/phy/phy-qcom-qmp.h> 10 #include <dt-bindings/phy/phy-qcom-qmp.h>
11 #include <dt-bindings/power/qcom-rpmpd.h> 11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
13 #include <dt-bindings/clock/qcom,rpmh.h> 13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,dispcc-sm8150 14 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
15 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 15 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
16 #include <dt-bindings/clock/qcom,gpucc-sm8150. 16 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
17 #include <dt-bindings/clock/qcom,videocc-sm815 <<
18 #include <dt-bindings/interconnect/qcom,osm-l3 17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sm8150 18 #include <dt-bindings/interconnect/qcom,sm8150.h>
20 #include <dt-bindings/clock/qcom,sm8150-camcc. <<
21 #include <dt-bindings/thermal/thermal.h> 19 #include <dt-bindings/thermal/thermal.h>
22 20
23 / { 21 / {
24 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
25 23
26 #address-cells = <2>; 24 #address-cells = <2>;
27 #size-cells = <2>; 25 #size-cells = <2>;
28 26
29 chosen { }; 27 chosen { };
30 28
31 clocks { 29 clocks {
32 xo_board: xo-board { 30 xo_board: xo-board {
33 compatible = "fixed-cl 31 compatible = "fixed-clock";
34 #clock-cells = <0>; 32 #clock-cells = <0>;
35 clock-frequency = <384 33 clock-frequency = <38400000>;
36 clock-output-names = " 34 clock-output-names = "xo_board";
37 }; 35 };
38 36
39 sleep_clk: sleep-clk { 37 sleep_clk: sleep-clk {
40 compatible = "fixed-cl 38 compatible = "fixed-clock";
41 #clock-cells = <0>; 39 #clock-cells = <0>;
42 clock-frequency = <327 40 clock-frequency = <32764>;
43 clock-output-names = " 41 clock-output-names = "sleep_clk";
44 }; 42 };
45 }; 43 };
46 44
47 cpus { 45 cpus {
48 #address-cells = <2>; 46 #address-cells = <2>;
49 #size-cells = <0>; 47 #size-cells = <0>;
50 48
51 CPU0: cpu@0 { 49 CPU0: cpu@0 {
52 device_type = "cpu"; 50 device_type = "cpu";
53 compatible = "qcom,kry 51 compatible = "qcom,kryo485";
54 reg = <0x0 0x0>; 52 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 53 clocks = <&cpufreq_hw 0>;
56 enable-method = "psci" 54 enable-method = "psci";
57 capacity-dmips-mhz = < 55 capacity-dmips-mhz = <488>;
58 dynamic-power-coeffici 56 dynamic-power-coefficient = <232>;
59 next-level-cache = <&L 57 next-level-cache = <&L2_0>;
60 qcom,freq-domain = <&c 58 qcom,freq-domain = <&cpufreq_hw 0>;
61 operating-points-v2 = 59 operating-points-v2 = <&cpu0_opp_table>;
62 interconnects = <&gem_ 60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
63 <&osm_ 61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
64 power-domains = <&CPU_ 62 power-domains = <&CPU_PD0>;
65 power-domain-names = " 63 power-domain-names = "psci";
66 #cooling-cells = <2>; 64 #cooling-cells = <2>;
67 L2_0: l2-cache { 65 L2_0: l2-cache {
68 compatible = " 66 compatible = "cache";
69 cache-level = 67 cache-level = <2>;
70 cache-unified; 68 cache-unified;
71 next-level-cac 69 next-level-cache = <&L3_0>;
72 L3_0: l3-cache 70 L3_0: l3-cache {
73 compat 71 compatible = "cache";
74 cache- 72 cache-level = <3>;
75 cache- 73 cache-unified;
76 }; 74 };
77 }; 75 };
78 }; 76 };
79 77
80 CPU1: cpu@100 { 78 CPU1: cpu@100 {
81 device_type = "cpu"; 79 device_type = "cpu";
82 compatible = "qcom,kry 80 compatible = "qcom,kryo485";
83 reg = <0x0 0x100>; 81 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 82 clocks = <&cpufreq_hw 0>;
85 enable-method = "psci" 83 enable-method = "psci";
86 capacity-dmips-mhz = < 84 capacity-dmips-mhz = <488>;
87 dynamic-power-coeffici 85 dynamic-power-coefficient = <232>;
88 next-level-cache = <&L 86 next-level-cache = <&L2_100>;
89 qcom,freq-domain = <&c 87 qcom,freq-domain = <&cpufreq_hw 0>;
90 operating-points-v2 = 88 operating-points-v2 = <&cpu0_opp_table>;
91 interconnects = <&gem_ 89 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
92 <&osm_ 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
93 power-domains = <&CPU_ 91 power-domains = <&CPU_PD1>;
94 power-domain-names = " 92 power-domain-names = "psci";
95 #cooling-cells = <2>; 93 #cooling-cells = <2>;
96 L2_100: l2-cache { 94 L2_100: l2-cache {
97 compatible = " 95 compatible = "cache";
98 cache-level = 96 cache-level = <2>;
99 cache-unified; 97 cache-unified;
100 next-level-cac 98 next-level-cache = <&L3_0>;
101 }; 99 };
102 }; 100 };
103 101
104 CPU2: cpu@200 { 102 CPU2: cpu@200 {
105 device_type = "cpu"; 103 device_type = "cpu";
106 compatible = "qcom,kry 104 compatible = "qcom,kryo485";
107 reg = <0x0 0x200>; 105 reg = <0x0 0x200>;
108 clocks = <&cpufreq_hw 106 clocks = <&cpufreq_hw 0>;
109 enable-method = "psci" 107 enable-method = "psci";
110 capacity-dmips-mhz = < 108 capacity-dmips-mhz = <488>;
111 dynamic-power-coeffici 109 dynamic-power-coefficient = <232>;
112 next-level-cache = <&L 110 next-level-cache = <&L2_200>;
113 qcom,freq-domain = <&c 111 qcom,freq-domain = <&cpufreq_hw 0>;
114 operating-points-v2 = 112 operating-points-v2 = <&cpu0_opp_table>;
115 interconnects = <&gem_ 113 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 <&osm_ 114 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
117 power-domains = <&CPU_ 115 power-domains = <&CPU_PD2>;
118 power-domain-names = " 116 power-domain-names = "psci";
119 #cooling-cells = <2>; 117 #cooling-cells = <2>;
120 L2_200: l2-cache { 118 L2_200: l2-cache {
121 compatible = " 119 compatible = "cache";
122 cache-level = 120 cache-level = <2>;
123 cache-unified; 121 cache-unified;
124 next-level-cac 122 next-level-cache = <&L3_0>;
125 }; 123 };
126 }; 124 };
127 125
128 CPU3: cpu@300 { 126 CPU3: cpu@300 {
129 device_type = "cpu"; 127 device_type = "cpu";
130 compatible = "qcom,kry 128 compatible = "qcom,kryo485";
131 reg = <0x0 0x300>; 129 reg = <0x0 0x300>;
132 clocks = <&cpufreq_hw 130 clocks = <&cpufreq_hw 0>;
133 enable-method = "psci" 131 enable-method = "psci";
134 capacity-dmips-mhz = < 132 capacity-dmips-mhz = <488>;
135 dynamic-power-coeffici 133 dynamic-power-coefficient = <232>;
136 next-level-cache = <&L 134 next-level-cache = <&L2_300>;
137 qcom,freq-domain = <&c 135 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = 136 operating-points-v2 = <&cpu0_opp_table>;
139 interconnects = <&gem_ 137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
140 <&osm_ 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
141 power-domains = <&CPU_ 139 power-domains = <&CPU_PD3>;
142 power-domain-names = " 140 power-domain-names = "psci";
143 #cooling-cells = <2>; 141 #cooling-cells = <2>;
144 L2_300: l2-cache { 142 L2_300: l2-cache {
145 compatible = " 143 compatible = "cache";
146 cache-level = 144 cache-level = <2>;
147 cache-unified; 145 cache-unified;
148 next-level-cac 146 next-level-cache = <&L3_0>;
149 }; 147 };
150 }; 148 };
151 149
152 CPU4: cpu@400 { 150 CPU4: cpu@400 {
153 device_type = "cpu"; 151 device_type = "cpu";
154 compatible = "qcom,kry 152 compatible = "qcom,kryo485";
155 reg = <0x0 0x400>; 153 reg = <0x0 0x400>;
156 clocks = <&cpufreq_hw 154 clocks = <&cpufreq_hw 1>;
157 enable-method = "psci" 155 enable-method = "psci";
158 capacity-dmips-mhz = < 156 capacity-dmips-mhz = <1024>;
159 dynamic-power-coeffici 157 dynamic-power-coefficient = <369>;
160 next-level-cache = <&L 158 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&c 159 qcom,freq-domain = <&cpufreq_hw 1>;
162 operating-points-v2 = 160 operating-points-v2 = <&cpu4_opp_table>;
163 interconnects = <&gem_ 161 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
164 <&osm_ 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
165 power-domains = <&CPU_ 163 power-domains = <&CPU_PD4>;
166 power-domain-names = " 164 power-domain-names = "psci";
167 #cooling-cells = <2>; 165 #cooling-cells = <2>;
168 L2_400: l2-cache { 166 L2_400: l2-cache {
169 compatible = " 167 compatible = "cache";
170 cache-level = 168 cache-level = <2>;
171 cache-unified; 169 cache-unified;
172 next-level-cac 170 next-level-cache = <&L3_0>;
173 }; 171 };
174 }; 172 };
175 173
176 CPU5: cpu@500 { 174 CPU5: cpu@500 {
177 device_type = "cpu"; 175 device_type = "cpu";
178 compatible = "qcom,kry 176 compatible = "qcom,kryo485";
179 reg = <0x0 0x500>; 177 reg = <0x0 0x500>;
180 clocks = <&cpufreq_hw 178 clocks = <&cpufreq_hw 1>;
181 enable-method = "psci" 179 enable-method = "psci";
182 capacity-dmips-mhz = < 180 capacity-dmips-mhz = <1024>;
183 dynamic-power-coeffici 181 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L 182 next-level-cache = <&L2_500>;
185 qcom,freq-domain = <&c 183 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = 184 operating-points-v2 = <&cpu4_opp_table>;
187 interconnects = <&gem_ 185 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
188 <&osm_ 186 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
189 power-domains = <&CPU_ 187 power-domains = <&CPU_PD5>;
190 power-domain-names = " 188 power-domain-names = "psci";
191 #cooling-cells = <2>; 189 #cooling-cells = <2>;
192 L2_500: l2-cache { 190 L2_500: l2-cache {
193 compatible = " 191 compatible = "cache";
194 cache-level = 192 cache-level = <2>;
195 cache-unified; 193 cache-unified;
196 next-level-cac 194 next-level-cache = <&L3_0>;
197 }; 195 };
198 }; 196 };
199 197
200 CPU6: cpu@600 { 198 CPU6: cpu@600 {
201 device_type = "cpu"; 199 device_type = "cpu";
202 compatible = "qcom,kry 200 compatible = "qcom,kryo485";
203 reg = <0x0 0x600>; 201 reg = <0x0 0x600>;
204 clocks = <&cpufreq_hw 202 clocks = <&cpufreq_hw 1>;
205 enable-method = "psci" 203 enable-method = "psci";
206 capacity-dmips-mhz = < 204 capacity-dmips-mhz = <1024>;
207 dynamic-power-coeffici 205 dynamic-power-coefficient = <369>;
208 next-level-cache = <&L 206 next-level-cache = <&L2_600>;
209 qcom,freq-domain = <&c 207 qcom,freq-domain = <&cpufreq_hw 1>;
210 operating-points-v2 = 208 operating-points-v2 = <&cpu4_opp_table>;
211 interconnects = <&gem_ 209 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
212 <&osm_ 210 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
213 power-domains = <&CPU_ 211 power-domains = <&CPU_PD6>;
214 power-domain-names = " 212 power-domain-names = "psci";
215 #cooling-cells = <2>; 213 #cooling-cells = <2>;
216 L2_600: l2-cache { 214 L2_600: l2-cache {
217 compatible = " 215 compatible = "cache";
218 cache-level = 216 cache-level = <2>;
219 cache-unified; 217 cache-unified;
220 next-level-cac 218 next-level-cache = <&L3_0>;
221 }; 219 };
222 }; 220 };
223 221
224 CPU7: cpu@700 { 222 CPU7: cpu@700 {
225 device_type = "cpu"; 223 device_type = "cpu";
226 compatible = "qcom,kry 224 compatible = "qcom,kryo485";
227 reg = <0x0 0x700>; 225 reg = <0x0 0x700>;
228 clocks = <&cpufreq_hw 226 clocks = <&cpufreq_hw 2>;
229 enable-method = "psci" 227 enable-method = "psci";
230 capacity-dmips-mhz = < 228 capacity-dmips-mhz = <1024>;
231 dynamic-power-coeffici 229 dynamic-power-coefficient = <421>;
232 next-level-cache = <&L 230 next-level-cache = <&L2_700>;
233 qcom,freq-domain = <&c 231 qcom,freq-domain = <&cpufreq_hw 2>;
234 operating-points-v2 = 232 operating-points-v2 = <&cpu7_opp_table>;
235 interconnects = <&gem_ 233 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
236 <&osm_ 234 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 power-domains = <&CPU_ 235 power-domains = <&CPU_PD7>;
238 power-domain-names = " 236 power-domain-names = "psci";
239 #cooling-cells = <2>; 237 #cooling-cells = <2>;
240 L2_700: l2-cache { 238 L2_700: l2-cache {
241 compatible = " 239 compatible = "cache";
242 cache-level = 240 cache-level = <2>;
243 cache-unified; 241 cache-unified;
244 next-level-cac 242 next-level-cache = <&L3_0>;
245 }; 243 };
246 }; 244 };
247 245
248 cpu-map { 246 cpu-map {
249 cluster0 { 247 cluster0 {
250 core0 { 248 core0 {
251 cpu = 249 cpu = <&CPU0>;
252 }; 250 };
253 251
254 core1 { 252 core1 {
255 cpu = 253 cpu = <&CPU1>;
256 }; 254 };
257 255
258 core2 { 256 core2 {
259 cpu = 257 cpu = <&CPU2>;
260 }; 258 };
261 259
262 core3 { 260 core3 {
263 cpu = 261 cpu = <&CPU3>;
264 }; 262 };
265 263
266 core4 { 264 core4 {
267 cpu = 265 cpu = <&CPU4>;
268 }; 266 };
269 267
270 core5 { 268 core5 {
271 cpu = 269 cpu = <&CPU5>;
272 }; 270 };
273 271
274 core6 { 272 core6 {
275 cpu = 273 cpu = <&CPU6>;
276 }; 274 };
277 275
278 core7 { 276 core7 {
279 cpu = 277 cpu = <&CPU7>;
280 }; 278 };
281 }; 279 };
282 }; 280 };
283 281
284 idle-states { 282 idle-states {
285 entry-method = "psci"; 283 entry-method = "psci";
286 284
287 LITTLE_CPU_SLEEP_0: cp 285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
288 compatible = " 286 compatible = "arm,idle-state";
289 idle-state-nam 287 idle-state-name = "little-rail-power-collapse";
290 arm,psci-suspe 288 arm,psci-suspend-param = <0x40000004>;
291 entry-latency- 289 entry-latency-us = <355>;
292 exit-latency-u 290 exit-latency-us = <909>;
293 min-residency- 291 min-residency-us = <3934>;
294 local-timer-st 292 local-timer-stop;
295 }; 293 };
296 294
297 BIG_CPU_SLEEP_0: cpu-s 295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
298 compatible = " 296 compatible = "arm,idle-state";
299 idle-state-nam 297 idle-state-name = "big-rail-power-collapse";
300 arm,psci-suspe 298 arm,psci-suspend-param = <0x40000004>;
301 entry-latency- 299 entry-latency-us = <241>;
302 exit-latency-u 300 exit-latency-us = <1461>;
303 min-residency- 301 min-residency-us = <4488>;
304 local-timer-st 302 local-timer-stop;
305 }; 303 };
306 }; 304 };
307 305
308 domain-idle-states { 306 domain-idle-states {
309 CLUSTER_SLEEP_0: clust 307 CLUSTER_SLEEP_0: cluster-sleep-0 {
310 compatible = " 308 compatible = "domain-idle-state";
311 arm,psci-suspe 309 arm,psci-suspend-param = <0x4100c244>;
312 entry-latency- 310 entry-latency-us = <3263>;
313 exit-latency-u 311 exit-latency-us = <6562>;
314 min-residency- 312 min-residency-us = <9987>;
315 }; 313 };
316 }; 314 };
317 }; 315 };
318 316
319 cpu0_opp_table: opp-table-cpu0 { 317 cpu0_opp_table: opp-table-cpu0 {
320 compatible = "operating-points 318 compatible = "operating-points-v2";
321 opp-shared; 319 opp-shared;
322 320
323 cpu0_opp1: opp-300000000 { 321 cpu0_opp1: opp-300000000 {
324 opp-hz = /bits/ 64 <30 322 opp-hz = /bits/ 64 <300000000>;
325 opp-peak-kBps = <80000 323 opp-peak-kBps = <800000 9600000>;
326 }; 324 };
327 325
328 cpu0_opp2: opp-403200000 { 326 cpu0_opp2: opp-403200000 {
329 opp-hz = /bits/ 64 <40 327 opp-hz = /bits/ 64 <403200000>;
330 opp-peak-kBps = <80000 328 opp-peak-kBps = <800000 9600000>;
331 }; 329 };
332 330
333 cpu0_opp3: opp-499200000 { 331 cpu0_opp3: opp-499200000 {
334 opp-hz = /bits/ 64 <49 332 opp-hz = /bits/ 64 <499200000>;
335 opp-peak-kBps = <80000 333 opp-peak-kBps = <800000 12902400>;
336 }; 334 };
337 335
338 cpu0_opp4: opp-576000000 { 336 cpu0_opp4: opp-576000000 {
339 opp-hz = /bits/ 64 <57 337 opp-hz = /bits/ 64 <576000000>;
340 opp-peak-kBps = <80000 338 opp-peak-kBps = <800000 12902400>;
341 }; 339 };
342 340
343 cpu0_opp5: opp-672000000 { 341 cpu0_opp5: opp-672000000 {
344 opp-hz = /bits/ 64 <67 342 opp-hz = /bits/ 64 <672000000>;
345 opp-peak-kBps = <80000 343 opp-peak-kBps = <800000 15974400>;
346 }; 344 };
347 345
348 cpu0_opp6: opp-768000000 { 346 cpu0_opp6: opp-768000000 {
349 opp-hz = /bits/ 64 <76 347 opp-hz = /bits/ 64 <768000000>;
350 opp-peak-kBps = <18040 348 opp-peak-kBps = <1804000 19660800>;
351 }; 349 };
352 350
353 cpu0_opp7: opp-844800000 { 351 cpu0_opp7: opp-844800000 {
354 opp-hz = /bits/ 64 <84 352 opp-hz = /bits/ 64 <844800000>;
355 opp-peak-kBps = <18040 353 opp-peak-kBps = <1804000 19660800>;
356 }; 354 };
357 355
358 cpu0_opp8: opp-940800000 { 356 cpu0_opp8: opp-940800000 {
359 opp-hz = /bits/ 64 <94 357 opp-hz = /bits/ 64 <940800000>;
360 opp-peak-kBps = <18040 358 opp-peak-kBps = <1804000 22732800>;
361 }; 359 };
362 360
363 cpu0_opp9: opp-1036800000 { 361 cpu0_opp9: opp-1036800000 {
364 opp-hz = /bits/ 64 <10 362 opp-hz = /bits/ 64 <1036800000>;
365 opp-peak-kBps = <18040 363 opp-peak-kBps = <1804000 22732800>;
366 }; 364 };
367 365
368 cpu0_opp10: opp-1113600000 { 366 cpu0_opp10: opp-1113600000 {
369 opp-hz = /bits/ 64 <11 367 opp-hz = /bits/ 64 <1113600000>;
370 opp-peak-kBps = <21880 368 opp-peak-kBps = <2188000 25804800>;
371 }; 369 };
372 370
373 cpu0_opp11: opp-1209600000 { 371 cpu0_opp11: opp-1209600000 {
374 opp-hz = /bits/ 64 <12 372 opp-hz = /bits/ 64 <1209600000>;
375 opp-peak-kBps = <21880 373 opp-peak-kBps = <2188000 31948800>;
376 }; 374 };
377 375
378 cpu0_opp12: opp-1305600000 { 376 cpu0_opp12: opp-1305600000 {
379 opp-hz = /bits/ 64 <13 377 opp-hz = /bits/ 64 <1305600000>;
380 opp-peak-kBps = <30720 378 opp-peak-kBps = <3072000 31948800>;
381 }; 379 };
382 380
383 cpu0_opp13: opp-1382400000 { 381 cpu0_opp13: opp-1382400000 {
384 opp-hz = /bits/ 64 <13 382 opp-hz = /bits/ 64 <1382400000>;
385 opp-peak-kBps = <30720 383 opp-peak-kBps = <3072000 31948800>;
386 }; 384 };
387 385
388 cpu0_opp14: opp-1478400000 { 386 cpu0_opp14: opp-1478400000 {
389 opp-hz = /bits/ 64 <14 387 opp-hz = /bits/ 64 <1478400000>;
390 opp-peak-kBps = <30720 388 opp-peak-kBps = <3072000 31948800>;
391 }; 389 };
392 390
393 cpu0_opp15: opp-1555200000 { 391 cpu0_opp15: opp-1555200000 {
394 opp-hz = /bits/ 64 <15 392 opp-hz = /bits/ 64 <1555200000>;
395 opp-peak-kBps = <30720 393 opp-peak-kBps = <3072000 40550400>;
396 }; 394 };
397 395
398 cpu0_opp16: opp-1632000000 { 396 cpu0_opp16: opp-1632000000 {
399 opp-hz = /bits/ 64 <16 397 opp-hz = /bits/ 64 <1632000000>;
400 opp-peak-kBps = <30720 398 opp-peak-kBps = <3072000 40550400>;
401 }; 399 };
402 400
403 cpu0_opp17: opp-1708800000 { 401 cpu0_opp17: opp-1708800000 {
404 opp-hz = /bits/ 64 <17 402 opp-hz = /bits/ 64 <1708800000>;
405 opp-peak-kBps = <30720 403 opp-peak-kBps = <3072000 43008000>;
406 }; 404 };
407 405
408 cpu0_opp18: opp-1785600000 { 406 cpu0_opp18: opp-1785600000 {
409 opp-hz = /bits/ 64 <17 407 opp-hz = /bits/ 64 <1785600000>;
410 opp-peak-kBps = <30720 408 opp-peak-kBps = <3072000 43008000>;
411 }; 409 };
412 }; 410 };
413 411
414 cpu4_opp_table: opp-table-cpu4 { 412 cpu4_opp_table: opp-table-cpu4 {
415 compatible = "operating-points 413 compatible = "operating-points-v2";
416 opp-shared; 414 opp-shared;
417 415
418 cpu4_opp1: opp-710400000 { 416 cpu4_opp1: opp-710400000 {
419 opp-hz = /bits/ 64 <71 417 opp-hz = /bits/ 64 <710400000>;
420 opp-peak-kBps = <18040 418 opp-peak-kBps = <1804000 15974400>;
421 }; 419 };
422 420
423 cpu4_opp2: opp-825600000 { 421 cpu4_opp2: opp-825600000 {
424 opp-hz = /bits/ 64 <82 422 opp-hz = /bits/ 64 <825600000>;
425 opp-peak-kBps = <21880 423 opp-peak-kBps = <2188000 19660800>;
426 }; 424 };
427 425
428 cpu4_opp3: opp-940800000 { 426 cpu4_opp3: opp-940800000 {
429 opp-hz = /bits/ 64 <94 427 opp-hz = /bits/ 64 <940800000>;
430 opp-peak-kBps = <21880 428 opp-peak-kBps = <2188000 22732800>;
431 }; 429 };
432 430
433 cpu4_opp4: opp-1056000000 { 431 cpu4_opp4: opp-1056000000 {
434 opp-hz = /bits/ 64 <10 432 opp-hz = /bits/ 64 <1056000000>;
435 opp-peak-kBps = <30720 433 opp-peak-kBps = <3072000 25804800>;
436 }; 434 };
437 435
438 cpu4_opp5: opp-1171200000 { 436 cpu4_opp5: opp-1171200000 {
439 opp-hz = /bits/ 64 <11 437 opp-hz = /bits/ 64 <1171200000>;
440 opp-peak-kBps = <30720 438 opp-peak-kBps = <3072000 31948800>;
441 }; 439 };
442 440
443 cpu4_opp6: opp-1286400000 { 441 cpu4_opp6: opp-1286400000 {
444 opp-hz = /bits/ 64 <12 442 opp-hz = /bits/ 64 <1286400000>;
445 opp-peak-kBps = <40680 443 opp-peak-kBps = <4068000 31948800>;
446 }; 444 };
447 445
448 cpu4_opp7: opp-1401600000 { 446 cpu4_opp7: opp-1401600000 {
449 opp-hz = /bits/ 64 <14 447 opp-hz = /bits/ 64 <1401600000>;
450 opp-peak-kBps = <40680 448 opp-peak-kBps = <4068000 31948800>;
451 }; 449 };
452 450
453 cpu4_opp8: opp-1497600000 { 451 cpu4_opp8: opp-1497600000 {
454 opp-hz = /bits/ 64 <14 452 opp-hz = /bits/ 64 <1497600000>;
455 opp-peak-kBps = <40680 453 opp-peak-kBps = <4068000 40550400>;
456 }; 454 };
457 455
458 cpu4_opp9: opp-1612800000 { 456 cpu4_opp9: opp-1612800000 {
459 opp-hz = /bits/ 64 <16 457 opp-hz = /bits/ 64 <1612800000>;
460 opp-peak-kBps = <40680 458 opp-peak-kBps = <4068000 40550400>;
461 }; 459 };
462 460
463 cpu4_opp10: opp-1708800000 { 461 cpu4_opp10: opp-1708800000 {
464 opp-hz = /bits/ 64 <17 462 opp-hz = /bits/ 64 <1708800000>;
465 opp-peak-kBps = <40680 463 opp-peak-kBps = <4068000 43008000>;
466 }; 464 };
467 465
468 cpu4_opp11: opp-1804800000 { 466 cpu4_opp11: opp-1804800000 {
469 opp-hz = /bits/ 64 <18 467 opp-hz = /bits/ 64 <1804800000>;
470 opp-peak-kBps = <62200 468 opp-peak-kBps = <6220000 43008000>;
471 }; 469 };
472 470
473 cpu4_opp12: opp-1920000000 { 471 cpu4_opp12: opp-1920000000 {
474 opp-hz = /bits/ 64 <19 472 opp-hz = /bits/ 64 <1920000000>;
475 opp-peak-kBps = <62200 473 opp-peak-kBps = <6220000 49152000>;
476 }; 474 };
477 475
478 cpu4_opp13: opp-2016000000 { 476 cpu4_opp13: opp-2016000000 {
479 opp-hz = /bits/ 64 <20 477 opp-hz = /bits/ 64 <2016000000>;
480 opp-peak-kBps = <72160 478 opp-peak-kBps = <7216000 49152000>;
481 }; 479 };
482 480
483 cpu4_opp14: opp-2131200000 { 481 cpu4_opp14: opp-2131200000 {
484 opp-hz = /bits/ 64 <21 482 opp-hz = /bits/ 64 <2131200000>;
485 opp-peak-kBps = <83680 483 opp-peak-kBps = <8368000 49152000>;
486 }; 484 };
487 485
488 cpu4_opp15: opp-2227200000 { 486 cpu4_opp15: opp-2227200000 {
489 opp-hz = /bits/ 64 <22 487 opp-hz = /bits/ 64 <2227200000>;
490 opp-peak-kBps = <83680 488 opp-peak-kBps = <8368000 51609600>;
491 }; 489 };
492 490
493 cpu4_opp16: opp-2323200000 { 491 cpu4_opp16: opp-2323200000 {
494 opp-hz = /bits/ 64 <23 492 opp-hz = /bits/ 64 <2323200000>;
495 opp-peak-kBps = <83680 493 opp-peak-kBps = <8368000 51609600>;
496 }; 494 };
497 495
498 cpu4_opp17: opp-2419200000 { 496 cpu4_opp17: opp-2419200000 {
499 opp-hz = /bits/ 64 <24 497 opp-hz = /bits/ 64 <2419200000>;
500 opp-peak-kBps = <83680 498 opp-peak-kBps = <8368000 51609600>;
501 }; 499 };
502 }; 500 };
503 501
504 cpu7_opp_table: opp-table-cpu7 { 502 cpu7_opp_table: opp-table-cpu7 {
505 compatible = "operating-points 503 compatible = "operating-points-v2";
506 opp-shared; 504 opp-shared;
507 505
508 cpu7_opp1: opp-825600000 { 506 cpu7_opp1: opp-825600000 {
509 opp-hz = /bits/ 64 <82 507 opp-hz = /bits/ 64 <825600000>;
510 opp-peak-kBps = <21880 508 opp-peak-kBps = <2188000 19660800>;
511 }; 509 };
512 510
513 cpu7_opp2: opp-940800000 { 511 cpu7_opp2: opp-940800000 {
514 opp-hz = /bits/ 64 <94 512 opp-hz = /bits/ 64 <940800000>;
515 opp-peak-kBps = <21880 513 opp-peak-kBps = <2188000 22732800>;
516 }; 514 };
517 515
518 cpu7_opp3: opp-1056000000 { 516 cpu7_opp3: opp-1056000000 {
519 opp-hz = /bits/ 64 <10 517 opp-hz = /bits/ 64 <1056000000>;
520 opp-peak-kBps = <30720 518 opp-peak-kBps = <3072000 25804800>;
521 }; 519 };
522 520
523 cpu7_opp4: opp-1171200000 { 521 cpu7_opp4: opp-1171200000 {
524 opp-hz = /bits/ 64 <11 522 opp-hz = /bits/ 64 <1171200000>;
525 opp-peak-kBps = <30720 523 opp-peak-kBps = <3072000 31948800>;
526 }; 524 };
527 525
528 cpu7_opp5: opp-1286400000 { 526 cpu7_opp5: opp-1286400000 {
529 opp-hz = /bits/ 64 <12 527 opp-hz = /bits/ 64 <1286400000>;
530 opp-peak-kBps = <40680 528 opp-peak-kBps = <4068000 31948800>;
531 }; 529 };
532 530
533 cpu7_opp6: opp-1401600000 { 531 cpu7_opp6: opp-1401600000 {
534 opp-hz = /bits/ 64 <14 532 opp-hz = /bits/ 64 <1401600000>;
535 opp-peak-kBps = <40680 533 opp-peak-kBps = <4068000 31948800>;
536 }; 534 };
537 535
538 cpu7_opp7: opp-1497600000 { 536 cpu7_opp7: opp-1497600000 {
539 opp-hz = /bits/ 64 <14 537 opp-hz = /bits/ 64 <1497600000>;
540 opp-peak-kBps = <40680 538 opp-peak-kBps = <4068000 40550400>;
541 }; 539 };
542 540
543 cpu7_opp8: opp-1612800000 { 541 cpu7_opp8: opp-1612800000 {
544 opp-hz = /bits/ 64 <16 542 opp-hz = /bits/ 64 <1612800000>;
545 opp-peak-kBps = <40680 543 opp-peak-kBps = <4068000 40550400>;
546 }; 544 };
547 545
548 cpu7_opp9: opp-1708800000 { 546 cpu7_opp9: opp-1708800000 {
549 opp-hz = /bits/ 64 <17 547 opp-hz = /bits/ 64 <1708800000>;
550 opp-peak-kBps = <40680 548 opp-peak-kBps = <4068000 43008000>;
551 }; 549 };
552 550
553 cpu7_opp10: opp-1804800000 { 551 cpu7_opp10: opp-1804800000 {
554 opp-hz = /bits/ 64 <18 552 opp-hz = /bits/ 64 <1804800000>;
555 opp-peak-kBps = <62200 553 opp-peak-kBps = <6220000 43008000>;
556 }; 554 };
557 555
558 cpu7_opp11: opp-1920000000 { 556 cpu7_opp11: opp-1920000000 {
559 opp-hz = /bits/ 64 <19 557 opp-hz = /bits/ 64 <1920000000>;
560 opp-peak-kBps = <62200 558 opp-peak-kBps = <6220000 49152000>;
561 }; 559 };
562 560
563 cpu7_opp12: opp-2016000000 { 561 cpu7_opp12: opp-2016000000 {
564 opp-hz = /bits/ 64 <20 562 opp-hz = /bits/ 64 <2016000000>;
565 opp-peak-kBps = <72160 563 opp-peak-kBps = <7216000 49152000>;
566 }; 564 };
567 565
568 cpu7_opp13: opp-2131200000 { 566 cpu7_opp13: opp-2131200000 {
569 opp-hz = /bits/ 64 <21 567 opp-hz = /bits/ 64 <2131200000>;
570 opp-peak-kBps = <83680 568 opp-peak-kBps = <8368000 49152000>;
571 }; 569 };
572 570
573 cpu7_opp14: opp-2227200000 { 571 cpu7_opp14: opp-2227200000 {
574 opp-hz = /bits/ 64 <22 572 opp-hz = /bits/ 64 <2227200000>;
575 opp-peak-kBps = <83680 573 opp-peak-kBps = <8368000 51609600>;
576 }; 574 };
577 575
578 cpu7_opp15: opp-2323200000 { 576 cpu7_opp15: opp-2323200000 {
579 opp-hz = /bits/ 64 <23 577 opp-hz = /bits/ 64 <2323200000>;
580 opp-peak-kBps = <83680 578 opp-peak-kBps = <8368000 51609600>;
581 }; 579 };
582 580
583 cpu7_opp16: opp-2419200000 { 581 cpu7_opp16: opp-2419200000 {
584 opp-hz = /bits/ 64 <24 582 opp-hz = /bits/ 64 <2419200000>;
585 opp-peak-kBps = <83680 583 opp-peak-kBps = <8368000 51609600>;
586 }; 584 };
587 585
588 cpu7_opp17: opp-2534400000 { 586 cpu7_opp17: opp-2534400000 {
589 opp-hz = /bits/ 64 <25 587 opp-hz = /bits/ 64 <2534400000>;
590 opp-peak-kBps = <83680 588 opp-peak-kBps = <8368000 51609600>;
591 }; 589 };
592 590
593 cpu7_opp18: opp-2649600000 { 591 cpu7_opp18: opp-2649600000 {
594 opp-hz = /bits/ 64 <26 592 opp-hz = /bits/ 64 <2649600000>;
595 opp-peak-kBps = <83680 593 opp-peak-kBps = <8368000 51609600>;
596 }; 594 };
597 595
598 cpu7_opp19: opp-2745600000 { 596 cpu7_opp19: opp-2745600000 {
599 opp-hz = /bits/ 64 <27 597 opp-hz = /bits/ 64 <2745600000>;
600 opp-peak-kBps = <83680 598 opp-peak-kBps = <8368000 51609600>;
601 }; 599 };
602 600
603 cpu7_opp20: opp-2841600000 { 601 cpu7_opp20: opp-2841600000 {
604 opp-hz = /bits/ 64 <28 602 opp-hz = /bits/ 64 <2841600000>;
605 opp-peak-kBps = <83680 603 opp-peak-kBps = <8368000 51609600>;
606 }; 604 };
607 }; 605 };
608 606
609 firmware { 607 firmware {
610 scm: scm { 608 scm: scm {
611 compatible = "qcom,scm 609 compatible = "qcom,scm-sm8150", "qcom,scm";
612 #reset-cells = <1>; 610 #reset-cells = <1>;
613 }; 611 };
614 }; 612 };
615 613
616 memory@80000000 { 614 memory@80000000 {
617 device_type = "memory"; 615 device_type = "memory";
618 /* We expect the bootloader to 616 /* We expect the bootloader to fill in the size */
619 reg = <0x0 0x80000000 0x0 0x0> 617 reg = <0x0 0x80000000 0x0 0x0>;
620 }; 618 };
621 619
622 pmu { 620 pmu {
623 compatible = "arm,armv8-pmuv3" 621 compatible = "arm,armv8-pmuv3";
624 interrupts = <GIC_PPI 5 IRQ_TY 622 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
625 }; 623 };
626 624
627 psci { 625 psci {
628 compatible = "arm,psci-1.0"; 626 compatible = "arm,psci-1.0";
629 method = "smc"; 627 method = "smc";
630 628
631 CPU_PD0: power-domain-cpu0 { 629 CPU_PD0: power-domain-cpu0 {
632 #power-domain-cells = 630 #power-domain-cells = <0>;
633 power-domains = <&CLUS 631 power-domains = <&CLUSTER_PD>;
634 domain-idle-states = < 632 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 }; 633 };
636 634
637 CPU_PD1: power-domain-cpu1 { 635 CPU_PD1: power-domain-cpu1 {
638 #power-domain-cells = 636 #power-domain-cells = <0>;
639 power-domains = <&CLUS 637 power-domains = <&CLUSTER_PD>;
640 domain-idle-states = < 638 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
641 }; 639 };
642 640
643 CPU_PD2: power-domain-cpu2 { 641 CPU_PD2: power-domain-cpu2 {
644 #power-domain-cells = 642 #power-domain-cells = <0>;
645 power-domains = <&CLUS 643 power-domains = <&CLUSTER_PD>;
646 domain-idle-states = < 644 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
647 }; 645 };
648 646
649 CPU_PD3: power-domain-cpu3 { 647 CPU_PD3: power-domain-cpu3 {
650 #power-domain-cells = 648 #power-domain-cells = <0>;
651 power-domains = <&CLUS 649 power-domains = <&CLUSTER_PD>;
652 domain-idle-states = < 650 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
653 }; 651 };
654 652
655 CPU_PD4: power-domain-cpu4 { 653 CPU_PD4: power-domain-cpu4 {
656 #power-domain-cells = 654 #power-domain-cells = <0>;
657 power-domains = <&CLUS 655 power-domains = <&CLUSTER_PD>;
658 domain-idle-states = < 656 domain-idle-states = <&BIG_CPU_SLEEP_0>;
659 }; 657 };
660 658
661 CPU_PD5: power-domain-cpu5 { 659 CPU_PD5: power-domain-cpu5 {
662 #power-domain-cells = 660 #power-domain-cells = <0>;
663 power-domains = <&CLUS 661 power-domains = <&CLUSTER_PD>;
664 domain-idle-states = < 662 domain-idle-states = <&BIG_CPU_SLEEP_0>;
665 }; 663 };
666 664
667 CPU_PD6: power-domain-cpu6 { 665 CPU_PD6: power-domain-cpu6 {
668 #power-domain-cells = 666 #power-domain-cells = <0>;
669 power-domains = <&CLUS 667 power-domains = <&CLUSTER_PD>;
670 domain-idle-states = < 668 domain-idle-states = <&BIG_CPU_SLEEP_0>;
671 }; 669 };
672 670
673 CPU_PD7: power-domain-cpu7 { 671 CPU_PD7: power-domain-cpu7 {
674 #power-domain-cells = 672 #power-domain-cells = <0>;
675 power-domains = <&CLUS 673 power-domains = <&CLUSTER_PD>;
676 domain-idle-states = < 674 domain-idle-states = <&BIG_CPU_SLEEP_0>;
677 }; 675 };
678 676
679 CLUSTER_PD: power-domain-cpu-c 677 CLUSTER_PD: power-domain-cpu-cluster0 {
680 #power-domain-cells = 678 #power-domain-cells = <0>;
681 domain-idle-states = < 679 domain-idle-states = <&CLUSTER_SLEEP_0>;
682 }; 680 };
683 }; 681 };
684 682
685 reserved-memory { 683 reserved-memory {
686 #address-cells = <2>; 684 #address-cells = <2>;
687 #size-cells = <2>; 685 #size-cells = <2>;
688 ranges; 686 ranges;
689 687
690 hyp_mem: memory@85700000 { 688 hyp_mem: memory@85700000 {
691 reg = <0x0 0x85700000 689 reg = <0x0 0x85700000 0x0 0x600000>;
692 no-map; 690 no-map;
693 }; 691 };
694 692
695 xbl_mem: memory@85d00000 { 693 xbl_mem: memory@85d00000 {
696 reg = <0x0 0x85d00000 694 reg = <0x0 0x85d00000 0x0 0x140000>;
697 no-map; 695 no-map;
698 }; 696 };
699 697
700 aop_mem: memory@85f00000 { 698 aop_mem: memory@85f00000 {
701 reg = <0x0 0x85f00000 699 reg = <0x0 0x85f00000 0x0 0x20000>;
702 no-map; 700 no-map;
703 }; 701 };
704 702
705 aop_cmd_db: memory@85f20000 { 703 aop_cmd_db: memory@85f20000 {
706 compatible = "qcom,cmd 704 compatible = "qcom,cmd-db";
707 reg = <0x0 0x85f20000 705 reg = <0x0 0x85f20000 0x0 0x20000>;
708 no-map; 706 no-map;
709 }; 707 };
710 708
711 smem_mem: memory@86000000 { 709 smem_mem: memory@86000000 {
712 reg = <0x0 0x86000000 710 reg = <0x0 0x86000000 0x0 0x200000>;
713 no-map; 711 no-map;
714 }; 712 };
715 713
716 tz_mem: memory@86200000 { 714 tz_mem: memory@86200000 {
717 reg = <0x0 0x86200000 715 reg = <0x0 0x86200000 0x0 0x3900000>;
718 no-map; 716 no-map;
719 }; 717 };
720 718
721 rmtfs_mem: memory@89b00000 { 719 rmtfs_mem: memory@89b00000 {
722 compatible = "qcom,rmt 720 compatible = "qcom,rmtfs-mem";
723 reg = <0x0 0x89b00000 721 reg = <0x0 0x89b00000 0x0 0x200000>;
724 no-map; 722 no-map;
725 723
726 qcom,client-id = <1>; 724 qcom,client-id = <1>;
727 qcom,vmid = <QCOM_SCM_ 725 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
728 }; 726 };
729 727
730 camera_mem: memory@8b700000 { 728 camera_mem: memory@8b700000 {
731 reg = <0x0 0x8b700000 729 reg = <0x0 0x8b700000 0x0 0x500000>;
732 no-map; 730 no-map;
733 }; 731 };
734 732
735 wlan_mem: memory@8bc00000 { 733 wlan_mem: memory@8bc00000 {
736 reg = <0x0 0x8bc00000 734 reg = <0x0 0x8bc00000 0x0 0x180000>;
737 no-map; 735 no-map;
738 }; 736 };
739 737
740 npu_mem: memory@8bd80000 { 738 npu_mem: memory@8bd80000 {
741 reg = <0x0 0x8bd80000 739 reg = <0x0 0x8bd80000 0x0 0x80000>;
742 no-map; 740 no-map;
743 }; 741 };
744 742
745 adsp_mem: memory@8be00000 { 743 adsp_mem: memory@8be00000 {
746 reg = <0x0 0x8be00000 744 reg = <0x0 0x8be00000 0x0 0x1a00000>;
747 no-map; 745 no-map;
748 }; 746 };
749 747
750 mpss_mem: memory@8d800000 { 748 mpss_mem: memory@8d800000 {
751 reg = <0x0 0x8d800000 749 reg = <0x0 0x8d800000 0x0 0x9600000>;
752 no-map; 750 no-map;
753 }; 751 };
754 752
755 venus_mem: memory@96e00000 { 753 venus_mem: memory@96e00000 {
756 reg = <0x0 0x96e00000 754 reg = <0x0 0x96e00000 0x0 0x500000>;
757 no-map; 755 no-map;
758 }; 756 };
759 757
760 slpi_mem: memory@97300000 { 758 slpi_mem: memory@97300000 {
761 reg = <0x0 0x97300000 759 reg = <0x0 0x97300000 0x0 0x1400000>;
762 no-map; 760 no-map;
763 }; 761 };
764 762
765 ipa_fw_mem: memory@98700000 { 763 ipa_fw_mem: memory@98700000 {
766 reg = <0x0 0x98700000 764 reg = <0x0 0x98700000 0x0 0x10000>;
767 no-map; 765 no-map;
768 }; 766 };
769 767
770 ipa_gsi_mem: memory@98710000 { 768 ipa_gsi_mem: memory@98710000 {
771 reg = <0x0 0x98710000 769 reg = <0x0 0x98710000 0x0 0x5000>;
772 no-map; 770 no-map;
773 }; 771 };
774 772
775 gpu_mem: memory@98715000 { 773 gpu_mem: memory@98715000 {
776 reg = <0x0 0x98715000 774 reg = <0x0 0x98715000 0x0 0x2000>;
777 no-map; 775 no-map;
778 }; 776 };
779 777
780 spss_mem: memory@98800000 { 778 spss_mem: memory@98800000 {
781 reg = <0x0 0x98800000 779 reg = <0x0 0x98800000 0x0 0x100000>;
782 no-map; 780 no-map;
783 }; 781 };
784 782
785 cdsp_mem: memory@98900000 { 783 cdsp_mem: memory@98900000 {
786 reg = <0x0 0x98900000 784 reg = <0x0 0x98900000 0x0 0x1400000>;
787 no-map; 785 no-map;
788 }; 786 };
789 787
790 qseecom_mem: memory@9e400000 { 788 qseecom_mem: memory@9e400000 {
791 reg = <0x0 0x9e400000 789 reg = <0x0 0x9e400000 0x0 0x1400000>;
792 no-map; 790 no-map;
793 }; 791 };
794 }; 792 };
795 793
796 smem { 794 smem {
797 compatible = "qcom,smem"; 795 compatible = "qcom,smem";
798 memory-region = <&smem_mem>; 796 memory-region = <&smem_mem>;
799 hwlocks = <&tcsr_mutex 3>; 797 hwlocks = <&tcsr_mutex 3>;
800 }; 798 };
801 799
802 smp2p-cdsp { 800 smp2p-cdsp {
803 compatible = "qcom,smp2p"; 801 compatible = "qcom,smp2p";
804 qcom,smem = <94>, <432>; 802 qcom,smem = <94>, <432>;
805 803
806 interrupts = <GIC_SPI 576 IRQ_ 804 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
807 805
808 mboxes = <&apss_shared 6>; 806 mboxes = <&apss_shared 6>;
809 807
810 qcom,local-pid = <0>; 808 qcom,local-pid = <0>;
811 qcom,remote-pid = <5>; 809 qcom,remote-pid = <5>;
812 810
813 cdsp_smp2p_out: master-kernel 811 cdsp_smp2p_out: master-kernel {
814 qcom,entry-name = "mas 812 qcom,entry-name = "master-kernel";
815 #qcom,smem-state-cells 813 #qcom,smem-state-cells = <1>;
816 }; 814 };
817 815
818 cdsp_smp2p_in: slave-kernel { 816 cdsp_smp2p_in: slave-kernel {
819 qcom,entry-name = "sla 817 qcom,entry-name = "slave-kernel";
820 818
821 interrupt-controller; 819 interrupt-controller;
822 #interrupt-cells = <2> 820 #interrupt-cells = <2>;
823 }; 821 };
824 }; 822 };
825 823
826 smp2p-lpass { 824 smp2p-lpass {
827 compatible = "qcom,smp2p"; 825 compatible = "qcom,smp2p";
828 qcom,smem = <443>, <429>; 826 qcom,smem = <443>, <429>;
829 827
830 interrupts = <GIC_SPI 158 IRQ_ 828 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
831 829
832 mboxes = <&apss_shared 10>; 830 mboxes = <&apss_shared 10>;
833 831
834 qcom,local-pid = <0>; 832 qcom,local-pid = <0>;
835 qcom,remote-pid = <2>; 833 qcom,remote-pid = <2>;
836 834
837 adsp_smp2p_out: master-kernel 835 adsp_smp2p_out: master-kernel {
838 qcom,entry-name = "mas 836 qcom,entry-name = "master-kernel";
839 #qcom,smem-state-cells 837 #qcom,smem-state-cells = <1>;
840 }; 838 };
841 839
842 adsp_smp2p_in: slave-kernel { 840 adsp_smp2p_in: slave-kernel {
843 qcom,entry-name = "sla 841 qcom,entry-name = "slave-kernel";
844 842
845 interrupt-controller; 843 interrupt-controller;
846 #interrupt-cells = <2> 844 #interrupt-cells = <2>;
847 }; 845 };
848 }; 846 };
849 847
850 smp2p-mpss { 848 smp2p-mpss {
851 compatible = "qcom,smp2p"; 849 compatible = "qcom,smp2p";
852 qcom,smem = <435>, <428>; 850 qcom,smem = <435>, <428>;
853 851
854 interrupts = <GIC_SPI 451 IRQ_ 852 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
855 853
856 mboxes = <&apss_shared 14>; 854 mboxes = <&apss_shared 14>;
857 855
858 qcom,local-pid = <0>; 856 qcom,local-pid = <0>;
859 qcom,remote-pid = <1>; 857 qcom,remote-pid = <1>;
860 858
861 modem_smp2p_out: master-kernel 859 modem_smp2p_out: master-kernel {
862 qcom,entry-name = "mas 860 qcom,entry-name = "master-kernel";
863 #qcom,smem-state-cells 861 #qcom,smem-state-cells = <1>;
864 }; 862 };
865 863
866 modem_smp2p_in: slave-kernel { 864 modem_smp2p_in: slave-kernel {
867 qcom,entry-name = "sla 865 qcom,entry-name = "slave-kernel";
868 866
869 interrupt-controller; 867 interrupt-controller;
870 #interrupt-cells = <2> 868 #interrupt-cells = <2>;
871 }; 869 };
872 }; 870 };
873 871
874 smp2p-slpi { 872 smp2p-slpi {
875 compatible = "qcom,smp2p"; 873 compatible = "qcom,smp2p";
876 qcom,smem = <481>, <430>; 874 qcom,smem = <481>, <430>;
877 875
878 interrupts = <GIC_SPI 172 IRQ_ 876 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
879 877
880 mboxes = <&apss_shared 26>; 878 mboxes = <&apss_shared 26>;
881 879
882 qcom,local-pid = <0>; 880 qcom,local-pid = <0>;
883 qcom,remote-pid = <3>; 881 qcom,remote-pid = <3>;
884 882
885 slpi_smp2p_out: master-kernel 883 slpi_smp2p_out: master-kernel {
886 qcom,entry-name = "mas 884 qcom,entry-name = "master-kernel";
887 #qcom,smem-state-cells 885 #qcom,smem-state-cells = <1>;
888 }; 886 };
889 887
890 slpi_smp2p_in: slave-kernel { 888 slpi_smp2p_in: slave-kernel {
891 qcom,entry-name = "sla 889 qcom,entry-name = "slave-kernel";
892 890
893 interrupt-controller; 891 interrupt-controller;
894 #interrupt-cells = <2> 892 #interrupt-cells = <2>;
895 }; 893 };
896 }; 894 };
897 895
898 soc: soc@0 { 896 soc: soc@0 {
899 #address-cells = <2>; 897 #address-cells = <2>;
900 #size-cells = <2>; 898 #size-cells = <2>;
901 ranges = <0 0 0 0 0x10 0>; 899 ranges = <0 0 0 0 0x10 0>;
902 dma-ranges = <0 0 0 0 0x10 0>; 900 dma-ranges = <0 0 0 0 0x10 0>;
903 compatible = "simple-bus"; 901 compatible = "simple-bus";
904 902
905 gcc: clock-controller@100000 { 903 gcc: clock-controller@100000 {
906 compatible = "qcom,gcc 904 compatible = "qcom,gcc-sm8150";
907 reg = <0x0 0x00100000 905 reg = <0x0 0x00100000 0x0 0x1f0000>;
908 #clock-cells = <1>; 906 #clock-cells = <1>;
909 #reset-cells = <1>; 907 #reset-cells = <1>;
910 #power-domain-cells = 908 #power-domain-cells = <1>;
911 clock-names = "bi_tcxo 909 clock-names = "bi_tcxo",
912 "sleep_c 910 "sleep_clk";
913 clocks = <&rpmhcc RPMH 911 clocks = <&rpmhcc RPMH_CXO_CLK>,
914 <&sleep_clk>; 912 <&sleep_clk>;
915 }; 913 };
916 914
917 gpi_dma0: dma-controller@80000 915 gpi_dma0: dma-controller@800000 {
918 compatible = "qcom,sm8 916 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
919 reg = <0 0x00800000 0 917 reg = <0 0x00800000 0 0x60000>;
920 interrupts = <GIC_SPI 918 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 919 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 920 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 921 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 922 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 923 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 924 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 925 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 926 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 927 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 928 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 929 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 930 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
933 dma-channels = <13>; 931 dma-channels = <13>;
934 dma-channel-mask = <0x 932 dma-channel-mask = <0xfa>;
935 iommus = <&apps_smmu 0 933 iommus = <&apps_smmu 0x00d6 0x0>;
936 #dma-cells = <3>; 934 #dma-cells = <3>;
937 status = "disabled"; 935 status = "disabled";
938 }; 936 };
939 937
940 ethernet: ethernet@20000 { 938 ethernet: ethernet@20000 {
941 compatible = "qcom,sm8 939 compatible = "qcom,sm8150-ethqos";
942 reg = <0x0 0x00020000 940 reg = <0x0 0x00020000 0x0 0x10000>,
943 <0x0 0x00036000 941 <0x0 0x00036000 0x0 0x100>;
944 reg-names = "stmmaceth 942 reg-names = "stmmaceth", "rgmii";
945 clock-names = "stmmace 943 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
946 clocks = <&gcc GCC_EMA 944 clocks = <&gcc GCC_EMAC_AXI_CLK>,
947 <&gcc GCC_EMAC 945 <&gcc GCC_EMAC_SLV_AHB_CLK>,
948 <&gcc GCC_EMAC 946 <&gcc GCC_EMAC_PTP_CLK>,
949 <&gcc GCC_EMAC 947 <&gcc GCC_EMAC_RGMII_CLK>;
950 interrupts = <GIC_SPI 948 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 949 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "mac 950 interrupt-names = "macirq", "eth_lpi";
953 951
954 power-domains = <&gcc 952 power-domains = <&gcc EMAC_GDSC>;
955 resets = <&gcc GCC_EMA 953 resets = <&gcc GCC_EMAC_BCR>;
956 954
957 iommus = <&apps_smmu 0 955 iommus = <&apps_smmu 0x3c0 0x0>;
958 956
959 snps,tso; 957 snps,tso;
960 rx-fifo-depth = <4096> 958 rx-fifo-depth = <4096>;
961 tx-fifo-depth = <4096> 959 tx-fifo-depth = <4096>;
962 960
963 status = "disabled"; 961 status = "disabled";
964 }; 962 };
965 963
966 qfprom: efuse@784000 { 964 qfprom: efuse@784000 {
967 compatible = "qcom,sm8 965 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
968 reg = <0 0x00784000 0 966 reg = <0 0x00784000 0 0x8ff>;
969 #address-cells = <1>; 967 #address-cells = <1>;
970 #size-cells = <1>; 968 #size-cells = <1>;
971 969
972 gpu_speed_bin: gpu-spe !! 970 gpu_speed_bin: gpu_speed_bin@133 {
973 reg = <0x133 0 971 reg = <0x133 0x1>;
974 bits = <5 3>; 972 bits = <5 3>;
975 }; 973 };
976 }; 974 };
977 975
978 qupv3_id_0: geniqup@8c0000 { 976 qupv3_id_0: geniqup@8c0000 {
979 compatible = "qcom,gen 977 compatible = "qcom,geni-se-qup";
980 reg = <0x0 0x008c0000 978 reg = <0x0 0x008c0000 0x0 0x6000>;
981 clock-names = "m-ahb", 979 clock-names = "m-ahb", "s-ahb";
982 clocks = <&gcc GCC_QUP 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
983 <&gcc GCC_QUP 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
984 iommus = <&apps_smmu 0 982 iommus = <&apps_smmu 0xc3 0x0>;
985 #address-cells = <2>; 983 #address-cells = <2>;
986 #size-cells = <2>; 984 #size-cells = <2>;
987 ranges; 985 ranges;
988 status = "disabled"; 986 status = "disabled";
989 987
990 i2c0: i2c@880000 { 988 i2c0: i2c@880000 {
991 compatible = " 989 compatible = "qcom,geni-i2c";
992 reg = <0 0x008 990 reg = <0 0x00880000 0 0x4000>;
993 clock-names = 991 clock-names = "se";
994 clocks = <&gcc 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
995 dmas = <&gpi_d 993 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
996 <&gpi_d 994 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
997 dma-names = "t 995 dma-names = "tx", "rx";
998 pinctrl-names 996 pinctrl-names = "default";
999 pinctrl-0 = <& 997 pinctrl-0 = <&qup_i2c0_default>;
1000 interrupts = 998 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cell 999 #address-cells = <1>;
1002 #size-cells = 1000 #size-cells = <0>;
1003 status = "dis 1001 status = "disabled";
1004 }; 1002 };
1005 1003
1006 spi0: spi@880000 { 1004 spi0: spi@880000 {
1007 compatible = 1005 compatible = "qcom,geni-spi";
1008 reg = <0 0x00 1006 reg = <0 0x00880000 0 0x4000>;
1009 reg-names = " 1007 reg-names = "se";
1010 clock-names = 1008 clock-names = "se";
1011 clocks = <&gc 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1012 dmas = <&gpi_ 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1013 <&gpi_ 1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1014 dma-names = " 1012 dma-names = "tx", "rx";
1015 pinctrl-names 1013 pinctrl-names = "default";
1016 pinctrl-0 = < 1014 pinctrl-0 = <&qup_spi0_default>;
1017 interrupts = 1015 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1018 spi-max-frequ 1016 spi-max-frequency = <50000000>;
1019 #address-cell 1017 #address-cells = <1>;
1020 #size-cells = 1018 #size-cells = <0>;
1021 status = "dis 1019 status = "disabled";
1022 }; 1020 };
1023 1021
1024 i2c1: i2c@884000 { 1022 i2c1: i2c@884000 {
1025 compatible = 1023 compatible = "qcom,geni-i2c";
1026 reg = <0 0x00 1024 reg = <0 0x00884000 0 0x4000>;
1027 clock-names = 1025 clock-names = "se";
1028 clocks = <&gc 1026 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1029 dmas = <&gpi_ 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_ 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = " 1029 dma-names = "tx", "rx";
1032 pinctrl-names 1030 pinctrl-names = "default";
1033 pinctrl-0 = < 1031 pinctrl-0 = <&qup_i2c1_default>;
1034 interrupts = 1032 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1035 #address-cell 1033 #address-cells = <1>;
1036 #size-cells = 1034 #size-cells = <0>;
1037 status = "dis 1035 status = "disabled";
1038 }; 1036 };
1039 1037
1040 spi1: spi@884000 { 1038 spi1: spi@884000 {
1041 compatible = 1039 compatible = "qcom,geni-spi";
1042 reg = <0 0x00 1040 reg = <0 0x00884000 0 0x4000>;
1043 reg-names = " 1041 reg-names = "se";
1044 clock-names = 1042 clock-names = "se";
1045 clocks = <&gc 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1046 dmas = <&gpi_ 1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1047 <&gpi_ 1045 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1048 dma-names = " 1046 dma-names = "tx", "rx";
1049 pinctrl-names 1047 pinctrl-names = "default";
1050 pinctrl-0 = < 1048 pinctrl-0 = <&qup_spi1_default>;
1051 interrupts = 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1052 spi-max-frequ 1050 spi-max-frequency = <50000000>;
1053 #address-cell 1051 #address-cells = <1>;
1054 #size-cells = 1052 #size-cells = <0>;
1055 status = "dis 1053 status = "disabled";
1056 }; 1054 };
1057 1055
1058 i2c2: i2c@888000 { 1056 i2c2: i2c@888000 {
1059 compatible = 1057 compatible = "qcom,geni-i2c";
1060 reg = <0 0x00 1058 reg = <0 0x00888000 0 0x4000>;
1061 clock-names = 1059 clock-names = "se";
1062 clocks = <&gc 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1063 dmas = <&gpi_ 1061 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1064 <&gpi_ 1062 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1065 dma-names = " 1063 dma-names = "tx", "rx";
1066 pinctrl-names 1064 pinctrl-names = "default";
1067 pinctrl-0 = < 1065 pinctrl-0 = <&qup_i2c2_default>;
1068 interrupts = 1066 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cell 1067 #address-cells = <1>;
1070 #size-cells = 1068 #size-cells = <0>;
1071 status = "dis 1069 status = "disabled";
1072 }; 1070 };
1073 1071
1074 spi2: spi@888000 { 1072 spi2: spi@888000 {
1075 compatible = 1073 compatible = "qcom,geni-spi";
1076 reg = <0 0x00 1074 reg = <0 0x00888000 0 0x4000>;
1077 reg-names = " 1075 reg-names = "se";
1078 clock-names = 1076 clock-names = "se";
1079 clocks = <&gc 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1080 dmas = <&gpi_ 1078 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1081 <&gpi_ 1079 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1082 dma-names = " 1080 dma-names = "tx", "rx";
1083 pinctrl-names 1081 pinctrl-names = "default";
1084 pinctrl-0 = < 1082 pinctrl-0 = <&qup_spi2_default>;
1085 interrupts = 1083 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1086 spi-max-frequ 1084 spi-max-frequency = <50000000>;
1087 #address-cell 1085 #address-cells = <1>;
1088 #size-cells = 1086 #size-cells = <0>;
1089 status = "dis 1087 status = "disabled";
1090 }; 1088 };
1091 1089
1092 i2c3: i2c@88c000 { 1090 i2c3: i2c@88c000 {
1093 compatible = 1091 compatible = "qcom,geni-i2c";
1094 reg = <0 0x00 1092 reg = <0 0x0088c000 0 0x4000>;
1095 clock-names = 1093 clock-names = "se";
1096 clocks = <&gc 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1097 dmas = <&gpi_ 1095 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1098 <&gpi_ 1096 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1099 dma-names = " 1097 dma-names = "tx", "rx";
1100 pinctrl-names 1098 pinctrl-names = "default";
1101 pinctrl-0 = < 1099 pinctrl-0 = <&qup_i2c3_default>;
1102 interrupts = 1100 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1103 #address-cell 1101 #address-cells = <1>;
1104 #size-cells = 1102 #size-cells = <0>;
1105 status = "dis 1103 status = "disabled";
1106 }; 1104 };
1107 1105
1108 spi3: spi@88c000 { 1106 spi3: spi@88c000 {
1109 compatible = 1107 compatible = "qcom,geni-spi";
1110 reg = <0 0x00 1108 reg = <0 0x0088c000 0 0x4000>;
1111 reg-names = " 1109 reg-names = "se";
1112 clock-names = 1110 clock-names = "se";
1113 clocks = <&gc 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1114 dmas = <&gpi_ 1112 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1115 <&gpi_ 1113 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1116 dma-names = " 1114 dma-names = "tx", "rx";
1117 pinctrl-names 1115 pinctrl-names = "default";
1118 pinctrl-0 = < 1116 pinctrl-0 = <&qup_spi3_default>;
1119 interrupts = 1117 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1120 spi-max-frequ 1118 spi-max-frequency = <50000000>;
1121 #address-cell 1119 #address-cells = <1>;
1122 #size-cells = 1120 #size-cells = <0>;
1123 status = "dis 1121 status = "disabled";
1124 }; 1122 };
1125 1123
1126 i2c4: i2c@890000 { 1124 i2c4: i2c@890000 {
1127 compatible = 1125 compatible = "qcom,geni-i2c";
1128 reg = <0 0x00 1126 reg = <0 0x00890000 0 0x4000>;
1129 clock-names = 1127 clock-names = "se";
1130 clocks = <&gc 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1131 dmas = <&gpi_ 1129 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1132 <&gpi_ 1130 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1133 dma-names = " 1131 dma-names = "tx", "rx";
1134 pinctrl-names 1132 pinctrl-names = "default";
1135 pinctrl-0 = < 1133 pinctrl-0 = <&qup_i2c4_default>;
1136 interrupts = 1134 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1137 #address-cell 1135 #address-cells = <1>;
1138 #size-cells = 1136 #size-cells = <0>;
1139 status = "dis 1137 status = "disabled";
1140 }; 1138 };
1141 1139
1142 spi4: spi@890000 { 1140 spi4: spi@890000 {
1143 compatible = 1141 compatible = "qcom,geni-spi";
1144 reg = <0 0x00 1142 reg = <0 0x00890000 0 0x4000>;
1145 reg-names = " 1143 reg-names = "se";
1146 clock-names = 1144 clock-names = "se";
1147 clocks = <&gc 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1148 dmas = <&gpi_ 1146 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1149 <&gpi_ 1147 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1150 dma-names = " 1148 dma-names = "tx", "rx";
1151 pinctrl-names 1149 pinctrl-names = "default";
1152 pinctrl-0 = < 1150 pinctrl-0 = <&qup_spi4_default>;
1153 interrupts = 1151 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1154 spi-max-frequ 1152 spi-max-frequency = <50000000>;
1155 #address-cell 1153 #address-cells = <1>;
1156 #size-cells = 1154 #size-cells = <0>;
1157 status = "dis 1155 status = "disabled";
1158 }; 1156 };
1159 1157
1160 i2c5: i2c@894000 { 1158 i2c5: i2c@894000 {
1161 compatible = 1159 compatible = "qcom,geni-i2c";
1162 reg = <0 0x00 1160 reg = <0 0x00894000 0 0x4000>;
1163 clock-names = 1161 clock-names = "se";
1164 clocks = <&gc 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1165 dmas = <&gpi_ 1163 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1166 <&gpi_ 1164 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1167 dma-names = " 1165 dma-names = "tx", "rx";
1168 pinctrl-names 1166 pinctrl-names = "default";
1169 pinctrl-0 = < 1167 pinctrl-0 = <&qup_i2c5_default>;
1170 interrupts = 1168 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1171 #address-cell 1169 #address-cells = <1>;
1172 #size-cells = 1170 #size-cells = <0>;
1173 status = "dis 1171 status = "disabled";
1174 }; 1172 };
1175 1173
1176 spi5: spi@894000 { 1174 spi5: spi@894000 {
1177 compatible = 1175 compatible = "qcom,geni-spi";
1178 reg = <0 0x00 1176 reg = <0 0x00894000 0 0x4000>;
1179 reg-names = " 1177 reg-names = "se";
1180 clock-names = 1178 clock-names = "se";
1181 clocks = <&gc 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1182 dmas = <&gpi_ 1180 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1183 <&gpi_ 1181 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1184 dma-names = " 1182 dma-names = "tx", "rx";
1185 pinctrl-names 1183 pinctrl-names = "default";
1186 pinctrl-0 = < 1184 pinctrl-0 = <&qup_spi5_default>;
1187 interrupts = 1185 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1188 spi-max-frequ 1186 spi-max-frequency = <50000000>;
1189 #address-cell 1187 #address-cells = <1>;
1190 #size-cells = 1188 #size-cells = <0>;
1191 status = "dis 1189 status = "disabled";
1192 }; 1190 };
1193 1191
1194 i2c6: i2c@898000 { 1192 i2c6: i2c@898000 {
1195 compatible = 1193 compatible = "qcom,geni-i2c";
1196 reg = <0 0x00 1194 reg = <0 0x00898000 0 0x4000>;
1197 clock-names = 1195 clock-names = "se";
1198 clocks = <&gc 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1199 dmas = <&gpi_ 1197 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1200 <&gpi_ 1198 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1201 dma-names = " 1199 dma-names = "tx", "rx";
1202 pinctrl-names 1200 pinctrl-names = "default";
1203 pinctrl-0 = < 1201 pinctrl-0 = <&qup_i2c6_default>;
1204 interrupts = 1202 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1205 #address-cell 1203 #address-cells = <1>;
1206 #size-cells = 1204 #size-cells = <0>;
1207 status = "dis 1205 status = "disabled";
1208 }; 1206 };
1209 1207
1210 spi6: spi@898000 { 1208 spi6: spi@898000 {
1211 compatible = 1209 compatible = "qcom,geni-spi";
1212 reg = <0 0x00 1210 reg = <0 0x00898000 0 0x4000>;
1213 reg-names = " 1211 reg-names = "se";
1214 clock-names = 1212 clock-names = "se";
1215 clocks = <&gc 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1216 dmas = <&gpi_ 1214 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1217 <&gpi_ 1215 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1218 dma-names = " 1216 dma-names = "tx", "rx";
1219 pinctrl-names 1217 pinctrl-names = "default";
1220 pinctrl-0 = < 1218 pinctrl-0 = <&qup_spi6_default>;
1221 interrupts = 1219 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1222 spi-max-frequ 1220 spi-max-frequency = <50000000>;
1223 #address-cell 1221 #address-cells = <1>;
1224 #size-cells = 1222 #size-cells = <0>;
1225 status = "dis 1223 status = "disabled";
1226 }; 1224 };
1227 1225
1228 i2c7: i2c@89c000 { 1226 i2c7: i2c@89c000 {
1229 compatible = 1227 compatible = "qcom,geni-i2c";
1230 reg = <0 0x00 1228 reg = <0 0x0089c000 0 0x4000>;
1231 clock-names = 1229 clock-names = "se";
1232 clocks = <&gc 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1233 dmas = <&gpi_ 1231 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1234 <&gpi_ 1232 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1235 dma-names = " 1233 dma-names = "tx", "rx";
1236 pinctrl-names 1234 pinctrl-names = "default";
1237 pinctrl-0 = < 1235 pinctrl-0 = <&qup_i2c7_default>;
1238 interrupts = 1236 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1239 #address-cell 1237 #address-cells = <1>;
1240 #size-cells = 1238 #size-cells = <0>;
1241 status = "dis 1239 status = "disabled";
1242 }; 1240 };
1243 1241
1244 spi7: spi@89c000 { 1242 spi7: spi@89c000 {
1245 compatible = 1243 compatible = "qcom,geni-spi";
1246 reg = <0 0x00 1244 reg = <0 0x0089c000 0 0x4000>;
1247 reg-names = " 1245 reg-names = "se";
1248 clock-names = 1246 clock-names = "se";
1249 clocks = <&gc 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1250 dmas = <&gpi_ 1248 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1251 <&gpi_ 1249 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1252 dma-names = " 1250 dma-names = "tx", "rx";
1253 pinctrl-names 1251 pinctrl-names = "default";
1254 pinctrl-0 = < 1252 pinctrl-0 = <&qup_spi7_default>;
1255 interrupts = 1253 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1256 spi-max-frequ 1254 spi-max-frequency = <50000000>;
1257 #address-cell 1255 #address-cells = <1>;
1258 #size-cells = 1256 #size-cells = <0>;
1259 status = "dis 1257 status = "disabled";
1260 }; 1258 };
1261 }; 1259 };
1262 1260
1263 gpi_dma1: dma-controller@a000 1261 gpi_dma1: dma-controller@a00000 {
1264 compatible = "qcom,sm 1262 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1265 reg = <0 0x00a00000 0 1263 reg = <0 0x00a00000 0 0x60000>;
1266 interrupts = <GIC_SPI 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 1276 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1279 dma-channels = <13>; 1277 dma-channels = <13>;
1280 dma-channel-mask = <0 1278 dma-channel-mask = <0xfa>;
1281 iommus = <&apps_smmu 1279 iommus = <&apps_smmu 0x0616 0x0>;
1282 #dma-cells = <3>; 1280 #dma-cells = <3>;
1283 status = "disabled"; 1281 status = "disabled";
1284 }; 1282 };
1285 1283
1286 qupv3_id_1: geniqup@ac0000 { 1284 qupv3_id_1: geniqup@ac0000 {
1287 compatible = "qcom,ge 1285 compatible = "qcom,geni-se-qup";
1288 reg = <0x0 0x00ac0000 1286 reg = <0x0 0x00ac0000 0x0 0x6000>;
1289 clock-names = "m-ahb" 1287 clock-names = "m-ahb", "s-ahb";
1290 clocks = <&gcc GCC_QU 1288 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1291 <&gcc GCC_QU 1289 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1292 iommus = <&apps_smmu 1290 iommus = <&apps_smmu 0x603 0x0>;
1293 #address-cells = <2>; 1291 #address-cells = <2>;
1294 #size-cells = <2>; 1292 #size-cells = <2>;
1295 ranges; 1293 ranges;
1296 status = "disabled"; 1294 status = "disabled";
1297 1295
1298 i2c8: i2c@a80000 { 1296 i2c8: i2c@a80000 {
1299 compatible = 1297 compatible = "qcom,geni-i2c";
1300 reg = <0 0x00 1298 reg = <0 0x00a80000 0 0x4000>;
1301 clock-names = 1299 clock-names = "se";
1302 clocks = <&gc 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1303 dmas = <&gpi_ 1301 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1304 <&gpi_ 1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1305 dma-names = " 1303 dma-names = "tx", "rx";
1306 pinctrl-names 1304 pinctrl-names = "default";
1307 pinctrl-0 = < 1305 pinctrl-0 = <&qup_i2c8_default>;
1308 interrupts = 1306 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1309 #address-cell 1307 #address-cells = <1>;
1310 #size-cells = 1308 #size-cells = <0>;
1311 status = "dis 1309 status = "disabled";
1312 }; 1310 };
1313 1311
1314 spi8: spi@a80000 { 1312 spi8: spi@a80000 {
1315 compatible = 1313 compatible = "qcom,geni-spi";
1316 reg = <0 0x00 1314 reg = <0 0x00a80000 0 0x4000>;
1317 reg-names = " 1315 reg-names = "se";
1318 clock-names = 1316 clock-names = "se";
1319 clocks = <&gc 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1320 dmas = <&gpi_ 1318 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1321 <&gpi_ 1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1322 dma-names = " 1320 dma-names = "tx", "rx";
1323 pinctrl-names 1321 pinctrl-names = "default";
1324 pinctrl-0 = < 1322 pinctrl-0 = <&qup_spi8_default>;
1325 interrupts = 1323 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1326 spi-max-frequ 1324 spi-max-frequency = <50000000>;
1327 #address-cell 1325 #address-cells = <1>;
1328 #size-cells = 1326 #size-cells = <0>;
1329 status = "dis 1327 status = "disabled";
1330 }; 1328 };
1331 1329
1332 i2c9: i2c@a84000 { 1330 i2c9: i2c@a84000 {
1333 compatible = 1331 compatible = "qcom,geni-i2c";
1334 reg = <0 0x00 1332 reg = <0 0x00a84000 0 0x4000>;
1335 clock-names = 1333 clock-names = "se";
1336 clocks = <&gc 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1337 dmas = <&gpi_ 1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1338 <&gpi_ 1336 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1339 dma-names = " 1337 dma-names = "tx", "rx";
1340 pinctrl-names 1338 pinctrl-names = "default";
1341 pinctrl-0 = < 1339 pinctrl-0 = <&qup_i2c9_default>;
1342 interrupts = 1340 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1343 #address-cell 1341 #address-cells = <1>;
1344 #size-cells = 1342 #size-cells = <0>;
1345 status = "dis 1343 status = "disabled";
1346 }; 1344 };
1347 1345
1348 spi9: spi@a84000 { 1346 spi9: spi@a84000 {
1349 compatible = 1347 compatible = "qcom,geni-spi";
1350 reg = <0 0x00 1348 reg = <0 0x00a84000 0 0x4000>;
1351 reg-names = " 1349 reg-names = "se";
1352 clock-names = 1350 clock-names = "se";
1353 clocks = <&gc 1351 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1354 dmas = <&gpi_ 1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1355 <&gpi_ 1353 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1356 dma-names = " 1354 dma-names = "tx", "rx";
1357 pinctrl-names 1355 pinctrl-names = "default";
1358 pinctrl-0 = < 1356 pinctrl-0 = <&qup_spi9_default>;
1359 interrupts = 1357 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1360 spi-max-frequ 1358 spi-max-frequency = <50000000>;
1361 #address-cell 1359 #address-cells = <1>;
1362 #size-cells = 1360 #size-cells = <0>;
1363 status = "dis 1361 status = "disabled";
1364 }; 1362 };
1365 1363
1366 uart9: serial@a84000 1364 uart9: serial@a84000 {
1367 compatible = 1365 compatible = "qcom,geni-uart";
1368 reg = <0x0 0x 1366 reg = <0x0 0x00a84000 0x0 0x4000>;
1369 clocks = <&gc 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1370 clock-names = 1368 clock-names = "se";
1371 pinctrl-0 = < 1369 pinctrl-0 = <&qup_uart9_default>;
1372 pinctrl-names 1370 pinctrl-names = "default";
1373 interrupts = 1371 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1374 status = "dis 1372 status = "disabled";
1375 }; 1373 };
1376 1374
1377 i2c10: i2c@a88000 { 1375 i2c10: i2c@a88000 {
1378 compatible = 1376 compatible = "qcom,geni-i2c";
1379 reg = <0 0x00 1377 reg = <0 0x00a88000 0 0x4000>;
1380 clock-names = 1378 clock-names = "se";
1381 clocks = <&gc 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1382 dmas = <&gpi_ 1380 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1383 <&gpi_ 1381 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1384 dma-names = " 1382 dma-names = "tx", "rx";
1385 pinctrl-names 1383 pinctrl-names = "default";
1386 pinctrl-0 = < 1384 pinctrl-0 = <&qup_i2c10_default>;
1387 interrupts = 1385 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1388 #address-cell 1386 #address-cells = <1>;
1389 #size-cells = 1387 #size-cells = <0>;
1390 status = "dis 1388 status = "disabled";
1391 }; 1389 };
1392 1390
1393 spi10: spi@a88000 { 1391 spi10: spi@a88000 {
1394 compatible = 1392 compatible = "qcom,geni-spi";
1395 reg = <0 0x00 1393 reg = <0 0x00a88000 0 0x4000>;
1396 reg-names = " 1394 reg-names = "se";
1397 clock-names = 1395 clock-names = "se";
1398 clocks = <&gc 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1399 dmas = <&gpi_ 1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1400 <&gpi_ 1398 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1401 dma-names = " 1399 dma-names = "tx", "rx";
1402 pinctrl-names 1400 pinctrl-names = "default";
1403 pinctrl-0 = < 1401 pinctrl-0 = <&qup_spi10_default>;
1404 interrupts = 1402 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1405 spi-max-frequ 1403 spi-max-frequency = <50000000>;
1406 #address-cell 1404 #address-cells = <1>;
1407 #size-cells = 1405 #size-cells = <0>;
1408 status = "dis 1406 status = "disabled";
1409 }; 1407 };
1410 1408
1411 i2c11: i2c@a8c000 { 1409 i2c11: i2c@a8c000 {
1412 compatible = 1410 compatible = "qcom,geni-i2c";
1413 reg = <0 0x00 1411 reg = <0 0x00a8c000 0 0x4000>;
1414 clock-names = 1412 clock-names = "se";
1415 clocks = <&gc 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1416 dmas = <&gpi_ 1414 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1417 <&gpi_ 1415 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1418 dma-names = " 1416 dma-names = "tx", "rx";
1419 pinctrl-names 1417 pinctrl-names = "default";
1420 pinctrl-0 = < 1418 pinctrl-0 = <&qup_i2c11_default>;
1421 interrupts = 1419 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1422 #address-cell 1420 #address-cells = <1>;
1423 #size-cells = 1421 #size-cells = <0>;
1424 status = "dis 1422 status = "disabled";
1425 }; 1423 };
1426 1424
1427 spi11: spi@a8c000 { 1425 spi11: spi@a8c000 {
1428 compatible = 1426 compatible = "qcom,geni-spi";
1429 reg = <0 0x00 1427 reg = <0 0x00a8c000 0 0x4000>;
1430 reg-names = " 1428 reg-names = "se";
1431 clock-names = 1429 clock-names = "se";
1432 clocks = <&gc 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1433 dmas = <&gpi_ 1431 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1434 <&gpi_ 1432 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1435 dma-names = " 1433 dma-names = "tx", "rx";
1436 pinctrl-names 1434 pinctrl-names = "default";
1437 pinctrl-0 = < 1435 pinctrl-0 = <&qup_spi11_default>;
1438 interrupts = 1436 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1439 spi-max-frequ 1437 spi-max-frequency = <50000000>;
1440 #address-cell 1438 #address-cells = <1>;
1441 #size-cells = 1439 #size-cells = <0>;
1442 status = "dis 1440 status = "disabled";
1443 }; 1441 };
1444 1442
1445 uart2: serial@a90000 1443 uart2: serial@a90000 {
1446 compatible = 1444 compatible = "qcom,geni-debug-uart";
1447 reg = <0x0 0x 1445 reg = <0x0 0x00a90000 0x0 0x4000>;
1448 clock-names = 1446 clock-names = "se";
1449 clocks = <&gc 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1450 interrupts = 1448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1451 status = "dis 1449 status = "disabled";
1452 }; 1450 };
1453 1451
1454 i2c12: i2c@a90000 { 1452 i2c12: i2c@a90000 {
1455 compatible = 1453 compatible = "qcom,geni-i2c";
1456 reg = <0 0x00 1454 reg = <0 0x00a90000 0 0x4000>;
1457 clock-names = 1455 clock-names = "se";
1458 clocks = <&gc 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1459 dmas = <&gpi_ 1457 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1460 <&gpi_ 1458 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1461 dma-names = " 1459 dma-names = "tx", "rx";
1462 pinctrl-names 1460 pinctrl-names = "default";
1463 pinctrl-0 = < 1461 pinctrl-0 = <&qup_i2c12_default>;
1464 interrupts = 1462 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1465 #address-cell 1463 #address-cells = <1>;
1466 #size-cells = 1464 #size-cells = <0>;
1467 status = "dis 1465 status = "disabled";
1468 }; 1466 };
1469 1467
1470 spi12: spi@a90000 { 1468 spi12: spi@a90000 {
1471 compatible = 1469 compatible = "qcom,geni-spi";
1472 reg = <0 0x00 1470 reg = <0 0x00a90000 0 0x4000>;
1473 reg-names = " 1471 reg-names = "se";
1474 clock-names = 1472 clock-names = "se";
1475 clocks = <&gc 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1476 dmas = <&gpi_ 1474 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1477 <&gpi_ 1475 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1478 dma-names = " 1476 dma-names = "tx", "rx";
1479 pinctrl-names 1477 pinctrl-names = "default";
1480 pinctrl-0 = < 1478 pinctrl-0 = <&qup_spi12_default>;
1481 interrupts = 1479 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1482 spi-max-frequ 1480 spi-max-frequency = <50000000>;
1483 #address-cell 1481 #address-cells = <1>;
1484 #size-cells = 1482 #size-cells = <0>;
1485 status = "dis 1483 status = "disabled";
1486 }; 1484 };
1487 1485
1488 i2c16: i2c@94000 { 1486 i2c16: i2c@94000 {
1489 compatible = 1487 compatible = "qcom,geni-i2c";
1490 reg = <0 0x00 1488 reg = <0 0x00094000 0 0x4000>;
1491 clock-names = 1489 clock-names = "se";
1492 clocks = <&gc 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1493 dmas = <&gpi_ 1491 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1494 <&gpi_ 1492 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1495 dma-names = " 1493 dma-names = "tx", "rx";
1496 pinctrl-names 1494 pinctrl-names = "default";
1497 pinctrl-0 = < 1495 pinctrl-0 = <&qup_i2c16_default>;
1498 interrupts = 1496 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1499 #address-cell 1497 #address-cells = <1>;
1500 #size-cells = 1498 #size-cells = <0>;
1501 status = "dis 1499 status = "disabled";
1502 }; 1500 };
1503 1501
1504 spi16: spi@a94000 { 1502 spi16: spi@a94000 {
1505 compatible = 1503 compatible = "qcom,geni-spi";
1506 reg = <0 0x00 1504 reg = <0 0x00a94000 0 0x4000>;
1507 reg-names = " 1505 reg-names = "se";
1508 clock-names = 1506 clock-names = "se";
1509 clocks = <&gc 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1510 dmas = <&gpi_ 1508 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1511 <&gpi_ 1509 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1512 dma-names = " 1510 dma-names = "tx", "rx";
1513 pinctrl-names 1511 pinctrl-names = "default";
1514 pinctrl-0 = < 1512 pinctrl-0 = <&qup_spi16_default>;
1515 interrupts = 1513 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1516 spi-max-frequ 1514 spi-max-frequency = <50000000>;
1517 #address-cell 1515 #address-cells = <1>;
1518 #size-cells = 1516 #size-cells = <0>;
1519 status = "dis 1517 status = "disabled";
1520 }; 1518 };
1521 }; 1519 };
1522 1520
1523 gpi_dma2: dma-controller@c000 1521 gpi_dma2: dma-controller@c00000 {
1524 compatible = "qcom,sm 1522 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1525 reg = <0 0x00c00000 0 1523 reg = <0 0x00c00000 0 0x60000>;
1526 interrupts = <GIC_SPI 1524 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 1525 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 1526 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 1527 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 1528 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 1529 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 1530 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 1531 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 1532 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 1533 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 1534 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 1535 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 1536 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1539 dma-channels = <13>; 1537 dma-channels = <13>;
1540 dma-channel-mask = <0 1538 dma-channel-mask = <0xfa>;
1541 iommus = <&apps_smmu 1539 iommus = <&apps_smmu 0x07b6 0x0>;
1542 #dma-cells = <3>; 1540 #dma-cells = <3>;
1543 status = "disabled"; 1541 status = "disabled";
1544 }; 1542 };
1545 1543
1546 qupv3_id_2: geniqup@cc0000 { 1544 qupv3_id_2: geniqup@cc0000 {
1547 compatible = "qcom,ge 1545 compatible = "qcom,geni-se-qup";
1548 reg = <0x0 0x00cc0000 1546 reg = <0x0 0x00cc0000 0x0 0x6000>;
1549 1547
1550 clock-names = "m-ahb" 1548 clock-names = "m-ahb", "s-ahb";
1551 clocks = <&gcc GCC_QU 1549 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1552 <&gcc GCC_QU 1550 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1553 iommus = <&apps_smmu 1551 iommus = <&apps_smmu 0x7a3 0x0>;
1554 #address-cells = <2>; 1552 #address-cells = <2>;
1555 #size-cells = <2>; 1553 #size-cells = <2>;
1556 ranges; 1554 ranges;
1557 status = "disabled"; 1555 status = "disabled";
1558 1556
1559 i2c17: i2c@c80000 { 1557 i2c17: i2c@c80000 {
1560 compatible = 1558 compatible = "qcom,geni-i2c";
1561 reg = <0 0x00 1559 reg = <0 0x00c80000 0 0x4000>;
1562 clock-names = 1560 clock-names = "se";
1563 clocks = <&gc 1561 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1564 dmas = <&gpi_ 1562 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1565 <&gpi_ 1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1566 dma-names = " 1564 dma-names = "tx", "rx";
1567 pinctrl-names 1565 pinctrl-names = "default";
1568 pinctrl-0 = < 1566 pinctrl-0 = <&qup_i2c17_default>;
1569 interrupts = 1567 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1570 #address-cell 1568 #address-cells = <1>;
1571 #size-cells = 1569 #size-cells = <0>;
1572 status = "dis 1570 status = "disabled";
1573 }; 1571 };
1574 1572
1575 spi17: spi@c80000 { 1573 spi17: spi@c80000 {
1576 compatible = 1574 compatible = "qcom,geni-spi";
1577 reg = <0 0x00 1575 reg = <0 0x00c80000 0 0x4000>;
1578 reg-names = " 1576 reg-names = "se";
1579 clock-names = 1577 clock-names = "se";
1580 clocks = <&gc 1578 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1581 dmas = <&gpi_ 1579 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1582 <&gpi_ 1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1583 dma-names = " 1581 dma-names = "tx", "rx";
1584 pinctrl-names 1582 pinctrl-names = "default";
1585 pinctrl-0 = < 1583 pinctrl-0 = <&qup_spi17_default>;
1586 interrupts = 1584 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1587 spi-max-frequ 1585 spi-max-frequency = <50000000>;
1588 #address-cell 1586 #address-cells = <1>;
1589 #size-cells = 1587 #size-cells = <0>;
1590 status = "dis 1588 status = "disabled";
1591 }; 1589 };
1592 1590
1593 i2c18: i2c@c84000 { 1591 i2c18: i2c@c84000 {
1594 compatible = 1592 compatible = "qcom,geni-i2c";
1595 reg = <0 0x00 1593 reg = <0 0x00c84000 0 0x4000>;
1596 clock-names = 1594 clock-names = "se";
1597 clocks = <&gc 1595 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1598 dmas = <&gpi_ 1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1599 <&gpi_ 1597 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1600 dma-names = " 1598 dma-names = "tx", "rx";
1601 pinctrl-names 1599 pinctrl-names = "default";
1602 pinctrl-0 = < 1600 pinctrl-0 = <&qup_i2c18_default>;
1603 interrupts = 1601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1604 #address-cell 1602 #address-cells = <1>;
1605 #size-cells = 1603 #size-cells = <0>;
1606 status = "dis 1604 status = "disabled";
1607 }; 1605 };
1608 1606
1609 spi18: spi@c84000 { 1607 spi18: spi@c84000 {
1610 compatible = 1608 compatible = "qcom,geni-spi";
1611 reg = <0 0x00 1609 reg = <0 0x00c84000 0 0x4000>;
1612 reg-names = " 1610 reg-names = "se";
1613 clock-names = 1611 clock-names = "se";
1614 clocks = <&gc 1612 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1615 dmas = <&gpi_ 1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1616 <&gpi_ 1614 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1617 dma-names = " 1615 dma-names = "tx", "rx";
1618 pinctrl-names 1616 pinctrl-names = "default";
1619 pinctrl-0 = < 1617 pinctrl-0 = <&qup_spi18_default>;
1620 interrupts = 1618 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1621 spi-max-frequ 1619 spi-max-frequency = <50000000>;
1622 #address-cell 1620 #address-cells = <1>;
1623 #size-cells = 1621 #size-cells = <0>;
1624 status = "dis 1622 status = "disabled";
1625 }; 1623 };
1626 1624
1627 i2c19: i2c@c88000 { 1625 i2c19: i2c@c88000 {
1628 compatible = 1626 compatible = "qcom,geni-i2c";
1629 reg = <0 0x00 1627 reg = <0 0x00c88000 0 0x4000>;
1630 clock-names = 1628 clock-names = "se";
1631 clocks = <&gc 1629 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1632 dmas = <&gpi_ 1630 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1633 <&gpi_ 1631 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1634 dma-names = " 1632 dma-names = "tx", "rx";
1635 pinctrl-names 1633 pinctrl-names = "default";
1636 pinctrl-0 = < 1634 pinctrl-0 = <&qup_i2c19_default>;
1637 interrupts = 1635 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1638 #address-cell 1636 #address-cells = <1>;
1639 #size-cells = 1637 #size-cells = <0>;
1640 status = "dis 1638 status = "disabled";
1641 }; 1639 };
1642 1640
1643 spi19: spi@c88000 { 1641 spi19: spi@c88000 {
1644 compatible = 1642 compatible = "qcom,geni-spi";
1645 reg = <0 0x00 1643 reg = <0 0x00c88000 0 0x4000>;
1646 reg-names = " 1644 reg-names = "se";
1647 clock-names = 1645 clock-names = "se";
1648 clocks = <&gc 1646 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1649 dmas = <&gpi_ 1647 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1650 <&gpi_ 1648 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1651 dma-names = " 1649 dma-names = "tx", "rx";
1652 pinctrl-names 1650 pinctrl-names = "default";
1653 pinctrl-0 = < 1651 pinctrl-0 = <&qup_spi19_default>;
1654 interrupts = 1652 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1655 spi-max-frequ 1653 spi-max-frequency = <50000000>;
1656 #address-cell 1654 #address-cells = <1>;
1657 #size-cells = 1655 #size-cells = <0>;
1658 status = "dis 1656 status = "disabled";
1659 }; 1657 };
1660 1658
1661 i2c13: i2c@c8c000 { 1659 i2c13: i2c@c8c000 {
1662 compatible = 1660 compatible = "qcom,geni-i2c";
1663 reg = <0 0x00 1661 reg = <0 0x00c8c000 0 0x4000>;
1664 clock-names = 1662 clock-names = "se";
1665 clocks = <&gc 1663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1666 dmas = <&gpi_ 1664 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1667 <&gpi_ 1665 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1668 dma-names = " 1666 dma-names = "tx", "rx";
1669 pinctrl-names 1667 pinctrl-names = "default";
1670 pinctrl-0 = < 1668 pinctrl-0 = <&qup_i2c13_default>;
1671 interrupts = 1669 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1672 #address-cell 1670 #address-cells = <1>;
1673 #size-cells = 1671 #size-cells = <0>;
1674 status = "dis 1672 status = "disabled";
1675 }; 1673 };
1676 1674
1677 spi13: spi@c8c000 { 1675 spi13: spi@c8c000 {
1678 compatible = 1676 compatible = "qcom,geni-spi";
1679 reg = <0 0x00 1677 reg = <0 0x00c8c000 0 0x4000>;
1680 reg-names = " 1678 reg-names = "se";
1681 clock-names = 1679 clock-names = "se";
1682 clocks = <&gc 1680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1683 dmas = <&gpi_ 1681 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1684 <&gpi_ 1682 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1685 dma-names = " 1683 dma-names = "tx", "rx";
1686 pinctrl-names 1684 pinctrl-names = "default";
1687 pinctrl-0 = < 1685 pinctrl-0 = <&qup_spi13_default>;
1688 interrupts = 1686 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1689 spi-max-frequ 1687 spi-max-frequency = <50000000>;
1690 #address-cell 1688 #address-cells = <1>;
1691 #size-cells = 1689 #size-cells = <0>;
1692 status = "dis 1690 status = "disabled";
1693 }; 1691 };
1694 1692
1695 i2c14: i2c@c90000 { 1693 i2c14: i2c@c90000 {
1696 compatible = 1694 compatible = "qcom,geni-i2c";
1697 reg = <0 0x00 1695 reg = <0 0x00c90000 0 0x4000>;
1698 clock-names = 1696 clock-names = "se";
1699 clocks = <&gc 1697 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1700 dmas = <&gpi_ 1698 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1701 <&gpi_ 1699 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1702 dma-names = " 1700 dma-names = "tx", "rx";
1703 pinctrl-names 1701 pinctrl-names = "default";
1704 pinctrl-0 = < 1702 pinctrl-0 = <&qup_i2c14_default>;
1705 interrupts = 1703 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1706 #address-cell 1704 #address-cells = <1>;
1707 #size-cells = 1705 #size-cells = <0>;
1708 status = "dis 1706 status = "disabled";
1709 }; 1707 };
1710 1708
1711 spi14: spi@c90000 { 1709 spi14: spi@c90000 {
1712 compatible = 1710 compatible = "qcom,geni-spi";
1713 reg = <0 0x00 1711 reg = <0 0x00c90000 0 0x4000>;
1714 reg-names = " 1712 reg-names = "se";
1715 clock-names = 1713 clock-names = "se";
1716 clocks = <&gc 1714 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1717 dmas = <&gpi_ 1715 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1718 <&gpi_ 1716 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1719 dma-names = " 1717 dma-names = "tx", "rx";
1720 pinctrl-names 1718 pinctrl-names = "default";
1721 pinctrl-0 = < 1719 pinctrl-0 = <&qup_spi14_default>;
1722 interrupts = 1720 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1723 spi-max-frequ 1721 spi-max-frequency = <50000000>;
1724 #address-cell 1722 #address-cells = <1>;
1725 #size-cells = 1723 #size-cells = <0>;
1726 status = "dis 1724 status = "disabled";
1727 }; 1725 };
1728 1726
1729 i2c15: i2c@c94000 { 1727 i2c15: i2c@c94000 {
1730 compatible = 1728 compatible = "qcom,geni-i2c";
1731 reg = <0 0x00 1729 reg = <0 0x00c94000 0 0x4000>;
1732 clock-names = 1730 clock-names = "se";
1733 clocks = <&gc 1731 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1734 dmas = <&gpi_ 1732 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1735 <&gpi_ 1733 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1736 dma-names = " 1734 dma-names = "tx", "rx";
1737 pinctrl-names 1735 pinctrl-names = "default";
1738 pinctrl-0 = < 1736 pinctrl-0 = <&qup_i2c15_default>;
1739 interrupts = 1737 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1740 #address-cell 1738 #address-cells = <1>;
1741 #size-cells = 1739 #size-cells = <0>;
1742 status = "dis 1740 status = "disabled";
1743 }; 1741 };
1744 1742
1745 spi15: spi@c94000 { 1743 spi15: spi@c94000 {
1746 compatible = 1744 compatible = "qcom,geni-spi";
1747 reg = <0 0x00 1745 reg = <0 0x00c94000 0 0x4000>;
1748 reg-names = " 1746 reg-names = "se";
1749 clock-names = 1747 clock-names = "se";
1750 clocks = <&gc 1748 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1751 dmas = <&gpi_ 1749 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1752 <&gpi_ 1750 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1753 dma-names = " 1751 dma-names = "tx", "rx";
1754 pinctrl-names 1752 pinctrl-names = "default";
1755 pinctrl-0 = < 1753 pinctrl-0 = <&qup_spi15_default>;
1756 interrupts = 1754 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1757 spi-max-frequ 1755 spi-max-frequency = <50000000>;
1758 #address-cell 1756 #address-cells = <1>;
1759 #size-cells = 1757 #size-cells = <0>;
1760 status = "dis 1758 status = "disabled";
1761 }; 1759 };
1762 }; 1760 };
1763 1761
1764 config_noc: interconnect@1500 1762 config_noc: interconnect@1500000 {
1765 compatible = "qcom,sm 1763 compatible = "qcom,sm8150-config-noc";
1766 reg = <0 0x01500000 0 1764 reg = <0 0x01500000 0 0x7400>;
1767 #interconnect-cells = 1765 #interconnect-cells = <2>;
1768 qcom,bcm-voters = <&a 1766 qcom,bcm-voters = <&apps_bcm_voter>;
1769 }; 1767 };
1770 1768
1771 system_noc: interconnect@1620 1769 system_noc: interconnect@1620000 {
1772 compatible = "qcom,sm 1770 compatible = "qcom,sm8150-system-noc";
1773 reg = <0 0x01620000 0 1771 reg = <0 0x01620000 0 0x19400>;
1774 #interconnect-cells = 1772 #interconnect-cells = <2>;
1775 qcom,bcm-voters = <&a 1773 qcom,bcm-voters = <&apps_bcm_voter>;
1776 }; 1774 };
1777 1775
1778 mc_virt: interconnect@163a000 1776 mc_virt: interconnect@163a000 {
1779 compatible = "qcom,sm 1777 compatible = "qcom,sm8150-mc-virt";
1780 reg = <0 0x0163a000 0 1778 reg = <0 0x0163a000 0 0x1000>;
1781 #interconnect-cells = 1779 #interconnect-cells = <2>;
1782 qcom,bcm-voters = <&a 1780 qcom,bcm-voters = <&apps_bcm_voter>;
1783 }; 1781 };
1784 1782
1785 aggre1_noc: interconnect@16e0 1783 aggre1_noc: interconnect@16e0000 {
1786 compatible = "qcom,sm 1784 compatible = "qcom,sm8150-aggre1-noc";
1787 reg = <0 0x016e0000 0 1785 reg = <0 0x016e0000 0 0xd080>;
1788 #interconnect-cells = 1786 #interconnect-cells = <2>;
1789 qcom,bcm-voters = <&a 1787 qcom,bcm-voters = <&apps_bcm_voter>;
1790 }; 1788 };
1791 1789
1792 aggre2_noc: interconnect@1700 1790 aggre2_noc: interconnect@1700000 {
1793 compatible = "qcom,sm 1791 compatible = "qcom,sm8150-aggre2-noc";
1794 reg = <0 0x01700000 0 1792 reg = <0 0x01700000 0 0x20000>;
1795 #interconnect-cells = 1793 #interconnect-cells = <2>;
1796 qcom,bcm-voters = <&a 1794 qcom,bcm-voters = <&apps_bcm_voter>;
1797 }; 1795 };
1798 1796
1799 compute_noc: interconnect@172 1797 compute_noc: interconnect@1720000 {
1800 compatible = "qcom,sm 1798 compatible = "qcom,sm8150-compute-noc";
1801 reg = <0 0x01720000 0 1799 reg = <0 0x01720000 0 0x7000>;
1802 #interconnect-cells = 1800 #interconnect-cells = <2>;
1803 qcom,bcm-voters = <&a 1801 qcom,bcm-voters = <&apps_bcm_voter>;
1804 }; 1802 };
1805 1803
1806 mmss_noc: interconnect@174000 1804 mmss_noc: interconnect@1740000 {
1807 compatible = "qcom,sm 1805 compatible = "qcom,sm8150-mmss-noc";
1808 reg = <0 0x01740000 0 1806 reg = <0 0x01740000 0 0x1c100>;
1809 #interconnect-cells = 1807 #interconnect-cells = <2>;
1810 qcom,bcm-voters = <&a 1808 qcom,bcm-voters = <&apps_bcm_voter>;
1811 }; 1809 };
1812 1810
1813 system-cache-controller@92000 1811 system-cache-controller@9200000 {
1814 compatible = "qcom,sm 1812 compatible = "qcom,sm8150-llcc";
1815 reg = <0 0x09200000 0 1813 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
1816 <0 0x09300000 0 1814 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
1817 <0 0x09600000 0 1815 <0 0x09600000 0 0x50000>;
1818 reg-names = "llcc0_ba 1816 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1819 "llcc3_ba 1817 "llcc3_base", "llcc_broadcast_base";
1820 interrupts = <GIC_SPI 1818 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1821 }; 1819 };
1822 1820
1823 dma@10a2000 { 1821 dma@10a2000 {
1824 compatible = "qcom,sm 1822 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1825 reg = <0x0 0x010a2000 1823 reg = <0x0 0x010a2000 0x0 0x1000>,
1826 <0x0 0x010ad000 1824 <0x0 0x010ad000 0x0 0x3000>;
1827 }; 1825 };
1828 1826
1829 pcie0: pcie@1c00000 { 1827 pcie0: pcie@1c00000 {
1830 compatible = "qcom,pc 1828 compatible = "qcom,pcie-sm8150";
1831 reg = <0 0x01c00000 0 1829 reg = <0 0x01c00000 0 0x3000>,
1832 <0 0x60000000 0 1830 <0 0x60000000 0 0xf1d>,
1833 <0 0x60000f20 0 1831 <0 0x60000f20 0 0xa8>,
1834 <0 0x60001000 0 1832 <0 0x60001000 0 0x1000>,
1835 <0 0x60100000 0 1833 <0 0x60100000 0 0x100000>;
1836 reg-names = "parf", " 1834 reg-names = "parf", "dbi", "elbi", "atu", "config";
1837 device_type = "pci"; 1835 device_type = "pci";
1838 linux,pci-domain = <0 1836 linux,pci-domain = <0>;
1839 bus-range = <0x00 0xf 1837 bus-range = <0x00 0xff>;
1840 num-lanes = <1>; 1838 num-lanes = <1>;
1841 1839
1842 #address-cells = <3>; 1840 #address-cells = <3>;
1843 #size-cells = <2>; 1841 #size-cells = <2>;
1844 1842
1845 ranges = <0x01000000 1843 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1846 <0x02000000 1844 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1847 1845
1848 interrupts = <GIC_SPI !! 1846 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1849 <GIC_SPI !! 1847 interrupt-names = "msi";
1850 <GIC_SPI <<
1851 <GIC_SPI <<
1852 <GIC_SPI <<
1853 <GIC_SPI <<
1854 <GIC_SPI <<
1855 <GIC_SPI <<
1856 interrupt-names = "ms <<
1857 "ms <<
1858 "ms <<
1859 "ms <<
1860 "ms <<
1861 "ms <<
1862 "ms <<
1863 "ms <<
1864 #interrupt-cells = <1 1848 #interrupt-cells = <1>;
1865 interrupt-map-mask = 1849 interrupt-map-mask = <0 0 0 0x7>;
1866 interrupt-map = <0 0 1850 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1867 <0 0 1851 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1868 <0 0 1852 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1869 <0 0 1853 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1870 1854
1871 clocks = <&gcc GCC_PC 1855 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1872 <&gcc GCC_PC 1856 <&gcc GCC_PCIE_0_AUX_CLK>,
1873 <&gcc GCC_PC 1857 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1874 <&gcc GCC_PC 1858 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1875 <&gcc GCC_PC 1859 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1876 <&gcc GCC_PC 1860 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1877 <&gcc GCC_AG !! 1861 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1878 <&rpmhcc RPM <<
1879 clock-names = "pipe", 1862 clock-names = "pipe",
1880 "aux", 1863 "aux",
1881 "cfg", 1864 "cfg",
1882 "bus_ma 1865 "bus_master",
1883 "bus_sl 1866 "bus_slave",
1884 "slave_ 1867 "slave_q2a",
1885 "tbu", !! 1868 "tbu";
1886 "ref"; <<
1887 1869
1888 iommu-map = <0x0 &a 1870 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1889 <0x100 &a 1871 <0x100 &apps_smmu 0x1d81 0x1>;
1890 1872
1891 resets = <&gcc GCC_PC 1873 resets = <&gcc GCC_PCIE_0_BCR>;
1892 reset-names = "pci"; 1874 reset-names = "pci";
1893 1875
1894 power-domains = <&gcc 1876 power-domains = <&gcc PCIE_0_GDSC>;
1895 1877
1896 phys = <&pcie0_phy>; 1878 phys = <&pcie0_phy>;
1897 phy-names = "pciephy" 1879 phy-names = "pciephy";
1898 1880
1899 perst-gpios = <&tlmm 1881 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1900 wake-gpios = <&tlmm 3 1882 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1901 1883
1902 pinctrl-names = "defa 1884 pinctrl-names = "default";
1903 pinctrl-0 = <&pcie0_d 1885 pinctrl-0 = <&pcie0_default_state>;
1904 1886
1905 status = "disabled"; 1887 status = "disabled";
1906 <<
1907 pcie@0 { <<
1908 device_type = <<
1909 reg = <0x0 0x <<
1910 bus-range = < <<
1911 <<
1912 #address-cell <<
1913 #size-cells = <<
1914 ranges; <<
1915 }; <<
1916 }; 1888 };
1917 1889
1918 pcie0_phy: phy@1c06000 { 1890 pcie0_phy: phy@1c06000 {
1919 compatible = "qcom,sm 1891 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1920 reg = <0 0x01c06000 0 1892 reg = <0 0x01c06000 0 0x1000>;
1921 clocks = <&gcc GCC_PC 1893 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1922 <&gcc GCC_PC 1894 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1923 <&gcc GCC_PC 1895 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1924 <&gcc GCC_PC 1896 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1925 <&gcc GCC_PC 1897 <&gcc GCC_PCIE_0_PIPE_CLK>;
1926 clock-names = "aux", 1898 clock-names = "aux",
1927 "cfg_ah 1899 "cfg_ahb",
1928 "ref", 1900 "ref",
1929 "refgen 1901 "refgen",
1930 "pipe"; 1902 "pipe";
1931 1903
1932 clock-output-names = 1904 clock-output-names = "pcie_0_pipe_clk";
1933 #clock-cells = <0>; 1905 #clock-cells = <0>;
1934 1906
1935 #phy-cells = <0>; 1907 #phy-cells = <0>;
1936 1908
1937 resets = <&gcc GCC_PC 1909 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1938 reset-names = "phy"; 1910 reset-names = "phy";
1939 1911
1940 assigned-clocks = <&g 1912 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1941 assigned-clock-rates 1913 assigned-clock-rates = <100000000>;
1942 1914
1943 status = "disabled"; 1915 status = "disabled";
1944 }; 1916 };
1945 1917
1946 pcie1: pcie@1c08000 { 1918 pcie1: pcie@1c08000 {
1947 compatible = "qcom,pc 1919 compatible = "qcom,pcie-sm8150";
1948 reg = <0 0x01c08000 0 1920 reg = <0 0x01c08000 0 0x3000>,
1949 <0 0x40000000 0 1921 <0 0x40000000 0 0xf1d>,
1950 <0 0x40000f20 0 1922 <0 0x40000f20 0 0xa8>,
1951 <0 0x40001000 0 1923 <0 0x40001000 0 0x1000>,
1952 <0 0x40100000 0 1924 <0 0x40100000 0 0x100000>;
1953 reg-names = "parf", " 1925 reg-names = "parf", "dbi", "elbi", "atu", "config";
1954 device_type = "pci"; 1926 device_type = "pci";
1955 linux,pci-domain = <1 1927 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xf 1928 bus-range = <0x00 0xff>;
1957 num-lanes = <2>; 1929 num-lanes = <2>;
1958 1930
1959 #address-cells = <3>; 1931 #address-cells = <3>;
1960 #size-cells = <2>; 1932 #size-cells = <2>;
1961 1933
1962 ranges = <0x01000000 1934 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1963 <0x02000000 1935 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1964 1936
1965 interrupts = <GIC_SPI !! 1937 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
1966 <GIC_SPI !! 1938 interrupt-names = "msi";
1967 <GIC_SPI <<
1968 <GIC_SPI <<
1969 <GIC_SPI <<
1970 <GIC_SPI <<
1971 <GIC_SPI <<
1972 <GIC_SPI <<
1973 interrupt-names = "ms <<
1974 "ms <<
1975 "ms <<
1976 "ms <<
1977 "ms <<
1978 "ms <<
1979 "ms <<
1980 "ms <<
1981 #interrupt-cells = <1 1939 #interrupt-cells = <1>;
1982 interrupt-map-mask = 1940 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 1941 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1984 <0 0 1942 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1985 <0 0 1943 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1986 <0 0 1944 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 1945
1988 clocks = <&gcc GCC_PC 1946 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1989 <&gcc GCC_PC 1947 <&gcc GCC_PCIE_1_AUX_CLK>,
1990 <&gcc GCC_PC 1948 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1991 <&gcc GCC_PC 1949 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1992 <&gcc GCC_PC 1950 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1993 <&gcc GCC_PC 1951 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1994 <&gcc GCC_AG !! 1952 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 <&rpmhcc RPM <<
1996 clock-names = "pipe", 1953 clock-names = "pipe",
1997 "aux", 1954 "aux",
1998 "cfg", 1955 "cfg",
1999 "bus_ma 1956 "bus_master",
2000 "bus_sl 1957 "bus_slave",
2001 "slave_ 1958 "slave_q2a",
2002 "tbu", !! 1959 "tbu";
2003 "ref"; <<
2004 1960
2005 assigned-clocks = <&g 1961 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates 1962 assigned-clock-rates = <19200000>;
2007 1963
2008 iommu-map = <0x0 &a 1964 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
2009 <0x100 &a 1965 <0x100 &apps_smmu 0x1e01 0x1>;
2010 1966
2011 resets = <&gcc GCC_PC 1967 resets = <&gcc GCC_PCIE_1_BCR>;
2012 reset-names = "pci"; 1968 reset-names = "pci";
2013 1969
2014 power-domains = <&gcc 1970 power-domains = <&gcc PCIE_1_GDSC>;
2015 1971
2016 phys = <&pcie1_phy>; 1972 phys = <&pcie1_phy>;
2017 phy-names = "pciephy" 1973 phy-names = "pciephy";
2018 1974
2019 perst-gpios = <&tlmm 1975 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
2020 enable-gpio = <&tlmm 1976 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
2021 1977
2022 pinctrl-names = "defa 1978 pinctrl-names = "default";
2023 pinctrl-0 = <&pcie1_d 1979 pinctrl-0 = <&pcie1_default_state>;
2024 1980
2025 status = "disabled"; 1981 status = "disabled";
2026 <<
2027 pcie@0 { <<
2028 device_type = <<
2029 reg = <0x0 0x <<
2030 bus-range = < <<
2031 <<
2032 #address-cell <<
2033 #size-cells = <<
2034 ranges; <<
2035 }; <<
2036 }; 1982 };
2037 1983
2038 pcie1_phy: phy@1c0e000 { 1984 pcie1_phy: phy@1c0e000 {
2039 compatible = "qcom,sm 1985 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
2040 reg = <0 0x01c0e000 0 1986 reg = <0 0x01c0e000 0 0x1000>;
2041 clocks = <&gcc GCC_PC 1987 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2042 <&gcc GCC_PC 1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2043 <&gcc GCC_PC 1989 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2044 <&gcc GCC_PC 1990 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2045 <&gcc GCC_PC 1991 <&gcc GCC_PCIE_1_PIPE_CLK>;
2046 clock-names = "aux", 1992 clock-names = "aux",
2047 "cfg_ah 1993 "cfg_ahb",
2048 "ref", 1994 "ref",
2049 "refgen 1995 "refgen",
2050 "pipe"; 1996 "pipe";
2051 1997
2052 clock-output-names = 1998 clock-output-names = "pcie_1_pipe_clk";
2053 #clock-cells = <0>; 1999 #clock-cells = <0>;
2054 2000
2055 #phy-cells = <0>; 2001 #phy-cells = <0>;
2056 2002
2057 resets = <&gcc GCC_PC 2003 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2058 reset-names = "phy"; 2004 reset-names = "phy";
2059 2005
2060 assigned-clocks = <&g 2006 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2061 assigned-clock-rates 2007 assigned-clock-rates = <100000000>;
2062 2008
2063 status = "disabled"; 2009 status = "disabled";
2064 }; 2010 };
2065 2011
2066 ufs_mem_hc: ufshc@1d84000 { 2012 ufs_mem_hc: ufshc@1d84000 {
2067 compatible = "qcom,sm 2013 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2068 "jedec,u 2014 "jedec,ufs-2.0";
2069 reg = <0 0x01d84000 0 2015 reg = <0 0x01d84000 0 0x2500>,
2070 <0 0x01d90000 0 2016 <0 0x01d90000 0 0x8000>;
2071 reg-names = "std", "i 2017 reg-names = "std", "ice";
2072 interrupts = <GIC_SPI 2018 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2073 phys = <&ufs_mem_phy> 2019 phys = <&ufs_mem_phy>;
2074 phy-names = "ufsphy"; 2020 phy-names = "ufsphy";
2075 lanes-per-direction = 2021 lanes-per-direction = <2>;
2076 #reset-cells = <1>; 2022 #reset-cells = <1>;
2077 resets = <&gcc GCC_UF 2023 resets = <&gcc GCC_UFS_PHY_BCR>;
2078 reset-names = "rst"; 2024 reset-names = "rst";
2079 2025
2080 iommus = <&apps_smmu 2026 iommus = <&apps_smmu 0x300 0>;
2081 2027
2082 clock-names = 2028 clock-names =
2083 "core_clk", 2029 "core_clk",
2084 "bus_aggr_clk 2030 "bus_aggr_clk",
2085 "iface_clk", 2031 "iface_clk",
2086 "core_clk_uni 2032 "core_clk_unipro",
2087 "ref_clk", 2033 "ref_clk",
2088 "tx_lane0_syn 2034 "tx_lane0_sync_clk",
2089 "rx_lane0_syn 2035 "rx_lane0_sync_clk",
2090 "rx_lane1_syn 2036 "rx_lane1_sync_clk",
2091 "ice_core_clk 2037 "ice_core_clk";
2092 clocks = 2038 clocks =
2093 <&gcc GCC_UFS 2039 <&gcc GCC_UFS_PHY_AXI_CLK>,
2094 <&gcc GCC_AGG 2040 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2095 <&gcc GCC_UFS 2041 <&gcc GCC_UFS_PHY_AHB_CLK>,
2096 <&gcc GCC_UFS 2042 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2097 <&rpmhcc RPMH 2043 <&rpmhcc RPMH_CXO_CLK>,
2098 <&gcc GCC_UFS 2044 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2099 <&gcc GCC_UFS 2045 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2100 <&gcc GCC_UFS 2046 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
2101 <&gcc GCC_UFS 2047 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
2102 freq-table-hz = 2048 freq-table-hz =
2103 <37500000 300 2049 <37500000 300000000>,
2104 <0 0>, 2050 <0 0>,
2105 <0 0>, 2051 <0 0>,
2106 <37500000 300 2052 <37500000 300000000>,
2107 <0 0>, 2053 <0 0>,
2108 <0 0>, 2054 <0 0>,
2109 <0 0>, 2055 <0 0>,
2110 <0 0>, 2056 <0 0>,
2111 <0 300000000> 2057 <0 300000000>;
2112 2058
2113 status = "disabled"; 2059 status = "disabled";
2114 }; 2060 };
2115 2061
2116 ufs_mem_phy: phy@1d87000 { 2062 ufs_mem_phy: phy@1d87000 {
2117 compatible = "qcom,sm 2063 compatible = "qcom,sm8150-qmp-ufs-phy";
2118 reg = <0 0x01d87000 0 2064 reg = <0 0x01d87000 0 0x1000>;
2119 2065
2120 clocks = <&rpmhcc RPM <<
2121 <&gcc GCC_UF <<
2122 <&gcc GCC_UF <<
2123 clock-names = "ref", 2066 clock-names = "ref",
2124 "ref_au !! 2067 "ref_aux";
2125 "qref"; !! 2068 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>> 2069 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2126 2070
2127 power-domains = <&gcc 2071 power-domains = <&gcc UFS_PHY_GDSC>;
2128 2072
2129 resets = <&ufs_mem_hc 2073 resets = <&ufs_mem_hc 0>;
2130 reset-names = "ufsphy 2074 reset-names = "ufsphy";
2131 2075
2132 #phy-cells = <0>; 2076 #phy-cells = <0>;
2133 2077
2134 status = "disabled"; 2078 status = "disabled";
2135 }; 2079 };
2136 2080
2137 cryptobam: dma-controller@1dc 2081 cryptobam: dma-controller@1dc4000 {
2138 compatible = "qcom,ba 2082 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2139 reg = <0 0x01dc4000 0 2083 reg = <0 0x01dc4000 0 0x24000>;
2140 interrupts = <GIC_SPI 2084 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2141 #dma-cells = <1>; 2085 #dma-cells = <1>;
2142 qcom,ee = <0>; 2086 qcom,ee = <0>;
2143 qcom,controlled-remot 2087 qcom,controlled-remotely;
2144 num-channels = <8>; 2088 num-channels = <8>;
2145 qcom,num-ees = <2>; 2089 qcom,num-ees = <2>;
2146 iommus = <&apps_smmu 2090 iommus = <&apps_smmu 0x502 0x0641>,
2147 <&apps_smmu 2091 <&apps_smmu 0x504 0x0011>,
2148 <&apps_smmu 2092 <&apps_smmu 0x506 0x0011>,
2149 <&apps_smmu 2093 <&apps_smmu 0x508 0x0011>,
2150 <&apps_smmu 2094 <&apps_smmu 0x512 0x0000>;
2151 }; 2095 };
2152 2096
2153 crypto: crypto@1dfa000 { 2097 crypto: crypto@1dfa000 {
2154 compatible = "qcom,sm 2098 compatible = "qcom,sm8150-qce", "qcom,qce";
2155 reg = <0 0x01dfa000 0 2099 reg = <0 0x01dfa000 0 0x6000>;
2156 dmas = <&cryptobam 4> 2100 dmas = <&cryptobam 4>, <&cryptobam 5>;
2157 dma-names = "rx", "tx 2101 dma-names = "rx", "tx";
2158 iommus = <&apps_smmu 2102 iommus = <&apps_smmu 0x502 0x0641>,
2159 <&apps_smmu 2103 <&apps_smmu 0x504 0x0011>,
2160 <&apps_smmu 2104 <&apps_smmu 0x506 0x0011>,
2161 <&apps_smmu 2105 <&apps_smmu 0x508 0x0011>,
2162 <&apps_smmu 2106 <&apps_smmu 0x512 0x0000>;
2163 interconnects = <&agg 2107 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2164 interconnect-names = 2108 interconnect-names = "memory";
2165 }; 2109 };
2166 2110
2167 tcsr_mutex: hwlock@1f40000 { 2111 tcsr_mutex: hwlock@1f40000 {
2168 compatible = "qcom,tc 2112 compatible = "qcom,tcsr-mutex";
2169 reg = <0x0 0x01f40000 2113 reg = <0x0 0x01f40000 0x0 0x20000>;
2170 #hwlock-cells = <1>; 2114 #hwlock-cells = <1>;
2171 }; 2115 };
2172 2116
2173 tcsr_regs_1: syscon@1f60000 { 2117 tcsr_regs_1: syscon@1f60000 {
2174 compatible = "qcom,sm 2118 compatible = "qcom,sm8150-tcsr", "syscon";
2175 reg = <0x0 0x01f60000 2119 reg = <0x0 0x01f60000 0x0 0x20000>;
2176 }; 2120 };
2177 2121
2178 remoteproc_slpi: remoteproc@2 2122 remoteproc_slpi: remoteproc@2400000 {
2179 compatible = "qcom,sm 2123 compatible = "qcom,sm8150-slpi-pas";
2180 reg = <0x0 0x02400000 2124 reg = <0x0 0x02400000 0x0 0x4040>;
2181 2125
2182 interrupts-extended = 2126 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2183 2127 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2184 2128 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2185 2129 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2186 2130 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2187 interrupt-names = "wd 2131 interrupt-names = "wdog", "fatal", "ready",
2188 "ha 2132 "handover", "stop-ack";
2189 2133
2190 clocks = <&rpmhcc RPM 2134 clocks = <&rpmhcc RPMH_CXO_CLK>;
2191 clock-names = "xo"; 2135 clock-names = "xo";
2192 2136
2193 power-domains = <&rpm 2137 power-domains = <&rpmhpd SM8150_LCX>,
2194 <&rpm 2138 <&rpmhpd SM8150_LMX>;
2195 power-domain-names = 2139 power-domain-names = "lcx", "lmx";
2196 2140
2197 memory-region = <&slp 2141 memory-region = <&slpi_mem>;
2198 2142
2199 qcom,qmp = <&aoss_qmp 2143 qcom,qmp = <&aoss_qmp>;
2200 2144
2201 qcom,smem-states = <& 2145 qcom,smem-states = <&slpi_smp2p_out 0>;
2202 qcom,smem-state-names 2146 qcom,smem-state-names = "stop";
2203 2147
2204 status = "disabled"; 2148 status = "disabled";
2205 2149
2206 glink-edge { 2150 glink-edge {
2207 interrupts = 2151 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
2208 label = "dsps 2152 label = "dsps";
2209 qcom,remote-p 2153 qcom,remote-pid = <3>;
2210 mboxes = <&ap 2154 mboxes = <&apss_shared 24>;
2211 2155
2212 fastrpc { 2156 fastrpc {
2213 compa 2157 compatible = "qcom,fastrpc";
2214 qcom, 2158 qcom,glink-channels = "fastrpcglink-apps-dsp";
2215 label 2159 label = "sdsp";
2216 qcom, 2160 qcom,non-secure-domain;
2217 #addr 2161 #address-cells = <1>;
2218 #size 2162 #size-cells = <0>;
2219 2163
2220 compu 2164 compute-cb@1 {
2221 2165 compatible = "qcom,fastrpc-compute-cb";
2222 2166 reg = <1>;
2223 2167 iommus = <&apps_smmu 0x05a1 0x0>;
2224 }; 2168 };
2225 2169
2226 compu 2170 compute-cb@2 {
2227 2171 compatible = "qcom,fastrpc-compute-cb";
2228 2172 reg = <2>;
2229 2173 iommus = <&apps_smmu 0x05a2 0x0>;
2230 }; 2174 };
2231 2175
2232 compu 2176 compute-cb@3 {
2233 2177 compatible = "qcom,fastrpc-compute-cb";
2234 2178 reg = <3>;
2235 2179 iommus = <&apps_smmu 0x05a3 0x0>;
2236 2180 /* note: shared-cb = <4> in downstream */
2237 }; 2181 };
2238 }; 2182 };
2239 }; 2183 };
2240 }; 2184 };
2241 2185
2242 gpu: gpu@2c00000 { 2186 gpu: gpu@2c00000 {
2243 compatible = "qcom,ad 2187 compatible = "qcom,adreno-640.1", "qcom,adreno";
2244 reg = <0 0x02c00000 0 2188 reg = <0 0x02c00000 0 0x40000>;
2245 reg-names = "kgsl_3d0 2189 reg-names = "kgsl_3d0_reg_memory";
2246 2190
2247 interrupts = <GIC_SPI 2191 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2248 2192
2249 iommus = <&adreno_smm 2193 iommus = <&adreno_smmu 0 0x401>;
2250 2194
2251 operating-points-v2 = 2195 operating-points-v2 = <&gpu_opp_table>;
2252 2196
2253 qcom,gmu = <&gmu>; 2197 qcom,gmu = <&gmu>;
2254 2198
2255 nvmem-cells = <&gpu_s 2199 nvmem-cells = <&gpu_speed_bin>;
2256 nvmem-cell-names = "s 2200 nvmem-cell-names = "speed_bin";
2257 #cooling-cells = <2>; <<
2258 2201
2259 status = "disabled"; 2202 status = "disabled";
2260 2203
2261 zap-shader { 2204 zap-shader {
2262 memory-region 2205 memory-region = <&gpu_mem>;
2263 }; 2206 };
2264 2207
2265 gpu_opp_table: opp-ta 2208 gpu_opp_table: opp-table {
2266 compatible = 2209 compatible = "operating-points-v2";
2267 2210
2268 opp-675000000 2211 opp-675000000 {
2269 opp-h 2212 opp-hz = /bits/ 64 <675000000>;
2270 opp-l 2213 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2271 opp-s 2214 opp-supported-hw = <0x2>;
2272 }; 2215 };
2273 2216
2274 opp-585000000 2217 opp-585000000 {
2275 opp-h 2218 opp-hz = /bits/ 64 <585000000>;
2276 opp-l 2219 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2277 opp-s 2220 opp-supported-hw = <0x3>;
2278 }; 2221 };
2279 2222
2280 opp-499200000 2223 opp-499200000 {
2281 opp-h 2224 opp-hz = /bits/ 64 <499200000>;
2282 opp-l 2225 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2283 opp-s 2226 opp-supported-hw = <0x3>;
2284 }; 2227 };
2285 2228
2286 opp-427000000 2229 opp-427000000 {
2287 opp-h 2230 opp-hz = /bits/ 64 <427000000>;
2288 opp-l 2231 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2289 opp-s 2232 opp-supported-hw = <0x3>;
2290 }; 2233 };
2291 2234
2292 opp-345000000 2235 opp-345000000 {
2293 opp-h 2236 opp-hz = /bits/ 64 <345000000>;
2294 opp-l 2237 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2295 opp-s 2238 opp-supported-hw = <0x3>;
2296 }; 2239 };
2297 2240
2298 opp-257000000 2241 opp-257000000 {
2299 opp-h 2242 opp-hz = /bits/ 64 <257000000>;
2300 opp-l 2243 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2301 opp-s 2244 opp-supported-hw = <0x3>;
2302 }; 2245 };
2303 }; 2246 };
2304 }; 2247 };
2305 2248
2306 gmu: gmu@2c6a000 { 2249 gmu: gmu@2c6a000 {
2307 compatible = "qcom,ad 2250 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2308 2251
2309 reg = <0 0x02c6a000 0 2252 reg = <0 0x02c6a000 0 0x30000>,
2310 <0 0x0b290000 0 2253 <0 0x0b290000 0 0x10000>,
2311 <0 0x0b490000 0 2254 <0 0x0b490000 0 0x10000>;
2312 reg-names = "gmu", "g 2255 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2313 2256
2314 interrupts = <GIC_SPI 2257 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2315 <GIC_SPI 2258 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2316 interrupt-names = "hf 2259 interrupt-names = "hfi", "gmu";
2317 2260
2318 clocks = <&gpucc GPU_ 2261 clocks = <&gpucc GPU_CC_AHB_CLK>,
2319 <&gpucc GPU_ 2262 <&gpucc GPU_CC_CX_GMU_CLK>,
2320 <&gpucc GPU_ 2263 <&gpucc GPU_CC_CXO_CLK>,
2321 <&gcc GCC_DD 2264 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2322 <&gcc GCC_GP 2265 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2323 clock-names = "ahb", 2266 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2324 2267
2325 power-domains = <&gpu 2268 power-domains = <&gpucc GPU_CX_GDSC>,
2326 <&gpu 2269 <&gpucc GPU_GX_GDSC>;
2327 power-domain-names = 2270 power-domain-names = "cx", "gx";
2328 2271
2329 iommus = <&adreno_smm 2272 iommus = <&adreno_smmu 5 0x400>;
2330 2273
2331 operating-points-v2 = 2274 operating-points-v2 = <&gmu_opp_table>;
2332 2275
2333 status = "disabled"; 2276 status = "disabled";
2334 2277
2335 gmu_opp_table: opp-ta 2278 gmu_opp_table: opp-table {
2336 compatible = 2279 compatible = "operating-points-v2";
2337 2280
2338 opp-200000000 2281 opp-200000000 {
2339 opp-h 2282 opp-hz = /bits/ 64 <200000000>;
2340 opp-l 2283 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2341 }; 2284 };
2342 }; 2285 };
2343 }; 2286 };
2344 2287
2345 gpucc: clock-controller@2c900 2288 gpucc: clock-controller@2c90000 {
2346 compatible = "qcom,sm 2289 compatible = "qcom,sm8150-gpucc";
2347 reg = <0 0x02c90000 0 2290 reg = <0 0x02c90000 0 0x9000>;
2348 clocks = <&rpmhcc RPM 2291 clocks = <&rpmhcc RPMH_CXO_CLK>,
2349 <&gcc GCC_GP 2292 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2350 <&gcc GCC_GP 2293 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2351 clock-names = "bi_tcx 2294 clock-names = "bi_tcxo",
2352 "gcc_gp 2295 "gcc_gpu_gpll0_clk_src",
2353 "gcc_gp 2296 "gcc_gpu_gpll0_div_clk_src";
2354 #clock-cells = <1>; 2297 #clock-cells = <1>;
2355 #reset-cells = <1>; 2298 #reset-cells = <1>;
2356 #power-domain-cells = 2299 #power-domain-cells = <1>;
2357 }; 2300 };
2358 2301
2359 adreno_smmu: iommu@2ca0000 { 2302 adreno_smmu: iommu@2ca0000 {
2360 compatible = "qcom,sm 2303 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2361 "qcom,sm 2304 "qcom,smmu-500", "arm,mmu-500";
2362 reg = <0 0x02ca0000 0 2305 reg = <0 0x02ca0000 0 0x10000>;
2363 #iommu-cells = <2>; 2306 #iommu-cells = <2>;
2364 #global-interrupts = 2307 #global-interrupts = <1>;
2365 interrupts = <GIC_SPI 2308 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2366 <GIC_SPI 681 2309 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2367 <GIC_SPI 682 2310 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2368 <GIC_SPI 683 2311 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2369 <GIC_SPI 684 2312 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2370 <GIC_SPI 685 2313 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2371 <GIC_SPI 686 2314 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2372 <GIC_SPI 687 2315 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2373 <GIC_SPI 688 2316 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2374 clocks = <&gpucc GPU_ 2317 clocks = <&gpucc GPU_CC_AHB_CLK>,
2375 <&gcc GCC_GP 2318 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2376 <&gcc GCC_GP 2319 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2377 clock-names = "ahb", 2320 clock-names = "ahb", "bus", "iface";
2378 2321
2379 power-domains = <&gpu 2322 power-domains = <&gpucc GPU_CX_GDSC>;
2380 }; 2323 };
2381 2324
2382 tlmm: pinctrl@3100000 { 2325 tlmm: pinctrl@3100000 {
2383 compatible = "qcom,sm 2326 compatible = "qcom,sm8150-pinctrl";
2384 reg = <0x0 0x03100000 2327 reg = <0x0 0x03100000 0x0 0x300000>,
2385 <0x0 0x03500000 2328 <0x0 0x03500000 0x0 0x300000>,
2386 <0x0 0x03900000 2329 <0x0 0x03900000 0x0 0x300000>,
2387 <0x0 0x03D00000 2330 <0x0 0x03D00000 0x0 0x300000>;
2388 reg-names = "west", " 2331 reg-names = "west", "east", "north", "south";
2389 interrupts = <GIC_SPI 2332 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2390 gpio-ranges = <&tlmm 2333 gpio-ranges = <&tlmm 0 0 176>;
2391 gpio-controller; 2334 gpio-controller;
2392 #gpio-cells = <2>; 2335 #gpio-cells = <2>;
2393 interrupt-controller; 2336 interrupt-controller;
2394 #interrupt-cells = <2 2337 #interrupt-cells = <2>;
2395 wakeup-parent = <&pdc 2338 wakeup-parent = <&pdc>;
2396 2339
2397 qup_i2c0_default: qup 2340 qup_i2c0_default: qup-i2c0-default-state {
2398 pins = "gpio0 2341 pins = "gpio0", "gpio1";
2399 function = "q 2342 function = "qup0";
2400 drive-strengt 2343 drive-strength = <0x02>;
2401 bias-disable; 2344 bias-disable;
2402 }; 2345 };
2403 2346
2404 qup_spi0_default: qup 2347 qup_spi0_default: qup-spi0-default-state {
2405 pins = "gpio0 2348 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2406 function = "q 2349 function = "qup0";
2407 drive-strengt 2350 drive-strength = <6>;
2408 bias-disable; 2351 bias-disable;
2409 }; 2352 };
2410 2353
2411 qup_i2c1_default: qup 2354 qup_i2c1_default: qup-i2c1-default-state {
2412 pins = "gpio1 2355 pins = "gpio114", "gpio115";
2413 function = "q 2356 function = "qup1";
2414 drive-strengt 2357 drive-strength = <2>;
2415 bias-disable; 2358 bias-disable;
2416 }; 2359 };
2417 2360
2418 qup_spi1_default: qup 2361 qup_spi1_default: qup-spi1-default-state {
2419 pins = "gpio1 2362 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2420 function = "q 2363 function = "qup1";
2421 drive-strengt 2364 drive-strength = <6>;
2422 bias-disable; 2365 bias-disable;
2423 }; 2366 };
2424 2367
2425 qup_i2c2_default: qup 2368 qup_i2c2_default: qup-i2c2-default-state {
2426 pins = "gpio1 2369 pins = "gpio126", "gpio127";
2427 function = "q 2370 function = "qup2";
2428 drive-strengt 2371 drive-strength = <2>;
2429 bias-disable; 2372 bias-disable;
2430 }; 2373 };
2431 2374
2432 qup_spi2_default: qup 2375 qup_spi2_default: qup-spi2-default-state {
2433 pins = "gpio1 2376 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2434 function = "q 2377 function = "qup2";
2435 drive-strengt 2378 drive-strength = <6>;
2436 bias-disable; 2379 bias-disable;
2437 }; 2380 };
2438 2381
2439 qup_i2c3_default: qup 2382 qup_i2c3_default: qup-i2c3-default-state {
2440 pins = "gpio1 2383 pins = "gpio144", "gpio145";
2441 function = "q 2384 function = "qup3";
2442 drive-strengt 2385 drive-strength = <2>;
2443 bias-disable; 2386 bias-disable;
2444 }; 2387 };
2445 2388
2446 qup_spi3_default: qup 2389 qup_spi3_default: qup-spi3-default-state {
2447 pins = "gpio1 2390 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2448 function = "q 2391 function = "qup3";
2449 drive-strengt 2392 drive-strength = <6>;
2450 bias-disable; 2393 bias-disable;
2451 }; 2394 };
2452 2395
2453 qup_i2c4_default: qup 2396 qup_i2c4_default: qup-i2c4-default-state {
2454 pins = "gpio5 2397 pins = "gpio51", "gpio52";
2455 function = "q 2398 function = "qup4";
2456 drive-strengt 2399 drive-strength = <2>;
2457 bias-disable; 2400 bias-disable;
2458 }; 2401 };
2459 2402
2460 qup_spi4_default: qup 2403 qup_spi4_default: qup-spi4-default-state {
2461 pins = "gpio5 2404 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2462 function = "q 2405 function = "qup4";
2463 drive-strengt 2406 drive-strength = <6>;
2464 bias-disable; 2407 bias-disable;
2465 }; 2408 };
2466 2409
2467 qup_i2c5_default: qup 2410 qup_i2c5_default: qup-i2c5-default-state {
2468 pins = "gpio1 2411 pins = "gpio121", "gpio122";
2469 function = "q 2412 function = "qup5";
2470 drive-strengt 2413 drive-strength = <2>;
2471 bias-disable; 2414 bias-disable;
2472 }; 2415 };
2473 2416
2474 qup_spi5_default: qup 2417 qup_spi5_default: qup-spi5-default-state {
2475 pins = "gpio1 2418 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2476 function = "q 2419 function = "qup5";
2477 drive-strengt 2420 drive-strength = <6>;
2478 bias-disable; 2421 bias-disable;
2479 }; 2422 };
2480 2423
2481 qup_i2c6_default: qup 2424 qup_i2c6_default: qup-i2c6-default-state {
2482 pins = "gpio6 2425 pins = "gpio6", "gpio7";
2483 function = "q 2426 function = "qup6";
2484 drive-strengt 2427 drive-strength = <2>;
2485 bias-disable; 2428 bias-disable;
2486 }; 2429 };
2487 2430
2488 qup_spi6_default: qup !! 2431 qup_spi6_default: qup-spi6_default-state {
2489 pins = "gpio4 2432 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2490 function = "q 2433 function = "qup6";
2491 drive-strengt 2434 drive-strength = <6>;
2492 bias-disable; 2435 bias-disable;
2493 }; 2436 };
2494 2437
2495 qup_i2c7_default: qup 2438 qup_i2c7_default: qup-i2c7-default-state {
2496 pins = "gpio9 2439 pins = "gpio98", "gpio99";
2497 function = "q 2440 function = "qup7";
2498 drive-strengt 2441 drive-strength = <2>;
2499 bias-disable; 2442 bias-disable;
2500 }; 2443 };
2501 2444
2502 qup_spi7_default: qup !! 2445 qup_spi7_default: qup-spi7_default-state {
2503 pins = "gpio9 2446 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2504 function = "q 2447 function = "qup7";
2505 drive-strengt 2448 drive-strength = <6>;
2506 bias-disable; 2449 bias-disable;
2507 }; 2450 };
2508 2451
2509 qup_i2c8_default: qup 2452 qup_i2c8_default: qup-i2c8-default-state {
2510 pins = "gpio8 2453 pins = "gpio88", "gpio89";
2511 function = "q 2454 function = "qup8";
2512 drive-strengt 2455 drive-strength = <2>;
2513 bias-disable; 2456 bias-disable;
2514 }; 2457 };
2515 2458
2516 qup_spi8_default: qup 2459 qup_spi8_default: qup-spi8-default-state {
2517 pins = "gpio8 2460 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2518 function = "q 2461 function = "qup8";
2519 drive-strengt 2462 drive-strength = <6>;
2520 bias-disable; 2463 bias-disable;
2521 }; 2464 };
2522 2465
2523 qup_i2c9_default: qup 2466 qup_i2c9_default: qup-i2c9-default-state {
2524 pins = "gpio3 2467 pins = "gpio39", "gpio40";
2525 function = "q 2468 function = "qup9";
2526 drive-strengt 2469 drive-strength = <2>;
2527 bias-disable; 2470 bias-disable;
2528 }; 2471 };
2529 2472
2530 qup_spi9_default: qup 2473 qup_spi9_default: qup-spi9-default-state {
2531 pins = "gpio3 2474 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2532 function = "q 2475 function = "qup9";
2533 drive-strengt 2476 drive-strength = <6>;
2534 bias-disable; 2477 bias-disable;
2535 }; 2478 };
2536 2479
2537 qup_uart9_default: qu 2480 qup_uart9_default: qup-uart9-default-state {
2538 pins = "gpio4 2481 pins = "gpio41", "gpio42";
2539 function = "q 2482 function = "qup9";
2540 drive-strengt 2483 drive-strength = <2>;
2541 bias-disable; 2484 bias-disable;
2542 }; 2485 };
2543 2486
2544 qup_i2c10_default: qu 2487 qup_i2c10_default: qup-i2c10-default-state {
2545 pins = "gpio9 2488 pins = "gpio9", "gpio10";
2546 function = "q 2489 function = "qup10";
2547 drive-strengt 2490 drive-strength = <2>;
2548 bias-disable; 2491 bias-disable;
2549 }; 2492 };
2550 2493
2551 qup_spi10_default: qu 2494 qup_spi10_default: qup-spi10-default-state {
2552 pins = "gpio9 2495 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2553 function = "q 2496 function = "qup10";
2554 drive-strengt 2497 drive-strength = <6>;
2555 bias-disable; 2498 bias-disable;
2556 }; 2499 };
2557 2500
2558 qup_i2c11_default: qu 2501 qup_i2c11_default: qup-i2c11-default-state {
2559 pins = "gpio9 2502 pins = "gpio94", "gpio95";
2560 function = "q 2503 function = "qup11";
2561 drive-strengt 2504 drive-strength = <2>;
2562 bias-disable; 2505 bias-disable;
2563 }; 2506 };
2564 2507
2565 qup_spi11_default: qu 2508 qup_spi11_default: qup-spi11-default-state {
2566 pins = "gpio9 2509 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2567 function = "q 2510 function = "qup11";
2568 drive-strengt 2511 drive-strength = <6>;
2569 bias-disable; 2512 bias-disable;
2570 }; 2513 };
2571 2514
2572 qup_i2c12_default: qu 2515 qup_i2c12_default: qup-i2c12-default-state {
2573 pins = "gpio8 2516 pins = "gpio83", "gpio84";
2574 function = "q 2517 function = "qup12";
2575 drive-strengt 2518 drive-strength = <2>;
2576 bias-disable; 2519 bias-disable;
2577 }; 2520 };
2578 2521
2579 qup_spi12_default: qu 2522 qup_spi12_default: qup-spi12-default-state {
2580 pins = "gpio8 2523 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2581 function = "q 2524 function = "qup12";
2582 drive-strengt 2525 drive-strength = <6>;
2583 bias-disable; 2526 bias-disable;
2584 }; 2527 };
2585 2528
2586 qup_i2c13_default: qu 2529 qup_i2c13_default: qup-i2c13-default-state {
2587 pins = "gpio4 2530 pins = "gpio43", "gpio44";
2588 function = "q 2531 function = "qup13";
2589 drive-strengt 2532 drive-strength = <2>;
2590 bias-disable; 2533 bias-disable;
2591 }; 2534 };
2592 2535
2593 qup_spi13_default: qu 2536 qup_spi13_default: qup-spi13-default-state {
2594 pins = "gpio4 2537 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2595 function = "q 2538 function = "qup13";
2596 drive-strengt 2539 drive-strength = <6>;
2597 bias-disable; 2540 bias-disable;
2598 }; 2541 };
2599 2542
2600 qup_i2c14_default: qu 2543 qup_i2c14_default: qup-i2c14-default-state {
2601 pins = "gpio4 2544 pins = "gpio47", "gpio48";
2602 function = "q 2545 function = "qup14";
2603 drive-strengt 2546 drive-strength = <2>;
2604 bias-disable; 2547 bias-disable;
2605 }; 2548 };
2606 2549
2607 qup_spi14_default: qu 2550 qup_spi14_default: qup-spi14-default-state {
2608 pins = "gpio4 2551 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2609 function = "q 2552 function = "qup14";
2610 drive-strengt 2553 drive-strength = <6>;
2611 bias-disable; 2554 bias-disable;
2612 }; 2555 };
2613 2556
2614 qup_i2c15_default: qu 2557 qup_i2c15_default: qup-i2c15-default-state {
2615 pins = "gpio2 2558 pins = "gpio27", "gpio28";
2616 function = "q 2559 function = "qup15";
2617 drive-strengt 2560 drive-strength = <2>;
2618 bias-disable; 2561 bias-disable;
2619 }; 2562 };
2620 2563
2621 qup_spi15_default: qu 2564 qup_spi15_default: qup-spi15-default-state {
2622 pins = "gpio2 2565 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2623 function = "q 2566 function = "qup15";
2624 drive-strengt 2567 drive-strength = <6>;
2625 bias-disable; 2568 bias-disable;
2626 }; 2569 };
2627 2570
2628 qup_i2c16_default: qu 2571 qup_i2c16_default: qup-i2c16-default-state {
2629 pins = "gpio8 2572 pins = "gpio86", "gpio85";
2630 function = "q 2573 function = "qup16";
2631 drive-strengt 2574 drive-strength = <2>;
2632 bias-disable; 2575 bias-disable;
2633 }; 2576 };
2634 2577
2635 qup_spi16_default: qu 2578 qup_spi16_default: qup-spi16-default-state {
2636 pins = "gpio8 2579 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2637 function = "q 2580 function = "qup16";
2638 drive-strengt 2581 drive-strength = <6>;
2639 bias-disable; 2582 bias-disable;
2640 }; 2583 };
2641 2584
2642 qup_i2c17_default: qu 2585 qup_i2c17_default: qup-i2c17-default-state {
2643 pins = "gpio5 2586 pins = "gpio55", "gpio56";
2644 function = "q 2587 function = "qup17";
2645 drive-strengt 2588 drive-strength = <2>;
2646 bias-disable; 2589 bias-disable;
2647 }; 2590 };
2648 2591
2649 qup_spi17_default: qu 2592 qup_spi17_default: qup-spi17-default-state {
2650 pins = "gpio5 2593 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2651 function = "q 2594 function = "qup17";
2652 drive-strengt 2595 drive-strength = <6>;
2653 bias-disable; 2596 bias-disable;
2654 }; 2597 };
2655 2598
2656 qup_i2c18_default: qu 2599 qup_i2c18_default: qup-i2c18-default-state {
2657 pins = "gpio2 2600 pins = "gpio23", "gpio24";
2658 function = "q 2601 function = "qup18";
2659 drive-strengt 2602 drive-strength = <2>;
2660 bias-disable; 2603 bias-disable;
2661 }; 2604 };
2662 2605
2663 qup_spi18_default: qu 2606 qup_spi18_default: qup-spi18-default-state {
2664 pins = "gpio2 2607 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2665 function = "q 2608 function = "qup18";
2666 drive-strengt 2609 drive-strength = <6>;
2667 bias-disable; 2610 bias-disable;
2668 }; 2611 };
2669 2612
2670 qup_i2c19_default: qu 2613 qup_i2c19_default: qup-i2c19-default-state {
2671 pins = "gpio5 2614 pins = "gpio57", "gpio58";
2672 function = "q 2615 function = "qup19";
2673 drive-strengt 2616 drive-strength = <2>;
2674 bias-disable; 2617 bias-disable;
2675 }; 2618 };
2676 2619
2677 qup_spi19_default: qu 2620 qup_spi19_default: qup-spi19-default-state {
2678 pins = "gpio5 2621 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2679 function = "q 2622 function = "qup19";
2680 drive-strengt 2623 drive-strength = <6>;
2681 bias-disable; 2624 bias-disable;
2682 }; 2625 };
2683 2626
2684 pcie0_default_state: 2627 pcie0_default_state: pcie0-default-state {
2685 perst-pins { 2628 perst-pins {
2686 pins 2629 pins = "gpio35";
2687 funct 2630 function = "gpio";
2688 drive 2631 drive-strength = <2>;
2689 bias- 2632 bias-pull-down;
2690 }; 2633 };
2691 2634
2692 clkreq-pins { 2635 clkreq-pins {
2693 pins 2636 pins = "gpio36";
2694 funct 2637 function = "pci_e0";
2695 drive 2638 drive-strength = <2>;
2696 bias- 2639 bias-pull-up;
2697 }; 2640 };
2698 2641
2699 wake-pins { 2642 wake-pins {
2700 pins 2643 pins = "gpio37";
2701 funct 2644 function = "gpio";
2702 drive 2645 drive-strength = <2>;
2703 bias- 2646 bias-pull-up;
2704 }; 2647 };
2705 }; 2648 };
2706 2649
2707 pcie1_default_state: 2650 pcie1_default_state: pcie1-default-state {
2708 perst-pins { 2651 perst-pins {
2709 pins 2652 pins = "gpio102";
2710 funct 2653 function = "gpio";
2711 drive 2654 drive-strength = <2>;
2712 bias- 2655 bias-pull-down;
2713 }; 2656 };
2714 2657
2715 clkreq-pins { 2658 clkreq-pins {
2716 pins 2659 pins = "gpio103";
2717 funct 2660 function = "pci_e1";
2718 drive 2661 drive-strength = <2>;
2719 bias- 2662 bias-pull-up;
2720 }; 2663 };
2721 2664
2722 wake-pins { 2665 wake-pins {
2723 pins 2666 pins = "gpio104";
2724 funct 2667 function = "gpio";
2725 drive 2668 drive-strength = <2>;
2726 bias- 2669 bias-pull-up;
2727 }; 2670 };
2728 }; 2671 };
2729 }; 2672 };
2730 2673
2731 remoteproc_mpss: remoteproc@4 2674 remoteproc_mpss: remoteproc@4080000 {
2732 compatible = "qcom,sm 2675 compatible = "qcom,sm8150-mpss-pas";
2733 reg = <0x0 0x04080000 2676 reg = <0x0 0x04080000 0x0 0x4040>;
2734 2677
2735 interrupts-extended = 2678 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2736 2679 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2737 2680 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2738 2681 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2739 2682 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2740 2683 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2741 interrupt-names = "wd 2684 interrupt-names = "wdog", "fatal", "ready", "handover",
2742 "st 2685 "stop-ack", "shutdown-ack";
2743 2686
2744 clocks = <&rpmhcc RPM 2687 clocks = <&rpmhcc RPMH_CXO_CLK>;
2745 clock-names = "xo"; 2688 clock-names = "xo";
2746 2689
2747 power-domains = <&rpm 2690 power-domains = <&rpmhpd SM8150_CX>,
2748 <&rpm 2691 <&rpmhpd SM8150_MSS>;
2749 power-domain-names = 2692 power-domain-names = "cx", "mss";
2750 2693
2751 memory-region = <&mps 2694 memory-region = <&mpss_mem>;
2752 2695
2753 qcom,qmp = <&aoss_qmp 2696 qcom,qmp = <&aoss_qmp>;
2754 2697
2755 qcom,smem-states = <& 2698 qcom,smem-states = <&modem_smp2p_out 0>;
2756 qcom,smem-state-names 2699 qcom,smem-state-names = "stop";
2757 2700
2758 status = "disabled"; 2701 status = "disabled";
2759 2702
2760 glink-edge { 2703 glink-edge {
2761 interrupts = 2704 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2762 label = "mode 2705 label = "modem";
2763 qcom,remote-p 2706 qcom,remote-pid = <1>;
2764 mboxes = <&ap 2707 mboxes = <&apss_shared 12>;
2765 }; 2708 };
2766 }; 2709 };
2767 2710
2768 stm@6002000 { 2711 stm@6002000 {
2769 compatible = "arm,cor 2712 compatible = "arm,coresight-stm", "arm,primecell";
2770 reg = <0 0x06002000 0 2713 reg = <0 0x06002000 0 0x1000>,
2771 <0 0x16280000 0 2714 <0 0x16280000 0 0x180000>;
2772 reg-names = "stm-base 2715 reg-names = "stm-base", "stm-stimulus-base";
2773 2716
2774 clocks = <&aoss_qmp>; 2717 clocks = <&aoss_qmp>;
2775 clock-names = "apb_pc 2718 clock-names = "apb_pclk";
2776 2719
2777 out-ports { 2720 out-ports {
2778 port { 2721 port {
2779 stm_o 2722 stm_out: endpoint {
2780 2723 remote-endpoint = <&funnel0_in7>;
2781 }; 2724 };
2782 }; 2725 };
2783 }; 2726 };
2784 }; 2727 };
2785 2728
2786 funnel@6041000 { 2729 funnel@6041000 {
2787 compatible = "arm,cor 2730 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2788 reg = <0 0x06041000 0 2731 reg = <0 0x06041000 0 0x1000>;
2789 2732
2790 clocks = <&aoss_qmp>; 2733 clocks = <&aoss_qmp>;
2791 clock-names = "apb_pc 2734 clock-names = "apb_pclk";
2792 2735
2793 out-ports { 2736 out-ports {
2794 port { 2737 port {
2795 funne 2738 funnel0_out: endpoint {
2796 2739 remote-endpoint = <&merge_funnel_in0>;
2797 }; 2740 };
2798 }; 2741 };
2799 }; 2742 };
2800 2743
2801 in-ports { 2744 in-ports {
2802 #address-cell 2745 #address-cells = <1>;
2803 #size-cells = 2746 #size-cells = <0>;
2804 2747
2805 port@7 { 2748 port@7 {
2806 reg = 2749 reg = <7>;
2807 funne 2750 funnel0_in7: endpoint {
2808 2751 remote-endpoint = <&stm_out>;
2809 }; 2752 };
2810 }; 2753 };
2811 }; 2754 };
2812 }; 2755 };
2813 2756
2814 funnel@6042000 { 2757 funnel@6042000 {
2815 compatible = "arm,cor 2758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2816 reg = <0 0x06042000 0 2759 reg = <0 0x06042000 0 0x1000>;
2817 2760
2818 clocks = <&aoss_qmp>; 2761 clocks = <&aoss_qmp>;
2819 clock-names = "apb_pc 2762 clock-names = "apb_pclk";
2820 2763
2821 out-ports { 2764 out-ports {
2822 port { 2765 port {
2823 funne 2766 funnel1_out: endpoint {
2824 2767 remote-endpoint = <&merge_funnel_in1>;
2825 }; 2768 };
2826 }; 2769 };
2827 }; 2770 };
2828 2771
2829 in-ports { 2772 in-ports {
2830 #address-cell 2773 #address-cells = <1>;
2831 #size-cells = 2774 #size-cells = <0>;
2832 2775
2833 port@4 { 2776 port@4 {
2834 reg = 2777 reg = <4>;
2835 funne 2778 funnel1_in4: endpoint {
2836 2779 remote-endpoint = <&swao_replicator_out>;
2837 }; 2780 };
2838 }; 2781 };
2839 }; 2782 };
2840 }; 2783 };
2841 2784
2842 funnel@6043000 { 2785 funnel@6043000 {
2843 compatible = "arm,cor 2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2844 reg = <0 0x06043000 0 2787 reg = <0 0x06043000 0 0x1000>;
2845 2788
2846 clocks = <&aoss_qmp>; 2789 clocks = <&aoss_qmp>;
2847 clock-names = "apb_pc 2790 clock-names = "apb_pclk";
2848 2791
2849 out-ports { 2792 out-ports {
2850 port { 2793 port {
2851 funne 2794 funnel2_out: endpoint {
2852 2795 remote-endpoint = <&merge_funnel_in2>;
2853 }; 2796 };
2854 }; 2797 };
2855 }; 2798 };
2856 2799
2857 in-ports { 2800 in-ports {
2858 #address-cell 2801 #address-cells = <1>;
2859 #size-cells = 2802 #size-cells = <0>;
2860 2803
2861 port@2 { 2804 port@2 {
2862 reg = 2805 reg = <2>;
2863 funne 2806 funnel2_in2: endpoint {
2864 2807 remote-endpoint = <&apss_merge_funnel_out>;
2865 }; 2808 };
2866 }; 2809 };
2867 }; 2810 };
2868 }; 2811 };
2869 2812
2870 funnel@6045000 { 2813 funnel@6045000 {
2871 compatible = "arm,cor 2814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2872 reg = <0 0x06045000 0 2815 reg = <0 0x06045000 0 0x1000>;
2873 2816
2874 clocks = <&aoss_qmp>; 2817 clocks = <&aoss_qmp>;
2875 clock-names = "apb_pc 2818 clock-names = "apb_pclk";
2876 2819
2877 out-ports { 2820 out-ports {
2878 port { 2821 port {
2879 merge 2822 merge_funnel_out: endpoint {
2880 2823 remote-endpoint = <&etf_in>;
2881 }; 2824 };
2882 }; 2825 };
2883 }; 2826 };
2884 2827
2885 in-ports { 2828 in-ports {
2886 #address-cell 2829 #address-cells = <1>;
2887 #size-cells = 2830 #size-cells = <0>;
2888 2831
2889 port@0 { 2832 port@0 {
2890 reg = 2833 reg = <0>;
2891 merge 2834 merge_funnel_in0: endpoint {
2892 2835 remote-endpoint = <&funnel0_out>;
2893 }; 2836 };
2894 }; 2837 };
2895 2838
2896 port@1 { 2839 port@1 {
2897 reg = 2840 reg = <1>;
2898 merge 2841 merge_funnel_in1: endpoint {
2899 2842 remote-endpoint = <&funnel1_out>;
2900 }; 2843 };
2901 }; 2844 };
2902 2845
2903 port@2 { 2846 port@2 {
2904 reg = 2847 reg = <2>;
2905 merge 2848 merge_funnel_in2: endpoint {
2906 2849 remote-endpoint = <&funnel2_out>;
2907 }; 2850 };
2908 }; 2851 };
2909 }; 2852 };
2910 }; 2853 };
2911 2854
2912 replicator@6046000 { 2855 replicator@6046000 {
2913 compatible = "arm,cor 2856 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2914 reg = <0 0x06046000 0 2857 reg = <0 0x06046000 0 0x1000>;
2915 2858
2916 clocks = <&aoss_qmp>; 2859 clocks = <&aoss_qmp>;
2917 clock-names = "apb_pc 2860 clock-names = "apb_pclk";
2918 2861
2919 out-ports { 2862 out-ports {
2920 #address-cell 2863 #address-cells = <1>;
2921 #size-cells = 2864 #size-cells = <0>;
2922 2865
2923 port@0 { 2866 port@0 {
2924 reg = 2867 reg = <0>;
2925 repli 2868 replicator_out0: endpoint {
2926 2869 remote-endpoint = <&etr_in>;
2927 }; 2870 };
2928 }; 2871 };
2929 2872
2930 port@1 { 2873 port@1 {
2931 reg = 2874 reg = <1>;
2932 repli 2875 replicator_out1: endpoint {
2933 2876 remote-endpoint = <&replicator1_in>;
2934 }; 2877 };
2935 }; 2878 };
2936 }; 2879 };
2937 2880
2938 in-ports { 2881 in-ports {
2939 port { 2882 port {
2940 repli 2883 replicator_in0: endpoint {
2941 2884 remote-endpoint = <&etf_out>;
2942 }; 2885 };
2943 }; 2886 };
2944 }; 2887 };
2945 }; 2888 };
2946 2889
2947 etf@6047000 { 2890 etf@6047000 {
2948 compatible = "arm,cor 2891 compatible = "arm,coresight-tmc", "arm,primecell";
2949 reg = <0 0x06047000 0 2892 reg = <0 0x06047000 0 0x1000>;
2950 2893
2951 clocks = <&aoss_qmp>; 2894 clocks = <&aoss_qmp>;
2952 clock-names = "apb_pc 2895 clock-names = "apb_pclk";
2953 2896
2954 out-ports { 2897 out-ports {
2955 port { 2898 port {
2956 etf_o 2899 etf_out: endpoint {
2957 2900 remote-endpoint = <&replicator_in0>;
2958 }; 2901 };
2959 }; 2902 };
2960 }; 2903 };
2961 2904
2962 in-ports { 2905 in-ports {
2963 port { 2906 port {
2964 etf_i 2907 etf_in: endpoint {
2965 2908 remote-endpoint = <&merge_funnel_out>;
2966 }; 2909 };
2967 }; 2910 };
2968 }; 2911 };
2969 }; 2912 };
2970 2913
2971 etr@6048000 { 2914 etr@6048000 {
2972 compatible = "arm,cor 2915 compatible = "arm,coresight-tmc", "arm,primecell";
2973 reg = <0 0x06048000 0 2916 reg = <0 0x06048000 0 0x1000>;
2974 iommus = <&apps_smmu 2917 iommus = <&apps_smmu 0x05e0 0x0>;
2975 2918
2976 clocks = <&aoss_qmp>; 2919 clocks = <&aoss_qmp>;
2977 clock-names = "apb_pc 2920 clock-names = "apb_pclk";
2978 arm,scatter-gather; 2921 arm,scatter-gather;
2979 2922
2980 in-ports { 2923 in-ports {
2981 port { 2924 port {
2982 etr_i 2925 etr_in: endpoint {
2983 2926 remote-endpoint = <&replicator_out0>;
2984 }; 2927 };
2985 }; 2928 };
2986 }; 2929 };
2987 }; 2930 };
2988 2931
2989 replicator@604a000 { 2932 replicator@604a000 {
2990 compatible = "arm,cor 2933 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2991 reg = <0 0x0604a000 0 2934 reg = <0 0x0604a000 0 0x1000>;
2992 2935
2993 clocks = <&aoss_qmp>; 2936 clocks = <&aoss_qmp>;
2994 clock-names = "apb_pc 2937 clock-names = "apb_pclk";
2995 2938
2996 out-ports { 2939 out-ports {
2997 #address-cell 2940 #address-cells = <1>;
2998 #size-cells = 2941 #size-cells = <0>;
2999 2942
3000 port@1 { 2943 port@1 {
3001 reg = 2944 reg = <1>;
3002 repli 2945 replicator1_out: endpoint {
3003 2946 remote-endpoint = <&swao_funnel_in>;
3004 }; 2947 };
3005 }; 2948 };
3006 }; 2949 };
3007 2950
3008 in-ports { 2951 in-ports {
3009 2952
3010 port { 2953 port {
3011 repli 2954 replicator1_in: endpoint {
3012 2955 remote-endpoint = <&replicator_out1>;
3013 }; 2956 };
3014 }; 2957 };
3015 }; 2958 };
3016 }; 2959 };
3017 2960
3018 funnel@6b08000 { 2961 funnel@6b08000 {
3019 compatible = "arm,cor 2962 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3020 reg = <0 0x06b08000 0 2963 reg = <0 0x06b08000 0 0x1000>;
3021 2964
3022 clocks = <&aoss_qmp>; 2965 clocks = <&aoss_qmp>;
3023 clock-names = "apb_pc 2966 clock-names = "apb_pclk";
3024 2967
3025 out-ports { 2968 out-ports {
3026 port { 2969 port {
3027 swao_ 2970 swao_funnel_out: endpoint {
3028 2971 remote-endpoint = <&swao_etf_in>;
3029 }; 2972 };
3030 }; 2973 };
3031 }; 2974 };
3032 2975
3033 in-ports { 2976 in-ports {
3034 #address-cell 2977 #address-cells = <1>;
3035 #size-cells = 2978 #size-cells = <0>;
3036 2979
3037 port@6 { 2980 port@6 {
3038 reg = 2981 reg = <6>;
3039 swao_ 2982 swao_funnel_in: endpoint {
3040 2983 remote-endpoint = <&replicator1_out>;
3041 }; 2984 };
3042 }; 2985 };
3043 }; 2986 };
3044 }; 2987 };
3045 2988
3046 etf@6b09000 { 2989 etf@6b09000 {
3047 compatible = "arm,cor 2990 compatible = "arm,coresight-tmc", "arm,primecell";
3048 reg = <0 0x06b09000 0 2991 reg = <0 0x06b09000 0 0x1000>;
3049 2992
3050 clocks = <&aoss_qmp>; 2993 clocks = <&aoss_qmp>;
3051 clock-names = "apb_pc 2994 clock-names = "apb_pclk";
3052 2995
3053 out-ports { 2996 out-ports {
3054 port { 2997 port {
3055 swao_ 2998 swao_etf_out: endpoint {
3056 2999 remote-endpoint = <&swao_replicator_in>;
3057 }; 3000 };
3058 }; 3001 };
3059 }; 3002 };
3060 3003
3061 in-ports { 3004 in-ports {
3062 port { 3005 port {
3063 swao_ 3006 swao_etf_in: endpoint {
3064 3007 remote-endpoint = <&swao_funnel_out>;
3065 }; 3008 };
3066 }; 3009 };
3067 }; 3010 };
3068 }; 3011 };
3069 3012
3070 replicator@6b0a000 { 3013 replicator@6b0a000 {
3071 compatible = "arm,cor 3014 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3072 reg = <0 0x06b0a000 0 3015 reg = <0 0x06b0a000 0 0x1000>;
3073 3016
3074 clocks = <&aoss_qmp>; 3017 clocks = <&aoss_qmp>;
3075 clock-names = "apb_pc 3018 clock-names = "apb_pclk";
3076 qcom,replicator-loses 3019 qcom,replicator-loses-context;
3077 3020
3078 out-ports { 3021 out-ports {
3079 port { 3022 port {
3080 swao_ 3023 swao_replicator_out: endpoint {
3081 3024 remote-endpoint = <&funnel1_in4>;
3082 }; 3025 };
3083 }; 3026 };
3084 }; 3027 };
3085 3028
3086 in-ports { 3029 in-ports {
3087 port { 3030 port {
3088 swao_ 3031 swao_replicator_in: endpoint {
3089 3032 remote-endpoint = <&swao_etf_out>;
3090 }; 3033 };
3091 }; 3034 };
3092 }; 3035 };
3093 }; 3036 };
3094 3037
3095 etm@7040000 { 3038 etm@7040000 {
3096 compatible = "arm,cor 3039 compatible = "arm,coresight-etm4x", "arm,primecell";
3097 reg = <0 0x07040000 0 3040 reg = <0 0x07040000 0 0x1000>;
3098 3041
3099 cpu = <&CPU0>; 3042 cpu = <&CPU0>;
3100 3043
3101 clocks = <&aoss_qmp>; 3044 clocks = <&aoss_qmp>;
3102 clock-names = "apb_pc 3045 clock-names = "apb_pclk";
3103 arm,coresight-loses-c 3046 arm,coresight-loses-context-with-cpu;
3104 qcom,skip-power-up; 3047 qcom,skip-power-up;
3105 3048
3106 out-ports { 3049 out-ports {
3107 port { 3050 port {
3108 etm0_ 3051 etm0_out: endpoint {
3109 3052 remote-endpoint = <&apss_funnel_in0>;
3110 }; 3053 };
3111 }; 3054 };
3112 }; 3055 };
3113 }; 3056 };
3114 3057
3115 etm@7140000 { 3058 etm@7140000 {
3116 compatible = "arm,cor 3059 compatible = "arm,coresight-etm4x", "arm,primecell";
3117 reg = <0 0x07140000 0 3060 reg = <0 0x07140000 0 0x1000>;
3118 3061
3119 cpu = <&CPU1>; 3062 cpu = <&CPU1>;
3120 3063
3121 clocks = <&aoss_qmp>; 3064 clocks = <&aoss_qmp>;
3122 clock-names = "apb_pc 3065 clock-names = "apb_pclk";
3123 arm,coresight-loses-c 3066 arm,coresight-loses-context-with-cpu;
3124 qcom,skip-power-up; 3067 qcom,skip-power-up;
3125 3068
3126 out-ports { 3069 out-ports {
3127 port { 3070 port {
3128 etm1_ 3071 etm1_out: endpoint {
3129 3072 remote-endpoint = <&apss_funnel_in1>;
3130 }; 3073 };
3131 }; 3074 };
3132 }; 3075 };
3133 }; 3076 };
3134 3077
3135 etm@7240000 { 3078 etm@7240000 {
3136 compatible = "arm,cor 3079 compatible = "arm,coresight-etm4x", "arm,primecell";
3137 reg = <0 0x07240000 0 3080 reg = <0 0x07240000 0 0x1000>;
3138 3081
3139 cpu = <&CPU2>; 3082 cpu = <&CPU2>;
3140 3083
3141 clocks = <&aoss_qmp>; 3084 clocks = <&aoss_qmp>;
3142 clock-names = "apb_pc 3085 clock-names = "apb_pclk";
3143 arm,coresight-loses-c 3086 arm,coresight-loses-context-with-cpu;
3144 qcom,skip-power-up; 3087 qcom,skip-power-up;
3145 3088
3146 out-ports { 3089 out-ports {
3147 port { 3090 port {
3148 etm2_ 3091 etm2_out: endpoint {
3149 3092 remote-endpoint = <&apss_funnel_in2>;
3150 }; 3093 };
3151 }; 3094 };
3152 }; 3095 };
3153 }; 3096 };
3154 3097
3155 etm@7340000 { 3098 etm@7340000 {
3156 compatible = "arm,cor 3099 compatible = "arm,coresight-etm4x", "arm,primecell";
3157 reg = <0 0x07340000 0 3100 reg = <0 0x07340000 0 0x1000>;
3158 3101
3159 cpu = <&CPU3>; 3102 cpu = <&CPU3>;
3160 3103
3161 clocks = <&aoss_qmp>; 3104 clocks = <&aoss_qmp>;
3162 clock-names = "apb_pc 3105 clock-names = "apb_pclk";
3163 arm,coresight-loses-c 3106 arm,coresight-loses-context-with-cpu;
3164 qcom,skip-power-up; 3107 qcom,skip-power-up;
3165 3108
3166 out-ports { 3109 out-ports {
3167 port { 3110 port {
3168 etm3_ 3111 etm3_out: endpoint {
3169 3112 remote-endpoint = <&apss_funnel_in3>;
3170 }; 3113 };
3171 }; 3114 };
3172 }; 3115 };
3173 }; 3116 };
3174 3117
3175 etm@7440000 { 3118 etm@7440000 {
3176 compatible = "arm,cor 3119 compatible = "arm,coresight-etm4x", "arm,primecell";
3177 reg = <0 0x07440000 0 3120 reg = <0 0x07440000 0 0x1000>;
3178 3121
3179 cpu = <&CPU4>; 3122 cpu = <&CPU4>;
3180 3123
3181 clocks = <&aoss_qmp>; 3124 clocks = <&aoss_qmp>;
3182 clock-names = "apb_pc 3125 clock-names = "apb_pclk";
3183 arm,coresight-loses-c 3126 arm,coresight-loses-context-with-cpu;
3184 qcom,skip-power-up; 3127 qcom,skip-power-up;
3185 3128
3186 out-ports { 3129 out-ports {
3187 port { 3130 port {
3188 etm4_ 3131 etm4_out: endpoint {
3189 3132 remote-endpoint = <&apss_funnel_in4>;
3190 }; 3133 };
3191 }; 3134 };
3192 }; 3135 };
3193 }; 3136 };
3194 3137
3195 etm@7540000 { 3138 etm@7540000 {
3196 compatible = "arm,cor 3139 compatible = "arm,coresight-etm4x", "arm,primecell";
3197 reg = <0 0x07540000 0 3140 reg = <0 0x07540000 0 0x1000>;
3198 3141
3199 cpu = <&CPU5>; 3142 cpu = <&CPU5>;
3200 3143
3201 clocks = <&aoss_qmp>; 3144 clocks = <&aoss_qmp>;
3202 clock-names = "apb_pc 3145 clock-names = "apb_pclk";
3203 arm,coresight-loses-c 3146 arm,coresight-loses-context-with-cpu;
3204 qcom,skip-power-up; 3147 qcom,skip-power-up;
3205 3148
3206 out-ports { 3149 out-ports {
3207 port { 3150 port {
3208 etm5_ 3151 etm5_out: endpoint {
3209 3152 remote-endpoint = <&apss_funnel_in5>;
3210 }; 3153 };
3211 }; 3154 };
3212 }; 3155 };
3213 }; 3156 };
3214 3157
3215 etm@7640000 { 3158 etm@7640000 {
3216 compatible = "arm,cor 3159 compatible = "arm,coresight-etm4x", "arm,primecell";
3217 reg = <0 0x07640000 0 3160 reg = <0 0x07640000 0 0x1000>;
3218 3161
3219 cpu = <&CPU6>; 3162 cpu = <&CPU6>;
3220 3163
3221 clocks = <&aoss_qmp>; 3164 clocks = <&aoss_qmp>;
3222 clock-names = "apb_pc 3165 clock-names = "apb_pclk";
3223 arm,coresight-loses-c 3166 arm,coresight-loses-context-with-cpu;
3224 qcom,skip-power-up; 3167 qcom,skip-power-up;
3225 3168
3226 out-ports { 3169 out-ports {
3227 port { 3170 port {
3228 etm6_ 3171 etm6_out: endpoint {
3229 3172 remote-endpoint = <&apss_funnel_in6>;
3230 }; 3173 };
3231 }; 3174 };
3232 }; 3175 };
3233 }; 3176 };
3234 3177
3235 etm@7740000 { 3178 etm@7740000 {
3236 compatible = "arm,cor 3179 compatible = "arm,coresight-etm4x", "arm,primecell";
3237 reg = <0 0x07740000 0 3180 reg = <0 0x07740000 0 0x1000>;
3238 3181
3239 cpu = <&CPU7>; 3182 cpu = <&CPU7>;
3240 3183
3241 clocks = <&aoss_qmp>; 3184 clocks = <&aoss_qmp>;
3242 clock-names = "apb_pc 3185 clock-names = "apb_pclk";
3243 arm,coresight-loses-c 3186 arm,coresight-loses-context-with-cpu;
3244 qcom,skip-power-up; 3187 qcom,skip-power-up;
3245 3188
3246 out-ports { 3189 out-ports {
3247 port { 3190 port {
3248 etm7_ 3191 etm7_out: endpoint {
3249 3192 remote-endpoint = <&apss_funnel_in7>;
3250 }; 3193 };
3251 }; 3194 };
3252 }; 3195 };
3253 }; 3196 };
3254 3197
3255 funnel@7800000 { /* APSS Funn 3198 funnel@7800000 { /* APSS Funnel */
3256 compatible = "arm,cor 3199 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3257 reg = <0 0x07800000 0 3200 reg = <0 0x07800000 0 0x1000>;
3258 3201
3259 clocks = <&aoss_qmp>; 3202 clocks = <&aoss_qmp>;
3260 clock-names = "apb_pc 3203 clock-names = "apb_pclk";
3261 3204
3262 out-ports { 3205 out-ports {
3263 port { 3206 port {
3264 apss_ 3207 apss_funnel_out: endpoint {
3265 3208 remote-endpoint = <&apss_merge_funnel_in>;
3266 }; 3209 };
3267 }; 3210 };
3268 }; 3211 };
3269 3212
3270 in-ports { 3213 in-ports {
3271 #address-cell 3214 #address-cells = <1>;
3272 #size-cells = 3215 #size-cells = <0>;
3273 3216
3274 port@0 { 3217 port@0 {
3275 reg = 3218 reg = <0>;
3276 apss_ 3219 apss_funnel_in0: endpoint {
3277 3220 remote-endpoint = <&etm0_out>;
3278 }; 3221 };
3279 }; 3222 };
3280 3223
3281 port@1 { 3224 port@1 {
3282 reg = 3225 reg = <1>;
3283 apss_ 3226 apss_funnel_in1: endpoint {
3284 3227 remote-endpoint = <&etm1_out>;
3285 }; 3228 };
3286 }; 3229 };
3287 3230
3288 port@2 { 3231 port@2 {
3289 reg = 3232 reg = <2>;
3290 apss_ 3233 apss_funnel_in2: endpoint {
3291 3234 remote-endpoint = <&etm2_out>;
3292 }; 3235 };
3293 }; 3236 };
3294 3237
3295 port@3 { 3238 port@3 {
3296 reg = 3239 reg = <3>;
3297 apss_ 3240 apss_funnel_in3: endpoint {
3298 3241 remote-endpoint = <&etm3_out>;
3299 }; 3242 };
3300 }; 3243 };
3301 3244
3302 port@4 { 3245 port@4 {
3303 reg = 3246 reg = <4>;
3304 apss_ 3247 apss_funnel_in4: endpoint {
3305 3248 remote-endpoint = <&etm4_out>;
3306 }; 3249 };
3307 }; 3250 };
3308 3251
3309 port@5 { 3252 port@5 {
3310 reg = 3253 reg = <5>;
3311 apss_ 3254 apss_funnel_in5: endpoint {
3312 3255 remote-endpoint = <&etm5_out>;
3313 }; 3256 };
3314 }; 3257 };
3315 3258
3316 port@6 { 3259 port@6 {
3317 reg = 3260 reg = <6>;
3318 apss_ 3261 apss_funnel_in6: endpoint {
3319 3262 remote-endpoint = <&etm6_out>;
3320 }; 3263 };
3321 }; 3264 };
3322 3265
3323 port@7 { 3266 port@7 {
3324 reg = 3267 reg = <7>;
3325 apss_ 3268 apss_funnel_in7: endpoint {
3326 3269 remote-endpoint = <&etm7_out>;
3327 }; 3270 };
3328 }; 3271 };
3329 }; 3272 };
3330 }; 3273 };
3331 3274
3332 funnel@7810000 { 3275 funnel@7810000 {
3333 compatible = "arm,cor 3276 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3334 reg = <0 0x07810000 0 3277 reg = <0 0x07810000 0 0x1000>;
3335 3278
3336 clocks = <&aoss_qmp>; 3279 clocks = <&aoss_qmp>;
3337 clock-names = "apb_pc 3280 clock-names = "apb_pclk";
3338 3281
3339 out-ports { 3282 out-ports {
3340 port { 3283 port {
3341 apss_ 3284 apss_merge_funnel_out: endpoint {
3342 3285 remote-endpoint = <&funnel2_in2>;
3343 }; 3286 };
3344 }; 3287 };
3345 }; 3288 };
3346 3289
3347 in-ports { 3290 in-ports {
3348 port { 3291 port {
3349 apss_ 3292 apss_merge_funnel_in: endpoint {
3350 3293 remote-endpoint = <&apss_funnel_out>;
3351 }; 3294 };
3352 }; 3295 };
3353 }; 3296 };
3354 }; 3297 };
3355 3298
3356 remoteproc_cdsp: remoteproc@8 3299 remoteproc_cdsp: remoteproc@8300000 {
3357 compatible = "qcom,sm 3300 compatible = "qcom,sm8150-cdsp-pas";
3358 reg = <0x0 0x08300000 3301 reg = <0x0 0x08300000 0x0 0x4040>;
3359 3302
3360 interrupts-extended = 3303 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3361 3304 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3362 3305 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3363 3306 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3364 3307 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3365 interrupt-names = "wd 3308 interrupt-names = "wdog", "fatal", "ready",
3366 "ha 3309 "handover", "stop-ack";
3367 3310
3368 clocks = <&rpmhcc RPM 3311 clocks = <&rpmhcc RPMH_CXO_CLK>;
3369 clock-names = "xo"; 3312 clock-names = "xo";
3370 3313
3371 power-domains = <&rpm 3314 power-domains = <&rpmhpd SM8150_CX>;
3372 3315
3373 memory-region = <&cds 3316 memory-region = <&cdsp_mem>;
3374 3317
3375 qcom,qmp = <&aoss_qmp 3318 qcom,qmp = <&aoss_qmp>;
3376 3319
3377 qcom,smem-states = <& 3320 qcom,smem-states = <&cdsp_smp2p_out 0>;
3378 qcom,smem-state-names 3321 qcom,smem-state-names = "stop";
3379 3322
3380 status = "disabled"; 3323 status = "disabled";
3381 3324
3382 glink-edge { 3325 glink-edge {
3383 interrupts = 3326 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3384 label = "cdsp 3327 label = "cdsp";
3385 qcom,remote-p 3328 qcom,remote-pid = <5>;
3386 mboxes = <&ap 3329 mboxes = <&apss_shared 4>;
3387 3330
3388 fastrpc { 3331 fastrpc {
3389 compa 3332 compatible = "qcom,fastrpc";
3390 qcom, 3333 qcom,glink-channels = "fastrpcglink-apps-dsp";
3391 label 3334 label = "cdsp";
3392 qcom, 3335 qcom,non-secure-domain;
3393 #addr 3336 #address-cells = <1>;
3394 #size 3337 #size-cells = <0>;
3395 3338
3396 compu 3339 compute-cb@1 {
3397 3340 compatible = "qcom,fastrpc-compute-cb";
3398 3341 reg = <1>;
3399 3342 iommus = <&apps_smmu 0x1001 0x0460>;
3400 }; 3343 };
3401 3344
3402 compu 3345 compute-cb@2 {
3403 3346 compatible = "qcom,fastrpc-compute-cb";
3404 3347 reg = <2>;
3405 3348 iommus = <&apps_smmu 0x1002 0x0460>;
3406 }; 3349 };
3407 3350
3408 compu 3351 compute-cb@3 {
3409 3352 compatible = "qcom,fastrpc-compute-cb";
3410 3353 reg = <3>;
3411 3354 iommus = <&apps_smmu 0x1003 0x0460>;
3412 }; 3355 };
3413 3356
3414 compu 3357 compute-cb@4 {
3415 3358 compatible = "qcom,fastrpc-compute-cb";
3416 3359 reg = <4>;
3417 3360 iommus = <&apps_smmu 0x1004 0x0460>;
3418 }; 3361 };
3419 3362
3420 compu 3363 compute-cb@5 {
3421 3364 compatible = "qcom,fastrpc-compute-cb";
3422 3365 reg = <5>;
3423 3366 iommus = <&apps_smmu 0x1005 0x0460>;
3424 }; 3367 };
3425 3368
3426 compu 3369 compute-cb@6 {
3427 3370 compatible = "qcom,fastrpc-compute-cb";
3428 3371 reg = <6>;
3429 3372 iommus = <&apps_smmu 0x1006 0x0460>;
3430 }; 3373 };
3431 3374
3432 compu 3375 compute-cb@7 {
3433 3376 compatible = "qcom,fastrpc-compute-cb";
3434 3377 reg = <7>;
3435 3378 iommus = <&apps_smmu 0x1007 0x0460>;
3436 }; 3379 };
3437 3380
3438 compu 3381 compute-cb@8 {
3439 3382 compatible = "qcom,fastrpc-compute-cb";
3440 3383 reg = <8>;
3441 3384 iommus = <&apps_smmu 0x1008 0x0460>;
3442 }; 3385 };
3443 3386
3444 /* no 3387 /* note: secure cb9 in downstream */
3445 }; 3388 };
3446 }; 3389 };
3447 }; 3390 };
3448 3391
3449 usb_1_hsphy: phy@88e2000 { 3392 usb_1_hsphy: phy@88e2000 {
3450 compatible = "qcom,sm 3393 compatible = "qcom,sm8150-usb-hs-phy",
3451 "qcom,us 3394 "qcom,usb-snps-hs-7nm-phy";
3452 reg = <0 0x088e2000 0 3395 reg = <0 0x088e2000 0 0x400>;
3453 status = "disabled"; 3396 status = "disabled";
3454 #phy-cells = <0>; 3397 #phy-cells = <0>;
3455 3398
3456 clocks = <&rpmhcc RPM 3399 clocks = <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ref"; 3400 clock-names = "ref";
3458 3401
3459 resets = <&gcc GCC_QU 3402 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3460 }; 3403 };
3461 3404
3462 usb_2_hsphy: phy@88e3000 { 3405 usb_2_hsphy: phy@88e3000 {
3463 compatible = "qcom,sm 3406 compatible = "qcom,sm8150-usb-hs-phy",
3464 "qcom,us 3407 "qcom,usb-snps-hs-7nm-phy";
3465 reg = <0 0x088e3000 0 3408 reg = <0 0x088e3000 0 0x400>;
3466 status = "disabled"; 3409 status = "disabled";
3467 #phy-cells = <0>; 3410 #phy-cells = <0>;
3468 3411
3469 clocks = <&rpmhcc RPM 3412 clocks = <&rpmhcc RPMH_CXO_CLK>;
3470 clock-names = "ref"; 3413 clock-names = "ref";
3471 3414
3472 resets = <&gcc GCC_QU 3415 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3473 }; 3416 };
3474 3417
3475 usb_1_qmpphy: phy@88e8000 { 3418 usb_1_qmpphy: phy@88e8000 {
3476 compatible = "qcom,sm 3419 compatible = "qcom,sm8150-qmp-usb3-dp-phy";
3477 reg = <0 0x088e8000 0 3420 reg = <0 0x088e8000 0 0x3000>;
3478 3421
3479 clocks = <&gcc GCC_US 3422 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3480 <&gcc GCC_US 3423 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3481 <&gcc GCC_US 3424 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3482 <&gcc GCC_US 3425 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3483 clock-names = "aux", 3426 clock-names = "aux",
3484 "ref", 3427 "ref",
3485 "com_au 3428 "com_aux",
3486 "usb3_p 3429 "usb3_pipe";
3487 3430
3488 resets = <&gcc GCC_US 3431 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3489 <&gcc GCC_US 3432 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3490 reset-names = "phy", 3433 reset-names = "phy", "common";
3491 3434
3492 #clock-cells = <1>; 3435 #clock-cells = <1>;
3493 #phy-cells = <1>; 3436 #phy-cells = <1>;
3494 3437
3495 status = "disabled"; 3438 status = "disabled";
3496 3439
3497 ports { 3440 ports {
3498 #address-cell 3441 #address-cells = <1>;
3499 #size-cells = 3442 #size-cells = <0>;
3500 3443
3501 port@0 { 3444 port@0 {
3502 reg = 3445 reg = <0>;
3503 3446
3504 usb_1 3447 usb_1_qmpphy_out: endpoint {
3505 }; 3448 };
3506 }; 3449 };
3507 3450
3508 port@1 { 3451 port@1 {
3509 reg = 3452 reg = <1>;
3510 3453
3511 usb_1 3454 usb_1_qmpphy_usb_ss_in: endpoint {
3512 <<
3513 }; 3455 };
3514 }; 3456 };
3515 3457
3516 port@2 { 3458 port@2 {
3517 reg = 3459 reg = <2>;
3518 3460
3519 usb_1 3461 usb_1_qmpphy_dp_in: endpoint {
3520 <<
3521 }; 3462 };
3522 }; 3463 };
3523 }; 3464 };
3524 }; 3465 };
3525 3466
3526 usb_2_qmpphy: phy@88eb000 { 3467 usb_2_qmpphy: phy@88eb000 {
3527 compatible = "qcom,sm 3468 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3528 reg = <0 0x088eb000 0 3469 reg = <0 0x088eb000 0 0x1000>;
3529 3470
3530 clocks = <&gcc GCC_US 3471 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3531 <&gcc GCC_US 3472 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3532 <&gcc GCC_US 3473 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3533 <&gcc GCC_US 3474 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3534 clock-names = "aux", 3475 clock-names = "aux",
3535 "ref", 3476 "ref",
3536 "com_au 3477 "com_aux",
3537 "pipe"; 3478 "pipe";
3538 clock-output-names = 3479 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3539 #clock-cells = <0>; 3480 #clock-cells = <0>;
3540 #phy-cells = <0>; 3481 #phy-cells = <0>;
3541 3482
3542 resets = <&gcc GCC_US 3483 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3543 <&gcc GCC_US 3484 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
3544 reset-names = "phy", 3485 reset-names = "phy",
3545 "phy_ph 3486 "phy_phy";
3546 3487
3547 status = "disabled"; 3488 status = "disabled";
3548 }; 3489 };
3549 3490
3550 sdhc_2: mmc@8804000 { 3491 sdhc_2: mmc@8804000 {
3551 compatible = "qcom,sm 3492 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3552 reg = <0 0x08804000 0 3493 reg = <0 0x08804000 0 0x1000>;
3553 3494
3554 interrupts = <GIC_SPI 3495 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 3496 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3556 interrupt-names = "hc 3497 interrupt-names = "hc_irq", "pwr_irq";
3557 3498
3558 clocks = <&gcc GCC_SD 3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3559 <&gcc GCC_SD 3500 <&gcc GCC_SDCC2_APPS_CLK>,
3560 <&rpmhcc RPM 3501 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface" 3502 clock-names = "iface", "core", "xo";
3562 iommus = <&apps_smmu 3503 iommus = <&apps_smmu 0x6a0 0x0>;
3563 qcom,dll-config = <0x 3504 qcom,dll-config = <0x0007642c>;
3564 qcom,ddr-config = <0x 3505 qcom,ddr-config = <0x80040868>;
3565 power-domains = <&rpm 3506 power-domains = <&rpmhpd 0>;
3566 operating-points-v2 = 3507 operating-points-v2 = <&sdhc2_opp_table>;
3567 3508
3568 status = "disabled"; 3509 status = "disabled";
3569 3510
3570 sdhc2_opp_table: opp- 3511 sdhc2_opp_table: opp-table {
3571 compatible = 3512 compatible = "operating-points-v2";
3572 3513
3573 opp-19200000 3514 opp-19200000 {
3574 opp-h 3515 opp-hz = /bits/ 64 <19200000>;
3575 requi 3516 required-opps = <&rpmhpd_opp_min_svs>;
3576 }; 3517 };
3577 3518
3578 opp-50000000 3519 opp-50000000 {
3579 opp-h 3520 opp-hz = /bits/ 64 <50000000>;
3580 requi 3521 required-opps = <&rpmhpd_opp_low_svs>;
3581 }; 3522 };
3582 3523
3583 opp-100000000 3524 opp-100000000 {
3584 opp-h 3525 opp-hz = /bits/ 64 <100000000>;
3585 requi 3526 required-opps = <&rpmhpd_opp_svs>;
3586 }; 3527 };
3587 3528
3588 opp-202000000 3529 opp-202000000 {
3589 opp-h 3530 opp-hz = /bits/ 64 <202000000>;
3590 requi 3531 required-opps = <&rpmhpd_opp_svs_l1>;
3591 }; 3532 };
3592 }; 3533 };
3593 }; 3534 };
3594 3535
3595 dc_noc: interconnect@9160000 3536 dc_noc: interconnect@9160000 {
3596 compatible = "qcom,sm 3537 compatible = "qcom,sm8150-dc-noc";
3597 reg = <0 0x09160000 0 3538 reg = <0 0x09160000 0 0x3200>;
3598 #interconnect-cells = 3539 #interconnect-cells = <2>;
3599 qcom,bcm-voters = <&a 3540 qcom,bcm-voters = <&apps_bcm_voter>;
3600 }; 3541 };
3601 3542
3602 gem_noc: interconnect@9680000 3543 gem_noc: interconnect@9680000 {
3603 compatible = "qcom,sm 3544 compatible = "qcom,sm8150-gem-noc";
3604 reg = <0 0x09680000 0 3545 reg = <0 0x09680000 0 0x3e200>;
3605 #interconnect-cells = 3546 #interconnect-cells = <2>;
3606 qcom,bcm-voters = <&a 3547 qcom,bcm-voters = <&apps_bcm_voter>;
3607 }; 3548 };
3608 3549
3609 usb_1: usb@a6f8800 { 3550 usb_1: usb@a6f8800 {
3610 compatible = "qcom,sm 3551 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3611 reg = <0 0x0a6f8800 0 3552 reg = <0 0x0a6f8800 0 0x400>;
3612 status = "disabled"; 3553 status = "disabled";
3613 #address-cells = <2>; 3554 #address-cells = <2>;
3614 #size-cells = <2>; 3555 #size-cells = <2>;
3615 ranges; 3556 ranges;
3616 dma-ranges; 3557 dma-ranges;
3617 3558
3618 clocks = <&gcc GCC_CF 3559 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3619 <&gcc GCC_US 3560 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3620 <&gcc GCC_AG 3561 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3621 <&gcc GCC_US 3562 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3622 <&gcc GCC_US 3563 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3623 <&gcc GCC_US 3564 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3624 clock-names = "cfg_no 3565 clock-names = "cfg_noc",
3625 "core", 3566 "core",
3626 "iface" 3567 "iface",
3627 "sleep" 3568 "sleep",
3628 "mock_u 3569 "mock_utmi",
3629 "xo"; 3570 "xo";
3630 3571
3631 assigned-clocks = <&g 3572 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3632 <&g 3573 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3633 assigned-clock-rates 3574 assigned-clock-rates = <19200000>, <200000000>;
3634 3575
3635 interrupts-extended = !! 3576 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3636 !! 3577 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3637 <<
3638 3578 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
3639 !! 3579 <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
3640 interrupt-names = "pw !! 3580 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3641 "hs !! 3581 "dm_hs_phy_irq", "dp_hs_phy_irq";
3642 "dp <<
3643 "dm <<
3644 "ss <<
3645 3582
3646 power-domains = <&gcc 3583 power-domains = <&gcc USB30_PRIM_GDSC>;
3647 3584
3648 resets = <&gcc GCC_US 3585 resets = <&gcc GCC_USB30_PRIM_BCR>;
3649 3586
3650 interconnects = <&agg 3587 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
3651 <&gem 3588 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
3652 interconnect-names = 3589 interconnect-names = "usb-ddr", "apps-usb";
3653 3590
3654 usb_1_dwc3: usb@a6000 3591 usb_1_dwc3: usb@a600000 {
3655 compatible = 3592 compatible = "snps,dwc3";
3656 reg = <0 0x0a 3593 reg = <0 0x0a600000 0 0xcd00>;
3657 interrupts = 3594 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3658 iommus = <&ap 3595 iommus = <&apps_smmu 0x140 0>;
3659 snps,dis_u2_s 3596 snps,dis_u2_susphy_quirk;
3660 snps,dis_enbl 3597 snps,dis_enblslpm_quirk;
3661 phys = <&usb_ 3598 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3662 phy-names = " 3599 phy-names = "usb2-phy", "usb3-phy";
3663 3600
3664 ports { 3601 ports {
3665 #addr 3602 #address-cells = <1>;
3666 #size 3603 #size-cells = <0>;
3667 3604
3668 port@ 3605 port@0 {
3669 3606 reg = <0>;
3670 3607
3671 3608 usb_1_dwc3_hs: endpoint {
3672 3609 };
3673 }; 3610 };
3674 3611
3675 port@ 3612 port@1 {
3676 3613 reg = <1>;
3677 3614
3678 3615 usb_1_dwc3_ss: endpoint {
3679 <<
3680 3616 };
3681 }; 3617 };
3682 }; 3618 };
3683 }; 3619 };
3684 }; 3620 };
3685 3621
3686 usb_2: usb@a8f8800 { 3622 usb_2: usb@a8f8800 {
3687 compatible = "qcom,sm 3623 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3688 reg = <0 0x0a8f8800 0 3624 reg = <0 0x0a8f8800 0 0x400>;
3689 status = "disabled"; 3625 status = "disabled";
3690 #address-cells = <2>; 3626 #address-cells = <2>;
3691 #size-cells = <2>; 3627 #size-cells = <2>;
3692 ranges; 3628 ranges;
3693 dma-ranges; 3629 dma-ranges;
3694 3630
3695 clocks = <&gcc GCC_CF 3631 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3696 <&gcc GCC_US 3632 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3697 <&gcc GCC_AG 3633 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3698 <&gcc GCC_US 3634 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3699 <&gcc GCC_US 3635 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3700 <&gcc GCC_US 3636 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3701 clock-names = "cfg_no 3637 clock-names = "cfg_noc",
3702 "core", 3638 "core",
3703 "iface" 3639 "iface",
3704 "sleep" 3640 "sleep",
3705 "mock_u 3641 "mock_utmi",
3706 "xo"; 3642 "xo";
3707 3643
3708 assigned-clocks = <&g 3644 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3709 <&g 3645 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3710 assigned-clock-rates 3646 assigned-clock-rates = <19200000>, <200000000>;
3711 3647
3712 interrupts-extended = !! 3648 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3713 !! 3649 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
3714 <<
3715 3650 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
3716 !! 3651 <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
3717 interrupt-names = "pw !! 3652 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3718 "hs !! 3653 "dm_hs_phy_irq", "dp_hs_phy_irq";
3719 "dp <<
3720 "dm <<
3721 "ss <<
3722 3654
3723 power-domains = <&gcc 3655 power-domains = <&gcc USB30_SEC_GDSC>;
3724 3656
3725 resets = <&gcc GCC_US 3657 resets = <&gcc GCC_USB30_SEC_BCR>;
3726 3658
3727 interconnects = <&agg 3659 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
3728 <&gem 3660 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
3729 interconnect-names = 3661 interconnect-names = "usb-ddr", "apps-usb";
3730 3662
3731 usb_2_dwc3: usb@a8000 3663 usb_2_dwc3: usb@a800000 {
3732 compatible = 3664 compatible = "snps,dwc3";
3733 reg = <0 0x0a 3665 reg = <0 0x0a800000 0 0xcd00>;
3734 interrupts = 3666 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3735 iommus = <&ap 3667 iommus = <&apps_smmu 0x160 0>;
3736 snps,dis_u2_s 3668 snps,dis_u2_susphy_quirk;
3737 snps,dis_enbl 3669 snps,dis_enblslpm_quirk;
3738 phys = <&usb_ 3670 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>;
3739 phy-names = " 3671 phy-names = "usb2-phy", "usb3-phy";
3740 }; 3672 };
3741 }; 3673 };
3742 3674
3743 videocc: clock-controller@ab0 <<
3744 compatible = "qcom,sm <<
3745 reg = <0 0x0ab00000 0 <<
3746 clocks = <&gcc GCC_VI <<
3747 <&rpmhcc RPM <<
3748 clock-names = "iface" <<
3749 power-domains = <&rpm <<
3750 required-opps = <&rpm <<
3751 #clock-cells = <1>; <<
3752 #reset-cells = <1>; <<
3753 #power-domain-cells = <<
3754 }; <<
3755 <<
3756 camnoc_virt: interconnect@ac0 3675 camnoc_virt: interconnect@ac00000 {
3757 compatible = "qcom,sm 3676 compatible = "qcom,sm8150-camnoc-virt";
3758 reg = <0 0x0ac00000 0 3677 reg = <0 0x0ac00000 0 0x1000>;
3759 #interconnect-cells = 3678 #interconnect-cells = <2>;
3760 qcom,bcm-voters = <&a 3679 qcom,bcm-voters = <&apps_bcm_voter>;
3761 }; 3680 };
3762 3681
3763 camcc: clock-controller@ad000 <<
3764 compatible = "qcom,sm <<
3765 reg = <0 0x0ad00000 0 <<
3766 clocks = <&rpmhcc RPM <<
3767 <&gcc GCC_CA <<
3768 power-domains = <&rpm <<
3769 required-opps = <&rpm <<
3770 #clock-cells = <1>; <<
3771 #reset-cells = <1>; <<
3772 #power-domain-cells = <<
3773 }; <<
3774 <<
3775 mdss: display-subsystem@ae000 3682 mdss: display-subsystem@ae00000 {
3776 compatible = "qcom,sm 3683 compatible = "qcom,sm8150-mdss";
3777 reg = <0 0x0ae00000 0 3684 reg = <0 0x0ae00000 0 0x1000>;
3778 reg-names = "mdss"; 3685 reg-names = "mdss";
3779 3686
3780 interconnects = <&mms 3687 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
3781 <&mms 3688 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
3782 interconnect-names = 3689 interconnect-names = "mdp0-mem", "mdp1-mem";
3783 3690
3784 power-domains = <&dis 3691 power-domains = <&dispcc MDSS_GDSC>;
3785 3692
3786 clocks = <&dispcc DIS 3693 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3787 <&gcc GCC_DI 3694 <&gcc GCC_DISP_HF_AXI_CLK>,
3788 <&gcc GCC_DI 3695 <&gcc GCC_DISP_SF_AXI_CLK>,
3789 <&dispcc DIS 3696 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3790 clock-names = "iface" 3697 clock-names = "iface", "bus", "nrt_bus", "core";
3791 3698
3792 interrupts = <GIC_SPI 3699 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3793 interrupt-controller; 3700 interrupt-controller;
3794 #interrupt-cells = <1 3701 #interrupt-cells = <1>;
3795 3702
3796 iommus = <&apps_smmu 3703 iommus = <&apps_smmu 0x800 0x420>;
3797 3704
3798 status = "disabled"; 3705 status = "disabled";
3799 3706
3800 #address-cells = <2>; 3707 #address-cells = <2>;
3801 #size-cells = <2>; 3708 #size-cells = <2>;
3802 ranges; 3709 ranges;
3803 3710
3804 mdss_mdp: display-con 3711 mdss_mdp: display-controller@ae01000 {
3805 compatible = 3712 compatible = "qcom,sm8150-dpu";
3806 reg = <0 0x0a 3713 reg = <0 0x0ae01000 0 0x8f000>,
3807 <0 0x0a 3714 <0 0x0aeb0000 0 0x2008>;
3808 reg-names = " 3715 reg-names = "mdp", "vbif";
3809 3716
3810 clocks = <&di 3717 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3811 <&gc 3718 <&gcc GCC_DISP_HF_AXI_CLK>,
3812 <&di 3719 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3813 <&di 3720 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3814 clock-names = 3721 clock-names = "iface", "bus", "core", "vsync";
3815 3722
3816 assigned-cloc 3723 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3817 assigned-cloc 3724 assigned-clock-rates = <19200000>;
3818 3725
3819 operating-poi 3726 operating-points-v2 = <&mdp_opp_table>;
3820 power-domains 3727 power-domains = <&rpmhpd SM8150_MMCX>;
3821 3728
3822 interrupt-par 3729 interrupt-parent = <&mdss>;
3823 interrupts = 3730 interrupts = <0>;
3824 3731
3825 ports { 3732 ports {
3826 #addr 3733 #address-cells = <1>;
3827 #size 3734 #size-cells = <0>;
3828 3735
3829 port@ 3736 port@0 {
3830 3737 reg = <0>;
3831 3738 dpu_intf1_out: endpoint {
3832 3739 remote-endpoint = <&mdss_dsi0_in>;
3833 3740 };
3834 }; 3741 };
3835 3742
3836 port@ 3743 port@1 {
3837 3744 reg = <1>;
3838 3745 dpu_intf2_out: endpoint {
3839 3746 remote-endpoint = <&mdss_dsi1_in>;
3840 3747 };
3841 }; 3748 };
3842 3749
3843 port@ 3750 port@2 {
3844 3751 reg = <2>;
3845 3752 dpu_intf0_out: endpoint {
3846 3753 remote-endpoint = <&mdss_dp_in>;
3847 3754 };
3848 }; 3755 };
3849 }; 3756 };
3850 3757
3851 mdp_opp_table 3758 mdp_opp_table: opp-table {
3852 compa 3759 compatible = "operating-points-v2";
3853 3760
3854 opp-1 3761 opp-171428571 {
3855 3762 opp-hz = /bits/ 64 <171428571>;
3856 3763 required-opps = <&rpmhpd_opp_low_svs>;
3857 }; 3764 };
3858 3765
3859 opp-3 3766 opp-300000000 {
3860 3767 opp-hz = /bits/ 64 <300000000>;
3861 3768 required-opps = <&rpmhpd_opp_svs>;
3862 }; 3769 };
3863 3770
3864 opp-3 3771 opp-345000000 {
3865 3772 opp-hz = /bits/ 64 <345000000>;
3866 3773 required-opps = <&rpmhpd_opp_svs_l1>;
3867 }; 3774 };
3868 3775
3869 opp-4 3776 opp-460000000 {
3870 3777 opp-hz = /bits/ 64 <460000000>;
3871 3778 required-opps = <&rpmhpd_opp_nom>;
3872 }; 3779 };
3873 }; 3780 };
3874 }; 3781 };
3875 3782
3876 mdss_dp: displayport- 3783 mdss_dp: displayport-controller@ae90000 {
3877 compatible = 3784 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp";
3878 reg = <0 0xae 3785 reg = <0 0xae90000 0 0x200>,
3879 <0 0xae 3786 <0 0xae90200 0 0x200>,
3880 <0 0xae 3787 <0 0xae90400 0 0x600>,
3881 <0 0x0a 3788 <0 0x0ae90a00 0 0x600>,
3882 <0 0x0a 3789 <0 0x0ae91000 0 0x600>;
3883 3790
3884 interrupt-par 3791 interrupt-parent = <&mdss>;
3885 interrupts = 3792 interrupts = <12>;
3886 clocks = <&di 3793 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3887 <&di 3794 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3888 <&di 3795 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3889 <&di 3796 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3890 <&di 3797 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3891 clock-names = 3798 clock-names = "core_iface",
3892 3799 "core_aux",
3893 3800 "ctrl_link",
3894 3801 "ctrl_link_iface",
3895 3802 "stream_pixel";
3896 3803
3897 assigned-cloc 3804 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3898 3805 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3899 assigned-cloc 3806 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3900 3807 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3901 3808
3902 phys = <&usb_ 3809 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3903 phy-names = " 3810 phy-names = "dp";
3904 3811
3905 #sound-dai-ce 3812 #sound-dai-cells = <0>;
3906 3813
3907 operating-poi 3814 operating-points-v2 = <&dp_opp_table>;
3908 power-domains 3815 power-domains = <&rpmhpd SM8250_MMCX>;
3909 3816
3910 status = "dis 3817 status = "disabled";
3911 3818
3912 ports { 3819 ports {
3913 #addr 3820 #address-cells = <1>;
3914 #size 3821 #size-cells = <0>;
3915 3822
3916 port@ 3823 port@0 {
3917 3824 reg = <0>;
3918 3825 mdss_dp_in: endpoint {
3919 3826 remote-endpoint = <&dpu_intf0_out>;
3920 3827 };
3921 }; 3828 };
3922 3829
3923 port@ 3830 port@1 {
3924 3831 reg = <1>;
3925 3832
3926 3833 mdss_dp_out: endpoint {
3927 <<
3928 3834 };
3929 }; 3835 };
3930 }; 3836 };
3931 3837
3932 dp_opp_table: 3838 dp_opp_table: opp-table {
3933 compa 3839 compatible = "operating-points-v2";
3934 3840
3935 opp-1 3841 opp-160000000 {
3936 3842 opp-hz = /bits/ 64 <160000000>;
3937 3843 required-opps = <&rpmhpd_opp_low_svs>;
3938 }; 3844 };
3939 3845
3940 opp-2 3846 opp-270000000 {
3941 3847 opp-hz = /bits/ 64 <270000000>;
3942 3848 required-opps = <&rpmhpd_opp_svs>;
3943 }; 3849 };
3944 3850
3945 opp-5 3851 opp-540000000 {
3946 3852 opp-hz = /bits/ 64 <540000000>;
3947 3853 required-opps = <&rpmhpd_opp_svs_l1>;
3948 }; 3854 };
3949 3855
3950 opp-8 3856 opp-810000000 {
3951 3857 opp-hz = /bits/ 64 <810000000>;
3952 3858 required-opps = <&rpmhpd_opp_nom>;
3953 }; 3859 };
3954 }; 3860 };
3955 }; 3861 };
3956 3862
3957 mdss_dsi0: dsi@ae9400 3863 mdss_dsi0: dsi@ae94000 {
3958 compatible = 3864 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3959 reg = <0 0x0a 3865 reg = <0 0x0ae94000 0 0x400>;
3960 reg-names = " 3866 reg-names = "dsi_ctrl";
3961 3867
3962 interrupt-par 3868 interrupt-parent = <&mdss>;
3963 interrupts = 3869 interrupts = <4>;
3964 3870
3965 clocks = <&di 3871 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3966 <&di 3872 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3967 <&di 3873 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3968 <&di 3874 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3969 <&di 3875 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3970 <&gc 3876 <&gcc GCC_DISP_HF_AXI_CLK>;
3971 clock-names = 3877 clock-names = "byte",
3972 3878 "byte_intf",
3973 3879 "pixel",
3974 3880 "core",
3975 3881 "iface",
3976 3882 "bus";
3977 3883
3978 assigned-cloc 3884 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3979 3885 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3980 assigned-cloc 3886 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3981 3887 <&mdss_dsi0_phy 1>;
3982 3888
3983 operating-poi 3889 operating-points-v2 = <&dsi_opp_table>;
3984 power-domains 3890 power-domains = <&rpmhpd SM8150_MMCX>;
3985 3891
3986 phys = <&mdss 3892 phys = <&mdss_dsi0_phy>;
3987 3893
3988 status = "dis 3894 status = "disabled";
3989 3895
3990 #address-cell 3896 #address-cells = <1>;
3991 #size-cells = 3897 #size-cells = <0>;
3992 3898
3993 ports { 3899 ports {
3994 #addr 3900 #address-cells = <1>;
3995 #size 3901 #size-cells = <0>;
3996 3902
3997 port@ 3903 port@0 {
3998 3904 reg = <0>;
3999 3905 mdss_dsi0_in: endpoint {
4000 3906 remote-endpoint = <&dpu_intf1_out>;
4001 3907 };
4002 }; 3908 };
4003 3909
4004 port@ 3910 port@1 {
4005 3911 reg = <1>;
4006 3912 mdss_dsi0_out: endpoint {
4007 3913 };
4008 }; 3914 };
4009 }; 3915 };
4010 3916
4011 dsi_opp_table 3917 dsi_opp_table: opp-table {
4012 compa 3918 compatible = "operating-points-v2";
4013 3919
4014 opp-1 3920 opp-187500000 {
4015 3921 opp-hz = /bits/ 64 <187500000>;
4016 3922 required-opps = <&rpmhpd_opp_low_svs>;
4017 }; 3923 };
4018 3924
4019 opp-3 3925 opp-300000000 {
4020 3926 opp-hz = /bits/ 64 <300000000>;
4021 3927 required-opps = <&rpmhpd_opp_svs>;
4022 }; 3928 };
4023 3929
4024 opp-3 3930 opp-358000000 {
4025 3931 opp-hz = /bits/ 64 <358000000>;
4026 3932 required-opps = <&rpmhpd_opp_svs_l1>;
4027 }; 3933 };
4028 }; 3934 };
4029 }; 3935 };
4030 3936
4031 mdss_dsi0_phy: phy@ae 3937 mdss_dsi0_phy: phy@ae94400 {
4032 compatible = 3938 compatible = "qcom,dsi-phy-7nm-8150";
4033 reg = <0 0x0a 3939 reg = <0 0x0ae94400 0 0x200>,
4034 <0 0x0a 3940 <0 0x0ae94600 0 0x280>,
4035 <0 0x0a 3941 <0 0x0ae94900 0 0x260>;
4036 reg-names = " 3942 reg-names = "dsi_phy",
4037 " 3943 "dsi_phy_lane",
4038 " 3944 "dsi_pll";
4039 3945
4040 #clock-cells 3946 #clock-cells = <1>;
4041 #phy-cells = 3947 #phy-cells = <0>;
4042 3948
4043 clocks = <&di 3949 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4044 <&rp 3950 <&rpmhcc RPMH_CXO_CLK>;
4045 clock-names = 3951 clock-names = "iface", "ref";
4046 3952
4047 status = "dis 3953 status = "disabled";
4048 }; 3954 };
4049 3955
4050 mdss_dsi1: dsi@ae9600 3956 mdss_dsi1: dsi@ae96000 {
4051 compatible = 3957 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
4052 reg = <0 0x0a 3958 reg = <0 0x0ae96000 0 0x400>;
4053 reg-names = " 3959 reg-names = "dsi_ctrl";
4054 3960
4055 interrupt-par 3961 interrupt-parent = <&mdss>;
4056 interrupts = 3962 interrupts = <5>;
4057 3963
4058 clocks = <&di 3964 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4059 <&di 3965 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4060 <&di 3966 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4061 <&di 3967 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4062 <&di 3968 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4063 <&gc 3969 <&gcc GCC_DISP_HF_AXI_CLK>;
4064 clock-names = 3970 clock-names = "byte",
4065 3971 "byte_intf",
4066 3972 "pixel",
4067 3973 "core",
4068 3974 "iface",
4069 3975 "bus";
4070 3976
4071 assigned-cloc 3977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
4072 3978 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4073 assigned-cloc 3979 assigned-clock-parents = <&mdss_dsi1_phy 0>,
4074 3980 <&mdss_dsi1_phy 1>;
4075 3981
4076 operating-poi 3982 operating-points-v2 = <&dsi_opp_table>;
4077 power-domains 3983 power-domains = <&rpmhpd SM8150_MMCX>;
4078 3984
4079 phys = <&mdss 3985 phys = <&mdss_dsi1_phy>;
4080 3986
4081 status = "dis 3987 status = "disabled";
4082 3988
4083 #address-cell 3989 #address-cells = <1>;
4084 #size-cells = 3990 #size-cells = <0>;
4085 3991
4086 ports { 3992 ports {
4087 #addr 3993 #address-cells = <1>;
4088 #size 3994 #size-cells = <0>;
4089 3995
4090 port@ 3996 port@0 {
4091 3997 reg = <0>;
4092 3998 mdss_dsi1_in: endpoint {
4093 3999 remote-endpoint = <&dpu_intf2_out>;
4094 4000 };
4095 }; 4001 };
4096 4002
4097 port@ 4003 port@1 {
4098 4004 reg = <1>;
4099 4005 mdss_dsi1_out: endpoint {
4100 4006 };
4101 }; 4007 };
4102 }; 4008 };
4103 }; 4009 };
4104 4010
4105 mdss_dsi1_phy: phy@ae 4011 mdss_dsi1_phy: phy@ae96400 {
4106 compatible = 4012 compatible = "qcom,dsi-phy-7nm-8150";
4107 reg = <0 0x0a 4013 reg = <0 0x0ae96400 0 0x200>,
4108 <0 0x0a 4014 <0 0x0ae96600 0 0x280>,
4109 <0 0x0a 4015 <0 0x0ae96900 0 0x260>;
4110 reg-names = " 4016 reg-names = "dsi_phy",
4111 " 4017 "dsi_phy_lane",
4112 " 4018 "dsi_pll";
4113 4019
4114 #clock-cells 4020 #clock-cells = <1>;
4115 #phy-cells = 4021 #phy-cells = <0>;
4116 4022
4117 clocks = <&di 4023 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4118 <&rp 4024 <&rpmhcc RPMH_CXO_CLK>;
4119 clock-names = 4025 clock-names = "iface", "ref";
4120 4026
4121 status = "dis 4027 status = "disabled";
4122 }; 4028 };
4123 }; 4029 };
4124 4030
4125 dispcc: clock-controller@af00 4031 dispcc: clock-controller@af00000 {
4126 compatible = "qcom,sm 4032 compatible = "qcom,sm8150-dispcc";
4127 reg = <0 0x0af00000 0 4033 reg = <0 0x0af00000 0 0x10000>;
4128 clocks = <&rpmhcc RPM 4034 clocks = <&rpmhcc RPMH_CXO_CLK>,
4129 <&mdss_dsi0_ 4035 <&mdss_dsi0_phy 0>,
4130 <&mdss_dsi0_ 4036 <&mdss_dsi0_phy 1>,
4131 <&mdss_dsi1_ 4037 <&mdss_dsi1_phy 0>,
4132 <&mdss_dsi1_ 4038 <&mdss_dsi1_phy 1>,
4133 <&usb_1_qmpp 4039 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4134 <&usb_1_qmpp 4040 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4135 clock-names = "bi_tcx 4041 clock-names = "bi_tcxo",
4136 "dsi0_p 4042 "dsi0_phy_pll_out_byteclk",
4137 "dsi0_p 4043 "dsi0_phy_pll_out_dsiclk",
4138 "dsi1_p 4044 "dsi1_phy_pll_out_byteclk",
4139 "dsi1_p 4045 "dsi1_phy_pll_out_dsiclk",
4140 "dp_phy 4046 "dp_phy_pll_link_clk",
4141 "dp_phy 4047 "dp_phy_pll_vco_div_clk";
4142 power-domains = <&rpm 4048 power-domains = <&rpmhpd SM8150_MMCX>;
4143 required-opps = <&rpm 4049 required-opps = <&rpmhpd_opp_low_svs>;
4144 #clock-cells = <1>; 4050 #clock-cells = <1>;
4145 #reset-cells = <1>; 4051 #reset-cells = <1>;
4146 #power-domain-cells = 4052 #power-domain-cells = <1>;
4147 }; 4053 };
4148 4054
4149 pdc: interrupt-controller@b22 4055 pdc: interrupt-controller@b220000 {
4150 compatible = "qcom,sm 4056 compatible = "qcom,sm8150-pdc", "qcom,pdc";
4151 reg = <0 0x0b220000 0 4057 reg = <0 0x0b220000 0 0x30000>;
4152 qcom,pdc-ranges = <0 4058 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4153 <12 4059 <125 63 1>;
4154 #interrupt-cells = <2 4060 #interrupt-cells = <2>;
4155 interrupt-parent = <& 4061 interrupt-parent = <&intc>;
4156 interrupt-controller; 4062 interrupt-controller;
4157 }; 4063 };
4158 4064
4159 aoss_qmp: power-management@c3 4065 aoss_qmp: power-management@c300000 {
4160 compatible = "qcom,sm 4066 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
4161 reg = <0x0 0x0c300000 4067 reg = <0x0 0x0c300000 0x0 0x400>;
4162 interrupts = <GIC_SPI 4068 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
4163 mboxes = <&apss_share 4069 mboxes = <&apss_shared 0>;
4164 4070
4165 #clock-cells = <0>; 4071 #clock-cells = <0>;
4166 }; 4072 };
4167 4073
4168 sram@c3f0000 { 4074 sram@c3f0000 {
4169 compatible = "qcom,rp 4075 compatible = "qcom,rpmh-stats";
4170 reg = <0 0x0c3f0000 0 4076 reg = <0 0x0c3f0000 0 0x400>;
4171 }; 4077 };
4172 4078
4173 tsens0: thermal-sensor@c26300 4079 tsens0: thermal-sensor@c263000 {
4174 compatible = "qcom,sm 4080 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4175 reg = <0 0x0c263000 0 4081 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4176 <0 0x0c222000 0 4082 <0 0x0c222000 0 0x1ff>; /* SROT */
4177 #qcom,sensors = <16>; 4083 #qcom,sensors = <16>;
4178 interrupts = <GIC_SPI 4084 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4179 <GIC_SPI 4085 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4180 interrupt-names = "up 4086 interrupt-names = "uplow", "critical";
4181 #thermal-sensor-cells 4087 #thermal-sensor-cells = <1>;
4182 }; 4088 };
4183 4089
4184 tsens1: thermal-sensor@c26500 4090 tsens1: thermal-sensor@c265000 {
4185 compatible = "qcom,sm 4091 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4186 reg = <0 0x0c265000 0 4092 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4187 <0 0x0c223000 0 4093 <0 0x0c223000 0 0x1ff>; /* SROT */
4188 #qcom,sensors = <8>; 4094 #qcom,sensors = <8>;
4189 interrupts = <GIC_SPI 4095 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4190 <GIC_SPI 4096 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4191 interrupt-names = "up 4097 interrupt-names = "uplow", "critical";
4192 #thermal-sensor-cells 4098 #thermal-sensor-cells = <1>;
4193 }; 4099 };
4194 4100
4195 spmi_bus: spmi@c440000 { 4101 spmi_bus: spmi@c440000 {
4196 compatible = "qcom,sp 4102 compatible = "qcom,spmi-pmic-arb";
4197 reg = <0x0 0x0c440000 4103 reg = <0x0 0x0c440000 0x0 0x0001100>,
4198 <0x0 0x0c600000 4104 <0x0 0x0c600000 0x0 0x2000000>,
4199 <0x0 0x0e600000 4105 <0x0 0x0e600000 0x0 0x0100000>,
4200 <0x0 0x0e700000 4106 <0x0 0x0e700000 0x0 0x00a0000>,
4201 <0x0 0x0c40a000 4107 <0x0 0x0c40a000 0x0 0x0026000>;
4202 reg-names = "core", " 4108 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4203 interrupt-names = "pe 4109 interrupt-names = "periph_irq";
4204 interrupts = <GIC_SPI 4110 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
4205 qcom,ee = <0>; 4111 qcom,ee = <0>;
4206 qcom,channel = <0>; 4112 qcom,channel = <0>;
4207 #address-cells = <2>; 4113 #address-cells = <2>;
4208 #size-cells = <0>; 4114 #size-cells = <0>;
4209 interrupt-controller; 4115 interrupt-controller;
4210 #interrupt-cells = <4 4116 #interrupt-cells = <4>;
4211 }; 4117 };
4212 4118
4213 apps_smmu: iommu@15000000 { 4119 apps_smmu: iommu@15000000 {
4214 compatible = "qcom,sm 4120 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4215 reg = <0 0x15000000 0 4121 reg = <0 0x15000000 0 0x100000>;
4216 #iommu-cells = <2>; 4122 #iommu-cells = <2>;
4217 #global-interrupts = 4123 #global-interrupts = <1>;
4218 interrupts = <GIC_SPI 4124 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4219 <GIC_SPI 4125 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4220 <GIC_SPI 4126 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4221 <GIC_SPI 4127 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4222 <GIC_SPI 4128 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4223 <GIC_SPI 4129 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4224 <GIC_SPI 4130 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4225 <GIC_SPI 4131 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4226 <GIC_SPI 4132 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4227 <GIC_SPI 4133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4228 <GIC_SPI 4134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4229 <GIC_SPI 4135 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4230 <GIC_SPI 4136 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4231 <GIC_SPI 4137 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4232 <GIC_SPI 4138 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4233 <GIC_SPI 4139 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4234 <GIC_SPI 4140 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4235 <GIC_SPI 4141 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4236 <GIC_SPI 4142 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4237 <GIC_SPI 4143 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4238 <GIC_SPI 4144 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4239 <GIC_SPI 4145 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4240 <GIC_SPI 4146 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4241 <GIC_SPI 4147 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4242 <GIC_SPI 4148 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4243 <GIC_SPI 4149 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4244 <GIC_SPI 4150 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4245 <GIC_SPI 4151 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4246 <GIC_SPI 4152 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4247 <GIC_SPI 4153 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4248 <GIC_SPI 4154 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4249 <GIC_SPI 4155 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4250 <GIC_SPI 4156 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4251 <GIC_SPI 4157 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4252 <GIC_SPI 4158 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4253 <GIC_SPI 4159 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4254 <GIC_SPI 4160 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4255 <GIC_SPI 4161 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4256 <GIC_SPI 4162 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4257 <GIC_SPI 4163 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4258 <GIC_SPI 4164 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4259 <GIC_SPI 4165 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4260 <GIC_SPI 4166 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4261 <GIC_SPI 4167 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4262 <GIC_SPI 4168 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4263 <GIC_SPI 4169 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4264 <GIC_SPI 4170 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4265 <GIC_SPI 4171 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4266 <GIC_SPI 4172 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4267 <GIC_SPI 4173 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4268 <GIC_SPI 4174 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4269 <GIC_SPI 4175 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4270 <GIC_SPI 4176 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4271 <GIC_SPI 4177 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4272 <GIC_SPI 4178 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4273 <GIC_SPI 4179 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4274 <GIC_SPI 4180 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4275 <GIC_SPI 4181 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4276 <GIC_SPI 4182 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4277 <GIC_SPI 4183 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4278 <GIC_SPI 4184 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4279 <GIC_SPI 4185 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4280 <GIC_SPI 4186 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4281 <GIC_SPI 4187 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4282 <GIC_SPI 4188 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4283 <GIC_SPI 4189 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4284 <GIC_SPI 4190 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4285 <GIC_SPI 4191 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4286 <GIC_SPI 4192 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4287 <GIC_SPI 4193 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4288 <GIC_SPI 4194 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4289 <GIC_SPI 4195 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4290 <GIC_SPI 4196 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4291 <GIC_SPI 4197 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4292 <GIC_SPI 4198 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4293 <GIC_SPI 4199 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4294 <GIC_SPI 4200 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4295 <GIC_SPI 4201 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4296 <GIC_SPI 4202 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4297 <GIC_SPI 4203 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4298 <GIC_SPI 4204 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
4299 }; 4205 };
4300 4206
4301 remoteproc_adsp: remoteproc@1 4207 remoteproc_adsp: remoteproc@17300000 {
4302 compatible = "qcom,sm 4208 compatible = "qcom,sm8150-adsp-pas";
4303 reg = <0x0 0x17300000 4209 reg = <0x0 0x17300000 0x0 0x4040>;
4304 4210
4305 interrupts-extended = 4211 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4306 4212 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
4307 4213 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4308 4214 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
4309 4215 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
4310 interrupt-names = "wd 4216 interrupt-names = "wdog", "fatal", "ready",
4311 "ha 4217 "handover", "stop-ack";
4312 4218
4313 clocks = <&rpmhcc RPM 4219 clocks = <&rpmhcc RPMH_CXO_CLK>;
4314 clock-names = "xo"; 4220 clock-names = "xo";
4315 4221
4316 power-domains = <&rpm 4222 power-domains = <&rpmhpd SM8150_CX>;
4317 4223
4318 memory-region = <&ads 4224 memory-region = <&adsp_mem>;
4319 4225
4320 qcom,qmp = <&aoss_qmp 4226 qcom,qmp = <&aoss_qmp>;
4321 4227
4322 qcom,smem-states = <& 4228 qcom,smem-states = <&adsp_smp2p_out 0>;
4323 qcom,smem-state-names 4229 qcom,smem-state-names = "stop";
4324 4230
4325 status = "disabled"; 4231 status = "disabled";
4326 4232
4327 glink-edge { 4233 glink-edge {
4328 interrupts = 4234 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
4329 label = "lpas 4235 label = "lpass";
4330 qcom,remote-p 4236 qcom,remote-pid = <2>;
4331 mboxes = <&ap 4237 mboxes = <&apss_shared 8>;
4332 4238
4333 fastrpc { 4239 fastrpc {
4334 compa 4240 compatible = "qcom,fastrpc";
4335 qcom, 4241 qcom,glink-channels = "fastrpcglink-apps-dsp";
4336 label 4242 label = "adsp";
4337 qcom, 4243 qcom,non-secure-domain;
4338 #addr 4244 #address-cells = <1>;
4339 #size 4245 #size-cells = <0>;
4340 4246
4341 compu 4247 compute-cb@3 {
4342 4248 compatible = "qcom,fastrpc-compute-cb";
4343 4249 reg = <3>;
4344 4250 iommus = <&apps_smmu 0x1b23 0x0>;
4345 }; 4251 };
4346 4252
4347 compu 4253 compute-cb@4 {
4348 4254 compatible = "qcom,fastrpc-compute-cb";
4349 4255 reg = <4>;
4350 4256 iommus = <&apps_smmu 0x1b24 0x0>;
4351 }; 4257 };
4352 4258
4353 compu 4259 compute-cb@5 {
4354 4260 compatible = "qcom,fastrpc-compute-cb";
4355 4261 reg = <5>;
4356 4262 iommus = <&apps_smmu 0x1b25 0x0>;
4357 }; 4263 };
4358 }; 4264 };
4359 }; 4265 };
4360 }; 4266 };
4361 4267
4362 intc: interrupt-controller@17 4268 intc: interrupt-controller@17a00000 {
4363 compatible = "arm,gic 4269 compatible = "arm,gic-v3";
4364 interrupt-controller; 4270 interrupt-controller;
4365 #interrupt-cells = <3 4271 #interrupt-cells = <3>;
4366 reg = <0x0 0x17a00000 4272 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
4367 <0x0 0x17a60000 4273 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
4368 interrupts = <GIC_PPI 4274 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4369 }; 4275 };
4370 4276
4371 apss_shared: mailbox@17c00000 4277 apss_shared: mailbox@17c00000 {
4372 compatible = "qcom,sm 4278 compatible = "qcom,sm8150-apss-shared",
4373 "qcom,sd 4279 "qcom,sdm845-apss-shared";
4374 reg = <0x0 0x17c00000 4280 reg = <0x0 0x17c00000 0x0 0x1000>;
4375 #mbox-cells = <1>; 4281 #mbox-cells = <1>;
4376 }; 4282 };
4377 4283
4378 watchdog@17c10000 { 4284 watchdog@17c10000 {
4379 compatible = "qcom,ap 4285 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4380 reg = <0 0x17c10000 0 4286 reg = <0 0x17c10000 0 0x1000>;
4381 clocks = <&sleep_clk> 4287 clocks = <&sleep_clk>;
4382 interrupts = <GIC_SPI 4288 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4383 }; 4289 };
4384 4290
4385 timer@17c20000 { 4291 timer@17c20000 {
4386 #address-cells = <1>; 4292 #address-cells = <1>;
4387 #size-cells = <1>; 4293 #size-cells = <1>;
4388 ranges = <0 0 0 0x200 4294 ranges = <0 0 0 0x20000000>;
4389 compatible = "arm,arm 4295 compatible = "arm,armv7-timer-mem";
4390 reg = <0x0 0x17c20000 4296 reg = <0x0 0x17c20000 0x0 0x1000>;
4391 clock-frequency = <19 4297 clock-frequency = <19200000>;
4392 4298
4393 frame@17c21000 { 4299 frame@17c21000 {
4394 frame-number 4300 frame-number = <0>;
4395 interrupts = 4301 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4396 4302 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4397 reg = <0x17c2 4303 reg = <0x17c21000 0x1000>,
4398 <0x17c2 4304 <0x17c22000 0x1000>;
4399 }; 4305 };
4400 4306
4401 frame@17c23000 { 4307 frame@17c23000 {
4402 frame-number 4308 frame-number = <1>;
4403 interrupts = 4309 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4404 reg = <0x17c2 4310 reg = <0x17c23000 0x1000>;
4405 status = "dis 4311 status = "disabled";
4406 }; 4312 };
4407 4313
4408 frame@17c25000 { 4314 frame@17c25000 {
4409 frame-number 4315 frame-number = <2>;
4410 interrupts = 4316 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4411 reg = <0x17c2 4317 reg = <0x17c25000 0x1000>;
4412 status = "dis 4318 status = "disabled";
4413 }; 4319 };
4414 4320
4415 frame@17c27000 { 4321 frame@17c27000 {
4416 frame-number 4322 frame-number = <3>;
4417 interrupts = 4323 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4418 reg = <0x17c2 4324 reg = <0x17c26000 0x1000>;
4419 status = "dis 4325 status = "disabled";
4420 }; 4326 };
4421 4327
4422 frame@17c29000 { 4328 frame@17c29000 {
4423 frame-number 4329 frame-number = <4>;
4424 interrupts = 4330 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4425 reg = <0x17c2 4331 reg = <0x17c29000 0x1000>;
4426 status = "dis 4332 status = "disabled";
4427 }; 4333 };
4428 4334
4429 frame@17c2b000 { 4335 frame@17c2b000 {
4430 frame-number 4336 frame-number = <5>;
4431 interrupts = 4337 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4432 reg = <0x17c2 4338 reg = <0x17c2b000 0x1000>;
4433 status = "dis 4339 status = "disabled";
4434 }; 4340 };
4435 4341
4436 frame@17c2d000 { 4342 frame@17c2d000 {
4437 frame-number 4343 frame-number = <6>;
4438 interrupts = 4344 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4439 reg = <0x17c2 4345 reg = <0x17c2d000 0x1000>;
4440 status = "dis 4346 status = "disabled";
4441 }; 4347 };
4442 }; 4348 };
4443 4349
4444 apps_rsc: rsc@18200000 { 4350 apps_rsc: rsc@18200000 {
4445 label = "apps_rsc"; 4351 label = "apps_rsc";
4446 compatible = "qcom,rp 4352 compatible = "qcom,rpmh-rsc";
4447 reg = <0x0 0x18200000 4353 reg = <0x0 0x18200000 0x0 0x10000>,
4448 <0x0 0x18210000 4354 <0x0 0x18210000 0x0 0x10000>,
4449 <0x0 0x18220000 4355 <0x0 0x18220000 0x0 0x10000>;
4450 reg-names = "drv-0", 4356 reg-names = "drv-0", "drv-1", "drv-2";
4451 interrupts = <GIC_SPI 4357 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4452 <GIC_SPI 4358 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4453 <GIC_SPI 4359 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4454 qcom,tcs-offset = <0x 4360 qcom,tcs-offset = <0xd00>;
4455 qcom,drv-id = <2>; 4361 qcom,drv-id = <2>;
4456 qcom,tcs-config = <AC 4362 qcom,tcs-config = <ACTIVE_TCS 2>,
4457 <SL 4363 <SLEEP_TCS 3>,
4458 <WA 4364 <WAKE_TCS 3>,
4459 <CO 4365 <CONTROL_TCS 1>;
4460 power-domains = <&CLU 4366 power-domains = <&CLUSTER_PD>;
4461 4367
4462 rpmhcc: clock-control 4368 rpmhcc: clock-controller {
4463 compatible = 4369 compatible = "qcom,sm8150-rpmh-clk";
4464 #clock-cells 4370 #clock-cells = <1>;
4465 clock-names = 4371 clock-names = "xo";
4466 clocks = <&xo 4372 clocks = <&xo_board>;
4467 }; 4373 };
4468 4374
4469 rpmhpd: power-control 4375 rpmhpd: power-controller {
4470 compatible = 4376 compatible = "qcom,sm8150-rpmhpd";
4471 #power-domain 4377 #power-domain-cells = <1>;
4472 operating-poi 4378 operating-points-v2 = <&rpmhpd_opp_table>;
4473 4379
4474 rpmhpd_opp_ta 4380 rpmhpd_opp_table: opp-table {
4475 compa 4381 compatible = "operating-points-v2";
4476 4382
4477 rpmhp 4383 rpmhpd_opp_ret: opp1 {
4478 4384 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4479 }; 4385 };
4480 4386
4481 rpmhp 4387 rpmhpd_opp_min_svs: opp2 {
4482 4388 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4483 }; 4389 };
4484 4390
4485 rpmhp 4391 rpmhpd_opp_low_svs: opp3 {
4486 4392 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4487 }; 4393 };
4488 4394
4489 rpmhp 4395 rpmhpd_opp_svs: opp4 {
4490 4396 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4491 }; 4397 };
4492 4398
4493 rpmhp 4399 rpmhpd_opp_svs_l1: opp5 {
4494 4400 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4495 }; 4401 };
4496 4402
4497 rpmhp 4403 rpmhpd_opp_svs_l2: opp6 {
4498 4404 opp-level = <224>;
4499 }; 4405 };
4500 4406
4501 rpmhp 4407 rpmhpd_opp_nom: opp7 {
4502 4408 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4503 }; 4409 };
4504 4410
4505 rpmhp 4411 rpmhpd_opp_nom_l1: opp8 {
4506 4412 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4507 }; 4413 };
4508 4414
4509 rpmhp 4415 rpmhpd_opp_nom_l2: opp9 {
4510 4416 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4511 }; 4417 };
4512 4418
4513 rpmhp 4419 rpmhpd_opp_turbo: opp10 {
4514 4420 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4515 }; 4421 };
4516 4422
4517 rpmhp 4423 rpmhpd_opp_turbo_l1: opp11 {
4518 4424 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4519 }; 4425 };
4520 }; 4426 };
4521 }; 4427 };
4522 4428
4523 apps_bcm_voter: bcm-v 4429 apps_bcm_voter: bcm-voter {
4524 compatible = 4430 compatible = "qcom,bcm-voter";
4525 }; 4431 };
4526 }; 4432 };
4527 4433
4528 osm_l3: interconnect@18321000 4434 osm_l3: interconnect@18321000 {
4529 compatible = "qcom,sm 4435 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4530 reg = <0 0x18321000 0 4436 reg = <0 0x18321000 0 0x1400>;
4531 4437
4532 clocks = <&rpmhcc RPM 4438 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4533 clock-names = "xo", " 4439 clock-names = "xo", "alternate";
4534 4440
4535 #interconnect-cells = 4441 #interconnect-cells = <1>;
4536 }; 4442 };
4537 4443
4538 cpufreq_hw: cpufreq@18323000 4444 cpufreq_hw: cpufreq@18323000 {
4539 compatible = "qcom,sm 4445 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4540 reg = <0 0x18323000 0 4446 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
4541 <0 0x18327800 0 4447 <0 0x18327800 0 0x1400>;
4542 reg-names = "freq-dom 4448 reg-names = "freq-domain0", "freq-domain1",
4543 "freq-dom 4449 "freq-domain2";
4544 4450
4545 clocks = <&rpmhcc RPM 4451 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
4546 clock-names = "xo", " 4452 clock-names = "xo", "alternate";
4547 4453
4548 #freq-domain-cells = 4454 #freq-domain-cells = <1>;
4549 #clock-cells = <1>; 4455 #clock-cells = <1>;
4550 }; 4456 };
4551 4457
4552 lmh_cluster1: lmh@18350800 { 4458 lmh_cluster1: lmh@18350800 {
4553 compatible = "qcom,sm 4459 compatible = "qcom,sm8150-lmh";
4554 reg = <0 0x18350800 0 4460 reg = <0 0x18350800 0 0x400>;
4555 interrupts = <GIC_SPI 4461 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
4556 cpus = <&CPU4>; 4462 cpus = <&CPU4>;
4557 qcom,lmh-temp-arm-mil 4463 qcom,lmh-temp-arm-millicelsius = <60000>;
4558 qcom,lmh-temp-low-mil 4464 qcom,lmh-temp-low-millicelsius = <84500>;
4559 qcom,lmh-temp-high-mi 4465 qcom,lmh-temp-high-millicelsius = <85000>;
4560 interrupt-controller; 4466 interrupt-controller;
4561 #interrupt-cells = <1 4467 #interrupt-cells = <1>;
4562 }; 4468 };
4563 4469
4564 lmh_cluster0: lmh@18358800 { 4470 lmh_cluster0: lmh@18358800 {
4565 compatible = "qcom,sm 4471 compatible = "qcom,sm8150-lmh";
4566 reg = <0 0x18358800 0 4472 reg = <0 0x18358800 0 0x400>;
4567 interrupts = <GIC_SPI 4473 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4568 cpus = <&CPU0>; 4474 cpus = <&CPU0>;
4569 qcom,lmh-temp-arm-mil 4475 qcom,lmh-temp-arm-millicelsius = <60000>;
4570 qcom,lmh-temp-low-mil 4476 qcom,lmh-temp-low-millicelsius = <84500>;
4571 qcom,lmh-temp-high-mi 4477 qcom,lmh-temp-high-millicelsius = <85000>;
4572 interrupt-controller; 4478 interrupt-controller;
4573 #interrupt-cells = <1 4479 #interrupt-cells = <1>;
4574 }; 4480 };
4575 4481
4576 wifi: wifi@18800000 { 4482 wifi: wifi@18800000 {
4577 compatible = "qcom,wc 4483 compatible = "qcom,wcn3990-wifi";
4578 reg = <0 0x18800000 0 4484 reg = <0 0x18800000 0 0x800000>;
4579 reg-names = "membase" 4485 reg-names = "membase";
4580 memory-region = <&wla 4486 memory-region = <&wlan_mem>;
4581 clock-names = "cxo_re 4487 clock-names = "cxo_ref_clk_pin", "qdss";
4582 clocks = <&rpmhcc RPM 4488 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
4583 interrupts = <GIC_SPI 4489 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4584 <GIC_SPI 4490 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
4585 <GIC_SPI 4491 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
4586 <GIC_SPI 4492 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
4587 <GIC_SPI 4493 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4588 <GIC_SPI 4494 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4589 <GIC_SPI 4495 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4590 <GIC_SPI 4496 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4591 <GIC_SPI 4497 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4592 <GIC_SPI 4498 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4593 <GIC_SPI 4499 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4594 <GIC_SPI 4500 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
4595 iommus = <&apps_smmu 4501 iommus = <&apps_smmu 0x0640 0x1>;
4596 status = "disabled"; 4502 status = "disabled";
4597 }; 4503 };
4598 }; 4504 };
4599 4505
4600 timer { 4506 timer {
4601 compatible = "arm,armv8-timer 4507 compatible = "arm,armv8-timer";
4602 interrupts = <GIC_PPI 1 IRQ_T 4508 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4603 <GIC_PPI 2 IRQ_T 4509 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4604 <GIC_PPI 3 IRQ_T 4510 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4605 <GIC_PPI 0 IRQ_T 4511 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4606 }; 4512 };
4607 4513
4608 thermal-zones { 4514 thermal-zones {
4609 cpu0-thermal { 4515 cpu0-thermal {
4610 polling-delay-passive 4516 polling-delay-passive = <250>;
>> 4517 polling-delay = <1000>;
4611 4518
4612 thermal-sensors = <&t 4519 thermal-sensors = <&tsens0 1>;
4613 4520
4614 trips { 4521 trips {
4615 cpu0_alert0: 4522 cpu0_alert0: trip-point0 {
4616 tempe 4523 temperature = <90000>;
4617 hyste 4524 hysteresis = <2000>;
4618 type 4525 type = "passive";
4619 }; 4526 };
4620 4527
4621 cpu0_alert1: 4528 cpu0_alert1: trip-point1 {
4622 tempe 4529 temperature = <95000>;
4623 hyste 4530 hysteresis = <2000>;
4624 type 4531 type = "passive";
4625 }; 4532 };
4626 4533
4627 cpu0_crit: cp 4534 cpu0_crit: cpu-crit {
4628 tempe 4535 temperature = <110000>;
4629 hyste 4536 hysteresis = <1000>;
4630 type 4537 type = "critical";
4631 }; 4538 };
4632 }; 4539 };
4633 4540
4634 cooling-maps { 4541 cooling-maps {
4635 map0 { 4542 map0 {
4636 trip 4543 trip = <&cpu0_alert0>;
4637 cooli 4544 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4638 4545 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 4546 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4640 4547 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4641 }; 4548 };
4642 map1 { 4549 map1 {
4643 trip 4550 trip = <&cpu0_alert1>;
4644 cooli 4551 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4645 4552 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4646 4553 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4647 4554 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4648 }; 4555 };
4649 }; 4556 };
4650 }; 4557 };
4651 4558
4652 cpu1-thermal { 4559 cpu1-thermal {
4653 polling-delay-passive 4560 polling-delay-passive = <250>;
>> 4561 polling-delay = <1000>;
4654 4562
4655 thermal-sensors = <&t 4563 thermal-sensors = <&tsens0 2>;
4656 4564
4657 trips { 4565 trips {
4658 cpu1_alert0: 4566 cpu1_alert0: trip-point0 {
4659 tempe 4567 temperature = <90000>;
4660 hyste 4568 hysteresis = <2000>;
4661 type 4569 type = "passive";
4662 }; 4570 };
4663 4571
4664 cpu1_alert1: 4572 cpu1_alert1: trip-point1 {
4665 tempe 4573 temperature = <95000>;
4666 hyste 4574 hysteresis = <2000>;
4667 type 4575 type = "passive";
4668 }; 4576 };
4669 4577
4670 cpu1_crit: cp 4578 cpu1_crit: cpu-crit {
4671 tempe 4579 temperature = <110000>;
4672 hyste 4580 hysteresis = <1000>;
4673 type 4581 type = "critical";
4674 }; 4582 };
4675 }; 4583 };
4676 4584
4677 cooling-maps { 4585 cooling-maps {
4678 map0 { 4586 map0 {
4679 trip 4587 trip = <&cpu1_alert0>;
4680 cooli 4588 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4681 4589 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4682 4590 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 4591 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4684 }; 4592 };
4685 map1 { 4593 map1 {
4686 trip 4594 trip = <&cpu1_alert1>;
4687 cooli 4595 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4688 4596 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4689 4597 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4690 4598 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4691 }; 4599 };
4692 }; 4600 };
4693 }; 4601 };
4694 4602
4695 cpu2-thermal { 4603 cpu2-thermal {
4696 polling-delay-passive 4604 polling-delay-passive = <250>;
>> 4605 polling-delay = <1000>;
4697 4606
4698 thermal-sensors = <&t 4607 thermal-sensors = <&tsens0 3>;
4699 4608
4700 trips { 4609 trips {
4701 cpu2_alert0: 4610 cpu2_alert0: trip-point0 {
4702 tempe 4611 temperature = <90000>;
4703 hyste 4612 hysteresis = <2000>;
4704 type 4613 type = "passive";
4705 }; 4614 };
4706 4615
4707 cpu2_alert1: 4616 cpu2_alert1: trip-point1 {
4708 tempe 4617 temperature = <95000>;
4709 hyste 4618 hysteresis = <2000>;
4710 type 4619 type = "passive";
4711 }; 4620 };
4712 4621
4713 cpu2_crit: cp 4622 cpu2_crit: cpu-crit {
4714 tempe 4623 temperature = <110000>;
4715 hyste 4624 hysteresis = <1000>;
4716 type 4625 type = "critical";
4717 }; 4626 };
4718 }; 4627 };
4719 4628
4720 cooling-maps { 4629 cooling-maps {
4721 map0 { 4630 map0 {
4722 trip 4631 trip = <&cpu2_alert0>;
4723 cooli 4632 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4724 4633 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4725 4634 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4726 4635 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4727 }; 4636 };
4728 map1 { 4637 map1 {
4729 trip 4638 trip = <&cpu2_alert1>;
4730 cooli 4639 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4731 4640 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4732 4641 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4733 4642 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4734 }; 4643 };
4735 }; 4644 };
4736 }; 4645 };
4737 4646
4738 cpu3-thermal { 4647 cpu3-thermal {
4739 polling-delay-passive 4648 polling-delay-passive = <250>;
>> 4649 polling-delay = <1000>;
4740 4650
4741 thermal-sensors = <&t 4651 thermal-sensors = <&tsens0 4>;
4742 4652
4743 trips { 4653 trips {
4744 cpu3_alert0: 4654 cpu3_alert0: trip-point0 {
4745 tempe 4655 temperature = <90000>;
4746 hyste 4656 hysteresis = <2000>;
4747 type 4657 type = "passive";
4748 }; 4658 };
4749 4659
4750 cpu3_alert1: 4660 cpu3_alert1: trip-point1 {
4751 tempe 4661 temperature = <95000>;
4752 hyste 4662 hysteresis = <2000>;
4753 type 4663 type = "passive";
4754 }; 4664 };
4755 4665
4756 cpu3_crit: cp 4666 cpu3_crit: cpu-crit {
4757 tempe 4667 temperature = <110000>;
4758 hyste 4668 hysteresis = <1000>;
4759 type 4669 type = "critical";
4760 }; 4670 };
4761 }; 4671 };
4762 4672
4763 cooling-maps { 4673 cooling-maps {
4764 map0 { 4674 map0 {
4765 trip 4675 trip = <&cpu3_alert0>;
4766 cooli 4676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4767 4677 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4768 4678 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4769 4679 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4770 }; 4680 };
4771 map1 { 4681 map1 {
4772 trip 4682 trip = <&cpu3_alert1>;
4773 cooli 4683 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4774 4684 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4775 4685 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4776 4686 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4777 }; 4687 };
4778 }; 4688 };
4779 }; 4689 };
4780 4690
4781 cpu4-top-thermal { 4691 cpu4-top-thermal {
4782 polling-delay-passive 4692 polling-delay-passive = <250>;
>> 4693 polling-delay = <1000>;
4783 4694
4784 thermal-sensors = <&t 4695 thermal-sensors = <&tsens0 7>;
4785 4696
4786 trips { 4697 trips {
4787 cpu4_top_aler 4698 cpu4_top_alert0: trip-point0 {
4788 tempe 4699 temperature = <90000>;
4789 hyste 4700 hysteresis = <2000>;
4790 type 4701 type = "passive";
4791 }; 4702 };
4792 4703
4793 cpu4_top_aler 4704 cpu4_top_alert1: trip-point1 {
4794 tempe 4705 temperature = <95000>;
4795 hyste 4706 hysteresis = <2000>;
4796 type 4707 type = "passive";
4797 }; 4708 };
4798 4709
4799 cpu4_top_crit 4710 cpu4_top_crit: cpu-crit {
4800 tempe 4711 temperature = <110000>;
4801 hyste 4712 hysteresis = <1000>;
4802 type 4713 type = "critical";
4803 }; 4714 };
4804 }; 4715 };
4805 4716
4806 cooling-maps { 4717 cooling-maps {
4807 map0 { 4718 map0 {
4808 trip 4719 trip = <&cpu4_top_alert0>;
4809 cooli 4720 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4810 4721 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4811 4722 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4812 4723 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4813 }; 4724 };
4814 map1 { 4725 map1 {
4815 trip 4726 trip = <&cpu4_top_alert1>;
4816 cooli 4727 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4817 4728 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4818 4729 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4819 4730 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4820 }; 4731 };
4821 }; 4732 };
4822 }; 4733 };
4823 4734
4824 cpu5-top-thermal { 4735 cpu5-top-thermal {
4825 polling-delay-passive 4736 polling-delay-passive = <250>;
>> 4737 polling-delay = <1000>;
4826 4738
4827 thermal-sensors = <&t 4739 thermal-sensors = <&tsens0 8>;
4828 4740
4829 trips { 4741 trips {
4830 cpu5_top_aler 4742 cpu5_top_alert0: trip-point0 {
4831 tempe 4743 temperature = <90000>;
4832 hyste 4744 hysteresis = <2000>;
4833 type 4745 type = "passive";
4834 }; 4746 };
4835 4747
4836 cpu5_top_aler 4748 cpu5_top_alert1: trip-point1 {
4837 tempe 4749 temperature = <95000>;
4838 hyste 4750 hysteresis = <2000>;
4839 type 4751 type = "passive";
4840 }; 4752 };
4841 4753
4842 cpu5_top_crit 4754 cpu5_top_crit: cpu-crit {
4843 tempe 4755 temperature = <110000>;
4844 hyste 4756 hysteresis = <1000>;
4845 type 4757 type = "critical";
4846 }; 4758 };
4847 }; 4759 };
4848 4760
4849 cooling-maps { 4761 cooling-maps {
4850 map0 { 4762 map0 {
4851 trip 4763 trip = <&cpu5_top_alert0>;
4852 cooli 4764 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4853 4765 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4854 4766 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4855 4767 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4856 }; 4768 };
4857 map1 { 4769 map1 {
4858 trip 4770 trip = <&cpu5_top_alert1>;
4859 cooli 4771 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4860 4772 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4861 4773 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4862 4774 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4863 }; 4775 };
4864 }; 4776 };
4865 }; 4777 };
4866 4778
4867 cpu6-top-thermal { 4779 cpu6-top-thermal {
4868 polling-delay-passive 4780 polling-delay-passive = <250>;
>> 4781 polling-delay = <1000>;
4869 4782
4870 thermal-sensors = <&t 4783 thermal-sensors = <&tsens0 9>;
4871 4784
4872 trips { 4785 trips {
4873 cpu6_top_aler 4786 cpu6_top_alert0: trip-point0 {
4874 tempe 4787 temperature = <90000>;
4875 hyste 4788 hysteresis = <2000>;
4876 type 4789 type = "passive";
4877 }; 4790 };
4878 4791
4879 cpu6_top_aler 4792 cpu6_top_alert1: trip-point1 {
4880 tempe 4793 temperature = <95000>;
4881 hyste 4794 hysteresis = <2000>;
4882 type 4795 type = "passive";
4883 }; 4796 };
4884 4797
4885 cpu6_top_crit 4798 cpu6_top_crit: cpu-crit {
4886 tempe 4799 temperature = <110000>;
4887 hyste 4800 hysteresis = <1000>;
4888 type 4801 type = "critical";
4889 }; 4802 };
4890 }; 4803 };
4891 4804
4892 cooling-maps { 4805 cooling-maps {
4893 map0 { 4806 map0 {
4894 trip 4807 trip = <&cpu6_top_alert0>;
4895 cooli 4808 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4896 4809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4897 4810 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4898 4811 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4899 }; 4812 };
4900 map1 { 4813 map1 {
4901 trip 4814 trip = <&cpu6_top_alert1>;
4902 cooli 4815 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 4816 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4904 4817 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4905 4818 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4906 }; 4819 };
4907 }; 4820 };
4908 }; 4821 };
4909 4822
4910 cpu7-top-thermal { 4823 cpu7-top-thermal {
4911 polling-delay-passive 4824 polling-delay-passive = <250>;
>> 4825 polling-delay = <1000>;
4912 4826
4913 thermal-sensors = <&t 4827 thermal-sensors = <&tsens0 10>;
4914 4828
4915 trips { 4829 trips {
4916 cpu7_top_aler 4830 cpu7_top_alert0: trip-point0 {
4917 tempe 4831 temperature = <90000>;
4918 hyste 4832 hysteresis = <2000>;
4919 type 4833 type = "passive";
4920 }; 4834 };
4921 4835
4922 cpu7_top_aler 4836 cpu7_top_alert1: trip-point1 {
4923 tempe 4837 temperature = <95000>;
4924 hyste 4838 hysteresis = <2000>;
4925 type 4839 type = "passive";
4926 }; 4840 };
4927 4841
4928 cpu7_top_crit 4842 cpu7_top_crit: cpu-crit {
4929 tempe 4843 temperature = <110000>;
4930 hyste 4844 hysteresis = <1000>;
4931 type 4845 type = "critical";
4932 }; 4846 };
4933 }; 4847 };
4934 4848
4935 cooling-maps { 4849 cooling-maps {
4936 map0 { 4850 map0 {
4937 trip 4851 trip = <&cpu7_top_alert0>;
4938 cooli 4852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 4853 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4940 4854 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4941 4855 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4942 }; 4856 };
4943 map1 { 4857 map1 {
4944 trip 4858 trip = <&cpu7_top_alert1>;
4945 cooli 4859 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4946 4860 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 4861 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4948 4862 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4949 }; 4863 };
4950 }; 4864 };
4951 }; 4865 };
4952 4866
4953 cpu4-bottom-thermal { 4867 cpu4-bottom-thermal {
4954 polling-delay-passive 4868 polling-delay-passive = <250>;
>> 4869 polling-delay = <1000>;
4955 4870
4956 thermal-sensors = <&t 4871 thermal-sensors = <&tsens0 11>;
4957 4872
4958 trips { 4873 trips {
4959 cpu4_bottom_a 4874 cpu4_bottom_alert0: trip-point0 {
4960 tempe 4875 temperature = <90000>;
4961 hyste 4876 hysteresis = <2000>;
4962 type 4877 type = "passive";
4963 }; 4878 };
4964 4879
4965 cpu4_bottom_a 4880 cpu4_bottom_alert1: trip-point1 {
4966 tempe 4881 temperature = <95000>;
4967 hyste 4882 hysteresis = <2000>;
4968 type 4883 type = "passive";
4969 }; 4884 };
4970 4885
4971 cpu4_bottom_c 4886 cpu4_bottom_crit: cpu-crit {
4972 tempe 4887 temperature = <110000>;
4973 hyste 4888 hysteresis = <1000>;
4974 type 4889 type = "critical";
4975 }; 4890 };
4976 }; 4891 };
4977 4892
4978 cooling-maps { 4893 cooling-maps {
4979 map0 { 4894 map0 {
4980 trip 4895 trip = <&cpu4_bottom_alert0>;
4981 cooli 4896 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4982 4897 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4983 4898 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4984 4899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4985 }; 4900 };
4986 map1 { 4901 map1 {
4987 trip 4902 trip = <&cpu4_bottom_alert1>;
4988 cooli 4903 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4989 4904 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4990 4905 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4991 4906 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4992 }; 4907 };
4993 }; 4908 };
4994 }; 4909 };
4995 4910
4996 cpu5-bottom-thermal { 4911 cpu5-bottom-thermal {
4997 polling-delay-passive 4912 polling-delay-passive = <250>;
>> 4913 polling-delay = <1000>;
4998 4914
4999 thermal-sensors = <&t 4915 thermal-sensors = <&tsens0 12>;
5000 4916
5001 trips { 4917 trips {
5002 cpu5_bottom_a 4918 cpu5_bottom_alert0: trip-point0 {
5003 tempe 4919 temperature = <90000>;
5004 hyste 4920 hysteresis = <2000>;
5005 type 4921 type = "passive";
5006 }; 4922 };
5007 4923
5008 cpu5_bottom_a 4924 cpu5_bottom_alert1: trip-point1 {
5009 tempe 4925 temperature = <95000>;
5010 hyste 4926 hysteresis = <2000>;
5011 type 4927 type = "passive";
5012 }; 4928 };
5013 4929
5014 cpu5_bottom_c 4930 cpu5_bottom_crit: cpu-crit {
5015 tempe 4931 temperature = <110000>;
5016 hyste 4932 hysteresis = <1000>;
5017 type 4933 type = "critical";
5018 }; 4934 };
5019 }; 4935 };
5020 4936
5021 cooling-maps { 4937 cooling-maps {
5022 map0 { 4938 map0 {
5023 trip 4939 trip = <&cpu5_bottom_alert0>;
5024 cooli 4940 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5025 4941 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5026 4942 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5027 4943 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5028 }; 4944 };
5029 map1 { 4945 map1 {
5030 trip 4946 trip = <&cpu5_bottom_alert1>;
5031 cooli 4947 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5032 4948 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5033 4949 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5034 4950 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5035 }; 4951 };
5036 }; 4952 };
5037 }; 4953 };
5038 4954
5039 cpu6-bottom-thermal { 4955 cpu6-bottom-thermal {
5040 polling-delay-passive 4956 polling-delay-passive = <250>;
>> 4957 polling-delay = <1000>;
5041 4958
5042 thermal-sensors = <&t 4959 thermal-sensors = <&tsens0 13>;
5043 4960
5044 trips { 4961 trips {
5045 cpu6_bottom_a 4962 cpu6_bottom_alert0: trip-point0 {
5046 tempe 4963 temperature = <90000>;
5047 hyste 4964 hysteresis = <2000>;
5048 type 4965 type = "passive";
5049 }; 4966 };
5050 4967
5051 cpu6_bottom_a 4968 cpu6_bottom_alert1: trip-point1 {
5052 tempe 4969 temperature = <95000>;
5053 hyste 4970 hysteresis = <2000>;
5054 type 4971 type = "passive";
5055 }; 4972 };
5056 4973
5057 cpu6_bottom_c 4974 cpu6_bottom_crit: cpu-crit {
5058 tempe 4975 temperature = <110000>;
5059 hyste 4976 hysteresis = <1000>;
5060 type 4977 type = "critical";
5061 }; 4978 };
5062 }; 4979 };
5063 4980
5064 cooling-maps { 4981 cooling-maps {
5065 map0 { 4982 map0 {
5066 trip 4983 trip = <&cpu6_bottom_alert0>;
5067 cooli 4984 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5068 4985 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5069 4986 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5070 4987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5071 }; 4988 };
5072 map1 { 4989 map1 {
5073 trip 4990 trip = <&cpu6_bottom_alert1>;
5074 cooli 4991 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5075 4992 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5076 4993 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5077 4994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5078 }; 4995 };
5079 }; 4996 };
5080 }; 4997 };
5081 4998
5082 cpu7-bottom-thermal { 4999 cpu7-bottom-thermal {
5083 polling-delay-passive 5000 polling-delay-passive = <250>;
>> 5001 polling-delay = <1000>;
5084 5002
5085 thermal-sensors = <&t 5003 thermal-sensors = <&tsens0 14>;
5086 5004
5087 trips { 5005 trips {
5088 cpu7_bottom_a 5006 cpu7_bottom_alert0: trip-point0 {
5089 tempe 5007 temperature = <90000>;
5090 hyste 5008 hysteresis = <2000>;
5091 type 5009 type = "passive";
5092 }; 5010 };
5093 5011
5094 cpu7_bottom_a 5012 cpu7_bottom_alert1: trip-point1 {
5095 tempe 5013 temperature = <95000>;
5096 hyste 5014 hysteresis = <2000>;
5097 type 5015 type = "passive";
5098 }; 5016 };
5099 5017
5100 cpu7_bottom_c 5018 cpu7_bottom_crit: cpu-crit {
5101 tempe 5019 temperature = <110000>;
5102 hyste 5020 hysteresis = <1000>;
5103 type 5021 type = "critical";
5104 }; 5022 };
5105 }; 5023 };
5106 5024
5107 cooling-maps { 5025 cooling-maps {
5108 map0 { 5026 map0 {
5109 trip 5027 trip = <&cpu7_bottom_alert0>;
5110 cooli 5028 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5111 5029 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5112 5030 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5113 5031 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5114 }; 5032 };
5115 map1 { 5033 map1 {
5116 trip 5034 trip = <&cpu7_bottom_alert1>;
5117 cooli 5035 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5118 5036 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5119 5037 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5120 5038 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5121 }; 5039 };
5122 }; 5040 };
5123 }; 5041 };
5124 5042
5125 aoss0-thermal { 5043 aoss0-thermal {
5126 polling-delay-passive 5044 polling-delay-passive = <250>;
>> 5045 polling-delay = <1000>;
5127 5046
5128 thermal-sensors = <&t 5047 thermal-sensors = <&tsens0 0>;
5129 5048
5130 trips { 5049 trips {
5131 aoss0_alert0: 5050 aoss0_alert0: trip-point0 {
5132 tempe 5051 temperature = <90000>;
5133 hyste 5052 hysteresis = <2000>;
5134 type 5053 type = "hot";
5135 }; 5054 };
5136 }; 5055 };
5137 }; 5056 };
5138 5057
5139 cluster0-thermal { 5058 cluster0-thermal {
5140 polling-delay-passive 5059 polling-delay-passive = <250>;
>> 5060 polling-delay = <1000>;
5141 5061
5142 thermal-sensors = <&t 5062 thermal-sensors = <&tsens0 5>;
5143 5063
5144 trips { 5064 trips {
5145 cluster0_aler 5065 cluster0_alert0: trip-point0 {
5146 tempe 5066 temperature = <90000>;
5147 hyste 5067 hysteresis = <2000>;
5148 type 5068 type = "hot";
5149 }; 5069 };
5150 cluster0_crit !! 5070 cluster0_crit: cluster0_crit {
5151 tempe 5071 temperature = <110000>;
5152 hyste 5072 hysteresis = <2000>;
5153 type 5073 type = "critical";
5154 }; 5074 };
5155 }; 5075 };
5156 }; 5076 };
5157 5077
5158 cluster1-thermal { 5078 cluster1-thermal {
5159 polling-delay-passive 5079 polling-delay-passive = <250>;
>> 5080 polling-delay = <1000>;
5160 5081
5161 thermal-sensors = <&t 5082 thermal-sensors = <&tsens0 6>;
5162 5083
5163 trips { 5084 trips {
5164 cluster1_aler 5085 cluster1_alert0: trip-point0 {
5165 tempe 5086 temperature = <90000>;
5166 hyste 5087 hysteresis = <2000>;
5167 type 5088 type = "hot";
5168 }; 5089 };
5169 cluster1_crit !! 5090 cluster1_crit: cluster1_crit {
5170 tempe 5091 temperature = <110000>;
5171 hyste 5092 hysteresis = <2000>;
5172 type 5093 type = "critical";
5173 }; 5094 };
5174 }; 5095 };
5175 }; 5096 };
5176 5097
5177 gpu-top-thermal { 5098 gpu-top-thermal {
5178 polling-delay-passive 5099 polling-delay-passive = <250>;
>> 5100 polling-delay = <1000>;
5179 5101
5180 thermal-sensors = <&t 5102 thermal-sensors = <&tsens0 15>;
5181 5103
5182 cooling-maps { <<
5183 map0 { <<
5184 trip <<
5185 cooli <<
5186 }; <<
5187 }; <<
5188 <<
5189 trips { 5104 trips {
5190 gpu_top_alert !! 5105 gpu1_alert0: trip-point0 {
5191 tempe <<
5192 hyste <<
5193 type <<
5194 }; <<
5195 <<
5196 trip-point1 { <<
5197 tempe 5106 temperature = <90000>;
5198 hyste !! 5107 hysteresis = <2000>;
5199 type 5108 type = "hot";
5200 }; 5109 };
5201 <<
5202 trip-point2 { <<
5203 tempe <<
5204 hyste <<
5205 type <<
5206 }; <<
5207 }; 5110 };
5208 }; 5111 };
5209 5112
5210 aoss1-thermal { 5113 aoss1-thermal {
5211 polling-delay-passive 5114 polling-delay-passive = <250>;
>> 5115 polling-delay = <1000>;
5212 5116
5213 thermal-sensors = <&t 5117 thermal-sensors = <&tsens1 0>;
5214 5118
5215 trips { 5119 trips {
5216 aoss1_alert0: 5120 aoss1_alert0: trip-point0 {
5217 tempe 5121 temperature = <90000>;
5218 hyste 5122 hysteresis = <2000>;
5219 type 5123 type = "hot";
5220 }; 5124 };
5221 }; 5125 };
5222 }; 5126 };
5223 5127
5224 wlan-thermal { 5128 wlan-thermal {
5225 polling-delay-passive 5129 polling-delay-passive = <250>;
>> 5130 polling-delay = <1000>;
5226 5131
5227 thermal-sensors = <&t 5132 thermal-sensors = <&tsens1 1>;
5228 5133
5229 trips { 5134 trips {
5230 wlan_alert0: 5135 wlan_alert0: trip-point0 {
5231 tempe 5136 temperature = <90000>;
5232 hyste 5137 hysteresis = <2000>;
5233 type 5138 type = "hot";
5234 }; 5139 };
5235 }; 5140 };
5236 }; 5141 };
5237 5142
5238 video-thermal { 5143 video-thermal {
5239 polling-delay-passive 5144 polling-delay-passive = <250>;
>> 5145 polling-delay = <1000>;
5240 5146
5241 thermal-sensors = <&t 5147 thermal-sensors = <&tsens1 2>;
5242 5148
5243 trips { 5149 trips {
5244 video_alert0: 5150 video_alert0: trip-point0 {
5245 tempe 5151 temperature = <90000>;
5246 hyste 5152 hysteresis = <2000>;
5247 type 5153 type = "hot";
5248 }; 5154 };
5249 }; 5155 };
5250 }; 5156 };
5251 5157
5252 mem-thermal { 5158 mem-thermal {
5253 polling-delay-passive 5159 polling-delay-passive = <250>;
>> 5160 polling-delay = <1000>;
5254 5161
5255 thermal-sensors = <&t 5162 thermal-sensors = <&tsens1 3>;
5256 5163
5257 trips { 5164 trips {
5258 mem_alert0: t 5165 mem_alert0: trip-point0 {
5259 tempe 5166 temperature = <90000>;
5260 hyste 5167 hysteresis = <2000>;
5261 type 5168 type = "hot";
5262 }; 5169 };
5263 }; 5170 };
5264 }; 5171 };
5265 5172
5266 q6-hvx-thermal { 5173 q6-hvx-thermal {
5267 polling-delay-passive 5174 polling-delay-passive = <250>;
>> 5175 polling-delay = <1000>;
5268 5176
5269 thermal-sensors = <&t 5177 thermal-sensors = <&tsens1 4>;
5270 5178
5271 trips { 5179 trips {
5272 q6_hvx_alert0 5180 q6_hvx_alert0: trip-point0 {
5273 tempe 5181 temperature = <90000>;
5274 hyste 5182 hysteresis = <2000>;
5275 type 5183 type = "hot";
5276 }; 5184 };
5277 }; 5185 };
5278 }; 5186 };
5279 5187
5280 camera-thermal { 5188 camera-thermal {
5281 polling-delay-passive 5189 polling-delay-passive = <250>;
>> 5190 polling-delay = <1000>;
5282 5191
5283 thermal-sensors = <&t 5192 thermal-sensors = <&tsens1 5>;
5284 5193
5285 trips { 5194 trips {
5286 camera_alert0 5195 camera_alert0: trip-point0 {
5287 tempe 5196 temperature = <90000>;
5288 hyste 5197 hysteresis = <2000>;
5289 type 5198 type = "hot";
5290 }; 5199 };
5291 }; 5200 };
5292 }; 5201 };
5293 5202
5294 compute-thermal { 5203 compute-thermal {
5295 polling-delay-passive 5204 polling-delay-passive = <250>;
>> 5205 polling-delay = <1000>;
5296 5206
5297 thermal-sensors = <&t 5207 thermal-sensors = <&tsens1 6>;
5298 5208
5299 trips { 5209 trips {
5300 compute_alert 5210 compute_alert0: trip-point0 {
5301 tempe 5211 temperature = <90000>;
5302 hyste 5212 hysteresis = <2000>;
5303 type 5213 type = "hot";
5304 }; 5214 };
5305 }; 5215 };
5306 }; 5216 };
5307 5217
5308 modem-thermal { 5218 modem-thermal {
5309 polling-delay-passive 5219 polling-delay-passive = <250>;
>> 5220 polling-delay = <1000>;
5310 5221
5311 thermal-sensors = <&t 5222 thermal-sensors = <&tsens1 7>;
5312 5223
5313 trips { 5224 trips {
5314 modem_alert0: 5225 modem_alert0: trip-point0 {
5315 tempe 5226 temperature = <90000>;
5316 hyste 5227 hysteresis = <2000>;
5317 type 5228 type = "hot";
5318 }; 5229 };
5319 }; 5230 };
5320 }; 5231 };
5321 5232
5322 npu-thermal { 5233 npu-thermal {
5323 polling-delay-passive 5234 polling-delay-passive = <250>;
>> 5235 polling-delay = <1000>;
5324 5236
5325 thermal-sensors = <&t 5237 thermal-sensors = <&tsens1 8>;
5326 5238
5327 trips { 5239 trips {
5328 npu_alert0: t 5240 npu_alert0: trip-point0 {
5329 tempe 5241 temperature = <90000>;
5330 hyste 5242 hysteresis = <2000>;
5331 type 5243 type = "hot";
5332 }; 5244 };
5333 }; 5245 };
5334 }; 5246 };
5335 5247
5336 modem-vec-thermal { 5248 modem-vec-thermal {
5337 polling-delay-passive 5249 polling-delay-passive = <250>;
>> 5250 polling-delay = <1000>;
5338 5251
5339 thermal-sensors = <&t 5252 thermal-sensors = <&tsens1 9>;
5340 5253
5341 trips { 5254 trips {
5342 modem_vec_ale 5255 modem_vec_alert0: trip-point0 {
5343 tempe 5256 temperature = <90000>;
5344 hyste 5257 hysteresis = <2000>;
5345 type 5258 type = "hot";
5346 }; 5259 };
5347 }; 5260 };
5348 }; 5261 };
5349 5262
5350 modem-scl-thermal { 5263 modem-scl-thermal {
5351 polling-delay-passive 5264 polling-delay-passive = <250>;
>> 5265 polling-delay = <1000>;
5352 5266
5353 thermal-sensors = <&t 5267 thermal-sensors = <&tsens1 10>;
5354 5268
5355 trips { 5269 trips {
5356 modem_scl_ale 5270 modem_scl_alert0: trip-point0 {
5357 tempe 5271 temperature = <90000>;
5358 hyste 5272 hysteresis = <2000>;
5359 type 5273 type = "hot";
5360 }; 5274 };
5361 }; 5275 };
5362 }; 5276 };
5363 5277
5364 gpu-bottom-thermal { 5278 gpu-bottom-thermal {
5365 polling-delay-passive 5279 polling-delay-passive = <250>;
>> 5280 polling-delay = <1000>;
5366 5281
5367 thermal-sensors = <&t 5282 thermal-sensors = <&tsens1 11>;
5368 5283
5369 cooling-maps { <<
5370 map0 { <<
5371 trip <<
5372 cooli <<
5373 }; <<
5374 }; <<
5375 <<
5376 trips { 5284 trips {
5377 gpu_bottom_al !! 5285 gpu2_alert0: trip-point0 {
5378 tempe <<
5379 hyste <<
5380 type <<
5381 }; <<
5382 <<
5383 trip-point1 { <<
5384 tempe 5286 temperature = <90000>;
5385 hyste !! 5287 hysteresis = <2000>;
5386 type 5288 type = "hot";
5387 }; <<
5388 <<
5389 trip-point2 { <<
5390 tempe <<
5391 hyste <<
5392 type <<
5393 }; 5289 };
5394 }; 5290 };
5395 }; 5291 };
5396 }; 5292 };
5397 }; 5293 };
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