1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, The Linux Foundation. A
4 */
5
6 #include <dt-bindings/interrupt-controller/arm
7 #include <dt-bindings/clock/qcom,dispcc-sm8250
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3
14 #include <dt-bindings/interconnect/qcom,sm8250
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250.
24 #include <dt-bindings/clock/qcom,videocc-sm825
25
26 / {
27 interrupt-parent = <&intc>;
28
29 #address-cells = <2>;
30 #size-cells = <2>;
31
32 aliases {
33 i2c0 = &i2c0;
34 i2c1 = &i2c1;
35 i2c2 = &i2c2;
36 i2c3 = &i2c3;
37 i2c4 = &i2c4;
38 i2c5 = &i2c5;
39 i2c6 = &i2c6;
40 i2c7 = &i2c7;
41 i2c8 = &i2c8;
42 i2c9 = &i2c9;
43 i2c10 = &i2c10;
44 i2c11 = &i2c11;
45 i2c12 = &i2c12;
46 i2c13 = &i2c13;
47 i2c14 = &i2c14;
48 i2c15 = &i2c15;
49 i2c16 = &i2c16;
50 i2c17 = &i2c17;
51 i2c18 = &i2c18;
52 i2c19 = &i2c19;
53 spi0 = &spi0;
54 spi1 = &spi1;
55 spi2 = &spi2;
56 spi3 = &spi3;
57 spi4 = &spi4;
58 spi5 = &spi5;
59 spi6 = &spi6;
60 spi7 = &spi7;
61 spi8 = &spi8;
62 spi9 = &spi9;
63 spi10 = &spi10;
64 spi11 = &spi11;
65 spi12 = &spi12;
66 spi13 = &spi13;
67 spi14 = &spi14;
68 spi15 = &spi15;
69 spi16 = &spi16;
70 spi17 = &spi17;
71 spi18 = &spi18;
72 spi19 = &spi19;
73 };
74
75 chosen { };
76
77 clocks {
78 xo_board: xo-board {
79 compatible = "fixed-cl
80 #clock-cells = <0>;
81 clock-frequency = <384
82 clock-output-names = "
83 };
84
85 sleep_clk: sleep-clk {
86 compatible = "fixed-cl
87 clock-frequency = <327
88 #clock-cells = <0>;
89 };
90 };
91
92 cpus {
93 #address-cells = <2>;
94 #size-cells = <0>;
95
96 CPU0: cpu@0 {
97 device_type = "cpu";
98 compatible = "qcom,kry
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw
101 enable-method = "psci"
102 capacity-dmips-mhz = <
103 dynamic-power-coeffici
104 next-level-cache = <&L
105 power-domains = <&CPU_
106 power-domain-names = "
107 qcom,freq-domain = <&c
108 operating-points-v2 =
109 interconnects = <&gem_
110 <&epss
111 #cooling-cells = <2>;
112 L2_0: l2-cache {
113 compatible = "
114 cache-level =
115 cache-size = <
116 cache-unified;
117 next-level-cac
118 L3_0: l3-cache
119 compat
120 cache-
121 cache-
122 cache-
123 };
124 };
125 };
126
127 CPU1: cpu@100 {
128 device_type = "cpu";
129 compatible = "qcom,kry
130 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw
132 enable-method = "psci"
133 capacity-dmips-mhz = <
134 dynamic-power-coeffici
135 next-level-cache = <&L
136 power-domains = <&CPU_
137 power-domain-names = "
138 qcom,freq-domain = <&c
139 operating-points-v2 =
140 interconnects = <&gem_
141 <&epss
142 #cooling-cells = <2>;
143 L2_100: l2-cache {
144 compatible = "
145 cache-level =
146 cache-size = <
147 cache-unified;
148 next-level-cac
149 };
150 };
151
152 CPU2: cpu@200 {
153 device_type = "cpu";
154 compatible = "qcom,kry
155 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw
157 enable-method = "psci"
158 capacity-dmips-mhz = <
159 dynamic-power-coeffici
160 next-level-cache = <&L
161 power-domains = <&CPU_
162 power-domain-names = "
163 qcom,freq-domain = <&c
164 operating-points-v2 =
165 interconnects = <&gem_
166 <&epss
167 #cooling-cells = <2>;
168 L2_200: l2-cache {
169 compatible = "
170 cache-level =
171 cache-size = <
172 cache-unified;
173 next-level-cac
174 };
175 };
176
177 CPU3: cpu@300 {
178 device_type = "cpu";
179 compatible = "qcom,kry
180 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw
182 enable-method = "psci"
183 capacity-dmips-mhz = <
184 dynamic-power-coeffici
185 next-level-cache = <&L
186 power-domains = <&CPU_
187 power-domain-names = "
188 qcom,freq-domain = <&c
189 operating-points-v2 =
190 interconnects = <&gem_
191 <&epss
192 #cooling-cells = <2>;
193 L2_300: l2-cache {
194 compatible = "
195 cache-level =
196 cache-size = <
197 cache-unified;
198 next-level-cac
199 };
200 };
201
202 CPU4: cpu@400 {
203 device_type = "cpu";
204 compatible = "qcom,kry
205 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw
207 enable-method = "psci"
208 capacity-dmips-mhz = <
209 dynamic-power-coeffici
210 next-level-cache = <&L
211 power-domains = <&CPU_
212 power-domain-names = "
213 qcom,freq-domain = <&c
214 operating-points-v2 =
215 interconnects = <&gem_
216 <&epss
217 #cooling-cells = <2>;
218 L2_400: l2-cache {
219 compatible = "
220 cache-level =
221 cache-size = <
222 cache-unified;
223 next-level-cac
224 };
225 };
226
227 CPU5: cpu@500 {
228 device_type = "cpu";
229 compatible = "qcom,kry
230 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw
232 enable-method = "psci"
233 capacity-dmips-mhz = <
234 dynamic-power-coeffici
235 next-level-cache = <&L
236 power-domains = <&CPU_
237 power-domain-names = "
238 qcom,freq-domain = <&c
239 operating-points-v2 =
240 interconnects = <&gem_
241 <&epss
242 #cooling-cells = <2>;
243 L2_500: l2-cache {
244 compatible = "
245 cache-level =
246 cache-size = <
247 cache-unified;
248 next-level-cac
249 };
250 };
251
252 CPU6: cpu@600 {
253 device_type = "cpu";
254 compatible = "qcom,kry
255 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw
257 enable-method = "psci"
258 capacity-dmips-mhz = <
259 dynamic-power-coeffici
260 next-level-cache = <&L
261 power-domains = <&CPU_
262 power-domain-names = "
263 qcom,freq-domain = <&c
264 operating-points-v2 =
265 interconnects = <&gem_
266 <&epss
267 #cooling-cells = <2>;
268 L2_600: l2-cache {
269 compatible = "
270 cache-level =
271 cache-size = <
272 cache-unified;
273 next-level-cac
274 };
275 };
276
277 CPU7: cpu@700 {
278 device_type = "cpu";
279 compatible = "qcom,kry
280 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw
282 enable-method = "psci"
283 capacity-dmips-mhz = <
284 dynamic-power-coeffici
285 next-level-cache = <&L
286 power-domains = <&CPU_
287 power-domain-names = "
288 qcom,freq-domain = <&c
289 operating-points-v2 =
290 interconnects = <&gem_
291 <&epss
292 #cooling-cells = <2>;
293 L2_700: l2-cache {
294 compatible = "
295 cache-level =
296 cache-size = <
297 cache-unified;
298 next-level-cac
299 };
300 };
301
302 cpu-map {
303 cluster0 {
304 core0 {
305 cpu =
306 };
307
308 core1 {
309 cpu =
310 };
311
312 core2 {
313 cpu =
314 };
315
316 core3 {
317 cpu =
318 };
319
320 core4 {
321 cpu =
322 };
323
324 core5 {
325 cpu =
326 };
327
328 core6 {
329 cpu =
330 };
331
332 core7 {
333 cpu =
334 };
335 };
336 };
337
338 idle-states {
339 entry-method = "psci";
340
341 LITTLE_CPU_SLEEP_0: cp
342 compatible = "
343 idle-state-nam
344 arm,psci-suspe
345 entry-latency-
346 exit-latency-u
347 min-residency-
348 local-timer-st
349 };
350
351 BIG_CPU_SLEEP_0: cpu-s
352 compatible = "
353 idle-state-nam
354 arm,psci-suspe
355 entry-latency-
356 exit-latency-u
357 min-residency-
358 local-timer-st
359 };
360 };
361
362 domain-idle-states {
363 CLUSTER_SLEEP_0: clust
364 compatible = "
365 arm,psci-suspe
366 entry-latency-
367 exit-latency-u
368 min-residency-
369 };
370 };
371 };
372
373 qup_virt: interconnect-qup-virt {
374 compatible = "qcom,sm8250-qup-
375 #interconnect-cells = <2>;
376 qcom,bcm-voters = <&apps_bcm_v
377 };
378
379 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points
381 opp-shared;
382
383 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30
385 opp-peak-kBps = <80000
386 };
387
388 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40
390 opp-peak-kBps = <80000
391 };
392
393 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51
395 opp-peak-kBps = <80000
396 };
397
398 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61
400 opp-peak-kBps = <80000
401 };
402
403 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69
405 opp-peak-kBps = <80000
406 };
407
408 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78
410 opp-peak-kBps = <18040
411 };
412
413 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88
415 opp-peak-kBps = <18040
416 };
417
418 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97
420 opp-peak-kBps = <18040
421 };
422
423 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10
425 opp-peak-kBps = <18040
426 };
427
428 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11
430 opp-peak-kBps = <18040
431 };
432
433 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12
435 opp-peak-kBps = <18040
436 };
437
438 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13
440 opp-peak-kBps = <21880
441 };
442
443 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14
445 opp-peak-kBps = <21880
446 };
447
448 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15
450 opp-peak-kBps = <30720
451 };
452
453 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16
455 opp-peak-kBps = <30720
456 };
457
458 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17
460 opp-peak-kBps = <40680
461 };
462
463 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18
465 opp-peak-kBps = <40680
466 };
467 };
468
469 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points
471 opp-shared;
472
473 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71
475 opp-peak-kBps = <18040
476 };
477
478 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82
480 opp-peak-kBps = <21880
481 };
482
483 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94
485 opp-peak-kBps = <21880
486 };
487
488 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10
490 opp-peak-kBps = <30720
491 };
492
493 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11
495 opp-peak-kBps = <30720
496 };
497
498 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12
500 opp-peak-kBps = <40680
501 };
502
503 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13
505 opp-peak-kBps = <40680
506 };
507
508 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14
510 opp-peak-kBps = <40680
511 };
512
513 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15
515 opp-peak-kBps = <54120
516 };
517
518 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16
520 opp-peak-kBps = <54120
521 };
522
523 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17
525 opp-peak-kBps = <54120
526 };
527
528 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18
530 opp-peak-kBps = <62200
531 };
532
533 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19
535 opp-peak-kBps = <62200
536 };
537
538 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20
540 opp-peak-kBps = <72160
541 };
542
543 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21
545 opp-peak-kBps = <72160
546 };
547
548 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22
550 opp-peak-kBps = <72160
551 };
552
553 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23
555 opp-peak-kBps = <83680
556 };
557
558 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24
560 opp-peak-kBps = <83680
561 };
562 };
563
564 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points
566 opp-shared;
567
568 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84
570 opp-peak-kBps = <21880
571 };
572
573 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96
575 opp-peak-kBps = <21880
576 };
577
578 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10
580 opp-peak-kBps = <30720
581 };
582
583 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11
585 opp-peak-kBps = <30720
586 };
587
588 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13
590 opp-peak-kBps = <40680
591 };
592
593 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14
595 opp-peak-kBps = <40680
596 };
597
598 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15
600 opp-peak-kBps = <40680
601 };
602
603 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16
605 opp-peak-kBps = <54120
606 };
607
608 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17
610 opp-peak-kBps = <54120
611 };
612
613 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18
615 opp-peak-kBps = <62200
616 };
617
618 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19
620 opp-peak-kBps = <62200
621 };
622
623 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20
625 opp-peak-kBps = <72160
626 };
627
628 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21
630 opp-peak-kBps = <72160
631 };
632
633 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22
635 opp-peak-kBps = <72160
636 };
637
638 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23
640 opp-peak-kBps = <83680
641 };
642
643 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24
645 opp-peak-kBps = <83680
646 };
647
648 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25
650 opp-peak-kBps = <83680
651 };
652
653 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26
655 opp-peak-kBps = <83680
656 };
657
658 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27
660 opp-peak-kBps = <83680
661 };
662
663 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28
665 opp-peak-kBps = <83680
666 };
667 };
668
669 firmware {
670 scm: scm {
671 compatible = "qcom,scm
672 qcom,dload-mode = <&tc
673 #reset-cells = <1>;
674 };
675 };
676
677 memory@80000000 {
678 device_type = "memory";
679 /* We expect the bootloader to
680 reg = <0x0 0x80000000 0x0 0x0>
681 };
682
683 pmu {
684 compatible = "arm,armv8-pmuv3"
685 interrupts = <GIC_PPI 7 IRQ_TY
686 };
687
688 psci {
689 compatible = "arm,psci-1.0";
690 method = "smc";
691
692 CPU_PD0: power-domain-cpu0 {
693 #power-domain-cells =
694 power-domains = <&CLUS
695 domain-idle-states = <
696 };
697
698 CPU_PD1: power-domain-cpu1 {
699 #power-domain-cells =
700 power-domains = <&CLUS
701 domain-idle-states = <
702 };
703
704 CPU_PD2: power-domain-cpu2 {
705 #power-domain-cells =
706 power-domains = <&CLUS
707 domain-idle-states = <
708 };
709
710 CPU_PD3: power-domain-cpu3 {
711 #power-domain-cells =
712 power-domains = <&CLUS
713 domain-idle-states = <
714 };
715
716 CPU_PD4: power-domain-cpu4 {
717 #power-domain-cells =
718 power-domains = <&CLUS
719 domain-idle-states = <
720 };
721
722 CPU_PD5: power-domain-cpu5 {
723 #power-domain-cells =
724 power-domains = <&CLUS
725 domain-idle-states = <
726 };
727
728 CPU_PD6: power-domain-cpu6 {
729 #power-domain-cells =
730 power-domains = <&CLUS
731 domain-idle-states = <
732 };
733
734 CPU_PD7: power-domain-cpu7 {
735 #power-domain-cells =
736 power-domains = <&CLUS
737 domain-idle-states = <
738 };
739
740 CLUSTER_PD: power-domain-cpu-c
741 #power-domain-cells =
742 domain-idle-states = <
743 };
744 };
745
746 qup_opp_table: opp-table-qup {
747 compatible = "operating-points
748
749 opp-50000000 {
750 opp-hz = /bits/ 64 <50
751 required-opps = <&rpmh
752 };
753
754 opp-75000000 {
755 opp-hz = /bits/ 64 <75
756 required-opps = <&rpmh
757 };
758
759 opp-120000000 {
760 opp-hz = /bits/ 64 <12
761 required-opps = <&rpmh
762 };
763 };
764
765 reserved-memory {
766 #address-cells = <2>;
767 #size-cells = <2>;
768 ranges;
769
770 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000
772 no-map;
773 };
774
775 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000
777 no-map;
778 };
779
780 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd
782 reg = <0x0 0x80860000
783 no-map;
784 };
785
786 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000
788 no-map;
789 };
790
791 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000
793 no-map;
794 };
795
796 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000
798 no-map;
799 };
800
801 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000
803 no-map;
804 };
805
806 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000
808 no-map;
809 };
810
811 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000
813 no-map;
814 };
815
816 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000
818 no-map;
819 };
820
821 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000
823 no-map;
824 };
825
826 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000
828 no-map;
829 };
830
831 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000
833 no-map;
834 };
835
836 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000
838 no-map;
839 };
840
841 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000
843 no-map;
844 };
845
846 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000
848 no-map;
849 };
850
851 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000
853 no-map;
854 };
855
856 cdsp_secure_heap: memory@8bf00
857 reg = <0x0 0x8bf00000
858 no-map;
859 };
860 };
861
862 smem {
863 compatible = "qcom,smem";
864 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>;
866 };
867
868 smp2p-adsp {
869 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I
872 I
873 I
874 mboxes = <&ipcc IPCC_CLIENT_LP
875 IPCC_MPROC_SIG
876
877 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>;
879
880 smp2p_adsp_out: master-kernel
881 qcom,entry-name = "mas
882 #qcom,smem-state-cells
883 };
884
885 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla
887 interrupt-controller;
888 #interrupt-cells = <2>
889 };
890 };
891
892 smp2p-cdsp {
893 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I
896 I
897 I
898 mboxes = <&ipcc IPCC_CLIENT_CD
899 IPCC_MPROC_SIG
900
901 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>;
903
904 smp2p_cdsp_out: master-kernel
905 qcom,entry-name = "mas
906 #qcom,smem-state-cells
907 };
908
909 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla
911 interrupt-controller;
912 #interrupt-cells = <2>
913 };
914 };
915
916 smp2p-slpi {
917 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I
920 I
921 I
922 mboxes = <&ipcc IPCC_CLIENT_SL
923 IPCC_MPROC_SIG
924
925 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>;
927
928 smp2p_slpi_out: master-kernel
929 qcom,entry-name = "mas
930 #qcom,smem-state-cells
931 };
932
933 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla
935 interrupt-controller;
936 #interrupt-cells = <2>
937 };
938 };
939
940 soc: soc@0 {
941 #address-cells = <2>;
942 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus";
946
947 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc
949 reg = <0x0 0x00100000
950 #clock-cells = <1>;
951 #reset-cells = <1>;
952 #power-domain-cells =
953 clock-names = "bi_tcxo
954 "bi_tcxo
955 "sleep_c
956 clocks = <&rpmhcc RPMH
957 <&rpmhcc RPMH
958 <&sleep_clk>;
959 };
960
961 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8
963 reg = <0 0x00408000 0
964 interrupts = <GIC_SPI
965 interrupt-controller;
966 #interrupt-cells = <3>
967 #mbox-cells = <2>;
968 };
969
970 qfprom: efuse@784000 {
971 compatible = "qcom,sm8
972 reg = <0 0x00784000 0
973 #address-cells = <1>;
974 #size-cells = <1>;
975
976 gpu_speed_bin: gpu-spe
977 reg = <0x19b 0
978 bits = <5 3>;
979 };
980 };
981
982 rng: rng@793000 {
983 compatible = "qcom,prn
984 reg = <0 0x00793000 0
985 clocks = <&gcc GCC_PRN
986 clock-names = "core";
987 };
988
989 gpi_dma2: dma-controller@80000
990 compatible = "qcom,sm8
991 reg = <0 0x00800000 0
992 interrupts = <GIC_SPI
993 <GIC_SPI
994 <GIC_SPI
995 <GIC_SPI
996 <GIC_SPI
997 <GIC_SPI
998 <GIC_SPI
999 <GIC_SPI
1000 <GIC_SPI
1001 <GIC_SPI
1002 dma-channels = <10>;
1003 dma-channel-mask = <0
1004 iommus = <&apps_smmu
1005 #dma-cells = <3>;
1006 status = "disabled";
1007 };
1008
1009 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge
1011 reg = <0x0 0x008c0000
1012 clock-names = "m-ahb"
1013 clocks = <&gcc GCC_QU
1014 <&gcc GCC_QU
1015 #address-cells = <2>;
1016 #size-cells = <2>;
1017 iommus = <&apps_smmu
1018 ranges;
1019 status = "disabled";
1020
1021 i2c14: i2c@880000 {
1022 compatible =
1023 reg = <0 0x00
1024 clock-names =
1025 clocks = <&gc
1026 pinctrl-names
1027 pinctrl-0 = <
1028 interrupts =
1029 dmas = <&gpi_
1030 <&gpi_
1031 dma-names = "
1032 power-domains
1033 interconnects
1034
1035
1036 interconnect-
1037
1038
1039 #address-cell
1040 #size-cells =
1041 status = "dis
1042 };
1043
1044 spi14: spi@880000 {
1045 compatible =
1046 reg = <0 0x00
1047 clock-names =
1048 clocks = <&gc
1049 interrupts =
1050 dmas = <&gpi_
1051 <&gpi_
1052 dma-names = "
1053 power-domains
1054 operating-poi
1055 interconnects
1056
1057
1058 interconnect-
1059
1060
1061 #address-cell
1062 #size-cells =
1063 status = "dis
1064 };
1065
1066 i2c15: i2c@884000 {
1067 compatible =
1068 reg = <0 0x00
1069 clock-names =
1070 clocks = <&gc
1071 pinctrl-names
1072 pinctrl-0 = <
1073 interrupts =
1074 dmas = <&gpi_
1075 <&gpi_
1076 dma-names = "
1077 power-domains
1078 interconnects
1079
1080
1081 interconnect-
1082
1083
1084 #address-cell
1085 #size-cells =
1086 status = "dis
1087 };
1088
1089 spi15: spi@884000 {
1090 compatible =
1091 reg = <0 0x00
1092 clock-names =
1093 clocks = <&gc
1094 interrupts =
1095 dmas = <&gpi_
1096 <&gpi_
1097 dma-names = "
1098 power-domains
1099 operating-poi
1100 interconnects
1101
1102
1103 interconnect-
1104
1105
1106 #address-cell
1107 #size-cells =
1108 status = "dis
1109 };
1110
1111 i2c16: i2c@888000 {
1112 compatible =
1113 reg = <0 0x00
1114 clock-names =
1115 clocks = <&gc
1116 pinctrl-names
1117 pinctrl-0 = <
1118 interrupts =
1119 dmas = <&gpi_
1120 <&gpi_
1121 dma-names = "
1122 power-domains
1123 interconnects
1124
1125
1126 interconnect-
1127
1128
1129 #address-cell
1130 #size-cells =
1131 status = "dis
1132 };
1133
1134 spi16: spi@888000 {
1135 compatible =
1136 reg = <0 0x00
1137 clock-names =
1138 clocks = <&gc
1139 interrupts =
1140 dmas = <&gpi_
1141 <&gpi_
1142 dma-names = "
1143 power-domains
1144 operating-poi
1145 interconnects
1146
1147
1148 interconnect-
1149
1150
1151 #address-cell
1152 #size-cells =
1153 status = "dis
1154 };
1155
1156 i2c17: i2c@88c000 {
1157 compatible =
1158 reg = <0 0x00
1159 clock-names =
1160 clocks = <&gc
1161 pinctrl-names
1162 pinctrl-0 = <
1163 interrupts =
1164 dmas = <&gpi_
1165 <&gpi_
1166 dma-names = "
1167 power-domains
1168 interconnects
1169
1170
1171 interconnect-
1172
1173
1174 #address-cell
1175 #size-cells =
1176 status = "dis
1177 };
1178
1179 spi17: spi@88c000 {
1180 compatible =
1181 reg = <0 0x00
1182 clock-names =
1183 clocks = <&gc
1184 interrupts =
1185 dmas = <&gpi_
1186 <&gpi_
1187 dma-names = "
1188 power-domains
1189 operating-poi
1190 interconnects
1191
1192
1193 interconnect-
1194
1195
1196 #address-cell
1197 #size-cells =
1198 status = "dis
1199 };
1200
1201 uart17: serial@88c000
1202 compatible =
1203 reg = <0 0x00
1204 clock-names =
1205 clocks = <&gc
1206 pinctrl-names
1207 pinctrl-0 = <
1208 interrupts =
1209 power-domains
1210 operating-poi
1211 interconnects
1212
1213 interconnect-
1214
1215 status = "dis
1216 };
1217
1218 i2c18: i2c@890000 {
1219 compatible =
1220 reg = <0 0x00
1221 clock-names =
1222 clocks = <&gc
1223 pinctrl-names
1224 pinctrl-0 = <
1225 interrupts =
1226 dmas = <&gpi_
1227 <&gpi_
1228 dma-names = "
1229 power-domains
1230 interconnects
1231
1232
1233 interconnect-
1234
1235
1236 #address-cell
1237 #size-cells =
1238 status = "dis
1239 };
1240
1241 spi18: spi@890000 {
1242 compatible =
1243 reg = <0 0x00
1244 clock-names =
1245 clocks = <&gc
1246 interrupts =
1247 dmas = <&gpi_
1248 <&gpi_
1249 dma-names = "
1250 power-domains
1251 operating-poi
1252 interconnects
1253
1254
1255 interconnect-
1256
1257
1258 #address-cell
1259 #size-cells =
1260 status = "dis
1261 };
1262
1263 uart18: serial@890000
1264 compatible =
1265 reg = <0 0x00
1266 clock-names =
1267 clocks = <&gc
1268 pinctrl-names
1269 pinctrl-0 = <
1270 interrupts =
1271 power-domains
1272 operating-poi
1273 interconnects
1274
1275 interconnect-
1276
1277 status = "dis
1278 };
1279
1280 i2c19: i2c@894000 {
1281 compatible =
1282 reg = <0 0x00
1283 clock-names =
1284 clocks = <&gc
1285 pinctrl-names
1286 pinctrl-0 = <
1287 interrupts =
1288 dmas = <&gpi_
1289 <&gpi_
1290 dma-names = "
1291 power-domains
1292 interconnects
1293
1294
1295 interconnect-
1296
1297
1298 #address-cell
1299 #size-cells =
1300 status = "dis
1301 };
1302
1303 spi19: spi@894000 {
1304 compatible =
1305 reg = <0 0x00
1306 clock-names =
1307 clocks = <&gc
1308 interrupts =
1309 dmas = <&gpi_
1310 <&gpi_
1311 dma-names = "
1312 power-domains
1313 operating-poi
1314 interconnects
1315
1316
1317 interconnect-
1318
1319
1320 #address-cell
1321 #size-cells =
1322 status = "dis
1323 };
1324 };
1325
1326 gpi_dma0: dma-controller@9000
1327 compatible = "qcom,sm
1328 reg = <0 0x00900000 0
1329 interrupts = <GIC_SPI
1330 <GIC_SPI
1331 <GIC_SPI
1332 <GIC_SPI
1333 <GIC_SPI
1334 <GIC_SPI
1335 <GIC_SPI
1336 <GIC_SPI
1337 <GIC_SPI
1338 <GIC_SPI
1339 <GIC_SPI
1340 <GIC_SPI
1341 <GIC_SPI
1342 dma-channels = <15>;
1343 dma-channel-mask = <0
1344 iommus = <&apps_smmu
1345 #dma-cells = <3>;
1346 status = "disabled";
1347 };
1348
1349 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge
1351 reg = <0x0 0x009c0000
1352 clock-names = "m-ahb"
1353 clocks = <&gcc GCC_QU
1354 <&gcc GCC_QU
1355 #address-cells = <2>;
1356 #size-cells = <2>;
1357 iommus = <&apps_smmu
1358 ranges;
1359 status = "disabled";
1360
1361 i2c0: i2c@980000 {
1362 compatible =
1363 reg = <0 0x00
1364 clock-names =
1365 clocks = <&gc
1366 pinctrl-names
1367 pinctrl-0 = <
1368 interrupts =
1369 dmas = <&gpi_
1370 <&gpi_
1371 dma-names = "
1372 power-domains
1373 interconnects
1374
1375
1376 interconnect-
1377
1378
1379 #address-cell
1380 #size-cells =
1381 status = "dis
1382 };
1383
1384 spi0: spi@980000 {
1385 compatible =
1386 reg = <0 0x00
1387 clock-names =
1388 clocks = <&gc
1389 interrupts =
1390 dmas = <&gpi_
1391 <&gpi_
1392 dma-names = "
1393 power-domains
1394 operating-poi
1395 interconnects
1396
1397
1398 interconnect-
1399
1400
1401 #address-cell
1402 #size-cells =
1403 status = "dis
1404 };
1405
1406 i2c1: i2c@984000 {
1407 compatible =
1408 reg = <0 0x00
1409 clock-names =
1410 clocks = <&gc
1411 pinctrl-names
1412 pinctrl-0 = <
1413 interrupts =
1414 dmas = <&gpi_
1415 <&gpi_
1416 dma-names = "
1417 power-domains
1418 interconnects
1419
1420
1421 interconnect-
1422
1423
1424 #address-cell
1425 #size-cells =
1426 status = "dis
1427 };
1428
1429 spi1: spi@984000 {
1430 compatible =
1431 reg = <0 0x00
1432 clock-names =
1433 clocks = <&gc
1434 interrupts =
1435 dmas = <&gpi_
1436 <&gpi_
1437 dma-names = "
1438 power-domains
1439 operating-poi
1440 interconnects
1441
1442
1443 interconnect-
1444
1445
1446 #address-cell
1447 #size-cells =
1448 status = "dis
1449 };
1450
1451 i2c2: i2c@988000 {
1452 compatible =
1453 reg = <0 0x00
1454 clock-names =
1455 clocks = <&gc
1456 pinctrl-names
1457 pinctrl-0 = <
1458 interrupts =
1459 dmas = <&gpi_
1460 <&gpi_
1461 dma-names = "
1462 power-domains
1463 interconnects
1464
1465
1466 interconnect-
1467
1468
1469 #address-cell
1470 #size-cells =
1471 status = "dis
1472 };
1473
1474 spi2: spi@988000 {
1475 compatible =
1476 reg = <0 0x00
1477 clock-names =
1478 clocks = <&gc
1479 interrupts =
1480 dmas = <&gpi_
1481 <&gpi_
1482 dma-names = "
1483 power-domains
1484 operating-poi
1485 interconnects
1486
1487
1488 interconnect-
1489
1490
1491 #address-cell
1492 #size-cells =
1493 status = "dis
1494 };
1495
1496 uart2: serial@988000
1497 compatible =
1498 reg = <0 0x00
1499 clock-names =
1500 clocks = <&gc
1501 pinctrl-names
1502 pinctrl-0 = <
1503 interrupts =
1504 power-domains
1505 operating-poi
1506 interconnects
1507
1508 interconnect-
1509
1510 status = "dis
1511 };
1512
1513 i2c3: i2c@98c000 {
1514 compatible =
1515 reg = <0 0x00
1516 clock-names =
1517 clocks = <&gc
1518 pinctrl-names
1519 pinctrl-0 = <
1520 interrupts =
1521 dmas = <&gpi_
1522 <&gpi_
1523 dma-names = "
1524 power-domains
1525 interconnects
1526
1527
1528 interconnect-
1529
1530
1531 #address-cell
1532 #size-cells =
1533 status = "dis
1534 };
1535
1536 spi3: spi@98c000 {
1537 compatible =
1538 reg = <0 0x00
1539 clock-names =
1540 clocks = <&gc
1541 interrupts =
1542 dmas = <&gpi_
1543 <&gpi_
1544 dma-names = "
1545 power-domains
1546 operating-poi
1547 interconnects
1548
1549
1550 interconnect-
1551
1552
1553 #address-cell
1554 #size-cells =
1555 status = "dis
1556 };
1557
1558 i2c4: i2c@990000 {
1559 compatible =
1560 reg = <0 0x00
1561 clock-names =
1562 clocks = <&gc
1563 pinctrl-names
1564 pinctrl-0 = <
1565 interrupts =
1566 dmas = <&gpi_
1567 <&gpi_
1568 dma-names = "
1569 power-domains
1570 interconnects
1571
1572
1573 interconnect-
1574
1575
1576 #address-cell
1577 #size-cells =
1578 status = "dis
1579 };
1580
1581 spi4: spi@990000 {
1582 compatible =
1583 reg = <0 0x00
1584 clock-names =
1585 clocks = <&gc
1586 interrupts =
1587 dmas = <&gpi_
1588 <&gpi_
1589 dma-names = "
1590 power-domains
1591 operating-poi
1592 interconnects
1593
1594
1595 interconnect-
1596
1597
1598 #address-cell
1599 #size-cells =
1600 status = "dis
1601 };
1602
1603 i2c5: i2c@994000 {
1604 compatible =
1605 reg = <0 0x00
1606 clock-names =
1607 clocks = <&gc
1608 pinctrl-names
1609 pinctrl-0 = <
1610 interrupts =
1611 dmas = <&gpi_
1612 <&gpi_
1613 dma-names = "
1614 power-domains
1615 interconnects
1616
1617
1618 interconnect-
1619
1620
1621 #address-cell
1622 #size-cells =
1623 status = "dis
1624 };
1625
1626 spi5: spi@994000 {
1627 compatible =
1628 reg = <0 0x00
1629 clock-names =
1630 clocks = <&gc
1631 interrupts =
1632 dmas = <&gpi_
1633 <&gpi_
1634 dma-names = "
1635 power-domains
1636 operating-poi
1637 interconnects
1638
1639
1640 interconnect-
1641
1642
1643 #address-cell
1644 #size-cells =
1645 status = "dis
1646 };
1647
1648 i2c6: i2c@998000 {
1649 compatible =
1650 reg = <0 0x00
1651 clock-names =
1652 clocks = <&gc
1653 pinctrl-names
1654 pinctrl-0 = <
1655 interrupts =
1656 dmas = <&gpi_
1657 <&gpi_
1658 dma-names = "
1659 power-domains
1660 interconnects
1661
1662
1663 interconnect-
1664
1665
1666 #address-cell
1667 #size-cells =
1668 status = "dis
1669 };
1670
1671 spi6: spi@998000 {
1672 compatible =
1673 reg = <0 0x00
1674 clock-names =
1675 clocks = <&gc
1676 interrupts =
1677 dmas = <&gpi_
1678 <&gpi_
1679 dma-names = "
1680 power-domains
1681 operating-poi
1682 interconnects
1683
1684
1685 interconnect-
1686
1687
1688 #address-cell
1689 #size-cells =
1690 status = "dis
1691 };
1692
1693 uart6: serial@998000
1694 compatible =
1695 reg = <0 0x00
1696 clock-names =
1697 clocks = <&gc
1698 pinctrl-names
1699 pinctrl-0 = <
1700 interrupts =
1701 power-domains
1702 operating-poi
1703 interconnects
1704
1705 interconnect-
1706
1707 status = "dis
1708 };
1709
1710 i2c7: i2c@99c000 {
1711 compatible =
1712 reg = <0 0x00
1713 clock-names =
1714 clocks = <&gc
1715 pinctrl-names
1716 pinctrl-0 = <
1717 interrupts =
1718 dmas = <&gpi_
1719 <&gpi_
1720 dma-names = "
1721 power-domains
1722 interconnects
1723
1724
1725 interconnect-
1726
1727
1728 #address-cell
1729 #size-cells =
1730 status = "dis
1731 };
1732
1733 spi7: spi@99c000 {
1734 compatible =
1735 reg = <0 0x00
1736 clock-names =
1737 clocks = <&gc
1738 interrupts =
1739 dmas = <&gpi_
1740 <&gpi_
1741 dma-names = "
1742 power-domains
1743 operating-poi
1744 interconnects
1745
1746
1747 interconnect-
1748
1749
1750 #address-cell
1751 #size-cells =
1752 status = "dis
1753 };
1754 };
1755
1756 gpi_dma1: dma-controller@a000
1757 compatible = "qcom,sm
1758 reg = <0 0x00a00000 0
1759 interrupts = <GIC_SPI
1760 <GIC_SPI
1761 <GIC_SPI
1762 <GIC_SPI
1763 <GIC_SPI
1764 <GIC_SPI
1765 <GIC_SPI
1766 <GIC_SPI
1767 <GIC_SPI
1768 <GIC_SPI
1769 dma-channels = <10>;
1770 dma-channel-mask = <0
1771 iommus = <&apps_smmu
1772 #dma-cells = <3>;
1773 status = "disabled";
1774 };
1775
1776 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge
1778 reg = <0x0 0x00ac0000
1779 clock-names = "m-ahb"
1780 clocks = <&gcc GCC_QU
1781 <&gcc GCC_QU
1782 #address-cells = <2>;
1783 #size-cells = <2>;
1784 iommus = <&apps_smmu
1785 ranges;
1786 status = "disabled";
1787
1788 i2c8: i2c@a80000 {
1789 compatible =
1790 reg = <0 0x00
1791 clock-names =
1792 clocks = <&gc
1793 pinctrl-names
1794 pinctrl-0 = <
1795 interrupts =
1796 dmas = <&gpi_
1797 <&gpi_
1798 dma-names = "
1799 power-domains
1800 interconnects
1801
1802
1803 interconnect-
1804
1805
1806 #address-cell
1807 #size-cells =
1808 status = "dis
1809 };
1810
1811 spi8: spi@a80000 {
1812 compatible =
1813 reg = <0 0x00
1814 clock-names =
1815 clocks = <&gc
1816 interrupts =
1817 dmas = <&gpi_
1818 <&gpi_
1819 dma-names = "
1820 power-domains
1821 operating-poi
1822 interconnects
1823
1824
1825 interconnect-
1826
1827
1828 #address-cell
1829 #size-cells =
1830 status = "dis
1831 };
1832
1833 i2c9: i2c@a84000 {
1834 compatible =
1835 reg = <0 0x00
1836 clock-names =
1837 clocks = <&gc
1838 pinctrl-names
1839 pinctrl-0 = <
1840 interrupts =
1841 dmas = <&gpi_
1842 <&gpi_
1843 dma-names = "
1844 power-domains
1845 interconnects
1846
1847
1848 interconnect-
1849
1850
1851 #address-cell
1852 #size-cells =
1853 status = "dis
1854 };
1855
1856 spi9: spi@a84000 {
1857 compatible =
1858 reg = <0 0x00
1859 clock-names =
1860 clocks = <&gc
1861 interrupts =
1862 dmas = <&gpi_
1863 <&gpi_
1864 dma-names = "
1865 power-domains
1866 operating-poi
1867 interconnects
1868
1869
1870 interconnect-
1871
1872
1873 #address-cell
1874 #size-cells =
1875 status = "dis
1876 };
1877
1878 i2c10: i2c@a88000 {
1879 compatible =
1880 reg = <0 0x00
1881 clock-names =
1882 clocks = <&gc
1883 pinctrl-names
1884 pinctrl-0 = <
1885 interrupts =
1886 dmas = <&gpi_
1887 <&gpi_
1888 dma-names = "
1889 power-domains
1890 interconnects
1891
1892
1893 interconnect-
1894
1895
1896 #address-cell
1897 #size-cells =
1898 status = "dis
1899 };
1900
1901 spi10: spi@a88000 {
1902 compatible =
1903 reg = <0 0x00
1904 clock-names =
1905 clocks = <&gc
1906 interrupts =
1907 dmas = <&gpi_
1908 <&gpi_
1909 dma-names = "
1910 power-domains
1911 operating-poi
1912 interconnects
1913
1914
1915 interconnect-
1916
1917
1918 #address-cell
1919 #size-cells =
1920 status = "dis
1921 };
1922
1923 i2c11: i2c@a8c000 {
1924 compatible =
1925 reg = <0 0x00
1926 clock-names =
1927 clocks = <&gc
1928 pinctrl-names
1929 pinctrl-0 = <
1930 interrupts =
1931 dmas = <&gpi_
1932 <&gpi_
1933 dma-names = "
1934 power-domains
1935 interconnects
1936
1937
1938 interconnect-
1939
1940
1941 #address-cell
1942 #size-cells =
1943 status = "dis
1944 };
1945
1946 spi11: spi@a8c000 {
1947 compatible =
1948 reg = <0 0x00
1949 clock-names =
1950 clocks = <&gc
1951 interrupts =
1952 dmas = <&gpi_
1953 <&gpi_
1954 dma-names = "
1955 power-domains
1956 operating-poi
1957 interconnects
1958
1959
1960 interconnect-
1961
1962
1963 #address-cell
1964 #size-cells =
1965 status = "dis
1966 };
1967
1968 i2c12: i2c@a90000 {
1969 compatible =
1970 reg = <0 0x00
1971 clock-names =
1972 clocks = <&gc
1973 pinctrl-names
1974 pinctrl-0 = <
1975 interrupts =
1976 dmas = <&gpi_
1977 <&gpi_
1978 dma-names = "
1979 power-domains
1980 interconnects
1981
1982
1983 interconnect-
1984
1985
1986 #address-cell
1987 #size-cells =
1988 status = "dis
1989 };
1990
1991 spi12: spi@a90000 {
1992 compatible =
1993 reg = <0 0x00
1994 clock-names =
1995 clocks = <&gc
1996 interrupts =
1997 dmas = <&gpi_
1998 <&gpi_
1999 dma-names = "
2000 power-domains
2001 operating-poi
2002 interconnects
2003
2004
2005 interconnect-
2006
2007
2008 #address-cell
2009 #size-cells =
2010 status = "dis
2011 };
2012
2013 uart12: serial@a90000
2014 compatible =
2015 reg = <0x0 0x
2016 clock-names =
2017 clocks = <&gc
2018 pinctrl-names
2019 pinctrl-0 = <
2020 interrupts =
2021 power-domains
2022 operating-poi
2023 interconnects
2024
2025 interconnect-
2026
2027 status = "dis
2028 };
2029
2030 i2c13: i2c@a94000 {
2031 compatible =
2032 reg = <0 0x00
2033 clock-names =
2034 clocks = <&gc
2035 pinctrl-names
2036 pinctrl-0 = <
2037 interrupts =
2038 dmas = <&gpi_
2039 <&gpi_
2040 dma-names = "
2041 power-domains
2042 interconnects
2043
2044
2045 interconnect-
2046
2047
2048 #address-cell
2049 #size-cells =
2050 status = "dis
2051 };
2052
2053 spi13: spi@a94000 {
2054 compatible =
2055 reg = <0 0x00
2056 clock-names =
2057 clocks = <&gc
2058 interrupts =
2059 dmas = <&gpi_
2060 <&gpi_
2061 dma-names = "
2062 power-domains
2063 operating-poi
2064 interconnects
2065
2066
2067 interconnect-
2068
2069
2070 #address-cell
2071 #size-cells =
2072 status = "dis
2073 };
2074 };
2075
2076 config_noc: interconnect@1500
2077 compatible = "qcom,sm
2078 reg = <0 0x01500000 0
2079 #interconnect-cells =
2080 qcom,bcm-voters = <&a
2081 };
2082
2083 system_noc: interconnect@1620
2084 compatible = "qcom,sm
2085 reg = <0 0x01620000 0
2086 #interconnect-cells =
2087 qcom,bcm-voters = <&a
2088 };
2089
2090 mc_virt: interconnect@163d000
2091 compatible = "qcom,sm
2092 reg = <0 0x0163d000 0
2093 #interconnect-cells =
2094 qcom,bcm-voters = <&a
2095 };
2096
2097 aggre1_noc: interconnect@16e0
2098 compatible = "qcom,sm
2099 reg = <0 0x016e0000 0
2100 #interconnect-cells =
2101 qcom,bcm-voters = <&a
2102 };
2103
2104 aggre2_noc: interconnect@1700
2105 compatible = "qcom,sm
2106 reg = <0 0x01700000 0
2107 #interconnect-cells =
2108 qcom,bcm-voters = <&a
2109 };
2110
2111 compute_noc: interconnect@173
2112 compatible = "qcom,sm
2113 reg = <0 0x01733000 0
2114 #interconnect-cells =
2115 qcom,bcm-voters = <&a
2116 };
2117
2118 mmss_noc: interconnect@174000
2119 compatible = "qcom,sm
2120 reg = <0 0x01740000 0
2121 #interconnect-cells =
2122 qcom,bcm-voters = <&a
2123 };
2124
2125 pcie0: pcie@1c00000 {
2126 compatible = "qcom,pc
2127 reg = <0 0x01c00000 0
2128 <0 0x60000000 0
2129 <0 0x60000f20 0
2130 <0 0x60001000 0
2131 <0 0x60100000 0
2132 <0 0x01c03000 0
2133 reg-names = "parf", "
2134 device_type = "pci";
2135 linux,pci-domain = <0
2136 bus-range = <0x00 0xf
2137 num-lanes = <1>;
2138
2139 #address-cells = <3>;
2140 #size-cells = <2>;
2141
2142 ranges = <0x01000000
2143 <0x02000000
2144
2145 interrupts = <GIC_SPI
2146 <GIC_SPI
2147 <GIC_SPI
2148 <GIC_SPI
2149 <GIC_SPI
2150 <GIC_SPI
2151 <GIC_SPI
2152 <GIC_SPI
2153 interrupt-names = "ms
2154 "ms
2155 "ms
2156 "ms
2157 "ms
2158 "ms
2159 "ms
2160 "ms
2161 #interrupt-cells = <1
2162 interrupt-map-mask =
2163 interrupt-map = <0 0
2164 <0 0
2165 <0 0
2166 <0 0
2167
2168 clocks = <&gcc GCC_PC
2169 <&gcc GCC_PC
2170 <&gcc GCC_PC
2171 <&gcc GCC_PC
2172 <&gcc GCC_PC
2173 <&gcc GCC_PC
2174 <&gcc GCC_AG
2175 <&gcc GCC_DD
2176 clock-names = "pipe",
2177 "aux",
2178 "cfg",
2179 "bus_ma
2180 "bus_sl
2181 "slave_
2182 "tbu",
2183 "ddrss_
2184
2185 iommu-map = <0x0 &a
2186 <0x100 &a
2187
2188 resets = <&gcc GCC_PC
2189 reset-names = "pci";
2190
2191 power-domains = <&gcc
2192
2193 phys = <&pcie0_phy>;
2194 phy-names = "pciephy"
2195
2196 perst-gpios = <&tlmm
2197 wake-gpios = <&tlmm 8
2198
2199 pinctrl-names = "defa
2200 pinctrl-0 = <&pcie0_d
2201 dma-coherent;
2202
2203 status = "disabled";
2204
2205 pcieport0: pcie@0 {
2206 device_type =
2207 reg = <0x0 0x
2208 bus-range = <
2209
2210 #address-cell
2211 #size-cells =
2212 ranges;
2213 };
2214 };
2215
2216 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm
2218 reg = <0 0x01c06000 0
2219
2220 clocks = <&gcc GCC_PC
2221 <&gcc GCC_PC
2222 <&gcc GCC_PC
2223 <&gcc GCC_PC
2224 <&gcc GCC_PC
2225 clock-names = "aux",
2226 "cfg_ah
2227 "ref",
2228 "refgen
2229 "pipe";
2230
2231 clock-output-names =
2232 #clock-cells = <0>;
2233
2234 #phy-cells = <0>;
2235
2236 resets = <&gcc GCC_PC
2237 reset-names = "phy";
2238
2239 assigned-clocks = <&g
2240 assigned-clock-rates
2241
2242 status = "disabled";
2243 };
2244
2245 pcie1: pcie@1c08000 {
2246 compatible = "qcom,pc
2247 reg = <0 0x01c08000 0
2248 <0 0x40000000 0
2249 <0 0x40000f20 0
2250 <0 0x40001000 0
2251 <0 0x40100000 0
2252 <0 0x01c0b000 0
2253 reg-names = "parf", "
2254 device_type = "pci";
2255 linux,pci-domain = <1
2256 bus-range = <0x00 0xf
2257 num-lanes = <2>;
2258
2259 #address-cells = <3>;
2260 #size-cells = <2>;
2261
2262 ranges = <0x01000000
2263 <0x02000000
2264
2265 interrupts = <GIC_SPI
2266 <GIC_SPI
2267 <GIC_SPI
2268 <GIC_SPI
2269 <GIC_SPI
2270 <GIC_SPI
2271 <GIC_SPI
2272 <GIC_SPI
2273 interrupt-names = "ms
2274 "ms
2275 "ms
2276 "ms
2277 "ms
2278 "ms
2279 "ms
2280 "ms
2281 #interrupt-cells = <1
2282 interrupt-map-mask =
2283 interrupt-map = <0 0
2284 <0 0
2285 <0 0
2286 <0 0
2287
2288 clocks = <&gcc GCC_PC
2289 <&gcc GCC_PC
2290 <&gcc GCC_PC
2291 <&gcc GCC_PC
2292 <&gcc GCC_PC
2293 <&gcc GCC_PC
2294 <&gcc GCC_PC
2295 <&gcc GCC_AG
2296 <&gcc GCC_DD
2297 clock-names = "pipe",
2298 "aux",
2299 "cfg",
2300 "bus_ma
2301 "bus_sl
2302 "slave_
2303 "ref",
2304 "tbu",
2305 "ddrss_
2306
2307 assigned-clocks = <&g
2308 assigned-clock-rates
2309
2310 iommu-map = <0x0 &a
2311 <0x100 &a
2312
2313 resets = <&gcc GCC_PC
2314 reset-names = "pci";
2315
2316 power-domains = <&gcc
2317
2318 phys = <&pcie1_phy>;
2319 phy-names = "pciephy"
2320
2321 perst-gpios = <&tlmm
2322 wake-gpios = <&tlmm 8
2323
2324 pinctrl-names = "defa
2325 pinctrl-0 = <&pcie1_d
2326 dma-coherent;
2327
2328 status = "disabled";
2329
2330 pcie@0 {
2331 device_type =
2332 reg = <0x0 0x
2333 bus-range = <
2334
2335 #address-cell
2336 #size-cells =
2337 ranges;
2338 };
2339 };
2340
2341 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm
2343 reg = <0 0x01c0e000 0
2344
2345 clocks = <&gcc GCC_PC
2346 <&gcc GCC_PC
2347 <&gcc GCC_PC
2348 <&gcc GCC_PC
2349 <&gcc GCC_PC
2350 clock-names = "aux",
2351 "cfg_ah
2352 "ref",
2353 "refgen
2354 "pipe";
2355
2356 clock-output-names =
2357 #clock-cells = <0>;
2358
2359 #phy-cells = <0>;
2360
2361 resets = <&gcc GCC_PC
2362 reset-names = "phy";
2363
2364 assigned-clocks = <&g
2365 assigned-clock-rates
2366
2367 status = "disabled";
2368 };
2369
2370 pcie2: pcie@1c10000 {
2371 compatible = "qcom,pc
2372 reg = <0 0x01c10000 0
2373 <0 0x64000000 0
2374 <0 0x64000f20 0
2375 <0 0x64001000 0
2376 <0 0x64100000 0
2377 <0 0x01c13000 0
2378 reg-names = "parf", "
2379 device_type = "pci";
2380 linux,pci-domain = <2
2381 bus-range = <0x00 0xf
2382 num-lanes = <2>;
2383
2384 #address-cells = <3>;
2385 #size-cells = <2>;
2386
2387 ranges = <0x01000000
2388 <0x02000000
2389
2390 interrupts = <GIC_SPI
2391 <GIC_SPI
2392 <GIC_SPI
2393 <GIC_SPI
2394 <GIC_SPI
2395 <GIC_SPI
2396 <GIC_SPI
2397 <GIC_SPI
2398 interrupt-names = "ms
2399 "ms
2400 "ms
2401 "ms
2402 "ms
2403 "ms
2404 "ms
2405 "ms
2406 #interrupt-cells = <1
2407 interrupt-map-mask =
2408 interrupt-map = <0 0
2409 <0 0
2410 <0 0
2411 <0 0
2412
2413 clocks = <&gcc GCC_PC
2414 <&gcc GCC_PC
2415 <&gcc GCC_PC
2416 <&gcc GCC_PC
2417 <&gcc GCC_PC
2418 <&gcc GCC_PC
2419 <&gcc GCC_PC
2420 <&gcc GCC_AG
2421 <&gcc GCC_DD
2422 clock-names = "pipe",
2423 "aux",
2424 "cfg",
2425 "bus_ma
2426 "bus_sl
2427 "slave_
2428 "ref",
2429 "tbu",
2430 "ddrss_
2431
2432 assigned-clocks = <&g
2433 assigned-clock-rates
2434
2435 iommu-map = <0x0 &a
2436 <0x100 &a
2437
2438 resets = <&gcc GCC_PC
2439 reset-names = "pci";
2440
2441 power-domains = <&gcc
2442
2443 phys = <&pcie2_phy>;
2444 phy-names = "pciephy"
2445
2446 perst-gpios = <&tlmm
2447 wake-gpios = <&tlmm 8
2448
2449 pinctrl-names = "defa
2450 pinctrl-0 = <&pcie2_d
2451 dma-coherent;
2452
2453 status = "disabled";
2454
2455 pcie@0 {
2456 device_type =
2457 reg = <0x0 0x
2458 bus-range = <
2459
2460 #address-cell
2461 #size-cells =
2462 ranges;
2463 };
2464 };
2465
2466 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm
2468 reg = <0 0x01c16000 0
2469
2470 clocks = <&gcc GCC_PC
2471 <&gcc GCC_PC
2472 <&gcc GCC_PC
2473 <&gcc GCC_PC
2474 <&gcc GCC_PC
2475 clock-names = "aux",
2476 "cfg_ah
2477 "ref",
2478 "refgen
2479 "pipe";
2480
2481 clock-output-names =
2482 #clock-cells = <0>;
2483
2484 #phy-cells = <0>;
2485
2486 resets = <&gcc GCC_PC
2487 reset-names = "phy";
2488
2489 assigned-clocks = <&g
2490 assigned-clock-rates
2491
2492 status = "disabled";
2493 };
2494
2495 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm
2497 "jedec,u
2498 reg = <0 0x01d84000 0
2499 interrupts = <GIC_SPI
2500 phys = <&ufs_mem_phy>
2501 phy-names = "ufsphy";
2502 lanes-per-direction =
2503 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF
2505 reset-names = "rst";
2506
2507 power-domains = <&gcc
2508
2509 iommus = <&apps_smmu
2510
2511 clock-names =
2512 "core_clk",
2513 "bus_aggr_clk
2514 "iface_clk",
2515 "core_clk_uni
2516 "ref_clk",
2517 "tx_lane0_syn
2518 "rx_lane0_syn
2519 "rx_lane1_syn
2520 clocks =
2521 <&gcc GCC_UFS
2522 <&gcc GCC_AGG
2523 <&gcc GCC_UFS
2524 <&gcc GCC_UFS
2525 <&rpmhcc RPMH
2526 <&gcc GCC_UFS
2527 <&gcc GCC_UFS
2528 <&gcc GCC_UFS
2529
2530 operating-points-v2 =
2531
2532 interconnects = <&agg
2533 <&gem
2534 interconnect-names =
2535
2536 status = "disabled";
2537
2538 ufs_opp_table: opp-ta
2539 compatible =
2540
2541 opp-37500000
2542 opp-h
2543
2544
2545
2546
2547
2548
2549
2550 requi
2551 };
2552
2553 opp-300000000
2554 opp-h
2555
2556
2557
2558
2559
2560
2561
2562 requi
2563 };
2564 };
2565 };
2566
2567 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm
2569 reg = <0 0x01d87000 0
2570
2571 clocks = <&rpmhcc RPM
2572 <&gcc GCC_UF
2573 <&gcc GCC_UF
2574 clock-names = "ref",
2575 "ref_au
2576 "qref";
2577
2578 resets = <&ufs_mem_hc
2579 reset-names = "ufsphy
2580
2581 power-domains = <&gcc
2582
2583 #phy-cells = <0>;
2584
2585 status = "disabled";
2586 };
2587
2588 cryptobam: dma-controller@1dc
2589 compatible = "qcom,ba
2590 reg = <0 0x01dc4000 0
2591 interrupts = <GIC_SPI
2592 #dma-cells = <1>;
2593 qcom,ee = <0>;
2594 qcom,controlled-remot
2595 num-channels = <8>;
2596 qcom,num-ees = <2>;
2597 iommus = <&apps_smmu
2598 <&apps_smmu
2599 <&apps_smmu
2600 <&apps_smmu
2601 <&apps_smmu
2602 <&apps_smmu
2603 };
2604
2605 crypto: crypto@1dfa000 {
2606 compatible = "qcom,sm
2607 reg = <0 0x01dfa000 0
2608 dmas = <&cryptobam 4>
2609 dma-names = "rx", "tx
2610 iommus = <&apps_smmu
2611 <&apps_smmu
2612 <&apps_smmu
2613 <&apps_smmu
2614 <&apps_smmu
2615 <&apps_smmu
2616 interconnects = <&agg
2617 interconnect-names =
2618 };
2619
2620 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc
2622 reg = <0x0 0x01f40000
2623 #hwlock-cells = <1>;
2624 };
2625
2626 tcsr: syscon@1fc0000 {
2627 compatible = "qcom,sm
2628 reg = <0x0 0x1fc0000
2629 };
2630
2631 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm
2633 reg = <0 0x03240000 0
2634 clocks = <&q6afecc LP
2635 <&q6afecc LP
2636 <&q6afecc LP
2637 <&q6afecc LP
2638 <&vamacro>;
2639
2640 clock-names = "mclk",
2641
2642 #clock-cells = <0>;
2643 clock-output-names =
2644 #sound-dai-cells = <1
2645
2646 pinctrl-names = "defa
2647 pinctrl-0 = <&wsa_swr
2648
2649 status = "disabled";
2650 };
2651
2652 swr0: soundwire@3250000 {
2653 reg = <0 0x03250000 0
2654 compatible = "qcom,so
2655 interrupts = <GIC_SPI
2656 clocks = <&wsamacro>;
2657 clock-names = "iface"
2658
2659 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6>
2661
2662 qcom,ports-sinterval-
2663 qcom,ports-offset1 =
2664 qcom,ports-offset2 =
2665 qcom,ports-block-pack
2666
2667 #sound-dai-cells = <1
2668 #address-cells = <2>;
2669 #size-cells = <0>;
2670
2671 status = "disabled";
2672 };
2673
2674 vamacro: codec@3370000 {
2675 compatible = "qcom,sm
2676 reg = <0 0x03370000 0
2677 clocks = <&q6afecc LP
2678 <&q6afecc LPA
2679 <&q6afecc LPA
2680
2681 clock-names = "mclk",
2682
2683 #clock-cells = <0>;
2684 clock-output-names =
2685 #sound-dai-cells = <1
2686 };
2687
2688 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa
2690 pinctrl-0 = <&rx_swr_
2691 compatible = "qcom,sm
2692 reg = <0 0x03200000 0
2693 status = "disabled";
2694
2695 clocks = <&q6afecc LP
2696 <&q6afecc LPA
2697 <&q6afecc LPA
2698 <&q6afecc LPA
2699 <&vamacro>;
2700
2701 clock-names = "mclk",
2702
2703 #clock-cells = <0>;
2704 clock-output-names =
2705 #sound-dai-cells = <1
2706 };
2707
2708 swr1: soundwire@3210000 {
2709 reg = <0 0x03210000 0
2710 compatible = "qcom,so
2711 status = "disabled";
2712 interrupts = <GIC_SPI
2713 clocks = <&rxmacro>;
2714 clock-names = "iface"
2715 label = "RX";
2716 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5>
2718
2719 qcom,ports-sinterval-
2720 qcom,ports-offset1 =
2721 qcom,ports-offset2 =
2722 qcom,ports-hstart =
2723 qcom,ports-hstop =
2724 qcom,ports-word-lengt
2725 qcom,ports-block-pack
2726 qcom,ports-lane-contr
2727 qcom,ports-block-grou
2728
2729 #sound-dai-cells = <1
2730 #address-cells = <2>;
2731 #size-cells = <0>;
2732 };
2733
2734 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa
2736 pinctrl-0 = <&tx_swr_
2737 compatible = "qcom,sm
2738 reg = <0 0x03220000 0
2739 status = "disabled";
2740
2741 clocks = <&q6afecc LP
2742 <&q6afecc LP
2743 <&q6afecc LP
2744 <&q6afecc LP
2745 <&vamacro>;
2746
2747 clock-names = "mclk",
2748
2749 #clock-cells = <0>;
2750 clock-output-names =
2751 #sound-dai-cells = <1
2752 };
2753
2754 /* tx macro */
2755 swr2: soundwire@3230000 {
2756 reg = <0 0x03230000 0
2757 compatible = "qcom,so
2758 interrupts = <GIC_SPI
2759 interrupt-names = "co
2760 status = "disabled";
2761
2762 clocks = <&txmacro>;
2763 clock-names = "iface"
2764 label = "TX";
2765
2766 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0>
2768 qcom,ports-sinterval-
2769 qcom,ports-offset1 =
2770 qcom,ports-offset2 =
2771 qcom,ports-block-pack
2772 qcom,ports-hstart =
2773 qcom,ports-hstop =
2774 qcom,ports-word-lengt
2775 qcom,ports-block-grou
2776 qcom,ports-lane-contr
2777 #sound-dai-cells = <1
2778 #address-cells = <2>;
2779 #size-cells = <0>;
2780 };
2781
2782 lpass_tlmm: pinctrl@33c0000 {
2783 compatible = "qcom,sm
2784 reg = <0 0x033c0000 0
2785 <0 0x03550000 0
2786 gpio-controller;
2787 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass
2789
2790 clocks = <&q6afecc LP
2791 <&q6afecc LPA
2792 clock-names = "core",
2793
2794 wsa_swr_active: wsa-s
2795 clk-pins {
2796 pins
2797 funct
2798 drive
2799 slew-
2800 bias-
2801 };
2802
2803 data-pins {
2804 pins
2805 funct
2806 drive
2807 slew-
2808 bias-
2809 };
2810 };
2811
2812 wsa_swr_sleep: wsa-sw
2813 clk-pins {
2814 pins
2815 funct
2816 drive
2817 bias-
2818 };
2819
2820 data-pins {
2821 pins
2822 funct
2823 drive
2824 bias-
2825 };
2826 };
2827
2828 dmic01_active: dmic01
2829 clk-pins {
2830 pins
2831 funct
2832 drive
2833 outpu
2834 };
2835 data-pins {
2836 pins
2837 funct
2838 drive
2839 };
2840 };
2841
2842 dmic01_sleep: dmic01-
2843 clk-pins {
2844 pins
2845 funct
2846 drive
2847 bias-
2848 outpu
2849 };
2850
2851 data-pins {
2852 pins
2853 funct
2854 drive
2855 bias-
2856 };
2857 };
2858
2859 rx_swr_active: rx-swr
2860 clk-pins {
2861 pins
2862 funct
2863 drive
2864 slew-
2865 bias-
2866 };
2867
2868 data-pins {
2869 pins
2870 funct
2871 drive
2872 slew-
2873 bias-
2874 };
2875 };
2876
2877 tx_swr_active: tx-swr
2878 clk-pins {
2879 pins
2880 funct
2881 drive
2882 slew-
2883 bias-
2884 };
2885
2886 data-pins {
2887 pins
2888 funct
2889 drive
2890 slew-
2891 bias-
2892 };
2893 };
2894
2895 tx_swr_sleep: tx-swr-
2896 clk-pins {
2897 pins
2898 funct
2899 drive
2900 bias-
2901 };
2902
2903 data1-pins {
2904 pins
2905 funct
2906 drive
2907 bias-
2908 };
2909
2910 data2-pins {
2911 pins
2912 funct
2913 drive
2914 bias-
2915 };
2916 };
2917 };
2918
2919 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad
2921 "qcom,ad
2922
2923 reg = <0 0x03d00000 0
2924 reg-names = "kgsl_3d0
2925
2926 interrupts = <GIC_SPI
2927
2928 iommus = <&adreno_smm
2929
2930 operating-points-v2 =
2931
2932 qcom,gmu = <&gmu>;
2933
2934 nvmem-cells = <&gpu_s
2935 nvmem-cell-names = "s
2936 #cooling-cells = <2>;
2937
2938 status = "disabled";
2939
2940 zap-shader {
2941 memory-region
2942 };
2943
2944 gpu_opp_table: opp-ta
2945 compatible =
2946
2947 opp-670000000
2948 opp-h
2949 opp-l
2950 opp-s
2951 };
2952
2953 opp-587000000
2954 opp-h
2955 opp-l
2956 opp-s
2957 };
2958
2959 opp-525000000
2960 opp-h
2961 opp-l
2962 opp-s
2963 };
2964
2965 opp-490000000
2966 opp-h
2967 opp-l
2968 opp-s
2969 };
2970
2971 opp-441600000
2972 opp-h
2973 opp-l
2974 opp-s
2975 };
2976
2977 opp-400000000
2978 opp-h
2979 opp-l
2980 opp-s
2981 };
2982
2983 opp-305000000
2984 opp-h
2985 opp-l
2986 opp-s
2987 };
2988 };
2989 };
2990
2991 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad
2993
2994 reg = <0 0x03d6a000 0
2995 <0 0x3de0000 0
2996 <0 0xb290000 0
2997 <0 0xb490000 0
2998 reg-names = "gmu", "r
2999
3000 interrupts = <GIC_SPI
3001 <GIC_SPI
3002 interrupt-names = "hf
3003
3004 clocks = <&gpucc GPU_
3005 <&gpucc GPU_
3006 <&gpucc GPU_
3007 <&gcc GCC_DD
3008 <&gcc GCC_GP
3009 clock-names = "ahb",
3010
3011 power-domains = <&gpu
3012 <&gpu
3013 power-domain-names =
3014
3015 iommus = <&adreno_smm
3016
3017 operating-points-v2 =
3018
3019 status = "disabled";
3020
3021 gmu_opp_table: opp-ta
3022 compatible =
3023
3024 opp-200000000
3025 opp-h
3026 opp-l
3027 };
3028 };
3029 };
3030
3031 gpucc: clock-controller@3d900
3032 compatible = "qcom,sm
3033 reg = <0 0x03d90000 0
3034 clocks = <&rpmhcc RPM
3035 <&gcc GCC_GP
3036 <&gcc GCC_GP
3037 clock-names = "bi_tcx
3038 "gcc_gp
3039 "gcc_gp
3040 #clock-cells = <1>;
3041 #reset-cells = <1>;
3042 #power-domain-cells =
3043 };
3044
3045 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm
3047 "qcom,sm
3048 reg = <0 0x03da0000 0
3049 #iommu-cells = <2>;
3050 #global-interrupts =
3051 interrupts = <GIC_SPI
3052 <GIC_SPI
3053 <GIC_SPI
3054 <GIC_SPI
3055 <GIC_SPI
3056 <GIC_SPI
3057 <GIC_SPI
3058 <GIC_SPI
3059 <GIC_SPI
3060 <GIC_SPI
3061 clocks = <&gpucc GPU_
3062 <&gcc GCC_GP
3063 <&gcc GCC_GP
3064 clock-names = "ahb",
3065
3066 power-domains = <&gpu
3067 dma-coherent;
3068 };
3069
3070 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm
3072 reg = <0 0x05c00000 0
3073
3074 interrupts-extended =
3075
3076
3077
3078
3079 interrupt-names = "wd
3080 "ha
3081
3082 clocks = <&rpmhcc RPM
3083 clock-names = "xo";
3084
3085 power-domains = <&rpm
3086 <&rpm
3087 power-domain-names =
3088
3089 memory-region = <&slp
3090
3091 qcom,qmp = <&aoss_qmp
3092
3093 qcom,smem-states = <&
3094 qcom,smem-state-names
3095
3096 status = "disabled";
3097
3098 glink-edge {
3099 interrupts-ex
3100
3101
3102 mboxes = <&ip
3103
3104
3105 label = "slpi
3106 qcom,remote-p
3107
3108 fastrpc {
3109 compa
3110 qcom,
3111 label
3112 qcom,
3113 #addr
3114 #size
3115
3116 compu
3117
3118
3119
3120 };
3121
3122 compu
3123
3124
3125
3126 };
3127
3128 compu
3129
3130
3131
3132
3133 };
3134 };
3135 };
3136 };
3137
3138 stm@6002000 {
3139 compatible = "arm,cor
3140 reg = <0 0x06002000 0
3141 reg-names = "stm-base
3142
3143 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc
3145
3146 out-ports {
3147 port {
3148 stm_o
3149
3150 };
3151 };
3152 };
3153 };
3154
3155 tpda@6004000 {
3156 compatible = "qcom,co
3157 reg = <0 0x06004000 0
3158
3159 clocks = <&aoss_qmp>;
3160 clock-names = "apb_pc
3161
3162 out-ports {
3163
3164 port {
3165 tpda_
3166
3167 };
3168 };
3169 };
3170
3171 in-ports {
3172 #address-cell
3173 #size-cells =
3174
3175 port@9 {
3176 reg =
3177 tpda_
3178
3179 };
3180 };
3181
3182 port@17 {
3183 reg =
3184 tpda_
3185
3186 };
3187 };
3188 };
3189 };
3190
3191 funnel@6005000 {
3192 compatible = "arm,cor
3193 reg = <0 0x06005000 0
3194
3195 clocks = <&aoss_qmp>;
3196 clock-names = "apb_pc
3197
3198 out-ports {
3199 port {
3200 funne
3201
3202 };
3203 };
3204 };
3205
3206 in-ports {
3207 port {
3208 funne
3209
3210 };
3211 };
3212 };
3213 };
3214
3215 funnel@6041000 {
3216 compatible = "arm,cor
3217 reg = <0 0x06041000 0
3218
3219 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc
3221
3222 out-ports {
3223 port {
3224 funne
3225
3226 };
3227 };
3228 };
3229
3230 in-ports {
3231 #address-cell
3232 #size-cells =
3233
3234 port@6 {
3235 reg =
3236 funne
3237
3238 };
3239 };
3240
3241 port@7 {
3242 reg =
3243 funne
3244
3245 };
3246 };
3247 };
3248 };
3249
3250 funnel@6042000 {
3251 compatible = "arm,cor
3252 reg = <0 0x06042000 0
3253
3254 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc
3256
3257 out-ports {
3258 port {
3259 funne
3260
3261 };
3262 };
3263 };
3264
3265 in-ports {
3266 #address-cell
3267 #size-cells =
3268
3269 port@4 {
3270 reg =
3271 funne
3272 remot
3273 };
3274 };
3275 };
3276 };
3277
3278 funnel@6045000 {
3279 compatible = "arm,cor
3280 reg = <0 0x06045000 0
3281
3282 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc
3284
3285 out-ports {
3286 port {
3287 funne
3288 remot
3289 };
3290 };
3291 };
3292
3293 in-ports {
3294 #address-cell
3295 #size-cells =
3296
3297 port@0 {
3298 reg =
3299 funne
3300 remot
3301 };
3302 };
3303
3304 port@1 {
3305 reg =
3306 funne
3307 remot
3308 };
3309 };
3310 };
3311 };
3312
3313 replicator@6046000 {
3314 compatible = "arm,cor
3315 reg = <0 0x06046000 0
3316
3317 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc
3319
3320 out-ports {
3321 port {
3322 repli
3323
3324 };
3325 };
3326 };
3327
3328 in-ports {
3329 port {
3330 repli
3331
3332 };
3333 };
3334 };
3335 };
3336
3337 etr@6048000 {
3338 compatible = "arm,cor
3339 reg = <0 0x06048000 0
3340
3341 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc
3343 arm,scatter-gather;
3344
3345 in-ports {
3346 port {
3347 etr_i
3348
3349 };
3350 };
3351 };
3352 };
3353
3354 tpdm@684c000 {
3355 compatible = "qcom,co
3356 reg = <0 0x0684c000 0
3357
3358 clocks = <&aoss_qmp>;
3359 clock-names = "apb_pc
3360
3361 out-ports {
3362 port {
3363 tpdm_
3364
3365 };
3366 };
3367 };
3368 };
3369
3370 funnel@6b04000 {
3371 compatible = "arm,cor
3372 arm,primecell-periphi
3373
3374 reg = <0 0x06b04000 0
3375
3376 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc
3378
3379 out-ports {
3380 port {
3381 funne
3382
3383 };
3384 };
3385 };
3386
3387 in-ports {
3388 #address-cell
3389 #size-cells =
3390
3391 port@7 {
3392 reg =
3393 funne
3394
3395 };
3396 };
3397 };
3398 };
3399
3400 etf@6b05000 {
3401 compatible = "arm,cor
3402 reg = <0 0x06b05000 0
3403
3404 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc
3406
3407 out-ports {
3408 port {
3409 etf_o
3410
3411 };
3412 };
3413 };
3414
3415 in-ports {
3416
3417 port {
3418 etf_i
3419
3420 };
3421 };
3422 };
3423 };
3424
3425 replicator@6b06000 {
3426 compatible = "arm,cor
3427 reg = <0 0x06b06000 0
3428
3429 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc
3431
3432 out-ports {
3433 port {
3434 repli
3435
3436 };
3437 };
3438 };
3439
3440 in-ports {
3441 port {
3442 repli
3443
3444 };
3445 };
3446 };
3447 };
3448
3449 tpdm@6c08000 {
3450 compatible = "qcom,co
3451 reg = <0 0x06c08000 0
3452
3453 clocks = <&aoss_qmp>;
3454 clock-names = "apb_pc
3455
3456 out-ports {
3457 port {
3458 tpdm_
3459
3460 };
3461 };
3462 };
3463 };
3464
3465 funnel@6c0b000 {
3466 compatible = "arm,cor
3467 reg = <0 0x06c0b000 0
3468
3469 clocks = <&aoss_qmp>;
3470 clock-names = "apb_pc
3471
3472 out-ports {
3473 port {
3474 funne
3475 remot
3476 };
3477 };
3478 };
3479
3480 in-ports {
3481 #address-cell
3482 #size-cells =
3483
3484 port@3 {
3485 reg =
3486 funne
3487
3488 };
3489 };
3490 };
3491 };
3492
3493 funnel@6c2d000 {
3494 compatible = "arm,cor
3495 reg = <0 0x06c2d000 0
3496
3497 clocks = <&aoss_qmp>;
3498 clock-names = "apb_pc
3499
3500 out-ports {
3501 port {
3502 tpdm_
3503
3504 };
3505 };
3506 };
3507
3508 in-ports {
3509 #address-cell
3510 #size-cells =
3511
3512 port@2 {
3513 reg =
3514 funne
3515 remot
3516 };
3517 };
3518 };
3519 };
3520
3521 etm@7040000 {
3522 compatible = "arm,cor
3523 reg = <0 0x07040000 0
3524
3525 cpu = <&CPU0>;
3526
3527 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc
3529 arm,coresight-loses-c
3530
3531 out-ports {
3532 port {
3533 etm0_
3534
3535 };
3536 };
3537 };
3538 };
3539
3540 etm@7140000 {
3541 compatible = "arm,cor
3542 reg = <0 0x07140000 0
3543
3544 cpu = <&CPU1>;
3545
3546 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc
3548 arm,coresight-loses-c
3549
3550 out-ports {
3551 port {
3552 etm1_
3553
3554 };
3555 };
3556 };
3557 };
3558
3559 etm@7240000 {
3560 compatible = "arm,cor
3561 reg = <0 0x07240000 0
3562
3563 cpu = <&CPU2>;
3564
3565 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc
3567 arm,coresight-loses-c
3568
3569 out-ports {
3570 port {
3571 etm2_
3572
3573 };
3574 };
3575 };
3576 };
3577
3578 etm@7340000 {
3579 compatible = "arm,cor
3580 reg = <0 0x07340000 0
3581
3582 cpu = <&CPU3>;
3583
3584 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc
3586 arm,coresight-loses-c
3587
3588 out-ports {
3589 port {
3590 etm3_
3591
3592 };
3593 };
3594 };
3595 };
3596
3597 etm@7440000 {
3598 compatible = "arm,cor
3599 reg = <0 0x07440000 0
3600
3601 cpu = <&CPU4>;
3602
3603 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc
3605 arm,coresight-loses-c
3606
3607 out-ports {
3608 port {
3609 etm4_
3610
3611 };
3612 };
3613 };
3614 };
3615
3616 etm@7540000 {
3617 compatible = "arm,cor
3618 reg = <0 0x07540000 0
3619
3620 cpu = <&CPU5>;
3621
3622 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc
3624 arm,coresight-loses-c
3625
3626 out-ports {
3627 port {
3628 etm5_
3629
3630 };
3631 };
3632 };
3633 };
3634
3635 etm@7640000 {
3636 compatible = "arm,cor
3637 reg = <0 0x07640000 0
3638
3639 cpu = <&CPU6>;
3640
3641 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc
3643 arm,coresight-loses-c
3644
3645 out-ports {
3646 port {
3647 etm6_
3648
3649 };
3650 };
3651 };
3652 };
3653
3654 etm@7740000 {
3655 compatible = "arm,cor
3656 reg = <0 0x07740000 0
3657
3658 cpu = <&CPU7>;
3659
3660 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc
3662 arm,coresight-loses-c
3663
3664 out-ports {
3665 port {
3666 etm7_
3667
3668 };
3669 };
3670 };
3671 };
3672
3673 funnel@7800000 {
3674 compatible = "arm,cor
3675 reg = <0 0x07800000 0
3676
3677 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc
3679
3680 out-ports {
3681 port {
3682 funne
3683 remot
3684 };
3685 };
3686 };
3687
3688 in-ports {
3689 #address-cell
3690 #size-cells =
3691
3692 port@0 {
3693 reg =
3694 apss_
3695
3696 };
3697 };
3698
3699 port@1 {
3700 reg =
3701 apss_
3702
3703 };
3704 };
3705
3706 port@2 {
3707 reg =
3708 apss_
3709
3710 };
3711 };
3712
3713 port@3 {
3714 reg =
3715 apss_
3716
3717 };
3718 };
3719
3720 port@4 {
3721 reg =
3722 apss_
3723
3724 };
3725 };
3726
3727 port@5 {
3728 reg =
3729 apss_
3730
3731 };
3732 };
3733
3734 port@6 {
3735 reg =
3736 apss_
3737
3738 };
3739 };
3740
3741 port@7 {
3742 reg =
3743 apss_
3744
3745 };
3746 };
3747 };
3748 };
3749
3750 funnel@7810000 {
3751 compatible = "arm,cor
3752 reg = <0 0x07810000 0
3753
3754 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc
3756
3757 out-ports {
3758 port {
3759 funne
3760 remot
3761 };
3762 };
3763 };
3764
3765 in-ports {
3766 port {
3767 funne
3768 remot
3769 };
3770 };
3771 };
3772 };
3773
3774 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm
3776 reg = <0 0x08300000 0
3777
3778 interrupts-extended =
3779
3780
3781
3782
3783 interrupt-names = "wd
3784 "ha
3785
3786 clocks = <&rpmhcc RPM
3787 clock-names = "xo";
3788
3789 power-domains = <&rpm
3790
3791 memory-region = <&cds
3792
3793 qcom,qmp = <&aoss_qmp
3794
3795 qcom,smem-states = <&
3796 qcom,smem-state-names
3797
3798 status = "disabled";
3799
3800 glink-edge {
3801 interrupts-ex
3802
3803
3804 mboxes = <&ip
3805
3806
3807 label = "cdsp
3808 qcom,remote-p
3809
3810 fastrpc {
3811 compa
3812 qcom,
3813 label
3814 qcom,
3815 #addr
3816 #size
3817
3818 compu
3819
3820
3821
3822 };
3823
3824 compu
3825
3826
3827
3828 };
3829
3830 compu
3831
3832
3833
3834 };
3835
3836 compu
3837
3838
3839
3840 };
3841
3842 compu
3843
3844
3845
3846 };
3847
3848 compu
3849
3850
3851
3852 };
3853
3854 compu
3855
3856
3857
3858 };
3859
3860 compu
3861
3862
3863
3864 };
3865
3866 /* no
3867 };
3868 };
3869 };
3870
3871 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm
3873 "qcom,us
3874 reg = <0 0x088e3000 0
3875 status = "disabled";
3876 #phy-cells = <0>;
3877
3878 clocks = <&rpmhcc RPM
3879 clock-names = "ref";
3880
3881 resets = <&gcc GCC_QU
3882 };
3883
3884 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm
3886 "qcom,us
3887 reg = <0 0x088e4000 0
3888 status = "disabled";
3889 #phy-cells = <0>;
3890
3891 clocks = <&rpmhcc RPM
3892 clock-names = "ref";
3893
3894 resets = <&gcc GCC_QU
3895 };
3896
3897 usb_1_qmpphy: phy@88e8000 {
3898 compatible = "qcom,sm
3899 reg = <0 0x088e8000 0
3900 status = "disabled";
3901
3902 clocks = <&gcc GCC_US
3903 <&rpmhcc RPM
3904 <&gcc GCC_US
3905 <&gcc GCC_US
3906 clock-names = "aux",
3907 "ref",
3908 "com_au
3909 "usb3_p
3910
3911 resets = <&gcc GCC_US
3912 <&gcc GCC_US
3913 reset-names = "phy",
3914
3915 #clock-cells = <1>;
3916 #phy-cells = <1>;
3917
3918 orientation-switch;
3919
3920 ports {
3921 #address-cell
3922 #size-cells =
3923
3924 port@0 {
3925 reg =
3926 usb_1
3927 };
3928
3929 port@1 {
3930 reg =
3931
3932 usb_1
3933
3934 };
3935 };
3936
3937 port@2 {
3938 reg =
3939
3940 usb_1
3941 };
3942 };
3943 };
3944
3945 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm
3947 reg = <0 0x088eb000 0
3948
3949 clocks = <&gcc GCC_US
3950 <&gcc GCC_US
3951 <&gcc GCC_US
3952 <&gcc GCC_US
3953 clock-names = "aux",
3954 "ref",
3955 "com_au
3956 "pipe";
3957 clock-output-names =
3958 #clock-cells = <0>;
3959 #phy-cells = <0>;
3960
3961 resets = <&gcc GCC_US
3962 <&gcc GCC_US
3963 reset-names = "phy",
3964 "phy_ph
3965
3966 status = "disabled";
3967 };
3968
3969 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm
3971 reg = <0 0x08804000 0
3972
3973 interrupts = <GIC_SPI
3974 <GIC_SPI
3975 interrupt-names = "hc
3976
3977 clocks = <&gcc GCC_SD
3978 <&gcc GCC_SD
3979 <&rpmhcc RPM
3980 clock-names = "iface"
3981 iommus = <&apps_smmu
3982 qcom,dll-config = <0x
3983 qcom,ddr-config = <0x
3984 power-domains = <&rpm
3985 operating-points-v2 =
3986
3987 status = "disabled";
3988
3989 sdhc2_opp_table: opp-
3990 compatible =
3991
3992 opp-19200000
3993 opp-h
3994 requi
3995 };
3996
3997 opp-50000000
3998 opp-h
3999 requi
4000 };
4001
4002 opp-100000000
4003 opp-h
4004 requi
4005 };
4006
4007 opp-202000000
4008 opp-h
4009 requi
4010 };
4011 };
4012 };
4013
4014 pmu@9091000 {
4015 compatible = "qcom,sm
4016 reg = <0 0x09091000 0
4017
4018 interrupts = <GIC_SPI
4019
4020 interconnects = <&mc_
4021
4022 operating-points-v2 =
4023
4024 llcc_bwmon_opp_table:
4025 compatible =
4026
4027 opp-800000 {
4028 opp-p
4029 };
4030
4031 opp-1200000 {
4032 opp-p
4033 };
4034
4035 opp-1804000 {
4036 opp-p
4037 };
4038
4039 opp-2188000 {
4040 opp-p
4041 };
4042
4043 opp-2724000 {
4044 opp-p
4045 };
4046
4047 opp-3072000 {
4048 opp-p
4049 };
4050
4051 opp-4068000 {
4052 opp-p
4053 };
4054
4055 /* 1353 MHz,
4056
4057 opp-6220000 {
4058 opp-p
4059 };
4060
4061 opp-7216000 {
4062 opp-p
4063 };
4064
4065 opp-8368000 {
4066 opp-p
4067 };
4068
4069 /* LPDDR5 */
4070 opp-10944000
4071 opp-p
4072 };
4073 };
4074 };
4075
4076 pmu@90b6400 {
4077 compatible = "qcom,sm
4078 reg = <0 0x090b6400 0
4079
4080 interrupts = <GIC_SPI
4081
4082 interconnects = <&gem
4083 operating-points-v2 =
4084
4085 cpu_bwmon_opp_table:
4086 compatible =
4087
4088 opp-800000 {
4089 opp-p
4090 };
4091
4092 opp-1804000 {
4093 opp-p
4094 };
4095
4096 opp-2188000 {
4097 opp-p
4098 };
4099
4100 opp-2724000 {
4101 opp-p
4102 };
4103
4104 opp-3072000 {
4105 opp-p
4106 };
4107
4108 /* 1017MHz, 1
4109
4110 opp-6220000 {
4111 opp-p
4112 };
4113
4114 opp-6832000 {
4115 opp-p
4116 };
4117
4118 opp-8368000 {
4119 opp-p
4120 };
4121
4122 /* 2133MHz, L
4123
4124 /* LPDDR5 */
4125 opp-10944000
4126 opp-p
4127 };
4128
4129 /* LPDDR5 */
4130 opp-12784000
4131 opp-p
4132 };
4133 };
4134 };
4135
4136 dc_noc: interconnect@90c0000
4137 compatible = "qcom,sm
4138 reg = <0 0x090c0000 0
4139 #interconnect-cells =
4140 qcom,bcm-voters = <&a
4141 };
4142
4143 gem_noc: interconnect@9100000
4144 compatible = "qcom,sm
4145 reg = <0 0x09100000 0
4146 #interconnect-cells =
4147 qcom,bcm-voters = <&a
4148 };
4149
4150 npu_noc: interconnect@9990000
4151 compatible = "qcom,sm
4152 reg = <0 0x09990000 0
4153 #interconnect-cells =
4154 qcom,bcm-voters = <&a
4155 };
4156
4157 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm
4159 reg = <0 0x0a6f8800 0
4160 status = "disabled";
4161 #address-cells = <2>;
4162 #size-cells = <2>;
4163 ranges;
4164 dma-ranges;
4165
4166 clocks = <&gcc GCC_CF
4167 <&gcc GCC_US
4168 <&gcc GCC_AG
4169 <&gcc GCC_US
4170 <&gcc GCC_US
4171 <&gcc GCC_US
4172 clock-names = "cfg_no
4173 "core",
4174 "iface"
4175 "sleep"
4176 "mock_u
4177 "xo";
4178
4179 assigned-clocks = <&g
4180 <&g
4181 assigned-clock-rates
4182
4183 interrupts-extended =
4184
4185
4186
4187
4188 interrupt-names = "pw
4189 "hs
4190 "dp
4191 "dm
4192 "ss
4193
4194 power-domains = <&gcc
4195 wakeup-source;
4196
4197 resets = <&gcc GCC_US
4198
4199 interconnects = <&agg
4200 <&gem
4201 interconnect-names =
4202
4203 usb_1_dwc3: usb@a6000
4204 compatible =
4205 reg = <0 0x0a
4206 interrupts =
4207 iommus = <&ap
4208 snps,dis_u2_s
4209 snps,dis_enbl
4210 phys = <&usb_
4211 phy-names = "
4212
4213 ports {
4214 #addr
4215 #size
4216
4217 port@
4218
4219
4220
4221
4222 };
4223
4224 port@
4225
4226
4227
4228
4229
4230 };
4231 };
4232 };
4233 };
4234
4235 system-cache-controller@92000
4236 compatible = "qcom,sm
4237 reg = <0 0x09200000 0
4238 <0 0x09300000 0
4239 <0 0x09600000 0
4240 reg-names = "llcc0_ba
4241 "llcc3_ba
4242 };
4243
4244 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm
4246 reg = <0 0x0a8f8800 0
4247 status = "disabled";
4248 #address-cells = <2>;
4249 #size-cells = <2>;
4250 ranges;
4251 dma-ranges;
4252
4253 clocks = <&gcc GCC_CF
4254 <&gcc GCC_US
4255 <&gcc GCC_AG
4256 <&gcc GCC_US
4257 <&gcc GCC_US
4258 <&gcc GCC_US
4259 clock-names = "cfg_no
4260 "core",
4261 "iface"
4262 "sleep"
4263 "mock_u
4264 "xo";
4265
4266 assigned-clocks = <&g
4267 <&g
4268 assigned-clock-rates
4269
4270 interrupts-extended =
4271
4272
4273
4274
4275 interrupt-names = "pw
4276 "hs
4277 "dp
4278 "dm
4279 "ss
4280
4281 power-domains = <&gcc
4282 wakeup-source;
4283
4284 resets = <&gcc GCC_US
4285
4286 interconnects = <&agg
4287 <&gem
4288 interconnect-names =
4289
4290 usb_2_dwc3: usb@a8000
4291 compatible =
4292 reg = <0 0x0a
4293 interrupts =
4294 iommus = <&ap
4295 snps,dis_u2_s
4296 snps,dis_enbl
4297 phys = <&usb_
4298 phy-names = "
4299 };
4300 };
4301
4302 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm
4304 reg = <0 0x0aa00000 0
4305 interrupts = <GIC_SPI
4306 power-domains = <&vid
4307 <&vid
4308 <&rpm
4309 power-domain-names =
4310 operating-points-v2 =
4311
4312 clocks = <&gcc GCC_VI
4313 <&videocc VI
4314 <&videocc VI
4315 clock-names = "iface"
4316
4317 interconnects = <&gem
4318 <&mms
4319 interconnect-names =
4320
4321 iommus = <&apps_smmu
4322 memory-region = <&vid
4323
4324 resets = <&gcc GCC_VI
4325 <&videocc VI
4326 reset-names = "bus",
4327
4328 status = "disabled";
4329
4330 video-decoder {
4331 compatible =
4332 };
4333
4334 video-encoder {
4335 compatible =
4336 };
4337
4338 venus_opp_table: opp-
4339 compatible =
4340
4341 opp-720000000
4342 opp-h
4343 requi
4344 };
4345
4346 opp-101400000
4347 opp-h
4348 requi
4349 };
4350
4351 opp-109800000
4352 opp-h
4353 requi
4354 };
4355
4356 opp-133200000
4357 opp-h
4358 requi
4359 };
4360 };
4361 };
4362
4363 videocc: clock-controller@abf
4364 compatible = "qcom,sm
4365 reg = <0 0x0abf0000 0
4366 clocks = <&gcc GCC_VI
4367 <&rpmhcc RPM
4368 <&rpmhcc RPM
4369 power-domains = <&rpm
4370 required-opps = <&rpm
4371 clock-names = "iface"
4372 #clock-cells = <1>;
4373 #reset-cells = <1>;
4374 #power-domain-cells =
4375 };
4376
4377 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm
4379 #address-cells = <1>;
4380 #size-cells = <0>;
4381
4382 reg = <0 0x0ac4f000 0
4383 interrupts = <GIC_SPI
4384 power-domains = <&cam
4385
4386 clocks = <&camcc CAM_
4387 <&camcc CAM_
4388 <&camcc CAM_
4389 <&camcc CAM_
4390 <&camcc CAM_
4391 clock-names = "camnoc
4392 "slow_a
4393 "cpas_a
4394 "cci",
4395 "cci_sr
4396
4397 pinctrl-0 = <&cci0_de
4398 pinctrl-1 = <&cci0_sl
4399 pinctrl-names = "defa
4400
4401 status = "disabled";
4402
4403 cci0_i2c0: i2c-bus@0
4404 reg = <0>;
4405 clock-frequen
4406 #address-cell
4407 #size-cells =
4408 };
4409
4410 cci0_i2c1: i2c-bus@1
4411 reg = <1>;
4412 clock-frequen
4413 #address-cell
4414 #size-cells =
4415 };
4416 };
4417
4418 cci1: cci@ac50000 {
4419 compatible = "qcom,sm
4420 #address-cells = <1>;
4421 #size-cells = <0>;
4422
4423 reg = <0 0x0ac50000 0
4424 interrupts = <GIC_SPI
4425 power-domains = <&cam
4426
4427 clocks = <&camcc CAM_
4428 <&camcc CAM_
4429 <&camcc CAM_
4430 <&camcc CAM_
4431 <&camcc CAM_
4432 clock-names = "camnoc
4433 "slow_a
4434 "cpas_a
4435 "cci",
4436 "cci_sr
4437
4438 pinctrl-0 = <&cci1_de
4439 pinctrl-1 = <&cci1_sl
4440 pinctrl-names = "defa
4441
4442 status = "disabled";
4443
4444 cci1_i2c0: i2c-bus@0
4445 reg = <0>;
4446 clock-frequen
4447 #address-cell
4448 #size-cells =
4449 };
4450
4451 cci1_i2c1: i2c-bus@1
4452 reg = <1>;
4453 clock-frequen
4454 #address-cell
4455 #size-cells =
4456 };
4457 };
4458
4459 camss: camss@ac6a000 {
4460 compatible = "qcom,sm
4461 status = "disabled";
4462
4463 reg = <0 0x0ac6a000 0
4464 <0 0x0ac6c000 0
4465 <0 0x0ac6e000 0
4466 <0 0x0ac70000 0
4467 <0 0x0ac72000 0
4468 <0 0x0ac74000 0
4469 <0 0x0acb4000 0
4470 <0 0x0acc3000 0
4471 <0 0x0acd9000 0
4472 <0 0x0acdb200 0
4473 reg-names = "csiphy0"
4474 "csiphy1"
4475 "csiphy2"
4476 "csiphy3"
4477 "csiphy4"
4478 "csiphy5"
4479 "vfe0",
4480 "vfe1",
4481 "vfe_lite
4482 "vfe_lite
4483
4484 interrupts = <GIC_SPI
4485 <GIC_SPI
4486 <GIC_SPI
4487 <GIC_SPI
4488 <GIC_SPI
4489 <GIC_SPI
4490 <GIC_SPI
4491 <GIC_SPI
4492 <GIC_SPI
4493 <GIC_SPI
4494 <GIC_SPI
4495 <GIC_SPI
4496 <GIC_SPI
4497 <GIC_SPI
4498 interrupt-names = "cs
4499 "cs
4500 "cs
4501 "cs
4502 "cs
4503 "cs
4504 "cs
4505 "cs
4506 "cs
4507 "cs
4508 "vf
4509 "vf
4510 "vf
4511 "vf
4512
4513 power-domains = <&cam
4514 <&cam
4515 <&cam
4516
4517 clocks = <&gcc GCC_CA
4518 <&gcc GCC_CA
4519 <&gcc GCC_CA
4520 <&camcc CAM_
4521 <&camcc CAM_
4522 <&camcc CAM_
4523 <&camcc CAM_
4524 <&camcc CAM_
4525 <&camcc CAM_
4526 <&camcc CAM_
4527 <&camcc CAM_
4528 <&camcc CAM_
4529 <&camcc CAM_
4530 <&camcc CAM_
4531 <&camcc CAM_
4532 <&camcc CAM_
4533 <&camcc CAM_
4534 <&camcc CAM_
4535 <&camcc CAM_
4536 <&camcc CAM_
4537 <&camcc CAM_
4538 <&camcc CAM_
4539 <&camcc CAM_
4540 <&camcc CAM_
4541 <&camcc CAM_
4542 <&camcc CAM_
4543 <&camcc CAM_
4544 <&camcc CAM_
4545 <&camcc CAM_
4546 <&camcc CAM_
4547 <&camcc CAM_
4548 <&camcc CAM_
4549 <&camcc CAM_
4550 <&camcc CAM_
4551 <&camcc CAM_
4552 <&camcc CAM_
4553 <&camcc CAM_
4554
4555 clock-names = "cam_ah
4556 "cam_hf
4557 "cam_sf
4558 "camnoc
4559 "camnoc
4560 "core_a
4561 "cpas_a
4562 "csiphy
4563 "csiphy
4564 "csiphy
4565 "csiphy
4566 "csiphy
4567 "csiphy
4568 "csiphy
4569 "csiphy
4570 "csiphy
4571 "csiphy
4572 "csiphy
4573 "csiphy
4574 "slow_a
4575 "vfe0_a
4576 "vfe0_a
4577 "vfe0",
4578 "vfe0_c
4579 "vfe0_c
4580 "vfe0_a
4581 "vfe1_a
4582 "vfe1_a
4583 "vfe1",
4584 "vfe1_c
4585 "vfe1_c
4586 "vfe1_a
4587 "vfe_li
4588 "vfe_li
4589 "vfe_li
4590 "vfe_li
4591 "vfe_li
4592
4593 iommus = <&apps_smmu
4594 <&apps_smmu
4595 <&apps_smmu
4596 <&apps_smmu
4597 <&apps_smmu
4598 <&apps_smmu
4599 <&apps_smmu
4600 <&apps_smmu
4601
4602 interconnects = <&gem
4603 <&mms
4604 <&mms
4605 <&mms
4606 interconnect-names =
4607
4608
4609
4610
4611 ports {
4612 #address-cell
4613 #size-cells =
4614
4615 port@0 {
4616 reg =
4617 };
4618
4619 port@1 {
4620 reg =
4621 };
4622
4623 port@2 {
4624 reg =
4625 };
4626
4627 port@3 {
4628 reg =
4629 };
4630
4631 port@4 {
4632 reg =
4633 };
4634
4635 port@5 {
4636 reg =
4637 };
4638 };
4639 };
4640
4641 camcc: clock-controller@ad000
4642 compatible = "qcom,sm
4643 reg = <0 0x0ad00000 0
4644 clocks = <&gcc GCC_CA
4645 <&rpmhcc RPM
4646 <&rpmhcc RPM
4647 <&sleep_clk>
4648 clock-names = "iface"
4649 power-domains = <&rpm
4650 required-opps = <&rpm
4651 status = "disabled";
4652 #clock-cells = <1>;
4653 #reset-cells = <1>;
4654 #power-domain-cells =
4655 };
4656
4657 mdss: display-subsystem@ae000
4658 compatible = "qcom,sm
4659 reg = <0 0x0ae00000 0
4660 reg-names = "mdss";
4661
4662 interconnects = <&mms
4663 <&mms
4664 interconnect-names =
4665
4666 power-domains = <&dis
4667
4668 clocks = <&dispcc DIS
4669 <&gcc GCC_DI
4670 <&gcc GCC_DI
4671 <&dispcc DIS
4672 clock-names = "iface"
4673
4674 interrupts = <GIC_SPI
4675 interrupt-controller;
4676 #interrupt-cells = <1
4677
4678 iommus = <&apps_smmu
4679
4680 status = "disabled";
4681
4682 #address-cells = <2>;
4683 #size-cells = <2>;
4684 ranges;
4685
4686 mdss_mdp: display-con
4687 compatible =
4688 reg = <0 0x0a
4689 <0 0x0a
4690 reg-names = "
4691
4692 clocks = <&di
4693 <&gc
4694 <&di
4695 <&di
4696 clock-names =
4697
4698 assigned-cloc
4699 assigned-cloc
4700
4701 operating-poi
4702 power-domains
4703
4704 interrupt-par
4705 interrupts =
4706
4707 ports {
4708 #addr
4709 #size
4710
4711 port@
4712
4713
4714
4715
4716 };
4717
4718 port@
4719
4720
4721
4722
4723 };
4724
4725 port@
4726
4727
4728
4729
4730
4731 };
4732 };
4733
4734 mdp_opp_table
4735 compa
4736
4737 opp-2
4738
4739
4740 };
4741
4742 opp-3
4743
4744
4745 };
4746
4747 opp-3
4748
4749
4750 };
4751
4752 opp-4
4753
4754
4755 };
4756 };
4757 };
4758
4759 mdss_dp: displayport-
4760 compatible =
4761 reg = <0 0xae
4762 <0 0xae
4763 <0 0xae
4764 <0 0xae
4765 <0 0xae
4766 interrupt-par
4767 interrupts =
4768 clocks = <&di
4769 <&di
4770 <&di
4771 <&di
4772 <&di
4773 clock-names =
4774
4775
4776
4777
4778
4779 assigned-cloc
4780
4781 assigned-cloc
4782
4783
4784 phys = <&usb_
4785 phy-names = "
4786
4787 #sound-dai-ce
4788
4789 operating-poi
4790 power-domains
4791
4792 status = "dis
4793
4794 ports {
4795 #addr
4796 #size
4797
4798 port@
4799
4800
4801
4802
4803 };
4804
4805 port@
4806
4807
4808
4809
4810 };
4811 };
4812
4813 dp_opp_table:
4814 compa
4815
4816 opp-1
4817
4818
4819 };
4820
4821 opp-2
4822
4823
4824 };
4825
4826 opp-5
4827
4828
4829 };
4830
4831 opp-8
4832
4833
4834 };
4835 };
4836 };
4837
4838 mdss_dsi0: dsi@ae9400
4839 compatible =
4840
4841 reg = <0 0x0a
4842 reg-names = "
4843
4844 interrupt-par
4845 interrupts =
4846
4847 clocks = <&di
4848 <&di
4849 <&di
4850 <&di
4851 <&di
4852 <&gcc
4853 clock-names =
4854
4855
4856
4857
4858
4859
4860 assigned-cloc
4861 assigned-cloc
4862
4863 operating-poi
4864 power-domains
4865
4866 phys = <&mdss
4867
4868 status = "dis
4869
4870 #address-cell
4871 #size-cells =
4872
4873 ports {
4874 #addr
4875 #size
4876
4877 port@
4878
4879
4880
4881
4882 };
4883
4884 port@
4885
4886
4887
4888 };
4889 };
4890
4891 dsi_opp_table
4892 compa
4893
4894 opp-1
4895
4896
4897 };
4898
4899 opp-3
4900
4901
4902 };
4903
4904 opp-3
4905
4906
4907 };
4908 };
4909 };
4910
4911 mdss_dsi0_phy: phy@ae
4912 compatible =
4913 reg = <0 0x0a
4914 <0 0x0a
4915 <0 0x0a
4916 reg-names = "
4917 "
4918 "
4919
4920 #clock-cells
4921 #phy-cells =
4922
4923 clocks = <&di
4924 <&rp
4925 clock-names =
4926
4927 status = "dis
4928 };
4929
4930 mdss_dsi1: dsi@ae9600
4931 compatible =
4932
4933 reg = <0 0x0a
4934 reg-names = "
4935
4936 interrupt-par
4937 interrupts =
4938
4939 clocks = <&di
4940 <&di
4941 <&di
4942 <&di
4943 <&di
4944 <&gc
4945 clock-names =
4946
4947
4948
4949
4950
4951
4952 assigned-cloc
4953 assigned-cloc
4954
4955 operating-poi
4956 power-domains
4957
4958 phys = <&mdss
4959
4960 status = "dis
4961
4962 #address-cell
4963 #size-cells =
4964
4965 ports {
4966 #addr
4967 #size
4968
4969 port@
4970
4971
4972
4973
4974 };
4975
4976 port@
4977
4978
4979
4980 };
4981 };
4982 };
4983
4984 mdss_dsi1_phy: phy@ae
4985 compatible =
4986 reg = <0 0x0a
4987 <0 0x0a
4988 <0 0x0a
4989 reg-names = "
4990 "
4991 "
4992
4993 #clock-cells
4994 #phy-cells =
4995
4996 clocks = <&di
4997 <&rp
4998 clock-names =
4999
5000 status = "dis
5001 };
5002 };
5003
5004 dispcc: clock-controller@af00
5005 compatible = "qcom,sm
5006 reg = <0 0x0af00000 0
5007 power-domains = <&rpm
5008 required-opps = <&rpm
5009 clocks = <&rpmhcc RPM
5010 <&mdss_dsi0_
5011 <&mdss_dsi0_
5012 <&mdss_dsi1_
5013 <&mdss_dsi1_
5014 <&usb_1_qmpp
5015 <&usb_1_qmpp
5016 clock-names = "bi_tcx
5017 "dsi0_p
5018 "dsi0_p
5019 "dsi1_p
5020 "dsi1_p
5021 "dp_phy
5022 "dp_phy
5023 #clock-cells = <1>;
5024 #reset-cells = <1>;
5025 #power-domain-cells =
5026 };
5027
5028 pdc: interrupt-controller@b22
5029 compatible = "qcom,sm
5030 reg = <0 0x0b220000 0
5031 qcom,pdc-ranges = <0
5032 <12
5033 #interrupt-cells = <2
5034 interrupt-parent = <&
5035 interrupt-controller;
5036 };
5037
5038 tsens0: thermal-sensor@c26300
5039 compatible = "qcom,sm
5040 reg = <0 0x0c263000 0
5041 <0 0x0c222000 0
5042 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI
5044 <GIC_SPI
5045 interrupt-names = "up
5046 #thermal-sensor-cells
5047 };
5048
5049 tsens1: thermal-sensor@c26500
5050 compatible = "qcom,sm
5051 reg = <0 0x0c265000 0
5052 <0 0x0c223000 0
5053 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI
5055 <GIC_SPI
5056 interrupt-names = "up
5057 #thermal-sensor-cells
5058 };
5059
5060 aoss_qmp: power-management@c3
5061 compatible = "qcom,sm
5062 reg = <0 0x0c300000 0
5063 interrupts-extended =
5064
5065
5066 mboxes = <&ipcc IPCC_
5067 IPCC_
5068
5069 #clock-cells = <0>;
5070 };
5071
5072 sram@c3f0000 {
5073 compatible = "qcom,rp
5074 reg = <0 0x0c3f0000 0
5075 };
5076
5077 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp
5079 reg = <0x0 0x0c440000
5080 <0x0 0x0c600000
5081 <0x0 0x0e600000
5082 <0x0 0x0e700000
5083 <0x0 0x0c40a000
5084 reg-names = "core", "
5085 interrupt-names = "pe
5086 interrupts-extended =
5087 qcom,ee = <0>;
5088 qcom,channel = <0>;
5089 #address-cells = <2>;
5090 #size-cells = <0>;
5091 interrupt-controller;
5092 #interrupt-cells = <4
5093 };
5094
5095 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm
5097 reg = <0 0x0f100000 0
5098 <0 0x0f500000 0
5099 <0 0x0f900000 0
5100 reg-names = "west", "
5101 interrupts = <GIC_SPI
5102 gpio-controller;
5103 #gpio-cells = <2>;
5104 interrupt-controller;
5105 #interrupt-cells = <2
5106 gpio-ranges = <&tlmm
5107 wakeup-parent = <&pdc
5108
5109 cam2_default: cam2-de
5110 rst-pins {
5111 pins
5112 funct
5113 drive
5114 bias-
5115 };
5116
5117 mclk-pins {
5118 pins
5119 funct
5120 drive
5121 bias-
5122 };
5123 };
5124
5125 cam2_suspend: cam2-su
5126 rst-pins {
5127 pins
5128 funct
5129 drive
5130 bias-
5131 outpu
5132 };
5133
5134 mclk-pins {
5135 pins
5136 funct
5137 drive
5138 bias-
5139 };
5140 };
5141
5142 cci0_default: cci0-de
5143 cci0_i2c0_def
5144 /* SD
5145 pins
5146 funct
5147
5148 bias-
5149 drive
5150 };
5151
5152 cci0_i2c1_def
5153 /* SD
5154 pins
5155 funct
5156
5157 bias-
5158 drive
5159 };
5160 };
5161
5162 cci0_sleep: cci0-slee
5163 cci0_i2c0_sle
5164 /* SD
5165 pins
5166 funct
5167
5168 drive
5169 bias-
5170 };
5171
5172 cci0_i2c1_sle
5173 /* SD
5174 pins
5175 funct
5176
5177 drive
5178 bias-
5179 };
5180 };
5181
5182 cci1_default: cci1-de
5183 cci1_i2c0_def
5184 /* SD
5185 pins
5186 funct
5187
5188 bias-
5189 drive
5190 };
5191
5192 cci1_i2c1_def
5193 /* SD
5194 pins
5195 funct
5196
5197 bias-
5198 drive
5199 };
5200 };
5201
5202 cci1_sleep: cci1-slee
5203 cci1_i2c0_sle
5204 /* SD
5205 pins
5206 funct
5207
5208 bias-
5209 drive
5210 };
5211
5212 cci1_i2c1_sle
5213 /* SD
5214 pins
5215 funct
5216
5217 bias-
5218 drive
5219 };
5220 };
5221
5222 pri_mi2s_active: pri-
5223 sclk-pins {
5224 pins
5225 funct
5226 drive
5227 bias-
5228 };
5229
5230 ws-pins {
5231 pins
5232 funct
5233 drive
5234 outpu
5235 };
5236
5237 data0-pins {
5238 pins
5239 funct
5240 drive
5241 bias-
5242 outpu
5243 };
5244
5245 data1-pins {
5246 pins
5247 funct
5248 drive
5249 outpu
5250 };
5251 };
5252
5253 qup_i2c0_default: qup
5254 pins = "gpio2
5255 function = "q
5256 drive-strengt
5257 bias-disable;
5258 };
5259
5260 qup_i2c1_default: qup
5261 pins = "gpio4
5262 function = "q
5263 drive-strengt
5264 bias-disable;
5265 };
5266
5267 qup_i2c2_default: qup
5268 pins = "gpio1
5269 function = "q
5270 drive-strengt
5271 bias-disable;
5272 };
5273
5274 qup_i2c3_default: qup
5275 pins = "gpio1
5276 function = "q
5277 drive-strengt
5278 bias-disable;
5279 };
5280
5281 qup_i2c4_default: qup
5282 pins = "gpio8
5283 function = "q
5284 drive-strengt
5285 bias-disable;
5286 };
5287
5288 qup_i2c5_default: qup
5289 pins = "gpio1
5290 function = "q
5291 drive-strengt
5292 bias-disable;
5293 };
5294
5295 qup_i2c6_default: qup
5296 pins = "gpio1
5297 function = "q
5298 drive-strengt
5299 bias-disable;
5300 };
5301
5302 qup_i2c7_default: qup
5303 pins = "gpio2
5304 function = "q
5305 drive-strengt
5306 bias-disable;
5307 };
5308
5309 qup_i2c8_default: qup
5310 pins = "gpio2
5311 function = "q
5312 drive-strengt
5313 bias-disable;
5314 };
5315
5316 qup_i2c9_default: qup
5317 pins = "gpio1
5318 function = "q
5319 drive-strengt
5320 bias-disable;
5321 };
5322
5323 qup_i2c10_default: qu
5324 pins = "gpio1
5325 function = "q
5326 drive-strengt
5327 bias-disable;
5328 };
5329
5330 qup_i2c11_default: qu
5331 pins = "gpio6
5332 function = "q
5333 drive-strengt
5334 bias-disable;
5335 };
5336
5337 qup_i2c12_default: qu
5338 pins = "gpio3
5339 function = "q
5340 drive-strengt
5341 bias-disable;
5342 };
5343
5344 qup_i2c13_default: qu
5345 pins = "gpio3
5346 function = "q
5347 drive-strengt
5348 bias-disable;
5349 };
5350
5351 qup_i2c14_default: qu
5352 pins = "gpio4
5353 function = "q
5354 drive-strengt
5355 bias-disable;
5356 };
5357
5358 qup_i2c15_default: qu
5359 pins = "gpio4
5360 function = "q
5361 drive-strengt
5362 bias-disable;
5363 };
5364
5365 qup_i2c16_default: qu
5366 pins = "gpio4
5367 function = "q
5368 drive-strengt
5369 bias-disable;
5370 };
5371
5372 qup_i2c17_default: qu
5373 pins = "gpio5
5374 function = "q
5375 drive-strengt
5376 bias-disable;
5377 };
5378
5379 qup_i2c18_default: qu
5380 pins = "gpio5
5381 function = "q
5382 drive-strengt
5383 bias-disable;
5384 };
5385
5386 qup_i2c19_default: qu
5387 pins = "gpio0
5388 function = "q
5389 drive-strengt
5390 bias-disable;
5391 };
5392
5393 qup_spi0_cs: qup-spi0
5394 pins = "gpio3
5395 function = "q
5396 };
5397
5398 qup_spi0_cs_gpio: qup
5399 pins = "gpio3
5400 function = "g
5401 };
5402
5403 qup_spi0_data_clk: qu
5404 pins = "gpio2
5405 "gpio3
5406 function = "q
5407 };
5408
5409 qup_spi1_cs: qup-spi1
5410 pins = "gpio7
5411 function = "q
5412 };
5413
5414 qup_spi1_cs_gpio: qup
5415 pins = "gpio7
5416 function = "g
5417 };
5418
5419 qup_spi1_data_clk: qu
5420 pins = "gpio4
5421 "gpio6
5422 function = "q
5423 };
5424
5425 qup_spi2_cs: qup-spi2
5426 pins = "gpio1
5427 function = "q
5428 };
5429
5430 qup_spi2_cs_gpio: qup
5431 pins = "gpio1
5432 function = "g
5433 };
5434
5435 qup_spi2_data_clk: qu
5436 pins = "gpio1
5437 "gpio1
5438 function = "q
5439 };
5440
5441 qup_spi3_cs: qup-spi3
5442 pins = "gpio1
5443 function = "q
5444 };
5445
5446 qup_spi3_cs_gpio: qup
5447 pins = "gpio1
5448 function = "g
5449 };
5450
5451 qup_spi3_data_clk: qu
5452 pins = "gpio1
5453 "gpio1
5454 function = "q
5455 };
5456
5457 qup_spi4_cs: qup-spi4
5458 pins = "gpio1
5459 function = "q
5460 };
5461
5462 qup_spi4_cs_gpio: qup
5463 pins = "gpio1
5464 function = "g
5465 };
5466
5467 qup_spi4_data_clk: qu
5468 pins = "gpio8
5469 "gpio1
5470 function = "q
5471 };
5472
5473 qup_spi5_cs: qup-spi5
5474 pins = "gpio1
5475 function = "q
5476 };
5477
5478 qup_spi5_cs_gpio: qup
5479 pins = "gpio1
5480 function = "g
5481 };
5482
5483 qup_spi5_data_clk: qu
5484 pins = "gpio1
5485 "gpio1
5486 function = "q
5487 };
5488
5489 qup_spi6_cs: qup-spi6
5490 pins = "gpio1
5491 function = "q
5492 };
5493
5494 qup_spi6_cs_gpio: qup
5495 pins = "gpio1
5496 function = "g
5497 };
5498
5499 qup_spi6_data_clk: qu
5500 pins = "gpio1
5501 "gpio1
5502 function = "q
5503 };
5504
5505 qup_spi7_cs: qup-spi7
5506 pins = "gpio2
5507 function = "q
5508 };
5509
5510 qup_spi7_cs_gpio: qup
5511 pins = "gpio2
5512 function = "g
5513 };
5514
5515 qup_spi7_data_clk: qu
5516 pins = "gpio2
5517 "gpio2
5518 function = "q
5519 };
5520
5521 qup_spi8_cs: qup-spi8
5522 pins = "gpio2
5523 function = "q
5524 };
5525
5526 qup_spi8_cs_gpio: qup
5527 pins = "gpio2
5528 function = "g
5529 };
5530
5531 qup_spi8_data_clk: qu
5532 pins = "gpio2
5533 "gpio2
5534 function = "q
5535 };
5536
5537 qup_spi9_cs: qup-spi9
5538 pins = "gpio1
5539 function = "q
5540 };
5541
5542 qup_spi9_cs_gpio: qup
5543 pins = "gpio1
5544 function = "g
5545 };
5546
5547 qup_spi9_data_clk: qu
5548 pins = "gpio1
5549 "gpio1
5550 function = "q
5551 };
5552
5553 qup_spi10_cs: qup-spi
5554 pins = "gpio1
5555 function = "q
5556 };
5557
5558 qup_spi10_cs_gpio: qu
5559 pins = "gpio1
5560 function = "g
5561 };
5562
5563 qup_spi10_data_clk: q
5564 pins = "gpio1
5565 "gpio1
5566 function = "q
5567 };
5568
5569 qup_spi11_cs: qup-spi
5570 pins = "gpio6
5571 function = "q
5572 };
5573
5574 qup_spi11_cs_gpio: qu
5575 pins = "gpio6
5576 function = "g
5577 };
5578
5579 qup_spi11_data_clk: q
5580 pins = "gpio6
5581 "gpio6
5582 function = "q
5583 };
5584
5585 qup_spi12_cs: qup-spi
5586 pins = "gpio3
5587 function = "q
5588 };
5589
5590 qup_spi12_cs_gpio: qu
5591 pins = "gpio3
5592 function = "g
5593 };
5594
5595 qup_spi12_data_clk: q
5596 pins = "gpio3
5597 "gpio3
5598 function = "q
5599 };
5600
5601 qup_spi13_cs: qup-spi
5602 pins = "gpio3
5603 function = "q
5604 };
5605
5606 qup_spi13_cs_gpio: qu
5607 pins = "gpio3
5608 function = "g
5609 };
5610
5611 qup_spi13_data_clk: q
5612 pins = "gpio3
5613 "gpio3
5614 function = "q
5615 };
5616
5617 qup_spi14_cs: qup-spi
5618 pins = "gpio4
5619 function = "q
5620 };
5621
5622 qup_spi14_cs_gpio: qu
5623 pins = "gpio4
5624 function = "g
5625 };
5626
5627 qup_spi14_data_clk: q
5628 pins = "gpio4
5629 "gpio4
5630 function = "q
5631 };
5632
5633 qup_spi15_cs: qup-spi
5634 pins = "gpio4
5635 function = "q
5636 };
5637
5638 qup_spi15_cs_gpio: qu
5639 pins = "gpio4
5640 function = "g
5641 };
5642
5643 qup_spi15_data_clk: q
5644 pins = "gpio4
5645 "gpio4
5646 function = "q
5647 };
5648
5649 qup_spi16_cs: qup-spi
5650 pins = "gpio5
5651 function = "q
5652 };
5653
5654 qup_spi16_cs_gpio: qu
5655 pins = "gpio5
5656 function = "g
5657 };
5658
5659 qup_spi16_data_clk: q
5660 pins = "gpio4
5661 "gpio5
5662 function = "q
5663 };
5664
5665 qup_spi17_cs: qup-spi
5666 pins = "gpio5
5667 function = "q
5668 };
5669
5670 qup_spi17_cs_gpio: qu
5671 pins = "gpio5
5672 function = "g
5673 };
5674
5675 qup_spi17_data_clk: q
5676 pins = "gpio5
5677 "gpio5
5678 function = "q
5679 };
5680
5681 qup_spi18_cs: qup-spi
5682 pins = "gpio5
5683 function = "q
5684 };
5685
5686 qup_spi18_cs_gpio: qu
5687 pins = "gpio5
5688 function = "g
5689 };
5690
5691 qup_spi18_data_clk: q
5692 pins = "gpio5
5693 "gpio5
5694 function = "q
5695 };
5696
5697 qup_spi19_cs: qup-spi
5698 pins = "gpio3
5699 function = "q
5700 };
5701
5702 qup_spi19_cs_gpio: qu
5703 pins = "gpio3
5704 function = "g
5705 };
5706
5707 qup_spi19_data_clk: q
5708 pins = "gpio0
5709 "gpio2
5710 function = "q
5711 };
5712
5713 qup_uart2_default: qu
5714 pins = "gpio1
5715 function = "q
5716 };
5717
5718 qup_uart6_default: qu
5719 pins = "gpio1
5720 function = "q
5721 };
5722
5723 qup_uart12_default: q
5724 pins = "gpio3
5725 function = "q
5726 };
5727
5728 qup_uart17_default: q
5729 pins = "gpio5
5730 function = "q
5731 };
5732
5733 qup_uart18_default: q
5734 pins = "gpio5
5735 function = "q
5736 };
5737
5738 tert_mi2s_active: ter
5739 sck-pins {
5740 pins
5741 funct
5742 drive
5743 bias-
5744 };
5745
5746 data0-pins {
5747 pins
5748 funct
5749 drive
5750 bias-
5751 outpu
5752 };
5753
5754 ws-pins {
5755 pins
5756 funct
5757 drive
5758 outpu
5759 };
5760 };
5761
5762 sdc2_sleep_state: sdc
5763 clk-pins {
5764 pins
5765 drive
5766 bias-
5767 };
5768
5769 cmd-pins {
5770 pins
5771 drive
5772 bias-
5773 };
5774
5775 data-pins {
5776 pins
5777 drive
5778 bias-
5779 };
5780 };
5781
5782 pcie0_default_state:
5783 perst-pins {
5784 pins
5785 funct
5786 drive
5787 bias-
5788 };
5789
5790 clkreq-pins {
5791 pins
5792 funct
5793 drive
5794 bias-
5795 };
5796
5797 wake-pins {
5798 pins
5799 funct
5800 drive
5801 bias-
5802 };
5803 };
5804
5805 pcie1_default_state:
5806 perst-pins {
5807 pins
5808 funct
5809 drive
5810 bias-
5811 };
5812
5813 clkreq-pins {
5814 pins
5815 funct
5816 drive
5817 bias-
5818 };
5819
5820 wake-pins {
5821 pins
5822 funct
5823 drive
5824 bias-
5825 };
5826 };
5827
5828 pcie2_default_state:
5829 perst-pins {
5830 pins
5831 funct
5832 drive
5833 bias-
5834 };
5835
5836 clkreq-pins {
5837 pins
5838 funct
5839 drive
5840 bias-
5841 };
5842
5843 wake-pins {
5844 pins
5845 funct
5846 drive
5847 bias-
5848 };
5849 };
5850 };
5851
5852 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm
5854 reg = <0 0x15000000 0
5855 #iommu-cells = <2>;
5856 #global-interrupts =
5857 interrupts = <GIC_SPI
5858 <GIC_SPI
5859 <GIC_SPI
5860 <GIC_SPI
5861 <GIC_SPI
5862 <GIC_SPI
5863 <GIC_SPI
5864 <GIC_SPI
5865 <GIC_SPI
5866 <GIC_SPI
5867 <GIC_SPI
5868 <GIC_SPI
5869 <GIC_SPI
5870 <GIC_SPI
5871 <GIC_SPI
5872 <GIC_SPI
5873 <GIC_SPI
5874 <GIC_SPI
5875 <GIC_SPI
5876 <GIC_SPI
5877 <GIC_SPI
5878 <GIC_SPI
5879 <GIC_SPI
5880 <GIC_SPI
5881 <GIC_SPI
5882 <GIC_SPI
5883 <GIC_SPI
5884 <GIC_SPI
5885 <GIC_SPI
5886 <GIC_SPI
5887 <GIC_SPI
5888 <GIC_SPI
5889 <GIC_SPI
5890 <GIC_SPI
5891 <GIC_SPI
5892 <GIC_SPI
5893 <GIC_SPI
5894 <GIC_SPI
5895 <GIC_SPI
5896 <GIC_SPI
5897 <GIC_SPI
5898 <GIC_SPI
5899 <GIC_SPI
5900 <GIC_SPI
5901 <GIC_SPI
5902 <GIC_SPI
5903 <GIC_SPI
5904 <GIC_SPI
5905 <GIC_SPI
5906 <GIC_SPI
5907 <GIC_SPI
5908 <GIC_SPI
5909 <GIC_SPI
5910 <GIC_SPI
5911 <GIC_SPI
5912 <GIC_SPI
5913 <GIC_SPI
5914 <GIC_SPI
5915 <GIC_SPI
5916 <GIC_SPI
5917 <GIC_SPI
5918 <GIC_SPI
5919 <GIC_SPI
5920 <GIC_SPI
5921 <GIC_SPI
5922 <GIC_SPI
5923 <GIC_SPI
5924 <GIC_SPI
5925 <GIC_SPI
5926 <GIC_SPI
5927 <GIC_SPI
5928 <GIC_SPI
5929 <GIC_SPI
5930 <GIC_SPI
5931 <GIC_SPI
5932 <GIC_SPI
5933 <GIC_SPI
5934 <GIC_SPI
5935 <GIC_SPI
5936 <GIC_SPI
5937 <GIC_SPI
5938 <GIC_SPI
5939 <GIC_SPI
5940 <GIC_SPI
5941 <GIC_SPI
5942 <GIC_SPI
5943 <GIC_SPI
5944 <GIC_SPI
5945 <GIC_SPI
5946 <GIC_SPI
5947 <GIC_SPI
5948 <GIC_SPI
5949 <GIC_SPI
5950 <GIC_SPI
5951 <GIC_SPI
5952 <GIC_SPI
5953 <GIC_SPI
5954 <GIC_SPI
5955 dma-coherent;
5956 };
5957
5958 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm
5960 reg = <0 0x17300000 0
5961
5962 interrupts-extended =
5963
5964
5965
5966
5967 interrupt-names = "wd
5968 "ha
5969
5970 clocks = <&rpmhcc RPM
5971 clock-names = "xo";
5972
5973 power-domains = <&rpm
5974 <&rpm
5975 power-domain-names =
5976
5977 memory-region = <&ads
5978
5979 qcom,qmp = <&aoss_qmp
5980
5981 qcom,smem-states = <&
5982 qcom,smem-state-names
5983
5984 status = "disabled";
5985
5986 glink-edge {
5987 interrupts-ex
5988
5989
5990 mboxes = <&ip
5991
5992
5993 label = "lpas
5994 qcom,remote-p
5995
5996 apr {
5997 compa
5998 qcom,
5999 qcom,
6000 #addr
6001 #size
6002
6003 servi
6004
6005
6006
6007 };
6008
6009 q6afe
6010
6011
6012
6013
6014
6015
6016
6017
6018
6019
6020
6021
6022
6023
6024 };
6025
6026 q6asm
6027
6028
6029
6030
6031
6032
6033
6034
6035
6036
6037 };
6038
6039 q6adm
6040
6041
6042
6043
6044
6045
6046
6047 };
6048 };
6049
6050 fastrpc {
6051 compa
6052 qcom,
6053 label
6054 qcom,
6055 #addr
6056 #size
6057
6058 compu
6059
6060
6061
6062 };
6063
6064 compu
6065
6066
6067
6068 };
6069
6070 compu
6071
6072
6073
6074 };
6075 };
6076 };
6077 };
6078
6079 intc: interrupt-controller@17
6080 compatible = "arm,gic
6081 #interrupt-cells = <3
6082 interrupt-controller;
6083 reg = <0x0 0x17a00000
6084 <0x0 0x17a60000
6085 interrupts = <GIC_PPI
6086 };
6087
6088 watchdog@17c10000 {
6089 compatible = "qcom,ap
6090 reg = <0 0x17c10000 0
6091 clocks = <&sleep_clk>
6092 interrupts = <GIC_SPI
6093 };
6094
6095 timer@17c20000 {
6096 #address-cells = <1>;
6097 #size-cells = <1>;
6098 ranges = <0 0 0 0x200
6099 compatible = "arm,arm
6100 reg = <0x0 0x17c20000
6101 clock-frequency = <19
6102
6103 frame@17c21000 {
6104 frame-number
6105 interrupts =
6106
6107 reg = <0x17c2
6108 <0x17c2
6109 };
6110
6111 frame@17c23000 {
6112 frame-number
6113 interrupts =
6114 reg = <0x17c2
6115 status = "dis
6116 };
6117
6118 frame@17c25000 {
6119 frame-number
6120 interrupts =
6121 reg = <0x17c2
6122 status = "dis
6123 };
6124
6125 frame@17c27000 {
6126 frame-number
6127 interrupts =
6128 reg = <0x17c2
6129 status = "dis
6130 };
6131
6132 frame@17c29000 {
6133 frame-number
6134 interrupts =
6135 reg = <0x17c2
6136 status = "dis
6137 };
6138
6139 frame@17c2b000 {
6140 frame-number
6141 interrupts =
6142 reg = <0x17c2
6143 status = "dis
6144 };
6145
6146 frame@17c2d000 {
6147 frame-number
6148 interrupts =
6149 reg = <0x17c2
6150 status = "dis
6151 };
6152 };
6153
6154 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc";
6156 compatible = "qcom,rp
6157 reg = <0x0 0x18200000
6158 <0x0 0x182100
6159 <0x0 0x182200
6160 reg-names = "drv-0",
6161 interrupts = <GIC_SPI
6162 <GIC_SPI
6163 <GIC_SPI
6164 qcom,tcs-offset = <0x
6165 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC
6167 <WA
6168 power-domains = <&CLU
6169
6170 rpmhcc: clock-control
6171 compatible =
6172 #clock-cells
6173 clock-names =
6174 clocks = <&xo
6175 };
6176
6177 rpmhpd: power-control
6178 compatible =
6179 #power-domain
6180 operating-poi
6181
6182 rpmhpd_opp_ta
6183 compa
6184
6185 rpmhp
6186
6187 };
6188
6189 rpmhp
6190
6191 };
6192
6193 rpmhp
6194
6195 };
6196
6197 rpmhp
6198
6199 };
6200
6201 rpmhp
6202
6203 };
6204
6205 rpmhp
6206
6207 };
6208
6209 rpmhp
6210
6211 };
6212
6213 rpmhp
6214
6215 };
6216
6217 rpmhp
6218
6219 };
6220
6221 rpmhp
6222
6223 };
6224 };
6225 };
6226
6227 apps_bcm_voter: bcm-v
6228 compatible =
6229 };
6230 };
6231
6232 epss_l3: interconnect@1859000
6233 compatible = "qcom,sm
6234 reg = <0 0x18590000 0
6235
6236 clocks = <&rpmhcc RPM
6237 clock-names = "xo", "
6238
6239 #interconnect-cells =
6240 };
6241
6242 cpufreq_hw: cpufreq@18591000
6243 compatible = "qcom,sm
6244 reg = <0 0x18591000 0
6245 <0 0x18592000 0
6246 <0 0x18593000 0
6247 reg-names = "freq-dom
6248 "freq-dom
6249
6250 clocks = <&rpmhcc RPM
6251 clock-names = "xo", "
6252 interrupts = <GIC_SPI
6253 <GIC_SPI
6254 <GIC_SPI
6255 interrupt-names = "dc
6256 #freq-domain-cells =
6257 #clock-cells = <1>;
6258 };
6259 };
6260
6261 sound: sound {
6262 };
6263
6264 timer {
6265 compatible = "arm,armv8-timer
6266 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK
6268 <GIC_PPI 14
6269 (GIC_CPU_MASK
6270 <GIC_PPI 11
6271 (GIC_CPU_MASK
6272 <GIC_PPI 10
6273 (GIC_CPU_MASK
6274 };
6275
6276 thermal-zones {
6277 cpu0-thermal {
6278 polling-delay-passive
6279
6280 thermal-sensors = <&t
6281
6282 trips {
6283 cpu0_alert0:
6284 tempe
6285 hyste
6286 type
6287 };
6288
6289 cpu0_alert1:
6290 tempe
6291 hyste
6292 type
6293 };
6294
6295 cpu0_crit: cp
6296 tempe
6297 hyste
6298 type
6299 };
6300 };
6301
6302 cooling-maps {
6303 map0 {
6304 trip
6305 cooli
6306
6307
6308
6309 };
6310 map1 {
6311 trip
6312 cooli
6313
6314
6315
6316 };
6317 };
6318 };
6319
6320 cpu1-thermal {
6321 polling-delay-passive
6322
6323 thermal-sensors = <&t
6324
6325 trips {
6326 cpu1_alert0:
6327 tempe
6328 hyste
6329 type
6330 };
6331
6332 cpu1_alert1:
6333 tempe
6334 hyste
6335 type
6336 };
6337
6338 cpu1_crit: cp
6339 tempe
6340 hyste
6341 type
6342 };
6343 };
6344
6345 cooling-maps {
6346 map0 {
6347 trip
6348 cooli
6349
6350
6351
6352 };
6353 map1 {
6354 trip
6355 cooli
6356
6357
6358
6359 };
6360 };
6361 };
6362
6363 cpu2-thermal {
6364 polling-delay-passive
6365
6366 thermal-sensors = <&t
6367
6368 trips {
6369 cpu2_alert0:
6370 tempe
6371 hyste
6372 type
6373 };
6374
6375 cpu2_alert1:
6376 tempe
6377 hyste
6378 type
6379 };
6380
6381 cpu2_crit: cp
6382 tempe
6383 hyste
6384 type
6385 };
6386 };
6387
6388 cooling-maps {
6389 map0 {
6390 trip
6391 cooli
6392
6393
6394
6395 };
6396 map1 {
6397 trip
6398 cooli
6399
6400
6401
6402 };
6403 };
6404 };
6405
6406 cpu3-thermal {
6407 polling-delay-passive
6408
6409 thermal-sensors = <&t
6410
6411 trips {
6412 cpu3_alert0:
6413 tempe
6414 hyste
6415 type
6416 };
6417
6418 cpu3_alert1:
6419 tempe
6420 hyste
6421 type
6422 };
6423
6424 cpu3_crit: cp
6425 tempe
6426 hyste
6427 type
6428 };
6429 };
6430
6431 cooling-maps {
6432 map0 {
6433 trip
6434 cooli
6435
6436
6437
6438 };
6439 map1 {
6440 trip
6441 cooli
6442
6443
6444
6445 };
6446 };
6447 };
6448
6449 cpu4-top-thermal {
6450 polling-delay-passive
6451
6452 thermal-sensors = <&t
6453
6454 trips {
6455 cpu4_top_aler
6456 tempe
6457 hyste
6458 type
6459 };
6460
6461 cpu4_top_aler
6462 tempe
6463 hyste
6464 type
6465 };
6466
6467 cpu4_top_crit
6468 tempe
6469 hyste
6470 type
6471 };
6472 };
6473
6474 cooling-maps {
6475 map0 {
6476 trip
6477 cooli
6478
6479
6480
6481 };
6482 map1 {
6483 trip
6484 cooli
6485
6486
6487
6488 };
6489 };
6490 };
6491
6492 cpu5-top-thermal {
6493 polling-delay-passive
6494
6495 thermal-sensors = <&t
6496
6497 trips {
6498 cpu5_top_aler
6499 tempe
6500 hyste
6501 type
6502 };
6503
6504 cpu5_top_aler
6505 tempe
6506 hyste
6507 type
6508 };
6509
6510 cpu5_top_crit
6511 tempe
6512 hyste
6513 type
6514 };
6515 };
6516
6517 cooling-maps {
6518 map0 {
6519 trip
6520 cooli
6521
6522
6523
6524 };
6525 map1 {
6526 trip
6527 cooli
6528
6529
6530
6531 };
6532 };
6533 };
6534
6535 cpu6-top-thermal {
6536 polling-delay-passive
6537
6538 thermal-sensors = <&t
6539
6540 trips {
6541 cpu6_top_aler
6542 tempe
6543 hyste
6544 type
6545 };
6546
6547 cpu6_top_aler
6548 tempe
6549 hyste
6550 type
6551 };
6552
6553 cpu6_top_crit
6554 tempe
6555 hyste
6556 type
6557 };
6558 };
6559
6560 cooling-maps {
6561 map0 {
6562 trip
6563 cooli
6564
6565
6566
6567 };
6568 map1 {
6569 trip
6570 cooli
6571
6572
6573
6574 };
6575 };
6576 };
6577
6578 cpu7-top-thermal {
6579 polling-delay-passive
6580
6581 thermal-sensors = <&t
6582
6583 trips {
6584 cpu7_top_aler
6585 tempe
6586 hyste
6587 type
6588 };
6589
6590 cpu7_top_aler
6591 tempe
6592 hyste
6593 type
6594 };
6595
6596 cpu7_top_crit
6597 tempe
6598 hyste
6599 type
6600 };
6601 };
6602
6603 cooling-maps {
6604 map0 {
6605 trip
6606 cooli
6607
6608
6609
6610 };
6611 map1 {
6612 trip
6613 cooli
6614
6615
6616
6617 };
6618 };
6619 };
6620
6621 cpu4-bottom-thermal {
6622 polling-delay-passive
6623
6624 thermal-sensors = <&t
6625
6626 trips {
6627 cpu4_bottom_a
6628 tempe
6629 hyste
6630 type
6631 };
6632
6633 cpu4_bottom_a
6634 tempe
6635 hyste
6636 type
6637 };
6638
6639 cpu4_bottom_c
6640 tempe
6641 hyste
6642 type
6643 };
6644 };
6645
6646 cooling-maps {
6647 map0 {
6648 trip
6649 cooli
6650
6651
6652
6653 };
6654 map1 {
6655 trip
6656 cooli
6657
6658
6659
6660 };
6661 };
6662 };
6663
6664 cpu5-bottom-thermal {
6665 polling-delay-passive
6666
6667 thermal-sensors = <&t
6668
6669 trips {
6670 cpu5_bottom_a
6671 tempe
6672 hyste
6673 type
6674 };
6675
6676 cpu5_bottom_a
6677 tempe
6678 hyste
6679 type
6680 };
6681
6682 cpu5_bottom_c
6683 tempe
6684 hyste
6685 type
6686 };
6687 };
6688
6689 cooling-maps {
6690 map0 {
6691 trip
6692 cooli
6693
6694
6695
6696 };
6697 map1 {
6698 trip
6699 cooli
6700
6701
6702
6703 };
6704 };
6705 };
6706
6707 cpu6-bottom-thermal {
6708 polling-delay-passive
6709
6710 thermal-sensors = <&t
6711
6712 trips {
6713 cpu6_bottom_a
6714 tempe
6715 hyste
6716 type
6717 };
6718
6719 cpu6_bottom_a
6720 tempe
6721 hyste
6722 type
6723 };
6724
6725 cpu6_bottom_c
6726 tempe
6727 hyste
6728 type
6729 };
6730 };
6731
6732 cooling-maps {
6733 map0 {
6734 trip
6735 cooli
6736
6737
6738
6739 };
6740 map1 {
6741 trip
6742 cooli
6743
6744
6745
6746 };
6747 };
6748 };
6749
6750 cpu7-bottom-thermal {
6751 polling-delay-passive
6752
6753 thermal-sensors = <&t
6754
6755 trips {
6756 cpu7_bottom_a
6757 tempe
6758 hyste
6759 type
6760 };
6761
6762 cpu7_bottom_a
6763 tempe
6764 hyste
6765 type
6766 };
6767
6768 cpu7_bottom_c
6769 tempe
6770 hyste
6771 type
6772 };
6773 };
6774
6775 cooling-maps {
6776 map0 {
6777 trip
6778 cooli
6779
6780
6781
6782 };
6783 map1 {
6784 trip
6785 cooli
6786
6787
6788
6789 };
6790 };
6791 };
6792
6793 aoss0-thermal {
6794 polling-delay-passive
6795
6796 thermal-sensors = <&t
6797
6798 trips {
6799 aoss0_alert0:
6800 tempe
6801 hyste
6802 type
6803 };
6804 };
6805 };
6806
6807 cluster0-thermal {
6808 polling-delay-passive
6809
6810 thermal-sensors = <&t
6811
6812 trips {
6813 cluster0_aler
6814 tempe
6815 hyste
6816 type
6817 };
6818 cluster0_crit
6819 tempe
6820 hyste
6821 type
6822 };
6823 };
6824 };
6825
6826 cluster1-thermal {
6827 polling-delay-passive
6828
6829 thermal-sensors = <&t
6830
6831 trips {
6832 cluster1_aler
6833 tempe
6834 hyste
6835 type
6836 };
6837 cluster1_crit
6838 tempe
6839 hyste
6840 type
6841 };
6842 };
6843 };
6844
6845 gpu-top-thermal {
6846 polling-delay-passive
6847
6848 thermal-sensors = <&t
6849
6850 cooling-maps {
6851 map0 {
6852 trip
6853 cooli
6854 };
6855 };
6856
6857 trips {
6858 gpu_top_alert
6859 tempe
6860 hyste
6861 type
6862 };
6863
6864 trip-point1 {
6865 tempe
6866 hyste
6867 type
6868 };
6869
6870 trip-point2 {
6871 tempe
6872 hyste
6873 type
6874 };
6875 };
6876 };
6877
6878 aoss1-thermal {
6879 polling-delay-passive
6880
6881 thermal-sensors = <&t
6882
6883 trips {
6884 aoss1_alert0:
6885 tempe
6886 hyste
6887 type
6888 };
6889 };
6890 };
6891
6892 wlan-thermal {
6893 polling-delay-passive
6894
6895 thermal-sensors = <&t
6896
6897 trips {
6898 wlan_alert0:
6899 tempe
6900 hyste
6901 type
6902 };
6903 };
6904 };
6905
6906 video-thermal {
6907 polling-delay-passive
6908
6909 thermal-sensors = <&t
6910
6911 trips {
6912 video_alert0:
6913 tempe
6914 hyste
6915 type
6916 };
6917 };
6918 };
6919
6920 mem-thermal {
6921 polling-delay-passive
6922
6923 thermal-sensors = <&t
6924
6925 trips {
6926 mem_alert0: t
6927 tempe
6928 hyste
6929 type
6930 };
6931 };
6932 };
6933
6934 q6-hvx-thermal {
6935 polling-delay-passive
6936
6937 thermal-sensors = <&t
6938
6939 trips {
6940 q6_hvx_alert0
6941 tempe
6942 hyste
6943 type
6944 };
6945 };
6946 };
6947
6948 camera-thermal {
6949 polling-delay-passive
6950
6951 thermal-sensors = <&t
6952
6953 trips {
6954 camera_alert0
6955 tempe
6956 hyste
6957 type
6958 };
6959 };
6960 };
6961
6962 compute-thermal {
6963 polling-delay-passive
6964
6965 thermal-sensors = <&t
6966
6967 trips {
6968 compute_alert
6969 tempe
6970 hyste
6971 type
6972 };
6973 };
6974 };
6975
6976 npu-thermal {
6977 polling-delay-passive
6978
6979 thermal-sensors = <&t
6980
6981 trips {
6982 npu_alert0: t
6983 tempe
6984 hyste
6985 type
6986 };
6987 };
6988 };
6989
6990 gpu-bottom-thermal {
6991 polling-delay-passive
6992
6993 thermal-sensors = <&t
6994
6995 cooling-maps {
6996 map0 {
6997 trip
6998 cooli
6999 };
7000 };
7001
7002 trips {
7003 gpu_bottom_al
7004 tempe
7005 hyste
7006 type
7007 };
7008
7009 trip-point1 {
7010 tempe
7011 hyste
7012 type
7013 };
7014
7015 trip-point2 {
7016 tempe
7017 hyste
7018 type
7019 };
7020 };
7021 };
7022 };
7023 };
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