1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> <<
12 #include <dt-bindings/gpio/gpio.h> <<
13 #include <dt-bindings/interconnect/qcom,osm-l3 11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 12 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 13 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 14 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 16 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 18 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 19 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 <<
25 20
26 / { 21 / {
27 interrupt-parent = <&intc>; 22 interrupt-parent = <&intc>;
28 23
29 #address-cells = <2>; 24 #address-cells = <2>;
30 #size-cells = <2>; 25 #size-cells = <2>;
31 26
32 aliases { 27 aliases {
33 i2c0 = &i2c0; 28 i2c0 = &i2c0;
34 i2c1 = &i2c1; 29 i2c1 = &i2c1;
35 i2c2 = &i2c2; 30 i2c2 = &i2c2;
36 i2c3 = &i2c3; 31 i2c3 = &i2c3;
37 i2c4 = &i2c4; 32 i2c4 = &i2c4;
38 i2c5 = &i2c5; 33 i2c5 = &i2c5;
39 i2c6 = &i2c6; 34 i2c6 = &i2c6;
40 i2c7 = &i2c7; 35 i2c7 = &i2c7;
41 i2c8 = &i2c8; 36 i2c8 = &i2c8;
42 i2c9 = &i2c9; 37 i2c9 = &i2c9;
43 i2c10 = &i2c10; 38 i2c10 = &i2c10;
44 i2c11 = &i2c11; 39 i2c11 = &i2c11;
45 i2c12 = &i2c12; 40 i2c12 = &i2c12;
46 i2c13 = &i2c13; 41 i2c13 = &i2c13;
47 i2c14 = &i2c14; 42 i2c14 = &i2c14;
48 i2c15 = &i2c15; 43 i2c15 = &i2c15;
49 i2c16 = &i2c16; 44 i2c16 = &i2c16;
50 i2c17 = &i2c17; 45 i2c17 = &i2c17;
51 i2c18 = &i2c18; 46 i2c18 = &i2c18;
52 i2c19 = &i2c19; 47 i2c19 = &i2c19;
53 spi0 = &spi0; 48 spi0 = &spi0;
54 spi1 = &spi1; 49 spi1 = &spi1;
55 spi2 = &spi2; 50 spi2 = &spi2;
56 spi3 = &spi3; 51 spi3 = &spi3;
57 spi4 = &spi4; 52 spi4 = &spi4;
58 spi5 = &spi5; 53 spi5 = &spi5;
59 spi6 = &spi6; 54 spi6 = &spi6;
60 spi7 = &spi7; 55 spi7 = &spi7;
61 spi8 = &spi8; 56 spi8 = &spi8;
62 spi9 = &spi9; 57 spi9 = &spi9;
63 spi10 = &spi10; 58 spi10 = &spi10;
64 spi11 = &spi11; 59 spi11 = &spi11;
65 spi12 = &spi12; 60 spi12 = &spi12;
66 spi13 = &spi13; 61 spi13 = &spi13;
67 spi14 = &spi14; 62 spi14 = &spi14;
68 spi15 = &spi15; 63 spi15 = &spi15;
69 spi16 = &spi16; 64 spi16 = &spi16;
70 spi17 = &spi17; 65 spi17 = &spi17;
71 spi18 = &spi18; 66 spi18 = &spi18;
72 spi19 = &spi19; 67 spi19 = &spi19;
73 }; 68 };
74 69
75 chosen { }; 70 chosen { };
76 71
77 clocks { 72 clocks {
78 xo_board: xo-board { 73 xo_board: xo-board {
79 compatible = "fixed-cl 74 compatible = "fixed-clock";
80 #clock-cells = <0>; 75 #clock-cells = <0>;
81 clock-frequency = <384 76 clock-frequency = <38400000>;
82 clock-output-names = " 77 clock-output-names = "xo_board";
83 }; 78 };
84 79
85 sleep_clk: sleep-clk { 80 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 81 compatible = "fixed-clock";
87 clock-frequency = <327 82 clock-frequency = <32768>;
88 #clock-cells = <0>; 83 #clock-cells = <0>;
89 }; 84 };
90 }; 85 };
91 86
92 cpus { 87 cpus {
93 #address-cells = <2>; 88 #address-cells = <2>;
94 #size-cells = <0>; 89 #size-cells = <0>;
95 90
96 CPU0: cpu@0 { 91 CPU0: cpu@0 {
97 device_type = "cpu"; 92 device_type = "cpu";
98 compatible = "qcom,kry 93 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 94 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 95 enable-method = "psci";
102 capacity-dmips-mhz = < 96 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 97 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 98 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ <<
106 power-domain-names = " <<
107 qcom,freq-domain = <&c 99 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <<
109 interconnects = <&gem_ <<
110 <&epss <<
111 #cooling-cells = <2>; 100 #cooling-cells = <2>;
112 L2_0: l2-cache { 101 L2_0: l2-cache {
113 compatible = " 102 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 103 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 104 L3_0: l3-cache {
119 compat 105 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 106 };
124 }; 107 };
125 }; 108 };
126 109
127 CPU1: cpu@100 { 110 CPU1: cpu@100 {
128 device_type = "cpu"; 111 device_type = "cpu";
129 compatible = "qcom,kry 112 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 113 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 114 enable-method = "psci";
133 capacity-dmips-mhz = < 115 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 116 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 117 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ <<
137 power-domain-names = " <<
138 qcom,freq-domain = <&c 118 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <<
140 interconnects = <&gem_ <<
141 <&epss <<
142 #cooling-cells = <2>; 119 #cooling-cells = <2>;
143 L2_100: l2-cache { 120 L2_100: l2-cache {
144 compatible = " 121 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 122 next-level-cache = <&L3_0>;
149 }; 123 };
150 }; 124 };
151 125
152 CPU2: cpu@200 { 126 CPU2: cpu@200 {
153 device_type = "cpu"; 127 device_type = "cpu";
154 compatible = "qcom,kry 128 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 129 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 130 enable-method = "psci";
158 capacity-dmips-mhz = < 131 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 132 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 133 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ <<
162 power-domain-names = " <<
163 qcom,freq-domain = <&c 134 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <<
165 interconnects = <&gem_ <<
166 <&epss <<
167 #cooling-cells = <2>; 135 #cooling-cells = <2>;
168 L2_200: l2-cache { 136 L2_200: l2-cache {
169 compatible = " 137 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 138 next-level-cache = <&L3_0>;
174 }; 139 };
175 }; 140 };
176 141
177 CPU3: cpu@300 { 142 CPU3: cpu@300 {
178 device_type = "cpu"; 143 device_type = "cpu";
179 compatible = "qcom,kry 144 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 145 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 146 enable-method = "psci";
183 capacity-dmips-mhz = < 147 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 148 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 149 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ <<
187 power-domain-names = " <<
188 qcom,freq-domain = <&c 150 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <<
190 interconnects = <&gem_ <<
191 <&epss <<
192 #cooling-cells = <2>; 151 #cooling-cells = <2>;
193 L2_300: l2-cache { 152 L2_300: l2-cache {
194 compatible = " 153 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 154 next-level-cache = <&L3_0>;
199 }; 155 };
200 }; 156 };
201 157
202 CPU4: cpu@400 { 158 CPU4: cpu@400 {
203 device_type = "cpu"; 159 device_type = "cpu";
204 compatible = "qcom,kry 160 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 161 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 162 enable-method = "psci";
208 capacity-dmips-mhz = < 163 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 164 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 165 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ <<
212 power-domain-names = " <<
213 qcom,freq-domain = <&c 166 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <<
215 interconnects = <&gem_ <<
216 <&epss <<
217 #cooling-cells = <2>; 167 #cooling-cells = <2>;
218 L2_400: l2-cache { 168 L2_400: l2-cache {
219 compatible = " 169 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 170 next-level-cache = <&L3_0>;
224 }; 171 };
225 }; 172 };
226 173
227 CPU5: cpu@500 { 174 CPU5: cpu@500 {
228 device_type = "cpu"; 175 device_type = "cpu";
229 compatible = "qcom,kry 176 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 177 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 178 enable-method = "psci";
233 capacity-dmips-mhz = < 179 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 180 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 181 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ <<
237 power-domain-names = " <<
238 qcom,freq-domain = <&c 182 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <<
240 interconnects = <&gem_ <<
241 <&epss <<
242 #cooling-cells = <2>; 183 #cooling-cells = <2>;
243 L2_500: l2-cache { 184 L2_500: l2-cache {
244 compatible = " 185 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 186 next-level-cache = <&L3_0>;
249 }; 187 };
>> 188
250 }; 189 };
251 190
252 CPU6: cpu@600 { 191 CPU6: cpu@600 {
253 device_type = "cpu"; 192 device_type = "cpu";
254 compatible = "qcom,kry 193 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 194 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 195 enable-method = "psci";
258 capacity-dmips-mhz = < 196 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 197 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 198 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ <<
262 power-domain-names = " <<
263 qcom,freq-domain = <&c 199 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <<
265 interconnects = <&gem_ <<
266 <&epss <<
267 #cooling-cells = <2>; 200 #cooling-cells = <2>;
268 L2_600: l2-cache { 201 L2_600: l2-cache {
269 compatible = " 202 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 203 next-level-cache = <&L3_0>;
274 }; 204 };
275 }; 205 };
276 206
277 CPU7: cpu@700 { 207 CPU7: cpu@700 {
278 device_type = "cpu"; 208 device_type = "cpu";
279 compatible = "qcom,kry 209 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 210 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 211 enable-method = "psci";
283 capacity-dmips-mhz = < 212 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 213 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 214 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ <<
287 power-domain-names = " <<
288 qcom,freq-domain = <&c 215 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <<
290 interconnects = <&gem_ <<
291 <&epss <<
292 #cooling-cells = <2>; 216 #cooling-cells = <2>;
293 L2_700: l2-cache { 217 L2_700: l2-cache {
294 compatible = " 218 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 219 next-level-cache = <&L3_0>;
299 }; 220 };
300 }; 221 };
301 222
302 cpu-map { 223 cpu-map {
303 cluster0 { 224 cluster0 {
304 core0 { 225 core0 {
305 cpu = 226 cpu = <&CPU0>;
306 }; 227 };
307 228
308 core1 { 229 core1 {
309 cpu = 230 cpu = <&CPU1>;
310 }; 231 };
311 232
312 core2 { 233 core2 {
313 cpu = 234 cpu = <&CPU2>;
314 }; 235 };
315 236
316 core3 { 237 core3 {
317 cpu = 238 cpu = <&CPU3>;
318 }; 239 };
319 240
320 core4 { 241 core4 {
321 cpu = 242 cpu = <&CPU4>;
322 }; 243 };
323 244
324 core5 { 245 core5 {
325 cpu = 246 cpu = <&CPU5>;
326 }; 247 };
327 248
328 core6 { 249 core6 {
329 cpu = 250 cpu = <&CPU6>;
330 }; 251 };
331 252
332 core7 { 253 core7 {
333 cpu = 254 cpu = <&CPU7>;
334 }; 255 };
335 }; 256 };
336 }; 257 };
337 <<
338 idle-states { <<
339 entry-method = "psci"; <<
340 <<
341 LITTLE_CPU_SLEEP_0: cp <<
342 compatible = " <<
343 idle-state-nam <<
344 arm,psci-suspe <<
345 entry-latency- <<
346 exit-latency-u <<
347 min-residency- <<
348 local-timer-st <<
349 }; <<
350 <<
351 BIG_CPU_SLEEP_0: cpu-s <<
352 compatible = " <<
353 idle-state-nam <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 local-timer-st <<
359 }; <<
360 }; <<
361 <<
362 domain-idle-states { <<
363 CLUSTER_SLEEP_0: clust <<
364 compatible = " <<
365 arm,psci-suspe <<
366 entry-latency- <<
367 exit-latency-u <<
368 min-residency- <<
369 }; <<
370 }; <<
371 }; <<
372 <<
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points <<
381 opp-shared; <<
382 <<
383 cpu0_opp1: opp-300000000 { <<
384 opp-hz = /bits/ 64 <30 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp2: opp-403200000 { <<
389 opp-hz = /bits/ 64 <40 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp3: opp-518400000 { <<
394 opp-hz = /bits/ 64 <51 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp4: opp-614400000 { <<
399 opp-hz = /bits/ 64 <61 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp5: opp-691200000 { <<
404 opp-hz = /bits/ 64 <69 <<
405 opp-peak-kBps = <80000 <<
406 }; <<
407 <<
408 cpu0_opp6: opp-787200000 { <<
409 opp-hz = /bits/ 64 <78 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp7: opp-883200000 { <<
414 opp-hz = /bits/ 64 <88 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp8: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp9: opp-1075200000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp10: opp-1171200000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <18040 <<
431 }; <<
432 <<
433 cpu0_opp11: opp-1248000000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <18040 <<
436 }; <<
437 <<
438 cpu0_opp12: opp-1344000000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp13: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <21880 <<
446 }; <<
447 <<
448 cpu0_opp14: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp15: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <30720 <<
456 }; <<
457 <<
458 cpu0_opp16: opp-1708800000 { <<
459 opp-hz = /bits/ 64 <17 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp17: opp-1804800000 { <<
464 opp-hz = /bits/ 64 <18 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-710400000 { <<
474 opp-hz = /bits/ 64 <71 <<
475 opp-peak-kBps = <18040 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-825600000 { <<
479 opp-hz = /bits/ 64 <82 <<
480 opp-peak-kBps = <21880 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-940800000 { <<
484 opp-hz = /bits/ 64 <94 <<
485 opp-peak-kBps = <21880 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-1056000000 { <<
489 opp-hz = /bits/ 64 <10 <<
490 opp-peak-kBps = <30720 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-1171200000 { <<
494 opp-hz = /bits/ 64 <11 <<
495 opp-peak-kBps = <30720 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-1286400000 { <<
499 opp-hz = /bits/ 64 <12 <<
500 opp-peak-kBps = <40680 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-1382400000 { <<
504 opp-hz = /bits/ 64 <13 <<
505 opp-peak-kBps = <40680 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-1478400000 { <<
509 opp-hz = /bits/ 64 <14 <<
510 opp-peak-kBps = <40680 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-1574400000 { <<
514 opp-hz = /bits/ 64 <15 <<
515 opp-peak-kBps = <54120 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1670400000 { <<
519 opp-hz = /bits/ 64 <16 <<
520 opp-peak-kBps = <54120 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1766400000 { <<
524 opp-hz = /bits/ 64 <17 <<
525 opp-peak-kBps = <54120 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1862400000 { <<
529 opp-hz = /bits/ 64 <18 <<
530 opp-peak-kBps = <62200 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1958400000 { <<
534 opp-hz = /bits/ 64 <19 <<
535 opp-peak-kBps = <62200 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-2054400000 { <<
539 opp-hz = /bits/ 64 <20 <<
540 opp-peak-kBps = <72160 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-2150400000 { <<
544 opp-hz = /bits/ 64 <21 <<
545 opp-peak-kBps = <72160 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-2246400000 { <<
549 opp-hz = /bits/ 64 <22 <<
550 opp-peak-kBps = <72160 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-2342400000 { <<
554 opp-hz = /bits/ 64 <23 <<
555 opp-peak-kBps = <83680 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-2419200000 { <<
559 opp-hz = /bits/ 64 <24 <<
560 opp-peak-kBps = <83680 <<
561 }; <<
562 }; <<
563 <<
564 cpu7_opp_table: opp-table-cpu7 { <<
565 compatible = "operating-points <<
566 opp-shared; <<
567 <<
568 cpu7_opp1: opp-844800000 { <<
569 opp-hz = /bits/ 64 <84 <<
570 opp-peak-kBps = <21880 <<
571 }; <<
572 <<
573 cpu7_opp2: opp-960000000 { <<
574 opp-hz = /bits/ 64 <96 <<
575 opp-peak-kBps = <21880 <<
576 }; <<
577 <<
578 cpu7_opp3: opp-1075200000 { <<
579 opp-hz = /bits/ 64 <10 <<
580 opp-peak-kBps = <30720 <<
581 }; <<
582 <<
583 cpu7_opp4: opp-1190400000 { <<
584 opp-hz = /bits/ 64 <11 <<
585 opp-peak-kBps = <30720 <<
586 }; <<
587 <<
588 cpu7_opp5: opp-1305600000 { <<
589 opp-hz = /bits/ 64 <13 <<
590 opp-peak-kBps = <40680 <<
591 }; <<
592 <<
593 cpu7_opp6: opp-1401600000 { <<
594 opp-hz = /bits/ 64 <14 <<
595 opp-peak-kBps = <40680 <<
596 }; <<
597 <<
598 cpu7_opp7: opp-1516800000 { <<
599 opp-hz = /bits/ 64 <15 <<
600 opp-peak-kBps = <40680 <<
601 }; <<
602 <<
603 cpu7_opp8: opp-1632000000 { <<
604 opp-hz = /bits/ 64 <16 <<
605 opp-peak-kBps = <54120 <<
606 }; <<
607 <<
608 cpu7_opp9: opp-1747200000 { <<
609 opp-hz = /bits/ 64 <17 <<
610 opp-peak-kBps = <54120 <<
611 }; <<
612 <<
613 cpu7_opp10: opp-1862400000 { <<
614 opp-hz = /bits/ 64 <18 <<
615 opp-peak-kBps = <62200 <<
616 }; <<
617 <<
618 cpu7_opp11: opp-1977600000 { <<
619 opp-hz = /bits/ 64 <19 <<
620 opp-peak-kBps = <62200 <<
621 }; <<
622 <<
623 cpu7_opp12: opp-2073600000 { <<
624 opp-hz = /bits/ 64 <20 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu7_opp13: opp-2169600000 { <<
629 opp-hz = /bits/ 64 <21 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 <<
633 cpu7_opp14: opp-2265600000 { <<
634 opp-hz = /bits/ 64 <22 <<
635 opp-peak-kBps = <72160 <<
636 }; <<
637 <<
638 cpu7_opp15: opp-2361600000 { <<
639 opp-hz = /bits/ 64 <23 <<
640 opp-peak-kBps = <83680 <<
641 }; <<
642 <<
643 cpu7_opp16: opp-2457600000 { <<
644 opp-hz = /bits/ 64 <24 <<
645 opp-peak-kBps = <83680 <<
646 }; <<
647 <<
648 cpu7_opp17: opp-2553600000 { <<
649 opp-hz = /bits/ 64 <25 <<
650 opp-peak-kBps = <83680 <<
651 }; <<
652 <<
653 cpu7_opp18: opp-2649600000 { <<
654 opp-hz = /bits/ 64 <26 <<
655 opp-peak-kBps = <83680 <<
656 }; <<
657 <<
658 cpu7_opp19: opp-2745600000 { <<
659 opp-hz = /bits/ 64 <27 <<
660 opp-peak-kBps = <83680 <<
661 }; <<
662 <<
663 cpu7_opp20: opp-2841600000 { <<
664 opp-hz = /bits/ 64 <28 <<
665 opp-peak-kBps = <83680 <<
666 }; <<
667 }; 258 };
668 259
669 firmware { 260 firmware {
670 scm: scm { 261 scm: scm {
671 compatible = "qcom,scm !! 262 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 263 #reset-cells = <1>;
674 }; 264 };
675 }; 265 };
676 266
677 memory@80000000 { 267 memory@80000000 {
678 device_type = "memory"; 268 device_type = "memory";
679 /* We expect the bootloader to 269 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 270 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 271 };
682 272
>> 273 mmcx_reg: mmcx-reg {
>> 274 compatible = "regulator-fixed-domain";
>> 275 power-domains = <&rpmhpd SM8250_MMCX>;
>> 276 required-opps = <&rpmhpd_opp_low_svs>;
>> 277 regulator-name = "MMCX";
>> 278 };
>> 279
683 pmu { 280 pmu {
684 compatible = "arm,armv8-pmuv3" 281 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 282 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 283 };
687 284
688 psci { 285 psci {
689 compatible = "arm,psci-1.0"; 286 compatible = "arm,psci-1.0";
690 method = "smc"; 287 method = "smc";
691 <<
692 CPU_PD0: power-domain-cpu0 { <<
693 #power-domain-cells = <<
694 power-domains = <&CLUS <<
695 domain-idle-states = < <<
696 }; <<
697 <<
698 CPU_PD1: power-domain-cpu1 { <<
699 #power-domain-cells = <<
700 power-domains = <&CLUS <<
701 domain-idle-states = < <<
702 }; <<
703 <<
704 CPU_PD2: power-domain-cpu2 { <<
705 #power-domain-cells = <<
706 power-domains = <&CLUS <<
707 domain-idle-states = < <<
708 }; <<
709 <<
710 CPU_PD3: power-domain-cpu3 { <<
711 #power-domain-cells = <<
712 power-domains = <&CLUS <<
713 domain-idle-states = < <<
714 }; <<
715 <<
716 CPU_PD4: power-domain-cpu4 { <<
717 #power-domain-cells = <<
718 power-domains = <&CLUS <<
719 domain-idle-states = < <<
720 }; <<
721 <<
722 CPU_PD5: power-domain-cpu5 { <<
723 #power-domain-cells = <<
724 power-domains = <&CLUS <<
725 domain-idle-states = < <<
726 }; <<
727 <<
728 CPU_PD6: power-domain-cpu6 { <<
729 #power-domain-cells = <<
730 power-domains = <&CLUS <<
731 domain-idle-states = < <<
732 }; <<
733 <<
734 CPU_PD7: power-domain-cpu7 { <<
735 #power-domain-cells = <<
736 power-domains = <&CLUS <<
737 domain-idle-states = < <<
738 }; <<
739 <<
740 CLUSTER_PD: power-domain-cpu-c <<
741 #power-domain-cells = <<
742 domain-idle-states = < <<
743 }; <<
744 }; <<
745 <<
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; 288 };
764 289
765 reserved-memory { 290 reserved-memory {
766 #address-cells = <2>; 291 #address-cells = <2>;
767 #size-cells = <2>; 292 #size-cells = <2>;
768 ranges; 293 ranges;
769 294
770 hyp_mem: memory@80000000 { 295 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 296 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 297 no-map;
773 }; 298 };
774 299
775 xbl_aop_mem: memory@80700000 { 300 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 301 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 302 no-map;
778 }; 303 };
779 304
780 cmd_db: memory@80860000 { 305 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 306 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 307 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 308 no-map;
784 }; 309 };
785 310
786 smem_mem: memory@80900000 { 311 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 312 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 313 no-map;
789 }; 314 };
790 315
791 removed_mem: memory@80b00000 { 316 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 317 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 318 no-map;
794 }; 319 };
795 320
796 camera_mem: memory@86200000 { 321 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 322 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 323 no-map;
799 }; 324 };
800 325
801 wlan_mem: memory@86700000 { 326 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 327 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 328 no-map;
804 }; 329 };
805 330
806 ipa_fw_mem: memory@86800000 { 331 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 332 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 333 no-map;
809 }; 334 };
810 335
811 ipa_gsi_mem: memory@86810000 { 336 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 337 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 338 no-map;
814 }; 339 };
815 340
816 gpu_mem: memory@8681a000 { 341 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 342 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 343 no-map;
819 }; 344 };
820 345
821 npu_mem: memory@86900000 { 346 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 347 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 348 no-map;
824 }; 349 };
825 350
826 video_mem: memory@86e00000 { 351 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 352 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 353 no-map;
829 }; 354 };
830 355
831 cvp_mem: memory@87300000 { 356 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 357 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 358 no-map;
834 }; 359 };
835 360
836 cdsp_mem: memory@87800000 { 361 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 362 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 363 no-map;
839 }; 364 };
840 365
841 slpi_mem: memory@88c00000 { 366 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 367 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 368 no-map;
844 }; 369 };
845 370
846 adsp_mem: memory@8a100000 { 371 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 372 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 373 no-map;
849 }; 374 };
850 375
851 spss_mem: memory@8be00000 { 376 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 377 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 378 no-map;
854 }; 379 };
855 380
856 cdsp_secure_heap: memory@8bf00 381 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 382 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 383 no-map;
859 }; 384 };
860 }; 385 };
861 386
862 smem { 387 smem {
863 compatible = "qcom,smem"; 388 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 389 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 390 hwlocks = <&tcsr_mutex 3>;
866 }; 391 };
867 392
868 smp2p-adsp { 393 smp2p-adsp {
869 compatible = "qcom,smp2p"; 394 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 395 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 396 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 397 IPCC_MPROC_SIGNAL_SMP2P
873 I 398 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 399 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 400 IPCC_MPROC_SIGNAL_SMP2P>;
876 401
877 qcom,local-pid = <0>; 402 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 403 qcom,remote-pid = <2>;
879 404
880 smp2p_adsp_out: master-kernel 405 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 406 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 407 #qcom,smem-state-cells = <1>;
883 }; 408 };
884 409
885 smp2p_adsp_in: slave-kernel { 410 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 411 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 412 interrupt-controller;
888 #interrupt-cells = <2> 413 #interrupt-cells = <2>;
889 }; 414 };
890 }; 415 };
891 416
892 smp2p-cdsp { 417 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 418 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 419 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 420 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 421 IPCC_MPROC_SIGNAL_SMP2P
897 I 422 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 423 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 424 IPCC_MPROC_SIGNAL_SMP2P>;
900 425
901 qcom,local-pid = <0>; 426 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 427 qcom,remote-pid = <5>;
903 428
904 smp2p_cdsp_out: master-kernel 429 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 430 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 431 #qcom,smem-state-cells = <1>;
907 }; 432 };
908 433
909 smp2p_cdsp_in: slave-kernel { 434 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 435 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 436 interrupt-controller;
912 #interrupt-cells = <2> 437 #interrupt-cells = <2>;
913 }; 438 };
914 }; 439 };
915 440
916 smp2p-slpi { 441 smp2p-slpi {
917 compatible = "qcom,smp2p"; 442 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 443 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 444 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 445 IPCC_MPROC_SIGNAL_SMP2P
921 I 446 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 447 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 448 IPCC_MPROC_SIGNAL_SMP2P>;
924 449
925 qcom,local-pid = <0>; 450 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 451 qcom,remote-pid = <3>;
927 452
928 smp2p_slpi_out: master-kernel 453 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 454 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 455 #qcom,smem-state-cells = <1>;
931 }; 456 };
932 457
933 smp2p_slpi_in: slave-kernel { 458 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 459 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 460 interrupt-controller;
936 #interrupt-cells = <2> 461 #interrupt-cells = <2>;
937 }; 462 };
938 }; 463 };
939 464
940 soc: soc@0 { 465 soc: soc@0 {
941 #address-cells = <2>; 466 #address-cells = <2>;
942 #size-cells = <2>; 467 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 468 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 469 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 470 compatible = "simple-bus";
946 471
947 gcc: clock-controller@100000 { 472 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 473 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 474 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 475 #clock-cells = <1>;
951 #reset-cells = <1>; 476 #reset-cells = <1>;
952 #power-domain-cells = 477 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 478 clock-names = "bi_tcxo",
954 "bi_tcxo 479 "bi_tcxo_ao",
955 "sleep_c 480 "sleep_clk";
956 clocks = <&rpmhcc RPMH 481 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 482 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 483 <&sleep_clk>;
959 }; 484 };
960 485
961 ipcc: mailbox@408000 { 486 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 487 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 488 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 489 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 490 interrupt-controller;
966 #interrupt-cells = <3> 491 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 492 #mbox-cells = <2>;
968 }; 493 };
969 494
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 495 rng: rng@793000 {
983 compatible = "qcom,prn 496 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 497 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 498 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 499 clock-names = "core";
987 }; 500 };
988 501
989 gpi_dma2: dma-controller@80000 !! 502 qup_opp_table: qup-opp-table {
990 compatible = "qcom,sm8 !! 503 compatible = "operating-points-v2";
991 reg = <0 0x00800000 0 !! 504
992 interrupts = <GIC_SPI !! 505 opp-50000000 {
993 <GIC_SPI !! 506 opp-hz = /bits/ 64 <50000000>;
994 <GIC_SPI !! 507 required-opps = <&rpmhpd_opp_min_svs>;
995 <GIC_SPI !! 508 };
996 <GIC_SPI !! 509
997 <GIC_SPI !! 510 opp-75000000 {
998 <GIC_SPI !! 511 opp-hz = /bits/ 64 <75000000>;
999 <GIC_SPI !! 512 required-opps = <&rpmhpd_opp_low_svs>;
1000 <GIC_SPI !! 513 };
1001 <GIC_SPI !! 514
1002 dma-channels = <10>; !! 515 opp-120000000 {
1003 dma-channel-mask = <0 !! 516 opp-hz = /bits/ 64 <120000000>;
1004 iommus = <&apps_smmu !! 517 required-opps = <&rpmhpd_opp_svs>;
1005 #dma-cells = <3>; !! 518 };
1006 status = "disabled"; <<
1007 }; 519 };
1008 520
1009 qupv3_id_2: geniqup@8c0000 { 521 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 522 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 523 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 524 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 525 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 526 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 527 #address-cells = <2>;
1016 #size-cells = <2>; 528 #size-cells = <2>;
1017 iommus = <&apps_smmu 529 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 530 ranges;
1019 status = "disabled"; 531 status = "disabled";
1020 532
1021 i2c14: i2c@880000 { 533 i2c14: i2c@880000 {
1022 compatible = 534 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 535 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 536 clock-names = "se";
1025 clocks = <&gc 537 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 538 pinctrl-names = "default";
1027 pinctrl-0 = < 539 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 540 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 541 #address-cells = <1>;
1040 #size-cells = 542 #size-cells = <0>;
1041 status = "dis 543 status = "disabled";
1042 }; 544 };
1043 545
1044 spi14: spi@880000 { 546 spi14: spi@880000 {
1045 compatible = 547 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 548 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 549 clock-names = "se";
1048 clocks = <&gc 550 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
>> 551 pinctrl-names = "default";
>> 552 pinctrl-0 = <&qup_spi14_default>;
1049 interrupts = 553 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ <<
1051 <&gpi_ <<
1052 dma-names = " <<
1053 power-domains <<
1054 operating-poi <<
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 554 #address-cells = <1>;
1062 #size-cells = 555 #size-cells = <0>;
>> 556 power-domains = <&rpmhpd SM8250_CX>;
>> 557 operating-points-v2 = <&qup_opp_table>;
1063 status = "dis 558 status = "disabled";
1064 }; 559 };
1065 560
1066 i2c15: i2c@884000 { 561 i2c15: i2c@884000 {
1067 compatible = 562 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 563 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 564 clock-names = "se";
1070 clocks = <&gc 565 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 566 pinctrl-names = "default";
1072 pinctrl-0 = < 567 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 568 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ <<
1075 <&gpi_ <<
1076 dma-names = " <<
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 569 #address-cells = <1>;
1085 #size-cells = 570 #size-cells = <0>;
1086 status = "dis 571 status = "disabled";
1087 }; 572 };
1088 573
1089 spi15: spi@884000 { 574 spi15: spi@884000 {
1090 compatible = 575 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 576 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 577 clock-names = "se";
1093 clocks = <&gc 578 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
>> 579 pinctrl-names = "default";
>> 580 pinctrl-0 = <&qup_spi15_default>;
1094 interrupts = 581 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ <<
1096 <&gpi_ <<
1097 dma-names = " <<
1098 power-domains <<
1099 operating-poi <<
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 582 #address-cells = <1>;
1107 #size-cells = 583 #size-cells = <0>;
>> 584 power-domains = <&rpmhpd SM8250_CX>;
>> 585 operating-points-v2 = <&qup_opp_table>;
1108 status = "dis 586 status = "disabled";
1109 }; 587 };
1110 588
1111 i2c16: i2c@888000 { 589 i2c16: i2c@888000 {
1112 compatible = 590 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 591 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 592 clock-names = "se";
1115 clocks = <&gc 593 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 594 pinctrl-names = "default";
1117 pinctrl-0 = < 595 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 596 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ <<
1120 <&gpi_ <<
1121 dma-names = " <<
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 597 #address-cells = <1>;
1130 #size-cells = 598 #size-cells = <0>;
1131 status = "dis 599 status = "disabled";
1132 }; 600 };
1133 601
1134 spi16: spi@888000 { 602 spi16: spi@888000 {
1135 compatible = 603 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 604 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 605 clock-names = "se";
1138 clocks = <&gc 606 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
>> 607 pinctrl-names = "default";
>> 608 pinctrl-0 = <&qup_spi16_default>;
1139 interrupts = 609 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ <<
1141 <&gpi_ <<
1142 dma-names = " <<
1143 power-domains <<
1144 operating-poi <<
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 610 #address-cells = <1>;
1152 #size-cells = 611 #size-cells = <0>;
>> 612 power-domains = <&rpmhpd SM8250_CX>;
>> 613 operating-points-v2 = <&qup_opp_table>;
1153 status = "dis 614 status = "disabled";
1154 }; 615 };
1155 616
1156 i2c17: i2c@88c000 { 617 i2c17: i2c@88c000 {
1157 compatible = 618 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 619 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 620 clock-names = "se";
1160 clocks = <&gc 621 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 622 pinctrl-names = "default";
1162 pinctrl-0 = < 623 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 624 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ <<
1165 <&gpi_ <<
1166 dma-names = " <<
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 625 #address-cells = <1>;
1175 #size-cells = 626 #size-cells = <0>;
1176 status = "dis 627 status = "disabled";
1177 }; 628 };
1178 629
1179 spi17: spi@88c000 { 630 spi17: spi@88c000 {
1180 compatible = 631 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 632 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 633 clock-names = "se";
1183 clocks = <&gc 634 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
>> 635 pinctrl-names = "default";
>> 636 pinctrl-0 = <&qup_spi17_default>;
1184 interrupts = 637 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ <<
1186 <&gpi_ <<
1187 dma-names = " <<
1188 power-domains <<
1189 operating-poi <<
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 638 #address-cells = <1>;
1197 #size-cells = 639 #size-cells = <0>;
>> 640 power-domains = <&rpmhpd SM8250_CX>;
>> 641 operating-points-v2 = <&qup_opp_table>;
1198 status = "dis 642 status = "disabled";
1199 }; 643 };
1200 644
1201 uart17: serial@88c000 645 uart17: serial@88c000 {
1202 compatible = 646 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 647 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 648 clock-names = "se";
1205 clocks = <&gc 649 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 650 pinctrl-names = "default";
1207 pinctrl-0 = < 651 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 652 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 653 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 654 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 655 status = "disabled";
1216 }; 656 };
1217 657
1218 i2c18: i2c@890000 { 658 i2c18: i2c@890000 {
1219 compatible = 659 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 660 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 661 clock-names = "se";
1222 clocks = <&gc 662 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 663 pinctrl-names = "default";
1224 pinctrl-0 = < 664 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 665 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ <<
1227 <&gpi_ <<
1228 dma-names = " <<
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 666 #address-cells = <1>;
1237 #size-cells = 667 #size-cells = <0>;
1238 status = "dis 668 status = "disabled";
1239 }; 669 };
1240 670
1241 spi18: spi@890000 { 671 spi18: spi@890000 {
1242 compatible = 672 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 673 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 674 clock-names = "se";
1245 clocks = <&gc 675 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
>> 676 pinctrl-names = "default";
>> 677 pinctrl-0 = <&qup_spi18_default>;
1246 interrupts = 678 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ <<
1248 <&gpi_ <<
1249 dma-names = " <<
1250 power-domains <<
1251 operating-poi <<
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 679 #address-cells = <1>;
1259 #size-cells = 680 #size-cells = <0>;
>> 681 power-domains = <&rpmhpd SM8250_CX>;
>> 682 operating-points-v2 = <&qup_opp_table>;
1260 status = "dis 683 status = "disabled";
1261 }; 684 };
1262 685
1263 uart18: serial@890000 686 uart18: serial@890000 {
1264 compatible = 687 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 688 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 689 clock-names = "se";
1267 clocks = <&gc 690 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 691 pinctrl-names = "default";
1269 pinctrl-0 = < 692 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 693 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 694 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 695 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 696 status = "disabled";
1278 }; 697 };
1279 698
1280 i2c19: i2c@894000 { 699 i2c19: i2c@894000 {
1281 compatible = 700 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 701 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 702 clock-names = "se";
1284 clocks = <&gc 703 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 704 pinctrl-names = "default";
1286 pinctrl-0 = < 705 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 706 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ <<
1289 <&gpi_ <<
1290 dma-names = " <<
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 707 #address-cells = <1>;
1299 #size-cells = 708 #size-cells = <0>;
1300 status = "dis 709 status = "disabled";
1301 }; 710 };
1302 711
1303 spi19: spi@894000 { 712 spi19: spi@894000 {
1304 compatible = 713 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 714 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 715 clock-names = "se";
1307 clocks = <&gc 716 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
>> 717 pinctrl-names = "default";
>> 718 pinctrl-0 = <&qup_spi19_default>;
1308 interrupts = 719 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ <<
1310 <&gpi_ <<
1311 dma-names = " <<
1312 power-domains <<
1313 operating-poi <<
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 720 #address-cells = <1>;
1321 #size-cells = 721 #size-cells = <0>;
>> 722 power-domains = <&rpmhpd SM8250_CX>;
>> 723 operating-points-v2 = <&qup_opp_table>;
1322 status = "dis 724 status = "disabled";
1323 }; 725 };
1324 }; 726 };
1325 727
1326 gpi_dma0: dma-controller@9000 <<
1327 compatible = "qcom,sm <<
1328 reg = <0 0x00900000 0 <<
1329 interrupts = <GIC_SPI <<
1330 <GIC_SPI <<
1331 <GIC_SPI <<
1332 <GIC_SPI <<
1333 <GIC_SPI <<
1334 <GIC_SPI <<
1335 <GIC_SPI <<
1336 <GIC_SPI <<
1337 <GIC_SPI <<
1338 <GIC_SPI <<
1339 <GIC_SPI <<
1340 <GIC_SPI <<
1341 <GIC_SPI <<
1342 dma-channels = <15>; <<
1343 dma-channel-mask = <0 <<
1344 iommus = <&apps_smmu <<
1345 #dma-cells = <3>; <<
1346 status = "disabled"; <<
1347 }; <<
1348 <<
1349 qupv3_id_0: geniqup@9c0000 { 728 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 729 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 730 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 731 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 732 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 733 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 734 #address-cells = <2>;
1356 #size-cells = <2>; 735 #size-cells = <2>;
1357 iommus = <&apps_smmu 736 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 737 ranges;
1359 status = "disabled"; 738 status = "disabled";
1360 739
1361 i2c0: i2c@980000 { 740 i2c0: i2c@980000 {
1362 compatible = 741 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 742 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 743 clock-names = "se";
1365 clocks = <&gc 744 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 745 pinctrl-names = "default";
1367 pinctrl-0 = < 746 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 747 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ <<
1370 <&gpi_ <<
1371 dma-names = " <<
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 748 #address-cells = <1>;
1380 #size-cells = 749 #size-cells = <0>;
1381 status = "dis 750 status = "disabled";
1382 }; 751 };
1383 752
1384 spi0: spi@980000 { 753 spi0: spi@980000 {
1385 compatible = 754 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 755 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 756 clock-names = "se";
1388 clocks = <&gc 757 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
>> 758 pinctrl-names = "default";
>> 759 pinctrl-0 = <&qup_spi0_default>;
1389 interrupts = 760 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ <<
1391 <&gpi_ <<
1392 dma-names = " <<
1393 power-domains <<
1394 operating-poi <<
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 761 #address-cells = <1>;
1402 #size-cells = 762 #size-cells = <0>;
>> 763 power-domains = <&rpmhpd SM8250_CX>;
>> 764 operating-points-v2 = <&qup_opp_table>;
1403 status = "dis 765 status = "disabled";
1404 }; 766 };
1405 767
1406 i2c1: i2c@984000 { 768 i2c1: i2c@984000 {
1407 compatible = 769 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 770 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 771 clock-names = "se";
1410 clocks = <&gc 772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 773 pinctrl-names = "default";
1412 pinctrl-0 = < 774 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 775 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ <<
1415 <&gpi_ <<
1416 dma-names = " <<
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 776 #address-cells = <1>;
1425 #size-cells = 777 #size-cells = <0>;
1426 status = "dis 778 status = "disabled";
1427 }; 779 };
1428 780
1429 spi1: spi@984000 { 781 spi1: spi@984000 {
1430 compatible = 782 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 783 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 784 clock-names = "se";
1433 clocks = <&gc 785 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
>> 786 pinctrl-names = "default";
>> 787 pinctrl-0 = <&qup_spi1_default>;
1434 interrupts = 788 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ <<
1436 <&gpi_ <<
1437 dma-names = " <<
1438 power-domains <<
1439 operating-poi <<
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 789 #address-cells = <1>;
1447 #size-cells = 790 #size-cells = <0>;
>> 791 power-domains = <&rpmhpd SM8250_CX>;
>> 792 operating-points-v2 = <&qup_opp_table>;
1448 status = "dis 793 status = "disabled";
1449 }; 794 };
1450 795
1451 i2c2: i2c@988000 { 796 i2c2: i2c@988000 {
1452 compatible = 797 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 798 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 799 clock-names = "se";
1455 clocks = <&gc 800 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 801 pinctrl-names = "default";
1457 pinctrl-0 = < 802 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 803 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 804 #address-cells = <1>;
1470 #size-cells = 805 #size-cells = <0>;
1471 status = "dis 806 status = "disabled";
1472 }; 807 };
1473 808
1474 spi2: spi@988000 { 809 spi2: spi@988000 {
1475 compatible = 810 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 811 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 812 clock-names = "se";
1478 clocks = <&gc 813 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
>> 814 pinctrl-names = "default";
>> 815 pinctrl-0 = <&qup_spi2_default>;
1479 interrupts = 816 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ <<
1481 <&gpi_ <<
1482 dma-names = " <<
1483 power-domains <<
1484 operating-poi <<
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 817 #address-cells = <1>;
1492 #size-cells = 818 #size-cells = <0>;
>> 819 power-domains = <&rpmhpd SM8250_CX>;
>> 820 operating-points-v2 = <&qup_opp_table>;
1493 status = "dis 821 status = "disabled";
1494 }; 822 };
1495 823
1496 uart2: serial@988000 824 uart2: serial@988000 {
1497 compatible = 825 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 826 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 827 clock-names = "se";
1500 clocks = <&gc 828 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 829 pinctrl-names = "default";
1502 pinctrl-0 = < 830 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 831 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 832 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 833 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 834 status = "disabled";
1511 }; 835 };
1512 836
1513 i2c3: i2c@98c000 { 837 i2c3: i2c@98c000 {
1514 compatible = 838 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 839 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 840 clock-names = "se";
1517 clocks = <&gc 841 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 842 pinctrl-names = "default";
1519 pinctrl-0 = < 843 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 844 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ <<
1522 <&gpi_ <<
1523 dma-names = " <<
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 845 #address-cells = <1>;
1532 #size-cells = 846 #size-cells = <0>;
1533 status = "dis 847 status = "disabled";
1534 }; 848 };
1535 849
1536 spi3: spi@98c000 { 850 spi3: spi@98c000 {
1537 compatible = 851 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 852 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 853 clock-names = "se";
1540 clocks = <&gc 854 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
>> 855 pinctrl-names = "default";
>> 856 pinctrl-0 = <&qup_spi3_default>;
1541 interrupts = 857 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ <<
1543 <&gpi_ <<
1544 dma-names = " <<
1545 power-domains <<
1546 operating-poi <<
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 858 #address-cells = <1>;
1554 #size-cells = 859 #size-cells = <0>;
>> 860 power-domains = <&rpmhpd SM8250_CX>;
>> 861 operating-points-v2 = <&qup_opp_table>;
1555 status = "dis 862 status = "disabled";
1556 }; 863 };
1557 864
1558 i2c4: i2c@990000 { 865 i2c4: i2c@990000 {
1559 compatible = 866 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 867 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 868 clock-names = "se";
1562 clocks = <&gc 869 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 870 pinctrl-names = "default";
1564 pinctrl-0 = < 871 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 872 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ <<
1567 <&gpi_ <<
1568 dma-names = " <<
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 873 #address-cells = <1>;
1577 #size-cells = 874 #size-cells = <0>;
1578 status = "dis 875 status = "disabled";
1579 }; 876 };
1580 877
1581 spi4: spi@990000 { 878 spi4: spi@990000 {
1582 compatible = 879 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 880 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 881 clock-names = "se";
1585 clocks = <&gc 882 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
>> 883 pinctrl-names = "default";
>> 884 pinctrl-0 = <&qup_spi4_default>;
1586 interrupts = 885 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ <<
1588 <&gpi_ <<
1589 dma-names = " <<
1590 power-domains <<
1591 operating-poi <<
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 886 #address-cells = <1>;
1599 #size-cells = 887 #size-cells = <0>;
>> 888 power-domains = <&rpmhpd SM8250_CX>;
>> 889 operating-points-v2 = <&qup_opp_table>;
1600 status = "dis 890 status = "disabled";
1601 }; 891 };
1602 892
1603 i2c5: i2c@994000 { 893 i2c5: i2c@994000 {
1604 compatible = 894 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 895 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 896 clock-names = "se";
1607 clocks = <&gc 897 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 898 pinctrl-names = "default";
1609 pinctrl-0 = < 899 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 900 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ <<
1612 <&gpi_ <<
1613 dma-names = " <<
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 901 #address-cells = <1>;
1622 #size-cells = 902 #size-cells = <0>;
1623 status = "dis 903 status = "disabled";
1624 }; 904 };
1625 905
1626 spi5: spi@994000 { 906 spi5: spi@994000 {
1627 compatible = 907 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 908 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 909 clock-names = "se";
1630 clocks = <&gc 910 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
>> 911 pinctrl-names = "default";
>> 912 pinctrl-0 = <&qup_spi5_default>;
1631 interrupts = 913 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 power-domains <<
1636 operating-poi <<
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 914 #address-cells = <1>;
1644 #size-cells = 915 #size-cells = <0>;
>> 916 power-domains = <&rpmhpd SM8250_CX>;
>> 917 operating-points-v2 = <&qup_opp_table>;
1645 status = "dis 918 status = "disabled";
1646 }; 919 };
1647 920
1648 i2c6: i2c@998000 { 921 i2c6: i2c@998000 {
1649 compatible = 922 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 923 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 924 clock-names = "se";
1652 clocks = <&gc 925 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 926 pinctrl-names = "default";
1654 pinctrl-0 = < 927 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 928 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ <<
1657 <&gpi_ <<
1658 dma-names = " <<
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 929 #address-cells = <1>;
1667 #size-cells = 930 #size-cells = <0>;
1668 status = "dis 931 status = "disabled";
1669 }; 932 };
1670 933
1671 spi6: spi@998000 { 934 spi6: spi@998000 {
1672 compatible = 935 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 936 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 937 clock-names = "se";
1675 clocks = <&gc 938 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
>> 939 pinctrl-names = "default";
>> 940 pinctrl-0 = <&qup_spi6_default>;
1676 interrupts = 941 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ <<
1678 <&gpi_ <<
1679 dma-names = " <<
1680 power-domains <<
1681 operating-poi <<
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 942 #address-cells = <1>;
1689 #size-cells = 943 #size-cells = <0>;
>> 944 power-domains = <&rpmhpd SM8250_CX>;
>> 945 operating-points-v2 = <&qup_opp_table>;
1690 status = "dis 946 status = "disabled";
1691 }; 947 };
1692 948
1693 uart6: serial@998000 949 uart6: serial@998000 {
1694 compatible = 950 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 951 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 952 clock-names = "se";
1697 clocks = <&gc 953 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 954 pinctrl-names = "default";
1699 pinctrl-0 = < 955 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 956 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 957 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 958 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 959 status = "disabled";
1708 }; 960 };
1709 961
1710 i2c7: i2c@99c000 { 962 i2c7: i2c@99c000 {
1711 compatible = 963 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 964 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 965 clock-names = "se";
1714 clocks = <&gc 966 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 967 pinctrl-names = "default";
1716 pinctrl-0 = < 968 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 969 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ <<
1719 <&gpi_ <<
1720 dma-names = " <<
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 970 #address-cells = <1>;
1729 #size-cells = 971 #size-cells = <0>;
1730 status = "dis 972 status = "disabled";
1731 }; 973 };
1732 974
1733 spi7: spi@99c000 { 975 spi7: spi@99c000 {
1734 compatible = 976 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 977 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 978 clock-names = "se";
1737 clocks = <&gc 979 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> 980 pinctrl-names = "default";
>> 981 pinctrl-0 = <&qup_spi7_default>;
1738 interrupts = 982 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ <<
1740 <&gpi_ <<
1741 dma-names = " <<
1742 power-domains <<
1743 operating-poi <<
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 983 #address-cells = <1>;
1751 #size-cells = 984 #size-cells = <0>;
>> 985 power-domains = <&rpmhpd SM8250_CX>;
>> 986 operating-points-v2 = <&qup_opp_table>;
1752 status = "dis 987 status = "disabled";
1753 }; 988 };
1754 }; 989 };
1755 990
1756 gpi_dma1: dma-controller@a000 <<
1757 compatible = "qcom,sm <<
1758 reg = <0 0x00a00000 0 <<
1759 interrupts = <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 dma-channels = <10>; <<
1770 dma-channel-mask = <0 <<
1771 iommus = <&apps_smmu <<
1772 #dma-cells = <3>; <<
1773 status = "disabled"; <<
1774 }; <<
1775 <<
1776 qupv3_id_1: geniqup@ac0000 { 991 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 992 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 993 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 994 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 995 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 996 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 997 #address-cells = <2>;
1783 #size-cells = <2>; 998 #size-cells = <2>;
1784 iommus = <&apps_smmu 999 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1000 ranges;
1786 status = "disabled"; 1001 status = "disabled";
1787 1002
1788 i2c8: i2c@a80000 { 1003 i2c8: i2c@a80000 {
1789 compatible = 1004 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1005 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1006 clock-names = "se";
1792 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1008 pinctrl-names = "default";
1794 pinctrl-0 = < 1009 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1010 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ <<
1797 <&gpi_ <<
1798 dma-names = " <<
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1011 #address-cells = <1>;
1807 #size-cells = 1012 #size-cells = <0>;
1808 status = "dis 1013 status = "disabled";
1809 }; 1014 };
1810 1015
1811 spi8: spi@a80000 { 1016 spi8: spi@a80000 {
1812 compatible = 1017 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1018 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1019 clock-names = "se";
1815 clocks = <&gc 1020 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
>> 1021 pinctrl-names = "default";
>> 1022 pinctrl-0 = <&qup_spi8_default>;
1816 interrupts = 1023 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ <<
1818 <&gpi_ <<
1819 dma-names = " <<
1820 power-domains <<
1821 operating-poi <<
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1024 #address-cells = <1>;
1829 #size-cells = 1025 #size-cells = <0>;
>> 1026 power-domains = <&rpmhpd SM8250_CX>;
>> 1027 operating-points-v2 = <&qup_opp_table>;
1830 status = "dis 1028 status = "disabled";
1831 }; 1029 };
1832 1030
1833 i2c9: i2c@a84000 { 1031 i2c9: i2c@a84000 {
1834 compatible = 1032 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1033 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1034 clock-names = "se";
1837 clocks = <&gc 1035 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1036 pinctrl-names = "default";
1839 pinctrl-0 = < 1037 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1038 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ <<
1842 <&gpi_ <<
1843 dma-names = " <<
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1039 #address-cells = <1>;
1852 #size-cells = 1040 #size-cells = <0>;
1853 status = "dis 1041 status = "disabled";
1854 }; 1042 };
1855 1043
1856 spi9: spi@a84000 { 1044 spi9: spi@a84000 {
1857 compatible = 1045 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1046 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1047 clock-names = "se";
1860 clocks = <&gc 1048 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
>> 1049 pinctrl-names = "default";
>> 1050 pinctrl-0 = <&qup_spi9_default>;
1861 interrupts = 1051 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ <<
1863 <&gpi_ <<
1864 dma-names = " <<
1865 power-domains <<
1866 operating-poi <<
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1052 #address-cells = <1>;
1874 #size-cells = 1053 #size-cells = <0>;
>> 1054 power-domains = <&rpmhpd SM8250_CX>;
>> 1055 operating-points-v2 = <&qup_opp_table>;
1875 status = "dis 1056 status = "disabled";
1876 }; 1057 };
1877 1058
1878 i2c10: i2c@a88000 { 1059 i2c10: i2c@a88000 {
1879 compatible = 1060 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1061 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1062 clock-names = "se";
1882 clocks = <&gc 1063 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1064 pinctrl-names = "default";
1884 pinctrl-0 = < 1065 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1066 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ <<
1887 <&gpi_ <<
1888 dma-names = " <<
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1067 #address-cells = <1>;
1897 #size-cells = 1068 #size-cells = <0>;
1898 status = "dis 1069 status = "disabled";
1899 }; 1070 };
1900 1071
1901 spi10: spi@a88000 { 1072 spi10: spi@a88000 {
1902 compatible = 1073 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1074 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1075 clock-names = "se";
1905 clocks = <&gc 1076 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
>> 1077 pinctrl-names = "default";
>> 1078 pinctrl-0 = <&qup_spi10_default>;
1906 interrupts = 1079 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ <<
1908 <&gpi_ <<
1909 dma-names = " <<
1910 power-domains <<
1911 operating-poi <<
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1080 #address-cells = <1>;
1919 #size-cells = 1081 #size-cells = <0>;
>> 1082 power-domains = <&rpmhpd SM8250_CX>;
>> 1083 operating-points-v2 = <&qup_opp_table>;
1920 status = "dis 1084 status = "disabled";
1921 }; 1085 };
1922 1086
1923 i2c11: i2c@a8c000 { 1087 i2c11: i2c@a8c000 {
1924 compatible = 1088 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1089 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1090 clock-names = "se";
1927 clocks = <&gc 1091 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1092 pinctrl-names = "default";
1929 pinctrl-0 = < 1093 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1094 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ <<
1932 <&gpi_ <<
1933 dma-names = " <<
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1095 #address-cells = <1>;
1942 #size-cells = 1096 #size-cells = <0>;
1943 status = "dis 1097 status = "disabled";
1944 }; 1098 };
1945 1099
1946 spi11: spi@a8c000 { 1100 spi11: spi@a8c000 {
1947 compatible = 1101 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1102 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1103 clock-names = "se";
1950 clocks = <&gc 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
>> 1105 pinctrl-names = "default";
>> 1106 pinctrl-0 = <&qup_spi11_default>;
1951 interrupts = 1107 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ <<
1953 <&gpi_ <<
1954 dma-names = " <<
1955 power-domains <<
1956 operating-poi <<
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1108 #address-cells = <1>;
1964 #size-cells = 1109 #size-cells = <0>;
>> 1110 power-domains = <&rpmhpd SM8250_CX>;
>> 1111 operating-points-v2 = <&qup_opp_table>;
1965 status = "dis 1112 status = "disabled";
1966 }; 1113 };
1967 1114
1968 i2c12: i2c@a90000 { 1115 i2c12: i2c@a90000 {
1969 compatible = 1116 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1117 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1118 clock-names = "se";
1972 clocks = <&gc 1119 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1120 pinctrl-names = "default";
1974 pinctrl-0 = < 1121 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1122 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ <<
1977 <&gpi_ <<
1978 dma-names = " <<
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1123 #address-cells = <1>;
1987 #size-cells = 1124 #size-cells = <0>;
1988 status = "dis 1125 status = "disabled";
1989 }; 1126 };
1990 1127
1991 spi12: spi@a90000 { 1128 spi12: spi@a90000 {
1992 compatible = 1129 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1130 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1131 clock-names = "se";
1995 clocks = <&gc 1132 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
>> 1133 pinctrl-names = "default";
>> 1134 pinctrl-0 = <&qup_spi12_default>;
1996 interrupts = 1135 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ <<
1998 <&gpi_ <<
1999 dma-names = " <<
2000 power-domains <<
2001 operating-poi <<
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1136 #address-cells = <1>;
2009 #size-cells = 1137 #size-cells = <0>;
>> 1138 power-domains = <&rpmhpd SM8250_CX>;
>> 1139 operating-points-v2 = <&qup_opp_table>;
2010 status = "dis 1140 status = "disabled";
2011 }; 1141 };
2012 1142
2013 uart12: serial@a90000 1143 uart12: serial@a90000 {
2014 compatible = 1144 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1145 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1146 clock-names = "se";
2017 clocks = <&gc 1147 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1148 pinctrl-names = "default";
2019 pinctrl-0 = < 1149 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1150 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1151 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1152 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1153 status = "disabled";
2028 }; 1154 };
2029 1155
2030 i2c13: i2c@a94000 { 1156 i2c13: i2c@a94000 {
2031 compatible = 1157 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1158 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1159 clock-names = "se";
2034 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1161 pinctrl-names = "default";
2036 pinctrl-0 = < 1162 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1163 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ <<
2039 <&gpi_ <<
2040 dma-names = " <<
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1164 #address-cells = <1>;
2049 #size-cells = 1165 #size-cells = <0>;
2050 status = "dis 1166 status = "disabled";
2051 }; 1167 };
2052 1168
2053 spi13: spi@a94000 { 1169 spi13: spi@a94000 {
2054 compatible = 1170 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1171 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1172 clock-names = "se";
2057 clocks = <&gc 1173 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
>> 1174 pinctrl-names = "default";
>> 1175 pinctrl-0 = <&qup_spi13_default>;
2058 interrupts = 1176 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ <<
2060 <&gpi_ <<
2061 dma-names = " <<
2062 power-domains <<
2063 operating-poi <<
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1177 #address-cells = <1>;
2071 #size-cells = 1178 #size-cells = <0>;
>> 1179 power-domains = <&rpmhpd SM8250_CX>;
>> 1180 operating-points-v2 = <&qup_opp_table>;
2072 status = "dis 1181 status = "disabled";
2073 }; 1182 };
2074 }; 1183 };
2075 1184
2076 config_noc: interconnect@1500 1185 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1186 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1187 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1188 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1189 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1190 };
2082 1191
2083 system_noc: interconnect@1620 1192 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1193 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1194 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1195 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1196 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1197 };
2089 1198
2090 mc_virt: interconnect@163d000 1199 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1200 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1201 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1202 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1203 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1204 };
2096 1205
2097 aggre1_noc: interconnect@16e0 1206 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1207 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1208 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1209 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1210 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1211 };
2103 1212
2104 aggre2_noc: interconnect@1700 1213 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1214 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1215 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1216 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1217 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1218 };
2110 1219
2111 compute_noc: interconnect@173 1220 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1221 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1222 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1223 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1224 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1225 };
2117 1226
2118 mmss_noc: interconnect@174000 1227 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1228 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1229 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1230 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1231 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1232 };
2124 1233
2125 pcie0: pcie@1c00000 { !! 1234 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1235 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1236 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1237 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1238 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1239 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1240 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1241 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1242 device_type = "pci";
2135 linux,pci-domain = <0 1243 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1244 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1245 num-lanes = <1>;
2138 1246
2139 #address-cells = <3>; 1247 #address-cells = <3>;
2140 #size-cells = <2>; 1248 #size-cells = <2>;
2141 1249
2142 ranges = <0x01000000 !! 1250 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1251 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1252
2145 interrupts = <GIC_SPI !! 1253 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1254 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1255 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1256 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1257 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1258 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1259 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1260 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1261
2168 clocks = <&gcc GCC_PC 1262 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1263 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1264 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1265 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1266 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1267 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1268 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1269 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1270 clock-names = "pipe",
2177 "aux", 1271 "aux",
2178 "cfg", 1272 "cfg",
2179 "bus_ma 1273 "bus_master",
2180 "bus_sl 1274 "bus_slave",
2181 "slave_ 1275 "slave_q2a",
2182 "tbu", 1276 "tbu",
2183 "ddrss_ 1277 "ddrss_sf_tbu";
2184 1278
>> 1279 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1280 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1281 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1282
2188 resets = <&gcc GCC_PC 1283 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1284 reset-names = "pci";
2190 1285
2191 power-domains = <&gcc 1286 power-domains = <&gcc PCIE_0_GDSC>;
2192 1287
2193 phys = <&pcie0_phy>; !! 1288 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1289 phy-names = "pciephy";
2195 1290
2196 perst-gpios = <&tlmm <<
2197 wake-gpios = <&tlmm 8 <<
2198 <<
2199 pinctrl-names = "defa <<
2200 pinctrl-0 = <&pcie0_d <<
2201 dma-coherent; <<
2202 <<
2203 status = "disabled"; 1291 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1292 };
2215 1293
2216 pcie0_phy: phy@1c06000 { 1294 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1295 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1296 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1297 #address-cells = <2>;
>> 1298 #size-cells = <2>;
>> 1299 ranges;
2220 clocks = <&gcc GCC_PC 1300 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1301 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1302 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1303 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1304 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1305
2236 resets = <&gcc GCC_PC 1306 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1307 reset-names = "phy";
2238 1308
2239 assigned-clocks = <&g 1309 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1310 assigned-clock-rates = <100000000>;
2241 1311
2242 status = "disabled"; 1312 status = "disabled";
>> 1313
>> 1314 pcie0_lane: lanes@1c06200 {
>> 1315 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1316 <0 0x1c06400 0 0x200>, /* rx */
>> 1317 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1318 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1319 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1320 clock-names = "pipe0";
>> 1321
>> 1322 #phy-cells = <0>;
>> 1323 clock-output-names = "pcie_0_pipe_clk";
>> 1324 };
2243 }; 1325 };
2244 1326
2245 pcie1: pcie@1c08000 { !! 1327 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1328 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1329 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1330 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1331 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1332 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1333 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1334 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1335 device_type = "pci";
2255 linux,pci-domain = <1 1336 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1337 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1338 num-lanes = <2>;
2258 1339
2259 #address-cells = <3>; 1340 #address-cells = <3>;
2260 #size-cells = <2>; 1341 #size-cells = <2>;
2261 1342
2262 ranges = <0x01000000 !! 1343 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1344 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1345
2265 interrupts = <GIC_SPI !! 1346 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
2266 <GIC_SPI !! 1347 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1348 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1349 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1350 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1351 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1352 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1353 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1354
2288 clocks = <&gcc GCC_PC 1355 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1356 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1357 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1358 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1359 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1360 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1361 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1362 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1363 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1364 clock-names = "pipe",
2298 "aux", 1365 "aux",
2299 "cfg", 1366 "cfg",
2300 "bus_ma 1367 "bus_master",
2301 "bus_sl 1368 "bus_slave",
2302 "slave_ 1369 "slave_q2a",
2303 "ref", 1370 "ref",
2304 "tbu", 1371 "tbu",
2305 "ddrss_ 1372 "ddrss_sf_tbu";
2306 1373
2307 assigned-clocks = <&g 1374 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1375 assigned-clock-rates = <19200000>;
2309 1376
>> 1377 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1378 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1379 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1380
2313 resets = <&gcc GCC_PC 1381 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1382 reset-names = "pci";
2315 1383
2316 power-domains = <&gcc 1384 power-domains = <&gcc PCIE_1_GDSC>;
2317 1385
2318 phys = <&pcie1_phy>; !! 1386 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1387 phy-names = "pciephy";
2320 1388
2321 perst-gpios = <&tlmm <<
2322 wake-gpios = <&tlmm 8 <<
2323 <<
2324 pinctrl-names = "defa <<
2325 pinctrl-0 = <&pcie1_d <<
2326 dma-coherent; <<
2327 <<
2328 status = "disabled"; 1389 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1390 };
2340 1391
2341 pcie1_phy: phy@1c0e000 { 1392 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1393 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1394 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1395 #address-cells = <2>;
>> 1396 #size-cells = <2>;
>> 1397 ranges;
2345 clocks = <&gcc GCC_PC 1398 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1399 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1400 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1401 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1402 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1403
2361 resets = <&gcc GCC_PC 1404 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1405 reset-names = "phy";
2363 1406
2364 assigned-clocks = <&g 1407 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1408 assigned-clock-rates = <100000000>;
2366 1409
2367 status = "disabled"; 1410 status = "disabled";
>> 1411
>> 1412 pcie1_lane: lanes@1c0e200 {
>> 1413 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1414 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1415 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1416 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1417 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1418 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1419 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1420 clock-names = "pipe0";
>> 1421
>> 1422 #phy-cells = <0>;
>> 1423 clock-output-names = "pcie_1_pipe_clk";
>> 1424 };
2368 }; 1425 };
2369 1426
2370 pcie2: pcie@1c10000 { !! 1427 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 1428 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 1429 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 1430 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 1431 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 1432 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 1433 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 1434 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 1435 device_type = "pci";
2380 linux,pci-domain = <2 1436 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 1437 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 1438 num-lanes = <2>;
2383 1439
2384 #address-cells = <3>; 1440 #address-cells = <3>;
2385 #size-cells = <2>; 1441 #size-cells = <2>;
2386 1442
2387 ranges = <0x01000000 !! 1443 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 1444 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 1445
2390 interrupts = <GIC_SPI !! 1446 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
2391 <GIC_SPI !! 1447 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 1448 #interrupt-cells = <1>;
2407 interrupt-map-mask = 1449 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 1450 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 1451 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 1452 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 1453 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 1454
2413 clocks = <&gcc GCC_PC 1455 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 1456 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 1457 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 1458 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 1459 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 1460 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 1461 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 1462 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 1463 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 1464 clock-names = "pipe",
2423 "aux", 1465 "aux",
2424 "cfg", 1466 "cfg",
2425 "bus_ma 1467 "bus_master",
2426 "bus_sl 1468 "bus_slave",
2427 "slave_ 1469 "slave_q2a",
2428 "ref", 1470 "ref",
2429 "tbu", 1471 "tbu",
2430 "ddrss_ 1472 "ddrss_sf_tbu";
2431 1473
2432 assigned-clocks = <&g 1474 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 1475 assigned-clock-rates = <19200000>;
2434 1476
>> 1477 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 1478 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 1479 <0x100 &apps_smmu 0x1d01 0x1>;
2437 1480
2438 resets = <&gcc GCC_PC 1481 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 1482 reset-names = "pci";
2440 1483
2441 power-domains = <&gcc 1484 power-domains = <&gcc PCIE_2_GDSC>;
2442 1485
2443 phys = <&pcie2_phy>; !! 1486 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 1487 phy-names = "pciephy";
2445 1488
2446 perst-gpios = <&tlmm <<
2447 wake-gpios = <&tlmm 8 <<
2448 <<
2449 pinctrl-names = "defa <<
2450 pinctrl-0 = <&pcie2_d <<
2451 dma-coherent; <<
2452 <<
2453 status = "disabled"; 1489 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 1490 };
2465 1491
2466 pcie2_phy: phy@1c16000 { 1492 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 1493 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 1494 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 1495 #address-cells = <2>;
>> 1496 #size-cells = <2>;
>> 1497 ranges;
2470 clocks = <&gcc GCC_PC 1498 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 1499 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 1500 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 1501 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 1502 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 1503
2486 resets = <&gcc GCC_PC 1504 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 1505 reset-names = "phy";
2488 1506
2489 assigned-clocks = <&g 1507 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 1508 assigned-clock-rates = <100000000>;
2491 1509
2492 status = "disabled"; 1510 status = "disabled";
>> 1511
>> 1512 pcie2_lane: lanes@1c0e200 {
>> 1513 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 1514 <0 0x1c16400 0 0x200>, /* rx0 */
>> 1515 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 1516 <0 0x1c16600 0 0x170>, /* tx1 */
>> 1517 <0 0x1c16800 0 0x200>, /* rx1 */
>> 1518 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1519 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 1520 clock-names = "pipe0";
>> 1521
>> 1522 #phy-cells = <0>;
>> 1523 clock-output-names = "pcie_2_pipe_clk";
>> 1524 };
2493 }; 1525 };
2494 1526
2495 ufs_mem_hc: ufshc@1d84000 { 1527 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 1528 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 1529 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 1530 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 1531 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 1532 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 1533 phy-names = "ufsphy";
2502 lanes-per-direction = 1534 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 1535 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 1536 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 1537 reset-names = "rst";
2506 1538
2507 power-domains = <&gcc 1539 power-domains = <&gcc UFS_PHY_GDSC>;
2508 1540
2509 iommus = <&apps_smmu 1541 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 1542
2511 clock-names = 1543 clock-names =
2512 "core_clk", 1544 "core_clk",
2513 "bus_aggr_clk 1545 "bus_aggr_clk",
2514 "iface_clk", 1546 "iface_clk",
2515 "core_clk_uni 1547 "core_clk_unipro",
2516 "ref_clk", 1548 "ref_clk",
2517 "tx_lane0_syn 1549 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 1550 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 1551 "rx_lane1_sync_clk";
2520 clocks = 1552 clocks =
2521 <&gcc GCC_UFS 1553 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 1554 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 1555 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 1556 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 1557 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 1558 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 1559 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 1560 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 1561 freq-table-hz =
2530 operating-points-v2 = !! 1562 <37500000 300000000>,
2531 !! 1563 <0 0>,
2532 interconnects = <&agg !! 1564 <0 0>,
2533 <&gem !! 1565 <37500000 300000000>,
2534 interconnect-names = !! 1566 <0 0>,
>> 1567 <0 0>,
>> 1568 <0 0>,
>> 1569 <0 0>;
2535 1570
2536 status = "disabled"; 1571 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 1572 };
2566 1573
2567 ufs_mem_phy: phy@1d87000 { 1574 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 1575 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 1576 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 1577 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 1578 #size-cells = <2>;
2572 <&gcc GCC_UF !! 1579 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 1580 clock-names = "ref",
2575 "ref_au !! 1581 "ref_aux";
2576 "qref"; !! 1582 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 1583 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 1584
2578 resets = <&ufs_mem_hc 1585 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 1586 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 1587 status = "disabled";
>> 1588
>> 1589 ufs_mem_phy_lanes: lanes@1d87400 {
>> 1590 reg = <0 0x01d87400 0 0x108>,
>> 1591 <0 0x01d87600 0 0x1e0>,
>> 1592 <0 0x01d87c00 0 0x1dc>,
>> 1593 <0 0x01d87800 0 0x108>,
>> 1594 <0 0x01d87a00 0 0x1e0>;
>> 1595 #phy-cells = <0>;
>> 1596 };
2586 }; 1597 };
2587 1598
2588 cryptobam: dma-controller@1dc !! 1599 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 1600 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 1601 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 1602 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 1603 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 1604 };
2619 1605
2620 tcsr_mutex: hwlock@1f40000 { 1606 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 1607 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 1608 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 1609 #hwlock-cells = <1>;
2624 }; 1610 };
2625 1611
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 1612 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 1613 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 1614 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 1615 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 1616 <&audiocc 0>,
2636 <&q6afecc LP 1617 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 1618 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1619 <&aoncc 0>,
2638 <&vamacro>; 1620 <&vamacro>;
2639 1621
2640 clock-names = "mclk", !! 1622 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 1623
2642 #clock-cells = <0>; 1624 #clock-cells = <0>;
>> 1625 clock-frequency = <9600000>;
2643 clock-output-names = 1626 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 1627 #sound-dai-cells = <1>;
2645 1628
2646 pinctrl-names = "defa 1629 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 1630 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 1631 };
2651 1632
2652 swr0: soundwire@3250000 { !! 1633 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 1634 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 1635 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 1636 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 1637 clocks = <&wsamacro>;
2657 clock-names = "iface" 1638 clock-names = "iface";
2658 1639
2659 qcom,din-ports = <2>; 1640 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 1641 qcom,dout-ports = <6>;
2661 1642
2662 qcom,ports-sinterval- 1643 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 1644 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 1645 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 1646 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 1647
2667 #sound-dai-cells = <1 1648 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 1649 #address-cells = <2>;
2669 #size-cells = <0>; 1650 #size-cells = <0>;
>> 1651 };
2670 1652
2671 status = "disabled"; !! 1653 audiocc: clock-controller@3300000 {
>> 1654 compatible = "qcom,sm8250-lpass-audiocc";
>> 1655 reg = <0 0x03300000 0 0x30000>;
>> 1656 #clock-cells = <1>;
>> 1657 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1658 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1659 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 1660 clock-names = "core", "audio", "bus";
2672 }; 1661 };
2673 1662
2674 vamacro: codec@3370000 { 1663 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 1664 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 1665 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 1666 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 1667 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 1668 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 1669
2681 clock-names = "mclk", 1670 clock-names = "mclk", "macro", "dcodec";
2682 1671
2683 #clock-cells = <0>; 1672 #clock-cells = <0>;
>> 1673 clock-frequency = <9600000>;
2684 clock-output-names = 1674 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 1675 #sound-dai-cells = <1>;
2686 }; 1676 };
2687 1677
2688 rxmacro: rxmacro@3200000 { !! 1678 aoncc: clock-controller@3380000 {
2689 pinctrl-names = "defa !! 1679 compatible = "qcom,sm8250-lpass-aoncc";
2690 pinctrl-0 = <&rx_swr_ !! 1680 reg = <0 0x03380000 0 0x40000>;
2691 compatible = "qcom,sm !! 1681 #clock-cells = <1>;
2692 reg = <0 0x03200000 0 !! 1682 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2693 status = "disabled"; <<
2694 <<
2695 clocks = <&q6afecc LP <<
2696 <&q6afecc LPA <<
2697 <&q6afecc LPA <<
2698 <&q6afecc LPA 1683 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; !! 1684 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2700 !! 1685 clock-names = "core", "audio", "bus";
2701 clock-names = "mclk", <<
2702 <<
2703 #clock-cells = <0>; <<
2704 clock-output-names = <<
2705 #sound-dai-cells = <1 <<
2706 }; 1686 };
2707 1687
2708 swr1: soundwire@3210000 { !! 1688 lpass_tlmm: pinctrl@33c0000{
2709 reg = <0 0x03210000 0 <<
2710 compatible = "qcom,so <<
2711 status = "disabled"; <<
2712 interrupts = <GIC_SPI <<
2713 clocks = <&rxmacro>; <<
2714 clock-names = "iface" <<
2715 label = "RX"; <<
2716 qcom,din-ports = <0>; <<
2717 qcom,dout-ports = <5> <<
2718 <<
2719 qcom,ports-sinterval- <<
2720 qcom,ports-offset1 = <<
2721 qcom,ports-offset2 = <<
2722 qcom,ports-hstart = <<
2723 qcom,ports-hstop = <<
2724 qcom,ports-word-lengt <<
2725 qcom,ports-block-pack <<
2726 qcom,ports-lane-contr <<
2727 qcom,ports-block-grou <<
2728 <<
2729 #sound-dai-cells = <1 <<
2730 #address-cells = <2>; <<
2731 #size-cells = <0>; <<
2732 }; <<
2733 <<
2734 txmacro: txmacro@3220000 { <<
2735 pinctrl-names = "defa <<
2736 pinctrl-0 = <&tx_swr_ <<
2737 compatible = "qcom,sm <<
2738 reg = <0 0x03220000 0 <<
2739 status = "disabled"; <<
2740 <<
2741 clocks = <&q6afecc LP <<
2742 <&q6afecc LP <<
2743 <&q6afecc LP <<
2744 <&q6afecc LP <<
2745 <&vamacro>; <<
2746 <<
2747 clock-names = "mclk", <<
2748 <<
2749 #clock-cells = <0>; <<
2750 clock-output-names = <<
2751 #sound-dai-cells = <1 <<
2752 }; <<
2753 <<
2754 /* tx macro */ <<
2755 swr2: soundwire@3230000 { <<
2756 reg = <0 0x03230000 0 <<
2757 compatible = "qcom,so <<
2758 interrupts = <GIC_SPI <<
2759 interrupt-names = "co <<
2760 status = "disabled"; <<
2761 <<
2762 clocks = <&txmacro>; <<
2763 clock-names = "iface" <<
2764 label = "TX"; <<
2765 <<
2766 qcom,din-ports = <5>; <<
2767 qcom,dout-ports = <0> <<
2768 qcom,ports-sinterval- <<
2769 qcom,ports-offset1 = <<
2770 qcom,ports-offset2 = <<
2771 qcom,ports-block-pack <<
2772 qcom,ports-hstart = <<
2773 qcom,ports-hstop = <<
2774 qcom,ports-word-lengt <<
2775 qcom,ports-block-grou <<
2776 qcom,ports-lane-contr <<
2777 #sound-dai-cells = <1 <<
2778 #address-cells = <2>; <<
2779 #size-cells = <0>; <<
2780 }; <<
2781 <<
2782 lpass_tlmm: pinctrl@33c0000 { <<
2783 compatible = "qcom,sm 1689 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 1690 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 1691 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 1692 gpio-controller;
2787 #gpio-cells = <2>; 1693 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 1694 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 1695
2790 clocks = <&q6afecc LP 1696 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 1697 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 1698 clock-names = "core", "audio";
2793 1699
2794 wsa_swr_active: wsa-s !! 1700 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 1701 clk {
2796 pins 1702 pins = "gpio10";
2797 funct 1703 function = "wsa_swr_clk";
2798 drive 1704 drive-strength = <2>;
2799 slew- 1705 slew-rate = <1>;
2800 bias- 1706 bias-disable;
2801 }; 1707 };
2802 1708
2803 data-pins { !! 1709 data {
2804 pins 1710 pins = "gpio11";
2805 funct 1711 function = "wsa_swr_data";
2806 drive 1712 drive-strength = <2>;
2807 slew- 1713 slew-rate = <1>;
2808 bias- 1714 bias-bus-hold;
>> 1715
2809 }; 1716 };
2810 }; 1717 };
2811 1718
2812 wsa_swr_sleep: wsa-sw !! 1719 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 1720 clk {
2814 pins 1721 pins = "gpio10";
2815 funct 1722 function = "wsa_swr_clk";
2816 drive 1723 drive-strength = <2>;
>> 1724 input-enable;
2817 bias- 1725 bias-pull-down;
2818 }; 1726 };
2819 1727
2820 data-pins { !! 1728 data {
2821 pins 1729 pins = "gpio11";
2822 funct 1730 function = "wsa_swr_data";
2823 drive 1731 drive-strength = <2>;
>> 1732 input-enable;
2824 bias- 1733 bias-pull-down;
>> 1734
2825 }; 1735 };
2826 }; 1736 };
2827 1737
2828 dmic01_active: dmic01 !! 1738 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 1739 clk {
2830 pins 1740 pins = "gpio6";
2831 funct 1741 function = "dmic1_clk";
2832 drive 1742 drive-strength = <8>;
2833 outpu 1743 output-high;
2834 }; 1744 };
2835 data-pins { !! 1745 data {
2836 pins 1746 pins = "gpio7";
2837 funct 1747 function = "dmic1_data";
2838 drive 1748 drive-strength = <8>;
>> 1749 input-enable;
2839 }; 1750 };
2840 }; 1751 };
2841 1752
2842 dmic01_sleep: dmic01- !! 1753 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 1754 clk {
2844 pins 1755 pins = "gpio6";
2845 funct 1756 function = "dmic1_clk";
2846 drive 1757 drive-strength = <2>;
2847 bias- 1758 bias-disable;
2848 outpu 1759 output-low;
2849 }; 1760 };
2850 1761
2851 data-pins { !! 1762 data {
2852 pins 1763 pins = "gpio7";
2853 funct 1764 function = "dmic1_data";
2854 drive 1765 drive-strength = <2>;
2855 bias- !! 1766 pull-down;
2856 }; !! 1767 input-enable;
2857 }; <<
2858 <<
2859 rx_swr_active: rx-swr <<
2860 clk-pins { <<
2861 pins <<
2862 funct <<
2863 drive <<
2864 slew- <<
2865 bias- <<
2866 }; <<
2867 <<
2868 data-pins { <<
2869 pins <<
2870 funct <<
2871 drive <<
2872 slew- <<
2873 bias- <<
2874 }; <<
2875 }; <<
2876 <<
2877 tx_swr_active: tx-swr <<
2878 clk-pins { <<
2879 pins <<
2880 funct <<
2881 drive <<
2882 slew- <<
2883 bias- <<
2884 }; <<
2885 <<
2886 data-pins { <<
2887 pins <<
2888 funct <<
2889 drive <<
2890 slew- <<
2891 bias- <<
2892 }; <<
2893 }; <<
2894 <<
2895 tx_swr_sleep: tx-swr- <<
2896 clk-pins { <<
2897 pins <<
2898 funct <<
2899 drive <<
2900 bias- <<
2901 }; <<
2902 <<
2903 data1-pins { <<
2904 pins <<
2905 funct <<
2906 drive <<
2907 bias- <<
2908 }; <<
2909 <<
2910 data2-pins { <<
2911 pins <<
2912 funct <<
2913 drive <<
2914 bias- <<
2915 }; 1768 };
2916 }; 1769 };
2917 }; 1770 };
2918 1771
2919 gpu: gpu@3d00000 { 1772 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 1773 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 1774 "qcom,adreno";
>> 1775 #stream-id-cells = <16>;
2922 1776
2923 reg = <0 0x03d00000 0 1777 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 1778 reg-names = "kgsl_3d0_reg_memory";
2925 1779
2926 interrupts = <GIC_SPI 1780 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 1781
2928 iommus = <&adreno_smm 1782 iommus = <&adreno_smmu 0 0x401>;
2929 1783
2930 operating-points-v2 = 1784 operating-points-v2 = <&gpu_opp_table>;
2931 1785
2932 qcom,gmu = <&gmu>; 1786 qcom,gmu = <&gmu>;
2933 1787
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; <<
2939 <<
2940 zap-shader { 1788 zap-shader {
2941 memory-region 1789 memory-region = <&gpu_mem>;
2942 }; 1790 };
2943 1791
>> 1792 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 1793 gpu_opp_table: opp-table {
2945 compatible = 1794 compatible = "operating-points-v2";
2946 1795
2947 opp-670000000 1796 opp-670000000 {
2948 opp-h 1797 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 1798 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 1799 };
2952 1800
2953 opp-587000000 1801 opp-587000000 {
2954 opp-h 1802 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 1803 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 1804 };
2958 1805
2959 opp-525000000 1806 opp-525000000 {
2960 opp-h 1807 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 1808 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 1809 };
2964 1810
2965 opp-490000000 1811 opp-490000000 {
2966 opp-h 1812 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 1813 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 1814 };
2970 1815
2971 opp-441600000 1816 opp-441600000 {
2972 opp-h 1817 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 1819 };
2976 1820
2977 opp-400000000 1821 opp-400000000 {
2978 opp-h 1822 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 1823 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 1824 };
2982 1825
2983 opp-305000000 1826 opp-305000000 {
2984 opp-h 1827 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 1828 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 1829 };
2988 }; 1830 };
2989 }; 1831 };
2990 1832
2991 gmu: gmu@3d6a000 { 1833 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 1834 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 1835
2994 reg = <0 0x03d6a000 0 1836 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 1837 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 1838 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 1839 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 1840 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 1841
3000 interrupts = <GIC_SPI 1842 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 1843 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 1844 interrupt-names = "hfi", "gmu";
3003 1845
3004 clocks = <&gpucc GPU_ 1846 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 1847 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 1848 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 1849 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 1850 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 1851 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 1852
3011 power-domains = <&gpu 1853 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 1854 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 1855 power-domain-names = "cx", "gx";
3014 1856
3015 iommus = <&adreno_smm 1857 iommus = <&adreno_smmu 5 0x400>;
3016 1858
3017 operating-points-v2 = 1859 operating-points-v2 = <&gmu_opp_table>;
3018 1860
3019 status = "disabled"; <<
3020 <<
3021 gmu_opp_table: opp-ta 1861 gmu_opp_table: opp-table {
3022 compatible = 1862 compatible = "operating-points-v2";
3023 1863
3024 opp-200000000 1864 opp-200000000 {
3025 opp-h 1865 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 1866 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 1867 };
3028 }; 1868 };
3029 }; 1869 };
3030 1870
3031 gpucc: clock-controller@3d900 1871 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 1872 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 1873 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 1874 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 1875 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 1876 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 1877 clock-names = "bi_tcxo",
3038 "gcc_gp 1878 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 1879 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 1880 #clock-cells = <1>;
3041 #reset-cells = <1>; 1881 #reset-cells = <1>;
3042 #power-domain-cells = 1882 #power-domain-cells = <1>;
3043 }; 1883 };
3044 1884
3045 adreno_smmu: iommu@3da0000 { 1885 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 1886 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 1887 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 1888 #iommu-cells = <2>;
3050 #global-interrupts = 1889 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 1890 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 1891 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 1892 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 1893 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 1894 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 1895 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 1896 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 1897 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 1898 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 1899 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 1900 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 1901 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 1902 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 1903 clock-names = "ahb", "bus", "iface";
3065 1904
3066 power-domains = <&gpu 1905 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 1906 };
3069 1907
3070 slpi: remoteproc@5c00000 { 1908 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 1909 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 1910 reg = <0 0x05c00000 0 0x4000>;
3073 1911
3074 interrupts-extended = !! 1912 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 1913 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 1914 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 1915 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 1916 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 1917 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 1918 "handover", "stop-ack";
3081 1919
3082 clocks = <&rpmhcc RPM 1920 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 1921 clock-names = "xo";
3084 1922
3085 power-domains = <&rpm !! 1923 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
3086 <&rpm !! 1924 <&rpmhpd SM8250_LCX>,
3087 power-domain-names = !! 1925 <&rpmhpd SM8250_LMX>;
>> 1926 power-domain-names = "load_state", "lcx", "lmx";
3088 1927
3089 memory-region = <&slp 1928 memory-region = <&slpi_mem>;
3090 1929
3091 qcom,qmp = <&aoss_qmp <<
3092 <<
3093 qcom,smem-states = <& 1930 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 1931 qcom,smem-state-names = "stop";
3095 1932
3096 status = "disabled"; 1933 status = "disabled";
3097 1934
3098 glink-edge { 1935 glink-edge {
3099 interrupts-ex 1936 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 1937 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 1938 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 1939 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 1940 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 1941
3105 label = "slpi 1942 label = "slpi";
3106 qcom,remote-p 1943 qcom,remote-pid = <3>;
3107 1944
3108 fastrpc { 1945 fastrpc {
3109 compa 1946 compatible = "qcom,fastrpc";
3110 qcom, 1947 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 1948 label = "sdsp";
3112 qcom, <<
3113 #addr 1949 #address-cells = <1>;
3114 #size 1950 #size-cells = <0>;
3115 1951
3116 compu 1952 compute-cb@1 {
3117 1953 compatible = "qcom,fastrpc-compute-cb";
3118 1954 reg = <1>;
3119 1955 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 1956 };
3121 1957
3122 compu 1958 compute-cb@2 {
3123 1959 compatible = "qcom,fastrpc-compute-cb";
3124 1960 reg = <2>;
3125 1961 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 1962 };
3127 1963
3128 compu 1964 compute-cb@3 {
3129 1965 compatible = "qcom,fastrpc-compute-cb";
3130 1966 reg = <3>;
3131 1967 iommus = <&apps_smmu 0x0543 0x0>;
3132 1968 /* note: shared-cb = <4> in downstream */
3133 }; 1969 };
3134 }; 1970 };
3135 }; 1971 };
3136 }; 1972 };
3137 1973
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 1974 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 1975 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 1976 reg = <0 0x08300000 0 0x10000>;
3777 1977
3778 interrupts-extended = !! 1978 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 1979 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 1980 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 1981 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 1982 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 1983 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 1984 "handover", "stop-ack";
3785 1985
3786 clocks = <&rpmhcc RPM 1986 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 1987 clock-names = "xo";
3788 1988
3789 power-domains = <&rpm !! 1989 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 1990 <&rpmhpd SM8250_CX>;
>> 1991 power-domain-names = "load_state", "cx";
3790 1992
3791 memory-region = <&cds 1993 memory-region = <&cdsp_mem>;
3792 1994
3793 qcom,qmp = <&aoss_qmp <<
3794 <<
3795 qcom,smem-states = <& 1995 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 1996 qcom,smem-state-names = "stop";
3797 1997
3798 status = "disabled"; 1998 status = "disabled";
3799 1999
3800 glink-edge { 2000 glink-edge {
3801 interrupts-ex 2001 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2002 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2003 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2004 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2005 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2006
3807 label = "cdsp 2007 label = "cdsp";
3808 qcom,remote-p 2008 qcom,remote-pid = <5>;
3809 2009
3810 fastrpc { 2010 fastrpc {
3811 compa 2011 compatible = "qcom,fastrpc";
3812 qcom, 2012 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2013 label = "cdsp";
3814 qcom, <<
3815 #addr 2014 #address-cells = <1>;
3816 #size 2015 #size-cells = <0>;
3817 2016
3818 compu 2017 compute-cb@1 {
3819 2018 compatible = "qcom,fastrpc-compute-cb";
3820 2019 reg = <1>;
3821 2020 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2021 };
3823 2022
3824 compu 2023 compute-cb@2 {
3825 2024 compatible = "qcom,fastrpc-compute-cb";
3826 2025 reg = <2>;
3827 2026 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2027 };
3829 2028
3830 compu 2029 compute-cb@3 {
3831 2030 compatible = "qcom,fastrpc-compute-cb";
3832 2031 reg = <3>;
3833 2032 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2033 };
3835 2034
3836 compu 2035 compute-cb@4 {
3837 2036 compatible = "qcom,fastrpc-compute-cb";
3838 2037 reg = <4>;
3839 2038 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2039 };
3841 2040
3842 compu 2041 compute-cb@5 {
3843 2042 compatible = "qcom,fastrpc-compute-cb";
3844 2043 reg = <5>;
3845 2044 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2045 };
3847 2046
3848 compu 2047 compute-cb@6 {
3849 2048 compatible = "qcom,fastrpc-compute-cb";
3850 2049 reg = <6>;
3851 2050 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2051 };
3853 2052
3854 compu 2053 compute-cb@7 {
3855 2054 compatible = "qcom,fastrpc-compute-cb";
3856 2055 reg = <7>;
3857 2056 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2057 };
3859 2058
3860 compu 2059 compute-cb@8 {
3861 2060 compatible = "qcom,fastrpc-compute-cb";
3862 2061 reg = <8>;
3863 2062 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2063 };
3865 2064
3866 /* no 2065 /* note: secure cb9 in downstream */
3867 }; 2066 };
3868 }; 2067 };
3869 }; 2068 };
3870 2069
>> 2070 sound: sound {
>> 2071 };
>> 2072
3871 usb_1_hsphy: phy@88e3000 { 2073 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2074 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2075 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2076 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2077 status = "disabled";
3876 #phy-cells = <0>; 2078 #phy-cells = <0>;
3877 2079
3878 clocks = <&rpmhcc RPM 2080 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2081 clock-names = "ref";
3880 2082
3881 resets = <&gcc GCC_QU 2083 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2084 };
3883 2085
3884 usb_2_hsphy: phy@88e4000 { 2086 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2087 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2088 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2089 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2090 status = "disabled";
3889 #phy-cells = <0>; 2091 #phy-cells = <0>;
3890 2092
3891 clocks = <&rpmhcc RPM 2093 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2094 clock-names = "ref";
3893 2095
3894 resets = <&gcc GCC_QU 2096 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2097 };
3896 2098
3897 usb_1_qmpphy: phy@88e8000 { !! 2099 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm !! 2100 compatible = "qcom,sm8250-qmp-usb3-phy";
3899 reg = <0 0x088e8000 0 !! 2101 reg = <0 0x088e9000 0 0x200>,
>> 2102 <0 0x088e8000 0 0x20>;
>> 2103 reg-names = "reg-base", "dp_com";
3900 status = "disabled"; 2104 status = "disabled";
>> 2105 #clock-cells = <1>;
>> 2106 #address-cells = <2>;
>> 2107 #size-cells = <2>;
>> 2108 ranges;
3901 2109
3902 clocks = <&gcc GCC_US 2110 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2111 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2112 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2113 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2114
3911 resets = <&gcc GCC_US 2115 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2116 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2117 reset-names = "phy", "common";
3914 2118
3915 #clock-cells = <1>; !! 2119 usb_1_ssphy: lanes@88e9200 {
3916 #phy-cells = <1>; !! 2120 reg = <0 0x088e9200 0 0x200>,
3917 !! 2121 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2122 <0 0x088e9c00 0 0x400>,
3919 !! 2123 <0 0x088e9600 0 0x200>,
3920 ports { !! 2124 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2125 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2126 #phy-cells = <0>;
3923 !! 2127 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3924 port@0 { !! 2128 clock-names = "pipe0";
3925 reg = !! 2129 clock-output-names = "usb3_phy_pipe_clk_src";
3926 usb_1 <<
3927 }; <<
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 <<
3940 usb_1 <<
3941 }; <<
3942 }; 2130 };
3943 }; 2131 };
3944 2132
3945 usb_2_qmpphy: phy@88eb000 { 2133 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2134 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2135 reg = <0 0x088eb000 0 0x200>;
>> 2136 status = "disabled";
>> 2137 #clock-cells = <1>;
>> 2138 #address-cells = <2>;
>> 2139 #size-cells = <2>;
>> 2140 ranges;
3948 2141
3949 clocks = <&gcc GCC_US 2142 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2143 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2144 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2145 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2146 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2147
3961 resets = <&gcc GCC_US !! 2148 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2149 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2150 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2151
3966 status = "disabled"; !! 2152 usb_2_ssphy: lane@88eb200 {
>> 2153 reg = <0 0x088eb200 0 0x200>,
>> 2154 <0 0x088eb400 0 0x200>,
>> 2155 <0 0x088eb800 0 0x800>;
>> 2156 #phy-cells = <0>;
>> 2157 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2158 clock-names = "pipe0";
>> 2159 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2160 };
3967 }; 2161 };
3968 2162
3969 sdhc_2: mmc@8804000 { !! 2163 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2164 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2165 reg = <0 0x08804000 0 0x1000>;
3972 2166
3973 interrupts = <GIC_SPI 2167 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2168 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2169 interrupt-names = "hc_irq", "pwr_irq";
3976 2170
3977 clocks = <&gcc GCC_SD 2171 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2172 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2173 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2174 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2175 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2176 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2177 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2178 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2179 operating-points-v2 = <&sdhc2_opp_table>;
3986 2180
3987 status = "disabled"; 2181 status = "disabled";
3988 2182
3989 sdhc2_opp_table: opp- !! 2183 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2184 compatible = "operating-points-v2";
3991 2185
3992 opp-19200000 2186 opp-19200000 {
3993 opp-h 2187 opp-hz = /bits/ 64 <19200000>;
3994 requi 2188 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2189 };
3996 2190
3997 opp-50000000 2191 opp-50000000 {
3998 opp-h 2192 opp-hz = /bits/ 64 <50000000>;
3999 requi 2193 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2194 };
4001 2195
4002 opp-100000000 2196 opp-100000000 {
4003 opp-h 2197 opp-hz = /bits/ 64 <100000000>;
4004 requi 2198 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2199 };
4006 2200
4007 opp-202000000 2201 opp-202000000 {
4008 opp-h 2202 opp-hz = /bits/ 64 <202000000>;
4009 requi 2203 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2204 };
4011 }; 2205 };
4012 }; 2206 };
4013 2207
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2208 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2209 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2210 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2211 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2212 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2213 };
4142 2214
4143 gem_noc: interconnect@9100000 2215 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2216 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2217 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2218 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2219 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2220 };
4149 2221
4150 npu_noc: interconnect@9990000 2222 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2223 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2224 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2225 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2226 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2227 };
4156 2228
4157 usb_1: usb@a6f8800 { 2229 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2230 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2231 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2232 status = "disabled";
4161 #address-cells = <2>; 2233 #address-cells = <2>;
4162 #size-cells = <2>; 2234 #size-cells = <2>;
4163 ranges; 2235 ranges;
4164 dma-ranges; 2236 dma-ranges;
4165 2237
4166 clocks = <&gcc GCC_CF 2238 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 2239 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 2240 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 2241 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2242 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 2243 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 2244 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 2245 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 2246
4179 assigned-clocks = <&g 2247 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 2248 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 2249 assigned-clock-rates = <19200000>, <200000000>;
4182 2250
4183 interrupts-extended = !! 2251 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 2252 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 2253 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 2254 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 2255 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 2256 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 2257
4194 power-domains = <&gcc 2258 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 2259
4197 resets = <&gcc GCC_US 2260 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 2261
4199 interconnects = <&agg !! 2262 usb_1_dwc3: dwc3@a600000 {
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 <<
4204 compatible = 2263 compatible = "snps,dwc3";
4205 reg = <0 0x0a 2264 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 2265 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 2266 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 2267 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 2268 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 2269 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 2270 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 2271 };
4233 }; 2272 };
4234 2273
4235 system-cache-controller@92000 2274 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 2275 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 2276 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 2277 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 2278 };
4243 2279
4244 usb_2: usb@a8f8800 { 2280 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 2281 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 2282 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 2283 status = "disabled";
4248 #address-cells = <2>; 2284 #address-cells = <2>;
4249 #size-cells = <2>; 2285 #size-cells = <2>;
4250 ranges; 2286 ranges;
4251 dma-ranges; 2287 dma-ranges;
4252 2288
4253 clocks = <&gcc GCC_CF 2289 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 2290 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 2291 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 2292 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2293 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 2294 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 2295 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 2296 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 2297
4266 assigned-clocks = <&g 2298 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 2299 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 2300 assigned-clock-rates = <19200000>, <200000000>;
4269 2301
4270 interrupts-extended = !! 2302 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 2303 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 2304 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 2305 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 2306 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 2307 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 2308
4281 power-domains = <&gcc 2309 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 2310
4284 resets = <&gcc GCC_US 2311 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 2312
4286 interconnects = <&agg !! 2313 usb_2_dwc3: dwc3@a800000 {
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 <<
4291 compatible = 2314 compatible = "snps,dwc3";
4292 reg = <0 0x0a 2315 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 2316 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 2317 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 2318 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 2319 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 2320 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 2321 phy-names = "usb2-phy", "usb3-phy";
4299 }; 2322 };
4300 }; 2323 };
4301 2324
4302 venus: video-codec@aa00000 { !! 2325 mdss: mdss@ae00000 {
4303 compatible = "qcom,sm !! 2326 compatible = "qcom,sdm845-mdss";
4304 reg = <0 0x0aa00000 0 <<
4305 interrupts = <GIC_SPI <<
4306 power-domains = <&vid <<
4307 <&vid <<
4308 <&rpm <<
4309 power-domain-names = <<
4310 operating-points-v2 = <<
4311 <<
4312 clocks = <&gcc GCC_VI <<
4313 <&videocc VI <<
4314 <&videocc VI <<
4315 clock-names = "iface" <<
4316 <<
4317 interconnects = <&gem <<
4318 <&mms <<
4319 interconnect-names = <<
4320 <<
4321 iommus = <&apps_smmu <<
4322 memory-region = <&vid <<
4323 <<
4324 resets = <&gcc GCC_VI <<
4325 <&videocc VI <<
4326 reset-names = "bus", <<
4327 <<
4328 status = "disabled"; <<
4329 <<
4330 video-decoder { <<
4331 compatible = <<
4332 }; <<
4333 <<
4334 video-encoder { <<
4335 compatible = <<
4336 }; <<
4337 <<
4338 venus_opp_table: opp- <<
4339 compatible = <<
4340 <<
4341 opp-720000000 <<
4342 opp-h <<
4343 requi <<
4344 }; <<
4345 <<
4346 opp-101400000 <<
4347 opp-h <<
4348 requi <<
4349 }; <<
4350 <<
4351 opp-109800000 <<
4352 opp-h <<
4353 requi <<
4354 }; <<
4355 <<
4356 opp-133200000 <<
4357 opp-h <<
4358 requi <<
4359 }; <<
4360 }; <<
4361 }; <<
4362 <<
4363 videocc: clock-controller@abf <<
4364 compatible = "qcom,sm <<
4365 reg = <0 0x0abf0000 0 <<
4366 clocks = <&gcc GCC_VI <<
4367 <&rpmhcc RPM <<
4368 <&rpmhcc RPM <<
4369 power-domains = <&rpm <<
4370 required-opps = <&rpm <<
4371 clock-names = "iface" <<
4372 #clock-cells = <1>; <<
4373 #reset-cells = <1>; <<
4374 #power-domain-cells = <<
4375 }; <<
4376 <<
4377 cci0: cci@ac4f000 { <<
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm <<
4659 reg = <0 0x0ae00000 0 2327 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 2328 reg-names = "mdss";
4661 2329
4662 interconnects = <&mms !! 2330 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 2331 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 2332 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 2333
4666 power-domains = <&dis 2334 power-domains = <&dispcc MDSS_GDSC>;
4667 2335
4668 clocks = <&dispcc DIS 2336 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 2337 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 2338 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 2339 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 2340 clock-names = "iface", "bus", "nrt_bus", "core";
4673 2341
>> 2342 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2343 assigned-clock-rates = <460000000>;
>> 2344
4674 interrupts = <GIC_SPI 2345 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 2346 interrupt-controller;
4676 #interrupt-cells = <1 2347 #interrupt-cells = <1>;
4677 2348
4678 iommus = <&apps_smmu 2349 iommus = <&apps_smmu 0x820 0x402>;
4679 2350
4680 status = "disabled"; 2351 status = "disabled";
4681 2352
4682 #address-cells = <2>; 2353 #address-cells = <2>;
4683 #size-cells = <2>; 2354 #size-cells = <2>;
4684 ranges; 2355 ranges;
4685 2356
4686 mdss_mdp: display-con !! 2357 mdss_mdp: mdp@ae01000 {
4687 compatible = !! 2358 compatible = "qcom,sdm845-dpu";
4688 reg = <0 0x0a 2359 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 2360 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 2361 reg-names = "mdp", "vbif";
4691 2362
4692 clocks = <&di 2363 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 2364 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 2365 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 2366 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 2367 clock-names = "iface", "bus", "core", "vsync";
4697 2368
4698 assigned-cloc !! 2369 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 2370 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 2371 assigned-clock-rates = <460000000>,
>> 2372 <19200000>;
4700 2373
4701 operating-poi 2374 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 2375 power-domains = <&rpmhpd SM8250_MMCX>;
4703 2376
4704 interrupt-par 2377 interrupt-parent = <&mdss>;
4705 interrupts = !! 2378 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> 2379
>> 2380 status = "disabled";
4706 2381
4707 ports { 2382 ports {
4708 #addr 2383 #address-cells = <1>;
4709 #size 2384 #size-cells = <0>;
4710 2385
4711 port@ 2386 port@0 {
4712 2387 reg = <0>;
4713 2388 dpu_intf1_out: endpoint {
4714 !! 2389 remote-endpoint = <&dsi0_in>;
4715 2390 };
4716 }; 2391 };
4717 2392
4718 port@ 2393 port@1 {
4719 2394 reg = <1>;
4720 2395 dpu_intf2_out: endpoint {
4721 !! 2396 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 2397 };
4731 }; 2398 };
4732 }; 2399 };
4733 2400
4734 mdp_opp_table !! 2401 mdp_opp_table: mdp-opp-table {
4735 compa 2402 compatible = "operating-points-v2";
4736 2403
4737 opp-2 2404 opp-200000000 {
4738 2405 opp-hz = /bits/ 64 <200000000>;
4739 2406 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 2407 };
4741 2408
4742 opp-3 2409 opp-300000000 {
4743 2410 opp-hz = /bits/ 64 <300000000>;
4744 2411 required-opps = <&rpmhpd_opp_svs>;
4745 }; 2412 };
4746 2413
4747 opp-3 2414 opp-345000000 {
4748 2415 opp-hz = /bits/ 64 <345000000>;
4749 2416 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 2417 };
4751 2418
4752 opp-4 2419 opp-460000000 {
4753 2420 opp-hz = /bits/ 64 <460000000>;
4754 2421 required-opps = <&rpmhpd_opp_nom>;
4755 }; 2422 };
4756 }; 2423 };
4757 }; 2424 };
4758 2425
4759 mdss_dp: displayport- !! 2426 dsi0: dsi@ae94000 {
4760 compatible = !! 2427 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 2428 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 2429 reg-names = "dsi_ctrl";
4843 2430
4844 interrupt-par 2431 interrupt-parent = <&mdss>;
4845 interrupts = !! 2432 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 2433
4847 clocks = <&di 2434 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 2435 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 2436 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 2437 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 2438 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 2439 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 2440 clock-names = "byte",
4854 2441 "byte_intf",
4855 2442 "pixel",
4856 2443 "core",
4857 2444 "iface",
4858 2445 "bus";
4859 2446
4860 assigned-cloc <<
4861 assigned-cloc <<
4862 <<
4863 operating-poi 2447 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 2448 power-domains = <&rpmhpd SM8250_MMCX>;
4865 2449
4866 phys = <&mdss !! 2450 phys = <&dsi0_phy>;
>> 2451 phy-names = "dsi";
4867 2452
4868 status = "dis 2453 status = "disabled";
4869 2454
4870 #address-cell <<
4871 #size-cells = <<
4872 <<
4873 ports { 2455 ports {
4874 #addr 2456 #address-cells = <1>;
4875 #size 2457 #size-cells = <0>;
4876 2458
4877 port@ 2459 port@0 {
4878 2460 reg = <0>;
4879 !! 2461 dsi0_in: endpoint {
4880 2462 remote-endpoint = <&dpu_intf1_out>;
4881 2463 };
4882 }; 2464 };
4883 2465
4884 port@ 2466 port@1 {
4885 2467 reg = <1>;
4886 !! 2468 dsi0_out: endpoint {
4887 2469 };
4888 }; 2470 };
4889 }; 2471 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 2472 };
4910 2473
4911 mdss_dsi0_phy: phy@ae !! 2474 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 2475 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 2476 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 2477 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 2478 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 2479 reg-names = "dsi_phy",
4917 " 2480 "dsi_phy_lane",
4918 " 2481 "dsi_pll";
4919 2482
4920 #clock-cells 2483 #clock-cells = <1>;
4921 #phy-cells = 2484 #phy-cells = <0>;
4922 2485
4923 clocks = <&di 2486 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 2487 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 2488 clock-names = "iface", "ref";
4926 2489
4927 status = "dis 2490 status = "disabled";
4928 }; 2491 };
4929 2492
4930 mdss_dsi1: dsi@ae9600 !! 2493 dsi1: dsi@ae96000 {
4931 compatible = !! 2494 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 2495 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 2496 reg-names = "dsi_ctrl";
4935 2497
4936 interrupt-par 2498 interrupt-parent = <&mdss>;
4937 interrupts = !! 2499 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 2500
4939 clocks = <&di 2501 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 2502 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 2503 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 2504 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 2505 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 2506 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 2507 clock-names = "byte",
4946 2508 "byte_intf",
4947 2509 "pixel",
4948 2510 "core",
4949 2511 "iface",
4950 2512 "bus";
4951 2513
4952 assigned-cloc <<
4953 assigned-cloc <<
4954 <<
4955 operating-poi 2514 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 2515 power-domains = <&rpmhpd SM8250_MMCX>;
4957 2516
4958 phys = <&mdss !! 2517 phys = <&dsi1_phy>;
>> 2518 phy-names = "dsi";
4959 2519
4960 status = "dis 2520 status = "disabled";
4961 2521
4962 #address-cell <<
4963 #size-cells = <<
4964 <<
4965 ports { 2522 ports {
4966 #addr 2523 #address-cells = <1>;
4967 #size 2524 #size-cells = <0>;
4968 2525
4969 port@ 2526 port@0 {
4970 2527 reg = <0>;
4971 !! 2528 dsi1_in: endpoint {
4972 2529 remote-endpoint = <&dpu_intf2_out>;
4973 2530 };
4974 }; 2531 };
4975 2532
4976 port@ 2533 port@1 {
4977 2534 reg = <1>;
4978 !! 2535 dsi1_out: endpoint {
4979 2536 };
4980 }; 2537 };
4981 }; 2538 };
4982 }; 2539 };
4983 2540
4984 mdss_dsi1_phy: phy@ae !! 2541 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 2542 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 2543 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 2544 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 2545 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 2546 reg-names = "dsi_phy",
4990 " 2547 "dsi_phy_lane",
4991 " 2548 "dsi_pll";
4992 2549
4993 #clock-cells 2550 #clock-cells = <1>;
4994 #phy-cells = 2551 #phy-cells = <0>;
4995 2552
4996 clocks = <&di 2553 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 2554 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 2555 clock-names = "iface", "ref";
4999 2556
5000 status = "dis 2557 status = "disabled";
>> 2558
>> 2559 dsi_opp_table: dsi-opp-table {
>> 2560 compatible = "operating-points-v2";
>> 2561
>> 2562 opp-187500000 {
>> 2563 opp-hz = /bits/ 64 <187500000>;
>> 2564 required-opps = <&rpmhpd_opp_low_svs>;
>> 2565 };
>> 2566
>> 2567 opp-300000000 {
>> 2568 opp-hz = /bits/ 64 <300000000>;
>> 2569 required-opps = <&rpmhpd_opp_svs>;
>> 2570 };
>> 2571
>> 2572 opp-358000000 {
>> 2573 opp-hz = /bits/ 64 <358000000>;
>> 2574 required-opps = <&rpmhpd_opp_svs_l1>;
>> 2575 };
>> 2576 };
5001 }; 2577 };
5002 }; 2578 };
5003 2579
5004 dispcc: clock-controller@af00 2580 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 2581 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 2582 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 2583 mmcx-supply = <&mmcx_reg>;
5008 required-opps = <&rpm <<
5009 clocks = <&rpmhcc RPM 2584 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 2585 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 2586 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 2587 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 2588 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 2589 <0>,
5015 <&usb_1_qmpp !! 2590 <0>;
5016 clock-names = "bi_tcx 2591 clock-names = "bi_tcxo",
5017 "dsi0_p 2592 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 2593 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 2594 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 2595 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 2596 "dp_phy_pll_link_clk",
5022 "dp_phy 2597 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 2598 #clock-cells = <1>;
5024 #reset-cells = <1>; 2599 #reset-cells = <1>;
5025 #power-domain-cells = 2600 #power-domain-cells = <1>;
5026 }; 2601 };
5027 2602
5028 pdc: interrupt-controller@b22 2603 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 2604 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 2605 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 2606 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 2607 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 2608 #interrupt-cells = <2>;
5034 interrupt-parent = <& 2609 interrupt-parent = <&intc>;
5035 interrupt-controller; 2610 interrupt-controller;
5036 }; 2611 };
5037 2612
5038 tsens0: thermal-sensor@c26300 2613 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 2614 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 2615 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 2616 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 2617 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 2618 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 2619 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 2620 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 2621 #thermal-sensor-cells = <1>;
5047 }; 2622 };
5048 2623
5049 tsens1: thermal-sensor@c26500 2624 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 2625 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 2626 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 2627 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 2628 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 2629 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 2630 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 2631 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 2632 #thermal-sensor-cells = <1>;
5058 }; 2633 };
5059 2634
5060 aoss_qmp: power-management@c3 !! 2635 aoss_qmp: qmp@c300000 {
5061 compatible = "qcom,sm !! 2636 compatible = "qcom,sm8250-aoss-qmp";
5062 reg = <0 0x0c300000 0 !! 2637 reg = <0 0x0c300000 0 0x100000>;
5063 interrupts-extended = 2638 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 2639 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 2640 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 2641 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 2642 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 2643
5069 #clock-cells = <0>; 2644 #clock-cells = <0>;
5070 }; !! 2645 #power-domain-cells = <1>;
5071 <<
5072 sram@c3f0000 { <<
5073 compatible = "qcom,rp <<
5074 reg = <0 0x0c3f0000 0 <<
5075 }; 2646 };
5076 2647
5077 spmi_bus: spmi@c440000 { 2648 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 2649 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 2650 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 2651 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 2652 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 2653 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 2654 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 2655 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 2656 interrupt-names = "periph_irq";
5086 interrupts-extended = 2657 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 2658 qcom,ee = <0>;
5088 qcom,channel = <0>; 2659 qcom,channel = <0>;
5089 #address-cells = <2>; 2660 #address-cells = <2>;
5090 #size-cells = <0>; 2661 #size-cells = <0>;
5091 interrupt-controller; 2662 interrupt-controller;
5092 #interrupt-cells = <4 2663 #interrupt-cells = <4>;
5093 }; 2664 };
5094 2665
5095 tlmm: pinctrl@f100000 { 2666 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 2667 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 2668 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 2669 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 2670 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 2671 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 2672 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 2673 gpio-controller;
5103 #gpio-cells = <2>; 2674 #gpio-cells = <2>;
5104 interrupt-controller; 2675 interrupt-controller;
5105 #interrupt-cells = <2 2676 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 2677 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 2678 wakeup-parent = <&pdc>;
5108 2679
5109 cam2_default: cam2-de !! 2680 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 2681 sclk {
5111 pins <<
5112 funct <<
5113 drive <<
5114 bias- <<
5115 }; <<
5116 <<
5117 mclk-pins { <<
5118 pins <<
5119 funct <<
5120 drive <<
5121 bias- <<
5122 }; <<
5123 }; <<
5124 <<
5125 cam2_suspend: cam2-su <<
5126 rst-pins { <<
5127 pins <<
5128 funct <<
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; <<
5133 <<
5134 mclk-pins { <<
5135 pins <<
5136 funct <<
5137 drive <<
5138 bias- <<
5139 }; <<
5140 }; <<
5141 <<
5142 cci0_default: cci0-de <<
5143 cci0_i2c0_def <<
5144 /* SD <<
5145 pins <<
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; <<
5151 <<
5152 cci0_i2c1_def <<
5153 /* SD <<
5154 pins <<
5155 funct <<
5156 <<
5157 bias- <<
5158 drive <<
5159 }; <<
5160 }; <<
5161 <<
5162 cci0_sleep: cci0-slee <<
5163 cci0_i2c0_sle <<
5164 /* SD <<
5165 pins <<
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; <<
5171 <<
5172 cci0_i2c1_sle <<
5173 /* SD <<
5174 pins <<
5175 funct <<
5176 <<
5177 drive <<
5178 bias- <<
5179 }; <<
5180 }; <<
5181 <<
5182 cci1_default: cci1-de <<
5183 cci1_i2c0_def <<
5184 /* SD <<
5185 pins <<
5186 funct <<
5187 <<
5188 bias- <<
5189 drive <<
5190 }; <<
5191 <<
5192 cci1_i2c1_def <<
5193 /* SD <<
5194 pins <<
5195 funct <<
5196 <<
5197 bias- <<
5198 drive <<
5199 }; <<
5200 }; <<
5201 <<
5202 cci1_sleep: cci1-slee <<
5203 cci1_i2c0_sle <<
5204 /* SD <<
5205 pins <<
5206 funct <<
5207 <<
5208 bias- <<
5209 drive <<
5210 }; <<
5211 <<
5212 cci1_i2c1_sle <<
5213 /* SD <<
5214 pins <<
5215 funct <<
5216 <<
5217 bias- <<
5218 drive <<
5219 }; <<
5220 }; <<
5221 <<
5222 pri_mi2s_active: pri- <<
5223 sclk-pins { <<
5224 pins 2682 pins = "gpio138";
5225 funct 2683 function = "mi2s0_sck";
5226 drive 2684 drive-strength = <8>;
5227 bias- 2685 bias-disable;
5228 }; 2686 };
5229 2687
5230 ws-pins { !! 2688 ws {
5231 pins 2689 pins = "gpio141";
5232 funct 2690 function = "mi2s0_ws";
5233 drive 2691 drive-strength = <8>;
5234 outpu 2692 output-high;
5235 }; 2693 };
5236 2694
5237 data0-pins { !! 2695 data0 {
5238 pins 2696 pins = "gpio139";
5239 funct 2697 function = "mi2s0_data0";
5240 drive 2698 drive-strength = <8>;
5241 bias- 2699 bias-disable;
5242 outpu 2700 output-high;
5243 }; 2701 };
5244 2702
5245 data1-pins { !! 2703 data1 {
5246 pins 2704 pins = "gpio140";
5247 funct 2705 function = "mi2s0_data1";
5248 drive 2706 drive-strength = <8>;
5249 outpu 2707 output-high;
5250 }; 2708 };
5251 }; 2709 };
5252 2710
5253 qup_i2c0_default: qup !! 2711 qup_i2c0_default: qup-i2c0-default {
5254 pins = "gpio2 !! 2712 mux {
5255 function = "q !! 2713 pins = "gpio28", "gpio29";
5256 drive-strengt !! 2714 function = "qup0";
5257 bias-disable; !! 2715 };
5258 }; <<
5259 2716
5260 qup_i2c1_default: qup !! 2717 config {
5261 pins = "gpio4 !! 2718 pins = "gpio28", "gpio29";
5262 function = "q !! 2719 drive-strength = <2>;
5263 drive-strengt !! 2720 bias-disable;
5264 bias-disable; !! 2721 };
5265 }; 2722 };
5266 2723
5267 qup_i2c2_default: qup !! 2724 qup_i2c1_default: qup-i2c1-default {
5268 pins = "gpio1 !! 2725 pinmux {
5269 function = "q !! 2726 pins = "gpio4", "gpio5";
5270 drive-strengt !! 2727 function = "qup1";
5271 bias-disable; !! 2728 };
5272 }; <<
5273 2729
5274 qup_i2c3_default: qup !! 2730 config {
5275 pins = "gpio1 !! 2731 pins = "gpio4", "gpio5";
5276 function = "q !! 2732 drive-strength = <2>;
5277 drive-strengt !! 2733 bias-disable;
5278 bias-disable; !! 2734 };
5279 }; 2735 };
5280 2736
5281 qup_i2c4_default: qup !! 2737 qup_i2c2_default: qup-i2c2-default {
5282 pins = "gpio8 !! 2738 mux {
5283 function = "q !! 2739 pins = "gpio115", "gpio116";
5284 drive-strengt !! 2740 function = "qup2";
5285 bias-disable; !! 2741 };
5286 }; <<
5287 2742
5288 qup_i2c5_default: qup !! 2743 config {
5289 pins = "gpio1 !! 2744 pins = "gpio115", "gpio116";
5290 function = "q !! 2745 drive-strength = <2>;
5291 drive-strengt !! 2746 bias-disable;
5292 bias-disable; !! 2747 };
5293 }; 2748 };
5294 2749
5295 qup_i2c6_default: qup !! 2750 qup_i2c3_default: qup-i2c3-default {
5296 pins = "gpio1 !! 2751 mux {
5297 function = "q !! 2752 pins = "gpio119", "gpio120";
5298 drive-strengt !! 2753 function = "qup3";
5299 bias-disable; !! 2754 };
5300 }; <<
5301 2755
5302 qup_i2c7_default: qup !! 2756 config {
5303 pins = "gpio2 !! 2757 pins = "gpio119", "gpio120";
5304 function = "q !! 2758 drive-strength = <2>;
5305 drive-strengt !! 2759 bias-disable;
5306 bias-disable; !! 2760 };
5307 }; 2761 };
5308 2762
5309 qup_i2c8_default: qup !! 2763 qup_i2c4_default: qup-i2c4-default {
5310 pins = "gpio2 !! 2764 mux {
5311 function = "q !! 2765 pins = "gpio8", "gpio9";
5312 drive-strengt !! 2766 function = "qup4";
5313 bias-disable; !! 2767 };
5314 }; <<
5315 2768
5316 qup_i2c9_default: qup !! 2769 config {
5317 pins = "gpio1 !! 2770 pins = "gpio8", "gpio9";
5318 function = "q !! 2771 drive-strength = <2>;
5319 drive-strengt !! 2772 bias-disable;
5320 bias-disable; !! 2773 };
5321 }; 2774 };
5322 2775
5323 qup_i2c10_default: qu !! 2776 qup_i2c5_default: qup-i2c5-default {
5324 pins = "gpio1 !! 2777 mux {
5325 function = "q !! 2778 pins = "gpio12", "gpio13";
5326 drive-strengt !! 2779 function = "qup5";
5327 bias-disable; !! 2780 };
5328 }; <<
5329 2781
5330 qup_i2c11_default: qu !! 2782 config {
5331 pins = "gpio6 !! 2783 pins = "gpio12", "gpio13";
5332 function = "q !! 2784 drive-strength = <2>;
5333 drive-strengt !! 2785 bias-disable;
5334 bias-disable; !! 2786 };
5335 }; 2787 };
5336 2788
5337 qup_i2c12_default: qu !! 2789 qup_i2c6_default: qup-i2c6-default {
5338 pins = "gpio3 !! 2790 mux {
5339 function = "q !! 2791 pins = "gpio16", "gpio17";
5340 drive-strengt !! 2792 function = "qup6";
5341 bias-disable; !! 2793 };
5342 }; <<
5343 2794
5344 qup_i2c13_default: qu !! 2795 config {
5345 pins = "gpio3 !! 2796 pins = "gpio16", "gpio17";
5346 function = "q !! 2797 drive-strength = <2>;
5347 drive-strengt !! 2798 bias-disable;
5348 bias-disable; !! 2799 };
5349 }; 2800 };
5350 2801
5351 qup_i2c14_default: qu !! 2802 qup_i2c7_default: qup-i2c7-default {
5352 pins = "gpio4 !! 2803 mux {
5353 function = "q !! 2804 pins = "gpio20", "gpio21";
5354 drive-strengt !! 2805 function = "qup7";
5355 bias-disable; !! 2806 };
5356 }; <<
5357 2807
5358 qup_i2c15_default: qu !! 2808 config {
5359 pins = "gpio4 !! 2809 pins = "gpio20", "gpio21";
5360 function = "q !! 2810 drive-strength = <2>;
5361 drive-strengt !! 2811 bias-disable;
5362 bias-disable; !! 2812 };
5363 }; 2813 };
5364 2814
5365 qup_i2c16_default: qu !! 2815 qup_i2c8_default: qup-i2c8-default {
5366 pins = "gpio4 !! 2816 mux {
5367 function = "q !! 2817 pins = "gpio24", "gpio25";
5368 drive-strengt !! 2818 function = "qup8";
5369 bias-disable; !! 2819 };
5370 }; <<
5371 2820
5372 qup_i2c17_default: qu !! 2821 config {
5373 pins = "gpio5 !! 2822 pins = "gpio24", "gpio25";
5374 function = "q !! 2823 drive-strength = <2>;
5375 drive-strengt !! 2824 bias-disable;
5376 bias-disable; !! 2825 };
5377 }; 2826 };
5378 2827
5379 qup_i2c18_default: qu !! 2828 qup_i2c9_default: qup-i2c9-default {
5380 pins = "gpio5 !! 2829 mux {
5381 function = "q !! 2830 pins = "gpio125", "gpio126";
5382 drive-strengt !! 2831 function = "qup9";
5383 bias-disable; !! 2832 };
5384 }; <<
5385 2833
5386 qup_i2c19_default: qu !! 2834 config {
5387 pins = "gpio0 !! 2835 pins = "gpio125", "gpio126";
5388 function = "q !! 2836 drive-strength = <2>;
5389 drive-strengt !! 2837 bias-disable;
5390 bias-disable; !! 2838 };
5391 }; 2839 };
5392 2840
5393 qup_spi0_cs: qup-spi0 !! 2841 qup_i2c10_default: qup-i2c10-default {
5394 pins = "gpio3 !! 2842 mux {
5395 function = "q !! 2843 pins = "gpio129", "gpio130";
5396 }; !! 2844 function = "qup10";
>> 2845 };
5397 2846
5398 qup_spi0_cs_gpio: qup !! 2847 config {
5399 pins = "gpio3 !! 2848 pins = "gpio129", "gpio130";
5400 function = "g !! 2849 drive-strength = <2>;
>> 2850 bias-disable;
>> 2851 };
5401 }; 2852 };
5402 2853
5403 qup_spi0_data_clk: qu !! 2854 qup_i2c11_default: qup-i2c11-default {
5404 pins = "gpio2 !! 2855 mux {
5405 "gpio3 !! 2856 pins = "gpio60", "gpio61";
5406 function = "q !! 2857 function = "qup11";
5407 }; !! 2858 };
5408 2859
5409 qup_spi1_cs: qup-spi1 !! 2860 config {
5410 pins = "gpio7 !! 2861 pins = "gpio60", "gpio61";
5411 function = "q !! 2862 drive-strength = <2>;
>> 2863 bias-disable;
>> 2864 };
5412 }; 2865 };
5413 2866
5414 qup_spi1_cs_gpio: qup !! 2867 qup_i2c12_default: qup-i2c12-default {
5415 pins = "gpio7 !! 2868 mux {
5416 function = "g !! 2869 pins = "gpio32", "gpio33";
5417 }; !! 2870 function = "qup12";
>> 2871 };
5418 2872
5419 qup_spi1_data_clk: qu !! 2873 config {
5420 pins = "gpio4 !! 2874 pins = "gpio32", "gpio33";
5421 "gpio6 !! 2875 drive-strength = <2>;
5422 function = "q !! 2876 bias-disable;
>> 2877 };
5423 }; 2878 };
5424 2879
5425 qup_spi2_cs: qup-spi2 !! 2880 qup_i2c13_default: qup-i2c13-default {
5426 pins = "gpio1 !! 2881 mux {
5427 function = "q !! 2882 pins = "gpio36", "gpio37";
5428 }; !! 2883 function = "qup13";
>> 2884 };
5429 2885
5430 qup_spi2_cs_gpio: qup !! 2886 config {
5431 pins = "gpio1 !! 2887 pins = "gpio36", "gpio37";
5432 function = "g !! 2888 drive-strength = <2>;
>> 2889 bias-disable;
>> 2890 };
5433 }; 2891 };
5434 2892
5435 qup_spi2_data_clk: qu !! 2893 qup_i2c14_default: qup-i2c14-default {
5436 pins = "gpio1 !! 2894 mux {
5437 "gpio1 !! 2895 pins = "gpio40", "gpio41";
5438 function = "q !! 2896 function = "qup14";
5439 }; !! 2897 };
5440 2898
5441 qup_spi3_cs: qup-spi3 !! 2899 config {
5442 pins = "gpio1 !! 2900 pins = "gpio40", "gpio41";
5443 function = "q !! 2901 drive-strength = <2>;
>> 2902 bias-disable;
>> 2903 };
5444 }; 2904 };
5445 2905
5446 qup_spi3_cs_gpio: qup !! 2906 qup_i2c15_default: qup-i2c15-default {
5447 pins = "gpio1 !! 2907 mux {
5448 function = "g !! 2908 pins = "gpio44", "gpio45";
5449 }; !! 2909 function = "qup15";
>> 2910 };
5450 2911
5451 qup_spi3_data_clk: qu !! 2912 config {
5452 pins = "gpio1 !! 2913 pins = "gpio44", "gpio45";
5453 "gpio1 !! 2914 drive-strength = <2>;
5454 function = "q !! 2915 bias-disable;
>> 2916 };
5455 }; 2917 };
5456 2918
5457 qup_spi4_cs: qup-spi4 !! 2919 qup_i2c16_default: qup-i2c16-default {
5458 pins = "gpio1 !! 2920 mux {
5459 function = "q !! 2921 pins = "gpio48", "gpio49";
5460 }; !! 2922 function = "qup16";
>> 2923 };
5461 2924
5462 qup_spi4_cs_gpio: qup !! 2925 config {
5463 pins = "gpio1 !! 2926 pins = "gpio48", "gpio49";
5464 function = "g !! 2927 drive-strength = <2>;
>> 2928 bias-disable;
>> 2929 };
5465 }; 2930 };
5466 2931
5467 qup_spi4_data_clk: qu !! 2932 qup_i2c17_default: qup-i2c17-default {
5468 pins = "gpio8 !! 2933 mux {
5469 "gpio1 !! 2934 pins = "gpio52", "gpio53";
5470 function = "q !! 2935 function = "qup17";
5471 }; !! 2936 };
5472 2937
5473 qup_spi5_cs: qup-spi5 !! 2938 config {
5474 pins = "gpio1 !! 2939 pins = "gpio52", "gpio53";
5475 function = "q !! 2940 drive-strength = <2>;
>> 2941 bias-disable;
>> 2942 };
5476 }; 2943 };
5477 2944
5478 qup_spi5_cs_gpio: qup !! 2945 qup_i2c18_default: qup-i2c18-default {
5479 pins = "gpio1 !! 2946 mux {
5480 function = "g !! 2947 pins = "gpio56", "gpio57";
5481 }; !! 2948 function = "qup18";
>> 2949 };
5482 2950
5483 qup_spi5_data_clk: qu !! 2951 config {
5484 pins = "gpio1 !! 2952 pins = "gpio56", "gpio57";
5485 "gpio1 !! 2953 drive-strength = <2>;
5486 function = "q !! 2954 bias-disable;
>> 2955 };
5487 }; 2956 };
5488 2957
5489 qup_spi6_cs: qup-spi6 !! 2958 qup_i2c19_default: qup-i2c19-default {
5490 pins = "gpio1 !! 2959 mux {
5491 function = "q !! 2960 pins = "gpio0", "gpio1";
5492 }; !! 2961 function = "qup19";
>> 2962 };
5493 2963
5494 qup_spi6_cs_gpio: qup !! 2964 config {
5495 pins = "gpio1 !! 2965 pins = "gpio0", "gpio1";
5496 function = "g !! 2966 drive-strength = <2>;
>> 2967 bias-disable;
>> 2968 };
5497 }; 2969 };
5498 2970
5499 qup_spi6_data_clk: qu !! 2971 qup_spi0_default: qup-spi0-default {
5500 pins = "gpio1 !! 2972 mux {
5501 "gpio1 !! 2973 pins = "gpio28", "gpio29",
5502 function = "q !! 2974 "gpio30", "gpio31";
5503 }; !! 2975 function = "qup0";
>> 2976 };
5504 2977
5505 qup_spi7_cs: qup-spi7 !! 2978 config {
5506 pins = "gpio2 !! 2979 pins = "gpio28", "gpio29",
5507 function = "q !! 2980 "gpio30", "gpio31";
>> 2981 drive-strength = <6>;
>> 2982 bias-disable;
>> 2983 };
5508 }; 2984 };
5509 2985
5510 qup_spi7_cs_gpio: qup !! 2986 qup_spi1_default: qup-spi1-default {
5511 pins = "gpio2 !! 2987 mux {
5512 function = "g !! 2988 pins = "gpio4", "gpio5",
5513 }; !! 2989 "gpio6", "gpio7";
>> 2990 function = "qup1";
>> 2991 };
5514 2992
5515 qup_spi7_data_clk: qu !! 2993 config {
5516 pins = "gpio2 !! 2994 pins = "gpio4", "gpio5",
5517 "gpio2 !! 2995 "gpio6", "gpio7";
5518 function = "q !! 2996 drive-strength = <6>;
>> 2997 bias-disable;
>> 2998 };
5519 }; 2999 };
5520 3000
5521 qup_spi8_cs: qup-spi8 !! 3001 qup_spi2_default: qup-spi2-default {
5522 pins = "gpio2 !! 3002 mux {
5523 function = "q !! 3003 pins = "gpio115", "gpio116",
5524 }; !! 3004 "gpio117", "gpio118";
>> 3005 function = "qup2";
>> 3006 };
5525 3007
5526 qup_spi8_cs_gpio: qup !! 3008 config {
5527 pins = "gpio2 !! 3009 pins = "gpio115", "gpio116",
5528 function = "g !! 3010 "gpio117", "gpio118";
>> 3011 drive-strength = <6>;
>> 3012 bias-disable;
>> 3013 };
5529 }; 3014 };
5530 3015
5531 qup_spi8_data_clk: qu !! 3016 qup_spi3_default: qup-spi3-default {
5532 pins = "gpio2 !! 3017 mux {
5533 "gpio2 !! 3018 pins = "gpio119", "gpio120",
5534 function = "q !! 3019 "gpio121", "gpio122";
5535 }; !! 3020 function = "qup3";
>> 3021 };
5536 3022
5537 qup_spi9_cs: qup-spi9 !! 3023 config {
5538 pins = "gpio1 !! 3024 pins = "gpio119", "gpio120",
5539 function = "q !! 3025 "gpio121", "gpio122";
>> 3026 drive-strength = <6>;
>> 3027 bias-disable;
>> 3028 };
5540 }; 3029 };
5541 3030
5542 qup_spi9_cs_gpio: qup !! 3031 qup_spi4_default: qup-spi4-default {
5543 pins = "gpio1 !! 3032 mux {
5544 function = "g !! 3033 pins = "gpio8", "gpio9",
5545 }; !! 3034 "gpio10", "gpio11";
>> 3035 function = "qup4";
>> 3036 };
5546 3037
5547 qup_spi9_data_clk: qu !! 3038 config {
5548 pins = "gpio1 !! 3039 pins = "gpio8", "gpio9",
5549 "gpio1 !! 3040 "gpio10", "gpio11";
5550 function = "q !! 3041 drive-strength = <6>;
>> 3042 bias-disable;
>> 3043 };
5551 }; 3044 };
5552 3045
5553 qup_spi10_cs: qup-spi !! 3046 qup_spi5_default: qup-spi5-default {
5554 pins = "gpio1 !! 3047 mux {
5555 function = "q !! 3048 pins = "gpio12", "gpio13",
5556 }; !! 3049 "gpio14", "gpio15";
>> 3050 function = "qup5";
>> 3051 };
5557 3052
5558 qup_spi10_cs_gpio: qu !! 3053 config {
5559 pins = "gpio1 !! 3054 pins = "gpio12", "gpio13",
5560 function = "g !! 3055 "gpio14", "gpio15";
>> 3056 drive-strength = <6>;
>> 3057 bias-disable;
>> 3058 };
5561 }; 3059 };
5562 3060
5563 qup_spi10_data_clk: q !! 3061 qup_spi6_default: qup-spi6-default {
5564 pins = "gpio1 !! 3062 mux {
5565 "gpio1 !! 3063 pins = "gpio16", "gpio17",
5566 function = "q !! 3064 "gpio18", "gpio19";
5567 }; !! 3065 function = "qup6";
>> 3066 };
5568 3067
5569 qup_spi11_cs: qup-spi !! 3068 config {
5570 pins = "gpio6 !! 3069 pins = "gpio16", "gpio17",
5571 function = "q !! 3070 "gpio18", "gpio19";
>> 3071 drive-strength = <6>;
>> 3072 bias-disable;
>> 3073 };
5572 }; 3074 };
5573 3075
5574 qup_spi11_cs_gpio: qu !! 3076 qup_spi7_default: qup-spi7-default {
5575 pins = "gpio6 !! 3077 mux {
5576 function = "g !! 3078 pins = "gpio20", "gpio21",
5577 }; !! 3079 "gpio22", "gpio23";
>> 3080 function = "qup7";
>> 3081 };
5578 3082
5579 qup_spi11_data_clk: q !! 3083 config {
5580 pins = "gpio6 !! 3084 pins = "gpio20", "gpio21",
5581 "gpio6 !! 3085 "gpio22", "gpio23";
5582 function = "q !! 3086 drive-strength = <6>;
>> 3087 bias-disable;
>> 3088 };
5583 }; 3089 };
5584 3090
5585 qup_spi12_cs: qup-spi !! 3091 qup_spi8_default: qup-spi8-default {
5586 pins = "gpio3 !! 3092 mux {
5587 function = "q !! 3093 pins = "gpio24", "gpio25",
5588 }; !! 3094 "gpio26", "gpio27";
>> 3095 function = "qup8";
>> 3096 };
5589 3097
5590 qup_spi12_cs_gpio: qu !! 3098 config {
5591 pins = "gpio3 !! 3099 pins = "gpio24", "gpio25",
5592 function = "g !! 3100 "gpio26", "gpio27";
>> 3101 drive-strength = <6>;
>> 3102 bias-disable;
>> 3103 };
5593 }; 3104 };
5594 3105
5595 qup_spi12_data_clk: q !! 3106 qup_spi9_default: qup-spi9-default {
5596 pins = "gpio3 !! 3107 mux {
5597 "gpio3 !! 3108 pins = "gpio125", "gpio126",
5598 function = "q !! 3109 "gpio127", "gpio128";
5599 }; !! 3110 function = "qup9";
>> 3111 };
5600 3112
5601 qup_spi13_cs: qup-spi !! 3113 config {
5602 pins = "gpio3 !! 3114 pins = "gpio125", "gpio126",
5603 function = "q !! 3115 "gpio127", "gpio128";
>> 3116 drive-strength = <6>;
>> 3117 bias-disable;
>> 3118 };
5604 }; 3119 };
5605 3120
5606 qup_spi13_cs_gpio: qu !! 3121 qup_spi10_default: qup-spi10-default {
5607 pins = "gpio3 !! 3122 mux {
5608 function = "g !! 3123 pins = "gpio129", "gpio130",
5609 }; !! 3124 "gpio131", "gpio132";
>> 3125 function = "qup10";
>> 3126 };
5610 3127
5611 qup_spi13_data_clk: q !! 3128 config {
5612 pins = "gpio3 !! 3129 pins = "gpio129", "gpio130",
5613 "gpio3 !! 3130 "gpio131", "gpio132";
5614 function = "q !! 3131 drive-strength = <6>;
>> 3132 bias-disable;
>> 3133 };
5615 }; 3134 };
5616 3135
5617 qup_spi14_cs: qup-spi !! 3136 qup_spi11_default: qup-spi11-default {
5618 pins = "gpio4 !! 3137 mux {
5619 function = "q !! 3138 pins = "gpio60", "gpio61",
5620 }; !! 3139 "gpio62", "gpio63";
>> 3140 function = "qup11";
>> 3141 };
5621 3142
5622 qup_spi14_cs_gpio: qu !! 3143 config {
5623 pins = "gpio4 !! 3144 pins = "gpio60", "gpio61",
5624 function = "g !! 3145 "gpio62", "gpio63";
>> 3146 drive-strength = <6>;
>> 3147 bias-disable;
>> 3148 };
5625 }; 3149 };
5626 3150
5627 qup_spi14_data_clk: q !! 3151 qup_spi12_default: qup-spi12-default {
5628 pins = "gpio4 !! 3152 mux {
5629 "gpio4 !! 3153 pins = "gpio32", "gpio33",
5630 function = "q !! 3154 "gpio34", "gpio35";
5631 }; !! 3155 function = "qup12";
>> 3156 };
5632 3157
5633 qup_spi15_cs: qup-spi !! 3158 config {
5634 pins = "gpio4 !! 3159 pins = "gpio32", "gpio33",
5635 function = "q !! 3160 "gpio34", "gpio35";
>> 3161 drive-strength = <6>;
>> 3162 bias-disable;
>> 3163 };
5636 }; 3164 };
5637 3165
5638 qup_spi15_cs_gpio: qu !! 3166 qup_spi13_default: qup-spi13-default {
5639 pins = "gpio4 !! 3167 mux {
5640 function = "g !! 3168 pins = "gpio36", "gpio37",
5641 }; !! 3169 "gpio38", "gpio39";
>> 3170 function = "qup13";
>> 3171 };
5642 3172
5643 qup_spi15_data_clk: q !! 3173 config {
5644 pins = "gpio4 !! 3174 pins = "gpio36", "gpio37",
5645 "gpio4 !! 3175 "gpio38", "gpio39";
5646 function = "q !! 3176 drive-strength = <6>;
>> 3177 bias-disable;
>> 3178 };
5647 }; 3179 };
5648 3180
5649 qup_spi16_cs: qup-spi !! 3181 qup_spi14_default: qup-spi14-default {
5650 pins = "gpio5 !! 3182 mux {
5651 function = "q !! 3183 pins = "gpio40", "gpio41",
5652 }; !! 3184 "gpio42", "gpio43";
>> 3185 function = "qup14";
>> 3186 };
5653 3187
5654 qup_spi16_cs_gpio: qu !! 3188 config {
5655 pins = "gpio5 !! 3189 pins = "gpio40", "gpio41",
5656 function = "g !! 3190 "gpio42", "gpio43";
>> 3191 drive-strength = <6>;
>> 3192 bias-disable;
>> 3193 };
5657 }; 3194 };
5658 3195
5659 qup_spi16_data_clk: q !! 3196 qup_spi15_default: qup-spi15-default {
5660 pins = "gpio4 !! 3197 mux {
5661 "gpio5 !! 3198 pins = "gpio44", "gpio45",
5662 function = "q !! 3199 "gpio46", "gpio47";
5663 }; !! 3200 function = "qup15";
>> 3201 };
5664 3202
5665 qup_spi17_cs: qup-spi !! 3203 config {
5666 pins = "gpio5 !! 3204 pins = "gpio44", "gpio45",
5667 function = "q !! 3205 "gpio46", "gpio47";
>> 3206 drive-strength = <6>;
>> 3207 bias-disable;
>> 3208 };
5668 }; 3209 };
5669 3210
5670 qup_spi17_cs_gpio: qu !! 3211 qup_spi16_default: qup-spi16-default {
5671 pins = "gpio5 !! 3212 mux {
5672 function = "g !! 3213 pins = "gpio48", "gpio49",
5673 }; !! 3214 "gpio50", "gpio51";
>> 3215 function = "qup16";
>> 3216 };
5674 3217
5675 qup_spi17_data_clk: q !! 3218 config {
5676 pins = "gpio5 !! 3219 pins = "gpio48", "gpio49",
5677 "gpio5 !! 3220 "gpio50", "gpio51";
5678 function = "q !! 3221 drive-strength = <6>;
>> 3222 bias-disable;
>> 3223 };
5679 }; 3224 };
5680 3225
5681 qup_spi18_cs: qup-spi !! 3226 qup_spi17_default: qup-spi17-default {
5682 pins = "gpio5 !! 3227 mux {
5683 function = "q !! 3228 pins = "gpio52", "gpio53",
5684 }; !! 3229 "gpio54", "gpio55";
>> 3230 function = "qup17";
>> 3231 };
5685 3232
5686 qup_spi18_cs_gpio: qu !! 3233 config {
5687 pins = "gpio5 !! 3234 pins = "gpio52", "gpio53",
5688 function = "g !! 3235 "gpio54", "gpio55";
>> 3236 drive-strength = <6>;
>> 3237 bias-disable;
>> 3238 };
5689 }; 3239 };
5690 3240
5691 qup_spi18_data_clk: q !! 3241 qup_spi18_default: qup-spi18-default {
5692 pins = "gpio5 !! 3242 mux {
5693 "gpio5 !! 3243 pins = "gpio56", "gpio57",
5694 function = "q !! 3244 "gpio58", "gpio59";
5695 }; !! 3245 function = "qup18";
>> 3246 };
5696 3247
5697 qup_spi19_cs: qup-spi !! 3248 config {
5698 pins = "gpio3 !! 3249 pins = "gpio56", "gpio57",
5699 function = "q !! 3250 "gpio58", "gpio59";
>> 3251 drive-strength = <6>;
>> 3252 bias-disable;
>> 3253 };
5700 }; 3254 };
5701 3255
5702 qup_spi19_cs_gpio: qu !! 3256 qup_spi19_default: qup-spi19-default {
5703 pins = "gpio3 !! 3257 mux {
5704 function = "g !! 3258 pins = "gpio0", "gpio1",
5705 }; !! 3259 "gpio2", "gpio3";
>> 3260 function = "qup19";
>> 3261 };
5706 3262
5707 qup_spi19_data_clk: q !! 3263 config {
5708 pins = "gpio0 !! 3264 pins = "gpio0", "gpio1",
5709 "gpio2 !! 3265 "gpio2", "gpio3";
5710 function = "q !! 3266 drive-strength = <6>;
>> 3267 bias-disable;
>> 3268 };
5711 }; 3269 };
5712 3270
5713 qup_uart2_default: qu !! 3271 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 3272 mux {
5715 function = "q !! 3273 pins = "gpio117", "gpio118";
>> 3274 function = "qup2";
>> 3275 };
5716 }; 3276 };
5717 3277
5718 qup_uart6_default: qu !! 3278 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 3279 mux {
5720 function = "q !! 3280 pins = "gpio16", "gpio17",
>> 3281 "gpio18", "gpio19";
>> 3282 function = "qup6";
>> 3283 };
5721 }; 3284 };
5722 3285
5723 qup_uart12_default: q !! 3286 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 3287 mux {
5725 function = "q !! 3288 pins = "gpio34", "gpio35";
>> 3289 function = "qup12";
>> 3290 };
5726 }; 3291 };
5727 3292
5728 qup_uart17_default: q !! 3293 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 3294 mux {
5730 function = "q !! 3295 pins = "gpio52", "gpio53",
>> 3296 "gpio54", "gpio55";
>> 3297 function = "qup17";
>> 3298 };
5731 }; 3299 };
5732 3300
5733 qup_uart18_default: q !! 3301 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 3302 mux {
5735 function = "q !! 3303 pins = "gpio58", "gpio59";
>> 3304 function = "qup18";
>> 3305 };
5736 }; 3306 };
5737 3307
5738 tert_mi2s_active: ter !! 3308 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 3309 sck {
5740 pins 3310 pins = "gpio133";
5741 funct 3311 function = "mi2s2_sck";
5742 drive 3312 drive-strength = <8>;
5743 bias- 3313 bias-disable;
5744 }; 3314 };
5745 3315
5746 data0-pins { !! 3316 data0 {
5747 pins 3317 pins = "gpio134";
5748 funct 3318 function = "mi2s2_data0";
5749 drive 3319 drive-strength = <8>;
5750 bias- 3320 bias-disable;
5751 outpu 3321 output-high;
5752 }; 3322 };
5753 3323
5754 ws-pins { !! 3324 ws {
5755 pins 3325 pins = "gpio135";
5756 funct 3326 function = "mi2s2_ws";
5757 drive 3327 drive-strength = <8>;
5758 outpu 3328 output-high;
5759 }; 3329 };
5760 }; 3330 };
5761 <<
5762 sdc2_sleep_state: sdc <<
5763 clk-pins { <<
5764 pins <<
5765 drive <<
5766 bias- <<
5767 }; <<
5768 <<
5769 cmd-pins { <<
5770 pins <<
5771 drive <<
5772 bias- <<
5773 }; <<
5774 <<
5775 data-pins { <<
5776 pins <<
5777 drive <<
5778 bias- <<
5779 }; <<
5780 }; <<
5781 <<
5782 pcie0_default_state: <<
5783 perst-pins { <<
5784 pins <<
5785 funct <<
5786 drive <<
5787 bias- <<
5788 }; <<
5789 <<
5790 clkreq-pins { <<
5791 pins <<
5792 funct <<
5793 drive <<
5794 bias- <<
5795 }; <<
5796 <<
5797 wake-pins { <<
5798 pins <<
5799 funct <<
5800 drive <<
5801 bias- <<
5802 }; <<
5803 }; <<
5804 <<
5805 pcie1_default_state: <<
5806 perst-pins { <<
5807 pins <<
5808 funct <<
5809 drive <<
5810 bias- <<
5811 }; <<
5812 <<
5813 clkreq-pins { <<
5814 pins <<
5815 funct <<
5816 drive <<
5817 bias- <<
5818 }; <<
5819 <<
5820 wake-pins { <<
5821 pins <<
5822 funct <<
5823 drive <<
5824 bias- <<
5825 }; <<
5826 }; <<
5827 <<
5828 pcie2_default_state: <<
5829 perst-pins { <<
5830 pins <<
5831 funct <<
5832 drive <<
5833 bias- <<
5834 }; <<
5835 <<
5836 clkreq-pins { <<
5837 pins <<
5838 funct <<
5839 drive <<
5840 bias- <<
5841 }; <<
5842 <<
5843 wake-pins { <<
5844 pins <<
5845 funct <<
5846 drive <<
5847 bias- <<
5848 }; <<
5849 }; <<
5850 }; 3331 };
5851 3332
5852 apps_smmu: iommu@15000000 { 3333 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 3334 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 3335 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 3336 #iommu-cells = <2>;
5856 #global-interrupts = 3337 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 3338 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 3339 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 3340 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 3341 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 3342 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 3343 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 3344 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 3345 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 3346 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 3347 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 3348 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 3349 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 3350 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 3351 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 3352 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 3353 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 3354 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 3355 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 3356 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 3357 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 3358 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 3359 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 3360 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 3361 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 3362 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 3363 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 3364 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 3365 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 3366 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 3367 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 3368 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 3369 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 3370 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 3371 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 3372 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 3373 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 3374 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 3375 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 3376 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 3377 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 3378 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 3379 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 3380 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 3381 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 3382 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 3383 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 3384 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 3385 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 3386 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 3387 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 3388 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 3389 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 3390 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 3391 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 3392 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 3393 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 3394 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 3395 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 3396 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 3397 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 3398 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 3399 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 3400 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 3401 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 3402 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 3403 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 3404 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 3405 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 3406 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 3407 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 3408 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 3409 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 3410 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 3411 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 3412 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 3413 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 3414 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 3415 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 3416 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 3417 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 3418 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 3419 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 3420 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 3421 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 3422 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 3423 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 3424 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 3425 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 3426 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 3427 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 3428 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 3429 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 3430 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 3431 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 3432 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 3433 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 3434 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 3435 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 3436 };
5957 3437
5958 adsp: remoteproc@17300000 { 3438 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 3439 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 3440 reg = <0 0x17300000 0 0x100>;
5961 3441
5962 interrupts-extended = !! 3442 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 3443 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 3444 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 3445 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 3446 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 3447 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 3448 "handover", "stop-ack";
5969 3449
5970 clocks = <&rpmhcc RPM 3450 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 3451 clock-names = "xo";
5972 3452
5973 power-domains = <&rpm !! 3453 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
5974 <&rpm !! 3454 <&rpmhpd SM8250_LCX>,
5975 power-domain-names = !! 3455 <&rpmhpd SM8250_LMX>;
>> 3456 power-domain-names = "load_state", "lcx", "lmx";
5976 3457
5977 memory-region = <&ads 3458 memory-region = <&adsp_mem>;
5978 3459
5979 qcom,qmp = <&aoss_qmp <<
5980 <<
5981 qcom,smem-states = <& 3460 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 3461 qcom,smem-state-names = "stop";
5983 3462
5984 status = "disabled"; 3463 status = "disabled";
5985 3464
5986 glink-edge { 3465 glink-edge {
5987 interrupts-ex 3466 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 3467 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 3468 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 3469 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 3470 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 3471
5993 label = "lpas 3472 label = "lpass";
5994 qcom,remote-p 3473 qcom,remote-pid = <2>;
5995 3474
5996 apr { 3475 apr {
5997 compa 3476 compatible = "qcom,apr-v2";
5998 qcom, 3477 qcom,glink-channels = "apr_audio_svc";
5999 qcom, !! 3478 qcom,apr-domain = <APR_DOMAIN_ADSP>;
6000 #addr 3479 #address-cells = <1>;
6001 #size 3480 #size-cells = <0>;
6002 3481
6003 servi !! 3482 apr-service@3 {
6004 3483 reg = <APR_SVC_ADSP_CORE>;
6005 3484 compatible = "qcom,q6core";
6006 3485 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 3486 };
6008 3487
6009 q6afe !! 3488 q6afe: apr-service@4 {
6010 3489 compatible = "qcom,q6afe";
6011 3490 reg = <APR_SVC_AFE>;
6012 3491 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 3492 q6afedai: dais {
6014 3493 compatible = "qcom,q6afe-dais";
6015 3494 #address-cells = <1>;
6016 3495 #size-cells = <0>;
6017 3496 #sound-dai-cells = <1>;
6018 3497 };
6019 3498
6020 !! 3499 q6afecc: cc {
6021 3500 compatible = "qcom,q6afe-clocks";
6022 3501 #clock-cells = <2>;
6023 3502 };
6024 }; 3503 };
6025 3504
6026 q6asm !! 3505 q6asm: apr-service@7 {
6027 3506 compatible = "qcom,q6asm";
6028 3507 reg = <APR_SVC_ASM>;
6029 3508 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 3509 q6asmdai: dais {
6031 3510 compatible = "qcom,q6asm-dais";
6032 3511 #address-cells = <1>;
6033 3512 #size-cells = <0>;
6034 3513 #sound-dai-cells = <1>;
6035 3514 iommus = <&apps_smmu 0x1801 0x0>;
6036 3515 };
6037 }; 3516 };
6038 3517
6039 q6adm !! 3518 q6adm: apr-service@8 {
6040 3519 compatible = "qcom,q6adm";
6041 3520 reg = <APR_SVC_ADM>;
6042 3521 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 3522 q6routing: routing {
6044 3523 compatible = "qcom,q6adm-routing";
6045 3524 #sound-dai-cells = <0>;
6046 3525 };
6047 }; 3526 };
6048 }; 3527 };
6049 3528
6050 fastrpc { 3529 fastrpc {
6051 compa 3530 compatible = "qcom,fastrpc";
6052 qcom, 3531 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 3532 label = "adsp";
6054 qcom, <<
6055 #addr 3533 #address-cells = <1>;
6056 #size 3534 #size-cells = <0>;
6057 3535
6058 compu 3536 compute-cb@3 {
6059 3537 compatible = "qcom,fastrpc-compute-cb";
6060 3538 reg = <3>;
6061 3539 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 3540 };
6063 3541
6064 compu 3542 compute-cb@4 {
6065 3543 compatible = "qcom,fastrpc-compute-cb";
6066 3544 reg = <4>;
6067 3545 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 3546 };
6069 3547
6070 compu 3548 compute-cb@5 {
6071 3549 compatible = "qcom,fastrpc-compute-cb";
6072 3550 reg = <5>;
6073 3551 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 3552 };
6075 }; 3553 };
6076 }; 3554 };
6077 }; 3555 };
6078 3556
6079 intc: interrupt-controller@17 3557 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 3558 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 3559 #interrupt-cells = <3>;
6082 interrupt-controller; 3560 interrupt-controller;
6083 reg = <0x0 0x17a00000 3561 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 3562 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 3563 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 3564 };
6087 3565
6088 watchdog@17c10000 { 3566 watchdog@17c10000 {
6089 compatible = "qcom,ap 3567 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 3568 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 3569 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 3570 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 3571 };
6094 3572
6095 timer@17c20000 { 3573 timer@17c20000 {
6096 #address-cells = <1>; !! 3574 #address-cells = <2>;
6097 #size-cells = <1>; !! 3575 #size-cells = <2>;
6098 ranges = <0 0 0 0x200 !! 3576 ranges;
6099 compatible = "arm,arm 3577 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 3578 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 3579 clock-frequency = <19200000>;
6102 3580
6103 frame@17c21000 { 3581 frame@17c21000 {
6104 frame-number 3582 frame-number = <0>;
6105 interrupts = 3583 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 3584 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 !! 3585 reg = <0x0 0x17c21000 0x0 0x1000>,
6108 <0x17c2 !! 3586 <0x0 0x17c22000 0x0 0x1000>;
6109 }; 3587 };
6110 3588
6111 frame@17c23000 { 3589 frame@17c23000 {
6112 frame-number 3590 frame-number = <1>;
6113 interrupts = 3591 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 !! 3592 reg = <0x0 0x17c23000 0x0 0x1000>;
6115 status = "dis 3593 status = "disabled";
6116 }; 3594 };
6117 3595
6118 frame@17c25000 { 3596 frame@17c25000 {
6119 frame-number 3597 frame-number = <2>;
6120 interrupts = 3598 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 !! 3599 reg = <0x0 0x17c25000 0x0 0x1000>;
6122 status = "dis 3600 status = "disabled";
6123 }; 3601 };
6124 3602
6125 frame@17c27000 { 3603 frame@17c27000 {
6126 frame-number 3604 frame-number = <3>;
6127 interrupts = 3605 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 !! 3606 reg = <0x0 0x17c27000 0x0 0x1000>;
6129 status = "dis 3607 status = "disabled";
6130 }; 3608 };
6131 3609
6132 frame@17c29000 { 3610 frame@17c29000 {
6133 frame-number 3611 frame-number = <4>;
6134 interrupts = 3612 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 !! 3613 reg = <0x0 0x17c29000 0x0 0x1000>;
6136 status = "dis 3614 status = "disabled";
6137 }; 3615 };
6138 3616
6139 frame@17c2b000 { 3617 frame@17c2b000 {
6140 frame-number 3618 frame-number = <5>;
6141 interrupts = 3619 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 !! 3620 reg = <0x0 0x17c2b000 0x0 0x1000>;
6143 status = "dis 3621 status = "disabled";
6144 }; 3622 };
6145 3623
6146 frame@17c2d000 { 3624 frame@17c2d000 {
6147 frame-number 3625 frame-number = <6>;
6148 interrupts = 3626 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 !! 3627 reg = <0x0 0x17c2d000 0x0 0x1000>;
6150 status = "dis 3628 status = "disabled";
6151 }; 3629 };
6152 }; 3630 };
6153 3631
6154 apps_rsc: rsc@18200000 { 3632 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 3633 label = "apps_rsc";
6156 compatible = "qcom,rp 3634 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 3635 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 3636 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 3637 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 3638 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 3639 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 3640 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 3641 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 3642 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 3643 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 3644 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 3645 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 3646
6170 rpmhcc: clock-control 3647 rpmhcc: clock-controller {
6171 compatible = 3648 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 3649 #clock-cells = <1>;
6173 clock-names = 3650 clock-names = "xo";
6174 clocks = <&xo 3651 clocks = <&xo_board>;
6175 }; 3652 };
6176 3653
6177 rpmhpd: power-control 3654 rpmhpd: power-controller {
6178 compatible = 3655 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 3656 #power-domain-cells = <1>;
6180 operating-poi 3657 operating-points-v2 = <&rpmhpd_opp_table>;
6181 3658
6182 rpmhpd_opp_ta 3659 rpmhpd_opp_table: opp-table {
6183 compa 3660 compatible = "operating-points-v2";
6184 3661
6185 rpmhp 3662 rpmhpd_opp_ret: opp1 {
6186 3663 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 3664 };
6188 3665
6189 rpmhp 3666 rpmhpd_opp_min_svs: opp2 {
6190 3667 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 3668 };
6192 3669
6193 rpmhp 3670 rpmhpd_opp_low_svs: opp3 {
6194 3671 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 3672 };
6196 3673
6197 rpmhp 3674 rpmhpd_opp_svs: opp4 {
6198 3675 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 3676 };
6200 3677
6201 rpmhp 3678 rpmhpd_opp_svs_l1: opp5 {
6202 3679 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 3680 };
6204 3681
6205 rpmhp 3682 rpmhpd_opp_nom: opp6 {
6206 3683 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 3684 };
6208 3685
6209 rpmhp 3686 rpmhpd_opp_nom_l1: opp7 {
6210 3687 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 3688 };
6212 3689
6213 rpmhp 3690 rpmhpd_opp_nom_l2: opp8 {
6214 3691 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 3692 };
6216 3693
6217 rpmhp 3694 rpmhpd_opp_turbo: opp9 {
6218 3695 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 3696 };
6220 3697
6221 rpmhp 3698 rpmhpd_opp_turbo_l1: opp10 {
6222 3699 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 3700 };
6224 }; 3701 };
6225 }; 3702 };
6226 3703
6227 apps_bcm_voter: bcm-v !! 3704 apps_bcm_voter: bcm_voter {
6228 compatible = 3705 compatible = "qcom,bcm-voter";
6229 }; 3706 };
6230 }; 3707 };
6231 3708
6232 epss_l3: interconnect@1859000 !! 3709 epss_l3: interconnect@18591000 {
6233 compatible = "qcom,sm !! 3710 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 3711 reg = <0 0x18590000 0 0x1000>;
6235 3712
6236 clocks = <&rpmhcc RPM 3713 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 3714 clock-names = "xo", "alternate";
6238 3715
6239 #interconnect-cells = 3716 #interconnect-cells = <1>;
6240 }; 3717 };
6241 3718
6242 cpufreq_hw: cpufreq@18591000 3719 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 3720 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 3721 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 3722 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 3723 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 3724 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 3725 "freq-domain2";
6249 3726
6250 clocks = <&rpmhcc RPM 3727 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 3728 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI !! 3729
6253 <GIC_SPI <<
6254 <GIC_SPI <<
6255 interrupt-names = "dc <<
6256 #freq-domain-cells = 3730 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 3731 };
6259 }; 3732 };
6260 3733
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 3734 timer {
6265 compatible = "arm,armv8-timer 3735 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 3736 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 3737 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 3738 <GIC_PPI 14
6269 (GIC_CPU_MASK 3739 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 3740 <GIC_PPI 11
6271 (GIC_CPU_MASK 3741 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 3742 <GIC_PPI 10
6273 (GIC_CPU_MASK 3743 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 3744 };
6275 3745
6276 thermal-zones { 3746 thermal-zones {
6277 cpu0-thermal { 3747 cpu0-thermal {
6278 polling-delay-passive 3748 polling-delay-passive = <250>;
>> 3749 polling-delay = <1000>;
6279 3750
6280 thermal-sensors = <&t 3751 thermal-sensors = <&tsens0 1>;
6281 3752
6282 trips { 3753 trips {
6283 cpu0_alert0: 3754 cpu0_alert0: trip-point0 {
6284 tempe 3755 temperature = <90000>;
6285 hyste 3756 hysteresis = <2000>;
6286 type 3757 type = "passive";
6287 }; 3758 };
6288 3759
6289 cpu0_alert1: 3760 cpu0_alert1: trip-point1 {
6290 tempe 3761 temperature = <95000>;
6291 hyste 3762 hysteresis = <2000>;
6292 type 3763 type = "passive";
6293 }; 3764 };
6294 3765
6295 cpu0_crit: cp !! 3766 cpu0_crit: cpu_crit {
6296 tempe 3767 temperature = <110000>;
6297 hyste 3768 hysteresis = <1000>;
6298 type 3769 type = "critical";
6299 }; 3770 };
6300 }; 3771 };
6301 3772
6302 cooling-maps { 3773 cooling-maps {
6303 map0 { 3774 map0 {
6304 trip 3775 trip = <&cpu0_alert0>;
6305 cooli 3776 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 3777 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 3778 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 3779 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 3780 };
6310 map1 { 3781 map1 {
6311 trip 3782 trip = <&cpu0_alert1>;
6312 cooli 3783 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 3784 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 3785 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 3786 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 3787 };
6317 }; 3788 };
6318 }; 3789 };
6319 3790
6320 cpu1-thermal { 3791 cpu1-thermal {
6321 polling-delay-passive 3792 polling-delay-passive = <250>;
>> 3793 polling-delay = <1000>;
6322 3794
6323 thermal-sensors = <&t 3795 thermal-sensors = <&tsens0 2>;
6324 3796
6325 trips { 3797 trips {
6326 cpu1_alert0: 3798 cpu1_alert0: trip-point0 {
6327 tempe 3799 temperature = <90000>;
6328 hyste 3800 hysteresis = <2000>;
6329 type 3801 type = "passive";
6330 }; 3802 };
6331 3803
6332 cpu1_alert1: 3804 cpu1_alert1: trip-point1 {
6333 tempe 3805 temperature = <95000>;
6334 hyste 3806 hysteresis = <2000>;
6335 type 3807 type = "passive";
6336 }; 3808 };
6337 3809
6338 cpu1_crit: cp !! 3810 cpu1_crit: cpu_crit {
6339 tempe 3811 temperature = <110000>;
6340 hyste 3812 hysteresis = <1000>;
6341 type 3813 type = "critical";
6342 }; 3814 };
6343 }; 3815 };
6344 3816
6345 cooling-maps { 3817 cooling-maps {
6346 map0 { 3818 map0 {
6347 trip 3819 trip = <&cpu1_alert0>;
6348 cooli 3820 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 3821 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 3822 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 3823 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 3824 };
6353 map1 { 3825 map1 {
6354 trip 3826 trip = <&cpu1_alert1>;
6355 cooli 3827 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 3828 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 3829 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 3830 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 3831 };
6360 }; 3832 };
6361 }; 3833 };
6362 3834
6363 cpu2-thermal { 3835 cpu2-thermal {
6364 polling-delay-passive 3836 polling-delay-passive = <250>;
>> 3837 polling-delay = <1000>;
6365 3838
6366 thermal-sensors = <&t 3839 thermal-sensors = <&tsens0 3>;
6367 3840
6368 trips { 3841 trips {
6369 cpu2_alert0: 3842 cpu2_alert0: trip-point0 {
6370 tempe 3843 temperature = <90000>;
6371 hyste 3844 hysteresis = <2000>;
6372 type 3845 type = "passive";
6373 }; 3846 };
6374 3847
6375 cpu2_alert1: 3848 cpu2_alert1: trip-point1 {
6376 tempe 3849 temperature = <95000>;
6377 hyste 3850 hysteresis = <2000>;
6378 type 3851 type = "passive";
6379 }; 3852 };
6380 3853
6381 cpu2_crit: cp !! 3854 cpu2_crit: cpu_crit {
6382 tempe 3855 temperature = <110000>;
6383 hyste 3856 hysteresis = <1000>;
6384 type 3857 type = "critical";
6385 }; 3858 };
6386 }; 3859 };
6387 3860
6388 cooling-maps { 3861 cooling-maps {
6389 map0 { 3862 map0 {
6390 trip 3863 trip = <&cpu2_alert0>;
6391 cooli 3864 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 3865 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 3866 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 3867 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 3868 };
6396 map1 { 3869 map1 {
6397 trip 3870 trip = <&cpu2_alert1>;
6398 cooli 3871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 3872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 3873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 3874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 3875 };
6403 }; 3876 };
6404 }; 3877 };
6405 3878
6406 cpu3-thermal { 3879 cpu3-thermal {
6407 polling-delay-passive 3880 polling-delay-passive = <250>;
>> 3881 polling-delay = <1000>;
6408 3882
6409 thermal-sensors = <&t 3883 thermal-sensors = <&tsens0 4>;
6410 3884
6411 trips { 3885 trips {
6412 cpu3_alert0: 3886 cpu3_alert0: trip-point0 {
6413 tempe 3887 temperature = <90000>;
6414 hyste 3888 hysteresis = <2000>;
6415 type 3889 type = "passive";
6416 }; 3890 };
6417 3891
6418 cpu3_alert1: 3892 cpu3_alert1: trip-point1 {
6419 tempe 3893 temperature = <95000>;
6420 hyste 3894 hysteresis = <2000>;
6421 type 3895 type = "passive";
6422 }; 3896 };
6423 3897
6424 cpu3_crit: cp !! 3898 cpu3_crit: cpu_crit {
6425 tempe 3899 temperature = <110000>;
6426 hyste 3900 hysteresis = <1000>;
6427 type 3901 type = "critical";
6428 }; 3902 };
6429 }; 3903 };
6430 3904
6431 cooling-maps { 3905 cooling-maps {
6432 map0 { 3906 map0 {
6433 trip 3907 trip = <&cpu3_alert0>;
6434 cooli 3908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 3909 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 3910 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 3911 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 3912 };
6439 map1 { 3913 map1 {
6440 trip 3914 trip = <&cpu3_alert1>;
6441 cooli 3915 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 3916 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 3917 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 3918 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 3919 };
6446 }; 3920 };
6447 }; 3921 };
6448 3922
6449 cpu4-top-thermal { 3923 cpu4-top-thermal {
6450 polling-delay-passive 3924 polling-delay-passive = <250>;
>> 3925 polling-delay = <1000>;
6451 3926
6452 thermal-sensors = <&t 3927 thermal-sensors = <&tsens0 7>;
6453 3928
6454 trips { 3929 trips {
6455 cpu4_top_aler 3930 cpu4_top_alert0: trip-point0 {
6456 tempe 3931 temperature = <90000>;
6457 hyste 3932 hysteresis = <2000>;
6458 type 3933 type = "passive";
6459 }; 3934 };
6460 3935
6461 cpu4_top_aler 3936 cpu4_top_alert1: trip-point1 {
6462 tempe 3937 temperature = <95000>;
6463 hyste 3938 hysteresis = <2000>;
6464 type 3939 type = "passive";
6465 }; 3940 };
6466 3941
6467 cpu4_top_crit !! 3942 cpu4_top_crit: cpu_crit {
6468 tempe 3943 temperature = <110000>;
6469 hyste 3944 hysteresis = <1000>;
6470 type 3945 type = "critical";
6471 }; 3946 };
6472 }; 3947 };
6473 3948
6474 cooling-maps { 3949 cooling-maps {
6475 map0 { 3950 map0 {
6476 trip 3951 trip = <&cpu4_top_alert0>;
6477 cooli 3952 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 3953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 3954 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 3955 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 3956 };
6482 map1 { 3957 map1 {
6483 trip 3958 trip = <&cpu4_top_alert1>;
6484 cooli 3959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 3960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 3961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 3962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 3963 };
6489 }; 3964 };
6490 }; 3965 };
6491 3966
6492 cpu5-top-thermal { 3967 cpu5-top-thermal {
6493 polling-delay-passive 3968 polling-delay-passive = <250>;
>> 3969 polling-delay = <1000>;
6494 3970
6495 thermal-sensors = <&t 3971 thermal-sensors = <&tsens0 8>;
6496 3972
6497 trips { 3973 trips {
6498 cpu5_top_aler 3974 cpu5_top_alert0: trip-point0 {
6499 tempe 3975 temperature = <90000>;
6500 hyste 3976 hysteresis = <2000>;
6501 type 3977 type = "passive";
6502 }; 3978 };
6503 3979
6504 cpu5_top_aler 3980 cpu5_top_alert1: trip-point1 {
6505 tempe 3981 temperature = <95000>;
6506 hyste 3982 hysteresis = <2000>;
6507 type 3983 type = "passive";
6508 }; 3984 };
6509 3985
6510 cpu5_top_crit !! 3986 cpu5_top_crit: cpu_crit {
6511 tempe 3987 temperature = <110000>;
6512 hyste 3988 hysteresis = <1000>;
6513 type 3989 type = "critical";
6514 }; 3990 };
6515 }; 3991 };
6516 3992
6517 cooling-maps { 3993 cooling-maps {
6518 map0 { 3994 map0 {
6519 trip 3995 trip = <&cpu5_top_alert0>;
6520 cooli 3996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 3997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 3998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 3999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4000 };
6525 map1 { 4001 map1 {
6526 trip 4002 trip = <&cpu5_top_alert1>;
6527 cooli 4003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4007 };
6532 }; 4008 };
6533 }; 4009 };
6534 4010
6535 cpu6-top-thermal { 4011 cpu6-top-thermal {
6536 polling-delay-passive 4012 polling-delay-passive = <250>;
>> 4013 polling-delay = <1000>;
6537 4014
6538 thermal-sensors = <&t 4015 thermal-sensors = <&tsens0 9>;
6539 4016
6540 trips { 4017 trips {
6541 cpu6_top_aler 4018 cpu6_top_alert0: trip-point0 {
6542 tempe 4019 temperature = <90000>;
6543 hyste 4020 hysteresis = <2000>;
6544 type 4021 type = "passive";
6545 }; 4022 };
6546 4023
6547 cpu6_top_aler 4024 cpu6_top_alert1: trip-point1 {
6548 tempe 4025 temperature = <95000>;
6549 hyste 4026 hysteresis = <2000>;
6550 type 4027 type = "passive";
6551 }; 4028 };
6552 4029
6553 cpu6_top_crit !! 4030 cpu6_top_crit: cpu_crit {
6554 tempe 4031 temperature = <110000>;
6555 hyste 4032 hysteresis = <1000>;
6556 type 4033 type = "critical";
6557 }; 4034 };
6558 }; 4035 };
6559 4036
6560 cooling-maps { 4037 cooling-maps {
6561 map0 { 4038 map0 {
6562 trip 4039 trip = <&cpu6_top_alert0>;
6563 cooli 4040 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 4041 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 4042 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 4043 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 4044 };
6568 map1 { 4045 map1 {
6569 trip 4046 trip = <&cpu6_top_alert1>;
6570 cooli 4047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 4048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 4049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 4050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 4051 };
6575 }; 4052 };
6576 }; 4053 };
6577 4054
6578 cpu7-top-thermal { 4055 cpu7-top-thermal {
6579 polling-delay-passive 4056 polling-delay-passive = <250>;
>> 4057 polling-delay = <1000>;
6580 4058
6581 thermal-sensors = <&t 4059 thermal-sensors = <&tsens0 10>;
6582 4060
6583 trips { 4061 trips {
6584 cpu7_top_aler 4062 cpu7_top_alert0: trip-point0 {
6585 tempe 4063 temperature = <90000>;
6586 hyste 4064 hysteresis = <2000>;
6587 type 4065 type = "passive";
6588 }; 4066 };
6589 4067
6590 cpu7_top_aler 4068 cpu7_top_alert1: trip-point1 {
6591 tempe 4069 temperature = <95000>;
6592 hyste 4070 hysteresis = <2000>;
6593 type 4071 type = "passive";
6594 }; 4072 };
6595 4073
6596 cpu7_top_crit !! 4074 cpu7_top_crit: cpu_crit {
6597 tempe 4075 temperature = <110000>;
6598 hyste 4076 hysteresis = <1000>;
6599 type 4077 type = "critical";
6600 }; 4078 };
6601 }; 4079 };
6602 4080
6603 cooling-maps { 4081 cooling-maps {
6604 map0 { 4082 map0 {
6605 trip 4083 trip = <&cpu7_top_alert0>;
6606 cooli 4084 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 4085 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 4086 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 4087 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 4088 };
6611 map1 { 4089 map1 {
6612 trip 4090 trip = <&cpu7_top_alert1>;
6613 cooli 4091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 4092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 4093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 4094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 4095 };
6618 }; 4096 };
6619 }; 4097 };
6620 4098
6621 cpu4-bottom-thermal { 4099 cpu4-bottom-thermal {
6622 polling-delay-passive 4100 polling-delay-passive = <250>;
>> 4101 polling-delay = <1000>;
6623 4102
6624 thermal-sensors = <&t 4103 thermal-sensors = <&tsens0 11>;
6625 4104
6626 trips { 4105 trips {
6627 cpu4_bottom_a 4106 cpu4_bottom_alert0: trip-point0 {
6628 tempe 4107 temperature = <90000>;
6629 hyste 4108 hysteresis = <2000>;
6630 type 4109 type = "passive";
6631 }; 4110 };
6632 4111
6633 cpu4_bottom_a 4112 cpu4_bottom_alert1: trip-point1 {
6634 tempe 4113 temperature = <95000>;
6635 hyste 4114 hysteresis = <2000>;
6636 type 4115 type = "passive";
6637 }; 4116 };
6638 4117
6639 cpu4_bottom_c !! 4118 cpu4_bottom_crit: cpu_crit {
6640 tempe 4119 temperature = <110000>;
6641 hyste 4120 hysteresis = <1000>;
6642 type 4121 type = "critical";
6643 }; 4122 };
6644 }; 4123 };
6645 4124
6646 cooling-maps { 4125 cooling-maps {
6647 map0 { 4126 map0 {
6648 trip 4127 trip = <&cpu4_bottom_alert0>;
6649 cooli 4128 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 4129 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 4130 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 4131 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 4132 };
6654 map1 { 4133 map1 {
6655 trip 4134 trip = <&cpu4_bottom_alert1>;
6656 cooli 4135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 4136 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 4137 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 4138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 4139 };
6661 }; 4140 };
6662 }; 4141 };
6663 4142
6664 cpu5-bottom-thermal { 4143 cpu5-bottom-thermal {
6665 polling-delay-passive 4144 polling-delay-passive = <250>;
>> 4145 polling-delay = <1000>;
6666 4146
6667 thermal-sensors = <&t 4147 thermal-sensors = <&tsens0 12>;
6668 4148
6669 trips { 4149 trips {
6670 cpu5_bottom_a 4150 cpu5_bottom_alert0: trip-point0 {
6671 tempe 4151 temperature = <90000>;
6672 hyste 4152 hysteresis = <2000>;
6673 type 4153 type = "passive";
6674 }; 4154 };
6675 4155
6676 cpu5_bottom_a 4156 cpu5_bottom_alert1: trip-point1 {
6677 tempe 4157 temperature = <95000>;
6678 hyste 4158 hysteresis = <2000>;
6679 type 4159 type = "passive";
6680 }; 4160 };
6681 4161
6682 cpu5_bottom_c !! 4162 cpu5_bottom_crit: cpu_crit {
6683 tempe 4163 temperature = <110000>;
6684 hyste 4164 hysteresis = <1000>;
6685 type 4165 type = "critical";
6686 }; 4166 };
6687 }; 4167 };
6688 4168
6689 cooling-maps { 4169 cooling-maps {
6690 map0 { 4170 map0 {
6691 trip 4171 trip = <&cpu5_bottom_alert0>;
6692 cooli 4172 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 4173 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 4174 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 4175 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 4176 };
6697 map1 { 4177 map1 {
6698 trip 4178 trip = <&cpu5_bottom_alert1>;
6699 cooli 4179 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 4180 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 4181 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 4182 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 4183 };
6704 }; 4184 };
6705 }; 4185 };
6706 4186
6707 cpu6-bottom-thermal { 4187 cpu6-bottom-thermal {
6708 polling-delay-passive 4188 polling-delay-passive = <250>;
>> 4189 polling-delay = <1000>;
6709 4190
6710 thermal-sensors = <&t 4191 thermal-sensors = <&tsens0 13>;
6711 4192
6712 trips { 4193 trips {
6713 cpu6_bottom_a 4194 cpu6_bottom_alert0: trip-point0 {
6714 tempe 4195 temperature = <90000>;
6715 hyste 4196 hysteresis = <2000>;
6716 type 4197 type = "passive";
6717 }; 4198 };
6718 4199
6719 cpu6_bottom_a 4200 cpu6_bottom_alert1: trip-point1 {
6720 tempe 4201 temperature = <95000>;
6721 hyste 4202 hysteresis = <2000>;
6722 type 4203 type = "passive";
6723 }; 4204 };
6724 4205
6725 cpu6_bottom_c !! 4206 cpu6_bottom_crit: cpu_crit {
6726 tempe 4207 temperature = <110000>;
6727 hyste 4208 hysteresis = <1000>;
6728 type 4209 type = "critical";
6729 }; 4210 };
6730 }; 4211 };
6731 4212
6732 cooling-maps { 4213 cooling-maps {
6733 map0 { 4214 map0 {
6734 trip 4215 trip = <&cpu6_bottom_alert0>;
6735 cooli 4216 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 4217 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 4218 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 4219 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 4220 };
6740 map1 { 4221 map1 {
6741 trip 4222 trip = <&cpu6_bottom_alert1>;
6742 cooli 4223 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 4224 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 4225 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 4226 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 4227 };
6747 }; 4228 };
6748 }; 4229 };
6749 4230
6750 cpu7-bottom-thermal { 4231 cpu7-bottom-thermal {
6751 polling-delay-passive 4232 polling-delay-passive = <250>;
>> 4233 polling-delay = <1000>;
6752 4234
6753 thermal-sensors = <&t 4235 thermal-sensors = <&tsens0 14>;
6754 4236
6755 trips { 4237 trips {
6756 cpu7_bottom_a 4238 cpu7_bottom_alert0: trip-point0 {
6757 tempe 4239 temperature = <90000>;
6758 hyste 4240 hysteresis = <2000>;
6759 type 4241 type = "passive";
6760 }; 4242 };
6761 4243
6762 cpu7_bottom_a 4244 cpu7_bottom_alert1: trip-point1 {
6763 tempe 4245 temperature = <95000>;
6764 hyste 4246 hysteresis = <2000>;
6765 type 4247 type = "passive";
6766 }; 4248 };
6767 4249
6768 cpu7_bottom_c !! 4250 cpu7_bottom_crit: cpu_crit {
6769 tempe 4251 temperature = <110000>;
6770 hyste 4252 hysteresis = <1000>;
6771 type 4253 type = "critical";
6772 }; 4254 };
6773 }; 4255 };
6774 4256
6775 cooling-maps { 4257 cooling-maps {
6776 map0 { 4258 map0 {
6777 trip 4259 trip = <&cpu7_bottom_alert0>;
6778 cooli 4260 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 4261 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 4262 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 4263 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 4264 };
6783 map1 { 4265 map1 {
6784 trip 4266 trip = <&cpu7_bottom_alert1>;
6785 cooli 4267 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 4268 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 4269 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 4270 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 4271 };
6790 }; 4272 };
6791 }; 4273 };
6792 4274
6793 aoss0-thermal { 4275 aoss0-thermal {
6794 polling-delay-passive 4276 polling-delay-passive = <250>;
>> 4277 polling-delay = <1000>;
6795 4278
6796 thermal-sensors = <&t 4279 thermal-sensors = <&tsens0 0>;
6797 4280
6798 trips { 4281 trips {
6799 aoss0_alert0: 4282 aoss0_alert0: trip-point0 {
6800 tempe 4283 temperature = <90000>;
6801 hyste 4284 hysteresis = <2000>;
6802 type 4285 type = "hot";
6803 }; 4286 };
6804 }; 4287 };
6805 }; 4288 };
6806 4289
6807 cluster0-thermal { 4290 cluster0-thermal {
6808 polling-delay-passive 4291 polling-delay-passive = <250>;
>> 4292 polling-delay = <1000>;
6809 4293
6810 thermal-sensors = <&t 4294 thermal-sensors = <&tsens0 5>;
6811 4295
6812 trips { 4296 trips {
6813 cluster0_aler 4297 cluster0_alert0: trip-point0 {
6814 tempe 4298 temperature = <90000>;
6815 hyste 4299 hysteresis = <2000>;
6816 type 4300 type = "hot";
6817 }; 4301 };
6818 cluster0_crit !! 4302 cluster0_crit: cluster0_crit {
6819 tempe 4303 temperature = <110000>;
6820 hyste 4304 hysteresis = <2000>;
6821 type 4305 type = "critical";
6822 }; 4306 };
6823 }; 4307 };
6824 }; 4308 };
6825 4309
6826 cluster1-thermal { 4310 cluster1-thermal {
6827 polling-delay-passive 4311 polling-delay-passive = <250>;
>> 4312 polling-delay = <1000>;
6828 4313
6829 thermal-sensors = <&t 4314 thermal-sensors = <&tsens0 6>;
6830 4315
6831 trips { 4316 trips {
6832 cluster1_aler 4317 cluster1_alert0: trip-point0 {
6833 tempe 4318 temperature = <90000>;
6834 hyste 4319 hysteresis = <2000>;
6835 type 4320 type = "hot";
6836 }; 4321 };
6837 cluster1_crit !! 4322 cluster1_crit: cluster1_crit {
6838 tempe 4323 temperature = <110000>;
6839 hyste 4324 hysteresis = <2000>;
6840 type 4325 type = "critical";
6841 }; 4326 };
6842 }; 4327 };
6843 }; 4328 };
6844 4329
6845 gpu-top-thermal { !! 4330 gpu-thermal-top {
6846 polling-delay-passive 4331 polling-delay-passive = <250>;
>> 4332 polling-delay = <1000>;
6847 4333
6848 thermal-sensors = <&t 4334 thermal-sensors = <&tsens0 15>;
6849 4335
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 4336 trips {
6858 gpu_top_alert !! 4337 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 4338 temperature = <90000>;
6866 hyste !! 4339 hysteresis = <2000>;
6867 type 4340 type = "hot";
6868 }; 4341 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 4342 };
6876 }; 4343 };
6877 4344
6878 aoss1-thermal { 4345 aoss1-thermal {
6879 polling-delay-passive 4346 polling-delay-passive = <250>;
>> 4347 polling-delay = <1000>;
6880 4348
6881 thermal-sensors = <&t 4349 thermal-sensors = <&tsens1 0>;
6882 4350
6883 trips { 4351 trips {
6884 aoss1_alert0: 4352 aoss1_alert0: trip-point0 {
6885 tempe 4353 temperature = <90000>;
6886 hyste 4354 hysteresis = <2000>;
6887 type 4355 type = "hot";
6888 }; 4356 };
6889 }; 4357 };
6890 }; 4358 };
6891 4359
6892 wlan-thermal { 4360 wlan-thermal {
6893 polling-delay-passive 4361 polling-delay-passive = <250>;
>> 4362 polling-delay = <1000>;
6894 4363
6895 thermal-sensors = <&t 4364 thermal-sensors = <&tsens1 1>;
6896 4365
6897 trips { 4366 trips {
6898 wlan_alert0: 4367 wlan_alert0: trip-point0 {
6899 tempe 4368 temperature = <90000>;
6900 hyste 4369 hysteresis = <2000>;
6901 type 4370 type = "hot";
6902 }; 4371 };
6903 }; 4372 };
6904 }; 4373 };
6905 4374
6906 video-thermal { 4375 video-thermal {
6907 polling-delay-passive 4376 polling-delay-passive = <250>;
>> 4377 polling-delay = <1000>;
6908 4378
6909 thermal-sensors = <&t 4379 thermal-sensors = <&tsens1 2>;
6910 4380
6911 trips { 4381 trips {
6912 video_alert0: 4382 video_alert0: trip-point0 {
6913 tempe 4383 temperature = <90000>;
6914 hyste 4384 hysteresis = <2000>;
6915 type 4385 type = "hot";
6916 }; 4386 };
6917 }; 4387 };
6918 }; 4388 };
6919 4389
6920 mem-thermal { 4390 mem-thermal {
6921 polling-delay-passive 4391 polling-delay-passive = <250>;
>> 4392 polling-delay = <1000>;
6922 4393
6923 thermal-sensors = <&t 4394 thermal-sensors = <&tsens1 3>;
6924 4395
6925 trips { 4396 trips {
6926 mem_alert0: t 4397 mem_alert0: trip-point0 {
6927 tempe 4398 temperature = <90000>;
6928 hyste 4399 hysteresis = <2000>;
6929 type 4400 type = "hot";
6930 }; 4401 };
6931 }; 4402 };
6932 }; 4403 };
6933 4404
6934 q6-hvx-thermal { 4405 q6-hvx-thermal {
6935 polling-delay-passive 4406 polling-delay-passive = <250>;
>> 4407 polling-delay = <1000>;
6936 4408
6937 thermal-sensors = <&t 4409 thermal-sensors = <&tsens1 4>;
6938 4410
6939 trips { 4411 trips {
6940 q6_hvx_alert0 4412 q6_hvx_alert0: trip-point0 {
6941 tempe 4413 temperature = <90000>;
6942 hyste 4414 hysteresis = <2000>;
6943 type 4415 type = "hot";
6944 }; 4416 };
6945 }; 4417 };
6946 }; 4418 };
6947 4419
6948 camera-thermal { 4420 camera-thermal {
6949 polling-delay-passive 4421 polling-delay-passive = <250>;
>> 4422 polling-delay = <1000>;
6950 4423
6951 thermal-sensors = <&t 4424 thermal-sensors = <&tsens1 5>;
6952 4425
6953 trips { 4426 trips {
6954 camera_alert0 4427 camera_alert0: trip-point0 {
6955 tempe 4428 temperature = <90000>;
6956 hyste 4429 hysteresis = <2000>;
6957 type 4430 type = "hot";
6958 }; 4431 };
6959 }; 4432 };
6960 }; 4433 };
6961 4434
6962 compute-thermal { 4435 compute-thermal {
6963 polling-delay-passive 4436 polling-delay-passive = <250>;
>> 4437 polling-delay = <1000>;
6964 4438
6965 thermal-sensors = <&t 4439 thermal-sensors = <&tsens1 6>;
6966 4440
6967 trips { 4441 trips {
6968 compute_alert 4442 compute_alert0: trip-point0 {
6969 tempe 4443 temperature = <90000>;
6970 hyste 4444 hysteresis = <2000>;
6971 type 4445 type = "hot";
6972 }; 4446 };
6973 }; 4447 };
6974 }; 4448 };
6975 4449
6976 npu-thermal { 4450 npu-thermal {
6977 polling-delay-passive 4451 polling-delay-passive = <250>;
>> 4452 polling-delay = <1000>;
6978 4453
6979 thermal-sensors = <&t 4454 thermal-sensors = <&tsens1 7>;
6980 4455
6981 trips { 4456 trips {
6982 npu_alert0: t 4457 npu_alert0: trip-point0 {
6983 tempe 4458 temperature = <90000>;
6984 hyste 4459 hysteresis = <2000>;
6985 type 4460 type = "hot";
6986 }; 4461 };
6987 }; 4462 };
6988 }; 4463 };
6989 4464
6990 gpu-bottom-thermal { !! 4465 gpu-thermal-bottom {
6991 polling-delay-passive 4466 polling-delay-passive = <250>;
>> 4467 polling-delay = <1000>;
6992 4468
6993 thermal-sensors = <&t 4469 thermal-sensors = <&tsens1 8>;
6994 4470
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 4471 trips {
7003 gpu_bottom_al !! 4472 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 4473 temperature = <90000>;
7011 hyste !! 4474 hysteresis = <2000>;
7012 type 4475 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 4476 };
7020 }; 4477 };
7021 }; 4478 };
7022 }; 4479 };
7023 }; 4480 };
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