1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> <<
12 #include <dt-bindings/gpio/gpio.h> <<
13 #include <dt-bindings/interconnect/qcom,osm-l3 11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 12 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 13 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 14 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h> 15 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 16 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 18 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 19 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 20 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 21
26 / { 22 / {
27 interrupt-parent = <&intc>; 23 interrupt-parent = <&intc>;
28 24
29 #address-cells = <2>; 25 #address-cells = <2>;
30 #size-cells = <2>; 26 #size-cells = <2>;
31 27
32 aliases { 28 aliases {
33 i2c0 = &i2c0; 29 i2c0 = &i2c0;
34 i2c1 = &i2c1; 30 i2c1 = &i2c1;
35 i2c2 = &i2c2; 31 i2c2 = &i2c2;
36 i2c3 = &i2c3; 32 i2c3 = &i2c3;
37 i2c4 = &i2c4; 33 i2c4 = &i2c4;
38 i2c5 = &i2c5; 34 i2c5 = &i2c5;
39 i2c6 = &i2c6; 35 i2c6 = &i2c6;
40 i2c7 = &i2c7; 36 i2c7 = &i2c7;
41 i2c8 = &i2c8; 37 i2c8 = &i2c8;
42 i2c9 = &i2c9; 38 i2c9 = &i2c9;
43 i2c10 = &i2c10; 39 i2c10 = &i2c10;
44 i2c11 = &i2c11; 40 i2c11 = &i2c11;
45 i2c12 = &i2c12; 41 i2c12 = &i2c12;
46 i2c13 = &i2c13; 42 i2c13 = &i2c13;
47 i2c14 = &i2c14; 43 i2c14 = &i2c14;
48 i2c15 = &i2c15; 44 i2c15 = &i2c15;
49 i2c16 = &i2c16; 45 i2c16 = &i2c16;
50 i2c17 = &i2c17; 46 i2c17 = &i2c17;
51 i2c18 = &i2c18; 47 i2c18 = &i2c18;
52 i2c19 = &i2c19; 48 i2c19 = &i2c19;
53 spi0 = &spi0; 49 spi0 = &spi0;
54 spi1 = &spi1; 50 spi1 = &spi1;
55 spi2 = &spi2; 51 spi2 = &spi2;
56 spi3 = &spi3; 52 spi3 = &spi3;
57 spi4 = &spi4; 53 spi4 = &spi4;
58 spi5 = &spi5; 54 spi5 = &spi5;
59 spi6 = &spi6; 55 spi6 = &spi6;
60 spi7 = &spi7; 56 spi7 = &spi7;
61 spi8 = &spi8; 57 spi8 = &spi8;
62 spi9 = &spi9; 58 spi9 = &spi9;
63 spi10 = &spi10; 59 spi10 = &spi10;
64 spi11 = &spi11; 60 spi11 = &spi11;
65 spi12 = &spi12; 61 spi12 = &spi12;
66 spi13 = &spi13; 62 spi13 = &spi13;
67 spi14 = &spi14; 63 spi14 = &spi14;
68 spi15 = &spi15; 64 spi15 = &spi15;
69 spi16 = &spi16; 65 spi16 = &spi16;
70 spi17 = &spi17; 66 spi17 = &spi17;
71 spi18 = &spi18; 67 spi18 = &spi18;
72 spi19 = &spi19; 68 spi19 = &spi19;
73 }; 69 };
74 70
75 chosen { }; 71 chosen { };
76 72
77 clocks { 73 clocks {
78 xo_board: xo-board { 74 xo_board: xo-board {
79 compatible = "fixed-cl 75 compatible = "fixed-clock";
80 #clock-cells = <0>; 76 #clock-cells = <0>;
81 clock-frequency = <384 77 clock-frequency = <38400000>;
82 clock-output-names = " 78 clock-output-names = "xo_board";
83 }; 79 };
84 80
85 sleep_clk: sleep-clk { 81 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 82 compatible = "fixed-clock";
87 clock-frequency = <327 83 clock-frequency = <32768>;
88 #clock-cells = <0>; 84 #clock-cells = <0>;
89 }; 85 };
90 }; 86 };
91 87
92 cpus { 88 cpus {
93 #address-cells = <2>; 89 #address-cells = <2>;
94 #size-cells = <0>; 90 #size-cells = <0>;
95 91
96 CPU0: cpu@0 { 92 CPU0: cpu@0 {
97 device_type = "cpu"; 93 device_type = "cpu";
98 compatible = "qcom,kry 94 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 95 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 96 enable-method = "psci";
102 capacity-dmips-mhz = < 97 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 98 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 99 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ <<
106 power-domain-names = " <<
107 qcom,freq-domain = <&c 100 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <<
109 interconnects = <&gem_ <<
110 <&epss <<
111 #cooling-cells = <2>; 101 #cooling-cells = <2>;
112 L2_0: l2-cache { 102 L2_0: l2-cache {
113 compatible = " 103 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 104 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 105 L3_0: l3-cache {
119 compat 106 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 107 };
124 }; 108 };
125 }; 109 };
126 110
127 CPU1: cpu@100 { 111 CPU1: cpu@100 {
128 device_type = "cpu"; 112 device_type = "cpu";
129 compatible = "qcom,kry 113 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 114 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 115 enable-method = "psci";
133 capacity-dmips-mhz = < 116 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 117 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 118 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ <<
137 power-domain-names = " <<
138 qcom,freq-domain = <&c 119 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <<
140 interconnects = <&gem_ <<
141 <&epss <<
142 #cooling-cells = <2>; 120 #cooling-cells = <2>;
143 L2_100: l2-cache { 121 L2_100: l2-cache {
144 compatible = " 122 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 123 next-level-cache = <&L3_0>;
149 }; 124 };
150 }; 125 };
151 126
152 CPU2: cpu@200 { 127 CPU2: cpu@200 {
153 device_type = "cpu"; 128 device_type = "cpu";
154 compatible = "qcom,kry 129 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 130 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 131 enable-method = "psci";
158 capacity-dmips-mhz = < 132 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 133 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 134 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ <<
162 power-domain-names = " <<
163 qcom,freq-domain = <&c 135 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <<
165 interconnects = <&gem_ <<
166 <&epss <<
167 #cooling-cells = <2>; 136 #cooling-cells = <2>;
168 L2_200: l2-cache { 137 L2_200: l2-cache {
169 compatible = " 138 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 139 next-level-cache = <&L3_0>;
174 }; 140 };
175 }; 141 };
176 142
177 CPU3: cpu@300 { 143 CPU3: cpu@300 {
178 device_type = "cpu"; 144 device_type = "cpu";
179 compatible = "qcom,kry 145 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 146 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 147 enable-method = "psci";
183 capacity-dmips-mhz = < 148 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 149 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 150 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ <<
187 power-domain-names = " <<
188 qcom,freq-domain = <&c 151 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <<
190 interconnects = <&gem_ <<
191 <&epss <<
192 #cooling-cells = <2>; 152 #cooling-cells = <2>;
193 L2_300: l2-cache { 153 L2_300: l2-cache {
194 compatible = " 154 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 155 next-level-cache = <&L3_0>;
199 }; 156 };
200 }; 157 };
201 158
202 CPU4: cpu@400 { 159 CPU4: cpu@400 {
203 device_type = "cpu"; 160 device_type = "cpu";
204 compatible = "qcom,kry 161 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 162 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 163 enable-method = "psci";
208 capacity-dmips-mhz = < 164 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 165 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 166 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ <<
212 power-domain-names = " <<
213 qcom,freq-domain = <&c 167 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <<
215 interconnects = <&gem_ <<
216 <&epss <<
217 #cooling-cells = <2>; 168 #cooling-cells = <2>;
218 L2_400: l2-cache { 169 L2_400: l2-cache {
219 compatible = " 170 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 171 next-level-cache = <&L3_0>;
224 }; 172 };
225 }; 173 };
226 174
227 CPU5: cpu@500 { 175 CPU5: cpu@500 {
228 device_type = "cpu"; 176 device_type = "cpu";
229 compatible = "qcom,kry 177 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 178 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 179 enable-method = "psci";
233 capacity-dmips-mhz = < 180 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 181 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 182 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ <<
237 power-domain-names = " <<
238 qcom,freq-domain = <&c 183 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <<
240 interconnects = <&gem_ <<
241 <&epss <<
242 #cooling-cells = <2>; 184 #cooling-cells = <2>;
243 L2_500: l2-cache { 185 L2_500: l2-cache {
244 compatible = " 186 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 187 next-level-cache = <&L3_0>;
249 }; 188 };
>> 189
250 }; 190 };
251 191
252 CPU6: cpu@600 { 192 CPU6: cpu@600 {
253 device_type = "cpu"; 193 device_type = "cpu";
254 compatible = "qcom,kry 194 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 195 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 196 enable-method = "psci";
258 capacity-dmips-mhz = < 197 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 198 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 199 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ <<
262 power-domain-names = " <<
263 qcom,freq-domain = <&c 200 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <<
265 interconnects = <&gem_ <<
266 <&epss <<
267 #cooling-cells = <2>; 201 #cooling-cells = <2>;
268 L2_600: l2-cache { 202 L2_600: l2-cache {
269 compatible = " 203 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 204 next-level-cache = <&L3_0>;
274 }; 205 };
275 }; 206 };
276 207
277 CPU7: cpu@700 { 208 CPU7: cpu@700 {
278 device_type = "cpu"; 209 device_type = "cpu";
279 compatible = "qcom,kry 210 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 211 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 212 enable-method = "psci";
283 capacity-dmips-mhz = < 213 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 214 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 215 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ <<
287 power-domain-names = " <<
288 qcom,freq-domain = <&c 216 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <<
290 interconnects = <&gem_ <<
291 <&epss <<
292 #cooling-cells = <2>; 217 #cooling-cells = <2>;
293 L2_700: l2-cache { 218 L2_700: l2-cache {
294 compatible = " 219 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 220 next-level-cache = <&L3_0>;
299 }; 221 };
300 }; 222 };
301 223
302 cpu-map { 224 cpu-map {
303 cluster0 { 225 cluster0 {
304 core0 { 226 core0 {
305 cpu = 227 cpu = <&CPU0>;
306 }; 228 };
307 229
308 core1 { 230 core1 {
309 cpu = 231 cpu = <&CPU1>;
310 }; 232 };
311 233
312 core2 { 234 core2 {
313 cpu = 235 cpu = <&CPU2>;
314 }; 236 };
315 237
316 core3 { 238 core3 {
317 cpu = 239 cpu = <&CPU3>;
318 }; 240 };
319 241
320 core4 { 242 core4 {
321 cpu = 243 cpu = <&CPU4>;
322 }; 244 };
323 245
324 core5 { 246 core5 {
325 cpu = 247 cpu = <&CPU5>;
326 }; 248 };
327 249
328 core6 { 250 core6 {
329 cpu = 251 cpu = <&CPU6>;
330 }; 252 };
331 253
332 core7 { 254 core7 {
333 cpu = 255 cpu = <&CPU7>;
334 }; 256 };
335 }; 257 };
336 }; 258 };
337 <<
338 idle-states { <<
339 entry-method = "psci"; <<
340 <<
341 LITTLE_CPU_SLEEP_0: cp <<
342 compatible = " <<
343 idle-state-nam <<
344 arm,psci-suspe <<
345 entry-latency- <<
346 exit-latency-u <<
347 min-residency- <<
348 local-timer-st <<
349 }; <<
350 <<
351 BIG_CPU_SLEEP_0: cpu-s <<
352 compatible = " <<
353 idle-state-nam <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 local-timer-st <<
359 }; <<
360 }; <<
361 <<
362 domain-idle-states { <<
363 CLUSTER_SLEEP_0: clust <<
364 compatible = " <<
365 arm,psci-suspe <<
366 entry-latency- <<
367 exit-latency-u <<
368 min-residency- <<
369 }; <<
370 }; <<
371 }; <<
372 <<
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points <<
381 opp-shared; <<
382 <<
383 cpu0_opp1: opp-300000000 { <<
384 opp-hz = /bits/ 64 <30 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp2: opp-403200000 { <<
389 opp-hz = /bits/ 64 <40 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp3: opp-518400000 { <<
394 opp-hz = /bits/ 64 <51 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp4: opp-614400000 { <<
399 opp-hz = /bits/ 64 <61 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp5: opp-691200000 { <<
404 opp-hz = /bits/ 64 <69 <<
405 opp-peak-kBps = <80000 <<
406 }; <<
407 <<
408 cpu0_opp6: opp-787200000 { <<
409 opp-hz = /bits/ 64 <78 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp7: opp-883200000 { <<
414 opp-hz = /bits/ 64 <88 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp8: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp9: opp-1075200000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp10: opp-1171200000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <18040 <<
431 }; <<
432 <<
433 cpu0_opp11: opp-1248000000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <18040 <<
436 }; <<
437 <<
438 cpu0_opp12: opp-1344000000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp13: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <21880 <<
446 }; <<
447 <<
448 cpu0_opp14: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp15: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <30720 <<
456 }; <<
457 <<
458 cpu0_opp16: opp-1708800000 { <<
459 opp-hz = /bits/ 64 <17 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp17: opp-1804800000 { <<
464 opp-hz = /bits/ 64 <18 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-710400000 { <<
474 opp-hz = /bits/ 64 <71 <<
475 opp-peak-kBps = <18040 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-825600000 { <<
479 opp-hz = /bits/ 64 <82 <<
480 opp-peak-kBps = <21880 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-940800000 { <<
484 opp-hz = /bits/ 64 <94 <<
485 opp-peak-kBps = <21880 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-1056000000 { <<
489 opp-hz = /bits/ 64 <10 <<
490 opp-peak-kBps = <30720 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-1171200000 { <<
494 opp-hz = /bits/ 64 <11 <<
495 opp-peak-kBps = <30720 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-1286400000 { <<
499 opp-hz = /bits/ 64 <12 <<
500 opp-peak-kBps = <40680 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-1382400000 { <<
504 opp-hz = /bits/ 64 <13 <<
505 opp-peak-kBps = <40680 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-1478400000 { <<
509 opp-hz = /bits/ 64 <14 <<
510 opp-peak-kBps = <40680 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-1574400000 { <<
514 opp-hz = /bits/ 64 <15 <<
515 opp-peak-kBps = <54120 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1670400000 { <<
519 opp-hz = /bits/ 64 <16 <<
520 opp-peak-kBps = <54120 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1766400000 { <<
524 opp-hz = /bits/ 64 <17 <<
525 opp-peak-kBps = <54120 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1862400000 { <<
529 opp-hz = /bits/ 64 <18 <<
530 opp-peak-kBps = <62200 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1958400000 { <<
534 opp-hz = /bits/ 64 <19 <<
535 opp-peak-kBps = <62200 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-2054400000 { <<
539 opp-hz = /bits/ 64 <20 <<
540 opp-peak-kBps = <72160 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-2150400000 { <<
544 opp-hz = /bits/ 64 <21 <<
545 opp-peak-kBps = <72160 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-2246400000 { <<
549 opp-hz = /bits/ 64 <22 <<
550 opp-peak-kBps = <72160 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-2342400000 { <<
554 opp-hz = /bits/ 64 <23 <<
555 opp-peak-kBps = <83680 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-2419200000 { <<
559 opp-hz = /bits/ 64 <24 <<
560 opp-peak-kBps = <83680 <<
561 }; <<
562 }; <<
563 <<
564 cpu7_opp_table: opp-table-cpu7 { <<
565 compatible = "operating-points <<
566 opp-shared; <<
567 <<
568 cpu7_opp1: opp-844800000 { <<
569 opp-hz = /bits/ 64 <84 <<
570 opp-peak-kBps = <21880 <<
571 }; <<
572 <<
573 cpu7_opp2: opp-960000000 { <<
574 opp-hz = /bits/ 64 <96 <<
575 opp-peak-kBps = <21880 <<
576 }; <<
577 <<
578 cpu7_opp3: opp-1075200000 { <<
579 opp-hz = /bits/ 64 <10 <<
580 opp-peak-kBps = <30720 <<
581 }; <<
582 <<
583 cpu7_opp4: opp-1190400000 { <<
584 opp-hz = /bits/ 64 <11 <<
585 opp-peak-kBps = <30720 <<
586 }; <<
587 <<
588 cpu7_opp5: opp-1305600000 { <<
589 opp-hz = /bits/ 64 <13 <<
590 opp-peak-kBps = <40680 <<
591 }; <<
592 <<
593 cpu7_opp6: opp-1401600000 { <<
594 opp-hz = /bits/ 64 <14 <<
595 opp-peak-kBps = <40680 <<
596 }; <<
597 <<
598 cpu7_opp7: opp-1516800000 { <<
599 opp-hz = /bits/ 64 <15 <<
600 opp-peak-kBps = <40680 <<
601 }; <<
602 <<
603 cpu7_opp8: opp-1632000000 { <<
604 opp-hz = /bits/ 64 <16 <<
605 opp-peak-kBps = <54120 <<
606 }; <<
607 <<
608 cpu7_opp9: opp-1747200000 { <<
609 opp-hz = /bits/ 64 <17 <<
610 opp-peak-kBps = <54120 <<
611 }; <<
612 <<
613 cpu7_opp10: opp-1862400000 { <<
614 opp-hz = /bits/ 64 <18 <<
615 opp-peak-kBps = <62200 <<
616 }; <<
617 <<
618 cpu7_opp11: opp-1977600000 { <<
619 opp-hz = /bits/ 64 <19 <<
620 opp-peak-kBps = <62200 <<
621 }; <<
622 <<
623 cpu7_opp12: opp-2073600000 { <<
624 opp-hz = /bits/ 64 <20 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu7_opp13: opp-2169600000 { <<
629 opp-hz = /bits/ 64 <21 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 <<
633 cpu7_opp14: opp-2265600000 { <<
634 opp-hz = /bits/ 64 <22 <<
635 opp-peak-kBps = <72160 <<
636 }; <<
637 <<
638 cpu7_opp15: opp-2361600000 { <<
639 opp-hz = /bits/ 64 <23 <<
640 opp-peak-kBps = <83680 <<
641 }; <<
642 <<
643 cpu7_opp16: opp-2457600000 { <<
644 opp-hz = /bits/ 64 <24 <<
645 opp-peak-kBps = <83680 <<
646 }; <<
647 <<
648 cpu7_opp17: opp-2553600000 { <<
649 opp-hz = /bits/ 64 <25 <<
650 opp-peak-kBps = <83680 <<
651 }; <<
652 <<
653 cpu7_opp18: opp-2649600000 { <<
654 opp-hz = /bits/ 64 <26 <<
655 opp-peak-kBps = <83680 <<
656 }; <<
657 <<
658 cpu7_opp19: opp-2745600000 { <<
659 opp-hz = /bits/ 64 <27 <<
660 opp-peak-kBps = <83680 <<
661 }; <<
662 <<
663 cpu7_opp20: opp-2841600000 { <<
664 opp-hz = /bits/ 64 <28 <<
665 opp-peak-kBps = <83680 <<
666 }; <<
667 }; 259 };
668 260
669 firmware { 261 firmware {
670 scm: scm { 262 scm: scm {
671 compatible = "qcom,scm !! 263 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 264 #reset-cells = <1>;
674 }; 265 };
675 }; 266 };
676 267
677 memory@80000000 { 268 memory@80000000 {
678 device_type = "memory"; 269 device_type = "memory";
679 /* We expect the bootloader to 270 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 271 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 272 };
682 273
>> 274 mmcx_reg: mmcx-reg {
>> 275 compatible = "regulator-fixed-domain";
>> 276 power-domains = <&rpmhpd SM8250_MMCX>;
>> 277 required-opps = <&rpmhpd_opp_low_svs>;
>> 278 regulator-name = "MMCX";
>> 279 };
>> 280
683 pmu { 281 pmu {
684 compatible = "arm,armv8-pmuv3" 282 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 283 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 284 };
687 285
688 psci { 286 psci {
689 compatible = "arm,psci-1.0"; 287 compatible = "arm,psci-1.0";
690 method = "smc"; 288 method = "smc";
691 <<
692 CPU_PD0: power-domain-cpu0 { <<
693 #power-domain-cells = <<
694 power-domains = <&CLUS <<
695 domain-idle-states = < <<
696 }; <<
697 <<
698 CPU_PD1: power-domain-cpu1 { <<
699 #power-domain-cells = <<
700 power-domains = <&CLUS <<
701 domain-idle-states = < <<
702 }; <<
703 <<
704 CPU_PD2: power-domain-cpu2 { <<
705 #power-domain-cells = <<
706 power-domains = <&CLUS <<
707 domain-idle-states = < <<
708 }; <<
709 <<
710 CPU_PD3: power-domain-cpu3 { <<
711 #power-domain-cells = <<
712 power-domains = <&CLUS <<
713 domain-idle-states = < <<
714 }; <<
715 <<
716 CPU_PD4: power-domain-cpu4 { <<
717 #power-domain-cells = <<
718 power-domains = <&CLUS <<
719 domain-idle-states = < <<
720 }; <<
721 <<
722 CPU_PD5: power-domain-cpu5 { <<
723 #power-domain-cells = <<
724 power-domains = <&CLUS <<
725 domain-idle-states = < <<
726 }; <<
727 <<
728 CPU_PD6: power-domain-cpu6 { <<
729 #power-domain-cells = <<
730 power-domains = <&CLUS <<
731 domain-idle-states = < <<
732 }; <<
733 <<
734 CPU_PD7: power-domain-cpu7 { <<
735 #power-domain-cells = <<
736 power-domains = <&CLUS <<
737 domain-idle-states = < <<
738 }; <<
739 <<
740 CLUSTER_PD: power-domain-cpu-c <<
741 #power-domain-cells = <<
742 domain-idle-states = < <<
743 }; <<
744 }; <<
745 <<
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; 289 };
764 290
765 reserved-memory { 291 reserved-memory {
766 #address-cells = <2>; 292 #address-cells = <2>;
767 #size-cells = <2>; 293 #size-cells = <2>;
768 ranges; 294 ranges;
769 295
770 hyp_mem: memory@80000000 { 296 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 297 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 298 no-map;
773 }; 299 };
774 300
775 xbl_aop_mem: memory@80700000 { 301 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 302 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 303 no-map;
778 }; 304 };
779 305
780 cmd_db: memory@80860000 { 306 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 307 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 308 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 309 no-map;
784 }; 310 };
785 311
786 smem_mem: memory@80900000 { 312 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 313 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 314 no-map;
789 }; 315 };
790 316
791 removed_mem: memory@80b00000 { 317 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 318 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 319 no-map;
794 }; 320 };
795 321
796 camera_mem: memory@86200000 { 322 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 323 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 324 no-map;
799 }; 325 };
800 326
801 wlan_mem: memory@86700000 { 327 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 328 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 329 no-map;
804 }; 330 };
805 331
806 ipa_fw_mem: memory@86800000 { 332 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 333 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 334 no-map;
809 }; 335 };
810 336
811 ipa_gsi_mem: memory@86810000 { 337 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 338 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 339 no-map;
814 }; 340 };
815 341
816 gpu_mem: memory@8681a000 { 342 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 343 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 344 no-map;
819 }; 345 };
820 346
821 npu_mem: memory@86900000 { 347 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 348 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 349 no-map;
824 }; 350 };
825 351
826 video_mem: memory@86e00000 { 352 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 353 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 354 no-map;
829 }; 355 };
830 356
831 cvp_mem: memory@87300000 { 357 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 358 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 359 no-map;
834 }; 360 };
835 361
836 cdsp_mem: memory@87800000 { 362 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 363 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 364 no-map;
839 }; 365 };
840 366
841 slpi_mem: memory@88c00000 { 367 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 368 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 369 no-map;
844 }; 370 };
845 371
846 adsp_mem: memory@8a100000 { 372 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 373 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 374 no-map;
849 }; 375 };
850 376
851 spss_mem: memory@8be00000 { 377 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 378 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 379 no-map;
854 }; 380 };
855 381
856 cdsp_secure_heap: memory@8bf00 382 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 383 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 384 no-map;
859 }; 385 };
860 }; 386 };
861 387
862 smem { 388 smem {
863 compatible = "qcom,smem"; 389 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 390 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 391 hwlocks = <&tcsr_mutex 3>;
866 }; 392 };
867 393
868 smp2p-adsp { 394 smp2p-adsp {
869 compatible = "qcom,smp2p"; 395 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 396 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 397 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 398 IPCC_MPROC_SIGNAL_SMP2P
873 I 399 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 400 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 401 IPCC_MPROC_SIGNAL_SMP2P>;
876 402
877 qcom,local-pid = <0>; 403 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 404 qcom,remote-pid = <2>;
879 405
880 smp2p_adsp_out: master-kernel 406 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 407 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 408 #qcom,smem-state-cells = <1>;
883 }; 409 };
884 410
885 smp2p_adsp_in: slave-kernel { 411 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 412 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 413 interrupt-controller;
888 #interrupt-cells = <2> 414 #interrupt-cells = <2>;
889 }; 415 };
890 }; 416 };
891 417
892 smp2p-cdsp { 418 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 419 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 420 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 421 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 422 IPCC_MPROC_SIGNAL_SMP2P
897 I 423 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 424 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 425 IPCC_MPROC_SIGNAL_SMP2P>;
900 426
901 qcom,local-pid = <0>; 427 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 428 qcom,remote-pid = <5>;
903 429
904 smp2p_cdsp_out: master-kernel 430 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 431 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 432 #qcom,smem-state-cells = <1>;
907 }; 433 };
908 434
909 smp2p_cdsp_in: slave-kernel { 435 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 436 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 437 interrupt-controller;
912 #interrupt-cells = <2> 438 #interrupt-cells = <2>;
913 }; 439 };
914 }; 440 };
915 441
916 smp2p-slpi { 442 smp2p-slpi {
917 compatible = "qcom,smp2p"; 443 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 444 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 445 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 446 IPCC_MPROC_SIGNAL_SMP2P
921 I 447 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 448 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 449 IPCC_MPROC_SIGNAL_SMP2P>;
924 450
925 qcom,local-pid = <0>; 451 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 452 qcom,remote-pid = <3>;
927 453
928 smp2p_slpi_out: master-kernel 454 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 455 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 456 #qcom,smem-state-cells = <1>;
931 }; 457 };
932 458
933 smp2p_slpi_in: slave-kernel { 459 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 460 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 461 interrupt-controller;
936 #interrupt-cells = <2> 462 #interrupt-cells = <2>;
937 }; 463 };
938 }; 464 };
939 465
940 soc: soc@0 { 466 soc: soc@0 {
941 #address-cells = <2>; 467 #address-cells = <2>;
942 #size-cells = <2>; 468 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 469 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 470 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 471 compatible = "simple-bus";
946 472
947 gcc: clock-controller@100000 { 473 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 474 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 475 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 476 #clock-cells = <1>;
951 #reset-cells = <1>; 477 #reset-cells = <1>;
952 #power-domain-cells = 478 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 479 clock-names = "bi_tcxo",
954 "bi_tcxo 480 "bi_tcxo_ao",
955 "sleep_c 481 "sleep_clk";
956 clocks = <&rpmhcc RPMH 482 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 483 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 484 <&sleep_clk>;
959 }; 485 };
960 486
961 ipcc: mailbox@408000 { 487 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 488 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 489 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 490 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 491 interrupt-controller;
966 #interrupt-cells = <3> 492 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 493 #mbox-cells = <2>;
968 }; 494 };
969 495
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 496 rng: rng@793000 {
983 compatible = "qcom,prn 497 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 498 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 499 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 500 clock-names = "core";
987 }; 501 };
988 502
989 gpi_dma2: dma-controller@80000 !! 503 qup_opp_table: qup-opp-table {
990 compatible = "qcom,sm8 !! 504 compatible = "operating-points-v2";
991 reg = <0 0x00800000 0 !! 505
992 interrupts = <GIC_SPI !! 506 opp-50000000 {
993 <GIC_SPI !! 507 opp-hz = /bits/ 64 <50000000>;
994 <GIC_SPI !! 508 required-opps = <&rpmhpd_opp_min_svs>;
995 <GIC_SPI !! 509 };
996 <GIC_SPI !! 510
997 <GIC_SPI !! 511 opp-75000000 {
998 <GIC_SPI !! 512 opp-hz = /bits/ 64 <75000000>;
999 <GIC_SPI !! 513 required-opps = <&rpmhpd_opp_low_svs>;
1000 <GIC_SPI !! 514 };
1001 <GIC_SPI !! 515
1002 dma-channels = <10>; !! 516 opp-120000000 {
1003 dma-channel-mask = <0 !! 517 opp-hz = /bits/ 64 <120000000>;
1004 iommus = <&apps_smmu !! 518 required-opps = <&rpmhpd_opp_svs>;
1005 #dma-cells = <3>; !! 519 };
1006 status = "disabled"; <<
1007 }; 520 };
1008 521
1009 qupv3_id_2: geniqup@8c0000 { 522 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 523 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 524 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 525 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 526 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 527 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 528 #address-cells = <2>;
1016 #size-cells = <2>; 529 #size-cells = <2>;
1017 iommus = <&apps_smmu 530 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 531 ranges;
1019 status = "disabled"; 532 status = "disabled";
1020 533
1021 i2c14: i2c@880000 { 534 i2c14: i2c@880000 {
1022 compatible = 535 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 536 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 537 clock-names = "se";
1025 clocks = <&gc 538 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 539 pinctrl-names = "default";
1027 pinctrl-0 = < 540 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 541 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 542 #address-cells = <1>;
1040 #size-cells = 543 #size-cells = <0>;
1041 status = "dis 544 status = "disabled";
1042 }; 545 };
1043 546
1044 spi14: spi@880000 { 547 spi14: spi@880000 {
1045 compatible = 548 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 549 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 550 clock-names = "se";
1048 clocks = <&gc 551 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 552 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ <<
1051 <&gpi_ <<
1052 dma-names = " <<
1053 power-domains <<
1054 operating-poi <<
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 553 #address-cells = <1>;
1062 #size-cells = 554 #size-cells = <0>;
>> 555 power-domains = <&rpmhpd SM8250_CX>;
>> 556 operating-points-v2 = <&qup_opp_table>;
1063 status = "dis 557 status = "disabled";
1064 }; 558 };
1065 559
1066 i2c15: i2c@884000 { 560 i2c15: i2c@884000 {
1067 compatible = 561 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 562 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 563 clock-names = "se";
1070 clocks = <&gc 564 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 565 pinctrl-names = "default";
1072 pinctrl-0 = < 566 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 567 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ <<
1075 <&gpi_ <<
1076 dma-names = " <<
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 568 #address-cells = <1>;
1085 #size-cells = 569 #size-cells = <0>;
1086 status = "dis 570 status = "disabled";
1087 }; 571 };
1088 572
1089 spi15: spi@884000 { 573 spi15: spi@884000 {
1090 compatible = 574 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 575 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 576 clock-names = "se";
1093 clocks = <&gc 577 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 578 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ <<
1096 <&gpi_ <<
1097 dma-names = " <<
1098 power-domains <<
1099 operating-poi <<
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 579 #address-cells = <1>;
1107 #size-cells = 580 #size-cells = <0>;
>> 581 power-domains = <&rpmhpd SM8250_CX>;
>> 582 operating-points-v2 = <&qup_opp_table>;
1108 status = "dis 583 status = "disabled";
1109 }; 584 };
1110 585
1111 i2c16: i2c@888000 { 586 i2c16: i2c@888000 {
1112 compatible = 587 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 588 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 589 clock-names = "se";
1115 clocks = <&gc 590 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 591 pinctrl-names = "default";
1117 pinctrl-0 = < 592 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 593 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ <<
1120 <&gpi_ <<
1121 dma-names = " <<
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 594 #address-cells = <1>;
1130 #size-cells = 595 #size-cells = <0>;
1131 status = "dis 596 status = "disabled";
1132 }; 597 };
1133 598
1134 spi16: spi@888000 { 599 spi16: spi@888000 {
1135 compatible = 600 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 601 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 602 clock-names = "se";
1138 clocks = <&gc 603 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 604 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ <<
1141 <&gpi_ <<
1142 dma-names = " <<
1143 power-domains <<
1144 operating-poi <<
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 605 #address-cells = <1>;
1152 #size-cells = 606 #size-cells = <0>;
>> 607 power-domains = <&rpmhpd SM8250_CX>;
>> 608 operating-points-v2 = <&qup_opp_table>;
1153 status = "dis 609 status = "disabled";
1154 }; 610 };
1155 611
1156 i2c17: i2c@88c000 { 612 i2c17: i2c@88c000 {
1157 compatible = 613 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 614 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 615 clock-names = "se";
1160 clocks = <&gc 616 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 617 pinctrl-names = "default";
1162 pinctrl-0 = < 618 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 619 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ <<
1165 <&gpi_ <<
1166 dma-names = " <<
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 620 #address-cells = <1>;
1175 #size-cells = 621 #size-cells = <0>;
1176 status = "dis 622 status = "disabled";
1177 }; 623 };
1178 624
1179 spi17: spi@88c000 { 625 spi17: spi@88c000 {
1180 compatible = 626 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 627 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 628 clock-names = "se";
1183 clocks = <&gc 629 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 630 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ <<
1186 <&gpi_ <<
1187 dma-names = " <<
1188 power-domains <<
1189 operating-poi <<
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 631 #address-cells = <1>;
1197 #size-cells = 632 #size-cells = <0>;
>> 633 power-domains = <&rpmhpd SM8250_CX>;
>> 634 operating-points-v2 = <&qup_opp_table>;
1198 status = "dis 635 status = "disabled";
1199 }; 636 };
1200 637
1201 uart17: serial@88c000 638 uart17: serial@88c000 {
1202 compatible = 639 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 640 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 641 clock-names = "se";
1205 clocks = <&gc 642 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 643 pinctrl-names = "default";
1207 pinctrl-0 = < 644 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 645 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 646 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 647 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 648 status = "disabled";
1216 }; 649 };
1217 650
1218 i2c18: i2c@890000 { 651 i2c18: i2c@890000 {
1219 compatible = 652 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 653 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 654 clock-names = "se";
1222 clocks = <&gc 655 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 656 pinctrl-names = "default";
1224 pinctrl-0 = < 657 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 658 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ <<
1227 <&gpi_ <<
1228 dma-names = " <<
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 659 #address-cells = <1>;
1237 #size-cells = 660 #size-cells = <0>;
1238 status = "dis 661 status = "disabled";
1239 }; 662 };
1240 663
1241 spi18: spi@890000 { 664 spi18: spi@890000 {
1242 compatible = 665 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 666 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 667 clock-names = "se";
1245 clocks = <&gc 668 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 669 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ <<
1248 <&gpi_ <<
1249 dma-names = " <<
1250 power-domains <<
1251 operating-poi <<
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 670 #address-cells = <1>;
1259 #size-cells = 671 #size-cells = <0>;
>> 672 power-domains = <&rpmhpd SM8250_CX>;
>> 673 operating-points-v2 = <&qup_opp_table>;
1260 status = "dis 674 status = "disabled";
1261 }; 675 };
1262 676
1263 uart18: serial@890000 677 uart18: serial@890000 {
1264 compatible = 678 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 679 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 680 clock-names = "se";
1267 clocks = <&gc 681 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 682 pinctrl-names = "default";
1269 pinctrl-0 = < 683 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 684 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 685 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 686 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 687 status = "disabled";
1278 }; 688 };
1279 689
1280 i2c19: i2c@894000 { 690 i2c19: i2c@894000 {
1281 compatible = 691 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 692 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 693 clock-names = "se";
1284 clocks = <&gc 694 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 695 pinctrl-names = "default";
1286 pinctrl-0 = < 696 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 697 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ <<
1289 <&gpi_ <<
1290 dma-names = " <<
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 698 #address-cells = <1>;
1299 #size-cells = 699 #size-cells = <0>;
1300 status = "dis 700 status = "disabled";
1301 }; 701 };
1302 702
1303 spi19: spi@894000 { 703 spi19: spi@894000 {
1304 compatible = 704 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 705 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 706 clock-names = "se";
1307 clocks = <&gc 707 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 708 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ <<
1310 <&gpi_ <<
1311 dma-names = " <<
1312 power-domains <<
1313 operating-poi <<
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 709 #address-cells = <1>;
1321 #size-cells = 710 #size-cells = <0>;
>> 711 power-domains = <&rpmhpd SM8250_CX>;
>> 712 operating-points-v2 = <&qup_opp_table>;
1322 status = "dis 713 status = "disabled";
1323 }; 714 };
1324 }; 715 };
1325 716
1326 gpi_dma0: dma-controller@9000 <<
1327 compatible = "qcom,sm <<
1328 reg = <0 0x00900000 0 <<
1329 interrupts = <GIC_SPI <<
1330 <GIC_SPI <<
1331 <GIC_SPI <<
1332 <GIC_SPI <<
1333 <GIC_SPI <<
1334 <GIC_SPI <<
1335 <GIC_SPI <<
1336 <GIC_SPI <<
1337 <GIC_SPI <<
1338 <GIC_SPI <<
1339 <GIC_SPI <<
1340 <GIC_SPI <<
1341 <GIC_SPI <<
1342 dma-channels = <15>; <<
1343 dma-channel-mask = <0 <<
1344 iommus = <&apps_smmu <<
1345 #dma-cells = <3>; <<
1346 status = "disabled"; <<
1347 }; <<
1348 <<
1349 qupv3_id_0: geniqup@9c0000 { 717 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 718 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 719 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 720 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 721 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 722 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 723 #address-cells = <2>;
1356 #size-cells = <2>; 724 #size-cells = <2>;
1357 iommus = <&apps_smmu 725 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 726 ranges;
1359 status = "disabled"; 727 status = "disabled";
1360 728
1361 i2c0: i2c@980000 { 729 i2c0: i2c@980000 {
1362 compatible = 730 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 731 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 732 clock-names = "se";
1365 clocks = <&gc 733 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 734 pinctrl-names = "default";
1367 pinctrl-0 = < 735 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 736 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ <<
1370 <&gpi_ <<
1371 dma-names = " <<
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 737 #address-cells = <1>;
1380 #size-cells = 738 #size-cells = <0>;
1381 status = "dis 739 status = "disabled";
1382 }; 740 };
1383 741
1384 spi0: spi@980000 { 742 spi0: spi@980000 {
1385 compatible = 743 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 744 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 745 clock-names = "se";
1388 clocks = <&gc 746 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 747 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ <<
1391 <&gpi_ <<
1392 dma-names = " <<
1393 power-domains <<
1394 operating-poi <<
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 748 #address-cells = <1>;
1402 #size-cells = 749 #size-cells = <0>;
>> 750 power-domains = <&rpmhpd SM8250_CX>;
>> 751 operating-points-v2 = <&qup_opp_table>;
1403 status = "dis 752 status = "disabled";
1404 }; 753 };
1405 754
1406 i2c1: i2c@984000 { 755 i2c1: i2c@984000 {
1407 compatible = 756 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 757 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 758 clock-names = "se";
1410 clocks = <&gc 759 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 760 pinctrl-names = "default";
1412 pinctrl-0 = < 761 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 762 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ <<
1415 <&gpi_ <<
1416 dma-names = " <<
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 763 #address-cells = <1>;
1425 #size-cells = 764 #size-cells = <0>;
1426 status = "dis 765 status = "disabled";
1427 }; 766 };
1428 767
1429 spi1: spi@984000 { 768 spi1: spi@984000 {
1430 compatible = 769 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 770 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 771 clock-names = "se";
1433 clocks = <&gc 772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 773 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ <<
1436 <&gpi_ <<
1437 dma-names = " <<
1438 power-domains <<
1439 operating-poi <<
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 774 #address-cells = <1>;
1447 #size-cells = 775 #size-cells = <0>;
>> 776 power-domains = <&rpmhpd SM8250_CX>;
>> 777 operating-points-v2 = <&qup_opp_table>;
1448 status = "dis 778 status = "disabled";
1449 }; 779 };
1450 780
1451 i2c2: i2c@988000 { 781 i2c2: i2c@988000 {
1452 compatible = 782 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 783 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 784 clock-names = "se";
1455 clocks = <&gc 785 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 786 pinctrl-names = "default";
1457 pinctrl-0 = < 787 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 788 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 789 #address-cells = <1>;
1470 #size-cells = 790 #size-cells = <0>;
1471 status = "dis 791 status = "disabled";
1472 }; 792 };
1473 793
1474 spi2: spi@988000 { 794 spi2: spi@988000 {
1475 compatible = 795 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 796 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 797 clock-names = "se";
1478 clocks = <&gc 798 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 799 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ <<
1481 <&gpi_ <<
1482 dma-names = " <<
1483 power-domains <<
1484 operating-poi <<
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 800 #address-cells = <1>;
1492 #size-cells = 801 #size-cells = <0>;
>> 802 power-domains = <&rpmhpd SM8250_CX>;
>> 803 operating-points-v2 = <&qup_opp_table>;
1493 status = "dis 804 status = "disabled";
1494 }; 805 };
1495 806
1496 uart2: serial@988000 807 uart2: serial@988000 {
1497 compatible = 808 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 809 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 810 clock-names = "se";
1500 clocks = <&gc 811 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 812 pinctrl-names = "default";
1502 pinctrl-0 = < 813 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 814 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 815 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 816 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 817 status = "disabled";
1511 }; 818 };
1512 819
1513 i2c3: i2c@98c000 { 820 i2c3: i2c@98c000 {
1514 compatible = 821 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 822 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 823 clock-names = "se";
1517 clocks = <&gc 824 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 825 pinctrl-names = "default";
1519 pinctrl-0 = < 826 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 827 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ <<
1522 <&gpi_ <<
1523 dma-names = " <<
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 828 #address-cells = <1>;
1532 #size-cells = 829 #size-cells = <0>;
1533 status = "dis 830 status = "disabled";
1534 }; 831 };
1535 832
1536 spi3: spi@98c000 { 833 spi3: spi@98c000 {
1537 compatible = 834 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 835 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 836 clock-names = "se";
1540 clocks = <&gc 837 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 838 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ <<
1543 <&gpi_ <<
1544 dma-names = " <<
1545 power-domains <<
1546 operating-poi <<
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 839 #address-cells = <1>;
1554 #size-cells = 840 #size-cells = <0>;
>> 841 power-domains = <&rpmhpd SM8250_CX>;
>> 842 operating-points-v2 = <&qup_opp_table>;
1555 status = "dis 843 status = "disabled";
1556 }; 844 };
1557 845
1558 i2c4: i2c@990000 { 846 i2c4: i2c@990000 {
1559 compatible = 847 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 848 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 849 clock-names = "se";
1562 clocks = <&gc 850 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 851 pinctrl-names = "default";
1564 pinctrl-0 = < 852 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 853 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ <<
1567 <&gpi_ <<
1568 dma-names = " <<
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 854 #address-cells = <1>;
1577 #size-cells = 855 #size-cells = <0>;
1578 status = "dis 856 status = "disabled";
1579 }; 857 };
1580 858
1581 spi4: spi@990000 { 859 spi4: spi@990000 {
1582 compatible = 860 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 861 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 862 clock-names = "se";
1585 clocks = <&gc 863 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 864 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ <<
1588 <&gpi_ <<
1589 dma-names = " <<
1590 power-domains <<
1591 operating-poi <<
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 865 #address-cells = <1>;
1599 #size-cells = 866 #size-cells = <0>;
>> 867 power-domains = <&rpmhpd SM8250_CX>;
>> 868 operating-points-v2 = <&qup_opp_table>;
1600 status = "dis 869 status = "disabled";
1601 }; 870 };
1602 871
1603 i2c5: i2c@994000 { 872 i2c5: i2c@994000 {
1604 compatible = 873 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 874 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 875 clock-names = "se";
1607 clocks = <&gc 876 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 877 pinctrl-names = "default";
1609 pinctrl-0 = < 878 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 879 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ <<
1612 <&gpi_ <<
1613 dma-names = " <<
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 880 #address-cells = <1>;
1622 #size-cells = 881 #size-cells = <0>;
1623 status = "dis 882 status = "disabled";
1624 }; 883 };
1625 884
1626 spi5: spi@994000 { 885 spi5: spi@994000 {
1627 compatible = 886 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 887 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 888 clock-names = "se";
1630 clocks = <&gc 889 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 890 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 power-domains <<
1636 operating-poi <<
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 891 #address-cells = <1>;
1644 #size-cells = 892 #size-cells = <0>;
>> 893 power-domains = <&rpmhpd SM8250_CX>;
>> 894 operating-points-v2 = <&qup_opp_table>;
1645 status = "dis 895 status = "disabled";
1646 }; 896 };
1647 897
1648 i2c6: i2c@998000 { 898 i2c6: i2c@998000 {
1649 compatible = 899 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 900 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 901 clock-names = "se";
1652 clocks = <&gc 902 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 903 pinctrl-names = "default";
1654 pinctrl-0 = < 904 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 905 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ <<
1657 <&gpi_ <<
1658 dma-names = " <<
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 906 #address-cells = <1>;
1667 #size-cells = 907 #size-cells = <0>;
1668 status = "dis 908 status = "disabled";
1669 }; 909 };
1670 910
1671 spi6: spi@998000 { 911 spi6: spi@998000 {
1672 compatible = 912 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 913 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 914 clock-names = "se";
1675 clocks = <&gc 915 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 916 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ <<
1678 <&gpi_ <<
1679 dma-names = " <<
1680 power-domains <<
1681 operating-poi <<
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 917 #address-cells = <1>;
1689 #size-cells = 918 #size-cells = <0>;
>> 919 power-domains = <&rpmhpd SM8250_CX>;
>> 920 operating-points-v2 = <&qup_opp_table>;
1690 status = "dis 921 status = "disabled";
1691 }; 922 };
1692 923
1693 uart6: serial@998000 924 uart6: serial@998000 {
1694 compatible = 925 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 926 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 927 clock-names = "se";
1697 clocks = <&gc 928 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 929 pinctrl-names = "default";
1699 pinctrl-0 = < 930 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 931 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 932 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 933 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 934 status = "disabled";
1708 }; 935 };
1709 936
1710 i2c7: i2c@99c000 { 937 i2c7: i2c@99c000 {
1711 compatible = 938 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 939 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 940 clock-names = "se";
1714 clocks = <&gc 941 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 942 pinctrl-names = "default";
1716 pinctrl-0 = < 943 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 944 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ <<
1719 <&gpi_ <<
1720 dma-names = " <<
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 945 #address-cells = <1>;
1729 #size-cells = 946 #size-cells = <0>;
1730 status = "dis 947 status = "disabled";
1731 }; 948 };
1732 949
1733 spi7: spi@99c000 { 950 spi7: spi@99c000 {
1734 compatible = 951 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 952 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 953 clock-names = "se";
1737 clocks = <&gc 954 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 955 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ <<
1740 <&gpi_ <<
1741 dma-names = " <<
1742 power-domains <<
1743 operating-poi <<
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 956 #address-cells = <1>;
1751 #size-cells = 957 #size-cells = <0>;
>> 958 power-domains = <&rpmhpd SM8250_CX>;
>> 959 operating-points-v2 = <&qup_opp_table>;
1752 status = "dis 960 status = "disabled";
1753 }; 961 };
1754 }; 962 };
1755 963
1756 gpi_dma1: dma-controller@a000 <<
1757 compatible = "qcom,sm <<
1758 reg = <0 0x00a00000 0 <<
1759 interrupts = <GIC_SPI <<
1760 <GIC_SPI <<
1761 <GIC_SPI <<
1762 <GIC_SPI <<
1763 <GIC_SPI <<
1764 <GIC_SPI <<
1765 <GIC_SPI <<
1766 <GIC_SPI <<
1767 <GIC_SPI <<
1768 <GIC_SPI <<
1769 dma-channels = <10>; <<
1770 dma-channel-mask = <0 <<
1771 iommus = <&apps_smmu <<
1772 #dma-cells = <3>; <<
1773 status = "disabled"; <<
1774 }; <<
1775 <<
1776 qupv3_id_1: geniqup@ac0000 { 964 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 965 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 966 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 967 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 968 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 969 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 970 #address-cells = <2>;
1783 #size-cells = <2>; 971 #size-cells = <2>;
1784 iommus = <&apps_smmu 972 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 973 ranges;
1786 status = "disabled"; 974 status = "disabled";
1787 975
1788 i2c8: i2c@a80000 { 976 i2c8: i2c@a80000 {
1789 compatible = 977 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 978 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 979 clock-names = "se";
1792 clocks = <&gc 980 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 981 pinctrl-names = "default";
1794 pinctrl-0 = < 982 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 983 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ <<
1797 <&gpi_ <<
1798 dma-names = " <<
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 984 #address-cells = <1>;
1807 #size-cells = 985 #size-cells = <0>;
1808 status = "dis 986 status = "disabled";
1809 }; 987 };
1810 988
1811 spi8: spi@a80000 { 989 spi8: spi@a80000 {
1812 compatible = 990 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 991 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 992 clock-names = "se";
1815 clocks = <&gc 993 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 994 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ <<
1818 <&gpi_ <<
1819 dma-names = " <<
1820 power-domains <<
1821 operating-poi <<
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 995 #address-cells = <1>;
1829 #size-cells = 996 #size-cells = <0>;
>> 997 power-domains = <&rpmhpd SM8250_CX>;
>> 998 operating-points-v2 = <&qup_opp_table>;
1830 status = "dis 999 status = "disabled";
1831 }; 1000 };
1832 1001
1833 i2c9: i2c@a84000 { 1002 i2c9: i2c@a84000 {
1834 compatible = 1003 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1004 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1005 clock-names = "se";
1837 clocks = <&gc 1006 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1007 pinctrl-names = "default";
1839 pinctrl-0 = < 1008 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1009 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ <<
1842 <&gpi_ <<
1843 dma-names = " <<
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1010 #address-cells = <1>;
1852 #size-cells = 1011 #size-cells = <0>;
1853 status = "dis 1012 status = "disabled";
1854 }; 1013 };
1855 1014
1856 spi9: spi@a84000 { 1015 spi9: spi@a84000 {
1857 compatible = 1016 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1017 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1018 clock-names = "se";
1860 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1020 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ <<
1863 <&gpi_ <<
1864 dma-names = " <<
1865 power-domains <<
1866 operating-poi <<
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1021 #address-cells = <1>;
1874 #size-cells = 1022 #size-cells = <0>;
>> 1023 power-domains = <&rpmhpd SM8250_CX>;
>> 1024 operating-points-v2 = <&qup_opp_table>;
1875 status = "dis 1025 status = "disabled";
1876 }; 1026 };
1877 1027
1878 i2c10: i2c@a88000 { 1028 i2c10: i2c@a88000 {
1879 compatible = 1029 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1030 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1031 clock-names = "se";
1882 clocks = <&gc 1032 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1033 pinctrl-names = "default";
1884 pinctrl-0 = < 1034 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1035 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ <<
1887 <&gpi_ <<
1888 dma-names = " <<
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1036 #address-cells = <1>;
1897 #size-cells = 1037 #size-cells = <0>;
1898 status = "dis 1038 status = "disabled";
1899 }; 1039 };
1900 1040
1901 spi10: spi@a88000 { 1041 spi10: spi@a88000 {
1902 compatible = 1042 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1043 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1044 clock-names = "se";
1905 clocks = <&gc 1045 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1046 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ <<
1908 <&gpi_ <<
1909 dma-names = " <<
1910 power-domains <<
1911 operating-poi <<
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1047 #address-cells = <1>;
1919 #size-cells = 1048 #size-cells = <0>;
>> 1049 power-domains = <&rpmhpd SM8250_CX>;
>> 1050 operating-points-v2 = <&qup_opp_table>;
1920 status = "dis 1051 status = "disabled";
1921 }; 1052 };
1922 1053
1923 i2c11: i2c@a8c000 { 1054 i2c11: i2c@a8c000 {
1924 compatible = 1055 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1056 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1057 clock-names = "se";
1927 clocks = <&gc 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1059 pinctrl-names = "default";
1929 pinctrl-0 = < 1060 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1061 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ <<
1932 <&gpi_ <<
1933 dma-names = " <<
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1062 #address-cells = <1>;
1942 #size-cells = 1063 #size-cells = <0>;
1943 status = "dis 1064 status = "disabled";
1944 }; 1065 };
1945 1066
1946 spi11: spi@a8c000 { 1067 spi11: spi@a8c000 {
1947 compatible = 1068 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1069 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1070 clock-names = "se";
1950 clocks = <&gc 1071 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1072 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ <<
1953 <&gpi_ <<
1954 dma-names = " <<
1955 power-domains <<
1956 operating-poi <<
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1073 #address-cells = <1>;
1964 #size-cells = 1074 #size-cells = <0>;
>> 1075 power-domains = <&rpmhpd SM8250_CX>;
>> 1076 operating-points-v2 = <&qup_opp_table>;
1965 status = "dis 1077 status = "disabled";
1966 }; 1078 };
1967 1079
1968 i2c12: i2c@a90000 { 1080 i2c12: i2c@a90000 {
1969 compatible = 1081 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1082 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1083 clock-names = "se";
1972 clocks = <&gc 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1085 pinctrl-names = "default";
1974 pinctrl-0 = < 1086 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1087 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ <<
1977 <&gpi_ <<
1978 dma-names = " <<
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1088 #address-cells = <1>;
1987 #size-cells = 1089 #size-cells = <0>;
1988 status = "dis 1090 status = "disabled";
1989 }; 1091 };
1990 1092
1991 spi12: spi@a90000 { 1093 spi12: spi@a90000 {
1992 compatible = 1094 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1095 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1096 clock-names = "se";
1995 clocks = <&gc 1097 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1098 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ <<
1998 <&gpi_ <<
1999 dma-names = " <<
2000 power-domains <<
2001 operating-poi <<
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1099 #address-cells = <1>;
2009 #size-cells = 1100 #size-cells = <0>;
>> 1101 power-domains = <&rpmhpd SM8250_CX>;
>> 1102 operating-points-v2 = <&qup_opp_table>;
2010 status = "dis 1103 status = "disabled";
2011 }; 1104 };
2012 1105
2013 uart12: serial@a90000 1106 uart12: serial@a90000 {
2014 compatible = 1107 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1108 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1109 clock-names = "se";
2017 clocks = <&gc 1110 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1111 pinctrl-names = "default";
2019 pinctrl-0 = < 1112 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1113 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1114 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1115 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1116 status = "disabled";
2028 }; 1117 };
2029 1118
2030 i2c13: i2c@a94000 { 1119 i2c13: i2c@a94000 {
2031 compatible = 1120 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1121 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1122 clock-names = "se";
2034 clocks = <&gc 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1124 pinctrl-names = "default";
2036 pinctrl-0 = < 1125 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1126 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ <<
2039 <&gpi_ <<
2040 dma-names = " <<
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1127 #address-cells = <1>;
2049 #size-cells = 1128 #size-cells = <0>;
2050 status = "dis 1129 status = "disabled";
2051 }; 1130 };
2052 1131
2053 spi13: spi@a94000 { 1132 spi13: spi@a94000 {
2054 compatible = 1133 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1134 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1135 clock-names = "se";
2057 clocks = <&gc 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1137 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ <<
2060 <&gpi_ <<
2061 dma-names = " <<
2062 power-domains <<
2063 operating-poi <<
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1138 #address-cells = <1>;
2071 #size-cells = 1139 #size-cells = <0>;
>> 1140 power-domains = <&rpmhpd SM8250_CX>;
>> 1141 operating-points-v2 = <&qup_opp_table>;
2072 status = "dis 1142 status = "disabled";
2073 }; 1143 };
2074 }; 1144 };
2075 1145
2076 config_noc: interconnect@1500 1146 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1147 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1148 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1149 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1150 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1151 };
2082 1152
2083 system_noc: interconnect@1620 1153 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1154 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1155 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1156 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1157 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1158 };
2089 1159
2090 mc_virt: interconnect@163d000 1160 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1161 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1162 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1163 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1164 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1165 };
2096 1166
2097 aggre1_noc: interconnect@16e0 1167 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1168 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1169 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1170 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1171 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1172 };
2103 1173
2104 aggre2_noc: interconnect@1700 1174 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1175 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1176 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1177 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1178 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1179 };
2110 1180
2111 compute_noc: interconnect@173 1181 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1182 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1183 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1184 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1185 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1186 };
2117 1187
2118 mmss_noc: interconnect@174000 1188 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1189 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1190 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1191 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1192 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1193 };
2124 1194
2125 pcie0: pcie@1c00000 { !! 1195 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1196 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1197 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1198 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1199 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1200 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1201 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1202 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1203 device_type = "pci";
2135 linux,pci-domain = <0 1204 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1205 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1206 num-lanes = <1>;
2138 1207
2139 #address-cells = <3>; 1208 #address-cells = <3>;
2140 #size-cells = <2>; 1209 #size-cells = <2>;
2141 1210
2142 ranges = <0x01000000 !! 1211 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1212 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1213
2145 interrupts = <GIC_SPI !! 1214 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1215 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1216 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1217 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1218 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1219 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1220 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1221 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1222
2168 clocks = <&gcc GCC_PC 1223 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1224 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1225 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1226 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1227 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1228 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1229 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1230 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1231 clock-names = "pipe",
2177 "aux", 1232 "aux",
2178 "cfg", 1233 "cfg",
2179 "bus_ma 1234 "bus_master",
2180 "bus_sl 1235 "bus_slave",
2181 "slave_ 1236 "slave_q2a",
2182 "tbu", 1237 "tbu",
2183 "ddrss_ 1238 "ddrss_sf_tbu";
2184 1239
>> 1240 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1241 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1242 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1243
2188 resets = <&gcc GCC_PC 1244 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1245 reset-names = "pci";
2190 1246
2191 power-domains = <&gcc 1247 power-domains = <&gcc PCIE_0_GDSC>;
2192 1248
2193 phys = <&pcie0_phy>; !! 1249 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1250 phy-names = "pciephy";
2195 1251
2196 perst-gpios = <&tlmm <<
2197 wake-gpios = <&tlmm 8 <<
2198 <<
2199 pinctrl-names = "defa <<
2200 pinctrl-0 = <&pcie0_d <<
2201 dma-coherent; <<
2202 <<
2203 status = "disabled"; 1252 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1253 };
2215 1254
2216 pcie0_phy: phy@1c06000 { 1255 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1256 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1257 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1258 #address-cells = <2>;
>> 1259 #size-cells = <2>;
>> 1260 ranges;
2220 clocks = <&gcc GCC_PC 1261 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1262 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1263 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1264 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1265 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1266
2236 resets = <&gcc GCC_PC 1267 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1268 reset-names = "phy";
2238 1269
2239 assigned-clocks = <&g 1270 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1271 assigned-clock-rates = <100000000>;
2241 1272
2242 status = "disabled"; 1273 status = "disabled";
>> 1274
>> 1275 pcie0_lane: lanes@1c06200 {
>> 1276 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1277 <0 0x1c06400 0 0x200>, /* rx */
>> 1278 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1279 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1280 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1281 clock-names = "pipe0";
>> 1282
>> 1283 #phy-cells = <0>;
>> 1284 clock-output-names = "pcie_0_pipe_clk";
>> 1285 };
2243 }; 1286 };
2244 1287
2245 pcie1: pcie@1c08000 { !! 1288 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1289 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1290 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1291 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1292 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1293 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1294 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1295 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1296 device_type = "pci";
2255 linux,pci-domain = <1 1297 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1298 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1299 num-lanes = <2>;
2258 1300
2259 #address-cells = <3>; 1301 #address-cells = <3>;
2260 #size-cells = <2>; 1302 #size-cells = <2>;
2261 1303
2262 ranges = <0x01000000 !! 1304 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1305 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1306
2265 interrupts = <GIC_SPI !! 1307 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
2266 <GIC_SPI !! 1308 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1309 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1310 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1311 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1312 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1313 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1314 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1315
2288 clocks = <&gcc GCC_PC 1316 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1317 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1318 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1319 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1320 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1321 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1322 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1323 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1324 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1325 clock-names = "pipe",
2298 "aux", 1326 "aux",
2299 "cfg", 1327 "cfg",
2300 "bus_ma 1328 "bus_master",
2301 "bus_sl 1329 "bus_slave",
2302 "slave_ 1330 "slave_q2a",
2303 "ref", 1331 "ref",
2304 "tbu", 1332 "tbu",
2305 "ddrss_ 1333 "ddrss_sf_tbu";
2306 1334
2307 assigned-clocks = <&g 1335 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1336 assigned-clock-rates = <19200000>;
2309 1337
>> 1338 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1339 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1340 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1341
2313 resets = <&gcc GCC_PC 1342 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1343 reset-names = "pci";
2315 1344
2316 power-domains = <&gcc 1345 power-domains = <&gcc PCIE_1_GDSC>;
2317 1346
2318 phys = <&pcie1_phy>; !! 1347 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1348 phy-names = "pciephy";
2320 1349
2321 perst-gpios = <&tlmm <<
2322 wake-gpios = <&tlmm 8 <<
2323 <<
2324 pinctrl-names = "defa <<
2325 pinctrl-0 = <&pcie1_d <<
2326 dma-coherent; <<
2327 <<
2328 status = "disabled"; 1350 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1351 };
2340 1352
2341 pcie1_phy: phy@1c0e000 { 1353 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1354 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1355 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1356 #address-cells = <2>;
>> 1357 #size-cells = <2>;
>> 1358 ranges;
2345 clocks = <&gcc GCC_PC 1359 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1360 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1361 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1362 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1363 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1364
2361 resets = <&gcc GCC_PC 1365 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1366 reset-names = "phy";
2363 1367
2364 assigned-clocks = <&g 1368 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1369 assigned-clock-rates = <100000000>;
2366 1370
2367 status = "disabled"; 1371 status = "disabled";
>> 1372
>> 1373 pcie1_lane: lanes@1c0e200 {
>> 1374 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1375 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1376 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1377 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1378 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1379 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1380 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1381 clock-names = "pipe0";
>> 1382
>> 1383 #phy-cells = <0>;
>> 1384 clock-output-names = "pcie_1_pipe_clk";
>> 1385 };
2368 }; 1386 };
2369 1387
2370 pcie2: pcie@1c10000 { !! 1388 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 1389 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 1390 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 1391 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 1392 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 1393 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 1394 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 1395 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 1396 device_type = "pci";
2380 linux,pci-domain = <2 1397 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 1398 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 1399 num-lanes = <2>;
2383 1400
2384 #address-cells = <3>; 1401 #address-cells = <3>;
2385 #size-cells = <2>; 1402 #size-cells = <2>;
2386 1403
2387 ranges = <0x01000000 !! 1404 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 1405 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 1406
2390 interrupts = <GIC_SPI !! 1407 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
2391 <GIC_SPI !! 1408 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 1409 #interrupt-cells = <1>;
2407 interrupt-map-mask = 1410 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 1411 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 1412 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 1413 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 1414 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 1415
2413 clocks = <&gcc GCC_PC 1416 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 1417 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 1418 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 1419 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 1420 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 1421 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 1422 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 1423 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 1424 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 1425 clock-names = "pipe",
2423 "aux", 1426 "aux",
2424 "cfg", 1427 "cfg",
2425 "bus_ma 1428 "bus_master",
2426 "bus_sl 1429 "bus_slave",
2427 "slave_ 1430 "slave_q2a",
2428 "ref", 1431 "ref",
2429 "tbu", 1432 "tbu",
2430 "ddrss_ 1433 "ddrss_sf_tbu";
2431 1434
2432 assigned-clocks = <&g 1435 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 1436 assigned-clock-rates = <19200000>;
2434 1437
>> 1438 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 1439 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 1440 <0x100 &apps_smmu 0x1d01 0x1>;
2437 1441
2438 resets = <&gcc GCC_PC 1442 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 1443 reset-names = "pci";
2440 1444
2441 power-domains = <&gcc 1445 power-domains = <&gcc PCIE_2_GDSC>;
2442 1446
2443 phys = <&pcie2_phy>; !! 1447 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 1448 phy-names = "pciephy";
2445 1449
2446 perst-gpios = <&tlmm <<
2447 wake-gpios = <&tlmm 8 <<
2448 <<
2449 pinctrl-names = "defa <<
2450 pinctrl-0 = <&pcie2_d <<
2451 dma-coherent; <<
2452 <<
2453 status = "disabled"; 1450 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 1451 };
2465 1452
2466 pcie2_phy: phy@1c16000 { 1453 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 1454 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 1455 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 1456 #address-cells = <2>;
>> 1457 #size-cells = <2>;
>> 1458 ranges;
2470 clocks = <&gcc GCC_PC 1459 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 1460 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 1461 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 1462 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 1463 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 1464
2486 resets = <&gcc GCC_PC 1465 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 1466 reset-names = "phy";
2488 1467
2489 assigned-clocks = <&g 1468 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 1469 assigned-clock-rates = <100000000>;
2491 1470
2492 status = "disabled"; 1471 status = "disabled";
>> 1472
>> 1473 pcie2_lane: lanes@1c16200 {
>> 1474 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 1475 <0 0x1c16400 0 0x200>, /* rx0 */
>> 1476 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 1477 <0 0x1c16600 0 0x170>, /* tx1 */
>> 1478 <0 0x1c16800 0 0x200>, /* rx1 */
>> 1479 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1480 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 1481 clock-names = "pipe0";
>> 1482
>> 1483 #phy-cells = <0>;
>> 1484 clock-output-names = "pcie_2_pipe_clk";
>> 1485 };
2493 }; 1486 };
2494 1487
2495 ufs_mem_hc: ufshc@1d84000 { 1488 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 1489 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 1490 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 1491 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 1492 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 1493 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 1494 phy-names = "ufsphy";
2502 lanes-per-direction = 1495 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 1496 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 1497 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 1498 reset-names = "rst";
2506 1499
2507 power-domains = <&gcc 1500 power-domains = <&gcc UFS_PHY_GDSC>;
2508 1501
2509 iommus = <&apps_smmu 1502 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 1503
2511 clock-names = 1504 clock-names =
2512 "core_clk", 1505 "core_clk",
2513 "bus_aggr_clk 1506 "bus_aggr_clk",
2514 "iface_clk", 1507 "iface_clk",
2515 "core_clk_uni 1508 "core_clk_unipro",
2516 "ref_clk", 1509 "ref_clk",
2517 "tx_lane0_syn 1510 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 1511 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 1512 "rx_lane1_sync_clk";
2520 clocks = 1513 clocks =
2521 <&gcc GCC_UFS 1514 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 1515 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 1516 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 1517 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 1518 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 1519 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 1520 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 1521 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 1522 freq-table-hz =
2530 operating-points-v2 = !! 1523 <37500000 300000000>,
2531 !! 1524 <0 0>,
2532 interconnects = <&agg !! 1525 <0 0>,
2533 <&gem !! 1526 <37500000 300000000>,
2534 interconnect-names = !! 1527 <0 0>,
>> 1528 <0 0>,
>> 1529 <0 0>,
>> 1530 <0 0>;
2535 1531
2536 status = "disabled"; 1532 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 1533 };
2566 1534
2567 ufs_mem_phy: phy@1d87000 { 1535 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 1536 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 1537 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 1538 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 1539 #size-cells = <2>;
2572 <&gcc GCC_UF !! 1540 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 1541 clock-names = "ref",
2575 "ref_au !! 1542 "ref_aux";
2576 "qref"; !! 1543 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 1544 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 1545
2578 resets = <&ufs_mem_hc 1546 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 1547 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 1548 status = "disabled";
>> 1549
>> 1550 ufs_mem_phy_lanes: lanes@1d87400 {
>> 1551 reg = <0 0x01d87400 0 0x108>,
>> 1552 <0 0x01d87600 0 0x1e0>,
>> 1553 <0 0x01d87c00 0 0x1dc>,
>> 1554 <0 0x01d87800 0 0x108>,
>> 1555 <0 0x01d87a00 0 0x1e0>;
>> 1556 #phy-cells = <0>;
>> 1557 };
2586 }; 1558 };
2587 1559
2588 cryptobam: dma-controller@1dc !! 1560 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 1561 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 1562 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 1563 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 1564 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 1565 };
2619 1566
2620 tcsr_mutex: hwlock@1f40000 { 1567 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 1568 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 1569 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 1570 #hwlock-cells = <1>;
2624 }; 1571 };
2625 1572
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 1573 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 1574 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 1575 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 1576 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 1577 <&audiocc 0>,
2636 <&q6afecc LP 1578 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 1579 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1580 <&aoncc 0>,
2638 <&vamacro>; 1581 <&vamacro>;
2639 1582
2640 clock-names = "mclk", !! 1583 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 1584
2642 #clock-cells = <0>; 1585 #clock-cells = <0>;
>> 1586 clock-frequency = <9600000>;
2643 clock-output-names = 1587 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 1588 #sound-dai-cells = <1>;
2645 1589
2646 pinctrl-names = "defa 1590 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 1591 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 1592 };
2651 1593
2652 swr0: soundwire@3250000 { !! 1594 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 1595 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 1596 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 1597 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 1598 clocks = <&wsamacro>;
2657 clock-names = "iface" 1599 clock-names = "iface";
2658 1600
2659 qcom,din-ports = <2>; 1601 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 1602 qcom,dout-ports = <6>;
2661 1603
2662 qcom,ports-sinterval- 1604 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 1605 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 1606 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 1607 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 1608
2667 #sound-dai-cells = <1 1609 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 1610 #address-cells = <2>;
2669 #size-cells = <0>; 1611 #size-cells = <0>;
>> 1612 };
2670 1613
2671 status = "disabled"; !! 1614 audiocc: clock-controller@3300000 {
>> 1615 compatible = "qcom,sm8250-lpass-audiocc";
>> 1616 reg = <0 0x03300000 0 0x30000>;
>> 1617 #clock-cells = <1>;
>> 1618 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1619 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1620 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 1621 clock-names = "core", "audio", "bus";
2672 }; 1622 };
2673 1623
2674 vamacro: codec@3370000 { 1624 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 1625 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 1626 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 1627 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 1628 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 1629 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 1630
2681 clock-names = "mclk", 1631 clock-names = "mclk", "macro", "dcodec";
2682 1632
2683 #clock-cells = <0>; 1633 #clock-cells = <0>;
>> 1634 clock-frequency = <9600000>;
2684 clock-output-names = 1635 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 1636 #sound-dai-cells = <1>;
2686 }; 1637 };
2687 1638
2688 rxmacro: rxmacro@3200000 { !! 1639 aoncc: clock-controller@3380000 {
2689 pinctrl-names = "defa !! 1640 compatible = "qcom,sm8250-lpass-aoncc";
2690 pinctrl-0 = <&rx_swr_ !! 1641 reg = <0 0x03380000 0 0x40000>;
2691 compatible = "qcom,sm !! 1642 #clock-cells = <1>;
2692 reg = <0 0x03200000 0 !! 1643 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2693 status = "disabled"; <<
2694 <<
2695 clocks = <&q6afecc LP <<
2696 <&q6afecc LPA <<
2697 <&q6afecc LPA <<
2698 <&q6afecc LPA 1644 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; !! 1645 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2700 !! 1646 clock-names = "core", "audio", "bus";
2701 clock-names = "mclk", <<
2702 <<
2703 #clock-cells = <0>; <<
2704 clock-output-names = <<
2705 #sound-dai-cells = <1 <<
2706 }; 1647 };
2707 1648
2708 swr1: soundwire@3210000 { !! 1649 lpass_tlmm: pinctrl@33c0000{
2709 reg = <0 0x03210000 0 <<
2710 compatible = "qcom,so <<
2711 status = "disabled"; <<
2712 interrupts = <GIC_SPI <<
2713 clocks = <&rxmacro>; <<
2714 clock-names = "iface" <<
2715 label = "RX"; <<
2716 qcom,din-ports = <0>; <<
2717 qcom,dout-ports = <5> <<
2718 <<
2719 qcom,ports-sinterval- <<
2720 qcom,ports-offset1 = <<
2721 qcom,ports-offset2 = <<
2722 qcom,ports-hstart = <<
2723 qcom,ports-hstop = <<
2724 qcom,ports-word-lengt <<
2725 qcom,ports-block-pack <<
2726 qcom,ports-lane-contr <<
2727 qcom,ports-block-grou <<
2728 <<
2729 #sound-dai-cells = <1 <<
2730 #address-cells = <2>; <<
2731 #size-cells = <0>; <<
2732 }; <<
2733 <<
2734 txmacro: txmacro@3220000 { <<
2735 pinctrl-names = "defa <<
2736 pinctrl-0 = <&tx_swr_ <<
2737 compatible = "qcom,sm <<
2738 reg = <0 0x03220000 0 <<
2739 status = "disabled"; <<
2740 <<
2741 clocks = <&q6afecc LP <<
2742 <&q6afecc LP <<
2743 <&q6afecc LP <<
2744 <&q6afecc LP <<
2745 <&vamacro>; <<
2746 <<
2747 clock-names = "mclk", <<
2748 <<
2749 #clock-cells = <0>; <<
2750 clock-output-names = <<
2751 #sound-dai-cells = <1 <<
2752 }; <<
2753 <<
2754 /* tx macro */ <<
2755 swr2: soundwire@3230000 { <<
2756 reg = <0 0x03230000 0 <<
2757 compatible = "qcom,so <<
2758 interrupts = <GIC_SPI <<
2759 interrupt-names = "co <<
2760 status = "disabled"; <<
2761 <<
2762 clocks = <&txmacro>; <<
2763 clock-names = "iface" <<
2764 label = "TX"; <<
2765 <<
2766 qcom,din-ports = <5>; <<
2767 qcom,dout-ports = <0> <<
2768 qcom,ports-sinterval- <<
2769 qcom,ports-offset1 = <<
2770 qcom,ports-offset2 = <<
2771 qcom,ports-block-pack <<
2772 qcom,ports-hstart = <<
2773 qcom,ports-hstop = <<
2774 qcom,ports-word-lengt <<
2775 qcom,ports-block-grou <<
2776 qcom,ports-lane-contr <<
2777 #sound-dai-cells = <1 <<
2778 #address-cells = <2>; <<
2779 #size-cells = <0>; <<
2780 }; <<
2781 <<
2782 lpass_tlmm: pinctrl@33c0000 { <<
2783 compatible = "qcom,sm 1650 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 1651 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 1652 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 1653 gpio-controller;
2787 #gpio-cells = <2>; 1654 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 1655 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 1656
2790 clocks = <&q6afecc LP 1657 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 1658 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 1659 clock-names = "core", "audio";
2793 1660
2794 wsa_swr_active: wsa-s !! 1661 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 1662 clk {
2796 pins 1663 pins = "gpio10";
2797 funct 1664 function = "wsa_swr_clk";
2798 drive 1665 drive-strength = <2>;
2799 slew- 1666 slew-rate = <1>;
2800 bias- 1667 bias-disable;
2801 }; 1668 };
2802 1669
2803 data-pins { !! 1670 data {
2804 pins 1671 pins = "gpio11";
2805 funct 1672 function = "wsa_swr_data";
2806 drive 1673 drive-strength = <2>;
2807 slew- 1674 slew-rate = <1>;
2808 bias- 1675 bias-bus-hold;
>> 1676
2809 }; 1677 };
2810 }; 1678 };
2811 1679
2812 wsa_swr_sleep: wsa-sw !! 1680 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 1681 clk {
2814 pins 1682 pins = "gpio10";
2815 funct 1683 function = "wsa_swr_clk";
2816 drive 1684 drive-strength = <2>;
>> 1685 input-enable;
2817 bias- 1686 bias-pull-down;
2818 }; 1687 };
2819 1688
2820 data-pins { !! 1689 data {
2821 pins 1690 pins = "gpio11";
2822 funct 1691 function = "wsa_swr_data";
2823 drive 1692 drive-strength = <2>;
>> 1693 input-enable;
2824 bias- 1694 bias-pull-down;
>> 1695
2825 }; 1696 };
2826 }; 1697 };
2827 1698
2828 dmic01_active: dmic01 !! 1699 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 1700 clk {
2830 pins 1701 pins = "gpio6";
2831 funct 1702 function = "dmic1_clk";
2832 drive 1703 drive-strength = <8>;
2833 outpu 1704 output-high;
2834 }; 1705 };
2835 data-pins { !! 1706 data {
2836 pins 1707 pins = "gpio7";
2837 funct 1708 function = "dmic1_data";
2838 drive 1709 drive-strength = <8>;
>> 1710 input-enable;
2839 }; 1711 };
2840 }; 1712 };
2841 1713
2842 dmic01_sleep: dmic01- !! 1714 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 1715 clk {
2844 pins 1716 pins = "gpio6";
2845 funct 1717 function = "dmic1_clk";
2846 drive 1718 drive-strength = <2>;
2847 bias- 1719 bias-disable;
2848 outpu 1720 output-low;
2849 }; 1721 };
2850 1722
2851 data-pins { !! 1723 data {
2852 pins 1724 pins = "gpio7";
2853 funct 1725 function = "dmic1_data";
2854 drive 1726 drive-strength = <2>;
2855 bias- !! 1727 pull-down;
2856 }; !! 1728 input-enable;
2857 }; <<
2858 <<
2859 rx_swr_active: rx-swr <<
2860 clk-pins { <<
2861 pins <<
2862 funct <<
2863 drive <<
2864 slew- <<
2865 bias- <<
2866 }; <<
2867 <<
2868 data-pins { <<
2869 pins <<
2870 funct <<
2871 drive <<
2872 slew- <<
2873 bias- <<
2874 }; <<
2875 }; <<
2876 <<
2877 tx_swr_active: tx-swr <<
2878 clk-pins { <<
2879 pins <<
2880 funct <<
2881 drive <<
2882 slew- <<
2883 bias- <<
2884 }; <<
2885 <<
2886 data-pins { <<
2887 pins <<
2888 funct <<
2889 drive <<
2890 slew- <<
2891 bias- <<
2892 }; <<
2893 }; <<
2894 <<
2895 tx_swr_sleep: tx-swr- <<
2896 clk-pins { <<
2897 pins <<
2898 funct <<
2899 drive <<
2900 bias- <<
2901 }; <<
2902 <<
2903 data1-pins { <<
2904 pins <<
2905 funct <<
2906 drive <<
2907 bias- <<
2908 }; <<
2909 <<
2910 data2-pins { <<
2911 pins <<
2912 funct <<
2913 drive <<
2914 bias- <<
2915 }; 1729 };
2916 }; 1730 };
2917 }; 1731 };
2918 1732
2919 gpu: gpu@3d00000 { 1733 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 1734 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 1735 "qcom,adreno";
>> 1736 #stream-id-cells = <16>;
2922 1737
2923 reg = <0 0x03d00000 0 1738 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 1739 reg-names = "kgsl_3d0_reg_memory";
2925 1740
2926 interrupts = <GIC_SPI 1741 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 1742
2928 iommus = <&adreno_smm 1743 iommus = <&adreno_smmu 0 0x401>;
2929 1744
2930 operating-points-v2 = 1745 operating-points-v2 = <&gpu_opp_table>;
2931 1746
2932 qcom,gmu = <&gmu>; 1747 qcom,gmu = <&gmu>;
2933 1748
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; <<
2939 <<
2940 zap-shader { 1749 zap-shader {
2941 memory-region 1750 memory-region = <&gpu_mem>;
2942 }; 1751 };
2943 1752
>> 1753 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 1754 gpu_opp_table: opp-table {
2945 compatible = 1755 compatible = "operating-points-v2";
2946 1756
2947 opp-670000000 1757 opp-670000000 {
2948 opp-h 1758 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 1759 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 1760 };
2952 1761
2953 opp-587000000 1762 opp-587000000 {
2954 opp-h 1763 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 1764 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 1765 };
2958 1766
2959 opp-525000000 1767 opp-525000000 {
2960 opp-h 1768 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 1769 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 1770 };
2964 1771
2965 opp-490000000 1772 opp-490000000 {
2966 opp-h 1773 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 1774 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 1775 };
2970 1776
2971 opp-441600000 1777 opp-441600000 {
2972 opp-h 1778 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 1779 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 1780 };
2976 1781
2977 opp-400000000 1782 opp-400000000 {
2978 opp-h 1783 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 1784 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 1785 };
2982 1786
2983 opp-305000000 1787 opp-305000000 {
2984 opp-h 1788 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 1789 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 1790 };
2988 }; 1791 };
2989 }; 1792 };
2990 1793
2991 gmu: gmu@3d6a000 { 1794 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 1795 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 1796
2994 reg = <0 0x03d6a000 0 1797 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 1798 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 1799 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 1800 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 1801 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 1802
3000 interrupts = <GIC_SPI 1803 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 1804 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 1805 interrupt-names = "hfi", "gmu";
3003 1806
3004 clocks = <&gpucc GPU_ 1807 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 1808 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 1809 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 1810 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 1811 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 1812 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 1813
3011 power-domains = <&gpu 1814 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 1815 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 1816 power-domain-names = "cx", "gx";
3014 1817
3015 iommus = <&adreno_smm 1818 iommus = <&adreno_smmu 5 0x400>;
3016 1819
3017 operating-points-v2 = 1820 operating-points-v2 = <&gmu_opp_table>;
3018 1821
3019 status = "disabled"; <<
3020 <<
3021 gmu_opp_table: opp-ta 1822 gmu_opp_table: opp-table {
3022 compatible = 1823 compatible = "operating-points-v2";
3023 1824
3024 opp-200000000 1825 opp-200000000 {
3025 opp-h 1826 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 1827 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 1828 };
3028 }; 1829 };
3029 }; 1830 };
3030 1831
3031 gpucc: clock-controller@3d900 1832 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 1833 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 1834 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 1835 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 1836 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 1837 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 1838 clock-names = "bi_tcxo",
3038 "gcc_gp 1839 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 1840 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 1841 #clock-cells = <1>;
3041 #reset-cells = <1>; 1842 #reset-cells = <1>;
3042 #power-domain-cells = 1843 #power-domain-cells = <1>;
3043 }; 1844 };
3044 1845
3045 adreno_smmu: iommu@3da0000 { 1846 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 1847 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 1848 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 1849 #iommu-cells = <2>;
3050 #global-interrupts = 1850 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 1851 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 1852 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 1853 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 1854 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 1855 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 1856 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 1857 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 1858 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 1859 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 1860 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 1861 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 1862 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 1863 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 1864 clock-names = "ahb", "bus", "iface";
3065 1865
3066 power-domains = <&gpu 1866 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 1867 };
3069 1868
3070 slpi: remoteproc@5c00000 { 1869 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 1870 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 1871 reg = <0 0x05c00000 0 0x4000>;
3073 1872
3074 interrupts-extended = !! 1873 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 1874 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 1875 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 1876 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 1877 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 1878 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 1879 "handover", "stop-ack";
3081 1880
3082 clocks = <&rpmhcc RPM 1881 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 1882 clock-names = "xo";
3084 1883
3085 power-domains = <&rpm !! 1884 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
3086 <&rpm !! 1885 <&rpmhpd SM8250_LCX>,
3087 power-domain-names = !! 1886 <&rpmhpd SM8250_LMX>;
>> 1887 power-domain-names = "load_state", "lcx", "lmx";
3088 1888
3089 memory-region = <&slp 1889 memory-region = <&slpi_mem>;
3090 1890
3091 qcom,qmp = <&aoss_qmp <<
3092 <<
3093 qcom,smem-states = <& 1891 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 1892 qcom,smem-state-names = "stop";
3095 1893
3096 status = "disabled"; 1894 status = "disabled";
3097 1895
3098 glink-edge { 1896 glink-edge {
3099 interrupts-ex 1897 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 1898 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 1899 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 1900 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 1901 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 1902
3105 label = "slpi 1903 label = "slpi";
3106 qcom,remote-p 1904 qcom,remote-pid = <3>;
3107 1905
3108 fastrpc { 1906 fastrpc {
3109 compa 1907 compatible = "qcom,fastrpc";
3110 qcom, 1908 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 1909 label = "sdsp";
3112 qcom, <<
3113 #addr 1910 #address-cells = <1>;
3114 #size 1911 #size-cells = <0>;
3115 1912
3116 compu 1913 compute-cb@1 {
3117 1914 compatible = "qcom,fastrpc-compute-cb";
3118 1915 reg = <1>;
3119 1916 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 1917 };
3121 1918
3122 compu 1919 compute-cb@2 {
3123 1920 compatible = "qcom,fastrpc-compute-cb";
3124 1921 reg = <2>;
3125 1922 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 1923 };
3127 1924
3128 compu 1925 compute-cb@3 {
3129 1926 compatible = "qcom,fastrpc-compute-cb";
3130 1927 reg = <3>;
3131 1928 iommus = <&apps_smmu 0x0543 0x0>;
3132 1929 /* note: shared-cb = <4> in downstream */
3133 }; 1930 };
3134 }; 1931 };
3135 }; 1932 };
3136 }; 1933 };
3137 1934
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 1935 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 1936 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 1937 reg = <0 0x08300000 0 0x10000>;
3777 1938
3778 interrupts-extended = !! 1939 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 1940 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 1941 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 1942 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 1943 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 1944 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 1945 "handover", "stop-ack";
3785 1946
3786 clocks = <&rpmhcc RPM 1947 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 1948 clock-names = "xo";
3788 1949
3789 power-domains = <&rpm !! 1950 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 1951 <&rpmhpd SM8250_CX>;
>> 1952 power-domain-names = "load_state", "cx";
3790 1953
3791 memory-region = <&cds 1954 memory-region = <&cdsp_mem>;
3792 1955
3793 qcom,qmp = <&aoss_qmp <<
3794 <<
3795 qcom,smem-states = <& 1956 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 1957 qcom,smem-state-names = "stop";
3797 1958
3798 status = "disabled"; 1959 status = "disabled";
3799 1960
3800 glink-edge { 1961 glink-edge {
3801 interrupts-ex 1962 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 1963 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 1964 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 1965 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 1966 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 1967
3807 label = "cdsp 1968 label = "cdsp";
3808 qcom,remote-p 1969 qcom,remote-pid = <5>;
3809 1970
3810 fastrpc { 1971 fastrpc {
3811 compa 1972 compatible = "qcom,fastrpc";
3812 qcom, 1973 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 1974 label = "cdsp";
3814 qcom, <<
3815 #addr 1975 #address-cells = <1>;
3816 #size 1976 #size-cells = <0>;
3817 1977
3818 compu 1978 compute-cb@1 {
3819 1979 compatible = "qcom,fastrpc-compute-cb";
3820 1980 reg = <1>;
3821 1981 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 1982 };
3823 1983
3824 compu 1984 compute-cb@2 {
3825 1985 compatible = "qcom,fastrpc-compute-cb";
3826 1986 reg = <2>;
3827 1987 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 1988 };
3829 1989
3830 compu 1990 compute-cb@3 {
3831 1991 compatible = "qcom,fastrpc-compute-cb";
3832 1992 reg = <3>;
3833 1993 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 1994 };
3835 1995
3836 compu 1996 compute-cb@4 {
3837 1997 compatible = "qcom,fastrpc-compute-cb";
3838 1998 reg = <4>;
3839 1999 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2000 };
3841 2001
3842 compu 2002 compute-cb@5 {
3843 2003 compatible = "qcom,fastrpc-compute-cb";
3844 2004 reg = <5>;
3845 2005 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2006 };
3847 2007
3848 compu 2008 compute-cb@6 {
3849 2009 compatible = "qcom,fastrpc-compute-cb";
3850 2010 reg = <6>;
3851 2011 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2012 };
3853 2013
3854 compu 2014 compute-cb@7 {
3855 2015 compatible = "qcom,fastrpc-compute-cb";
3856 2016 reg = <7>;
3857 2017 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2018 };
3859 2019
3860 compu 2020 compute-cb@8 {
3861 2021 compatible = "qcom,fastrpc-compute-cb";
3862 2022 reg = <8>;
3863 2023 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2024 };
3865 2025
3866 /* no 2026 /* note: secure cb9 in downstream */
3867 }; 2027 };
3868 }; 2028 };
3869 }; 2029 };
3870 2030
>> 2031 sound: sound {
>> 2032 };
>> 2033
3871 usb_1_hsphy: phy@88e3000 { 2034 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2035 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2036 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2037 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2038 status = "disabled";
3876 #phy-cells = <0>; 2039 #phy-cells = <0>;
3877 2040
3878 clocks = <&rpmhcc RPM 2041 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2042 clock-names = "ref";
3880 2043
3881 resets = <&gcc GCC_QU 2044 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2045 };
3883 2046
3884 usb_2_hsphy: phy@88e4000 { 2047 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2048 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2049 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2050 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2051 status = "disabled";
3889 #phy-cells = <0>; 2052 #phy-cells = <0>;
3890 2053
3891 clocks = <&rpmhcc RPM 2054 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2055 clock-names = "ref";
3893 2056
3894 resets = <&gcc GCC_QU 2057 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2058 };
3896 2059
3897 usb_1_qmpphy: phy@88e8000 { !! 2060 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2061 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2062 reg = <0 0x088e9000 0 0x200>,
>> 2063 <0 0x088e8000 0 0x40>,
>> 2064 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2065 status = "disabled";
>> 2066 #address-cells = <2>;
>> 2067 #size-cells = <2>;
>> 2068 ranges;
3901 2069
3902 clocks = <&gcc GCC_US 2070 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2071 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2072 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2073 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2074
3911 resets = <&gcc GCC_US 2075 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2076 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2077 reset-names = "phy", "common";
3914 2078
3915 #clock-cells = <1>; !! 2079 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2080 reg = <0 0x088e9200 0 0x200>,
3917 !! 2081 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2082 <0 0x088e9c00 0 0x400>,
3919 !! 2083 <0 0x088e9600 0 0x200>,
3920 ports { !! 2084 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2085 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2086 #clock-cells = <0>;
3923 !! 2087 #phy-cells = <0>;
3924 port@0 { !! 2088 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2089 clock-names = "pipe0";
3926 usb_1 !! 2090 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2091 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2092
3940 usb_1 !! 2093 dp_phy: dp-phy@88ea200 {
3941 }; !! 2094 reg = <0 0x088ea200 0 0x200>,
>> 2095 <0 0x088ea400 0 0x200>,
>> 2096 <0 0x088eac00 0 0x400>,
>> 2097 <0 0x088ea600 0 0x200>,
>> 2098 <0 0x088ea800 0 0x200>,
>> 2099 <0 0x088eaa00 0 0x100>;
>> 2100 #phy-cells = <0>;
>> 2101 #clock-cells = <1>;
>> 2102 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 2103 clock-names = "pipe0";
>> 2104 clock-output-names = "usb3_phy_pipe_clk_src";
3942 }; 2105 };
3943 }; 2106 };
3944 2107
3945 usb_2_qmpphy: phy@88eb000 { 2108 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2109 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2110 reg = <0 0x088eb000 0 0x200>;
>> 2111 status = "disabled";
>> 2112 #address-cells = <2>;
>> 2113 #size-cells = <2>;
>> 2114 ranges;
3948 2115
3949 clocks = <&gcc GCC_US 2116 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2117 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2118 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2119 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2120 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2121
3961 resets = <&gcc GCC_US !! 2122 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2123 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2124 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2125
3966 status = "disabled"; !! 2126 usb_2_ssphy: lanes@88eb200 {
>> 2127 reg = <0 0x088eb200 0 0x200>,
>> 2128 <0 0x088eb400 0 0x200>,
>> 2129 <0 0x088eb800 0 0x800>;
>> 2130 #clock-cells = <0>;
>> 2131 #phy-cells = <0>;
>> 2132 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2133 clock-names = "pipe0";
>> 2134 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2135 };
3967 }; 2136 };
3968 2137
3969 sdhc_2: mmc@8804000 { !! 2138 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2139 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2140 reg = <0 0x08804000 0 0x1000>;
3972 2141
3973 interrupts = <GIC_SPI 2142 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2143 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2144 interrupt-names = "hc_irq", "pwr_irq";
3976 2145
3977 clocks = <&gcc GCC_SD 2146 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2147 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2148 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2149 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2150 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2151 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2152 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2153 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2154 operating-points-v2 = <&sdhc2_opp_table>;
3986 2155
3987 status = "disabled"; 2156 status = "disabled";
3988 2157
3989 sdhc2_opp_table: opp- !! 2158 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2159 compatible = "operating-points-v2";
3991 2160
3992 opp-19200000 2161 opp-19200000 {
3993 opp-h 2162 opp-hz = /bits/ 64 <19200000>;
3994 requi 2163 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2164 };
3996 2165
3997 opp-50000000 2166 opp-50000000 {
3998 opp-h 2167 opp-hz = /bits/ 64 <50000000>;
3999 requi 2168 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2169 };
4001 2170
4002 opp-100000000 2171 opp-100000000 {
4003 opp-h 2172 opp-hz = /bits/ 64 <100000000>;
4004 requi 2173 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2174 };
4006 2175
4007 opp-202000000 2176 opp-202000000 {
4008 opp-h 2177 opp-hz = /bits/ 64 <202000000>;
4009 requi 2178 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2179 };
4011 }; 2180 };
4012 }; 2181 };
4013 2182
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2183 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2184 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2185 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2186 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2187 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2188 };
4142 2189
4143 gem_noc: interconnect@9100000 2190 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2191 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2192 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2193 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2194 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2195 };
4149 2196
4150 npu_noc: interconnect@9990000 2197 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2198 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2199 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2200 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2201 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2202 };
4156 2203
4157 usb_1: usb@a6f8800 { 2204 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2205 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2206 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2207 status = "disabled";
4161 #address-cells = <2>; 2208 #address-cells = <2>;
4162 #size-cells = <2>; 2209 #size-cells = <2>;
4163 ranges; 2210 ranges;
4164 dma-ranges; 2211 dma-ranges;
4165 2212
4166 clocks = <&gcc GCC_CF 2213 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 2214 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 2215 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 2216 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2217 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 2218 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 2219 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 2220 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 2221
4179 assigned-clocks = <&g 2222 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 2223 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 2224 assigned-clock-rates = <19200000>, <200000000>;
4182 2225
4183 interrupts-extended = !! 2226 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 2227 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 2228 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 2229 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 2230 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 2231 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 2232
4194 power-domains = <&gcc 2233 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 2234
4197 resets = <&gcc GCC_US 2235 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 2236
4199 interconnects = <&agg !! 2237 usb_1_dwc3: dwc3@a600000 {
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 <<
4204 compatible = 2238 compatible = "snps,dwc3";
4205 reg = <0 0x0a 2239 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 2240 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 2241 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 2242 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 2243 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 2244 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 2245 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 2246 };
4233 }; 2247 };
4234 2248
4235 system-cache-controller@92000 2249 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 2250 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 2251 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 2252 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 2253 };
4243 2254
4244 usb_2: usb@a8f8800 { 2255 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 2256 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 2257 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 2258 status = "disabled";
4248 #address-cells = <2>; 2259 #address-cells = <2>;
4249 #size-cells = <2>; 2260 #size-cells = <2>;
4250 ranges; 2261 ranges;
4251 dma-ranges; 2262 dma-ranges;
4252 2263
4253 clocks = <&gcc GCC_CF 2264 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 2265 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 2266 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 2267 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2268 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 2269 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 2270 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 2271 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 2272
4266 assigned-clocks = <&g 2273 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 2274 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 2275 assigned-clock-rates = <19200000>, <200000000>;
4269 2276
4270 interrupts-extended = !! 2277 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 2278 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 2279 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 2280 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 2281 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 2282 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 2283
4281 power-domains = <&gcc 2284 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 2285
4284 resets = <&gcc GCC_US 2286 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 2287
4286 interconnects = <&agg !! 2288 usb_2_dwc3: dwc3@a800000 {
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 <<
4291 compatible = 2289 compatible = "snps,dwc3";
4292 reg = <0 0x0a 2290 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 2291 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 2292 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 2293 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 2294 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 2295 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 2296 phy-names = "usb2-phy", "usb3-phy";
4299 }; 2297 };
4300 }; 2298 };
4301 2299
4302 venus: video-codec@aa00000 { 2300 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 2301 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 2302 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 2303 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 2304 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 2305 <&videocc MVS0_GDSC>,
4308 <&rpm !! 2306 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 2307 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 2308 operating-points-v2 = <&venus_opp_table>;
4311 2309
4312 clocks = <&gcc GCC_VI 2310 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 2311 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 2312 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 2313 clock-names = "iface", "core", "vcodec0_core";
4316 2314
4317 interconnects = <&gem !! 2315 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 2316 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 2317 interconnect-names = "cpu-cfg", "video-mem";
4320 2318
4321 iommus = <&apps_smmu 2319 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 2320 memory-region = <&video_mem>;
4323 2321
4324 resets = <&gcc GCC_VI 2322 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 2323 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 2324 reset-names = "bus", "core";
4327 2325
4328 status = "disabled"; <<
4329 <<
4330 video-decoder { 2326 video-decoder {
4331 compatible = 2327 compatible = "venus-decoder";
4332 }; 2328 };
4333 2329
4334 video-encoder { 2330 video-encoder {
4335 compatible = 2331 compatible = "venus-encoder";
4336 }; 2332 };
4337 2333
4338 venus_opp_table: opp- !! 2334 venus_opp_table: venus-opp-table {
4339 compatible = 2335 compatible = "operating-points-v2";
4340 2336
4341 opp-720000000 2337 opp-720000000 {
4342 opp-h 2338 opp-hz = /bits/ 64 <720000000>;
4343 requi 2339 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 2340 };
4345 2341
4346 opp-101400000 2342 opp-1014000000 {
4347 opp-h 2343 opp-hz = /bits/ 64 <1014000000>;
4348 requi 2344 required-opps = <&rpmhpd_opp_svs>;
4349 }; 2345 };
4350 2346
4351 opp-109800000 2347 opp-1098000000 {
4352 opp-h 2348 opp-hz = /bits/ 64 <1098000000>;
4353 requi 2349 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 2350 };
4355 2351
4356 opp-133200000 2352 opp-1332000000 {
4357 opp-h 2353 opp-hz = /bits/ 64 <1332000000>;
4358 requi 2354 required-opps = <&rpmhpd_opp_nom>;
4359 }; 2355 };
4360 }; 2356 };
4361 }; 2357 };
4362 2358
4363 videocc: clock-controller@abf 2359 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 2360 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 2361 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 2362 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 2363 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 2364 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 2365 mmcx-supply = <&mmcx_reg>;
4370 required-opps = <&rpm <<
4371 clock-names = "iface" 2366 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 2367 #clock-cells = <1>;
4373 #reset-cells = <1>; 2368 #reset-cells = <1>;
4374 #power-domain-cells = 2369 #power-domain-cells = <1>;
4375 }; 2370 };
4376 2371
4377 cci0: cci@ac4f000 { !! 2372 mdss: mdss@ae00000 {
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm 2373 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 2374 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 2375 reg-names = "mdss";
4661 2376
4662 interconnects = <&mms !! 2377 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 2378 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 2379 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 2380
4666 power-domains = <&dis 2381 power-domains = <&dispcc MDSS_GDSC>;
4667 2382
4668 clocks = <&dispcc DIS 2383 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 2384 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 2385 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 2386 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 2387 clock-names = "iface", "bus", "nrt_bus", "core";
4673 2388
>> 2389 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2390 assigned-clock-rates = <460000000>;
>> 2391
4674 interrupts = <GIC_SPI 2392 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 2393 interrupt-controller;
4676 #interrupt-cells = <1 2394 #interrupt-cells = <1>;
4677 2395
4678 iommus = <&apps_smmu 2396 iommus = <&apps_smmu 0x820 0x402>;
4679 2397
4680 status = "disabled"; 2398 status = "disabled";
4681 2399
4682 #address-cells = <2>; 2400 #address-cells = <2>;
4683 #size-cells = <2>; 2401 #size-cells = <2>;
4684 ranges; 2402 ranges;
4685 2403
4686 mdss_mdp: display-con !! 2404 mdss_mdp: mdp@ae01000 {
4687 compatible = 2405 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 2406 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 2407 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 2408 reg-names = "mdp", "vbif";
4691 2409
4692 clocks = <&di 2410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 2411 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 2412 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 2413 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 2414 clock-names = "iface", "bus", "core", "vsync";
4697 2415
4698 assigned-cloc !! 2416 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 2417 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 2418 assigned-clock-rates = <460000000>,
>> 2419 <19200000>;
4700 2420
4701 operating-poi 2421 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 2422 power-domains = <&rpmhpd SM8250_MMCX>;
4703 2423
4704 interrupt-par 2424 interrupt-parent = <&mdss>;
4705 interrupts = !! 2425 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
>> 2426
>> 2427 status = "disabled";
4706 2428
4707 ports { 2429 ports {
4708 #addr 2430 #address-cells = <1>;
4709 #size 2431 #size-cells = <0>;
4710 2432
4711 port@ 2433 port@0 {
4712 2434 reg = <0>;
4713 2435 dpu_intf1_out: endpoint {
4714 !! 2436 remote-endpoint = <&dsi0_in>;
4715 2437 };
4716 }; 2438 };
4717 2439
4718 port@ 2440 port@1 {
4719 2441 reg = <1>;
4720 2442 dpu_intf2_out: endpoint {
4721 !! 2443 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 2444 };
4731 }; 2445 };
4732 }; 2446 };
4733 2447
4734 mdp_opp_table !! 2448 mdp_opp_table: mdp-opp-table {
4735 compa 2449 compatible = "operating-points-v2";
4736 2450
4737 opp-2 2451 opp-200000000 {
4738 2452 opp-hz = /bits/ 64 <200000000>;
4739 2453 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 2454 };
4741 2455
4742 opp-3 2456 opp-300000000 {
4743 2457 opp-hz = /bits/ 64 <300000000>;
4744 2458 required-opps = <&rpmhpd_opp_svs>;
4745 }; 2459 };
4746 2460
4747 opp-3 2461 opp-345000000 {
4748 2462 opp-hz = /bits/ 64 <345000000>;
4749 2463 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 2464 };
4751 2465
4752 opp-4 2466 opp-460000000 {
4753 2467 opp-hz = /bits/ 64 <460000000>;
4754 2468 required-opps = <&rpmhpd_opp_nom>;
4755 }; 2469 };
4756 }; 2470 };
4757 }; 2471 };
4758 2472
4759 mdss_dp: displayport- !! 2473 dsi0: dsi@ae94000 {
4760 compatible = !! 2474 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 2475 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 2476 reg-names = "dsi_ctrl";
4843 2477
4844 interrupt-par 2478 interrupt-parent = <&mdss>;
4845 interrupts = !! 2479 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 2480
4847 clocks = <&di 2481 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 2482 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 2483 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 2484 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 2485 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 2486 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 2487 clock-names = "byte",
4854 2488 "byte_intf",
4855 2489 "pixel",
4856 2490 "core",
4857 2491 "iface",
4858 2492 "bus";
4859 2493
4860 assigned-cloc <<
4861 assigned-cloc <<
4862 <<
4863 operating-poi 2494 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 2495 power-domains = <&rpmhpd SM8250_MMCX>;
4865 2496
4866 phys = <&mdss !! 2497 phys = <&dsi0_phy>;
>> 2498 phy-names = "dsi";
4867 2499
4868 status = "dis 2500 status = "disabled";
4869 2501
4870 #address-cell <<
4871 #size-cells = <<
4872 <<
4873 ports { 2502 ports {
4874 #addr 2503 #address-cells = <1>;
4875 #size 2504 #size-cells = <0>;
4876 2505
4877 port@ 2506 port@0 {
4878 2507 reg = <0>;
4879 !! 2508 dsi0_in: endpoint {
4880 2509 remote-endpoint = <&dpu_intf1_out>;
4881 2510 };
4882 }; 2511 };
4883 2512
4884 port@ 2513 port@1 {
4885 2514 reg = <1>;
4886 !! 2515 dsi0_out: endpoint {
4887 2516 };
4888 }; 2517 };
4889 }; 2518 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 2519 };
4910 2520
4911 mdss_dsi0_phy: phy@ae !! 2521 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 2522 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 2523 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 2524 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 2525 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 2526 reg-names = "dsi_phy",
4917 " 2527 "dsi_phy_lane",
4918 " 2528 "dsi_pll";
4919 2529
4920 #clock-cells 2530 #clock-cells = <1>;
4921 #phy-cells = 2531 #phy-cells = <0>;
4922 2532
4923 clocks = <&di 2533 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 2534 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 2535 clock-names = "iface", "ref";
4926 2536
4927 status = "dis 2537 status = "disabled";
4928 }; 2538 };
4929 2539
4930 mdss_dsi1: dsi@ae9600 !! 2540 dsi1: dsi@ae96000 {
4931 compatible = !! 2541 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 2542 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 2543 reg-names = "dsi_ctrl";
4935 2544
4936 interrupt-par 2545 interrupt-parent = <&mdss>;
4937 interrupts = !! 2546 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 2547
4939 clocks = <&di 2548 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 2549 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 2550 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 2551 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 2552 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 2553 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 2554 clock-names = "byte",
4946 2555 "byte_intf",
4947 2556 "pixel",
4948 2557 "core",
4949 2558 "iface",
4950 2559 "bus";
4951 2560
4952 assigned-cloc <<
4953 assigned-cloc <<
4954 <<
4955 operating-poi 2561 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 2562 power-domains = <&rpmhpd SM8250_MMCX>;
4957 2563
4958 phys = <&mdss !! 2564 phys = <&dsi1_phy>;
>> 2565 phy-names = "dsi";
4959 2566
4960 status = "dis 2567 status = "disabled";
4961 2568
4962 #address-cell <<
4963 #size-cells = <<
4964 <<
4965 ports { 2569 ports {
4966 #addr 2570 #address-cells = <1>;
4967 #size 2571 #size-cells = <0>;
4968 2572
4969 port@ 2573 port@0 {
4970 2574 reg = <0>;
4971 !! 2575 dsi1_in: endpoint {
4972 2576 remote-endpoint = <&dpu_intf2_out>;
4973 2577 };
4974 }; 2578 };
4975 2579
4976 port@ 2580 port@1 {
4977 2581 reg = <1>;
4978 !! 2582 dsi1_out: endpoint {
4979 2583 };
4980 }; 2584 };
4981 }; 2585 };
4982 }; 2586 };
4983 2587
4984 mdss_dsi1_phy: phy@ae !! 2588 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 2589 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 2590 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 2591 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 2592 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 2593 reg-names = "dsi_phy",
4990 " 2594 "dsi_phy_lane",
4991 " 2595 "dsi_pll";
4992 2596
4993 #clock-cells 2597 #clock-cells = <1>;
4994 #phy-cells = 2598 #phy-cells = <0>;
4995 2599
4996 clocks = <&di 2600 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 2601 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 2602 clock-names = "iface", "ref";
4999 2603
5000 status = "dis 2604 status = "disabled";
>> 2605
>> 2606 dsi_opp_table: dsi-opp-table {
>> 2607 compatible = "operating-points-v2";
>> 2608
>> 2609 opp-187500000 {
>> 2610 opp-hz = /bits/ 64 <187500000>;
>> 2611 required-opps = <&rpmhpd_opp_low_svs>;
>> 2612 };
>> 2613
>> 2614 opp-300000000 {
>> 2615 opp-hz = /bits/ 64 <300000000>;
>> 2616 required-opps = <&rpmhpd_opp_svs>;
>> 2617 };
>> 2618
>> 2619 opp-358000000 {
>> 2620 opp-hz = /bits/ 64 <358000000>;
>> 2621 required-opps = <&rpmhpd_opp_svs_l1>;
>> 2622 };
>> 2623 };
5001 }; 2624 };
5002 }; 2625 };
5003 2626
5004 dispcc: clock-controller@af00 2627 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 2628 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 2629 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 2630 mmcx-supply = <&mmcx_reg>;
5008 required-opps = <&rpm <<
5009 clocks = <&rpmhcc RPM 2631 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 2632 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 2633 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 2634 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 2635 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 2636 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 2637 <&dp_phy 1>;
5016 clock-names = "bi_tcx 2638 clock-names = "bi_tcxo",
5017 "dsi0_p 2639 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 2640 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 2641 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 2642 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 2643 "dp_phy_pll_link_clk",
5022 "dp_phy 2644 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 2645 #clock-cells = <1>;
5024 #reset-cells = <1>; 2646 #reset-cells = <1>;
5025 #power-domain-cells = 2647 #power-domain-cells = <1>;
5026 }; 2648 };
5027 2649
5028 pdc: interrupt-controller@b22 2650 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 2651 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 2652 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 2653 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 2654 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 2655 #interrupt-cells = <2>;
5034 interrupt-parent = <& 2656 interrupt-parent = <&intc>;
5035 interrupt-controller; 2657 interrupt-controller;
5036 }; 2658 };
5037 2659
5038 tsens0: thermal-sensor@c26300 2660 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 2661 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 2662 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 2663 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 2664 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 2665 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 2666 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 2667 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 2668 #thermal-sensor-cells = <1>;
5047 }; 2669 };
5048 2670
5049 tsens1: thermal-sensor@c26500 2671 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 2672 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 2673 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 2674 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 2675 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 2676 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 2677 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 2678 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 2679 #thermal-sensor-cells = <1>;
5058 }; 2680 };
5059 2681
5060 aoss_qmp: power-management@c3 !! 2682 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm !! 2683 compatible = "qcom,sm8250-aoss-qmp";
5062 reg = <0 0x0c300000 0 !! 2684 reg = <0 0x0c300000 0 0x100000>;
5063 interrupts-extended = 2685 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 2686 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 2687 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 2688 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 2689 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 2690
5069 #clock-cells = <0>; 2691 #clock-cells = <0>;
5070 }; !! 2692 #power-domain-cells = <1>;
5071 <<
5072 sram@c3f0000 { <<
5073 compatible = "qcom,rp <<
5074 reg = <0 0x0c3f0000 0 <<
5075 }; 2693 };
5076 2694
5077 spmi_bus: spmi@c440000 { 2695 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 2696 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 2697 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 2698 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 2699 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 2700 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 2701 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 2702 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 2703 interrupt-names = "periph_irq";
5086 interrupts-extended = 2704 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 2705 qcom,ee = <0>;
5088 qcom,channel = <0>; 2706 qcom,channel = <0>;
5089 #address-cells = <2>; 2707 #address-cells = <2>;
5090 #size-cells = <0>; 2708 #size-cells = <0>;
5091 interrupt-controller; 2709 interrupt-controller;
5092 #interrupt-cells = <4 2710 #interrupt-cells = <4>;
5093 }; 2711 };
5094 2712
5095 tlmm: pinctrl@f100000 { 2713 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 2714 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 2715 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 2716 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 2717 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 2718 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 2719 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 2720 gpio-controller;
5103 #gpio-cells = <2>; 2721 #gpio-cells = <2>;
5104 interrupt-controller; 2722 interrupt-controller;
5105 #interrupt-cells = <2 2723 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 2724 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 2725 wakeup-parent = <&pdc>;
5108 2726
5109 cam2_default: cam2-de !! 2727 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 2728 sclk {
5111 pins !! 2729 pins = "gpio138";
5112 funct !! 2730 function = "mi2s0_sck";
5113 drive !! 2731 drive-strength = <8>;
5114 bias- 2732 bias-disable;
5115 }; 2733 };
5116 2734
5117 mclk-pins { !! 2735 ws {
5118 pins !! 2736 pins = "gpio141";
5119 funct !! 2737 function = "mi2s0_ws";
5120 drive !! 2738 drive-strength = <8>;
>> 2739 output-high;
>> 2740 };
>> 2741
>> 2742 data0 {
>> 2743 pins = "gpio139";
>> 2744 function = "mi2s0_data0";
>> 2745 drive-strength = <8>;
5121 bias- 2746 bias-disable;
>> 2747 output-high;
>> 2748 };
>> 2749
>> 2750 data1 {
>> 2751 pins = "gpio140";
>> 2752 function = "mi2s0_data1";
>> 2753 drive-strength = <8>;
>> 2754 output-high;
5122 }; 2755 };
5123 }; 2756 };
5124 2757
5125 cam2_suspend: cam2-su !! 2758 qup_i2c0_default: qup-i2c0-default {
5126 rst-pins { !! 2759 mux {
5127 pins !! 2760 pins = "gpio28", "gpio29";
5128 funct !! 2761 function = "qup0";
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; 2762 };
5133 2763
5134 mclk-pins { !! 2764 config {
5135 pins !! 2765 pins = "gpio28", "gpio29";
5136 funct <<
5137 drive 2766 drive-strength = <2>;
5138 bias- 2767 bias-disable;
5139 }; 2768 };
5140 }; 2769 };
5141 2770
5142 cci0_default: cci0-de !! 2771 qup_i2c1_default: qup-i2c1-default {
5143 cci0_i2c0_def !! 2772 pinmux {
5144 /* SD !! 2773 pins = "gpio4", "gpio5";
5145 pins !! 2774 function = "qup1";
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; 2775 };
5151 2776
5152 cci0_i2c1_def !! 2777 config {
5153 /* SD !! 2778 pins = "gpio4", "gpio5";
5154 pins !! 2779 drive-strength = <2>;
5155 funct !! 2780 bias-disable;
5156 <<
5157 bias- <<
5158 drive <<
5159 }; 2781 };
5160 }; 2782 };
5161 2783
5162 cci0_sleep: cci0-slee !! 2784 qup_i2c2_default: qup-i2c2-default {
5163 cci0_i2c0_sle !! 2785 mux {
5164 /* SD !! 2786 pins = "gpio115", "gpio116";
5165 pins !! 2787 function = "qup2";
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; 2788 };
5171 2789
5172 cci0_i2c1_sle !! 2790 config {
5173 /* SD !! 2791 pins = "gpio115", "gpio116";
5174 pins !! 2792 drive-strength = <2>;
5175 funct !! 2793 bias-disable;
5176 <<
5177 drive <<
5178 bias- <<
5179 }; 2794 };
5180 }; 2795 };
5181 2796
5182 cci1_default: cci1-de !! 2797 qup_i2c3_default: qup-i2c3-default {
5183 cci1_i2c0_def !! 2798 mux {
5184 /* SD !! 2799 pins = "gpio119", "gpio120";
5185 pins !! 2800 function = "qup3";
5186 funct !! 2801 };
5187 2802
5188 bias- !! 2803 config {
5189 drive !! 2804 pins = "gpio119", "gpio120";
>> 2805 drive-strength = <2>;
>> 2806 bias-disable;
5190 }; 2807 };
>> 2808 };
5191 2809
5192 cci1_i2c1_def !! 2810 qup_i2c4_default: qup-i2c4-default {
5193 /* SD !! 2811 mux {
5194 pins !! 2812 pins = "gpio8", "gpio9";
5195 funct !! 2813 function = "qup4";
>> 2814 };
5196 2815
5197 bias- !! 2816 config {
5198 drive !! 2817 pins = "gpio8", "gpio9";
>> 2818 drive-strength = <2>;
>> 2819 bias-disable;
5199 }; 2820 };
5200 }; 2821 };
5201 2822
5202 cci1_sleep: cci1-slee !! 2823 qup_i2c5_default: qup-i2c5-default {
5203 cci1_i2c0_sle !! 2824 mux {
5204 /* SD !! 2825 pins = "gpio12", "gpio13";
5205 pins !! 2826 function = "qup5";
5206 funct !! 2827 };
5207 2828
5208 bias- !! 2829 config {
5209 drive !! 2830 pins = "gpio12", "gpio13";
>> 2831 drive-strength = <2>;
>> 2832 bias-disable;
5210 }; 2833 };
>> 2834 };
5211 2835
5212 cci1_i2c1_sle !! 2836 qup_i2c6_default: qup-i2c6-default {
5213 /* SD !! 2837 mux {
5214 pins !! 2838 pins = "gpio16", "gpio17";
5215 funct !! 2839 function = "qup6";
>> 2840 };
5216 2841
5217 bias- !! 2842 config {
5218 drive !! 2843 pins = "gpio16", "gpio17";
>> 2844 drive-strength = <2>;
>> 2845 bias-disable;
5219 }; 2846 };
5220 }; 2847 };
5221 2848
5222 pri_mi2s_active: pri- !! 2849 qup_i2c7_default: qup-i2c7-default {
5223 sclk-pins { !! 2850 mux {
5224 pins !! 2851 pins = "gpio20", "gpio21";
5225 funct !! 2852 function = "qup7";
5226 drive !! 2853 };
>> 2854
>> 2855 config {
>> 2856 pins = "gpio20", "gpio21";
>> 2857 drive-strength = <2>;
5227 bias- 2858 bias-disable;
5228 }; 2859 };
>> 2860 };
5229 2861
5230 ws-pins { !! 2862 qup_i2c8_default: qup-i2c8-default {
5231 pins !! 2863 mux {
5232 funct !! 2864 pins = "gpio24", "gpio25";
5233 drive !! 2865 function = "qup8";
5234 outpu <<
5235 }; 2866 };
5236 2867
5237 data0-pins { !! 2868 config {
5238 pins !! 2869 pins = "gpio24", "gpio25";
5239 funct !! 2870 drive-strength = <2>;
5240 drive <<
5241 bias- 2871 bias-disable;
5242 outpu <<
5243 }; 2872 };
>> 2873 };
5244 2874
5245 data1-pins { !! 2875 qup_i2c9_default: qup-i2c9-default {
5246 pins !! 2876 mux {
5247 funct !! 2877 pins = "gpio125", "gpio126";
5248 drive !! 2878 function = "qup9";
5249 outpu <<
5250 }; 2879 };
5251 }; <<
5252 2880
5253 qup_i2c0_default: qup !! 2881 config {
5254 pins = "gpio2 !! 2882 pins = "gpio125", "gpio126";
5255 function = "q !! 2883 drive-strength = <2>;
5256 drive-strengt !! 2884 bias-disable;
5257 bias-disable; !! 2885 };
5258 }; 2886 };
5259 2887
5260 qup_i2c1_default: qup !! 2888 qup_i2c10_default: qup-i2c10-default {
5261 pins = "gpio4 !! 2889 mux {
5262 function = "q !! 2890 pins = "gpio129", "gpio130";
5263 drive-strengt !! 2891 function = "qup10";
5264 bias-disable; !! 2892 };
5265 }; <<
5266 2893
5267 qup_i2c2_default: qup !! 2894 config {
5268 pins = "gpio1 !! 2895 pins = "gpio129", "gpio130";
5269 function = "q !! 2896 drive-strength = <2>;
5270 drive-strengt !! 2897 bias-disable;
5271 bias-disable; !! 2898 };
5272 }; 2899 };
5273 2900
5274 qup_i2c3_default: qup !! 2901 qup_i2c11_default: qup-i2c11-default {
5275 pins = "gpio1 !! 2902 mux {
5276 function = "q !! 2903 pins = "gpio60", "gpio61";
5277 drive-strengt !! 2904 function = "qup11";
5278 bias-disable; !! 2905 };
5279 }; <<
5280 2906
5281 qup_i2c4_default: qup !! 2907 config {
5282 pins = "gpio8 !! 2908 pins = "gpio60", "gpio61";
5283 function = "q !! 2909 drive-strength = <2>;
5284 drive-strengt !! 2910 bias-disable;
5285 bias-disable; !! 2911 };
5286 }; 2912 };
5287 2913
5288 qup_i2c5_default: qup !! 2914 qup_i2c12_default: qup-i2c12-default {
5289 pins = "gpio1 !! 2915 mux {
5290 function = "q !! 2916 pins = "gpio32", "gpio33";
5291 drive-strengt !! 2917 function = "qup12";
5292 bias-disable; !! 2918 };
5293 }; <<
5294 2919
5295 qup_i2c6_default: qup !! 2920 config {
5296 pins = "gpio1 !! 2921 pins = "gpio32", "gpio33";
5297 function = "q !! 2922 drive-strength = <2>;
5298 drive-strengt !! 2923 bias-disable;
5299 bias-disable; !! 2924 };
5300 }; 2925 };
5301 2926
5302 qup_i2c7_default: qup !! 2927 qup_i2c13_default: qup-i2c13-default {
5303 pins = "gpio2 !! 2928 mux {
5304 function = "q !! 2929 pins = "gpio36", "gpio37";
5305 drive-strengt !! 2930 function = "qup13";
5306 bias-disable; !! 2931 };
5307 }; <<
5308 2932
5309 qup_i2c8_default: qup !! 2933 config {
5310 pins = "gpio2 !! 2934 pins = "gpio36", "gpio37";
5311 function = "q !! 2935 drive-strength = <2>;
5312 drive-strengt !! 2936 bias-disable;
5313 bias-disable; !! 2937 };
5314 }; 2938 };
5315 2939
5316 qup_i2c9_default: qup !! 2940 qup_i2c14_default: qup-i2c14-default {
5317 pins = "gpio1 !! 2941 mux {
5318 function = "q !! 2942 pins = "gpio40", "gpio41";
5319 drive-strengt !! 2943 function = "qup14";
5320 bias-disable; !! 2944 };
5321 }; <<
5322 2945
5323 qup_i2c10_default: qu !! 2946 config {
5324 pins = "gpio1 !! 2947 pins = "gpio40", "gpio41";
5325 function = "q !! 2948 drive-strength = <2>;
5326 drive-strengt !! 2949 bias-disable;
5327 bias-disable; !! 2950 };
5328 }; 2951 };
5329 2952
5330 qup_i2c11_default: qu !! 2953 qup_i2c15_default: qup-i2c15-default {
5331 pins = "gpio6 !! 2954 mux {
5332 function = "q !! 2955 pins = "gpio44", "gpio45";
5333 drive-strengt !! 2956 function = "qup15";
5334 bias-disable; !! 2957 };
5335 }; <<
5336 2958
5337 qup_i2c12_default: qu !! 2959 config {
5338 pins = "gpio3 !! 2960 pins = "gpio44", "gpio45";
5339 function = "q !! 2961 drive-strength = <2>;
5340 drive-strengt !! 2962 bias-disable;
5341 bias-disable; !! 2963 };
5342 }; 2964 };
5343 2965
5344 qup_i2c13_default: qu !! 2966 qup_i2c16_default: qup-i2c16-default {
5345 pins = "gpio3 !! 2967 mux {
5346 function = "q !! 2968 pins = "gpio48", "gpio49";
5347 drive-strengt !! 2969 function = "qup16";
5348 bias-disable; !! 2970 };
5349 }; <<
5350 2971
5351 qup_i2c14_default: qu !! 2972 config {
5352 pins = "gpio4 !! 2973 pins = "gpio48", "gpio49";
5353 function = "q !! 2974 drive-strength = <2>;
5354 drive-strengt !! 2975 bias-disable;
5355 bias-disable; !! 2976 };
5356 }; 2977 };
5357 2978
5358 qup_i2c15_default: qu !! 2979 qup_i2c17_default: qup-i2c17-default {
5359 pins = "gpio4 !! 2980 mux {
5360 function = "q !! 2981 pins = "gpio52", "gpio53";
5361 drive-strengt !! 2982 function = "qup17";
5362 bias-disable; !! 2983 };
5363 }; <<
5364 2984
5365 qup_i2c16_default: qu !! 2985 config {
5366 pins = "gpio4 !! 2986 pins = "gpio52", "gpio53";
5367 function = "q !! 2987 drive-strength = <2>;
5368 drive-strengt !! 2988 bias-disable;
5369 bias-disable; !! 2989 };
5370 }; 2990 };
5371 2991
5372 qup_i2c17_default: qu !! 2992 qup_i2c18_default: qup-i2c18-default {
5373 pins = "gpio5 !! 2993 mux {
5374 function = "q !! 2994 pins = "gpio56", "gpio57";
5375 drive-strengt !! 2995 function = "qup18";
5376 bias-disable; !! 2996 };
5377 }; <<
5378 2997
5379 qup_i2c18_default: qu !! 2998 config {
5380 pins = "gpio5 !! 2999 pins = "gpio56", "gpio57";
5381 function = "q !! 3000 drive-strength = <2>;
5382 drive-strengt !! 3001 bias-disable;
5383 bias-disable; !! 3002 };
5384 }; 3003 };
5385 3004
5386 qup_i2c19_default: qu !! 3005 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 3006 mux {
5388 function = "q !! 3007 pins = "gpio0", "gpio1";
5389 drive-strengt !! 3008 function = "qup19";
5390 bias-disable; !! 3009 };
>> 3010
>> 3011 config {
>> 3012 pins = "gpio0", "gpio1";
>> 3013 drive-strength = <2>;
>> 3014 bias-disable;
>> 3015 };
5391 }; 3016 };
5392 3017
5393 qup_spi0_cs: qup-spi0 !! 3018 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 3019 pins = "gpio31";
5395 function = "q 3020 function = "qup0";
5396 }; 3021 };
5397 3022
5398 qup_spi0_cs_gpio: qup !! 3023 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 3024 pins = "gpio31";
5400 function = "g 3025 function = "gpio";
5401 }; 3026 };
5402 3027
5403 qup_spi0_data_clk: qu !! 3028 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 3029 pins = "gpio28", "gpio29",
5405 "gpio3 3030 "gpio30";
5406 function = "q 3031 function = "qup0";
5407 }; 3032 };
5408 3033
5409 qup_spi1_cs: qup-spi1 !! 3034 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 3035 pins = "gpio7";
5411 function = "q 3036 function = "qup1";
5412 }; 3037 };
5413 3038
5414 qup_spi1_cs_gpio: qup !! 3039 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 3040 pins = "gpio7";
5416 function = "g 3041 function = "gpio";
5417 }; 3042 };
5418 3043
5419 qup_spi1_data_clk: qu !! 3044 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 3045 pins = "gpio4", "gpio5",
5421 "gpio6 3046 "gpio6";
5422 function = "q 3047 function = "qup1";
5423 }; 3048 };
5424 3049
5425 qup_spi2_cs: qup-spi2 !! 3050 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 3051 pins = "gpio118";
5427 function = "q 3052 function = "qup2";
5428 }; 3053 };
5429 3054
5430 qup_spi2_cs_gpio: qup !! 3055 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 3056 pins = "gpio118";
5432 function = "g 3057 function = "gpio";
5433 }; 3058 };
5434 3059
5435 qup_spi2_data_clk: qu !! 3060 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 3061 pins = "gpio115", "gpio116",
5437 "gpio1 3062 "gpio117";
5438 function = "q 3063 function = "qup2";
5439 }; 3064 };
5440 3065
5441 qup_spi3_cs: qup-spi3 !! 3066 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 3067 pins = "gpio122";
5443 function = "q 3068 function = "qup3";
5444 }; 3069 };
5445 3070
5446 qup_spi3_cs_gpio: qup !! 3071 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 3072 pins = "gpio122";
5448 function = "g 3073 function = "gpio";
5449 }; 3074 };
5450 3075
5451 qup_spi3_data_clk: qu !! 3076 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 3077 pins = "gpio119", "gpio120",
5453 "gpio1 3078 "gpio121";
5454 function = "q 3079 function = "qup3";
5455 }; 3080 };
5456 3081
5457 qup_spi4_cs: qup-spi4 !! 3082 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 3083 pins = "gpio11";
5459 function = "q 3084 function = "qup4";
5460 }; 3085 };
5461 3086
5462 qup_spi4_cs_gpio: qup !! 3087 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 3088 pins = "gpio11";
5464 function = "g 3089 function = "gpio";
5465 }; 3090 };
5466 3091
5467 qup_spi4_data_clk: qu !! 3092 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 3093 pins = "gpio8", "gpio9",
5469 "gpio1 3094 "gpio10";
5470 function = "q 3095 function = "qup4";
5471 }; 3096 };
5472 3097
5473 qup_spi5_cs: qup-spi5 !! 3098 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 3099 pins = "gpio15";
5475 function = "q 3100 function = "qup5";
5476 }; 3101 };
5477 3102
5478 qup_spi5_cs_gpio: qup !! 3103 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 3104 pins = "gpio15";
5480 function = "g 3105 function = "gpio";
5481 }; 3106 };
5482 3107
5483 qup_spi5_data_clk: qu !! 3108 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 3109 pins = "gpio12", "gpio13",
5485 "gpio1 3110 "gpio14";
5486 function = "q 3111 function = "qup5";
5487 }; 3112 };
5488 3113
5489 qup_spi6_cs: qup-spi6 !! 3114 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 3115 pins = "gpio19";
5491 function = "q 3116 function = "qup6";
5492 }; 3117 };
5493 3118
5494 qup_spi6_cs_gpio: qup !! 3119 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 3120 pins = "gpio19";
5496 function = "g 3121 function = "gpio";
5497 }; 3122 };
5498 3123
5499 qup_spi6_data_clk: qu !! 3124 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 3125 pins = "gpio16", "gpio17",
5501 "gpio1 3126 "gpio18";
5502 function = "q 3127 function = "qup6";
5503 }; 3128 };
5504 3129
5505 qup_spi7_cs: qup-spi7 !! 3130 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 3131 pins = "gpio23";
5507 function = "q 3132 function = "qup7";
5508 }; 3133 };
5509 3134
5510 qup_spi7_cs_gpio: qup !! 3135 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 3136 pins = "gpio23";
5512 function = "g 3137 function = "gpio";
5513 }; 3138 };
5514 3139
5515 qup_spi7_data_clk: qu !! 3140 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 3141 pins = "gpio20", "gpio21",
5517 "gpio2 3142 "gpio22";
5518 function = "q 3143 function = "qup7";
5519 }; 3144 };
5520 3145
5521 qup_spi8_cs: qup-spi8 !! 3146 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 3147 pins = "gpio27";
5523 function = "q 3148 function = "qup8";
5524 }; 3149 };
5525 3150
5526 qup_spi8_cs_gpio: qup !! 3151 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 3152 pins = "gpio27";
5528 function = "g 3153 function = "gpio";
5529 }; 3154 };
5530 3155
5531 qup_spi8_data_clk: qu !! 3156 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 3157 pins = "gpio24", "gpio25",
5533 "gpio2 3158 "gpio26";
5534 function = "q 3159 function = "qup8";
5535 }; 3160 };
5536 3161
5537 qup_spi9_cs: qup-spi9 !! 3162 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 3163 pins = "gpio128";
5539 function = "q 3164 function = "qup9";
5540 }; 3165 };
5541 3166
5542 qup_spi9_cs_gpio: qup !! 3167 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 3168 pins = "gpio128";
5544 function = "g 3169 function = "gpio";
5545 }; 3170 };
5546 3171
5547 qup_spi9_data_clk: qu !! 3172 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 3173 pins = "gpio125", "gpio126",
5549 "gpio1 3174 "gpio127";
5550 function = "q 3175 function = "qup9";
5551 }; 3176 };
5552 3177
5553 qup_spi10_cs: qup-spi !! 3178 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 3179 pins = "gpio132";
5555 function = "q 3180 function = "qup10";
5556 }; 3181 };
5557 3182
5558 qup_spi10_cs_gpio: qu !! 3183 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 3184 pins = "gpio132";
5560 function = "g 3185 function = "gpio";
5561 }; 3186 };
5562 3187
5563 qup_spi10_data_clk: q !! 3188 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 3189 pins = "gpio129", "gpio130",
5565 "gpio1 3190 "gpio131";
5566 function = "q 3191 function = "qup10";
5567 }; 3192 };
5568 3193
5569 qup_spi11_cs: qup-spi !! 3194 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 3195 pins = "gpio63";
5571 function = "q 3196 function = "qup11";
5572 }; 3197 };
5573 3198
5574 qup_spi11_cs_gpio: qu !! 3199 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 3200 pins = "gpio63";
5576 function = "g 3201 function = "gpio";
5577 }; 3202 };
5578 3203
5579 qup_spi11_data_clk: q !! 3204 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 3205 pins = "gpio60", "gpio61",
5581 "gpio6 3206 "gpio62";
5582 function = "q 3207 function = "qup11";
5583 }; 3208 };
5584 3209
5585 qup_spi12_cs: qup-spi !! 3210 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 3211 pins = "gpio35";
5587 function = "q 3212 function = "qup12";
5588 }; 3213 };
5589 3214
5590 qup_spi12_cs_gpio: qu !! 3215 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 3216 pins = "gpio35";
5592 function = "g 3217 function = "gpio";
5593 }; 3218 };
5594 3219
5595 qup_spi12_data_clk: q !! 3220 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 3221 pins = "gpio32", "gpio33",
5597 "gpio3 3222 "gpio34";
5598 function = "q 3223 function = "qup12";
5599 }; 3224 };
5600 3225
5601 qup_spi13_cs: qup-spi !! 3226 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 3227 pins = "gpio39";
5603 function = "q 3228 function = "qup13";
5604 }; 3229 };
5605 3230
5606 qup_spi13_cs_gpio: qu !! 3231 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 3232 pins = "gpio39";
5608 function = "g 3233 function = "gpio";
5609 }; 3234 };
5610 3235
5611 qup_spi13_data_clk: q !! 3236 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 3237 pins = "gpio36", "gpio37",
5613 "gpio3 3238 "gpio38";
5614 function = "q 3239 function = "qup13";
5615 }; 3240 };
5616 3241
5617 qup_spi14_cs: qup-spi !! 3242 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 3243 pins = "gpio43";
5619 function = "q 3244 function = "qup14";
5620 }; 3245 };
5621 3246
5622 qup_spi14_cs_gpio: qu !! 3247 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 3248 pins = "gpio43";
5624 function = "g 3249 function = "gpio";
5625 }; 3250 };
5626 3251
5627 qup_spi14_data_clk: q !! 3252 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 3253 pins = "gpio40", "gpio41",
5629 "gpio4 3254 "gpio42";
5630 function = "q 3255 function = "qup14";
5631 }; 3256 };
5632 3257
5633 qup_spi15_cs: qup-spi !! 3258 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 3259 pins = "gpio47";
5635 function = "q 3260 function = "qup15";
5636 }; 3261 };
5637 3262
5638 qup_spi15_cs_gpio: qu !! 3263 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 3264 pins = "gpio47";
5640 function = "g 3265 function = "gpio";
5641 }; 3266 };
5642 3267
5643 qup_spi15_data_clk: q !! 3268 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 3269 pins = "gpio44", "gpio45",
5645 "gpio4 3270 "gpio46";
5646 function = "q 3271 function = "qup15";
5647 }; 3272 };
5648 3273
5649 qup_spi16_cs: qup-spi !! 3274 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 3275 pins = "gpio51";
5651 function = "q 3276 function = "qup16";
5652 }; 3277 };
5653 3278
5654 qup_spi16_cs_gpio: qu !! 3279 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 3280 pins = "gpio51";
5656 function = "g 3281 function = "gpio";
5657 }; 3282 };
5658 3283
5659 qup_spi16_data_clk: q !! 3284 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 3285 pins = "gpio48", "gpio49",
5661 "gpio5 3286 "gpio50";
5662 function = "q 3287 function = "qup16";
5663 }; 3288 };
5664 3289
5665 qup_spi17_cs: qup-spi !! 3290 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 3291 pins = "gpio55";
5667 function = "q 3292 function = "qup17";
5668 }; 3293 };
5669 3294
5670 qup_spi17_cs_gpio: qu !! 3295 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 3296 pins = "gpio55";
5672 function = "g 3297 function = "gpio";
5673 }; 3298 };
5674 3299
5675 qup_spi17_data_clk: q !! 3300 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 3301 pins = "gpio52", "gpio53",
5677 "gpio5 3302 "gpio54";
5678 function = "q 3303 function = "qup17";
5679 }; 3304 };
5680 3305
5681 qup_spi18_cs: qup-spi !! 3306 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 3307 pins = "gpio59";
5683 function = "q 3308 function = "qup18";
5684 }; 3309 };
5685 3310
5686 qup_spi18_cs_gpio: qu !! 3311 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 3312 pins = "gpio59";
5688 function = "g 3313 function = "gpio";
5689 }; 3314 };
5690 3315
5691 qup_spi18_data_clk: q !! 3316 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 3317 pins = "gpio56", "gpio57",
5693 "gpio5 3318 "gpio58";
5694 function = "q 3319 function = "qup18";
5695 }; 3320 };
5696 3321
5697 qup_spi19_cs: qup-spi !! 3322 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 3323 pins = "gpio3";
5699 function = "q 3324 function = "qup19";
5700 }; 3325 };
5701 3326
5702 qup_spi19_cs_gpio: qu !! 3327 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 3328 pins = "gpio3";
5704 function = "g 3329 function = "gpio";
5705 }; 3330 };
5706 3331
5707 qup_spi19_data_clk: q !! 3332 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 3333 pins = "gpio0", "gpio1",
5709 "gpio2 3334 "gpio2";
5710 function = "q 3335 function = "qup19";
5711 }; 3336 };
5712 3337
5713 qup_uart2_default: qu !! 3338 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 3339 mux {
5715 function = "q !! 3340 pins = "gpio117", "gpio118";
>> 3341 function = "qup2";
>> 3342 };
5716 }; 3343 };
5717 3344
5718 qup_uart6_default: qu !! 3345 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 3346 mux {
5720 function = "q !! 3347 pins = "gpio16", "gpio17",
>> 3348 "gpio18", "gpio19";
>> 3349 function = "qup6";
>> 3350 };
5721 }; 3351 };
5722 3352
5723 qup_uart12_default: q !! 3353 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 3354 mux {
5725 function = "q !! 3355 pins = "gpio34", "gpio35";
>> 3356 function = "qup12";
>> 3357 };
5726 }; 3358 };
5727 3359
5728 qup_uart17_default: q !! 3360 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 3361 mux {
5730 function = "q !! 3362 pins = "gpio52", "gpio53",
>> 3363 "gpio54", "gpio55";
>> 3364 function = "qup17";
>> 3365 };
5731 }; 3366 };
5732 3367
5733 qup_uart18_default: q !! 3368 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 3369 mux {
5735 function = "q !! 3370 pins = "gpio58", "gpio59";
>> 3371 function = "qup18";
>> 3372 };
5736 }; 3373 };
5737 3374
5738 tert_mi2s_active: ter !! 3375 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 3376 sck {
5740 pins 3377 pins = "gpio133";
5741 funct 3378 function = "mi2s2_sck";
5742 drive 3379 drive-strength = <8>;
5743 bias- 3380 bias-disable;
5744 }; 3381 };
5745 3382
5746 data0-pins { !! 3383 data0 {
5747 pins 3384 pins = "gpio134";
5748 funct 3385 function = "mi2s2_data0";
5749 drive 3386 drive-strength = <8>;
5750 bias- 3387 bias-disable;
5751 outpu 3388 output-high;
5752 }; 3389 };
5753 3390
5754 ws-pins { !! 3391 ws {
5755 pins 3392 pins = "gpio135";
5756 funct 3393 function = "mi2s2_ws";
5757 drive 3394 drive-strength = <8>;
5758 outpu 3395 output-high;
5759 }; 3396 };
5760 }; 3397 };
5761 <<
5762 sdc2_sleep_state: sdc <<
5763 clk-pins { <<
5764 pins <<
5765 drive <<
5766 bias- <<
5767 }; <<
5768 <<
5769 cmd-pins { <<
5770 pins <<
5771 drive <<
5772 bias- <<
5773 }; <<
5774 <<
5775 data-pins { <<
5776 pins <<
5777 drive <<
5778 bias- <<
5779 }; <<
5780 }; <<
5781 <<
5782 pcie0_default_state: <<
5783 perst-pins { <<
5784 pins <<
5785 funct <<
5786 drive <<
5787 bias- <<
5788 }; <<
5789 <<
5790 clkreq-pins { <<
5791 pins <<
5792 funct <<
5793 drive <<
5794 bias- <<
5795 }; <<
5796 <<
5797 wake-pins { <<
5798 pins <<
5799 funct <<
5800 drive <<
5801 bias- <<
5802 }; <<
5803 }; <<
5804 <<
5805 pcie1_default_state: <<
5806 perst-pins { <<
5807 pins <<
5808 funct <<
5809 drive <<
5810 bias- <<
5811 }; <<
5812 <<
5813 clkreq-pins { <<
5814 pins <<
5815 funct <<
5816 drive <<
5817 bias- <<
5818 }; <<
5819 <<
5820 wake-pins { <<
5821 pins <<
5822 funct <<
5823 drive <<
5824 bias- <<
5825 }; <<
5826 }; <<
5827 <<
5828 pcie2_default_state: <<
5829 perst-pins { <<
5830 pins <<
5831 funct <<
5832 drive <<
5833 bias- <<
5834 }; <<
5835 <<
5836 clkreq-pins { <<
5837 pins <<
5838 funct <<
5839 drive <<
5840 bias- <<
5841 }; <<
5842 <<
5843 wake-pins { <<
5844 pins <<
5845 funct <<
5846 drive <<
5847 bias- <<
5848 }; <<
5849 }; <<
5850 }; 3398 };
5851 3399
5852 apps_smmu: iommu@15000000 { 3400 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 3401 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 3402 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 3403 #iommu-cells = <2>;
5856 #global-interrupts = 3404 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 3405 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 3406 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 3407 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 3408 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 3409 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 3410 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 3411 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 3412 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 3413 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 3414 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 3415 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 3416 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 3417 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 3418 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 3419 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 3420 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 3421 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 3422 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 3423 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 3424 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 3425 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 3426 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 3427 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 3428 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 3429 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 3430 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 3431 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 3432 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 3433 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 3434 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 3435 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 3436 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 3437 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 3438 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 3439 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 3440 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 3441 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 3442 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 3443 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 3444 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 3445 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 3446 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 3447 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 3448 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 3449 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 3450 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 3451 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 3452 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 3453 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 3454 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 3455 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 3456 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 3457 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 3458 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 3459 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 3460 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 3461 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 3462 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 3463 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 3464 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 3465 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 3466 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 3467 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 3468 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 3469 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 3470 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 3471 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 3472 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 3473 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 3474 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 3475 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 3476 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 3477 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 3478 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 3479 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 3480 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 3481 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 3482 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 3483 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 3484 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 3485 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 3486 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 3487 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 3488 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 3489 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 3490 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 3491 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 3492 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 3493 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 3494 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 3495 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 3496 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 3497 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 3498 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 3499 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 3500 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 3501 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 3502 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 3503 };
5957 3504
5958 adsp: remoteproc@17300000 { 3505 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 3506 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 3507 reg = <0 0x17300000 0 0x100>;
5961 3508
5962 interrupts-extended = !! 3509 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 3510 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 3511 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 3512 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 3513 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 3514 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 3515 "handover", "stop-ack";
5969 3516
5970 clocks = <&rpmhcc RPM 3517 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 3518 clock-names = "xo";
5972 3519
5973 power-domains = <&rpm !! 3520 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
5974 <&rpm !! 3521 <&rpmhpd SM8250_LCX>,
5975 power-domain-names = !! 3522 <&rpmhpd SM8250_LMX>;
>> 3523 power-domain-names = "load_state", "lcx", "lmx";
5976 3524
5977 memory-region = <&ads 3525 memory-region = <&adsp_mem>;
5978 3526
5979 qcom,qmp = <&aoss_qmp <<
5980 <<
5981 qcom,smem-states = <& 3527 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 3528 qcom,smem-state-names = "stop";
5983 3529
5984 status = "disabled"; 3530 status = "disabled";
5985 3531
5986 glink-edge { 3532 glink-edge {
5987 interrupts-ex 3533 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 3534 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 3535 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 3536 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 3537 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 3538
5993 label = "lpas 3539 label = "lpass";
5994 qcom,remote-p 3540 qcom,remote-pid = <2>;
5995 3541
5996 apr { 3542 apr {
5997 compa 3543 compatible = "qcom,apr-v2";
5998 qcom, 3544 qcom,glink-channels = "apr_audio_svc";
5999 qcom, !! 3545 qcom,apr-domain = <APR_DOMAIN_ADSP>;
6000 #addr 3546 #address-cells = <1>;
6001 #size 3547 #size-cells = <0>;
6002 3548
6003 servi !! 3549 apr-service@3 {
6004 3550 reg = <APR_SVC_ADSP_CORE>;
6005 3551 compatible = "qcom,q6core";
6006 3552 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 3553 };
6008 3554
6009 q6afe !! 3555 q6afe: apr-service@4 {
6010 3556 compatible = "qcom,q6afe";
6011 3557 reg = <APR_SVC_AFE>;
6012 3558 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 3559 q6afedai: dais {
6014 3560 compatible = "qcom,q6afe-dais";
6015 3561 #address-cells = <1>;
6016 3562 #size-cells = <0>;
6017 3563 #sound-dai-cells = <1>;
6018 3564 };
6019 3565
6020 !! 3566 q6afecc: cc {
6021 3567 compatible = "qcom,q6afe-clocks";
6022 3568 #clock-cells = <2>;
6023 3569 };
6024 }; 3570 };
6025 3571
6026 q6asm !! 3572 q6asm: apr-service@7 {
6027 3573 compatible = "qcom,q6asm";
6028 3574 reg = <APR_SVC_ASM>;
6029 3575 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 3576 q6asmdai: dais {
6031 3577 compatible = "qcom,q6asm-dais";
6032 3578 #address-cells = <1>;
6033 3579 #size-cells = <0>;
6034 3580 #sound-dai-cells = <1>;
6035 3581 iommus = <&apps_smmu 0x1801 0x0>;
6036 3582 };
6037 }; 3583 };
6038 3584
6039 q6adm !! 3585 q6adm: apr-service@8 {
6040 3586 compatible = "qcom,q6adm";
6041 3587 reg = <APR_SVC_ADM>;
6042 3588 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 3589 q6routing: routing {
6044 3590 compatible = "qcom,q6adm-routing";
6045 3591 #sound-dai-cells = <0>;
6046 3592 };
6047 }; 3593 };
6048 }; 3594 };
6049 3595
6050 fastrpc { 3596 fastrpc {
6051 compa 3597 compatible = "qcom,fastrpc";
6052 qcom, 3598 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 3599 label = "adsp";
6054 qcom, <<
6055 #addr 3600 #address-cells = <1>;
6056 #size 3601 #size-cells = <0>;
6057 3602
6058 compu 3603 compute-cb@3 {
6059 3604 compatible = "qcom,fastrpc-compute-cb";
6060 3605 reg = <3>;
6061 3606 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 3607 };
6063 3608
6064 compu 3609 compute-cb@4 {
6065 3610 compatible = "qcom,fastrpc-compute-cb";
6066 3611 reg = <4>;
6067 3612 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 3613 };
6069 3614
6070 compu 3615 compute-cb@5 {
6071 3616 compatible = "qcom,fastrpc-compute-cb";
6072 3617 reg = <5>;
6073 3618 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 3619 };
6075 }; 3620 };
6076 }; 3621 };
6077 }; 3622 };
6078 3623
6079 intc: interrupt-controller@17 3624 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 3625 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 3626 #interrupt-cells = <3>;
6082 interrupt-controller; 3627 interrupt-controller;
6083 reg = <0x0 0x17a00000 3628 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 3629 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 3630 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 3631 };
6087 3632
6088 watchdog@17c10000 { 3633 watchdog@17c10000 {
6089 compatible = "qcom,ap 3634 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 3635 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 3636 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 3637 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 3638 };
6094 3639
6095 timer@17c20000 { 3640 timer@17c20000 {
6096 #address-cells = <1>; !! 3641 #address-cells = <2>;
6097 #size-cells = <1>; !! 3642 #size-cells = <2>;
6098 ranges = <0 0 0 0x200 !! 3643 ranges;
6099 compatible = "arm,arm 3644 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 3645 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 3646 clock-frequency = <19200000>;
6102 3647
6103 frame@17c21000 { 3648 frame@17c21000 {
6104 frame-number 3649 frame-number = <0>;
6105 interrupts = 3650 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 3651 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 !! 3652 reg = <0x0 0x17c21000 0x0 0x1000>,
6108 <0x17c2 !! 3653 <0x0 0x17c22000 0x0 0x1000>;
6109 }; 3654 };
6110 3655
6111 frame@17c23000 { 3656 frame@17c23000 {
6112 frame-number 3657 frame-number = <1>;
6113 interrupts = 3658 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 !! 3659 reg = <0x0 0x17c23000 0x0 0x1000>;
6115 status = "dis 3660 status = "disabled";
6116 }; 3661 };
6117 3662
6118 frame@17c25000 { 3663 frame@17c25000 {
6119 frame-number 3664 frame-number = <2>;
6120 interrupts = 3665 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 !! 3666 reg = <0x0 0x17c25000 0x0 0x1000>;
6122 status = "dis 3667 status = "disabled";
6123 }; 3668 };
6124 3669
6125 frame@17c27000 { 3670 frame@17c27000 {
6126 frame-number 3671 frame-number = <3>;
6127 interrupts = 3672 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 !! 3673 reg = <0x0 0x17c27000 0x0 0x1000>;
6129 status = "dis 3674 status = "disabled";
6130 }; 3675 };
6131 3676
6132 frame@17c29000 { 3677 frame@17c29000 {
6133 frame-number 3678 frame-number = <4>;
6134 interrupts = 3679 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 !! 3680 reg = <0x0 0x17c29000 0x0 0x1000>;
6136 status = "dis 3681 status = "disabled";
6137 }; 3682 };
6138 3683
6139 frame@17c2b000 { 3684 frame@17c2b000 {
6140 frame-number 3685 frame-number = <5>;
6141 interrupts = 3686 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 !! 3687 reg = <0x0 0x17c2b000 0x0 0x1000>;
6143 status = "dis 3688 status = "disabled";
6144 }; 3689 };
6145 3690
6146 frame@17c2d000 { 3691 frame@17c2d000 {
6147 frame-number 3692 frame-number = <6>;
6148 interrupts = 3693 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 !! 3694 reg = <0x0 0x17c2d000 0x0 0x1000>;
6150 status = "dis 3695 status = "disabled";
6151 }; 3696 };
6152 }; 3697 };
6153 3698
6154 apps_rsc: rsc@18200000 { 3699 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 3700 label = "apps_rsc";
6156 compatible = "qcom,rp 3701 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 3702 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 3703 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 3704 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 3705 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 3706 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 3707 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 3708 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 3709 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 3710 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 3711 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 3712 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 3713
6170 rpmhcc: clock-control 3714 rpmhcc: clock-controller {
6171 compatible = 3715 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 3716 #clock-cells = <1>;
6173 clock-names = 3717 clock-names = "xo";
6174 clocks = <&xo 3718 clocks = <&xo_board>;
6175 }; 3719 };
6176 3720
6177 rpmhpd: power-control 3721 rpmhpd: power-controller {
6178 compatible = 3722 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 3723 #power-domain-cells = <1>;
6180 operating-poi 3724 operating-points-v2 = <&rpmhpd_opp_table>;
6181 3725
6182 rpmhpd_opp_ta 3726 rpmhpd_opp_table: opp-table {
6183 compa 3727 compatible = "operating-points-v2";
6184 3728
6185 rpmhp 3729 rpmhpd_opp_ret: opp1 {
6186 3730 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 3731 };
6188 3732
6189 rpmhp 3733 rpmhpd_opp_min_svs: opp2 {
6190 3734 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 3735 };
6192 3736
6193 rpmhp 3737 rpmhpd_opp_low_svs: opp3 {
6194 3738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 3739 };
6196 3740
6197 rpmhp 3741 rpmhpd_opp_svs: opp4 {
6198 3742 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 3743 };
6200 3744
6201 rpmhp 3745 rpmhpd_opp_svs_l1: opp5 {
6202 3746 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 3747 };
6204 3748
6205 rpmhp 3749 rpmhpd_opp_nom: opp6 {
6206 3750 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 3751 };
6208 3752
6209 rpmhp 3753 rpmhpd_opp_nom_l1: opp7 {
6210 3754 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 3755 };
6212 3756
6213 rpmhp 3757 rpmhpd_opp_nom_l2: opp8 {
6214 3758 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 3759 };
6216 3760
6217 rpmhp 3761 rpmhpd_opp_turbo: opp9 {
6218 3762 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 3763 };
6220 3764
6221 rpmhp 3765 rpmhpd_opp_turbo_l1: opp10 {
6222 3766 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 3767 };
6224 }; 3768 };
6225 }; 3769 };
6226 3770
6227 apps_bcm_voter: bcm-v !! 3771 apps_bcm_voter: bcm_voter {
6228 compatible = 3772 compatible = "qcom,bcm-voter";
6229 }; 3773 };
6230 }; 3774 };
6231 3775
6232 epss_l3: interconnect@1859000 3776 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 3777 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 3778 reg = <0 0x18590000 0 0x1000>;
6235 3779
6236 clocks = <&rpmhcc RPM 3780 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 3781 clock-names = "xo", "alternate";
6238 3782
6239 #interconnect-cells = 3783 #interconnect-cells = <1>;
6240 }; 3784 };
6241 3785
6242 cpufreq_hw: cpufreq@18591000 3786 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 3787 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 3788 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 3789 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 3790 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 3791 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 3792 "freq-domain2";
6249 3793
6250 clocks = <&rpmhcc RPM 3794 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 3795 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI !! 3796
6253 <GIC_SPI <<
6254 <GIC_SPI <<
6255 interrupt-names = "dc <<
6256 #freq-domain-cells = 3797 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 3798 };
6259 }; 3799 };
6260 3800
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 3801 timer {
6265 compatible = "arm,armv8-timer 3802 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 3803 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 3804 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 3805 <GIC_PPI 14
6269 (GIC_CPU_MASK 3806 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 3807 <GIC_PPI 11
6271 (GIC_CPU_MASK 3808 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 3809 <GIC_PPI 10
6273 (GIC_CPU_MASK 3810 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 3811 };
6275 3812
6276 thermal-zones { 3813 thermal-zones {
6277 cpu0-thermal { 3814 cpu0-thermal {
6278 polling-delay-passive 3815 polling-delay-passive = <250>;
>> 3816 polling-delay = <1000>;
6279 3817
6280 thermal-sensors = <&t 3818 thermal-sensors = <&tsens0 1>;
6281 3819
6282 trips { 3820 trips {
6283 cpu0_alert0: 3821 cpu0_alert0: trip-point0 {
6284 tempe 3822 temperature = <90000>;
6285 hyste 3823 hysteresis = <2000>;
6286 type 3824 type = "passive";
6287 }; 3825 };
6288 3826
6289 cpu0_alert1: 3827 cpu0_alert1: trip-point1 {
6290 tempe 3828 temperature = <95000>;
6291 hyste 3829 hysteresis = <2000>;
6292 type 3830 type = "passive";
6293 }; 3831 };
6294 3832
6295 cpu0_crit: cp !! 3833 cpu0_crit: cpu_crit {
6296 tempe 3834 temperature = <110000>;
6297 hyste 3835 hysteresis = <1000>;
6298 type 3836 type = "critical";
6299 }; 3837 };
6300 }; 3838 };
6301 3839
6302 cooling-maps { 3840 cooling-maps {
6303 map0 { 3841 map0 {
6304 trip 3842 trip = <&cpu0_alert0>;
6305 cooli 3843 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 3844 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 3845 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 3846 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 3847 };
6310 map1 { 3848 map1 {
6311 trip 3849 trip = <&cpu0_alert1>;
6312 cooli 3850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 3851 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 3852 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 3853 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 3854 };
6317 }; 3855 };
6318 }; 3856 };
6319 3857
6320 cpu1-thermal { 3858 cpu1-thermal {
6321 polling-delay-passive 3859 polling-delay-passive = <250>;
>> 3860 polling-delay = <1000>;
6322 3861
6323 thermal-sensors = <&t 3862 thermal-sensors = <&tsens0 2>;
6324 3863
6325 trips { 3864 trips {
6326 cpu1_alert0: 3865 cpu1_alert0: trip-point0 {
6327 tempe 3866 temperature = <90000>;
6328 hyste 3867 hysteresis = <2000>;
6329 type 3868 type = "passive";
6330 }; 3869 };
6331 3870
6332 cpu1_alert1: 3871 cpu1_alert1: trip-point1 {
6333 tempe 3872 temperature = <95000>;
6334 hyste 3873 hysteresis = <2000>;
6335 type 3874 type = "passive";
6336 }; 3875 };
6337 3876
6338 cpu1_crit: cp !! 3877 cpu1_crit: cpu_crit {
6339 tempe 3878 temperature = <110000>;
6340 hyste 3879 hysteresis = <1000>;
6341 type 3880 type = "critical";
6342 }; 3881 };
6343 }; 3882 };
6344 3883
6345 cooling-maps { 3884 cooling-maps {
6346 map0 { 3885 map0 {
6347 trip 3886 trip = <&cpu1_alert0>;
6348 cooli 3887 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 3888 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 3889 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 3890 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 3891 };
6353 map1 { 3892 map1 {
6354 trip 3893 trip = <&cpu1_alert1>;
6355 cooli 3894 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 3895 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 3896 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 3897 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 3898 };
6360 }; 3899 };
6361 }; 3900 };
6362 3901
6363 cpu2-thermal { 3902 cpu2-thermal {
6364 polling-delay-passive 3903 polling-delay-passive = <250>;
>> 3904 polling-delay = <1000>;
6365 3905
6366 thermal-sensors = <&t 3906 thermal-sensors = <&tsens0 3>;
6367 3907
6368 trips { 3908 trips {
6369 cpu2_alert0: 3909 cpu2_alert0: trip-point0 {
6370 tempe 3910 temperature = <90000>;
6371 hyste 3911 hysteresis = <2000>;
6372 type 3912 type = "passive";
6373 }; 3913 };
6374 3914
6375 cpu2_alert1: 3915 cpu2_alert1: trip-point1 {
6376 tempe 3916 temperature = <95000>;
6377 hyste 3917 hysteresis = <2000>;
6378 type 3918 type = "passive";
6379 }; 3919 };
6380 3920
6381 cpu2_crit: cp !! 3921 cpu2_crit: cpu_crit {
6382 tempe 3922 temperature = <110000>;
6383 hyste 3923 hysteresis = <1000>;
6384 type 3924 type = "critical";
6385 }; 3925 };
6386 }; 3926 };
6387 3927
6388 cooling-maps { 3928 cooling-maps {
6389 map0 { 3929 map0 {
6390 trip 3930 trip = <&cpu2_alert0>;
6391 cooli 3931 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 3932 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 3933 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 3934 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 3935 };
6396 map1 { 3936 map1 {
6397 trip 3937 trip = <&cpu2_alert1>;
6398 cooli 3938 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 3939 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 3940 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 3941 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 3942 };
6403 }; 3943 };
6404 }; 3944 };
6405 3945
6406 cpu3-thermal { 3946 cpu3-thermal {
6407 polling-delay-passive 3947 polling-delay-passive = <250>;
>> 3948 polling-delay = <1000>;
6408 3949
6409 thermal-sensors = <&t 3950 thermal-sensors = <&tsens0 4>;
6410 3951
6411 trips { 3952 trips {
6412 cpu3_alert0: 3953 cpu3_alert0: trip-point0 {
6413 tempe 3954 temperature = <90000>;
6414 hyste 3955 hysteresis = <2000>;
6415 type 3956 type = "passive";
6416 }; 3957 };
6417 3958
6418 cpu3_alert1: 3959 cpu3_alert1: trip-point1 {
6419 tempe 3960 temperature = <95000>;
6420 hyste 3961 hysteresis = <2000>;
6421 type 3962 type = "passive";
6422 }; 3963 };
6423 3964
6424 cpu3_crit: cp !! 3965 cpu3_crit: cpu_crit {
6425 tempe 3966 temperature = <110000>;
6426 hyste 3967 hysteresis = <1000>;
6427 type 3968 type = "critical";
6428 }; 3969 };
6429 }; 3970 };
6430 3971
6431 cooling-maps { 3972 cooling-maps {
6432 map0 { 3973 map0 {
6433 trip 3974 trip = <&cpu3_alert0>;
6434 cooli 3975 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 3976 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 3977 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 3978 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 3979 };
6439 map1 { 3980 map1 {
6440 trip 3981 trip = <&cpu3_alert1>;
6441 cooli 3982 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 3983 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 3984 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 3985 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 3986 };
6446 }; 3987 };
6447 }; 3988 };
6448 3989
6449 cpu4-top-thermal { 3990 cpu4-top-thermal {
6450 polling-delay-passive 3991 polling-delay-passive = <250>;
>> 3992 polling-delay = <1000>;
6451 3993
6452 thermal-sensors = <&t 3994 thermal-sensors = <&tsens0 7>;
6453 3995
6454 trips { 3996 trips {
6455 cpu4_top_aler 3997 cpu4_top_alert0: trip-point0 {
6456 tempe 3998 temperature = <90000>;
6457 hyste 3999 hysteresis = <2000>;
6458 type 4000 type = "passive";
6459 }; 4001 };
6460 4002
6461 cpu4_top_aler 4003 cpu4_top_alert1: trip-point1 {
6462 tempe 4004 temperature = <95000>;
6463 hyste 4005 hysteresis = <2000>;
6464 type 4006 type = "passive";
6465 }; 4007 };
6466 4008
6467 cpu4_top_crit !! 4009 cpu4_top_crit: cpu_crit {
6468 tempe 4010 temperature = <110000>;
6469 hyste 4011 hysteresis = <1000>;
6470 type 4012 type = "critical";
6471 }; 4013 };
6472 }; 4014 };
6473 4015
6474 cooling-maps { 4016 cooling-maps {
6475 map0 { 4017 map0 {
6476 trip 4018 trip = <&cpu4_top_alert0>;
6477 cooli 4019 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 4020 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 4021 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 4022 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 4023 };
6482 map1 { 4024 map1 {
6483 trip 4025 trip = <&cpu4_top_alert1>;
6484 cooli 4026 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 4027 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 4028 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 4029 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 4030 };
6489 }; 4031 };
6490 }; 4032 };
6491 4033
6492 cpu5-top-thermal { 4034 cpu5-top-thermal {
6493 polling-delay-passive 4035 polling-delay-passive = <250>;
>> 4036 polling-delay = <1000>;
6494 4037
6495 thermal-sensors = <&t 4038 thermal-sensors = <&tsens0 8>;
6496 4039
6497 trips { 4040 trips {
6498 cpu5_top_aler 4041 cpu5_top_alert0: trip-point0 {
6499 tempe 4042 temperature = <90000>;
6500 hyste 4043 hysteresis = <2000>;
6501 type 4044 type = "passive";
6502 }; 4045 };
6503 4046
6504 cpu5_top_aler 4047 cpu5_top_alert1: trip-point1 {
6505 tempe 4048 temperature = <95000>;
6506 hyste 4049 hysteresis = <2000>;
6507 type 4050 type = "passive";
6508 }; 4051 };
6509 4052
6510 cpu5_top_crit !! 4053 cpu5_top_crit: cpu_crit {
6511 tempe 4054 temperature = <110000>;
6512 hyste 4055 hysteresis = <1000>;
6513 type 4056 type = "critical";
6514 }; 4057 };
6515 }; 4058 };
6516 4059
6517 cooling-maps { 4060 cooling-maps {
6518 map0 { 4061 map0 {
6519 trip 4062 trip = <&cpu5_top_alert0>;
6520 cooli 4063 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 4064 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 4065 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 4066 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4067 };
6525 map1 { 4068 map1 {
6526 trip 4069 trip = <&cpu5_top_alert1>;
6527 cooli 4070 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4071 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4072 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4073 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4074 };
6532 }; 4075 };
6533 }; 4076 };
6534 4077
6535 cpu6-top-thermal { 4078 cpu6-top-thermal {
6536 polling-delay-passive 4079 polling-delay-passive = <250>;
>> 4080 polling-delay = <1000>;
6537 4081
6538 thermal-sensors = <&t 4082 thermal-sensors = <&tsens0 9>;
6539 4083
6540 trips { 4084 trips {
6541 cpu6_top_aler 4085 cpu6_top_alert0: trip-point0 {
6542 tempe 4086 temperature = <90000>;
6543 hyste 4087 hysteresis = <2000>;
6544 type 4088 type = "passive";
6545 }; 4089 };
6546 4090
6547 cpu6_top_aler 4091 cpu6_top_alert1: trip-point1 {
6548 tempe 4092 temperature = <95000>;
6549 hyste 4093 hysteresis = <2000>;
6550 type 4094 type = "passive";
6551 }; 4095 };
6552 4096
6553 cpu6_top_crit !! 4097 cpu6_top_crit: cpu_crit {
6554 tempe 4098 temperature = <110000>;
6555 hyste 4099 hysteresis = <1000>;
6556 type 4100 type = "critical";
6557 }; 4101 };
6558 }; 4102 };
6559 4103
6560 cooling-maps { 4104 cooling-maps {
6561 map0 { 4105 map0 {
6562 trip 4106 trip = <&cpu6_top_alert0>;
6563 cooli 4107 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 4108 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 4109 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 4110 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 4111 };
6568 map1 { 4112 map1 {
6569 trip 4113 trip = <&cpu6_top_alert1>;
6570 cooli 4114 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 4115 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 4116 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 4117 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 4118 };
6575 }; 4119 };
6576 }; 4120 };
6577 4121
6578 cpu7-top-thermal { 4122 cpu7-top-thermal {
6579 polling-delay-passive 4123 polling-delay-passive = <250>;
>> 4124 polling-delay = <1000>;
6580 4125
6581 thermal-sensors = <&t 4126 thermal-sensors = <&tsens0 10>;
6582 4127
6583 trips { 4128 trips {
6584 cpu7_top_aler 4129 cpu7_top_alert0: trip-point0 {
6585 tempe 4130 temperature = <90000>;
6586 hyste 4131 hysteresis = <2000>;
6587 type 4132 type = "passive";
6588 }; 4133 };
6589 4134
6590 cpu7_top_aler 4135 cpu7_top_alert1: trip-point1 {
6591 tempe 4136 temperature = <95000>;
6592 hyste 4137 hysteresis = <2000>;
6593 type 4138 type = "passive";
6594 }; 4139 };
6595 4140
6596 cpu7_top_crit !! 4141 cpu7_top_crit: cpu_crit {
6597 tempe 4142 temperature = <110000>;
6598 hyste 4143 hysteresis = <1000>;
6599 type 4144 type = "critical";
6600 }; 4145 };
6601 }; 4146 };
6602 4147
6603 cooling-maps { 4148 cooling-maps {
6604 map0 { 4149 map0 {
6605 trip 4150 trip = <&cpu7_top_alert0>;
6606 cooli 4151 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 4152 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 4153 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 4154 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 4155 };
6611 map1 { 4156 map1 {
6612 trip 4157 trip = <&cpu7_top_alert1>;
6613 cooli 4158 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 4159 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 4160 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 4161 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 4162 };
6618 }; 4163 };
6619 }; 4164 };
6620 4165
6621 cpu4-bottom-thermal { 4166 cpu4-bottom-thermal {
6622 polling-delay-passive 4167 polling-delay-passive = <250>;
>> 4168 polling-delay = <1000>;
6623 4169
6624 thermal-sensors = <&t 4170 thermal-sensors = <&tsens0 11>;
6625 4171
6626 trips { 4172 trips {
6627 cpu4_bottom_a 4173 cpu4_bottom_alert0: trip-point0 {
6628 tempe 4174 temperature = <90000>;
6629 hyste 4175 hysteresis = <2000>;
6630 type 4176 type = "passive";
6631 }; 4177 };
6632 4178
6633 cpu4_bottom_a 4179 cpu4_bottom_alert1: trip-point1 {
6634 tempe 4180 temperature = <95000>;
6635 hyste 4181 hysteresis = <2000>;
6636 type 4182 type = "passive";
6637 }; 4183 };
6638 4184
6639 cpu4_bottom_c !! 4185 cpu4_bottom_crit: cpu_crit {
6640 tempe 4186 temperature = <110000>;
6641 hyste 4187 hysteresis = <1000>;
6642 type 4188 type = "critical";
6643 }; 4189 };
6644 }; 4190 };
6645 4191
6646 cooling-maps { 4192 cooling-maps {
6647 map0 { 4193 map0 {
6648 trip 4194 trip = <&cpu4_bottom_alert0>;
6649 cooli 4195 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 4196 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 4197 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 4198 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 4199 };
6654 map1 { 4200 map1 {
6655 trip 4201 trip = <&cpu4_bottom_alert1>;
6656 cooli 4202 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 4203 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 4204 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 4205 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 4206 };
6661 }; 4207 };
6662 }; 4208 };
6663 4209
6664 cpu5-bottom-thermal { 4210 cpu5-bottom-thermal {
6665 polling-delay-passive 4211 polling-delay-passive = <250>;
>> 4212 polling-delay = <1000>;
6666 4213
6667 thermal-sensors = <&t 4214 thermal-sensors = <&tsens0 12>;
6668 4215
6669 trips { 4216 trips {
6670 cpu5_bottom_a 4217 cpu5_bottom_alert0: trip-point0 {
6671 tempe 4218 temperature = <90000>;
6672 hyste 4219 hysteresis = <2000>;
6673 type 4220 type = "passive";
6674 }; 4221 };
6675 4222
6676 cpu5_bottom_a 4223 cpu5_bottom_alert1: trip-point1 {
6677 tempe 4224 temperature = <95000>;
6678 hyste 4225 hysteresis = <2000>;
6679 type 4226 type = "passive";
6680 }; 4227 };
6681 4228
6682 cpu5_bottom_c !! 4229 cpu5_bottom_crit: cpu_crit {
6683 tempe 4230 temperature = <110000>;
6684 hyste 4231 hysteresis = <1000>;
6685 type 4232 type = "critical";
6686 }; 4233 };
6687 }; 4234 };
6688 4235
6689 cooling-maps { 4236 cooling-maps {
6690 map0 { 4237 map0 {
6691 trip 4238 trip = <&cpu5_bottom_alert0>;
6692 cooli 4239 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 4240 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 4241 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 4242 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 4243 };
6697 map1 { 4244 map1 {
6698 trip 4245 trip = <&cpu5_bottom_alert1>;
6699 cooli 4246 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 4247 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 4248 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 4249 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 4250 };
6704 }; 4251 };
6705 }; 4252 };
6706 4253
6707 cpu6-bottom-thermal { 4254 cpu6-bottom-thermal {
6708 polling-delay-passive 4255 polling-delay-passive = <250>;
>> 4256 polling-delay = <1000>;
6709 4257
6710 thermal-sensors = <&t 4258 thermal-sensors = <&tsens0 13>;
6711 4259
6712 trips { 4260 trips {
6713 cpu6_bottom_a 4261 cpu6_bottom_alert0: trip-point0 {
6714 tempe 4262 temperature = <90000>;
6715 hyste 4263 hysteresis = <2000>;
6716 type 4264 type = "passive";
6717 }; 4265 };
6718 4266
6719 cpu6_bottom_a 4267 cpu6_bottom_alert1: trip-point1 {
6720 tempe 4268 temperature = <95000>;
6721 hyste 4269 hysteresis = <2000>;
6722 type 4270 type = "passive";
6723 }; 4271 };
6724 4272
6725 cpu6_bottom_c !! 4273 cpu6_bottom_crit: cpu_crit {
6726 tempe 4274 temperature = <110000>;
6727 hyste 4275 hysteresis = <1000>;
6728 type 4276 type = "critical";
6729 }; 4277 };
6730 }; 4278 };
6731 4279
6732 cooling-maps { 4280 cooling-maps {
6733 map0 { 4281 map0 {
6734 trip 4282 trip = <&cpu6_bottom_alert0>;
6735 cooli 4283 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 4284 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 4285 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 4286 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 4287 };
6740 map1 { 4288 map1 {
6741 trip 4289 trip = <&cpu6_bottom_alert1>;
6742 cooli 4290 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 4291 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 4292 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 4293 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 4294 };
6747 }; 4295 };
6748 }; 4296 };
6749 4297
6750 cpu7-bottom-thermal { 4298 cpu7-bottom-thermal {
6751 polling-delay-passive 4299 polling-delay-passive = <250>;
>> 4300 polling-delay = <1000>;
6752 4301
6753 thermal-sensors = <&t 4302 thermal-sensors = <&tsens0 14>;
6754 4303
6755 trips { 4304 trips {
6756 cpu7_bottom_a 4305 cpu7_bottom_alert0: trip-point0 {
6757 tempe 4306 temperature = <90000>;
6758 hyste 4307 hysteresis = <2000>;
6759 type 4308 type = "passive";
6760 }; 4309 };
6761 4310
6762 cpu7_bottom_a 4311 cpu7_bottom_alert1: trip-point1 {
6763 tempe 4312 temperature = <95000>;
6764 hyste 4313 hysteresis = <2000>;
6765 type 4314 type = "passive";
6766 }; 4315 };
6767 4316
6768 cpu7_bottom_c !! 4317 cpu7_bottom_crit: cpu_crit {
6769 tempe 4318 temperature = <110000>;
6770 hyste 4319 hysteresis = <1000>;
6771 type 4320 type = "critical";
6772 }; 4321 };
6773 }; 4322 };
6774 4323
6775 cooling-maps { 4324 cooling-maps {
6776 map0 { 4325 map0 {
6777 trip 4326 trip = <&cpu7_bottom_alert0>;
6778 cooli 4327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 4328 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 4329 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 4330 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 4331 };
6783 map1 { 4332 map1 {
6784 trip 4333 trip = <&cpu7_bottom_alert1>;
6785 cooli 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 4338 };
6790 }; 4339 };
6791 }; 4340 };
6792 4341
6793 aoss0-thermal { 4342 aoss0-thermal {
6794 polling-delay-passive 4343 polling-delay-passive = <250>;
>> 4344 polling-delay = <1000>;
6795 4345
6796 thermal-sensors = <&t 4346 thermal-sensors = <&tsens0 0>;
6797 4347
6798 trips { 4348 trips {
6799 aoss0_alert0: 4349 aoss0_alert0: trip-point0 {
6800 tempe 4350 temperature = <90000>;
6801 hyste 4351 hysteresis = <2000>;
6802 type 4352 type = "hot";
6803 }; 4353 };
6804 }; 4354 };
6805 }; 4355 };
6806 4356
6807 cluster0-thermal { 4357 cluster0-thermal {
6808 polling-delay-passive 4358 polling-delay-passive = <250>;
>> 4359 polling-delay = <1000>;
6809 4360
6810 thermal-sensors = <&t 4361 thermal-sensors = <&tsens0 5>;
6811 4362
6812 trips { 4363 trips {
6813 cluster0_aler 4364 cluster0_alert0: trip-point0 {
6814 tempe 4365 temperature = <90000>;
6815 hyste 4366 hysteresis = <2000>;
6816 type 4367 type = "hot";
6817 }; 4368 };
6818 cluster0_crit !! 4369 cluster0_crit: cluster0_crit {
6819 tempe 4370 temperature = <110000>;
6820 hyste 4371 hysteresis = <2000>;
6821 type 4372 type = "critical";
6822 }; 4373 };
6823 }; 4374 };
6824 }; 4375 };
6825 4376
6826 cluster1-thermal { 4377 cluster1-thermal {
6827 polling-delay-passive 4378 polling-delay-passive = <250>;
>> 4379 polling-delay = <1000>;
6828 4380
6829 thermal-sensors = <&t 4381 thermal-sensors = <&tsens0 6>;
6830 4382
6831 trips { 4383 trips {
6832 cluster1_aler 4384 cluster1_alert0: trip-point0 {
6833 tempe 4385 temperature = <90000>;
6834 hyste 4386 hysteresis = <2000>;
6835 type 4387 type = "hot";
6836 }; 4388 };
6837 cluster1_crit !! 4389 cluster1_crit: cluster1_crit {
6838 tempe 4390 temperature = <110000>;
6839 hyste 4391 hysteresis = <2000>;
6840 type 4392 type = "critical";
6841 }; 4393 };
6842 }; 4394 };
6843 }; 4395 };
6844 4396
6845 gpu-top-thermal { !! 4397 gpu-thermal-top {
6846 polling-delay-passive 4398 polling-delay-passive = <250>;
>> 4399 polling-delay = <1000>;
6847 4400
6848 thermal-sensors = <&t 4401 thermal-sensors = <&tsens0 15>;
6849 4402
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 4403 trips {
6858 gpu_top_alert !! 4404 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 4405 temperature = <90000>;
6866 hyste !! 4406 hysteresis = <2000>;
6867 type 4407 type = "hot";
6868 }; 4408 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 4409 };
6876 }; 4410 };
6877 4411
6878 aoss1-thermal { 4412 aoss1-thermal {
6879 polling-delay-passive 4413 polling-delay-passive = <250>;
>> 4414 polling-delay = <1000>;
6880 4415
6881 thermal-sensors = <&t 4416 thermal-sensors = <&tsens1 0>;
6882 4417
6883 trips { 4418 trips {
6884 aoss1_alert0: 4419 aoss1_alert0: trip-point0 {
6885 tempe 4420 temperature = <90000>;
6886 hyste 4421 hysteresis = <2000>;
6887 type 4422 type = "hot";
6888 }; 4423 };
6889 }; 4424 };
6890 }; 4425 };
6891 4426
6892 wlan-thermal { 4427 wlan-thermal {
6893 polling-delay-passive 4428 polling-delay-passive = <250>;
>> 4429 polling-delay = <1000>;
6894 4430
6895 thermal-sensors = <&t 4431 thermal-sensors = <&tsens1 1>;
6896 4432
6897 trips { 4433 trips {
6898 wlan_alert0: 4434 wlan_alert0: trip-point0 {
6899 tempe 4435 temperature = <90000>;
6900 hyste 4436 hysteresis = <2000>;
6901 type 4437 type = "hot";
6902 }; 4438 };
6903 }; 4439 };
6904 }; 4440 };
6905 4441
6906 video-thermal { 4442 video-thermal {
6907 polling-delay-passive 4443 polling-delay-passive = <250>;
>> 4444 polling-delay = <1000>;
6908 4445
6909 thermal-sensors = <&t 4446 thermal-sensors = <&tsens1 2>;
6910 4447
6911 trips { 4448 trips {
6912 video_alert0: 4449 video_alert0: trip-point0 {
6913 tempe 4450 temperature = <90000>;
6914 hyste 4451 hysteresis = <2000>;
6915 type 4452 type = "hot";
6916 }; 4453 };
6917 }; 4454 };
6918 }; 4455 };
6919 4456
6920 mem-thermal { 4457 mem-thermal {
6921 polling-delay-passive 4458 polling-delay-passive = <250>;
>> 4459 polling-delay = <1000>;
6922 4460
6923 thermal-sensors = <&t 4461 thermal-sensors = <&tsens1 3>;
6924 4462
6925 trips { 4463 trips {
6926 mem_alert0: t 4464 mem_alert0: trip-point0 {
6927 tempe 4465 temperature = <90000>;
6928 hyste 4466 hysteresis = <2000>;
6929 type 4467 type = "hot";
6930 }; 4468 };
6931 }; 4469 };
6932 }; 4470 };
6933 4471
6934 q6-hvx-thermal { 4472 q6-hvx-thermal {
6935 polling-delay-passive 4473 polling-delay-passive = <250>;
>> 4474 polling-delay = <1000>;
6936 4475
6937 thermal-sensors = <&t 4476 thermal-sensors = <&tsens1 4>;
6938 4477
6939 trips { 4478 trips {
6940 q6_hvx_alert0 4479 q6_hvx_alert0: trip-point0 {
6941 tempe 4480 temperature = <90000>;
6942 hyste 4481 hysteresis = <2000>;
6943 type 4482 type = "hot";
6944 }; 4483 };
6945 }; 4484 };
6946 }; 4485 };
6947 4486
6948 camera-thermal { 4487 camera-thermal {
6949 polling-delay-passive 4488 polling-delay-passive = <250>;
>> 4489 polling-delay = <1000>;
6950 4490
6951 thermal-sensors = <&t 4491 thermal-sensors = <&tsens1 5>;
6952 4492
6953 trips { 4493 trips {
6954 camera_alert0 4494 camera_alert0: trip-point0 {
6955 tempe 4495 temperature = <90000>;
6956 hyste 4496 hysteresis = <2000>;
6957 type 4497 type = "hot";
6958 }; 4498 };
6959 }; 4499 };
6960 }; 4500 };
6961 4501
6962 compute-thermal { 4502 compute-thermal {
6963 polling-delay-passive 4503 polling-delay-passive = <250>;
>> 4504 polling-delay = <1000>;
6964 4505
6965 thermal-sensors = <&t 4506 thermal-sensors = <&tsens1 6>;
6966 4507
6967 trips { 4508 trips {
6968 compute_alert 4509 compute_alert0: trip-point0 {
6969 tempe 4510 temperature = <90000>;
6970 hyste 4511 hysteresis = <2000>;
6971 type 4512 type = "hot";
6972 }; 4513 };
6973 }; 4514 };
6974 }; 4515 };
6975 4516
6976 npu-thermal { 4517 npu-thermal {
6977 polling-delay-passive 4518 polling-delay-passive = <250>;
>> 4519 polling-delay = <1000>;
6978 4520
6979 thermal-sensors = <&t 4521 thermal-sensors = <&tsens1 7>;
6980 4522
6981 trips { 4523 trips {
6982 npu_alert0: t 4524 npu_alert0: trip-point0 {
6983 tempe 4525 temperature = <90000>;
6984 hyste 4526 hysteresis = <2000>;
6985 type 4527 type = "hot";
6986 }; 4528 };
6987 }; 4529 };
6988 }; 4530 };
6989 4531
6990 gpu-bottom-thermal { !! 4532 gpu-thermal-bottom {
6991 polling-delay-passive 4533 polling-delay-passive = <250>;
>> 4534 polling-delay = <1000>;
6992 4535
6993 thermal-sensors = <&t 4536 thermal-sensors = <&tsens1 8>;
6994 4537
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 4538 trips {
7003 gpu_bottom_al !! 4539 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 4540 temperature = <90000>;
7011 hyste !! 4541 hysteresis = <2000>;
7012 type 4542 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 4543 };
7020 }; 4544 };
7021 }; 4545 };
7022 }; 4546 };
7023 }; 4547 };
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