1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 16 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 18 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 20 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 21 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 23
26 / { 24 / {
27 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
28 26
29 #address-cells = <2>; 27 #address-cells = <2>;
30 #size-cells = <2>; 28 #size-cells = <2>;
31 29
32 aliases { 30 aliases {
33 i2c0 = &i2c0; 31 i2c0 = &i2c0;
34 i2c1 = &i2c1; 32 i2c1 = &i2c1;
35 i2c2 = &i2c2; 33 i2c2 = &i2c2;
36 i2c3 = &i2c3; 34 i2c3 = &i2c3;
37 i2c4 = &i2c4; 35 i2c4 = &i2c4;
38 i2c5 = &i2c5; 36 i2c5 = &i2c5;
39 i2c6 = &i2c6; 37 i2c6 = &i2c6;
40 i2c7 = &i2c7; 38 i2c7 = &i2c7;
41 i2c8 = &i2c8; 39 i2c8 = &i2c8;
42 i2c9 = &i2c9; 40 i2c9 = &i2c9;
43 i2c10 = &i2c10; 41 i2c10 = &i2c10;
44 i2c11 = &i2c11; 42 i2c11 = &i2c11;
45 i2c12 = &i2c12; 43 i2c12 = &i2c12;
46 i2c13 = &i2c13; 44 i2c13 = &i2c13;
47 i2c14 = &i2c14; 45 i2c14 = &i2c14;
48 i2c15 = &i2c15; 46 i2c15 = &i2c15;
49 i2c16 = &i2c16; 47 i2c16 = &i2c16;
50 i2c17 = &i2c17; 48 i2c17 = &i2c17;
51 i2c18 = &i2c18; 49 i2c18 = &i2c18;
52 i2c19 = &i2c19; 50 i2c19 = &i2c19;
53 spi0 = &spi0; 51 spi0 = &spi0;
54 spi1 = &spi1; 52 spi1 = &spi1;
55 spi2 = &spi2; 53 spi2 = &spi2;
56 spi3 = &spi3; 54 spi3 = &spi3;
57 spi4 = &spi4; 55 spi4 = &spi4;
58 spi5 = &spi5; 56 spi5 = &spi5;
59 spi6 = &spi6; 57 spi6 = &spi6;
60 spi7 = &spi7; 58 spi7 = &spi7;
61 spi8 = &spi8; 59 spi8 = &spi8;
62 spi9 = &spi9; 60 spi9 = &spi9;
63 spi10 = &spi10; 61 spi10 = &spi10;
64 spi11 = &spi11; 62 spi11 = &spi11;
65 spi12 = &spi12; 63 spi12 = &spi12;
66 spi13 = &spi13; 64 spi13 = &spi13;
67 spi14 = &spi14; 65 spi14 = &spi14;
68 spi15 = &spi15; 66 spi15 = &spi15;
69 spi16 = &spi16; 67 spi16 = &spi16;
70 spi17 = &spi17; 68 spi17 = &spi17;
71 spi18 = &spi18; 69 spi18 = &spi18;
72 spi19 = &spi19; 70 spi19 = &spi19;
73 }; 71 };
74 72
75 chosen { }; 73 chosen { };
76 74
77 clocks { 75 clocks {
78 xo_board: xo-board { 76 xo_board: xo-board {
79 compatible = "fixed-cl 77 compatible = "fixed-clock";
80 #clock-cells = <0>; 78 #clock-cells = <0>;
81 clock-frequency = <384 79 clock-frequency = <38400000>;
82 clock-output-names = " 80 clock-output-names = "xo_board";
83 }; 81 };
84 82
85 sleep_clk: sleep-clk { 83 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 84 compatible = "fixed-clock";
87 clock-frequency = <327 85 clock-frequency = <32768>;
88 #clock-cells = <0>; 86 #clock-cells = <0>;
89 }; 87 };
90 }; 88 };
91 89
92 cpus { 90 cpus {
93 #address-cells = <2>; 91 #address-cells = <2>;
94 #size-cells = <0>; 92 #size-cells = <0>;
95 93
96 CPU0: cpu@0 { 94 CPU0: cpu@0 {
97 device_type = "cpu"; 95 device_type = "cpu";
98 compatible = "qcom,kry 96 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 97 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 98 enable-method = "psci";
102 capacity-dmips-mhz = < 99 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 100 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 101 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ <<
106 power-domain-names = " <<
107 qcom,freq-domain = <&c 102 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <<
109 interconnects = <&gem_ <<
110 <&epss <<
111 #cooling-cells = <2>; 103 #cooling-cells = <2>;
112 L2_0: l2-cache { 104 L2_0: l2-cache {
113 compatible = " 105 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 106 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 107 L3_0: l3-cache {
119 compat 108 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 109 };
124 }; 110 };
125 }; 111 };
126 112
127 CPU1: cpu@100 { 113 CPU1: cpu@100 {
128 device_type = "cpu"; 114 device_type = "cpu";
129 compatible = "qcom,kry 115 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 116 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 117 enable-method = "psci";
133 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 119 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 120 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ <<
137 power-domain-names = " <<
138 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <<
140 interconnects = <&gem_ <<
141 <&epss <<
142 #cooling-cells = <2>; 122 #cooling-cells = <2>;
143 L2_100: l2-cache { 123 L2_100: l2-cache {
144 compatible = " 124 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 125 next-level-cache = <&L3_0>;
149 }; 126 };
150 }; 127 };
151 128
152 CPU2: cpu@200 { 129 CPU2: cpu@200 {
153 device_type = "cpu"; 130 device_type = "cpu";
154 compatible = "qcom,kry 131 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 132 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 133 enable-method = "psci";
158 capacity-dmips-mhz = < 134 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 135 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 136 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ <<
162 power-domain-names = " <<
163 qcom,freq-domain = <&c 137 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <<
165 interconnects = <&gem_ <<
166 <&epss <<
167 #cooling-cells = <2>; 138 #cooling-cells = <2>;
168 L2_200: l2-cache { 139 L2_200: l2-cache {
169 compatible = " 140 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 141 next-level-cache = <&L3_0>;
174 }; 142 };
175 }; 143 };
176 144
177 CPU3: cpu@300 { 145 CPU3: cpu@300 {
178 device_type = "cpu"; 146 device_type = "cpu";
179 compatible = "qcom,kry 147 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 148 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 149 enable-method = "psci";
183 capacity-dmips-mhz = < 150 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 151 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 152 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ <<
187 power-domain-names = " <<
188 qcom,freq-domain = <&c 153 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <<
190 interconnects = <&gem_ <<
191 <&epss <<
192 #cooling-cells = <2>; 154 #cooling-cells = <2>;
193 L2_300: l2-cache { 155 L2_300: l2-cache {
194 compatible = " 156 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 157 next-level-cache = <&L3_0>;
199 }; 158 };
200 }; 159 };
201 160
202 CPU4: cpu@400 { 161 CPU4: cpu@400 {
203 device_type = "cpu"; 162 device_type = "cpu";
204 compatible = "qcom,kry 163 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 164 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 165 enable-method = "psci";
208 capacity-dmips-mhz = < 166 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 167 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 168 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ <<
212 power-domain-names = " <<
213 qcom,freq-domain = <&c 169 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <<
215 interconnects = <&gem_ <<
216 <&epss <<
217 #cooling-cells = <2>; 170 #cooling-cells = <2>;
218 L2_400: l2-cache { 171 L2_400: l2-cache {
219 compatible = " 172 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 173 next-level-cache = <&L3_0>;
224 }; 174 };
225 }; 175 };
226 176
227 CPU5: cpu@500 { 177 CPU5: cpu@500 {
228 device_type = "cpu"; 178 device_type = "cpu";
229 compatible = "qcom,kry 179 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 180 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 181 enable-method = "psci";
233 capacity-dmips-mhz = < 182 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 183 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 184 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ <<
237 power-domain-names = " <<
238 qcom,freq-domain = <&c 185 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <<
240 interconnects = <&gem_ <<
241 <&epss <<
242 #cooling-cells = <2>; 186 #cooling-cells = <2>;
243 L2_500: l2-cache { 187 L2_500: l2-cache {
244 compatible = " 188 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 189 next-level-cache = <&L3_0>;
249 }; 190 };
>> 191
250 }; 192 };
251 193
252 CPU6: cpu@600 { 194 CPU6: cpu@600 {
253 device_type = "cpu"; 195 device_type = "cpu";
254 compatible = "qcom,kry 196 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 197 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 198 enable-method = "psci";
258 capacity-dmips-mhz = < 199 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 200 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 201 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ <<
262 power-domain-names = " <<
263 qcom,freq-domain = <&c 202 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <<
265 interconnects = <&gem_ <<
266 <&epss <<
267 #cooling-cells = <2>; 203 #cooling-cells = <2>;
268 L2_600: l2-cache { 204 L2_600: l2-cache {
269 compatible = " 205 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 206 next-level-cache = <&L3_0>;
274 }; 207 };
275 }; 208 };
276 209
277 CPU7: cpu@700 { 210 CPU7: cpu@700 {
278 device_type = "cpu"; 211 device_type = "cpu";
279 compatible = "qcom,kry 212 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 213 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 214 enable-method = "psci";
283 capacity-dmips-mhz = < 215 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 216 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 217 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ <<
287 power-domain-names = " <<
288 qcom,freq-domain = <&c 218 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <<
290 interconnects = <&gem_ <<
291 <&epss <<
292 #cooling-cells = <2>; 219 #cooling-cells = <2>;
293 L2_700: l2-cache { 220 L2_700: l2-cache {
294 compatible = " 221 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 222 next-level-cache = <&L3_0>;
299 }; 223 };
300 }; 224 };
301 225
302 cpu-map { 226 cpu-map {
303 cluster0 { 227 cluster0 {
304 core0 { 228 core0 {
305 cpu = 229 cpu = <&CPU0>;
306 }; 230 };
307 231
308 core1 { 232 core1 {
309 cpu = 233 cpu = <&CPU1>;
310 }; 234 };
311 235
312 core2 { 236 core2 {
313 cpu = 237 cpu = <&CPU2>;
314 }; 238 };
315 239
316 core3 { 240 core3 {
317 cpu = 241 cpu = <&CPU3>;
318 }; 242 };
319 243
320 core4 { 244 core4 {
321 cpu = 245 cpu = <&CPU4>;
322 }; 246 };
323 247
324 core5 { 248 core5 {
325 cpu = 249 cpu = <&CPU5>;
326 }; 250 };
327 251
328 core6 { 252 core6 {
329 cpu = 253 cpu = <&CPU6>;
330 }; 254 };
331 255
332 core7 { 256 core7 {
333 cpu = 257 cpu = <&CPU7>;
334 }; 258 };
335 }; 259 };
336 }; 260 };
337 <<
338 idle-states { <<
339 entry-method = "psci"; <<
340 <<
341 LITTLE_CPU_SLEEP_0: cp <<
342 compatible = " <<
343 idle-state-nam <<
344 arm,psci-suspe <<
345 entry-latency- <<
346 exit-latency-u <<
347 min-residency- <<
348 local-timer-st <<
349 }; <<
350 <<
351 BIG_CPU_SLEEP_0: cpu-s <<
352 compatible = " <<
353 idle-state-nam <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 local-timer-st <<
359 }; <<
360 }; <<
361 <<
362 domain-idle-states { <<
363 CLUSTER_SLEEP_0: clust <<
364 compatible = " <<
365 arm,psci-suspe <<
366 entry-latency- <<
367 exit-latency-u <<
368 min-residency- <<
369 }; <<
370 }; <<
371 }; <<
372 <<
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points <<
381 opp-shared; <<
382 <<
383 cpu0_opp1: opp-300000000 { <<
384 opp-hz = /bits/ 64 <30 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp2: opp-403200000 { <<
389 opp-hz = /bits/ 64 <40 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp3: opp-518400000 { <<
394 opp-hz = /bits/ 64 <51 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp4: opp-614400000 { <<
399 opp-hz = /bits/ 64 <61 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp5: opp-691200000 { <<
404 opp-hz = /bits/ 64 <69 <<
405 opp-peak-kBps = <80000 <<
406 }; <<
407 <<
408 cpu0_opp6: opp-787200000 { <<
409 opp-hz = /bits/ 64 <78 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp7: opp-883200000 { <<
414 opp-hz = /bits/ 64 <88 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp8: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp9: opp-1075200000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp10: opp-1171200000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <18040 <<
431 }; <<
432 <<
433 cpu0_opp11: opp-1248000000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <18040 <<
436 }; <<
437 <<
438 cpu0_opp12: opp-1344000000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp13: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <21880 <<
446 }; <<
447 <<
448 cpu0_opp14: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp15: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <30720 <<
456 }; <<
457 <<
458 cpu0_opp16: opp-1708800000 { <<
459 opp-hz = /bits/ 64 <17 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp17: opp-1804800000 { <<
464 opp-hz = /bits/ 64 <18 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-710400000 { <<
474 opp-hz = /bits/ 64 <71 <<
475 opp-peak-kBps = <18040 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-825600000 { <<
479 opp-hz = /bits/ 64 <82 <<
480 opp-peak-kBps = <21880 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-940800000 { <<
484 opp-hz = /bits/ 64 <94 <<
485 opp-peak-kBps = <21880 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-1056000000 { <<
489 opp-hz = /bits/ 64 <10 <<
490 opp-peak-kBps = <30720 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-1171200000 { <<
494 opp-hz = /bits/ 64 <11 <<
495 opp-peak-kBps = <30720 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-1286400000 { <<
499 opp-hz = /bits/ 64 <12 <<
500 opp-peak-kBps = <40680 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-1382400000 { <<
504 opp-hz = /bits/ 64 <13 <<
505 opp-peak-kBps = <40680 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-1478400000 { <<
509 opp-hz = /bits/ 64 <14 <<
510 opp-peak-kBps = <40680 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-1574400000 { <<
514 opp-hz = /bits/ 64 <15 <<
515 opp-peak-kBps = <54120 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1670400000 { <<
519 opp-hz = /bits/ 64 <16 <<
520 opp-peak-kBps = <54120 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1766400000 { <<
524 opp-hz = /bits/ 64 <17 <<
525 opp-peak-kBps = <54120 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1862400000 { <<
529 opp-hz = /bits/ 64 <18 <<
530 opp-peak-kBps = <62200 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1958400000 { <<
534 opp-hz = /bits/ 64 <19 <<
535 opp-peak-kBps = <62200 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-2054400000 { <<
539 opp-hz = /bits/ 64 <20 <<
540 opp-peak-kBps = <72160 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-2150400000 { <<
544 opp-hz = /bits/ 64 <21 <<
545 opp-peak-kBps = <72160 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-2246400000 { <<
549 opp-hz = /bits/ 64 <22 <<
550 opp-peak-kBps = <72160 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-2342400000 { <<
554 opp-hz = /bits/ 64 <23 <<
555 opp-peak-kBps = <83680 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-2419200000 { <<
559 opp-hz = /bits/ 64 <24 <<
560 opp-peak-kBps = <83680 <<
561 }; <<
562 }; <<
563 <<
564 cpu7_opp_table: opp-table-cpu7 { <<
565 compatible = "operating-points <<
566 opp-shared; <<
567 <<
568 cpu7_opp1: opp-844800000 { <<
569 opp-hz = /bits/ 64 <84 <<
570 opp-peak-kBps = <21880 <<
571 }; <<
572 <<
573 cpu7_opp2: opp-960000000 { <<
574 opp-hz = /bits/ 64 <96 <<
575 opp-peak-kBps = <21880 <<
576 }; <<
577 <<
578 cpu7_opp3: opp-1075200000 { <<
579 opp-hz = /bits/ 64 <10 <<
580 opp-peak-kBps = <30720 <<
581 }; <<
582 <<
583 cpu7_opp4: opp-1190400000 { <<
584 opp-hz = /bits/ 64 <11 <<
585 opp-peak-kBps = <30720 <<
586 }; <<
587 <<
588 cpu7_opp5: opp-1305600000 { <<
589 opp-hz = /bits/ 64 <13 <<
590 opp-peak-kBps = <40680 <<
591 }; <<
592 <<
593 cpu7_opp6: opp-1401600000 { <<
594 opp-hz = /bits/ 64 <14 <<
595 opp-peak-kBps = <40680 <<
596 }; <<
597 <<
598 cpu7_opp7: opp-1516800000 { <<
599 opp-hz = /bits/ 64 <15 <<
600 opp-peak-kBps = <40680 <<
601 }; <<
602 <<
603 cpu7_opp8: opp-1632000000 { <<
604 opp-hz = /bits/ 64 <16 <<
605 opp-peak-kBps = <54120 <<
606 }; <<
607 <<
608 cpu7_opp9: opp-1747200000 { <<
609 opp-hz = /bits/ 64 <17 <<
610 opp-peak-kBps = <54120 <<
611 }; <<
612 <<
613 cpu7_opp10: opp-1862400000 { <<
614 opp-hz = /bits/ 64 <18 <<
615 opp-peak-kBps = <62200 <<
616 }; <<
617 <<
618 cpu7_opp11: opp-1977600000 { <<
619 opp-hz = /bits/ 64 <19 <<
620 opp-peak-kBps = <62200 <<
621 }; <<
622 <<
623 cpu7_opp12: opp-2073600000 { <<
624 opp-hz = /bits/ 64 <20 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu7_opp13: opp-2169600000 { <<
629 opp-hz = /bits/ 64 <21 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 <<
633 cpu7_opp14: opp-2265600000 { <<
634 opp-hz = /bits/ 64 <22 <<
635 opp-peak-kBps = <72160 <<
636 }; <<
637 <<
638 cpu7_opp15: opp-2361600000 { <<
639 opp-hz = /bits/ 64 <23 <<
640 opp-peak-kBps = <83680 <<
641 }; <<
642 <<
643 cpu7_opp16: opp-2457600000 { <<
644 opp-hz = /bits/ 64 <24 <<
645 opp-peak-kBps = <83680 <<
646 }; <<
647 <<
648 cpu7_opp17: opp-2553600000 { <<
649 opp-hz = /bits/ 64 <25 <<
650 opp-peak-kBps = <83680 <<
651 }; <<
652 <<
653 cpu7_opp18: opp-2649600000 { <<
654 opp-hz = /bits/ 64 <26 <<
655 opp-peak-kBps = <83680 <<
656 }; <<
657 <<
658 cpu7_opp19: opp-2745600000 { <<
659 opp-hz = /bits/ 64 <27 <<
660 opp-peak-kBps = <83680 <<
661 }; <<
662 <<
663 cpu7_opp20: opp-2841600000 { <<
664 opp-hz = /bits/ 64 <28 <<
665 opp-peak-kBps = <83680 <<
666 }; <<
667 }; 261 };
668 262
669 firmware { 263 firmware {
670 scm: scm { 264 scm: scm {
671 compatible = "qcom,scm !! 265 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 266 #reset-cells = <1>;
674 }; 267 };
675 }; 268 };
676 269
677 memory@80000000 { 270 memory@80000000 {
678 device_type = "memory"; 271 device_type = "memory";
679 /* We expect the bootloader to 272 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 273 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 274 };
682 275
>> 276 mmcx_reg: mmcx-reg {
>> 277 compatible = "regulator-fixed-domain";
>> 278 power-domains = <&rpmhpd SM8250_MMCX>;
>> 279 required-opps = <&rpmhpd_opp_low_svs>;
>> 280 regulator-name = "MMCX";
>> 281 };
>> 282
683 pmu { 283 pmu {
684 compatible = "arm,armv8-pmuv3" 284 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 286 };
687 287
688 psci { 288 psci {
689 compatible = "arm,psci-1.0"; 289 compatible = "arm,psci-1.0";
690 method = "smc"; 290 method = "smc";
691 <<
692 CPU_PD0: power-domain-cpu0 { <<
693 #power-domain-cells = <<
694 power-domains = <&CLUS <<
695 domain-idle-states = < <<
696 }; <<
697 <<
698 CPU_PD1: power-domain-cpu1 { <<
699 #power-domain-cells = <<
700 power-domains = <&CLUS <<
701 domain-idle-states = < <<
702 }; <<
703 <<
704 CPU_PD2: power-domain-cpu2 { <<
705 #power-domain-cells = <<
706 power-domains = <&CLUS <<
707 domain-idle-states = < <<
708 }; <<
709 <<
710 CPU_PD3: power-domain-cpu3 { <<
711 #power-domain-cells = <<
712 power-domains = <&CLUS <<
713 domain-idle-states = < <<
714 }; <<
715 <<
716 CPU_PD4: power-domain-cpu4 { <<
717 #power-domain-cells = <<
718 power-domains = <&CLUS <<
719 domain-idle-states = < <<
720 }; <<
721 <<
722 CPU_PD5: power-domain-cpu5 { <<
723 #power-domain-cells = <<
724 power-domains = <&CLUS <<
725 domain-idle-states = < <<
726 }; <<
727 <<
728 CPU_PD6: power-domain-cpu6 { <<
729 #power-domain-cells = <<
730 power-domains = <&CLUS <<
731 domain-idle-states = < <<
732 }; <<
733 <<
734 CPU_PD7: power-domain-cpu7 { <<
735 #power-domain-cells = <<
736 power-domains = <&CLUS <<
737 domain-idle-states = < <<
738 }; <<
739 <<
740 CLUSTER_PD: power-domain-cpu-c <<
741 #power-domain-cells = <<
742 domain-idle-states = < <<
743 }; <<
744 }; <<
745 <<
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; 291 };
764 292
765 reserved-memory { 293 reserved-memory {
766 #address-cells = <2>; 294 #address-cells = <2>;
767 #size-cells = <2>; 295 #size-cells = <2>;
768 ranges; 296 ranges;
769 297
770 hyp_mem: memory@80000000 { 298 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 299 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 300 no-map;
773 }; 301 };
774 302
775 xbl_aop_mem: memory@80700000 { 303 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 304 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 305 no-map;
778 }; 306 };
779 307
780 cmd_db: memory@80860000 { 308 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 309 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 310 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 311 no-map;
784 }; 312 };
785 313
786 smem_mem: memory@80900000 { 314 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 315 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 316 no-map;
789 }; 317 };
790 318
791 removed_mem: memory@80b00000 { 319 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 320 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 321 no-map;
794 }; 322 };
795 323
796 camera_mem: memory@86200000 { 324 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 325 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 326 no-map;
799 }; 327 };
800 328
801 wlan_mem: memory@86700000 { 329 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 330 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 331 no-map;
804 }; 332 };
805 333
806 ipa_fw_mem: memory@86800000 { 334 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 335 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 336 no-map;
809 }; 337 };
810 338
811 ipa_gsi_mem: memory@86810000 { 339 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 340 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 341 no-map;
814 }; 342 };
815 343
816 gpu_mem: memory@8681a000 { 344 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 345 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 346 no-map;
819 }; 347 };
820 348
821 npu_mem: memory@86900000 { 349 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 350 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 351 no-map;
824 }; 352 };
825 353
826 video_mem: memory@86e00000 { 354 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 355 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 356 no-map;
829 }; 357 };
830 358
831 cvp_mem: memory@87300000 { 359 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 360 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 361 no-map;
834 }; 362 };
835 363
836 cdsp_mem: memory@87800000 { 364 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 365 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 366 no-map;
839 }; 367 };
840 368
841 slpi_mem: memory@88c00000 { 369 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 370 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 371 no-map;
844 }; 372 };
845 373
846 adsp_mem: memory@8a100000 { 374 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 375 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 376 no-map;
849 }; 377 };
850 378
851 spss_mem: memory@8be00000 { 379 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 380 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 381 no-map;
854 }; 382 };
855 383
856 cdsp_secure_heap: memory@8bf00 384 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 385 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 386 no-map;
859 }; 387 };
860 }; 388 };
861 389
862 smem { 390 smem {
863 compatible = "qcom,smem"; 391 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 392 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 393 hwlocks = <&tcsr_mutex 3>;
866 }; 394 };
867 395
868 smp2p-adsp { 396 smp2p-adsp {
869 compatible = "qcom,smp2p"; 397 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 398 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 400 IPCC_MPROC_SIGNAL_SMP2P
873 I 401 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 402 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 403 IPCC_MPROC_SIGNAL_SMP2P>;
876 404
877 qcom,local-pid = <0>; 405 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 406 qcom,remote-pid = <2>;
879 407
880 smp2p_adsp_out: master-kernel 408 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 409 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 410 #qcom,smem-state-cells = <1>;
883 }; 411 };
884 412
885 smp2p_adsp_in: slave-kernel { 413 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 414 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 415 interrupt-controller;
888 #interrupt-cells = <2> 416 #interrupt-cells = <2>;
889 }; 417 };
890 }; 418 };
891 419
892 smp2p-cdsp { 420 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 421 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 422 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 424 IPCC_MPROC_SIGNAL_SMP2P
897 I 425 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 426 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 427 IPCC_MPROC_SIGNAL_SMP2P>;
900 428
901 qcom,local-pid = <0>; 429 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 430 qcom,remote-pid = <5>;
903 431
904 smp2p_cdsp_out: master-kernel 432 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 433 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 434 #qcom,smem-state-cells = <1>;
907 }; 435 };
908 436
909 smp2p_cdsp_in: slave-kernel { 437 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 438 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 439 interrupt-controller;
912 #interrupt-cells = <2> 440 #interrupt-cells = <2>;
913 }; 441 };
914 }; 442 };
915 443
916 smp2p-slpi { 444 smp2p-slpi {
917 compatible = "qcom,smp2p"; 445 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 446 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 448 IPCC_MPROC_SIGNAL_SMP2P
921 I 449 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 450 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 451 IPCC_MPROC_SIGNAL_SMP2P>;
924 452
925 qcom,local-pid = <0>; 453 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 454 qcom,remote-pid = <3>;
927 455
928 smp2p_slpi_out: master-kernel 456 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 457 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 458 #qcom,smem-state-cells = <1>;
931 }; 459 };
932 460
933 smp2p_slpi_in: slave-kernel { 461 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 462 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 463 interrupt-controller;
936 #interrupt-cells = <2> 464 #interrupt-cells = <2>;
937 }; 465 };
938 }; 466 };
939 467
940 soc: soc@0 { 468 soc: soc@0 {
941 #address-cells = <2>; 469 #address-cells = <2>;
942 #size-cells = <2>; 470 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 471 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 472 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 473 compatible = "simple-bus";
946 474
947 gcc: clock-controller@100000 { 475 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 476 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 477 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 478 #clock-cells = <1>;
951 #reset-cells = <1>; 479 #reset-cells = <1>;
952 #power-domain-cells = 480 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 481 clock-names = "bi_tcxo",
954 "bi_tcxo 482 "bi_tcxo_ao",
955 "sleep_c 483 "sleep_clk";
956 clocks = <&rpmhcc RPMH 484 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 485 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 486 <&sleep_clk>;
959 }; 487 };
960 488
961 ipcc: mailbox@408000 { 489 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 491 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 493 interrupt-controller;
966 #interrupt-cells = <3> 494 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 495 #mbox-cells = <2>;
968 }; 496 };
969 497
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 498 rng: rng@793000 {
983 compatible = "qcom,prn 499 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 500 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 501 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 502 clock-names = "core";
987 }; 503 };
988 504
>> 505 qup_opp_table: qup-opp-table {
>> 506 compatible = "operating-points-v2";
>> 507
>> 508 opp-50000000 {
>> 509 opp-hz = /bits/ 64 <50000000>;
>> 510 required-opps = <&rpmhpd_opp_min_svs>;
>> 511 };
>> 512
>> 513 opp-75000000 {
>> 514 opp-hz = /bits/ 64 <75000000>;
>> 515 required-opps = <&rpmhpd_opp_low_svs>;
>> 516 };
>> 517
>> 518 opp-120000000 {
>> 519 opp-hz = /bits/ 64 <120000000>;
>> 520 required-opps = <&rpmhpd_opp_svs>;
>> 521 };
>> 522 };
>> 523
989 gpi_dma2: dma-controller@80000 524 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 !! 525 compatible = "qcom,sm8250-gpi-dma";
991 reg = <0 0x00800000 0 526 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 537 dma-channels = <10>;
1003 dma-channel-mask = <0 538 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 539 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 540 #dma-cells = <3>;
1006 status = "disabled"; 541 status = "disabled";
1007 }; 542 };
1008 543
1009 qupv3_id_2: geniqup@8c0000 { 544 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 545 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 546 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 547 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 550 #address-cells = <2>;
1016 #size-cells = <2>; 551 #size-cells = <2>;
1017 iommus = <&apps_smmu 552 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 553 ranges;
1019 status = "disabled"; 554 status = "disabled";
1020 555
1021 i2c14: i2c@880000 { 556 i2c14: i2c@880000 {
1022 compatible = 557 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 558 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 559 clock-names = "se";
1025 clocks = <&gc 560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 561 pinctrl-names = "default";
1027 pinctrl-0 = < 562 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 563 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ <<
1030 <&gpi_ <<
1031 dma-names = " <<
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 564 #address-cells = <1>;
1040 #size-cells = 565 #size-cells = <0>;
1041 status = "dis 566 status = "disabled";
1042 }; 567 };
1043 568
1044 spi14: spi@880000 { 569 spi14: spi@880000 {
1045 compatible = 570 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 571 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 572 clock-names = "se";
1048 clocks = <&gc 573 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 574 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ <<
1051 <&gpi_ <<
1052 dma-names = " <<
1053 power-domains <<
1054 operating-poi <<
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 575 #address-cells = <1>;
1062 #size-cells = 576 #size-cells = <0>;
>> 577 power-domains = <&rpmhpd SM8250_CX>;
>> 578 operating-points-v2 = <&qup_opp_table>;
1063 status = "dis 579 status = "disabled";
1064 }; 580 };
1065 581
1066 i2c15: i2c@884000 { 582 i2c15: i2c@884000 {
1067 compatible = 583 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 584 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 585 clock-names = "se";
1070 clocks = <&gc 586 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 587 pinctrl-names = "default";
1072 pinctrl-0 = < 588 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 589 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ <<
1075 <&gpi_ <<
1076 dma-names = " <<
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 590 #address-cells = <1>;
1085 #size-cells = 591 #size-cells = <0>;
1086 status = "dis 592 status = "disabled";
1087 }; 593 };
1088 594
1089 spi15: spi@884000 { 595 spi15: spi@884000 {
1090 compatible = 596 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 597 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 598 clock-names = "se";
1093 clocks = <&gc 599 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 600 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ <<
1096 <&gpi_ <<
1097 dma-names = " <<
1098 power-domains <<
1099 operating-poi <<
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 601 #address-cells = <1>;
1107 #size-cells = 602 #size-cells = <0>;
>> 603 power-domains = <&rpmhpd SM8250_CX>;
>> 604 operating-points-v2 = <&qup_opp_table>;
1108 status = "dis 605 status = "disabled";
1109 }; 606 };
1110 607
1111 i2c16: i2c@888000 { 608 i2c16: i2c@888000 {
1112 compatible = 609 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 610 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 611 clock-names = "se";
1115 clocks = <&gc 612 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 613 pinctrl-names = "default";
1117 pinctrl-0 = < 614 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 615 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ <<
1120 <&gpi_ <<
1121 dma-names = " <<
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 616 #address-cells = <1>;
1130 #size-cells = 617 #size-cells = <0>;
1131 status = "dis 618 status = "disabled";
1132 }; 619 };
1133 620
1134 spi16: spi@888000 { 621 spi16: spi@888000 {
1135 compatible = 622 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 623 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 624 clock-names = "se";
1138 clocks = <&gc 625 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 626 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ <<
1141 <&gpi_ <<
1142 dma-names = " <<
1143 power-domains <<
1144 operating-poi <<
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 627 #address-cells = <1>;
1152 #size-cells = 628 #size-cells = <0>;
>> 629 power-domains = <&rpmhpd SM8250_CX>;
>> 630 operating-points-v2 = <&qup_opp_table>;
1153 status = "dis 631 status = "disabled";
1154 }; 632 };
1155 633
1156 i2c17: i2c@88c000 { 634 i2c17: i2c@88c000 {
1157 compatible = 635 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 636 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 637 clock-names = "se";
1160 clocks = <&gc 638 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 639 pinctrl-names = "default";
1162 pinctrl-0 = < 640 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 641 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ <<
1165 <&gpi_ <<
1166 dma-names = " <<
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 642 #address-cells = <1>;
1175 #size-cells = 643 #size-cells = <0>;
1176 status = "dis 644 status = "disabled";
1177 }; 645 };
1178 646
1179 spi17: spi@88c000 { 647 spi17: spi@88c000 {
1180 compatible = 648 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 649 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 650 clock-names = "se";
1183 clocks = <&gc 651 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 652 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ <<
1186 <&gpi_ <<
1187 dma-names = " <<
1188 power-domains <<
1189 operating-poi <<
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 653 #address-cells = <1>;
1197 #size-cells = 654 #size-cells = <0>;
>> 655 power-domains = <&rpmhpd SM8250_CX>;
>> 656 operating-points-v2 = <&qup_opp_table>;
1198 status = "dis 657 status = "disabled";
1199 }; 658 };
1200 659
1201 uart17: serial@88c000 660 uart17: serial@88c000 {
1202 compatible = 661 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 662 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 663 clock-names = "se";
1205 clocks = <&gc 664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 665 pinctrl-names = "default";
1207 pinctrl-0 = < 666 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 667 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 668 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 669 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 670 status = "disabled";
1216 }; 671 };
1217 672
1218 i2c18: i2c@890000 { 673 i2c18: i2c@890000 {
1219 compatible = 674 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 675 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 676 clock-names = "se";
1222 clocks = <&gc 677 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 678 pinctrl-names = "default";
1224 pinctrl-0 = < 679 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 680 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ <<
1227 <&gpi_ <<
1228 dma-names = " <<
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 681 #address-cells = <1>;
1237 #size-cells = 682 #size-cells = <0>;
1238 status = "dis 683 status = "disabled";
1239 }; 684 };
1240 685
1241 spi18: spi@890000 { 686 spi18: spi@890000 {
1242 compatible = 687 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 688 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 689 clock-names = "se";
1245 clocks = <&gc 690 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 691 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ <<
1248 <&gpi_ <<
1249 dma-names = " <<
1250 power-domains <<
1251 operating-poi <<
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 692 #address-cells = <1>;
1259 #size-cells = 693 #size-cells = <0>;
>> 694 power-domains = <&rpmhpd SM8250_CX>;
>> 695 operating-points-v2 = <&qup_opp_table>;
1260 status = "dis 696 status = "disabled";
1261 }; 697 };
1262 698
1263 uart18: serial@890000 699 uart18: serial@890000 {
1264 compatible = 700 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 701 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 702 clock-names = "se";
1267 clocks = <&gc 703 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 704 pinctrl-names = "default";
1269 pinctrl-0 = < 705 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 706 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 707 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 708 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 709 status = "disabled";
1278 }; 710 };
1279 711
1280 i2c19: i2c@894000 { 712 i2c19: i2c@894000 {
1281 compatible = 713 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 714 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 715 clock-names = "se";
1284 clocks = <&gc 716 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 717 pinctrl-names = "default";
1286 pinctrl-0 = < 718 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 719 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ <<
1289 <&gpi_ <<
1290 dma-names = " <<
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 720 #address-cells = <1>;
1299 #size-cells = 721 #size-cells = <0>;
1300 status = "dis 722 status = "disabled";
1301 }; 723 };
1302 724
1303 spi19: spi@894000 { 725 spi19: spi@894000 {
1304 compatible = 726 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 727 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 728 clock-names = "se";
1307 clocks = <&gc 729 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 730 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ <<
1310 <&gpi_ <<
1311 dma-names = " <<
1312 power-domains <<
1313 operating-poi <<
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 731 #address-cells = <1>;
1321 #size-cells = 732 #size-cells = <0>;
>> 733 power-domains = <&rpmhpd SM8250_CX>;
>> 734 operating-points-v2 = <&qup_opp_table>;
1322 status = "dis 735 status = "disabled";
1323 }; 736 };
1324 }; 737 };
1325 738
1326 gpi_dma0: dma-controller@9000 739 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm !! 740 compatible = "qcom,sm8250-gpi-dma";
1328 reg = <0 0x00900000 0 741 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 742 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 743 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 744 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 745 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 746 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 747 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 748 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 749 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 750 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 751 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 752 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 753 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 754 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 755 dma-channels = <15>;
1343 dma-channel-mask = <0 756 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 757 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 758 #dma-cells = <3>;
1346 status = "disabled"; 759 status = "disabled";
1347 }; 760 };
1348 761
1349 qupv3_id_0: geniqup@9c0000 { 762 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 763 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 764 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 765 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 766 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 767 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 768 #address-cells = <2>;
1356 #size-cells = <2>; 769 #size-cells = <2>;
1357 iommus = <&apps_smmu 770 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 771 ranges;
1359 status = "disabled"; 772 status = "disabled";
1360 773
1361 i2c0: i2c@980000 { 774 i2c0: i2c@980000 {
1362 compatible = 775 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 776 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 777 clock-names = "se";
1365 clocks = <&gc 778 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 779 pinctrl-names = "default";
1367 pinctrl-0 = < 780 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 781 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ <<
1370 <&gpi_ <<
1371 dma-names = " <<
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 782 #address-cells = <1>;
1380 #size-cells = 783 #size-cells = <0>;
1381 status = "dis 784 status = "disabled";
1382 }; 785 };
1383 786
1384 spi0: spi@980000 { 787 spi0: spi@980000 {
1385 compatible = 788 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 789 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 790 clock-names = "se";
1388 clocks = <&gc 791 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 792 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ <<
1391 <&gpi_ <<
1392 dma-names = " <<
1393 power-domains <<
1394 operating-poi <<
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 793 #address-cells = <1>;
1402 #size-cells = 794 #size-cells = <0>;
>> 795 power-domains = <&rpmhpd SM8250_CX>;
>> 796 operating-points-v2 = <&qup_opp_table>;
1403 status = "dis 797 status = "disabled";
1404 }; 798 };
1405 799
1406 i2c1: i2c@984000 { 800 i2c1: i2c@984000 {
1407 compatible = 801 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 802 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 803 clock-names = "se";
1410 clocks = <&gc 804 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 805 pinctrl-names = "default";
1412 pinctrl-0 = < 806 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 807 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ <<
1415 <&gpi_ <<
1416 dma-names = " <<
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 808 #address-cells = <1>;
1425 #size-cells = 809 #size-cells = <0>;
1426 status = "dis 810 status = "disabled";
1427 }; 811 };
1428 812
1429 spi1: spi@984000 { 813 spi1: spi@984000 {
1430 compatible = 814 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 815 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 816 clock-names = "se";
1433 clocks = <&gc 817 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 818 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ <<
1436 <&gpi_ <<
1437 dma-names = " <<
1438 power-domains <<
1439 operating-poi <<
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 819 #address-cells = <1>;
1447 #size-cells = 820 #size-cells = <0>;
>> 821 power-domains = <&rpmhpd SM8250_CX>;
>> 822 operating-points-v2 = <&qup_opp_table>;
1448 status = "dis 823 status = "disabled";
1449 }; 824 };
1450 825
1451 i2c2: i2c@988000 { 826 i2c2: i2c@988000 {
1452 compatible = 827 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 828 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 829 clock-names = "se";
1455 clocks = <&gc 830 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 831 pinctrl-names = "default";
1457 pinctrl-0 = < 832 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 833 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ <<
1460 <&gpi_ <<
1461 dma-names = " <<
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 834 #address-cells = <1>;
1470 #size-cells = 835 #size-cells = <0>;
1471 status = "dis 836 status = "disabled";
1472 }; 837 };
1473 838
1474 spi2: spi@988000 { 839 spi2: spi@988000 {
1475 compatible = 840 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 841 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 842 clock-names = "se";
1478 clocks = <&gc 843 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 844 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ <<
1481 <&gpi_ <<
1482 dma-names = " <<
1483 power-domains <<
1484 operating-poi <<
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 845 #address-cells = <1>;
1492 #size-cells = 846 #size-cells = <0>;
>> 847 power-domains = <&rpmhpd SM8250_CX>;
>> 848 operating-points-v2 = <&qup_opp_table>;
1493 status = "dis 849 status = "disabled";
1494 }; 850 };
1495 851
1496 uart2: serial@988000 852 uart2: serial@988000 {
1497 compatible = 853 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 854 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 855 clock-names = "se";
1500 clocks = <&gc 856 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 857 pinctrl-names = "default";
1502 pinctrl-0 = < 858 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 859 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 860 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 861 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 862 status = "disabled";
1511 }; 863 };
1512 864
1513 i2c3: i2c@98c000 { 865 i2c3: i2c@98c000 {
1514 compatible = 866 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 867 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 868 clock-names = "se";
1517 clocks = <&gc 869 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 870 pinctrl-names = "default";
1519 pinctrl-0 = < 871 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 872 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ <<
1522 <&gpi_ <<
1523 dma-names = " <<
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 873 #address-cells = <1>;
1532 #size-cells = 874 #size-cells = <0>;
1533 status = "dis 875 status = "disabled";
1534 }; 876 };
1535 877
1536 spi3: spi@98c000 { 878 spi3: spi@98c000 {
1537 compatible = 879 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 880 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 881 clock-names = "se";
1540 clocks = <&gc 882 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 883 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ <<
1543 <&gpi_ <<
1544 dma-names = " <<
1545 power-domains <<
1546 operating-poi <<
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 884 #address-cells = <1>;
1554 #size-cells = 885 #size-cells = <0>;
>> 886 power-domains = <&rpmhpd SM8250_CX>;
>> 887 operating-points-v2 = <&qup_opp_table>;
1555 status = "dis 888 status = "disabled";
1556 }; 889 };
1557 890
1558 i2c4: i2c@990000 { 891 i2c4: i2c@990000 {
1559 compatible = 892 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 893 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 894 clock-names = "se";
1562 clocks = <&gc 895 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 896 pinctrl-names = "default";
1564 pinctrl-0 = < 897 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 898 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ <<
1567 <&gpi_ <<
1568 dma-names = " <<
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 899 #address-cells = <1>;
1577 #size-cells = 900 #size-cells = <0>;
1578 status = "dis 901 status = "disabled";
1579 }; 902 };
1580 903
1581 spi4: spi@990000 { 904 spi4: spi@990000 {
1582 compatible = 905 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 906 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 907 clock-names = "se";
1585 clocks = <&gc 908 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 909 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ <<
1588 <&gpi_ <<
1589 dma-names = " <<
1590 power-domains <<
1591 operating-poi <<
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 910 #address-cells = <1>;
1599 #size-cells = 911 #size-cells = <0>;
>> 912 power-domains = <&rpmhpd SM8250_CX>;
>> 913 operating-points-v2 = <&qup_opp_table>;
1600 status = "dis 914 status = "disabled";
1601 }; 915 };
1602 916
1603 i2c5: i2c@994000 { 917 i2c5: i2c@994000 {
1604 compatible = 918 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 919 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 920 clock-names = "se";
1607 clocks = <&gc 921 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 922 pinctrl-names = "default";
1609 pinctrl-0 = < 923 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 924 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ <<
1612 <&gpi_ <<
1613 dma-names = " <<
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 925 #address-cells = <1>;
1622 #size-cells = 926 #size-cells = <0>;
1623 status = "dis 927 status = "disabled";
1624 }; 928 };
1625 929
1626 spi5: spi@994000 { 930 spi5: spi@994000 {
1627 compatible = 931 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 932 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 933 clock-names = "se";
1630 clocks = <&gc 934 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 935 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ <<
1633 <&gpi_ <<
1634 dma-names = " <<
1635 power-domains <<
1636 operating-poi <<
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 936 #address-cells = <1>;
1644 #size-cells = 937 #size-cells = <0>;
>> 938 power-domains = <&rpmhpd SM8250_CX>;
>> 939 operating-points-v2 = <&qup_opp_table>;
1645 status = "dis 940 status = "disabled";
1646 }; 941 };
1647 942
1648 i2c6: i2c@998000 { 943 i2c6: i2c@998000 {
1649 compatible = 944 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 945 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 946 clock-names = "se";
1652 clocks = <&gc 947 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 948 pinctrl-names = "default";
1654 pinctrl-0 = < 949 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 950 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ <<
1657 <&gpi_ <<
1658 dma-names = " <<
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 951 #address-cells = <1>;
1667 #size-cells = 952 #size-cells = <0>;
1668 status = "dis 953 status = "disabled";
1669 }; 954 };
1670 955
1671 spi6: spi@998000 { 956 spi6: spi@998000 {
1672 compatible = 957 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 958 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 959 clock-names = "se";
1675 clocks = <&gc 960 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 961 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ <<
1678 <&gpi_ <<
1679 dma-names = " <<
1680 power-domains <<
1681 operating-poi <<
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 962 #address-cells = <1>;
1689 #size-cells = 963 #size-cells = <0>;
>> 964 power-domains = <&rpmhpd SM8250_CX>;
>> 965 operating-points-v2 = <&qup_opp_table>;
1690 status = "dis 966 status = "disabled";
1691 }; 967 };
1692 968
1693 uart6: serial@998000 969 uart6: serial@998000 {
1694 compatible = 970 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 971 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 972 clock-names = "se";
1697 clocks = <&gc 973 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 974 pinctrl-names = "default";
1699 pinctrl-0 = < 975 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 976 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 977 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 978 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 979 status = "disabled";
1708 }; 980 };
1709 981
1710 i2c7: i2c@99c000 { 982 i2c7: i2c@99c000 {
1711 compatible = 983 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 984 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 985 clock-names = "se";
1714 clocks = <&gc 986 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 987 pinctrl-names = "default";
1716 pinctrl-0 = < 988 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 989 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ <<
1719 <&gpi_ <<
1720 dma-names = " <<
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 990 #address-cells = <1>;
1729 #size-cells = 991 #size-cells = <0>;
1730 status = "dis 992 status = "disabled";
1731 }; 993 };
1732 994
1733 spi7: spi@99c000 { 995 spi7: spi@99c000 {
1734 compatible = 996 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 997 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 998 clock-names = "se";
1737 clocks = <&gc 999 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1000 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ <<
1740 <&gpi_ <<
1741 dma-names = " <<
1742 power-domains <<
1743 operating-poi <<
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1001 #address-cells = <1>;
1751 #size-cells = 1002 #size-cells = <0>;
>> 1003 power-domains = <&rpmhpd SM8250_CX>;
>> 1004 operating-points-v2 = <&qup_opp_table>;
1752 status = "dis 1005 status = "disabled";
1753 }; 1006 };
1754 }; 1007 };
1755 1008
1756 gpi_dma1: dma-controller@a000 1009 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm !! 1010 compatible = "qcom,sm8250-gpi-dma";
1758 reg = <0 0x00a00000 0 1011 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1012 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1013 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1014 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1015 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1016 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1017 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1018 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1019 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1020 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1021 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1022 dma-channels = <10>;
1770 dma-channel-mask = <0 1023 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1024 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1025 #dma-cells = <3>;
1773 status = "disabled"; 1026 status = "disabled";
1774 }; 1027 };
1775 1028
1776 qupv3_id_1: geniqup@ac0000 { 1029 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1030 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1031 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1032 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1033 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1034 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1035 #address-cells = <2>;
1783 #size-cells = <2>; 1036 #size-cells = <2>;
1784 iommus = <&apps_smmu 1037 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1038 ranges;
1786 status = "disabled"; 1039 status = "disabled";
1787 1040
1788 i2c8: i2c@a80000 { 1041 i2c8: i2c@a80000 {
1789 compatible = 1042 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1043 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1044 clock-names = "se";
1792 clocks = <&gc 1045 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1046 pinctrl-names = "default";
1794 pinctrl-0 = < 1047 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1048 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ <<
1797 <&gpi_ <<
1798 dma-names = " <<
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1049 #address-cells = <1>;
1807 #size-cells = 1050 #size-cells = <0>;
1808 status = "dis 1051 status = "disabled";
1809 }; 1052 };
1810 1053
1811 spi8: spi@a80000 { 1054 spi8: spi@a80000 {
1812 compatible = 1055 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1056 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1057 clock-names = "se";
1815 clocks = <&gc 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1059 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ <<
1818 <&gpi_ <<
1819 dma-names = " <<
1820 power-domains <<
1821 operating-poi <<
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1060 #address-cells = <1>;
1829 #size-cells = 1061 #size-cells = <0>;
>> 1062 power-domains = <&rpmhpd SM8250_CX>;
>> 1063 operating-points-v2 = <&qup_opp_table>;
1830 status = "dis 1064 status = "disabled";
1831 }; 1065 };
1832 1066
1833 i2c9: i2c@a84000 { 1067 i2c9: i2c@a84000 {
1834 compatible = 1068 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1069 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1070 clock-names = "se";
1837 clocks = <&gc 1071 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1072 pinctrl-names = "default";
1839 pinctrl-0 = < 1073 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1074 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ <<
1842 <&gpi_ <<
1843 dma-names = " <<
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1075 #address-cells = <1>;
1852 #size-cells = 1076 #size-cells = <0>;
1853 status = "dis 1077 status = "disabled";
1854 }; 1078 };
1855 1079
1856 spi9: spi@a84000 { 1080 spi9: spi@a84000 {
1857 compatible = 1081 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1082 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1083 clock-names = "se";
1860 clocks = <&gc 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1085 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ <<
1863 <&gpi_ <<
1864 dma-names = " <<
1865 power-domains <<
1866 operating-poi <<
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1086 #address-cells = <1>;
1874 #size-cells = 1087 #size-cells = <0>;
>> 1088 power-domains = <&rpmhpd SM8250_CX>;
>> 1089 operating-points-v2 = <&qup_opp_table>;
1875 status = "dis 1090 status = "disabled";
1876 }; 1091 };
1877 1092
1878 i2c10: i2c@a88000 { 1093 i2c10: i2c@a88000 {
1879 compatible = 1094 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1095 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1096 clock-names = "se";
1882 clocks = <&gc 1097 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1098 pinctrl-names = "default";
1884 pinctrl-0 = < 1099 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1100 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ <<
1887 <&gpi_ <<
1888 dma-names = " <<
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1101 #address-cells = <1>;
1897 #size-cells = 1102 #size-cells = <0>;
1898 status = "dis 1103 status = "disabled";
1899 }; 1104 };
1900 1105
1901 spi10: spi@a88000 { 1106 spi10: spi@a88000 {
1902 compatible = 1107 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1108 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1109 clock-names = "se";
1905 clocks = <&gc 1110 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1111 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ <<
1908 <&gpi_ <<
1909 dma-names = " <<
1910 power-domains <<
1911 operating-poi <<
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1112 #address-cells = <1>;
1919 #size-cells = 1113 #size-cells = <0>;
>> 1114 power-domains = <&rpmhpd SM8250_CX>;
>> 1115 operating-points-v2 = <&qup_opp_table>;
1920 status = "dis 1116 status = "disabled";
1921 }; 1117 };
1922 1118
1923 i2c11: i2c@a8c000 { 1119 i2c11: i2c@a8c000 {
1924 compatible = 1120 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1121 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1122 clock-names = "se";
1927 clocks = <&gc 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1124 pinctrl-names = "default";
1929 pinctrl-0 = < 1125 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1126 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ <<
1932 <&gpi_ <<
1933 dma-names = " <<
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1127 #address-cells = <1>;
1942 #size-cells = 1128 #size-cells = <0>;
1943 status = "dis 1129 status = "disabled";
1944 }; 1130 };
1945 1131
1946 spi11: spi@a8c000 { 1132 spi11: spi@a8c000 {
1947 compatible = 1133 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1134 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1135 clock-names = "se";
1950 clocks = <&gc 1136 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1137 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ <<
1953 <&gpi_ <<
1954 dma-names = " <<
1955 power-domains <<
1956 operating-poi <<
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1138 #address-cells = <1>;
1964 #size-cells = 1139 #size-cells = <0>;
>> 1140 power-domains = <&rpmhpd SM8250_CX>;
>> 1141 operating-points-v2 = <&qup_opp_table>;
1965 status = "dis 1142 status = "disabled";
1966 }; 1143 };
1967 1144
1968 i2c12: i2c@a90000 { 1145 i2c12: i2c@a90000 {
1969 compatible = 1146 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1147 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1148 clock-names = "se";
1972 clocks = <&gc 1149 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1150 pinctrl-names = "default";
1974 pinctrl-0 = < 1151 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1152 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ <<
1977 <&gpi_ <<
1978 dma-names = " <<
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1153 #address-cells = <1>;
1987 #size-cells = 1154 #size-cells = <0>;
1988 status = "dis 1155 status = "disabled";
1989 }; 1156 };
1990 1157
1991 spi12: spi@a90000 { 1158 spi12: spi@a90000 {
1992 compatible = 1159 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1160 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1161 clock-names = "se";
1995 clocks = <&gc 1162 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1163 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ <<
1998 <&gpi_ <<
1999 dma-names = " <<
2000 power-domains <<
2001 operating-poi <<
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1164 #address-cells = <1>;
2009 #size-cells = 1165 #size-cells = <0>;
>> 1166 power-domains = <&rpmhpd SM8250_CX>;
>> 1167 operating-points-v2 = <&qup_opp_table>;
2010 status = "dis 1168 status = "disabled";
2011 }; 1169 };
2012 1170
2013 uart12: serial@a90000 1171 uart12: serial@a90000 {
2014 compatible = 1172 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1173 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1174 clock-names = "se";
2017 clocks = <&gc 1175 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1176 pinctrl-names = "default";
2019 pinctrl-0 = < 1177 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1178 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1179 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1180 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1181 status = "disabled";
2028 }; 1182 };
2029 1183
2030 i2c13: i2c@a94000 { 1184 i2c13: i2c@a94000 {
2031 compatible = 1185 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1186 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1187 clock-names = "se";
2034 clocks = <&gc 1188 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1189 pinctrl-names = "default";
2036 pinctrl-0 = < 1190 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1191 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ <<
2039 <&gpi_ <<
2040 dma-names = " <<
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1192 #address-cells = <1>;
2049 #size-cells = 1193 #size-cells = <0>;
2050 status = "dis 1194 status = "disabled";
2051 }; 1195 };
2052 1196
2053 spi13: spi@a94000 { 1197 spi13: spi@a94000 {
2054 compatible = 1198 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1199 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1200 clock-names = "se";
2057 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1202 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ <<
2060 <&gpi_ <<
2061 dma-names = " <<
2062 power-domains <<
2063 operating-poi <<
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1203 #address-cells = <1>;
2071 #size-cells = 1204 #size-cells = <0>;
>> 1205 power-domains = <&rpmhpd SM8250_CX>;
>> 1206 operating-points-v2 = <&qup_opp_table>;
2072 status = "dis 1207 status = "disabled";
2073 }; 1208 };
2074 }; 1209 };
2075 1210
2076 config_noc: interconnect@1500 1211 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1212 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1213 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1214 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1215 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1216 };
2082 1217
2083 system_noc: interconnect@1620 1218 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1219 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1220 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1221 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1222 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1223 };
2089 1224
2090 mc_virt: interconnect@163d000 1225 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1226 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1227 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1228 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1229 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1230 };
2096 1231
2097 aggre1_noc: interconnect@16e0 1232 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1233 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1234 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1235 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1236 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1237 };
2103 1238
2104 aggre2_noc: interconnect@1700 1239 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1240 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1241 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1242 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1243 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1244 };
2110 1245
2111 compute_noc: interconnect@173 1246 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1247 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1248 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1249 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1250 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1251 };
2117 1252
2118 mmss_noc: interconnect@174000 1253 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1254 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1255 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1256 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1257 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1258 };
2124 1259
2125 pcie0: pcie@1c00000 { !! 1260 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1261 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1262 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1263 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1264 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1265 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1266 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1267 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1268 device_type = "pci";
2135 linux,pci-domain = <0 1269 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1270 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1271 num-lanes = <1>;
2138 1272
2139 #address-cells = <3>; 1273 #address-cells = <3>;
2140 #size-cells = <2>; 1274 #size-cells = <2>;
2141 1275
2142 ranges = <0x01000000 !! 1276 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1277 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1278
2145 interrupts = <GIC_SPI !! 1279 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1280 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1281 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1282 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1283 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1284 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1285 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1286 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1287
2168 clocks = <&gcc GCC_PC 1288 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1289 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1290 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1291 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1292 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1293 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1294 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1295 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1296 clock-names = "pipe",
2177 "aux", 1297 "aux",
2178 "cfg", 1298 "cfg",
2179 "bus_ma 1299 "bus_master",
2180 "bus_sl 1300 "bus_slave",
2181 "slave_ 1301 "slave_q2a",
2182 "tbu", 1302 "tbu",
2183 "ddrss_ 1303 "ddrss_sf_tbu";
2184 1304
>> 1305 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1306 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1307 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1308
2188 resets = <&gcc GCC_PC 1309 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1310 reset-names = "pci";
2190 1311
2191 power-domains = <&gcc 1312 power-domains = <&gcc PCIE_0_GDSC>;
2192 1313
2193 phys = <&pcie0_phy>; !! 1314 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1315 phy-names = "pciephy";
2195 1316
2196 perst-gpios = <&tlmm !! 1317 perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 !! 1318 enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1319
2199 pinctrl-names = "defa 1320 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1321 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1322
2203 status = "disabled"; 1323 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1324 };
2215 1325
2216 pcie0_phy: phy@1c06000 { 1326 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1327 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1328 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1329 #address-cells = <2>;
>> 1330 #size-cells = <2>;
>> 1331 ranges;
2220 clocks = <&gcc GCC_PC 1332 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1333 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1334 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1335 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1336 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1337
2236 resets = <&gcc GCC_PC 1338 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1339 reset-names = "phy";
2238 1340
2239 assigned-clocks = <&g 1341 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1342 assigned-clock-rates = <100000000>;
2241 1343
2242 status = "disabled"; 1344 status = "disabled";
>> 1345
>> 1346 pcie0_lane: lanes@1c06200 {
>> 1347 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1348 <0 0x1c06400 0 0x200>, /* rx */
>> 1349 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1350 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1351 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1352 clock-names = "pipe0";
>> 1353
>> 1354 #phy-cells = <0>;
>> 1355 clock-output-names = "pcie_0_pipe_clk";
>> 1356 };
2243 }; 1357 };
2244 1358
2245 pcie1: pcie@1c08000 { !! 1359 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1360 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1361 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1362 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1363 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1364 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1365 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1366 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1367 device_type = "pci";
2255 linux,pci-domain = <1 1368 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1369 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1370 num-lanes = <2>;
2258 1371
2259 #address-cells = <3>; 1372 #address-cells = <3>;
2260 #size-cells = <2>; 1373 #size-cells = <2>;
2261 1374
2262 ranges = <0x01000000 !! 1375 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1376 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1377
2265 interrupts = <GIC_SPI !! 1378 interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
2266 <GIC_SPI !! 1379 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1380 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1381 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1382 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1383 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1384 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1385 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1386
2288 clocks = <&gcc GCC_PC 1387 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1388 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1389 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1390 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1391 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1392 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1393 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1394 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1395 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1396 clock-names = "pipe",
2298 "aux", 1397 "aux",
2299 "cfg", 1398 "cfg",
2300 "bus_ma 1399 "bus_master",
2301 "bus_sl 1400 "bus_slave",
2302 "slave_ 1401 "slave_q2a",
2303 "ref", 1402 "ref",
2304 "tbu", 1403 "tbu",
2305 "ddrss_ 1404 "ddrss_sf_tbu";
2306 1405
2307 assigned-clocks = <&g 1406 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1407 assigned-clock-rates = <19200000>;
2309 1408
>> 1409 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1410 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1411 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1412
2313 resets = <&gcc GCC_PC 1413 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1414 reset-names = "pci";
2315 1415
2316 power-domains = <&gcc 1416 power-domains = <&gcc PCIE_1_GDSC>;
2317 1417
2318 phys = <&pcie1_phy>; !! 1418 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1419 phy-names = "pciephy";
2320 1420
2321 perst-gpios = <&tlmm !! 1421 perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 !! 1422 enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1423
2324 pinctrl-names = "defa 1424 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1425 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1426
2328 status = "disabled"; 1427 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1428 };
2340 1429
2341 pcie1_phy: phy@1c0e000 { 1430 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1431 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1432 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1433 #address-cells = <2>;
>> 1434 #size-cells = <2>;
>> 1435 ranges;
2345 clocks = <&gcc GCC_PC 1436 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1437 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1438 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1439 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1440 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1441
2361 resets = <&gcc GCC_PC 1442 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1443 reset-names = "phy";
2363 1444
2364 assigned-clocks = <&g 1445 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1446 assigned-clock-rates = <100000000>;
2366 1447
2367 status = "disabled"; 1448 status = "disabled";
>> 1449
>> 1450 pcie1_lane: lanes@1c0e200 {
>> 1451 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1452 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1453 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1454 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1455 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1456 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1457 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1458 clock-names = "pipe0";
>> 1459
>> 1460 #phy-cells = <0>;
>> 1461 clock-output-names = "pcie_1_pipe_clk";
>> 1462 };
2368 }; 1463 };
2369 1464
2370 pcie2: pcie@1c10000 { !! 1465 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 1466 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 1467 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 1468 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 1469 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 1470 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 1471 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 1472 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 1473 device_type = "pci";
2380 linux,pci-domain = <2 1474 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 1475 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 1476 num-lanes = <2>;
2383 1477
2384 #address-cells = <3>; 1478 #address-cells = <3>;
2385 #size-cells = <2>; 1479 #size-cells = <2>;
2386 1480
2387 ranges = <0x01000000 !! 1481 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 1482 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 1483
2390 interrupts = <GIC_SPI !! 1484 interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
2391 <GIC_SPI !! 1485 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 1486 #interrupt-cells = <1>;
2407 interrupt-map-mask = 1487 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 1488 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 1489 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 1490 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 1491 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 1492
2413 clocks = <&gcc GCC_PC 1493 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 1494 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 1495 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 1496 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 1497 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 1498 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 1499 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 1500 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 1501 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 1502 clock-names = "pipe",
2423 "aux", 1503 "aux",
2424 "cfg", 1504 "cfg",
2425 "bus_ma 1505 "bus_master",
2426 "bus_sl 1506 "bus_slave",
2427 "slave_ 1507 "slave_q2a",
2428 "ref", 1508 "ref",
2429 "tbu", 1509 "tbu",
2430 "ddrss_ 1510 "ddrss_sf_tbu";
2431 1511
2432 assigned-clocks = <&g 1512 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 1513 assigned-clock-rates = <19200000>;
2434 1514
>> 1515 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 1516 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 1517 <0x100 &apps_smmu 0x1d01 0x1>;
2437 1518
2438 resets = <&gcc GCC_PC 1519 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 1520 reset-names = "pci";
2440 1521
2441 power-domains = <&gcc 1522 power-domains = <&gcc PCIE_2_GDSC>;
2442 1523
2443 phys = <&pcie2_phy>; !! 1524 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 1525 phy-names = "pciephy";
2445 1526
2446 perst-gpios = <&tlmm !! 1527 perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 !! 1528 enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 1529
2449 pinctrl-names = "defa 1530 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 1531 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 1532
2453 status = "disabled"; 1533 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 1534 };
2465 1535
2466 pcie2_phy: phy@1c16000 { 1536 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 1537 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 1538 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 1539 #address-cells = <2>;
>> 1540 #size-cells = <2>;
>> 1541 ranges;
2470 clocks = <&gcc GCC_PC 1542 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 1543 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 1544 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 1545 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 1546 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 1547
2486 resets = <&gcc GCC_PC 1548 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 1549 reset-names = "phy";
2488 1550
2489 assigned-clocks = <&g 1551 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 1552 assigned-clock-rates = <100000000>;
2491 1553
2492 status = "disabled"; 1554 status = "disabled";
>> 1555
>> 1556 pcie2_lane: lanes@1c16200 {
>> 1557 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 1558 <0 0x1c16400 0 0x200>, /* rx0 */
>> 1559 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 1560 <0 0x1c16600 0 0x170>, /* tx1 */
>> 1561 <0 0x1c16800 0 0x200>, /* rx1 */
>> 1562 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1563 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 1564 clock-names = "pipe0";
>> 1565
>> 1566 #phy-cells = <0>;
>> 1567 clock-output-names = "pcie_2_pipe_clk";
>> 1568 };
2493 }; 1569 };
2494 1570
2495 ufs_mem_hc: ufshc@1d84000 { 1571 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 1572 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 1573 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 1574 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 1575 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 1576 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 1577 phy-names = "ufsphy";
2502 lanes-per-direction = 1578 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 1579 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 1580 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 1581 reset-names = "rst";
2506 1582
2507 power-domains = <&gcc 1583 power-domains = <&gcc UFS_PHY_GDSC>;
2508 1584
2509 iommus = <&apps_smmu 1585 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 1586
2511 clock-names = 1587 clock-names =
2512 "core_clk", 1588 "core_clk",
2513 "bus_aggr_clk 1589 "bus_aggr_clk",
2514 "iface_clk", 1590 "iface_clk",
2515 "core_clk_uni 1591 "core_clk_unipro",
2516 "ref_clk", 1592 "ref_clk",
2517 "tx_lane0_syn 1593 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 1594 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 1595 "rx_lane1_sync_clk";
2520 clocks = 1596 clocks =
2521 <&gcc GCC_UFS 1597 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 1598 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 1599 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 1600 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 1601 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 1602 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 1603 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 1604 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 1605 freq-table-hz =
2530 operating-points-v2 = !! 1606 <37500000 300000000>,
2531 !! 1607 <0 0>,
2532 interconnects = <&agg !! 1608 <0 0>,
2533 <&gem !! 1609 <37500000 300000000>,
2534 interconnect-names = !! 1610 <0 0>,
>> 1611 <0 0>,
>> 1612 <0 0>,
>> 1613 <0 0>;
2535 1614
2536 status = "disabled"; 1615 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 1616 };
2566 1617
2567 ufs_mem_phy: phy@1d87000 { 1618 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 1619 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 1620 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 1621 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 1622 #size-cells = <2>;
2572 <&gcc GCC_UF !! 1623 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 1624 clock-names = "ref",
2575 "ref_au !! 1625 "ref_aux";
2576 "qref"; !! 1626 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 1627 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 1628
2578 resets = <&ufs_mem_hc 1629 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 1630 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 1631 status = "disabled";
>> 1632
>> 1633 ufs_mem_phy_lanes: lanes@1d87400 {
>> 1634 reg = <0 0x01d87400 0 0x108>,
>> 1635 <0 0x01d87600 0 0x1e0>,
>> 1636 <0 0x01d87c00 0 0x1dc>,
>> 1637 <0 0x01d87800 0 0x108>,
>> 1638 <0 0x01d87a00 0 0x1e0>;
>> 1639 #phy-cells = <0>;
>> 1640 };
2586 }; 1641 };
2587 1642
2588 cryptobam: dma-controller@1dc !! 1643 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 1644 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 1645 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 1646 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 1647 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 1648 };
2619 1649
2620 tcsr_mutex: hwlock@1f40000 { 1650 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 1651 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 1652 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 1653 #hwlock-cells = <1>;
2624 }; 1654 };
2625 1655
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 1656 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 1657 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 1658 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 1659 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 1660 <&audiocc 0>,
2636 <&q6afecc LP 1661 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 1662 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1663 <&aoncc 0>,
2638 <&vamacro>; 1664 <&vamacro>;
2639 1665
2640 clock-names = "mclk", !! 1666 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 1667
2642 #clock-cells = <0>; 1668 #clock-cells = <0>;
>> 1669 clock-frequency = <9600000>;
2643 clock-output-names = 1670 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 1671 #sound-dai-cells = <1>;
2645 1672
2646 pinctrl-names = "defa 1673 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 1674 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 1675 };
2651 1676
2652 swr0: soundwire@3250000 { !! 1677 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 1678 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 1679 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 1680 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 1681 clocks = <&wsamacro>;
2657 clock-names = "iface" 1682 clock-names = "iface";
2658 1683
2659 qcom,din-ports = <2>; 1684 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 1685 qcom,dout-ports = <6>;
2661 1686
2662 qcom,ports-sinterval- 1687 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 1688 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 1689 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 1690 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 1691
2667 #sound-dai-cells = <1 1692 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 1693 #address-cells = <2>;
2669 #size-cells = <0>; 1694 #size-cells = <0>;
>> 1695 };
2670 1696
2671 status = "disabled"; !! 1697 audiocc: clock-controller@3300000 {
>> 1698 compatible = "qcom,sm8250-lpass-audiocc";
>> 1699 reg = <0 0x03300000 0 0x30000>;
>> 1700 #clock-cells = <1>;
>> 1701 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1702 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1703 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 1704 clock-names = "core", "audio", "bus";
2672 }; 1705 };
2673 1706
2674 vamacro: codec@3370000 { 1707 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 1708 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 1709 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 1710 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 1711 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 1712 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 1713
2681 clock-names = "mclk", 1714 clock-names = "mclk", "macro", "dcodec";
2682 1715
2683 #clock-cells = <0>; 1716 #clock-cells = <0>;
>> 1717 clock-frequency = <9600000>;
2684 clock-output-names = 1718 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 1719 #sound-dai-cells = <1>;
2686 }; 1720 };
2687 1721
2688 rxmacro: rxmacro@3200000 { !! 1722 aoncc: clock-controller@3380000 {
2689 pinctrl-names = "defa !! 1723 compatible = "qcom,sm8250-lpass-aoncc";
2690 pinctrl-0 = <&rx_swr_ !! 1724 reg = <0 0x03380000 0 0x40000>;
2691 compatible = "qcom,sm !! 1725 #clock-cells = <1>;
2692 reg = <0 0x03200000 0 !! 1726 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2693 status = "disabled"; <<
2694 <<
2695 clocks = <&q6afecc LP <<
2696 <&q6afecc LPA <<
2697 <&q6afecc LPA <<
2698 <&q6afecc LPA 1727 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; !! 1728 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2700 !! 1729 clock-names = "core", "audio", "bus";
2701 clock-names = "mclk", <<
2702 <<
2703 #clock-cells = <0>; <<
2704 clock-output-names = <<
2705 #sound-dai-cells = <1 <<
2706 }; <<
2707 <<
2708 swr1: soundwire@3210000 { <<
2709 reg = <0 0x03210000 0 <<
2710 compatible = "qcom,so <<
2711 status = "disabled"; <<
2712 interrupts = <GIC_SPI <<
2713 clocks = <&rxmacro>; <<
2714 clock-names = "iface" <<
2715 label = "RX"; <<
2716 qcom,din-ports = <0>; <<
2717 qcom,dout-ports = <5> <<
2718 <<
2719 qcom,ports-sinterval- <<
2720 qcom,ports-offset1 = <<
2721 qcom,ports-offset2 = <<
2722 qcom,ports-hstart = <<
2723 qcom,ports-hstop = <<
2724 qcom,ports-word-lengt <<
2725 qcom,ports-block-pack <<
2726 qcom,ports-lane-contr <<
2727 qcom,ports-block-grou <<
2728 <<
2729 #sound-dai-cells = <1 <<
2730 #address-cells = <2>; <<
2731 #size-cells = <0>; <<
2732 }; <<
2733 <<
2734 txmacro: txmacro@3220000 { <<
2735 pinctrl-names = "defa <<
2736 pinctrl-0 = <&tx_swr_ <<
2737 compatible = "qcom,sm <<
2738 reg = <0 0x03220000 0 <<
2739 status = "disabled"; <<
2740 <<
2741 clocks = <&q6afecc LP <<
2742 <&q6afecc LP <<
2743 <&q6afecc LP <<
2744 <&q6afecc LP <<
2745 <&vamacro>; <<
2746 <<
2747 clock-names = "mclk", <<
2748 <<
2749 #clock-cells = <0>; <<
2750 clock-output-names = <<
2751 #sound-dai-cells = <1 <<
2752 }; 1730 };
2753 1731
2754 /* tx macro */ !! 1732 lpass_tlmm: pinctrl@33c0000{
2755 swr2: soundwire@3230000 { <<
2756 reg = <0 0x03230000 0 <<
2757 compatible = "qcom,so <<
2758 interrupts = <GIC_SPI <<
2759 interrupt-names = "co <<
2760 status = "disabled"; <<
2761 <<
2762 clocks = <&txmacro>; <<
2763 clock-names = "iface" <<
2764 label = "TX"; <<
2765 <<
2766 qcom,din-ports = <5>; <<
2767 qcom,dout-ports = <0> <<
2768 qcom,ports-sinterval- <<
2769 qcom,ports-offset1 = <<
2770 qcom,ports-offset2 = <<
2771 qcom,ports-block-pack <<
2772 qcom,ports-hstart = <<
2773 qcom,ports-hstop = <<
2774 qcom,ports-word-lengt <<
2775 qcom,ports-block-grou <<
2776 qcom,ports-lane-contr <<
2777 #sound-dai-cells = <1 <<
2778 #address-cells = <2>; <<
2779 #size-cells = <0>; <<
2780 }; <<
2781 <<
2782 lpass_tlmm: pinctrl@33c0000 { <<
2783 compatible = "qcom,sm 1733 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 1734 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 1735 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 1736 gpio-controller;
2787 #gpio-cells = <2>; 1737 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 1738 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 1739
2790 clocks = <&q6afecc LP 1740 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 1741 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 1742 clock-names = "core", "audio";
2793 1743
2794 wsa_swr_active: wsa-s !! 1744 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 1745 clk {
2796 pins 1746 pins = "gpio10";
2797 funct 1747 function = "wsa_swr_clk";
2798 drive 1748 drive-strength = <2>;
2799 slew- 1749 slew-rate = <1>;
2800 bias- 1750 bias-disable;
2801 }; 1751 };
2802 1752
2803 data-pins { !! 1753 data {
2804 pins 1754 pins = "gpio11";
2805 funct 1755 function = "wsa_swr_data";
2806 drive 1756 drive-strength = <2>;
2807 slew- 1757 slew-rate = <1>;
2808 bias- 1758 bias-bus-hold;
>> 1759
2809 }; 1760 };
2810 }; 1761 };
2811 1762
2812 wsa_swr_sleep: wsa-sw !! 1763 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 1764 clk {
2814 pins 1765 pins = "gpio10";
2815 funct 1766 function = "wsa_swr_clk";
2816 drive 1767 drive-strength = <2>;
>> 1768 input-enable;
2817 bias- 1769 bias-pull-down;
2818 }; 1770 };
2819 1771
2820 data-pins { !! 1772 data {
2821 pins 1773 pins = "gpio11";
2822 funct 1774 function = "wsa_swr_data";
2823 drive 1775 drive-strength = <2>;
>> 1776 input-enable;
2824 bias- 1777 bias-pull-down;
>> 1778
2825 }; 1779 };
2826 }; 1780 };
2827 1781
2828 dmic01_active: dmic01 !! 1782 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 1783 clk {
2830 pins 1784 pins = "gpio6";
2831 funct 1785 function = "dmic1_clk";
2832 drive 1786 drive-strength = <8>;
2833 outpu 1787 output-high;
2834 }; 1788 };
2835 data-pins { !! 1789 data {
2836 pins 1790 pins = "gpio7";
2837 funct 1791 function = "dmic1_data";
2838 drive 1792 drive-strength = <8>;
>> 1793 input-enable;
2839 }; 1794 };
2840 }; 1795 };
2841 1796
2842 dmic01_sleep: dmic01- !! 1797 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 1798 clk {
2844 pins 1799 pins = "gpio6";
2845 funct 1800 function = "dmic1_clk";
2846 drive 1801 drive-strength = <2>;
2847 bias- 1802 bias-disable;
2848 outpu 1803 output-low;
2849 }; 1804 };
2850 1805
2851 data-pins { !! 1806 data {
2852 pins 1807 pins = "gpio7";
2853 funct 1808 function = "dmic1_data";
2854 drive 1809 drive-strength = <2>;
2855 bias- !! 1810 pull-down;
2856 }; !! 1811 input-enable;
2857 }; <<
2858 <<
2859 rx_swr_active: rx-swr <<
2860 clk-pins { <<
2861 pins <<
2862 funct <<
2863 drive <<
2864 slew- <<
2865 bias- <<
2866 }; <<
2867 <<
2868 data-pins { <<
2869 pins <<
2870 funct <<
2871 drive <<
2872 slew- <<
2873 bias- <<
2874 }; <<
2875 }; <<
2876 <<
2877 tx_swr_active: tx-swr <<
2878 clk-pins { <<
2879 pins <<
2880 funct <<
2881 drive <<
2882 slew- <<
2883 bias- <<
2884 }; <<
2885 <<
2886 data-pins { <<
2887 pins <<
2888 funct <<
2889 drive <<
2890 slew- <<
2891 bias- <<
2892 }; <<
2893 }; <<
2894 <<
2895 tx_swr_sleep: tx-swr- <<
2896 clk-pins { <<
2897 pins <<
2898 funct <<
2899 drive <<
2900 bias- <<
2901 }; <<
2902 <<
2903 data1-pins { <<
2904 pins <<
2905 funct <<
2906 drive <<
2907 bias- <<
2908 }; <<
2909 <<
2910 data2-pins { <<
2911 pins <<
2912 funct <<
2913 drive <<
2914 bias- <<
2915 }; 1812 };
2916 }; 1813 };
2917 }; 1814 };
2918 1815
2919 gpu: gpu@3d00000 { 1816 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 1817 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 1818 "qcom,adreno";
>> 1819 #stream-id-cells = <16>;
2922 1820
2923 reg = <0 0x03d00000 0 1821 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 1822 reg-names = "kgsl_3d0_reg_memory";
2925 1823
2926 interrupts = <GIC_SPI 1824 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 1825
2928 iommus = <&adreno_smm 1826 iommus = <&adreno_smmu 0 0x401>;
2929 1827
2930 operating-points-v2 = 1828 operating-points-v2 = <&gpu_opp_table>;
2931 1829
2932 qcom,gmu = <&gmu>; 1830 qcom,gmu = <&gmu>;
2933 1831
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 1832 status = "disabled";
2939 1833
2940 zap-shader { 1834 zap-shader {
2941 memory-region 1835 memory-region = <&gpu_mem>;
2942 }; 1836 };
2943 1837
>> 1838 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 1839 gpu_opp_table: opp-table {
2945 compatible = 1840 compatible = "operating-points-v2";
2946 1841
2947 opp-670000000 1842 opp-670000000 {
2948 opp-h 1843 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 1844 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 1845 };
2952 1846
2953 opp-587000000 1847 opp-587000000 {
2954 opp-h 1848 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 1849 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 1850 };
2958 1851
2959 opp-525000000 1852 opp-525000000 {
2960 opp-h 1853 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 1854 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 1855 };
2964 1856
2965 opp-490000000 1857 opp-490000000 {
2966 opp-h 1858 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 1859 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 1860 };
2970 1861
2971 opp-441600000 1862 opp-441600000 {
2972 opp-h 1863 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 1864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 1865 };
2976 1866
2977 opp-400000000 1867 opp-400000000 {
2978 opp-h 1868 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 1869 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 1870 };
2982 1871
2983 opp-305000000 1872 opp-305000000 {
2984 opp-h 1873 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 1874 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 1875 };
2988 }; 1876 };
2989 }; 1877 };
2990 1878
2991 gmu: gmu@3d6a000 { 1879 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 1880 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 1881
2994 reg = <0 0x03d6a000 0 1882 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 1883 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 1884 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 1885 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 1886 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 1887
3000 interrupts = <GIC_SPI 1888 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 1889 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 1890 interrupt-names = "hfi", "gmu";
3003 1891
3004 clocks = <&gpucc GPU_ 1892 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 1893 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 1894 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 1895 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 1896 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 1897 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 1898
3011 power-domains = <&gpu 1899 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 1900 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 1901 power-domain-names = "cx", "gx";
3014 1902
3015 iommus = <&adreno_smm 1903 iommus = <&adreno_smmu 5 0x400>;
3016 1904
3017 operating-points-v2 = 1905 operating-points-v2 = <&gmu_opp_table>;
3018 1906
3019 status = "disabled"; 1907 status = "disabled";
3020 1908
3021 gmu_opp_table: opp-ta 1909 gmu_opp_table: opp-table {
3022 compatible = 1910 compatible = "operating-points-v2";
3023 1911
3024 opp-200000000 1912 opp-200000000 {
3025 opp-h 1913 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 1914 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 1915 };
3028 }; 1916 };
3029 }; 1917 };
3030 1918
3031 gpucc: clock-controller@3d900 1919 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 1920 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 1921 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 1922 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 1923 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 1924 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 1925 clock-names = "bi_tcxo",
3038 "gcc_gp 1926 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 1927 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 1928 #clock-cells = <1>;
3041 #reset-cells = <1>; 1929 #reset-cells = <1>;
3042 #power-domain-cells = 1930 #power-domain-cells = <1>;
3043 }; 1931 };
3044 1932
3045 adreno_smmu: iommu@3da0000 { 1933 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 1934 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 1935 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 1936 #iommu-cells = <2>;
3050 #global-interrupts = 1937 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 1938 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 1939 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 1940 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 1941 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 1942 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 1943 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 1944 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 1945 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 1946 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 1947 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 1948 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 1949 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 1950 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 1951 clock-names = "ahb", "bus", "iface";
3065 1952
3066 power-domains = <&gpu 1953 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 1954 };
3069 1955
3070 slpi: remoteproc@5c00000 { 1956 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 1957 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 1958 reg = <0 0x05c00000 0 0x4000>;
3073 1959
3074 interrupts-extended = !! 1960 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 1961 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 1962 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 1963 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 1964 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 1965 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 1966 "handover", "stop-ack";
3081 1967
3082 clocks = <&rpmhcc RPM 1968 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 1969 clock-names = "xo";
3084 1970
3085 power-domains = <&rpm !! 1971 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
3086 <&rpm !! 1972 <&rpmhpd SM8250_LCX>,
3087 power-domain-names = !! 1973 <&rpmhpd SM8250_LMX>;
>> 1974 power-domain-names = "load_state", "lcx", "lmx";
3088 1975
3089 memory-region = <&slp 1976 memory-region = <&slpi_mem>;
3090 1977
3091 qcom,qmp = <&aoss_qmp <<
3092 <<
3093 qcom,smem-states = <& 1978 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 1979 qcom,smem-state-names = "stop";
3095 1980
3096 status = "disabled"; 1981 status = "disabled";
3097 1982
3098 glink-edge { 1983 glink-edge {
3099 interrupts-ex 1984 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 1985 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 1986 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 1987 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 1988 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 1989
3105 label = "slpi 1990 label = "slpi";
3106 qcom,remote-p 1991 qcom,remote-pid = <3>;
3107 1992
3108 fastrpc { 1993 fastrpc {
3109 compa 1994 compatible = "qcom,fastrpc";
3110 qcom, 1995 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 1996 label = "sdsp";
3112 qcom, <<
3113 #addr 1997 #address-cells = <1>;
3114 #size 1998 #size-cells = <0>;
3115 1999
3116 compu 2000 compute-cb@1 {
3117 2001 compatible = "qcom,fastrpc-compute-cb";
3118 2002 reg = <1>;
3119 2003 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2004 };
3121 2005
3122 compu 2006 compute-cb@2 {
3123 2007 compatible = "qcom,fastrpc-compute-cb";
3124 2008 reg = <2>;
3125 2009 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2010 };
3127 2011
3128 compu 2012 compute-cb@3 {
3129 2013 compatible = "qcom,fastrpc-compute-cb";
3130 2014 reg = <3>;
3131 2015 iommus = <&apps_smmu 0x0543 0x0>;
3132 2016 /* note: shared-cb = <4> in downstream */
3133 }; 2017 };
3134 }; 2018 };
3135 }; 2019 };
3136 }; 2020 };
3137 2021
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 2022 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 2023 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 2024 reg = <0 0x08300000 0 0x10000>;
3777 2025
3778 interrupts-extended = !! 2026 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 2027 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 2028 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 2029 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 2030 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 2031 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 2032 "handover", "stop-ack";
3785 2033
3786 clocks = <&rpmhcc RPM 2034 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 2035 clock-names = "xo";
3788 2036
3789 power-domains = <&rpm !! 2037 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 2038 <&rpmhpd SM8250_CX>;
>> 2039 power-domain-names = "load_state", "cx";
3790 2040
3791 memory-region = <&cds 2041 memory-region = <&cdsp_mem>;
3792 2042
3793 qcom,qmp = <&aoss_qmp <<
3794 <<
3795 qcom,smem-states = <& 2043 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 2044 qcom,smem-state-names = "stop";
3797 2045
3798 status = "disabled"; 2046 status = "disabled";
3799 2047
3800 glink-edge { 2048 glink-edge {
3801 interrupts-ex 2049 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2050 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2051 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2052 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2053 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2054
3807 label = "cdsp 2055 label = "cdsp";
3808 qcom,remote-p 2056 qcom,remote-pid = <5>;
3809 2057
3810 fastrpc { 2058 fastrpc {
3811 compa 2059 compatible = "qcom,fastrpc";
3812 qcom, 2060 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2061 label = "cdsp";
3814 qcom, <<
3815 #addr 2062 #address-cells = <1>;
3816 #size 2063 #size-cells = <0>;
3817 2064
3818 compu 2065 compute-cb@1 {
3819 2066 compatible = "qcom,fastrpc-compute-cb";
3820 2067 reg = <1>;
3821 2068 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2069 };
3823 2070
3824 compu 2071 compute-cb@2 {
3825 2072 compatible = "qcom,fastrpc-compute-cb";
3826 2073 reg = <2>;
3827 2074 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2075 };
3829 2076
3830 compu 2077 compute-cb@3 {
3831 2078 compatible = "qcom,fastrpc-compute-cb";
3832 2079 reg = <3>;
3833 2080 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2081 };
3835 2082
3836 compu 2083 compute-cb@4 {
3837 2084 compatible = "qcom,fastrpc-compute-cb";
3838 2085 reg = <4>;
3839 2086 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2087 };
3841 2088
3842 compu 2089 compute-cb@5 {
3843 2090 compatible = "qcom,fastrpc-compute-cb";
3844 2091 reg = <5>;
3845 2092 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2093 };
3847 2094
3848 compu 2095 compute-cb@6 {
3849 2096 compatible = "qcom,fastrpc-compute-cb";
3850 2097 reg = <6>;
3851 2098 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2099 };
3853 2100
3854 compu 2101 compute-cb@7 {
3855 2102 compatible = "qcom,fastrpc-compute-cb";
3856 2103 reg = <7>;
3857 2104 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2105 };
3859 2106
3860 compu 2107 compute-cb@8 {
3861 2108 compatible = "qcom,fastrpc-compute-cb";
3862 2109 reg = <8>;
3863 2110 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2111 };
3865 2112
3866 /* no 2113 /* note: secure cb9 in downstream */
3867 }; 2114 };
3868 }; 2115 };
3869 }; 2116 };
3870 2117
>> 2118 sound: sound {
>> 2119 };
>> 2120
3871 usb_1_hsphy: phy@88e3000 { 2121 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2122 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2123 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2124 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2125 status = "disabled";
3876 #phy-cells = <0>; 2126 #phy-cells = <0>;
3877 2127
3878 clocks = <&rpmhcc RPM 2128 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2129 clock-names = "ref";
3880 2130
3881 resets = <&gcc GCC_QU 2131 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2132 };
3883 2133
3884 usb_2_hsphy: phy@88e4000 { 2134 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2135 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2136 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2137 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2138 status = "disabled";
3889 #phy-cells = <0>; 2139 #phy-cells = <0>;
3890 2140
3891 clocks = <&rpmhcc RPM 2141 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2142 clock-names = "ref";
3893 2143
3894 resets = <&gcc GCC_QU 2144 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2145 };
3896 2146
3897 usb_1_qmpphy: phy@88e8000 { !! 2147 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2148 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2149 reg = <0 0x088e9000 0 0x200>,
>> 2150 <0 0x088e8000 0 0x40>,
>> 2151 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2152 status = "disabled";
>> 2153 #address-cells = <2>;
>> 2154 #size-cells = <2>;
>> 2155 ranges;
3901 2156
3902 clocks = <&gcc GCC_US 2157 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2158 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2159 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2160 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2161
3911 resets = <&gcc GCC_US 2162 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2163 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2164 reset-names = "phy", "common";
3914 2165
3915 #clock-cells = <1>; !! 2166 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2167 reg = <0 0x088e9200 0 0x200>,
3917 !! 2168 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2169 <0 0x088e9c00 0 0x400>,
3919 !! 2170 <0 0x088e9600 0 0x200>,
3920 ports { !! 2171 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2172 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2173 #clock-cells = <0>;
3923 !! 2174 #phy-cells = <0>;
3924 port@0 { !! 2175 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2176 clock-names = "pipe0";
3926 usb_1 !! 2177 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2178 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2179
3940 usb_1 !! 2180 dp_phy: dp-phy@88ea200 {
3941 }; !! 2181 reg = <0 0x088ea200 0 0x200>,
>> 2182 <0 0x088ea400 0 0x200>,
>> 2183 <0 0x088eac00 0 0x400>,
>> 2184 <0 0x088ea600 0 0x200>,
>> 2185 <0 0x088ea800 0 0x200>,
>> 2186 <0 0x088eaa00 0 0x100>;
>> 2187 #phy-cells = <0>;
>> 2188 #clock-cells = <1>;
>> 2189 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 2190 clock-names = "pipe0";
>> 2191 clock-output-names = "usb3_phy_pipe_clk_src";
3942 }; 2192 };
3943 }; 2193 };
3944 2194
3945 usb_2_qmpphy: phy@88eb000 { 2195 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2196 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2197 reg = <0 0x088eb000 0 0x200>;
>> 2198 status = "disabled";
>> 2199 #address-cells = <2>;
>> 2200 #size-cells = <2>;
>> 2201 ranges;
3948 2202
3949 clocks = <&gcc GCC_US 2203 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2204 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2205 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2206 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2207 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2208
3961 resets = <&gcc GCC_US !! 2209 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2210 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2211 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2212
3966 status = "disabled"; !! 2213 usb_2_ssphy: lanes@88eb200 {
>> 2214 reg = <0 0x088eb200 0 0x200>,
>> 2215 <0 0x088eb400 0 0x200>,
>> 2216 <0 0x088eb800 0 0x800>;
>> 2217 #clock-cells = <0>;
>> 2218 #phy-cells = <0>;
>> 2219 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2220 clock-names = "pipe0";
>> 2221 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2222 };
3967 }; 2223 };
3968 2224
3969 sdhc_2: mmc@8804000 { !! 2225 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2226 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2227 reg = <0 0x08804000 0 0x1000>;
3972 2228
3973 interrupts = <GIC_SPI 2229 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2230 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2231 interrupt-names = "hc_irq", "pwr_irq";
3976 2232
3977 clocks = <&gcc GCC_SD 2233 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2234 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2235 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2236 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2237 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2238 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2239 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2240 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2241 operating-points-v2 = <&sdhc2_opp_table>;
3986 2242
3987 status = "disabled"; 2243 status = "disabled";
3988 2244
3989 sdhc2_opp_table: opp- !! 2245 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2246 compatible = "operating-points-v2";
3991 2247
3992 opp-19200000 2248 opp-19200000 {
3993 opp-h 2249 opp-hz = /bits/ 64 <19200000>;
3994 requi 2250 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2251 };
3996 2252
3997 opp-50000000 2253 opp-50000000 {
3998 opp-h 2254 opp-hz = /bits/ 64 <50000000>;
3999 requi 2255 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2256 };
4001 2257
4002 opp-100000000 2258 opp-100000000 {
4003 opp-h 2259 opp-hz = /bits/ 64 <100000000>;
4004 requi 2260 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2261 };
4006 2262
4007 opp-202000000 2263 opp-202000000 {
4008 opp-h 2264 opp-hz = /bits/ 64 <202000000>;
4009 requi 2265 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2266 };
4011 }; 2267 };
4012 }; 2268 };
4013 2269
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2270 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2271 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2272 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2273 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2274 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2275 };
4142 2276
4143 gem_noc: interconnect@9100000 2277 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2278 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2279 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2280 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2281 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2282 };
4149 2283
4150 npu_noc: interconnect@9990000 2284 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2285 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2286 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2287 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2288 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2289 };
4156 2290
4157 usb_1: usb@a6f8800 { 2291 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2292 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2293 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2294 status = "disabled";
4161 #address-cells = <2>; 2295 #address-cells = <2>;
4162 #size-cells = <2>; 2296 #size-cells = <2>;
4163 ranges; 2297 ranges;
4164 dma-ranges; 2298 dma-ranges;
4165 2299
4166 clocks = <&gcc GCC_CF 2300 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 2301 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 2302 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 2303 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2304 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 2305 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 2306 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 2307 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 2308
4179 assigned-clocks = <&g 2309 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 2310 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 2311 assigned-clock-rates = <19200000>, <200000000>;
4182 2312
4183 interrupts-extended = !! 2313 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 2314 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 2315 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 2316 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 2317 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 2318 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 2319
4194 power-domains = <&gcc 2320 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 2321
4197 resets = <&gcc GCC_US 2322 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 2323
4199 interconnects = <&agg !! 2324 usb_1_dwc3: dwc3@a600000 {
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 <<
4204 compatible = 2325 compatible = "snps,dwc3";
4205 reg = <0 0x0a 2326 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 2327 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 2328 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 2329 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 2330 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 2331 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 2332 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 2333 };
4233 }; 2334 };
4234 2335
4235 system-cache-controller@92000 2336 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 2337 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 2338 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 2339 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 2340 };
4243 2341
4244 usb_2: usb@a8f8800 { 2342 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 2343 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 2344 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 2345 status = "disabled";
4248 #address-cells = <2>; 2346 #address-cells = <2>;
4249 #size-cells = <2>; 2347 #size-cells = <2>;
4250 ranges; 2348 ranges;
4251 dma-ranges; 2349 dma-ranges;
4252 2350
4253 clocks = <&gcc GCC_CF 2351 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 2352 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 2353 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 2354 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2355 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 2356 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 2357 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 2358 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 2359
4266 assigned-clocks = <&g 2360 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 2361 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 2362 assigned-clock-rates = <19200000>, <200000000>;
4269 2363
4270 interrupts-extended = !! 2364 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 2365 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 2366 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 2367 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 2368 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 2369 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 2370
4281 power-domains = <&gcc 2371 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 2372
4284 resets = <&gcc GCC_US 2373 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 2374
4286 interconnects = <&agg !! 2375 usb_2_dwc3: dwc3@a800000 {
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 <<
4291 compatible = 2376 compatible = "snps,dwc3";
4292 reg = <0 0x0a 2377 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 2378 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 2379 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 2380 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 2381 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 2382 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 2383 phy-names = "usb2-phy", "usb3-phy";
4299 }; 2384 };
4300 }; 2385 };
4301 2386
4302 venus: video-codec@aa00000 { 2387 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 2388 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 2389 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 2390 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 2391 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 2392 <&videocc MVS0_GDSC>,
4308 <&rpm !! 2393 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 2394 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 2395 operating-points-v2 = <&venus_opp_table>;
4311 2396
4312 clocks = <&gcc GCC_VI 2397 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 2398 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 2399 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 2400 clock-names = "iface", "core", "vcodec0_core";
4316 2401
4317 interconnects = <&gem !! 2402 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 2403 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 2404 interconnect-names = "cpu-cfg", "video-mem";
4320 2405
4321 iommus = <&apps_smmu 2406 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 2407 memory-region = <&video_mem>;
4323 2408
4324 resets = <&gcc GCC_VI 2409 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 2410 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 2411 reset-names = "bus", "core";
4327 2412
4328 status = "disabled"; 2413 status = "disabled";
4329 2414
4330 video-decoder { 2415 video-decoder {
4331 compatible = 2416 compatible = "venus-decoder";
4332 }; 2417 };
4333 2418
4334 video-encoder { 2419 video-encoder {
4335 compatible = 2420 compatible = "venus-encoder";
4336 }; 2421 };
4337 2422
4338 venus_opp_table: opp- !! 2423 venus_opp_table: venus-opp-table {
4339 compatible = 2424 compatible = "operating-points-v2";
4340 2425
4341 opp-720000000 2426 opp-720000000 {
4342 opp-h 2427 opp-hz = /bits/ 64 <720000000>;
4343 requi 2428 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 2429 };
4345 2430
4346 opp-101400000 2431 opp-1014000000 {
4347 opp-h 2432 opp-hz = /bits/ 64 <1014000000>;
4348 requi 2433 required-opps = <&rpmhpd_opp_svs>;
4349 }; 2434 };
4350 2435
4351 opp-109800000 2436 opp-1098000000 {
4352 opp-h 2437 opp-hz = /bits/ 64 <1098000000>;
4353 requi 2438 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 2439 };
4355 2440
4356 opp-133200000 2441 opp-1332000000 {
4357 opp-h 2442 opp-hz = /bits/ 64 <1332000000>;
4358 requi 2443 required-opps = <&rpmhpd_opp_nom>;
4359 }; 2444 };
4360 }; 2445 };
4361 }; 2446 };
4362 2447
4363 videocc: clock-controller@abf 2448 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 2449 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 2450 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 2451 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 2452 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 2453 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 2454 mmcx-supply = <&mmcx_reg>;
4370 required-opps = <&rpm <<
4371 clock-names = "iface" 2455 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 2456 #clock-cells = <1>;
4373 #reset-cells = <1>; 2457 #reset-cells = <1>;
4374 #power-domain-cells = 2458 #power-domain-cells = <1>;
4375 }; 2459 };
4376 2460
4377 cci0: cci@ac4f000 { !! 2461 mdss: mdss@ae00000 {
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm 2462 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 2463 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 2464 reg-names = "mdss";
4661 2465
4662 interconnects = <&mms !! 2466 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 2467 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 2468 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 2469
4666 power-domains = <&dis 2470 power-domains = <&dispcc MDSS_GDSC>;
4667 2471
4668 clocks = <&dispcc DIS 2472 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 2473 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 2474 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 2475 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 2476 clock-names = "iface", "bus", "nrt_bus", "core";
4673 2477
>> 2478 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2479 assigned-clock-rates = <460000000>;
>> 2480
4674 interrupts = <GIC_SPI 2481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 2482 interrupt-controller;
4676 #interrupt-cells = <1 2483 #interrupt-cells = <1>;
4677 2484
4678 iommus = <&apps_smmu 2485 iommus = <&apps_smmu 0x820 0x402>;
4679 2486
4680 status = "disabled"; 2487 status = "disabled";
4681 2488
4682 #address-cells = <2>; 2489 #address-cells = <2>;
4683 #size-cells = <2>; 2490 #size-cells = <2>;
4684 ranges; 2491 ranges;
4685 2492
4686 mdss_mdp: display-con !! 2493 mdss_mdp: mdp@ae01000 {
4687 compatible = 2494 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 2495 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 2496 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 2497 reg-names = "mdp", "vbif";
4691 2498
4692 clocks = <&di 2499 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 2500 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 2501 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 2502 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 2503 clock-names = "iface", "bus", "core", "vsync";
4697 2504
4698 assigned-cloc !! 2505 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 2506 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 2507 assigned-clock-rates = <460000000>,
>> 2508 <19200000>;
4700 2509
4701 operating-poi 2510 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 2511 power-domains = <&rpmhpd SM8250_MMCX>;
4703 2512
4704 interrupt-par 2513 interrupt-parent = <&mdss>;
4705 interrupts = !! 2514 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4706 2515
4707 ports { 2516 ports {
4708 #addr 2517 #address-cells = <1>;
4709 #size 2518 #size-cells = <0>;
4710 2519
4711 port@ 2520 port@0 {
4712 2521 reg = <0>;
4713 2522 dpu_intf1_out: endpoint {
4714 !! 2523 remote-endpoint = <&dsi0_in>;
4715 2524 };
4716 }; 2525 };
4717 2526
4718 port@ 2527 port@1 {
4719 2528 reg = <1>;
4720 2529 dpu_intf2_out: endpoint {
4721 !! 2530 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 2531 };
4731 }; 2532 };
4732 }; 2533 };
4733 2534
4734 mdp_opp_table !! 2535 mdp_opp_table: mdp-opp-table {
4735 compa 2536 compatible = "operating-points-v2";
4736 2537
4737 opp-2 2538 opp-200000000 {
4738 2539 opp-hz = /bits/ 64 <200000000>;
4739 2540 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 2541 };
4741 2542
4742 opp-3 2543 opp-300000000 {
4743 2544 opp-hz = /bits/ 64 <300000000>;
4744 2545 required-opps = <&rpmhpd_opp_svs>;
4745 }; 2546 };
4746 2547
4747 opp-3 2548 opp-345000000 {
4748 2549 opp-hz = /bits/ 64 <345000000>;
4749 2550 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 2551 };
4751 2552
4752 opp-4 2553 opp-460000000 {
4753 2554 opp-hz = /bits/ 64 <460000000>;
4754 2555 required-opps = <&rpmhpd_opp_nom>;
4755 }; 2556 };
4756 }; 2557 };
4757 }; 2558 };
4758 2559
4759 mdss_dp: displayport- !! 2560 dsi0: dsi@ae94000 {
4760 compatible = !! 2561 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 2562 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 2563 reg-names = "dsi_ctrl";
4843 2564
4844 interrupt-par 2565 interrupt-parent = <&mdss>;
4845 interrupts = !! 2566 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 2567
4847 clocks = <&di 2568 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 2569 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 2570 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 2571 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 2572 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 2573 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 2574 clock-names = "byte",
4854 2575 "byte_intf",
4855 2576 "pixel",
4856 2577 "core",
4857 2578 "iface",
4858 2579 "bus";
4859 2580
4860 assigned-cloc <<
4861 assigned-cloc <<
4862 <<
4863 operating-poi 2581 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 2582 power-domains = <&rpmhpd SM8250_MMCX>;
4865 2583
4866 phys = <&mdss !! 2584 phys = <&dsi0_phy>;
>> 2585 phy-names = "dsi";
4867 2586
4868 status = "dis 2587 status = "disabled";
4869 2588
4870 #address-cell 2589 #address-cells = <1>;
4871 #size-cells = 2590 #size-cells = <0>;
4872 2591
4873 ports { 2592 ports {
4874 #addr 2593 #address-cells = <1>;
4875 #size 2594 #size-cells = <0>;
4876 2595
4877 port@ 2596 port@0 {
4878 2597 reg = <0>;
4879 !! 2598 dsi0_in: endpoint {
4880 2599 remote-endpoint = <&dpu_intf1_out>;
4881 2600 };
4882 }; 2601 };
4883 2602
4884 port@ 2603 port@1 {
4885 2604 reg = <1>;
4886 !! 2605 dsi0_out: endpoint {
4887 2606 };
4888 }; 2607 };
4889 }; 2608 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 2609 };
4910 2610
4911 mdss_dsi0_phy: phy@ae !! 2611 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 2612 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 2613 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 2614 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 2615 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 2616 reg-names = "dsi_phy",
4917 " 2617 "dsi_phy_lane",
4918 " 2618 "dsi_pll";
4919 2619
4920 #clock-cells 2620 #clock-cells = <1>;
4921 #phy-cells = 2621 #phy-cells = <0>;
4922 2622
4923 clocks = <&di 2623 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 2624 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 2625 clock-names = "iface", "ref";
4926 2626
4927 status = "dis 2627 status = "disabled";
4928 }; 2628 };
4929 2629
4930 mdss_dsi1: dsi@ae9600 !! 2630 dsi1: dsi@ae96000 {
4931 compatible = !! 2631 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 2632 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 2633 reg-names = "dsi_ctrl";
4935 2634
4936 interrupt-par 2635 interrupt-parent = <&mdss>;
4937 interrupts = !! 2636 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 2637
4939 clocks = <&di 2638 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 2639 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 2640 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 2641 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 2642 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 2643 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 2644 clock-names = "byte",
4946 2645 "byte_intf",
4947 2646 "pixel",
4948 2647 "core",
4949 2648 "iface",
4950 2649 "bus";
4951 2650
4952 assigned-cloc <<
4953 assigned-cloc <<
4954 <<
4955 operating-poi 2651 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 2652 power-domains = <&rpmhpd SM8250_MMCX>;
4957 2653
4958 phys = <&mdss !! 2654 phys = <&dsi1_phy>;
>> 2655 phy-names = "dsi";
4959 2656
4960 status = "dis 2657 status = "disabled";
4961 2658
4962 #address-cell 2659 #address-cells = <1>;
4963 #size-cells = 2660 #size-cells = <0>;
4964 2661
4965 ports { 2662 ports {
4966 #addr 2663 #address-cells = <1>;
4967 #size 2664 #size-cells = <0>;
4968 2665
4969 port@ 2666 port@0 {
4970 2667 reg = <0>;
4971 !! 2668 dsi1_in: endpoint {
4972 2669 remote-endpoint = <&dpu_intf2_out>;
4973 2670 };
4974 }; 2671 };
4975 2672
4976 port@ 2673 port@1 {
4977 2674 reg = <1>;
4978 !! 2675 dsi1_out: endpoint {
4979 2676 };
4980 }; 2677 };
4981 }; 2678 };
4982 }; 2679 };
4983 2680
4984 mdss_dsi1_phy: phy@ae !! 2681 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 2682 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 2683 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 2684 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 2685 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 2686 reg-names = "dsi_phy",
4990 " 2687 "dsi_phy_lane",
4991 " 2688 "dsi_pll";
4992 2689
4993 #clock-cells 2690 #clock-cells = <1>;
4994 #phy-cells = 2691 #phy-cells = <0>;
4995 2692
4996 clocks = <&di 2693 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 2694 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 2695 clock-names = "iface", "ref";
4999 2696
5000 status = "dis 2697 status = "disabled";
>> 2698
>> 2699 dsi_opp_table: dsi-opp-table {
>> 2700 compatible = "operating-points-v2";
>> 2701
>> 2702 opp-187500000 {
>> 2703 opp-hz = /bits/ 64 <187500000>;
>> 2704 required-opps = <&rpmhpd_opp_low_svs>;
>> 2705 };
>> 2706
>> 2707 opp-300000000 {
>> 2708 opp-hz = /bits/ 64 <300000000>;
>> 2709 required-opps = <&rpmhpd_opp_svs>;
>> 2710 };
>> 2711
>> 2712 opp-358000000 {
>> 2713 opp-hz = /bits/ 64 <358000000>;
>> 2714 required-opps = <&rpmhpd_opp_svs_l1>;
>> 2715 };
>> 2716 };
5001 }; 2717 };
5002 }; 2718 };
5003 2719
5004 dispcc: clock-controller@af00 2720 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 2721 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 2722 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 2723 mmcx-supply = <&mmcx_reg>;
5008 required-opps = <&rpm <<
5009 clocks = <&rpmhcc RPM 2724 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 2725 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 2726 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 2727 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 2728 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 2729 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 2730 <&dp_phy 1>;
5016 clock-names = "bi_tcx 2731 clock-names = "bi_tcxo",
5017 "dsi0_p 2732 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 2733 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 2734 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 2735 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 2736 "dp_phy_pll_link_clk",
5022 "dp_phy 2737 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 2738 #clock-cells = <1>;
5024 #reset-cells = <1>; 2739 #reset-cells = <1>;
5025 #power-domain-cells = 2740 #power-domain-cells = <1>;
5026 }; 2741 };
5027 2742
5028 pdc: interrupt-controller@b22 2743 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 2744 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 2745 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 2746 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 2747 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 2748 #interrupt-cells = <2>;
5034 interrupt-parent = <& 2749 interrupt-parent = <&intc>;
5035 interrupt-controller; 2750 interrupt-controller;
5036 }; 2751 };
5037 2752
5038 tsens0: thermal-sensor@c26300 2753 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 2754 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 2755 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 2756 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 2757 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 2758 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 2759 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 2760 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 2761 #thermal-sensor-cells = <1>;
5047 }; 2762 };
5048 2763
5049 tsens1: thermal-sensor@c26500 2764 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 2765 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 2766 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 2767 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 2768 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 2769 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 2770 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 2771 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 2772 #thermal-sensor-cells = <1>;
5058 }; 2773 };
5059 2774
5060 aoss_qmp: power-management@c3 !! 2775 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm !! 2776 compatible = "qcom,sm8250-aoss-qmp";
5062 reg = <0 0x0c300000 0 !! 2777 reg = <0 0x0c300000 0 0x100000>;
5063 interrupts-extended = 2778 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 2779 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 2780 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 2781 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 2782 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 2783
5069 #clock-cells = <0>; 2784 #clock-cells = <0>;
5070 }; !! 2785 #power-domain-cells = <1>;
5071 <<
5072 sram@c3f0000 { <<
5073 compatible = "qcom,rp <<
5074 reg = <0 0x0c3f0000 0 <<
5075 }; 2786 };
5076 2787
5077 spmi_bus: spmi@c440000 { 2788 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 2789 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 2790 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 2791 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 2792 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 2793 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 2794 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 2795 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 2796 interrupt-names = "periph_irq";
5086 interrupts-extended = 2797 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 2798 qcom,ee = <0>;
5088 qcom,channel = <0>; 2799 qcom,channel = <0>;
5089 #address-cells = <2>; 2800 #address-cells = <2>;
5090 #size-cells = <0>; 2801 #size-cells = <0>;
5091 interrupt-controller; 2802 interrupt-controller;
5092 #interrupt-cells = <4 2803 #interrupt-cells = <4>;
5093 }; 2804 };
5094 2805
5095 tlmm: pinctrl@f100000 { 2806 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 2807 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 2808 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 2809 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 2810 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 2811 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 2812 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 2813 gpio-controller;
5103 #gpio-cells = <2>; 2814 #gpio-cells = <2>;
5104 interrupt-controller; 2815 interrupt-controller;
5105 #interrupt-cells = <2 2816 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 2817 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 2818 wakeup-parent = <&pdc>;
5108 2819
5109 cam2_default: cam2-de !! 2820 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 2821 sclk {
5111 pins !! 2822 pins = "gpio138";
5112 funct !! 2823 function = "mi2s0_sck";
5113 drive !! 2824 drive-strength = <8>;
5114 bias- 2825 bias-disable;
5115 }; 2826 };
5116 2827
5117 mclk-pins { !! 2828 ws {
5118 pins !! 2829 pins = "gpio141";
5119 funct !! 2830 function = "mi2s0_ws";
5120 drive !! 2831 drive-strength = <8>;
>> 2832 output-high;
>> 2833 };
>> 2834
>> 2835 data0 {
>> 2836 pins = "gpio139";
>> 2837 function = "mi2s0_data0";
>> 2838 drive-strength = <8>;
5121 bias- 2839 bias-disable;
>> 2840 output-high;
>> 2841 };
>> 2842
>> 2843 data1 {
>> 2844 pins = "gpio140";
>> 2845 function = "mi2s0_data1";
>> 2846 drive-strength = <8>;
>> 2847 output-high;
5122 }; 2848 };
5123 }; 2849 };
5124 2850
5125 cam2_suspend: cam2-su !! 2851 qup_i2c0_default: qup-i2c0-default {
5126 rst-pins { !! 2852 mux {
5127 pins !! 2853 pins = "gpio28", "gpio29";
5128 funct !! 2854 function = "qup0";
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; 2855 };
5133 2856
5134 mclk-pins { !! 2857 config {
5135 pins !! 2858 pins = "gpio28", "gpio29";
5136 funct <<
5137 drive 2859 drive-strength = <2>;
5138 bias- 2860 bias-disable;
5139 }; 2861 };
5140 }; 2862 };
5141 2863
5142 cci0_default: cci0-de !! 2864 qup_i2c1_default: qup-i2c1-default {
5143 cci0_i2c0_def !! 2865 pinmux {
5144 /* SD !! 2866 pins = "gpio4", "gpio5";
5145 pins !! 2867 function = "qup1";
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; 2868 };
5151 2869
5152 cci0_i2c1_def !! 2870 config {
5153 /* SD !! 2871 pins = "gpio4", "gpio5";
5154 pins !! 2872 drive-strength = <2>;
5155 funct !! 2873 bias-disable;
5156 <<
5157 bias- <<
5158 drive <<
5159 }; 2874 };
5160 }; 2875 };
5161 2876
5162 cci0_sleep: cci0-slee !! 2877 qup_i2c2_default: qup-i2c2-default {
5163 cci0_i2c0_sle !! 2878 mux {
5164 /* SD !! 2879 pins = "gpio115", "gpio116";
5165 pins !! 2880 function = "qup2";
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; 2881 };
5171 2882
5172 cci0_i2c1_sle !! 2883 config {
5173 /* SD !! 2884 pins = "gpio115", "gpio116";
5174 pins !! 2885 drive-strength = <2>;
5175 funct !! 2886 bias-disable;
5176 <<
5177 drive <<
5178 bias- <<
5179 }; 2887 };
5180 }; 2888 };
5181 2889
5182 cci1_default: cci1-de !! 2890 qup_i2c3_default: qup-i2c3-default {
5183 cci1_i2c0_def !! 2891 mux {
5184 /* SD !! 2892 pins = "gpio119", "gpio120";
5185 pins !! 2893 function = "qup3";
5186 funct !! 2894 };
5187 2895
5188 bias- !! 2896 config {
5189 drive !! 2897 pins = "gpio119", "gpio120";
>> 2898 drive-strength = <2>;
>> 2899 bias-disable;
5190 }; 2900 };
>> 2901 };
5191 2902
5192 cci1_i2c1_def !! 2903 qup_i2c4_default: qup-i2c4-default {
5193 /* SD !! 2904 mux {
5194 pins !! 2905 pins = "gpio8", "gpio9";
5195 funct !! 2906 function = "qup4";
>> 2907 };
5196 2908
5197 bias- !! 2909 config {
5198 drive !! 2910 pins = "gpio8", "gpio9";
>> 2911 drive-strength = <2>;
>> 2912 bias-disable;
5199 }; 2913 };
5200 }; 2914 };
5201 2915
5202 cci1_sleep: cci1-slee !! 2916 qup_i2c5_default: qup-i2c5-default {
5203 cci1_i2c0_sle !! 2917 mux {
5204 /* SD !! 2918 pins = "gpio12", "gpio13";
5205 pins !! 2919 function = "qup5";
5206 funct !! 2920 };
5207 2921
5208 bias- !! 2922 config {
5209 drive !! 2923 pins = "gpio12", "gpio13";
>> 2924 drive-strength = <2>;
>> 2925 bias-disable;
5210 }; 2926 };
>> 2927 };
5211 2928
5212 cci1_i2c1_sle !! 2929 qup_i2c6_default: qup-i2c6-default {
5213 /* SD !! 2930 mux {
5214 pins !! 2931 pins = "gpio16", "gpio17";
5215 funct !! 2932 function = "qup6";
>> 2933 };
5216 2934
5217 bias- !! 2935 config {
5218 drive !! 2936 pins = "gpio16", "gpio17";
>> 2937 drive-strength = <2>;
>> 2938 bias-disable;
5219 }; 2939 };
5220 }; 2940 };
5221 2941
5222 pri_mi2s_active: pri- !! 2942 qup_i2c7_default: qup-i2c7-default {
5223 sclk-pins { !! 2943 mux {
5224 pins !! 2944 pins = "gpio20", "gpio21";
5225 funct !! 2945 function = "qup7";
5226 drive !! 2946 };
>> 2947
>> 2948 config {
>> 2949 pins = "gpio20", "gpio21";
>> 2950 drive-strength = <2>;
5227 bias- 2951 bias-disable;
5228 }; 2952 };
>> 2953 };
5229 2954
5230 ws-pins { !! 2955 qup_i2c8_default: qup-i2c8-default {
5231 pins !! 2956 mux {
5232 funct !! 2957 pins = "gpio24", "gpio25";
5233 drive !! 2958 function = "qup8";
5234 outpu <<
5235 }; 2959 };
5236 2960
5237 data0-pins { !! 2961 config {
5238 pins !! 2962 pins = "gpio24", "gpio25";
5239 funct !! 2963 drive-strength = <2>;
5240 drive <<
5241 bias- 2964 bias-disable;
5242 outpu <<
5243 }; 2965 };
>> 2966 };
5244 2967
5245 data1-pins { !! 2968 qup_i2c9_default: qup-i2c9-default {
5246 pins !! 2969 mux {
5247 funct !! 2970 pins = "gpio125", "gpio126";
5248 drive !! 2971 function = "qup9";
5249 outpu <<
5250 }; 2972 };
5251 }; <<
5252 2973
5253 qup_i2c0_default: qup !! 2974 config {
5254 pins = "gpio2 !! 2975 pins = "gpio125", "gpio126";
5255 function = "q !! 2976 drive-strength = <2>;
5256 drive-strengt !! 2977 bias-disable;
5257 bias-disable; !! 2978 };
5258 }; 2979 };
5259 2980
5260 qup_i2c1_default: qup !! 2981 qup_i2c10_default: qup-i2c10-default {
5261 pins = "gpio4 !! 2982 mux {
5262 function = "q !! 2983 pins = "gpio129", "gpio130";
5263 drive-strengt !! 2984 function = "qup10";
5264 bias-disable; !! 2985 };
5265 }; <<
5266 2986
5267 qup_i2c2_default: qup !! 2987 config {
5268 pins = "gpio1 !! 2988 pins = "gpio129", "gpio130";
5269 function = "q !! 2989 drive-strength = <2>;
5270 drive-strengt !! 2990 bias-disable;
5271 bias-disable; !! 2991 };
5272 }; 2992 };
5273 2993
5274 qup_i2c3_default: qup !! 2994 qup_i2c11_default: qup-i2c11-default {
5275 pins = "gpio1 !! 2995 mux {
5276 function = "q !! 2996 pins = "gpio60", "gpio61";
5277 drive-strengt !! 2997 function = "qup11";
5278 bias-disable; !! 2998 };
5279 }; <<
5280 2999
5281 qup_i2c4_default: qup !! 3000 config {
5282 pins = "gpio8 !! 3001 pins = "gpio60", "gpio61";
5283 function = "q !! 3002 drive-strength = <2>;
5284 drive-strengt !! 3003 bias-disable;
5285 bias-disable; !! 3004 };
5286 }; 3005 };
5287 3006
5288 qup_i2c5_default: qup !! 3007 qup_i2c12_default: qup-i2c12-default {
5289 pins = "gpio1 !! 3008 mux {
5290 function = "q !! 3009 pins = "gpio32", "gpio33";
5291 drive-strengt !! 3010 function = "qup12";
5292 bias-disable; !! 3011 };
5293 }; <<
5294 3012
5295 qup_i2c6_default: qup !! 3013 config {
5296 pins = "gpio1 !! 3014 pins = "gpio32", "gpio33";
5297 function = "q !! 3015 drive-strength = <2>;
5298 drive-strengt !! 3016 bias-disable;
5299 bias-disable; !! 3017 };
5300 }; 3018 };
5301 3019
5302 qup_i2c7_default: qup !! 3020 qup_i2c13_default: qup-i2c13-default {
5303 pins = "gpio2 !! 3021 mux {
5304 function = "q !! 3022 pins = "gpio36", "gpio37";
5305 drive-strengt !! 3023 function = "qup13";
5306 bias-disable; !! 3024 };
5307 }; <<
5308 3025
5309 qup_i2c8_default: qup !! 3026 config {
5310 pins = "gpio2 !! 3027 pins = "gpio36", "gpio37";
5311 function = "q !! 3028 drive-strength = <2>;
5312 drive-strengt !! 3029 bias-disable;
5313 bias-disable; !! 3030 };
5314 }; 3031 };
5315 3032
5316 qup_i2c9_default: qup !! 3033 qup_i2c14_default: qup-i2c14-default {
5317 pins = "gpio1 !! 3034 mux {
5318 function = "q !! 3035 pins = "gpio40", "gpio41";
5319 drive-strengt !! 3036 function = "qup14";
5320 bias-disable; !! 3037 };
5321 }; <<
5322 3038
5323 qup_i2c10_default: qu !! 3039 config {
5324 pins = "gpio1 !! 3040 pins = "gpio40", "gpio41";
5325 function = "q !! 3041 drive-strength = <2>;
5326 drive-strengt !! 3042 bias-disable;
5327 bias-disable; !! 3043 };
5328 }; 3044 };
5329 3045
5330 qup_i2c11_default: qu !! 3046 qup_i2c15_default: qup-i2c15-default {
5331 pins = "gpio6 !! 3047 mux {
5332 function = "q !! 3048 pins = "gpio44", "gpio45";
5333 drive-strengt !! 3049 function = "qup15";
5334 bias-disable; !! 3050 };
5335 }; <<
5336 3051
5337 qup_i2c12_default: qu !! 3052 config {
5338 pins = "gpio3 !! 3053 pins = "gpio44", "gpio45";
5339 function = "q !! 3054 drive-strength = <2>;
5340 drive-strengt !! 3055 bias-disable;
5341 bias-disable; !! 3056 };
5342 }; 3057 };
5343 3058
5344 qup_i2c13_default: qu !! 3059 qup_i2c16_default: qup-i2c16-default {
5345 pins = "gpio3 !! 3060 mux {
5346 function = "q !! 3061 pins = "gpio48", "gpio49";
5347 drive-strengt !! 3062 function = "qup16";
5348 bias-disable; !! 3063 };
5349 }; <<
5350 3064
5351 qup_i2c14_default: qu !! 3065 config {
5352 pins = "gpio4 !! 3066 pins = "gpio48", "gpio49";
5353 function = "q !! 3067 drive-strength = <2>;
5354 drive-strengt !! 3068 bias-disable;
5355 bias-disable; !! 3069 };
5356 }; 3070 };
5357 3071
5358 qup_i2c15_default: qu !! 3072 qup_i2c17_default: qup-i2c17-default {
5359 pins = "gpio4 !! 3073 mux {
5360 function = "q !! 3074 pins = "gpio52", "gpio53";
5361 drive-strengt !! 3075 function = "qup17";
5362 bias-disable; !! 3076 };
5363 }; <<
5364 3077
5365 qup_i2c16_default: qu !! 3078 config {
5366 pins = "gpio4 !! 3079 pins = "gpio52", "gpio53";
5367 function = "q !! 3080 drive-strength = <2>;
5368 drive-strengt !! 3081 bias-disable;
5369 bias-disable; !! 3082 };
5370 }; 3083 };
5371 3084
5372 qup_i2c17_default: qu !! 3085 qup_i2c18_default: qup-i2c18-default {
5373 pins = "gpio5 !! 3086 mux {
5374 function = "q !! 3087 pins = "gpio56", "gpio57";
5375 drive-strengt !! 3088 function = "qup18";
5376 bias-disable; !! 3089 };
5377 }; <<
5378 3090
5379 qup_i2c18_default: qu !! 3091 config {
5380 pins = "gpio5 !! 3092 pins = "gpio56", "gpio57";
5381 function = "q !! 3093 drive-strength = <2>;
5382 drive-strengt !! 3094 bias-disable;
5383 bias-disable; !! 3095 };
5384 }; 3096 };
5385 3097
5386 qup_i2c19_default: qu !! 3098 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 3099 mux {
5388 function = "q !! 3100 pins = "gpio0", "gpio1";
5389 drive-strengt !! 3101 function = "qup19";
5390 bias-disable; !! 3102 };
>> 3103
>> 3104 config {
>> 3105 pins = "gpio0", "gpio1";
>> 3106 drive-strength = <2>;
>> 3107 bias-disable;
>> 3108 };
5391 }; 3109 };
5392 3110
5393 qup_spi0_cs: qup-spi0 !! 3111 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 3112 pins = "gpio31";
5395 function = "q 3113 function = "qup0";
5396 }; 3114 };
5397 3115
5398 qup_spi0_cs_gpio: qup !! 3116 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 3117 pins = "gpio31";
5400 function = "g 3118 function = "gpio";
5401 }; 3119 };
5402 3120
5403 qup_spi0_data_clk: qu !! 3121 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 3122 pins = "gpio28", "gpio29",
5405 "gpio3 3123 "gpio30";
5406 function = "q 3124 function = "qup0";
5407 }; 3125 };
5408 3126
5409 qup_spi1_cs: qup-spi1 !! 3127 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 3128 pins = "gpio7";
5411 function = "q 3129 function = "qup1";
5412 }; 3130 };
5413 3131
5414 qup_spi1_cs_gpio: qup !! 3132 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 3133 pins = "gpio7";
5416 function = "g 3134 function = "gpio";
5417 }; 3135 };
5418 3136
5419 qup_spi1_data_clk: qu !! 3137 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 3138 pins = "gpio4", "gpio5",
5421 "gpio6 3139 "gpio6";
5422 function = "q 3140 function = "qup1";
5423 }; 3141 };
5424 3142
5425 qup_spi2_cs: qup-spi2 !! 3143 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 3144 pins = "gpio118";
5427 function = "q 3145 function = "qup2";
5428 }; 3146 };
5429 3147
5430 qup_spi2_cs_gpio: qup !! 3148 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 3149 pins = "gpio118";
5432 function = "g 3150 function = "gpio";
5433 }; 3151 };
5434 3152
5435 qup_spi2_data_clk: qu !! 3153 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 3154 pins = "gpio115", "gpio116",
5437 "gpio1 3155 "gpio117";
5438 function = "q 3156 function = "qup2";
5439 }; 3157 };
5440 3158
5441 qup_spi3_cs: qup-spi3 !! 3159 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 3160 pins = "gpio122";
5443 function = "q 3161 function = "qup3";
5444 }; 3162 };
5445 3163
5446 qup_spi3_cs_gpio: qup !! 3164 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 3165 pins = "gpio122";
5448 function = "g 3166 function = "gpio";
5449 }; 3167 };
5450 3168
5451 qup_spi3_data_clk: qu !! 3169 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 3170 pins = "gpio119", "gpio120",
5453 "gpio1 3171 "gpio121";
5454 function = "q 3172 function = "qup3";
5455 }; 3173 };
5456 3174
5457 qup_spi4_cs: qup-spi4 !! 3175 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 3176 pins = "gpio11";
5459 function = "q 3177 function = "qup4";
5460 }; 3178 };
5461 3179
5462 qup_spi4_cs_gpio: qup !! 3180 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 3181 pins = "gpio11";
5464 function = "g 3182 function = "gpio";
5465 }; 3183 };
5466 3184
5467 qup_spi4_data_clk: qu !! 3185 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 3186 pins = "gpio8", "gpio9",
5469 "gpio1 3187 "gpio10";
5470 function = "q 3188 function = "qup4";
5471 }; 3189 };
5472 3190
5473 qup_spi5_cs: qup-spi5 !! 3191 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 3192 pins = "gpio15";
5475 function = "q 3193 function = "qup5";
5476 }; 3194 };
5477 3195
5478 qup_spi5_cs_gpio: qup !! 3196 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 3197 pins = "gpio15";
5480 function = "g 3198 function = "gpio";
5481 }; 3199 };
5482 3200
5483 qup_spi5_data_clk: qu !! 3201 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 3202 pins = "gpio12", "gpio13",
5485 "gpio1 3203 "gpio14";
5486 function = "q 3204 function = "qup5";
5487 }; 3205 };
5488 3206
5489 qup_spi6_cs: qup-spi6 !! 3207 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 3208 pins = "gpio19";
5491 function = "q 3209 function = "qup6";
5492 }; 3210 };
5493 3211
5494 qup_spi6_cs_gpio: qup !! 3212 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 3213 pins = "gpio19";
5496 function = "g 3214 function = "gpio";
5497 }; 3215 };
5498 3216
5499 qup_spi6_data_clk: qu !! 3217 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 3218 pins = "gpio16", "gpio17",
5501 "gpio1 3219 "gpio18";
5502 function = "q 3220 function = "qup6";
5503 }; 3221 };
5504 3222
5505 qup_spi7_cs: qup-spi7 !! 3223 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 3224 pins = "gpio23";
5507 function = "q 3225 function = "qup7";
5508 }; 3226 };
5509 3227
5510 qup_spi7_cs_gpio: qup !! 3228 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 3229 pins = "gpio23";
5512 function = "g 3230 function = "gpio";
5513 }; 3231 };
5514 3232
5515 qup_spi7_data_clk: qu !! 3233 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 3234 pins = "gpio20", "gpio21",
5517 "gpio2 3235 "gpio22";
5518 function = "q 3236 function = "qup7";
5519 }; 3237 };
5520 3238
5521 qup_spi8_cs: qup-spi8 !! 3239 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 3240 pins = "gpio27";
5523 function = "q 3241 function = "qup8";
5524 }; 3242 };
5525 3243
5526 qup_spi8_cs_gpio: qup !! 3244 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 3245 pins = "gpio27";
5528 function = "g 3246 function = "gpio";
5529 }; 3247 };
5530 3248
5531 qup_spi8_data_clk: qu !! 3249 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 3250 pins = "gpio24", "gpio25",
5533 "gpio2 3251 "gpio26";
5534 function = "q 3252 function = "qup8";
5535 }; 3253 };
5536 3254
5537 qup_spi9_cs: qup-spi9 !! 3255 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 3256 pins = "gpio128";
5539 function = "q 3257 function = "qup9";
5540 }; 3258 };
5541 3259
5542 qup_spi9_cs_gpio: qup !! 3260 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 3261 pins = "gpio128";
5544 function = "g 3262 function = "gpio";
5545 }; 3263 };
5546 3264
5547 qup_spi9_data_clk: qu !! 3265 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 3266 pins = "gpio125", "gpio126",
5549 "gpio1 3267 "gpio127";
5550 function = "q 3268 function = "qup9";
5551 }; 3269 };
5552 3270
5553 qup_spi10_cs: qup-spi !! 3271 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 3272 pins = "gpio132";
5555 function = "q 3273 function = "qup10";
5556 }; 3274 };
5557 3275
5558 qup_spi10_cs_gpio: qu !! 3276 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 3277 pins = "gpio132";
5560 function = "g 3278 function = "gpio";
5561 }; 3279 };
5562 3280
5563 qup_spi10_data_clk: q !! 3281 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 3282 pins = "gpio129", "gpio130",
5565 "gpio1 3283 "gpio131";
5566 function = "q 3284 function = "qup10";
5567 }; 3285 };
5568 3286
5569 qup_spi11_cs: qup-spi !! 3287 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 3288 pins = "gpio63";
5571 function = "q 3289 function = "qup11";
5572 }; 3290 };
5573 3291
5574 qup_spi11_cs_gpio: qu !! 3292 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 3293 pins = "gpio63";
5576 function = "g 3294 function = "gpio";
5577 }; 3295 };
5578 3296
5579 qup_spi11_data_clk: q !! 3297 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 3298 pins = "gpio60", "gpio61",
5581 "gpio6 3299 "gpio62";
5582 function = "q 3300 function = "qup11";
5583 }; 3301 };
5584 3302
5585 qup_spi12_cs: qup-spi !! 3303 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 3304 pins = "gpio35";
5587 function = "q 3305 function = "qup12";
5588 }; 3306 };
5589 3307
5590 qup_spi12_cs_gpio: qu !! 3308 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 3309 pins = "gpio35";
5592 function = "g 3310 function = "gpio";
5593 }; 3311 };
5594 3312
5595 qup_spi12_data_clk: q !! 3313 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 3314 pins = "gpio32", "gpio33",
5597 "gpio3 3315 "gpio34";
5598 function = "q 3316 function = "qup12";
5599 }; 3317 };
5600 3318
5601 qup_spi13_cs: qup-spi !! 3319 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 3320 pins = "gpio39";
5603 function = "q 3321 function = "qup13";
5604 }; 3322 };
5605 3323
5606 qup_spi13_cs_gpio: qu !! 3324 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 3325 pins = "gpio39";
5608 function = "g 3326 function = "gpio";
5609 }; 3327 };
5610 3328
5611 qup_spi13_data_clk: q !! 3329 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 3330 pins = "gpio36", "gpio37",
5613 "gpio3 3331 "gpio38";
5614 function = "q 3332 function = "qup13";
5615 }; 3333 };
5616 3334
5617 qup_spi14_cs: qup-spi !! 3335 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 3336 pins = "gpio43";
5619 function = "q 3337 function = "qup14";
5620 }; 3338 };
5621 3339
5622 qup_spi14_cs_gpio: qu !! 3340 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 3341 pins = "gpio43";
5624 function = "g 3342 function = "gpio";
5625 }; 3343 };
5626 3344
5627 qup_spi14_data_clk: q !! 3345 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 3346 pins = "gpio40", "gpio41",
5629 "gpio4 3347 "gpio42";
5630 function = "q 3348 function = "qup14";
5631 }; 3349 };
5632 3350
5633 qup_spi15_cs: qup-spi !! 3351 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 3352 pins = "gpio47";
5635 function = "q 3353 function = "qup15";
5636 }; 3354 };
5637 3355
5638 qup_spi15_cs_gpio: qu !! 3356 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 3357 pins = "gpio47";
5640 function = "g 3358 function = "gpio";
5641 }; 3359 };
5642 3360
5643 qup_spi15_data_clk: q !! 3361 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 3362 pins = "gpio44", "gpio45",
5645 "gpio4 3363 "gpio46";
5646 function = "q 3364 function = "qup15";
5647 }; 3365 };
5648 3366
5649 qup_spi16_cs: qup-spi !! 3367 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 3368 pins = "gpio51";
5651 function = "q 3369 function = "qup16";
5652 }; 3370 };
5653 3371
5654 qup_spi16_cs_gpio: qu !! 3372 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 3373 pins = "gpio51";
5656 function = "g 3374 function = "gpio";
5657 }; 3375 };
5658 3376
5659 qup_spi16_data_clk: q !! 3377 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 3378 pins = "gpio48", "gpio49",
5661 "gpio5 3379 "gpio50";
5662 function = "q 3380 function = "qup16";
5663 }; 3381 };
5664 3382
5665 qup_spi17_cs: qup-spi !! 3383 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 3384 pins = "gpio55";
5667 function = "q 3385 function = "qup17";
5668 }; 3386 };
5669 3387
5670 qup_spi17_cs_gpio: qu !! 3388 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 3389 pins = "gpio55";
5672 function = "g 3390 function = "gpio";
5673 }; 3391 };
5674 3392
5675 qup_spi17_data_clk: q !! 3393 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 3394 pins = "gpio52", "gpio53",
5677 "gpio5 3395 "gpio54";
5678 function = "q 3396 function = "qup17";
5679 }; 3397 };
5680 3398
5681 qup_spi18_cs: qup-spi !! 3399 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 3400 pins = "gpio59";
5683 function = "q 3401 function = "qup18";
5684 }; 3402 };
5685 3403
5686 qup_spi18_cs_gpio: qu !! 3404 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 3405 pins = "gpio59";
5688 function = "g 3406 function = "gpio";
5689 }; 3407 };
5690 3408
5691 qup_spi18_data_clk: q !! 3409 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 3410 pins = "gpio56", "gpio57",
5693 "gpio5 3411 "gpio58";
5694 function = "q 3412 function = "qup18";
5695 }; 3413 };
5696 3414
5697 qup_spi19_cs: qup-spi !! 3415 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 3416 pins = "gpio3";
5699 function = "q 3417 function = "qup19";
5700 }; 3418 };
5701 3419
5702 qup_spi19_cs_gpio: qu !! 3420 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 3421 pins = "gpio3";
5704 function = "g 3422 function = "gpio";
5705 }; 3423 };
5706 3424
5707 qup_spi19_data_clk: q !! 3425 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 3426 pins = "gpio0", "gpio1",
5709 "gpio2 3427 "gpio2";
5710 function = "q 3428 function = "qup19";
5711 }; 3429 };
5712 3430
5713 qup_uart2_default: qu !! 3431 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 3432 mux {
5715 function = "q !! 3433 pins = "gpio117", "gpio118";
>> 3434 function = "qup2";
>> 3435 };
5716 }; 3436 };
5717 3437
5718 qup_uart6_default: qu !! 3438 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 3439 mux {
5720 function = "q !! 3440 pins = "gpio16", "gpio17",
>> 3441 "gpio18", "gpio19";
>> 3442 function = "qup6";
>> 3443 };
5721 }; 3444 };
5722 3445
5723 qup_uart12_default: q !! 3446 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 3447 mux {
5725 function = "q !! 3448 pins = "gpio34", "gpio35";
>> 3449 function = "qup12";
>> 3450 };
5726 }; 3451 };
5727 3452
5728 qup_uart17_default: q !! 3453 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 3454 mux {
5730 function = "q !! 3455 pins = "gpio52", "gpio53",
>> 3456 "gpio54", "gpio55";
>> 3457 function = "qup17";
>> 3458 };
5731 }; 3459 };
5732 3460
5733 qup_uart18_default: q !! 3461 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 3462 mux {
5735 function = "q !! 3463 pins = "gpio58", "gpio59";
>> 3464 function = "qup18";
>> 3465 };
5736 }; 3466 };
5737 3467
5738 tert_mi2s_active: ter !! 3468 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 3469 sck {
5740 pins 3470 pins = "gpio133";
5741 funct 3471 function = "mi2s2_sck";
5742 drive 3472 drive-strength = <8>;
5743 bias- 3473 bias-disable;
5744 }; 3474 };
5745 3475
5746 data0-pins { !! 3476 data0 {
5747 pins 3477 pins = "gpio134";
5748 funct 3478 function = "mi2s2_data0";
5749 drive 3479 drive-strength = <8>;
5750 bias- 3480 bias-disable;
5751 outpu 3481 output-high;
5752 }; 3482 };
5753 3483
5754 ws-pins { !! 3484 ws {
5755 pins 3485 pins = "gpio135";
5756 funct 3486 function = "mi2s2_ws";
5757 drive 3487 drive-strength = <8>;
5758 outpu 3488 output-high;
5759 }; 3489 };
5760 }; 3490 };
5761 3491
5762 sdc2_sleep_state: sdc !! 3492 sdc2_sleep_state: sdc2-sleep {
5763 clk-pins { !! 3493 clk {
5764 pins 3494 pins = "sdc2_clk";
5765 drive 3495 drive-strength = <2>;
5766 bias- 3496 bias-disable;
5767 }; 3497 };
5768 3498
5769 cmd-pins { !! 3499 cmd {
5770 pins 3500 pins = "sdc2_cmd";
5771 drive 3501 drive-strength = <2>;
5772 bias- 3502 bias-pull-up;
5773 }; 3503 };
5774 3504
5775 data-pins { !! 3505 data {
5776 pins 3506 pins = "sdc2_data";
5777 drive 3507 drive-strength = <2>;
5778 bias- 3508 bias-pull-up;
5779 }; 3509 };
5780 }; 3510 };
5781 3511
5782 pcie0_default_state: !! 3512 pcie0_default_state: pcie0-default {
5783 perst-pins { !! 3513 perst {
5784 pins 3514 pins = "gpio79";
5785 funct 3515 function = "gpio";
5786 drive 3516 drive-strength = <2>;
5787 bias- 3517 bias-pull-down;
5788 }; 3518 };
5789 3519
5790 clkreq-pins { !! 3520 clkreq {
5791 pins 3521 pins = "gpio80";
5792 funct 3522 function = "pci_e0";
5793 drive 3523 drive-strength = <2>;
5794 bias- 3524 bias-pull-up;
5795 }; 3525 };
5796 3526
5797 wake-pins { !! 3527 wake {
5798 pins 3528 pins = "gpio81";
5799 funct 3529 function = "gpio";
5800 drive 3530 drive-strength = <2>;
5801 bias- 3531 bias-pull-up;
5802 }; 3532 };
5803 }; 3533 };
5804 3534
5805 pcie1_default_state: !! 3535 pcie1_default_state: pcie1-default {
5806 perst-pins { !! 3536 perst {
5807 pins 3537 pins = "gpio82";
5808 funct 3538 function = "gpio";
5809 drive 3539 drive-strength = <2>;
5810 bias- 3540 bias-pull-down;
5811 }; 3541 };
5812 3542
5813 clkreq-pins { !! 3543 clkreq {
5814 pins 3544 pins = "gpio83";
5815 funct 3545 function = "pci_e1";
5816 drive 3546 drive-strength = <2>;
5817 bias- 3547 bias-pull-up;
5818 }; 3548 };
5819 3549
5820 wake-pins { !! 3550 wake {
5821 pins 3551 pins = "gpio84";
5822 funct 3552 function = "gpio";
5823 drive 3553 drive-strength = <2>;
5824 bias- 3554 bias-pull-up;
5825 }; 3555 };
5826 }; 3556 };
5827 3557
5828 pcie2_default_state: !! 3558 pcie2_default_state: pcie2-default {
5829 perst-pins { !! 3559 perst {
5830 pins 3560 pins = "gpio85";
5831 funct 3561 function = "gpio";
5832 drive 3562 drive-strength = <2>;
5833 bias- 3563 bias-pull-down;
5834 }; 3564 };
5835 3565
5836 clkreq-pins { !! 3566 clkreq {
5837 pins 3567 pins = "gpio86";
5838 funct 3568 function = "pci_e2";
5839 drive 3569 drive-strength = <2>;
5840 bias- 3570 bias-pull-up;
5841 }; 3571 };
5842 3572
5843 wake-pins { !! 3573 wake {
5844 pins 3574 pins = "gpio87";
5845 funct 3575 function = "gpio";
5846 drive 3576 drive-strength = <2>;
5847 bias- 3577 bias-pull-up;
5848 }; 3578 };
5849 }; 3579 };
5850 }; 3580 };
5851 3581
5852 apps_smmu: iommu@15000000 { 3582 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 3583 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 3584 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 3585 #iommu-cells = <2>;
5856 #global-interrupts = 3586 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 3587 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 3588 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 3589 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 3590 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 3591 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 3592 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 3593 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 3594 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 3595 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 3596 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 3597 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 3598 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 3599 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 3600 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 3601 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 3602 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 3603 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 3604 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 3605 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 3606 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 3607 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 3608 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 3609 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 3610 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 3611 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 3612 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 3613 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 3614 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 3615 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 3616 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 3617 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 3618 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 3619 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 3620 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 3621 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 3622 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 3623 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 3624 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 3625 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 3626 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 3627 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 3628 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 3629 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 3630 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 3631 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 3632 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 3633 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 3634 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 3635 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 3636 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 3637 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 3638 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 3639 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 3640 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 3641 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 3642 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 3643 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 3644 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 3645 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 3646 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 3647 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 3648 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 3649 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 3650 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 3651 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 3652 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 3653 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 3654 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 3655 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 3656 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 3657 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 3658 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 3659 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 3660 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 3661 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 3662 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 3663 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 3664 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 3665 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 3666 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 3667 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 3668 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 3669 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 3670 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 3671 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 3672 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 3673 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 3674 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 3675 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 3676 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 3677 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 3678 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 3679 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 3680 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 3681 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 3682 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 3683 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 3684 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 3685 };
5957 3686
5958 adsp: remoteproc@17300000 { 3687 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 3688 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 3689 reg = <0 0x17300000 0 0x100>;
5961 3690
5962 interrupts-extended = !! 3691 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 3692 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 3693 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 3694 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 3695 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 3696 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 3697 "handover", "stop-ack";
5969 3698
5970 clocks = <&rpmhcc RPM 3699 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 3700 clock-names = "xo";
5972 3701
5973 power-domains = <&rpm !! 3702 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
5974 <&rpm !! 3703 <&rpmhpd SM8250_LCX>,
5975 power-domain-names = !! 3704 <&rpmhpd SM8250_LMX>;
>> 3705 power-domain-names = "load_state", "lcx", "lmx";
5976 3706
5977 memory-region = <&ads 3707 memory-region = <&adsp_mem>;
5978 3708
5979 qcom,qmp = <&aoss_qmp <<
5980 <<
5981 qcom,smem-states = <& 3709 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 3710 qcom,smem-state-names = "stop";
5983 3711
5984 status = "disabled"; 3712 status = "disabled";
5985 3713
5986 glink-edge { 3714 glink-edge {
5987 interrupts-ex 3715 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 3716 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 3717 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 3718 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 3719 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 3720
5993 label = "lpas 3721 label = "lpass";
5994 qcom,remote-p 3722 qcom,remote-pid = <2>;
5995 3723
5996 apr { 3724 apr {
5997 compa 3725 compatible = "qcom,apr-v2";
5998 qcom, 3726 qcom,glink-channels = "apr_audio_svc";
5999 qcom, !! 3727 qcom,apr-domain = <APR_DOMAIN_ADSP>;
6000 #addr 3728 #address-cells = <1>;
6001 #size 3729 #size-cells = <0>;
6002 3730
6003 servi !! 3731 apr-service@3 {
6004 3732 reg = <APR_SVC_ADSP_CORE>;
6005 3733 compatible = "qcom,q6core";
6006 3734 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 3735 };
6008 3736
6009 q6afe !! 3737 q6afe: apr-service@4 {
6010 3738 compatible = "qcom,q6afe";
6011 3739 reg = <APR_SVC_AFE>;
6012 3740 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 3741 q6afedai: dais {
6014 3742 compatible = "qcom,q6afe-dais";
6015 3743 #address-cells = <1>;
6016 3744 #size-cells = <0>;
6017 3745 #sound-dai-cells = <1>;
6018 3746 };
6019 3747
6020 !! 3748 q6afecc: cc {
6021 3749 compatible = "qcom,q6afe-clocks";
6022 3750 #clock-cells = <2>;
6023 3751 };
6024 }; 3752 };
6025 3753
6026 q6asm !! 3754 q6asm: apr-service@7 {
6027 3755 compatible = "qcom,q6asm";
6028 3756 reg = <APR_SVC_ASM>;
6029 3757 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 3758 q6asmdai: dais {
6031 3759 compatible = "qcom,q6asm-dais";
6032 3760 #address-cells = <1>;
6033 3761 #size-cells = <0>;
6034 3762 #sound-dai-cells = <1>;
6035 3763 iommus = <&apps_smmu 0x1801 0x0>;
6036 3764 };
6037 }; 3765 };
6038 3766
6039 q6adm !! 3767 q6adm: apr-service@8 {
6040 3768 compatible = "qcom,q6adm";
6041 3769 reg = <APR_SVC_ADM>;
6042 3770 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 3771 q6routing: routing {
6044 3772 compatible = "qcom,q6adm-routing";
6045 3773 #sound-dai-cells = <0>;
6046 3774 };
6047 }; 3775 };
6048 }; 3776 };
6049 3777
6050 fastrpc { 3778 fastrpc {
6051 compa 3779 compatible = "qcom,fastrpc";
6052 qcom, 3780 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 3781 label = "adsp";
6054 qcom, <<
6055 #addr 3782 #address-cells = <1>;
6056 #size 3783 #size-cells = <0>;
6057 3784
6058 compu 3785 compute-cb@3 {
6059 3786 compatible = "qcom,fastrpc-compute-cb";
6060 3787 reg = <3>;
6061 3788 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 3789 };
6063 3790
6064 compu 3791 compute-cb@4 {
6065 3792 compatible = "qcom,fastrpc-compute-cb";
6066 3793 reg = <4>;
6067 3794 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 3795 };
6069 3796
6070 compu 3797 compute-cb@5 {
6071 3798 compatible = "qcom,fastrpc-compute-cb";
6072 3799 reg = <5>;
6073 3800 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 3801 };
6075 }; 3802 };
6076 }; 3803 };
6077 }; 3804 };
6078 3805
6079 intc: interrupt-controller@17 3806 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 3807 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 3808 #interrupt-cells = <3>;
6082 interrupt-controller; 3809 interrupt-controller;
6083 reg = <0x0 0x17a00000 3810 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 3811 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 3812 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 3813 };
6087 3814
6088 watchdog@17c10000 { 3815 watchdog@17c10000 {
6089 compatible = "qcom,ap 3816 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 3817 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 3818 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 3819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 3820 };
6094 3821
6095 timer@17c20000 { 3822 timer@17c20000 {
6096 #address-cells = <1>; !! 3823 #address-cells = <2>;
6097 #size-cells = <1>; !! 3824 #size-cells = <2>;
6098 ranges = <0 0 0 0x200 !! 3825 ranges;
6099 compatible = "arm,arm 3826 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 3827 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 3828 clock-frequency = <19200000>;
6102 3829
6103 frame@17c21000 { 3830 frame@17c21000 {
6104 frame-number 3831 frame-number = <0>;
6105 interrupts = 3832 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 3833 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 !! 3834 reg = <0x0 0x17c21000 0x0 0x1000>,
6108 <0x17c2 !! 3835 <0x0 0x17c22000 0x0 0x1000>;
6109 }; 3836 };
6110 3837
6111 frame@17c23000 { 3838 frame@17c23000 {
6112 frame-number 3839 frame-number = <1>;
6113 interrupts = 3840 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 !! 3841 reg = <0x0 0x17c23000 0x0 0x1000>;
6115 status = "dis 3842 status = "disabled";
6116 }; 3843 };
6117 3844
6118 frame@17c25000 { 3845 frame@17c25000 {
6119 frame-number 3846 frame-number = <2>;
6120 interrupts = 3847 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 !! 3848 reg = <0x0 0x17c25000 0x0 0x1000>;
6122 status = "dis 3849 status = "disabled";
6123 }; 3850 };
6124 3851
6125 frame@17c27000 { 3852 frame@17c27000 {
6126 frame-number 3853 frame-number = <3>;
6127 interrupts = 3854 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 !! 3855 reg = <0x0 0x17c27000 0x0 0x1000>;
6129 status = "dis 3856 status = "disabled";
6130 }; 3857 };
6131 3858
6132 frame@17c29000 { 3859 frame@17c29000 {
6133 frame-number 3860 frame-number = <4>;
6134 interrupts = 3861 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 !! 3862 reg = <0x0 0x17c29000 0x0 0x1000>;
6136 status = "dis 3863 status = "disabled";
6137 }; 3864 };
6138 3865
6139 frame@17c2b000 { 3866 frame@17c2b000 {
6140 frame-number 3867 frame-number = <5>;
6141 interrupts = 3868 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 !! 3869 reg = <0x0 0x17c2b000 0x0 0x1000>;
6143 status = "dis 3870 status = "disabled";
6144 }; 3871 };
6145 3872
6146 frame@17c2d000 { 3873 frame@17c2d000 {
6147 frame-number 3874 frame-number = <6>;
6148 interrupts = 3875 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 !! 3876 reg = <0x0 0x17c2d000 0x0 0x1000>;
6150 status = "dis 3877 status = "disabled";
6151 }; 3878 };
6152 }; 3879 };
6153 3880
6154 apps_rsc: rsc@18200000 { 3881 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 3882 label = "apps_rsc";
6156 compatible = "qcom,rp 3883 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 3884 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 3885 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 3886 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 3887 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 3888 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 3889 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 3890 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 3891 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 3892 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 3893 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 3894 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 3895
6170 rpmhcc: clock-control 3896 rpmhcc: clock-controller {
6171 compatible = 3897 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 3898 #clock-cells = <1>;
6173 clock-names = 3899 clock-names = "xo";
6174 clocks = <&xo 3900 clocks = <&xo_board>;
6175 }; 3901 };
6176 3902
6177 rpmhpd: power-control 3903 rpmhpd: power-controller {
6178 compatible = 3904 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 3905 #power-domain-cells = <1>;
6180 operating-poi 3906 operating-points-v2 = <&rpmhpd_opp_table>;
6181 3907
6182 rpmhpd_opp_ta 3908 rpmhpd_opp_table: opp-table {
6183 compa 3909 compatible = "operating-points-v2";
6184 3910
6185 rpmhp 3911 rpmhpd_opp_ret: opp1 {
6186 3912 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 3913 };
6188 3914
6189 rpmhp 3915 rpmhpd_opp_min_svs: opp2 {
6190 3916 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 3917 };
6192 3918
6193 rpmhp 3919 rpmhpd_opp_low_svs: opp3 {
6194 3920 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 3921 };
6196 3922
6197 rpmhp 3923 rpmhpd_opp_svs: opp4 {
6198 3924 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 3925 };
6200 3926
6201 rpmhp 3927 rpmhpd_opp_svs_l1: opp5 {
6202 3928 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 3929 };
6204 3930
6205 rpmhp 3931 rpmhpd_opp_nom: opp6 {
6206 3932 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 3933 };
6208 3934
6209 rpmhp 3935 rpmhpd_opp_nom_l1: opp7 {
6210 3936 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 3937 };
6212 3938
6213 rpmhp 3939 rpmhpd_opp_nom_l2: opp8 {
6214 3940 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 3941 };
6216 3942
6217 rpmhp 3943 rpmhpd_opp_turbo: opp9 {
6218 3944 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 3945 };
6220 3946
6221 rpmhp 3947 rpmhpd_opp_turbo_l1: opp10 {
6222 3948 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 3949 };
6224 }; 3950 };
6225 }; 3951 };
6226 3952
6227 apps_bcm_voter: bcm-v !! 3953 apps_bcm_voter: bcm_voter {
6228 compatible = 3954 compatible = "qcom,bcm-voter";
6229 }; 3955 };
6230 }; 3956 };
6231 3957
6232 epss_l3: interconnect@1859000 3958 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 3959 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 3960 reg = <0 0x18590000 0 0x1000>;
6235 3961
6236 clocks = <&rpmhcc RPM 3962 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 3963 clock-names = "xo", "alternate";
6238 3964
6239 #interconnect-cells = 3965 #interconnect-cells = <1>;
6240 }; 3966 };
6241 3967
6242 cpufreq_hw: cpufreq@18591000 3968 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 3969 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 3970 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 3971 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 3972 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 3973 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 3974 "freq-domain2";
6249 3975
6250 clocks = <&rpmhcc RPM 3976 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 3977 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI !! 3978
6253 <GIC_SPI <<
6254 <GIC_SPI <<
6255 interrupt-names = "dc <<
6256 #freq-domain-cells = 3979 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 3980 };
6259 }; 3981 };
6260 3982
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 3983 timer {
6265 compatible = "arm,armv8-timer 3984 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 3985 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 3986 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 3987 <GIC_PPI 14
6269 (GIC_CPU_MASK 3988 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 3989 <GIC_PPI 11
6271 (GIC_CPU_MASK 3990 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 3991 <GIC_PPI 10
6273 (GIC_CPU_MASK 3992 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 3993 };
6275 3994
6276 thermal-zones { 3995 thermal-zones {
6277 cpu0-thermal { 3996 cpu0-thermal {
6278 polling-delay-passive 3997 polling-delay-passive = <250>;
>> 3998 polling-delay = <1000>;
6279 3999
6280 thermal-sensors = <&t 4000 thermal-sensors = <&tsens0 1>;
6281 4001
6282 trips { 4002 trips {
6283 cpu0_alert0: 4003 cpu0_alert0: trip-point0 {
6284 tempe 4004 temperature = <90000>;
6285 hyste 4005 hysteresis = <2000>;
6286 type 4006 type = "passive";
6287 }; 4007 };
6288 4008
6289 cpu0_alert1: 4009 cpu0_alert1: trip-point1 {
6290 tempe 4010 temperature = <95000>;
6291 hyste 4011 hysteresis = <2000>;
6292 type 4012 type = "passive";
6293 }; 4013 };
6294 4014
6295 cpu0_crit: cp !! 4015 cpu0_crit: cpu_crit {
6296 tempe 4016 temperature = <110000>;
6297 hyste 4017 hysteresis = <1000>;
6298 type 4018 type = "critical";
6299 }; 4019 };
6300 }; 4020 };
6301 4021
6302 cooling-maps { 4022 cooling-maps {
6303 map0 { 4023 map0 {
6304 trip 4024 trip = <&cpu0_alert0>;
6305 cooli 4025 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 4026 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 4027 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 4028 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 4029 };
6310 map1 { 4030 map1 {
6311 trip 4031 trip = <&cpu0_alert1>;
6312 cooli 4032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 4033 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 4034 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 4035 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 4036 };
6317 }; 4037 };
6318 }; 4038 };
6319 4039
6320 cpu1-thermal { 4040 cpu1-thermal {
6321 polling-delay-passive 4041 polling-delay-passive = <250>;
>> 4042 polling-delay = <1000>;
6322 4043
6323 thermal-sensors = <&t 4044 thermal-sensors = <&tsens0 2>;
6324 4045
6325 trips { 4046 trips {
6326 cpu1_alert0: 4047 cpu1_alert0: trip-point0 {
6327 tempe 4048 temperature = <90000>;
6328 hyste 4049 hysteresis = <2000>;
6329 type 4050 type = "passive";
6330 }; 4051 };
6331 4052
6332 cpu1_alert1: 4053 cpu1_alert1: trip-point1 {
6333 tempe 4054 temperature = <95000>;
6334 hyste 4055 hysteresis = <2000>;
6335 type 4056 type = "passive";
6336 }; 4057 };
6337 4058
6338 cpu1_crit: cp !! 4059 cpu1_crit: cpu_crit {
6339 tempe 4060 temperature = <110000>;
6340 hyste 4061 hysteresis = <1000>;
6341 type 4062 type = "critical";
6342 }; 4063 };
6343 }; 4064 };
6344 4065
6345 cooling-maps { 4066 cooling-maps {
6346 map0 { 4067 map0 {
6347 trip 4068 trip = <&cpu1_alert0>;
6348 cooli 4069 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 4070 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 4071 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 4072 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 4073 };
6353 map1 { 4074 map1 {
6354 trip 4075 trip = <&cpu1_alert1>;
6355 cooli 4076 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 4077 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 4078 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 4079 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 4080 };
6360 }; 4081 };
6361 }; 4082 };
6362 4083
6363 cpu2-thermal { 4084 cpu2-thermal {
6364 polling-delay-passive 4085 polling-delay-passive = <250>;
>> 4086 polling-delay = <1000>;
6365 4087
6366 thermal-sensors = <&t 4088 thermal-sensors = <&tsens0 3>;
6367 4089
6368 trips { 4090 trips {
6369 cpu2_alert0: 4091 cpu2_alert0: trip-point0 {
6370 tempe 4092 temperature = <90000>;
6371 hyste 4093 hysteresis = <2000>;
6372 type 4094 type = "passive";
6373 }; 4095 };
6374 4096
6375 cpu2_alert1: 4097 cpu2_alert1: trip-point1 {
6376 tempe 4098 temperature = <95000>;
6377 hyste 4099 hysteresis = <2000>;
6378 type 4100 type = "passive";
6379 }; 4101 };
6380 4102
6381 cpu2_crit: cp !! 4103 cpu2_crit: cpu_crit {
6382 tempe 4104 temperature = <110000>;
6383 hyste 4105 hysteresis = <1000>;
6384 type 4106 type = "critical";
6385 }; 4107 };
6386 }; 4108 };
6387 4109
6388 cooling-maps { 4110 cooling-maps {
6389 map0 { 4111 map0 {
6390 trip 4112 trip = <&cpu2_alert0>;
6391 cooli 4113 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 4114 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 4115 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 4116 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 4117 };
6396 map1 { 4118 map1 {
6397 trip 4119 trip = <&cpu2_alert1>;
6398 cooli 4120 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 4121 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 4122 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 4123 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 4124 };
6403 }; 4125 };
6404 }; 4126 };
6405 4127
6406 cpu3-thermal { 4128 cpu3-thermal {
6407 polling-delay-passive 4129 polling-delay-passive = <250>;
>> 4130 polling-delay = <1000>;
6408 4131
6409 thermal-sensors = <&t 4132 thermal-sensors = <&tsens0 4>;
6410 4133
6411 trips { 4134 trips {
6412 cpu3_alert0: 4135 cpu3_alert0: trip-point0 {
6413 tempe 4136 temperature = <90000>;
6414 hyste 4137 hysteresis = <2000>;
6415 type 4138 type = "passive";
6416 }; 4139 };
6417 4140
6418 cpu3_alert1: 4141 cpu3_alert1: trip-point1 {
6419 tempe 4142 temperature = <95000>;
6420 hyste 4143 hysteresis = <2000>;
6421 type 4144 type = "passive";
6422 }; 4145 };
6423 4146
6424 cpu3_crit: cp !! 4147 cpu3_crit: cpu_crit {
6425 tempe 4148 temperature = <110000>;
6426 hyste 4149 hysteresis = <1000>;
6427 type 4150 type = "critical";
6428 }; 4151 };
6429 }; 4152 };
6430 4153
6431 cooling-maps { 4154 cooling-maps {
6432 map0 { 4155 map0 {
6433 trip 4156 trip = <&cpu3_alert0>;
6434 cooli 4157 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 4158 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 4159 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 4160 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 4161 };
6439 map1 { 4162 map1 {
6440 trip 4163 trip = <&cpu3_alert1>;
6441 cooli 4164 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 4165 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 4166 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 4167 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 4168 };
6446 }; 4169 };
6447 }; 4170 };
6448 4171
6449 cpu4-top-thermal { 4172 cpu4-top-thermal {
6450 polling-delay-passive 4173 polling-delay-passive = <250>;
>> 4174 polling-delay = <1000>;
6451 4175
6452 thermal-sensors = <&t 4176 thermal-sensors = <&tsens0 7>;
6453 4177
6454 trips { 4178 trips {
6455 cpu4_top_aler 4179 cpu4_top_alert0: trip-point0 {
6456 tempe 4180 temperature = <90000>;
6457 hyste 4181 hysteresis = <2000>;
6458 type 4182 type = "passive";
6459 }; 4183 };
6460 4184
6461 cpu4_top_aler 4185 cpu4_top_alert1: trip-point1 {
6462 tempe 4186 temperature = <95000>;
6463 hyste 4187 hysteresis = <2000>;
6464 type 4188 type = "passive";
6465 }; 4189 };
6466 4190
6467 cpu4_top_crit !! 4191 cpu4_top_crit: cpu_crit {
6468 tempe 4192 temperature = <110000>;
6469 hyste 4193 hysteresis = <1000>;
6470 type 4194 type = "critical";
6471 }; 4195 };
6472 }; 4196 };
6473 4197
6474 cooling-maps { 4198 cooling-maps {
6475 map0 { 4199 map0 {
6476 trip 4200 trip = <&cpu4_top_alert0>;
6477 cooli 4201 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 4202 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 4203 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 4204 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 4205 };
6482 map1 { 4206 map1 {
6483 trip 4207 trip = <&cpu4_top_alert1>;
6484 cooli 4208 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 4209 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 4210 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 4211 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 4212 };
6489 }; 4213 };
6490 }; 4214 };
6491 4215
6492 cpu5-top-thermal { 4216 cpu5-top-thermal {
6493 polling-delay-passive 4217 polling-delay-passive = <250>;
>> 4218 polling-delay = <1000>;
6494 4219
6495 thermal-sensors = <&t 4220 thermal-sensors = <&tsens0 8>;
6496 4221
6497 trips { 4222 trips {
6498 cpu5_top_aler 4223 cpu5_top_alert0: trip-point0 {
6499 tempe 4224 temperature = <90000>;
6500 hyste 4225 hysteresis = <2000>;
6501 type 4226 type = "passive";
6502 }; 4227 };
6503 4228
6504 cpu5_top_aler 4229 cpu5_top_alert1: trip-point1 {
6505 tempe 4230 temperature = <95000>;
6506 hyste 4231 hysteresis = <2000>;
6507 type 4232 type = "passive";
6508 }; 4233 };
6509 4234
6510 cpu5_top_crit !! 4235 cpu5_top_crit: cpu_crit {
6511 tempe 4236 temperature = <110000>;
6512 hyste 4237 hysteresis = <1000>;
6513 type 4238 type = "critical";
6514 }; 4239 };
6515 }; 4240 };
6516 4241
6517 cooling-maps { 4242 cooling-maps {
6518 map0 { 4243 map0 {
6519 trip 4244 trip = <&cpu5_top_alert0>;
6520 cooli 4245 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 4246 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 4247 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 4248 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4249 };
6525 map1 { 4250 map1 {
6526 trip 4251 trip = <&cpu5_top_alert1>;
6527 cooli 4252 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4253 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4254 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4255 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4256 };
6532 }; 4257 };
6533 }; 4258 };
6534 4259
6535 cpu6-top-thermal { 4260 cpu6-top-thermal {
6536 polling-delay-passive 4261 polling-delay-passive = <250>;
>> 4262 polling-delay = <1000>;
6537 4263
6538 thermal-sensors = <&t 4264 thermal-sensors = <&tsens0 9>;
6539 4265
6540 trips { 4266 trips {
6541 cpu6_top_aler 4267 cpu6_top_alert0: trip-point0 {
6542 tempe 4268 temperature = <90000>;
6543 hyste 4269 hysteresis = <2000>;
6544 type 4270 type = "passive";
6545 }; 4271 };
6546 4272
6547 cpu6_top_aler 4273 cpu6_top_alert1: trip-point1 {
6548 tempe 4274 temperature = <95000>;
6549 hyste 4275 hysteresis = <2000>;
6550 type 4276 type = "passive";
6551 }; 4277 };
6552 4278
6553 cpu6_top_crit !! 4279 cpu6_top_crit: cpu_crit {
6554 tempe 4280 temperature = <110000>;
6555 hyste 4281 hysteresis = <1000>;
6556 type 4282 type = "critical";
6557 }; 4283 };
6558 }; 4284 };
6559 4285
6560 cooling-maps { 4286 cooling-maps {
6561 map0 { 4287 map0 {
6562 trip 4288 trip = <&cpu6_top_alert0>;
6563 cooli 4289 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 4290 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 4291 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 4292 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 4293 };
6568 map1 { 4294 map1 {
6569 trip 4295 trip = <&cpu6_top_alert1>;
6570 cooli 4296 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 4297 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 4298 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 4299 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 4300 };
6575 }; 4301 };
6576 }; 4302 };
6577 4303
6578 cpu7-top-thermal { 4304 cpu7-top-thermal {
6579 polling-delay-passive 4305 polling-delay-passive = <250>;
>> 4306 polling-delay = <1000>;
6580 4307
6581 thermal-sensors = <&t 4308 thermal-sensors = <&tsens0 10>;
6582 4309
6583 trips { 4310 trips {
6584 cpu7_top_aler 4311 cpu7_top_alert0: trip-point0 {
6585 tempe 4312 temperature = <90000>;
6586 hyste 4313 hysteresis = <2000>;
6587 type 4314 type = "passive";
6588 }; 4315 };
6589 4316
6590 cpu7_top_aler 4317 cpu7_top_alert1: trip-point1 {
6591 tempe 4318 temperature = <95000>;
6592 hyste 4319 hysteresis = <2000>;
6593 type 4320 type = "passive";
6594 }; 4321 };
6595 4322
6596 cpu7_top_crit !! 4323 cpu7_top_crit: cpu_crit {
6597 tempe 4324 temperature = <110000>;
6598 hyste 4325 hysteresis = <1000>;
6599 type 4326 type = "critical";
6600 }; 4327 };
6601 }; 4328 };
6602 4329
6603 cooling-maps { 4330 cooling-maps {
6604 map0 { 4331 map0 {
6605 trip 4332 trip = <&cpu7_top_alert0>;
6606 cooli 4333 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 4334 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 4335 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 4336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 4337 };
6611 map1 { 4338 map1 {
6612 trip 4339 trip = <&cpu7_top_alert1>;
6613 cooli 4340 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 4341 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 4342 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 4343 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 4344 };
6618 }; 4345 };
6619 }; 4346 };
6620 4347
6621 cpu4-bottom-thermal { 4348 cpu4-bottom-thermal {
6622 polling-delay-passive 4349 polling-delay-passive = <250>;
>> 4350 polling-delay = <1000>;
6623 4351
6624 thermal-sensors = <&t 4352 thermal-sensors = <&tsens0 11>;
6625 4353
6626 trips { 4354 trips {
6627 cpu4_bottom_a 4355 cpu4_bottom_alert0: trip-point0 {
6628 tempe 4356 temperature = <90000>;
6629 hyste 4357 hysteresis = <2000>;
6630 type 4358 type = "passive";
6631 }; 4359 };
6632 4360
6633 cpu4_bottom_a 4361 cpu4_bottom_alert1: trip-point1 {
6634 tempe 4362 temperature = <95000>;
6635 hyste 4363 hysteresis = <2000>;
6636 type 4364 type = "passive";
6637 }; 4365 };
6638 4366
6639 cpu4_bottom_c !! 4367 cpu4_bottom_crit: cpu_crit {
6640 tempe 4368 temperature = <110000>;
6641 hyste 4369 hysteresis = <1000>;
6642 type 4370 type = "critical";
6643 }; 4371 };
6644 }; 4372 };
6645 4373
6646 cooling-maps { 4374 cooling-maps {
6647 map0 { 4375 map0 {
6648 trip 4376 trip = <&cpu4_bottom_alert0>;
6649 cooli 4377 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 4378 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 4379 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 4380 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 4381 };
6654 map1 { 4382 map1 {
6655 trip 4383 trip = <&cpu4_bottom_alert1>;
6656 cooli 4384 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 4385 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 4386 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 4387 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 4388 };
6661 }; 4389 };
6662 }; 4390 };
6663 4391
6664 cpu5-bottom-thermal { 4392 cpu5-bottom-thermal {
6665 polling-delay-passive 4393 polling-delay-passive = <250>;
>> 4394 polling-delay = <1000>;
6666 4395
6667 thermal-sensors = <&t 4396 thermal-sensors = <&tsens0 12>;
6668 4397
6669 trips { 4398 trips {
6670 cpu5_bottom_a 4399 cpu5_bottom_alert0: trip-point0 {
6671 tempe 4400 temperature = <90000>;
6672 hyste 4401 hysteresis = <2000>;
6673 type 4402 type = "passive";
6674 }; 4403 };
6675 4404
6676 cpu5_bottom_a 4405 cpu5_bottom_alert1: trip-point1 {
6677 tempe 4406 temperature = <95000>;
6678 hyste 4407 hysteresis = <2000>;
6679 type 4408 type = "passive";
6680 }; 4409 };
6681 4410
6682 cpu5_bottom_c !! 4411 cpu5_bottom_crit: cpu_crit {
6683 tempe 4412 temperature = <110000>;
6684 hyste 4413 hysteresis = <1000>;
6685 type 4414 type = "critical";
6686 }; 4415 };
6687 }; 4416 };
6688 4417
6689 cooling-maps { 4418 cooling-maps {
6690 map0 { 4419 map0 {
6691 trip 4420 trip = <&cpu5_bottom_alert0>;
6692 cooli 4421 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 4422 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 4423 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 4424 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 4425 };
6697 map1 { 4426 map1 {
6698 trip 4427 trip = <&cpu5_bottom_alert1>;
6699 cooli 4428 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 4429 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 4430 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 4431 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 4432 };
6704 }; 4433 };
6705 }; 4434 };
6706 4435
6707 cpu6-bottom-thermal { 4436 cpu6-bottom-thermal {
6708 polling-delay-passive 4437 polling-delay-passive = <250>;
>> 4438 polling-delay = <1000>;
6709 4439
6710 thermal-sensors = <&t 4440 thermal-sensors = <&tsens0 13>;
6711 4441
6712 trips { 4442 trips {
6713 cpu6_bottom_a 4443 cpu6_bottom_alert0: trip-point0 {
6714 tempe 4444 temperature = <90000>;
6715 hyste 4445 hysteresis = <2000>;
6716 type 4446 type = "passive";
6717 }; 4447 };
6718 4448
6719 cpu6_bottom_a 4449 cpu6_bottom_alert1: trip-point1 {
6720 tempe 4450 temperature = <95000>;
6721 hyste 4451 hysteresis = <2000>;
6722 type 4452 type = "passive";
6723 }; 4453 };
6724 4454
6725 cpu6_bottom_c !! 4455 cpu6_bottom_crit: cpu_crit {
6726 tempe 4456 temperature = <110000>;
6727 hyste 4457 hysteresis = <1000>;
6728 type 4458 type = "critical";
6729 }; 4459 };
6730 }; 4460 };
6731 4461
6732 cooling-maps { 4462 cooling-maps {
6733 map0 { 4463 map0 {
6734 trip 4464 trip = <&cpu6_bottom_alert0>;
6735 cooli 4465 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 4466 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 4467 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 4468 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 4469 };
6740 map1 { 4470 map1 {
6741 trip 4471 trip = <&cpu6_bottom_alert1>;
6742 cooli 4472 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 4473 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 4474 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 4475 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 4476 };
6747 }; 4477 };
6748 }; 4478 };
6749 4479
6750 cpu7-bottom-thermal { 4480 cpu7-bottom-thermal {
6751 polling-delay-passive 4481 polling-delay-passive = <250>;
>> 4482 polling-delay = <1000>;
6752 4483
6753 thermal-sensors = <&t 4484 thermal-sensors = <&tsens0 14>;
6754 4485
6755 trips { 4486 trips {
6756 cpu7_bottom_a 4487 cpu7_bottom_alert0: trip-point0 {
6757 tempe 4488 temperature = <90000>;
6758 hyste 4489 hysteresis = <2000>;
6759 type 4490 type = "passive";
6760 }; 4491 };
6761 4492
6762 cpu7_bottom_a 4493 cpu7_bottom_alert1: trip-point1 {
6763 tempe 4494 temperature = <95000>;
6764 hyste 4495 hysteresis = <2000>;
6765 type 4496 type = "passive";
6766 }; 4497 };
6767 4498
6768 cpu7_bottom_c !! 4499 cpu7_bottom_crit: cpu_crit {
6769 tempe 4500 temperature = <110000>;
6770 hyste 4501 hysteresis = <1000>;
6771 type 4502 type = "critical";
6772 }; 4503 };
6773 }; 4504 };
6774 4505
6775 cooling-maps { 4506 cooling-maps {
6776 map0 { 4507 map0 {
6777 trip 4508 trip = <&cpu7_bottom_alert0>;
6778 cooli 4509 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 4510 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 4511 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 4512 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 4513 };
6783 map1 { 4514 map1 {
6784 trip 4515 trip = <&cpu7_bottom_alert1>;
6785 cooli 4516 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 4517 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 4518 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 4519 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 4520 };
6790 }; 4521 };
6791 }; 4522 };
6792 4523
6793 aoss0-thermal { 4524 aoss0-thermal {
6794 polling-delay-passive 4525 polling-delay-passive = <250>;
>> 4526 polling-delay = <1000>;
6795 4527
6796 thermal-sensors = <&t 4528 thermal-sensors = <&tsens0 0>;
6797 4529
6798 trips { 4530 trips {
6799 aoss0_alert0: 4531 aoss0_alert0: trip-point0 {
6800 tempe 4532 temperature = <90000>;
6801 hyste 4533 hysteresis = <2000>;
6802 type 4534 type = "hot";
6803 }; 4535 };
6804 }; 4536 };
6805 }; 4537 };
6806 4538
6807 cluster0-thermal { 4539 cluster0-thermal {
6808 polling-delay-passive 4540 polling-delay-passive = <250>;
>> 4541 polling-delay = <1000>;
6809 4542
6810 thermal-sensors = <&t 4543 thermal-sensors = <&tsens0 5>;
6811 4544
6812 trips { 4545 trips {
6813 cluster0_aler 4546 cluster0_alert0: trip-point0 {
6814 tempe 4547 temperature = <90000>;
6815 hyste 4548 hysteresis = <2000>;
6816 type 4549 type = "hot";
6817 }; 4550 };
6818 cluster0_crit !! 4551 cluster0_crit: cluster0_crit {
6819 tempe 4552 temperature = <110000>;
6820 hyste 4553 hysteresis = <2000>;
6821 type 4554 type = "critical";
6822 }; 4555 };
6823 }; 4556 };
6824 }; 4557 };
6825 4558
6826 cluster1-thermal { 4559 cluster1-thermal {
6827 polling-delay-passive 4560 polling-delay-passive = <250>;
>> 4561 polling-delay = <1000>;
6828 4562
6829 thermal-sensors = <&t 4563 thermal-sensors = <&tsens0 6>;
6830 4564
6831 trips { 4565 trips {
6832 cluster1_aler 4566 cluster1_alert0: trip-point0 {
6833 tempe 4567 temperature = <90000>;
6834 hyste 4568 hysteresis = <2000>;
6835 type 4569 type = "hot";
6836 }; 4570 };
6837 cluster1_crit !! 4571 cluster1_crit: cluster1_crit {
6838 tempe 4572 temperature = <110000>;
6839 hyste 4573 hysteresis = <2000>;
6840 type 4574 type = "critical";
6841 }; 4575 };
6842 }; 4576 };
6843 }; 4577 };
6844 4578
6845 gpu-top-thermal { !! 4579 gpu-thermal-top {
6846 polling-delay-passive 4580 polling-delay-passive = <250>;
>> 4581 polling-delay = <1000>;
6847 4582
6848 thermal-sensors = <&t 4583 thermal-sensors = <&tsens0 15>;
6849 4584
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 4585 trips {
6858 gpu_top_alert !! 4586 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 4587 temperature = <90000>;
6866 hyste !! 4588 hysteresis = <2000>;
6867 type 4589 type = "hot";
6868 }; 4590 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 4591 };
6876 }; 4592 };
6877 4593
6878 aoss1-thermal { 4594 aoss1-thermal {
6879 polling-delay-passive 4595 polling-delay-passive = <250>;
>> 4596 polling-delay = <1000>;
6880 4597
6881 thermal-sensors = <&t 4598 thermal-sensors = <&tsens1 0>;
6882 4599
6883 trips { 4600 trips {
6884 aoss1_alert0: 4601 aoss1_alert0: trip-point0 {
6885 tempe 4602 temperature = <90000>;
6886 hyste 4603 hysteresis = <2000>;
6887 type 4604 type = "hot";
6888 }; 4605 };
6889 }; 4606 };
6890 }; 4607 };
6891 4608
6892 wlan-thermal { 4609 wlan-thermal {
6893 polling-delay-passive 4610 polling-delay-passive = <250>;
>> 4611 polling-delay = <1000>;
6894 4612
6895 thermal-sensors = <&t 4613 thermal-sensors = <&tsens1 1>;
6896 4614
6897 trips { 4615 trips {
6898 wlan_alert0: 4616 wlan_alert0: trip-point0 {
6899 tempe 4617 temperature = <90000>;
6900 hyste 4618 hysteresis = <2000>;
6901 type 4619 type = "hot";
6902 }; 4620 };
6903 }; 4621 };
6904 }; 4622 };
6905 4623
6906 video-thermal { 4624 video-thermal {
6907 polling-delay-passive 4625 polling-delay-passive = <250>;
>> 4626 polling-delay = <1000>;
6908 4627
6909 thermal-sensors = <&t 4628 thermal-sensors = <&tsens1 2>;
6910 4629
6911 trips { 4630 trips {
6912 video_alert0: 4631 video_alert0: trip-point0 {
6913 tempe 4632 temperature = <90000>;
6914 hyste 4633 hysteresis = <2000>;
6915 type 4634 type = "hot";
6916 }; 4635 };
6917 }; 4636 };
6918 }; 4637 };
6919 4638
6920 mem-thermal { 4639 mem-thermal {
6921 polling-delay-passive 4640 polling-delay-passive = <250>;
>> 4641 polling-delay = <1000>;
6922 4642
6923 thermal-sensors = <&t 4643 thermal-sensors = <&tsens1 3>;
6924 4644
6925 trips { 4645 trips {
6926 mem_alert0: t 4646 mem_alert0: trip-point0 {
6927 tempe 4647 temperature = <90000>;
6928 hyste 4648 hysteresis = <2000>;
6929 type 4649 type = "hot";
6930 }; 4650 };
6931 }; 4651 };
6932 }; 4652 };
6933 4653
6934 q6-hvx-thermal { 4654 q6-hvx-thermal {
6935 polling-delay-passive 4655 polling-delay-passive = <250>;
>> 4656 polling-delay = <1000>;
6936 4657
6937 thermal-sensors = <&t 4658 thermal-sensors = <&tsens1 4>;
6938 4659
6939 trips { 4660 trips {
6940 q6_hvx_alert0 4661 q6_hvx_alert0: trip-point0 {
6941 tempe 4662 temperature = <90000>;
6942 hyste 4663 hysteresis = <2000>;
6943 type 4664 type = "hot";
6944 }; 4665 };
6945 }; 4666 };
6946 }; 4667 };
6947 4668
6948 camera-thermal { 4669 camera-thermal {
6949 polling-delay-passive 4670 polling-delay-passive = <250>;
>> 4671 polling-delay = <1000>;
6950 4672
6951 thermal-sensors = <&t 4673 thermal-sensors = <&tsens1 5>;
6952 4674
6953 trips { 4675 trips {
6954 camera_alert0 4676 camera_alert0: trip-point0 {
6955 tempe 4677 temperature = <90000>;
6956 hyste 4678 hysteresis = <2000>;
6957 type 4679 type = "hot";
6958 }; 4680 };
6959 }; 4681 };
6960 }; 4682 };
6961 4683
6962 compute-thermal { 4684 compute-thermal {
6963 polling-delay-passive 4685 polling-delay-passive = <250>;
>> 4686 polling-delay = <1000>;
6964 4687
6965 thermal-sensors = <&t 4688 thermal-sensors = <&tsens1 6>;
6966 4689
6967 trips { 4690 trips {
6968 compute_alert 4691 compute_alert0: trip-point0 {
6969 tempe 4692 temperature = <90000>;
6970 hyste 4693 hysteresis = <2000>;
6971 type 4694 type = "hot";
6972 }; 4695 };
6973 }; 4696 };
6974 }; 4697 };
6975 4698
6976 npu-thermal { 4699 npu-thermal {
6977 polling-delay-passive 4700 polling-delay-passive = <250>;
>> 4701 polling-delay = <1000>;
6978 4702
6979 thermal-sensors = <&t 4703 thermal-sensors = <&tsens1 7>;
6980 4704
6981 trips { 4705 trips {
6982 npu_alert0: t 4706 npu_alert0: trip-point0 {
6983 tempe 4707 temperature = <90000>;
6984 hyste 4708 hysteresis = <2000>;
6985 type 4709 type = "hot";
6986 }; 4710 };
6987 }; 4711 };
6988 }; 4712 };
6989 4713
6990 gpu-bottom-thermal { !! 4714 gpu-thermal-bottom {
6991 polling-delay-passive 4715 polling-delay-passive = <250>;
>> 4716 polling-delay = <1000>;
6992 4717
6993 thermal-sensors = <&t 4718 thermal-sensors = <&tsens1 8>;
6994 4719
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 4720 trips {
7003 gpu_bottom_al !! 4721 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 4722 temperature = <90000>;
7011 hyste !! 4723 hysteresis = <2000>;
7012 type 4724 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 4725 };
7020 }; 4726 };
7021 }; 4727 };
7022 }; 4728 };
7023 }; 4729 };
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