1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> !! 16 #include <dt-bindings/power/qcom-aoss-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h> 17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 18 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 20 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 21 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 23
26 / { 24 / {
27 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
28 26
29 #address-cells = <2>; 27 #address-cells = <2>;
30 #size-cells = <2>; 28 #size-cells = <2>;
31 29
32 aliases { 30 aliases {
33 i2c0 = &i2c0; 31 i2c0 = &i2c0;
34 i2c1 = &i2c1; 32 i2c1 = &i2c1;
35 i2c2 = &i2c2; 33 i2c2 = &i2c2;
36 i2c3 = &i2c3; 34 i2c3 = &i2c3;
37 i2c4 = &i2c4; 35 i2c4 = &i2c4;
38 i2c5 = &i2c5; 36 i2c5 = &i2c5;
39 i2c6 = &i2c6; 37 i2c6 = &i2c6;
40 i2c7 = &i2c7; 38 i2c7 = &i2c7;
41 i2c8 = &i2c8; 39 i2c8 = &i2c8;
42 i2c9 = &i2c9; 40 i2c9 = &i2c9;
43 i2c10 = &i2c10; 41 i2c10 = &i2c10;
44 i2c11 = &i2c11; 42 i2c11 = &i2c11;
45 i2c12 = &i2c12; 43 i2c12 = &i2c12;
46 i2c13 = &i2c13; 44 i2c13 = &i2c13;
47 i2c14 = &i2c14; 45 i2c14 = &i2c14;
48 i2c15 = &i2c15; 46 i2c15 = &i2c15;
49 i2c16 = &i2c16; 47 i2c16 = &i2c16;
50 i2c17 = &i2c17; 48 i2c17 = &i2c17;
51 i2c18 = &i2c18; 49 i2c18 = &i2c18;
52 i2c19 = &i2c19; 50 i2c19 = &i2c19;
53 spi0 = &spi0; 51 spi0 = &spi0;
54 spi1 = &spi1; 52 spi1 = &spi1;
55 spi2 = &spi2; 53 spi2 = &spi2;
56 spi3 = &spi3; 54 spi3 = &spi3;
57 spi4 = &spi4; 55 spi4 = &spi4;
58 spi5 = &spi5; 56 spi5 = &spi5;
59 spi6 = &spi6; 57 spi6 = &spi6;
60 spi7 = &spi7; 58 spi7 = &spi7;
61 spi8 = &spi8; 59 spi8 = &spi8;
62 spi9 = &spi9; 60 spi9 = &spi9;
63 spi10 = &spi10; 61 spi10 = &spi10;
64 spi11 = &spi11; 62 spi11 = &spi11;
65 spi12 = &spi12; 63 spi12 = &spi12;
66 spi13 = &spi13; 64 spi13 = &spi13;
67 spi14 = &spi14; 65 spi14 = &spi14;
68 spi15 = &spi15; 66 spi15 = &spi15;
69 spi16 = &spi16; 67 spi16 = &spi16;
70 spi17 = &spi17; 68 spi17 = &spi17;
71 spi18 = &spi18; 69 spi18 = &spi18;
72 spi19 = &spi19; 70 spi19 = &spi19;
73 }; 71 };
74 72
75 chosen { }; 73 chosen { };
76 74
77 clocks { 75 clocks {
78 xo_board: xo-board { 76 xo_board: xo-board {
79 compatible = "fixed-cl 77 compatible = "fixed-clock";
80 #clock-cells = <0>; 78 #clock-cells = <0>;
81 clock-frequency = <384 79 clock-frequency = <38400000>;
82 clock-output-names = " 80 clock-output-names = "xo_board";
83 }; 81 };
84 82
85 sleep_clk: sleep-clk { 83 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 84 compatible = "fixed-clock";
87 clock-frequency = <327 85 clock-frequency = <32768>;
88 #clock-cells = <0>; 86 #clock-cells = <0>;
89 }; 87 };
90 }; 88 };
91 89
92 cpus { 90 cpus {
93 #address-cells = <2>; 91 #address-cells = <2>;
94 #size-cells = <0>; 92 #size-cells = <0>;
95 93
96 CPU0: cpu@0 { 94 CPU0: cpu@0 {
97 device_type = "cpu"; 95 device_type = "cpu";
98 compatible = "qcom,kry 96 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 97 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 98 enable-method = "psci";
102 capacity-dmips-mhz = < 99 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici 100 dynamic-power-coefficient = <105>;
104 next-level-cache = <&L 101 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ <<
106 power-domain-names = " <<
107 qcom,freq-domain = <&c 102 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <<
109 interconnects = <&gem_ <<
110 <&epss <<
111 #cooling-cells = <2>; 103 #cooling-cells = <2>;
112 L2_0: l2-cache { 104 L2_0: l2-cache {
113 compatible = " 105 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 106 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 107 L3_0: l3-cache {
119 compat 108 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 109 };
124 }; 110 };
125 }; 111 };
126 112
127 CPU1: cpu@100 { 113 CPU1: cpu@100 {
128 device_type = "cpu"; 114 device_type = "cpu";
129 compatible = "qcom,kry 115 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 116 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 117 enable-method = "psci";
133 capacity-dmips-mhz = < 118 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici 119 dynamic-power-coefficient = <105>;
135 next-level-cache = <&L 120 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ <<
137 power-domain-names = " <<
138 qcom,freq-domain = <&c 121 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <<
140 interconnects = <&gem_ <<
141 <&epss <<
142 #cooling-cells = <2>; 122 #cooling-cells = <2>;
143 L2_100: l2-cache { 123 L2_100: l2-cache {
144 compatible = " 124 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 125 next-level-cache = <&L3_0>;
149 }; 126 };
150 }; 127 };
151 128
152 CPU2: cpu@200 { 129 CPU2: cpu@200 {
153 device_type = "cpu"; 130 device_type = "cpu";
154 compatible = "qcom,kry 131 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 132 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 133 enable-method = "psci";
158 capacity-dmips-mhz = < 134 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici 135 dynamic-power-coefficient = <105>;
160 next-level-cache = <&L 136 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ <<
162 power-domain-names = " <<
163 qcom,freq-domain = <&c 137 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <<
165 interconnects = <&gem_ <<
166 <&epss <<
167 #cooling-cells = <2>; 138 #cooling-cells = <2>;
168 L2_200: l2-cache { 139 L2_200: l2-cache {
169 compatible = " 140 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 141 next-level-cache = <&L3_0>;
174 }; 142 };
175 }; 143 };
176 144
177 CPU3: cpu@300 { 145 CPU3: cpu@300 {
178 device_type = "cpu"; 146 device_type = "cpu";
179 compatible = "qcom,kry 147 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 148 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 149 enable-method = "psci";
183 capacity-dmips-mhz = < 150 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici 151 dynamic-power-coefficient = <105>;
185 next-level-cache = <&L 152 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ <<
187 power-domain-names = " <<
188 qcom,freq-domain = <&c 153 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <<
190 interconnects = <&gem_ <<
191 <&epss <<
192 #cooling-cells = <2>; 154 #cooling-cells = <2>;
193 L2_300: l2-cache { 155 L2_300: l2-cache {
194 compatible = " 156 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 157 next-level-cache = <&L3_0>;
199 }; 158 };
200 }; 159 };
201 160
202 CPU4: cpu@400 { 161 CPU4: cpu@400 {
203 device_type = "cpu"; 162 device_type = "cpu";
204 compatible = "qcom,kry 163 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 164 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 165 enable-method = "psci";
208 capacity-dmips-mhz = < 166 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 167 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 168 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ <<
212 power-domain-names = " <<
213 qcom,freq-domain = <&c 169 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <<
215 interconnects = <&gem_ <<
216 <&epss <<
217 #cooling-cells = <2>; 170 #cooling-cells = <2>;
218 L2_400: l2-cache { 171 L2_400: l2-cache {
219 compatible = " 172 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 173 next-level-cache = <&L3_0>;
224 }; 174 };
225 }; 175 };
226 176
227 CPU5: cpu@500 { 177 CPU5: cpu@500 {
228 device_type = "cpu"; 178 device_type = "cpu";
229 compatible = "qcom,kry 179 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 180 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 181 enable-method = "psci";
233 capacity-dmips-mhz = < 182 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 183 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 184 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ <<
237 power-domain-names = " <<
238 qcom,freq-domain = <&c 185 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <<
240 interconnects = <&gem_ <<
241 <&epss <<
242 #cooling-cells = <2>; 186 #cooling-cells = <2>;
243 L2_500: l2-cache { 187 L2_500: l2-cache {
244 compatible = " 188 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 189 next-level-cache = <&L3_0>;
249 }; 190 };
>> 191
250 }; 192 };
251 193
252 CPU6: cpu@600 { 194 CPU6: cpu@600 {
253 device_type = "cpu"; 195 device_type = "cpu";
254 compatible = "qcom,kry 196 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 197 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 198 enable-method = "psci";
258 capacity-dmips-mhz = < 199 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 200 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 201 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ <<
262 power-domain-names = " <<
263 qcom,freq-domain = <&c 202 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <<
265 interconnects = <&gem_ <<
266 <&epss <<
267 #cooling-cells = <2>; 203 #cooling-cells = <2>;
268 L2_600: l2-cache { 204 L2_600: l2-cache {
269 compatible = " 205 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 206 next-level-cache = <&L3_0>;
274 }; 207 };
275 }; 208 };
276 209
277 CPU7: cpu@700 { 210 CPU7: cpu@700 {
278 device_type = "cpu"; 211 device_type = "cpu";
279 compatible = "qcom,kry 212 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 213 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 214 enable-method = "psci";
283 capacity-dmips-mhz = < 215 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 216 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 217 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ <<
287 power-domain-names = " <<
288 qcom,freq-domain = <&c 218 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <<
290 interconnects = <&gem_ <<
291 <&epss <<
292 #cooling-cells = <2>; 219 #cooling-cells = <2>;
293 L2_700: l2-cache { 220 L2_700: l2-cache {
294 compatible = " 221 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 222 next-level-cache = <&L3_0>;
299 }; 223 };
300 }; 224 };
301 225
302 cpu-map { 226 cpu-map {
303 cluster0 { 227 cluster0 {
304 core0 { 228 core0 {
305 cpu = 229 cpu = <&CPU0>;
306 }; 230 };
307 231
308 core1 { 232 core1 {
309 cpu = 233 cpu = <&CPU1>;
310 }; 234 };
311 235
312 core2 { 236 core2 {
313 cpu = 237 cpu = <&CPU2>;
314 }; 238 };
315 239
316 core3 { 240 core3 {
317 cpu = 241 cpu = <&CPU3>;
318 }; 242 };
319 243
320 core4 { 244 core4 {
321 cpu = 245 cpu = <&CPU4>;
322 }; 246 };
323 247
324 core5 { 248 core5 {
325 cpu = 249 cpu = <&CPU5>;
326 }; 250 };
327 251
328 core6 { 252 core6 {
329 cpu = 253 cpu = <&CPU6>;
330 }; 254 };
331 255
332 core7 { 256 core7 {
333 cpu = 257 cpu = <&CPU7>;
334 }; 258 };
335 }; 259 };
336 }; 260 };
337 <<
338 idle-states { <<
339 entry-method = "psci"; <<
340 <<
341 LITTLE_CPU_SLEEP_0: cp <<
342 compatible = " <<
343 idle-state-nam <<
344 arm,psci-suspe <<
345 entry-latency- <<
346 exit-latency-u <<
347 min-residency- <<
348 local-timer-st <<
349 }; <<
350 <<
351 BIG_CPU_SLEEP_0: cpu-s <<
352 compatible = " <<
353 idle-state-nam <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 local-timer-st <<
359 }; <<
360 }; <<
361 <<
362 domain-idle-states { <<
363 CLUSTER_SLEEP_0: clust <<
364 compatible = " <<
365 arm,psci-suspe <<
366 entry-latency- <<
367 exit-latency-u <<
368 min-residency- <<
369 }; <<
370 }; <<
371 }; <<
372 <<
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points <<
381 opp-shared; <<
382 <<
383 cpu0_opp1: opp-300000000 { <<
384 opp-hz = /bits/ 64 <30 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp2: opp-403200000 { <<
389 opp-hz = /bits/ 64 <40 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp3: opp-518400000 { <<
394 opp-hz = /bits/ 64 <51 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp4: opp-614400000 { <<
399 opp-hz = /bits/ 64 <61 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp5: opp-691200000 { <<
404 opp-hz = /bits/ 64 <69 <<
405 opp-peak-kBps = <80000 <<
406 }; <<
407 <<
408 cpu0_opp6: opp-787200000 { <<
409 opp-hz = /bits/ 64 <78 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp7: opp-883200000 { <<
414 opp-hz = /bits/ 64 <88 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp8: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp9: opp-1075200000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp10: opp-1171200000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <18040 <<
431 }; <<
432 <<
433 cpu0_opp11: opp-1248000000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <18040 <<
436 }; <<
437 <<
438 cpu0_opp12: opp-1344000000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp13: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <21880 <<
446 }; <<
447 <<
448 cpu0_opp14: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp15: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <30720 <<
456 }; <<
457 <<
458 cpu0_opp16: opp-1708800000 { <<
459 opp-hz = /bits/ 64 <17 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp17: opp-1804800000 { <<
464 opp-hz = /bits/ 64 <18 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-710400000 { <<
474 opp-hz = /bits/ 64 <71 <<
475 opp-peak-kBps = <18040 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-825600000 { <<
479 opp-hz = /bits/ 64 <82 <<
480 opp-peak-kBps = <21880 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-940800000 { <<
484 opp-hz = /bits/ 64 <94 <<
485 opp-peak-kBps = <21880 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-1056000000 { <<
489 opp-hz = /bits/ 64 <10 <<
490 opp-peak-kBps = <30720 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-1171200000 { <<
494 opp-hz = /bits/ 64 <11 <<
495 opp-peak-kBps = <30720 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-1286400000 { <<
499 opp-hz = /bits/ 64 <12 <<
500 opp-peak-kBps = <40680 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-1382400000 { <<
504 opp-hz = /bits/ 64 <13 <<
505 opp-peak-kBps = <40680 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-1478400000 { <<
509 opp-hz = /bits/ 64 <14 <<
510 opp-peak-kBps = <40680 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-1574400000 { <<
514 opp-hz = /bits/ 64 <15 <<
515 opp-peak-kBps = <54120 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1670400000 { <<
519 opp-hz = /bits/ 64 <16 <<
520 opp-peak-kBps = <54120 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1766400000 { <<
524 opp-hz = /bits/ 64 <17 <<
525 opp-peak-kBps = <54120 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1862400000 { <<
529 opp-hz = /bits/ 64 <18 <<
530 opp-peak-kBps = <62200 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1958400000 { <<
534 opp-hz = /bits/ 64 <19 <<
535 opp-peak-kBps = <62200 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-2054400000 { <<
539 opp-hz = /bits/ 64 <20 <<
540 opp-peak-kBps = <72160 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-2150400000 { <<
544 opp-hz = /bits/ 64 <21 <<
545 opp-peak-kBps = <72160 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-2246400000 { <<
549 opp-hz = /bits/ 64 <22 <<
550 opp-peak-kBps = <72160 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-2342400000 { <<
554 opp-hz = /bits/ 64 <23 <<
555 opp-peak-kBps = <83680 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-2419200000 { <<
559 opp-hz = /bits/ 64 <24 <<
560 opp-peak-kBps = <83680 <<
561 }; <<
562 }; <<
563 <<
564 cpu7_opp_table: opp-table-cpu7 { <<
565 compatible = "operating-points <<
566 opp-shared; <<
567 <<
568 cpu7_opp1: opp-844800000 { <<
569 opp-hz = /bits/ 64 <84 <<
570 opp-peak-kBps = <21880 <<
571 }; <<
572 <<
573 cpu7_opp2: opp-960000000 { <<
574 opp-hz = /bits/ 64 <96 <<
575 opp-peak-kBps = <21880 <<
576 }; <<
577 <<
578 cpu7_opp3: opp-1075200000 { <<
579 opp-hz = /bits/ 64 <10 <<
580 opp-peak-kBps = <30720 <<
581 }; <<
582 <<
583 cpu7_opp4: opp-1190400000 { <<
584 opp-hz = /bits/ 64 <11 <<
585 opp-peak-kBps = <30720 <<
586 }; <<
587 <<
588 cpu7_opp5: opp-1305600000 { <<
589 opp-hz = /bits/ 64 <13 <<
590 opp-peak-kBps = <40680 <<
591 }; <<
592 <<
593 cpu7_opp6: opp-1401600000 { <<
594 opp-hz = /bits/ 64 <14 <<
595 opp-peak-kBps = <40680 <<
596 }; <<
597 <<
598 cpu7_opp7: opp-1516800000 { <<
599 opp-hz = /bits/ 64 <15 <<
600 opp-peak-kBps = <40680 <<
601 }; <<
602 <<
603 cpu7_opp8: opp-1632000000 { <<
604 opp-hz = /bits/ 64 <16 <<
605 opp-peak-kBps = <54120 <<
606 }; <<
607 <<
608 cpu7_opp9: opp-1747200000 { <<
609 opp-hz = /bits/ 64 <17 <<
610 opp-peak-kBps = <54120 <<
611 }; <<
612 <<
613 cpu7_opp10: opp-1862400000 { <<
614 opp-hz = /bits/ 64 <18 <<
615 opp-peak-kBps = <62200 <<
616 }; <<
617 <<
618 cpu7_opp11: opp-1977600000 { <<
619 opp-hz = /bits/ 64 <19 <<
620 opp-peak-kBps = <62200 <<
621 }; <<
622 <<
623 cpu7_opp12: opp-2073600000 { <<
624 opp-hz = /bits/ 64 <20 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu7_opp13: opp-2169600000 { <<
629 opp-hz = /bits/ 64 <21 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 <<
633 cpu7_opp14: opp-2265600000 { <<
634 opp-hz = /bits/ 64 <22 <<
635 opp-peak-kBps = <72160 <<
636 }; <<
637 <<
638 cpu7_opp15: opp-2361600000 { <<
639 opp-hz = /bits/ 64 <23 <<
640 opp-peak-kBps = <83680 <<
641 }; <<
642 <<
643 cpu7_opp16: opp-2457600000 { <<
644 opp-hz = /bits/ 64 <24 <<
645 opp-peak-kBps = <83680 <<
646 }; <<
647 <<
648 cpu7_opp17: opp-2553600000 { <<
649 opp-hz = /bits/ 64 <25 <<
650 opp-peak-kBps = <83680 <<
651 }; <<
652 <<
653 cpu7_opp18: opp-2649600000 { <<
654 opp-hz = /bits/ 64 <26 <<
655 opp-peak-kBps = <83680 <<
656 }; <<
657 <<
658 cpu7_opp19: opp-2745600000 { <<
659 opp-hz = /bits/ 64 <27 <<
660 opp-peak-kBps = <83680 <<
661 }; <<
662 <<
663 cpu7_opp20: opp-2841600000 { <<
664 opp-hz = /bits/ 64 <28 <<
665 opp-peak-kBps = <83680 <<
666 }; <<
667 }; 261 };
668 262
669 firmware { 263 firmware {
670 scm: scm { 264 scm: scm {
671 compatible = "qcom,scm !! 265 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 266 #reset-cells = <1>;
674 }; 267 };
675 }; 268 };
676 269
677 memory@80000000 { 270 memory@80000000 {
678 device_type = "memory"; 271 device_type = "memory";
679 /* We expect the bootloader to 272 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 273 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 274 };
682 275
>> 276 mmcx_reg: mmcx-reg {
>> 277 compatible = "regulator-fixed-domain";
>> 278 power-domains = <&rpmhpd SM8250_MMCX>;
>> 279 required-opps = <&rpmhpd_opp_low_svs>;
>> 280 regulator-name = "MMCX";
>> 281 };
>> 282
683 pmu { 283 pmu {
684 compatible = "arm,armv8-pmuv3" 284 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 286 };
687 287
688 psci { 288 psci {
689 compatible = "arm,psci-1.0"; 289 compatible = "arm,psci-1.0";
690 method = "smc"; 290 method = "smc";
691 <<
692 CPU_PD0: power-domain-cpu0 { <<
693 #power-domain-cells = <<
694 power-domains = <&CLUS <<
695 domain-idle-states = < <<
696 }; <<
697 <<
698 CPU_PD1: power-domain-cpu1 { <<
699 #power-domain-cells = <<
700 power-domains = <&CLUS <<
701 domain-idle-states = < <<
702 }; <<
703 <<
704 CPU_PD2: power-domain-cpu2 { <<
705 #power-domain-cells = <<
706 power-domains = <&CLUS <<
707 domain-idle-states = < <<
708 }; <<
709 <<
710 CPU_PD3: power-domain-cpu3 { <<
711 #power-domain-cells = <<
712 power-domains = <&CLUS <<
713 domain-idle-states = < <<
714 }; <<
715 <<
716 CPU_PD4: power-domain-cpu4 { <<
717 #power-domain-cells = <<
718 power-domains = <&CLUS <<
719 domain-idle-states = < <<
720 }; <<
721 <<
722 CPU_PD5: power-domain-cpu5 { <<
723 #power-domain-cells = <<
724 power-domains = <&CLUS <<
725 domain-idle-states = < <<
726 }; <<
727 <<
728 CPU_PD6: power-domain-cpu6 { <<
729 #power-domain-cells = <<
730 power-domains = <&CLUS <<
731 domain-idle-states = < <<
732 }; <<
733 <<
734 CPU_PD7: power-domain-cpu7 { <<
735 #power-domain-cells = <<
736 power-domains = <&CLUS <<
737 domain-idle-states = < <<
738 }; <<
739 <<
740 CLUSTER_PD: power-domain-cpu-c <<
741 #power-domain-cells = <<
742 domain-idle-states = < <<
743 }; <<
744 }; <<
745 <<
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; 291 };
764 292
765 reserved-memory { 293 reserved-memory {
766 #address-cells = <2>; 294 #address-cells = <2>;
767 #size-cells = <2>; 295 #size-cells = <2>;
768 ranges; 296 ranges;
769 297
770 hyp_mem: memory@80000000 { 298 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 299 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 300 no-map;
773 }; 301 };
774 302
775 xbl_aop_mem: memory@80700000 { 303 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 304 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 305 no-map;
778 }; 306 };
779 307
780 cmd_db: memory@80860000 { 308 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 309 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 310 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 311 no-map;
784 }; 312 };
785 313
786 smem_mem: memory@80900000 { 314 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 315 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 316 no-map;
789 }; 317 };
790 318
791 removed_mem: memory@80b00000 { 319 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 320 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 321 no-map;
794 }; 322 };
795 323
796 camera_mem: memory@86200000 { 324 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 325 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 326 no-map;
799 }; 327 };
800 328
801 wlan_mem: memory@86700000 { 329 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 330 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 331 no-map;
804 }; 332 };
805 333
806 ipa_fw_mem: memory@86800000 { 334 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 335 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 336 no-map;
809 }; 337 };
810 338
811 ipa_gsi_mem: memory@86810000 { 339 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 340 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 341 no-map;
814 }; 342 };
815 343
816 gpu_mem: memory@8681a000 { 344 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 345 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 346 no-map;
819 }; 347 };
820 348
821 npu_mem: memory@86900000 { 349 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 350 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 351 no-map;
824 }; 352 };
825 353
826 video_mem: memory@86e00000 { 354 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 355 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 356 no-map;
829 }; 357 };
830 358
831 cvp_mem: memory@87300000 { 359 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 360 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 361 no-map;
834 }; 362 };
835 363
836 cdsp_mem: memory@87800000 { 364 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 365 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 366 no-map;
839 }; 367 };
840 368
841 slpi_mem: memory@88c00000 { 369 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 370 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 371 no-map;
844 }; 372 };
845 373
846 adsp_mem: memory@8a100000 { 374 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 375 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 376 no-map;
849 }; 377 };
850 378
851 spss_mem: memory@8be00000 { 379 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 380 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 381 no-map;
854 }; 382 };
855 383
856 cdsp_secure_heap: memory@8bf00 384 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 385 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 386 no-map;
859 }; 387 };
860 }; 388 };
861 389
862 smem { 390 smem {
863 compatible = "qcom,smem"; 391 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 392 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 393 hwlocks = <&tcsr_mutex 3>;
866 }; 394 };
867 395
868 smp2p-adsp { 396 smp2p-adsp {
869 compatible = "qcom,smp2p"; 397 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 398 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 400 IPCC_MPROC_SIGNAL_SMP2P
873 I 401 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 402 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 403 IPCC_MPROC_SIGNAL_SMP2P>;
876 404
877 qcom,local-pid = <0>; 405 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 406 qcom,remote-pid = <2>;
879 407
880 smp2p_adsp_out: master-kernel 408 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 409 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 410 #qcom,smem-state-cells = <1>;
883 }; 411 };
884 412
885 smp2p_adsp_in: slave-kernel { 413 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 414 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 415 interrupt-controller;
888 #interrupt-cells = <2> 416 #interrupt-cells = <2>;
889 }; 417 };
890 }; 418 };
891 419
892 smp2p-cdsp { 420 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 421 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 422 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 424 IPCC_MPROC_SIGNAL_SMP2P
897 I 425 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 426 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 427 IPCC_MPROC_SIGNAL_SMP2P>;
900 428
901 qcom,local-pid = <0>; 429 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 430 qcom,remote-pid = <5>;
903 431
904 smp2p_cdsp_out: master-kernel 432 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 433 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 434 #qcom,smem-state-cells = <1>;
907 }; 435 };
908 436
909 smp2p_cdsp_in: slave-kernel { 437 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 438 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 439 interrupt-controller;
912 #interrupt-cells = <2> 440 #interrupt-cells = <2>;
913 }; 441 };
914 }; 442 };
915 443
916 smp2p-slpi { 444 smp2p-slpi {
917 compatible = "qcom,smp2p"; 445 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 446 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 448 IPCC_MPROC_SIGNAL_SMP2P
921 I 449 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 450 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 451 IPCC_MPROC_SIGNAL_SMP2P>;
924 452
925 qcom,local-pid = <0>; 453 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 454 qcom,remote-pid = <3>;
927 455
928 smp2p_slpi_out: master-kernel 456 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 457 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 458 #qcom,smem-state-cells = <1>;
931 }; 459 };
932 460
933 smp2p_slpi_in: slave-kernel { 461 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 462 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 463 interrupt-controller;
936 #interrupt-cells = <2> 464 #interrupt-cells = <2>;
937 }; 465 };
938 }; 466 };
939 467
940 soc: soc@0 { 468 soc: soc@0 {
941 #address-cells = <2>; 469 #address-cells = <2>;
942 #size-cells = <2>; 470 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 471 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 472 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 473 compatible = "simple-bus";
946 474
947 gcc: clock-controller@100000 { 475 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 476 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 477 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 478 #clock-cells = <1>;
951 #reset-cells = <1>; 479 #reset-cells = <1>;
952 #power-domain-cells = 480 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 481 clock-names = "bi_tcxo",
954 "bi_tcxo 482 "bi_tcxo_ao",
955 "sleep_c 483 "sleep_clk";
956 clocks = <&rpmhcc RPMH 484 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 485 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 486 <&sleep_clk>;
959 }; 487 };
960 488
961 ipcc: mailbox@408000 { 489 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 491 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 493 interrupt-controller;
966 #interrupt-cells = <3> 494 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 495 #mbox-cells = <2>;
968 }; 496 };
969 497
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 498 rng: rng@793000 {
983 compatible = "qcom,prn 499 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 500 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 501 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 502 clock-names = "core";
987 }; 503 };
988 504
>> 505 qup_opp_table: qup-opp-table {
>> 506 compatible = "operating-points-v2";
>> 507
>> 508 opp-50000000 {
>> 509 opp-hz = /bits/ 64 <50000000>;
>> 510 required-opps = <&rpmhpd_opp_min_svs>;
>> 511 };
>> 512
>> 513 opp-75000000 {
>> 514 opp-hz = /bits/ 64 <75000000>;
>> 515 required-opps = <&rpmhpd_opp_low_svs>;
>> 516 };
>> 517
>> 518 opp-120000000 {
>> 519 opp-hz = /bits/ 64 <120000000>;
>> 520 required-opps = <&rpmhpd_opp_svs>;
>> 521 };
>> 522 };
>> 523
989 gpi_dma2: dma-controller@80000 524 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 !! 525 compatible = "qcom,sm8250-gpi-dma";
991 reg = <0 0x00800000 0 526 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 537 dma-channels = <10>;
1003 dma-channel-mask = <0 538 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 539 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 540 #dma-cells = <3>;
1006 status = "disabled"; 541 status = "disabled";
1007 }; 542 };
1008 543
1009 qupv3_id_2: geniqup@8c0000 { 544 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 545 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 546 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 547 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 550 #address-cells = <2>;
1016 #size-cells = <2>; 551 #size-cells = <2>;
1017 iommus = <&apps_smmu 552 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 553 ranges;
1019 status = "disabled"; 554 status = "disabled";
1020 555
1021 i2c14: i2c@880000 { 556 i2c14: i2c@880000 {
1022 compatible = 557 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 558 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 559 clock-names = "se";
1025 clocks = <&gc 560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 561 pinctrl-names = "default";
1027 pinctrl-0 = < 562 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 563 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 564 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 565 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 566 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 567 #address-cells = <1>;
1040 #size-cells = 568 #size-cells = <0>;
1041 status = "dis 569 status = "disabled";
1042 }; 570 };
1043 571
1044 spi14: spi@880000 { 572 spi14: spi@880000 {
1045 compatible = 573 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 574 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 575 clock-names = "se";
1048 clocks = <&gc 576 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 577 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 578 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 579 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 580 dma-names = "tx", "rx";
1053 power-domains !! 581 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 582 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 583 #address-cells = <1>;
1062 #size-cells = 584 #size-cells = <0>;
1063 status = "dis 585 status = "disabled";
1064 }; 586 };
1065 587
1066 i2c15: i2c@884000 { 588 i2c15: i2c@884000 {
1067 compatible = 589 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 590 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 591 clock-names = "se";
1070 clocks = <&gc 592 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 593 pinctrl-names = "default";
1072 pinctrl-0 = < 594 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 595 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 597 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 598 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 599 #address-cells = <1>;
1085 #size-cells = 600 #size-cells = <0>;
1086 status = "dis 601 status = "disabled";
1087 }; 602 };
1088 603
1089 spi15: spi@884000 { 604 spi15: spi@884000 {
1090 compatible = 605 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 606 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 607 clock-names = "se";
1093 clocks = <&gc 608 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 609 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 610 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 611 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 612 dma-names = "tx", "rx";
1098 power-domains !! 613 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 614 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 615 #address-cells = <1>;
1107 #size-cells = 616 #size-cells = <0>;
1108 status = "dis 617 status = "disabled";
1109 }; 618 };
1110 619
1111 i2c16: i2c@888000 { 620 i2c16: i2c@888000 {
1112 compatible = 621 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 622 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 623 clock-names = "se";
1115 clocks = <&gc 624 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 625 pinctrl-names = "default";
1117 pinctrl-0 = < 626 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 627 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 628 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 629 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 630 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 631 #address-cells = <1>;
1130 #size-cells = 632 #size-cells = <0>;
1131 status = "dis 633 status = "disabled";
1132 }; 634 };
1133 635
1134 spi16: spi@888000 { 636 spi16: spi@888000 {
1135 compatible = 637 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 638 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 639 clock-names = "se";
1138 clocks = <&gc 640 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 641 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 642 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 643 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 644 dma-names = "tx", "rx";
1143 power-domains !! 645 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 646 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 647 #address-cells = <1>;
1152 #size-cells = 648 #size-cells = <0>;
1153 status = "dis 649 status = "disabled";
1154 }; 650 };
1155 651
1156 i2c17: i2c@88c000 { 652 i2c17: i2c@88c000 {
1157 compatible = 653 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 654 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 655 clock-names = "se";
1160 clocks = <&gc 656 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 657 pinctrl-names = "default";
1162 pinctrl-0 = < 658 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 659 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 660 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 661 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 662 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 663 #address-cells = <1>;
1175 #size-cells = 664 #size-cells = <0>;
1176 status = "dis 665 status = "disabled";
1177 }; 666 };
1178 667
1179 spi17: spi@88c000 { 668 spi17: spi@88c000 {
1180 compatible = 669 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 670 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 671 clock-names = "se";
1183 clocks = <&gc 672 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 673 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 674 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 675 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 676 dma-names = "tx", "rx";
1188 power-domains !! 677 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 678 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 679 #address-cells = <1>;
1197 #size-cells = 680 #size-cells = <0>;
1198 status = "dis 681 status = "disabled";
1199 }; 682 };
1200 683
1201 uart17: serial@88c000 684 uart17: serial@88c000 {
1202 compatible = 685 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 686 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 687 clock-names = "se";
1205 clocks = <&gc 688 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 689 pinctrl-names = "default";
1207 pinctrl-0 = < 690 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 691 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 692 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 693 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 694 status = "disabled";
1216 }; 695 };
1217 696
1218 i2c18: i2c@890000 { 697 i2c18: i2c@890000 {
1219 compatible = 698 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 699 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 700 clock-names = "se";
1222 clocks = <&gc 701 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 702 pinctrl-names = "default";
1224 pinctrl-0 = < 703 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 705 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 706 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 707 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 708 #address-cells = <1>;
1237 #size-cells = 709 #size-cells = <0>;
1238 status = "dis 710 status = "disabled";
1239 }; 711 };
1240 712
1241 spi18: spi@890000 { 713 spi18: spi@890000 {
1242 compatible = 714 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 715 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 716 clock-names = "se";
1245 clocks = <&gc 717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 718 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 719 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 720 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 721 dma-names = "tx", "rx";
1250 power-domains !! 722 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 723 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 724 #address-cells = <1>;
1259 #size-cells = 725 #size-cells = <0>;
1260 status = "dis 726 status = "disabled";
1261 }; 727 };
1262 728
1263 uart18: serial@890000 729 uart18: serial@890000 {
1264 compatible = 730 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 731 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 732 clock-names = "se";
1267 clocks = <&gc 733 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 734 pinctrl-names = "default";
1269 pinctrl-0 = < 735 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 736 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 737 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 738 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 739 status = "disabled";
1278 }; 740 };
1279 741
1280 i2c19: i2c@894000 { 742 i2c19: i2c@894000 {
1281 compatible = 743 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 744 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 745 clock-names = "se";
1284 clocks = <&gc 746 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 747 pinctrl-names = "default";
1286 pinctrl-0 = < 748 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 749 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 750 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 751 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 752 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 753 #address-cells = <1>;
1299 #size-cells = 754 #size-cells = <0>;
1300 status = "dis 755 status = "disabled";
1301 }; 756 };
1302 757
1303 spi19: spi@894000 { 758 spi19: spi@894000 {
1304 compatible = 759 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 760 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 761 clock-names = "se";
1307 clocks = <&gc 762 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 763 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 764 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 765 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 766 dma-names = "tx", "rx";
1312 power-domains !! 767 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 768 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 769 #address-cells = <1>;
1321 #size-cells = 770 #size-cells = <0>;
1322 status = "dis 771 status = "disabled";
1323 }; 772 };
1324 }; 773 };
1325 774
1326 gpi_dma0: dma-controller@9000 775 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm !! 776 compatible = "qcom,sm8250-gpi-dma";
1328 reg = <0 0x00900000 0 777 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 779 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 780 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 781 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 782 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 783 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 784 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 785 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 786 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 787 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 788 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 789 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 790 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 791 dma-channels = <15>;
1343 dma-channel-mask = <0 792 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 793 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 794 #dma-cells = <3>;
1346 status = "disabled"; 795 status = "disabled";
1347 }; 796 };
1348 797
1349 qupv3_id_0: geniqup@9c0000 { 798 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 799 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 800 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 801 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 804 #address-cells = <2>;
1356 #size-cells = <2>; 805 #size-cells = <2>;
1357 iommus = <&apps_smmu 806 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 807 ranges;
1359 status = "disabled"; 808 status = "disabled";
1360 809
1361 i2c0: i2c@980000 { 810 i2c0: i2c@980000 {
1362 compatible = 811 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 812 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 813 clock-names = "se";
1365 clocks = <&gc 814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 815 pinctrl-names = "default";
1367 pinctrl-0 = < 816 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 818 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 819 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 820 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 821 #address-cells = <1>;
1380 #size-cells = 822 #size-cells = <0>;
1381 status = "dis 823 status = "disabled";
1382 }; 824 };
1383 825
1384 spi0: spi@980000 { 826 spi0: spi@980000 {
1385 compatible = 827 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 828 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 829 clock-names = "se";
1388 clocks = <&gc 830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 831 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 832 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 833 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 834 dma-names = "tx", "rx";
1393 power-domains !! 835 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 836 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 837 #address-cells = <1>;
1402 #size-cells = 838 #size-cells = <0>;
1403 status = "dis 839 status = "disabled";
1404 }; 840 };
1405 841
1406 i2c1: i2c@984000 { 842 i2c1: i2c@984000 {
1407 compatible = 843 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 844 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 845 clock-names = "se";
1410 clocks = <&gc 846 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 847 pinctrl-names = "default";
1412 pinctrl-0 = < 848 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 849 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 850 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 851 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 852 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 853 #address-cells = <1>;
1425 #size-cells = 854 #size-cells = <0>;
1426 status = "dis 855 status = "disabled";
1427 }; 856 };
1428 857
1429 spi1: spi@984000 { 858 spi1: spi@984000 {
1430 compatible = 859 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 860 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 861 clock-names = "se";
1433 clocks = <&gc 862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 864 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 865 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 866 dma-names = "tx", "rx";
1438 power-domains !! 867 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 868 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 869 #address-cells = <1>;
1447 #size-cells = 870 #size-cells = <0>;
1448 status = "dis 871 status = "disabled";
1449 }; 872 };
1450 873
1451 i2c2: i2c@988000 { 874 i2c2: i2c@988000 {
1452 compatible = 875 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 876 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 877 clock-names = "se";
1455 clocks = <&gc 878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 879 pinctrl-names = "default";
1457 pinctrl-0 = < 880 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 882 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 883 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 884 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 885 #address-cells = <1>;
1470 #size-cells = 886 #size-cells = <0>;
1471 status = "dis 887 status = "disabled";
1472 }; 888 };
1473 889
1474 spi2: spi@988000 { 890 spi2: spi@988000 {
1475 compatible = 891 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 892 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 893 clock-names = "se";
1478 clocks = <&gc 894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 895 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 896 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 897 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 898 dma-names = "tx", "rx";
1483 power-domains !! 899 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 900 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 901 #address-cells = <1>;
1492 #size-cells = 902 #size-cells = <0>;
1493 status = "dis 903 status = "disabled";
1494 }; 904 };
1495 905
1496 uart2: serial@988000 906 uart2: serial@988000 {
1497 compatible = 907 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 908 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 909 clock-names = "se";
1500 clocks = <&gc 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 911 pinctrl-names = "default";
1502 pinctrl-0 = < 912 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 914 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 915 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 916 status = "disabled";
1511 }; 917 };
1512 918
1513 i2c3: i2c@98c000 { 919 i2c3: i2c@98c000 {
1514 compatible = 920 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 921 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 922 clock-names = "se";
1517 clocks = <&gc 923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 924 pinctrl-names = "default";
1519 pinctrl-0 = < 925 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 927 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 928 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 929 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 930 #address-cells = <1>;
1532 #size-cells = 931 #size-cells = <0>;
1533 status = "dis 932 status = "disabled";
1534 }; 933 };
1535 934
1536 spi3: spi@98c000 { 935 spi3: spi@98c000 {
1537 compatible = 936 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 937 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 938 clock-names = "se";
1540 clocks = <&gc 939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 940 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 941 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 942 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 943 dma-names = "tx", "rx";
1545 power-domains !! 944 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 945 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 946 #address-cells = <1>;
1554 #size-cells = 947 #size-cells = <0>;
1555 status = "dis 948 status = "disabled";
1556 }; 949 };
1557 950
1558 i2c4: i2c@990000 { 951 i2c4: i2c@990000 {
1559 compatible = 952 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 953 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 954 clock-names = "se";
1562 clocks = <&gc 955 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 956 pinctrl-names = "default";
1564 pinctrl-0 = < 957 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 958 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 959 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 960 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 961 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 962 #address-cells = <1>;
1577 #size-cells = 963 #size-cells = <0>;
1578 status = "dis 964 status = "disabled";
1579 }; 965 };
1580 966
1581 spi4: spi@990000 { 967 spi4: spi@990000 {
1582 compatible = 968 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 969 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 970 clock-names = "se";
1585 clocks = <&gc 971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 972 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 973 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 974 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 975 dma-names = "tx", "rx";
1590 power-domains !! 976 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 977 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 978 #address-cells = <1>;
1599 #size-cells = 979 #size-cells = <0>;
1600 status = "dis 980 status = "disabled";
1601 }; 981 };
1602 982
1603 i2c5: i2c@994000 { 983 i2c5: i2c@994000 {
1604 compatible = 984 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 985 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 986 clock-names = "se";
1607 clocks = <&gc 987 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 988 pinctrl-names = "default";
1609 pinctrl-0 = < 989 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 990 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 991 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 992 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 993 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 994 #address-cells = <1>;
1622 #size-cells = 995 #size-cells = <0>;
1623 status = "dis 996 status = "disabled";
1624 }; 997 };
1625 998
1626 spi5: spi@994000 { 999 spi5: spi@994000 {
1627 compatible = 1000 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1001 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1002 clock-names = "se";
1630 clocks = <&gc 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1005 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1006 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1007 dma-names = "tx", "rx";
1635 power-domains !! 1008 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1009 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1010 #address-cells = <1>;
1644 #size-cells = 1011 #size-cells = <0>;
1645 status = "dis 1012 status = "disabled";
1646 }; 1013 };
1647 1014
1648 i2c6: i2c@998000 { 1015 i2c6: i2c@998000 {
1649 compatible = 1016 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1017 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1018 clock-names = "se";
1652 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1020 pinctrl-names = "default";
1654 pinctrl-0 = < 1021 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1022 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1023 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1024 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1025 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1026 #address-cells = <1>;
1667 #size-cells = 1027 #size-cells = <0>;
1668 status = "dis 1028 status = "disabled";
1669 }; 1029 };
1670 1030
1671 spi6: spi@998000 { 1031 spi6: spi@998000 {
1672 compatible = 1032 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1033 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1034 clock-names = "se";
1675 clocks = <&gc 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1036 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1037 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1038 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1039 dma-names = "tx", "rx";
1680 power-domains !! 1040 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1041 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1042 #address-cells = <1>;
1689 #size-cells = 1043 #size-cells = <0>;
1690 status = "dis 1044 status = "disabled";
1691 }; 1045 };
1692 1046
1693 uart6: serial@998000 1047 uart6: serial@998000 {
1694 compatible = 1048 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1049 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1050 clock-names = "se";
1697 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1052 pinctrl-names = "default";
1699 pinctrl-0 = < 1053 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1054 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1055 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1056 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1057 status = "disabled";
1708 }; 1058 };
1709 1059
1710 i2c7: i2c@99c000 { 1060 i2c7: i2c@99c000 {
1711 compatible = 1061 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1062 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1063 clock-names = "se";
1714 clocks = <&gc 1064 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1065 pinctrl-names = "default";
1716 pinctrl-0 = < 1066 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1067 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1068 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1069 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1070 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1071 #address-cells = <1>;
1729 #size-cells = 1072 #size-cells = <0>;
1730 status = "dis 1073 status = "disabled";
1731 }; 1074 };
1732 1075
1733 spi7: spi@99c000 { 1076 spi7: spi@99c000 {
1734 compatible = 1077 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1078 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1079 clock-names = "se";
1737 clocks = <&gc 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1081 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1082 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1083 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1084 dma-names = "tx", "rx";
1742 power-domains !! 1085 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1086 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1087 #address-cells = <1>;
1751 #size-cells = 1088 #size-cells = <0>;
1752 status = "dis 1089 status = "disabled";
1753 }; 1090 };
1754 }; 1091 };
1755 1092
1756 gpi_dma1: dma-controller@a000 1093 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm !! 1094 compatible = "qcom,sm8250-gpi-dma";
1758 reg = <0 0x00a00000 0 1095 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1096 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1097 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1098 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1099 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1100 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1101 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1102 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1103 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1104 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1105 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1106 dma-channels = <10>;
1770 dma-channel-mask = <0 1107 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1108 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1109 #dma-cells = <3>;
1773 status = "disabled"; 1110 status = "disabled";
1774 }; 1111 };
1775 1112
1776 qupv3_id_1: geniqup@ac0000 { 1113 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1114 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1115 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1116 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1117 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1118 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1119 #address-cells = <2>;
1783 #size-cells = <2>; 1120 #size-cells = <2>;
1784 iommus = <&apps_smmu 1121 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1122 ranges;
1786 status = "disabled"; 1123 status = "disabled";
1787 1124
1788 i2c8: i2c@a80000 { 1125 i2c8: i2c@a80000 {
1789 compatible = 1126 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1127 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1128 clock-names = "se";
1792 clocks = <&gc 1129 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1130 pinctrl-names = "default";
1794 pinctrl-0 = < 1131 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1132 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1133 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1134 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1135 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1136 #address-cells = <1>;
1807 #size-cells = 1137 #size-cells = <0>;
1808 status = "dis 1138 status = "disabled";
1809 }; 1139 };
1810 1140
1811 spi8: spi@a80000 { 1141 spi8: spi@a80000 {
1812 compatible = 1142 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1143 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1144 clock-names = "se";
1815 clocks = <&gc 1145 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1147 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1148 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1149 dma-names = "tx", "rx";
1820 power-domains !! 1150 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1151 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1152 #address-cells = <1>;
1829 #size-cells = 1153 #size-cells = <0>;
1830 status = "dis 1154 status = "disabled";
1831 }; 1155 };
1832 1156
1833 i2c9: i2c@a84000 { 1157 i2c9: i2c@a84000 {
1834 compatible = 1158 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1159 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1160 clock-names = "se";
1837 clocks = <&gc 1161 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1162 pinctrl-names = "default";
1839 pinctrl-0 = < 1163 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1165 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1166 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1167 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1168 #address-cells = <1>;
1852 #size-cells = 1169 #size-cells = <0>;
1853 status = "dis 1170 status = "disabled";
1854 }; 1171 };
1855 1172
1856 spi9: spi@a84000 { 1173 spi9: spi@a84000 {
1857 compatible = 1174 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1175 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1176 clock-names = "se";
1860 clocks = <&gc 1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1178 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1179 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1180 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1181 dma-names = "tx", "rx";
1865 power-domains !! 1182 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1183 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1184 #address-cells = <1>;
1874 #size-cells = 1185 #size-cells = <0>;
1875 status = "dis 1186 status = "disabled";
1876 }; 1187 };
1877 1188
1878 i2c10: i2c@a88000 { 1189 i2c10: i2c@a88000 {
1879 compatible = 1190 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1191 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1192 clock-names = "se";
1882 clocks = <&gc 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1194 pinctrl-names = "default";
1884 pinctrl-0 = < 1195 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1197 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1198 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1199 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1200 #address-cells = <1>;
1897 #size-cells = 1201 #size-cells = <0>;
1898 status = "dis 1202 status = "disabled";
1899 }; 1203 };
1900 1204
1901 spi10: spi@a88000 { 1205 spi10: spi@a88000 {
1902 compatible = 1206 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1207 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1208 clock-names = "se";
1905 clocks = <&gc 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1210 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1211 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1212 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1213 dma-names = "tx", "rx";
1910 power-domains !! 1214 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1215 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1216 #address-cells = <1>;
1919 #size-cells = 1217 #size-cells = <0>;
1920 status = "dis 1218 status = "disabled";
1921 }; 1219 };
1922 1220
1923 i2c11: i2c@a8c000 { 1221 i2c11: i2c@a8c000 {
1924 compatible = 1222 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1223 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1224 clock-names = "se";
1927 clocks = <&gc 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1226 pinctrl-names = "default";
1929 pinctrl-0 = < 1227 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1228 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1229 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1230 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1231 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1232 #address-cells = <1>;
1942 #size-cells = 1233 #size-cells = <0>;
1943 status = "dis 1234 status = "disabled";
1944 }; 1235 };
1945 1236
1946 spi11: spi@a8c000 { 1237 spi11: spi@a8c000 {
1947 compatible = 1238 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1239 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1240 clock-names = "se";
1950 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1242 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1243 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1244 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1245 dma-names = "tx", "rx";
1955 power-domains !! 1246 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1247 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1248 #address-cells = <1>;
1964 #size-cells = 1249 #size-cells = <0>;
1965 status = "dis 1250 status = "disabled";
1966 }; 1251 };
1967 1252
1968 i2c12: i2c@a90000 { 1253 i2c12: i2c@a90000 {
1969 compatible = 1254 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1255 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1256 clock-names = "se";
1972 clocks = <&gc 1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1258 pinctrl-names = "default";
1974 pinctrl-0 = < 1259 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1260 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1261 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1262 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1263 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1264 #address-cells = <1>;
1987 #size-cells = 1265 #size-cells = <0>;
1988 status = "dis 1266 status = "disabled";
1989 }; 1267 };
1990 1268
1991 spi12: spi@a90000 { 1269 spi12: spi@a90000 {
1992 compatible = 1270 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1271 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1272 clock-names = "se";
1995 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1274 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1275 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1276 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1277 dma-names = "tx", "rx";
2000 power-domains !! 1278 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1279 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1280 #address-cells = <1>;
2009 #size-cells = 1281 #size-cells = <0>;
2010 status = "dis 1282 status = "disabled";
2011 }; 1283 };
2012 1284
2013 uart12: serial@a90000 1285 uart12: serial@a90000 {
2014 compatible = 1286 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1287 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1288 clock-names = "se";
2017 clocks = <&gc 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1290 pinctrl-names = "default";
2019 pinctrl-0 = < 1291 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1292 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1293 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1294 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1295 status = "disabled";
2028 }; 1296 };
2029 1297
2030 i2c13: i2c@a94000 { 1298 i2c13: i2c@a94000 {
2031 compatible = 1299 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1300 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1301 clock-names = "se";
2034 clocks = <&gc 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1303 pinctrl-names = "default";
2036 pinctrl-0 = < 1304 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1305 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1306 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1307 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1308 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1309 #address-cells = <1>;
2049 #size-cells = 1310 #size-cells = <0>;
2050 status = "dis 1311 status = "disabled";
2051 }; 1312 };
2052 1313
2053 spi13: spi@a94000 { 1314 spi13: spi@a94000 {
2054 compatible = 1315 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1316 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1317 clock-names = "se";
2057 clocks = <&gc 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1320 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1321 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1322 dma-names = "tx", "rx";
2062 power-domains !! 1323 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1324 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1325 #address-cells = <1>;
2071 #size-cells = 1326 #size-cells = <0>;
2072 status = "dis 1327 status = "disabled";
2073 }; 1328 };
2074 }; 1329 };
2075 1330
2076 config_noc: interconnect@1500 1331 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1332 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1333 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1334 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1335 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1336 };
2082 1337
2083 system_noc: interconnect@1620 1338 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1339 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1340 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1341 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1342 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1343 };
2089 1344
2090 mc_virt: interconnect@163d000 1345 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1346 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1347 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1348 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1349 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1350 };
2096 1351
2097 aggre1_noc: interconnect@16e0 1352 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1353 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1354 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1355 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1356 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1357 };
2103 1358
2104 aggre2_noc: interconnect@1700 1359 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1360 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1361 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1362 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1363 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1364 };
2110 1365
2111 compute_noc: interconnect@173 1366 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1367 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1368 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1369 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1370 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1371 };
2117 1372
2118 mmss_noc: interconnect@174000 1373 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1374 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1375 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1376 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1377 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1378 };
2124 1379
2125 pcie0: pcie@1c00000 { !! 1380 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1381 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1382 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1383 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1384 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1385 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1386 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1387 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1388 device_type = "pci";
2135 linux,pci-domain = <0 1389 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1390 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1391 num-lanes = <1>;
2138 1392
2139 #address-cells = <3>; 1393 #address-cells = <3>;
2140 #size-cells = <2>; 1394 #size-cells = <2>;
2141 1395
2142 ranges = <0x01000000 1396 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 1397 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 1398
2145 interrupts = <GIC_SPI !! 1399 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1400 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1401 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1402 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1403 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1404 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1405 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1406 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1407
2168 clocks = <&gcc GCC_PC 1408 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1409 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1410 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1411 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1412 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1413 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1414 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1415 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1416 clock-names = "pipe",
2177 "aux", 1417 "aux",
2178 "cfg", 1418 "cfg",
2179 "bus_ma 1419 "bus_master",
2180 "bus_sl 1420 "bus_slave",
2181 "slave_ 1421 "slave_q2a",
2182 "tbu", 1422 "tbu",
2183 "ddrss_ 1423 "ddrss_sf_tbu";
2184 1424
>> 1425 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1426 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1427 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1428
2188 resets = <&gcc GCC_PC 1429 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1430 reset-names = "pci";
2190 1431
2191 power-domains = <&gcc 1432 power-domains = <&gcc PCIE_0_GDSC>;
2192 1433
2193 phys = <&pcie0_phy>; !! 1434 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1435 phy-names = "pciephy";
2195 1436
2196 perst-gpios = <&tlmm 1437 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1438 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1439
2199 pinctrl-names = "defa 1440 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1441 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; 1442 dma-coherent;
2202 1443
2203 status = "disabled"; 1444 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1445 };
2215 1446
2216 pcie0_phy: phy@1c06000 { 1447 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1448 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1449 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1450 #address-cells = <2>;
>> 1451 #size-cells = <2>;
>> 1452 ranges;
2220 clocks = <&gcc GCC_PC 1453 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1454 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1455 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1456 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1457 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1458
2236 resets = <&gcc GCC_PC 1459 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1460 reset-names = "phy";
2238 1461
2239 assigned-clocks = <&g 1462 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1463 assigned-clock-rates = <100000000>;
2241 1464
2242 status = "disabled"; 1465 status = "disabled";
>> 1466
>> 1467 pcie0_lane: phy@1c06200 {
>> 1468 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1469 <0 0x1c06400 0 0x200>, /* rx */
>> 1470 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1471 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1472 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1473 clock-names = "pipe0";
>> 1474
>> 1475 #phy-cells = <0>;
>> 1476
>> 1477 #clock-cells = <0>;
>> 1478 clock-output-names = "pcie_0_pipe_clk";
>> 1479 };
2243 }; 1480 };
2244 1481
2245 pcie1: pcie@1c08000 { !! 1482 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1483 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1484 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1485 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1486 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1487 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1488 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1489 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1490 device_type = "pci";
2255 linux,pci-domain = <1 1491 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1492 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1493 num-lanes = <2>;
2258 1494
2259 #address-cells = <3>; 1495 #address-cells = <3>;
2260 #size-cells = <2>; 1496 #size-cells = <2>;
2261 1497
2262 ranges = <0x01000000 1498 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1499 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1500
2265 interrupts = <GIC_SPI !! 1501 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1502 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1503 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1504 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1505 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1506 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1507 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1508 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1509
2288 clocks = <&gcc GCC_PC 1510 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1511 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1512 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1513 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1514 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1515 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1516 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1517 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1518 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1519 clock-names = "pipe",
2298 "aux", 1520 "aux",
2299 "cfg", 1521 "cfg",
2300 "bus_ma 1522 "bus_master",
2301 "bus_sl 1523 "bus_slave",
2302 "slave_ 1524 "slave_q2a",
2303 "ref", 1525 "ref",
2304 "tbu", 1526 "tbu",
2305 "ddrss_ 1527 "ddrss_sf_tbu";
2306 1528
2307 assigned-clocks = <&g 1529 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1530 assigned-clock-rates = <19200000>;
2309 1531
>> 1532 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1533 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1534 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1535
2313 resets = <&gcc GCC_PC 1536 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1537 reset-names = "pci";
2315 1538
2316 power-domains = <&gcc 1539 power-domains = <&gcc PCIE_1_GDSC>;
2317 1540
2318 phys = <&pcie1_phy>; !! 1541 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1542 phy-names = "pciephy";
2320 1543
2321 perst-gpios = <&tlmm 1544 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1545 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1546
2324 pinctrl-names = "defa 1547 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1548 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; 1549 dma-coherent;
2327 1550
2328 status = "disabled"; 1551 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1552 };
2340 1553
2341 pcie1_phy: phy@1c0e000 { 1554 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1555 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1556 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1557 #address-cells = <2>;
>> 1558 #size-cells = <2>;
>> 1559 ranges;
2345 clocks = <&gcc GCC_PC 1560 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1561 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1562 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1563 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1564 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1565
2361 resets = <&gcc GCC_PC 1566 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1567 reset-names = "phy";
2363 1568
2364 assigned-clocks = <&g 1569 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1570 assigned-clock-rates = <100000000>;
2366 1571
2367 status = "disabled"; 1572 status = "disabled";
>> 1573
>> 1574 pcie1_lane: phy@1c0e200 {
>> 1575 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1576 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1577 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1578 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1579 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1580 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1581 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1582 clock-names = "pipe0";
>> 1583
>> 1584 #phy-cells = <0>;
>> 1585
>> 1586 #clock-cells = <0>;
>> 1587 clock-output-names = "pcie_1_pipe_clk";
>> 1588 };
2368 }; 1589 };
2369 1590
2370 pcie2: pcie@1c10000 { !! 1591 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 1592 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 1593 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 1594 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 1595 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 1596 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 1597 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 1598 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 1599 device_type = "pci";
2380 linux,pci-domain = <2 1600 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 1601 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 1602 num-lanes = <2>;
2383 1603
2384 #address-cells = <3>; 1604 #address-cells = <3>;
2385 #size-cells = <2>; 1605 #size-cells = <2>;
2386 1606
2387 ranges = <0x01000000 1607 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 1608 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 1609
2390 interrupts = <GIC_SPI !! 1610 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 1611 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 1612 #interrupt-cells = <1>;
2407 interrupt-map-mask = 1613 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 1614 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 1615 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 1616 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 1617 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 1618
2413 clocks = <&gcc GCC_PC 1619 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 1620 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 1621 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 1622 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 1623 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 1624 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 1625 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 1626 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 1627 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 1628 clock-names = "pipe",
2423 "aux", 1629 "aux",
2424 "cfg", 1630 "cfg",
2425 "bus_ma 1631 "bus_master",
2426 "bus_sl 1632 "bus_slave",
2427 "slave_ 1633 "slave_q2a",
2428 "ref", 1634 "ref",
2429 "tbu", 1635 "tbu",
2430 "ddrss_ 1636 "ddrss_sf_tbu";
2431 1637
2432 assigned-clocks = <&g 1638 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 1639 assigned-clock-rates = <19200000>;
2434 1640
>> 1641 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 1642 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 1643 <0x100 &apps_smmu 0x1d01 0x1>;
2437 1644
2438 resets = <&gcc GCC_PC 1645 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 1646 reset-names = "pci";
2440 1647
2441 power-domains = <&gcc 1648 power-domains = <&gcc PCIE_2_GDSC>;
2442 1649
2443 phys = <&pcie2_phy>; !! 1650 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 1651 phy-names = "pciephy";
2445 1652
2446 perst-gpios = <&tlmm 1653 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 1654 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 1655
2449 pinctrl-names = "defa 1656 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 1657 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; 1658 dma-coherent;
2452 1659
2453 status = "disabled"; 1660 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 1661 };
2465 1662
2466 pcie2_phy: phy@1c16000 { 1663 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 1664 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 1665 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 1666 #address-cells = <2>;
>> 1667 #size-cells = <2>;
>> 1668 ranges;
2470 clocks = <&gcc GCC_PC 1669 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 1670 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 1671 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 1672 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 1673 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 1674
2486 resets = <&gcc GCC_PC 1675 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 1676 reset-names = "phy";
2488 1677
2489 assigned-clocks = <&g 1678 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 1679 assigned-clock-rates = <100000000>;
2491 1680
2492 status = "disabled"; 1681 status = "disabled";
>> 1682
>> 1683 pcie2_lane: phy@1c16200 {
>> 1684 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 1685 <0 0x1c16400 0 0x200>, /* rx0 */
>> 1686 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 1687 <0 0x1c16600 0 0x170>, /* tx1 */
>> 1688 <0 0x1c16800 0 0x200>, /* rx1 */
>> 1689 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1690 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 1691 clock-names = "pipe0";
>> 1692
>> 1693 #phy-cells = <0>;
>> 1694
>> 1695 #clock-cells = <0>;
>> 1696 clock-output-names = "pcie_2_pipe_clk";
>> 1697 };
2493 }; 1698 };
2494 1699
2495 ufs_mem_hc: ufshc@1d84000 { 1700 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 1701 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 1702 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 1703 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 1704 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 1705 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 1706 phy-names = "ufsphy";
2502 lanes-per-direction = 1707 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 1708 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 1709 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 1710 reset-names = "rst";
2506 1711
2507 power-domains = <&gcc 1712 power-domains = <&gcc UFS_PHY_GDSC>;
2508 1713
2509 iommus = <&apps_smmu 1714 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 1715
2511 clock-names = 1716 clock-names =
2512 "core_clk", 1717 "core_clk",
2513 "bus_aggr_clk 1718 "bus_aggr_clk",
2514 "iface_clk", 1719 "iface_clk",
2515 "core_clk_uni 1720 "core_clk_unipro",
2516 "ref_clk", 1721 "ref_clk",
2517 "tx_lane0_syn 1722 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 1723 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 1724 "rx_lane1_sync_clk";
2520 clocks = 1725 clocks =
2521 <&gcc GCC_UFS 1726 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 1727 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 1728 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 1729 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 1730 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 1731 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 1732 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 1733 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 1734 freq-table-hz =
2530 operating-points-v2 = !! 1735 <37500000 300000000>,
2531 !! 1736 <0 0>,
2532 interconnects = <&agg !! 1737 <0 0>,
2533 <&gem !! 1738 <37500000 300000000>,
2534 interconnect-names = !! 1739 <0 0>,
>> 1740 <0 0>,
>> 1741 <0 0>,
>> 1742 <0 0>;
2535 1743
2536 status = "disabled"; 1744 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 1745 };
2566 1746
2567 ufs_mem_phy: phy@1d87000 { 1747 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 1748 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 1749 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 1750 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 1751 #size-cells = <2>;
2572 <&gcc GCC_UF !! 1752 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 1753 clock-names = "ref",
2575 "ref_au !! 1754 "ref_aux";
2576 "qref"; !! 1755 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 1756 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 1757
2578 resets = <&ufs_mem_hc 1758 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 1759 reset-names = "ufsphy";
>> 1760 status = "disabled";
2580 1761
2581 power-domains = <&gcc 1762 power-domains = <&gcc UFS_PHY_GDSC>;
2582 1763
2583 #phy-cells = <0>; !! 1764 ufs_mem_phy_lanes: phy@1d87400 {
2584 !! 1765 reg = <0 0x01d87400 0 0x16c>,
2585 status = "disabled"; !! 1766 <0 0x01d87600 0 0x200>,
>> 1767 <0 0x01d87c00 0 0x200>,
>> 1768 <0 0x01d87800 0 0x16c>,
>> 1769 <0 0x01d87a00 0 0x200>;
>> 1770 #phy-cells = <0>;
>> 1771 };
2586 }; 1772 };
2587 1773
2588 cryptobam: dma-controller@1dc !! 1774 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 1775 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 1776 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 1777 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 1778 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 1779 };
2619 1780
2620 tcsr_mutex: hwlock@1f40000 { 1781 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 1782 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 1783 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 1784 #hwlock-cells = <1>;
2624 }; 1785 };
2625 1786
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 1787 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 1788 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 1789 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 1790 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 1791 <&audiocc 0>,
2636 <&q6afecc LP 1792 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 1793 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1794 <&aoncc 0>,
2638 <&vamacro>; 1795 <&vamacro>;
2639 1796
2640 clock-names = "mclk", !! 1797 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 1798
2642 #clock-cells = <0>; 1799 #clock-cells = <0>;
>> 1800 clock-frequency = <9600000>;
2643 clock-output-names = 1801 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 1802 #sound-dai-cells = <1>;
2645 1803
2646 pinctrl-names = "defa 1804 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 1805 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 1806 };
2651 1807
2652 swr0: soundwire@3250000 { !! 1808 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 1809 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 1810 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 1811 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 1812 clocks = <&wsamacro>;
2657 clock-names = "iface" 1813 clock-names = "iface";
2658 1814
2659 qcom,din-ports = <2>; 1815 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 1816 qcom,dout-ports = <6>;
2661 1817
2662 qcom,ports-sinterval- 1818 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 1819 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 1820 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 1821 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 1822
2667 #sound-dai-cells = <1 1823 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 1824 #address-cells = <2>;
2669 #size-cells = <0>; 1825 #size-cells = <0>;
>> 1826 };
2670 1827
2671 status = "disabled"; !! 1828 audiocc: clock-controller@3300000 {
>> 1829 compatible = "qcom,sm8250-lpass-audiocc";
>> 1830 reg = <0 0x03300000 0 0x30000>;
>> 1831 #clock-cells = <1>;
>> 1832 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1833 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1834 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 1835 clock-names = "core", "audio", "bus";
2672 }; 1836 };
2673 1837
2674 vamacro: codec@3370000 { 1838 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 1839 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 1840 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 1841 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 1842 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 1843 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 1844
2681 clock-names = "mclk", 1845 clock-names = "mclk", "macro", "dcodec";
2682 1846
2683 #clock-cells = <0>; 1847 #clock-cells = <0>;
>> 1848 clock-frequency = <9600000>;
2684 clock-output-names = 1849 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 1850 #sound-dai-cells = <1>;
2686 }; 1851 };
2687 1852
2688 rxmacro: rxmacro@3200000 { !! 1853 aoncc: clock-controller@3380000 {
2689 pinctrl-names = "defa !! 1854 compatible = "qcom,sm8250-lpass-aoncc";
2690 pinctrl-0 = <&rx_swr_ !! 1855 reg = <0 0x03380000 0 0x40000>;
2691 compatible = "qcom,sm !! 1856 #clock-cells = <1>;
2692 reg = <0 0x03200000 0 !! 1857 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2693 status = "disabled"; <<
2694 <<
2695 clocks = <&q6afecc LP <<
2696 <&q6afecc LPA <<
2697 <&q6afecc LPA <<
2698 <&q6afecc LPA 1858 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; !! 1859 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2700 !! 1860 clock-names = "core", "audio", "bus";
2701 clock-names = "mclk", <<
2702 <<
2703 #clock-cells = <0>; <<
2704 clock-output-names = <<
2705 #sound-dai-cells = <1 <<
2706 }; 1861 };
2707 1862
2708 swr1: soundwire@3210000 { !! 1863 lpass_tlmm: pinctrl@33c0000{
2709 reg = <0 0x03210000 0 <<
2710 compatible = "qcom,so <<
2711 status = "disabled"; <<
2712 interrupts = <GIC_SPI <<
2713 clocks = <&rxmacro>; <<
2714 clock-names = "iface" <<
2715 label = "RX"; <<
2716 qcom,din-ports = <0>; <<
2717 qcom,dout-ports = <5> <<
2718 <<
2719 qcom,ports-sinterval- <<
2720 qcom,ports-offset1 = <<
2721 qcom,ports-offset2 = <<
2722 qcom,ports-hstart = <<
2723 qcom,ports-hstop = <<
2724 qcom,ports-word-lengt <<
2725 qcom,ports-block-pack <<
2726 qcom,ports-lane-contr <<
2727 qcom,ports-block-grou <<
2728 <<
2729 #sound-dai-cells = <1 <<
2730 #address-cells = <2>; <<
2731 #size-cells = <0>; <<
2732 }; <<
2733 <<
2734 txmacro: txmacro@3220000 { <<
2735 pinctrl-names = "defa <<
2736 pinctrl-0 = <&tx_swr_ <<
2737 compatible = "qcom,sm <<
2738 reg = <0 0x03220000 0 <<
2739 status = "disabled"; <<
2740 <<
2741 clocks = <&q6afecc LP <<
2742 <&q6afecc LP <<
2743 <&q6afecc LP <<
2744 <&q6afecc LP <<
2745 <&vamacro>; <<
2746 <<
2747 clock-names = "mclk", <<
2748 <<
2749 #clock-cells = <0>; <<
2750 clock-output-names = <<
2751 #sound-dai-cells = <1 <<
2752 }; <<
2753 <<
2754 /* tx macro */ <<
2755 swr2: soundwire@3230000 { <<
2756 reg = <0 0x03230000 0 <<
2757 compatible = "qcom,so <<
2758 interrupts = <GIC_SPI <<
2759 interrupt-names = "co <<
2760 status = "disabled"; <<
2761 <<
2762 clocks = <&txmacro>; <<
2763 clock-names = "iface" <<
2764 label = "TX"; <<
2765 <<
2766 qcom,din-ports = <5>; <<
2767 qcom,dout-ports = <0> <<
2768 qcom,ports-sinterval- <<
2769 qcom,ports-offset1 = <<
2770 qcom,ports-offset2 = <<
2771 qcom,ports-block-pack <<
2772 qcom,ports-hstart = <<
2773 qcom,ports-hstop = <<
2774 qcom,ports-word-lengt <<
2775 qcom,ports-block-grou <<
2776 qcom,ports-lane-contr <<
2777 #sound-dai-cells = <1 <<
2778 #address-cells = <2>; <<
2779 #size-cells = <0>; <<
2780 }; <<
2781 <<
2782 lpass_tlmm: pinctrl@33c0000 { <<
2783 compatible = "qcom,sm 1864 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 1865 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 1866 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 1867 gpio-controller;
2787 #gpio-cells = <2>; 1868 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 1869 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 1870
2790 clocks = <&q6afecc LP 1871 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 1872 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 1873 clock-names = "core", "audio";
2793 1874
2794 wsa_swr_active: wsa-s !! 1875 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 1876 clk {
2796 pins 1877 pins = "gpio10";
2797 funct 1878 function = "wsa_swr_clk";
2798 drive 1879 drive-strength = <2>;
2799 slew- 1880 slew-rate = <1>;
2800 bias- 1881 bias-disable;
2801 }; 1882 };
2802 1883
2803 data-pins { !! 1884 data {
2804 pins 1885 pins = "gpio11";
2805 funct 1886 function = "wsa_swr_data";
2806 drive 1887 drive-strength = <2>;
2807 slew- 1888 slew-rate = <1>;
2808 bias- 1889 bias-bus-hold;
>> 1890
2809 }; 1891 };
2810 }; 1892 };
2811 1893
2812 wsa_swr_sleep: wsa-sw !! 1894 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 1895 clk {
2814 pins 1896 pins = "gpio10";
2815 funct 1897 function = "wsa_swr_clk";
2816 drive 1898 drive-strength = <2>;
>> 1899 input-enable;
2817 bias- 1900 bias-pull-down;
2818 }; 1901 };
2819 1902
2820 data-pins { !! 1903 data {
2821 pins 1904 pins = "gpio11";
2822 funct 1905 function = "wsa_swr_data";
2823 drive 1906 drive-strength = <2>;
>> 1907 input-enable;
2824 bias- 1908 bias-pull-down;
>> 1909
2825 }; 1910 };
2826 }; 1911 };
2827 1912
2828 dmic01_active: dmic01 !! 1913 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 1914 clk {
2830 pins 1915 pins = "gpio6";
2831 funct 1916 function = "dmic1_clk";
2832 drive 1917 drive-strength = <8>;
2833 outpu 1918 output-high;
2834 }; 1919 };
2835 data-pins { !! 1920 data {
2836 pins 1921 pins = "gpio7";
2837 funct 1922 function = "dmic1_data";
2838 drive 1923 drive-strength = <8>;
>> 1924 input-enable;
2839 }; 1925 };
2840 }; 1926 };
2841 1927
2842 dmic01_sleep: dmic01- !! 1928 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 1929 clk {
2844 pins 1930 pins = "gpio6";
2845 funct 1931 function = "dmic1_clk";
2846 drive 1932 drive-strength = <2>;
2847 bias- 1933 bias-disable;
2848 outpu 1934 output-low;
2849 }; 1935 };
2850 1936
2851 data-pins { !! 1937 data {
2852 pins 1938 pins = "gpio7";
2853 funct 1939 function = "dmic1_data";
2854 drive 1940 drive-strength = <2>;
2855 bias- 1941 bias-pull-down;
2856 }; !! 1942 input-enable;
2857 }; <<
2858 <<
2859 rx_swr_active: rx-swr <<
2860 clk-pins { <<
2861 pins <<
2862 funct <<
2863 drive <<
2864 slew- <<
2865 bias- <<
2866 }; <<
2867 <<
2868 data-pins { <<
2869 pins <<
2870 funct <<
2871 drive <<
2872 slew- <<
2873 bias- <<
2874 }; <<
2875 }; <<
2876 <<
2877 tx_swr_active: tx-swr <<
2878 clk-pins { <<
2879 pins <<
2880 funct <<
2881 drive <<
2882 slew- <<
2883 bias- <<
2884 }; <<
2885 <<
2886 data-pins { <<
2887 pins <<
2888 funct <<
2889 drive <<
2890 slew- <<
2891 bias- <<
2892 }; <<
2893 }; <<
2894 <<
2895 tx_swr_sleep: tx-swr- <<
2896 clk-pins { <<
2897 pins <<
2898 funct <<
2899 drive <<
2900 bias- <<
2901 }; <<
2902 <<
2903 data1-pins { <<
2904 pins <<
2905 funct <<
2906 drive <<
2907 bias- <<
2908 }; <<
2909 <<
2910 data2-pins { <<
2911 pins <<
2912 funct <<
2913 drive <<
2914 bias- <<
2915 }; 1943 };
2916 }; 1944 };
2917 }; 1945 };
2918 1946
2919 gpu: gpu@3d00000 { 1947 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 1948 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 1949 "qcom,adreno";
>> 1950 #stream-id-cells = <16>;
2922 1951
2923 reg = <0 0x03d00000 0 1952 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 1953 reg-names = "kgsl_3d0_reg_memory";
2925 1954
2926 interrupts = <GIC_SPI 1955 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 1956
2928 iommus = <&adreno_smm 1957 iommus = <&adreno_smmu 0 0x401>;
2929 1958
2930 operating-points-v2 = 1959 operating-points-v2 = <&gpu_opp_table>;
2931 1960
2932 qcom,gmu = <&gmu>; 1961 qcom,gmu = <&gmu>;
2933 1962
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 1963 status = "disabled";
2939 1964
2940 zap-shader { 1965 zap-shader {
2941 memory-region 1966 memory-region = <&gpu_mem>;
2942 }; 1967 };
2943 1968
>> 1969 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 1970 gpu_opp_table: opp-table {
2945 compatible = 1971 compatible = "operating-points-v2";
2946 1972
2947 opp-670000000 1973 opp-670000000 {
2948 opp-h 1974 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 1975 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 1976 };
2952 1977
2953 opp-587000000 1978 opp-587000000 {
2954 opp-h 1979 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 1980 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 1981 };
2958 1982
2959 opp-525000000 1983 opp-525000000 {
2960 opp-h 1984 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 1985 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 1986 };
2964 1987
2965 opp-490000000 1988 opp-490000000 {
2966 opp-h 1989 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 1990 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 1991 };
2970 1992
2971 opp-441600000 1993 opp-441600000 {
2972 opp-h 1994 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 1995 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 1996 };
2976 1997
2977 opp-400000000 1998 opp-400000000 {
2978 opp-h 1999 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2000 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 2001 };
2982 2002
2983 opp-305000000 2003 opp-305000000 {
2984 opp-h 2004 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2005 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 2006 };
2988 }; 2007 };
2989 }; 2008 };
2990 2009
2991 gmu: gmu@3d6a000 { 2010 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 2011 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2012
2994 reg = <0 0x03d6a000 0 2013 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2014 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2015 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2016 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2017 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2018
3000 interrupts = <GIC_SPI 2019 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2020 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2021 interrupt-names = "hfi", "gmu";
3003 2022
3004 clocks = <&gpucc GPU_ 2023 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2024 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2025 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2026 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2027 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2028 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2029
3011 power-domains = <&gpu 2030 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2031 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2032 power-domain-names = "cx", "gx";
3014 2033
3015 iommus = <&adreno_smm 2034 iommus = <&adreno_smmu 5 0x400>;
3016 2035
3017 operating-points-v2 = 2036 operating-points-v2 = <&gmu_opp_table>;
3018 2037
3019 status = "disabled"; 2038 status = "disabled";
3020 2039
3021 gmu_opp_table: opp-ta 2040 gmu_opp_table: opp-table {
3022 compatible = 2041 compatible = "operating-points-v2";
3023 2042
3024 opp-200000000 2043 opp-200000000 {
3025 opp-h 2044 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2045 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2046 };
3028 }; 2047 };
3029 }; 2048 };
3030 2049
3031 gpucc: clock-controller@3d900 2050 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2051 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2052 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2053 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2054 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2055 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2056 clock-names = "bi_tcxo",
3038 "gcc_gp 2057 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2058 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2059 #clock-cells = <1>;
3041 #reset-cells = <1>; 2060 #reset-cells = <1>;
3042 #power-domain-cells = 2061 #power-domain-cells = <1>;
3043 }; 2062 };
3044 2063
3045 adreno_smmu: iommu@3da0000 { 2064 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2065 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2066 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2067 #iommu-cells = <2>;
3050 #global-interrupts = 2068 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2069 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2070 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2071 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2072 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2073 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2074 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2075 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2076 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2077 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2078 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2079 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2080 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2081 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2082 clock-names = "ahb", "bus", "iface";
3065 2083
3066 power-domains = <&gpu 2084 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2085 };
3069 2086
3070 slpi: remoteproc@5c00000 { 2087 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2088 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2089 reg = <0 0x05c00000 0 0x4000>;
3073 2090
3074 interrupts-extended = !! 2091 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2092 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2093 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2094 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2095 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2096 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2097 "handover", "stop-ack";
3081 2098
3082 clocks = <&rpmhcc RPM 2099 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2100 clock-names = "xo";
3084 2101
3085 power-domains = <&rpm !! 2102 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
3086 <&rpm !! 2103 <&rpmhpd SM8250_LCX>,
3087 power-domain-names = !! 2104 <&rpmhpd SM8250_LMX>;
>> 2105 power-domain-names = "load_state", "lcx", "lmx";
3088 2106
3089 memory-region = <&slp 2107 memory-region = <&slpi_mem>;
3090 2108
3091 qcom,qmp = <&aoss_qmp <<
3092 <<
3093 qcom,smem-states = <& 2109 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2110 qcom,smem-state-names = "stop";
3095 2111
3096 status = "disabled"; 2112 status = "disabled";
3097 2113
3098 glink-edge { 2114 glink-edge {
3099 interrupts-ex 2115 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2116 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2117 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2118 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2119 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2120
3105 label = "slpi 2121 label = "slpi";
3106 qcom,remote-p 2122 qcom,remote-pid = <3>;
3107 2123
3108 fastrpc { 2124 fastrpc {
3109 compa 2125 compatible = "qcom,fastrpc";
3110 qcom, 2126 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2127 label = "sdsp";
3112 qcom, <<
3113 #addr 2128 #address-cells = <1>;
3114 #size 2129 #size-cells = <0>;
3115 2130
3116 compu 2131 compute-cb@1 {
3117 2132 compatible = "qcom,fastrpc-compute-cb";
3118 2133 reg = <1>;
3119 2134 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2135 };
3121 2136
3122 compu 2137 compute-cb@2 {
3123 2138 compatible = "qcom,fastrpc-compute-cb";
3124 2139 reg = <2>;
3125 2140 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2141 };
3127 2142
3128 compu 2143 compute-cb@3 {
3129 2144 compatible = "qcom,fastrpc-compute-cb";
3130 2145 reg = <3>;
3131 2146 iommus = <&apps_smmu 0x0543 0x0>;
3132 2147 /* note: shared-cb = <4> in downstream */
3133 }; 2148 };
3134 }; 2149 };
3135 }; 2150 };
3136 }; 2151 };
3137 2152
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 2153 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 2154 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 2155 reg = <0 0x08300000 0 0x10000>;
3777 2156
3778 interrupts-extended = !! 2157 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 2158 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 2159 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 2160 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 2161 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 2162 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 2163 "handover", "stop-ack";
3785 2164
3786 clocks = <&rpmhcc RPM 2165 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 2166 clock-names = "xo";
3788 2167
3789 power-domains = <&rpm !! 2168 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
>> 2169 <&rpmhpd SM8250_CX>;
>> 2170 power-domain-names = "load_state", "cx";
3790 2171
3791 memory-region = <&cds 2172 memory-region = <&cdsp_mem>;
3792 2173
3793 qcom,qmp = <&aoss_qmp <<
3794 <<
3795 qcom,smem-states = <& 2174 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 2175 qcom,smem-state-names = "stop";
3797 2176
3798 status = "disabled"; 2177 status = "disabled";
3799 2178
3800 glink-edge { 2179 glink-edge {
3801 interrupts-ex 2180 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2181 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2182 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2183 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2184 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2185
3807 label = "cdsp 2186 label = "cdsp";
3808 qcom,remote-p 2187 qcom,remote-pid = <5>;
3809 2188
3810 fastrpc { 2189 fastrpc {
3811 compa 2190 compatible = "qcom,fastrpc";
3812 qcom, 2191 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2192 label = "cdsp";
3814 qcom, <<
3815 #addr 2193 #address-cells = <1>;
3816 #size 2194 #size-cells = <0>;
3817 2195
3818 compu 2196 compute-cb@1 {
3819 2197 compatible = "qcom,fastrpc-compute-cb";
3820 2198 reg = <1>;
3821 2199 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2200 };
3823 2201
3824 compu 2202 compute-cb@2 {
3825 2203 compatible = "qcom,fastrpc-compute-cb";
3826 2204 reg = <2>;
3827 2205 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2206 };
3829 2207
3830 compu 2208 compute-cb@3 {
3831 2209 compatible = "qcom,fastrpc-compute-cb";
3832 2210 reg = <3>;
3833 2211 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2212 };
3835 2213
3836 compu 2214 compute-cb@4 {
3837 2215 compatible = "qcom,fastrpc-compute-cb";
3838 2216 reg = <4>;
3839 2217 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2218 };
3841 2219
3842 compu 2220 compute-cb@5 {
3843 2221 compatible = "qcom,fastrpc-compute-cb";
3844 2222 reg = <5>;
3845 2223 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2224 };
3847 2225
3848 compu 2226 compute-cb@6 {
3849 2227 compatible = "qcom,fastrpc-compute-cb";
3850 2228 reg = <6>;
3851 2229 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2230 };
3853 2231
3854 compu 2232 compute-cb@7 {
3855 2233 compatible = "qcom,fastrpc-compute-cb";
3856 2234 reg = <7>;
3857 2235 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2236 };
3859 2237
3860 compu 2238 compute-cb@8 {
3861 2239 compatible = "qcom,fastrpc-compute-cb";
3862 2240 reg = <8>;
3863 2241 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2242 };
3865 2243
3866 /* no 2244 /* note: secure cb9 in downstream */
3867 }; 2245 };
3868 }; 2246 };
3869 }; 2247 };
3870 2248
>> 2249 sound: sound {
>> 2250 };
>> 2251
3871 usb_1_hsphy: phy@88e3000 { 2252 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2253 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2254 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2255 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2256 status = "disabled";
3876 #phy-cells = <0>; 2257 #phy-cells = <0>;
3877 2258
3878 clocks = <&rpmhcc RPM 2259 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2260 clock-names = "ref";
3880 2261
3881 resets = <&gcc GCC_QU 2262 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2263 };
3883 2264
3884 usb_2_hsphy: phy@88e4000 { 2265 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2266 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2267 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2268 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2269 status = "disabled";
3889 #phy-cells = <0>; 2270 #phy-cells = <0>;
3890 2271
3891 clocks = <&rpmhcc RPM 2272 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2273 clock-names = "ref";
3893 2274
3894 resets = <&gcc GCC_QU 2275 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2276 };
3896 2277
3897 usb_1_qmpphy: phy@88e8000 { !! 2278 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2279 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2280 reg = <0 0x088e9000 0 0x200>,
>> 2281 <0 0x088e8000 0 0x40>,
>> 2282 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2283 status = "disabled";
>> 2284 #address-cells = <2>;
>> 2285 #size-cells = <2>;
>> 2286 ranges;
3901 2287
3902 clocks = <&gcc GCC_US 2288 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2289 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2290 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2291 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2292
3911 resets = <&gcc GCC_US 2293 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2294 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2295 reset-names = "phy", "common";
3914 2296
3915 #clock-cells = <1>; !! 2297 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2298 reg = <0 0x088e9200 0 0x200>,
3917 !! 2299 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2300 <0 0x088e9c00 0 0x400>,
3919 !! 2301 <0 0x088e9600 0 0x200>,
3920 ports { !! 2302 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2303 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2304 #clock-cells = <0>;
3923 !! 2305 #phy-cells = <0>;
3924 port@0 { !! 2306 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2307 clock-names = "pipe0";
3926 usb_1 !! 2308 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2309 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2310
3940 usb_1 !! 2311 dp_phy: dp-phy@88ea200 {
3941 }; !! 2312 reg = <0 0x088ea200 0 0x200>,
>> 2313 <0 0x088ea400 0 0x200>,
>> 2314 <0 0x088eaa00 0 0x200>,
>> 2315 <0 0x088ea600 0 0x200>,
>> 2316 <0 0x088ea800 0 0x200>;
>> 2317 #phy-cells = <0>;
>> 2318 #clock-cells = <1>;
3942 }; 2319 };
3943 }; 2320 };
3944 2321
3945 usb_2_qmpphy: phy@88eb000 { 2322 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2323 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2324 reg = <0 0x088eb000 0 0x200>;
>> 2325 status = "disabled";
>> 2326 #address-cells = <2>;
>> 2327 #size-cells = <2>;
>> 2328 ranges;
3948 2329
3949 clocks = <&gcc GCC_US 2330 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2331 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2332 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2333 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2334 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2335
3961 resets = <&gcc GCC_US !! 2336 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2337 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2338 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2339
3966 status = "disabled"; !! 2340 usb_2_ssphy: phy@88eb200 {
>> 2341 reg = <0 0x088eb200 0 0x200>,
>> 2342 <0 0x088eb400 0 0x200>,
>> 2343 <0 0x088eb800 0 0x800>;
>> 2344 #clock-cells = <0>;
>> 2345 #phy-cells = <0>;
>> 2346 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2347 clock-names = "pipe0";
>> 2348 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2349 };
3967 }; 2350 };
3968 2351
3969 sdhc_2: mmc@8804000 { !! 2352 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2353 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2354 reg = <0 0x08804000 0 0x1000>;
3972 2355
3973 interrupts = <GIC_SPI 2356 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2357 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2358 interrupt-names = "hc_irq", "pwr_irq";
3976 2359
3977 clocks = <&gcc GCC_SD 2360 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2361 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2362 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2363 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2364 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2365 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2366 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2367 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2368 operating-points-v2 = <&sdhc2_opp_table>;
3986 2369
3987 status = "disabled"; 2370 status = "disabled";
3988 2371
3989 sdhc2_opp_table: opp- !! 2372 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2373 compatible = "operating-points-v2";
3991 2374
3992 opp-19200000 2375 opp-19200000 {
3993 opp-h 2376 opp-hz = /bits/ 64 <19200000>;
3994 requi 2377 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2378 };
3996 2379
3997 opp-50000000 2380 opp-50000000 {
3998 opp-h 2381 opp-hz = /bits/ 64 <50000000>;
3999 requi 2382 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2383 };
4001 2384
4002 opp-100000000 2385 opp-100000000 {
4003 opp-h 2386 opp-hz = /bits/ 64 <100000000>;
4004 requi 2387 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2388 };
4006 2389
4007 opp-202000000 2390 opp-202000000 {
4008 opp-h 2391 opp-hz = /bits/ 64 <202000000>;
4009 requi 2392 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2393 };
4011 }; 2394 };
4012 }; 2395 };
4013 2396
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2397 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2398 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2399 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2400 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2401 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2402 };
4142 2403
4143 gem_noc: interconnect@9100000 2404 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2405 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2406 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2407 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2408 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2409 };
4149 2410
4150 npu_noc: interconnect@9990000 2411 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2412 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2413 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2414 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2415 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2416 };
4156 2417
4157 usb_1: usb@a6f8800 { 2418 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2419 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2420 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2421 status = "disabled";
4161 #address-cells = <2>; 2422 #address-cells = <2>;
4162 #size-cells = <2>; 2423 #size-cells = <2>;
4163 ranges; 2424 ranges;
4164 dma-ranges; 2425 dma-ranges;
4165 2426
4166 clocks = <&gcc GCC_CF 2427 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 2428 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 2429 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 2430 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2431 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 2432 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 2433 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 2434 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 2435
4179 assigned-clocks = <&g 2436 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 2437 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 2438 assigned-clock-rates = <19200000>, <200000000>;
4182 2439
4183 interrupts-extended = !! 2440 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 2441 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 2442 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 2443 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 2444 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 2445 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 2446
4194 power-domains = <&gcc 2447 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 2448
4197 resets = <&gcc GCC_US 2449 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 2450
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 2451 usb_1_dwc3: usb@a600000 {
4204 compatible = 2452 compatible = "snps,dwc3";
4205 reg = <0 0x0a 2453 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 2454 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 2455 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 2456 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 2457 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 2458 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 2459 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 2460 };
4233 }; 2461 };
4234 2462
4235 system-cache-controller@92000 2463 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 2464 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 2465 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 2466 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 2467 };
4243 2468
4244 usb_2: usb@a8f8800 { 2469 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 2470 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 2471 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 2472 status = "disabled";
4248 #address-cells = <2>; 2473 #address-cells = <2>;
4249 #size-cells = <2>; 2474 #size-cells = <2>;
4250 ranges; 2475 ranges;
4251 dma-ranges; 2476 dma-ranges;
4252 2477
4253 clocks = <&gcc GCC_CF 2478 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 2479 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 2480 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 2481 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2482 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 2483 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 2484 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 2485 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 2486
4266 assigned-clocks = <&g 2487 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 2488 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 2489 assigned-clock-rates = <19200000>, <200000000>;
4269 2490
4270 interrupts-extended = !! 2491 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 2492 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 2493 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 2494 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 2495 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 2496 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 2497
4281 power-domains = <&gcc 2498 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 2499
4284 resets = <&gcc GCC_US 2500 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 2501
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 2502 usb_2_dwc3: usb@a800000 {
4291 compatible = 2503 compatible = "snps,dwc3";
4292 reg = <0 0x0a 2504 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 2505 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 2506 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 2507 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 2508 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 2509 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 2510 phy-names = "usb2-phy", "usb3-phy";
4299 }; 2511 };
4300 }; 2512 };
4301 2513
4302 venus: video-codec@aa00000 { 2514 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 2515 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 2516 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 2517 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 2518 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 2519 <&videocc MVS0_GDSC>,
4308 <&rpm !! 2520 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 2521 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 2522 operating-points-v2 = <&venus_opp_table>;
4311 2523
4312 clocks = <&gcc GCC_VI 2524 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 2525 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 2526 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 2527 clock-names = "iface", "core", "vcodec0_core";
4316 2528
4317 interconnects = <&gem !! 2529 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 2530 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 2531 interconnect-names = "cpu-cfg", "video-mem";
4320 2532
4321 iommus = <&apps_smmu 2533 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 2534 memory-region = <&video_mem>;
4323 2535
4324 resets = <&gcc GCC_VI 2536 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 2537 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 2538 reset-names = "bus", "core";
4327 2539
4328 status = "disabled"; 2540 status = "disabled";
4329 2541
4330 video-decoder { 2542 video-decoder {
4331 compatible = 2543 compatible = "venus-decoder";
4332 }; 2544 };
4333 2545
4334 video-encoder { 2546 video-encoder {
4335 compatible = 2547 compatible = "venus-encoder";
4336 }; 2548 };
4337 2549
4338 venus_opp_table: opp- !! 2550 venus_opp_table: venus-opp-table {
4339 compatible = 2551 compatible = "operating-points-v2";
4340 2552
4341 opp-720000000 2553 opp-720000000 {
4342 opp-h 2554 opp-hz = /bits/ 64 <720000000>;
4343 requi 2555 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 2556 };
4345 2557
4346 opp-101400000 2558 opp-1014000000 {
4347 opp-h 2559 opp-hz = /bits/ 64 <1014000000>;
4348 requi 2560 required-opps = <&rpmhpd_opp_svs>;
4349 }; 2561 };
4350 2562
4351 opp-109800000 2563 opp-1098000000 {
4352 opp-h 2564 opp-hz = /bits/ 64 <1098000000>;
4353 requi 2565 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 2566 };
4355 2567
4356 opp-133200000 2568 opp-1332000000 {
4357 opp-h 2569 opp-hz = /bits/ 64 <1332000000>;
4358 requi 2570 required-opps = <&rpmhpd_opp_nom>;
4359 }; 2571 };
4360 }; 2572 };
4361 }; 2573 };
4362 2574
4363 videocc: clock-controller@abf 2575 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 2576 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 2577 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 2578 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 2579 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 2580 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 2581 mmcx-supply = <&mmcx_reg>;
4370 required-opps = <&rpm <<
4371 clock-names = "iface" 2582 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 2583 #clock-cells = <1>;
4373 #reset-cells = <1>; 2584 #reset-cells = <1>;
4374 #power-domain-cells = 2585 #power-domain-cells = <1>;
4375 }; 2586 };
4376 2587
4377 cci0: cci@ac4f000 { !! 2588 mdss: mdss@ae00000 {
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm 2589 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 2590 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 2591 reg-names = "mdss";
4661 2592
4662 interconnects = <&mms !! 2593 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 2594 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 2595 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 2596
4666 power-domains = <&dis 2597 power-domains = <&dispcc MDSS_GDSC>;
4667 2598
4668 clocks = <&dispcc DIS 2599 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 2600 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 2601 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 2602 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 2603 clock-names = "iface", "bus", "nrt_bus", "core";
4673 2604
>> 2605 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2606 assigned-clock-rates = <460000000>;
>> 2607
4674 interrupts = <GIC_SPI 2608 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 2609 interrupt-controller;
4676 #interrupt-cells = <1 2610 #interrupt-cells = <1>;
4677 2611
4678 iommus = <&apps_smmu 2612 iommus = <&apps_smmu 0x820 0x402>;
4679 2613
4680 status = "disabled"; 2614 status = "disabled";
4681 2615
4682 #address-cells = <2>; 2616 #address-cells = <2>;
4683 #size-cells = <2>; 2617 #size-cells = <2>;
4684 ranges; 2618 ranges;
4685 2619
4686 mdss_mdp: display-con !! 2620 mdss_mdp: mdp@ae01000 {
4687 compatible = 2621 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 2622 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 2623 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 2624 reg-names = "mdp", "vbif";
4691 2625
4692 clocks = <&di 2626 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 2627 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 2628 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 2629 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 2630 clock-names = "iface", "bus", "core", "vsync";
4697 2631
4698 assigned-cloc !! 2632 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 2633 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 2634 assigned-clock-rates = <460000000>,
>> 2635 <19200000>;
4700 2636
4701 operating-poi 2637 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 2638 power-domains = <&rpmhpd SM8250_MMCX>;
4703 2639
4704 interrupt-par 2640 interrupt-parent = <&mdss>;
4705 interrupts = !! 2641 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4706 2642
4707 ports { 2643 ports {
4708 #addr 2644 #address-cells = <1>;
4709 #size 2645 #size-cells = <0>;
4710 2646
4711 port@ 2647 port@0 {
4712 2648 reg = <0>;
4713 2649 dpu_intf1_out: endpoint {
4714 !! 2650 remote-endpoint = <&dsi0_in>;
4715 2651 };
4716 }; 2652 };
4717 2653
4718 port@ 2654 port@1 {
4719 2655 reg = <1>;
4720 2656 dpu_intf2_out: endpoint {
4721 !! 2657 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 2658 };
4731 }; 2659 };
4732 }; 2660 };
4733 2661
4734 mdp_opp_table !! 2662 mdp_opp_table: mdp-opp-table {
4735 compa 2663 compatible = "operating-points-v2";
4736 2664
4737 opp-2 2665 opp-200000000 {
4738 2666 opp-hz = /bits/ 64 <200000000>;
4739 2667 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 2668 };
4741 2669
4742 opp-3 2670 opp-300000000 {
4743 2671 opp-hz = /bits/ 64 <300000000>;
4744 2672 required-opps = <&rpmhpd_opp_svs>;
4745 }; 2673 };
4746 2674
4747 opp-3 2675 opp-345000000 {
4748 2676 opp-hz = /bits/ 64 <345000000>;
4749 2677 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 2678 };
4751 2679
4752 opp-4 2680 opp-460000000 {
4753 2681 opp-hz = /bits/ 64 <460000000>;
4754 2682 required-opps = <&rpmhpd_opp_nom>;
4755 }; 2683 };
4756 }; 2684 };
4757 }; 2685 };
4758 2686
4759 mdss_dp: displayport- !! 2687 dsi0: dsi@ae94000 {
4760 compatible = !! 2688 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 2689 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 2690 reg-names = "dsi_ctrl";
4843 2691
4844 interrupt-par 2692 interrupt-parent = <&mdss>;
4845 interrupts = !! 2693 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 2694
4847 clocks = <&di 2695 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 2696 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 2697 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 2698 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 2699 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 2700 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 2701 clock-names = "byte",
4854 2702 "byte_intf",
4855 2703 "pixel",
4856 2704 "core",
4857 2705 "iface",
4858 2706 "bus";
4859 2707
4860 assigned-cloc 2708 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 2709 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 2710
4863 operating-poi 2711 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 2712 power-domains = <&rpmhpd SM8250_MMCX>;
4865 2713
4866 phys = <&mdss !! 2714 phys = <&dsi0_phy>;
>> 2715 phy-names = "dsi";
4867 2716
4868 status = "dis 2717 status = "disabled";
4869 2718
4870 #address-cell 2719 #address-cells = <1>;
4871 #size-cells = 2720 #size-cells = <0>;
4872 2721
4873 ports { 2722 ports {
4874 #addr 2723 #address-cells = <1>;
4875 #size 2724 #size-cells = <0>;
4876 2725
4877 port@ 2726 port@0 {
4878 2727 reg = <0>;
4879 !! 2728 dsi0_in: endpoint {
4880 2729 remote-endpoint = <&dpu_intf1_out>;
4881 2730 };
4882 }; 2731 };
4883 2732
4884 port@ 2733 port@1 {
4885 2734 reg = <1>;
4886 !! 2735 dsi0_out: endpoint {
4887 2736 };
4888 }; 2737 };
4889 }; 2738 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 2739 };
4910 2740
4911 mdss_dsi0_phy: phy@ae !! 2741 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 2742 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 2743 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 2744 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 2745 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 2746 reg-names = "dsi_phy",
4917 " 2747 "dsi_phy_lane",
4918 " 2748 "dsi_pll";
4919 2749
4920 #clock-cells 2750 #clock-cells = <1>;
4921 #phy-cells = 2751 #phy-cells = <0>;
4922 2752
4923 clocks = <&di 2753 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 2754 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 2755 clock-names = "iface", "ref";
4926 2756
4927 status = "dis 2757 status = "disabled";
4928 }; 2758 };
4929 2759
4930 mdss_dsi1: dsi@ae9600 !! 2760 dsi1: dsi@ae96000 {
4931 compatible = !! 2761 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 2762 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 2763 reg-names = "dsi_ctrl";
4935 2764
4936 interrupt-par 2765 interrupt-parent = <&mdss>;
4937 interrupts = !! 2766 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 2767
4939 clocks = <&di 2768 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 2769 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 2770 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 2771 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 2772 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 2773 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 2774 clock-names = "byte",
4946 2775 "byte_intf",
4947 2776 "pixel",
4948 2777 "core",
4949 2778 "iface",
4950 2779 "bus";
4951 2780
4952 assigned-cloc 2781 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 2782 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 2783
4955 operating-poi 2784 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 2785 power-domains = <&rpmhpd SM8250_MMCX>;
4957 2786
4958 phys = <&mdss !! 2787 phys = <&dsi1_phy>;
>> 2788 phy-names = "dsi";
4959 2789
4960 status = "dis 2790 status = "disabled";
4961 2791
4962 #address-cell 2792 #address-cells = <1>;
4963 #size-cells = 2793 #size-cells = <0>;
4964 2794
4965 ports { 2795 ports {
4966 #addr 2796 #address-cells = <1>;
4967 #size 2797 #size-cells = <0>;
4968 2798
4969 port@ 2799 port@0 {
4970 2800 reg = <0>;
4971 !! 2801 dsi1_in: endpoint {
4972 2802 remote-endpoint = <&dpu_intf2_out>;
4973 2803 };
4974 }; 2804 };
4975 2805
4976 port@ 2806 port@1 {
4977 2807 reg = <1>;
4978 !! 2808 dsi1_out: endpoint {
4979 2809 };
4980 }; 2810 };
4981 }; 2811 };
4982 }; 2812 };
4983 2813
4984 mdss_dsi1_phy: phy@ae !! 2814 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 2815 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 2816 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 2817 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 2818 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 2819 reg-names = "dsi_phy",
4990 " 2820 "dsi_phy_lane",
4991 " 2821 "dsi_pll";
4992 2822
4993 #clock-cells 2823 #clock-cells = <1>;
4994 #phy-cells = 2824 #phy-cells = <0>;
4995 2825
4996 clocks = <&di 2826 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 2827 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 2828 clock-names = "iface", "ref";
4999 2829
5000 status = "dis 2830 status = "disabled";
>> 2831
>> 2832 dsi_opp_table: dsi-opp-table {
>> 2833 compatible = "operating-points-v2";
>> 2834
>> 2835 opp-187500000 {
>> 2836 opp-hz = /bits/ 64 <187500000>;
>> 2837 required-opps = <&rpmhpd_opp_low_svs>;
>> 2838 };
>> 2839
>> 2840 opp-300000000 {
>> 2841 opp-hz = /bits/ 64 <300000000>;
>> 2842 required-opps = <&rpmhpd_opp_svs>;
>> 2843 };
>> 2844
>> 2845 opp-358000000 {
>> 2846 opp-hz = /bits/ 64 <358000000>;
>> 2847 required-opps = <&rpmhpd_opp_svs_l1>;
>> 2848 };
>> 2849 };
5001 }; 2850 };
5002 }; 2851 };
5003 2852
5004 dispcc: clock-controller@af00 2853 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 2854 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 2855 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 2856 mmcx-supply = <&mmcx_reg>;
5008 required-opps = <&rpm <<
5009 clocks = <&rpmhcc RPM 2857 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 2858 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 2859 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 2860 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 2861 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 2862 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 2863 <&dp_phy 1>;
5016 clock-names = "bi_tcx 2864 clock-names = "bi_tcxo",
5017 "dsi0_p 2865 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 2866 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 2867 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 2868 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 2869 "dp_phy_pll_link_clk",
5022 "dp_phy 2870 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 2871 #clock-cells = <1>;
5024 #reset-cells = <1>; 2872 #reset-cells = <1>;
5025 #power-domain-cells = 2873 #power-domain-cells = <1>;
5026 }; 2874 };
5027 2875
5028 pdc: interrupt-controller@b22 2876 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 2877 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 2878 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 2879 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 2880 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 2881 #interrupt-cells = <2>;
5034 interrupt-parent = <& 2882 interrupt-parent = <&intc>;
5035 interrupt-controller; 2883 interrupt-controller;
5036 }; 2884 };
5037 2885
5038 tsens0: thermal-sensor@c26300 2886 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 2887 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 2888 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 2889 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 2890 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 2891 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 2892 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 2893 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 2894 #thermal-sensor-cells = <1>;
5047 }; 2895 };
5048 2896
5049 tsens1: thermal-sensor@c26500 2897 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 2898 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 2899 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 2900 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 2901 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 2902 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 2903 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 2904 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 2905 #thermal-sensor-cells = <1>;
5058 }; 2906 };
5059 2907
5060 aoss_qmp: power-management@c3 !! 2908 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm !! 2909 compatible = "qcom,sm8250-aoss-qmp";
5062 reg = <0 0x0c300000 0 !! 2910 reg = <0 0x0c300000 0 0x100000>;
5063 interrupts-extended = 2911 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 2912 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 2913 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 2914 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 2915 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 2916
5069 #clock-cells = <0>; 2917 #clock-cells = <0>;
5070 }; !! 2918 #power-domain-cells = <1>;
5071 <<
5072 sram@c3f0000 { <<
5073 compatible = "qcom,rp <<
5074 reg = <0 0x0c3f0000 0 <<
5075 }; 2919 };
5076 2920
5077 spmi_bus: spmi@c440000 { 2921 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 2922 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 2923 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 2924 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 2925 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 2926 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 2927 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 2928 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 2929 interrupt-names = "periph_irq";
5086 interrupts-extended = 2930 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 2931 qcom,ee = <0>;
5088 qcom,channel = <0>; 2932 qcom,channel = <0>;
5089 #address-cells = <2>; 2933 #address-cells = <2>;
5090 #size-cells = <0>; 2934 #size-cells = <0>;
5091 interrupt-controller; 2935 interrupt-controller;
5092 #interrupt-cells = <4 2936 #interrupt-cells = <4>;
5093 }; 2937 };
5094 2938
5095 tlmm: pinctrl@f100000 { 2939 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 2940 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 2941 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 2942 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 2943 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 2944 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 2945 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 2946 gpio-controller;
5103 #gpio-cells = <2>; 2947 #gpio-cells = <2>;
5104 interrupt-controller; 2948 interrupt-controller;
5105 #interrupt-cells = <2 2949 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 2950 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 2951 wakeup-parent = <&pdc>;
5108 2952
5109 cam2_default: cam2-de !! 2953 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 2954 sclk {
5111 pins !! 2955 pins = "gpio138";
5112 funct !! 2956 function = "mi2s0_sck";
5113 drive !! 2957 drive-strength = <8>;
5114 bias- 2958 bias-disable;
5115 }; 2959 };
5116 2960
5117 mclk-pins { !! 2961 ws {
5118 pins !! 2962 pins = "gpio141";
5119 funct !! 2963 function = "mi2s0_ws";
5120 drive !! 2964 drive-strength = <8>;
>> 2965 output-high;
>> 2966 };
>> 2967
>> 2968 data0 {
>> 2969 pins = "gpio139";
>> 2970 function = "mi2s0_data0";
>> 2971 drive-strength = <8>;
5121 bias- 2972 bias-disable;
>> 2973 output-high;
>> 2974 };
>> 2975
>> 2976 data1 {
>> 2977 pins = "gpio140";
>> 2978 function = "mi2s0_data1";
>> 2979 drive-strength = <8>;
>> 2980 output-high;
5122 }; 2981 };
5123 }; 2982 };
5124 2983
5125 cam2_suspend: cam2-su !! 2984 qup_i2c0_default: qup-i2c0-default {
5126 rst-pins { !! 2985 mux {
5127 pins !! 2986 pins = "gpio28", "gpio29";
5128 funct !! 2987 function = "qup0";
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; 2988 };
5133 2989
5134 mclk-pins { !! 2990 config {
5135 pins !! 2991 pins = "gpio28", "gpio29";
5136 funct <<
5137 drive 2992 drive-strength = <2>;
5138 bias- 2993 bias-disable;
5139 }; 2994 };
5140 }; 2995 };
5141 2996
5142 cci0_default: cci0-de !! 2997 qup_i2c1_default: qup-i2c1-default {
5143 cci0_i2c0_def !! 2998 pinmux {
5144 /* SD !! 2999 pins = "gpio4", "gpio5";
5145 pins !! 3000 function = "qup1";
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; 3001 };
5151 3002
5152 cci0_i2c1_def !! 3003 config {
5153 /* SD !! 3004 pins = "gpio4", "gpio5";
5154 pins !! 3005 drive-strength = <2>;
5155 funct !! 3006 bias-disable;
5156 <<
5157 bias- <<
5158 drive <<
5159 }; 3007 };
5160 }; 3008 };
5161 3009
5162 cci0_sleep: cci0-slee !! 3010 qup_i2c2_default: qup-i2c2-default {
5163 cci0_i2c0_sle !! 3011 mux {
5164 /* SD !! 3012 pins = "gpio115", "gpio116";
5165 pins !! 3013 function = "qup2";
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; 3014 };
5171 3015
5172 cci0_i2c1_sle !! 3016 config {
5173 /* SD !! 3017 pins = "gpio115", "gpio116";
5174 pins !! 3018 drive-strength = <2>;
5175 funct !! 3019 bias-disable;
5176 <<
5177 drive <<
5178 bias- <<
5179 }; 3020 };
5180 }; 3021 };
5181 3022
5182 cci1_default: cci1-de !! 3023 qup_i2c3_default: qup-i2c3-default {
5183 cci1_i2c0_def !! 3024 mux {
5184 /* SD !! 3025 pins = "gpio119", "gpio120";
5185 pins !! 3026 function = "qup3";
5186 funct !! 3027 };
5187 3028
5188 bias- !! 3029 config {
5189 drive !! 3030 pins = "gpio119", "gpio120";
>> 3031 drive-strength = <2>;
>> 3032 bias-disable;
5190 }; 3033 };
>> 3034 };
5191 3035
5192 cci1_i2c1_def !! 3036 qup_i2c4_default: qup-i2c4-default {
5193 /* SD !! 3037 mux {
5194 pins !! 3038 pins = "gpio8", "gpio9";
5195 funct !! 3039 function = "qup4";
>> 3040 };
5196 3041
5197 bias- !! 3042 config {
5198 drive !! 3043 pins = "gpio8", "gpio9";
>> 3044 drive-strength = <2>;
>> 3045 bias-disable;
5199 }; 3046 };
5200 }; 3047 };
5201 3048
5202 cci1_sleep: cci1-slee !! 3049 qup_i2c5_default: qup-i2c5-default {
5203 cci1_i2c0_sle !! 3050 mux {
5204 /* SD !! 3051 pins = "gpio12", "gpio13";
5205 pins !! 3052 function = "qup5";
5206 funct !! 3053 };
5207 3054
5208 bias- !! 3055 config {
5209 drive !! 3056 pins = "gpio12", "gpio13";
>> 3057 drive-strength = <2>;
>> 3058 bias-disable;
5210 }; 3059 };
>> 3060 };
5211 3061
5212 cci1_i2c1_sle !! 3062 qup_i2c6_default: qup-i2c6-default {
5213 /* SD !! 3063 mux {
5214 pins !! 3064 pins = "gpio16", "gpio17";
5215 funct !! 3065 function = "qup6";
>> 3066 };
5216 3067
5217 bias- !! 3068 config {
5218 drive !! 3069 pins = "gpio16", "gpio17";
>> 3070 drive-strength = <2>;
>> 3071 bias-disable;
5219 }; 3072 };
5220 }; 3073 };
5221 3074
5222 pri_mi2s_active: pri- !! 3075 qup_i2c7_default: qup-i2c7-default {
5223 sclk-pins { !! 3076 mux {
5224 pins !! 3077 pins = "gpio20", "gpio21";
5225 funct !! 3078 function = "qup7";
5226 drive !! 3079 };
>> 3080
>> 3081 config {
>> 3082 pins = "gpio20", "gpio21";
>> 3083 drive-strength = <2>;
5227 bias- 3084 bias-disable;
5228 }; 3085 };
>> 3086 };
5229 3087
5230 ws-pins { !! 3088 qup_i2c8_default: qup-i2c8-default {
5231 pins !! 3089 mux {
5232 funct !! 3090 pins = "gpio24", "gpio25";
5233 drive !! 3091 function = "qup8";
5234 outpu <<
5235 }; 3092 };
5236 3093
5237 data0-pins { !! 3094 config {
5238 pins !! 3095 pins = "gpio24", "gpio25";
5239 funct !! 3096 drive-strength = <2>;
5240 drive <<
5241 bias- 3097 bias-disable;
5242 outpu <<
5243 }; 3098 };
>> 3099 };
5244 3100
5245 data1-pins { !! 3101 qup_i2c9_default: qup-i2c9-default {
5246 pins !! 3102 mux {
5247 funct !! 3103 pins = "gpio125", "gpio126";
5248 drive !! 3104 function = "qup9";
5249 outpu <<
5250 }; 3105 };
5251 }; <<
5252 3106
5253 qup_i2c0_default: qup !! 3107 config {
5254 pins = "gpio2 !! 3108 pins = "gpio125", "gpio126";
5255 function = "q !! 3109 drive-strength = <2>;
5256 drive-strengt !! 3110 bias-disable;
5257 bias-disable; !! 3111 };
5258 }; 3112 };
5259 3113
5260 qup_i2c1_default: qup !! 3114 qup_i2c10_default: qup-i2c10-default {
5261 pins = "gpio4 !! 3115 mux {
5262 function = "q !! 3116 pins = "gpio129", "gpio130";
5263 drive-strengt !! 3117 function = "qup10";
5264 bias-disable; !! 3118 };
5265 }; <<
5266 3119
5267 qup_i2c2_default: qup !! 3120 config {
5268 pins = "gpio1 !! 3121 pins = "gpio129", "gpio130";
5269 function = "q !! 3122 drive-strength = <2>;
5270 drive-strengt !! 3123 bias-disable;
5271 bias-disable; !! 3124 };
5272 }; 3125 };
5273 3126
5274 qup_i2c3_default: qup !! 3127 qup_i2c11_default: qup-i2c11-default {
5275 pins = "gpio1 !! 3128 mux {
5276 function = "q !! 3129 pins = "gpio60", "gpio61";
5277 drive-strengt !! 3130 function = "qup11";
5278 bias-disable; !! 3131 };
5279 }; <<
5280 3132
5281 qup_i2c4_default: qup !! 3133 config {
5282 pins = "gpio8 !! 3134 pins = "gpio60", "gpio61";
5283 function = "q !! 3135 drive-strength = <2>;
5284 drive-strengt !! 3136 bias-disable;
5285 bias-disable; !! 3137 };
5286 }; 3138 };
5287 3139
5288 qup_i2c5_default: qup !! 3140 qup_i2c12_default: qup-i2c12-default {
5289 pins = "gpio1 !! 3141 mux {
5290 function = "q !! 3142 pins = "gpio32", "gpio33";
5291 drive-strengt !! 3143 function = "qup12";
5292 bias-disable; !! 3144 };
5293 }; <<
5294 3145
5295 qup_i2c6_default: qup !! 3146 config {
5296 pins = "gpio1 !! 3147 pins = "gpio32", "gpio33";
5297 function = "q !! 3148 drive-strength = <2>;
5298 drive-strengt !! 3149 bias-disable;
5299 bias-disable; !! 3150 };
5300 }; 3151 };
5301 3152
5302 qup_i2c7_default: qup !! 3153 qup_i2c13_default: qup-i2c13-default {
5303 pins = "gpio2 !! 3154 mux {
5304 function = "q !! 3155 pins = "gpio36", "gpio37";
5305 drive-strengt !! 3156 function = "qup13";
5306 bias-disable; !! 3157 };
5307 }; <<
5308 3158
5309 qup_i2c8_default: qup !! 3159 config {
5310 pins = "gpio2 !! 3160 pins = "gpio36", "gpio37";
5311 function = "q !! 3161 drive-strength = <2>;
5312 drive-strengt !! 3162 bias-disable;
5313 bias-disable; !! 3163 };
5314 }; 3164 };
5315 3165
5316 qup_i2c9_default: qup !! 3166 qup_i2c14_default: qup-i2c14-default {
5317 pins = "gpio1 !! 3167 mux {
5318 function = "q !! 3168 pins = "gpio40", "gpio41";
5319 drive-strengt !! 3169 function = "qup14";
5320 bias-disable; !! 3170 };
5321 }; <<
5322 3171
5323 qup_i2c10_default: qu !! 3172 config {
5324 pins = "gpio1 !! 3173 pins = "gpio40", "gpio41";
5325 function = "q !! 3174 drive-strength = <2>;
5326 drive-strengt !! 3175 bias-disable;
5327 bias-disable; !! 3176 };
5328 }; 3177 };
5329 3178
5330 qup_i2c11_default: qu !! 3179 qup_i2c15_default: qup-i2c15-default {
5331 pins = "gpio6 !! 3180 mux {
5332 function = "q !! 3181 pins = "gpio44", "gpio45";
5333 drive-strengt !! 3182 function = "qup15";
5334 bias-disable; !! 3183 };
5335 }; <<
5336 3184
5337 qup_i2c12_default: qu !! 3185 config {
5338 pins = "gpio3 !! 3186 pins = "gpio44", "gpio45";
5339 function = "q !! 3187 drive-strength = <2>;
5340 drive-strengt !! 3188 bias-disable;
5341 bias-disable; !! 3189 };
5342 }; 3190 };
5343 3191
5344 qup_i2c13_default: qu !! 3192 qup_i2c16_default: qup-i2c16-default {
5345 pins = "gpio3 !! 3193 mux {
5346 function = "q !! 3194 pins = "gpio48", "gpio49";
5347 drive-strengt !! 3195 function = "qup16";
5348 bias-disable; !! 3196 };
5349 }; <<
5350 3197
5351 qup_i2c14_default: qu !! 3198 config {
5352 pins = "gpio4 !! 3199 pins = "gpio48", "gpio49";
5353 function = "q !! 3200 drive-strength = <2>;
5354 drive-strengt !! 3201 bias-disable;
5355 bias-disable; !! 3202 };
5356 }; 3203 };
5357 3204
5358 qup_i2c15_default: qu !! 3205 qup_i2c17_default: qup-i2c17-default {
5359 pins = "gpio4 !! 3206 mux {
5360 function = "q !! 3207 pins = "gpio52", "gpio53";
5361 drive-strengt !! 3208 function = "qup17";
5362 bias-disable; !! 3209 };
5363 }; <<
5364 3210
5365 qup_i2c16_default: qu !! 3211 config {
5366 pins = "gpio4 !! 3212 pins = "gpio52", "gpio53";
5367 function = "q !! 3213 drive-strength = <2>;
5368 drive-strengt !! 3214 bias-disable;
5369 bias-disable; !! 3215 };
5370 }; 3216 };
5371 3217
5372 qup_i2c17_default: qu !! 3218 qup_i2c18_default: qup-i2c18-default {
5373 pins = "gpio5 !! 3219 mux {
5374 function = "q !! 3220 pins = "gpio56", "gpio57";
5375 drive-strengt !! 3221 function = "qup18";
5376 bias-disable; !! 3222 };
5377 }; <<
5378 3223
5379 qup_i2c18_default: qu !! 3224 config {
5380 pins = "gpio5 !! 3225 pins = "gpio56", "gpio57";
5381 function = "q !! 3226 drive-strength = <2>;
5382 drive-strengt !! 3227 bias-disable;
5383 bias-disable; !! 3228 };
5384 }; 3229 };
5385 3230
5386 qup_i2c19_default: qu !! 3231 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 3232 mux {
5388 function = "q !! 3233 pins = "gpio0", "gpio1";
5389 drive-strengt !! 3234 function = "qup19";
5390 bias-disable; !! 3235 };
>> 3236
>> 3237 config {
>> 3238 pins = "gpio0", "gpio1";
>> 3239 drive-strength = <2>;
>> 3240 bias-disable;
>> 3241 };
5391 }; 3242 };
5392 3243
5393 qup_spi0_cs: qup-spi0 !! 3244 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 3245 pins = "gpio31";
5395 function = "q 3246 function = "qup0";
5396 }; 3247 };
5397 3248
5398 qup_spi0_cs_gpio: qup !! 3249 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 3250 pins = "gpio31";
5400 function = "g 3251 function = "gpio";
5401 }; 3252 };
5402 3253
5403 qup_spi0_data_clk: qu !! 3254 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 3255 pins = "gpio28", "gpio29",
5405 "gpio3 3256 "gpio30";
5406 function = "q 3257 function = "qup0";
5407 }; 3258 };
5408 3259
5409 qup_spi1_cs: qup-spi1 !! 3260 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 3261 pins = "gpio7";
5411 function = "q 3262 function = "qup1";
5412 }; 3263 };
5413 3264
5414 qup_spi1_cs_gpio: qup !! 3265 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 3266 pins = "gpio7";
5416 function = "g 3267 function = "gpio";
5417 }; 3268 };
5418 3269
5419 qup_spi1_data_clk: qu !! 3270 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 3271 pins = "gpio4", "gpio5",
5421 "gpio6 3272 "gpio6";
5422 function = "q 3273 function = "qup1";
5423 }; 3274 };
5424 3275
5425 qup_spi2_cs: qup-spi2 !! 3276 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 3277 pins = "gpio118";
5427 function = "q 3278 function = "qup2";
5428 }; 3279 };
5429 3280
5430 qup_spi2_cs_gpio: qup !! 3281 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 3282 pins = "gpio118";
5432 function = "g 3283 function = "gpio";
5433 }; 3284 };
5434 3285
5435 qup_spi2_data_clk: qu !! 3286 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 3287 pins = "gpio115", "gpio116",
5437 "gpio1 3288 "gpio117";
5438 function = "q 3289 function = "qup2";
5439 }; 3290 };
5440 3291
5441 qup_spi3_cs: qup-spi3 !! 3292 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 3293 pins = "gpio122";
5443 function = "q 3294 function = "qup3";
5444 }; 3295 };
5445 3296
5446 qup_spi3_cs_gpio: qup !! 3297 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 3298 pins = "gpio122";
5448 function = "g 3299 function = "gpio";
5449 }; 3300 };
5450 3301
5451 qup_spi3_data_clk: qu !! 3302 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 3303 pins = "gpio119", "gpio120",
5453 "gpio1 3304 "gpio121";
5454 function = "q 3305 function = "qup3";
5455 }; 3306 };
5456 3307
5457 qup_spi4_cs: qup-spi4 !! 3308 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 3309 pins = "gpio11";
5459 function = "q 3310 function = "qup4";
5460 }; 3311 };
5461 3312
5462 qup_spi4_cs_gpio: qup !! 3313 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 3314 pins = "gpio11";
5464 function = "g 3315 function = "gpio";
5465 }; 3316 };
5466 3317
5467 qup_spi4_data_clk: qu !! 3318 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 3319 pins = "gpio8", "gpio9",
5469 "gpio1 3320 "gpio10";
5470 function = "q 3321 function = "qup4";
5471 }; 3322 };
5472 3323
5473 qup_spi5_cs: qup-spi5 !! 3324 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 3325 pins = "gpio15";
5475 function = "q 3326 function = "qup5";
5476 }; 3327 };
5477 3328
5478 qup_spi5_cs_gpio: qup !! 3329 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 3330 pins = "gpio15";
5480 function = "g 3331 function = "gpio";
5481 }; 3332 };
5482 3333
5483 qup_spi5_data_clk: qu !! 3334 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 3335 pins = "gpio12", "gpio13",
5485 "gpio1 3336 "gpio14";
5486 function = "q 3337 function = "qup5";
5487 }; 3338 };
5488 3339
5489 qup_spi6_cs: qup-spi6 !! 3340 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 3341 pins = "gpio19";
5491 function = "q 3342 function = "qup6";
5492 }; 3343 };
5493 3344
5494 qup_spi6_cs_gpio: qup !! 3345 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 3346 pins = "gpio19";
5496 function = "g 3347 function = "gpio";
5497 }; 3348 };
5498 3349
5499 qup_spi6_data_clk: qu !! 3350 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 3351 pins = "gpio16", "gpio17",
5501 "gpio1 3352 "gpio18";
5502 function = "q 3353 function = "qup6";
5503 }; 3354 };
5504 3355
5505 qup_spi7_cs: qup-spi7 !! 3356 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 3357 pins = "gpio23";
5507 function = "q 3358 function = "qup7";
5508 }; 3359 };
5509 3360
5510 qup_spi7_cs_gpio: qup !! 3361 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 3362 pins = "gpio23";
5512 function = "g 3363 function = "gpio";
5513 }; 3364 };
5514 3365
5515 qup_spi7_data_clk: qu !! 3366 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 3367 pins = "gpio20", "gpio21",
5517 "gpio2 3368 "gpio22";
5518 function = "q 3369 function = "qup7";
5519 }; 3370 };
5520 3371
5521 qup_spi8_cs: qup-spi8 !! 3372 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 3373 pins = "gpio27";
5523 function = "q 3374 function = "qup8";
5524 }; 3375 };
5525 3376
5526 qup_spi8_cs_gpio: qup !! 3377 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 3378 pins = "gpio27";
5528 function = "g 3379 function = "gpio";
5529 }; 3380 };
5530 3381
5531 qup_spi8_data_clk: qu !! 3382 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 3383 pins = "gpio24", "gpio25",
5533 "gpio2 3384 "gpio26";
5534 function = "q 3385 function = "qup8";
5535 }; 3386 };
5536 3387
5537 qup_spi9_cs: qup-spi9 !! 3388 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 3389 pins = "gpio128";
5539 function = "q 3390 function = "qup9";
5540 }; 3391 };
5541 3392
5542 qup_spi9_cs_gpio: qup !! 3393 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 3394 pins = "gpio128";
5544 function = "g 3395 function = "gpio";
5545 }; 3396 };
5546 3397
5547 qup_spi9_data_clk: qu !! 3398 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 3399 pins = "gpio125", "gpio126",
5549 "gpio1 3400 "gpio127";
5550 function = "q 3401 function = "qup9";
5551 }; 3402 };
5552 3403
5553 qup_spi10_cs: qup-spi !! 3404 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 3405 pins = "gpio132";
5555 function = "q 3406 function = "qup10";
5556 }; 3407 };
5557 3408
5558 qup_spi10_cs_gpio: qu !! 3409 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 3410 pins = "gpio132";
5560 function = "g 3411 function = "gpio";
5561 }; 3412 };
5562 3413
5563 qup_spi10_data_clk: q !! 3414 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 3415 pins = "gpio129", "gpio130",
5565 "gpio1 3416 "gpio131";
5566 function = "q 3417 function = "qup10";
5567 }; 3418 };
5568 3419
5569 qup_spi11_cs: qup-spi !! 3420 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 3421 pins = "gpio63";
5571 function = "q 3422 function = "qup11";
5572 }; 3423 };
5573 3424
5574 qup_spi11_cs_gpio: qu !! 3425 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 3426 pins = "gpio63";
5576 function = "g 3427 function = "gpio";
5577 }; 3428 };
5578 3429
5579 qup_spi11_data_clk: q !! 3430 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 3431 pins = "gpio60", "gpio61",
5581 "gpio6 3432 "gpio62";
5582 function = "q 3433 function = "qup11";
5583 }; 3434 };
5584 3435
5585 qup_spi12_cs: qup-spi !! 3436 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 3437 pins = "gpio35";
5587 function = "q 3438 function = "qup12";
5588 }; 3439 };
5589 3440
5590 qup_spi12_cs_gpio: qu !! 3441 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 3442 pins = "gpio35";
5592 function = "g 3443 function = "gpio";
5593 }; 3444 };
5594 3445
5595 qup_spi12_data_clk: q !! 3446 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 3447 pins = "gpio32", "gpio33",
5597 "gpio3 3448 "gpio34";
5598 function = "q 3449 function = "qup12";
5599 }; 3450 };
5600 3451
5601 qup_spi13_cs: qup-spi !! 3452 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 3453 pins = "gpio39";
5603 function = "q 3454 function = "qup13";
5604 }; 3455 };
5605 3456
5606 qup_spi13_cs_gpio: qu !! 3457 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 3458 pins = "gpio39";
5608 function = "g 3459 function = "gpio";
5609 }; 3460 };
5610 3461
5611 qup_spi13_data_clk: q !! 3462 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 3463 pins = "gpio36", "gpio37",
5613 "gpio3 3464 "gpio38";
5614 function = "q 3465 function = "qup13";
5615 }; 3466 };
5616 3467
5617 qup_spi14_cs: qup-spi !! 3468 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 3469 pins = "gpio43";
5619 function = "q 3470 function = "qup14";
5620 }; 3471 };
5621 3472
5622 qup_spi14_cs_gpio: qu !! 3473 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 3474 pins = "gpio43";
5624 function = "g 3475 function = "gpio";
5625 }; 3476 };
5626 3477
5627 qup_spi14_data_clk: q !! 3478 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 3479 pins = "gpio40", "gpio41",
5629 "gpio4 3480 "gpio42";
5630 function = "q 3481 function = "qup14";
5631 }; 3482 };
5632 3483
5633 qup_spi15_cs: qup-spi !! 3484 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 3485 pins = "gpio47";
5635 function = "q 3486 function = "qup15";
5636 }; 3487 };
5637 3488
5638 qup_spi15_cs_gpio: qu !! 3489 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 3490 pins = "gpio47";
5640 function = "g 3491 function = "gpio";
5641 }; 3492 };
5642 3493
5643 qup_spi15_data_clk: q !! 3494 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 3495 pins = "gpio44", "gpio45",
5645 "gpio4 3496 "gpio46";
5646 function = "q 3497 function = "qup15";
5647 }; 3498 };
5648 3499
5649 qup_spi16_cs: qup-spi !! 3500 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 3501 pins = "gpio51";
5651 function = "q 3502 function = "qup16";
5652 }; 3503 };
5653 3504
5654 qup_spi16_cs_gpio: qu !! 3505 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 3506 pins = "gpio51";
5656 function = "g 3507 function = "gpio";
5657 }; 3508 };
5658 3509
5659 qup_spi16_data_clk: q !! 3510 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 3511 pins = "gpio48", "gpio49",
5661 "gpio5 3512 "gpio50";
5662 function = "q 3513 function = "qup16";
5663 }; 3514 };
5664 3515
5665 qup_spi17_cs: qup-spi !! 3516 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 3517 pins = "gpio55";
5667 function = "q 3518 function = "qup17";
5668 }; 3519 };
5669 3520
5670 qup_spi17_cs_gpio: qu !! 3521 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 3522 pins = "gpio55";
5672 function = "g 3523 function = "gpio";
5673 }; 3524 };
5674 3525
5675 qup_spi17_data_clk: q !! 3526 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 3527 pins = "gpio52", "gpio53",
5677 "gpio5 3528 "gpio54";
5678 function = "q 3529 function = "qup17";
5679 }; 3530 };
5680 3531
5681 qup_spi18_cs: qup-spi !! 3532 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 3533 pins = "gpio59";
5683 function = "q 3534 function = "qup18";
5684 }; 3535 };
5685 3536
5686 qup_spi18_cs_gpio: qu !! 3537 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 3538 pins = "gpio59";
5688 function = "g 3539 function = "gpio";
5689 }; 3540 };
5690 3541
5691 qup_spi18_data_clk: q !! 3542 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 3543 pins = "gpio56", "gpio57",
5693 "gpio5 3544 "gpio58";
5694 function = "q 3545 function = "qup18";
5695 }; 3546 };
5696 3547
5697 qup_spi19_cs: qup-spi !! 3548 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 3549 pins = "gpio3";
5699 function = "q 3550 function = "qup19";
5700 }; 3551 };
5701 3552
5702 qup_spi19_cs_gpio: qu !! 3553 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 3554 pins = "gpio3";
5704 function = "g 3555 function = "gpio";
5705 }; 3556 };
5706 3557
5707 qup_spi19_data_clk: q !! 3558 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 3559 pins = "gpio0", "gpio1",
5709 "gpio2 3560 "gpio2";
5710 function = "q 3561 function = "qup19";
5711 }; 3562 };
5712 3563
5713 qup_uart2_default: qu !! 3564 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 3565 mux {
5715 function = "q !! 3566 pins = "gpio117", "gpio118";
>> 3567 function = "qup2";
>> 3568 };
5716 }; 3569 };
5717 3570
5718 qup_uart6_default: qu !! 3571 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 3572 mux {
5720 function = "q !! 3573 pins = "gpio16", "gpio17",
>> 3574 "gpio18", "gpio19";
>> 3575 function = "qup6";
>> 3576 };
5721 }; 3577 };
5722 3578
5723 qup_uart12_default: q !! 3579 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 3580 mux {
5725 function = "q !! 3581 pins = "gpio34", "gpio35";
>> 3582 function = "qup12";
>> 3583 };
5726 }; 3584 };
5727 3585
5728 qup_uart17_default: q !! 3586 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 3587 mux {
5730 function = "q !! 3588 pins = "gpio52", "gpio53",
>> 3589 "gpio54", "gpio55";
>> 3590 function = "qup17";
>> 3591 };
5731 }; 3592 };
5732 3593
5733 qup_uart18_default: q !! 3594 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 3595 mux {
5735 function = "q !! 3596 pins = "gpio58", "gpio59";
>> 3597 function = "qup18";
>> 3598 };
5736 }; 3599 };
5737 3600
5738 tert_mi2s_active: ter !! 3601 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 3602 sck {
5740 pins 3603 pins = "gpio133";
5741 funct 3604 function = "mi2s2_sck";
5742 drive 3605 drive-strength = <8>;
5743 bias- 3606 bias-disable;
5744 }; 3607 };
5745 3608
5746 data0-pins { !! 3609 data0 {
5747 pins 3610 pins = "gpio134";
5748 funct 3611 function = "mi2s2_data0";
5749 drive 3612 drive-strength = <8>;
5750 bias- 3613 bias-disable;
5751 outpu 3614 output-high;
5752 }; 3615 };
5753 3616
5754 ws-pins { !! 3617 ws {
5755 pins 3618 pins = "gpio135";
5756 funct 3619 function = "mi2s2_ws";
5757 drive 3620 drive-strength = <8>;
5758 outpu 3621 output-high;
5759 }; 3622 };
5760 }; 3623 };
5761 3624
5762 sdc2_sleep_state: sdc !! 3625 sdc2_sleep_state: sdc2-sleep {
5763 clk-pins { !! 3626 clk {
5764 pins 3627 pins = "sdc2_clk";
5765 drive 3628 drive-strength = <2>;
5766 bias- 3629 bias-disable;
5767 }; 3630 };
5768 3631
5769 cmd-pins { !! 3632 cmd {
5770 pins 3633 pins = "sdc2_cmd";
5771 drive 3634 drive-strength = <2>;
5772 bias- 3635 bias-pull-up;
5773 }; 3636 };
5774 3637
5775 data-pins { !! 3638 data {
5776 pins 3639 pins = "sdc2_data";
5777 drive 3640 drive-strength = <2>;
5778 bias- 3641 bias-pull-up;
5779 }; 3642 };
5780 }; 3643 };
5781 3644
5782 pcie0_default_state: !! 3645 pcie0_default_state: pcie0-default {
5783 perst-pins { !! 3646 perst {
5784 pins 3647 pins = "gpio79";
5785 funct 3648 function = "gpio";
5786 drive 3649 drive-strength = <2>;
5787 bias- 3650 bias-pull-down;
5788 }; 3651 };
5789 3652
5790 clkreq-pins { !! 3653 clkreq {
5791 pins 3654 pins = "gpio80";
5792 funct 3655 function = "pci_e0";
5793 drive 3656 drive-strength = <2>;
5794 bias- 3657 bias-pull-up;
5795 }; 3658 };
5796 3659
5797 wake-pins { !! 3660 wake {
5798 pins 3661 pins = "gpio81";
5799 funct 3662 function = "gpio";
5800 drive 3663 drive-strength = <2>;
5801 bias- 3664 bias-pull-up;
5802 }; 3665 };
5803 }; 3666 };
5804 3667
5805 pcie1_default_state: !! 3668 pcie1_default_state: pcie1-default {
5806 perst-pins { !! 3669 perst {
5807 pins 3670 pins = "gpio82";
5808 funct 3671 function = "gpio";
5809 drive 3672 drive-strength = <2>;
5810 bias- 3673 bias-pull-down;
5811 }; 3674 };
5812 3675
5813 clkreq-pins { !! 3676 clkreq {
5814 pins 3677 pins = "gpio83";
5815 funct 3678 function = "pci_e1";
5816 drive 3679 drive-strength = <2>;
5817 bias- 3680 bias-pull-up;
5818 }; 3681 };
5819 3682
5820 wake-pins { !! 3683 wake {
5821 pins 3684 pins = "gpio84";
5822 funct 3685 function = "gpio";
5823 drive 3686 drive-strength = <2>;
5824 bias- 3687 bias-pull-up;
5825 }; 3688 };
5826 }; 3689 };
5827 3690
5828 pcie2_default_state: !! 3691 pcie2_default_state: pcie2-default {
5829 perst-pins { !! 3692 perst {
5830 pins 3693 pins = "gpio85";
5831 funct 3694 function = "gpio";
5832 drive 3695 drive-strength = <2>;
5833 bias- 3696 bias-pull-down;
5834 }; 3697 };
5835 3698
5836 clkreq-pins { !! 3699 clkreq {
5837 pins 3700 pins = "gpio86";
5838 funct 3701 function = "pci_e2";
5839 drive 3702 drive-strength = <2>;
5840 bias- 3703 bias-pull-up;
5841 }; 3704 };
5842 3705
5843 wake-pins { !! 3706 wake {
5844 pins 3707 pins = "gpio87";
5845 funct 3708 function = "gpio";
5846 drive 3709 drive-strength = <2>;
5847 bias- 3710 bias-pull-up;
5848 }; 3711 };
5849 }; 3712 };
5850 }; 3713 };
5851 3714
5852 apps_smmu: iommu@15000000 { 3715 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 3716 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 3717 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 3718 #iommu-cells = <2>;
5856 #global-interrupts = 3719 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 3720 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 3721 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 3722 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 3723 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 3724 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 3725 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 3726 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 3727 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 3728 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 3729 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 3730 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 3731 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 3732 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 3733 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 3734 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 3735 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 3736 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 3737 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 3738 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 3739 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 3740 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 3741 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 3742 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 3743 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 3744 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 3745 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 3746 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 3747 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 3748 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 3749 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 3750 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 3751 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 3752 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 3753 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 3754 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 3755 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 3756 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 3757 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 3758 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 3759 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 3760 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 3761 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 3762 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 3763 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 3764 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 3765 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 3766 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 3767 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 3768 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 3769 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 3770 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 3771 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 3772 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 3773 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 3774 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 3775 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 3776 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 3777 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 3778 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 3779 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 3780 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 3781 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 3782 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 3783 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 3784 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 3785 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 3786 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 3787 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 3788 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 3789 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 3790 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 3791 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 3792 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 3793 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 3794 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 3795 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 3796 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 3797 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 3798 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 3799 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 3800 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 3801 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 3802 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 3803 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 3804 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 3805 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 3806 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 3807 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 3808 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 3809 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 3810 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 3811 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 3812 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 3813 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 3814 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 3815 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 3816 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 3817 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 3818 };
5957 3819
5958 adsp: remoteproc@17300000 { 3820 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 3821 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 3822 reg = <0 0x17300000 0 0x100>;
5961 3823
5962 interrupts-extended = !! 3824 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 3825 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 3826 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 3827 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 3828 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 3829 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 3830 "handover", "stop-ack";
5969 3831
5970 clocks = <&rpmhcc RPM 3832 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 3833 clock-names = "xo";
5972 3834
5973 power-domains = <&rpm !! 3835 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
5974 <&rpm !! 3836 <&rpmhpd SM8250_LCX>,
5975 power-domain-names = !! 3837 <&rpmhpd SM8250_LMX>;
>> 3838 power-domain-names = "load_state", "lcx", "lmx";
5976 3839
5977 memory-region = <&ads 3840 memory-region = <&adsp_mem>;
5978 3841
5979 qcom,qmp = <&aoss_qmp <<
5980 <<
5981 qcom,smem-states = <& 3842 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 3843 qcom,smem-state-names = "stop";
5983 3844
5984 status = "disabled"; 3845 status = "disabled";
5985 3846
5986 glink-edge { 3847 glink-edge {
5987 interrupts-ex 3848 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 3849 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 3850 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 3851 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 3852 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 3853
5993 label = "lpas 3854 label = "lpass";
5994 qcom,remote-p 3855 qcom,remote-pid = <2>;
5995 3856
5996 apr { 3857 apr {
5997 compa 3858 compatible = "qcom,apr-v2";
5998 qcom, 3859 qcom,glink-channels = "apr_audio_svc";
5999 qcom, !! 3860 qcom,apr-domain = <APR_DOMAIN_ADSP>;
6000 #addr 3861 #address-cells = <1>;
6001 #size 3862 #size-cells = <0>;
6002 3863
6003 servi !! 3864 apr-service@3 {
6004 3865 reg = <APR_SVC_ADSP_CORE>;
6005 3866 compatible = "qcom,q6core";
6006 3867 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 3868 };
6008 3869
6009 q6afe !! 3870 q6afe: apr-service@4 {
6010 3871 compatible = "qcom,q6afe";
6011 3872 reg = <APR_SVC_AFE>;
6012 3873 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 3874 q6afedai: dais {
6014 3875 compatible = "qcom,q6afe-dais";
6015 3876 #address-cells = <1>;
6016 3877 #size-cells = <0>;
6017 3878 #sound-dai-cells = <1>;
6018 3879 };
6019 3880
6020 !! 3881 q6afecc: cc {
6021 3882 compatible = "qcom,q6afe-clocks";
6022 3883 #clock-cells = <2>;
6023 3884 };
6024 }; 3885 };
6025 3886
6026 q6asm !! 3887 q6asm: apr-service@7 {
6027 3888 compatible = "qcom,q6asm";
6028 3889 reg = <APR_SVC_ASM>;
6029 3890 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 3891 q6asmdai: dais {
6031 3892 compatible = "qcom,q6asm-dais";
6032 3893 #address-cells = <1>;
6033 3894 #size-cells = <0>;
6034 3895 #sound-dai-cells = <1>;
6035 3896 iommus = <&apps_smmu 0x1801 0x0>;
6036 3897 };
6037 }; 3898 };
6038 3899
6039 q6adm !! 3900 q6adm: apr-service@8 {
6040 3901 compatible = "qcom,q6adm";
6041 3902 reg = <APR_SVC_ADM>;
6042 3903 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 3904 q6routing: routing {
6044 3905 compatible = "qcom,q6adm-routing";
6045 3906 #sound-dai-cells = <0>;
6046 3907 };
6047 }; 3908 };
6048 }; 3909 };
6049 3910
6050 fastrpc { 3911 fastrpc {
6051 compa 3912 compatible = "qcom,fastrpc";
6052 qcom, 3913 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 3914 label = "adsp";
6054 qcom, <<
6055 #addr 3915 #address-cells = <1>;
6056 #size 3916 #size-cells = <0>;
6057 3917
6058 compu 3918 compute-cb@3 {
6059 3919 compatible = "qcom,fastrpc-compute-cb";
6060 3920 reg = <3>;
6061 3921 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 3922 };
6063 3923
6064 compu 3924 compute-cb@4 {
6065 3925 compatible = "qcom,fastrpc-compute-cb";
6066 3926 reg = <4>;
6067 3927 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 3928 };
6069 3929
6070 compu 3930 compute-cb@5 {
6071 3931 compatible = "qcom,fastrpc-compute-cb";
6072 3932 reg = <5>;
6073 3933 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 3934 };
6075 }; 3935 };
6076 }; 3936 };
6077 }; 3937 };
6078 3938
6079 intc: interrupt-controller@17 3939 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 3940 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 3941 #interrupt-cells = <3>;
6082 interrupt-controller; 3942 interrupt-controller;
6083 reg = <0x0 0x17a00000 3943 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 3944 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 3945 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 3946 };
6087 3947
6088 watchdog@17c10000 { 3948 watchdog@17c10000 {
6089 compatible = "qcom,ap 3949 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 3950 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 3951 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI 3952 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6093 }; 3953 };
6094 3954
6095 timer@17c20000 { 3955 timer@17c20000 {
6096 #address-cells = <1>; !! 3956 #address-cells = <2>;
6097 #size-cells = <1>; !! 3957 #size-cells = <2>;
6098 ranges = <0 0 0 0x200 !! 3958 ranges;
6099 compatible = "arm,arm 3959 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 3960 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 3961 clock-frequency = <19200000>;
6102 3962
6103 frame@17c21000 { 3963 frame@17c21000 {
6104 frame-number 3964 frame-number = <0>;
6105 interrupts = 3965 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 3966 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 !! 3967 reg = <0x0 0x17c21000 0x0 0x1000>,
6108 <0x17c2 !! 3968 <0x0 0x17c22000 0x0 0x1000>;
6109 }; 3969 };
6110 3970
6111 frame@17c23000 { 3971 frame@17c23000 {
6112 frame-number 3972 frame-number = <1>;
6113 interrupts = 3973 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 !! 3974 reg = <0x0 0x17c23000 0x0 0x1000>;
6115 status = "dis 3975 status = "disabled";
6116 }; 3976 };
6117 3977
6118 frame@17c25000 { 3978 frame@17c25000 {
6119 frame-number 3979 frame-number = <2>;
6120 interrupts = 3980 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 !! 3981 reg = <0x0 0x17c25000 0x0 0x1000>;
6122 status = "dis 3982 status = "disabled";
6123 }; 3983 };
6124 3984
6125 frame@17c27000 { 3985 frame@17c27000 {
6126 frame-number 3986 frame-number = <3>;
6127 interrupts = 3987 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 !! 3988 reg = <0x0 0x17c27000 0x0 0x1000>;
6129 status = "dis 3989 status = "disabled";
6130 }; 3990 };
6131 3991
6132 frame@17c29000 { 3992 frame@17c29000 {
6133 frame-number 3993 frame-number = <4>;
6134 interrupts = 3994 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 !! 3995 reg = <0x0 0x17c29000 0x0 0x1000>;
6136 status = "dis 3996 status = "disabled";
6137 }; 3997 };
6138 3998
6139 frame@17c2b000 { 3999 frame@17c2b000 {
6140 frame-number 4000 frame-number = <5>;
6141 interrupts = 4001 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 !! 4002 reg = <0x0 0x17c2b000 0x0 0x1000>;
6143 status = "dis 4003 status = "disabled";
6144 }; 4004 };
6145 4005
6146 frame@17c2d000 { 4006 frame@17c2d000 {
6147 frame-number 4007 frame-number = <6>;
6148 interrupts = 4008 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 !! 4009 reg = <0x0 0x17c2d000 0x0 0x1000>;
6150 status = "dis 4010 status = "disabled";
6151 }; 4011 };
6152 }; 4012 };
6153 4013
6154 apps_rsc: rsc@18200000 { 4014 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 4015 label = "apps_rsc";
6156 compatible = "qcom,rp 4016 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 4017 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 4018 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 4019 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 4020 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 4021 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 4022 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 4023 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 4024 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 4025 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 4026 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 4027 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 4028
6170 rpmhcc: clock-control 4029 rpmhcc: clock-controller {
6171 compatible = 4030 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 4031 #clock-cells = <1>;
6173 clock-names = 4032 clock-names = "xo";
6174 clocks = <&xo 4033 clocks = <&xo_board>;
6175 }; 4034 };
6176 4035
6177 rpmhpd: power-control 4036 rpmhpd: power-controller {
6178 compatible = 4037 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 4038 #power-domain-cells = <1>;
6180 operating-poi 4039 operating-points-v2 = <&rpmhpd_opp_table>;
6181 4040
6182 rpmhpd_opp_ta 4041 rpmhpd_opp_table: opp-table {
6183 compa 4042 compatible = "operating-points-v2";
6184 4043
6185 rpmhp 4044 rpmhpd_opp_ret: opp1 {
6186 4045 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 4046 };
6188 4047
6189 rpmhp 4048 rpmhpd_opp_min_svs: opp2 {
6190 4049 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 4050 };
6192 4051
6193 rpmhp 4052 rpmhpd_opp_low_svs: opp3 {
6194 4053 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 4054 };
6196 4055
6197 rpmhp 4056 rpmhpd_opp_svs: opp4 {
6198 4057 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 4058 };
6200 4059
6201 rpmhp 4060 rpmhpd_opp_svs_l1: opp5 {
6202 4061 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 4062 };
6204 4063
6205 rpmhp 4064 rpmhpd_opp_nom: opp6 {
6206 4065 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 4066 };
6208 4067
6209 rpmhp 4068 rpmhpd_opp_nom_l1: opp7 {
6210 4069 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 4070 };
6212 4071
6213 rpmhp 4072 rpmhpd_opp_nom_l2: opp8 {
6214 4073 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 4074 };
6216 4075
6217 rpmhp 4076 rpmhpd_opp_turbo: opp9 {
6218 4077 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 4078 };
6220 4079
6221 rpmhp 4080 rpmhpd_opp_turbo_l1: opp10 {
6222 4081 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 4082 };
6224 }; 4083 };
6225 }; 4084 };
6226 4085
6227 apps_bcm_voter: bcm-v !! 4086 apps_bcm_voter: bcm_voter {
6228 compatible = 4087 compatible = "qcom,bcm-voter";
6229 }; 4088 };
6230 }; 4089 };
6231 4090
6232 epss_l3: interconnect@1859000 4091 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 4092 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 4093 reg = <0 0x18590000 0 0x1000>;
6235 4094
6236 clocks = <&rpmhcc RPM 4095 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 4096 clock-names = "xo", "alternate";
6238 4097
6239 #interconnect-cells = 4098 #interconnect-cells = <1>;
6240 }; 4099 };
6241 4100
6242 cpufreq_hw: cpufreq@18591000 4101 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 4102 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 4103 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 4104 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 4105 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 4106 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 4107 "freq-domain2";
6249 4108
6250 clocks = <&rpmhcc RPM 4109 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 4110 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI !! 4111
6253 <GIC_SPI <<
6254 <GIC_SPI <<
6255 interrupt-names = "dc <<
6256 #freq-domain-cells = 4112 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 4113 };
6259 }; 4114 };
6260 4115
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 4116 timer {
6265 compatible = "arm,armv8-timer 4117 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 4118 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 4119 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 4120 <GIC_PPI 14
6269 (GIC_CPU_MASK 4121 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 4122 <GIC_PPI 11
6271 (GIC_CPU_MASK 4123 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 4124 <GIC_PPI 10
6273 (GIC_CPU_MASK 4125 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 4126 };
6275 4127
6276 thermal-zones { 4128 thermal-zones {
6277 cpu0-thermal { 4129 cpu0-thermal {
6278 polling-delay-passive 4130 polling-delay-passive = <250>;
>> 4131 polling-delay = <1000>;
6279 4132
6280 thermal-sensors = <&t 4133 thermal-sensors = <&tsens0 1>;
6281 4134
6282 trips { 4135 trips {
6283 cpu0_alert0: 4136 cpu0_alert0: trip-point0 {
6284 tempe 4137 temperature = <90000>;
6285 hyste 4138 hysteresis = <2000>;
6286 type 4139 type = "passive";
6287 }; 4140 };
6288 4141
6289 cpu0_alert1: 4142 cpu0_alert1: trip-point1 {
6290 tempe 4143 temperature = <95000>;
6291 hyste 4144 hysteresis = <2000>;
6292 type 4145 type = "passive";
6293 }; 4146 };
6294 4147
6295 cpu0_crit: cp !! 4148 cpu0_crit: cpu_crit {
6296 tempe 4149 temperature = <110000>;
6297 hyste 4150 hysteresis = <1000>;
6298 type 4151 type = "critical";
6299 }; 4152 };
6300 }; 4153 };
6301 4154
6302 cooling-maps { 4155 cooling-maps {
6303 map0 { 4156 map0 {
6304 trip 4157 trip = <&cpu0_alert0>;
6305 cooli 4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 4159 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 4160 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 4161 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 4162 };
6310 map1 { 4163 map1 {
6311 trip 4164 trip = <&cpu0_alert1>;
6312 cooli 4165 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 4166 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 4167 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 4168 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 4169 };
6317 }; 4170 };
6318 }; 4171 };
6319 4172
6320 cpu1-thermal { 4173 cpu1-thermal {
6321 polling-delay-passive 4174 polling-delay-passive = <250>;
>> 4175 polling-delay = <1000>;
6322 4176
6323 thermal-sensors = <&t 4177 thermal-sensors = <&tsens0 2>;
6324 4178
6325 trips { 4179 trips {
6326 cpu1_alert0: 4180 cpu1_alert0: trip-point0 {
6327 tempe 4181 temperature = <90000>;
6328 hyste 4182 hysteresis = <2000>;
6329 type 4183 type = "passive";
6330 }; 4184 };
6331 4185
6332 cpu1_alert1: 4186 cpu1_alert1: trip-point1 {
6333 tempe 4187 temperature = <95000>;
6334 hyste 4188 hysteresis = <2000>;
6335 type 4189 type = "passive";
6336 }; 4190 };
6337 4191
6338 cpu1_crit: cp !! 4192 cpu1_crit: cpu_crit {
6339 tempe 4193 temperature = <110000>;
6340 hyste 4194 hysteresis = <1000>;
6341 type 4195 type = "critical";
6342 }; 4196 };
6343 }; 4197 };
6344 4198
6345 cooling-maps { 4199 cooling-maps {
6346 map0 { 4200 map0 {
6347 trip 4201 trip = <&cpu1_alert0>;
6348 cooli 4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 4203 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 4204 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 4205 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 4206 };
6353 map1 { 4207 map1 {
6354 trip 4208 trip = <&cpu1_alert1>;
6355 cooli 4209 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 4210 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 4211 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 4212 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 4213 };
6360 }; 4214 };
6361 }; 4215 };
6362 4216
6363 cpu2-thermal { 4217 cpu2-thermal {
6364 polling-delay-passive 4218 polling-delay-passive = <250>;
>> 4219 polling-delay = <1000>;
6365 4220
6366 thermal-sensors = <&t 4221 thermal-sensors = <&tsens0 3>;
6367 4222
6368 trips { 4223 trips {
6369 cpu2_alert0: 4224 cpu2_alert0: trip-point0 {
6370 tempe 4225 temperature = <90000>;
6371 hyste 4226 hysteresis = <2000>;
6372 type 4227 type = "passive";
6373 }; 4228 };
6374 4229
6375 cpu2_alert1: 4230 cpu2_alert1: trip-point1 {
6376 tempe 4231 temperature = <95000>;
6377 hyste 4232 hysteresis = <2000>;
6378 type 4233 type = "passive";
6379 }; 4234 };
6380 4235
6381 cpu2_crit: cp !! 4236 cpu2_crit: cpu_crit {
6382 tempe 4237 temperature = <110000>;
6383 hyste 4238 hysteresis = <1000>;
6384 type 4239 type = "critical";
6385 }; 4240 };
6386 }; 4241 };
6387 4242
6388 cooling-maps { 4243 cooling-maps {
6389 map0 { 4244 map0 {
6390 trip 4245 trip = <&cpu2_alert0>;
6391 cooli 4246 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 4247 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 4248 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 4249 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 4250 };
6396 map1 { 4251 map1 {
6397 trip 4252 trip = <&cpu2_alert1>;
6398 cooli 4253 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 4254 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 4255 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 4256 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 4257 };
6403 }; 4258 };
6404 }; 4259 };
6405 4260
6406 cpu3-thermal { 4261 cpu3-thermal {
6407 polling-delay-passive 4262 polling-delay-passive = <250>;
>> 4263 polling-delay = <1000>;
6408 4264
6409 thermal-sensors = <&t 4265 thermal-sensors = <&tsens0 4>;
6410 4266
6411 trips { 4267 trips {
6412 cpu3_alert0: 4268 cpu3_alert0: trip-point0 {
6413 tempe 4269 temperature = <90000>;
6414 hyste 4270 hysteresis = <2000>;
6415 type 4271 type = "passive";
6416 }; 4272 };
6417 4273
6418 cpu3_alert1: 4274 cpu3_alert1: trip-point1 {
6419 tempe 4275 temperature = <95000>;
6420 hyste 4276 hysteresis = <2000>;
6421 type 4277 type = "passive";
6422 }; 4278 };
6423 4279
6424 cpu3_crit: cp !! 4280 cpu3_crit: cpu_crit {
6425 tempe 4281 temperature = <110000>;
6426 hyste 4282 hysteresis = <1000>;
6427 type 4283 type = "critical";
6428 }; 4284 };
6429 }; 4285 };
6430 4286
6431 cooling-maps { 4287 cooling-maps {
6432 map0 { 4288 map0 {
6433 trip 4289 trip = <&cpu3_alert0>;
6434 cooli 4290 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 4291 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 4292 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 4293 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 4294 };
6439 map1 { 4295 map1 {
6440 trip 4296 trip = <&cpu3_alert1>;
6441 cooli 4297 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 4298 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 4299 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 4300 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 4301 };
6446 }; 4302 };
6447 }; 4303 };
6448 4304
6449 cpu4-top-thermal { 4305 cpu4-top-thermal {
6450 polling-delay-passive 4306 polling-delay-passive = <250>;
>> 4307 polling-delay = <1000>;
6451 4308
6452 thermal-sensors = <&t 4309 thermal-sensors = <&tsens0 7>;
6453 4310
6454 trips { 4311 trips {
6455 cpu4_top_aler 4312 cpu4_top_alert0: trip-point0 {
6456 tempe 4313 temperature = <90000>;
6457 hyste 4314 hysteresis = <2000>;
6458 type 4315 type = "passive";
6459 }; 4316 };
6460 4317
6461 cpu4_top_aler 4318 cpu4_top_alert1: trip-point1 {
6462 tempe 4319 temperature = <95000>;
6463 hyste 4320 hysteresis = <2000>;
6464 type 4321 type = "passive";
6465 }; 4322 };
6466 4323
6467 cpu4_top_crit !! 4324 cpu4_top_crit: cpu_crit {
6468 tempe 4325 temperature = <110000>;
6469 hyste 4326 hysteresis = <1000>;
6470 type 4327 type = "critical";
6471 }; 4328 };
6472 }; 4329 };
6473 4330
6474 cooling-maps { 4331 cooling-maps {
6475 map0 { 4332 map0 {
6476 trip 4333 trip = <&cpu4_top_alert0>;
6477 cooli 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 4338 };
6482 map1 { 4339 map1 {
6483 trip 4340 trip = <&cpu4_top_alert1>;
6484 cooli 4341 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 4342 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 4343 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 4344 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 4345 };
6489 }; 4346 };
6490 }; 4347 };
6491 4348
6492 cpu5-top-thermal { 4349 cpu5-top-thermal {
6493 polling-delay-passive 4350 polling-delay-passive = <250>;
>> 4351 polling-delay = <1000>;
6494 4352
6495 thermal-sensors = <&t 4353 thermal-sensors = <&tsens0 8>;
6496 4354
6497 trips { 4355 trips {
6498 cpu5_top_aler 4356 cpu5_top_alert0: trip-point0 {
6499 tempe 4357 temperature = <90000>;
6500 hyste 4358 hysteresis = <2000>;
6501 type 4359 type = "passive";
6502 }; 4360 };
6503 4361
6504 cpu5_top_aler 4362 cpu5_top_alert1: trip-point1 {
6505 tempe 4363 temperature = <95000>;
6506 hyste 4364 hysteresis = <2000>;
6507 type 4365 type = "passive";
6508 }; 4366 };
6509 4367
6510 cpu5_top_crit !! 4368 cpu5_top_crit: cpu_crit {
6511 tempe 4369 temperature = <110000>;
6512 hyste 4370 hysteresis = <1000>;
6513 type 4371 type = "critical";
6514 }; 4372 };
6515 }; 4373 };
6516 4374
6517 cooling-maps { 4375 cooling-maps {
6518 map0 { 4376 map0 {
6519 trip 4377 trip = <&cpu5_top_alert0>;
6520 cooli 4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 4379 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 4380 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 4381 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4382 };
6525 map1 { 4383 map1 {
6526 trip 4384 trip = <&cpu5_top_alert1>;
6527 cooli 4385 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4386 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4387 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4388 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4389 };
6532 }; 4390 };
6533 }; 4391 };
6534 4392
6535 cpu6-top-thermal { 4393 cpu6-top-thermal {
6536 polling-delay-passive 4394 polling-delay-passive = <250>;
>> 4395 polling-delay = <1000>;
6537 4396
6538 thermal-sensors = <&t 4397 thermal-sensors = <&tsens0 9>;
6539 4398
6540 trips { 4399 trips {
6541 cpu6_top_aler 4400 cpu6_top_alert0: trip-point0 {
6542 tempe 4401 temperature = <90000>;
6543 hyste 4402 hysteresis = <2000>;
6544 type 4403 type = "passive";
6545 }; 4404 };
6546 4405
6547 cpu6_top_aler 4406 cpu6_top_alert1: trip-point1 {
6548 tempe 4407 temperature = <95000>;
6549 hyste 4408 hysteresis = <2000>;
6550 type 4409 type = "passive";
6551 }; 4410 };
6552 4411
6553 cpu6_top_crit !! 4412 cpu6_top_crit: cpu_crit {
6554 tempe 4413 temperature = <110000>;
6555 hyste 4414 hysteresis = <1000>;
6556 type 4415 type = "critical";
6557 }; 4416 };
6558 }; 4417 };
6559 4418
6560 cooling-maps { 4419 cooling-maps {
6561 map0 { 4420 map0 {
6562 trip 4421 trip = <&cpu6_top_alert0>;
6563 cooli 4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 4423 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 4424 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 4425 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 4426 };
6568 map1 { 4427 map1 {
6569 trip 4428 trip = <&cpu6_top_alert1>;
6570 cooli 4429 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 4430 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 4431 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 4432 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 4433 };
6575 }; 4434 };
6576 }; 4435 };
6577 4436
6578 cpu7-top-thermal { 4437 cpu7-top-thermal {
6579 polling-delay-passive 4438 polling-delay-passive = <250>;
>> 4439 polling-delay = <1000>;
6580 4440
6581 thermal-sensors = <&t 4441 thermal-sensors = <&tsens0 10>;
6582 4442
6583 trips { 4443 trips {
6584 cpu7_top_aler 4444 cpu7_top_alert0: trip-point0 {
6585 tempe 4445 temperature = <90000>;
6586 hyste 4446 hysteresis = <2000>;
6587 type 4447 type = "passive";
6588 }; 4448 };
6589 4449
6590 cpu7_top_aler 4450 cpu7_top_alert1: trip-point1 {
6591 tempe 4451 temperature = <95000>;
6592 hyste 4452 hysteresis = <2000>;
6593 type 4453 type = "passive";
6594 }; 4454 };
6595 4455
6596 cpu7_top_crit !! 4456 cpu7_top_crit: cpu_crit {
6597 tempe 4457 temperature = <110000>;
6598 hyste 4458 hysteresis = <1000>;
6599 type 4459 type = "critical";
6600 }; 4460 };
6601 }; 4461 };
6602 4462
6603 cooling-maps { 4463 cooling-maps {
6604 map0 { 4464 map0 {
6605 trip 4465 trip = <&cpu7_top_alert0>;
6606 cooli 4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 4467 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 4468 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 4469 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 4470 };
6611 map1 { 4471 map1 {
6612 trip 4472 trip = <&cpu7_top_alert1>;
6613 cooli 4473 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 4474 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 4475 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 4476 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 4477 };
6618 }; 4478 };
6619 }; 4479 };
6620 4480
6621 cpu4-bottom-thermal { 4481 cpu4-bottom-thermal {
6622 polling-delay-passive 4482 polling-delay-passive = <250>;
>> 4483 polling-delay = <1000>;
6623 4484
6624 thermal-sensors = <&t 4485 thermal-sensors = <&tsens0 11>;
6625 4486
6626 trips { 4487 trips {
6627 cpu4_bottom_a 4488 cpu4_bottom_alert0: trip-point0 {
6628 tempe 4489 temperature = <90000>;
6629 hyste 4490 hysteresis = <2000>;
6630 type 4491 type = "passive";
6631 }; 4492 };
6632 4493
6633 cpu4_bottom_a 4494 cpu4_bottom_alert1: trip-point1 {
6634 tempe 4495 temperature = <95000>;
6635 hyste 4496 hysteresis = <2000>;
6636 type 4497 type = "passive";
6637 }; 4498 };
6638 4499
6639 cpu4_bottom_c !! 4500 cpu4_bottom_crit: cpu_crit {
6640 tempe 4501 temperature = <110000>;
6641 hyste 4502 hysteresis = <1000>;
6642 type 4503 type = "critical";
6643 }; 4504 };
6644 }; 4505 };
6645 4506
6646 cooling-maps { 4507 cooling-maps {
6647 map0 { 4508 map0 {
6648 trip 4509 trip = <&cpu4_bottom_alert0>;
6649 cooli 4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 4514 };
6654 map1 { 4515 map1 {
6655 trip 4516 trip = <&cpu4_bottom_alert1>;
6656 cooli 4517 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 4518 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 4519 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 4520 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 4521 };
6661 }; 4522 };
6662 }; 4523 };
6663 4524
6664 cpu5-bottom-thermal { 4525 cpu5-bottom-thermal {
6665 polling-delay-passive 4526 polling-delay-passive = <250>;
>> 4527 polling-delay = <1000>;
6666 4528
6667 thermal-sensors = <&t 4529 thermal-sensors = <&tsens0 12>;
6668 4530
6669 trips { 4531 trips {
6670 cpu5_bottom_a 4532 cpu5_bottom_alert0: trip-point0 {
6671 tempe 4533 temperature = <90000>;
6672 hyste 4534 hysteresis = <2000>;
6673 type 4535 type = "passive";
6674 }; 4536 };
6675 4537
6676 cpu5_bottom_a 4538 cpu5_bottom_alert1: trip-point1 {
6677 tempe 4539 temperature = <95000>;
6678 hyste 4540 hysteresis = <2000>;
6679 type 4541 type = "passive";
6680 }; 4542 };
6681 4543
6682 cpu5_bottom_c !! 4544 cpu5_bottom_crit: cpu_crit {
6683 tempe 4545 temperature = <110000>;
6684 hyste 4546 hysteresis = <1000>;
6685 type 4547 type = "critical";
6686 }; 4548 };
6687 }; 4549 };
6688 4550
6689 cooling-maps { 4551 cooling-maps {
6690 map0 { 4552 map0 {
6691 trip 4553 trip = <&cpu5_bottom_alert0>;
6692 cooli 4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 4558 };
6697 map1 { 4559 map1 {
6698 trip 4560 trip = <&cpu5_bottom_alert1>;
6699 cooli 4561 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 4562 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 4563 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 4564 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 4565 };
6704 }; 4566 };
6705 }; 4567 };
6706 4568
6707 cpu6-bottom-thermal { 4569 cpu6-bottom-thermal {
6708 polling-delay-passive 4570 polling-delay-passive = <250>;
>> 4571 polling-delay = <1000>;
6709 4572
6710 thermal-sensors = <&t 4573 thermal-sensors = <&tsens0 13>;
6711 4574
6712 trips { 4575 trips {
6713 cpu6_bottom_a 4576 cpu6_bottom_alert0: trip-point0 {
6714 tempe 4577 temperature = <90000>;
6715 hyste 4578 hysteresis = <2000>;
6716 type 4579 type = "passive";
6717 }; 4580 };
6718 4581
6719 cpu6_bottom_a 4582 cpu6_bottom_alert1: trip-point1 {
6720 tempe 4583 temperature = <95000>;
6721 hyste 4584 hysteresis = <2000>;
6722 type 4585 type = "passive";
6723 }; 4586 };
6724 4587
6725 cpu6_bottom_c !! 4588 cpu6_bottom_crit: cpu_crit {
6726 tempe 4589 temperature = <110000>;
6727 hyste 4590 hysteresis = <1000>;
6728 type 4591 type = "critical";
6729 }; 4592 };
6730 }; 4593 };
6731 4594
6732 cooling-maps { 4595 cooling-maps {
6733 map0 { 4596 map0 {
6734 trip 4597 trip = <&cpu6_bottom_alert0>;
6735 cooli 4598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 4599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 4600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 4601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 4602 };
6740 map1 { 4603 map1 {
6741 trip 4604 trip = <&cpu6_bottom_alert1>;
6742 cooli 4605 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 4606 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 4607 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 4608 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 4609 };
6747 }; 4610 };
6748 }; 4611 };
6749 4612
6750 cpu7-bottom-thermal { 4613 cpu7-bottom-thermal {
6751 polling-delay-passive 4614 polling-delay-passive = <250>;
>> 4615 polling-delay = <1000>;
6752 4616
6753 thermal-sensors = <&t 4617 thermal-sensors = <&tsens0 14>;
6754 4618
6755 trips { 4619 trips {
6756 cpu7_bottom_a 4620 cpu7_bottom_alert0: trip-point0 {
6757 tempe 4621 temperature = <90000>;
6758 hyste 4622 hysteresis = <2000>;
6759 type 4623 type = "passive";
6760 }; 4624 };
6761 4625
6762 cpu7_bottom_a 4626 cpu7_bottom_alert1: trip-point1 {
6763 tempe 4627 temperature = <95000>;
6764 hyste 4628 hysteresis = <2000>;
6765 type 4629 type = "passive";
6766 }; 4630 };
6767 4631
6768 cpu7_bottom_c !! 4632 cpu7_bottom_crit: cpu_crit {
6769 tempe 4633 temperature = <110000>;
6770 hyste 4634 hysteresis = <1000>;
6771 type 4635 type = "critical";
6772 }; 4636 };
6773 }; 4637 };
6774 4638
6775 cooling-maps { 4639 cooling-maps {
6776 map0 { 4640 map0 {
6777 trip 4641 trip = <&cpu7_bottom_alert0>;
6778 cooli 4642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 4643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 4644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 4645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 4646 };
6783 map1 { 4647 map1 {
6784 trip 4648 trip = <&cpu7_bottom_alert1>;
6785 cooli 4649 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 4650 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 4651 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 4652 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 4653 };
6790 }; 4654 };
6791 }; 4655 };
6792 4656
6793 aoss0-thermal { 4657 aoss0-thermal {
6794 polling-delay-passive 4658 polling-delay-passive = <250>;
>> 4659 polling-delay = <1000>;
6795 4660
6796 thermal-sensors = <&t 4661 thermal-sensors = <&tsens0 0>;
6797 4662
6798 trips { 4663 trips {
6799 aoss0_alert0: 4664 aoss0_alert0: trip-point0 {
6800 tempe 4665 temperature = <90000>;
6801 hyste 4666 hysteresis = <2000>;
6802 type 4667 type = "hot";
6803 }; 4668 };
6804 }; 4669 };
6805 }; 4670 };
6806 4671
6807 cluster0-thermal { 4672 cluster0-thermal {
6808 polling-delay-passive 4673 polling-delay-passive = <250>;
>> 4674 polling-delay = <1000>;
6809 4675
6810 thermal-sensors = <&t 4676 thermal-sensors = <&tsens0 5>;
6811 4677
6812 trips { 4678 trips {
6813 cluster0_aler 4679 cluster0_alert0: trip-point0 {
6814 tempe 4680 temperature = <90000>;
6815 hyste 4681 hysteresis = <2000>;
6816 type 4682 type = "hot";
6817 }; 4683 };
6818 cluster0_crit !! 4684 cluster0_crit: cluster0_crit {
6819 tempe 4685 temperature = <110000>;
6820 hyste 4686 hysteresis = <2000>;
6821 type 4687 type = "critical";
6822 }; 4688 };
6823 }; 4689 };
6824 }; 4690 };
6825 4691
6826 cluster1-thermal { 4692 cluster1-thermal {
6827 polling-delay-passive 4693 polling-delay-passive = <250>;
>> 4694 polling-delay = <1000>;
6828 4695
6829 thermal-sensors = <&t 4696 thermal-sensors = <&tsens0 6>;
6830 4697
6831 trips { 4698 trips {
6832 cluster1_aler 4699 cluster1_alert0: trip-point0 {
6833 tempe 4700 temperature = <90000>;
6834 hyste 4701 hysteresis = <2000>;
6835 type 4702 type = "hot";
6836 }; 4703 };
6837 cluster1_crit !! 4704 cluster1_crit: cluster1_crit {
6838 tempe 4705 temperature = <110000>;
6839 hyste 4706 hysteresis = <2000>;
6840 type 4707 type = "critical";
6841 }; 4708 };
6842 }; 4709 };
6843 }; 4710 };
6844 4711
6845 gpu-top-thermal { !! 4712 gpu-thermal-top {
6846 polling-delay-passive 4713 polling-delay-passive = <250>;
>> 4714 polling-delay = <1000>;
6847 4715
6848 thermal-sensors = <&t 4716 thermal-sensors = <&tsens0 15>;
6849 4717
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 4718 trips {
6858 gpu_top_alert !! 4719 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 4720 temperature = <90000>;
6866 hyste !! 4721 hysteresis = <2000>;
6867 type 4722 type = "hot";
6868 }; 4723 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 4724 };
6876 }; 4725 };
6877 4726
6878 aoss1-thermal { 4727 aoss1-thermal {
6879 polling-delay-passive 4728 polling-delay-passive = <250>;
>> 4729 polling-delay = <1000>;
6880 4730
6881 thermal-sensors = <&t 4731 thermal-sensors = <&tsens1 0>;
6882 4732
6883 trips { 4733 trips {
6884 aoss1_alert0: 4734 aoss1_alert0: trip-point0 {
6885 tempe 4735 temperature = <90000>;
6886 hyste 4736 hysteresis = <2000>;
6887 type 4737 type = "hot";
6888 }; 4738 };
6889 }; 4739 };
6890 }; 4740 };
6891 4741
6892 wlan-thermal { 4742 wlan-thermal {
6893 polling-delay-passive 4743 polling-delay-passive = <250>;
>> 4744 polling-delay = <1000>;
6894 4745
6895 thermal-sensors = <&t 4746 thermal-sensors = <&tsens1 1>;
6896 4747
6897 trips { 4748 trips {
6898 wlan_alert0: 4749 wlan_alert0: trip-point0 {
6899 tempe 4750 temperature = <90000>;
6900 hyste 4751 hysteresis = <2000>;
6901 type 4752 type = "hot";
6902 }; 4753 };
6903 }; 4754 };
6904 }; 4755 };
6905 4756
6906 video-thermal { 4757 video-thermal {
6907 polling-delay-passive 4758 polling-delay-passive = <250>;
>> 4759 polling-delay = <1000>;
6908 4760
6909 thermal-sensors = <&t 4761 thermal-sensors = <&tsens1 2>;
6910 4762
6911 trips { 4763 trips {
6912 video_alert0: 4764 video_alert0: trip-point0 {
6913 tempe 4765 temperature = <90000>;
6914 hyste 4766 hysteresis = <2000>;
6915 type 4767 type = "hot";
6916 }; 4768 };
6917 }; 4769 };
6918 }; 4770 };
6919 4771
6920 mem-thermal { 4772 mem-thermal {
6921 polling-delay-passive 4773 polling-delay-passive = <250>;
>> 4774 polling-delay = <1000>;
6922 4775
6923 thermal-sensors = <&t 4776 thermal-sensors = <&tsens1 3>;
6924 4777
6925 trips { 4778 trips {
6926 mem_alert0: t 4779 mem_alert0: trip-point0 {
6927 tempe 4780 temperature = <90000>;
6928 hyste 4781 hysteresis = <2000>;
6929 type 4782 type = "hot";
6930 }; 4783 };
6931 }; 4784 };
6932 }; 4785 };
6933 4786
6934 q6-hvx-thermal { 4787 q6-hvx-thermal {
6935 polling-delay-passive 4788 polling-delay-passive = <250>;
>> 4789 polling-delay = <1000>;
6936 4790
6937 thermal-sensors = <&t 4791 thermal-sensors = <&tsens1 4>;
6938 4792
6939 trips { 4793 trips {
6940 q6_hvx_alert0 4794 q6_hvx_alert0: trip-point0 {
6941 tempe 4795 temperature = <90000>;
6942 hyste 4796 hysteresis = <2000>;
6943 type 4797 type = "hot";
6944 }; 4798 };
6945 }; 4799 };
6946 }; 4800 };
6947 4801
6948 camera-thermal { 4802 camera-thermal {
6949 polling-delay-passive 4803 polling-delay-passive = <250>;
>> 4804 polling-delay = <1000>;
6950 4805
6951 thermal-sensors = <&t 4806 thermal-sensors = <&tsens1 5>;
6952 4807
6953 trips { 4808 trips {
6954 camera_alert0 4809 camera_alert0: trip-point0 {
6955 tempe 4810 temperature = <90000>;
6956 hyste 4811 hysteresis = <2000>;
6957 type 4812 type = "hot";
6958 }; 4813 };
6959 }; 4814 };
6960 }; 4815 };
6961 4816
6962 compute-thermal { 4817 compute-thermal {
6963 polling-delay-passive 4818 polling-delay-passive = <250>;
>> 4819 polling-delay = <1000>;
6964 4820
6965 thermal-sensors = <&t 4821 thermal-sensors = <&tsens1 6>;
6966 4822
6967 trips { 4823 trips {
6968 compute_alert 4824 compute_alert0: trip-point0 {
6969 tempe 4825 temperature = <90000>;
6970 hyste 4826 hysteresis = <2000>;
6971 type 4827 type = "hot";
6972 }; 4828 };
6973 }; 4829 };
6974 }; 4830 };
6975 4831
6976 npu-thermal { 4832 npu-thermal {
6977 polling-delay-passive 4833 polling-delay-passive = <250>;
>> 4834 polling-delay = <1000>;
6978 4835
6979 thermal-sensors = <&t 4836 thermal-sensors = <&tsens1 7>;
6980 4837
6981 trips { 4838 trips {
6982 npu_alert0: t 4839 npu_alert0: trip-point0 {
6983 tempe 4840 temperature = <90000>;
6984 hyste 4841 hysteresis = <2000>;
6985 type 4842 type = "hot";
6986 }; 4843 };
6987 }; 4844 };
6988 }; 4845 };
6989 4846
6990 gpu-bottom-thermal { !! 4847 gpu-thermal-bottom {
6991 polling-delay-passive 4848 polling-delay-passive = <250>;
>> 4849 polling-delay = <1000>;
6992 4850
6993 thermal-sensors = <&t 4851 thermal-sensors = <&tsens1 8>;
6994 4852
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 4853 trips {
7003 gpu_bottom_al !! 4854 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 4855 temperature = <90000>;
7011 hyste !! 4856 hysteresis = <2000>;
7012 type 4857 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 4858 };
7020 }; 4859 };
7021 }; 4860 };
7022 }; 4861 };
7023 }; 4862 };
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