1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 16 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 17 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 19 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 20 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 21 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 22
26 / { 23 / {
27 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
28 25
29 #address-cells = <2>; 26 #address-cells = <2>;
30 #size-cells = <2>; 27 #size-cells = <2>;
31 28
32 aliases { 29 aliases {
33 i2c0 = &i2c0; 30 i2c0 = &i2c0;
34 i2c1 = &i2c1; 31 i2c1 = &i2c1;
35 i2c2 = &i2c2; 32 i2c2 = &i2c2;
36 i2c3 = &i2c3; 33 i2c3 = &i2c3;
37 i2c4 = &i2c4; 34 i2c4 = &i2c4;
38 i2c5 = &i2c5; 35 i2c5 = &i2c5;
39 i2c6 = &i2c6; 36 i2c6 = &i2c6;
40 i2c7 = &i2c7; 37 i2c7 = &i2c7;
41 i2c8 = &i2c8; 38 i2c8 = &i2c8;
42 i2c9 = &i2c9; 39 i2c9 = &i2c9;
43 i2c10 = &i2c10; 40 i2c10 = &i2c10;
44 i2c11 = &i2c11; 41 i2c11 = &i2c11;
45 i2c12 = &i2c12; 42 i2c12 = &i2c12;
46 i2c13 = &i2c13; 43 i2c13 = &i2c13;
47 i2c14 = &i2c14; 44 i2c14 = &i2c14;
48 i2c15 = &i2c15; 45 i2c15 = &i2c15;
49 i2c16 = &i2c16; 46 i2c16 = &i2c16;
50 i2c17 = &i2c17; 47 i2c17 = &i2c17;
51 i2c18 = &i2c18; 48 i2c18 = &i2c18;
52 i2c19 = &i2c19; 49 i2c19 = &i2c19;
53 spi0 = &spi0; 50 spi0 = &spi0;
54 spi1 = &spi1; 51 spi1 = &spi1;
55 spi2 = &spi2; 52 spi2 = &spi2;
56 spi3 = &spi3; 53 spi3 = &spi3;
57 spi4 = &spi4; 54 spi4 = &spi4;
58 spi5 = &spi5; 55 spi5 = &spi5;
59 spi6 = &spi6; 56 spi6 = &spi6;
60 spi7 = &spi7; 57 spi7 = &spi7;
61 spi8 = &spi8; 58 spi8 = &spi8;
62 spi9 = &spi9; 59 spi9 = &spi9;
63 spi10 = &spi10; 60 spi10 = &spi10;
64 spi11 = &spi11; 61 spi11 = &spi11;
65 spi12 = &spi12; 62 spi12 = &spi12;
66 spi13 = &spi13; 63 spi13 = &spi13;
67 spi14 = &spi14; 64 spi14 = &spi14;
68 spi15 = &spi15; 65 spi15 = &spi15;
69 spi16 = &spi16; 66 spi16 = &spi16;
70 spi17 = &spi17; 67 spi17 = &spi17;
71 spi18 = &spi18; 68 spi18 = &spi18;
72 spi19 = &spi19; 69 spi19 = &spi19;
73 }; 70 };
74 71
75 chosen { }; 72 chosen { };
76 73
77 clocks { 74 clocks {
78 xo_board: xo-board { 75 xo_board: xo-board {
79 compatible = "fixed-cl 76 compatible = "fixed-clock";
80 #clock-cells = <0>; 77 #clock-cells = <0>;
81 clock-frequency = <384 78 clock-frequency = <38400000>;
82 clock-output-names = " 79 clock-output-names = "xo_board";
83 }; 80 };
84 81
85 sleep_clk: sleep-clk { 82 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 83 compatible = "fixed-clock";
87 clock-frequency = <327 84 clock-frequency = <32768>;
88 #clock-cells = <0>; 85 #clock-cells = <0>;
89 }; 86 };
90 }; 87 };
91 88
92 cpus { 89 cpus {
93 #address-cells = <2>; 90 #address-cells = <2>;
94 #size-cells = <0>; 91 #size-cells = <0>;
95 92
96 CPU0: cpu@0 { 93 CPU0: cpu@0 {
97 device_type = "cpu"; 94 device_type = "cpu";
98 compatible = "qcom,kry 95 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 96 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 97 enable-method = "psci";
102 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 99 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 100 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ <<
106 power-domain-names = " <<
107 qcom,freq-domain = <&c 101 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <<
109 interconnects = <&gem_ <<
110 <&epss <<
111 #cooling-cells = <2>; 102 #cooling-cells = <2>;
112 L2_0: l2-cache { 103 L2_0: l2-cache {
113 compatible = " 104 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 105 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 106 L3_0: l3-cache {
119 compat 107 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 108 };
124 }; 109 };
125 }; 110 };
126 111
127 CPU1: cpu@100 { 112 CPU1: cpu@100 {
128 device_type = "cpu"; 113 device_type = "cpu";
129 compatible = "qcom,kry 114 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 115 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 116 enable-method = "psci";
133 capacity-dmips-mhz = < 117 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 118 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 119 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ <<
137 power-domain-names = " <<
138 qcom,freq-domain = <&c 120 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = <<
140 interconnects = <&gem_ <<
141 <&epss <<
142 #cooling-cells = <2>; 121 #cooling-cells = <2>;
143 L2_100: l2-cache { 122 L2_100: l2-cache {
144 compatible = " 123 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 124 next-level-cache = <&L3_0>;
149 }; 125 };
150 }; 126 };
151 127
152 CPU2: cpu@200 { 128 CPU2: cpu@200 {
153 device_type = "cpu"; 129 device_type = "cpu";
154 compatible = "qcom,kry 130 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 131 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 132 enable-method = "psci";
158 capacity-dmips-mhz = < 133 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 134 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 135 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ <<
162 power-domain-names = " <<
163 qcom,freq-domain = <&c 136 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = <<
165 interconnects = <&gem_ <<
166 <&epss <<
167 #cooling-cells = <2>; 137 #cooling-cells = <2>;
168 L2_200: l2-cache { 138 L2_200: l2-cache {
169 compatible = " 139 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 140 next-level-cache = <&L3_0>;
174 }; 141 };
175 }; 142 };
176 143
177 CPU3: cpu@300 { 144 CPU3: cpu@300 {
178 device_type = "cpu"; 145 device_type = "cpu";
179 compatible = "qcom,kry 146 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 147 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 148 enable-method = "psci";
183 capacity-dmips-mhz = < 149 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 150 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 151 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ <<
187 power-domain-names = " <<
188 qcom,freq-domain = <&c 152 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = <<
190 interconnects = <&gem_ <<
191 <&epss <<
192 #cooling-cells = <2>; 153 #cooling-cells = <2>;
193 L2_300: l2-cache { 154 L2_300: l2-cache {
194 compatible = " 155 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 156 next-level-cache = <&L3_0>;
199 }; 157 };
200 }; 158 };
201 159
202 CPU4: cpu@400 { 160 CPU4: cpu@400 {
203 device_type = "cpu"; 161 device_type = "cpu";
204 compatible = "qcom,kry 162 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 163 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 164 enable-method = "psci";
208 capacity-dmips-mhz = < 165 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 166 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 167 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ <<
212 power-domain-names = " <<
213 qcom,freq-domain = <&c 168 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = <<
215 interconnects = <&gem_ <<
216 <&epss <<
217 #cooling-cells = <2>; 169 #cooling-cells = <2>;
218 L2_400: l2-cache { 170 L2_400: l2-cache {
219 compatible = " 171 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 172 next-level-cache = <&L3_0>;
224 }; 173 };
225 }; 174 };
226 175
227 CPU5: cpu@500 { 176 CPU5: cpu@500 {
228 device_type = "cpu"; 177 device_type = "cpu";
229 compatible = "qcom,kry 178 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 179 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 180 enable-method = "psci";
233 capacity-dmips-mhz = < 181 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 182 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 183 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ <<
237 power-domain-names = " <<
238 qcom,freq-domain = <&c 184 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = <<
240 interconnects = <&gem_ <<
241 <&epss <<
242 #cooling-cells = <2>; 185 #cooling-cells = <2>;
243 L2_500: l2-cache { 186 L2_500: l2-cache {
244 compatible = " 187 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 188 next-level-cache = <&L3_0>;
249 }; 189 };
>> 190
250 }; 191 };
251 192
252 CPU6: cpu@600 { 193 CPU6: cpu@600 {
253 device_type = "cpu"; 194 device_type = "cpu";
254 compatible = "qcom,kry 195 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 196 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 197 enable-method = "psci";
258 capacity-dmips-mhz = < 198 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 199 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 200 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ <<
262 power-domain-names = " <<
263 qcom,freq-domain = <&c 201 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = <<
265 interconnects = <&gem_ <<
266 <&epss <<
267 #cooling-cells = <2>; 202 #cooling-cells = <2>;
268 L2_600: l2-cache { 203 L2_600: l2-cache {
269 compatible = " 204 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 205 next-level-cache = <&L3_0>;
274 }; 206 };
275 }; 207 };
276 208
277 CPU7: cpu@700 { 209 CPU7: cpu@700 {
278 device_type = "cpu"; 210 device_type = "cpu";
279 compatible = "qcom,kry 211 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 212 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 213 enable-method = "psci";
283 capacity-dmips-mhz = < 214 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 215 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 216 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ <<
287 power-domain-names = " <<
288 qcom,freq-domain = <&c 217 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = <<
290 interconnects = <&gem_ <<
291 <&epss <<
292 #cooling-cells = <2>; 218 #cooling-cells = <2>;
293 L2_700: l2-cache { 219 L2_700: l2-cache {
294 compatible = " 220 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 221 next-level-cache = <&L3_0>;
299 }; 222 };
300 }; 223 };
301 224
302 cpu-map { 225 cpu-map {
303 cluster0 { 226 cluster0 {
304 core0 { 227 core0 {
305 cpu = 228 cpu = <&CPU0>;
306 }; 229 };
307 230
308 core1 { 231 core1 {
309 cpu = 232 cpu = <&CPU1>;
310 }; 233 };
311 234
312 core2 { 235 core2 {
313 cpu = 236 cpu = <&CPU2>;
314 }; 237 };
315 238
316 core3 { 239 core3 {
317 cpu = 240 cpu = <&CPU3>;
318 }; 241 };
319 242
320 core4 { 243 core4 {
321 cpu = 244 cpu = <&CPU4>;
322 }; 245 };
323 246
324 core5 { 247 core5 {
325 cpu = 248 cpu = <&CPU5>;
326 }; 249 };
327 250
328 core6 { 251 core6 {
329 cpu = 252 cpu = <&CPU6>;
330 }; 253 };
331 254
332 core7 { 255 core7 {
333 cpu = 256 cpu = <&CPU7>;
334 }; 257 };
335 }; 258 };
336 }; 259 };
337 <<
338 idle-states { <<
339 entry-method = "psci"; <<
340 <<
341 LITTLE_CPU_SLEEP_0: cp <<
342 compatible = " <<
343 idle-state-nam <<
344 arm,psci-suspe <<
345 entry-latency- <<
346 exit-latency-u <<
347 min-residency- <<
348 local-timer-st <<
349 }; <<
350 <<
351 BIG_CPU_SLEEP_0: cpu-s <<
352 compatible = " <<
353 idle-state-nam <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 local-timer-st <<
359 }; <<
360 }; <<
361 <<
362 domain-idle-states { <<
363 CLUSTER_SLEEP_0: clust <<
364 compatible = " <<
365 arm,psci-suspe <<
366 entry-latency- <<
367 exit-latency-u <<
368 min-residency- <<
369 }; <<
370 }; <<
371 }; <<
372 <<
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points <<
381 opp-shared; <<
382 <<
383 cpu0_opp1: opp-300000000 { <<
384 opp-hz = /bits/ 64 <30 <<
385 opp-peak-kBps = <80000 <<
386 }; <<
387 <<
388 cpu0_opp2: opp-403200000 { <<
389 opp-hz = /bits/ 64 <40 <<
390 opp-peak-kBps = <80000 <<
391 }; <<
392 <<
393 cpu0_opp3: opp-518400000 { <<
394 opp-hz = /bits/ 64 <51 <<
395 opp-peak-kBps = <80000 <<
396 }; <<
397 <<
398 cpu0_opp4: opp-614400000 { <<
399 opp-hz = /bits/ 64 <61 <<
400 opp-peak-kBps = <80000 <<
401 }; <<
402 <<
403 cpu0_opp5: opp-691200000 { <<
404 opp-hz = /bits/ 64 <69 <<
405 opp-peak-kBps = <80000 <<
406 }; <<
407 <<
408 cpu0_opp6: opp-787200000 { <<
409 opp-hz = /bits/ 64 <78 <<
410 opp-peak-kBps = <18040 <<
411 }; <<
412 <<
413 cpu0_opp7: opp-883200000 { <<
414 opp-hz = /bits/ 64 <88 <<
415 opp-peak-kBps = <18040 <<
416 }; <<
417 <<
418 cpu0_opp8: opp-979200000 { <<
419 opp-hz = /bits/ 64 <97 <<
420 opp-peak-kBps = <18040 <<
421 }; <<
422 <<
423 cpu0_opp9: opp-1075200000 { <<
424 opp-hz = /bits/ 64 <10 <<
425 opp-peak-kBps = <18040 <<
426 }; <<
427 <<
428 cpu0_opp10: opp-1171200000 { <<
429 opp-hz = /bits/ 64 <11 <<
430 opp-peak-kBps = <18040 <<
431 }; <<
432 <<
433 cpu0_opp11: opp-1248000000 { <<
434 opp-hz = /bits/ 64 <12 <<
435 opp-peak-kBps = <18040 <<
436 }; <<
437 <<
438 cpu0_opp12: opp-1344000000 { <<
439 opp-hz = /bits/ 64 <13 <<
440 opp-peak-kBps = <21880 <<
441 }; <<
442 <<
443 cpu0_opp13: opp-1420800000 { <<
444 opp-hz = /bits/ 64 <14 <<
445 opp-peak-kBps = <21880 <<
446 }; <<
447 <<
448 cpu0_opp14: opp-1516800000 { <<
449 opp-hz = /bits/ 64 <15 <<
450 opp-peak-kBps = <30720 <<
451 }; <<
452 <<
453 cpu0_opp15: opp-1612800000 { <<
454 opp-hz = /bits/ 64 <16 <<
455 opp-peak-kBps = <30720 <<
456 }; <<
457 <<
458 cpu0_opp16: opp-1708800000 { <<
459 opp-hz = /bits/ 64 <17 <<
460 opp-peak-kBps = <40680 <<
461 }; <<
462 <<
463 cpu0_opp17: opp-1804800000 { <<
464 opp-hz = /bits/ 64 <18 <<
465 opp-peak-kBps = <40680 <<
466 }; <<
467 }; <<
468 <<
469 cpu4_opp_table: opp-table-cpu4 { <<
470 compatible = "operating-points <<
471 opp-shared; <<
472 <<
473 cpu4_opp1: opp-710400000 { <<
474 opp-hz = /bits/ 64 <71 <<
475 opp-peak-kBps = <18040 <<
476 }; <<
477 <<
478 cpu4_opp2: opp-825600000 { <<
479 opp-hz = /bits/ 64 <82 <<
480 opp-peak-kBps = <21880 <<
481 }; <<
482 <<
483 cpu4_opp3: opp-940800000 { <<
484 opp-hz = /bits/ 64 <94 <<
485 opp-peak-kBps = <21880 <<
486 }; <<
487 <<
488 cpu4_opp4: opp-1056000000 { <<
489 opp-hz = /bits/ 64 <10 <<
490 opp-peak-kBps = <30720 <<
491 }; <<
492 <<
493 cpu4_opp5: opp-1171200000 { <<
494 opp-hz = /bits/ 64 <11 <<
495 opp-peak-kBps = <30720 <<
496 }; <<
497 <<
498 cpu4_opp6: opp-1286400000 { <<
499 opp-hz = /bits/ 64 <12 <<
500 opp-peak-kBps = <40680 <<
501 }; <<
502 <<
503 cpu4_opp7: opp-1382400000 { <<
504 opp-hz = /bits/ 64 <13 <<
505 opp-peak-kBps = <40680 <<
506 }; <<
507 <<
508 cpu4_opp8: opp-1478400000 { <<
509 opp-hz = /bits/ 64 <14 <<
510 opp-peak-kBps = <40680 <<
511 }; <<
512 <<
513 cpu4_opp9: opp-1574400000 { <<
514 opp-hz = /bits/ 64 <15 <<
515 opp-peak-kBps = <54120 <<
516 }; <<
517 <<
518 cpu4_opp10: opp-1670400000 { <<
519 opp-hz = /bits/ 64 <16 <<
520 opp-peak-kBps = <54120 <<
521 }; <<
522 <<
523 cpu4_opp11: opp-1766400000 { <<
524 opp-hz = /bits/ 64 <17 <<
525 opp-peak-kBps = <54120 <<
526 }; <<
527 <<
528 cpu4_opp12: opp-1862400000 { <<
529 opp-hz = /bits/ 64 <18 <<
530 opp-peak-kBps = <62200 <<
531 }; <<
532 <<
533 cpu4_opp13: opp-1958400000 { <<
534 opp-hz = /bits/ 64 <19 <<
535 opp-peak-kBps = <62200 <<
536 }; <<
537 <<
538 cpu4_opp14: opp-2054400000 { <<
539 opp-hz = /bits/ 64 <20 <<
540 opp-peak-kBps = <72160 <<
541 }; <<
542 <<
543 cpu4_opp15: opp-2150400000 { <<
544 opp-hz = /bits/ 64 <21 <<
545 opp-peak-kBps = <72160 <<
546 }; <<
547 <<
548 cpu4_opp16: opp-2246400000 { <<
549 opp-hz = /bits/ 64 <22 <<
550 opp-peak-kBps = <72160 <<
551 }; <<
552 <<
553 cpu4_opp17: opp-2342400000 { <<
554 opp-hz = /bits/ 64 <23 <<
555 opp-peak-kBps = <83680 <<
556 }; <<
557 <<
558 cpu4_opp18: opp-2419200000 { <<
559 opp-hz = /bits/ 64 <24 <<
560 opp-peak-kBps = <83680 <<
561 }; <<
562 }; <<
563 <<
564 cpu7_opp_table: opp-table-cpu7 { <<
565 compatible = "operating-points <<
566 opp-shared; <<
567 <<
568 cpu7_opp1: opp-844800000 { <<
569 opp-hz = /bits/ 64 <84 <<
570 opp-peak-kBps = <21880 <<
571 }; <<
572 <<
573 cpu7_opp2: opp-960000000 { <<
574 opp-hz = /bits/ 64 <96 <<
575 opp-peak-kBps = <21880 <<
576 }; <<
577 <<
578 cpu7_opp3: opp-1075200000 { <<
579 opp-hz = /bits/ 64 <10 <<
580 opp-peak-kBps = <30720 <<
581 }; <<
582 <<
583 cpu7_opp4: opp-1190400000 { <<
584 opp-hz = /bits/ 64 <11 <<
585 opp-peak-kBps = <30720 <<
586 }; <<
587 <<
588 cpu7_opp5: opp-1305600000 { <<
589 opp-hz = /bits/ 64 <13 <<
590 opp-peak-kBps = <40680 <<
591 }; <<
592 <<
593 cpu7_opp6: opp-1401600000 { <<
594 opp-hz = /bits/ 64 <14 <<
595 opp-peak-kBps = <40680 <<
596 }; <<
597 <<
598 cpu7_opp7: opp-1516800000 { <<
599 opp-hz = /bits/ 64 <15 <<
600 opp-peak-kBps = <40680 <<
601 }; <<
602 <<
603 cpu7_opp8: opp-1632000000 { <<
604 opp-hz = /bits/ 64 <16 <<
605 opp-peak-kBps = <54120 <<
606 }; <<
607 <<
608 cpu7_opp9: opp-1747200000 { <<
609 opp-hz = /bits/ 64 <17 <<
610 opp-peak-kBps = <54120 <<
611 }; <<
612 <<
613 cpu7_opp10: opp-1862400000 { <<
614 opp-hz = /bits/ 64 <18 <<
615 opp-peak-kBps = <62200 <<
616 }; <<
617 <<
618 cpu7_opp11: opp-1977600000 { <<
619 opp-hz = /bits/ 64 <19 <<
620 opp-peak-kBps = <62200 <<
621 }; <<
622 <<
623 cpu7_opp12: opp-2073600000 { <<
624 opp-hz = /bits/ 64 <20 <<
625 opp-peak-kBps = <72160 <<
626 }; <<
627 <<
628 cpu7_opp13: opp-2169600000 { <<
629 opp-hz = /bits/ 64 <21 <<
630 opp-peak-kBps = <72160 <<
631 }; <<
632 <<
633 cpu7_opp14: opp-2265600000 { <<
634 opp-hz = /bits/ 64 <22 <<
635 opp-peak-kBps = <72160 <<
636 }; <<
637 <<
638 cpu7_opp15: opp-2361600000 { <<
639 opp-hz = /bits/ 64 <23 <<
640 opp-peak-kBps = <83680 <<
641 }; <<
642 <<
643 cpu7_opp16: opp-2457600000 { <<
644 opp-hz = /bits/ 64 <24 <<
645 opp-peak-kBps = <83680 <<
646 }; <<
647 <<
648 cpu7_opp17: opp-2553600000 { <<
649 opp-hz = /bits/ 64 <25 <<
650 opp-peak-kBps = <83680 <<
651 }; <<
652 <<
653 cpu7_opp18: opp-2649600000 { <<
654 opp-hz = /bits/ 64 <26 <<
655 opp-peak-kBps = <83680 <<
656 }; <<
657 <<
658 cpu7_opp19: opp-2745600000 { <<
659 opp-hz = /bits/ 64 <27 <<
660 opp-peak-kBps = <83680 <<
661 }; <<
662 <<
663 cpu7_opp20: opp-2841600000 { <<
664 opp-hz = /bits/ 64 <28 <<
665 opp-peak-kBps = <83680 <<
666 }; <<
667 }; 260 };
668 261
669 firmware { 262 firmware {
670 scm: scm { 263 scm: scm {
671 compatible = "qcom,scm !! 264 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 265 #reset-cells = <1>;
674 }; 266 };
675 }; 267 };
676 268
677 memory@80000000 { 269 memory@80000000 {
678 device_type = "memory"; 270 device_type = "memory";
679 /* We expect the bootloader to 271 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 272 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 273 };
682 274
683 pmu { 275 pmu {
684 compatible = "arm,armv8-pmuv3" 276 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 277 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 278 };
687 279
688 psci { 280 psci {
689 compatible = "arm,psci-1.0"; 281 compatible = "arm,psci-1.0";
690 method = "smc"; 282 method = "smc";
691 <<
692 CPU_PD0: power-domain-cpu0 { <<
693 #power-domain-cells = <<
694 power-domains = <&CLUS <<
695 domain-idle-states = < <<
696 }; <<
697 <<
698 CPU_PD1: power-domain-cpu1 { <<
699 #power-domain-cells = <<
700 power-domains = <&CLUS <<
701 domain-idle-states = < <<
702 }; <<
703 <<
704 CPU_PD2: power-domain-cpu2 { <<
705 #power-domain-cells = <<
706 power-domains = <&CLUS <<
707 domain-idle-states = < <<
708 }; <<
709 <<
710 CPU_PD3: power-domain-cpu3 { <<
711 #power-domain-cells = <<
712 power-domains = <&CLUS <<
713 domain-idle-states = < <<
714 }; <<
715 <<
716 CPU_PD4: power-domain-cpu4 { <<
717 #power-domain-cells = <<
718 power-domains = <&CLUS <<
719 domain-idle-states = < <<
720 }; <<
721 <<
722 CPU_PD5: power-domain-cpu5 { <<
723 #power-domain-cells = <<
724 power-domains = <&CLUS <<
725 domain-idle-states = < <<
726 }; <<
727 <<
728 CPU_PD6: power-domain-cpu6 { <<
729 #power-domain-cells = <<
730 power-domains = <&CLUS <<
731 domain-idle-states = < <<
732 }; <<
733 <<
734 CPU_PD7: power-domain-cpu7 { <<
735 #power-domain-cells = <<
736 power-domains = <&CLUS <<
737 domain-idle-states = < <<
738 }; <<
739 <<
740 CLUSTER_PD: power-domain-cpu-c <<
741 #power-domain-cells = <<
742 domain-idle-states = < <<
743 }; <<
744 }; <<
745 <<
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; 283 };
764 284
765 reserved-memory { 285 reserved-memory {
766 #address-cells = <2>; 286 #address-cells = <2>;
767 #size-cells = <2>; 287 #size-cells = <2>;
768 ranges; 288 ranges;
769 289
770 hyp_mem: memory@80000000 { 290 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 291 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 292 no-map;
773 }; 293 };
774 294
775 xbl_aop_mem: memory@80700000 { 295 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 296 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 297 no-map;
778 }; 298 };
779 299
780 cmd_db: memory@80860000 { 300 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 301 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 302 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 303 no-map;
784 }; 304 };
785 305
786 smem_mem: memory@80900000 { 306 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 307 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 308 no-map;
789 }; 309 };
790 310
791 removed_mem: memory@80b00000 { 311 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 312 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 313 no-map;
794 }; 314 };
795 315
796 camera_mem: memory@86200000 { 316 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 317 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 318 no-map;
799 }; 319 };
800 320
801 wlan_mem: memory@86700000 { 321 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 322 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 323 no-map;
804 }; 324 };
805 325
806 ipa_fw_mem: memory@86800000 { 326 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 327 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 328 no-map;
809 }; 329 };
810 330
811 ipa_gsi_mem: memory@86810000 { 331 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 332 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 333 no-map;
814 }; 334 };
815 335
816 gpu_mem: memory@8681a000 { 336 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 337 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 338 no-map;
819 }; 339 };
820 340
821 npu_mem: memory@86900000 { 341 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 342 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 343 no-map;
824 }; 344 };
825 345
826 video_mem: memory@86e00000 { 346 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 347 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 348 no-map;
829 }; 349 };
830 350
831 cvp_mem: memory@87300000 { 351 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 352 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 353 no-map;
834 }; 354 };
835 355
836 cdsp_mem: memory@87800000 { 356 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 357 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 358 no-map;
839 }; 359 };
840 360
841 slpi_mem: memory@88c00000 { 361 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 362 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 363 no-map;
844 }; 364 };
845 365
846 adsp_mem: memory@8a100000 { 366 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 367 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 368 no-map;
849 }; 369 };
850 370
851 spss_mem: memory@8be00000 { 371 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 372 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 373 no-map;
854 }; 374 };
855 375
856 cdsp_secure_heap: memory@8bf00 376 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 377 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 378 no-map;
859 }; 379 };
860 }; 380 };
861 381
862 smem { 382 smem {
863 compatible = "qcom,smem"; 383 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 384 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 385 hwlocks = <&tcsr_mutex 3>;
866 }; 386 };
867 387
868 smp2p-adsp { 388 smp2p-adsp {
869 compatible = "qcom,smp2p"; 389 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 390 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 391 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 392 IPCC_MPROC_SIGNAL_SMP2P
873 I 393 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 394 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 395 IPCC_MPROC_SIGNAL_SMP2P>;
876 396
877 qcom,local-pid = <0>; 397 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 398 qcom,remote-pid = <2>;
879 399
880 smp2p_adsp_out: master-kernel 400 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 401 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 402 #qcom,smem-state-cells = <1>;
883 }; 403 };
884 404
885 smp2p_adsp_in: slave-kernel { 405 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 406 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 407 interrupt-controller;
888 #interrupt-cells = <2> 408 #interrupt-cells = <2>;
889 }; 409 };
890 }; 410 };
891 411
892 smp2p-cdsp { 412 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 413 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 414 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 415 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 416 IPCC_MPROC_SIGNAL_SMP2P
897 I 417 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 418 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 419 IPCC_MPROC_SIGNAL_SMP2P>;
900 420
901 qcom,local-pid = <0>; 421 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 422 qcom,remote-pid = <5>;
903 423
904 smp2p_cdsp_out: master-kernel 424 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 425 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 426 #qcom,smem-state-cells = <1>;
907 }; 427 };
908 428
909 smp2p_cdsp_in: slave-kernel { 429 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 430 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 431 interrupt-controller;
912 #interrupt-cells = <2> 432 #interrupt-cells = <2>;
913 }; 433 };
914 }; 434 };
915 435
916 smp2p-slpi { 436 smp2p-slpi {
917 compatible = "qcom,smp2p"; 437 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 438 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 439 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 440 IPCC_MPROC_SIGNAL_SMP2P
921 I 441 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 442 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 443 IPCC_MPROC_SIGNAL_SMP2P>;
924 444
925 qcom,local-pid = <0>; 445 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 446 qcom,remote-pid = <3>;
927 447
928 smp2p_slpi_out: master-kernel 448 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 449 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 450 #qcom,smem-state-cells = <1>;
931 }; 451 };
932 452
933 smp2p_slpi_in: slave-kernel { 453 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 454 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 455 interrupt-controller;
936 #interrupt-cells = <2> 456 #interrupt-cells = <2>;
937 }; 457 };
938 }; 458 };
939 459
940 soc: soc@0 { 460 soc: soc@0 {
941 #address-cells = <2>; 461 #address-cells = <2>;
942 #size-cells = <2>; 462 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 463 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 464 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 465 compatible = "simple-bus";
946 466
947 gcc: clock-controller@100000 { 467 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 468 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 469 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 470 #clock-cells = <1>;
951 #reset-cells = <1>; 471 #reset-cells = <1>;
952 #power-domain-cells = 472 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 473 clock-names = "bi_tcxo",
954 "bi_tcxo 474 "bi_tcxo_ao",
955 "sleep_c 475 "sleep_clk";
956 clocks = <&rpmhcc RPMH 476 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 477 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 478 <&sleep_clk>;
959 }; 479 };
960 480
961 ipcc: mailbox@408000 { 481 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 482 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 483 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 484 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 485 interrupt-controller;
966 #interrupt-cells = <3> 486 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 487 #mbox-cells = <2>;
968 }; 488 };
969 489
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 490 rng: rng@793000 {
983 compatible = "qcom,prn 491 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 492 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 493 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 494 clock-names = "core";
987 }; 495 };
988 496
>> 497 qup_opp_table: qup-opp-table {
>> 498 compatible = "operating-points-v2";
>> 499
>> 500 opp-50000000 {
>> 501 opp-hz = /bits/ 64 <50000000>;
>> 502 required-opps = <&rpmhpd_opp_min_svs>;
>> 503 };
>> 504
>> 505 opp-75000000 {
>> 506 opp-hz = /bits/ 64 <75000000>;
>> 507 required-opps = <&rpmhpd_opp_low_svs>;
>> 508 };
>> 509
>> 510 opp-120000000 {
>> 511 opp-hz = /bits/ 64 <120000000>;
>> 512 required-opps = <&rpmhpd_opp_svs>;
>> 513 };
>> 514 };
>> 515
989 gpi_dma2: dma-controller@80000 516 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 !! 517 compatible = "qcom,sm8250-gpi-dma";
991 reg = <0 0x00800000 0 518 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 519 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 520 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 521 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 522 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 523 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 524 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 525 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 526 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 527 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 528 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 529 dma-channels = <10>;
1003 dma-channel-mask = <0 530 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 531 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 532 #dma-cells = <3>;
1006 status = "disabled"; 533 status = "disabled";
1007 }; 534 };
1008 535
1009 qupv3_id_2: geniqup@8c0000 { 536 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 537 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 538 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 539 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 540 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 541 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 542 #address-cells = <2>;
1016 #size-cells = <2>; 543 #size-cells = <2>;
1017 iommus = <&apps_smmu 544 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 545 ranges;
1019 status = "disabled"; 546 status = "disabled";
1020 547
1021 i2c14: i2c@880000 { 548 i2c14: i2c@880000 {
1022 compatible = 549 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 550 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 551 clock-names = "se";
1025 clocks = <&gc 552 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 553 pinctrl-names = "default";
1027 pinctrl-0 = < 554 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 555 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 556 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 557 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 558 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 559 #address-cells = <1>;
1040 #size-cells = 560 #size-cells = <0>;
1041 status = "dis 561 status = "disabled";
1042 }; 562 };
1043 563
1044 spi14: spi@880000 { 564 spi14: spi@880000 {
1045 compatible = 565 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 566 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 567 clock-names = "se";
1048 clocks = <&gc 568 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 569 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 570 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 571 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 572 dma-names = "tx", "rx";
1053 power-domains !! 573 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 574 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 575 #address-cells = <1>;
1062 #size-cells = 576 #size-cells = <0>;
1063 status = "dis 577 status = "disabled";
1064 }; 578 };
1065 579
1066 i2c15: i2c@884000 { 580 i2c15: i2c@884000 {
1067 compatible = 581 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 582 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 583 clock-names = "se";
1070 clocks = <&gc 584 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 585 pinctrl-names = "default";
1072 pinctrl-0 = < 586 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 587 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 588 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 589 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 590 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 591 #address-cells = <1>;
1085 #size-cells = 592 #size-cells = <0>;
1086 status = "dis 593 status = "disabled";
1087 }; 594 };
1088 595
1089 spi15: spi@884000 { 596 spi15: spi@884000 {
1090 compatible = 597 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 598 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 599 clock-names = "se";
1093 clocks = <&gc 600 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 602 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 603 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 604 dma-names = "tx", "rx";
1098 power-domains !! 605 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 606 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 607 #address-cells = <1>;
1107 #size-cells = 608 #size-cells = <0>;
1108 status = "dis 609 status = "disabled";
1109 }; 610 };
1110 611
1111 i2c16: i2c@888000 { 612 i2c16: i2c@888000 {
1112 compatible = 613 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 614 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 615 clock-names = "se";
1115 clocks = <&gc 616 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 617 pinctrl-names = "default";
1117 pinctrl-0 = < 618 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 619 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 620 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 621 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 622 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 623 #address-cells = <1>;
1130 #size-cells = 624 #size-cells = <0>;
1131 status = "dis 625 status = "disabled";
1132 }; 626 };
1133 627
1134 spi16: spi@888000 { 628 spi16: spi@888000 {
1135 compatible = 629 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 630 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 631 clock-names = "se";
1138 clocks = <&gc 632 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 633 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 634 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 635 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 636 dma-names = "tx", "rx";
1143 power-domains !! 637 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 638 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 639 #address-cells = <1>;
1152 #size-cells = 640 #size-cells = <0>;
1153 status = "dis 641 status = "disabled";
1154 }; 642 };
1155 643
1156 i2c17: i2c@88c000 { 644 i2c17: i2c@88c000 {
1157 compatible = 645 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 646 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 647 clock-names = "se";
1160 clocks = <&gc 648 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 649 pinctrl-names = "default";
1162 pinctrl-0 = < 650 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 651 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 652 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 653 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 654 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 655 #address-cells = <1>;
1175 #size-cells = 656 #size-cells = <0>;
1176 status = "dis 657 status = "disabled";
1177 }; 658 };
1178 659
1179 spi17: spi@88c000 { 660 spi17: spi@88c000 {
1180 compatible = 661 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 662 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 663 clock-names = "se";
1183 clocks = <&gc 664 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 665 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 666 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 667 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 668 dma-names = "tx", "rx";
1188 power-domains !! 669 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 670 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 671 #address-cells = <1>;
1197 #size-cells = 672 #size-cells = <0>;
1198 status = "dis 673 status = "disabled";
1199 }; 674 };
1200 675
1201 uart17: serial@88c000 676 uart17: serial@88c000 {
1202 compatible = 677 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 678 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 679 clock-names = "se";
1205 clocks = <&gc 680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 681 pinctrl-names = "default";
1207 pinctrl-0 = < 682 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 683 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 684 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 685 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 686 status = "disabled";
1216 }; 687 };
1217 688
1218 i2c18: i2c@890000 { 689 i2c18: i2c@890000 {
1219 compatible = 690 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 691 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 692 clock-names = "se";
1222 clocks = <&gc 693 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 694 pinctrl-names = "default";
1224 pinctrl-0 = < 695 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 696 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 697 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 698 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 699 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 700 #address-cells = <1>;
1237 #size-cells = 701 #size-cells = <0>;
1238 status = "dis 702 status = "disabled";
1239 }; 703 };
1240 704
1241 spi18: spi@890000 { 705 spi18: spi@890000 {
1242 compatible = 706 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 707 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 708 clock-names = "se";
1245 clocks = <&gc 709 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 710 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 711 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 712 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 713 dma-names = "tx", "rx";
1250 power-domains !! 714 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 715 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 716 #address-cells = <1>;
1259 #size-cells = 717 #size-cells = <0>;
1260 status = "dis 718 status = "disabled";
1261 }; 719 };
1262 720
1263 uart18: serial@890000 721 uart18: serial@890000 {
1264 compatible = 722 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 723 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 724 clock-names = "se";
1267 clocks = <&gc 725 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 726 pinctrl-names = "default";
1269 pinctrl-0 = < 727 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 728 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 729 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 730 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 731 status = "disabled";
1278 }; 732 };
1279 733
1280 i2c19: i2c@894000 { 734 i2c19: i2c@894000 {
1281 compatible = 735 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 736 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 737 clock-names = "se";
1284 clocks = <&gc 738 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 739 pinctrl-names = "default";
1286 pinctrl-0 = < 740 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 741 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 742 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 743 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 744 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 745 #address-cells = <1>;
1299 #size-cells = 746 #size-cells = <0>;
1300 status = "dis 747 status = "disabled";
1301 }; 748 };
1302 749
1303 spi19: spi@894000 { 750 spi19: spi@894000 {
1304 compatible = 751 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 752 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 753 clock-names = "se";
1307 clocks = <&gc 754 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 755 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 756 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 757 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 758 dma-names = "tx", "rx";
1312 power-domains !! 759 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 760 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 761 #address-cells = <1>;
1321 #size-cells = 762 #size-cells = <0>;
1322 status = "dis 763 status = "disabled";
1323 }; 764 };
1324 }; 765 };
1325 766
1326 gpi_dma0: dma-controller@9000 767 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm !! 768 compatible = "qcom,sm8250-gpi-dma";
1328 reg = <0 0x00900000 0 769 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 770 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 771 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 772 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 773 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 774 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 775 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 776 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 777 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 778 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 779 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 780 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 781 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 782 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 783 dma-channels = <15>;
1343 dma-channel-mask = <0 784 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 785 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 786 #dma-cells = <3>;
1346 status = "disabled"; 787 status = "disabled";
1347 }; 788 };
1348 789
1349 qupv3_id_0: geniqup@9c0000 { 790 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 791 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 792 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 793 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 794 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 795 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 796 #address-cells = <2>;
1356 #size-cells = <2>; 797 #size-cells = <2>;
1357 iommus = <&apps_smmu 798 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 799 ranges;
1359 status = "disabled"; 800 status = "disabled";
1360 801
1361 i2c0: i2c@980000 { 802 i2c0: i2c@980000 {
1362 compatible = 803 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 804 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 805 clock-names = "se";
1365 clocks = <&gc 806 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 807 pinctrl-names = "default";
1367 pinctrl-0 = < 808 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 809 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 810 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 811 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 812 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 813 #address-cells = <1>;
1380 #size-cells = 814 #size-cells = <0>;
1381 status = "dis 815 status = "disabled";
1382 }; 816 };
1383 817
1384 spi0: spi@980000 { 818 spi0: spi@980000 {
1385 compatible = 819 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 820 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 821 clock-names = "se";
1388 clocks = <&gc 822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 823 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 824 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 825 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 826 dma-names = "tx", "rx";
1393 power-domains !! 827 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 828 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 829 #address-cells = <1>;
1402 #size-cells = 830 #size-cells = <0>;
1403 status = "dis 831 status = "disabled";
1404 }; 832 };
1405 833
1406 i2c1: i2c@984000 { 834 i2c1: i2c@984000 {
1407 compatible = 835 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 836 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 837 clock-names = "se";
1410 clocks = <&gc 838 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 839 pinctrl-names = "default";
1412 pinctrl-0 = < 840 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 841 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 842 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 843 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 844 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 845 #address-cells = <1>;
1425 #size-cells = 846 #size-cells = <0>;
1426 status = "dis 847 status = "disabled";
1427 }; 848 };
1428 849
1429 spi1: spi@984000 { 850 spi1: spi@984000 {
1430 compatible = 851 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 852 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 853 clock-names = "se";
1433 clocks = <&gc 854 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 855 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 856 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 857 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 858 dma-names = "tx", "rx";
1438 power-domains !! 859 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 860 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 861 #address-cells = <1>;
1447 #size-cells = 862 #size-cells = <0>;
1448 status = "dis 863 status = "disabled";
1449 }; 864 };
1450 865
1451 i2c2: i2c@988000 { 866 i2c2: i2c@988000 {
1452 compatible = 867 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 868 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 869 clock-names = "se";
1455 clocks = <&gc 870 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 871 pinctrl-names = "default";
1457 pinctrl-0 = < 872 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 873 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 874 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 875 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 876 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 877 #address-cells = <1>;
1470 #size-cells = 878 #size-cells = <0>;
1471 status = "dis 879 status = "disabled";
1472 }; 880 };
1473 881
1474 spi2: spi@988000 { 882 spi2: spi@988000 {
1475 compatible = 883 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 884 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 885 clock-names = "se";
1478 clocks = <&gc 886 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 887 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 888 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 889 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 890 dma-names = "tx", "rx";
1483 power-domains !! 891 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 892 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 893 #address-cells = <1>;
1492 #size-cells = 894 #size-cells = <0>;
1493 status = "dis 895 status = "disabled";
1494 }; 896 };
1495 897
1496 uart2: serial@988000 898 uart2: serial@988000 {
1497 compatible = 899 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 900 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 901 clock-names = "se";
1500 clocks = <&gc 902 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 903 pinctrl-names = "default";
1502 pinctrl-0 = < 904 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 905 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 906 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 907 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 908 status = "disabled";
1511 }; 909 };
1512 910
1513 i2c3: i2c@98c000 { 911 i2c3: i2c@98c000 {
1514 compatible = 912 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 913 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 914 clock-names = "se";
1517 clocks = <&gc 915 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 916 pinctrl-names = "default";
1519 pinctrl-0 = < 917 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 918 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 919 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 920 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 921 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 922 #address-cells = <1>;
1532 #size-cells = 923 #size-cells = <0>;
1533 status = "dis 924 status = "disabled";
1534 }; 925 };
1535 926
1536 spi3: spi@98c000 { 927 spi3: spi@98c000 {
1537 compatible = 928 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 929 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 930 clock-names = "se";
1540 clocks = <&gc 931 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 932 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 933 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 934 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 935 dma-names = "tx", "rx";
1545 power-domains !! 936 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 937 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 938 #address-cells = <1>;
1554 #size-cells = 939 #size-cells = <0>;
1555 status = "dis 940 status = "disabled";
1556 }; 941 };
1557 942
1558 i2c4: i2c@990000 { 943 i2c4: i2c@990000 {
1559 compatible = 944 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 945 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 946 clock-names = "se";
1562 clocks = <&gc 947 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 948 pinctrl-names = "default";
1564 pinctrl-0 = < 949 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 950 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 951 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 952 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 953 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 954 #address-cells = <1>;
1577 #size-cells = 955 #size-cells = <0>;
1578 status = "dis 956 status = "disabled";
1579 }; 957 };
1580 958
1581 spi4: spi@990000 { 959 spi4: spi@990000 {
1582 compatible = 960 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 961 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 962 clock-names = "se";
1585 clocks = <&gc 963 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 964 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 965 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 966 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 967 dma-names = "tx", "rx";
1590 power-domains !! 968 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 969 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 970 #address-cells = <1>;
1599 #size-cells = 971 #size-cells = <0>;
1600 status = "dis 972 status = "disabled";
1601 }; 973 };
1602 974
1603 i2c5: i2c@994000 { 975 i2c5: i2c@994000 {
1604 compatible = 976 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 977 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 978 clock-names = "se";
1607 clocks = <&gc 979 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 980 pinctrl-names = "default";
1609 pinctrl-0 = < 981 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 982 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 983 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 984 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 985 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 986 #address-cells = <1>;
1622 #size-cells = 987 #size-cells = <0>;
1623 status = "dis 988 status = "disabled";
1624 }; 989 };
1625 990
1626 spi5: spi@994000 { 991 spi5: spi@994000 {
1627 compatible = 992 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 993 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 994 clock-names = "se";
1630 clocks = <&gc 995 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 996 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 997 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 998 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 999 dma-names = "tx", "rx";
1635 power-domains !! 1000 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1001 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1002 #address-cells = <1>;
1644 #size-cells = 1003 #size-cells = <0>;
1645 status = "dis 1004 status = "disabled";
1646 }; 1005 };
1647 1006
1648 i2c6: i2c@998000 { 1007 i2c6: i2c@998000 {
1649 compatible = 1008 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1009 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1010 clock-names = "se";
1652 clocks = <&gc 1011 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1012 pinctrl-names = "default";
1654 pinctrl-0 = < 1013 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1014 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1015 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1016 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1017 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1018 #address-cells = <1>;
1667 #size-cells = 1019 #size-cells = <0>;
1668 status = "dis 1020 status = "disabled";
1669 }; 1021 };
1670 1022
1671 spi6: spi@998000 { 1023 spi6: spi@998000 {
1672 compatible = 1024 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1025 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1026 clock-names = "se";
1675 clocks = <&gc 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1028 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1029 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1030 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1031 dma-names = "tx", "rx";
1680 power-domains !! 1032 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1033 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1034 #address-cells = <1>;
1689 #size-cells = 1035 #size-cells = <0>;
1690 status = "dis 1036 status = "disabled";
1691 }; 1037 };
1692 1038
1693 uart6: serial@998000 1039 uart6: serial@998000 {
1694 compatible = 1040 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1041 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1042 clock-names = "se";
1697 clocks = <&gc 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1044 pinctrl-names = "default";
1699 pinctrl-0 = < 1045 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1046 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1047 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1048 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1049 status = "disabled";
1708 }; 1050 };
1709 1051
1710 i2c7: i2c@99c000 { 1052 i2c7: i2c@99c000 {
1711 compatible = 1053 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1054 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1055 clock-names = "se";
1714 clocks = <&gc 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1057 pinctrl-names = "default";
1716 pinctrl-0 = < 1058 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1059 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1060 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1061 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1062 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1063 #address-cells = <1>;
1729 #size-cells = 1064 #size-cells = <0>;
1730 status = "dis 1065 status = "disabled";
1731 }; 1066 };
1732 1067
1733 spi7: spi@99c000 { 1068 spi7: spi@99c000 {
1734 compatible = 1069 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1070 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1071 clock-names = "se";
1737 clocks = <&gc 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1073 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1074 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1075 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1076 dma-names = "tx", "rx";
1742 power-domains !! 1077 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1078 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1079 #address-cells = <1>;
1751 #size-cells = 1080 #size-cells = <0>;
1752 status = "dis 1081 status = "disabled";
1753 }; 1082 };
1754 }; 1083 };
1755 1084
1756 gpi_dma1: dma-controller@a000 1085 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm !! 1086 compatible = "qcom,sm8250-gpi-dma";
1758 reg = <0 0x00a00000 0 1087 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1088 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1089 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1090 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1091 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1092 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1093 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1094 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1095 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1096 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1097 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1098 dma-channels = <10>;
1770 dma-channel-mask = <0 1099 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1100 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1101 #dma-cells = <3>;
1773 status = "disabled"; 1102 status = "disabled";
1774 }; 1103 };
1775 1104
1776 qupv3_id_1: geniqup@ac0000 { 1105 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1106 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1107 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1108 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1109 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1110 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1111 #address-cells = <2>;
1783 #size-cells = <2>; 1112 #size-cells = <2>;
1784 iommus = <&apps_smmu 1113 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1114 ranges;
1786 status = "disabled"; 1115 status = "disabled";
1787 1116
1788 i2c8: i2c@a80000 { 1117 i2c8: i2c@a80000 {
1789 compatible = 1118 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1119 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1120 clock-names = "se";
1792 clocks = <&gc 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1122 pinctrl-names = "default";
1794 pinctrl-0 = < 1123 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1124 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1125 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1126 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1127 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1128 #address-cells = <1>;
1807 #size-cells = 1129 #size-cells = <0>;
1808 status = "dis 1130 status = "disabled";
1809 }; 1131 };
1810 1132
1811 spi8: spi@a80000 { 1133 spi8: spi@a80000 {
1812 compatible = 1134 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1135 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1136 clock-names = "se";
1815 clocks = <&gc 1137 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1138 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1139 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1140 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1141 dma-names = "tx", "rx";
1820 power-domains !! 1142 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1143 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1144 #address-cells = <1>;
1829 #size-cells = 1145 #size-cells = <0>;
1830 status = "dis 1146 status = "disabled";
1831 }; 1147 };
1832 1148
1833 i2c9: i2c@a84000 { 1149 i2c9: i2c@a84000 {
1834 compatible = 1150 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1151 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1152 clock-names = "se";
1837 clocks = <&gc 1153 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1154 pinctrl-names = "default";
1839 pinctrl-0 = < 1155 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1156 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1157 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1158 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1159 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1160 #address-cells = <1>;
1852 #size-cells = 1161 #size-cells = <0>;
1853 status = "dis 1162 status = "disabled";
1854 }; 1163 };
1855 1164
1856 spi9: spi@a84000 { 1165 spi9: spi@a84000 {
1857 compatible = 1166 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1167 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1168 clock-names = "se";
1860 clocks = <&gc 1169 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1170 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1171 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1172 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1173 dma-names = "tx", "rx";
1865 power-domains !! 1174 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1175 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1176 #address-cells = <1>;
1874 #size-cells = 1177 #size-cells = <0>;
1875 status = "dis 1178 status = "disabled";
1876 }; 1179 };
1877 1180
1878 i2c10: i2c@a88000 { 1181 i2c10: i2c@a88000 {
1879 compatible = 1182 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1183 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1184 clock-names = "se";
1882 clocks = <&gc 1185 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1186 pinctrl-names = "default";
1884 pinctrl-0 = < 1187 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1188 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1189 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1190 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1191 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1192 #address-cells = <1>;
1897 #size-cells = 1193 #size-cells = <0>;
1898 status = "dis 1194 status = "disabled";
1899 }; 1195 };
1900 1196
1901 spi10: spi@a88000 { 1197 spi10: spi@a88000 {
1902 compatible = 1198 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1199 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1200 clock-names = "se";
1905 clocks = <&gc 1201 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1202 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1203 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1204 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1205 dma-names = "tx", "rx";
1910 power-domains !! 1206 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1207 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1208 #address-cells = <1>;
1919 #size-cells = 1209 #size-cells = <0>;
1920 status = "dis 1210 status = "disabled";
1921 }; 1211 };
1922 1212
1923 i2c11: i2c@a8c000 { 1213 i2c11: i2c@a8c000 {
1924 compatible = 1214 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1215 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1216 clock-names = "se";
1927 clocks = <&gc 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1218 pinctrl-names = "default";
1929 pinctrl-0 = < 1219 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1220 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1221 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1222 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1223 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1224 #address-cells = <1>;
1942 #size-cells = 1225 #size-cells = <0>;
1943 status = "dis 1226 status = "disabled";
1944 }; 1227 };
1945 1228
1946 spi11: spi@a8c000 { 1229 spi11: spi@a8c000 {
1947 compatible = 1230 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1231 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1232 clock-names = "se";
1950 clocks = <&gc 1233 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1234 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1235 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1236 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1237 dma-names = "tx", "rx";
1955 power-domains !! 1238 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1239 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1240 #address-cells = <1>;
1964 #size-cells = 1241 #size-cells = <0>;
1965 status = "dis 1242 status = "disabled";
1966 }; 1243 };
1967 1244
1968 i2c12: i2c@a90000 { 1245 i2c12: i2c@a90000 {
1969 compatible = 1246 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1247 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1248 clock-names = "se";
1972 clocks = <&gc 1249 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1250 pinctrl-names = "default";
1974 pinctrl-0 = < 1251 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1252 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1253 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1254 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1255 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1256 #address-cells = <1>;
1987 #size-cells = 1257 #size-cells = <0>;
1988 status = "dis 1258 status = "disabled";
1989 }; 1259 };
1990 1260
1991 spi12: spi@a90000 { 1261 spi12: spi@a90000 {
1992 compatible = 1262 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1263 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1264 clock-names = "se";
1995 clocks = <&gc 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1266 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1267 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1268 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1269 dma-names = "tx", "rx";
2000 power-domains !! 1270 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1271 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1272 #address-cells = <1>;
2009 #size-cells = 1273 #size-cells = <0>;
2010 status = "dis 1274 status = "disabled";
2011 }; 1275 };
2012 1276
2013 uart12: serial@a90000 1277 uart12: serial@a90000 {
2014 compatible = 1278 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1279 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1280 clock-names = "se";
2017 clocks = <&gc 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1282 pinctrl-names = "default";
2019 pinctrl-0 = < 1283 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1284 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1285 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1286 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1287 status = "disabled";
2028 }; 1288 };
2029 1289
2030 i2c13: i2c@a94000 { 1290 i2c13: i2c@a94000 {
2031 compatible = 1291 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1292 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1293 clock-names = "se";
2034 clocks = <&gc 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1295 pinctrl-names = "default";
2036 pinctrl-0 = < 1296 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1297 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1298 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1299 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1300 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1301 #address-cells = <1>;
2049 #size-cells = 1302 #size-cells = <0>;
2050 status = "dis 1303 status = "disabled";
2051 }; 1304 };
2052 1305
2053 spi13: spi@a94000 { 1306 spi13: spi@a94000 {
2054 compatible = 1307 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1308 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1309 clock-names = "se";
2057 clocks = <&gc 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1311 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1312 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1313 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1314 dma-names = "tx", "rx";
2062 power-domains !! 1315 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1316 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1317 #address-cells = <1>;
2071 #size-cells = 1318 #size-cells = <0>;
2072 status = "dis 1319 status = "disabled";
2073 }; 1320 };
2074 }; 1321 };
2075 1322
2076 config_noc: interconnect@1500 1323 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1324 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1325 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1326 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1327 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1328 };
2082 1329
2083 system_noc: interconnect@1620 1330 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1331 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1332 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1333 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1334 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1335 };
2089 1336
2090 mc_virt: interconnect@163d000 1337 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1338 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1339 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1340 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1341 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1342 };
2096 1343
2097 aggre1_noc: interconnect@16e0 1344 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1345 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1346 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1347 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1348 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1349 };
2103 1350
2104 aggre2_noc: interconnect@1700 1351 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1352 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1353 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1354 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1355 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1356 };
2110 1357
2111 compute_noc: interconnect@173 1358 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1359 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1360 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1361 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1362 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1363 };
2117 1364
2118 mmss_noc: interconnect@174000 1365 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1366 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1367 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1368 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1369 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1370 };
2124 1371
2125 pcie0: pcie@1c00000 { !! 1372 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1373 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1374 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1375 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1376 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1377 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1378 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1379 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1380 device_type = "pci";
2135 linux,pci-domain = <0 1381 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1382 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1383 num-lanes = <1>;
2138 1384
2139 #address-cells = <3>; 1385 #address-cells = <3>;
2140 #size-cells = <2>; 1386 #size-cells = <2>;
2141 1387
2142 ranges = <0x01000000 !! 1388 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1389 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1390
2145 interrupts = <GIC_SPI !! 1391 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1392 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1393 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1394 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1395 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1396 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1397 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1398 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1399
2168 clocks = <&gcc GCC_PC 1400 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1401 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1402 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1403 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1404 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1405 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1406 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1407 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1408 clock-names = "pipe",
2177 "aux", 1409 "aux",
2178 "cfg", 1410 "cfg",
2179 "bus_ma 1411 "bus_master",
2180 "bus_sl 1412 "bus_slave",
2181 "slave_ 1413 "slave_q2a",
2182 "tbu", 1414 "tbu",
2183 "ddrss_ 1415 "ddrss_sf_tbu";
2184 1416
>> 1417 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1418 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1419 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1420
2188 resets = <&gcc GCC_PC 1421 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1422 reset-names = "pci";
2190 1423
2191 power-domains = <&gcc 1424 power-domains = <&gcc PCIE_0_GDSC>;
2192 1425
2193 phys = <&pcie0_phy>; !! 1426 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1427 phy-names = "pciephy";
2195 1428
2196 perst-gpios = <&tlmm 1429 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1430 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1431
2199 pinctrl-names = "defa 1432 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1433 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1434
2203 status = "disabled"; 1435 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1436 };
2215 1437
2216 pcie0_phy: phy@1c06000 { 1438 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1439 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1440 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1441 #address-cells = <2>;
>> 1442 #size-cells = <2>;
>> 1443 ranges;
2220 clocks = <&gcc GCC_PC 1444 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1445 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1446 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1447 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1448 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1449
2236 resets = <&gcc GCC_PC 1450 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1451 reset-names = "phy";
2238 1452
2239 assigned-clocks = <&g 1453 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1454 assigned-clock-rates = <100000000>;
2241 1455
2242 status = "disabled"; 1456 status = "disabled";
>> 1457
>> 1458 pcie0_lane: phy@1c06200 {
>> 1459 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1460 <0 0x1c06400 0 0x200>, /* rx */
>> 1461 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1462 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1463 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1464 clock-names = "pipe0";
>> 1465
>> 1466 #phy-cells = <0>;
>> 1467 clock-output-names = "pcie_0_pipe_clk";
>> 1468 };
2243 }; 1469 };
2244 1470
2245 pcie1: pcie@1c08000 { !! 1471 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1472 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1473 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1474 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1475 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1476 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1477 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1478 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1479 device_type = "pci";
2255 linux,pci-domain = <1 1480 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1481 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1482 num-lanes = <2>;
2258 1483
2259 #address-cells = <3>; 1484 #address-cells = <3>;
2260 #size-cells = <2>; 1485 #size-cells = <2>;
2261 1486
2262 ranges = <0x01000000 !! 1487 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1488 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1489
2265 interrupts = <GIC_SPI !! 1490 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1491 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1492 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1493 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1494 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1495 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1496 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1497 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1498
2288 clocks = <&gcc GCC_PC 1499 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1500 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1501 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1502 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1503 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1504 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1505 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1506 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1507 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1508 clock-names = "pipe",
2298 "aux", 1509 "aux",
2299 "cfg", 1510 "cfg",
2300 "bus_ma 1511 "bus_master",
2301 "bus_sl 1512 "bus_slave",
2302 "slave_ 1513 "slave_q2a",
2303 "ref", 1514 "ref",
2304 "tbu", 1515 "tbu",
2305 "ddrss_ 1516 "ddrss_sf_tbu";
2306 1517
2307 assigned-clocks = <&g 1518 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1519 assigned-clock-rates = <19200000>;
2309 1520
>> 1521 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1522 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1523 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1524
2313 resets = <&gcc GCC_PC 1525 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1526 reset-names = "pci";
2315 1527
2316 power-domains = <&gcc 1528 power-domains = <&gcc PCIE_1_GDSC>;
2317 1529
2318 phys = <&pcie1_phy>; !! 1530 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1531 phy-names = "pciephy";
2320 1532
2321 perst-gpios = <&tlmm 1533 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1534 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1535
2324 pinctrl-names = "defa 1536 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1537 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1538
2328 status = "disabled"; 1539 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1540 };
2340 1541
2341 pcie1_phy: phy@1c0e000 { 1542 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1543 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1544 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1545 #address-cells = <2>;
>> 1546 #size-cells = <2>;
>> 1547 ranges;
2345 clocks = <&gcc GCC_PC 1548 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1549 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1550 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1551 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1552 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1553
2361 resets = <&gcc GCC_PC 1554 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1555 reset-names = "phy";
2363 1556
2364 assigned-clocks = <&g 1557 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1558 assigned-clock-rates = <100000000>;
2366 1559
2367 status = "disabled"; 1560 status = "disabled";
>> 1561
>> 1562 pcie1_lane: phy@1c0e200 {
>> 1563 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1564 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1565 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1566 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1567 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1568 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1569 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1570 clock-names = "pipe0";
>> 1571
>> 1572 #phy-cells = <0>;
>> 1573 clock-output-names = "pcie_1_pipe_clk";
>> 1574 };
2368 }; 1575 };
2369 1576
2370 pcie2: pcie@1c10000 { !! 1577 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 1578 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 1579 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 1580 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 1581 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 1582 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 1583 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 1584 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 1585 device_type = "pci";
2380 linux,pci-domain = <2 1586 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 1587 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 1588 num-lanes = <2>;
2383 1589
2384 #address-cells = <3>; 1590 #address-cells = <3>;
2385 #size-cells = <2>; 1591 #size-cells = <2>;
2386 1592
2387 ranges = <0x01000000 !! 1593 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 1594 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 1595
2390 interrupts = <GIC_SPI !! 1596 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 1597 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 1598 #interrupt-cells = <1>;
2407 interrupt-map-mask = 1599 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 1600 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 1601 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 1602 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 1603 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 1604
2413 clocks = <&gcc GCC_PC 1605 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 1606 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 1607 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 1608 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 1609 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 1610 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 1611 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 1612 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 1613 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 1614 clock-names = "pipe",
2423 "aux", 1615 "aux",
2424 "cfg", 1616 "cfg",
2425 "bus_ma 1617 "bus_master",
2426 "bus_sl 1618 "bus_slave",
2427 "slave_ 1619 "slave_q2a",
2428 "ref", 1620 "ref",
2429 "tbu", 1621 "tbu",
2430 "ddrss_ 1622 "ddrss_sf_tbu";
2431 1623
2432 assigned-clocks = <&g 1624 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 1625 assigned-clock-rates = <19200000>;
2434 1626
>> 1627 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 1628 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 1629 <0x100 &apps_smmu 0x1d01 0x1>;
2437 1630
2438 resets = <&gcc GCC_PC 1631 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 1632 reset-names = "pci";
2440 1633
2441 power-domains = <&gcc 1634 power-domains = <&gcc PCIE_2_GDSC>;
2442 1635
2443 phys = <&pcie2_phy>; !! 1636 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 1637 phy-names = "pciephy";
2445 1638
2446 perst-gpios = <&tlmm 1639 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 1640 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 1641
2449 pinctrl-names = "defa 1642 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 1643 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 1644
2453 status = "disabled"; 1645 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 1646 };
2465 1647
2466 pcie2_phy: phy@1c16000 { 1648 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 1649 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 1650 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 1651 #address-cells = <2>;
>> 1652 #size-cells = <2>;
>> 1653 ranges;
2470 clocks = <&gcc GCC_PC 1654 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 1655 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 1656 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 1657 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 1658 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 1659
2486 resets = <&gcc GCC_PC 1660 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 1661 reset-names = "phy";
2488 1662
2489 assigned-clocks = <&g 1663 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 1664 assigned-clock-rates = <100000000>;
2491 1665
2492 status = "disabled"; 1666 status = "disabled";
>> 1667
>> 1668 pcie2_lane: phy@1c16200 {
>> 1669 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 1670 <0 0x1c16400 0 0x200>, /* rx0 */
>> 1671 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 1672 <0 0x1c16600 0 0x170>, /* tx1 */
>> 1673 <0 0x1c16800 0 0x200>, /* rx1 */
>> 1674 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1675 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 1676 clock-names = "pipe0";
>> 1677
>> 1678 #phy-cells = <0>;
>> 1679 clock-output-names = "pcie_2_pipe_clk";
>> 1680 };
2493 }; 1681 };
2494 1682
2495 ufs_mem_hc: ufshc@1d84000 { 1683 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 1684 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 1685 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 1686 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 1687 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 1688 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 1689 phy-names = "ufsphy";
2502 lanes-per-direction = 1690 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 1691 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 1692 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 1693 reset-names = "rst";
2506 1694
2507 power-domains = <&gcc 1695 power-domains = <&gcc UFS_PHY_GDSC>;
2508 1696
2509 iommus = <&apps_smmu 1697 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 1698
2511 clock-names = 1699 clock-names =
2512 "core_clk", 1700 "core_clk",
2513 "bus_aggr_clk 1701 "bus_aggr_clk",
2514 "iface_clk", 1702 "iface_clk",
2515 "core_clk_uni 1703 "core_clk_unipro",
2516 "ref_clk", 1704 "ref_clk",
2517 "tx_lane0_syn 1705 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 1706 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 1707 "rx_lane1_sync_clk";
2520 clocks = 1708 clocks =
2521 <&gcc GCC_UFS 1709 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 1710 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 1711 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 1712 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 1713 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 1714 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 1715 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 1716 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 1717 freq-table-hz =
2530 operating-points-v2 = !! 1718 <37500000 300000000>,
2531 !! 1719 <0 0>,
2532 interconnects = <&agg !! 1720 <0 0>,
2533 <&gem !! 1721 <37500000 300000000>,
2534 interconnect-names = !! 1722 <0 0>,
>> 1723 <0 0>,
>> 1724 <0 0>,
>> 1725 <0 0>;
2535 1726
2536 status = "disabled"; 1727 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 1728 };
2566 1729
2567 ufs_mem_phy: phy@1d87000 { 1730 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 1731 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 1732 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 1733 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 1734 #size-cells = <2>;
2572 <&gcc GCC_UF !! 1735 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 1736 clock-names = "ref",
2575 "ref_au !! 1737 "ref_aux";
2576 "qref"; !! 1738 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 1739 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 1740
2578 resets = <&ufs_mem_hc 1741 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 1742 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 1743 status = "disabled";
>> 1744
>> 1745 ufs_mem_phy_lanes: phy@1d87400 {
>> 1746 reg = <0 0x01d87400 0 0x108>,
>> 1747 <0 0x01d87600 0 0x1e0>,
>> 1748 <0 0x01d87c00 0 0x1dc>,
>> 1749 <0 0x01d87800 0 0x108>,
>> 1750 <0 0x01d87a00 0 0x1e0>;
>> 1751 #phy-cells = <0>;
>> 1752 };
2586 }; 1753 };
2587 1754
2588 cryptobam: dma-controller@1dc !! 1755 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 1756 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 1757 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 1758 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 1759 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 1760 };
2619 1761
2620 tcsr_mutex: hwlock@1f40000 { 1762 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 1763 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 1764 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 1765 #hwlock-cells = <1>;
2624 }; 1766 };
2625 1767
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 1768 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 1769 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 1770 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 1771 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 1772 <&audiocc 0>,
2636 <&q6afecc LP 1773 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 1774 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1775 <&aoncc 0>,
2638 <&vamacro>; 1776 <&vamacro>;
2639 1777
2640 clock-names = "mclk", !! 1778 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 1779
2642 #clock-cells = <0>; 1780 #clock-cells = <0>;
>> 1781 clock-frequency = <9600000>;
2643 clock-output-names = 1782 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 1783 #sound-dai-cells = <1>;
2645 1784
2646 pinctrl-names = "defa 1785 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 1786 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 1787 };
2651 1788
2652 swr0: soundwire@3250000 { !! 1789 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 1790 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 1791 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 1792 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 1793 clocks = <&wsamacro>;
2657 clock-names = "iface" 1794 clock-names = "iface";
2658 1795
2659 qcom,din-ports = <2>; 1796 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 1797 qcom,dout-ports = <6>;
2661 1798
2662 qcom,ports-sinterval- 1799 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 1800 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 1801 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 1802 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 1803
2667 #sound-dai-cells = <1 1804 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 1805 #address-cells = <2>;
2669 #size-cells = <0>; 1806 #size-cells = <0>;
>> 1807 };
2670 1808
2671 status = "disabled"; !! 1809 audiocc: clock-controller@3300000 {
>> 1810 compatible = "qcom,sm8250-lpass-audiocc";
>> 1811 reg = <0 0x03300000 0 0x30000>;
>> 1812 #clock-cells = <1>;
>> 1813 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1814 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 1815 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 1816 clock-names = "core", "audio", "bus";
2672 }; 1817 };
2673 1818
2674 vamacro: codec@3370000 { 1819 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 1820 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 1821 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 1822 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 1823 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 1824 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 1825
2681 clock-names = "mclk", 1826 clock-names = "mclk", "macro", "dcodec";
2682 1827
2683 #clock-cells = <0>; 1828 #clock-cells = <0>;
>> 1829 clock-frequency = <9600000>;
2684 clock-output-names = 1830 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 1831 #sound-dai-cells = <1>;
2686 }; 1832 };
2687 1833
2688 rxmacro: rxmacro@3200000 { !! 1834 aoncc: clock-controller@3380000 {
2689 pinctrl-names = "defa !! 1835 compatible = "qcom,sm8250-lpass-aoncc";
2690 pinctrl-0 = <&rx_swr_ !! 1836 reg = <0 0x03380000 0 0x40000>;
2691 compatible = "qcom,sm !! 1837 #clock-cells = <1>;
2692 reg = <0 0x03200000 0 !! 1838 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2693 status = "disabled"; <<
2694 <<
2695 clocks = <&q6afecc LP <<
2696 <&q6afecc LPA <<
2697 <&q6afecc LPA <<
2698 <&q6afecc LPA 1839 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; !! 1840 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2700 !! 1841 clock-names = "core", "audio", "bus";
2701 clock-names = "mclk", <<
2702 <<
2703 #clock-cells = <0>; <<
2704 clock-output-names = <<
2705 #sound-dai-cells = <1 <<
2706 }; <<
2707 <<
2708 swr1: soundwire@3210000 { <<
2709 reg = <0 0x03210000 0 <<
2710 compatible = "qcom,so <<
2711 status = "disabled"; <<
2712 interrupts = <GIC_SPI <<
2713 clocks = <&rxmacro>; <<
2714 clock-names = "iface" <<
2715 label = "RX"; <<
2716 qcom,din-ports = <0>; <<
2717 qcom,dout-ports = <5> <<
2718 <<
2719 qcom,ports-sinterval- <<
2720 qcom,ports-offset1 = <<
2721 qcom,ports-offset2 = <<
2722 qcom,ports-hstart = <<
2723 qcom,ports-hstop = <<
2724 qcom,ports-word-lengt <<
2725 qcom,ports-block-pack <<
2726 qcom,ports-lane-contr <<
2727 qcom,ports-block-grou <<
2728 <<
2729 #sound-dai-cells = <1 <<
2730 #address-cells = <2>; <<
2731 #size-cells = <0>; <<
2732 }; <<
2733 <<
2734 txmacro: txmacro@3220000 { <<
2735 pinctrl-names = "defa <<
2736 pinctrl-0 = <&tx_swr_ <<
2737 compatible = "qcom,sm <<
2738 reg = <0 0x03220000 0 <<
2739 status = "disabled"; <<
2740 <<
2741 clocks = <&q6afecc LP <<
2742 <&q6afecc LP <<
2743 <&q6afecc LP <<
2744 <&q6afecc LP <<
2745 <&vamacro>; <<
2746 <<
2747 clock-names = "mclk", <<
2748 <<
2749 #clock-cells = <0>; <<
2750 clock-output-names = <<
2751 #sound-dai-cells = <1 <<
2752 }; 1842 };
2753 1843
2754 /* tx macro */ !! 1844 lpass_tlmm: pinctrl@33c0000{
2755 swr2: soundwire@3230000 { <<
2756 reg = <0 0x03230000 0 <<
2757 compatible = "qcom,so <<
2758 interrupts = <GIC_SPI <<
2759 interrupt-names = "co <<
2760 status = "disabled"; <<
2761 <<
2762 clocks = <&txmacro>; <<
2763 clock-names = "iface" <<
2764 label = "TX"; <<
2765 <<
2766 qcom,din-ports = <5>; <<
2767 qcom,dout-ports = <0> <<
2768 qcom,ports-sinterval- <<
2769 qcom,ports-offset1 = <<
2770 qcom,ports-offset2 = <<
2771 qcom,ports-block-pack <<
2772 qcom,ports-hstart = <<
2773 qcom,ports-hstop = <<
2774 qcom,ports-word-lengt <<
2775 qcom,ports-block-grou <<
2776 qcom,ports-lane-contr <<
2777 #sound-dai-cells = <1 <<
2778 #address-cells = <2>; <<
2779 #size-cells = <0>; <<
2780 }; <<
2781 <<
2782 lpass_tlmm: pinctrl@33c0000 { <<
2783 compatible = "qcom,sm 1845 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 1846 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 1847 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 1848 gpio-controller;
2787 #gpio-cells = <2>; 1849 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 1850 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 1851
2790 clocks = <&q6afecc LP 1852 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 1853 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 1854 clock-names = "core", "audio";
2793 1855
2794 wsa_swr_active: wsa-s !! 1856 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 1857 clk {
2796 pins 1858 pins = "gpio10";
2797 funct 1859 function = "wsa_swr_clk";
2798 drive 1860 drive-strength = <2>;
2799 slew- 1861 slew-rate = <1>;
2800 bias- 1862 bias-disable;
2801 }; 1863 };
2802 1864
2803 data-pins { !! 1865 data {
2804 pins 1866 pins = "gpio11";
2805 funct 1867 function = "wsa_swr_data";
2806 drive 1868 drive-strength = <2>;
2807 slew- 1869 slew-rate = <1>;
2808 bias- 1870 bias-bus-hold;
>> 1871
2809 }; 1872 };
2810 }; 1873 };
2811 1874
2812 wsa_swr_sleep: wsa-sw !! 1875 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 1876 clk {
2814 pins 1877 pins = "gpio10";
2815 funct 1878 function = "wsa_swr_clk";
2816 drive 1879 drive-strength = <2>;
>> 1880 input-enable;
2817 bias- 1881 bias-pull-down;
2818 }; 1882 };
2819 1883
2820 data-pins { !! 1884 data {
2821 pins 1885 pins = "gpio11";
2822 funct 1886 function = "wsa_swr_data";
2823 drive 1887 drive-strength = <2>;
>> 1888 input-enable;
2824 bias- 1889 bias-pull-down;
>> 1890
2825 }; 1891 };
2826 }; 1892 };
2827 1893
2828 dmic01_active: dmic01 !! 1894 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 1895 clk {
2830 pins 1896 pins = "gpio6";
2831 funct 1897 function = "dmic1_clk";
2832 drive 1898 drive-strength = <8>;
2833 outpu 1899 output-high;
2834 }; 1900 };
2835 data-pins { !! 1901 data {
2836 pins 1902 pins = "gpio7";
2837 funct 1903 function = "dmic1_data";
2838 drive 1904 drive-strength = <8>;
>> 1905 input-enable;
2839 }; 1906 };
2840 }; 1907 };
2841 1908
2842 dmic01_sleep: dmic01- !! 1909 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 1910 clk {
2844 pins 1911 pins = "gpio6";
2845 funct 1912 function = "dmic1_clk";
2846 drive 1913 drive-strength = <2>;
2847 bias- 1914 bias-disable;
2848 outpu 1915 output-low;
2849 }; 1916 };
2850 1917
2851 data-pins { !! 1918 data {
2852 pins 1919 pins = "gpio7";
2853 funct 1920 function = "dmic1_data";
2854 drive 1921 drive-strength = <2>;
2855 bias- !! 1922 pull-down;
2856 }; !! 1923 input-enable;
2857 }; <<
2858 <<
2859 rx_swr_active: rx-swr <<
2860 clk-pins { <<
2861 pins <<
2862 funct <<
2863 drive <<
2864 slew- <<
2865 bias- <<
2866 }; <<
2867 <<
2868 data-pins { <<
2869 pins <<
2870 funct <<
2871 drive <<
2872 slew- <<
2873 bias- <<
2874 }; <<
2875 }; <<
2876 <<
2877 tx_swr_active: tx-swr <<
2878 clk-pins { <<
2879 pins <<
2880 funct <<
2881 drive <<
2882 slew- <<
2883 bias- <<
2884 }; <<
2885 <<
2886 data-pins { <<
2887 pins <<
2888 funct <<
2889 drive <<
2890 slew- <<
2891 bias- <<
2892 }; <<
2893 }; <<
2894 <<
2895 tx_swr_sleep: tx-swr- <<
2896 clk-pins { <<
2897 pins <<
2898 funct <<
2899 drive <<
2900 bias- <<
2901 }; <<
2902 <<
2903 data1-pins { <<
2904 pins <<
2905 funct <<
2906 drive <<
2907 bias- <<
2908 }; <<
2909 <<
2910 data2-pins { <<
2911 pins <<
2912 funct <<
2913 drive <<
2914 bias- <<
2915 }; 1924 };
2916 }; 1925 };
2917 }; 1926 };
2918 1927
2919 gpu: gpu@3d00000 { 1928 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 1929 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 1930 "qcom,adreno";
>> 1931 #stream-id-cells = <16>;
2922 1932
2923 reg = <0 0x03d00000 0 1933 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 1934 reg-names = "kgsl_3d0_reg_memory";
2925 1935
2926 interrupts = <GIC_SPI 1936 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 1937
2928 iommus = <&adreno_smm 1938 iommus = <&adreno_smmu 0 0x401>;
2929 1939
2930 operating-points-v2 = 1940 operating-points-v2 = <&gpu_opp_table>;
2931 1941
2932 qcom,gmu = <&gmu>; 1942 qcom,gmu = <&gmu>;
2933 1943
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 1944 status = "disabled";
2939 1945
2940 zap-shader { 1946 zap-shader {
2941 memory-region 1947 memory-region = <&gpu_mem>;
2942 }; 1948 };
2943 1949
>> 1950 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 1951 gpu_opp_table: opp-table {
2945 compatible = 1952 compatible = "operating-points-v2";
2946 1953
2947 opp-670000000 1954 opp-670000000 {
2948 opp-h 1955 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 1956 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 1957 };
2952 1958
2953 opp-587000000 1959 opp-587000000 {
2954 opp-h 1960 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 1961 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 1962 };
2958 1963
2959 opp-525000000 1964 opp-525000000 {
2960 opp-h 1965 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 1966 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 1967 };
2964 1968
2965 opp-490000000 1969 opp-490000000 {
2966 opp-h 1970 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 1971 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 1972 };
2970 1973
2971 opp-441600000 1974 opp-441600000 {
2972 opp-h 1975 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 1976 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 1977 };
2976 1978
2977 opp-400000000 1979 opp-400000000 {
2978 opp-h 1980 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 1981 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 1982 };
2982 1983
2983 opp-305000000 1984 opp-305000000 {
2984 opp-h 1985 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 1986 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 1987 };
2988 }; 1988 };
2989 }; 1989 };
2990 1990
2991 gmu: gmu@3d6a000 { 1991 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 1992 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 1993
2994 reg = <0 0x03d6a000 0 1994 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 1995 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 1996 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 1997 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 1998 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 1999
3000 interrupts = <GIC_SPI 2000 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2001 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2002 interrupt-names = "hfi", "gmu";
3003 2003
3004 clocks = <&gpucc GPU_ 2004 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2005 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2006 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2007 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2008 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2009 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2010
3011 power-domains = <&gpu 2011 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2012 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2013 power-domain-names = "cx", "gx";
3014 2014
3015 iommus = <&adreno_smm 2015 iommus = <&adreno_smmu 5 0x400>;
3016 2016
3017 operating-points-v2 = 2017 operating-points-v2 = <&gmu_opp_table>;
3018 2018
3019 status = "disabled"; 2019 status = "disabled";
3020 2020
3021 gmu_opp_table: opp-ta 2021 gmu_opp_table: opp-table {
3022 compatible = 2022 compatible = "operating-points-v2";
3023 2023
3024 opp-200000000 2024 opp-200000000 {
3025 opp-h 2025 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2027 };
3028 }; 2028 };
3029 }; 2029 };
3030 2030
3031 gpucc: clock-controller@3d900 2031 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2032 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2033 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2034 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2035 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2036 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2037 clock-names = "bi_tcxo",
3038 "gcc_gp 2038 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2039 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2040 #clock-cells = <1>;
3041 #reset-cells = <1>; 2041 #reset-cells = <1>;
3042 #power-domain-cells = 2042 #power-domain-cells = <1>;
3043 }; 2043 };
3044 2044
3045 adreno_smmu: iommu@3da0000 { 2045 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2046 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2047 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2048 #iommu-cells = <2>;
3050 #global-interrupts = 2049 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2050 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2051 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2052 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2053 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2054 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2055 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2056 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2057 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2058 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2059 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2060 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2061 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2062 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2063 clock-names = "ahb", "bus", "iface";
3065 2064
3066 power-domains = <&gpu 2065 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2066 };
3069 2067
3070 slpi: remoteproc@5c00000 { 2068 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2069 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2070 reg = <0 0x05c00000 0 0x4000>;
3073 2071
3074 interrupts-extended = !! 2072 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2073 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2074 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2075 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2076 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2077 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2078 "handover", "stop-ack";
3081 2079
3082 clocks = <&rpmhcc RPM 2080 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2081 clock-names = "xo";
3084 2082
3085 power-domains = <&rpm !! 2083 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2084 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2085 power-domain-names = "lcx", "lmx";
3088 2086
3089 memory-region = <&slp 2087 memory-region = <&slpi_mem>;
3090 2088
3091 qcom,qmp = <&aoss_qmp 2089 qcom,qmp = <&aoss_qmp>;
3092 2090
3093 qcom,smem-states = <& 2091 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2092 qcom,smem-state-names = "stop";
3095 2093
3096 status = "disabled"; 2094 status = "disabled";
3097 2095
3098 glink-edge { 2096 glink-edge {
3099 interrupts-ex 2097 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2098 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2099 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2100 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2101 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2102
3105 label = "slpi 2103 label = "slpi";
3106 qcom,remote-p 2104 qcom,remote-pid = <3>;
3107 2105
3108 fastrpc { 2106 fastrpc {
3109 compa 2107 compatible = "qcom,fastrpc";
3110 qcom, 2108 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2109 label = "sdsp";
3112 qcom, <<
3113 #addr 2110 #address-cells = <1>;
3114 #size 2111 #size-cells = <0>;
3115 2112
3116 compu 2113 compute-cb@1 {
3117 2114 compatible = "qcom,fastrpc-compute-cb";
3118 2115 reg = <1>;
3119 2116 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2117 };
3121 2118
3122 compu 2119 compute-cb@2 {
3123 2120 compatible = "qcom,fastrpc-compute-cb";
3124 2121 reg = <2>;
3125 2122 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2123 };
3127 2124
3128 compu 2125 compute-cb@3 {
3129 2126 compatible = "qcom,fastrpc-compute-cb";
3130 2127 reg = <3>;
3131 2128 iommus = <&apps_smmu 0x0543 0x0>;
3132 2129 /* note: shared-cb = <4> in downstream */
3133 }; 2130 };
3134 }; 2131 };
3135 }; 2132 };
3136 }; 2133 };
3137 2134
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 2135 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 2136 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 2137 reg = <0 0x08300000 0 0x10000>;
3777 2138
3778 interrupts-extended = !! 2139 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 2140 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 2141 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 2142 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 2143 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 2144 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 2145 "handover", "stop-ack";
3785 2146
3786 clocks = <&rpmhcc RPM 2147 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 2148 clock-names = "xo";
3788 2149
3789 power-domains = <&rpm !! 2150 power-domains = <&rpmhpd SM8250_CX>;
3790 2151
3791 memory-region = <&cds 2152 memory-region = <&cdsp_mem>;
3792 2153
3793 qcom,qmp = <&aoss_qmp 2154 qcom,qmp = <&aoss_qmp>;
3794 2155
3795 qcom,smem-states = <& 2156 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 2157 qcom,smem-state-names = "stop";
3797 2158
3798 status = "disabled"; 2159 status = "disabled";
3799 2160
3800 glink-edge { 2161 glink-edge {
3801 interrupts-ex 2162 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2163 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2164 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2165 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2166 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2167
3807 label = "cdsp 2168 label = "cdsp";
3808 qcom,remote-p 2169 qcom,remote-pid = <5>;
3809 2170
3810 fastrpc { 2171 fastrpc {
3811 compa 2172 compatible = "qcom,fastrpc";
3812 qcom, 2173 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2174 label = "cdsp";
3814 qcom, <<
3815 #addr 2175 #address-cells = <1>;
3816 #size 2176 #size-cells = <0>;
3817 2177
3818 compu 2178 compute-cb@1 {
3819 2179 compatible = "qcom,fastrpc-compute-cb";
3820 2180 reg = <1>;
3821 2181 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2182 };
3823 2183
3824 compu 2184 compute-cb@2 {
3825 2185 compatible = "qcom,fastrpc-compute-cb";
3826 2186 reg = <2>;
3827 2187 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2188 };
3829 2189
3830 compu 2190 compute-cb@3 {
3831 2191 compatible = "qcom,fastrpc-compute-cb";
3832 2192 reg = <3>;
3833 2193 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2194 };
3835 2195
3836 compu 2196 compute-cb@4 {
3837 2197 compatible = "qcom,fastrpc-compute-cb";
3838 2198 reg = <4>;
3839 2199 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2200 };
3841 2201
3842 compu 2202 compute-cb@5 {
3843 2203 compatible = "qcom,fastrpc-compute-cb";
3844 2204 reg = <5>;
3845 2205 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2206 };
3847 2207
3848 compu 2208 compute-cb@6 {
3849 2209 compatible = "qcom,fastrpc-compute-cb";
3850 2210 reg = <6>;
3851 2211 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2212 };
3853 2213
3854 compu 2214 compute-cb@7 {
3855 2215 compatible = "qcom,fastrpc-compute-cb";
3856 2216 reg = <7>;
3857 2217 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2218 };
3859 2219
3860 compu 2220 compute-cb@8 {
3861 2221 compatible = "qcom,fastrpc-compute-cb";
3862 2222 reg = <8>;
3863 2223 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2224 };
3865 2225
3866 /* no 2226 /* note: secure cb9 in downstream */
3867 }; 2227 };
3868 }; 2228 };
3869 }; 2229 };
3870 2230
>> 2231 sound: sound {
>> 2232 };
>> 2233
3871 usb_1_hsphy: phy@88e3000 { 2234 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2235 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2236 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2237 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2238 status = "disabled";
3876 #phy-cells = <0>; 2239 #phy-cells = <0>;
3877 2240
3878 clocks = <&rpmhcc RPM 2241 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2242 clock-names = "ref";
3880 2243
3881 resets = <&gcc GCC_QU 2244 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2245 };
3883 2246
3884 usb_2_hsphy: phy@88e4000 { 2247 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2248 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2249 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2250 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2251 status = "disabled";
3889 #phy-cells = <0>; 2252 #phy-cells = <0>;
3890 2253
3891 clocks = <&rpmhcc RPM 2254 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2255 clock-names = "ref";
3893 2256
3894 resets = <&gcc GCC_QU 2257 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2258 };
3896 2259
3897 usb_1_qmpphy: phy@88e8000 { !! 2260 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2261 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2262 reg = <0 0x088e9000 0 0x200>,
>> 2263 <0 0x088e8000 0 0x40>,
>> 2264 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2265 status = "disabled";
>> 2266 #address-cells = <2>;
>> 2267 #size-cells = <2>;
>> 2268 ranges;
3901 2269
3902 clocks = <&gcc GCC_US 2270 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2271 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2272 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2273 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2274
3911 resets = <&gcc GCC_US 2275 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2276 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2277 reset-names = "phy", "common";
3914 2278
3915 #clock-cells = <1>; !! 2279 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2280 reg = <0 0x088e9200 0 0x200>,
3917 !! 2281 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2282 <0 0x088e9c00 0 0x400>,
3919 !! 2283 <0 0x088e9600 0 0x200>,
3920 ports { !! 2284 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2285 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2286 #clock-cells = <0>;
3923 !! 2287 #phy-cells = <0>;
3924 port@0 { !! 2288 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2289 clock-names = "pipe0";
3926 usb_1 !! 2290 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2291 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2292
3940 usb_1 !! 2293 dp_phy: dp-phy@88ea200 {
3941 }; !! 2294 reg = <0 0x088ea200 0 0x200>,
>> 2295 <0 0x088ea400 0 0x200>,
>> 2296 <0 0x088eac00 0 0x400>,
>> 2297 <0 0x088ea600 0 0x200>,
>> 2298 <0 0x088ea800 0 0x200>,
>> 2299 <0 0x088eaa00 0 0x100>;
>> 2300 #phy-cells = <0>;
>> 2301 #clock-cells = <1>;
>> 2302 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 2303 clock-names = "pipe0";
>> 2304 clock-output-names = "usb3_phy_pipe_clk_src";
3942 }; 2305 };
3943 }; 2306 };
3944 2307
3945 usb_2_qmpphy: phy@88eb000 { 2308 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2309 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2310 reg = <0 0x088eb000 0 0x200>;
>> 2311 status = "disabled";
>> 2312 #address-cells = <2>;
>> 2313 #size-cells = <2>;
>> 2314 ranges;
3948 2315
3949 clocks = <&gcc GCC_US 2316 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2317 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2318 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2319 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2320 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2321
3961 resets = <&gcc GCC_US !! 2322 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2323 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2324 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2325
3966 status = "disabled"; !! 2326 usb_2_ssphy: phy@88eb200 {
>> 2327 reg = <0 0x088eb200 0 0x200>,
>> 2328 <0 0x088eb400 0 0x200>,
>> 2329 <0 0x088eb800 0 0x800>;
>> 2330 #clock-cells = <0>;
>> 2331 #phy-cells = <0>;
>> 2332 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2333 clock-names = "pipe0";
>> 2334 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2335 };
3967 }; 2336 };
3968 2337
3969 sdhc_2: mmc@8804000 { !! 2338 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2339 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2340 reg = <0 0x08804000 0 0x1000>;
3972 2341
3973 interrupts = <GIC_SPI 2342 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2343 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2344 interrupt-names = "hc_irq", "pwr_irq";
3976 2345
3977 clocks = <&gcc GCC_SD 2346 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2347 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2348 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2349 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2350 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2351 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2352 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2353 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2354 operating-points-v2 = <&sdhc2_opp_table>;
3986 2355
3987 status = "disabled"; 2356 status = "disabled";
3988 2357
3989 sdhc2_opp_table: opp- !! 2358 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2359 compatible = "operating-points-v2";
3991 2360
3992 opp-19200000 2361 opp-19200000 {
3993 opp-h 2362 opp-hz = /bits/ 64 <19200000>;
3994 requi 2363 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2364 };
3996 2365
3997 opp-50000000 2366 opp-50000000 {
3998 opp-h 2367 opp-hz = /bits/ 64 <50000000>;
3999 requi 2368 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2369 };
4001 2370
4002 opp-100000000 2371 opp-100000000 {
4003 opp-h 2372 opp-hz = /bits/ 64 <100000000>;
4004 requi 2373 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2374 };
4006 2375
4007 opp-202000000 2376 opp-202000000 {
4008 opp-h 2377 opp-hz = /bits/ 64 <202000000>;
4009 requi 2378 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2379 };
4011 }; 2380 };
4012 }; 2381 };
4013 2382
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2383 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2384 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2385 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2386 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2387 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2388 };
4142 2389
4143 gem_noc: interconnect@9100000 2390 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2391 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2392 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2393 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2394 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2395 };
4149 2396
4150 npu_noc: interconnect@9990000 2397 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2398 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2399 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2400 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2401 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2402 };
4156 2403
4157 usb_1: usb@a6f8800 { 2404 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2405 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2406 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2407 status = "disabled";
4161 #address-cells = <2>; 2408 #address-cells = <2>;
4162 #size-cells = <2>; 2409 #size-cells = <2>;
4163 ranges; 2410 ranges;
4164 dma-ranges; 2411 dma-ranges;
4165 2412
4166 clocks = <&gcc GCC_CF 2413 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 2414 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 2415 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 2416 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2417 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 2418 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 2419 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 2420 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 2421
4179 assigned-clocks = <&g 2422 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 2423 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 2424 assigned-clock-rates = <19200000>, <200000000>;
4182 2425
4183 interrupts-extended = !! 2426 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 2427 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 2428 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 2429 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 2430 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 2431 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 2432
4194 power-domains = <&gcc 2433 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 2434
4197 resets = <&gcc GCC_US 2435 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 2436
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 2437 usb_1_dwc3: usb@a600000 {
4204 compatible = 2438 compatible = "snps,dwc3";
4205 reg = <0 0x0a 2439 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 2440 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 2441 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 2442 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 2443 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 2444 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 2445 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 2446 };
4233 }; 2447 };
4234 2448
4235 system-cache-controller@92000 2449 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 2450 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 2451 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 2452 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 2453 };
4243 2454
4244 usb_2: usb@a8f8800 { 2455 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 2456 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 2457 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 2458 status = "disabled";
4248 #address-cells = <2>; 2459 #address-cells = <2>;
4249 #size-cells = <2>; 2460 #size-cells = <2>;
4250 ranges; 2461 ranges;
4251 dma-ranges; 2462 dma-ranges;
4252 2463
4253 clocks = <&gcc GCC_CF 2464 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 2465 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 2466 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 2467 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2468 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 2469 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 2470 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 2471 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 2472
4266 assigned-clocks = <&g 2473 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 2474 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 2475 assigned-clock-rates = <19200000>, <200000000>;
4269 2476
4270 interrupts-extended = !! 2477 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 2478 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 2479 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 2480 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 2481 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 2482 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 2483
4281 power-domains = <&gcc 2484 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 2485
4284 resets = <&gcc GCC_US 2486 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 2487
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 2488 usb_2_dwc3: usb@a800000 {
4291 compatible = 2489 compatible = "snps,dwc3";
4292 reg = <0 0x0a 2490 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 2491 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 2492 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 2493 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 2494 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 2495 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 2496 phy-names = "usb2-phy", "usb3-phy";
4299 }; 2497 };
4300 }; 2498 };
4301 2499
4302 venus: video-codec@aa00000 { 2500 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 2501 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 2502 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 2503 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 2504 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 2505 <&videocc MVS0_GDSC>,
4308 <&rpm !! 2506 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 2507 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 2508 operating-points-v2 = <&venus_opp_table>;
4311 2509
4312 clocks = <&gcc GCC_VI 2510 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 2511 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 2512 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 2513 clock-names = "iface", "core", "vcodec0_core";
4316 2514
4317 interconnects = <&gem !! 2515 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 2516 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 2517 interconnect-names = "cpu-cfg", "video-mem";
4320 2518
4321 iommus = <&apps_smmu 2519 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 2520 memory-region = <&video_mem>;
4323 2521
4324 resets = <&gcc GCC_VI 2522 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 2523 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 2524 reset-names = "bus", "core";
4327 2525
4328 status = "disabled"; 2526 status = "disabled";
4329 2527
4330 video-decoder { 2528 video-decoder {
4331 compatible = 2529 compatible = "venus-decoder";
4332 }; 2530 };
4333 2531
4334 video-encoder { 2532 video-encoder {
4335 compatible = 2533 compatible = "venus-encoder";
4336 }; 2534 };
4337 2535
4338 venus_opp_table: opp- !! 2536 venus_opp_table: venus-opp-table {
4339 compatible = 2537 compatible = "operating-points-v2";
4340 2538
4341 opp-720000000 2539 opp-720000000 {
4342 opp-h 2540 opp-hz = /bits/ 64 <720000000>;
4343 requi 2541 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 2542 };
4345 2543
4346 opp-101400000 2544 opp-1014000000 {
4347 opp-h 2545 opp-hz = /bits/ 64 <1014000000>;
4348 requi 2546 required-opps = <&rpmhpd_opp_svs>;
4349 }; 2547 };
4350 2548
4351 opp-109800000 2549 opp-1098000000 {
4352 opp-h 2550 opp-hz = /bits/ 64 <1098000000>;
4353 requi 2551 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 2552 };
4355 2553
4356 opp-133200000 2554 opp-1332000000 {
4357 opp-h 2555 opp-hz = /bits/ 64 <1332000000>;
4358 requi 2556 required-opps = <&rpmhpd_opp_nom>;
4359 }; 2557 };
4360 }; 2558 };
4361 }; 2559 };
4362 2560
4363 videocc: clock-controller@abf 2561 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 2562 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 2563 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 2564 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 2565 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 2566 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 2567 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 2568 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 2569 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 2570 #clock-cells = <1>;
4373 #reset-cells = <1>; 2571 #reset-cells = <1>;
4374 #power-domain-cells = 2572 #power-domain-cells = <1>;
4375 }; 2573 };
4376 2574
4377 cci0: cci@ac4f000 { !! 2575 mdss: mdss@ae00000 {
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm 2576 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 2577 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 2578 reg-names = "mdss";
4661 2579
4662 interconnects = <&mms !! 2580 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 2581 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 2582 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 2583
4666 power-domains = <&dis 2584 power-domains = <&dispcc MDSS_GDSC>;
4667 2585
4668 clocks = <&dispcc DIS 2586 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 2587 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 2588 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 2589 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 2590 clock-names = "iface", "bus", "nrt_bus", "core";
4673 2591
>> 2592 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 2593 assigned-clock-rates = <460000000>;
>> 2594
4674 interrupts = <GIC_SPI 2595 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 2596 interrupt-controller;
4676 #interrupt-cells = <1 2597 #interrupt-cells = <1>;
4677 2598
4678 iommus = <&apps_smmu 2599 iommus = <&apps_smmu 0x820 0x402>;
4679 2600
4680 status = "disabled"; 2601 status = "disabled";
4681 2602
4682 #address-cells = <2>; 2603 #address-cells = <2>;
4683 #size-cells = <2>; 2604 #size-cells = <2>;
4684 ranges; 2605 ranges;
4685 2606
4686 mdss_mdp: display-con !! 2607 mdss_mdp: mdp@ae01000 {
4687 compatible = 2608 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 2609 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 2610 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 2611 reg-names = "mdp", "vbif";
4691 2612
4692 clocks = <&di 2613 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 2614 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 2615 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 2616 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 2617 clock-names = "iface", "bus", "core", "vsync";
4697 2618
4698 assigned-cloc !! 2619 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 2620 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 2621 assigned-clock-rates = <460000000>,
>> 2622 <19200000>;
4700 2623
4701 operating-poi 2624 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 2625 power-domains = <&rpmhpd SM8250_MMCX>;
4703 2626
4704 interrupt-par 2627 interrupt-parent = <&mdss>;
4705 interrupts = !! 2628 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4706 2629
4707 ports { 2630 ports {
4708 #addr 2631 #address-cells = <1>;
4709 #size 2632 #size-cells = <0>;
4710 2633
4711 port@ 2634 port@0 {
4712 2635 reg = <0>;
4713 2636 dpu_intf1_out: endpoint {
4714 !! 2637 remote-endpoint = <&dsi0_in>;
4715 2638 };
4716 }; 2639 };
4717 2640
4718 port@ 2641 port@1 {
4719 2642 reg = <1>;
4720 2643 dpu_intf2_out: endpoint {
4721 !! 2644 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 2645 };
4731 }; 2646 };
4732 }; 2647 };
4733 2648
4734 mdp_opp_table !! 2649 mdp_opp_table: mdp-opp-table {
4735 compa 2650 compatible = "operating-points-v2";
4736 2651
4737 opp-2 2652 opp-200000000 {
4738 2653 opp-hz = /bits/ 64 <200000000>;
4739 2654 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 2655 };
4741 2656
4742 opp-3 2657 opp-300000000 {
4743 2658 opp-hz = /bits/ 64 <300000000>;
4744 2659 required-opps = <&rpmhpd_opp_svs>;
4745 }; 2660 };
4746 2661
4747 opp-3 2662 opp-345000000 {
4748 2663 opp-hz = /bits/ 64 <345000000>;
4749 2664 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 2665 };
4751 2666
4752 opp-4 2667 opp-460000000 {
4753 2668 opp-hz = /bits/ 64 <460000000>;
4754 2669 required-opps = <&rpmhpd_opp_nom>;
4755 }; 2670 };
4756 }; 2671 };
4757 }; 2672 };
4758 2673
4759 mdss_dp: displayport- !! 2674 dsi0: dsi@ae94000 {
4760 compatible = !! 2675 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 2676 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 2677 reg-names = "dsi_ctrl";
4843 2678
4844 interrupt-par 2679 interrupt-parent = <&mdss>;
4845 interrupts = !! 2680 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 2681
4847 clocks = <&di 2682 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 2683 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 2684 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 2685 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 2686 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 2687 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 2688 clock-names = "byte",
4854 2689 "byte_intf",
4855 2690 "pixel",
4856 2691 "core",
4857 2692 "iface",
4858 2693 "bus";
4859 2694
4860 assigned-cloc 2695 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 2696 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 2697
4863 operating-poi 2698 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 2699 power-domains = <&rpmhpd SM8250_MMCX>;
4865 2700
4866 phys = <&mdss !! 2701 phys = <&dsi0_phy>;
>> 2702 phy-names = "dsi";
4867 2703
4868 status = "dis 2704 status = "disabled";
4869 2705
4870 #address-cell 2706 #address-cells = <1>;
4871 #size-cells = 2707 #size-cells = <0>;
4872 2708
4873 ports { 2709 ports {
4874 #addr 2710 #address-cells = <1>;
4875 #size 2711 #size-cells = <0>;
4876 2712
4877 port@ 2713 port@0 {
4878 2714 reg = <0>;
4879 !! 2715 dsi0_in: endpoint {
4880 2716 remote-endpoint = <&dpu_intf1_out>;
4881 2717 };
4882 }; 2718 };
4883 2719
4884 port@ 2720 port@1 {
4885 2721 reg = <1>;
4886 !! 2722 dsi0_out: endpoint {
4887 2723 };
4888 }; 2724 };
4889 }; 2725 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 2726 };
4910 2727
4911 mdss_dsi0_phy: phy@ae !! 2728 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 2729 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 2730 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 2731 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 2732 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 2733 reg-names = "dsi_phy",
4917 " 2734 "dsi_phy_lane",
4918 " 2735 "dsi_pll";
4919 2736
4920 #clock-cells 2737 #clock-cells = <1>;
4921 #phy-cells = 2738 #phy-cells = <0>;
4922 2739
4923 clocks = <&di 2740 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 2741 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 2742 clock-names = "iface", "ref";
4926 2743
4927 status = "dis 2744 status = "disabled";
4928 }; 2745 };
4929 2746
4930 mdss_dsi1: dsi@ae9600 !! 2747 dsi1: dsi@ae96000 {
4931 compatible = !! 2748 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 2749 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 2750 reg-names = "dsi_ctrl";
4935 2751
4936 interrupt-par 2752 interrupt-parent = <&mdss>;
4937 interrupts = !! 2753 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 2754
4939 clocks = <&di 2755 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 2756 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 2757 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 2758 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 2759 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 2760 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 2761 clock-names = "byte",
4946 2762 "byte_intf",
4947 2763 "pixel",
4948 2764 "core",
4949 2765 "iface",
4950 2766 "bus";
4951 2767
4952 assigned-cloc 2768 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 2769 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 2770
4955 operating-poi 2771 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 2772 power-domains = <&rpmhpd SM8250_MMCX>;
4957 2773
4958 phys = <&mdss !! 2774 phys = <&dsi1_phy>;
>> 2775 phy-names = "dsi";
4959 2776
4960 status = "dis 2777 status = "disabled";
4961 2778
4962 #address-cell 2779 #address-cells = <1>;
4963 #size-cells = 2780 #size-cells = <0>;
4964 2781
4965 ports { 2782 ports {
4966 #addr 2783 #address-cells = <1>;
4967 #size 2784 #size-cells = <0>;
4968 2785
4969 port@ 2786 port@0 {
4970 2787 reg = <0>;
4971 !! 2788 dsi1_in: endpoint {
4972 2789 remote-endpoint = <&dpu_intf2_out>;
4973 2790 };
4974 }; 2791 };
4975 2792
4976 port@ 2793 port@1 {
4977 2794 reg = <1>;
4978 !! 2795 dsi1_out: endpoint {
4979 2796 };
4980 }; 2797 };
4981 }; 2798 };
4982 }; 2799 };
4983 2800
4984 mdss_dsi1_phy: phy@ae !! 2801 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 2802 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 2803 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 2804 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 2805 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 2806 reg-names = "dsi_phy",
4990 " 2807 "dsi_phy_lane",
4991 " 2808 "dsi_pll";
4992 2809
4993 #clock-cells 2810 #clock-cells = <1>;
4994 #phy-cells = 2811 #phy-cells = <0>;
4995 2812
4996 clocks = <&di 2813 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 2814 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 2815 clock-names = "iface", "ref";
4999 2816
5000 status = "dis 2817 status = "disabled";
>> 2818
>> 2819 dsi_opp_table: dsi-opp-table {
>> 2820 compatible = "operating-points-v2";
>> 2821
>> 2822 opp-187500000 {
>> 2823 opp-hz = /bits/ 64 <187500000>;
>> 2824 required-opps = <&rpmhpd_opp_low_svs>;
>> 2825 };
>> 2826
>> 2827 opp-300000000 {
>> 2828 opp-hz = /bits/ 64 <300000000>;
>> 2829 required-opps = <&rpmhpd_opp_svs>;
>> 2830 };
>> 2831
>> 2832 opp-358000000 {
>> 2833 opp-hz = /bits/ 64 <358000000>;
>> 2834 required-opps = <&rpmhpd_opp_svs_l1>;
>> 2835 };
>> 2836 };
5001 }; 2837 };
5002 }; 2838 };
5003 2839
5004 dispcc: clock-controller@af00 2840 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 2841 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 2842 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 2843 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 2844 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 2845 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 2846 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 2847 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 2848 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 2849 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 2850 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 2851 <&dp_phy 1>;
5016 clock-names = "bi_tcx 2852 clock-names = "bi_tcxo",
5017 "dsi0_p 2853 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 2854 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 2855 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 2856 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 2857 "dp_phy_pll_link_clk",
5022 "dp_phy 2858 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 2859 #clock-cells = <1>;
5024 #reset-cells = <1>; 2860 #reset-cells = <1>;
5025 #power-domain-cells = 2861 #power-domain-cells = <1>;
5026 }; 2862 };
5027 2863
5028 pdc: interrupt-controller@b22 2864 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 2865 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 2866 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 2867 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 2868 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 2869 #interrupt-cells = <2>;
5034 interrupt-parent = <& 2870 interrupt-parent = <&intc>;
5035 interrupt-controller; 2871 interrupt-controller;
5036 }; 2872 };
5037 2873
5038 tsens0: thermal-sensor@c26300 2874 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 2875 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 2876 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 2877 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 2878 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 2879 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 2880 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 2881 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 2882 #thermal-sensor-cells = <1>;
5047 }; 2883 };
5048 2884
5049 tsens1: thermal-sensor@c26500 2885 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 2886 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 2887 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 2888 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 2889 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 2890 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 2891 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 2892 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 2893 #thermal-sensor-cells = <1>;
5058 }; 2894 };
5059 2895
5060 aoss_qmp: power-management@c3 !! 2896 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm !! 2897 compatible = "qcom,sm8250-aoss-qmp";
5062 reg = <0 0x0c300000 0 2898 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 2899 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 2900 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 2901 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 2902 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 2903 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 2904
5069 #clock-cells = <0>; 2905 #clock-cells = <0>;
5070 }; 2906 };
5071 2907
5072 sram@c3f0000 { 2908 sram@c3f0000 {
5073 compatible = "qcom,rp 2909 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 2910 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 2911 };
5076 2912
5077 spmi_bus: spmi@c440000 { 2913 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 2914 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 2915 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 2916 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 2917 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 2918 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 2919 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 2920 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 2921 interrupt-names = "periph_irq";
5086 interrupts-extended = 2922 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 2923 qcom,ee = <0>;
5088 qcom,channel = <0>; 2924 qcom,channel = <0>;
5089 #address-cells = <2>; 2925 #address-cells = <2>;
5090 #size-cells = <0>; 2926 #size-cells = <0>;
5091 interrupt-controller; 2927 interrupt-controller;
5092 #interrupt-cells = <4 2928 #interrupt-cells = <4>;
5093 }; 2929 };
5094 2930
5095 tlmm: pinctrl@f100000 { 2931 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 2932 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 2933 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 2934 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 2935 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 2936 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 2937 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 2938 gpio-controller;
5103 #gpio-cells = <2>; 2939 #gpio-cells = <2>;
5104 interrupt-controller; 2940 interrupt-controller;
5105 #interrupt-cells = <2 2941 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 2942 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 2943 wakeup-parent = <&pdc>;
5108 2944
5109 cam2_default: cam2-de !! 2945 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 2946 sclk {
5111 pins !! 2947 pins = "gpio138";
5112 funct !! 2948 function = "mi2s0_sck";
5113 drive !! 2949 drive-strength = <8>;
5114 bias- 2950 bias-disable;
5115 }; 2951 };
5116 2952
5117 mclk-pins { !! 2953 ws {
5118 pins !! 2954 pins = "gpio141";
5119 funct !! 2955 function = "mi2s0_ws";
5120 drive !! 2956 drive-strength = <8>;
>> 2957 output-high;
>> 2958 };
>> 2959
>> 2960 data0 {
>> 2961 pins = "gpio139";
>> 2962 function = "mi2s0_data0";
>> 2963 drive-strength = <8>;
5121 bias- 2964 bias-disable;
>> 2965 output-high;
>> 2966 };
>> 2967
>> 2968 data1 {
>> 2969 pins = "gpio140";
>> 2970 function = "mi2s0_data1";
>> 2971 drive-strength = <8>;
>> 2972 output-high;
5122 }; 2973 };
5123 }; 2974 };
5124 2975
5125 cam2_suspend: cam2-su !! 2976 qup_i2c0_default: qup-i2c0-default {
5126 rst-pins { !! 2977 mux {
5127 pins !! 2978 pins = "gpio28", "gpio29";
5128 funct !! 2979 function = "qup0";
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; 2980 };
5133 2981
5134 mclk-pins { !! 2982 config {
5135 pins !! 2983 pins = "gpio28", "gpio29";
5136 funct <<
5137 drive 2984 drive-strength = <2>;
5138 bias- 2985 bias-disable;
5139 }; 2986 };
5140 }; 2987 };
5141 2988
5142 cci0_default: cci0-de !! 2989 qup_i2c1_default: qup-i2c1-default {
5143 cci0_i2c0_def !! 2990 pinmux {
5144 /* SD !! 2991 pins = "gpio4", "gpio5";
5145 pins !! 2992 function = "qup1";
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; 2993 };
5151 2994
5152 cci0_i2c1_def !! 2995 config {
5153 /* SD !! 2996 pins = "gpio4", "gpio5";
5154 pins !! 2997 drive-strength = <2>;
5155 funct !! 2998 bias-disable;
5156 <<
5157 bias- <<
5158 drive <<
5159 }; 2999 };
5160 }; 3000 };
5161 3001
5162 cci0_sleep: cci0-slee !! 3002 qup_i2c2_default: qup-i2c2-default {
5163 cci0_i2c0_sle !! 3003 mux {
5164 /* SD !! 3004 pins = "gpio115", "gpio116";
5165 pins !! 3005 function = "qup2";
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; 3006 };
5171 3007
5172 cci0_i2c1_sle !! 3008 config {
5173 /* SD !! 3009 pins = "gpio115", "gpio116";
5174 pins !! 3010 drive-strength = <2>;
5175 funct !! 3011 bias-disable;
5176 <<
5177 drive <<
5178 bias- <<
5179 }; 3012 };
5180 }; 3013 };
5181 3014
5182 cci1_default: cci1-de !! 3015 qup_i2c3_default: qup-i2c3-default {
5183 cci1_i2c0_def !! 3016 mux {
5184 /* SD !! 3017 pins = "gpio119", "gpio120";
5185 pins !! 3018 function = "qup3";
5186 funct !! 3019 };
5187 3020
5188 bias- !! 3021 config {
5189 drive !! 3022 pins = "gpio119", "gpio120";
>> 3023 drive-strength = <2>;
>> 3024 bias-disable;
5190 }; 3025 };
>> 3026 };
5191 3027
5192 cci1_i2c1_def !! 3028 qup_i2c4_default: qup-i2c4-default {
5193 /* SD !! 3029 mux {
5194 pins !! 3030 pins = "gpio8", "gpio9";
5195 funct !! 3031 function = "qup4";
>> 3032 };
5196 3033
5197 bias- !! 3034 config {
5198 drive !! 3035 pins = "gpio8", "gpio9";
>> 3036 drive-strength = <2>;
>> 3037 bias-disable;
5199 }; 3038 };
5200 }; 3039 };
5201 3040
5202 cci1_sleep: cci1-slee !! 3041 qup_i2c5_default: qup-i2c5-default {
5203 cci1_i2c0_sle !! 3042 mux {
5204 /* SD !! 3043 pins = "gpio12", "gpio13";
5205 pins !! 3044 function = "qup5";
5206 funct !! 3045 };
5207 3046
5208 bias- !! 3047 config {
5209 drive !! 3048 pins = "gpio12", "gpio13";
>> 3049 drive-strength = <2>;
>> 3050 bias-disable;
5210 }; 3051 };
>> 3052 };
5211 3053
5212 cci1_i2c1_sle !! 3054 qup_i2c6_default: qup-i2c6-default {
5213 /* SD !! 3055 mux {
5214 pins !! 3056 pins = "gpio16", "gpio17";
5215 funct !! 3057 function = "qup6";
>> 3058 };
5216 3059
5217 bias- !! 3060 config {
5218 drive !! 3061 pins = "gpio16", "gpio17";
>> 3062 drive-strength = <2>;
>> 3063 bias-disable;
5219 }; 3064 };
5220 }; 3065 };
5221 3066
5222 pri_mi2s_active: pri- !! 3067 qup_i2c7_default: qup-i2c7-default {
5223 sclk-pins { !! 3068 mux {
5224 pins !! 3069 pins = "gpio20", "gpio21";
5225 funct !! 3070 function = "qup7";
5226 drive !! 3071 };
>> 3072
>> 3073 config {
>> 3074 pins = "gpio20", "gpio21";
>> 3075 drive-strength = <2>;
5227 bias- 3076 bias-disable;
5228 }; 3077 };
>> 3078 };
5229 3079
5230 ws-pins { !! 3080 qup_i2c8_default: qup-i2c8-default {
5231 pins !! 3081 mux {
5232 funct !! 3082 pins = "gpio24", "gpio25";
5233 drive !! 3083 function = "qup8";
5234 outpu <<
5235 }; 3084 };
5236 3085
5237 data0-pins { !! 3086 config {
5238 pins !! 3087 pins = "gpio24", "gpio25";
5239 funct !! 3088 drive-strength = <2>;
5240 drive <<
5241 bias- 3089 bias-disable;
5242 outpu <<
5243 }; 3090 };
>> 3091 };
5244 3092
5245 data1-pins { !! 3093 qup_i2c9_default: qup-i2c9-default {
5246 pins !! 3094 mux {
5247 funct !! 3095 pins = "gpio125", "gpio126";
5248 drive !! 3096 function = "qup9";
5249 outpu <<
5250 }; 3097 };
5251 }; <<
5252 3098
5253 qup_i2c0_default: qup !! 3099 config {
5254 pins = "gpio2 !! 3100 pins = "gpio125", "gpio126";
5255 function = "q !! 3101 drive-strength = <2>;
5256 drive-strengt !! 3102 bias-disable;
5257 bias-disable; !! 3103 };
5258 }; 3104 };
5259 3105
5260 qup_i2c1_default: qup !! 3106 qup_i2c10_default: qup-i2c10-default {
5261 pins = "gpio4 !! 3107 mux {
5262 function = "q !! 3108 pins = "gpio129", "gpio130";
5263 drive-strengt !! 3109 function = "qup10";
5264 bias-disable; !! 3110 };
5265 }; <<
5266 3111
5267 qup_i2c2_default: qup !! 3112 config {
5268 pins = "gpio1 !! 3113 pins = "gpio129", "gpio130";
5269 function = "q !! 3114 drive-strength = <2>;
5270 drive-strengt !! 3115 bias-disable;
5271 bias-disable; !! 3116 };
5272 }; 3117 };
5273 3118
5274 qup_i2c3_default: qup !! 3119 qup_i2c11_default: qup-i2c11-default {
5275 pins = "gpio1 !! 3120 mux {
5276 function = "q !! 3121 pins = "gpio60", "gpio61";
5277 drive-strengt !! 3122 function = "qup11";
5278 bias-disable; !! 3123 };
5279 }; <<
5280 3124
5281 qup_i2c4_default: qup !! 3125 config {
5282 pins = "gpio8 !! 3126 pins = "gpio60", "gpio61";
5283 function = "q !! 3127 drive-strength = <2>;
5284 drive-strengt !! 3128 bias-disable;
5285 bias-disable; !! 3129 };
5286 }; 3130 };
5287 3131
5288 qup_i2c5_default: qup !! 3132 qup_i2c12_default: qup-i2c12-default {
5289 pins = "gpio1 !! 3133 mux {
5290 function = "q !! 3134 pins = "gpio32", "gpio33";
5291 drive-strengt !! 3135 function = "qup12";
5292 bias-disable; !! 3136 };
5293 }; <<
5294 3137
5295 qup_i2c6_default: qup !! 3138 config {
5296 pins = "gpio1 !! 3139 pins = "gpio32", "gpio33";
5297 function = "q !! 3140 drive-strength = <2>;
5298 drive-strengt !! 3141 bias-disable;
5299 bias-disable; !! 3142 };
5300 }; 3143 };
5301 3144
5302 qup_i2c7_default: qup !! 3145 qup_i2c13_default: qup-i2c13-default {
5303 pins = "gpio2 !! 3146 mux {
5304 function = "q !! 3147 pins = "gpio36", "gpio37";
5305 drive-strengt !! 3148 function = "qup13";
5306 bias-disable; !! 3149 };
5307 }; <<
5308 3150
5309 qup_i2c8_default: qup !! 3151 config {
5310 pins = "gpio2 !! 3152 pins = "gpio36", "gpio37";
5311 function = "q !! 3153 drive-strength = <2>;
5312 drive-strengt !! 3154 bias-disable;
5313 bias-disable; !! 3155 };
5314 }; 3156 };
5315 3157
5316 qup_i2c9_default: qup !! 3158 qup_i2c14_default: qup-i2c14-default {
5317 pins = "gpio1 !! 3159 mux {
5318 function = "q !! 3160 pins = "gpio40", "gpio41";
5319 drive-strengt !! 3161 function = "qup14";
5320 bias-disable; !! 3162 };
5321 }; <<
5322 3163
5323 qup_i2c10_default: qu !! 3164 config {
5324 pins = "gpio1 !! 3165 pins = "gpio40", "gpio41";
5325 function = "q !! 3166 drive-strength = <2>;
5326 drive-strengt !! 3167 bias-disable;
5327 bias-disable; !! 3168 };
5328 }; 3169 };
5329 3170
5330 qup_i2c11_default: qu !! 3171 qup_i2c15_default: qup-i2c15-default {
5331 pins = "gpio6 !! 3172 mux {
5332 function = "q !! 3173 pins = "gpio44", "gpio45";
5333 drive-strengt !! 3174 function = "qup15";
5334 bias-disable; !! 3175 };
5335 }; <<
5336 3176
5337 qup_i2c12_default: qu !! 3177 config {
5338 pins = "gpio3 !! 3178 pins = "gpio44", "gpio45";
5339 function = "q !! 3179 drive-strength = <2>;
5340 drive-strengt !! 3180 bias-disable;
5341 bias-disable; !! 3181 };
5342 }; 3182 };
5343 3183
5344 qup_i2c13_default: qu !! 3184 qup_i2c16_default: qup-i2c16-default {
5345 pins = "gpio3 !! 3185 mux {
5346 function = "q !! 3186 pins = "gpio48", "gpio49";
5347 drive-strengt !! 3187 function = "qup16";
5348 bias-disable; !! 3188 };
5349 }; <<
5350 3189
5351 qup_i2c14_default: qu !! 3190 config {
5352 pins = "gpio4 !! 3191 pins = "gpio48", "gpio49";
5353 function = "q !! 3192 drive-strength = <2>;
5354 drive-strengt !! 3193 bias-disable;
5355 bias-disable; !! 3194 };
5356 }; 3195 };
5357 3196
5358 qup_i2c15_default: qu !! 3197 qup_i2c17_default: qup-i2c17-default {
5359 pins = "gpio4 !! 3198 mux {
5360 function = "q !! 3199 pins = "gpio52", "gpio53";
5361 drive-strengt !! 3200 function = "qup17";
5362 bias-disable; !! 3201 };
5363 }; <<
5364 3202
5365 qup_i2c16_default: qu !! 3203 config {
5366 pins = "gpio4 !! 3204 pins = "gpio52", "gpio53";
5367 function = "q !! 3205 drive-strength = <2>;
5368 drive-strengt !! 3206 bias-disable;
5369 bias-disable; !! 3207 };
5370 }; 3208 };
5371 3209
5372 qup_i2c17_default: qu !! 3210 qup_i2c18_default: qup-i2c18-default {
5373 pins = "gpio5 !! 3211 mux {
5374 function = "q !! 3212 pins = "gpio56", "gpio57";
5375 drive-strengt !! 3213 function = "qup18";
5376 bias-disable; !! 3214 };
5377 }; <<
5378 3215
5379 qup_i2c18_default: qu !! 3216 config {
5380 pins = "gpio5 !! 3217 pins = "gpio56", "gpio57";
5381 function = "q !! 3218 drive-strength = <2>;
5382 drive-strengt !! 3219 bias-disable;
5383 bias-disable; !! 3220 };
5384 }; 3221 };
5385 3222
5386 qup_i2c19_default: qu !! 3223 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 3224 mux {
5388 function = "q !! 3225 pins = "gpio0", "gpio1";
5389 drive-strengt !! 3226 function = "qup19";
5390 bias-disable; !! 3227 };
>> 3228
>> 3229 config {
>> 3230 pins = "gpio0", "gpio1";
>> 3231 drive-strength = <2>;
>> 3232 bias-disable;
>> 3233 };
5391 }; 3234 };
5392 3235
5393 qup_spi0_cs: qup-spi0 !! 3236 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 3237 pins = "gpio31";
5395 function = "q 3238 function = "qup0";
5396 }; 3239 };
5397 3240
5398 qup_spi0_cs_gpio: qup !! 3241 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 3242 pins = "gpio31";
5400 function = "g 3243 function = "gpio";
5401 }; 3244 };
5402 3245
5403 qup_spi0_data_clk: qu !! 3246 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 3247 pins = "gpio28", "gpio29",
5405 "gpio3 3248 "gpio30";
5406 function = "q 3249 function = "qup0";
5407 }; 3250 };
5408 3251
5409 qup_spi1_cs: qup-spi1 !! 3252 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 3253 pins = "gpio7";
5411 function = "q 3254 function = "qup1";
5412 }; 3255 };
5413 3256
5414 qup_spi1_cs_gpio: qup !! 3257 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 3258 pins = "gpio7";
5416 function = "g 3259 function = "gpio";
5417 }; 3260 };
5418 3261
5419 qup_spi1_data_clk: qu !! 3262 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 3263 pins = "gpio4", "gpio5",
5421 "gpio6 3264 "gpio6";
5422 function = "q 3265 function = "qup1";
5423 }; 3266 };
5424 3267
5425 qup_spi2_cs: qup-spi2 !! 3268 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 3269 pins = "gpio118";
5427 function = "q 3270 function = "qup2";
5428 }; 3271 };
5429 3272
5430 qup_spi2_cs_gpio: qup !! 3273 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 3274 pins = "gpio118";
5432 function = "g 3275 function = "gpio";
5433 }; 3276 };
5434 3277
5435 qup_spi2_data_clk: qu !! 3278 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 3279 pins = "gpio115", "gpio116",
5437 "gpio1 3280 "gpio117";
5438 function = "q 3281 function = "qup2";
5439 }; 3282 };
5440 3283
5441 qup_spi3_cs: qup-spi3 !! 3284 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 3285 pins = "gpio122";
5443 function = "q 3286 function = "qup3";
5444 }; 3287 };
5445 3288
5446 qup_spi3_cs_gpio: qup !! 3289 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 3290 pins = "gpio122";
5448 function = "g 3291 function = "gpio";
5449 }; 3292 };
5450 3293
5451 qup_spi3_data_clk: qu !! 3294 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 3295 pins = "gpio119", "gpio120",
5453 "gpio1 3296 "gpio121";
5454 function = "q 3297 function = "qup3";
5455 }; 3298 };
5456 3299
5457 qup_spi4_cs: qup-spi4 !! 3300 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 3301 pins = "gpio11";
5459 function = "q 3302 function = "qup4";
5460 }; 3303 };
5461 3304
5462 qup_spi4_cs_gpio: qup !! 3305 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 3306 pins = "gpio11";
5464 function = "g 3307 function = "gpio";
5465 }; 3308 };
5466 3309
5467 qup_spi4_data_clk: qu !! 3310 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 3311 pins = "gpio8", "gpio9",
5469 "gpio1 3312 "gpio10";
5470 function = "q 3313 function = "qup4";
5471 }; 3314 };
5472 3315
5473 qup_spi5_cs: qup-spi5 !! 3316 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 3317 pins = "gpio15";
5475 function = "q 3318 function = "qup5";
5476 }; 3319 };
5477 3320
5478 qup_spi5_cs_gpio: qup !! 3321 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 3322 pins = "gpio15";
5480 function = "g 3323 function = "gpio";
5481 }; 3324 };
5482 3325
5483 qup_spi5_data_clk: qu !! 3326 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 3327 pins = "gpio12", "gpio13",
5485 "gpio1 3328 "gpio14";
5486 function = "q 3329 function = "qup5";
5487 }; 3330 };
5488 3331
5489 qup_spi6_cs: qup-spi6 !! 3332 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 3333 pins = "gpio19";
5491 function = "q 3334 function = "qup6";
5492 }; 3335 };
5493 3336
5494 qup_spi6_cs_gpio: qup !! 3337 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 3338 pins = "gpio19";
5496 function = "g 3339 function = "gpio";
5497 }; 3340 };
5498 3341
5499 qup_spi6_data_clk: qu !! 3342 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 3343 pins = "gpio16", "gpio17",
5501 "gpio1 3344 "gpio18";
5502 function = "q 3345 function = "qup6";
5503 }; 3346 };
5504 3347
5505 qup_spi7_cs: qup-spi7 !! 3348 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 3349 pins = "gpio23";
5507 function = "q 3350 function = "qup7";
5508 }; 3351 };
5509 3352
5510 qup_spi7_cs_gpio: qup !! 3353 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 3354 pins = "gpio23";
5512 function = "g 3355 function = "gpio";
5513 }; 3356 };
5514 3357
5515 qup_spi7_data_clk: qu !! 3358 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 3359 pins = "gpio20", "gpio21",
5517 "gpio2 3360 "gpio22";
5518 function = "q 3361 function = "qup7";
5519 }; 3362 };
5520 3363
5521 qup_spi8_cs: qup-spi8 !! 3364 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 3365 pins = "gpio27";
5523 function = "q 3366 function = "qup8";
5524 }; 3367 };
5525 3368
5526 qup_spi8_cs_gpio: qup !! 3369 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 3370 pins = "gpio27";
5528 function = "g 3371 function = "gpio";
5529 }; 3372 };
5530 3373
5531 qup_spi8_data_clk: qu !! 3374 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 3375 pins = "gpio24", "gpio25",
5533 "gpio2 3376 "gpio26";
5534 function = "q 3377 function = "qup8";
5535 }; 3378 };
5536 3379
5537 qup_spi9_cs: qup-spi9 !! 3380 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 3381 pins = "gpio128";
5539 function = "q 3382 function = "qup9";
5540 }; 3383 };
5541 3384
5542 qup_spi9_cs_gpio: qup !! 3385 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 3386 pins = "gpio128";
5544 function = "g 3387 function = "gpio";
5545 }; 3388 };
5546 3389
5547 qup_spi9_data_clk: qu !! 3390 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 3391 pins = "gpio125", "gpio126",
5549 "gpio1 3392 "gpio127";
5550 function = "q 3393 function = "qup9";
5551 }; 3394 };
5552 3395
5553 qup_spi10_cs: qup-spi !! 3396 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 3397 pins = "gpio132";
5555 function = "q 3398 function = "qup10";
5556 }; 3399 };
5557 3400
5558 qup_spi10_cs_gpio: qu !! 3401 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 3402 pins = "gpio132";
5560 function = "g 3403 function = "gpio";
5561 }; 3404 };
5562 3405
5563 qup_spi10_data_clk: q !! 3406 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 3407 pins = "gpio129", "gpio130",
5565 "gpio1 3408 "gpio131";
5566 function = "q 3409 function = "qup10";
5567 }; 3410 };
5568 3411
5569 qup_spi11_cs: qup-spi !! 3412 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 3413 pins = "gpio63";
5571 function = "q 3414 function = "qup11";
5572 }; 3415 };
5573 3416
5574 qup_spi11_cs_gpio: qu !! 3417 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 3418 pins = "gpio63";
5576 function = "g 3419 function = "gpio";
5577 }; 3420 };
5578 3421
5579 qup_spi11_data_clk: q !! 3422 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 3423 pins = "gpio60", "gpio61",
5581 "gpio6 3424 "gpio62";
5582 function = "q 3425 function = "qup11";
5583 }; 3426 };
5584 3427
5585 qup_spi12_cs: qup-spi !! 3428 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 3429 pins = "gpio35";
5587 function = "q 3430 function = "qup12";
5588 }; 3431 };
5589 3432
5590 qup_spi12_cs_gpio: qu !! 3433 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 3434 pins = "gpio35";
5592 function = "g 3435 function = "gpio";
5593 }; 3436 };
5594 3437
5595 qup_spi12_data_clk: q !! 3438 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 3439 pins = "gpio32", "gpio33",
5597 "gpio3 3440 "gpio34";
5598 function = "q 3441 function = "qup12";
5599 }; 3442 };
5600 3443
5601 qup_spi13_cs: qup-spi !! 3444 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 3445 pins = "gpio39";
5603 function = "q 3446 function = "qup13";
5604 }; 3447 };
5605 3448
5606 qup_spi13_cs_gpio: qu !! 3449 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 3450 pins = "gpio39";
5608 function = "g 3451 function = "gpio";
5609 }; 3452 };
5610 3453
5611 qup_spi13_data_clk: q !! 3454 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 3455 pins = "gpio36", "gpio37",
5613 "gpio3 3456 "gpio38";
5614 function = "q 3457 function = "qup13";
5615 }; 3458 };
5616 3459
5617 qup_spi14_cs: qup-spi !! 3460 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 3461 pins = "gpio43";
5619 function = "q 3462 function = "qup14";
5620 }; 3463 };
5621 3464
5622 qup_spi14_cs_gpio: qu !! 3465 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 3466 pins = "gpio43";
5624 function = "g 3467 function = "gpio";
5625 }; 3468 };
5626 3469
5627 qup_spi14_data_clk: q !! 3470 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 3471 pins = "gpio40", "gpio41",
5629 "gpio4 3472 "gpio42";
5630 function = "q 3473 function = "qup14";
5631 }; 3474 };
5632 3475
5633 qup_spi15_cs: qup-spi !! 3476 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 3477 pins = "gpio47";
5635 function = "q 3478 function = "qup15";
5636 }; 3479 };
5637 3480
5638 qup_spi15_cs_gpio: qu !! 3481 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 3482 pins = "gpio47";
5640 function = "g 3483 function = "gpio";
5641 }; 3484 };
5642 3485
5643 qup_spi15_data_clk: q !! 3486 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 3487 pins = "gpio44", "gpio45",
5645 "gpio4 3488 "gpio46";
5646 function = "q 3489 function = "qup15";
5647 }; 3490 };
5648 3491
5649 qup_spi16_cs: qup-spi !! 3492 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 3493 pins = "gpio51";
5651 function = "q 3494 function = "qup16";
5652 }; 3495 };
5653 3496
5654 qup_spi16_cs_gpio: qu !! 3497 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 3498 pins = "gpio51";
5656 function = "g 3499 function = "gpio";
5657 }; 3500 };
5658 3501
5659 qup_spi16_data_clk: q !! 3502 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 3503 pins = "gpio48", "gpio49",
5661 "gpio5 3504 "gpio50";
5662 function = "q 3505 function = "qup16";
5663 }; 3506 };
5664 3507
5665 qup_spi17_cs: qup-spi !! 3508 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 3509 pins = "gpio55";
5667 function = "q 3510 function = "qup17";
5668 }; 3511 };
5669 3512
5670 qup_spi17_cs_gpio: qu !! 3513 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 3514 pins = "gpio55";
5672 function = "g 3515 function = "gpio";
5673 }; 3516 };
5674 3517
5675 qup_spi17_data_clk: q !! 3518 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 3519 pins = "gpio52", "gpio53",
5677 "gpio5 3520 "gpio54";
5678 function = "q 3521 function = "qup17";
5679 }; 3522 };
5680 3523
5681 qup_spi18_cs: qup-spi !! 3524 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 3525 pins = "gpio59";
5683 function = "q 3526 function = "qup18";
5684 }; 3527 };
5685 3528
5686 qup_spi18_cs_gpio: qu !! 3529 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 3530 pins = "gpio59";
5688 function = "g 3531 function = "gpio";
5689 }; 3532 };
5690 3533
5691 qup_spi18_data_clk: q !! 3534 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 3535 pins = "gpio56", "gpio57",
5693 "gpio5 3536 "gpio58";
5694 function = "q 3537 function = "qup18";
5695 }; 3538 };
5696 3539
5697 qup_spi19_cs: qup-spi !! 3540 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 3541 pins = "gpio3";
5699 function = "q 3542 function = "qup19";
5700 }; 3543 };
5701 3544
5702 qup_spi19_cs_gpio: qu !! 3545 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 3546 pins = "gpio3";
5704 function = "g 3547 function = "gpio";
5705 }; 3548 };
5706 3549
5707 qup_spi19_data_clk: q !! 3550 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 3551 pins = "gpio0", "gpio1",
5709 "gpio2 3552 "gpio2";
5710 function = "q 3553 function = "qup19";
5711 }; 3554 };
5712 3555
5713 qup_uart2_default: qu !! 3556 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 3557 mux {
5715 function = "q !! 3558 pins = "gpio117", "gpio118";
>> 3559 function = "qup2";
>> 3560 };
5716 }; 3561 };
5717 3562
5718 qup_uart6_default: qu !! 3563 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 3564 mux {
5720 function = "q !! 3565 pins = "gpio16", "gpio17",
>> 3566 "gpio18", "gpio19";
>> 3567 function = "qup6";
>> 3568 };
5721 }; 3569 };
5722 3570
5723 qup_uart12_default: q !! 3571 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 3572 mux {
5725 function = "q !! 3573 pins = "gpio34", "gpio35";
>> 3574 function = "qup12";
>> 3575 };
5726 }; 3576 };
5727 3577
5728 qup_uart17_default: q !! 3578 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 3579 mux {
5730 function = "q !! 3580 pins = "gpio52", "gpio53",
>> 3581 "gpio54", "gpio55";
>> 3582 function = "qup17";
>> 3583 };
5731 }; 3584 };
5732 3585
5733 qup_uart18_default: q !! 3586 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 3587 mux {
5735 function = "q !! 3588 pins = "gpio58", "gpio59";
>> 3589 function = "qup18";
>> 3590 };
5736 }; 3591 };
5737 3592
5738 tert_mi2s_active: ter !! 3593 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 3594 sck {
5740 pins 3595 pins = "gpio133";
5741 funct 3596 function = "mi2s2_sck";
5742 drive 3597 drive-strength = <8>;
5743 bias- 3598 bias-disable;
5744 }; 3599 };
5745 3600
5746 data0-pins { !! 3601 data0 {
5747 pins 3602 pins = "gpio134";
5748 funct 3603 function = "mi2s2_data0";
5749 drive 3604 drive-strength = <8>;
5750 bias- 3605 bias-disable;
5751 outpu 3606 output-high;
5752 }; 3607 };
5753 3608
5754 ws-pins { !! 3609 ws {
5755 pins 3610 pins = "gpio135";
5756 funct 3611 function = "mi2s2_ws";
5757 drive 3612 drive-strength = <8>;
5758 outpu 3613 output-high;
5759 }; 3614 };
5760 }; 3615 };
5761 3616
5762 sdc2_sleep_state: sdc !! 3617 sdc2_sleep_state: sdc2-sleep {
5763 clk-pins { !! 3618 clk {
5764 pins 3619 pins = "sdc2_clk";
5765 drive 3620 drive-strength = <2>;
5766 bias- 3621 bias-disable;
5767 }; 3622 };
5768 3623
5769 cmd-pins { !! 3624 cmd {
5770 pins 3625 pins = "sdc2_cmd";
5771 drive 3626 drive-strength = <2>;
5772 bias- 3627 bias-pull-up;
5773 }; 3628 };
5774 3629
5775 data-pins { !! 3630 data {
5776 pins 3631 pins = "sdc2_data";
5777 drive 3632 drive-strength = <2>;
5778 bias- 3633 bias-pull-up;
5779 }; 3634 };
5780 }; 3635 };
5781 3636
5782 pcie0_default_state: !! 3637 pcie0_default_state: pcie0-default {
5783 perst-pins { !! 3638 perst {
5784 pins 3639 pins = "gpio79";
5785 funct 3640 function = "gpio";
5786 drive 3641 drive-strength = <2>;
5787 bias- 3642 bias-pull-down;
5788 }; 3643 };
5789 3644
5790 clkreq-pins { !! 3645 clkreq {
5791 pins 3646 pins = "gpio80";
5792 funct 3647 function = "pci_e0";
5793 drive 3648 drive-strength = <2>;
5794 bias- 3649 bias-pull-up;
5795 }; 3650 };
5796 3651
5797 wake-pins { !! 3652 wake {
5798 pins 3653 pins = "gpio81";
5799 funct 3654 function = "gpio";
5800 drive 3655 drive-strength = <2>;
5801 bias- 3656 bias-pull-up;
5802 }; 3657 };
5803 }; 3658 };
5804 3659
5805 pcie1_default_state: !! 3660 pcie1_default_state: pcie1-default {
5806 perst-pins { !! 3661 perst {
5807 pins 3662 pins = "gpio82";
5808 funct 3663 function = "gpio";
5809 drive 3664 drive-strength = <2>;
5810 bias- 3665 bias-pull-down;
5811 }; 3666 };
5812 3667
5813 clkreq-pins { !! 3668 clkreq {
5814 pins 3669 pins = "gpio83";
5815 funct 3670 function = "pci_e1";
5816 drive 3671 drive-strength = <2>;
5817 bias- 3672 bias-pull-up;
5818 }; 3673 };
5819 3674
5820 wake-pins { !! 3675 wake {
5821 pins 3676 pins = "gpio84";
5822 funct 3677 function = "gpio";
5823 drive 3678 drive-strength = <2>;
5824 bias- 3679 bias-pull-up;
5825 }; 3680 };
5826 }; 3681 };
5827 3682
5828 pcie2_default_state: !! 3683 pcie2_default_state: pcie2-default {
5829 perst-pins { !! 3684 perst {
5830 pins 3685 pins = "gpio85";
5831 funct 3686 function = "gpio";
5832 drive 3687 drive-strength = <2>;
5833 bias- 3688 bias-pull-down;
5834 }; 3689 };
5835 3690
5836 clkreq-pins { !! 3691 clkreq {
5837 pins 3692 pins = "gpio86";
5838 funct 3693 function = "pci_e2";
5839 drive 3694 drive-strength = <2>;
5840 bias- 3695 bias-pull-up;
5841 }; 3696 };
5842 3697
5843 wake-pins { !! 3698 wake {
5844 pins 3699 pins = "gpio87";
5845 funct 3700 function = "gpio";
5846 drive 3701 drive-strength = <2>;
5847 bias- 3702 bias-pull-up;
5848 }; 3703 };
5849 }; 3704 };
5850 }; 3705 };
5851 3706
5852 apps_smmu: iommu@15000000 { 3707 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 3708 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 3709 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 3710 #iommu-cells = <2>;
5856 #global-interrupts = 3711 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 3712 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 3713 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 3714 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 3715 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 3716 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 3717 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 3718 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 3719 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 3720 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 3721 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 3722 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 3723 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 3724 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 3725 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 3726 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 3727 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 3728 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 3729 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 3730 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 3731 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 3732 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 3733 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 3734 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 3735 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 3736 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 3737 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 3738 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 3739 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 3740 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 3741 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 3742 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 3743 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 3744 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 3745 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 3746 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 3747 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 3748 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 3749 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 3750 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 3751 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 3752 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 3753 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 3754 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 3755 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 3756 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 3757 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 3758 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 3759 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 3760 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 3761 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 3762 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 3763 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 3764 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 3765 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 3766 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 3767 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 3768 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 3769 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 3770 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 3771 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 3772 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 3773 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 3774 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 3775 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 3776 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 3777 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 3778 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 3779 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 3780 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 3781 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 3782 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 3783 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 3784 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 3785 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 3786 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 3787 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 3788 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 3789 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 3790 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 3791 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 3792 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 3793 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 3794 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 3795 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 3796 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 3797 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 3798 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 3799 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 3800 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 3801 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 3802 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 3803 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 3804 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 3805 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 3806 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 3807 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 3808 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 3809 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 3810 };
5957 3811
5958 adsp: remoteproc@17300000 { 3812 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 3813 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 3814 reg = <0 0x17300000 0 0x100>;
5961 3815
5962 interrupts-extended = !! 3816 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 3817 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 3818 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 3819 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 3820 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 3821 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 3822 "handover", "stop-ack";
5969 3823
5970 clocks = <&rpmhcc RPM 3824 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 3825 clock-names = "xo";
5972 3826
5973 power-domains = <&rpm !! 3827 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 3828 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 3829 power-domain-names = "lcx", "lmx";
5976 3830
5977 memory-region = <&ads 3831 memory-region = <&adsp_mem>;
5978 3832
5979 qcom,qmp = <&aoss_qmp 3833 qcom,qmp = <&aoss_qmp>;
5980 3834
5981 qcom,smem-states = <& 3835 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 3836 qcom,smem-state-names = "stop";
5983 3837
5984 status = "disabled"; 3838 status = "disabled";
5985 3839
5986 glink-edge { 3840 glink-edge {
5987 interrupts-ex 3841 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 3842 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 3843 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 3844 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 3845 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 3846
5993 label = "lpas 3847 label = "lpass";
5994 qcom,remote-p 3848 qcom,remote-pid = <2>;
5995 3849
5996 apr { 3850 apr {
5997 compa 3851 compatible = "qcom,apr-v2";
5998 qcom, 3852 qcom,glink-channels = "apr_audio_svc";
5999 qcom, !! 3853 qcom,apr-domain = <APR_DOMAIN_ADSP>;
6000 #addr 3854 #address-cells = <1>;
6001 #size 3855 #size-cells = <0>;
6002 3856
6003 servi !! 3857 apr-service@3 {
6004 3858 reg = <APR_SVC_ADSP_CORE>;
6005 3859 compatible = "qcom,q6core";
6006 3860 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 3861 };
6008 3862
6009 q6afe !! 3863 q6afe: apr-service@4 {
6010 3864 compatible = "qcom,q6afe";
6011 3865 reg = <APR_SVC_AFE>;
6012 3866 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 3867 q6afedai: dais {
6014 3868 compatible = "qcom,q6afe-dais";
6015 3869 #address-cells = <1>;
6016 3870 #size-cells = <0>;
6017 3871 #sound-dai-cells = <1>;
6018 3872 };
6019 3873
6020 !! 3874 q6afecc: cc {
6021 3875 compatible = "qcom,q6afe-clocks";
6022 3876 #clock-cells = <2>;
6023 3877 };
6024 }; 3878 };
6025 3879
6026 q6asm !! 3880 q6asm: apr-service@7 {
6027 3881 compatible = "qcom,q6asm";
6028 3882 reg = <APR_SVC_ASM>;
6029 3883 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 3884 q6asmdai: dais {
6031 3885 compatible = "qcom,q6asm-dais";
6032 3886 #address-cells = <1>;
6033 3887 #size-cells = <0>;
6034 3888 #sound-dai-cells = <1>;
6035 3889 iommus = <&apps_smmu 0x1801 0x0>;
6036 3890 };
6037 }; 3891 };
6038 3892
6039 q6adm !! 3893 q6adm: apr-service@8 {
6040 3894 compatible = "qcom,q6adm";
6041 3895 reg = <APR_SVC_ADM>;
6042 3896 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 3897 q6routing: routing {
6044 3898 compatible = "qcom,q6adm-routing";
6045 3899 #sound-dai-cells = <0>;
6046 3900 };
6047 }; 3901 };
6048 }; 3902 };
6049 3903
6050 fastrpc { 3904 fastrpc {
6051 compa 3905 compatible = "qcom,fastrpc";
6052 qcom, 3906 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 3907 label = "adsp";
6054 qcom, <<
6055 #addr 3908 #address-cells = <1>;
6056 #size 3909 #size-cells = <0>;
6057 3910
6058 compu 3911 compute-cb@3 {
6059 3912 compatible = "qcom,fastrpc-compute-cb";
6060 3913 reg = <3>;
6061 3914 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 3915 };
6063 3916
6064 compu 3917 compute-cb@4 {
6065 3918 compatible = "qcom,fastrpc-compute-cb";
6066 3919 reg = <4>;
6067 3920 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 3921 };
6069 3922
6070 compu 3923 compute-cb@5 {
6071 3924 compatible = "qcom,fastrpc-compute-cb";
6072 3925 reg = <5>;
6073 3926 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 3927 };
6075 }; 3928 };
6076 }; 3929 };
6077 }; 3930 };
6078 3931
6079 intc: interrupt-controller@17 3932 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 3933 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 3934 #interrupt-cells = <3>;
6082 interrupt-controller; 3935 interrupt-controller;
6083 reg = <0x0 0x17a00000 3936 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 3937 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 3938 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 3939 };
6087 3940
6088 watchdog@17c10000 { 3941 watchdog@17c10000 {
6089 compatible = "qcom,ap 3942 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 3943 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 3944 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 3945 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 3946 };
6094 3947
6095 timer@17c20000 { 3948 timer@17c20000 {
6096 #address-cells = <1>; !! 3949 #address-cells = <2>;
6097 #size-cells = <1>; !! 3950 #size-cells = <2>;
6098 ranges = <0 0 0 0x200 !! 3951 ranges;
6099 compatible = "arm,arm 3952 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 3953 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 3954 clock-frequency = <19200000>;
6102 3955
6103 frame@17c21000 { 3956 frame@17c21000 {
6104 frame-number 3957 frame-number = <0>;
6105 interrupts = 3958 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 3959 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 !! 3960 reg = <0x0 0x17c21000 0x0 0x1000>,
6108 <0x17c2 !! 3961 <0x0 0x17c22000 0x0 0x1000>;
6109 }; 3962 };
6110 3963
6111 frame@17c23000 { 3964 frame@17c23000 {
6112 frame-number 3965 frame-number = <1>;
6113 interrupts = 3966 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 !! 3967 reg = <0x0 0x17c23000 0x0 0x1000>;
6115 status = "dis 3968 status = "disabled";
6116 }; 3969 };
6117 3970
6118 frame@17c25000 { 3971 frame@17c25000 {
6119 frame-number 3972 frame-number = <2>;
6120 interrupts = 3973 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 !! 3974 reg = <0x0 0x17c25000 0x0 0x1000>;
6122 status = "dis 3975 status = "disabled";
6123 }; 3976 };
6124 3977
6125 frame@17c27000 { 3978 frame@17c27000 {
6126 frame-number 3979 frame-number = <3>;
6127 interrupts = 3980 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 !! 3981 reg = <0x0 0x17c27000 0x0 0x1000>;
6129 status = "dis 3982 status = "disabled";
6130 }; 3983 };
6131 3984
6132 frame@17c29000 { 3985 frame@17c29000 {
6133 frame-number 3986 frame-number = <4>;
6134 interrupts = 3987 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 !! 3988 reg = <0x0 0x17c29000 0x0 0x1000>;
6136 status = "dis 3989 status = "disabled";
6137 }; 3990 };
6138 3991
6139 frame@17c2b000 { 3992 frame@17c2b000 {
6140 frame-number 3993 frame-number = <5>;
6141 interrupts = 3994 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 !! 3995 reg = <0x0 0x17c2b000 0x0 0x1000>;
6143 status = "dis 3996 status = "disabled";
6144 }; 3997 };
6145 3998
6146 frame@17c2d000 { 3999 frame@17c2d000 {
6147 frame-number 4000 frame-number = <6>;
6148 interrupts = 4001 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 !! 4002 reg = <0x0 0x17c2d000 0x0 0x1000>;
6150 status = "dis 4003 status = "disabled";
6151 }; 4004 };
6152 }; 4005 };
6153 4006
6154 apps_rsc: rsc@18200000 { 4007 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 4008 label = "apps_rsc";
6156 compatible = "qcom,rp 4009 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 4010 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 4011 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 4012 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 4013 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 4014 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 4015 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 4016 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 4017 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 4018 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 4019 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 4020 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 4021
6170 rpmhcc: clock-control 4022 rpmhcc: clock-controller {
6171 compatible = 4023 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 4024 #clock-cells = <1>;
6173 clock-names = 4025 clock-names = "xo";
6174 clocks = <&xo 4026 clocks = <&xo_board>;
6175 }; 4027 };
6176 4028
6177 rpmhpd: power-control 4029 rpmhpd: power-controller {
6178 compatible = 4030 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 4031 #power-domain-cells = <1>;
6180 operating-poi 4032 operating-points-v2 = <&rpmhpd_opp_table>;
6181 4033
6182 rpmhpd_opp_ta 4034 rpmhpd_opp_table: opp-table {
6183 compa 4035 compatible = "operating-points-v2";
6184 4036
6185 rpmhp 4037 rpmhpd_opp_ret: opp1 {
6186 4038 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 4039 };
6188 4040
6189 rpmhp 4041 rpmhpd_opp_min_svs: opp2 {
6190 4042 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 4043 };
6192 4044
6193 rpmhp 4045 rpmhpd_opp_low_svs: opp3 {
6194 4046 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 4047 };
6196 4048
6197 rpmhp 4049 rpmhpd_opp_svs: opp4 {
6198 4050 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 4051 };
6200 4052
6201 rpmhp 4053 rpmhpd_opp_svs_l1: opp5 {
6202 4054 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 4055 };
6204 4056
6205 rpmhp 4057 rpmhpd_opp_nom: opp6 {
6206 4058 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 4059 };
6208 4060
6209 rpmhp 4061 rpmhpd_opp_nom_l1: opp7 {
6210 4062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 4063 };
6212 4064
6213 rpmhp 4065 rpmhpd_opp_nom_l2: opp8 {
6214 4066 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 4067 };
6216 4068
6217 rpmhp 4069 rpmhpd_opp_turbo: opp9 {
6218 4070 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 4071 };
6220 4072
6221 rpmhp 4073 rpmhpd_opp_turbo_l1: opp10 {
6222 4074 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 4075 };
6224 }; 4076 };
6225 }; 4077 };
6226 4078
6227 apps_bcm_voter: bcm-v !! 4079 apps_bcm_voter: bcm_voter {
6228 compatible = 4080 compatible = "qcom,bcm-voter";
6229 }; 4081 };
6230 }; 4082 };
6231 4083
6232 epss_l3: interconnect@1859000 4084 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 4085 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 4086 reg = <0 0x18590000 0 0x1000>;
6235 4087
6236 clocks = <&rpmhcc RPM 4088 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 4089 clock-names = "xo", "alternate";
6238 4090
6239 #interconnect-cells = 4091 #interconnect-cells = <1>;
6240 }; 4092 };
6241 4093
6242 cpufreq_hw: cpufreq@18591000 4094 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 4095 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 4096 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 4097 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 4098 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 4099 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 4100 "freq-domain2";
6249 4101
6250 clocks = <&rpmhcc RPM 4102 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 4103 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI !! 4104
6253 <GIC_SPI <<
6254 <GIC_SPI <<
6255 interrupt-names = "dc <<
6256 #freq-domain-cells = 4105 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 4106 };
6259 }; 4107 };
6260 4108
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 4109 timer {
6265 compatible = "arm,armv8-timer 4110 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 4111 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 4112 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 4113 <GIC_PPI 14
6269 (GIC_CPU_MASK 4114 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 4115 <GIC_PPI 11
6271 (GIC_CPU_MASK 4116 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 4117 <GIC_PPI 10
6273 (GIC_CPU_MASK 4118 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 4119 };
6275 4120
6276 thermal-zones { 4121 thermal-zones {
6277 cpu0-thermal { 4122 cpu0-thermal {
6278 polling-delay-passive 4123 polling-delay-passive = <250>;
>> 4124 polling-delay = <1000>;
6279 4125
6280 thermal-sensors = <&t 4126 thermal-sensors = <&tsens0 1>;
6281 4127
6282 trips { 4128 trips {
6283 cpu0_alert0: 4129 cpu0_alert0: trip-point0 {
6284 tempe 4130 temperature = <90000>;
6285 hyste 4131 hysteresis = <2000>;
6286 type 4132 type = "passive";
6287 }; 4133 };
6288 4134
6289 cpu0_alert1: 4135 cpu0_alert1: trip-point1 {
6290 tempe 4136 temperature = <95000>;
6291 hyste 4137 hysteresis = <2000>;
6292 type 4138 type = "passive";
6293 }; 4139 };
6294 4140
6295 cpu0_crit: cp !! 4141 cpu0_crit: cpu_crit {
6296 tempe 4142 temperature = <110000>;
6297 hyste 4143 hysteresis = <1000>;
6298 type 4144 type = "critical";
6299 }; 4145 };
6300 }; 4146 };
6301 4147
6302 cooling-maps { 4148 cooling-maps {
6303 map0 { 4149 map0 {
6304 trip 4150 trip = <&cpu0_alert0>;
6305 cooli 4151 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 4152 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 4153 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 4154 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 4155 };
6310 map1 { 4156 map1 {
6311 trip 4157 trip = <&cpu0_alert1>;
6312 cooli 4158 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 4159 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 4160 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 4161 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 4162 };
6317 }; 4163 };
6318 }; 4164 };
6319 4165
6320 cpu1-thermal { 4166 cpu1-thermal {
6321 polling-delay-passive 4167 polling-delay-passive = <250>;
>> 4168 polling-delay = <1000>;
6322 4169
6323 thermal-sensors = <&t 4170 thermal-sensors = <&tsens0 2>;
6324 4171
6325 trips { 4172 trips {
6326 cpu1_alert0: 4173 cpu1_alert0: trip-point0 {
6327 tempe 4174 temperature = <90000>;
6328 hyste 4175 hysteresis = <2000>;
6329 type 4176 type = "passive";
6330 }; 4177 };
6331 4178
6332 cpu1_alert1: 4179 cpu1_alert1: trip-point1 {
6333 tempe 4180 temperature = <95000>;
6334 hyste 4181 hysteresis = <2000>;
6335 type 4182 type = "passive";
6336 }; 4183 };
6337 4184
6338 cpu1_crit: cp !! 4185 cpu1_crit: cpu_crit {
6339 tempe 4186 temperature = <110000>;
6340 hyste 4187 hysteresis = <1000>;
6341 type 4188 type = "critical";
6342 }; 4189 };
6343 }; 4190 };
6344 4191
6345 cooling-maps { 4192 cooling-maps {
6346 map0 { 4193 map0 {
6347 trip 4194 trip = <&cpu1_alert0>;
6348 cooli 4195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 4196 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 4197 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 4198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 4199 };
6353 map1 { 4200 map1 {
6354 trip 4201 trip = <&cpu1_alert1>;
6355 cooli 4202 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 4203 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 4204 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 4205 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 4206 };
6360 }; 4207 };
6361 }; 4208 };
6362 4209
6363 cpu2-thermal { 4210 cpu2-thermal {
6364 polling-delay-passive 4211 polling-delay-passive = <250>;
>> 4212 polling-delay = <1000>;
6365 4213
6366 thermal-sensors = <&t 4214 thermal-sensors = <&tsens0 3>;
6367 4215
6368 trips { 4216 trips {
6369 cpu2_alert0: 4217 cpu2_alert0: trip-point0 {
6370 tempe 4218 temperature = <90000>;
6371 hyste 4219 hysteresis = <2000>;
6372 type 4220 type = "passive";
6373 }; 4221 };
6374 4222
6375 cpu2_alert1: 4223 cpu2_alert1: trip-point1 {
6376 tempe 4224 temperature = <95000>;
6377 hyste 4225 hysteresis = <2000>;
6378 type 4226 type = "passive";
6379 }; 4227 };
6380 4228
6381 cpu2_crit: cp !! 4229 cpu2_crit: cpu_crit {
6382 tempe 4230 temperature = <110000>;
6383 hyste 4231 hysteresis = <1000>;
6384 type 4232 type = "critical";
6385 }; 4233 };
6386 }; 4234 };
6387 4235
6388 cooling-maps { 4236 cooling-maps {
6389 map0 { 4237 map0 {
6390 trip 4238 trip = <&cpu2_alert0>;
6391 cooli 4239 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 4240 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 4241 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 4242 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 4243 };
6396 map1 { 4244 map1 {
6397 trip 4245 trip = <&cpu2_alert1>;
6398 cooli 4246 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 4247 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 4248 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 4249 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 4250 };
6403 }; 4251 };
6404 }; 4252 };
6405 4253
6406 cpu3-thermal { 4254 cpu3-thermal {
6407 polling-delay-passive 4255 polling-delay-passive = <250>;
>> 4256 polling-delay = <1000>;
6408 4257
6409 thermal-sensors = <&t 4258 thermal-sensors = <&tsens0 4>;
6410 4259
6411 trips { 4260 trips {
6412 cpu3_alert0: 4261 cpu3_alert0: trip-point0 {
6413 tempe 4262 temperature = <90000>;
6414 hyste 4263 hysteresis = <2000>;
6415 type 4264 type = "passive";
6416 }; 4265 };
6417 4266
6418 cpu3_alert1: 4267 cpu3_alert1: trip-point1 {
6419 tempe 4268 temperature = <95000>;
6420 hyste 4269 hysteresis = <2000>;
6421 type 4270 type = "passive";
6422 }; 4271 };
6423 4272
6424 cpu3_crit: cp !! 4273 cpu3_crit: cpu_crit {
6425 tempe 4274 temperature = <110000>;
6426 hyste 4275 hysteresis = <1000>;
6427 type 4276 type = "critical";
6428 }; 4277 };
6429 }; 4278 };
6430 4279
6431 cooling-maps { 4280 cooling-maps {
6432 map0 { 4281 map0 {
6433 trip 4282 trip = <&cpu3_alert0>;
6434 cooli 4283 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 4284 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 4285 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 4286 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 4287 };
6439 map1 { 4288 map1 {
6440 trip 4289 trip = <&cpu3_alert1>;
6441 cooli 4290 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 4291 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 4292 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 4293 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 4294 };
6446 }; 4295 };
6447 }; 4296 };
6448 4297
6449 cpu4-top-thermal { 4298 cpu4-top-thermal {
6450 polling-delay-passive 4299 polling-delay-passive = <250>;
>> 4300 polling-delay = <1000>;
6451 4301
6452 thermal-sensors = <&t 4302 thermal-sensors = <&tsens0 7>;
6453 4303
6454 trips { 4304 trips {
6455 cpu4_top_aler 4305 cpu4_top_alert0: trip-point0 {
6456 tempe 4306 temperature = <90000>;
6457 hyste 4307 hysteresis = <2000>;
6458 type 4308 type = "passive";
6459 }; 4309 };
6460 4310
6461 cpu4_top_aler 4311 cpu4_top_alert1: trip-point1 {
6462 tempe 4312 temperature = <95000>;
6463 hyste 4313 hysteresis = <2000>;
6464 type 4314 type = "passive";
6465 }; 4315 };
6466 4316
6467 cpu4_top_crit !! 4317 cpu4_top_crit: cpu_crit {
6468 tempe 4318 temperature = <110000>;
6469 hyste 4319 hysteresis = <1000>;
6470 type 4320 type = "critical";
6471 }; 4321 };
6472 }; 4322 };
6473 4323
6474 cooling-maps { 4324 cooling-maps {
6475 map0 { 4325 map0 {
6476 trip 4326 trip = <&cpu4_top_alert0>;
6477 cooli 4327 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 4328 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 4329 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 4330 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 4331 };
6482 map1 { 4332 map1 {
6483 trip 4333 trip = <&cpu4_top_alert1>;
6484 cooli 4334 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 4335 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 4336 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 4337 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 4338 };
6489 }; 4339 };
6490 }; 4340 };
6491 4341
6492 cpu5-top-thermal { 4342 cpu5-top-thermal {
6493 polling-delay-passive 4343 polling-delay-passive = <250>;
>> 4344 polling-delay = <1000>;
6494 4345
6495 thermal-sensors = <&t 4346 thermal-sensors = <&tsens0 8>;
6496 4347
6497 trips { 4348 trips {
6498 cpu5_top_aler 4349 cpu5_top_alert0: trip-point0 {
6499 tempe 4350 temperature = <90000>;
6500 hyste 4351 hysteresis = <2000>;
6501 type 4352 type = "passive";
6502 }; 4353 };
6503 4354
6504 cpu5_top_aler 4355 cpu5_top_alert1: trip-point1 {
6505 tempe 4356 temperature = <95000>;
6506 hyste 4357 hysteresis = <2000>;
6507 type 4358 type = "passive";
6508 }; 4359 };
6509 4360
6510 cpu5_top_crit !! 4361 cpu5_top_crit: cpu_crit {
6511 tempe 4362 temperature = <110000>;
6512 hyste 4363 hysteresis = <1000>;
6513 type 4364 type = "critical";
6514 }; 4365 };
6515 }; 4366 };
6516 4367
6517 cooling-maps { 4368 cooling-maps {
6518 map0 { 4369 map0 {
6519 trip 4370 trip = <&cpu5_top_alert0>;
6520 cooli 4371 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 4372 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 4373 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 4374 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4375 };
6525 map1 { 4376 map1 {
6526 trip 4377 trip = <&cpu5_top_alert1>;
6527 cooli 4378 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4379 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4380 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4381 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4382 };
6532 }; 4383 };
6533 }; 4384 };
6534 4385
6535 cpu6-top-thermal { 4386 cpu6-top-thermal {
6536 polling-delay-passive 4387 polling-delay-passive = <250>;
>> 4388 polling-delay = <1000>;
6537 4389
6538 thermal-sensors = <&t 4390 thermal-sensors = <&tsens0 9>;
6539 4391
6540 trips { 4392 trips {
6541 cpu6_top_aler 4393 cpu6_top_alert0: trip-point0 {
6542 tempe 4394 temperature = <90000>;
6543 hyste 4395 hysteresis = <2000>;
6544 type 4396 type = "passive";
6545 }; 4397 };
6546 4398
6547 cpu6_top_aler 4399 cpu6_top_alert1: trip-point1 {
6548 tempe 4400 temperature = <95000>;
6549 hyste 4401 hysteresis = <2000>;
6550 type 4402 type = "passive";
6551 }; 4403 };
6552 4404
6553 cpu6_top_crit !! 4405 cpu6_top_crit: cpu_crit {
6554 tempe 4406 temperature = <110000>;
6555 hyste 4407 hysteresis = <1000>;
6556 type 4408 type = "critical";
6557 }; 4409 };
6558 }; 4410 };
6559 4411
6560 cooling-maps { 4412 cooling-maps {
6561 map0 { 4413 map0 {
6562 trip 4414 trip = <&cpu6_top_alert0>;
6563 cooli 4415 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 4416 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 4417 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 4418 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 4419 };
6568 map1 { 4420 map1 {
6569 trip 4421 trip = <&cpu6_top_alert1>;
6570 cooli 4422 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 4423 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 4424 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 4425 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 4426 };
6575 }; 4427 };
6576 }; 4428 };
6577 4429
6578 cpu7-top-thermal { 4430 cpu7-top-thermal {
6579 polling-delay-passive 4431 polling-delay-passive = <250>;
>> 4432 polling-delay = <1000>;
6580 4433
6581 thermal-sensors = <&t 4434 thermal-sensors = <&tsens0 10>;
6582 4435
6583 trips { 4436 trips {
6584 cpu7_top_aler 4437 cpu7_top_alert0: trip-point0 {
6585 tempe 4438 temperature = <90000>;
6586 hyste 4439 hysteresis = <2000>;
6587 type 4440 type = "passive";
6588 }; 4441 };
6589 4442
6590 cpu7_top_aler 4443 cpu7_top_alert1: trip-point1 {
6591 tempe 4444 temperature = <95000>;
6592 hyste 4445 hysteresis = <2000>;
6593 type 4446 type = "passive";
6594 }; 4447 };
6595 4448
6596 cpu7_top_crit !! 4449 cpu7_top_crit: cpu_crit {
6597 tempe 4450 temperature = <110000>;
6598 hyste 4451 hysteresis = <1000>;
6599 type 4452 type = "critical";
6600 }; 4453 };
6601 }; 4454 };
6602 4455
6603 cooling-maps { 4456 cooling-maps {
6604 map0 { 4457 map0 {
6605 trip 4458 trip = <&cpu7_top_alert0>;
6606 cooli 4459 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 4460 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 4461 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 4462 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 4463 };
6611 map1 { 4464 map1 {
6612 trip 4465 trip = <&cpu7_top_alert1>;
6613 cooli 4466 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 4467 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 4468 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 4469 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 4470 };
6618 }; 4471 };
6619 }; 4472 };
6620 4473
6621 cpu4-bottom-thermal { 4474 cpu4-bottom-thermal {
6622 polling-delay-passive 4475 polling-delay-passive = <250>;
>> 4476 polling-delay = <1000>;
6623 4477
6624 thermal-sensors = <&t 4478 thermal-sensors = <&tsens0 11>;
6625 4479
6626 trips { 4480 trips {
6627 cpu4_bottom_a 4481 cpu4_bottom_alert0: trip-point0 {
6628 tempe 4482 temperature = <90000>;
6629 hyste 4483 hysteresis = <2000>;
6630 type 4484 type = "passive";
6631 }; 4485 };
6632 4486
6633 cpu4_bottom_a 4487 cpu4_bottom_alert1: trip-point1 {
6634 tempe 4488 temperature = <95000>;
6635 hyste 4489 hysteresis = <2000>;
6636 type 4490 type = "passive";
6637 }; 4491 };
6638 4492
6639 cpu4_bottom_c !! 4493 cpu4_bottom_crit: cpu_crit {
6640 tempe 4494 temperature = <110000>;
6641 hyste 4495 hysteresis = <1000>;
6642 type 4496 type = "critical";
6643 }; 4497 };
6644 }; 4498 };
6645 4499
6646 cooling-maps { 4500 cooling-maps {
6647 map0 { 4501 map0 {
6648 trip 4502 trip = <&cpu4_bottom_alert0>;
6649 cooli 4503 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 4504 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 4505 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 4506 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 4507 };
6654 map1 { 4508 map1 {
6655 trip 4509 trip = <&cpu4_bottom_alert1>;
6656 cooli 4510 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 4511 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 4512 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 4513 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 4514 };
6661 }; 4515 };
6662 }; 4516 };
6663 4517
6664 cpu5-bottom-thermal { 4518 cpu5-bottom-thermal {
6665 polling-delay-passive 4519 polling-delay-passive = <250>;
>> 4520 polling-delay = <1000>;
6666 4521
6667 thermal-sensors = <&t 4522 thermal-sensors = <&tsens0 12>;
6668 4523
6669 trips { 4524 trips {
6670 cpu5_bottom_a 4525 cpu5_bottom_alert0: trip-point0 {
6671 tempe 4526 temperature = <90000>;
6672 hyste 4527 hysteresis = <2000>;
6673 type 4528 type = "passive";
6674 }; 4529 };
6675 4530
6676 cpu5_bottom_a 4531 cpu5_bottom_alert1: trip-point1 {
6677 tempe 4532 temperature = <95000>;
6678 hyste 4533 hysteresis = <2000>;
6679 type 4534 type = "passive";
6680 }; 4535 };
6681 4536
6682 cpu5_bottom_c !! 4537 cpu5_bottom_crit: cpu_crit {
6683 tempe 4538 temperature = <110000>;
6684 hyste 4539 hysteresis = <1000>;
6685 type 4540 type = "critical";
6686 }; 4541 };
6687 }; 4542 };
6688 4543
6689 cooling-maps { 4544 cooling-maps {
6690 map0 { 4545 map0 {
6691 trip 4546 trip = <&cpu5_bottom_alert0>;
6692 cooli 4547 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 4548 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 4549 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 4550 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 4551 };
6697 map1 { 4552 map1 {
6698 trip 4553 trip = <&cpu5_bottom_alert1>;
6699 cooli 4554 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 4555 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 4556 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 4557 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 4558 };
6704 }; 4559 };
6705 }; 4560 };
6706 4561
6707 cpu6-bottom-thermal { 4562 cpu6-bottom-thermal {
6708 polling-delay-passive 4563 polling-delay-passive = <250>;
>> 4564 polling-delay = <1000>;
6709 4565
6710 thermal-sensors = <&t 4566 thermal-sensors = <&tsens0 13>;
6711 4567
6712 trips { 4568 trips {
6713 cpu6_bottom_a 4569 cpu6_bottom_alert0: trip-point0 {
6714 tempe 4570 temperature = <90000>;
6715 hyste 4571 hysteresis = <2000>;
6716 type 4572 type = "passive";
6717 }; 4573 };
6718 4574
6719 cpu6_bottom_a 4575 cpu6_bottom_alert1: trip-point1 {
6720 tempe 4576 temperature = <95000>;
6721 hyste 4577 hysteresis = <2000>;
6722 type 4578 type = "passive";
6723 }; 4579 };
6724 4580
6725 cpu6_bottom_c !! 4581 cpu6_bottom_crit: cpu_crit {
6726 tempe 4582 temperature = <110000>;
6727 hyste 4583 hysteresis = <1000>;
6728 type 4584 type = "critical";
6729 }; 4585 };
6730 }; 4586 };
6731 4587
6732 cooling-maps { 4588 cooling-maps {
6733 map0 { 4589 map0 {
6734 trip 4590 trip = <&cpu6_bottom_alert0>;
6735 cooli 4591 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 4592 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 4593 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 4594 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 4595 };
6740 map1 { 4596 map1 {
6741 trip 4597 trip = <&cpu6_bottom_alert1>;
6742 cooli 4598 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 4599 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 4600 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 4601 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 4602 };
6747 }; 4603 };
6748 }; 4604 };
6749 4605
6750 cpu7-bottom-thermal { 4606 cpu7-bottom-thermal {
6751 polling-delay-passive 4607 polling-delay-passive = <250>;
>> 4608 polling-delay = <1000>;
6752 4609
6753 thermal-sensors = <&t 4610 thermal-sensors = <&tsens0 14>;
6754 4611
6755 trips { 4612 trips {
6756 cpu7_bottom_a 4613 cpu7_bottom_alert0: trip-point0 {
6757 tempe 4614 temperature = <90000>;
6758 hyste 4615 hysteresis = <2000>;
6759 type 4616 type = "passive";
6760 }; 4617 };
6761 4618
6762 cpu7_bottom_a 4619 cpu7_bottom_alert1: trip-point1 {
6763 tempe 4620 temperature = <95000>;
6764 hyste 4621 hysteresis = <2000>;
6765 type 4622 type = "passive";
6766 }; 4623 };
6767 4624
6768 cpu7_bottom_c !! 4625 cpu7_bottom_crit: cpu_crit {
6769 tempe 4626 temperature = <110000>;
6770 hyste 4627 hysteresis = <1000>;
6771 type 4628 type = "critical";
6772 }; 4629 };
6773 }; 4630 };
6774 4631
6775 cooling-maps { 4632 cooling-maps {
6776 map0 { 4633 map0 {
6777 trip 4634 trip = <&cpu7_bottom_alert0>;
6778 cooli 4635 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 4636 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 4637 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 4638 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 4639 };
6783 map1 { 4640 map1 {
6784 trip 4641 trip = <&cpu7_bottom_alert1>;
6785 cooli 4642 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 4643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 4644 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 4645 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 4646 };
6790 }; 4647 };
6791 }; 4648 };
6792 4649
6793 aoss0-thermal { 4650 aoss0-thermal {
6794 polling-delay-passive 4651 polling-delay-passive = <250>;
>> 4652 polling-delay = <1000>;
6795 4653
6796 thermal-sensors = <&t 4654 thermal-sensors = <&tsens0 0>;
6797 4655
6798 trips { 4656 trips {
6799 aoss0_alert0: 4657 aoss0_alert0: trip-point0 {
6800 tempe 4658 temperature = <90000>;
6801 hyste 4659 hysteresis = <2000>;
6802 type 4660 type = "hot";
6803 }; 4661 };
6804 }; 4662 };
6805 }; 4663 };
6806 4664
6807 cluster0-thermal { 4665 cluster0-thermal {
6808 polling-delay-passive 4666 polling-delay-passive = <250>;
>> 4667 polling-delay = <1000>;
6809 4668
6810 thermal-sensors = <&t 4669 thermal-sensors = <&tsens0 5>;
6811 4670
6812 trips { 4671 trips {
6813 cluster0_aler 4672 cluster0_alert0: trip-point0 {
6814 tempe 4673 temperature = <90000>;
6815 hyste 4674 hysteresis = <2000>;
6816 type 4675 type = "hot";
6817 }; 4676 };
6818 cluster0_crit !! 4677 cluster0_crit: cluster0_crit {
6819 tempe 4678 temperature = <110000>;
6820 hyste 4679 hysteresis = <2000>;
6821 type 4680 type = "critical";
6822 }; 4681 };
6823 }; 4682 };
6824 }; 4683 };
6825 4684
6826 cluster1-thermal { 4685 cluster1-thermal {
6827 polling-delay-passive 4686 polling-delay-passive = <250>;
>> 4687 polling-delay = <1000>;
6828 4688
6829 thermal-sensors = <&t 4689 thermal-sensors = <&tsens0 6>;
6830 4690
6831 trips { 4691 trips {
6832 cluster1_aler 4692 cluster1_alert0: trip-point0 {
6833 tempe 4693 temperature = <90000>;
6834 hyste 4694 hysteresis = <2000>;
6835 type 4695 type = "hot";
6836 }; 4696 };
6837 cluster1_crit !! 4697 cluster1_crit: cluster1_crit {
6838 tempe 4698 temperature = <110000>;
6839 hyste 4699 hysteresis = <2000>;
6840 type 4700 type = "critical";
6841 }; 4701 };
6842 }; 4702 };
6843 }; 4703 };
6844 4704
6845 gpu-top-thermal { !! 4705 gpu-thermal-top {
6846 polling-delay-passive 4706 polling-delay-passive = <250>;
>> 4707 polling-delay = <1000>;
6847 4708
6848 thermal-sensors = <&t 4709 thermal-sensors = <&tsens0 15>;
6849 4710
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 4711 trips {
6858 gpu_top_alert !! 4712 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 4713 temperature = <90000>;
6866 hyste !! 4714 hysteresis = <2000>;
6867 type 4715 type = "hot";
6868 }; 4716 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 4717 };
6876 }; 4718 };
6877 4719
6878 aoss1-thermal { 4720 aoss1-thermal {
6879 polling-delay-passive 4721 polling-delay-passive = <250>;
>> 4722 polling-delay = <1000>;
6880 4723
6881 thermal-sensors = <&t 4724 thermal-sensors = <&tsens1 0>;
6882 4725
6883 trips { 4726 trips {
6884 aoss1_alert0: 4727 aoss1_alert0: trip-point0 {
6885 tempe 4728 temperature = <90000>;
6886 hyste 4729 hysteresis = <2000>;
6887 type 4730 type = "hot";
6888 }; 4731 };
6889 }; 4732 };
6890 }; 4733 };
6891 4734
6892 wlan-thermal { 4735 wlan-thermal {
6893 polling-delay-passive 4736 polling-delay-passive = <250>;
>> 4737 polling-delay = <1000>;
6894 4738
6895 thermal-sensors = <&t 4739 thermal-sensors = <&tsens1 1>;
6896 4740
6897 trips { 4741 trips {
6898 wlan_alert0: 4742 wlan_alert0: trip-point0 {
6899 tempe 4743 temperature = <90000>;
6900 hyste 4744 hysteresis = <2000>;
6901 type 4745 type = "hot";
6902 }; 4746 };
6903 }; 4747 };
6904 }; 4748 };
6905 4749
6906 video-thermal { 4750 video-thermal {
6907 polling-delay-passive 4751 polling-delay-passive = <250>;
>> 4752 polling-delay = <1000>;
6908 4753
6909 thermal-sensors = <&t 4754 thermal-sensors = <&tsens1 2>;
6910 4755
6911 trips { 4756 trips {
6912 video_alert0: 4757 video_alert0: trip-point0 {
6913 tempe 4758 temperature = <90000>;
6914 hyste 4759 hysteresis = <2000>;
6915 type 4760 type = "hot";
6916 }; 4761 };
6917 }; 4762 };
6918 }; 4763 };
6919 4764
6920 mem-thermal { 4765 mem-thermal {
6921 polling-delay-passive 4766 polling-delay-passive = <250>;
>> 4767 polling-delay = <1000>;
6922 4768
6923 thermal-sensors = <&t 4769 thermal-sensors = <&tsens1 3>;
6924 4770
6925 trips { 4771 trips {
6926 mem_alert0: t 4772 mem_alert0: trip-point0 {
6927 tempe 4773 temperature = <90000>;
6928 hyste 4774 hysteresis = <2000>;
6929 type 4775 type = "hot";
6930 }; 4776 };
6931 }; 4777 };
6932 }; 4778 };
6933 4779
6934 q6-hvx-thermal { 4780 q6-hvx-thermal {
6935 polling-delay-passive 4781 polling-delay-passive = <250>;
>> 4782 polling-delay = <1000>;
6936 4783
6937 thermal-sensors = <&t 4784 thermal-sensors = <&tsens1 4>;
6938 4785
6939 trips { 4786 trips {
6940 q6_hvx_alert0 4787 q6_hvx_alert0: trip-point0 {
6941 tempe 4788 temperature = <90000>;
6942 hyste 4789 hysteresis = <2000>;
6943 type 4790 type = "hot";
6944 }; 4791 };
6945 }; 4792 };
6946 }; 4793 };
6947 4794
6948 camera-thermal { 4795 camera-thermal {
6949 polling-delay-passive 4796 polling-delay-passive = <250>;
>> 4797 polling-delay = <1000>;
6950 4798
6951 thermal-sensors = <&t 4799 thermal-sensors = <&tsens1 5>;
6952 4800
6953 trips { 4801 trips {
6954 camera_alert0 4802 camera_alert0: trip-point0 {
6955 tempe 4803 temperature = <90000>;
6956 hyste 4804 hysteresis = <2000>;
6957 type 4805 type = "hot";
6958 }; 4806 };
6959 }; 4807 };
6960 }; 4808 };
6961 4809
6962 compute-thermal { 4810 compute-thermal {
6963 polling-delay-passive 4811 polling-delay-passive = <250>;
>> 4812 polling-delay = <1000>;
6964 4813
6965 thermal-sensors = <&t 4814 thermal-sensors = <&tsens1 6>;
6966 4815
6967 trips { 4816 trips {
6968 compute_alert 4817 compute_alert0: trip-point0 {
6969 tempe 4818 temperature = <90000>;
6970 hyste 4819 hysteresis = <2000>;
6971 type 4820 type = "hot";
6972 }; 4821 };
6973 }; 4822 };
6974 }; 4823 };
6975 4824
6976 npu-thermal { 4825 npu-thermal {
6977 polling-delay-passive 4826 polling-delay-passive = <250>;
>> 4827 polling-delay = <1000>;
6978 4828
6979 thermal-sensors = <&t 4829 thermal-sensors = <&tsens1 7>;
6980 4830
6981 trips { 4831 trips {
6982 npu_alert0: t 4832 npu_alert0: trip-point0 {
6983 tempe 4833 temperature = <90000>;
6984 hyste 4834 hysteresis = <2000>;
6985 type 4835 type = "hot";
6986 }; 4836 };
6987 }; 4837 };
6988 }; 4838 };
6989 4839
6990 gpu-bottom-thermal { !! 4840 gpu-thermal-bottom {
6991 polling-delay-passive 4841 polling-delay-passive = <250>;
>> 4842 polling-delay = <1000>;
6992 4843
6993 thermal-sensors = <&t 4844 thermal-sensors = <&tsens1 8>;
6994 4845
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 4846 trips {
7003 gpu_bottom_al !! 4847 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 4848 temperature = <90000>;
7011 hyste !! 4849 hysteresis = <2000>;
7012 type 4850 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 4851 };
7020 }; 4852 };
7021 }; 4853 };
7022 }; 4854 };
7023 }; 4855 };
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