1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 16 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 17 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 19 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 20 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 21 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 22
26 / { 23 / {
27 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
28 25
29 #address-cells = <2>; 26 #address-cells = <2>;
30 #size-cells = <2>; 27 #size-cells = <2>;
31 28
32 aliases { 29 aliases {
33 i2c0 = &i2c0; 30 i2c0 = &i2c0;
34 i2c1 = &i2c1; 31 i2c1 = &i2c1;
35 i2c2 = &i2c2; 32 i2c2 = &i2c2;
36 i2c3 = &i2c3; 33 i2c3 = &i2c3;
37 i2c4 = &i2c4; 34 i2c4 = &i2c4;
38 i2c5 = &i2c5; 35 i2c5 = &i2c5;
39 i2c6 = &i2c6; 36 i2c6 = &i2c6;
40 i2c7 = &i2c7; 37 i2c7 = &i2c7;
41 i2c8 = &i2c8; 38 i2c8 = &i2c8;
42 i2c9 = &i2c9; 39 i2c9 = &i2c9;
43 i2c10 = &i2c10; 40 i2c10 = &i2c10;
44 i2c11 = &i2c11; 41 i2c11 = &i2c11;
45 i2c12 = &i2c12; 42 i2c12 = &i2c12;
46 i2c13 = &i2c13; 43 i2c13 = &i2c13;
47 i2c14 = &i2c14; 44 i2c14 = &i2c14;
48 i2c15 = &i2c15; 45 i2c15 = &i2c15;
49 i2c16 = &i2c16; 46 i2c16 = &i2c16;
50 i2c17 = &i2c17; 47 i2c17 = &i2c17;
51 i2c18 = &i2c18; 48 i2c18 = &i2c18;
52 i2c19 = &i2c19; 49 i2c19 = &i2c19;
53 spi0 = &spi0; 50 spi0 = &spi0;
54 spi1 = &spi1; 51 spi1 = &spi1;
55 spi2 = &spi2; 52 spi2 = &spi2;
56 spi3 = &spi3; 53 spi3 = &spi3;
57 spi4 = &spi4; 54 spi4 = &spi4;
58 spi5 = &spi5; 55 spi5 = &spi5;
59 spi6 = &spi6; 56 spi6 = &spi6;
60 spi7 = &spi7; 57 spi7 = &spi7;
61 spi8 = &spi8; 58 spi8 = &spi8;
62 spi9 = &spi9; 59 spi9 = &spi9;
63 spi10 = &spi10; 60 spi10 = &spi10;
64 spi11 = &spi11; 61 spi11 = &spi11;
65 spi12 = &spi12; 62 spi12 = &spi12;
66 spi13 = &spi13; 63 spi13 = &spi13;
67 spi14 = &spi14; 64 spi14 = &spi14;
68 spi15 = &spi15; 65 spi15 = &spi15;
69 spi16 = &spi16; 66 spi16 = &spi16;
70 spi17 = &spi17; 67 spi17 = &spi17;
71 spi18 = &spi18; 68 spi18 = &spi18;
72 spi19 = &spi19; 69 spi19 = &spi19;
73 }; 70 };
74 71
75 chosen { }; 72 chosen { };
76 73
77 clocks { 74 clocks {
78 xo_board: xo-board { 75 xo_board: xo-board {
79 compatible = "fixed-cl 76 compatible = "fixed-clock";
80 #clock-cells = <0>; 77 #clock-cells = <0>;
81 clock-frequency = <384 78 clock-frequency = <38400000>;
82 clock-output-names = " 79 clock-output-names = "xo_board";
83 }; 80 };
84 81
85 sleep_clk: sleep-clk { 82 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 83 compatible = "fixed-clock";
87 clock-frequency = <327 84 clock-frequency = <32768>;
88 #clock-cells = <0>; 85 #clock-cells = <0>;
89 }; 86 };
90 }; 87 };
91 88
92 cpus { 89 cpus {
93 #address-cells = <2>; 90 #address-cells = <2>;
94 #size-cells = <0>; 91 #size-cells = <0>;
95 92
96 CPU0: cpu@0 { 93 CPU0: cpu@0 {
97 device_type = "cpu"; 94 device_type = "cpu";
98 compatible = "qcom,kry 95 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 96 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 97 enable-method = "psci";
102 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 99 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 100 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ <<
106 power-domain-names = " <<
107 qcom,freq-domain = <&c 101 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 102 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ !! 103 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
110 <&epss 104 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 105 #cooling-cells = <2>;
112 L2_0: l2-cache { 106 L2_0: l2-cache {
113 compatible = " 107 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 108 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 109 L3_0: l3-cache {
119 compat 110 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 111 };
124 }; 112 };
125 }; 113 };
126 114
127 CPU1: cpu@100 { 115 CPU1: cpu@100 {
128 device_type = "cpu"; 116 device_type = "cpu";
129 compatible = "qcom,kry 117 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 118 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 119 enable-method = "psci";
133 capacity-dmips-mhz = < 120 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 121 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 122 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ <<
137 power-domain-names = " <<
138 qcom,freq-domain = <&c 123 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 124 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ !! 125 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
141 <&epss 126 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 127 #cooling-cells = <2>;
143 L2_100: l2-cache { 128 L2_100: l2-cache {
144 compatible = " 129 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 130 next-level-cache = <&L3_0>;
149 }; 131 };
150 }; 132 };
151 133
152 CPU2: cpu@200 { 134 CPU2: cpu@200 {
153 device_type = "cpu"; 135 device_type = "cpu";
154 compatible = "qcom,kry 136 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 137 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 138 enable-method = "psci";
158 capacity-dmips-mhz = < 139 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 140 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 141 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ <<
162 power-domain-names = " <<
163 qcom,freq-domain = <&c 142 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 143 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ !! 144 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
166 <&epss 145 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 146 #cooling-cells = <2>;
168 L2_200: l2-cache { 147 L2_200: l2-cache {
169 compatible = " 148 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 149 next-level-cache = <&L3_0>;
174 }; 150 };
175 }; 151 };
176 152
177 CPU3: cpu@300 { 153 CPU3: cpu@300 {
178 device_type = "cpu"; 154 device_type = "cpu";
179 compatible = "qcom,kry 155 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 156 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 157 enable-method = "psci";
183 capacity-dmips-mhz = < 158 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 159 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 160 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ <<
187 power-domain-names = " <<
188 qcom,freq-domain = <&c 161 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 162 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ !! 163 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
191 <&epss 164 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 165 #cooling-cells = <2>;
193 L2_300: l2-cache { 166 L2_300: l2-cache {
194 compatible = " 167 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 168 next-level-cache = <&L3_0>;
199 }; 169 };
200 }; 170 };
201 171
202 CPU4: cpu@400 { 172 CPU4: cpu@400 {
203 device_type = "cpu"; 173 device_type = "cpu";
204 compatible = "qcom,kry 174 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 175 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 176 enable-method = "psci";
208 capacity-dmips-mhz = < 177 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 178 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 179 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ <<
212 power-domain-names = " <<
213 qcom,freq-domain = <&c 180 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 181 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ !! 182 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
216 <&epss 183 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 184 #cooling-cells = <2>;
218 L2_400: l2-cache { 185 L2_400: l2-cache {
219 compatible = " 186 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 187 next-level-cache = <&L3_0>;
224 }; 188 };
225 }; 189 };
226 190
227 CPU5: cpu@500 { 191 CPU5: cpu@500 {
228 device_type = "cpu"; 192 device_type = "cpu";
229 compatible = "qcom,kry 193 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 194 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 195 enable-method = "psci";
233 capacity-dmips-mhz = < 196 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 197 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 198 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ <<
237 power-domain-names = " <<
238 qcom,freq-domain = <&c 199 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 200 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ !! 201 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
241 <&epss 202 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 203 #cooling-cells = <2>;
243 L2_500: l2-cache { 204 L2_500: l2-cache {
244 compatible = " 205 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 206 next-level-cache = <&L3_0>;
249 }; 207 };
>> 208
250 }; 209 };
251 210
252 CPU6: cpu@600 { 211 CPU6: cpu@600 {
253 device_type = "cpu"; 212 device_type = "cpu";
254 compatible = "qcom,kry 213 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 214 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 215 enable-method = "psci";
258 capacity-dmips-mhz = < 216 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 217 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 218 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ <<
262 power-domain-names = " <<
263 qcom,freq-domain = <&c 219 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 220 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ !! 221 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
266 <&epss 222 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 223 #cooling-cells = <2>;
268 L2_600: l2-cache { 224 L2_600: l2-cache {
269 compatible = " 225 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 226 next-level-cache = <&L3_0>;
274 }; 227 };
275 }; 228 };
276 229
277 CPU7: cpu@700 { 230 CPU7: cpu@700 {
278 device_type = "cpu"; 231 device_type = "cpu";
279 compatible = "qcom,kry 232 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 233 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 234 enable-method = "psci";
283 capacity-dmips-mhz = < 235 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 236 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 237 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ <<
287 power-domain-names = " <<
288 qcom,freq-domain = <&c 238 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 239 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ !! 240 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
291 <&epss 241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 242 #cooling-cells = <2>;
293 L2_700: l2-cache { 243 L2_700: l2-cache {
294 compatible = " 244 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 245 next-level-cache = <&L3_0>;
299 }; 246 };
300 }; 247 };
301 248
302 cpu-map { 249 cpu-map {
303 cluster0 { 250 cluster0 {
304 core0 { 251 core0 {
305 cpu = 252 cpu = <&CPU0>;
306 }; 253 };
307 254
308 core1 { 255 core1 {
309 cpu = 256 cpu = <&CPU1>;
310 }; 257 };
311 258
312 core2 { 259 core2 {
313 cpu = 260 cpu = <&CPU2>;
314 }; 261 };
315 262
316 core3 { 263 core3 {
317 cpu = 264 cpu = <&CPU3>;
318 }; 265 };
319 266
320 core4 { 267 core4 {
321 cpu = 268 cpu = <&CPU4>;
322 }; 269 };
323 270
324 core5 { 271 core5 {
325 cpu = 272 cpu = <&CPU5>;
326 }; 273 };
327 274
328 core6 { 275 core6 {
329 cpu = 276 cpu = <&CPU6>;
330 }; 277 };
331 278
332 core7 { 279 core7 {
333 cpu = 280 cpu = <&CPU7>;
334 }; 281 };
335 }; 282 };
336 }; 283 };
337 <<
338 idle-states { <<
339 entry-method = "psci"; <<
340 <<
341 LITTLE_CPU_SLEEP_0: cp <<
342 compatible = " <<
343 idle-state-nam <<
344 arm,psci-suspe <<
345 entry-latency- <<
346 exit-latency-u <<
347 min-residency- <<
348 local-timer-st <<
349 }; <<
350 <<
351 BIG_CPU_SLEEP_0: cpu-s <<
352 compatible = " <<
353 idle-state-nam <<
354 arm,psci-suspe <<
355 entry-latency- <<
356 exit-latency-u <<
357 min-residency- <<
358 local-timer-st <<
359 }; <<
360 }; <<
361 <<
362 domain-idle-states { <<
363 CLUSTER_SLEEP_0: clust <<
364 compatible = " <<
365 arm,psci-suspe <<
366 entry-latency- <<
367 exit-latency-u <<
368 min-residency- <<
369 }; <<
370 }; <<
371 }; 284 };
372 285
373 qup_virt: interconnect-qup-virt { !! 286 cpu0_opp_table: cpu0_opp_table {
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points 287 compatible = "operating-points-v2";
381 opp-shared; 288 opp-shared;
382 289
383 cpu0_opp1: opp-300000000 { 290 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 291 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 292 opp-peak-kBps = <800000 9600000>;
386 }; 293 };
387 294
388 cpu0_opp2: opp-403200000 { 295 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 296 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 297 opp-peak-kBps = <800000 9600000>;
391 }; 298 };
392 299
393 cpu0_opp3: opp-518400000 { 300 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 301 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 302 opp-peak-kBps = <800000 16588800>;
396 }; 303 };
397 304
398 cpu0_opp4: opp-614400000 { 305 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 306 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 307 opp-peak-kBps = <800000 16588800>;
401 }; 308 };
402 309
403 cpu0_opp5: opp-691200000 { 310 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 311 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 312 opp-peak-kBps = <800000 19660800>;
406 }; 313 };
407 314
408 cpu0_opp6: opp-787200000 { 315 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 316 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 317 opp-peak-kBps = <1804000 19660800>;
411 }; 318 };
412 319
413 cpu0_opp7: opp-883200000 { 320 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 321 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 322 opp-peak-kBps = <1804000 23347200>;
416 }; 323 };
417 324
418 cpu0_opp8: opp-979200000 { 325 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 326 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 327 opp-peak-kBps = <1804000 26419200>;
421 }; 328 };
422 329
423 cpu0_opp9: opp-1075200000 { 330 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 331 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 332 opp-peak-kBps = <1804000 29491200>;
426 }; 333 };
427 334
428 cpu0_opp10: opp-1171200000 { 335 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 336 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 337 opp-peak-kBps = <1804000 32563200>;
431 }; 338 };
432 339
433 cpu0_opp11: opp-1248000000 { 340 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 341 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 342 opp-peak-kBps = <1804000 36249600>;
436 }; 343 };
437 344
438 cpu0_opp12: opp-1344000000 { 345 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 346 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 347 opp-peak-kBps = <2188000 36249600>;
441 }; 348 };
442 349
443 cpu0_opp13: opp-1420800000 { 350 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 351 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 352 opp-peak-kBps = <2188000 39321600>;
446 }; 353 };
447 354
448 cpu0_opp14: opp-1516800000 { 355 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 356 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 357 opp-peak-kBps = <3072000 42393600>;
451 }; 358 };
452 359
453 cpu0_opp15: opp-1612800000 { 360 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 361 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 362 opp-peak-kBps = <3072000 42393600>;
456 }; 363 };
457 364
458 cpu0_opp16: opp-1708800000 { 365 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 366 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 367 opp-peak-kBps = <4068000 42393600>;
461 }; 368 };
462 369
463 cpu0_opp17: opp-1804800000 { 370 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 371 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 372 opp-peak-kBps = <4068000 42393600>;
466 }; 373 };
467 }; 374 };
468 375
469 cpu4_opp_table: opp-table-cpu4 { !! 376 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 377 compatible = "operating-points-v2";
471 opp-shared; 378 opp-shared;
472 379
473 cpu4_opp1: opp-710400000 { 380 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 381 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 382 opp-peak-kBps = <1804000 19660800>;
476 }; 383 };
477 384
478 cpu4_opp2: opp-825600000 { 385 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 386 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 387 opp-peak-kBps = <2188000 23347200>;
481 }; 388 };
482 389
483 cpu4_opp3: opp-940800000 { 390 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 391 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 392 opp-peak-kBps = <2188000 26419200>;
486 }; 393 };
487 394
488 cpu4_opp4: opp-1056000000 { 395 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 396 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 397 opp-peak-kBps = <3072000 26419200>;
491 }; 398 };
492 399
493 cpu4_opp5: opp-1171200000 { 400 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 401 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 402 opp-peak-kBps = <3072000 29491200>;
496 }; 403 };
497 404
498 cpu4_opp6: opp-1286400000 { 405 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 406 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 407 opp-peak-kBps = <4068000 29491200>;
501 }; 408 };
502 409
503 cpu4_opp7: opp-1382400000 { 410 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 411 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 412 opp-peak-kBps = <4068000 32563200>;
506 }; 413 };
507 414
508 cpu4_opp8: opp-1478400000 { 415 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 416 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 417 opp-peak-kBps = <4068000 32563200>;
511 }; 418 };
512 419
513 cpu4_opp9: opp-1574400000 { 420 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 421 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 422 opp-peak-kBps = <5412000 39321600>;
516 }; 423 };
517 424
518 cpu4_opp10: opp-1670400000 { 425 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 426 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 427 opp-peak-kBps = <5412000 42393600>;
521 }; 428 };
522 429
523 cpu4_opp11: opp-1766400000 { 430 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 431 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 432 opp-peak-kBps = <5412000 45465600>;
526 }; 433 };
527 434
528 cpu4_opp12: opp-1862400000 { 435 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 436 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 437 opp-peak-kBps = <6220000 45465600>;
531 }; 438 };
532 439
533 cpu4_opp13: opp-1958400000 { 440 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 441 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 442 opp-peak-kBps = <6220000 48537600>;
536 }; 443 };
537 444
538 cpu4_opp14: opp-2054400000 { 445 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 446 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 447 opp-peak-kBps = <7216000 48537600>;
541 }; 448 };
542 449
543 cpu4_opp15: opp-2150400000 { 450 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 451 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 452 opp-peak-kBps = <7216000 51609600>;
546 }; 453 };
547 454
548 cpu4_opp16: opp-2246400000 { 455 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 456 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 457 opp-peak-kBps = <7216000 51609600>;
551 }; 458 };
552 459
553 cpu4_opp17: opp-2342400000 { 460 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 461 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 462 opp-peak-kBps = <8368000 51609600>;
556 }; 463 };
557 464
558 cpu4_opp18: opp-2419200000 { 465 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 466 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 467 opp-peak-kBps = <8368000 51609600>;
561 }; 468 };
562 }; 469 };
563 470
564 cpu7_opp_table: opp-table-cpu7 { !! 471 cpu7_opp_table: cpu7_opp_table {
565 compatible = "operating-points 472 compatible = "operating-points-v2";
566 opp-shared; 473 opp-shared;
567 474
568 cpu7_opp1: opp-844800000 { 475 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 476 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 477 opp-peak-kBps = <2188000 19660800>;
571 }; 478 };
572 479
573 cpu7_opp2: opp-960000000 { 480 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 481 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 482 opp-peak-kBps = <2188000 26419200>;
576 }; 483 };
577 484
578 cpu7_opp3: opp-1075200000 { 485 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 486 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 487 opp-peak-kBps = <3072000 26419200>;
581 }; 488 };
582 489
583 cpu7_opp4: opp-1190400000 { 490 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 491 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 492 opp-peak-kBps = <3072000 29491200>;
586 }; 493 };
587 494
588 cpu7_opp5: opp-1305600000 { 495 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 496 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 497 opp-peak-kBps = <4068000 32563200>;
591 }; 498 };
592 499
593 cpu7_opp6: opp-1401600000 { 500 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 501 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 502 opp-peak-kBps = <4068000 32563200>;
596 }; 503 };
597 504
598 cpu7_opp7: opp-1516800000 { 505 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 506 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 507 opp-peak-kBps = <4068000 36249600>;
601 }; 508 };
602 509
603 cpu7_opp8: opp-1632000000 { 510 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 511 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 512 opp-peak-kBps = <5412000 39321600>;
606 }; 513 };
607 514
608 cpu7_opp9: opp-1747200000 { 515 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 516 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 517 opp-peak-kBps = <5412000 42393600>;
611 }; 518 };
612 519
613 cpu7_opp10: opp-1862400000 { 520 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 521 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 522 opp-peak-kBps = <6220000 45465600>;
616 }; 523 };
617 524
618 cpu7_opp11: opp-1977600000 { 525 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 526 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 527 opp-peak-kBps = <6220000 48537600>;
621 }; 528 };
622 529
623 cpu7_opp12: opp-2073600000 { 530 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 531 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 532 opp-peak-kBps = <7216000 48537600>;
626 }; 533 };
627 534
628 cpu7_opp13: opp-2169600000 { 535 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 536 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 537 opp-peak-kBps = <7216000 51609600>;
631 }; 538 };
632 539
633 cpu7_opp14: opp-2265600000 { 540 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 541 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 542 opp-peak-kBps = <7216000 51609600>;
636 }; 543 };
637 544
638 cpu7_opp15: opp-2361600000 { 545 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 546 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 547 opp-peak-kBps = <8368000 51609600>;
641 }; 548 };
642 549
643 cpu7_opp16: opp-2457600000 { 550 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 551 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 552 opp-peak-kBps = <8368000 51609600>;
646 }; 553 };
647 554
648 cpu7_opp17: opp-2553600000 { 555 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 556 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 557 opp-peak-kBps = <8368000 51609600>;
651 }; 558 };
652 559
653 cpu7_opp18: opp-2649600000 { 560 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 561 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 562 opp-peak-kBps = <8368000 51609600>;
656 }; 563 };
657 564
658 cpu7_opp19: opp-2745600000 { 565 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 566 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 567 opp-peak-kBps = <8368000 51609600>;
661 }; 568 };
662 569
663 cpu7_opp20: opp-2841600000 { 570 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 571 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 572 opp-peak-kBps = <8368000 51609600>;
666 }; 573 };
667 }; 574 };
668 575
669 firmware { 576 firmware {
670 scm: scm { 577 scm: scm {
671 compatible = "qcom,scm !! 578 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 579 #reset-cells = <1>;
674 }; 580 };
675 }; 581 };
676 582
677 memory@80000000 { 583 memory@80000000 {
678 device_type = "memory"; 584 device_type = "memory";
679 /* We expect the bootloader to 585 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 586 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 587 };
682 588
683 pmu { 589 pmu {
684 compatible = "arm,armv8-pmuv3" 590 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 591 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 592 };
687 593
688 psci { 594 psci {
689 compatible = "arm,psci-1.0"; 595 compatible = "arm,psci-1.0";
690 method = "smc"; 596 method = "smc";
691 <<
692 CPU_PD0: power-domain-cpu0 { <<
693 #power-domain-cells = <<
694 power-domains = <&CLUS <<
695 domain-idle-states = < <<
696 }; <<
697 <<
698 CPU_PD1: power-domain-cpu1 { <<
699 #power-domain-cells = <<
700 power-domains = <&CLUS <<
701 domain-idle-states = < <<
702 }; <<
703 <<
704 CPU_PD2: power-domain-cpu2 { <<
705 #power-domain-cells = <<
706 power-domains = <&CLUS <<
707 domain-idle-states = < <<
708 }; <<
709 <<
710 CPU_PD3: power-domain-cpu3 { <<
711 #power-domain-cells = <<
712 power-domains = <&CLUS <<
713 domain-idle-states = < <<
714 }; <<
715 <<
716 CPU_PD4: power-domain-cpu4 { <<
717 #power-domain-cells = <<
718 power-domains = <&CLUS <<
719 domain-idle-states = < <<
720 }; <<
721 <<
722 CPU_PD5: power-domain-cpu5 { <<
723 #power-domain-cells = <<
724 power-domains = <&CLUS <<
725 domain-idle-states = < <<
726 }; <<
727 <<
728 CPU_PD6: power-domain-cpu6 { <<
729 #power-domain-cells = <<
730 power-domains = <&CLUS <<
731 domain-idle-states = < <<
732 }; <<
733 <<
734 CPU_PD7: power-domain-cpu7 { <<
735 #power-domain-cells = <<
736 power-domains = <&CLUS <<
737 domain-idle-states = < <<
738 }; <<
739 <<
740 CLUSTER_PD: power-domain-cpu-c <<
741 #power-domain-cells = <<
742 domain-idle-states = < <<
743 }; <<
744 }; <<
745 <<
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; 597 };
764 598
765 reserved-memory { 599 reserved-memory {
766 #address-cells = <2>; 600 #address-cells = <2>;
767 #size-cells = <2>; 601 #size-cells = <2>;
768 ranges; 602 ranges;
769 603
770 hyp_mem: memory@80000000 { 604 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 605 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 606 no-map;
773 }; 607 };
774 608
775 xbl_aop_mem: memory@80700000 { 609 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 610 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 611 no-map;
778 }; 612 };
779 613
780 cmd_db: memory@80860000 { 614 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 615 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 616 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 617 no-map;
784 }; 618 };
785 619
786 smem_mem: memory@80900000 { 620 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 621 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 622 no-map;
789 }; 623 };
790 624
791 removed_mem: memory@80b00000 { 625 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 626 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 627 no-map;
794 }; 628 };
795 629
796 camera_mem: memory@86200000 { 630 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 631 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 632 no-map;
799 }; 633 };
800 634
801 wlan_mem: memory@86700000 { 635 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 636 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 637 no-map;
804 }; 638 };
805 639
806 ipa_fw_mem: memory@86800000 { 640 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 641 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 642 no-map;
809 }; 643 };
810 644
811 ipa_gsi_mem: memory@86810000 { 645 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 646 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 647 no-map;
814 }; 648 };
815 649
816 gpu_mem: memory@8681a000 { 650 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 651 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 652 no-map;
819 }; 653 };
820 654
821 npu_mem: memory@86900000 { 655 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 656 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 657 no-map;
824 }; 658 };
825 659
826 video_mem: memory@86e00000 { 660 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 661 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 662 no-map;
829 }; 663 };
830 664
831 cvp_mem: memory@87300000 { 665 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 666 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 667 no-map;
834 }; 668 };
835 669
836 cdsp_mem: memory@87800000 { 670 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 671 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 672 no-map;
839 }; 673 };
840 674
841 slpi_mem: memory@88c00000 { 675 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 676 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 677 no-map;
844 }; 678 };
845 679
846 adsp_mem: memory@8a100000 { 680 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 681 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 682 no-map;
849 }; 683 };
850 684
851 spss_mem: memory@8be00000 { 685 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 686 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 687 no-map;
854 }; 688 };
855 689
856 cdsp_secure_heap: memory@8bf00 690 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 691 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 692 no-map;
859 }; 693 };
860 }; 694 };
861 695
862 smem { 696 smem {
863 compatible = "qcom,smem"; 697 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 698 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 699 hwlocks = <&tcsr_mutex 3>;
866 }; 700 };
867 701
868 smp2p-adsp { 702 smp2p-adsp {
869 compatible = "qcom,smp2p"; 703 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 704 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 705 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 706 IPCC_MPROC_SIGNAL_SMP2P
873 I 707 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 708 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 709 IPCC_MPROC_SIGNAL_SMP2P>;
876 710
877 qcom,local-pid = <0>; 711 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 712 qcom,remote-pid = <2>;
879 713
880 smp2p_adsp_out: master-kernel 714 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 715 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 716 #qcom,smem-state-cells = <1>;
883 }; 717 };
884 718
885 smp2p_adsp_in: slave-kernel { 719 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 720 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 721 interrupt-controller;
888 #interrupt-cells = <2> 722 #interrupt-cells = <2>;
889 }; 723 };
890 }; 724 };
891 725
892 smp2p-cdsp { 726 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 727 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 728 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 729 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 730 IPCC_MPROC_SIGNAL_SMP2P
897 I 731 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 732 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 733 IPCC_MPROC_SIGNAL_SMP2P>;
900 734
901 qcom,local-pid = <0>; 735 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 736 qcom,remote-pid = <5>;
903 737
904 smp2p_cdsp_out: master-kernel 738 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 739 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 740 #qcom,smem-state-cells = <1>;
907 }; 741 };
908 742
909 smp2p_cdsp_in: slave-kernel { 743 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 744 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 745 interrupt-controller;
912 #interrupt-cells = <2> 746 #interrupt-cells = <2>;
913 }; 747 };
914 }; 748 };
915 749
916 smp2p-slpi { 750 smp2p-slpi {
917 compatible = "qcom,smp2p"; 751 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 752 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 753 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 754 IPCC_MPROC_SIGNAL_SMP2P
921 I 755 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 756 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 757 IPCC_MPROC_SIGNAL_SMP2P>;
924 758
925 qcom,local-pid = <0>; 759 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 760 qcom,remote-pid = <3>;
927 761
928 smp2p_slpi_out: master-kernel 762 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 763 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 764 #qcom,smem-state-cells = <1>;
931 }; 765 };
932 766
933 smp2p_slpi_in: slave-kernel { 767 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 768 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 769 interrupt-controller;
936 #interrupt-cells = <2> 770 #interrupt-cells = <2>;
937 }; 771 };
938 }; 772 };
939 773
940 soc: soc@0 { 774 soc: soc@0 {
941 #address-cells = <2>; 775 #address-cells = <2>;
942 #size-cells = <2>; 776 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 777 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 778 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 779 compatible = "simple-bus";
946 780
947 gcc: clock-controller@100000 { 781 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 782 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 783 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 784 #clock-cells = <1>;
951 #reset-cells = <1>; 785 #reset-cells = <1>;
952 #power-domain-cells = 786 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 787 clock-names = "bi_tcxo",
954 "bi_tcxo 788 "bi_tcxo_ao",
955 "sleep_c 789 "sleep_clk";
956 clocks = <&rpmhcc RPMH 790 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 791 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 792 <&sleep_clk>;
959 }; 793 };
960 794
961 ipcc: mailbox@408000 { 795 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 796 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 797 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 798 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 799 interrupt-controller;
966 #interrupt-cells = <3> 800 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 801 #mbox-cells = <2>;
968 }; 802 };
969 803
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 804 rng: rng@793000 {
983 compatible = "qcom,prn 805 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 806 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 807 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 808 clock-names = "core";
987 }; 809 };
988 810
>> 811 qup_opp_table: qup-opp-table {
>> 812 compatible = "operating-points-v2";
>> 813
>> 814 opp-50000000 {
>> 815 opp-hz = /bits/ 64 <50000000>;
>> 816 required-opps = <&rpmhpd_opp_min_svs>;
>> 817 };
>> 818
>> 819 opp-75000000 {
>> 820 opp-hz = /bits/ 64 <75000000>;
>> 821 required-opps = <&rpmhpd_opp_low_svs>;
>> 822 };
>> 823
>> 824 opp-120000000 {
>> 825 opp-hz = /bits/ 64 <120000000>;
>> 826 required-opps = <&rpmhpd_opp_svs>;
>> 827 };
>> 828 };
>> 829
989 gpi_dma2: dma-controller@80000 830 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 !! 831 compatible = "qcom,sm8250-gpi-dma";
991 reg = <0 0x00800000 0 832 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 833 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 834 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 835 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 836 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 837 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 838 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 839 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 840 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 841 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 842 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 843 dma-channels = <10>;
1003 dma-channel-mask = <0 844 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 845 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 846 #dma-cells = <3>;
1006 status = "disabled"; 847 status = "disabled";
1007 }; 848 };
1008 849
1009 qupv3_id_2: geniqup@8c0000 { 850 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 851 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 852 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 853 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 854 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 855 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 856 #address-cells = <2>;
1016 #size-cells = <2>; 857 #size-cells = <2>;
1017 iommus = <&apps_smmu 858 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 859 ranges;
1019 status = "disabled"; 860 status = "disabled";
1020 861
1021 i2c14: i2c@880000 { 862 i2c14: i2c@880000 {
1022 compatible = 863 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 864 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 865 clock-names = "se";
1025 clocks = <&gc 866 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 867 pinctrl-names = "default";
1027 pinctrl-0 = < 868 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 869 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 870 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 871 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 872 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 873 #address-cells = <1>;
1040 #size-cells = 874 #size-cells = <0>;
1041 status = "dis 875 status = "disabled";
1042 }; 876 };
1043 877
1044 spi14: spi@880000 { 878 spi14: spi@880000 {
1045 compatible = 879 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 880 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 881 clock-names = "se";
1048 clocks = <&gc 882 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 883 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 884 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 885 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 886 dma-names = "tx", "rx";
1053 power-domains !! 887 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 888 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 889 #address-cells = <1>;
1062 #size-cells = 890 #size-cells = <0>;
1063 status = "dis 891 status = "disabled";
1064 }; 892 };
1065 893
1066 i2c15: i2c@884000 { 894 i2c15: i2c@884000 {
1067 compatible = 895 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 896 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 897 clock-names = "se";
1070 clocks = <&gc 898 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 899 pinctrl-names = "default";
1072 pinctrl-0 = < 900 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 901 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 903 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 904 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 905 #address-cells = <1>;
1085 #size-cells = 906 #size-cells = <0>;
1086 status = "dis 907 status = "disabled";
1087 }; 908 };
1088 909
1089 spi15: spi@884000 { 910 spi15: spi@884000 {
1090 compatible = 911 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 912 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 913 clock-names = "se";
1093 clocks = <&gc 914 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 915 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 916 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 917 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 918 dma-names = "tx", "rx";
1098 power-domains !! 919 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 920 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 921 #address-cells = <1>;
1107 #size-cells = 922 #size-cells = <0>;
1108 status = "dis 923 status = "disabled";
1109 }; 924 };
1110 925
1111 i2c16: i2c@888000 { 926 i2c16: i2c@888000 {
1112 compatible = 927 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 928 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 929 clock-names = "se";
1115 clocks = <&gc 930 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 931 pinctrl-names = "default";
1117 pinctrl-0 = < 932 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 933 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 934 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 935 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 936 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 937 #address-cells = <1>;
1130 #size-cells = 938 #size-cells = <0>;
1131 status = "dis 939 status = "disabled";
1132 }; 940 };
1133 941
1134 spi16: spi@888000 { 942 spi16: spi@888000 {
1135 compatible = 943 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 944 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 945 clock-names = "se";
1138 clocks = <&gc 946 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 947 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 948 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 949 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 950 dma-names = "tx", "rx";
1143 power-domains !! 951 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 952 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 953 #address-cells = <1>;
1152 #size-cells = 954 #size-cells = <0>;
1153 status = "dis 955 status = "disabled";
1154 }; 956 };
1155 957
1156 i2c17: i2c@88c000 { 958 i2c17: i2c@88c000 {
1157 compatible = 959 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 960 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 961 clock-names = "se";
1160 clocks = <&gc 962 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 963 pinctrl-names = "default";
1162 pinctrl-0 = < 964 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 965 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 966 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 967 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 968 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 969 #address-cells = <1>;
1175 #size-cells = 970 #size-cells = <0>;
1176 status = "dis 971 status = "disabled";
1177 }; 972 };
1178 973
1179 spi17: spi@88c000 { 974 spi17: spi@88c000 {
1180 compatible = 975 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 976 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 977 clock-names = "se";
1183 clocks = <&gc 978 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 979 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 980 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 981 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 982 dma-names = "tx", "rx";
1188 power-domains !! 983 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 984 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 985 #address-cells = <1>;
1197 #size-cells = 986 #size-cells = <0>;
1198 status = "dis 987 status = "disabled";
1199 }; 988 };
1200 989
1201 uart17: serial@88c000 990 uart17: serial@88c000 {
1202 compatible = 991 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 992 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 993 clock-names = "se";
1205 clocks = <&gc 994 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 995 pinctrl-names = "default";
1207 pinctrl-0 = < 996 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 997 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 998 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 999 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1000 status = "disabled";
1216 }; 1001 };
1217 1002
1218 i2c18: i2c@890000 { 1003 i2c18: i2c@890000 {
1219 compatible = 1004 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1005 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1006 clock-names = "se";
1222 clocks = <&gc 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1008 pinctrl-names = "default";
1224 pinctrl-0 = < 1009 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1010 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1011 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1012 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1013 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1014 #address-cells = <1>;
1237 #size-cells = 1015 #size-cells = <0>;
1238 status = "dis 1016 status = "disabled";
1239 }; 1017 };
1240 1018
1241 spi18: spi@890000 { 1019 spi18: spi@890000 {
1242 compatible = 1020 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1021 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1022 clock-names = "se";
1245 clocks = <&gc 1023 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1024 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1025 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1026 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1027 dma-names = "tx", "rx";
1250 power-domains !! 1028 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 1029 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1030 #address-cells = <1>;
1259 #size-cells = 1031 #size-cells = <0>;
1260 status = "dis 1032 status = "disabled";
1261 }; 1033 };
1262 1034
1263 uart18: serial@890000 1035 uart18: serial@890000 {
1264 compatible = 1036 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1037 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1038 clock-names = "se";
1267 clocks = <&gc 1039 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1040 pinctrl-names = "default";
1269 pinctrl-0 = < 1041 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1042 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 1043 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 1044 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1045 status = "disabled";
1278 }; 1046 };
1279 1047
1280 i2c19: i2c@894000 { 1048 i2c19: i2c@894000 {
1281 compatible = 1049 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1050 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1051 clock-names = "se";
1284 clocks = <&gc 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1053 pinctrl-names = "default";
1286 pinctrl-0 = < 1054 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1055 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1056 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1057 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1058 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1059 #address-cells = <1>;
1299 #size-cells = 1060 #size-cells = <0>;
1300 status = "dis 1061 status = "disabled";
1301 }; 1062 };
1302 1063
1303 spi19: spi@894000 { 1064 spi19: spi@894000 {
1304 compatible = 1065 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1066 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1067 clock-names = "se";
1307 clocks = <&gc 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1069 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1070 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1071 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1072 dma-names = "tx", "rx";
1312 power-domains !! 1073 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 1074 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1075 #address-cells = <1>;
1321 #size-cells = 1076 #size-cells = <0>;
1322 status = "dis 1077 status = "disabled";
1323 }; 1078 };
1324 }; 1079 };
1325 1080
1326 gpi_dma0: dma-controller@9000 1081 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm !! 1082 compatible = "qcom,sm8250-gpi-dma";
1328 reg = <0 0x00900000 0 1083 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1084 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1085 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1086 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1087 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1088 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1089 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1090 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1091 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1092 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1093 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1094 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1095 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1096 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1097 dma-channels = <15>;
1343 dma-channel-mask = <0 1098 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1099 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1100 #dma-cells = <3>;
1346 status = "disabled"; 1101 status = "disabled";
1347 }; 1102 };
1348 1103
1349 qupv3_id_0: geniqup@9c0000 { 1104 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1105 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1106 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1107 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1108 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1109 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1110 #address-cells = <2>;
1356 #size-cells = <2>; 1111 #size-cells = <2>;
1357 iommus = <&apps_smmu 1112 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1113 ranges;
1359 status = "disabled"; 1114 status = "disabled";
1360 1115
1361 i2c0: i2c@980000 { 1116 i2c0: i2c@980000 {
1362 compatible = 1117 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1118 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1119 clock-names = "se";
1365 clocks = <&gc 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1121 pinctrl-names = "default";
1367 pinctrl-0 = < 1122 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1123 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1124 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1125 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1126 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1127 #address-cells = <1>;
1380 #size-cells = 1128 #size-cells = <0>;
1381 status = "dis 1129 status = "disabled";
1382 }; 1130 };
1383 1131
1384 spi0: spi@980000 { 1132 spi0: spi@980000 {
1385 compatible = 1133 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1134 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1135 clock-names = "se";
1388 clocks = <&gc 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1137 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1138 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1139 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1140 dma-names = "tx", "rx";
1393 power-domains !! 1141 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 1142 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1143 #address-cells = <1>;
1402 #size-cells = 1144 #size-cells = <0>;
1403 status = "dis 1145 status = "disabled";
1404 }; 1146 };
1405 1147
1406 i2c1: i2c@984000 { 1148 i2c1: i2c@984000 {
1407 compatible = 1149 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1150 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1151 clock-names = "se";
1410 clocks = <&gc 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1153 pinctrl-names = "default";
1412 pinctrl-0 = < 1154 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1155 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1156 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1157 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1158 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1159 #address-cells = <1>;
1425 #size-cells = 1160 #size-cells = <0>;
1426 status = "dis 1161 status = "disabled";
1427 }; 1162 };
1428 1163
1429 spi1: spi@984000 { 1164 spi1: spi@984000 {
1430 compatible = 1165 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1166 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1167 clock-names = "se";
1433 clocks = <&gc 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1169 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1170 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1171 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1172 dma-names = "tx", "rx";
1438 power-domains !! 1173 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 1174 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1175 #address-cells = <1>;
1447 #size-cells = 1176 #size-cells = <0>;
1448 status = "dis 1177 status = "disabled";
1449 }; 1178 };
1450 1179
1451 i2c2: i2c@988000 { 1180 i2c2: i2c@988000 {
1452 compatible = 1181 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1182 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1183 clock-names = "se";
1455 clocks = <&gc 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1185 pinctrl-names = "default";
1457 pinctrl-0 = < 1186 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1187 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1188 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1189 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1190 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1191 #address-cells = <1>;
1470 #size-cells = 1192 #size-cells = <0>;
1471 status = "dis 1193 status = "disabled";
1472 }; 1194 };
1473 1195
1474 spi2: spi@988000 { 1196 spi2: spi@988000 {
1475 compatible = 1197 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1198 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1199 clock-names = "se";
1478 clocks = <&gc 1200 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1201 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1202 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1203 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1204 dma-names = "tx", "rx";
1483 power-domains !! 1205 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 1206 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1207 #address-cells = <1>;
1492 #size-cells = 1208 #size-cells = <0>;
1493 status = "dis 1209 status = "disabled";
1494 }; 1210 };
1495 1211
1496 uart2: serial@988000 1212 uart2: serial@988000 {
1497 compatible = 1213 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1214 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1215 clock-names = "se";
1500 clocks = <&gc 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1217 pinctrl-names = "default";
1502 pinctrl-0 = < 1218 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1219 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 1220 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 1221 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1222 status = "disabled";
1511 }; 1223 };
1512 1224
1513 i2c3: i2c@98c000 { 1225 i2c3: i2c@98c000 {
1514 compatible = 1226 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1227 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1228 clock-names = "se";
1517 clocks = <&gc 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1230 pinctrl-names = "default";
1519 pinctrl-0 = < 1231 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1232 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1233 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1234 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1235 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1236 #address-cells = <1>;
1532 #size-cells = 1237 #size-cells = <0>;
1533 status = "dis 1238 status = "disabled";
1534 }; 1239 };
1535 1240
1536 spi3: spi@98c000 { 1241 spi3: spi@98c000 {
1537 compatible = 1242 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1243 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1244 clock-names = "se";
1540 clocks = <&gc 1245 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1246 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1247 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1248 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1249 dma-names = "tx", "rx";
1545 power-domains !! 1250 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 1251 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1252 #address-cells = <1>;
1554 #size-cells = 1253 #size-cells = <0>;
1555 status = "dis 1254 status = "disabled";
1556 }; 1255 };
1557 1256
1558 i2c4: i2c@990000 { 1257 i2c4: i2c@990000 {
1559 compatible = 1258 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1259 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1260 clock-names = "se";
1562 clocks = <&gc 1261 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1262 pinctrl-names = "default";
1564 pinctrl-0 = < 1263 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1264 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1265 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1266 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1267 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1268 #address-cells = <1>;
1577 #size-cells = 1269 #size-cells = <0>;
1578 status = "dis 1270 status = "disabled";
1579 }; 1271 };
1580 1272
1581 spi4: spi@990000 { 1273 spi4: spi@990000 {
1582 compatible = 1274 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1275 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1276 clock-names = "se";
1585 clocks = <&gc 1277 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1278 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1279 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1280 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1281 dma-names = "tx", "rx";
1590 power-domains !! 1282 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 1283 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1284 #address-cells = <1>;
1599 #size-cells = 1285 #size-cells = <0>;
1600 status = "dis 1286 status = "disabled";
1601 }; 1287 };
1602 1288
1603 i2c5: i2c@994000 { 1289 i2c5: i2c@994000 {
1604 compatible = 1290 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1291 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1292 clock-names = "se";
1607 clocks = <&gc 1293 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1294 pinctrl-names = "default";
1609 pinctrl-0 = < 1295 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1296 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1297 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1298 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1299 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1300 #address-cells = <1>;
1622 #size-cells = 1301 #size-cells = <0>;
1623 status = "dis 1302 status = "disabled";
1624 }; 1303 };
1625 1304
1626 spi5: spi@994000 { 1305 spi5: spi@994000 {
1627 compatible = 1306 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1307 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1308 clock-names = "se";
1630 clocks = <&gc 1309 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1310 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1311 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1312 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1313 dma-names = "tx", "rx";
1635 power-domains !! 1314 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1315 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1316 #address-cells = <1>;
1644 #size-cells = 1317 #size-cells = <0>;
1645 status = "dis 1318 status = "disabled";
1646 }; 1319 };
1647 1320
1648 i2c6: i2c@998000 { 1321 i2c6: i2c@998000 {
1649 compatible = 1322 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1323 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1324 clock-names = "se";
1652 clocks = <&gc 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1326 pinctrl-names = "default";
1654 pinctrl-0 = < 1327 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1328 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1329 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1330 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1331 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1332 #address-cells = <1>;
1667 #size-cells = 1333 #size-cells = <0>;
1668 status = "dis 1334 status = "disabled";
1669 }; 1335 };
1670 1336
1671 spi6: spi@998000 { 1337 spi6: spi@998000 {
1672 compatible = 1338 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1339 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1340 clock-names = "se";
1675 clocks = <&gc 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1342 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1343 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1344 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1345 dma-names = "tx", "rx";
1680 power-domains !! 1346 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1347 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1348 #address-cells = <1>;
1689 #size-cells = 1349 #size-cells = <0>;
1690 status = "dis 1350 status = "disabled";
1691 }; 1351 };
1692 1352
1693 uart6: serial@998000 1353 uart6: serial@998000 {
1694 compatible = 1354 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1355 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1356 clock-names = "se";
1697 clocks = <&gc 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1358 pinctrl-names = "default";
1699 pinctrl-0 = < 1359 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1360 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1361 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1362 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1363 status = "disabled";
1708 }; 1364 };
1709 1365
1710 i2c7: i2c@99c000 { 1366 i2c7: i2c@99c000 {
1711 compatible = 1367 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1368 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1369 clock-names = "se";
1714 clocks = <&gc 1370 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1371 pinctrl-names = "default";
1716 pinctrl-0 = < 1372 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1373 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1374 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1375 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1376 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1377 #address-cells = <1>;
1729 #size-cells = 1378 #size-cells = <0>;
1730 status = "dis 1379 status = "disabled";
1731 }; 1380 };
1732 1381
1733 spi7: spi@99c000 { 1382 spi7: spi@99c000 {
1734 compatible = 1383 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1384 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1385 clock-names = "se";
1737 clocks = <&gc 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1387 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1388 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1389 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1390 dma-names = "tx", "rx";
1742 power-domains !! 1391 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1392 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1393 #address-cells = <1>;
1751 #size-cells = 1394 #size-cells = <0>;
1752 status = "dis 1395 status = "disabled";
1753 }; 1396 };
1754 }; 1397 };
1755 1398
1756 gpi_dma1: dma-controller@a000 1399 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm !! 1400 compatible = "qcom,sm8250-gpi-dma";
1758 reg = <0 0x00a00000 0 1401 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1402 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1403 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1404 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1405 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1406 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1407 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1408 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1409 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1410 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1411 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1412 dma-channels = <10>;
1770 dma-channel-mask = <0 1413 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1414 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1415 #dma-cells = <3>;
1773 status = "disabled"; 1416 status = "disabled";
1774 }; 1417 };
1775 1418
1776 qupv3_id_1: geniqup@ac0000 { 1419 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1420 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1421 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1422 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1423 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1424 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1425 #address-cells = <2>;
1783 #size-cells = <2>; 1426 #size-cells = <2>;
1784 iommus = <&apps_smmu 1427 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1428 ranges;
1786 status = "disabled"; 1429 status = "disabled";
1787 1430
1788 i2c8: i2c@a80000 { 1431 i2c8: i2c@a80000 {
1789 compatible = 1432 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1433 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1434 clock-names = "se";
1792 clocks = <&gc 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1436 pinctrl-names = "default";
1794 pinctrl-0 = < 1437 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1438 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1439 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1440 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1441 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1442 #address-cells = <1>;
1807 #size-cells = 1443 #size-cells = <0>;
1808 status = "dis 1444 status = "disabled";
1809 }; 1445 };
1810 1446
1811 spi8: spi@a80000 { 1447 spi8: spi@a80000 {
1812 compatible = 1448 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1449 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1450 clock-names = "se";
1815 clocks = <&gc 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1452 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1453 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1454 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1455 dma-names = "tx", "rx";
1820 power-domains !! 1456 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1457 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1458 #address-cells = <1>;
1829 #size-cells = 1459 #size-cells = <0>;
1830 status = "dis 1460 status = "disabled";
1831 }; 1461 };
1832 1462
1833 i2c9: i2c@a84000 { 1463 i2c9: i2c@a84000 {
1834 compatible = 1464 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1465 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1466 clock-names = "se";
1837 clocks = <&gc 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1468 pinctrl-names = "default";
1839 pinctrl-0 = < 1469 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1470 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1471 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1472 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1473 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1474 #address-cells = <1>;
1852 #size-cells = 1475 #size-cells = <0>;
1853 status = "dis 1476 status = "disabled";
1854 }; 1477 };
1855 1478
1856 spi9: spi@a84000 { 1479 spi9: spi@a84000 {
1857 compatible = 1480 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1481 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1482 clock-names = "se";
1860 clocks = <&gc 1483 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1484 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1485 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1486 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1487 dma-names = "tx", "rx";
1865 power-domains !! 1488 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1489 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1490 #address-cells = <1>;
1874 #size-cells = 1491 #size-cells = <0>;
1875 status = "dis 1492 status = "disabled";
1876 }; 1493 };
1877 1494
1878 i2c10: i2c@a88000 { 1495 i2c10: i2c@a88000 {
1879 compatible = 1496 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1497 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1498 clock-names = "se";
1882 clocks = <&gc 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1500 pinctrl-names = "default";
1884 pinctrl-0 = < 1501 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1502 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1503 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1504 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1505 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1506 #address-cells = <1>;
1897 #size-cells = 1507 #size-cells = <0>;
1898 status = "dis 1508 status = "disabled";
1899 }; 1509 };
1900 1510
1901 spi10: spi@a88000 { 1511 spi10: spi@a88000 {
1902 compatible = 1512 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1513 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1514 clock-names = "se";
1905 clocks = <&gc 1515 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1516 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1517 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1518 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1519 dma-names = "tx", "rx";
1910 power-domains !! 1520 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1521 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1522 #address-cells = <1>;
1919 #size-cells = 1523 #size-cells = <0>;
1920 status = "dis 1524 status = "disabled";
1921 }; 1525 };
1922 1526
1923 i2c11: i2c@a8c000 { 1527 i2c11: i2c@a8c000 {
1924 compatible = 1528 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1529 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1530 clock-names = "se";
1927 clocks = <&gc 1531 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1532 pinctrl-names = "default";
1929 pinctrl-0 = < 1533 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1534 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1535 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1536 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1537 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1538 #address-cells = <1>;
1942 #size-cells = 1539 #size-cells = <0>;
1943 status = "dis 1540 status = "disabled";
1944 }; 1541 };
1945 1542
1946 spi11: spi@a8c000 { 1543 spi11: spi@a8c000 {
1947 compatible = 1544 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1545 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1546 clock-names = "se";
1950 clocks = <&gc 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1548 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1549 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1550 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1551 dma-names = "tx", "rx";
1955 power-domains !! 1552 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1553 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1554 #address-cells = <1>;
1964 #size-cells = 1555 #size-cells = <0>;
1965 status = "dis 1556 status = "disabled";
1966 }; 1557 };
1967 1558
1968 i2c12: i2c@a90000 { 1559 i2c12: i2c@a90000 {
1969 compatible = 1560 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1561 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1562 clock-names = "se";
1972 clocks = <&gc 1563 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1564 pinctrl-names = "default";
1974 pinctrl-0 = < 1565 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1566 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1567 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1568 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1569 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1570 #address-cells = <1>;
1987 #size-cells = 1571 #size-cells = <0>;
1988 status = "dis 1572 status = "disabled";
1989 }; 1573 };
1990 1574
1991 spi12: spi@a90000 { 1575 spi12: spi@a90000 {
1992 compatible = 1576 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1577 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1578 clock-names = "se";
1995 clocks = <&gc 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1580 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1581 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1582 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1583 dma-names = "tx", "rx";
2000 power-domains !! 1584 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1585 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1586 #address-cells = <1>;
2009 #size-cells = 1587 #size-cells = <0>;
2010 status = "dis 1588 status = "disabled";
2011 }; 1589 };
2012 1590
2013 uart12: serial@a90000 1591 uart12: serial@a90000 {
2014 compatible = 1592 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1593 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1594 clock-names = "se";
2017 clocks = <&gc 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1596 pinctrl-names = "default";
2019 pinctrl-0 = < 1597 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1598 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1599 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1600 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1601 status = "disabled";
2028 }; 1602 };
2029 1603
2030 i2c13: i2c@a94000 { 1604 i2c13: i2c@a94000 {
2031 compatible = 1605 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1606 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1607 clock-names = "se";
2034 clocks = <&gc 1608 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1609 pinctrl-names = "default";
2036 pinctrl-0 = < 1610 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1611 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1612 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1613 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1614 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1615 #address-cells = <1>;
2049 #size-cells = 1616 #size-cells = <0>;
2050 status = "dis 1617 status = "disabled";
2051 }; 1618 };
2052 1619
2053 spi13: spi@a94000 { 1620 spi13: spi@a94000 {
2054 compatible = 1621 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1622 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1623 clock-names = "se";
2057 clocks = <&gc 1624 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1625 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1626 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1627 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1628 dma-names = "tx", "rx";
2062 power-domains !! 1629 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1630 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1631 #address-cells = <1>;
2071 #size-cells = 1632 #size-cells = <0>;
2072 status = "dis 1633 status = "disabled";
2073 }; 1634 };
2074 }; 1635 };
2075 1636
2076 config_noc: interconnect@1500 1637 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1638 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1639 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1640 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1641 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1642 };
2082 1643
2083 system_noc: interconnect@1620 1644 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1645 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1646 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1647 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1648 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1649 };
2089 1650
2090 mc_virt: interconnect@163d000 1651 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1652 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1653 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1654 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1655 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1656 };
2096 1657
2097 aggre1_noc: interconnect@16e0 1658 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1659 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1660 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1661 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1662 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1663 };
2103 1664
2104 aggre2_noc: interconnect@1700 1665 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1666 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1667 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1668 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1669 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1670 };
2110 1671
2111 compute_noc: interconnect@173 1672 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1673 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1674 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1675 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1676 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1677 };
2117 1678
2118 mmss_noc: interconnect@174000 1679 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1680 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1681 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1682 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1683 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1684 };
2124 1685
2125 pcie0: pcie@1c00000 { !! 1686 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1687 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1688 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1689 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1690 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1691 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1692 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1693 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1694 device_type = "pci";
2135 linux,pci-domain = <0 1695 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1696 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1697 num-lanes = <1>;
2138 1698
2139 #address-cells = <3>; 1699 #address-cells = <3>;
2140 #size-cells = <2>; 1700 #size-cells = <2>;
2141 1701
2142 ranges = <0x01000000 !! 1702 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1703 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1704
2145 interrupts = <GIC_SPI !! 1705 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1706 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1707 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1708 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1709 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1710 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1711 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1712 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1713
2168 clocks = <&gcc GCC_PC 1714 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1715 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1716 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1717 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1718 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1719 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1720 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1721 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1722 clock-names = "pipe",
2177 "aux", 1723 "aux",
2178 "cfg", 1724 "cfg",
2179 "bus_ma 1725 "bus_master",
2180 "bus_sl 1726 "bus_slave",
2181 "slave_ 1727 "slave_q2a",
2182 "tbu", 1728 "tbu",
2183 "ddrss_ 1729 "ddrss_sf_tbu";
2184 1730
>> 1731 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1732 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1733 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1734
2188 resets = <&gcc GCC_PC 1735 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1736 reset-names = "pci";
2190 1737
2191 power-domains = <&gcc 1738 power-domains = <&gcc PCIE_0_GDSC>;
2192 1739
2193 phys = <&pcie0_phy>; !! 1740 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1741 phy-names = "pciephy";
2195 1742
2196 perst-gpios = <&tlmm 1743 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1744 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1745
2199 pinctrl-names = "defa 1746 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1747 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1748
2203 status = "disabled"; 1749 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1750 };
2215 1751
2216 pcie0_phy: phy@1c06000 { 1752 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1753 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1754 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1755 #address-cells = <2>;
>> 1756 #size-cells = <2>;
>> 1757 ranges;
2220 clocks = <&gcc GCC_PC 1758 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1759 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1760 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1761 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1762 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1763
2236 resets = <&gcc GCC_PC 1764 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1765 reset-names = "phy";
2238 1766
2239 assigned-clocks = <&g 1767 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1768 assigned-clock-rates = <100000000>;
2241 1769
2242 status = "disabled"; 1770 status = "disabled";
>> 1771
>> 1772 pcie0_lane: phy@1c06200 {
>> 1773 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1774 <0 0x1c06400 0 0x200>, /* rx */
>> 1775 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1776 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1777 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1778 clock-names = "pipe0";
>> 1779
>> 1780 #phy-cells = <0>;
>> 1781 clock-output-names = "pcie_0_pipe_clk";
>> 1782 };
2243 }; 1783 };
2244 1784
2245 pcie1: pcie@1c08000 { !! 1785 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1786 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1787 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1788 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1789 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1790 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1791 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1792 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1793 device_type = "pci";
2255 linux,pci-domain = <1 1794 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1795 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1796 num-lanes = <2>;
2258 1797
2259 #address-cells = <3>; 1798 #address-cells = <3>;
2260 #size-cells = <2>; 1799 #size-cells = <2>;
2261 1800
2262 ranges = <0x01000000 !! 1801 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1802 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1803
2265 interrupts = <GIC_SPI !! 1804 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1805 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1806 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1807 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1808 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1809 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1810 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1811 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1812
2288 clocks = <&gcc GCC_PC 1813 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1814 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1815 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1816 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1817 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1818 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1819 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1820 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1821 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1822 clock-names = "pipe",
2298 "aux", 1823 "aux",
2299 "cfg", 1824 "cfg",
2300 "bus_ma 1825 "bus_master",
2301 "bus_sl 1826 "bus_slave",
2302 "slave_ 1827 "slave_q2a",
2303 "ref", 1828 "ref",
2304 "tbu", 1829 "tbu",
2305 "ddrss_ 1830 "ddrss_sf_tbu";
2306 1831
2307 assigned-clocks = <&g 1832 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1833 assigned-clock-rates = <19200000>;
2309 1834
>> 1835 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1836 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1837 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1838
2313 resets = <&gcc GCC_PC 1839 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1840 reset-names = "pci";
2315 1841
2316 power-domains = <&gcc 1842 power-domains = <&gcc PCIE_1_GDSC>;
2317 1843
2318 phys = <&pcie1_phy>; !! 1844 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1845 phy-names = "pciephy";
2320 1846
2321 perst-gpios = <&tlmm 1847 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1848 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1849
2324 pinctrl-names = "defa 1850 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1851 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1852
2328 status = "disabled"; 1853 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1854 };
2340 1855
2341 pcie1_phy: phy@1c0e000 { 1856 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1857 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1858 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1859 #address-cells = <2>;
>> 1860 #size-cells = <2>;
>> 1861 ranges;
2345 clocks = <&gcc GCC_PC 1862 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1863 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1864 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1865 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1866 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1867
2361 resets = <&gcc GCC_PC 1868 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1869 reset-names = "phy";
2363 1870
2364 assigned-clocks = <&g 1871 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1872 assigned-clock-rates = <100000000>;
2366 1873
2367 status = "disabled"; 1874 status = "disabled";
>> 1875
>> 1876 pcie1_lane: phy@1c0e200 {
>> 1877 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1878 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1879 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1880 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1881 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1882 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1883 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1884 clock-names = "pipe0";
>> 1885
>> 1886 #phy-cells = <0>;
>> 1887 clock-output-names = "pcie_1_pipe_clk";
>> 1888 };
2368 }; 1889 };
2369 1890
2370 pcie2: pcie@1c10000 { !! 1891 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 1892 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 1893 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 1894 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 1895 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 1896 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 1897 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 1898 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 1899 device_type = "pci";
2380 linux,pci-domain = <2 1900 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 1901 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 1902 num-lanes = <2>;
2383 1903
2384 #address-cells = <3>; 1904 #address-cells = <3>;
2385 #size-cells = <2>; 1905 #size-cells = <2>;
2386 1906
2387 ranges = <0x01000000 !! 1907 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 1908 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 1909
2390 interrupts = <GIC_SPI !! 1910 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 1911 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 1912 #interrupt-cells = <1>;
2407 interrupt-map-mask = 1913 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 1914 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 1915 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 1916 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 1917 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 1918
2413 clocks = <&gcc GCC_PC 1919 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 1920 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 1921 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 1922 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 1923 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 1924 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 1925 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 1926 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 1927 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 1928 clock-names = "pipe",
2423 "aux", 1929 "aux",
2424 "cfg", 1930 "cfg",
2425 "bus_ma 1931 "bus_master",
2426 "bus_sl 1932 "bus_slave",
2427 "slave_ 1933 "slave_q2a",
2428 "ref", 1934 "ref",
2429 "tbu", 1935 "tbu",
2430 "ddrss_ 1936 "ddrss_sf_tbu";
2431 1937
2432 assigned-clocks = <&g 1938 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 1939 assigned-clock-rates = <19200000>;
2434 1940
>> 1941 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 1942 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 1943 <0x100 &apps_smmu 0x1d01 0x1>;
2437 1944
2438 resets = <&gcc GCC_PC 1945 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 1946 reset-names = "pci";
2440 1947
2441 power-domains = <&gcc 1948 power-domains = <&gcc PCIE_2_GDSC>;
2442 1949
2443 phys = <&pcie2_phy>; !! 1950 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 1951 phy-names = "pciephy";
2445 1952
2446 perst-gpios = <&tlmm 1953 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 1954 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 1955
2449 pinctrl-names = "defa 1956 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 1957 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 1958
2453 status = "disabled"; 1959 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 1960 };
2465 1961
2466 pcie2_phy: phy@1c16000 { 1962 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 1963 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 1964 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 1965 #address-cells = <2>;
>> 1966 #size-cells = <2>;
>> 1967 ranges;
2470 clocks = <&gcc GCC_PC 1968 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 1969 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 1970 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 1971 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 1972 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 1973
2486 resets = <&gcc GCC_PC 1974 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 1975 reset-names = "phy";
2488 1976
2489 assigned-clocks = <&g 1977 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 1978 assigned-clock-rates = <100000000>;
2491 1979
2492 status = "disabled"; 1980 status = "disabled";
>> 1981
>> 1982 pcie2_lane: phy@1c16200 {
>> 1983 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 1984 <0 0x1c16400 0 0x200>, /* rx0 */
>> 1985 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 1986 <0 0x1c16600 0 0x170>, /* tx1 */
>> 1987 <0 0x1c16800 0 0x200>, /* rx1 */
>> 1988 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1989 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 1990 clock-names = "pipe0";
>> 1991
>> 1992 #phy-cells = <0>;
>> 1993 clock-output-names = "pcie_2_pipe_clk";
>> 1994 };
2493 }; 1995 };
2494 1996
2495 ufs_mem_hc: ufshc@1d84000 { 1997 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 1998 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 1999 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2000 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2001 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2002 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2003 phy-names = "ufsphy";
2502 lanes-per-direction = 2004 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2005 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2006 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2007 reset-names = "rst";
2506 2008
2507 power-domains = <&gcc 2009 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2010
2509 iommus = <&apps_smmu 2011 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2012
2511 clock-names = 2013 clock-names =
2512 "core_clk", 2014 "core_clk",
2513 "bus_aggr_clk 2015 "bus_aggr_clk",
2514 "iface_clk", 2016 "iface_clk",
2515 "core_clk_uni 2017 "core_clk_unipro",
2516 "ref_clk", 2018 "ref_clk",
2517 "tx_lane0_syn 2019 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2020 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2021 "rx_lane1_sync_clk";
2520 clocks = 2022 clocks =
2521 <&gcc GCC_UFS 2023 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2024 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2025 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2026 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2027 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2028 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2029 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2030 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2031 freq-table-hz =
2530 operating-points-v2 = !! 2032 <37500000 300000000>,
2531 !! 2033 <0 0>,
2532 interconnects = <&agg !! 2034 <0 0>,
2533 <&gem !! 2035 <37500000 300000000>,
2534 interconnect-names = !! 2036 <0 0>,
>> 2037 <0 0>,
>> 2038 <0 0>,
>> 2039 <0 0>;
2535 2040
2536 status = "disabled"; 2041 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2042 };
2566 2043
2567 ufs_mem_phy: phy@1d87000 { 2044 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2045 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2046 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2047 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2048 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2049 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2050 clock-names = "ref",
2575 "ref_au !! 2051 "ref_aux";
2576 "qref"; !! 2052 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2053 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2054
2578 resets = <&ufs_mem_hc 2055 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2056 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2057 status = "disabled";
>> 2058
>> 2059 ufs_mem_phy_lanes: phy@1d87400 {
>> 2060 reg = <0 0x01d87400 0 0x108>,
>> 2061 <0 0x01d87600 0 0x1e0>,
>> 2062 <0 0x01d87c00 0 0x1dc>,
>> 2063 <0 0x01d87800 0 0x108>,
>> 2064 <0 0x01d87a00 0 0x1e0>;
>> 2065 #phy-cells = <0>;
>> 2066 };
2586 }; 2067 };
2587 2068
2588 cryptobam: dma-controller@1dc !! 2069 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 2070 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 2071 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 2072 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 2073 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 2074 };
2619 2075
2620 tcsr_mutex: hwlock@1f40000 { 2076 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2077 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2078 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2079 #hwlock-cells = <1>;
2624 }; 2080 };
2625 2081
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2082 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2083 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2084 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2085 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 2086 <&audiocc 0>,
2636 <&q6afecc LP 2087 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2088 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2089 <&aoncc 0>,
2638 <&vamacro>; 2090 <&vamacro>;
2639 2091
2640 clock-names = "mclk", !! 2092 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2093
2642 #clock-cells = <0>; 2094 #clock-cells = <0>;
>> 2095 clock-frequency = <9600000>;
2643 clock-output-names = 2096 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2097 #sound-dai-cells = <1>;
2645 2098
2646 pinctrl-names = "defa 2099 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2100 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 2101 };
2651 2102
2652 swr0: soundwire@3250000 { !! 2103 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2104 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2105 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2106 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2107 clocks = <&wsamacro>;
2657 clock-names = "iface" 2108 clock-names = "iface";
2658 2109
2659 qcom,din-ports = <2>; 2110 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2111 qcom,dout-ports = <6>;
2661 2112
2662 qcom,ports-sinterval- 2113 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2114 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2115 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2116 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2117
2667 #sound-dai-cells = <1 2118 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2119 #address-cells = <2>;
2669 #size-cells = <0>; 2120 #size-cells = <0>;
>> 2121 };
2670 2122
2671 status = "disabled"; !! 2123 audiocc: clock-controller@3300000 {
>> 2124 compatible = "qcom,sm8250-lpass-audiocc";
>> 2125 reg = <0 0x03300000 0 0x30000>;
>> 2126 #clock-cells = <1>;
>> 2127 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2128 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2129 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2130 clock-names = "core", "audio", "bus";
2672 }; 2131 };
2673 2132
2674 vamacro: codec@3370000 { 2133 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2134 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2135 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2136 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 2137 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2138 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2139
2681 clock-names = "mclk", 2140 clock-names = "mclk", "macro", "dcodec";
2682 2141
2683 #clock-cells = <0>; 2142 #clock-cells = <0>;
>> 2143 clock-frequency = <9600000>;
2684 clock-output-names = 2144 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2145 #sound-dai-cells = <1>;
2686 }; 2146 };
2687 2147
2688 rxmacro: rxmacro@3200000 { 2148 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2149 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2150 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2151 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 !! 2152 reg = <0 0x3200000 0 0x1000>;
2693 status = "disabled"; 2153 status = "disabled";
2694 2154
2695 clocks = <&q6afecc LP 2155 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2156 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2157 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2158 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2159 <&vamacro>;
2700 2160
2701 clock-names = "mclk", 2161 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2162
2703 #clock-cells = <0>; 2163 #clock-cells = <0>;
>> 2164 clock-frequency = <9600000>;
2704 clock-output-names = 2165 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2166 #sound-dai-cells = <1>;
2706 }; 2167 };
2707 2168
2708 swr1: soundwire@3210000 { !! 2169 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 !! 2170 reg = <0 0x3210000 0 0x2000>;
2710 compatible = "qcom,so 2171 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2172 status = "disabled";
2712 interrupts = <GIC_SPI 2173 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2174 clocks = <&rxmacro>;
2714 clock-names = "iface" 2175 clock-names = "iface";
2715 label = "RX"; 2176 label = "RX";
2716 qcom,din-ports = <0>; 2177 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2178 qcom,dout-ports = <5>;
2718 2179
2719 qcom,ports-sinterval- !! 2180 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2720 qcom,ports-offset1 = !! 2181 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2721 qcom,ports-offset2 = !! 2182 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2722 qcom,ports-hstart = !! 2183 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2723 qcom,ports-hstop = !! 2184 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2724 qcom,ports-word-lengt !! 2185 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2725 qcom,ports-block-pack !! 2186 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2726 qcom,ports-lane-contr 2187 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou !! 2188 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2728 2189
2729 #sound-dai-cells = <1 2190 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2191 #address-cells = <2>;
2731 #size-cells = <0>; 2192 #size-cells = <0>;
2732 }; 2193 };
2733 2194
2734 txmacro: txmacro@3220000 { 2195 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2196 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2197 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2198 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 !! 2199 reg = <0 0x3220000 0 0x1000>;
2739 status = "disabled"; 2200 status = "disabled";
2740 2201
2741 clocks = <&q6afecc LP 2202 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2203 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2204 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2205 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2206 <&vamacro>;
2746 2207
2747 clock-names = "mclk", 2208 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2209
2749 #clock-cells = <0>; 2210 #clock-cells = <0>;
>> 2211 clock-frequency = <9600000>;
2750 clock-output-names = 2212 clock-output-names = "mclk";
>> 2213 #address-cells = <2>;
>> 2214 #size-cells = <2>;
2751 #sound-dai-cells = <1 2215 #sound-dai-cells = <1>;
2752 }; 2216 };
2753 2217
2754 /* tx macro */ 2218 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2219 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 !! 2220 reg = <0 0x3230000 0 0x2000>;
2757 compatible = "qcom,so 2221 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI !! 2222 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2223 interrupt-names = "core";
2760 status = "disabled"; 2224 status = "disabled";
2761 2225
2762 clocks = <&txmacro>; 2226 clocks = <&txmacro>;
2763 clock-names = "iface" 2227 clock-names = "iface";
2764 label = "TX"; 2228 label = "TX";
2765 2229
2766 qcom,din-ports = <5>; 2230 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2231 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- !! 2232 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = !! 2233 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = !! 2234 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack !! 2235 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2772 qcom,ports-hstart = !! 2236 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2773 qcom,ports-hstop = !! 2237 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2774 qcom,ports-word-lengt !! 2238 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2775 qcom,ports-block-grou !! 2239 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2776 qcom,ports-lane-contr !! 2240 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
>> 2241 qcom,port-offset = <1>;
2777 #sound-dai-cells = <1 2242 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2243 #address-cells = <2>;
2779 #size-cells = <0>; 2244 #size-cells = <0>;
2780 }; 2245 };
2781 2246
2782 lpass_tlmm: pinctrl@33c0000 { !! 2247 aoncc: clock-controller@3380000 {
>> 2248 compatible = "qcom,sm8250-lpass-aoncc";
>> 2249 reg = <0 0x03380000 0 0x40000>;
>> 2250 #clock-cells = <1>;
>> 2251 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2252 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2253 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2254 clock-names = "core", "audio", "bus";
>> 2255 };
>> 2256
>> 2257 lpass_tlmm: pinctrl@33c0000{
2783 compatible = "qcom,sm 2258 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2259 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2260 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2261 gpio-controller;
2787 #gpio-cells = <2>; 2262 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2263 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2264
2790 clocks = <&q6afecc LP 2265 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2266 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2267 clock-names = "core", "audio";
2793 2268
2794 wsa_swr_active: wsa-s !! 2269 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 2270 clk {
2796 pins 2271 pins = "gpio10";
2797 funct 2272 function = "wsa_swr_clk";
2798 drive 2273 drive-strength = <2>;
2799 slew- 2274 slew-rate = <1>;
2800 bias- 2275 bias-disable;
2801 }; 2276 };
2802 2277
2803 data-pins { !! 2278 data {
2804 pins 2279 pins = "gpio11";
2805 funct 2280 function = "wsa_swr_data";
2806 drive 2281 drive-strength = <2>;
2807 slew- 2282 slew-rate = <1>;
2808 bias- 2283 bias-bus-hold;
>> 2284
2809 }; 2285 };
2810 }; 2286 };
2811 2287
2812 wsa_swr_sleep: wsa-sw !! 2288 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 2289 clk {
2814 pins 2290 pins = "gpio10";
2815 funct 2291 function = "wsa_swr_clk";
2816 drive 2292 drive-strength = <2>;
>> 2293 input-enable;
2817 bias- 2294 bias-pull-down;
2818 }; 2295 };
2819 2296
2820 data-pins { !! 2297 data {
2821 pins 2298 pins = "gpio11";
2822 funct 2299 function = "wsa_swr_data";
2823 drive 2300 drive-strength = <2>;
>> 2301 input-enable;
2824 bias- 2302 bias-pull-down;
>> 2303
2825 }; 2304 };
2826 }; 2305 };
2827 2306
2828 dmic01_active: dmic01 !! 2307 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 2308 clk {
2830 pins 2309 pins = "gpio6";
2831 funct 2310 function = "dmic1_clk";
2832 drive 2311 drive-strength = <8>;
2833 outpu 2312 output-high;
2834 }; 2313 };
2835 data-pins { !! 2314 data {
2836 pins 2315 pins = "gpio7";
2837 funct 2316 function = "dmic1_data";
2838 drive 2317 drive-strength = <8>;
>> 2318 input-enable;
2839 }; 2319 };
2840 }; 2320 };
2841 2321
2842 dmic01_sleep: dmic01- !! 2322 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 2323 clk {
2844 pins 2324 pins = "gpio6";
2845 funct 2325 function = "dmic1_clk";
2846 drive 2326 drive-strength = <2>;
2847 bias- 2327 bias-disable;
2848 outpu 2328 output-low;
2849 }; 2329 };
2850 2330
2851 data-pins { !! 2331 data {
2852 pins 2332 pins = "gpio7";
2853 funct 2333 function = "dmic1_data";
2854 drive 2334 drive-strength = <2>;
2855 bias- !! 2335 pull-down;
>> 2336 input-enable;
2856 }; 2337 };
2857 }; 2338 };
2858 2339
2859 rx_swr_active: rx-swr !! 2340 rx_swr_active: rx_swr-active-pins {
2860 clk-pins { !! 2341 clk {
2861 pins 2342 pins = "gpio3";
2862 funct 2343 function = "swr_rx_clk";
2863 drive 2344 drive-strength = <2>;
2864 slew- 2345 slew-rate = <1>;
2865 bias- 2346 bias-disable;
2866 }; 2347 };
2867 2348
2868 data-pins { !! 2349 data {
2869 pins 2350 pins = "gpio4", "gpio5";
2870 funct 2351 function = "swr_rx_data";
2871 drive 2352 drive-strength = <2>;
2872 slew- 2353 slew-rate = <1>;
2873 bias- 2354 bias-bus-hold;
2874 }; 2355 };
2875 }; 2356 };
2876 2357
2877 tx_swr_active: tx-swr !! 2358 tx_swr_active: tx_swr-active-pins {
2878 clk-pins { !! 2359 clk {
2879 pins 2360 pins = "gpio0";
2880 funct 2361 function = "swr_tx_clk";
2881 drive 2362 drive-strength = <2>;
2882 slew- 2363 slew-rate = <1>;
2883 bias- 2364 bias-disable;
2884 }; 2365 };
2885 2366
2886 data-pins { !! 2367 data {
2887 pins 2368 pins = "gpio1", "gpio2";
2888 funct 2369 function = "swr_tx_data";
2889 drive 2370 drive-strength = <2>;
2890 slew- 2371 slew-rate = <1>;
2891 bias- 2372 bias-bus-hold;
2892 }; 2373 };
2893 }; 2374 };
2894 2375
2895 tx_swr_sleep: tx-swr- !! 2376 tx_swr_sleep: tx_swr-sleep-pins {
2896 clk-pins { !! 2377 clk {
2897 pins 2378 pins = "gpio0";
2898 funct 2379 function = "swr_tx_clk";
2899 drive 2380 drive-strength = <2>;
>> 2381 input-enable;
2900 bias- 2382 bias-pull-down;
2901 }; 2383 };
2902 2384
2903 data1-pins { !! 2385 data1 {
2904 pins 2386 pins = "gpio1";
2905 funct 2387 function = "swr_tx_data";
2906 drive 2388 drive-strength = <2>;
>> 2389 input-enable;
2907 bias- 2390 bias-bus-hold;
2908 }; 2391 };
2909 2392
2910 data2-pins { !! 2393 data2 {
2911 pins 2394 pins = "gpio2";
2912 funct 2395 function = "swr_tx_data";
2913 drive 2396 drive-strength = <2>;
>> 2397 input-enable;
2914 bias- 2398 bias-pull-down;
2915 }; 2399 };
2916 }; 2400 };
2917 }; 2401 };
2918 2402
2919 gpu: gpu@3d00000 { 2403 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2404 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2405 "qcom,adreno";
2922 2406
2923 reg = <0 0x03d00000 0 2407 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2408 reg-names = "kgsl_3d0_reg_memory";
2925 2409
2926 interrupts = <GIC_SPI 2410 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2411
2928 iommus = <&adreno_smm 2412 iommus = <&adreno_smmu 0 0x401>;
2929 2413
2930 operating-points-v2 = 2414 operating-points-v2 = <&gpu_opp_table>;
2931 2415
2932 qcom,gmu = <&gmu>; 2416 qcom,gmu = <&gmu>;
2933 2417
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 2418 status = "disabled";
2939 2419
2940 zap-shader { 2420 zap-shader {
2941 memory-region 2421 memory-region = <&gpu_mem>;
2942 }; 2422 };
2943 2423
>> 2424 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 2425 gpu_opp_table: opp-table {
2945 compatible = 2426 compatible = "operating-points-v2";
2946 2427
2947 opp-670000000 2428 opp-670000000 {
2948 opp-h 2429 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2430 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 2431 };
2952 2432
2953 opp-587000000 2433 opp-587000000 {
2954 opp-h 2434 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2435 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 2436 };
2958 2437
2959 opp-525000000 2438 opp-525000000 {
2960 opp-h 2439 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2440 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 2441 };
2964 2442
2965 opp-490000000 2443 opp-490000000 {
2966 opp-h 2444 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2445 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 2446 };
2970 2447
2971 opp-441600000 2448 opp-441600000 {
2972 opp-h 2449 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2450 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 2451 };
2976 2452
2977 opp-400000000 2453 opp-400000000 {
2978 opp-h 2454 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2455 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 2456 };
2982 2457
2983 opp-305000000 2458 opp-305000000 {
2984 opp-h 2459 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2460 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 2461 };
2988 }; 2462 };
2989 }; 2463 };
2990 2464
2991 gmu: gmu@3d6a000 { 2465 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 2466 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2467
2994 reg = <0 0x03d6a000 0 2468 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2469 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2470 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2471 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2472 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2473
3000 interrupts = <GIC_SPI 2474 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2475 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2476 interrupt-names = "hfi", "gmu";
3003 2477
3004 clocks = <&gpucc GPU_ 2478 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2479 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2480 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2481 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2482 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2483 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2484
3011 power-domains = <&gpu 2485 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2486 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2487 power-domain-names = "cx", "gx";
3014 2488
3015 iommus = <&adreno_smm 2489 iommus = <&adreno_smmu 5 0x400>;
3016 2490
3017 operating-points-v2 = 2491 operating-points-v2 = <&gmu_opp_table>;
3018 2492
3019 status = "disabled"; 2493 status = "disabled";
3020 2494
3021 gmu_opp_table: opp-ta 2495 gmu_opp_table: opp-table {
3022 compatible = 2496 compatible = "operating-points-v2";
3023 2497
3024 opp-200000000 2498 opp-200000000 {
3025 opp-h 2499 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2500 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2501 };
3028 }; 2502 };
3029 }; 2503 };
3030 2504
3031 gpucc: clock-controller@3d900 2505 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2506 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2507 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2508 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2509 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2510 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2511 clock-names = "bi_tcxo",
3038 "gcc_gp 2512 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2513 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2514 #clock-cells = <1>;
3041 #reset-cells = <1>; 2515 #reset-cells = <1>;
3042 #power-domain-cells = 2516 #power-domain-cells = <1>;
3043 }; 2517 };
3044 2518
3045 adreno_smmu: iommu@3da0000 { 2519 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2520 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2521 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2522 #iommu-cells = <2>;
3050 #global-interrupts = 2523 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2524 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2525 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2526 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2527 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2528 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2529 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2530 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2531 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2532 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2533 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2534 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2535 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2536 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2537 clock-names = "ahb", "bus", "iface";
3065 2538
3066 power-domains = <&gpu 2539 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2540 };
3069 2541
3070 slpi: remoteproc@5c00000 { 2542 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2543 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2544 reg = <0 0x05c00000 0 0x4000>;
3073 2545
3074 interrupts-extended = !! 2546 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2547 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2548 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2549 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2550 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2551 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2552 "handover", "stop-ack";
3081 2553
3082 clocks = <&rpmhcc RPM 2554 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2555 clock-names = "xo";
3084 2556
3085 power-domains = <&rpm !! 2557 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2558 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2559 power-domain-names = "lcx", "lmx";
3088 2560
3089 memory-region = <&slp 2561 memory-region = <&slpi_mem>;
3090 2562
3091 qcom,qmp = <&aoss_qmp 2563 qcom,qmp = <&aoss_qmp>;
3092 2564
3093 qcom,smem-states = <& 2565 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2566 qcom,smem-state-names = "stop";
3095 2567
3096 status = "disabled"; 2568 status = "disabled";
3097 2569
3098 glink-edge { 2570 glink-edge {
3099 interrupts-ex 2571 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2572 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2573 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2574 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2575 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2576
3105 label = "slpi 2577 label = "slpi";
3106 qcom,remote-p 2578 qcom,remote-pid = <3>;
3107 2579
3108 fastrpc { 2580 fastrpc {
3109 compa 2581 compatible = "qcom,fastrpc";
3110 qcom, 2582 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2583 label = "sdsp";
3112 qcom, <<
3113 #addr 2584 #address-cells = <1>;
3114 #size 2585 #size-cells = <0>;
3115 2586
3116 compu 2587 compute-cb@1 {
3117 2588 compatible = "qcom,fastrpc-compute-cb";
3118 2589 reg = <1>;
3119 2590 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2591 };
3121 2592
3122 compu 2593 compute-cb@2 {
3123 2594 compatible = "qcom,fastrpc-compute-cb";
3124 2595 reg = <2>;
3125 2596 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2597 };
3127 2598
3128 compu 2599 compute-cb@3 {
3129 2600 compatible = "qcom,fastrpc-compute-cb";
3130 2601 reg = <3>;
3131 2602 iommus = <&apps_smmu 0x0543 0x0>;
3132 2603 /* note: shared-cb = <4> in downstream */
3133 }; 2604 };
3134 }; 2605 };
3135 }; 2606 };
3136 }; 2607 };
3137 2608
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 2609 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 2610 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 2611 reg = <0 0x08300000 0 0x10000>;
3777 2612
3778 interrupts-extended = !! 2613 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 2614 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 2615 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 2616 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 2617 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 2618 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 2619 "handover", "stop-ack";
3785 2620
3786 clocks = <&rpmhcc RPM 2621 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 2622 clock-names = "xo";
3788 2623
3789 power-domains = <&rpm !! 2624 power-domains = <&rpmhpd SM8250_CX>;
3790 2625
3791 memory-region = <&cds 2626 memory-region = <&cdsp_mem>;
3792 2627
3793 qcom,qmp = <&aoss_qmp 2628 qcom,qmp = <&aoss_qmp>;
3794 2629
3795 qcom,smem-states = <& 2630 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 2631 qcom,smem-state-names = "stop";
3797 2632
3798 status = "disabled"; 2633 status = "disabled";
3799 2634
3800 glink-edge { 2635 glink-edge {
3801 interrupts-ex 2636 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2637 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2638 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2639 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2640 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2641
3807 label = "cdsp 2642 label = "cdsp";
3808 qcom,remote-p 2643 qcom,remote-pid = <5>;
3809 2644
3810 fastrpc { 2645 fastrpc {
3811 compa 2646 compatible = "qcom,fastrpc";
3812 qcom, 2647 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2648 label = "cdsp";
3814 qcom, <<
3815 #addr 2649 #address-cells = <1>;
3816 #size 2650 #size-cells = <0>;
3817 2651
3818 compu 2652 compute-cb@1 {
3819 2653 compatible = "qcom,fastrpc-compute-cb";
3820 2654 reg = <1>;
3821 2655 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2656 };
3823 2657
3824 compu 2658 compute-cb@2 {
3825 2659 compatible = "qcom,fastrpc-compute-cb";
3826 2660 reg = <2>;
3827 2661 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2662 };
3829 2663
3830 compu 2664 compute-cb@3 {
3831 2665 compatible = "qcom,fastrpc-compute-cb";
3832 2666 reg = <3>;
3833 2667 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2668 };
3835 2669
3836 compu 2670 compute-cb@4 {
3837 2671 compatible = "qcom,fastrpc-compute-cb";
3838 2672 reg = <4>;
3839 2673 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2674 };
3841 2675
3842 compu 2676 compute-cb@5 {
3843 2677 compatible = "qcom,fastrpc-compute-cb";
3844 2678 reg = <5>;
3845 2679 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2680 };
3847 2681
3848 compu 2682 compute-cb@6 {
3849 2683 compatible = "qcom,fastrpc-compute-cb";
3850 2684 reg = <6>;
3851 2685 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2686 };
3853 2687
3854 compu 2688 compute-cb@7 {
3855 2689 compatible = "qcom,fastrpc-compute-cb";
3856 2690 reg = <7>;
3857 2691 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2692 };
3859 2693
3860 compu 2694 compute-cb@8 {
3861 2695 compatible = "qcom,fastrpc-compute-cb";
3862 2696 reg = <8>;
3863 2697 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2698 };
3865 2699
3866 /* no 2700 /* note: secure cb9 in downstream */
3867 }; 2701 };
3868 }; 2702 };
3869 }; 2703 };
3870 2704
>> 2705 sound: sound {
>> 2706 };
>> 2707
3871 usb_1_hsphy: phy@88e3000 { 2708 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2709 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2710 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2711 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2712 status = "disabled";
3876 #phy-cells = <0>; 2713 #phy-cells = <0>;
3877 2714
3878 clocks = <&rpmhcc RPM 2715 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2716 clock-names = "ref";
3880 2717
3881 resets = <&gcc GCC_QU 2718 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2719 };
3883 2720
3884 usb_2_hsphy: phy@88e4000 { 2721 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2722 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2723 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2724 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2725 status = "disabled";
3889 #phy-cells = <0>; 2726 #phy-cells = <0>;
3890 2727
3891 clocks = <&rpmhcc RPM 2728 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2729 clock-names = "ref";
3893 2730
3894 resets = <&gcc GCC_QU 2731 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2732 };
3896 2733
3897 usb_1_qmpphy: phy@88e8000 { !! 2734 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2735 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2736 reg = <0 0x088e9000 0 0x200>,
>> 2737 <0 0x088e8000 0 0x40>,
>> 2738 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2739 status = "disabled";
>> 2740 #address-cells = <2>;
>> 2741 #size-cells = <2>;
>> 2742 ranges;
3901 2743
3902 clocks = <&gcc GCC_US 2744 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2745 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2746 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2747 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2748
3911 resets = <&gcc GCC_US 2749 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2750 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2751 reset-names = "phy", "common";
3914 2752
3915 #clock-cells = <1>; !! 2753 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2754 reg = <0 0x088e9200 0 0x200>,
3917 !! 2755 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2756 <0 0x088e9c00 0 0x400>,
3919 !! 2757 <0 0x088e9600 0 0x200>,
3920 ports { !! 2758 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2759 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2760 #clock-cells = <0>;
3923 !! 2761 #phy-cells = <0>;
3924 port@0 { !! 2762 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2763 clock-names = "pipe0";
3926 usb_1 !! 2764 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2765 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2766
3940 usb_1 !! 2767 dp_phy: dp-phy@88ea200 {
3941 }; !! 2768 reg = <0 0x088ea200 0 0x200>,
>> 2769 <0 0x088ea400 0 0x200>,
>> 2770 <0 0x088eac00 0 0x400>,
>> 2771 <0 0x088ea600 0 0x200>,
>> 2772 <0 0x088ea800 0 0x200>,
>> 2773 <0 0x088eaa00 0 0x100>;
>> 2774 #phy-cells = <0>;
>> 2775 #clock-cells = <1>;
>> 2776 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 2777 clock-names = "pipe0";
>> 2778 clock-output-names = "usb3_phy_pipe_clk_src";
3942 }; 2779 };
3943 }; 2780 };
3944 2781
3945 usb_2_qmpphy: phy@88eb000 { 2782 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2783 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2784 reg = <0 0x088eb000 0 0x200>;
>> 2785 status = "disabled";
>> 2786 #address-cells = <2>;
>> 2787 #size-cells = <2>;
>> 2788 ranges;
3948 2789
3949 clocks = <&gcc GCC_US 2790 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2791 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2792 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2793 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2794 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2795
3961 resets = <&gcc GCC_US !! 2796 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2797 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2798 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2799
3966 status = "disabled"; !! 2800 usb_2_ssphy: phy@88eb200 {
>> 2801 reg = <0 0x088eb200 0 0x200>,
>> 2802 <0 0x088eb400 0 0x200>,
>> 2803 <0 0x088eb800 0 0x800>;
>> 2804 #clock-cells = <0>;
>> 2805 #phy-cells = <0>;
>> 2806 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2807 clock-names = "pipe0";
>> 2808 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2809 };
3967 }; 2810 };
3968 2811
3969 sdhc_2: mmc@8804000 { !! 2812 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2813 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2814 reg = <0 0x08804000 0 0x1000>;
3972 2815
3973 interrupts = <GIC_SPI 2816 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2817 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2818 interrupt-names = "hc_irq", "pwr_irq";
3976 2819
3977 clocks = <&gcc GCC_SD 2820 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2821 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2822 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2823 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2824 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2825 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2826 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2827 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2828 operating-points-v2 = <&sdhc2_opp_table>;
3986 2829
3987 status = "disabled"; 2830 status = "disabled";
3988 2831
3989 sdhc2_opp_table: opp- !! 2832 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2833 compatible = "operating-points-v2";
3991 2834
3992 opp-19200000 2835 opp-19200000 {
3993 opp-h 2836 opp-hz = /bits/ 64 <19200000>;
3994 requi 2837 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2838 };
3996 2839
3997 opp-50000000 2840 opp-50000000 {
3998 opp-h 2841 opp-hz = /bits/ 64 <50000000>;
3999 requi 2842 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2843 };
4001 2844
4002 opp-100000000 2845 opp-100000000 {
4003 opp-h 2846 opp-hz = /bits/ 64 <100000000>;
4004 requi 2847 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2848 };
4006 2849
4007 opp-202000000 2850 opp-202000000 {
4008 opp-h 2851 opp-hz = /bits/ 64 <202000000>;
4009 requi 2852 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2853 };
4011 }; 2854 };
4012 }; 2855 };
4013 2856
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2857 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2858 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2859 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2860 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2861 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2862 };
4142 2863
4143 gem_noc: interconnect@9100000 2864 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2865 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2866 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2867 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2868 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2869 };
4149 2870
4150 npu_noc: interconnect@9990000 2871 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2872 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2873 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2874 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2875 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2876 };
4156 2877
4157 usb_1: usb@a6f8800 { 2878 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2879 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2880 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2881 status = "disabled";
4161 #address-cells = <2>; 2882 #address-cells = <2>;
4162 #size-cells = <2>; 2883 #size-cells = <2>;
4163 ranges; 2884 ranges;
4164 dma-ranges; 2885 dma-ranges;
4165 2886
4166 clocks = <&gcc GCC_CF 2887 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 2888 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 2889 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 2890 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 2891 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 2892 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 2893 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 2894 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 2895
4179 assigned-clocks = <&g 2896 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 2897 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 2898 assigned-clock-rates = <19200000>, <200000000>;
4182 2899
4183 interrupts-extended = !! 2900 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 2901 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 2902 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 2903 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 2904 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 2905 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 2906
4194 power-domains = <&gcc 2907 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 2908
4197 resets = <&gcc GCC_US 2909 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 2910
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 2911 usb_1_dwc3: usb@a600000 {
4204 compatible = 2912 compatible = "snps,dwc3";
4205 reg = <0 0x0a 2913 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 2914 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 2915 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 2916 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 2917 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 2918 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 2919 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 2920 };
4233 }; 2921 };
4234 2922
4235 system-cache-controller@92000 2923 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 2924 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 2925 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 2926 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 2927 };
4243 2928
4244 usb_2: usb@a8f8800 { 2929 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 2930 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 2931 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 2932 status = "disabled";
4248 #address-cells = <2>; 2933 #address-cells = <2>;
4249 #size-cells = <2>; 2934 #size-cells = <2>;
4250 ranges; 2935 ranges;
4251 dma-ranges; 2936 dma-ranges;
4252 2937
4253 clocks = <&gcc GCC_CF 2938 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 2939 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 2940 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 2941 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 2942 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 2943 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 2944 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 2945 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 2946
4266 assigned-clocks = <&g 2947 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 2948 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 2949 assigned-clock-rates = <19200000>, <200000000>;
4269 2950
4270 interrupts-extended = !! 2951 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 2952 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 2953 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 2954 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 2955 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 2956 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 2957
4281 power-domains = <&gcc 2958 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 2959
4284 resets = <&gcc GCC_US 2960 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 2961
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 2962 usb_2_dwc3: usb@a800000 {
4291 compatible = 2963 compatible = "snps,dwc3";
4292 reg = <0 0x0a 2964 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 2965 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 2966 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 2967 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 2968 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 2969 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 2970 phy-names = "usb2-phy", "usb3-phy";
4299 }; 2971 };
4300 }; 2972 };
4301 2973
4302 venus: video-codec@aa00000 { 2974 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 2975 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 2976 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 2977 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 2978 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 2979 <&videocc MVS0_GDSC>,
4308 <&rpm !! 2980 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 2981 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 2982 operating-points-v2 = <&venus_opp_table>;
4311 2983
4312 clocks = <&gcc GCC_VI 2984 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 2985 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 2986 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 2987 clock-names = "iface", "core", "vcodec0_core";
4316 2988
4317 interconnects = <&gem !! 2989 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 2990 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 2991 interconnect-names = "cpu-cfg", "video-mem";
4320 2992
4321 iommus = <&apps_smmu 2993 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 2994 memory-region = <&video_mem>;
4323 2995
4324 resets = <&gcc GCC_VI 2996 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 2997 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 2998 reset-names = "bus", "core";
4327 2999
4328 status = "disabled"; 3000 status = "disabled";
4329 3001
4330 video-decoder { 3002 video-decoder {
4331 compatible = 3003 compatible = "venus-decoder";
4332 }; 3004 };
4333 3005
4334 video-encoder { 3006 video-encoder {
4335 compatible = 3007 compatible = "venus-encoder";
4336 }; 3008 };
4337 3009
4338 venus_opp_table: opp- !! 3010 venus_opp_table: venus-opp-table {
4339 compatible = 3011 compatible = "operating-points-v2";
4340 3012
4341 opp-720000000 3013 opp-720000000 {
4342 opp-h 3014 opp-hz = /bits/ 64 <720000000>;
4343 requi 3015 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3016 };
4345 3017
4346 opp-101400000 3018 opp-1014000000 {
4347 opp-h 3019 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3020 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3021 };
4350 3022
4351 opp-109800000 3023 opp-1098000000 {
4352 opp-h 3024 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3025 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3026 };
4355 3027
4356 opp-133200000 3028 opp-1332000000 {
4357 opp-h 3029 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3030 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3031 };
4360 }; 3032 };
4361 }; 3033 };
4362 3034
4363 videocc: clock-controller@abf 3035 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 3036 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 3037 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 3038 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 3039 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 3040 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 3041 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 3042 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 3043 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 3044 #clock-cells = <1>;
4373 #reset-cells = <1>; 3045 #reset-cells = <1>;
4374 #power-domain-cells = 3046 #power-domain-cells = <1>;
4375 }; 3047 };
4376 3048
4377 cci0: cci@ac4f000 { !! 3049 mdss: mdss@ae00000 {
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm 3050 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 3051 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 3052 reg-names = "mdss";
4661 3053
4662 interconnects = <&mms !! 3054 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 3055 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 3056 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 3057
4666 power-domains = <&dis 3058 power-domains = <&dispcc MDSS_GDSC>;
4667 3059
4668 clocks = <&dispcc DIS 3060 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 3061 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 3062 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 3063 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 3064 clock-names = "iface", "bus", "nrt_bus", "core";
4673 3065
>> 3066 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 3067 assigned-clock-rates = <460000000>;
>> 3068
4674 interrupts = <GIC_SPI 3069 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 3070 interrupt-controller;
4676 #interrupt-cells = <1 3071 #interrupt-cells = <1>;
4677 3072
4678 iommus = <&apps_smmu 3073 iommus = <&apps_smmu 0x820 0x402>;
4679 3074
4680 status = "disabled"; 3075 status = "disabled";
4681 3076
4682 #address-cells = <2>; 3077 #address-cells = <2>;
4683 #size-cells = <2>; 3078 #size-cells = <2>;
4684 ranges; 3079 ranges;
4685 3080
4686 mdss_mdp: display-con !! 3081 mdss_mdp: mdp@ae01000 {
4687 compatible = 3082 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 3083 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 3084 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 3085 reg-names = "mdp", "vbif";
4691 3086
4692 clocks = <&di 3087 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 3088 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 3089 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 3090 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 3091 clock-names = "iface", "bus", "core", "vsync";
4697 3092
4698 assigned-cloc !! 3093 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 3094 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 3095 assigned-clock-rates = <460000000>,
>> 3096 <19200000>;
4700 3097
4701 operating-poi 3098 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 3099 power-domains = <&rpmhpd SM8250_MMCX>;
4703 3100
4704 interrupt-par 3101 interrupt-parent = <&mdss>;
4705 interrupts = !! 3102 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4706 3103
4707 ports { 3104 ports {
4708 #addr 3105 #address-cells = <1>;
4709 #size 3106 #size-cells = <0>;
4710 3107
4711 port@ 3108 port@0 {
4712 3109 reg = <0>;
4713 3110 dpu_intf1_out: endpoint {
4714 !! 3111 remote-endpoint = <&dsi0_in>;
4715 3112 };
4716 }; 3113 };
4717 3114
4718 port@ 3115 port@1 {
4719 3116 reg = <1>;
4720 3117 dpu_intf2_out: endpoint {
4721 !! 3118 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 3119 };
4731 }; 3120 };
4732 }; 3121 };
4733 3122
4734 mdp_opp_table !! 3123 mdp_opp_table: mdp-opp-table {
4735 compa 3124 compatible = "operating-points-v2";
4736 3125
4737 opp-2 3126 opp-200000000 {
4738 3127 opp-hz = /bits/ 64 <200000000>;
4739 3128 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 3129 };
4741 3130
4742 opp-3 3131 opp-300000000 {
4743 3132 opp-hz = /bits/ 64 <300000000>;
4744 3133 required-opps = <&rpmhpd_opp_svs>;
4745 }; 3134 };
4746 3135
4747 opp-3 3136 opp-345000000 {
4748 3137 opp-hz = /bits/ 64 <345000000>;
4749 3138 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 3139 };
4751 3140
4752 opp-4 3141 opp-460000000 {
4753 3142 opp-hz = /bits/ 64 <460000000>;
4754 3143 required-opps = <&rpmhpd_opp_nom>;
4755 }; 3144 };
4756 }; 3145 };
4757 }; 3146 };
4758 3147
4759 mdss_dp: displayport- !! 3148 dsi0: dsi@ae94000 {
4760 compatible = !! 3149 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 3150 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 3151 reg-names = "dsi_ctrl";
4843 3152
4844 interrupt-par 3153 interrupt-parent = <&mdss>;
4845 interrupts = !! 3154 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 3155
4847 clocks = <&di 3156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 3157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 3158 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 3159 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 3160 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 3161 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 3162 clock-names = "byte",
4854 3163 "byte_intf",
4855 3164 "pixel",
4856 3165 "core",
4857 3166 "iface",
4858 3167 "bus";
4859 3168
4860 assigned-cloc 3169 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 3170 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 3171
4863 operating-poi 3172 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 3173 power-domains = <&rpmhpd SM8250_MMCX>;
4865 3174
4866 phys = <&mdss !! 3175 phys = <&dsi0_phy>;
>> 3176 phy-names = "dsi";
4867 3177
4868 status = "dis 3178 status = "disabled";
4869 3179
4870 #address-cell 3180 #address-cells = <1>;
4871 #size-cells = 3181 #size-cells = <0>;
4872 3182
4873 ports { 3183 ports {
4874 #addr 3184 #address-cells = <1>;
4875 #size 3185 #size-cells = <0>;
4876 3186
4877 port@ 3187 port@0 {
4878 3188 reg = <0>;
4879 !! 3189 dsi0_in: endpoint {
4880 3190 remote-endpoint = <&dpu_intf1_out>;
4881 3191 };
4882 }; 3192 };
4883 3193
4884 port@ 3194 port@1 {
4885 3195 reg = <1>;
4886 !! 3196 dsi0_out: endpoint {
4887 3197 };
4888 }; 3198 };
4889 }; 3199 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 3200 };
4910 3201
4911 mdss_dsi0_phy: phy@ae !! 3202 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 3203 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 3204 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 3205 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 3206 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 3207 reg-names = "dsi_phy",
4917 " 3208 "dsi_phy_lane",
4918 " 3209 "dsi_pll";
4919 3210
4920 #clock-cells 3211 #clock-cells = <1>;
4921 #phy-cells = 3212 #phy-cells = <0>;
4922 3213
4923 clocks = <&di 3214 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 3215 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 3216 clock-names = "iface", "ref";
4926 3217
4927 status = "dis 3218 status = "disabled";
4928 }; 3219 };
4929 3220
4930 mdss_dsi1: dsi@ae9600 !! 3221 dsi1: dsi@ae96000 {
4931 compatible = !! 3222 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 3223 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 3224 reg-names = "dsi_ctrl";
4935 3225
4936 interrupt-par 3226 interrupt-parent = <&mdss>;
4937 interrupts = !! 3227 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 3228
4939 clocks = <&di 3229 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 3230 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 3231 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 3232 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 3233 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 3234 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 3235 clock-names = "byte",
4946 3236 "byte_intf",
4947 3237 "pixel",
4948 3238 "core",
4949 3239 "iface",
4950 3240 "bus";
4951 3241
4952 assigned-cloc 3242 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 3243 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 3244
4955 operating-poi 3245 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 3246 power-domains = <&rpmhpd SM8250_MMCX>;
4957 3247
4958 phys = <&mdss !! 3248 phys = <&dsi1_phy>;
>> 3249 phy-names = "dsi";
4959 3250
4960 status = "dis 3251 status = "disabled";
4961 3252
4962 #address-cell 3253 #address-cells = <1>;
4963 #size-cells = 3254 #size-cells = <0>;
4964 3255
4965 ports { 3256 ports {
4966 #addr 3257 #address-cells = <1>;
4967 #size 3258 #size-cells = <0>;
4968 3259
4969 port@ 3260 port@0 {
4970 3261 reg = <0>;
4971 !! 3262 dsi1_in: endpoint {
4972 3263 remote-endpoint = <&dpu_intf2_out>;
4973 3264 };
4974 }; 3265 };
4975 3266
4976 port@ 3267 port@1 {
4977 3268 reg = <1>;
4978 !! 3269 dsi1_out: endpoint {
4979 3270 };
4980 }; 3271 };
4981 }; 3272 };
4982 }; 3273 };
4983 3274
4984 mdss_dsi1_phy: phy@ae !! 3275 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 3276 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 3277 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 3278 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 3279 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 3280 reg-names = "dsi_phy",
4990 " 3281 "dsi_phy_lane",
4991 " 3282 "dsi_pll";
4992 3283
4993 #clock-cells 3284 #clock-cells = <1>;
4994 #phy-cells = 3285 #phy-cells = <0>;
4995 3286
4996 clocks = <&di 3287 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 3288 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 3289 clock-names = "iface", "ref";
4999 3290
5000 status = "dis 3291 status = "disabled";
>> 3292
>> 3293 dsi_opp_table: dsi-opp-table {
>> 3294 compatible = "operating-points-v2";
>> 3295
>> 3296 opp-187500000 {
>> 3297 opp-hz = /bits/ 64 <187500000>;
>> 3298 required-opps = <&rpmhpd_opp_low_svs>;
>> 3299 };
>> 3300
>> 3301 opp-300000000 {
>> 3302 opp-hz = /bits/ 64 <300000000>;
>> 3303 required-opps = <&rpmhpd_opp_svs>;
>> 3304 };
>> 3305
>> 3306 opp-358000000 {
>> 3307 opp-hz = /bits/ 64 <358000000>;
>> 3308 required-opps = <&rpmhpd_opp_svs_l1>;
>> 3309 };
>> 3310 };
5001 }; 3311 };
5002 }; 3312 };
5003 3313
5004 dispcc: clock-controller@af00 3314 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 3315 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 3316 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 3317 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 3318 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 3319 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 3320 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 3321 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 3322 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 3323 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 3324 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 3325 <&dp_phy 1>;
5016 clock-names = "bi_tcx 3326 clock-names = "bi_tcxo",
5017 "dsi0_p 3327 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 3328 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 3329 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 3330 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 3331 "dp_phy_pll_link_clk",
5022 "dp_phy 3332 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 3333 #clock-cells = <1>;
5024 #reset-cells = <1>; 3334 #reset-cells = <1>;
5025 #power-domain-cells = 3335 #power-domain-cells = <1>;
5026 }; 3336 };
5027 3337
5028 pdc: interrupt-controller@b22 3338 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 3339 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 3340 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 3341 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 3342 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 3343 #interrupt-cells = <2>;
5034 interrupt-parent = <& 3344 interrupt-parent = <&intc>;
5035 interrupt-controller; 3345 interrupt-controller;
5036 }; 3346 };
5037 3347
5038 tsens0: thermal-sensor@c26300 3348 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 3349 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 3350 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 3351 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 3352 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 3353 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 3354 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 3355 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 3356 #thermal-sensor-cells = <1>;
5047 }; 3357 };
5048 3358
5049 tsens1: thermal-sensor@c26500 3359 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 3360 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 3361 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 3362 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 3363 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 3364 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 3365 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 3366 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 3367 #thermal-sensor-cells = <1>;
5058 }; 3368 };
5059 3369
5060 aoss_qmp: power-management@c3 !! 3370 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm !! 3371 compatible = "qcom,sm8250-aoss-qmp";
5062 reg = <0 0x0c300000 0 3372 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 3373 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 3374 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 3375 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 3376 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 3377 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 3378
5069 #clock-cells = <0>; 3379 #clock-cells = <0>;
5070 }; 3380 };
5071 3381
5072 sram@c3f0000 { 3382 sram@c3f0000 {
5073 compatible = "qcom,rp 3383 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 3384 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 3385 };
5076 3386
5077 spmi_bus: spmi@c440000 { 3387 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 3388 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 3389 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 3390 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 3391 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 3392 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 3393 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 3394 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 3395 interrupt-names = "periph_irq";
5086 interrupts-extended = 3396 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 3397 qcom,ee = <0>;
5088 qcom,channel = <0>; 3398 qcom,channel = <0>;
5089 #address-cells = <2>; 3399 #address-cells = <2>;
5090 #size-cells = <0>; 3400 #size-cells = <0>;
5091 interrupt-controller; 3401 interrupt-controller;
5092 #interrupt-cells = <4 3402 #interrupt-cells = <4>;
5093 }; 3403 };
5094 3404
5095 tlmm: pinctrl@f100000 { 3405 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 3406 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 3407 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 3408 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 3409 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 3410 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 3411 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 3412 gpio-controller;
5103 #gpio-cells = <2>; 3413 #gpio-cells = <2>;
5104 interrupt-controller; 3414 interrupt-controller;
5105 #interrupt-cells = <2 3415 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 3416 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 3417 wakeup-parent = <&pdc>;
5108 3418
5109 cam2_default: cam2-de !! 3419 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 3420 sclk {
5111 pins !! 3421 pins = "gpio138";
5112 funct !! 3422 function = "mi2s0_sck";
5113 drive !! 3423 drive-strength = <8>;
5114 bias- 3424 bias-disable;
5115 }; 3425 };
5116 3426
5117 mclk-pins { !! 3427 ws {
5118 pins !! 3428 pins = "gpio141";
5119 funct !! 3429 function = "mi2s0_ws";
5120 drive !! 3430 drive-strength = <8>;
>> 3431 output-high;
>> 3432 };
>> 3433
>> 3434 data0 {
>> 3435 pins = "gpio139";
>> 3436 function = "mi2s0_data0";
>> 3437 drive-strength = <8>;
5121 bias- 3438 bias-disable;
>> 3439 output-high;
>> 3440 };
>> 3441
>> 3442 data1 {
>> 3443 pins = "gpio140";
>> 3444 function = "mi2s0_data1";
>> 3445 drive-strength = <8>;
>> 3446 output-high;
5122 }; 3447 };
5123 }; 3448 };
5124 3449
5125 cam2_suspend: cam2-su !! 3450 qup_i2c0_default: qup-i2c0-default {
5126 rst-pins { !! 3451 mux {
5127 pins !! 3452 pins = "gpio28", "gpio29";
5128 funct !! 3453 function = "qup0";
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; 3454 };
5133 3455
5134 mclk-pins { !! 3456 config {
5135 pins !! 3457 pins = "gpio28", "gpio29";
5136 funct <<
5137 drive 3458 drive-strength = <2>;
5138 bias- 3459 bias-disable;
5139 }; 3460 };
5140 }; 3461 };
5141 3462
5142 cci0_default: cci0-de !! 3463 qup_i2c1_default: qup-i2c1-default {
5143 cci0_i2c0_def !! 3464 pinmux {
5144 /* SD !! 3465 pins = "gpio4", "gpio5";
5145 pins !! 3466 function = "qup1";
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; 3467 };
5151 3468
5152 cci0_i2c1_def !! 3469 config {
5153 /* SD !! 3470 pins = "gpio4", "gpio5";
5154 pins !! 3471 drive-strength = <2>;
5155 funct !! 3472 bias-disable;
5156 <<
5157 bias- <<
5158 drive <<
5159 }; 3473 };
5160 }; 3474 };
5161 3475
5162 cci0_sleep: cci0-slee !! 3476 qup_i2c2_default: qup-i2c2-default {
5163 cci0_i2c0_sle !! 3477 mux {
5164 /* SD !! 3478 pins = "gpio115", "gpio116";
5165 pins !! 3479 function = "qup2";
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; 3480 };
5171 3481
5172 cci0_i2c1_sle !! 3482 config {
5173 /* SD !! 3483 pins = "gpio115", "gpio116";
5174 pins !! 3484 drive-strength = <2>;
5175 funct !! 3485 bias-disable;
5176 <<
5177 drive <<
5178 bias- <<
5179 }; 3486 };
5180 }; 3487 };
5181 3488
5182 cci1_default: cci1-de !! 3489 qup_i2c3_default: qup-i2c3-default {
5183 cci1_i2c0_def !! 3490 mux {
5184 /* SD !! 3491 pins = "gpio119", "gpio120";
5185 pins !! 3492 function = "qup3";
5186 funct !! 3493 };
5187 3494
5188 bias- !! 3495 config {
5189 drive !! 3496 pins = "gpio119", "gpio120";
>> 3497 drive-strength = <2>;
>> 3498 bias-disable;
5190 }; 3499 };
>> 3500 };
5191 3501
5192 cci1_i2c1_def !! 3502 qup_i2c4_default: qup-i2c4-default {
5193 /* SD !! 3503 mux {
5194 pins !! 3504 pins = "gpio8", "gpio9";
5195 funct !! 3505 function = "qup4";
>> 3506 };
5196 3507
5197 bias- !! 3508 config {
5198 drive !! 3509 pins = "gpio8", "gpio9";
>> 3510 drive-strength = <2>;
>> 3511 bias-disable;
5199 }; 3512 };
5200 }; 3513 };
5201 3514
5202 cci1_sleep: cci1-slee !! 3515 qup_i2c5_default: qup-i2c5-default {
5203 cci1_i2c0_sle !! 3516 mux {
5204 /* SD !! 3517 pins = "gpio12", "gpio13";
5205 pins !! 3518 function = "qup5";
5206 funct !! 3519 };
5207 3520
5208 bias- !! 3521 config {
5209 drive !! 3522 pins = "gpio12", "gpio13";
>> 3523 drive-strength = <2>;
>> 3524 bias-disable;
5210 }; 3525 };
>> 3526 };
5211 3527
5212 cci1_i2c1_sle !! 3528 qup_i2c6_default: qup-i2c6-default {
5213 /* SD !! 3529 mux {
5214 pins !! 3530 pins = "gpio16", "gpio17";
5215 funct !! 3531 function = "qup6";
>> 3532 };
5216 3533
5217 bias- !! 3534 config {
5218 drive !! 3535 pins = "gpio16", "gpio17";
>> 3536 drive-strength = <2>;
>> 3537 bias-disable;
5219 }; 3538 };
5220 }; 3539 };
5221 3540
5222 pri_mi2s_active: pri- !! 3541 qup_i2c7_default: qup-i2c7-default {
5223 sclk-pins { !! 3542 mux {
5224 pins !! 3543 pins = "gpio20", "gpio21";
5225 funct !! 3544 function = "qup7";
5226 drive !! 3545 };
>> 3546
>> 3547 config {
>> 3548 pins = "gpio20", "gpio21";
>> 3549 drive-strength = <2>;
5227 bias- 3550 bias-disable;
5228 }; 3551 };
>> 3552 };
5229 3553
5230 ws-pins { !! 3554 qup_i2c8_default: qup-i2c8-default {
5231 pins !! 3555 mux {
5232 funct !! 3556 pins = "gpio24", "gpio25";
5233 drive !! 3557 function = "qup8";
5234 outpu <<
5235 }; 3558 };
5236 3559
5237 data0-pins { !! 3560 config {
5238 pins !! 3561 pins = "gpio24", "gpio25";
5239 funct !! 3562 drive-strength = <2>;
5240 drive <<
5241 bias- 3563 bias-disable;
5242 outpu <<
5243 }; 3564 };
>> 3565 };
5244 3566
5245 data1-pins { !! 3567 qup_i2c9_default: qup-i2c9-default {
5246 pins !! 3568 mux {
5247 funct !! 3569 pins = "gpio125", "gpio126";
5248 drive !! 3570 function = "qup9";
5249 outpu <<
5250 }; 3571 };
5251 }; <<
5252 3572
5253 qup_i2c0_default: qup !! 3573 config {
5254 pins = "gpio2 !! 3574 pins = "gpio125", "gpio126";
5255 function = "q !! 3575 drive-strength = <2>;
5256 drive-strengt !! 3576 bias-disable;
5257 bias-disable; !! 3577 };
5258 }; 3578 };
5259 3579
5260 qup_i2c1_default: qup !! 3580 qup_i2c10_default: qup-i2c10-default {
5261 pins = "gpio4 !! 3581 mux {
5262 function = "q !! 3582 pins = "gpio129", "gpio130";
5263 drive-strengt !! 3583 function = "qup10";
5264 bias-disable; !! 3584 };
5265 }; <<
5266 3585
5267 qup_i2c2_default: qup !! 3586 config {
5268 pins = "gpio1 !! 3587 pins = "gpio129", "gpio130";
5269 function = "q !! 3588 drive-strength = <2>;
5270 drive-strengt !! 3589 bias-disable;
5271 bias-disable; !! 3590 };
5272 }; 3591 };
5273 3592
5274 qup_i2c3_default: qup !! 3593 qup_i2c11_default: qup-i2c11-default {
5275 pins = "gpio1 !! 3594 mux {
5276 function = "q !! 3595 pins = "gpio60", "gpio61";
5277 drive-strengt !! 3596 function = "qup11";
5278 bias-disable; !! 3597 };
5279 }; <<
5280 3598
5281 qup_i2c4_default: qup !! 3599 config {
5282 pins = "gpio8 !! 3600 pins = "gpio60", "gpio61";
5283 function = "q !! 3601 drive-strength = <2>;
5284 drive-strengt !! 3602 bias-disable;
5285 bias-disable; !! 3603 };
5286 }; 3604 };
5287 3605
5288 qup_i2c5_default: qup !! 3606 qup_i2c12_default: qup-i2c12-default {
5289 pins = "gpio1 !! 3607 mux {
5290 function = "q !! 3608 pins = "gpio32", "gpio33";
5291 drive-strengt !! 3609 function = "qup12";
5292 bias-disable; !! 3610 };
5293 }; <<
5294 3611
5295 qup_i2c6_default: qup !! 3612 config {
5296 pins = "gpio1 !! 3613 pins = "gpio32", "gpio33";
5297 function = "q !! 3614 drive-strength = <2>;
5298 drive-strengt !! 3615 bias-disable;
5299 bias-disable; !! 3616 };
5300 }; 3617 };
5301 3618
5302 qup_i2c7_default: qup !! 3619 qup_i2c13_default: qup-i2c13-default {
5303 pins = "gpio2 !! 3620 mux {
5304 function = "q !! 3621 pins = "gpio36", "gpio37";
5305 drive-strengt !! 3622 function = "qup13";
5306 bias-disable; !! 3623 };
5307 }; <<
5308 3624
5309 qup_i2c8_default: qup !! 3625 config {
5310 pins = "gpio2 !! 3626 pins = "gpio36", "gpio37";
5311 function = "q !! 3627 drive-strength = <2>;
5312 drive-strengt !! 3628 bias-disable;
5313 bias-disable; !! 3629 };
5314 }; 3630 };
5315 3631
5316 qup_i2c9_default: qup !! 3632 qup_i2c14_default: qup-i2c14-default {
5317 pins = "gpio1 !! 3633 mux {
5318 function = "q !! 3634 pins = "gpio40", "gpio41";
5319 drive-strengt !! 3635 function = "qup14";
5320 bias-disable; !! 3636 };
5321 }; <<
5322 3637
5323 qup_i2c10_default: qu !! 3638 config {
5324 pins = "gpio1 !! 3639 pins = "gpio40", "gpio41";
5325 function = "q !! 3640 drive-strength = <2>;
5326 drive-strengt !! 3641 bias-disable;
5327 bias-disable; !! 3642 };
5328 }; 3643 };
5329 3644
5330 qup_i2c11_default: qu !! 3645 qup_i2c15_default: qup-i2c15-default {
5331 pins = "gpio6 !! 3646 mux {
5332 function = "q !! 3647 pins = "gpio44", "gpio45";
5333 drive-strengt !! 3648 function = "qup15";
5334 bias-disable; !! 3649 };
5335 }; <<
5336 3650
5337 qup_i2c12_default: qu !! 3651 config {
5338 pins = "gpio3 !! 3652 pins = "gpio44", "gpio45";
5339 function = "q !! 3653 drive-strength = <2>;
5340 drive-strengt !! 3654 bias-disable;
5341 bias-disable; !! 3655 };
5342 }; 3656 };
5343 3657
5344 qup_i2c13_default: qu !! 3658 qup_i2c16_default: qup-i2c16-default {
5345 pins = "gpio3 !! 3659 mux {
5346 function = "q !! 3660 pins = "gpio48", "gpio49";
5347 drive-strengt !! 3661 function = "qup16";
5348 bias-disable; !! 3662 };
5349 }; <<
5350 3663
5351 qup_i2c14_default: qu !! 3664 config {
5352 pins = "gpio4 !! 3665 pins = "gpio48", "gpio49";
5353 function = "q !! 3666 drive-strength = <2>;
5354 drive-strengt !! 3667 bias-disable;
5355 bias-disable; !! 3668 };
5356 }; 3669 };
5357 3670
5358 qup_i2c15_default: qu !! 3671 qup_i2c17_default: qup-i2c17-default {
5359 pins = "gpio4 !! 3672 mux {
5360 function = "q !! 3673 pins = "gpio52", "gpio53";
5361 drive-strengt !! 3674 function = "qup17";
5362 bias-disable; !! 3675 };
5363 }; <<
5364 3676
5365 qup_i2c16_default: qu !! 3677 config {
5366 pins = "gpio4 !! 3678 pins = "gpio52", "gpio53";
5367 function = "q !! 3679 drive-strength = <2>;
5368 drive-strengt !! 3680 bias-disable;
5369 bias-disable; !! 3681 };
5370 }; 3682 };
5371 3683
5372 qup_i2c17_default: qu !! 3684 qup_i2c18_default: qup-i2c18-default {
5373 pins = "gpio5 !! 3685 mux {
5374 function = "q !! 3686 pins = "gpio56", "gpio57";
5375 drive-strengt !! 3687 function = "qup18";
5376 bias-disable; !! 3688 };
5377 }; <<
5378 3689
5379 qup_i2c18_default: qu !! 3690 config {
5380 pins = "gpio5 !! 3691 pins = "gpio56", "gpio57";
5381 function = "q !! 3692 drive-strength = <2>;
5382 drive-strengt !! 3693 bias-disable;
5383 bias-disable; !! 3694 };
5384 }; 3695 };
5385 3696
5386 qup_i2c19_default: qu !! 3697 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 3698 mux {
5388 function = "q !! 3699 pins = "gpio0", "gpio1";
5389 drive-strengt !! 3700 function = "qup19";
5390 bias-disable; !! 3701 };
>> 3702
>> 3703 config {
>> 3704 pins = "gpio0", "gpio1";
>> 3705 drive-strength = <2>;
>> 3706 bias-disable;
>> 3707 };
5391 }; 3708 };
5392 3709
5393 qup_spi0_cs: qup-spi0 !! 3710 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 3711 pins = "gpio31";
5395 function = "q 3712 function = "qup0";
5396 }; 3713 };
5397 3714
5398 qup_spi0_cs_gpio: qup !! 3715 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 3716 pins = "gpio31";
5400 function = "g 3717 function = "gpio";
5401 }; 3718 };
5402 3719
5403 qup_spi0_data_clk: qu !! 3720 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 3721 pins = "gpio28", "gpio29",
5405 "gpio3 3722 "gpio30";
5406 function = "q 3723 function = "qup0";
5407 }; 3724 };
5408 3725
5409 qup_spi1_cs: qup-spi1 !! 3726 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 3727 pins = "gpio7";
5411 function = "q 3728 function = "qup1";
5412 }; 3729 };
5413 3730
5414 qup_spi1_cs_gpio: qup !! 3731 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 3732 pins = "gpio7";
5416 function = "g 3733 function = "gpio";
5417 }; 3734 };
5418 3735
5419 qup_spi1_data_clk: qu !! 3736 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 3737 pins = "gpio4", "gpio5",
5421 "gpio6 3738 "gpio6";
5422 function = "q 3739 function = "qup1";
5423 }; 3740 };
5424 3741
5425 qup_spi2_cs: qup-spi2 !! 3742 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 3743 pins = "gpio118";
5427 function = "q 3744 function = "qup2";
5428 }; 3745 };
5429 3746
5430 qup_spi2_cs_gpio: qup !! 3747 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 3748 pins = "gpio118";
5432 function = "g 3749 function = "gpio";
5433 }; 3750 };
5434 3751
5435 qup_spi2_data_clk: qu !! 3752 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 3753 pins = "gpio115", "gpio116",
5437 "gpio1 3754 "gpio117";
5438 function = "q 3755 function = "qup2";
5439 }; 3756 };
5440 3757
5441 qup_spi3_cs: qup-spi3 !! 3758 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 3759 pins = "gpio122";
5443 function = "q 3760 function = "qup3";
5444 }; 3761 };
5445 3762
5446 qup_spi3_cs_gpio: qup !! 3763 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 3764 pins = "gpio122";
5448 function = "g 3765 function = "gpio";
5449 }; 3766 };
5450 3767
5451 qup_spi3_data_clk: qu !! 3768 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 3769 pins = "gpio119", "gpio120",
5453 "gpio1 3770 "gpio121";
5454 function = "q 3771 function = "qup3";
5455 }; 3772 };
5456 3773
5457 qup_spi4_cs: qup-spi4 !! 3774 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 3775 pins = "gpio11";
5459 function = "q 3776 function = "qup4";
5460 }; 3777 };
5461 3778
5462 qup_spi4_cs_gpio: qup !! 3779 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 3780 pins = "gpio11";
5464 function = "g 3781 function = "gpio";
5465 }; 3782 };
5466 3783
5467 qup_spi4_data_clk: qu !! 3784 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 3785 pins = "gpio8", "gpio9",
5469 "gpio1 3786 "gpio10";
5470 function = "q 3787 function = "qup4";
5471 }; 3788 };
5472 3789
5473 qup_spi5_cs: qup-spi5 !! 3790 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 3791 pins = "gpio15";
5475 function = "q 3792 function = "qup5";
5476 }; 3793 };
5477 3794
5478 qup_spi5_cs_gpio: qup !! 3795 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 3796 pins = "gpio15";
5480 function = "g 3797 function = "gpio";
5481 }; 3798 };
5482 3799
5483 qup_spi5_data_clk: qu !! 3800 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 3801 pins = "gpio12", "gpio13",
5485 "gpio1 3802 "gpio14";
5486 function = "q 3803 function = "qup5";
5487 }; 3804 };
5488 3805
5489 qup_spi6_cs: qup-spi6 !! 3806 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 3807 pins = "gpio19";
5491 function = "q 3808 function = "qup6";
5492 }; 3809 };
5493 3810
5494 qup_spi6_cs_gpio: qup !! 3811 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 3812 pins = "gpio19";
5496 function = "g 3813 function = "gpio";
5497 }; 3814 };
5498 3815
5499 qup_spi6_data_clk: qu !! 3816 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 3817 pins = "gpio16", "gpio17",
5501 "gpio1 3818 "gpio18";
5502 function = "q 3819 function = "qup6";
5503 }; 3820 };
5504 3821
5505 qup_spi7_cs: qup-spi7 !! 3822 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 3823 pins = "gpio23";
5507 function = "q 3824 function = "qup7";
5508 }; 3825 };
5509 3826
5510 qup_spi7_cs_gpio: qup !! 3827 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 3828 pins = "gpio23";
5512 function = "g 3829 function = "gpio";
5513 }; 3830 };
5514 3831
5515 qup_spi7_data_clk: qu !! 3832 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 3833 pins = "gpio20", "gpio21",
5517 "gpio2 3834 "gpio22";
5518 function = "q 3835 function = "qup7";
5519 }; 3836 };
5520 3837
5521 qup_spi8_cs: qup-spi8 !! 3838 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 3839 pins = "gpio27";
5523 function = "q 3840 function = "qup8";
5524 }; 3841 };
5525 3842
5526 qup_spi8_cs_gpio: qup !! 3843 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 3844 pins = "gpio27";
5528 function = "g 3845 function = "gpio";
5529 }; 3846 };
5530 3847
5531 qup_spi8_data_clk: qu !! 3848 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 3849 pins = "gpio24", "gpio25",
5533 "gpio2 3850 "gpio26";
5534 function = "q 3851 function = "qup8";
5535 }; 3852 };
5536 3853
5537 qup_spi9_cs: qup-spi9 !! 3854 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 3855 pins = "gpio128";
5539 function = "q 3856 function = "qup9";
5540 }; 3857 };
5541 3858
5542 qup_spi9_cs_gpio: qup !! 3859 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 3860 pins = "gpio128";
5544 function = "g 3861 function = "gpio";
5545 }; 3862 };
5546 3863
5547 qup_spi9_data_clk: qu !! 3864 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 3865 pins = "gpio125", "gpio126",
5549 "gpio1 3866 "gpio127";
5550 function = "q 3867 function = "qup9";
5551 }; 3868 };
5552 3869
5553 qup_spi10_cs: qup-spi !! 3870 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 3871 pins = "gpio132";
5555 function = "q 3872 function = "qup10";
5556 }; 3873 };
5557 3874
5558 qup_spi10_cs_gpio: qu !! 3875 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 3876 pins = "gpio132";
5560 function = "g 3877 function = "gpio";
5561 }; 3878 };
5562 3879
5563 qup_spi10_data_clk: q !! 3880 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 3881 pins = "gpio129", "gpio130",
5565 "gpio1 3882 "gpio131";
5566 function = "q 3883 function = "qup10";
5567 }; 3884 };
5568 3885
5569 qup_spi11_cs: qup-spi !! 3886 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 3887 pins = "gpio63";
5571 function = "q 3888 function = "qup11";
5572 }; 3889 };
5573 3890
5574 qup_spi11_cs_gpio: qu !! 3891 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 3892 pins = "gpio63";
5576 function = "g 3893 function = "gpio";
5577 }; 3894 };
5578 3895
5579 qup_spi11_data_clk: q !! 3896 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 3897 pins = "gpio60", "gpio61",
5581 "gpio6 3898 "gpio62";
5582 function = "q 3899 function = "qup11";
5583 }; 3900 };
5584 3901
5585 qup_spi12_cs: qup-spi !! 3902 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 3903 pins = "gpio35";
5587 function = "q 3904 function = "qup12";
5588 }; 3905 };
5589 3906
5590 qup_spi12_cs_gpio: qu !! 3907 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 3908 pins = "gpio35";
5592 function = "g 3909 function = "gpio";
5593 }; 3910 };
5594 3911
5595 qup_spi12_data_clk: q !! 3912 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 3913 pins = "gpio32", "gpio33",
5597 "gpio3 3914 "gpio34";
5598 function = "q 3915 function = "qup12";
5599 }; 3916 };
5600 3917
5601 qup_spi13_cs: qup-spi !! 3918 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 3919 pins = "gpio39";
5603 function = "q 3920 function = "qup13";
5604 }; 3921 };
5605 3922
5606 qup_spi13_cs_gpio: qu !! 3923 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 3924 pins = "gpio39";
5608 function = "g 3925 function = "gpio";
5609 }; 3926 };
5610 3927
5611 qup_spi13_data_clk: q !! 3928 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 3929 pins = "gpio36", "gpio37",
5613 "gpio3 3930 "gpio38";
5614 function = "q 3931 function = "qup13";
5615 }; 3932 };
5616 3933
5617 qup_spi14_cs: qup-spi !! 3934 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 3935 pins = "gpio43";
5619 function = "q 3936 function = "qup14";
5620 }; 3937 };
5621 3938
5622 qup_spi14_cs_gpio: qu !! 3939 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 3940 pins = "gpio43";
5624 function = "g 3941 function = "gpio";
5625 }; 3942 };
5626 3943
5627 qup_spi14_data_clk: q !! 3944 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 3945 pins = "gpio40", "gpio41",
5629 "gpio4 3946 "gpio42";
5630 function = "q 3947 function = "qup14";
5631 }; 3948 };
5632 3949
5633 qup_spi15_cs: qup-spi !! 3950 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 3951 pins = "gpio47";
5635 function = "q 3952 function = "qup15";
5636 }; 3953 };
5637 3954
5638 qup_spi15_cs_gpio: qu !! 3955 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 3956 pins = "gpio47";
5640 function = "g 3957 function = "gpio";
5641 }; 3958 };
5642 3959
5643 qup_spi15_data_clk: q !! 3960 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 3961 pins = "gpio44", "gpio45",
5645 "gpio4 3962 "gpio46";
5646 function = "q 3963 function = "qup15";
5647 }; 3964 };
5648 3965
5649 qup_spi16_cs: qup-spi !! 3966 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 3967 pins = "gpio51";
5651 function = "q 3968 function = "qup16";
5652 }; 3969 };
5653 3970
5654 qup_spi16_cs_gpio: qu !! 3971 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 3972 pins = "gpio51";
5656 function = "g 3973 function = "gpio";
5657 }; 3974 };
5658 3975
5659 qup_spi16_data_clk: q !! 3976 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 3977 pins = "gpio48", "gpio49",
5661 "gpio5 3978 "gpio50";
5662 function = "q 3979 function = "qup16";
5663 }; 3980 };
5664 3981
5665 qup_spi17_cs: qup-spi !! 3982 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 3983 pins = "gpio55";
5667 function = "q 3984 function = "qup17";
5668 }; 3985 };
5669 3986
5670 qup_spi17_cs_gpio: qu !! 3987 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 3988 pins = "gpio55";
5672 function = "g 3989 function = "gpio";
5673 }; 3990 };
5674 3991
5675 qup_spi17_data_clk: q !! 3992 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 3993 pins = "gpio52", "gpio53",
5677 "gpio5 3994 "gpio54";
5678 function = "q 3995 function = "qup17";
5679 }; 3996 };
5680 3997
5681 qup_spi18_cs: qup-spi !! 3998 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 3999 pins = "gpio59";
5683 function = "q 4000 function = "qup18";
5684 }; 4001 };
5685 4002
5686 qup_spi18_cs_gpio: qu !! 4003 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 4004 pins = "gpio59";
5688 function = "g 4005 function = "gpio";
5689 }; 4006 };
5690 4007
5691 qup_spi18_data_clk: q !! 4008 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 4009 pins = "gpio56", "gpio57",
5693 "gpio5 4010 "gpio58";
5694 function = "q 4011 function = "qup18";
5695 }; 4012 };
5696 4013
5697 qup_spi19_cs: qup-spi !! 4014 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 4015 pins = "gpio3";
5699 function = "q 4016 function = "qup19";
5700 }; 4017 };
5701 4018
5702 qup_spi19_cs_gpio: qu !! 4019 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 4020 pins = "gpio3";
5704 function = "g 4021 function = "gpio";
5705 }; 4022 };
5706 4023
5707 qup_spi19_data_clk: q !! 4024 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 4025 pins = "gpio0", "gpio1",
5709 "gpio2 4026 "gpio2";
5710 function = "q 4027 function = "qup19";
5711 }; 4028 };
5712 4029
5713 qup_uart2_default: qu !! 4030 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 4031 mux {
5715 function = "q !! 4032 pins = "gpio117", "gpio118";
>> 4033 function = "qup2";
>> 4034 };
5716 }; 4035 };
5717 4036
5718 qup_uart6_default: qu !! 4037 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 4038 mux {
5720 function = "q !! 4039 pins = "gpio16", "gpio17",
>> 4040 "gpio18", "gpio19";
>> 4041 function = "qup6";
>> 4042 };
5721 }; 4043 };
5722 4044
5723 qup_uart12_default: q !! 4045 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 4046 mux {
5725 function = "q !! 4047 pins = "gpio34", "gpio35";
>> 4048 function = "qup12";
>> 4049 };
5726 }; 4050 };
5727 4051
5728 qup_uart17_default: q !! 4052 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 4053 mux {
5730 function = "q !! 4054 pins = "gpio52", "gpio53",
>> 4055 "gpio54", "gpio55";
>> 4056 function = "qup17";
>> 4057 };
5731 }; 4058 };
5732 4059
5733 qup_uart18_default: q !! 4060 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 4061 mux {
5735 function = "q !! 4062 pins = "gpio58", "gpio59";
>> 4063 function = "qup18";
>> 4064 };
5736 }; 4065 };
5737 4066
5738 tert_mi2s_active: ter !! 4067 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 4068 sck {
5740 pins 4069 pins = "gpio133";
5741 funct 4070 function = "mi2s2_sck";
5742 drive 4071 drive-strength = <8>;
5743 bias- 4072 bias-disable;
5744 }; 4073 };
5745 4074
5746 data0-pins { !! 4075 data0 {
5747 pins 4076 pins = "gpio134";
5748 funct 4077 function = "mi2s2_data0";
5749 drive 4078 drive-strength = <8>;
5750 bias- 4079 bias-disable;
5751 outpu 4080 output-high;
5752 }; 4081 };
5753 4082
5754 ws-pins { !! 4083 ws {
5755 pins 4084 pins = "gpio135";
5756 funct 4085 function = "mi2s2_ws";
5757 drive 4086 drive-strength = <8>;
5758 outpu 4087 output-high;
5759 }; 4088 };
5760 }; 4089 };
5761 4090
5762 sdc2_sleep_state: sdc !! 4091 sdc2_sleep_state: sdc2-sleep {
5763 clk-pins { !! 4092 clk {
5764 pins 4093 pins = "sdc2_clk";
5765 drive 4094 drive-strength = <2>;
5766 bias- 4095 bias-disable;
5767 }; 4096 };
5768 4097
5769 cmd-pins { !! 4098 cmd {
5770 pins 4099 pins = "sdc2_cmd";
5771 drive 4100 drive-strength = <2>;
5772 bias- 4101 bias-pull-up;
5773 }; 4102 };
5774 4103
5775 data-pins { !! 4104 data {
5776 pins 4105 pins = "sdc2_data";
5777 drive 4106 drive-strength = <2>;
5778 bias- 4107 bias-pull-up;
5779 }; 4108 };
5780 }; 4109 };
5781 4110
5782 pcie0_default_state: !! 4111 pcie0_default_state: pcie0-default {
5783 perst-pins { !! 4112 perst {
5784 pins 4113 pins = "gpio79";
5785 funct 4114 function = "gpio";
5786 drive 4115 drive-strength = <2>;
5787 bias- 4116 bias-pull-down;
5788 }; 4117 };
5789 4118
5790 clkreq-pins { !! 4119 clkreq {
5791 pins 4120 pins = "gpio80";
5792 funct 4121 function = "pci_e0";
5793 drive 4122 drive-strength = <2>;
5794 bias- 4123 bias-pull-up;
5795 }; 4124 };
5796 4125
5797 wake-pins { !! 4126 wake {
5798 pins 4127 pins = "gpio81";
5799 funct 4128 function = "gpio";
5800 drive 4129 drive-strength = <2>;
5801 bias- 4130 bias-pull-up;
5802 }; 4131 };
5803 }; 4132 };
5804 4133
5805 pcie1_default_state: !! 4134 pcie1_default_state: pcie1-default {
5806 perst-pins { !! 4135 perst {
5807 pins 4136 pins = "gpio82";
5808 funct 4137 function = "gpio";
5809 drive 4138 drive-strength = <2>;
5810 bias- 4139 bias-pull-down;
5811 }; 4140 };
5812 4141
5813 clkreq-pins { !! 4142 clkreq {
5814 pins 4143 pins = "gpio83";
5815 funct 4144 function = "pci_e1";
5816 drive 4145 drive-strength = <2>;
5817 bias- 4146 bias-pull-up;
5818 }; 4147 };
5819 4148
5820 wake-pins { !! 4149 wake {
5821 pins 4150 pins = "gpio84";
5822 funct 4151 function = "gpio";
5823 drive 4152 drive-strength = <2>;
5824 bias- 4153 bias-pull-up;
5825 }; 4154 };
5826 }; 4155 };
5827 4156
5828 pcie2_default_state: !! 4157 pcie2_default_state: pcie2-default {
5829 perst-pins { !! 4158 perst {
5830 pins 4159 pins = "gpio85";
5831 funct 4160 function = "gpio";
5832 drive 4161 drive-strength = <2>;
5833 bias- 4162 bias-pull-down;
5834 }; 4163 };
5835 4164
5836 clkreq-pins { !! 4165 clkreq {
5837 pins 4166 pins = "gpio86";
5838 funct 4167 function = "pci_e2";
5839 drive 4168 drive-strength = <2>;
5840 bias- 4169 bias-pull-up;
5841 }; 4170 };
5842 4171
5843 wake-pins { !! 4172 wake {
5844 pins 4173 pins = "gpio87";
5845 funct 4174 function = "gpio";
5846 drive 4175 drive-strength = <2>;
5847 bias- 4176 bias-pull-up;
5848 }; 4177 };
5849 }; 4178 };
5850 }; 4179 };
5851 4180
5852 apps_smmu: iommu@15000000 { 4181 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 4182 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 4183 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 4184 #iommu-cells = <2>;
5856 #global-interrupts = 4185 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 4186 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 4187 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 4188 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 4189 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 4190 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 4191 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 4192 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 4193 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 4194 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 4195 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 4196 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 4197 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 4198 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 4199 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 4200 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 4201 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 4202 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 4203 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 4204 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 4205 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 4206 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 4207 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 4208 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 4209 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 4210 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 4211 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 4212 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 4213 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 4214 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 4215 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 4216 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 4217 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 4218 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 4219 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 4220 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 4221 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 4222 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 4223 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 4224 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 4225 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 4226 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 4227 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 4228 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 4229 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 4230 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 4231 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 4232 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 4233 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 4234 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 4235 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 4236 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 4237 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 4238 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 4239 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 4240 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 4241 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 4242 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 4243 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 4244 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 4245 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 4246 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 4247 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 4248 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 4249 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 4250 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 4251 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 4252 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 4253 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 4254 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 4255 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 4256 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 4257 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 4258 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 4259 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 4260 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 4261 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 4262 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 4263 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 4264 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 4265 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 4266 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 4267 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 4268 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 4269 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 4270 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 4271 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 4272 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 4273 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 4274 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 4275 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 4276 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 4277 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 4278 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 4279 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 4280 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 4281 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 4282 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 4283 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 4284 };
5957 4285
5958 adsp: remoteproc@17300000 { 4286 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 4287 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 4288 reg = <0 0x17300000 0 0x100>;
5961 4289
5962 interrupts-extended = !! 4290 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 4291 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 4292 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 4293 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 4294 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 4295 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 4296 "handover", "stop-ack";
5969 4297
5970 clocks = <&rpmhcc RPM 4298 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 4299 clock-names = "xo";
5972 4300
5973 power-domains = <&rpm !! 4301 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 4302 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 4303 power-domain-names = "lcx", "lmx";
5976 4304
5977 memory-region = <&ads 4305 memory-region = <&adsp_mem>;
5978 4306
5979 qcom,qmp = <&aoss_qmp 4307 qcom,qmp = <&aoss_qmp>;
5980 4308
5981 qcom,smem-states = <& 4309 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 4310 qcom,smem-state-names = "stop";
5983 4311
5984 status = "disabled"; 4312 status = "disabled";
5985 4313
5986 glink-edge { 4314 glink-edge {
5987 interrupts-ex 4315 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 4316 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 4317 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 4318 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 4319 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 4320
5993 label = "lpas 4321 label = "lpass";
5994 qcom,remote-p 4322 qcom,remote-pid = <2>;
5995 4323
5996 apr { 4324 apr {
5997 compa 4325 compatible = "qcom,apr-v2";
5998 qcom, 4326 qcom,glink-channels = "apr_audio_svc";
5999 qcom, !! 4327 qcom,apr-domain = <APR_DOMAIN_ADSP>;
6000 #addr 4328 #address-cells = <1>;
6001 #size 4329 #size-cells = <0>;
6002 4330
6003 servi !! 4331 apr-service@3 {
6004 4332 reg = <APR_SVC_ADSP_CORE>;
6005 4333 compatible = "qcom,q6core";
6006 4334 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 4335 };
6008 4336
6009 q6afe !! 4337 q6afe: apr-service@4 {
6010 4338 compatible = "qcom,q6afe";
6011 4339 reg = <APR_SVC_AFE>;
6012 4340 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 4341 q6afedai: dais {
6014 4342 compatible = "qcom,q6afe-dais";
6015 4343 #address-cells = <1>;
6016 4344 #size-cells = <0>;
6017 4345 #sound-dai-cells = <1>;
6018 4346 };
6019 4347
6020 !! 4348 q6afecc: cc {
6021 4349 compatible = "qcom,q6afe-clocks";
6022 4350 #clock-cells = <2>;
6023 4351 };
6024 }; 4352 };
6025 4353
6026 q6asm !! 4354 q6asm: apr-service@7 {
6027 4355 compatible = "qcom,q6asm";
6028 4356 reg = <APR_SVC_ASM>;
6029 4357 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 4358 q6asmdai: dais {
6031 4359 compatible = "qcom,q6asm-dais";
6032 4360 #address-cells = <1>;
6033 4361 #size-cells = <0>;
6034 4362 #sound-dai-cells = <1>;
6035 4363 iommus = <&apps_smmu 0x1801 0x0>;
6036 4364 };
6037 }; 4365 };
6038 4366
6039 q6adm !! 4367 q6adm: apr-service@8 {
6040 4368 compatible = "qcom,q6adm";
6041 4369 reg = <APR_SVC_ADM>;
6042 4370 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 4371 q6routing: routing {
6044 4372 compatible = "qcom,q6adm-routing";
6045 4373 #sound-dai-cells = <0>;
6046 4374 };
6047 }; 4375 };
6048 }; 4376 };
6049 4377
6050 fastrpc { 4378 fastrpc {
6051 compa 4379 compatible = "qcom,fastrpc";
6052 qcom, 4380 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 4381 label = "adsp";
6054 qcom, <<
6055 #addr 4382 #address-cells = <1>;
6056 #size 4383 #size-cells = <0>;
6057 4384
6058 compu 4385 compute-cb@3 {
6059 4386 compatible = "qcom,fastrpc-compute-cb";
6060 4387 reg = <3>;
6061 4388 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 4389 };
6063 4390
6064 compu 4391 compute-cb@4 {
6065 4392 compatible = "qcom,fastrpc-compute-cb";
6066 4393 reg = <4>;
6067 4394 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 4395 };
6069 4396
6070 compu 4397 compute-cb@5 {
6071 4398 compatible = "qcom,fastrpc-compute-cb";
6072 4399 reg = <5>;
6073 4400 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 4401 };
6075 }; 4402 };
6076 }; 4403 };
6077 }; 4404 };
6078 4405
6079 intc: interrupt-controller@17 4406 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 4407 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 4408 #interrupt-cells = <3>;
6082 interrupt-controller; 4409 interrupt-controller;
6083 reg = <0x0 0x17a00000 4410 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 4411 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 4412 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 4413 };
6087 4414
6088 watchdog@17c10000 { 4415 watchdog@17c10000 {
6089 compatible = "qcom,ap 4416 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 4417 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 4418 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 4419 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 4420 };
6094 4421
6095 timer@17c20000 { 4422 timer@17c20000 {
6096 #address-cells = <1>; !! 4423 #address-cells = <2>;
6097 #size-cells = <1>; !! 4424 #size-cells = <2>;
6098 ranges = <0 0 0 0x200 !! 4425 ranges;
6099 compatible = "arm,arm 4426 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 4427 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 4428 clock-frequency = <19200000>;
6102 4429
6103 frame@17c21000 { 4430 frame@17c21000 {
6104 frame-number 4431 frame-number = <0>;
6105 interrupts = 4432 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 4433 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 !! 4434 reg = <0x0 0x17c21000 0x0 0x1000>,
6108 <0x17c2 !! 4435 <0x0 0x17c22000 0x0 0x1000>;
6109 }; 4436 };
6110 4437
6111 frame@17c23000 { 4438 frame@17c23000 {
6112 frame-number 4439 frame-number = <1>;
6113 interrupts = 4440 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 !! 4441 reg = <0x0 0x17c23000 0x0 0x1000>;
6115 status = "dis 4442 status = "disabled";
6116 }; 4443 };
6117 4444
6118 frame@17c25000 { 4445 frame@17c25000 {
6119 frame-number 4446 frame-number = <2>;
6120 interrupts = 4447 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 !! 4448 reg = <0x0 0x17c25000 0x0 0x1000>;
6122 status = "dis 4449 status = "disabled";
6123 }; 4450 };
6124 4451
6125 frame@17c27000 { 4452 frame@17c27000 {
6126 frame-number 4453 frame-number = <3>;
6127 interrupts = 4454 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 !! 4455 reg = <0x0 0x17c27000 0x0 0x1000>;
6129 status = "dis 4456 status = "disabled";
6130 }; 4457 };
6131 4458
6132 frame@17c29000 { 4459 frame@17c29000 {
6133 frame-number 4460 frame-number = <4>;
6134 interrupts = 4461 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 !! 4462 reg = <0x0 0x17c29000 0x0 0x1000>;
6136 status = "dis 4463 status = "disabled";
6137 }; 4464 };
6138 4465
6139 frame@17c2b000 { 4466 frame@17c2b000 {
6140 frame-number 4467 frame-number = <5>;
6141 interrupts = 4468 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 !! 4469 reg = <0x0 0x17c2b000 0x0 0x1000>;
6143 status = "dis 4470 status = "disabled";
6144 }; 4471 };
6145 4472
6146 frame@17c2d000 { 4473 frame@17c2d000 {
6147 frame-number 4474 frame-number = <6>;
6148 interrupts = 4475 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 !! 4476 reg = <0x0 0x17c2d000 0x0 0x1000>;
6150 status = "dis 4477 status = "disabled";
6151 }; 4478 };
6152 }; 4479 };
6153 4480
6154 apps_rsc: rsc@18200000 { 4481 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 4482 label = "apps_rsc";
6156 compatible = "qcom,rp 4483 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 4484 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 4485 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 4486 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 4487 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 4488 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 4489 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 4490 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 4491 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 4492 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 4493 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 4494 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 4495
6170 rpmhcc: clock-control 4496 rpmhcc: clock-controller {
6171 compatible = 4497 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 4498 #clock-cells = <1>;
6173 clock-names = 4499 clock-names = "xo";
6174 clocks = <&xo 4500 clocks = <&xo_board>;
6175 }; 4501 };
6176 4502
6177 rpmhpd: power-control 4503 rpmhpd: power-controller {
6178 compatible = 4504 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 4505 #power-domain-cells = <1>;
6180 operating-poi 4506 operating-points-v2 = <&rpmhpd_opp_table>;
6181 4507
6182 rpmhpd_opp_ta 4508 rpmhpd_opp_table: opp-table {
6183 compa 4509 compatible = "operating-points-v2";
6184 4510
6185 rpmhp 4511 rpmhpd_opp_ret: opp1 {
6186 4512 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 4513 };
6188 4514
6189 rpmhp 4515 rpmhpd_opp_min_svs: opp2 {
6190 4516 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 4517 };
6192 4518
6193 rpmhp 4519 rpmhpd_opp_low_svs: opp3 {
6194 4520 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 4521 };
6196 4522
6197 rpmhp 4523 rpmhpd_opp_svs: opp4 {
6198 4524 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 4525 };
6200 4526
6201 rpmhp 4527 rpmhpd_opp_svs_l1: opp5 {
6202 4528 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 4529 };
6204 4530
6205 rpmhp 4531 rpmhpd_opp_nom: opp6 {
6206 4532 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 4533 };
6208 4534
6209 rpmhp 4535 rpmhpd_opp_nom_l1: opp7 {
6210 4536 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 4537 };
6212 4538
6213 rpmhp 4539 rpmhpd_opp_nom_l2: opp8 {
6214 4540 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 4541 };
6216 4542
6217 rpmhp 4543 rpmhpd_opp_turbo: opp9 {
6218 4544 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 4545 };
6220 4546
6221 rpmhp 4547 rpmhpd_opp_turbo_l1: opp10 {
6222 4548 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 4549 };
6224 }; 4550 };
6225 }; 4551 };
6226 4552
6227 apps_bcm_voter: bcm-v !! 4553 apps_bcm_voter: bcm_voter {
6228 compatible = 4554 compatible = "qcom,bcm-voter";
6229 }; 4555 };
6230 }; 4556 };
6231 4557
6232 epss_l3: interconnect@1859000 4558 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 4559 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 4560 reg = <0 0x18590000 0 0x1000>;
6235 4561
6236 clocks = <&rpmhcc RPM 4562 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 4563 clock-names = "xo", "alternate";
6238 4564
6239 #interconnect-cells = 4565 #interconnect-cells = <1>;
6240 }; 4566 };
6241 4567
6242 cpufreq_hw: cpufreq@18591000 4568 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 4569 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 4570 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 4571 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 4572 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 4573 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 4574 "freq-domain2";
6249 4575
6250 clocks = <&rpmhcc RPM 4576 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 4577 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI !! 4578
6253 <GIC_SPI <<
6254 <GIC_SPI <<
6255 interrupt-names = "dc <<
6256 #freq-domain-cells = 4579 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 4580 };
6259 }; 4581 };
6260 4582
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 4583 timer {
6265 compatible = "arm,armv8-timer 4584 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 4585 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 4586 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 4587 <GIC_PPI 14
6269 (GIC_CPU_MASK 4588 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 4589 <GIC_PPI 11
6271 (GIC_CPU_MASK 4590 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 4591 <GIC_PPI 10
6273 (GIC_CPU_MASK 4592 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 4593 };
6275 4594
6276 thermal-zones { 4595 thermal-zones {
6277 cpu0-thermal { 4596 cpu0-thermal {
6278 polling-delay-passive 4597 polling-delay-passive = <250>;
>> 4598 polling-delay = <1000>;
6279 4599
6280 thermal-sensors = <&t 4600 thermal-sensors = <&tsens0 1>;
6281 4601
6282 trips { 4602 trips {
6283 cpu0_alert0: 4603 cpu0_alert0: trip-point0 {
6284 tempe 4604 temperature = <90000>;
6285 hyste 4605 hysteresis = <2000>;
6286 type 4606 type = "passive";
6287 }; 4607 };
6288 4608
6289 cpu0_alert1: 4609 cpu0_alert1: trip-point1 {
6290 tempe 4610 temperature = <95000>;
6291 hyste 4611 hysteresis = <2000>;
6292 type 4612 type = "passive";
6293 }; 4613 };
6294 4614
6295 cpu0_crit: cp !! 4615 cpu0_crit: cpu_crit {
6296 tempe 4616 temperature = <110000>;
6297 hyste 4617 hysteresis = <1000>;
6298 type 4618 type = "critical";
6299 }; 4619 };
6300 }; 4620 };
6301 4621
6302 cooling-maps { 4622 cooling-maps {
6303 map0 { 4623 map0 {
6304 trip 4624 trip = <&cpu0_alert0>;
6305 cooli 4625 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 4626 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 4627 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 4628 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 4629 };
6310 map1 { 4630 map1 {
6311 trip 4631 trip = <&cpu0_alert1>;
6312 cooli 4632 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 4633 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 4634 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 4635 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 4636 };
6317 }; 4637 };
6318 }; 4638 };
6319 4639
6320 cpu1-thermal { 4640 cpu1-thermal {
6321 polling-delay-passive 4641 polling-delay-passive = <250>;
>> 4642 polling-delay = <1000>;
6322 4643
6323 thermal-sensors = <&t 4644 thermal-sensors = <&tsens0 2>;
6324 4645
6325 trips { 4646 trips {
6326 cpu1_alert0: 4647 cpu1_alert0: trip-point0 {
6327 tempe 4648 temperature = <90000>;
6328 hyste 4649 hysteresis = <2000>;
6329 type 4650 type = "passive";
6330 }; 4651 };
6331 4652
6332 cpu1_alert1: 4653 cpu1_alert1: trip-point1 {
6333 tempe 4654 temperature = <95000>;
6334 hyste 4655 hysteresis = <2000>;
6335 type 4656 type = "passive";
6336 }; 4657 };
6337 4658
6338 cpu1_crit: cp !! 4659 cpu1_crit: cpu_crit {
6339 tempe 4660 temperature = <110000>;
6340 hyste 4661 hysteresis = <1000>;
6341 type 4662 type = "critical";
6342 }; 4663 };
6343 }; 4664 };
6344 4665
6345 cooling-maps { 4666 cooling-maps {
6346 map0 { 4667 map0 {
6347 trip 4668 trip = <&cpu1_alert0>;
6348 cooli 4669 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 4670 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 4671 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 4672 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 4673 };
6353 map1 { 4674 map1 {
6354 trip 4675 trip = <&cpu1_alert1>;
6355 cooli 4676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 4677 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 4678 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 4679 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 4680 };
6360 }; 4681 };
6361 }; 4682 };
6362 4683
6363 cpu2-thermal { 4684 cpu2-thermal {
6364 polling-delay-passive 4685 polling-delay-passive = <250>;
>> 4686 polling-delay = <1000>;
6365 4687
6366 thermal-sensors = <&t 4688 thermal-sensors = <&tsens0 3>;
6367 4689
6368 trips { 4690 trips {
6369 cpu2_alert0: 4691 cpu2_alert0: trip-point0 {
6370 tempe 4692 temperature = <90000>;
6371 hyste 4693 hysteresis = <2000>;
6372 type 4694 type = "passive";
6373 }; 4695 };
6374 4696
6375 cpu2_alert1: 4697 cpu2_alert1: trip-point1 {
6376 tempe 4698 temperature = <95000>;
6377 hyste 4699 hysteresis = <2000>;
6378 type 4700 type = "passive";
6379 }; 4701 };
6380 4702
6381 cpu2_crit: cp !! 4703 cpu2_crit: cpu_crit {
6382 tempe 4704 temperature = <110000>;
6383 hyste 4705 hysteresis = <1000>;
6384 type 4706 type = "critical";
6385 }; 4707 };
6386 }; 4708 };
6387 4709
6388 cooling-maps { 4710 cooling-maps {
6389 map0 { 4711 map0 {
6390 trip 4712 trip = <&cpu2_alert0>;
6391 cooli 4713 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 4714 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 4715 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 4716 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 4717 };
6396 map1 { 4718 map1 {
6397 trip 4719 trip = <&cpu2_alert1>;
6398 cooli 4720 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 4721 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 4722 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 4723 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 4724 };
6403 }; 4725 };
6404 }; 4726 };
6405 4727
6406 cpu3-thermal { 4728 cpu3-thermal {
6407 polling-delay-passive 4729 polling-delay-passive = <250>;
>> 4730 polling-delay = <1000>;
6408 4731
6409 thermal-sensors = <&t 4732 thermal-sensors = <&tsens0 4>;
6410 4733
6411 trips { 4734 trips {
6412 cpu3_alert0: 4735 cpu3_alert0: trip-point0 {
6413 tempe 4736 temperature = <90000>;
6414 hyste 4737 hysteresis = <2000>;
6415 type 4738 type = "passive";
6416 }; 4739 };
6417 4740
6418 cpu3_alert1: 4741 cpu3_alert1: trip-point1 {
6419 tempe 4742 temperature = <95000>;
6420 hyste 4743 hysteresis = <2000>;
6421 type 4744 type = "passive";
6422 }; 4745 };
6423 4746
6424 cpu3_crit: cp !! 4747 cpu3_crit: cpu_crit {
6425 tempe 4748 temperature = <110000>;
6426 hyste 4749 hysteresis = <1000>;
6427 type 4750 type = "critical";
6428 }; 4751 };
6429 }; 4752 };
6430 4753
6431 cooling-maps { 4754 cooling-maps {
6432 map0 { 4755 map0 {
6433 trip 4756 trip = <&cpu3_alert0>;
6434 cooli 4757 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 4758 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 4759 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 4760 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 4761 };
6439 map1 { 4762 map1 {
6440 trip 4763 trip = <&cpu3_alert1>;
6441 cooli 4764 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 4765 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 4766 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 4767 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 4768 };
6446 }; 4769 };
6447 }; 4770 };
6448 4771
6449 cpu4-top-thermal { 4772 cpu4-top-thermal {
6450 polling-delay-passive 4773 polling-delay-passive = <250>;
>> 4774 polling-delay = <1000>;
6451 4775
6452 thermal-sensors = <&t 4776 thermal-sensors = <&tsens0 7>;
6453 4777
6454 trips { 4778 trips {
6455 cpu4_top_aler 4779 cpu4_top_alert0: trip-point0 {
6456 tempe 4780 temperature = <90000>;
6457 hyste 4781 hysteresis = <2000>;
6458 type 4782 type = "passive";
6459 }; 4783 };
6460 4784
6461 cpu4_top_aler 4785 cpu4_top_alert1: trip-point1 {
6462 tempe 4786 temperature = <95000>;
6463 hyste 4787 hysteresis = <2000>;
6464 type 4788 type = "passive";
6465 }; 4789 };
6466 4790
6467 cpu4_top_crit !! 4791 cpu4_top_crit: cpu_crit {
6468 tempe 4792 temperature = <110000>;
6469 hyste 4793 hysteresis = <1000>;
6470 type 4794 type = "critical";
6471 }; 4795 };
6472 }; 4796 };
6473 4797
6474 cooling-maps { 4798 cooling-maps {
6475 map0 { 4799 map0 {
6476 trip 4800 trip = <&cpu4_top_alert0>;
6477 cooli 4801 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 4802 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 4803 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 4804 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 4805 };
6482 map1 { 4806 map1 {
6483 trip 4807 trip = <&cpu4_top_alert1>;
6484 cooli 4808 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 4809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 4810 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 4811 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 4812 };
6489 }; 4813 };
6490 }; 4814 };
6491 4815
6492 cpu5-top-thermal { 4816 cpu5-top-thermal {
6493 polling-delay-passive 4817 polling-delay-passive = <250>;
>> 4818 polling-delay = <1000>;
6494 4819
6495 thermal-sensors = <&t 4820 thermal-sensors = <&tsens0 8>;
6496 4821
6497 trips { 4822 trips {
6498 cpu5_top_aler 4823 cpu5_top_alert0: trip-point0 {
6499 tempe 4824 temperature = <90000>;
6500 hyste 4825 hysteresis = <2000>;
6501 type 4826 type = "passive";
6502 }; 4827 };
6503 4828
6504 cpu5_top_aler 4829 cpu5_top_alert1: trip-point1 {
6505 tempe 4830 temperature = <95000>;
6506 hyste 4831 hysteresis = <2000>;
6507 type 4832 type = "passive";
6508 }; 4833 };
6509 4834
6510 cpu5_top_crit !! 4835 cpu5_top_crit: cpu_crit {
6511 tempe 4836 temperature = <110000>;
6512 hyste 4837 hysteresis = <1000>;
6513 type 4838 type = "critical";
6514 }; 4839 };
6515 }; 4840 };
6516 4841
6517 cooling-maps { 4842 cooling-maps {
6518 map0 { 4843 map0 {
6519 trip 4844 trip = <&cpu5_top_alert0>;
6520 cooli 4845 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 4846 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 4847 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 4848 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4849 };
6525 map1 { 4850 map1 {
6526 trip 4851 trip = <&cpu5_top_alert1>;
6527 cooli 4852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4853 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4854 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4855 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4856 };
6532 }; 4857 };
6533 }; 4858 };
6534 4859
6535 cpu6-top-thermal { 4860 cpu6-top-thermal {
6536 polling-delay-passive 4861 polling-delay-passive = <250>;
>> 4862 polling-delay = <1000>;
6537 4863
6538 thermal-sensors = <&t 4864 thermal-sensors = <&tsens0 9>;
6539 4865
6540 trips { 4866 trips {
6541 cpu6_top_aler 4867 cpu6_top_alert0: trip-point0 {
6542 tempe 4868 temperature = <90000>;
6543 hyste 4869 hysteresis = <2000>;
6544 type 4870 type = "passive";
6545 }; 4871 };
6546 4872
6547 cpu6_top_aler 4873 cpu6_top_alert1: trip-point1 {
6548 tempe 4874 temperature = <95000>;
6549 hyste 4875 hysteresis = <2000>;
6550 type 4876 type = "passive";
6551 }; 4877 };
6552 4878
6553 cpu6_top_crit !! 4879 cpu6_top_crit: cpu_crit {
6554 tempe 4880 temperature = <110000>;
6555 hyste 4881 hysteresis = <1000>;
6556 type 4882 type = "critical";
6557 }; 4883 };
6558 }; 4884 };
6559 4885
6560 cooling-maps { 4886 cooling-maps {
6561 map0 { 4887 map0 {
6562 trip 4888 trip = <&cpu6_top_alert0>;
6563 cooli 4889 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 4890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 4891 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 4892 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 4893 };
6568 map1 { 4894 map1 {
6569 trip 4895 trip = <&cpu6_top_alert1>;
6570 cooli 4896 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 4897 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 4898 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 4899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 4900 };
6575 }; 4901 };
6576 }; 4902 };
6577 4903
6578 cpu7-top-thermal { 4904 cpu7-top-thermal {
6579 polling-delay-passive 4905 polling-delay-passive = <250>;
>> 4906 polling-delay = <1000>;
6580 4907
6581 thermal-sensors = <&t 4908 thermal-sensors = <&tsens0 10>;
6582 4909
6583 trips { 4910 trips {
6584 cpu7_top_aler 4911 cpu7_top_alert0: trip-point0 {
6585 tempe 4912 temperature = <90000>;
6586 hyste 4913 hysteresis = <2000>;
6587 type 4914 type = "passive";
6588 }; 4915 };
6589 4916
6590 cpu7_top_aler 4917 cpu7_top_alert1: trip-point1 {
6591 tempe 4918 temperature = <95000>;
6592 hyste 4919 hysteresis = <2000>;
6593 type 4920 type = "passive";
6594 }; 4921 };
6595 4922
6596 cpu7_top_crit !! 4923 cpu7_top_crit: cpu_crit {
6597 tempe 4924 temperature = <110000>;
6598 hyste 4925 hysteresis = <1000>;
6599 type 4926 type = "critical";
6600 }; 4927 };
6601 }; 4928 };
6602 4929
6603 cooling-maps { 4930 cooling-maps {
6604 map0 { 4931 map0 {
6605 trip 4932 trip = <&cpu7_top_alert0>;
6606 cooli 4933 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 4934 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 4935 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 4936 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 4937 };
6611 map1 { 4938 map1 {
6612 trip 4939 trip = <&cpu7_top_alert1>;
6613 cooli 4940 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 4941 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 4942 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 4943 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 4944 };
6618 }; 4945 };
6619 }; 4946 };
6620 4947
6621 cpu4-bottom-thermal { 4948 cpu4-bottom-thermal {
6622 polling-delay-passive 4949 polling-delay-passive = <250>;
>> 4950 polling-delay = <1000>;
6623 4951
6624 thermal-sensors = <&t 4952 thermal-sensors = <&tsens0 11>;
6625 4953
6626 trips { 4954 trips {
6627 cpu4_bottom_a 4955 cpu4_bottom_alert0: trip-point0 {
6628 tempe 4956 temperature = <90000>;
6629 hyste 4957 hysteresis = <2000>;
6630 type 4958 type = "passive";
6631 }; 4959 };
6632 4960
6633 cpu4_bottom_a 4961 cpu4_bottom_alert1: trip-point1 {
6634 tempe 4962 temperature = <95000>;
6635 hyste 4963 hysteresis = <2000>;
6636 type 4964 type = "passive";
6637 }; 4965 };
6638 4966
6639 cpu4_bottom_c !! 4967 cpu4_bottom_crit: cpu_crit {
6640 tempe 4968 temperature = <110000>;
6641 hyste 4969 hysteresis = <1000>;
6642 type 4970 type = "critical";
6643 }; 4971 };
6644 }; 4972 };
6645 4973
6646 cooling-maps { 4974 cooling-maps {
6647 map0 { 4975 map0 {
6648 trip 4976 trip = <&cpu4_bottom_alert0>;
6649 cooli 4977 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 4978 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 4979 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 4980 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 4981 };
6654 map1 { 4982 map1 {
6655 trip 4983 trip = <&cpu4_bottom_alert1>;
6656 cooli 4984 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 4985 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 4986 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 4987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 4988 };
6661 }; 4989 };
6662 }; 4990 };
6663 4991
6664 cpu5-bottom-thermal { 4992 cpu5-bottom-thermal {
6665 polling-delay-passive 4993 polling-delay-passive = <250>;
>> 4994 polling-delay = <1000>;
6666 4995
6667 thermal-sensors = <&t 4996 thermal-sensors = <&tsens0 12>;
6668 4997
6669 trips { 4998 trips {
6670 cpu5_bottom_a 4999 cpu5_bottom_alert0: trip-point0 {
6671 tempe 5000 temperature = <90000>;
6672 hyste 5001 hysteresis = <2000>;
6673 type 5002 type = "passive";
6674 }; 5003 };
6675 5004
6676 cpu5_bottom_a 5005 cpu5_bottom_alert1: trip-point1 {
6677 tempe 5006 temperature = <95000>;
6678 hyste 5007 hysteresis = <2000>;
6679 type 5008 type = "passive";
6680 }; 5009 };
6681 5010
6682 cpu5_bottom_c !! 5011 cpu5_bottom_crit: cpu_crit {
6683 tempe 5012 temperature = <110000>;
6684 hyste 5013 hysteresis = <1000>;
6685 type 5014 type = "critical";
6686 }; 5015 };
6687 }; 5016 };
6688 5017
6689 cooling-maps { 5018 cooling-maps {
6690 map0 { 5019 map0 {
6691 trip 5020 trip = <&cpu5_bottom_alert0>;
6692 cooli 5021 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 5022 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 5023 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 5024 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 5025 };
6697 map1 { 5026 map1 {
6698 trip 5027 trip = <&cpu5_bottom_alert1>;
6699 cooli 5028 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 5029 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 5030 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 5031 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 5032 };
6704 }; 5033 };
6705 }; 5034 };
6706 5035
6707 cpu6-bottom-thermal { 5036 cpu6-bottom-thermal {
6708 polling-delay-passive 5037 polling-delay-passive = <250>;
>> 5038 polling-delay = <1000>;
6709 5039
6710 thermal-sensors = <&t 5040 thermal-sensors = <&tsens0 13>;
6711 5041
6712 trips { 5042 trips {
6713 cpu6_bottom_a 5043 cpu6_bottom_alert0: trip-point0 {
6714 tempe 5044 temperature = <90000>;
6715 hyste 5045 hysteresis = <2000>;
6716 type 5046 type = "passive";
6717 }; 5047 };
6718 5048
6719 cpu6_bottom_a 5049 cpu6_bottom_alert1: trip-point1 {
6720 tempe 5050 temperature = <95000>;
6721 hyste 5051 hysteresis = <2000>;
6722 type 5052 type = "passive";
6723 }; 5053 };
6724 5054
6725 cpu6_bottom_c !! 5055 cpu6_bottom_crit: cpu_crit {
6726 tempe 5056 temperature = <110000>;
6727 hyste 5057 hysteresis = <1000>;
6728 type 5058 type = "critical";
6729 }; 5059 };
6730 }; 5060 };
6731 5061
6732 cooling-maps { 5062 cooling-maps {
6733 map0 { 5063 map0 {
6734 trip 5064 trip = <&cpu6_bottom_alert0>;
6735 cooli 5065 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 5066 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 5067 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 5068 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 5069 };
6740 map1 { 5070 map1 {
6741 trip 5071 trip = <&cpu6_bottom_alert1>;
6742 cooli 5072 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 5073 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 5074 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 5075 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 5076 };
6747 }; 5077 };
6748 }; 5078 };
6749 5079
6750 cpu7-bottom-thermal { 5080 cpu7-bottom-thermal {
6751 polling-delay-passive 5081 polling-delay-passive = <250>;
>> 5082 polling-delay = <1000>;
6752 5083
6753 thermal-sensors = <&t 5084 thermal-sensors = <&tsens0 14>;
6754 5085
6755 trips { 5086 trips {
6756 cpu7_bottom_a 5087 cpu7_bottom_alert0: trip-point0 {
6757 tempe 5088 temperature = <90000>;
6758 hyste 5089 hysteresis = <2000>;
6759 type 5090 type = "passive";
6760 }; 5091 };
6761 5092
6762 cpu7_bottom_a 5093 cpu7_bottom_alert1: trip-point1 {
6763 tempe 5094 temperature = <95000>;
6764 hyste 5095 hysteresis = <2000>;
6765 type 5096 type = "passive";
6766 }; 5097 };
6767 5098
6768 cpu7_bottom_c !! 5099 cpu7_bottom_crit: cpu_crit {
6769 tempe 5100 temperature = <110000>;
6770 hyste 5101 hysteresis = <1000>;
6771 type 5102 type = "critical";
6772 }; 5103 };
6773 }; 5104 };
6774 5105
6775 cooling-maps { 5106 cooling-maps {
6776 map0 { 5107 map0 {
6777 trip 5108 trip = <&cpu7_bottom_alert0>;
6778 cooli 5109 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 5110 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 5111 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 5112 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 5113 };
6783 map1 { 5114 map1 {
6784 trip 5115 trip = <&cpu7_bottom_alert1>;
6785 cooli 5116 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 5117 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 5118 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 5119 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 5120 };
6790 }; 5121 };
6791 }; 5122 };
6792 5123
6793 aoss0-thermal { 5124 aoss0-thermal {
6794 polling-delay-passive 5125 polling-delay-passive = <250>;
>> 5126 polling-delay = <1000>;
6795 5127
6796 thermal-sensors = <&t 5128 thermal-sensors = <&tsens0 0>;
6797 5129
6798 trips { 5130 trips {
6799 aoss0_alert0: 5131 aoss0_alert0: trip-point0 {
6800 tempe 5132 temperature = <90000>;
6801 hyste 5133 hysteresis = <2000>;
6802 type 5134 type = "hot";
6803 }; 5135 };
6804 }; 5136 };
6805 }; 5137 };
6806 5138
6807 cluster0-thermal { 5139 cluster0-thermal {
6808 polling-delay-passive 5140 polling-delay-passive = <250>;
>> 5141 polling-delay = <1000>;
6809 5142
6810 thermal-sensors = <&t 5143 thermal-sensors = <&tsens0 5>;
6811 5144
6812 trips { 5145 trips {
6813 cluster0_aler 5146 cluster0_alert0: trip-point0 {
6814 tempe 5147 temperature = <90000>;
6815 hyste 5148 hysteresis = <2000>;
6816 type 5149 type = "hot";
6817 }; 5150 };
6818 cluster0_crit !! 5151 cluster0_crit: cluster0_crit {
6819 tempe 5152 temperature = <110000>;
6820 hyste 5153 hysteresis = <2000>;
6821 type 5154 type = "critical";
6822 }; 5155 };
6823 }; 5156 };
6824 }; 5157 };
6825 5158
6826 cluster1-thermal { 5159 cluster1-thermal {
6827 polling-delay-passive 5160 polling-delay-passive = <250>;
>> 5161 polling-delay = <1000>;
6828 5162
6829 thermal-sensors = <&t 5163 thermal-sensors = <&tsens0 6>;
6830 5164
6831 trips { 5165 trips {
6832 cluster1_aler 5166 cluster1_alert0: trip-point0 {
6833 tempe 5167 temperature = <90000>;
6834 hyste 5168 hysteresis = <2000>;
6835 type 5169 type = "hot";
6836 }; 5170 };
6837 cluster1_crit !! 5171 cluster1_crit: cluster1_crit {
6838 tempe 5172 temperature = <110000>;
6839 hyste 5173 hysteresis = <2000>;
6840 type 5174 type = "critical";
6841 }; 5175 };
6842 }; 5176 };
6843 }; 5177 };
6844 5178
6845 gpu-top-thermal { !! 5179 gpu-thermal-top {
6846 polling-delay-passive 5180 polling-delay-passive = <250>;
>> 5181 polling-delay = <1000>;
6847 5182
6848 thermal-sensors = <&t 5183 thermal-sensors = <&tsens0 15>;
6849 5184
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 5185 trips {
6858 gpu_top_alert !! 5186 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 5187 temperature = <90000>;
6866 hyste !! 5188 hysteresis = <2000>;
6867 type 5189 type = "hot";
6868 }; 5190 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 5191 };
6876 }; 5192 };
6877 5193
6878 aoss1-thermal { 5194 aoss1-thermal {
6879 polling-delay-passive 5195 polling-delay-passive = <250>;
>> 5196 polling-delay = <1000>;
6880 5197
6881 thermal-sensors = <&t 5198 thermal-sensors = <&tsens1 0>;
6882 5199
6883 trips { 5200 trips {
6884 aoss1_alert0: 5201 aoss1_alert0: trip-point0 {
6885 tempe 5202 temperature = <90000>;
6886 hyste 5203 hysteresis = <2000>;
6887 type 5204 type = "hot";
6888 }; 5205 };
6889 }; 5206 };
6890 }; 5207 };
6891 5208
6892 wlan-thermal { 5209 wlan-thermal {
6893 polling-delay-passive 5210 polling-delay-passive = <250>;
>> 5211 polling-delay = <1000>;
6894 5212
6895 thermal-sensors = <&t 5213 thermal-sensors = <&tsens1 1>;
6896 5214
6897 trips { 5215 trips {
6898 wlan_alert0: 5216 wlan_alert0: trip-point0 {
6899 tempe 5217 temperature = <90000>;
6900 hyste 5218 hysteresis = <2000>;
6901 type 5219 type = "hot";
6902 }; 5220 };
6903 }; 5221 };
6904 }; 5222 };
6905 5223
6906 video-thermal { 5224 video-thermal {
6907 polling-delay-passive 5225 polling-delay-passive = <250>;
>> 5226 polling-delay = <1000>;
6908 5227
6909 thermal-sensors = <&t 5228 thermal-sensors = <&tsens1 2>;
6910 5229
6911 trips { 5230 trips {
6912 video_alert0: 5231 video_alert0: trip-point0 {
6913 tempe 5232 temperature = <90000>;
6914 hyste 5233 hysteresis = <2000>;
6915 type 5234 type = "hot";
6916 }; 5235 };
6917 }; 5236 };
6918 }; 5237 };
6919 5238
6920 mem-thermal { 5239 mem-thermal {
6921 polling-delay-passive 5240 polling-delay-passive = <250>;
>> 5241 polling-delay = <1000>;
6922 5242
6923 thermal-sensors = <&t 5243 thermal-sensors = <&tsens1 3>;
6924 5244
6925 trips { 5245 trips {
6926 mem_alert0: t 5246 mem_alert0: trip-point0 {
6927 tempe 5247 temperature = <90000>;
6928 hyste 5248 hysteresis = <2000>;
6929 type 5249 type = "hot";
6930 }; 5250 };
6931 }; 5251 };
6932 }; 5252 };
6933 5253
6934 q6-hvx-thermal { 5254 q6-hvx-thermal {
6935 polling-delay-passive 5255 polling-delay-passive = <250>;
>> 5256 polling-delay = <1000>;
6936 5257
6937 thermal-sensors = <&t 5258 thermal-sensors = <&tsens1 4>;
6938 5259
6939 trips { 5260 trips {
6940 q6_hvx_alert0 5261 q6_hvx_alert0: trip-point0 {
6941 tempe 5262 temperature = <90000>;
6942 hyste 5263 hysteresis = <2000>;
6943 type 5264 type = "hot";
6944 }; 5265 };
6945 }; 5266 };
6946 }; 5267 };
6947 5268
6948 camera-thermal { 5269 camera-thermal {
6949 polling-delay-passive 5270 polling-delay-passive = <250>;
>> 5271 polling-delay = <1000>;
6950 5272
6951 thermal-sensors = <&t 5273 thermal-sensors = <&tsens1 5>;
6952 5274
6953 trips { 5275 trips {
6954 camera_alert0 5276 camera_alert0: trip-point0 {
6955 tempe 5277 temperature = <90000>;
6956 hyste 5278 hysteresis = <2000>;
6957 type 5279 type = "hot";
6958 }; 5280 };
6959 }; 5281 };
6960 }; 5282 };
6961 5283
6962 compute-thermal { 5284 compute-thermal {
6963 polling-delay-passive 5285 polling-delay-passive = <250>;
>> 5286 polling-delay = <1000>;
6964 5287
6965 thermal-sensors = <&t 5288 thermal-sensors = <&tsens1 6>;
6966 5289
6967 trips { 5290 trips {
6968 compute_alert 5291 compute_alert0: trip-point0 {
6969 tempe 5292 temperature = <90000>;
6970 hyste 5293 hysteresis = <2000>;
6971 type 5294 type = "hot";
6972 }; 5295 };
6973 }; 5296 };
6974 }; 5297 };
6975 5298
6976 npu-thermal { 5299 npu-thermal {
6977 polling-delay-passive 5300 polling-delay-passive = <250>;
>> 5301 polling-delay = <1000>;
6978 5302
6979 thermal-sensors = <&t 5303 thermal-sensors = <&tsens1 7>;
6980 5304
6981 trips { 5305 trips {
6982 npu_alert0: t 5306 npu_alert0: trip-point0 {
6983 tempe 5307 temperature = <90000>;
6984 hyste 5308 hysteresis = <2000>;
6985 type 5309 type = "hot";
6986 }; 5310 };
6987 }; 5311 };
6988 }; 5312 };
6989 5313
6990 gpu-bottom-thermal { !! 5314 gpu-thermal-bottom {
6991 polling-delay-passive 5315 polling-delay-passive = <250>;
>> 5316 polling-delay = <1000>;
6992 5317
6993 thermal-sensors = <&t 5318 thermal-sensors = <&tsens1 8>;
6994 5319
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 5320 trips {
7003 gpu_bottom_al !! 5321 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 5322 temperature = <90000>;
7011 hyste !! 5323 hysteresis = <2000>;
7012 type 5324 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 5325 };
7020 }; 5326 };
7021 }; 5327 };
7022 }; 5328 };
7023 }; 5329 };
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