1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 16 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 17 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 19 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 20 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. <<
24 #include <dt-bindings/clock/qcom,videocc-sm825 21 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 22
26 / { 23 / {
27 interrupt-parent = <&intc>; 24 interrupt-parent = <&intc>;
28 25
29 #address-cells = <2>; 26 #address-cells = <2>;
30 #size-cells = <2>; 27 #size-cells = <2>;
31 28
32 aliases { 29 aliases {
33 i2c0 = &i2c0; 30 i2c0 = &i2c0;
34 i2c1 = &i2c1; 31 i2c1 = &i2c1;
35 i2c2 = &i2c2; 32 i2c2 = &i2c2;
36 i2c3 = &i2c3; 33 i2c3 = &i2c3;
37 i2c4 = &i2c4; 34 i2c4 = &i2c4;
38 i2c5 = &i2c5; 35 i2c5 = &i2c5;
39 i2c6 = &i2c6; 36 i2c6 = &i2c6;
40 i2c7 = &i2c7; 37 i2c7 = &i2c7;
41 i2c8 = &i2c8; 38 i2c8 = &i2c8;
42 i2c9 = &i2c9; 39 i2c9 = &i2c9;
43 i2c10 = &i2c10; 40 i2c10 = &i2c10;
44 i2c11 = &i2c11; 41 i2c11 = &i2c11;
45 i2c12 = &i2c12; 42 i2c12 = &i2c12;
46 i2c13 = &i2c13; 43 i2c13 = &i2c13;
47 i2c14 = &i2c14; 44 i2c14 = &i2c14;
48 i2c15 = &i2c15; 45 i2c15 = &i2c15;
49 i2c16 = &i2c16; 46 i2c16 = &i2c16;
50 i2c17 = &i2c17; 47 i2c17 = &i2c17;
51 i2c18 = &i2c18; 48 i2c18 = &i2c18;
52 i2c19 = &i2c19; 49 i2c19 = &i2c19;
53 spi0 = &spi0; 50 spi0 = &spi0;
54 spi1 = &spi1; 51 spi1 = &spi1;
55 spi2 = &spi2; 52 spi2 = &spi2;
56 spi3 = &spi3; 53 spi3 = &spi3;
57 spi4 = &spi4; 54 spi4 = &spi4;
58 spi5 = &spi5; 55 spi5 = &spi5;
59 spi6 = &spi6; 56 spi6 = &spi6;
60 spi7 = &spi7; 57 spi7 = &spi7;
61 spi8 = &spi8; 58 spi8 = &spi8;
62 spi9 = &spi9; 59 spi9 = &spi9;
63 spi10 = &spi10; 60 spi10 = &spi10;
64 spi11 = &spi11; 61 spi11 = &spi11;
65 spi12 = &spi12; 62 spi12 = &spi12;
66 spi13 = &spi13; 63 spi13 = &spi13;
67 spi14 = &spi14; 64 spi14 = &spi14;
68 spi15 = &spi15; 65 spi15 = &spi15;
69 spi16 = &spi16; 66 spi16 = &spi16;
70 spi17 = &spi17; 67 spi17 = &spi17;
71 spi18 = &spi18; 68 spi18 = &spi18;
72 spi19 = &spi19; 69 spi19 = &spi19;
73 }; 70 };
74 71
75 chosen { }; 72 chosen { };
76 73
77 clocks { 74 clocks {
78 xo_board: xo-board { 75 xo_board: xo-board {
79 compatible = "fixed-cl 76 compatible = "fixed-clock";
80 #clock-cells = <0>; 77 #clock-cells = <0>;
81 clock-frequency = <384 78 clock-frequency = <38400000>;
82 clock-output-names = " 79 clock-output-names = "xo_board";
83 }; 80 };
84 81
85 sleep_clk: sleep-clk { 82 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 83 compatible = "fixed-clock";
87 clock-frequency = <327 84 clock-frequency = <32768>;
88 #clock-cells = <0>; 85 #clock-cells = <0>;
89 }; 86 };
90 }; 87 };
91 88
92 cpus { 89 cpus {
93 #address-cells = <2>; 90 #address-cells = <2>;
94 #size-cells = <0>; 91 #size-cells = <0>;
95 92
96 CPU0: cpu@0 { 93 CPU0: cpu@0 {
97 device_type = "cpu"; 94 device_type = "cpu";
98 compatible = "qcom,kry 95 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 96 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 97 enable-method = "psci";
102 capacity-dmips-mhz = < 98 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 99 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 100 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 101 power-domains = <&CPU_PD0>;
106 power-domain-names = " 102 power-domain-names = "psci";
107 qcom,freq-domain = <&c 103 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 104 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ !! 105 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
110 <&epss 106 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 107 #cooling-cells = <2>;
112 L2_0: l2-cache { 108 L2_0: l2-cache {
113 compatible = " 109 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 110 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 111 L3_0: l3-cache {
119 compat 112 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 113 };
124 }; 114 };
125 }; 115 };
126 116
127 CPU1: cpu@100 { 117 CPU1: cpu@100 {
128 device_type = "cpu"; 118 device_type = "cpu";
129 compatible = "qcom,kry 119 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 120 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 121 enable-method = "psci";
133 capacity-dmips-mhz = < 122 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 123 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 124 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 125 power-domains = <&CPU_PD1>;
137 power-domain-names = " 126 power-domain-names = "psci";
138 qcom,freq-domain = <&c 127 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 128 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ !! 129 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
141 <&epss 130 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 131 #cooling-cells = <2>;
143 L2_100: l2-cache { 132 L2_100: l2-cache {
144 compatible = " 133 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 134 next-level-cache = <&L3_0>;
149 }; 135 };
150 }; 136 };
151 137
152 CPU2: cpu@200 { 138 CPU2: cpu@200 {
153 device_type = "cpu"; 139 device_type = "cpu";
154 compatible = "qcom,kry 140 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 141 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 142 enable-method = "psci";
158 capacity-dmips-mhz = < 143 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 144 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 145 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 146 power-domains = <&CPU_PD2>;
162 power-domain-names = " 147 power-domain-names = "psci";
163 qcom,freq-domain = <&c 148 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 149 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ !! 150 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
166 <&epss 151 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 152 #cooling-cells = <2>;
168 L2_200: l2-cache { 153 L2_200: l2-cache {
169 compatible = " 154 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 155 next-level-cache = <&L3_0>;
174 }; 156 };
175 }; 157 };
176 158
177 CPU3: cpu@300 { 159 CPU3: cpu@300 {
178 device_type = "cpu"; 160 device_type = "cpu";
179 compatible = "qcom,kry 161 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 162 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 163 enable-method = "psci";
183 capacity-dmips-mhz = < 164 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 165 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 166 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 167 power-domains = <&CPU_PD3>;
187 power-domain-names = " 168 power-domain-names = "psci";
188 qcom,freq-domain = <&c 169 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 170 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ !! 171 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
191 <&epss 172 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 173 #cooling-cells = <2>;
193 L2_300: l2-cache { 174 L2_300: l2-cache {
194 compatible = " 175 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 176 next-level-cache = <&L3_0>;
199 }; 177 };
200 }; 178 };
201 179
202 CPU4: cpu@400 { 180 CPU4: cpu@400 {
203 device_type = "cpu"; 181 device_type = "cpu";
204 compatible = "qcom,kry 182 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 183 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 184 enable-method = "psci";
208 capacity-dmips-mhz = < 185 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 186 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 187 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 188 power-domains = <&CPU_PD4>;
212 power-domain-names = " 189 power-domain-names = "psci";
213 qcom,freq-domain = <&c 190 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 191 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ !! 192 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
216 <&epss 193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 194 #cooling-cells = <2>;
218 L2_400: l2-cache { 195 L2_400: l2-cache {
219 compatible = " 196 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 197 next-level-cache = <&L3_0>;
224 }; 198 };
225 }; 199 };
226 200
227 CPU5: cpu@500 { 201 CPU5: cpu@500 {
228 device_type = "cpu"; 202 device_type = "cpu";
229 compatible = "qcom,kry 203 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 204 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 205 enable-method = "psci";
233 capacity-dmips-mhz = < 206 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 207 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 208 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 209 power-domains = <&CPU_PD5>;
237 power-domain-names = " 210 power-domain-names = "psci";
238 qcom,freq-domain = <&c 211 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 212 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ !! 213 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
241 <&epss 214 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 215 #cooling-cells = <2>;
243 L2_500: l2-cache { 216 L2_500: l2-cache {
244 compatible = " 217 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 218 next-level-cache = <&L3_0>;
249 }; 219 };
>> 220
250 }; 221 };
251 222
252 CPU6: cpu@600 { 223 CPU6: cpu@600 {
253 device_type = "cpu"; 224 device_type = "cpu";
254 compatible = "qcom,kry 225 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 226 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 227 enable-method = "psci";
258 capacity-dmips-mhz = < 228 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 229 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 230 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 231 power-domains = <&CPU_PD6>;
262 power-domain-names = " 232 power-domain-names = "psci";
263 qcom,freq-domain = <&c 233 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 234 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ !! 235 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
266 <&epss 236 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 237 #cooling-cells = <2>;
268 L2_600: l2-cache { 238 L2_600: l2-cache {
269 compatible = " 239 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 240 next-level-cache = <&L3_0>;
274 }; 241 };
275 }; 242 };
276 243
277 CPU7: cpu@700 { 244 CPU7: cpu@700 {
278 device_type = "cpu"; 245 device_type = "cpu";
279 compatible = "qcom,kry 246 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 247 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 248 enable-method = "psci";
283 capacity-dmips-mhz = < 249 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 250 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 251 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 252 power-domains = <&CPU_PD7>;
287 power-domain-names = " 253 power-domain-names = "psci";
288 qcom,freq-domain = <&c 254 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 255 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ !! 256 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
291 <&epss 257 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 258 #cooling-cells = <2>;
293 L2_700: l2-cache { 259 L2_700: l2-cache {
294 compatible = " 260 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 261 next-level-cache = <&L3_0>;
299 }; 262 };
300 }; 263 };
301 264
302 cpu-map { 265 cpu-map {
303 cluster0 { 266 cluster0 {
304 core0 { 267 core0 {
305 cpu = 268 cpu = <&CPU0>;
306 }; 269 };
307 270
308 core1 { 271 core1 {
309 cpu = 272 cpu = <&CPU1>;
310 }; 273 };
311 274
312 core2 { 275 core2 {
313 cpu = 276 cpu = <&CPU2>;
314 }; 277 };
315 278
316 core3 { 279 core3 {
317 cpu = 280 cpu = <&CPU3>;
318 }; 281 };
319 282
320 core4 { 283 core4 {
321 cpu = 284 cpu = <&CPU4>;
322 }; 285 };
323 286
324 core5 { 287 core5 {
325 cpu = 288 cpu = <&CPU5>;
326 }; 289 };
327 290
328 core6 { 291 core6 {
329 cpu = 292 cpu = <&CPU6>;
330 }; 293 };
331 294
332 core7 { 295 core7 {
333 cpu = 296 cpu = <&CPU7>;
334 }; 297 };
335 }; 298 };
336 }; 299 };
337 300
338 idle-states { 301 idle-states {
339 entry-method = "psci"; 302 entry-method = "psci";
340 303
341 LITTLE_CPU_SLEEP_0: cp 304 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 305 compatible = "arm,idle-state";
343 idle-state-nam 306 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 307 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 308 entry-latency-us = <360>;
346 exit-latency-u 309 exit-latency-us = <531>;
347 min-residency- 310 min-residency-us = <3934>;
348 local-timer-st 311 local-timer-stop;
349 }; 312 };
350 313
351 BIG_CPU_SLEEP_0: cpu-s 314 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 315 compatible = "arm,idle-state";
353 idle-state-nam 316 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 317 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 318 entry-latency-us = <702>;
356 exit-latency-u 319 exit-latency-us = <1061>;
357 min-residency- 320 min-residency-us = <4488>;
358 local-timer-st 321 local-timer-stop;
359 }; 322 };
360 }; 323 };
361 324
362 domain-idle-states { 325 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 326 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 327 compatible = "domain-idle-state";
>> 328 idle-state-name = "cluster-llcc-off";
365 arm,psci-suspe 329 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 330 entry-latency-us = <3264>;
367 exit-latency-u 331 exit-latency-us = <6562>;
368 min-residency- 332 min-residency-us = <9987>;
>> 333 local-timer-stop;
369 }; 334 };
370 }; 335 };
371 }; 336 };
372 337
373 qup_virt: interconnect-qup-virt { !! 338 cpu0_opp_table: cpu0_opp_table {
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points 339 compatible = "operating-points-v2";
381 opp-shared; 340 opp-shared;
382 341
383 cpu0_opp1: opp-300000000 { 342 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 343 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 344 opp-peak-kBps = <800000 9600000>;
386 }; 345 };
387 346
388 cpu0_opp2: opp-403200000 { 347 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 348 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 349 opp-peak-kBps = <800000 9600000>;
391 }; 350 };
392 351
393 cpu0_opp3: opp-518400000 { 352 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 353 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 354 opp-peak-kBps = <800000 16588800>;
396 }; 355 };
397 356
398 cpu0_opp4: opp-614400000 { 357 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 358 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 359 opp-peak-kBps = <800000 16588800>;
401 }; 360 };
402 361
403 cpu0_opp5: opp-691200000 { 362 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 363 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 364 opp-peak-kBps = <800000 19660800>;
406 }; 365 };
407 366
408 cpu0_opp6: opp-787200000 { 367 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 368 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 369 opp-peak-kBps = <1804000 19660800>;
411 }; 370 };
412 371
413 cpu0_opp7: opp-883200000 { 372 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 373 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 374 opp-peak-kBps = <1804000 23347200>;
416 }; 375 };
417 376
418 cpu0_opp8: opp-979200000 { 377 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 378 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 379 opp-peak-kBps = <1804000 26419200>;
421 }; 380 };
422 381
423 cpu0_opp9: opp-1075200000 { 382 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 383 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 384 opp-peak-kBps = <1804000 29491200>;
426 }; 385 };
427 386
428 cpu0_opp10: opp-1171200000 { 387 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 388 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 389 opp-peak-kBps = <1804000 32563200>;
431 }; 390 };
432 391
433 cpu0_opp11: opp-1248000000 { 392 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 393 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 394 opp-peak-kBps = <1804000 36249600>;
436 }; 395 };
437 396
438 cpu0_opp12: opp-1344000000 { 397 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 398 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 399 opp-peak-kBps = <2188000 36249600>;
441 }; 400 };
442 401
443 cpu0_opp13: opp-1420800000 { 402 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 403 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 404 opp-peak-kBps = <2188000 39321600>;
446 }; 405 };
447 406
448 cpu0_opp14: opp-1516800000 { 407 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 408 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 409 opp-peak-kBps = <3072000 42393600>;
451 }; 410 };
452 411
453 cpu0_opp15: opp-1612800000 { 412 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 413 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 414 opp-peak-kBps = <3072000 42393600>;
456 }; 415 };
457 416
458 cpu0_opp16: opp-1708800000 { 417 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 418 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 419 opp-peak-kBps = <4068000 42393600>;
461 }; 420 };
462 421
463 cpu0_opp17: opp-1804800000 { 422 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 423 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 424 opp-peak-kBps = <4068000 42393600>;
466 }; 425 };
467 }; 426 };
468 427
469 cpu4_opp_table: opp-table-cpu4 { !! 428 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 429 compatible = "operating-points-v2";
471 opp-shared; 430 opp-shared;
472 431
473 cpu4_opp1: opp-710400000 { 432 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 433 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 434 opp-peak-kBps = <1804000 19660800>;
476 }; 435 };
477 436
478 cpu4_opp2: opp-825600000 { 437 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 438 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 439 opp-peak-kBps = <2188000 23347200>;
481 }; 440 };
482 441
483 cpu4_opp3: opp-940800000 { 442 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 443 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 444 opp-peak-kBps = <2188000 26419200>;
486 }; 445 };
487 446
488 cpu4_opp4: opp-1056000000 { 447 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 448 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 449 opp-peak-kBps = <3072000 26419200>;
491 }; 450 };
492 451
493 cpu4_opp5: opp-1171200000 { 452 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 453 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 454 opp-peak-kBps = <3072000 29491200>;
496 }; 455 };
497 456
498 cpu4_opp6: opp-1286400000 { 457 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 458 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 459 opp-peak-kBps = <4068000 29491200>;
501 }; 460 };
502 461
503 cpu4_opp7: opp-1382400000 { 462 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 463 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 464 opp-peak-kBps = <4068000 32563200>;
506 }; 465 };
507 466
508 cpu4_opp8: opp-1478400000 { 467 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 468 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 469 opp-peak-kBps = <4068000 32563200>;
511 }; 470 };
512 471
513 cpu4_opp9: opp-1574400000 { 472 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 473 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 474 opp-peak-kBps = <5412000 39321600>;
516 }; 475 };
517 476
518 cpu4_opp10: opp-1670400000 { 477 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 478 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 479 opp-peak-kBps = <5412000 42393600>;
521 }; 480 };
522 481
523 cpu4_opp11: opp-1766400000 { 482 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 483 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 484 opp-peak-kBps = <5412000 45465600>;
526 }; 485 };
527 486
528 cpu4_opp12: opp-1862400000 { 487 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 488 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 489 opp-peak-kBps = <6220000 45465600>;
531 }; 490 };
532 491
533 cpu4_opp13: opp-1958400000 { 492 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 493 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 494 opp-peak-kBps = <6220000 48537600>;
536 }; 495 };
537 496
538 cpu4_opp14: opp-2054400000 { 497 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 498 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 499 opp-peak-kBps = <7216000 48537600>;
541 }; 500 };
542 501
543 cpu4_opp15: opp-2150400000 { 502 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 503 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 504 opp-peak-kBps = <7216000 51609600>;
546 }; 505 };
547 506
548 cpu4_opp16: opp-2246400000 { 507 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 508 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 509 opp-peak-kBps = <7216000 51609600>;
551 }; 510 };
552 511
553 cpu4_opp17: opp-2342400000 { 512 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 513 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 514 opp-peak-kBps = <8368000 51609600>;
556 }; 515 };
557 516
558 cpu4_opp18: opp-2419200000 { 517 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 518 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 519 opp-peak-kBps = <8368000 51609600>;
561 }; 520 };
562 }; 521 };
563 522
564 cpu7_opp_table: opp-table-cpu7 { !! 523 cpu7_opp_table: cpu7_opp_table {
565 compatible = "operating-points 524 compatible = "operating-points-v2";
566 opp-shared; 525 opp-shared;
567 526
568 cpu7_opp1: opp-844800000 { 527 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 528 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 529 opp-peak-kBps = <2188000 19660800>;
571 }; 530 };
572 531
573 cpu7_opp2: opp-960000000 { 532 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 533 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 534 opp-peak-kBps = <2188000 26419200>;
576 }; 535 };
577 536
578 cpu7_opp3: opp-1075200000 { 537 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 538 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 539 opp-peak-kBps = <3072000 26419200>;
581 }; 540 };
582 541
583 cpu7_opp4: opp-1190400000 { 542 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 543 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 544 opp-peak-kBps = <3072000 29491200>;
586 }; 545 };
587 546
588 cpu7_opp5: opp-1305600000 { 547 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 548 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 549 opp-peak-kBps = <4068000 32563200>;
591 }; 550 };
592 551
593 cpu7_opp6: opp-1401600000 { 552 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 553 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 554 opp-peak-kBps = <4068000 32563200>;
596 }; 555 };
597 556
598 cpu7_opp7: opp-1516800000 { 557 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 558 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 559 opp-peak-kBps = <4068000 36249600>;
601 }; 560 };
602 561
603 cpu7_opp8: opp-1632000000 { 562 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 563 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 564 opp-peak-kBps = <5412000 39321600>;
606 }; 565 };
607 566
608 cpu7_opp9: opp-1747200000 { 567 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 568 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 569 opp-peak-kBps = <5412000 42393600>;
611 }; 570 };
612 571
613 cpu7_opp10: opp-1862400000 { 572 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 573 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 574 opp-peak-kBps = <6220000 45465600>;
616 }; 575 };
617 576
618 cpu7_opp11: opp-1977600000 { 577 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 578 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 579 opp-peak-kBps = <6220000 48537600>;
621 }; 580 };
622 581
623 cpu7_opp12: opp-2073600000 { 582 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 583 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 584 opp-peak-kBps = <7216000 48537600>;
626 }; 585 };
627 586
628 cpu7_opp13: opp-2169600000 { 587 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 588 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 589 opp-peak-kBps = <7216000 51609600>;
631 }; 590 };
632 591
633 cpu7_opp14: opp-2265600000 { 592 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 593 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 594 opp-peak-kBps = <7216000 51609600>;
636 }; 595 };
637 596
638 cpu7_opp15: opp-2361600000 { 597 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 598 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 599 opp-peak-kBps = <8368000 51609600>;
641 }; 600 };
642 601
643 cpu7_opp16: opp-2457600000 { 602 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 603 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 604 opp-peak-kBps = <8368000 51609600>;
646 }; 605 };
647 606
648 cpu7_opp17: opp-2553600000 { 607 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 608 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 609 opp-peak-kBps = <8368000 51609600>;
651 }; 610 };
652 611
653 cpu7_opp18: opp-2649600000 { 612 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 613 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 614 opp-peak-kBps = <8368000 51609600>;
656 }; 615 };
657 616
658 cpu7_opp19: opp-2745600000 { 617 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 618 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 619 opp-peak-kBps = <8368000 51609600>;
661 }; 620 };
662 621
663 cpu7_opp20: opp-2841600000 { 622 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 623 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 624 opp-peak-kBps = <8368000 51609600>;
666 }; 625 };
667 }; 626 };
668 627
669 firmware { 628 firmware {
670 scm: scm { 629 scm: scm {
671 compatible = "qcom,scm !! 630 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 631 #reset-cells = <1>;
674 }; 632 };
675 }; 633 };
676 634
677 memory@80000000 { 635 memory@80000000 {
678 device_type = "memory"; 636 device_type = "memory";
679 /* We expect the bootloader to 637 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 638 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 639 };
682 640
683 pmu { 641 pmu {
684 compatible = "arm,armv8-pmuv3" 642 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 643 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 644 };
687 645
688 psci { 646 psci {
689 compatible = "arm,psci-1.0"; 647 compatible = "arm,psci-1.0";
690 method = "smc"; 648 method = "smc";
691 649
692 CPU_PD0: power-domain-cpu0 { !! 650 CPU_PD0: cpu0 {
693 #power-domain-cells = 651 #power-domain-cells = <0>;
694 power-domains = <&CLUS 652 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 653 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 654 };
697 655
698 CPU_PD1: power-domain-cpu1 { !! 656 CPU_PD1: cpu1 {
699 #power-domain-cells = 657 #power-domain-cells = <0>;
700 power-domains = <&CLUS 658 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 659 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 660 };
703 661
704 CPU_PD2: power-domain-cpu2 { !! 662 CPU_PD2: cpu2 {
705 #power-domain-cells = 663 #power-domain-cells = <0>;
706 power-domains = <&CLUS 664 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 665 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 666 };
709 667
710 CPU_PD3: power-domain-cpu3 { !! 668 CPU_PD3: cpu3 {
711 #power-domain-cells = 669 #power-domain-cells = <0>;
712 power-domains = <&CLUS 670 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 671 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 672 };
715 673
716 CPU_PD4: power-domain-cpu4 { !! 674 CPU_PD4: cpu4 {
717 #power-domain-cells = 675 #power-domain-cells = <0>;
718 power-domains = <&CLUS 676 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 677 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 678 };
721 679
722 CPU_PD5: power-domain-cpu5 { !! 680 CPU_PD5: cpu5 {
723 #power-domain-cells = 681 #power-domain-cells = <0>;
724 power-domains = <&CLUS 682 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 683 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 684 };
727 685
728 CPU_PD6: power-domain-cpu6 { !! 686 CPU_PD6: cpu6 {
729 #power-domain-cells = 687 #power-domain-cells = <0>;
730 power-domains = <&CLUS 688 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 689 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 690 };
733 691
734 CPU_PD7: power-domain-cpu7 { !! 692 CPU_PD7: cpu7 {
735 #power-domain-cells = 693 #power-domain-cells = <0>;
736 power-domains = <&CLUS 694 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 695 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 696 };
739 697
740 CLUSTER_PD: power-domain-cpu-c !! 698 CLUSTER_PD: cpu-cluster0 {
741 #power-domain-cells = 699 #power-domain-cells = <0>;
742 domain-idle-states = < 700 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 701 };
744 }; 702 };
745 703
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; <<
764 <<
765 reserved-memory { 704 reserved-memory {
766 #address-cells = <2>; 705 #address-cells = <2>;
767 #size-cells = <2>; 706 #size-cells = <2>;
768 ranges; 707 ranges;
769 708
770 hyp_mem: memory@80000000 { 709 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 710 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 711 no-map;
773 }; 712 };
774 713
775 xbl_aop_mem: memory@80700000 { 714 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 715 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 716 no-map;
778 }; 717 };
779 718
780 cmd_db: memory@80860000 { 719 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 720 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 721 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 722 no-map;
784 }; 723 };
785 724
786 smem_mem: memory@80900000 { 725 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 726 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 727 no-map;
789 }; 728 };
790 729
791 removed_mem: memory@80b00000 { 730 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 731 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 732 no-map;
794 }; 733 };
795 734
796 camera_mem: memory@86200000 { 735 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 736 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 737 no-map;
799 }; 738 };
800 739
801 wlan_mem: memory@86700000 { 740 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 741 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 742 no-map;
804 }; 743 };
805 744
806 ipa_fw_mem: memory@86800000 { 745 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 746 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 747 no-map;
809 }; 748 };
810 749
811 ipa_gsi_mem: memory@86810000 { 750 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 751 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 752 no-map;
814 }; 753 };
815 754
816 gpu_mem: memory@8681a000 { 755 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 756 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 757 no-map;
819 }; 758 };
820 759
821 npu_mem: memory@86900000 { 760 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 761 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 762 no-map;
824 }; 763 };
825 764
826 video_mem: memory@86e00000 { 765 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 766 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 767 no-map;
829 }; 768 };
830 769
831 cvp_mem: memory@87300000 { 770 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 771 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 772 no-map;
834 }; 773 };
835 774
836 cdsp_mem: memory@87800000 { 775 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 776 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 777 no-map;
839 }; 778 };
840 779
841 slpi_mem: memory@88c00000 { 780 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 781 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 782 no-map;
844 }; 783 };
845 784
846 adsp_mem: memory@8a100000 { 785 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 786 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 787 no-map;
849 }; 788 };
850 789
851 spss_mem: memory@8be00000 { 790 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 791 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 792 no-map;
854 }; 793 };
855 794
856 cdsp_secure_heap: memory@8bf00 795 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 796 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 797 no-map;
859 }; 798 };
860 }; 799 };
861 800
862 smem { 801 smem {
863 compatible = "qcom,smem"; 802 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 803 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 804 hwlocks = <&tcsr_mutex 3>;
866 }; 805 };
867 806
868 smp2p-adsp { 807 smp2p-adsp {
869 compatible = "qcom,smp2p"; 808 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 809 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 810 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 811 IPCC_MPROC_SIGNAL_SMP2P
873 I 812 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 813 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 814 IPCC_MPROC_SIGNAL_SMP2P>;
876 815
877 qcom,local-pid = <0>; 816 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 817 qcom,remote-pid = <2>;
879 818
880 smp2p_adsp_out: master-kernel 819 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 820 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 821 #qcom,smem-state-cells = <1>;
883 }; 822 };
884 823
885 smp2p_adsp_in: slave-kernel { 824 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 825 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 826 interrupt-controller;
888 #interrupt-cells = <2> 827 #interrupt-cells = <2>;
889 }; 828 };
890 }; 829 };
891 830
892 smp2p-cdsp { 831 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 832 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 833 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 834 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 835 IPCC_MPROC_SIGNAL_SMP2P
897 I 836 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 837 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 838 IPCC_MPROC_SIGNAL_SMP2P>;
900 839
901 qcom,local-pid = <0>; 840 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 841 qcom,remote-pid = <5>;
903 842
904 smp2p_cdsp_out: master-kernel 843 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 844 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 845 #qcom,smem-state-cells = <1>;
907 }; 846 };
908 847
909 smp2p_cdsp_in: slave-kernel { 848 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 849 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 850 interrupt-controller;
912 #interrupt-cells = <2> 851 #interrupt-cells = <2>;
913 }; 852 };
914 }; 853 };
915 854
916 smp2p-slpi { 855 smp2p-slpi {
917 compatible = "qcom,smp2p"; 856 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 857 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 858 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 859 IPCC_MPROC_SIGNAL_SMP2P
921 I 860 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 861 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 862 IPCC_MPROC_SIGNAL_SMP2P>;
924 863
925 qcom,local-pid = <0>; 864 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 865 qcom,remote-pid = <3>;
927 866
928 smp2p_slpi_out: master-kernel 867 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 868 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 869 #qcom,smem-state-cells = <1>;
931 }; 870 };
932 871
933 smp2p_slpi_in: slave-kernel { 872 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 873 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 874 interrupt-controller;
936 #interrupt-cells = <2> 875 #interrupt-cells = <2>;
937 }; 876 };
938 }; 877 };
939 878
940 soc: soc@0 { 879 soc: soc@0 {
941 #address-cells = <2>; 880 #address-cells = <2>;
942 #size-cells = <2>; 881 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 882 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 883 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 884 compatible = "simple-bus";
946 885
947 gcc: clock-controller@100000 { 886 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 887 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 888 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 889 #clock-cells = <1>;
951 #reset-cells = <1>; 890 #reset-cells = <1>;
952 #power-domain-cells = 891 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 892 clock-names = "bi_tcxo",
954 "bi_tcxo 893 "bi_tcxo_ao",
955 "sleep_c 894 "sleep_clk";
956 clocks = <&rpmhcc RPMH 895 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 896 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 897 <&sleep_clk>;
959 }; 898 };
960 899
961 ipcc: mailbox@408000 { 900 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 901 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 902 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 903 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 904 interrupt-controller;
966 #interrupt-cells = <3> 905 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 906 #mbox-cells = <2>;
968 }; 907 };
969 908
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 909 rng: rng@793000 {
983 compatible = "qcom,prn 910 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 911 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 912 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 913 clock-names = "core";
987 }; 914 };
988 915
>> 916 qup_opp_table: qup-opp-table {
>> 917 compatible = "operating-points-v2";
>> 918
>> 919 opp-50000000 {
>> 920 opp-hz = /bits/ 64 <50000000>;
>> 921 required-opps = <&rpmhpd_opp_min_svs>;
>> 922 };
>> 923
>> 924 opp-75000000 {
>> 925 opp-hz = /bits/ 64 <75000000>;
>> 926 required-opps = <&rpmhpd_opp_low_svs>;
>> 927 };
>> 928
>> 929 opp-120000000 {
>> 930 opp-hz = /bits/ 64 <120000000>;
>> 931 required-opps = <&rpmhpd_opp_svs>;
>> 932 };
>> 933 };
>> 934
989 gpi_dma2: dma-controller@80000 935 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 !! 936 compatible = "qcom,sm8250-gpi-dma";
991 reg = <0 0x00800000 0 937 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 938 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 939 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 940 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 941 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 942 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 943 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 944 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 945 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 946 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 947 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 948 dma-channels = <10>;
1003 dma-channel-mask = <0 949 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 950 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 951 #dma-cells = <3>;
1006 status = "disabled"; 952 status = "disabled";
1007 }; 953 };
1008 954
1009 qupv3_id_2: geniqup@8c0000 { 955 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 956 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 957 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 958 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 959 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 960 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 961 #address-cells = <2>;
1016 #size-cells = <2>; 962 #size-cells = <2>;
1017 iommus = <&apps_smmu 963 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 964 ranges;
1019 status = "disabled"; 965 status = "disabled";
1020 966
1021 i2c14: i2c@880000 { 967 i2c14: i2c@880000 {
1022 compatible = 968 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 969 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 970 clock-names = "se";
1025 clocks = <&gc 971 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 972 pinctrl-names = "default";
1027 pinctrl-0 = < 973 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 974 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 975 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 976 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 977 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 978 #address-cells = <1>;
1040 #size-cells = 979 #size-cells = <0>;
1041 status = "dis 980 status = "disabled";
1042 }; 981 };
1043 982
1044 spi14: spi@880000 { 983 spi14: spi@880000 {
1045 compatible = 984 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 985 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 986 clock-names = "se";
1048 clocks = <&gc 987 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 988 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 989 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 990 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 991 dma-names = "tx", "rx";
1053 power-domains !! 992 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 993 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 994 #address-cells = <1>;
1062 #size-cells = 995 #size-cells = <0>;
1063 status = "dis 996 status = "disabled";
1064 }; 997 };
1065 998
1066 i2c15: i2c@884000 { 999 i2c15: i2c@884000 {
1067 compatible = 1000 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1001 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1002 clock-names = "se";
1070 clocks = <&gc 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1004 pinctrl-names = "default";
1072 pinctrl-0 = < 1005 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1006 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1007 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1008 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1009 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 1010 #address-cells = <1>;
1085 #size-cells = 1011 #size-cells = <0>;
1086 status = "dis 1012 status = "disabled";
1087 }; 1013 };
1088 1014
1089 spi15: spi@884000 { 1015 spi15: spi@884000 {
1090 compatible = 1016 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1017 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1018 clock-names = "se";
1093 clocks = <&gc 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1020 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1021 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1022 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1023 dma-names = "tx", "rx";
1098 power-domains !! 1024 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 1025 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 1026 #address-cells = <1>;
1107 #size-cells = 1027 #size-cells = <0>;
1108 status = "dis 1028 status = "disabled";
1109 }; 1029 };
1110 1030
1111 i2c16: i2c@888000 { 1031 i2c16: i2c@888000 {
1112 compatible = 1032 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1033 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1034 clock-names = "se";
1115 clocks = <&gc 1035 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1036 pinctrl-names = "default";
1117 pinctrl-0 = < 1037 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1038 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1039 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1040 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1041 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 1042 #address-cells = <1>;
1130 #size-cells = 1043 #size-cells = <0>;
1131 status = "dis 1044 status = "disabled";
1132 }; 1045 };
1133 1046
1134 spi16: spi@888000 { 1047 spi16: spi@888000 {
1135 compatible = 1048 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1049 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1050 clock-names = "se";
1138 clocks = <&gc 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1052 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1053 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1054 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1055 dma-names = "tx", "rx";
1143 power-domains !! 1056 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 1057 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 1058 #address-cells = <1>;
1152 #size-cells = 1059 #size-cells = <0>;
1153 status = "dis 1060 status = "disabled";
1154 }; 1061 };
1155 1062
1156 i2c17: i2c@88c000 { 1063 i2c17: i2c@88c000 {
1157 compatible = 1064 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1065 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1066 clock-names = "se";
1160 clocks = <&gc 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1068 pinctrl-names = "default";
1162 pinctrl-0 = < 1069 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1070 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1071 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1072 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1073 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 1074 #address-cells = <1>;
1175 #size-cells = 1075 #size-cells = <0>;
1176 status = "dis 1076 status = "disabled";
1177 }; 1077 };
1178 1078
1179 spi17: spi@88c000 { 1079 spi17: spi@88c000 {
1180 compatible = 1080 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1081 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1082 clock-names = "se";
1183 clocks = <&gc 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1084 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1085 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1086 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1087 dma-names = "tx", "rx";
1188 power-domains !! 1088 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 1089 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 1090 #address-cells = <1>;
1197 #size-cells = 1091 #size-cells = <0>;
1198 status = "dis 1092 status = "disabled";
1199 }; 1093 };
1200 1094
1201 uart17: serial@88c000 1095 uart17: serial@88c000 {
1202 compatible = 1096 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1097 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1098 clock-names = "se";
1205 clocks = <&gc 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1100 pinctrl-names = "default";
1207 pinctrl-0 = < 1101 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1102 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 1103 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 1104 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1105 status = "disabled";
1216 }; 1106 };
1217 1107
1218 i2c18: i2c@890000 { 1108 i2c18: i2c@890000 {
1219 compatible = 1109 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1110 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1111 clock-names = "se";
1222 clocks = <&gc 1112 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1113 pinctrl-names = "default";
1224 pinctrl-0 = < 1114 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1115 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1116 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1117 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1118 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1119 #address-cells = <1>;
1237 #size-cells = 1120 #size-cells = <0>;
1238 status = "dis 1121 status = "disabled";
1239 }; 1122 };
1240 1123
1241 spi18: spi@890000 { 1124 spi18: spi@890000 {
1242 compatible = 1125 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1126 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1127 clock-names = "se";
1245 clocks = <&gc 1128 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1129 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1130 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1131 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1132 dma-names = "tx", "rx";
1250 power-domains !! 1133 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 1134 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1135 #address-cells = <1>;
1259 #size-cells = 1136 #size-cells = <0>;
1260 status = "dis 1137 status = "disabled";
1261 }; 1138 };
1262 1139
1263 uart18: serial@890000 1140 uart18: serial@890000 {
1264 compatible = 1141 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1142 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1143 clock-names = "se";
1267 clocks = <&gc 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1145 pinctrl-names = "default";
1269 pinctrl-0 = < 1146 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1147 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 1148 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 1149 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1150 status = "disabled";
1278 }; 1151 };
1279 1152
1280 i2c19: i2c@894000 { 1153 i2c19: i2c@894000 {
1281 compatible = 1154 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1155 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1156 clock-names = "se";
1284 clocks = <&gc 1157 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1158 pinctrl-names = "default";
1286 pinctrl-0 = < 1159 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1160 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1161 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1162 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1163 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1164 #address-cells = <1>;
1299 #size-cells = 1165 #size-cells = <0>;
1300 status = "dis 1166 status = "disabled";
1301 }; 1167 };
1302 1168
1303 spi19: spi@894000 { 1169 spi19: spi@894000 {
1304 compatible = 1170 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1171 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1172 clock-names = "se";
1307 clocks = <&gc 1173 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1174 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1175 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1176 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1177 dma-names = "tx", "rx";
1312 power-domains !! 1178 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 1179 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1180 #address-cells = <1>;
1321 #size-cells = 1181 #size-cells = <0>;
1322 status = "dis 1182 status = "disabled";
1323 }; 1183 };
1324 }; 1184 };
1325 1185
1326 gpi_dma0: dma-controller@9000 1186 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm !! 1187 compatible = "qcom,sm8250-gpi-dma";
1328 reg = <0 0x00900000 0 1188 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1189 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1190 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1191 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1192 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1193 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1194 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1195 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1196 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1197 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1198 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1199 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1200 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1201 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1202 dma-channels = <15>;
1343 dma-channel-mask = <0 1203 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1204 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1205 #dma-cells = <3>;
1346 status = "disabled"; 1206 status = "disabled";
1347 }; 1207 };
1348 1208
1349 qupv3_id_0: geniqup@9c0000 { 1209 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1210 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1211 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1212 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1213 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1214 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1215 #address-cells = <2>;
1356 #size-cells = <2>; 1216 #size-cells = <2>;
1357 iommus = <&apps_smmu 1217 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1218 ranges;
1359 status = "disabled"; 1219 status = "disabled";
1360 1220
1361 i2c0: i2c@980000 { 1221 i2c0: i2c@980000 {
1362 compatible = 1222 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1223 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1224 clock-names = "se";
1365 clocks = <&gc 1225 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1226 pinctrl-names = "default";
1367 pinctrl-0 = < 1227 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1228 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1229 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1230 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1231 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1232 #address-cells = <1>;
1380 #size-cells = 1233 #size-cells = <0>;
1381 status = "dis 1234 status = "disabled";
1382 }; 1235 };
1383 1236
1384 spi0: spi@980000 { 1237 spi0: spi@980000 {
1385 compatible = 1238 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1239 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1240 clock-names = "se";
1388 clocks = <&gc 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1242 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1243 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1244 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1245 dma-names = "tx", "rx";
1393 power-domains !! 1246 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 1247 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1248 #address-cells = <1>;
1402 #size-cells = 1249 #size-cells = <0>;
1403 status = "dis 1250 status = "disabled";
1404 }; 1251 };
1405 1252
1406 i2c1: i2c@984000 { 1253 i2c1: i2c@984000 {
1407 compatible = 1254 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1255 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1256 clock-names = "se";
1410 clocks = <&gc 1257 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1258 pinctrl-names = "default";
1412 pinctrl-0 = < 1259 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1260 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1261 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1262 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1263 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1264 #address-cells = <1>;
1425 #size-cells = 1265 #size-cells = <0>;
1426 status = "dis 1266 status = "disabled";
1427 }; 1267 };
1428 1268
1429 spi1: spi@984000 { 1269 spi1: spi@984000 {
1430 compatible = 1270 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1271 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1272 clock-names = "se";
1433 clocks = <&gc 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1274 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1275 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1276 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1277 dma-names = "tx", "rx";
1438 power-domains !! 1278 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 1279 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1280 #address-cells = <1>;
1447 #size-cells = 1281 #size-cells = <0>;
1448 status = "dis 1282 status = "disabled";
1449 }; 1283 };
1450 1284
1451 i2c2: i2c@988000 { 1285 i2c2: i2c@988000 {
1452 compatible = 1286 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1287 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1288 clock-names = "se";
1455 clocks = <&gc 1289 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1290 pinctrl-names = "default";
1457 pinctrl-0 = < 1291 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1292 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1293 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1294 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1295 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1296 #address-cells = <1>;
1470 #size-cells = 1297 #size-cells = <0>;
1471 status = "dis 1298 status = "disabled";
1472 }; 1299 };
1473 1300
1474 spi2: spi@988000 { 1301 spi2: spi@988000 {
1475 compatible = 1302 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1303 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1304 clock-names = "se";
1478 clocks = <&gc 1305 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1306 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1307 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1308 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1309 dma-names = "tx", "rx";
1483 power-domains !! 1310 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 1311 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1312 #address-cells = <1>;
1492 #size-cells = 1313 #size-cells = <0>;
1493 status = "dis 1314 status = "disabled";
1494 }; 1315 };
1495 1316
1496 uart2: serial@988000 1317 uart2: serial@988000 {
1497 compatible = 1318 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1319 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1320 clock-names = "se";
1500 clocks = <&gc 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1322 pinctrl-names = "default";
1502 pinctrl-0 = < 1323 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1324 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 1325 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 1326 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1327 status = "disabled";
1511 }; 1328 };
1512 1329
1513 i2c3: i2c@98c000 { 1330 i2c3: i2c@98c000 {
1514 compatible = 1331 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1332 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1333 clock-names = "se";
1517 clocks = <&gc 1334 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1335 pinctrl-names = "default";
1519 pinctrl-0 = < 1336 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1337 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1338 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1339 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1340 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1341 #address-cells = <1>;
1532 #size-cells = 1342 #size-cells = <0>;
1533 status = "dis 1343 status = "disabled";
1534 }; 1344 };
1535 1345
1536 spi3: spi@98c000 { 1346 spi3: spi@98c000 {
1537 compatible = 1347 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1348 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1349 clock-names = "se";
1540 clocks = <&gc 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1351 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1352 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1353 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1354 dma-names = "tx", "rx";
1545 power-domains !! 1355 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 1356 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1357 #address-cells = <1>;
1554 #size-cells = 1358 #size-cells = <0>;
1555 status = "dis 1359 status = "disabled";
1556 }; 1360 };
1557 1361
1558 i2c4: i2c@990000 { 1362 i2c4: i2c@990000 {
1559 compatible = 1363 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1364 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1365 clock-names = "se";
1562 clocks = <&gc 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1367 pinctrl-names = "default";
1564 pinctrl-0 = < 1368 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1369 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1370 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1371 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1372 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1373 #address-cells = <1>;
1577 #size-cells = 1374 #size-cells = <0>;
1578 status = "dis 1375 status = "disabled";
1579 }; 1376 };
1580 1377
1581 spi4: spi@990000 { 1378 spi4: spi@990000 {
1582 compatible = 1379 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1380 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1381 clock-names = "se";
1585 clocks = <&gc 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1383 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1384 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1385 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1386 dma-names = "tx", "rx";
1590 power-domains !! 1387 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 1388 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1389 #address-cells = <1>;
1599 #size-cells = 1390 #size-cells = <0>;
1600 status = "dis 1391 status = "disabled";
1601 }; 1392 };
1602 1393
1603 i2c5: i2c@994000 { 1394 i2c5: i2c@994000 {
1604 compatible = 1395 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1396 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1397 clock-names = "se";
1607 clocks = <&gc 1398 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1399 pinctrl-names = "default";
1609 pinctrl-0 = < 1400 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1401 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1402 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1403 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1404 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1405 #address-cells = <1>;
1622 #size-cells = 1406 #size-cells = <0>;
1623 status = "dis 1407 status = "disabled";
1624 }; 1408 };
1625 1409
1626 spi5: spi@994000 { 1410 spi5: spi@994000 {
1627 compatible = 1411 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1412 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1413 clock-names = "se";
1630 clocks = <&gc 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1415 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1416 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1417 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1418 dma-names = "tx", "rx";
1635 power-domains !! 1419 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1420 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1421 #address-cells = <1>;
1644 #size-cells = 1422 #size-cells = <0>;
1645 status = "dis 1423 status = "disabled";
1646 }; 1424 };
1647 1425
1648 i2c6: i2c@998000 { 1426 i2c6: i2c@998000 {
1649 compatible = 1427 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1428 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1429 clock-names = "se";
1652 clocks = <&gc 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1431 pinctrl-names = "default";
1654 pinctrl-0 = < 1432 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1433 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1434 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1435 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1436 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1437 #address-cells = <1>;
1667 #size-cells = 1438 #size-cells = <0>;
1668 status = "dis 1439 status = "disabled";
1669 }; 1440 };
1670 1441
1671 spi6: spi@998000 { 1442 spi6: spi@998000 {
1672 compatible = 1443 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1444 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1445 clock-names = "se";
1675 clocks = <&gc 1446 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1447 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1448 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1449 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1450 dma-names = "tx", "rx";
1680 power-domains !! 1451 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1452 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1453 #address-cells = <1>;
1689 #size-cells = 1454 #size-cells = <0>;
1690 status = "dis 1455 status = "disabled";
1691 }; 1456 };
1692 1457
1693 uart6: serial@998000 1458 uart6: serial@998000 {
1694 compatible = 1459 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1460 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1461 clock-names = "se";
1697 clocks = <&gc 1462 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1463 pinctrl-names = "default";
1699 pinctrl-0 = < 1464 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1465 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1466 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1467 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1468 status = "disabled";
1708 }; 1469 };
1709 1470
1710 i2c7: i2c@99c000 { 1471 i2c7: i2c@99c000 {
1711 compatible = 1472 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1473 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1474 clock-names = "se";
1714 clocks = <&gc 1475 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1476 pinctrl-names = "default";
1716 pinctrl-0 = < 1477 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1478 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1479 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1480 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1481 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1482 #address-cells = <1>;
1729 #size-cells = 1483 #size-cells = <0>;
1730 status = "dis 1484 status = "disabled";
1731 }; 1485 };
1732 1486
1733 spi7: spi@99c000 { 1487 spi7: spi@99c000 {
1734 compatible = 1488 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1489 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1490 clock-names = "se";
1737 clocks = <&gc 1491 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1492 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1493 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1494 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1495 dma-names = "tx", "rx";
1742 power-domains !! 1496 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1497 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1498 #address-cells = <1>;
1751 #size-cells = 1499 #size-cells = <0>;
1752 status = "dis 1500 status = "disabled";
1753 }; 1501 };
1754 }; 1502 };
1755 1503
1756 gpi_dma1: dma-controller@a000 1504 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm !! 1505 compatible = "qcom,sm8250-gpi-dma";
1758 reg = <0 0x00a00000 0 1506 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1507 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1508 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1509 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1510 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1511 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1512 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1513 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1514 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1515 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1516 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1517 dma-channels = <10>;
1770 dma-channel-mask = <0 1518 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1519 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1520 #dma-cells = <3>;
1773 status = "disabled"; 1521 status = "disabled";
1774 }; 1522 };
1775 1523
1776 qupv3_id_1: geniqup@ac0000 { 1524 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1525 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1526 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1527 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1528 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1529 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1530 #address-cells = <2>;
1783 #size-cells = <2>; 1531 #size-cells = <2>;
1784 iommus = <&apps_smmu 1532 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1533 ranges;
1786 status = "disabled"; 1534 status = "disabled";
1787 1535
1788 i2c8: i2c@a80000 { 1536 i2c8: i2c@a80000 {
1789 compatible = 1537 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1538 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1539 clock-names = "se";
1792 clocks = <&gc 1540 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1541 pinctrl-names = "default";
1794 pinctrl-0 = < 1542 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1543 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1544 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1545 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1546 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1547 #address-cells = <1>;
1807 #size-cells = 1548 #size-cells = <0>;
1808 status = "dis 1549 status = "disabled";
1809 }; 1550 };
1810 1551
1811 spi8: spi@a80000 { 1552 spi8: spi@a80000 {
1812 compatible = 1553 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1554 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1555 clock-names = "se";
1815 clocks = <&gc 1556 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1557 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1558 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1560 dma-names = "tx", "rx";
1820 power-domains !! 1561 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1562 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1563 #address-cells = <1>;
1829 #size-cells = 1564 #size-cells = <0>;
1830 status = "dis 1565 status = "disabled";
1831 }; 1566 };
1832 1567
1833 i2c9: i2c@a84000 { 1568 i2c9: i2c@a84000 {
1834 compatible = 1569 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1570 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1571 clock-names = "se";
1837 clocks = <&gc 1572 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1573 pinctrl-names = "default";
1839 pinctrl-0 = < 1574 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1575 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1576 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1577 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1578 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1579 #address-cells = <1>;
1852 #size-cells = 1580 #size-cells = <0>;
1853 status = "dis 1581 status = "disabled";
1854 }; 1582 };
1855 1583
1856 spi9: spi@a84000 { 1584 spi9: spi@a84000 {
1857 compatible = 1585 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1586 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1587 clock-names = "se";
1860 clocks = <&gc 1588 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1589 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1590 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1591 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1592 dma-names = "tx", "rx";
1865 power-domains !! 1593 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1594 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1595 #address-cells = <1>;
1874 #size-cells = 1596 #size-cells = <0>;
1875 status = "dis 1597 status = "disabled";
1876 }; 1598 };
1877 1599
1878 i2c10: i2c@a88000 { 1600 i2c10: i2c@a88000 {
1879 compatible = 1601 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1602 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1603 clock-names = "se";
1882 clocks = <&gc 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1605 pinctrl-names = "default";
1884 pinctrl-0 = < 1606 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1607 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1608 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1609 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1610 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1611 #address-cells = <1>;
1897 #size-cells = 1612 #size-cells = <0>;
1898 status = "dis 1613 status = "disabled";
1899 }; 1614 };
1900 1615
1901 spi10: spi@a88000 { 1616 spi10: spi@a88000 {
1902 compatible = 1617 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1618 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1619 clock-names = "se";
1905 clocks = <&gc 1620 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1621 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1622 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1623 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1624 dma-names = "tx", "rx";
1910 power-domains !! 1625 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1626 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1627 #address-cells = <1>;
1919 #size-cells = 1628 #size-cells = <0>;
1920 status = "dis 1629 status = "disabled";
1921 }; 1630 };
1922 1631
1923 i2c11: i2c@a8c000 { 1632 i2c11: i2c@a8c000 {
1924 compatible = 1633 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1634 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1635 clock-names = "se";
1927 clocks = <&gc 1636 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1637 pinctrl-names = "default";
1929 pinctrl-0 = < 1638 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1639 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1640 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1641 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1642 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1643 #address-cells = <1>;
1942 #size-cells = 1644 #size-cells = <0>;
1943 status = "dis 1645 status = "disabled";
1944 }; 1646 };
1945 1647
1946 spi11: spi@a8c000 { 1648 spi11: spi@a8c000 {
1947 compatible = 1649 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1650 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1651 clock-names = "se";
1950 clocks = <&gc 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1653 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1654 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1655 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1656 dma-names = "tx", "rx";
1955 power-domains !! 1657 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1658 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1659 #address-cells = <1>;
1964 #size-cells = 1660 #size-cells = <0>;
1965 status = "dis 1661 status = "disabled";
1966 }; 1662 };
1967 1663
1968 i2c12: i2c@a90000 { 1664 i2c12: i2c@a90000 {
1969 compatible = 1665 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1666 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1667 clock-names = "se";
1972 clocks = <&gc 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1669 pinctrl-names = "default";
1974 pinctrl-0 = < 1670 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1671 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1672 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1673 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1674 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1675 #address-cells = <1>;
1987 #size-cells = 1676 #size-cells = <0>;
1988 status = "dis 1677 status = "disabled";
1989 }; 1678 };
1990 1679
1991 spi12: spi@a90000 { 1680 spi12: spi@a90000 {
1992 compatible = 1681 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1682 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1683 clock-names = "se";
1995 clocks = <&gc 1684 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1685 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1686 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1687 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1688 dma-names = "tx", "rx";
2000 power-domains !! 1689 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1690 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1691 #address-cells = <1>;
2009 #size-cells = 1692 #size-cells = <0>;
2010 status = "dis 1693 status = "disabled";
2011 }; 1694 };
2012 1695
2013 uart12: serial@a90000 1696 uart12: serial@a90000 {
2014 compatible = 1697 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1698 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1699 clock-names = "se";
2017 clocks = <&gc 1700 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1701 pinctrl-names = "default";
2019 pinctrl-0 = < 1702 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1703 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1704 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1705 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1706 status = "disabled";
2028 }; 1707 };
2029 1708
2030 i2c13: i2c@a94000 { 1709 i2c13: i2c@a94000 {
2031 compatible = 1710 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1711 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1712 clock-names = "se";
2034 clocks = <&gc 1713 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1714 pinctrl-names = "default";
2036 pinctrl-0 = < 1715 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1716 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1717 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1718 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1719 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1720 #address-cells = <1>;
2049 #size-cells = 1721 #size-cells = <0>;
2050 status = "dis 1722 status = "disabled";
2051 }; 1723 };
2052 1724
2053 spi13: spi@a94000 { 1725 spi13: spi@a94000 {
2054 compatible = 1726 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1727 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1728 clock-names = "se";
2057 clocks = <&gc 1729 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1730 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1731 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1732 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1733 dma-names = "tx", "rx";
2062 power-domains !! 1734 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1735 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1736 #address-cells = <1>;
2071 #size-cells = 1737 #size-cells = <0>;
2072 status = "dis 1738 status = "disabled";
2073 }; 1739 };
2074 }; 1740 };
2075 1741
2076 config_noc: interconnect@1500 1742 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1743 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1744 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1745 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1746 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1747 };
2082 1748
2083 system_noc: interconnect@1620 1749 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1750 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1751 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1752 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1753 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1754 };
2089 1755
2090 mc_virt: interconnect@163d000 1756 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1757 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1758 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1759 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1760 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1761 };
2096 1762
2097 aggre1_noc: interconnect@16e0 1763 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1764 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1765 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1766 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1767 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1768 };
2103 1769
2104 aggre2_noc: interconnect@1700 1770 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1771 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1772 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1773 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1774 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1775 };
2110 1776
2111 compute_noc: interconnect@173 1777 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1778 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1779 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1780 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1781 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1782 };
2117 1783
2118 mmss_noc: interconnect@174000 1784 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1785 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1786 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1787 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1788 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1789 };
2124 1790
2125 pcie0: pcie@1c00000 { !! 1791 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1792 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1793 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1794 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1795 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1796 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1797 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1798 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1799 device_type = "pci";
2135 linux,pci-domain = <0 1800 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1801 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1802 num-lanes = <1>;
2138 1803
2139 #address-cells = <3>; 1804 #address-cells = <3>;
2140 #size-cells = <2>; 1805 #size-cells = <2>;
2141 1806
2142 ranges = <0x01000000 !! 1807 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1808 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1809
2145 interrupts = <GIC_SPI !! 1810 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1811 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1812 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1813 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1814 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1815 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1816 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1817 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1818
2168 clocks = <&gcc GCC_PC 1819 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1820 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1821 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1822 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1823 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1824 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1825 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1826 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1827 clock-names = "pipe",
2177 "aux", 1828 "aux",
2178 "cfg", 1829 "cfg",
2179 "bus_ma 1830 "bus_master",
2180 "bus_sl 1831 "bus_slave",
2181 "slave_ 1832 "slave_q2a",
2182 "tbu", 1833 "tbu",
2183 "ddrss_ 1834 "ddrss_sf_tbu";
2184 1835
>> 1836 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1837 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1838 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1839
2188 resets = <&gcc GCC_PC 1840 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1841 reset-names = "pci";
2190 1842
2191 power-domains = <&gcc 1843 power-domains = <&gcc PCIE_0_GDSC>;
2192 1844
2193 phys = <&pcie0_phy>; !! 1845 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1846 phy-names = "pciephy";
2195 1847
2196 perst-gpios = <&tlmm 1848 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1849 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1850
2199 pinctrl-names = "defa 1851 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1852 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1853
2203 status = "disabled"; 1854 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1855 };
2215 1856
2216 pcie0_phy: phy@1c06000 { 1857 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1858 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1859 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1860 #address-cells = <2>;
>> 1861 #size-cells = <2>;
>> 1862 ranges;
2220 clocks = <&gcc GCC_PC 1863 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1864 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1865 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1866 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1867 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1868
2236 resets = <&gcc GCC_PC 1869 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1870 reset-names = "phy";
2238 1871
2239 assigned-clocks = <&g 1872 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1873 assigned-clock-rates = <100000000>;
2241 1874
2242 status = "disabled"; 1875 status = "disabled";
>> 1876
>> 1877 pcie0_lane: phy@1c06200 {
>> 1878 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1879 <0 0x1c06400 0 0x200>, /* rx */
>> 1880 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1881 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1882 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1883 clock-names = "pipe0";
>> 1884
>> 1885 #phy-cells = <0>;
>> 1886
>> 1887 #clock-cells = <0>;
>> 1888 clock-output-names = "pcie_0_pipe_clk";
>> 1889 };
2243 }; 1890 };
2244 1891
2245 pcie1: pcie@1c08000 { !! 1892 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1893 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1894 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1895 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1896 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1897 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1898 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1899 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1900 device_type = "pci";
2255 linux,pci-domain = <1 1901 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1902 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1903 num-lanes = <2>;
2258 1904
2259 #address-cells = <3>; 1905 #address-cells = <3>;
2260 #size-cells = <2>; 1906 #size-cells = <2>;
2261 1907
2262 ranges = <0x01000000 !! 1908 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1909 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1910
2265 interrupts = <GIC_SPI !! 1911 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1912 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1913 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1914 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1915 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1916 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1917 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1918 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1919
2288 clocks = <&gcc GCC_PC 1920 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1921 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1922 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1923 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1924 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1925 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1926 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1927 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1928 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1929 clock-names = "pipe",
2298 "aux", 1930 "aux",
2299 "cfg", 1931 "cfg",
2300 "bus_ma 1932 "bus_master",
2301 "bus_sl 1933 "bus_slave",
2302 "slave_ 1934 "slave_q2a",
2303 "ref", 1935 "ref",
2304 "tbu", 1936 "tbu",
2305 "ddrss_ 1937 "ddrss_sf_tbu";
2306 1938
2307 assigned-clocks = <&g 1939 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1940 assigned-clock-rates = <19200000>;
2309 1941
>> 1942 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1943 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1944 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1945
2313 resets = <&gcc GCC_PC 1946 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1947 reset-names = "pci";
2315 1948
2316 power-domains = <&gcc 1949 power-domains = <&gcc PCIE_1_GDSC>;
2317 1950
2318 phys = <&pcie1_phy>; !! 1951 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1952 phy-names = "pciephy";
2320 1953
2321 perst-gpios = <&tlmm 1954 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1955 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1956
2324 pinctrl-names = "defa 1957 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1958 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1959
2328 status = "disabled"; 1960 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1961 };
2340 1962
2341 pcie1_phy: phy@1c0e000 { 1963 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1964 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1965 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1966 #address-cells = <2>;
>> 1967 #size-cells = <2>;
>> 1968 ranges;
2345 clocks = <&gcc GCC_PC 1969 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1970 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1971 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1972 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1973 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1974
2361 resets = <&gcc GCC_PC 1975 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1976 reset-names = "phy";
2363 1977
2364 assigned-clocks = <&g 1978 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1979 assigned-clock-rates = <100000000>;
2366 1980
2367 status = "disabled"; 1981 status = "disabled";
>> 1982
>> 1983 pcie1_lane: phy@1c0e200 {
>> 1984 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1985 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1986 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1987 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1988 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1989 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1990 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1991 clock-names = "pipe0";
>> 1992
>> 1993 #phy-cells = <0>;
>> 1994
>> 1995 #clock-cells = <0>;
>> 1996 clock-output-names = "pcie_1_pipe_clk";
>> 1997 };
2368 }; 1998 };
2369 1999
2370 pcie2: pcie@1c10000 { !! 2000 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 2001 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 2002 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2003 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2004 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2005 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 2006 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 2007 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 2008 device_type = "pci";
2380 linux,pci-domain = <2 2009 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2010 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2011 num-lanes = <2>;
2383 2012
2384 #address-cells = <3>; 2013 #address-cells = <3>;
2385 #size-cells = <2>; 2014 #size-cells = <2>;
2386 2015
2387 ranges = <0x01000000 !! 2016 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2017 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2018
2390 interrupts = <GIC_SPI !! 2019 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2020 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2021 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2022 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2023 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2024 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2025 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2026 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2027
2413 clocks = <&gcc GCC_PC 2028 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2029 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2030 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2031 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2032 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2033 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2034 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2035 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2036 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2037 clock-names = "pipe",
2423 "aux", 2038 "aux",
2424 "cfg", 2039 "cfg",
2425 "bus_ma 2040 "bus_master",
2426 "bus_sl 2041 "bus_slave",
2427 "slave_ 2042 "slave_q2a",
2428 "ref", 2043 "ref",
2429 "tbu", 2044 "tbu",
2430 "ddrss_ 2045 "ddrss_sf_tbu";
2431 2046
2432 assigned-clocks = <&g 2047 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2048 assigned-clock-rates = <19200000>;
2434 2049
>> 2050 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 2051 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2052 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2053
2438 resets = <&gcc GCC_PC 2054 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2055 reset-names = "pci";
2440 2056
2441 power-domains = <&gcc 2057 power-domains = <&gcc PCIE_2_GDSC>;
2442 2058
2443 phys = <&pcie2_phy>; !! 2059 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 2060 phy-names = "pciephy";
2445 2061
2446 perst-gpios = <&tlmm 2062 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2063 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2064
2449 pinctrl-names = "defa 2065 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2066 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 2067
2453 status = "disabled"; 2068 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2069 };
2465 2070
2466 pcie2_phy: phy@1c16000 { 2071 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2072 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 2073 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 2074 #address-cells = <2>;
>> 2075 #size-cells = <2>;
>> 2076 ranges;
2470 clocks = <&gcc GCC_PC 2077 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2078 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2079 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 2080 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 2081 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 2082
2486 resets = <&gcc GCC_PC 2083 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2084 reset-names = "phy";
2488 2085
2489 assigned-clocks = <&g 2086 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2087 assigned-clock-rates = <100000000>;
2491 2088
2492 status = "disabled"; 2089 status = "disabled";
>> 2090
>> 2091 pcie2_lane: phy@1c16200 {
>> 2092 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 2093 <0 0x1c16400 0 0x200>, /* rx0 */
>> 2094 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 2095 <0 0x1c16600 0 0x170>, /* tx1 */
>> 2096 <0 0x1c16800 0 0x200>, /* rx1 */
>> 2097 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2098 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 2099 clock-names = "pipe0";
>> 2100
>> 2101 #phy-cells = <0>;
>> 2102
>> 2103 #clock-cells = <0>;
>> 2104 clock-output-names = "pcie_2_pipe_clk";
>> 2105 };
2493 }; 2106 };
2494 2107
2495 ufs_mem_hc: ufshc@1d84000 { 2108 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2109 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2110 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2111 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2112 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2113 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2114 phy-names = "ufsphy";
2502 lanes-per-direction = 2115 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2116 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2117 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2118 reset-names = "rst";
2506 2119
2507 power-domains = <&gcc 2120 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2121
2509 iommus = <&apps_smmu 2122 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2123
2511 clock-names = 2124 clock-names =
2512 "core_clk", 2125 "core_clk",
2513 "bus_aggr_clk 2126 "bus_aggr_clk",
2514 "iface_clk", 2127 "iface_clk",
2515 "core_clk_uni 2128 "core_clk_unipro",
2516 "ref_clk", 2129 "ref_clk",
2517 "tx_lane0_syn 2130 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2131 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2132 "rx_lane1_sync_clk";
2520 clocks = 2133 clocks =
2521 <&gcc GCC_UFS 2134 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2135 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2136 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2137 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2138 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2139 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2140 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2141 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2142 freq-table-hz =
2530 operating-points-v2 = !! 2143 <37500000 300000000>,
2531 !! 2144 <0 0>,
2532 interconnects = <&agg !! 2145 <0 0>,
2533 <&gem !! 2146 <37500000 300000000>,
2534 interconnect-names = !! 2147 <0 0>,
>> 2148 <0 0>,
>> 2149 <0 0>,
>> 2150 <0 0>;
2535 2151
2536 status = "disabled"; 2152 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2153 };
2566 2154
2567 ufs_mem_phy: phy@1d87000 { 2155 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2156 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2157 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2158 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2159 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2160 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2161 clock-names = "ref",
2575 "ref_au !! 2162 "ref_aux";
2576 "qref"; !! 2163 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2164 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2165
2578 resets = <&ufs_mem_hc 2166 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2167 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2168 status = "disabled";
>> 2169
>> 2170 ufs_mem_phy_lanes: phy@1d87400 {
>> 2171 reg = <0 0x01d87400 0 0x108>,
>> 2172 <0 0x01d87600 0 0x1e0>,
>> 2173 <0 0x01d87c00 0 0x1dc>,
>> 2174 <0 0x01d87800 0 0x108>,
>> 2175 <0 0x01d87a00 0 0x1e0>;
>> 2176 #phy-cells = <0>;
>> 2177 };
2586 }; 2178 };
2587 2179
2588 cryptobam: dma-controller@1dc !! 2180 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 2181 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 2182 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 2183 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 2184 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 2185 };
2619 2186
2620 tcsr_mutex: hwlock@1f40000 { 2187 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2188 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2189 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2190 #hwlock-cells = <1>;
2624 }; 2191 };
2625 2192
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2193 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2194 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2195 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2196 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 2197 <&audiocc 0>,
2636 <&q6afecc LP 2198 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2199 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2200 <&aoncc 0>,
2638 <&vamacro>; 2201 <&vamacro>;
2639 2202
2640 clock-names = "mclk", !! 2203 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2204
2642 #clock-cells = <0>; 2205 #clock-cells = <0>;
>> 2206 clock-frequency = <9600000>;
2643 clock-output-names = 2207 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2208 #sound-dai-cells = <1>;
2645 2209
2646 pinctrl-names = "defa 2210 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2211 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 2212 };
2651 2213
2652 swr0: soundwire@3250000 { !! 2214 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2215 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2216 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2217 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2218 clocks = <&wsamacro>;
2657 clock-names = "iface" 2219 clock-names = "iface";
2658 2220
2659 qcom,din-ports = <2>; 2221 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2222 qcom,dout-ports = <6>;
2661 2223
2662 qcom,ports-sinterval- 2224 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2225 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2226 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2227 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2228
2667 #sound-dai-cells = <1 2229 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2230 #address-cells = <2>;
2669 #size-cells = <0>; 2231 #size-cells = <0>;
>> 2232 };
2670 2233
2671 status = "disabled"; !! 2234 audiocc: clock-controller@3300000 {
>> 2235 compatible = "qcom,sm8250-lpass-audiocc";
>> 2236 reg = <0 0x03300000 0 0x30000>;
>> 2237 #clock-cells = <1>;
>> 2238 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2239 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2240 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2241 clock-names = "core", "audio", "bus";
2672 }; 2242 };
2673 2243
2674 vamacro: codec@3370000 { 2244 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2245 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2246 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2247 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 2248 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2249 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2250
2681 clock-names = "mclk", 2251 clock-names = "mclk", "macro", "dcodec";
2682 2252
2683 #clock-cells = <0>; 2253 #clock-cells = <0>;
>> 2254 clock-frequency = <9600000>;
2684 clock-output-names = 2255 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2256 #sound-dai-cells = <1>;
2686 }; 2257 };
2687 2258
2688 rxmacro: rxmacro@3200000 { 2259 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2260 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2261 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2262 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 !! 2263 reg = <0 0x3200000 0 0x1000>;
2693 status = "disabled"; 2264 status = "disabled";
2694 2265
2695 clocks = <&q6afecc LP 2266 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2267 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2268 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2269 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2270 <&vamacro>;
2700 2271
2701 clock-names = "mclk", 2272 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2273
2703 #clock-cells = <0>; 2274 #clock-cells = <0>;
>> 2275 clock-frequency = <9600000>;
2704 clock-output-names = 2276 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2277 #sound-dai-cells = <1>;
2706 }; 2278 };
2707 2279
2708 swr1: soundwire@3210000 { !! 2280 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 !! 2281 reg = <0 0x3210000 0 0x2000>;
2710 compatible = "qcom,so 2282 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2283 status = "disabled";
2712 interrupts = <GIC_SPI 2284 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2285 clocks = <&rxmacro>;
2714 clock-names = "iface" 2286 clock-names = "iface";
2715 label = "RX"; 2287 label = "RX";
2716 qcom,din-ports = <0>; 2288 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2289 qcom,dout-ports = <5>;
2718 2290
2719 qcom,ports-sinterval- !! 2291 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2720 qcom,ports-offset1 = !! 2292 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2721 qcom,ports-offset2 = !! 2293 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2722 qcom,ports-hstart = !! 2294 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2723 qcom,ports-hstop = !! 2295 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2724 qcom,ports-word-lengt !! 2296 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2725 qcom,ports-block-pack !! 2297 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2726 qcom,ports-lane-contr 2298 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou !! 2299 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2728 2300
2729 #sound-dai-cells = <1 2301 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2302 #address-cells = <2>;
2731 #size-cells = <0>; 2303 #size-cells = <0>;
2732 }; 2304 };
2733 2305
2734 txmacro: txmacro@3220000 { 2306 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2307 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2308 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2309 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 !! 2310 reg = <0 0x3220000 0 0x1000>;
2739 status = "disabled"; 2311 status = "disabled";
2740 2312
2741 clocks = <&q6afecc LP 2313 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2314 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2315 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2316 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2317 <&vamacro>;
2746 2318
2747 clock-names = "mclk", 2319 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2320
2749 #clock-cells = <0>; 2321 #clock-cells = <0>;
>> 2322 clock-frequency = <9600000>;
2750 clock-output-names = 2323 clock-output-names = "mclk";
>> 2324 #address-cells = <2>;
>> 2325 #size-cells = <2>;
2751 #sound-dai-cells = <1 2326 #sound-dai-cells = <1>;
2752 }; 2327 };
2753 2328
2754 /* tx macro */ 2329 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2330 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 !! 2331 reg = <0 0x3230000 0 0x2000>;
2757 compatible = "qcom,so 2332 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI !! 2333 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2334 interrupt-names = "core";
2760 status = "disabled"; 2335 status = "disabled";
2761 2336
2762 clocks = <&txmacro>; 2337 clocks = <&txmacro>;
2763 clock-names = "iface" 2338 clock-names = "iface";
2764 label = "TX"; 2339 label = "TX";
2765 2340
2766 qcom,din-ports = <5>; 2341 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2342 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- !! 2343 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = !! 2344 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = !! 2345 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack !! 2346 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2772 qcom,ports-hstart = !! 2347 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2773 qcom,ports-hstop = !! 2348 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2774 qcom,ports-word-lengt !! 2349 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2775 qcom,ports-block-grou !! 2350 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2776 qcom,ports-lane-contr !! 2351 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
>> 2352 qcom,port-offset = <1>;
2777 #sound-dai-cells = <1 2353 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2354 #address-cells = <2>;
2779 #size-cells = <0>; 2355 #size-cells = <0>;
2780 }; 2356 };
2781 2357
2782 lpass_tlmm: pinctrl@33c0000 { !! 2358 aoncc: clock-controller@3380000 {
>> 2359 compatible = "qcom,sm8250-lpass-aoncc";
>> 2360 reg = <0 0x03380000 0 0x40000>;
>> 2361 #clock-cells = <1>;
>> 2362 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2363 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2364 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2365 clock-names = "core", "audio", "bus";
>> 2366 };
>> 2367
>> 2368 lpass_tlmm: pinctrl@33c0000{
2783 compatible = "qcom,sm 2369 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2370 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2371 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2372 gpio-controller;
2787 #gpio-cells = <2>; 2373 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2374 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2375
2790 clocks = <&q6afecc LP 2376 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2377 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2378 clock-names = "core", "audio";
2793 2379
2794 wsa_swr_active: wsa-s !! 2380 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 2381 clk {
2796 pins 2382 pins = "gpio10";
2797 funct 2383 function = "wsa_swr_clk";
2798 drive 2384 drive-strength = <2>;
2799 slew- 2385 slew-rate = <1>;
2800 bias- 2386 bias-disable;
2801 }; 2387 };
2802 2388
2803 data-pins { !! 2389 data {
2804 pins 2390 pins = "gpio11";
2805 funct 2391 function = "wsa_swr_data";
2806 drive 2392 drive-strength = <2>;
2807 slew- 2393 slew-rate = <1>;
2808 bias- 2394 bias-bus-hold;
>> 2395
2809 }; 2396 };
2810 }; 2397 };
2811 2398
2812 wsa_swr_sleep: wsa-sw !! 2399 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 2400 clk {
2814 pins 2401 pins = "gpio10";
2815 funct 2402 function = "wsa_swr_clk";
2816 drive 2403 drive-strength = <2>;
>> 2404 input-enable;
2817 bias- 2405 bias-pull-down;
2818 }; 2406 };
2819 2407
2820 data-pins { !! 2408 data {
2821 pins 2409 pins = "gpio11";
2822 funct 2410 function = "wsa_swr_data";
2823 drive 2411 drive-strength = <2>;
>> 2412 input-enable;
2824 bias- 2413 bias-pull-down;
>> 2414
2825 }; 2415 };
2826 }; 2416 };
2827 2417
2828 dmic01_active: dmic01 !! 2418 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 2419 clk {
2830 pins 2420 pins = "gpio6";
2831 funct 2421 function = "dmic1_clk";
2832 drive 2422 drive-strength = <8>;
2833 outpu 2423 output-high;
2834 }; 2424 };
2835 data-pins { !! 2425 data {
2836 pins 2426 pins = "gpio7";
2837 funct 2427 function = "dmic1_data";
2838 drive 2428 drive-strength = <8>;
>> 2429 input-enable;
2839 }; 2430 };
2840 }; 2431 };
2841 2432
2842 dmic01_sleep: dmic01- !! 2433 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 2434 clk {
2844 pins 2435 pins = "gpio6";
2845 funct 2436 function = "dmic1_clk";
2846 drive 2437 drive-strength = <2>;
2847 bias- 2438 bias-disable;
2848 outpu 2439 output-low;
2849 }; 2440 };
2850 2441
2851 data-pins { !! 2442 data {
2852 pins 2443 pins = "gpio7";
2853 funct 2444 function = "dmic1_data";
2854 drive 2445 drive-strength = <2>;
2855 bias- !! 2446 pull-down;
>> 2447 input-enable;
2856 }; 2448 };
2857 }; 2449 };
2858 2450
2859 rx_swr_active: rx-swr !! 2451 rx_swr_active: rx_swr-active-pins {
2860 clk-pins { !! 2452 clk {
2861 pins 2453 pins = "gpio3";
2862 funct 2454 function = "swr_rx_clk";
2863 drive 2455 drive-strength = <2>;
2864 slew- 2456 slew-rate = <1>;
2865 bias- 2457 bias-disable;
2866 }; 2458 };
2867 2459
2868 data-pins { !! 2460 data {
2869 pins 2461 pins = "gpio4", "gpio5";
2870 funct 2462 function = "swr_rx_data";
2871 drive 2463 drive-strength = <2>;
2872 slew- 2464 slew-rate = <1>;
2873 bias- 2465 bias-bus-hold;
2874 }; 2466 };
2875 }; 2467 };
2876 2468
2877 tx_swr_active: tx-swr !! 2469 tx_swr_active: tx_swr-active-pins {
2878 clk-pins { !! 2470 clk {
2879 pins 2471 pins = "gpio0";
2880 funct 2472 function = "swr_tx_clk";
2881 drive 2473 drive-strength = <2>;
2882 slew- 2474 slew-rate = <1>;
2883 bias- 2475 bias-disable;
2884 }; 2476 };
2885 2477
2886 data-pins { !! 2478 data {
2887 pins 2479 pins = "gpio1", "gpio2";
2888 funct 2480 function = "swr_tx_data";
2889 drive 2481 drive-strength = <2>;
2890 slew- 2482 slew-rate = <1>;
2891 bias- 2483 bias-bus-hold;
2892 }; 2484 };
2893 }; 2485 };
2894 2486
2895 tx_swr_sleep: tx-swr- !! 2487 tx_swr_sleep: tx_swr-sleep-pins {
2896 clk-pins { !! 2488 clk {
2897 pins 2489 pins = "gpio0";
2898 funct 2490 function = "swr_tx_clk";
2899 drive 2491 drive-strength = <2>;
>> 2492 input-enable;
2900 bias- 2493 bias-pull-down;
2901 }; 2494 };
2902 2495
2903 data1-pins { !! 2496 data1 {
2904 pins 2497 pins = "gpio1";
2905 funct 2498 function = "swr_tx_data";
2906 drive 2499 drive-strength = <2>;
>> 2500 input-enable;
2907 bias- 2501 bias-bus-hold;
2908 }; 2502 };
2909 2503
2910 data2-pins { !! 2504 data2 {
2911 pins 2505 pins = "gpio2";
2912 funct 2506 function = "swr_tx_data";
2913 drive 2507 drive-strength = <2>;
>> 2508 input-enable;
2914 bias- 2509 bias-pull-down;
2915 }; 2510 };
2916 }; 2511 };
2917 }; 2512 };
2918 2513
2919 gpu: gpu@3d00000 { 2514 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2515 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2516 "qcom,adreno";
2922 2517
2923 reg = <0 0x03d00000 0 2518 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2519 reg-names = "kgsl_3d0_reg_memory";
2925 2520
2926 interrupts = <GIC_SPI 2521 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2522
2928 iommus = <&adreno_smm 2523 iommus = <&adreno_smmu 0 0x401>;
2929 2524
2930 operating-points-v2 = 2525 operating-points-v2 = <&gpu_opp_table>;
2931 2526
2932 qcom,gmu = <&gmu>; 2527 qcom,gmu = <&gmu>;
2933 2528
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 2529 status = "disabled";
2939 2530
2940 zap-shader { 2531 zap-shader {
2941 memory-region 2532 memory-region = <&gpu_mem>;
2942 }; 2533 };
2943 2534
>> 2535 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 2536 gpu_opp_table: opp-table {
2945 compatible = 2537 compatible = "operating-points-v2";
2946 2538
2947 opp-670000000 2539 opp-670000000 {
2948 opp-h 2540 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2541 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 2542 };
2952 2543
2953 opp-587000000 2544 opp-587000000 {
2954 opp-h 2545 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2546 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 2547 };
2958 2548
2959 opp-525000000 2549 opp-525000000 {
2960 opp-h 2550 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2551 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 2552 };
2964 2553
2965 opp-490000000 2554 opp-490000000 {
2966 opp-h 2555 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2556 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 2557 };
2970 2558
2971 opp-441600000 2559 opp-441600000 {
2972 opp-h 2560 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2561 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 2562 };
2976 2563
2977 opp-400000000 2564 opp-400000000 {
2978 opp-h 2565 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2566 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 2567 };
2982 2568
2983 opp-305000000 2569 opp-305000000 {
2984 opp-h 2570 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2571 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 2572 };
2988 }; 2573 };
2989 }; 2574 };
2990 2575
2991 gmu: gmu@3d6a000 { 2576 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 2577 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2578
2994 reg = <0 0x03d6a000 0 2579 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2580 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2581 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2582 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2583 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2584
3000 interrupts = <GIC_SPI 2585 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2586 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2587 interrupt-names = "hfi", "gmu";
3003 2588
3004 clocks = <&gpucc GPU_ 2589 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2590 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2591 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2592 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2593 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2594 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2595
3011 power-domains = <&gpu 2596 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2597 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2598 power-domain-names = "cx", "gx";
3014 2599
3015 iommus = <&adreno_smm 2600 iommus = <&adreno_smmu 5 0x400>;
3016 2601
3017 operating-points-v2 = 2602 operating-points-v2 = <&gmu_opp_table>;
3018 2603
3019 status = "disabled"; 2604 status = "disabled";
3020 2605
3021 gmu_opp_table: opp-ta 2606 gmu_opp_table: opp-table {
3022 compatible = 2607 compatible = "operating-points-v2";
3023 2608
3024 opp-200000000 2609 opp-200000000 {
3025 opp-h 2610 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2611 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2612 };
3028 }; 2613 };
3029 }; 2614 };
3030 2615
3031 gpucc: clock-controller@3d900 2616 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2617 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2618 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2619 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2620 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2621 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2622 clock-names = "bi_tcxo",
3038 "gcc_gp 2623 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2624 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2625 #clock-cells = <1>;
3041 #reset-cells = <1>; 2626 #reset-cells = <1>;
3042 #power-domain-cells = 2627 #power-domain-cells = <1>;
3043 }; 2628 };
3044 2629
3045 adreno_smmu: iommu@3da0000 { 2630 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2631 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2632 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2633 #iommu-cells = <2>;
3050 #global-interrupts = 2634 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2635 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2636 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2637 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2638 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2639 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2640 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2641 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2642 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2643 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2644 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2645 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2646 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2647 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2648 clock-names = "ahb", "bus", "iface";
3065 2649
3066 power-domains = <&gpu 2650 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2651 };
3069 2652
3070 slpi: remoteproc@5c00000 { 2653 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2654 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2655 reg = <0 0x05c00000 0 0x4000>;
3073 2656
3074 interrupts-extended = !! 2657 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2658 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2659 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2660 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2661 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2662 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2663 "handover", "stop-ack";
3081 2664
3082 clocks = <&rpmhcc RPM 2665 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2666 clock-names = "xo";
3084 2667
3085 power-domains = <&rpm !! 2668 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2669 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2670 power-domain-names = "lcx", "lmx";
3088 2671
3089 memory-region = <&slp 2672 memory-region = <&slpi_mem>;
3090 2673
3091 qcom,qmp = <&aoss_qmp 2674 qcom,qmp = <&aoss_qmp>;
3092 2675
3093 qcom,smem-states = <& 2676 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2677 qcom,smem-state-names = "stop";
3095 2678
3096 status = "disabled"; 2679 status = "disabled";
3097 2680
3098 glink-edge { 2681 glink-edge {
3099 interrupts-ex 2682 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2683 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2684 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2685 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2686 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2687
3105 label = "slpi 2688 label = "slpi";
3106 qcom,remote-p 2689 qcom,remote-pid = <3>;
3107 2690
3108 fastrpc { 2691 fastrpc {
3109 compa 2692 compatible = "qcom,fastrpc";
3110 qcom, 2693 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2694 label = "sdsp";
3112 qcom, 2695 qcom,non-secure-domain;
3113 #addr 2696 #address-cells = <1>;
3114 #size 2697 #size-cells = <0>;
3115 2698
3116 compu 2699 compute-cb@1 {
3117 2700 compatible = "qcom,fastrpc-compute-cb";
3118 2701 reg = <1>;
3119 2702 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2703 };
3121 2704
3122 compu 2705 compute-cb@2 {
3123 2706 compatible = "qcom,fastrpc-compute-cb";
3124 2707 reg = <2>;
3125 2708 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2709 };
3127 2710
3128 compu 2711 compute-cb@3 {
3129 2712 compatible = "qcom,fastrpc-compute-cb";
3130 2713 reg = <3>;
3131 2714 iommus = <&apps_smmu 0x0543 0x0>;
3132 2715 /* note: shared-cb = <4> in downstream */
3133 }; 2716 };
3134 }; 2717 };
3135 }; 2718 };
3136 }; 2719 };
3137 2720
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 2721 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 2722 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 2723 reg = <0 0x08300000 0 0x10000>;
3777 2724
3778 interrupts-extended = !! 2725 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 2726 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 2727 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 2728 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 2729 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 2730 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 2731 "handover", "stop-ack";
3785 2732
3786 clocks = <&rpmhcc RPM 2733 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 2734 clock-names = "xo";
3788 2735
3789 power-domains = <&rpm !! 2736 power-domains = <&rpmhpd SM8250_CX>;
3790 2737
3791 memory-region = <&cds 2738 memory-region = <&cdsp_mem>;
3792 2739
3793 qcom,qmp = <&aoss_qmp 2740 qcom,qmp = <&aoss_qmp>;
3794 2741
3795 qcom,smem-states = <& 2742 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 2743 qcom,smem-state-names = "stop";
3797 2744
3798 status = "disabled"; 2745 status = "disabled";
3799 2746
3800 glink-edge { 2747 glink-edge {
3801 interrupts-ex 2748 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2749 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2750 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2751 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2752 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2753
3807 label = "cdsp 2754 label = "cdsp";
3808 qcom,remote-p 2755 qcom,remote-pid = <5>;
3809 2756
3810 fastrpc { 2757 fastrpc {
3811 compa 2758 compatible = "qcom,fastrpc";
3812 qcom, 2759 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2760 label = "cdsp";
3814 qcom, 2761 qcom,non-secure-domain;
3815 #addr 2762 #address-cells = <1>;
3816 #size 2763 #size-cells = <0>;
3817 2764
3818 compu 2765 compute-cb@1 {
3819 2766 compatible = "qcom,fastrpc-compute-cb";
3820 2767 reg = <1>;
3821 2768 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2769 };
3823 2770
3824 compu 2771 compute-cb@2 {
3825 2772 compatible = "qcom,fastrpc-compute-cb";
3826 2773 reg = <2>;
3827 2774 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2775 };
3829 2776
3830 compu 2777 compute-cb@3 {
3831 2778 compatible = "qcom,fastrpc-compute-cb";
3832 2779 reg = <3>;
3833 2780 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2781 };
3835 2782
3836 compu 2783 compute-cb@4 {
3837 2784 compatible = "qcom,fastrpc-compute-cb";
3838 2785 reg = <4>;
3839 2786 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2787 };
3841 2788
3842 compu 2789 compute-cb@5 {
3843 2790 compatible = "qcom,fastrpc-compute-cb";
3844 2791 reg = <5>;
3845 2792 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2793 };
3847 2794
3848 compu 2795 compute-cb@6 {
3849 2796 compatible = "qcom,fastrpc-compute-cb";
3850 2797 reg = <6>;
3851 2798 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2799 };
3853 2800
3854 compu 2801 compute-cb@7 {
3855 2802 compatible = "qcom,fastrpc-compute-cb";
3856 2803 reg = <7>;
3857 2804 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2805 };
3859 2806
3860 compu 2807 compute-cb@8 {
3861 2808 compatible = "qcom,fastrpc-compute-cb";
3862 2809 reg = <8>;
3863 2810 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2811 };
3865 2812
3866 /* no 2813 /* note: secure cb9 in downstream */
3867 }; 2814 };
3868 }; 2815 };
3869 }; 2816 };
3870 2817
>> 2818 sound: sound {
>> 2819 };
>> 2820
3871 usb_1_hsphy: phy@88e3000 { 2821 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2822 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2823 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2824 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2825 status = "disabled";
3876 #phy-cells = <0>; 2826 #phy-cells = <0>;
3877 2827
3878 clocks = <&rpmhcc RPM 2828 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2829 clock-names = "ref";
3880 2830
3881 resets = <&gcc GCC_QU 2831 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2832 };
3883 2833
3884 usb_2_hsphy: phy@88e4000 { 2834 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2835 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2836 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2837 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2838 status = "disabled";
3889 #phy-cells = <0>; 2839 #phy-cells = <0>;
3890 2840
3891 clocks = <&rpmhcc RPM 2841 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2842 clock-names = "ref";
3893 2843
3894 resets = <&gcc GCC_QU 2844 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2845 };
3896 2846
3897 usb_1_qmpphy: phy@88e8000 { !! 2847 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2848 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2849 reg = <0 0x088e9000 0 0x200>,
>> 2850 <0 0x088e8000 0 0x40>,
>> 2851 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2852 status = "disabled";
>> 2853 #address-cells = <2>;
>> 2854 #size-cells = <2>;
>> 2855 ranges;
3901 2856
3902 clocks = <&gcc GCC_US 2857 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2858 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2859 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2860 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2861
3911 resets = <&gcc GCC_US 2862 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2863 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2864 reset-names = "phy", "common";
3914 2865
3915 #clock-cells = <1>; !! 2866 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2867 reg = <0 0x088e9200 0 0x200>,
3917 !! 2868 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2869 <0 0x088e9c00 0 0x400>,
3919 !! 2870 <0 0x088e9600 0 0x200>,
3920 ports { !! 2871 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2872 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2873 #clock-cells = <0>;
3923 !! 2874 #phy-cells = <0>;
3924 port@0 { !! 2875 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2876 clock-names = "pipe0";
3926 usb_1 !! 2877 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2878 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2879
3940 usb_1 !! 2880 dp_phy: dp-phy@88ea200 {
3941 }; !! 2881 reg = <0 0x088ea200 0 0x200>,
>> 2882 <0 0x088ea400 0 0x200>,
>> 2883 <0 0x088eac00 0 0x400>,
>> 2884 <0 0x088ea600 0 0x200>,
>> 2885 <0 0x088ea800 0 0x200>,
>> 2886 <0 0x088eaa00 0 0x100>;
>> 2887 #phy-cells = <0>;
>> 2888 #clock-cells = <1>;
>> 2889 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 2890 clock-names = "pipe0";
>> 2891 clock-output-names = "usb3_phy_pipe_clk_src";
3942 }; 2892 };
3943 }; 2893 };
3944 2894
3945 usb_2_qmpphy: phy@88eb000 { 2895 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2896 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2897 reg = <0 0x088eb000 0 0x200>;
>> 2898 status = "disabled";
>> 2899 #address-cells = <2>;
>> 2900 #size-cells = <2>;
>> 2901 ranges;
3948 2902
3949 clocks = <&gcc GCC_US 2903 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2904 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2905 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2906 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2907 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2908
3961 resets = <&gcc GCC_US !! 2909 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2910 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2911 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2912
3966 status = "disabled"; !! 2913 usb_2_ssphy: phy@88eb200 {
>> 2914 reg = <0 0x088eb200 0 0x200>,
>> 2915 <0 0x088eb400 0 0x200>,
>> 2916 <0 0x088eb800 0 0x800>;
>> 2917 #clock-cells = <0>;
>> 2918 #phy-cells = <0>;
>> 2919 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2920 clock-names = "pipe0";
>> 2921 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2922 };
3967 }; 2923 };
3968 2924
3969 sdhc_2: mmc@8804000 { !! 2925 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2926 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2927 reg = <0 0x08804000 0 0x1000>;
3972 2928
3973 interrupts = <GIC_SPI 2929 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2930 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2931 interrupt-names = "hc_irq", "pwr_irq";
3976 2932
3977 clocks = <&gcc GCC_SD 2933 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2934 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2935 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2936 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2937 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2938 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2939 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2940 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2941 operating-points-v2 = <&sdhc2_opp_table>;
3986 2942
3987 status = "disabled"; 2943 status = "disabled";
3988 2944
3989 sdhc2_opp_table: opp- !! 2945 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2946 compatible = "operating-points-v2";
3991 2947
3992 opp-19200000 2948 opp-19200000 {
3993 opp-h 2949 opp-hz = /bits/ 64 <19200000>;
3994 requi 2950 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2951 };
3996 2952
3997 opp-50000000 2953 opp-50000000 {
3998 opp-h 2954 opp-hz = /bits/ 64 <50000000>;
3999 requi 2955 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2956 };
4001 2957
4002 opp-100000000 2958 opp-100000000 {
4003 opp-h 2959 opp-hz = /bits/ 64 <100000000>;
4004 requi 2960 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2961 };
4006 2962
4007 opp-202000000 2963 opp-202000000 {
4008 opp-h 2964 opp-hz = /bits/ 64 <202000000>;
4009 requi 2965 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2966 };
4011 }; 2967 };
4012 }; 2968 };
4013 2969
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2970 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2971 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2972 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2973 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2974 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2975 };
4142 2976
4143 gem_noc: interconnect@9100000 2977 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2978 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2979 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2980 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2981 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2982 };
4149 2983
4150 npu_noc: interconnect@9990000 2984 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2985 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2986 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2987 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2988 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2989 };
4156 2990
4157 usb_1: usb@a6f8800 { 2991 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2992 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2993 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2994 status = "disabled";
4161 #address-cells = <2>; 2995 #address-cells = <2>;
4162 #size-cells = <2>; 2996 #size-cells = <2>;
4163 ranges; 2997 ranges;
4164 dma-ranges; 2998 dma-ranges;
4165 2999
4166 clocks = <&gcc GCC_CF 3000 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 3001 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 3002 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US <<
4170 <&gcc GCC_US 3003 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
>> 3004 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4171 <&gcc GCC_US 3005 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no !! 3006 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4173 "core", !! 3007 "sleep", "xo";
4174 "iface" <<
4175 "sleep" <<
4176 "mock_u <<
4177 "xo"; <<
4178 3008
4179 assigned-clocks = <&g 3009 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 3010 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 3011 assigned-clock-rates = <19200000>, <200000000>;
4182 3012
4183 interrupts-extended = !! 3013 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 3014 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 3015 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 3016 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 3017 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 3018 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 3019
4194 power-domains = <&gcc 3020 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 3021
4197 resets = <&gcc GCC_US 3022 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 3023
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 3024 usb_1_dwc3: usb@a600000 {
4204 compatible = 3025 compatible = "snps,dwc3";
4205 reg = <0 0x0a 3026 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 3027 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 3028 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 3029 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 3030 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 3031 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 3032 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 3033 };
4233 }; 3034 };
4234 3035
4235 system-cache-controller@92000 3036 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 3037 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 3038 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 3039 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 3040 };
4243 3041
4244 usb_2: usb@a8f8800 { 3042 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 3043 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 3044 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 3045 status = "disabled";
4248 #address-cells = <2>; 3046 #address-cells = <2>;
4249 #size-cells = <2>; 3047 #size-cells = <2>;
4250 ranges; 3048 ranges;
4251 dma-ranges; 3049 dma-ranges;
4252 3050
4253 clocks = <&gcc GCC_CF 3051 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 3052 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 3053 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US <<
4257 <&gcc GCC_US 3054 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
>> 3055 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4258 <&gcc GCC_US 3056 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no !! 3057 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
4260 "core", !! 3058 "sleep", "xo";
4261 "iface" <<
4262 "sleep" <<
4263 "mock_u <<
4264 "xo"; <<
4265 3059
4266 assigned-clocks = <&g 3060 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 3061 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 3062 assigned-clock-rates = <19200000>, <200000000>;
4269 3063
4270 interrupts-extended = !! 3064 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 3065 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 3066 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 3067 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 3068 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 3069 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 3070
4281 power-domains = <&gcc 3071 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 3072
4284 resets = <&gcc GCC_US 3073 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 3074
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 3075 usb_2_dwc3: usb@a800000 {
4291 compatible = 3076 compatible = "snps,dwc3";
4292 reg = <0 0x0a 3077 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 3078 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 3079 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 3080 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 3081 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 3082 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 3083 phy-names = "usb2-phy", "usb3-phy";
4299 }; 3084 };
4300 }; 3085 };
4301 3086
4302 venus: video-codec@aa00000 { 3087 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 3088 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 3089 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 3090 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 3091 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 3092 <&videocc MVS0_GDSC>,
4308 <&rpm !! 3093 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 3094 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 3095 operating-points-v2 = <&venus_opp_table>;
4311 3096
4312 clocks = <&gcc GCC_VI 3097 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 3098 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 3099 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 3100 clock-names = "iface", "core", "vcodec0_core";
4316 3101
4317 interconnects = <&gem !! 3102 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 3103 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 3104 interconnect-names = "cpu-cfg", "video-mem";
4320 3105
4321 iommus = <&apps_smmu 3106 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 3107 memory-region = <&video_mem>;
4323 3108
4324 resets = <&gcc GCC_VI 3109 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 3110 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 3111 reset-names = "bus", "core";
4327 3112
4328 status = "disabled"; 3113 status = "disabled";
4329 3114
4330 video-decoder { 3115 video-decoder {
4331 compatible = 3116 compatible = "venus-decoder";
4332 }; 3117 };
4333 3118
4334 video-encoder { 3119 video-encoder {
4335 compatible = 3120 compatible = "venus-encoder";
4336 }; 3121 };
4337 3122
4338 venus_opp_table: opp- !! 3123 venus_opp_table: venus-opp-table {
4339 compatible = 3124 compatible = "operating-points-v2";
4340 3125
4341 opp-720000000 3126 opp-720000000 {
4342 opp-h 3127 opp-hz = /bits/ 64 <720000000>;
4343 requi 3128 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3129 };
4345 3130
4346 opp-101400000 3131 opp-1014000000 {
4347 opp-h 3132 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3133 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3134 };
4350 3135
4351 opp-109800000 3136 opp-1098000000 {
4352 opp-h 3137 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3138 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3139 };
4355 3140
4356 opp-133200000 3141 opp-1332000000 {
4357 opp-h 3142 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3143 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3144 };
4360 }; 3145 };
4361 }; 3146 };
4362 3147
4363 videocc: clock-controller@abf 3148 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 3149 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 3150 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 3151 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 3152 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 3153 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 3154 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 3155 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 3156 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 3157 #clock-cells = <1>;
4373 #reset-cells = <1>; 3158 #reset-cells = <1>;
4374 #power-domain-cells = 3159 #power-domain-cells = <1>;
4375 }; 3160 };
4376 3161
4377 cci0: cci@ac4f000 { !! 3162 mdss: mdss@ae00000 {
4378 compatible = "qcom,sm <<
4379 #address-cells = <1>; <<
4380 #size-cells = <0>; <<
4381 <<
4382 reg = <0 0x0ac4f000 0 <<
4383 interrupts = <GIC_SPI <<
4384 power-domains = <&cam <<
4385 <<
4386 clocks = <&camcc CAM_ <<
4387 <&camcc CAM_ <<
4388 <&camcc CAM_ <<
4389 <&camcc CAM_ <<
4390 <&camcc CAM_ <<
4391 clock-names = "camnoc <<
4392 "slow_a <<
4393 "cpas_a <<
4394 "cci", <<
4395 "cci_sr <<
4396 <<
4397 pinctrl-0 = <&cci0_de <<
4398 pinctrl-1 = <&cci0_sl <<
4399 pinctrl-names = "defa <<
4400 <<
4401 status = "disabled"; <<
4402 <<
4403 cci0_i2c0: i2c-bus@0 <<
4404 reg = <0>; <<
4405 clock-frequen <<
4406 #address-cell <<
4407 #size-cells = <<
4408 }; <<
4409 <<
4410 cci0_i2c1: i2c-bus@1 <<
4411 reg = <1>; <<
4412 clock-frequen <<
4413 #address-cell <<
4414 #size-cells = <<
4415 }; <<
4416 }; <<
4417 <<
4418 cci1: cci@ac50000 { <<
4419 compatible = "qcom,sm <<
4420 #address-cells = <1>; <<
4421 #size-cells = <0>; <<
4422 <<
4423 reg = <0 0x0ac50000 0 <<
4424 interrupts = <GIC_SPI <<
4425 power-domains = <&cam <<
4426 <<
4427 clocks = <&camcc CAM_ <<
4428 <&camcc CAM_ <<
4429 <&camcc CAM_ <<
4430 <&camcc CAM_ <<
4431 <&camcc CAM_ <<
4432 clock-names = "camnoc <<
4433 "slow_a <<
4434 "cpas_a <<
4435 "cci", <<
4436 "cci_sr <<
4437 <<
4438 pinctrl-0 = <&cci1_de <<
4439 pinctrl-1 = <&cci1_sl <<
4440 pinctrl-names = "defa <<
4441 <<
4442 status = "disabled"; <<
4443 <<
4444 cci1_i2c0: i2c-bus@0 <<
4445 reg = <0>; <<
4446 clock-frequen <<
4447 #address-cell <<
4448 #size-cells = <<
4449 }; <<
4450 <<
4451 cci1_i2c1: i2c-bus@1 <<
4452 reg = <1>; <<
4453 clock-frequen <<
4454 #address-cell <<
4455 #size-cells = <<
4456 }; <<
4457 }; <<
4458 <<
4459 camss: camss@ac6a000 { <<
4460 compatible = "qcom,sm <<
4461 status = "disabled"; <<
4462 <<
4463 reg = <0 0x0ac6a000 0 <<
4464 <0 0x0ac6c000 0 <<
4465 <0 0x0ac6e000 0 <<
4466 <0 0x0ac70000 0 <<
4467 <0 0x0ac72000 0 <<
4468 <0 0x0ac74000 0 <<
4469 <0 0x0acb4000 0 <<
4470 <0 0x0acc3000 0 <<
4471 <0 0x0acd9000 0 <<
4472 <0 0x0acdb200 0 <<
4473 reg-names = "csiphy0" <<
4474 "csiphy1" <<
4475 "csiphy2" <<
4476 "csiphy3" <<
4477 "csiphy4" <<
4478 "csiphy5" <<
4479 "vfe0", <<
4480 "vfe1", <<
4481 "vfe_lite <<
4482 "vfe_lite <<
4483 <<
4484 interrupts = <GIC_SPI <<
4485 <GIC_SPI <<
4486 <GIC_SPI <<
4487 <GIC_SPI <<
4488 <GIC_SPI <<
4489 <GIC_SPI <<
4490 <GIC_SPI <<
4491 <GIC_SPI <<
4492 <GIC_SPI <<
4493 <GIC_SPI <<
4494 <GIC_SPI <<
4495 <GIC_SPI <<
4496 <GIC_SPI <<
4497 <GIC_SPI <<
4498 interrupt-names = "cs <<
4499 "cs <<
4500 "cs <<
4501 "cs <<
4502 "cs <<
4503 "cs <<
4504 "cs <<
4505 "cs <<
4506 "cs <<
4507 "cs <<
4508 "vf <<
4509 "vf <<
4510 "vf <<
4511 "vf <<
4512 <<
4513 power-domains = <&cam <<
4514 <&cam <<
4515 <&cam <<
4516 <<
4517 clocks = <&gcc GCC_CA <<
4518 <&gcc GCC_CA <<
4519 <&gcc GCC_CA <<
4520 <&camcc CAM_ <<
4521 <&camcc CAM_ <<
4522 <&camcc CAM_ <<
4523 <&camcc CAM_ <<
4524 <&camcc CAM_ <<
4525 <&camcc CAM_ <<
4526 <&camcc CAM_ <<
4527 <&camcc CAM_ <<
4528 <&camcc CAM_ <<
4529 <&camcc CAM_ <<
4530 <&camcc CAM_ <<
4531 <&camcc CAM_ <<
4532 <&camcc CAM_ <<
4533 <&camcc CAM_ <<
4534 <&camcc CAM_ <<
4535 <&camcc CAM_ <<
4536 <&camcc CAM_ <<
4537 <&camcc CAM_ <<
4538 <&camcc CAM_ <<
4539 <&camcc CAM_ <<
4540 <&camcc CAM_ <<
4541 <&camcc CAM_ <<
4542 <&camcc CAM_ <<
4543 <&camcc CAM_ <<
4544 <&camcc CAM_ <<
4545 <&camcc CAM_ <<
4546 <&camcc CAM_ <<
4547 <&camcc CAM_ <<
4548 <&camcc CAM_ <<
4549 <&camcc CAM_ <<
4550 <&camcc CAM_ <<
4551 <&camcc CAM_ <<
4552 <&camcc CAM_ <<
4553 <&camcc CAM_ <<
4554 <<
4555 clock-names = "cam_ah <<
4556 "cam_hf <<
4557 "cam_sf <<
4558 "camnoc <<
4559 "camnoc <<
4560 "core_a <<
4561 "cpas_a <<
4562 "csiphy <<
4563 "csiphy <<
4564 "csiphy <<
4565 "csiphy <<
4566 "csiphy <<
4567 "csiphy <<
4568 "csiphy <<
4569 "csiphy <<
4570 "csiphy <<
4571 "csiphy <<
4572 "csiphy <<
4573 "csiphy <<
4574 "slow_a <<
4575 "vfe0_a <<
4576 "vfe0_a <<
4577 "vfe0", <<
4578 "vfe0_c <<
4579 "vfe0_c <<
4580 "vfe0_a <<
4581 "vfe1_a <<
4582 "vfe1_a <<
4583 "vfe1", <<
4584 "vfe1_c <<
4585 "vfe1_c <<
4586 "vfe1_a <<
4587 "vfe_li <<
4588 "vfe_li <<
4589 "vfe_li <<
4590 "vfe_li <<
4591 "vfe_li <<
4592 <<
4593 iommus = <&apps_smmu <<
4594 <&apps_smmu <<
4595 <&apps_smmu <<
4596 <&apps_smmu <<
4597 <&apps_smmu <<
4598 <&apps_smmu <<
4599 <&apps_smmu <<
4600 <&apps_smmu <<
4601 <<
4602 interconnects = <&gem <<
4603 <&mms <<
4604 <&mms <<
4605 <&mms <<
4606 interconnect-names = <<
4607 <<
4608 <<
4609 <<
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; <<
4640 <<
4641 camcc: clock-controller@ad000 <<
4642 compatible = "qcom,sm <<
4643 reg = <0 0x0ad00000 0 <<
4644 clocks = <&gcc GCC_CA <<
4645 <&rpmhcc RPM <<
4646 <&rpmhcc RPM <<
4647 <&sleep_clk> <<
4648 clock-names = "iface" <<
4649 power-domains = <&rpm <<
4650 required-opps = <&rpm <<
4651 status = "disabled"; <<
4652 #clock-cells = <1>; <<
4653 #reset-cells = <1>; <<
4654 #power-domain-cells = <<
4655 }; <<
4656 <<
4657 mdss: display-subsystem@ae000 <<
4658 compatible = "qcom,sm 3163 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 3164 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 3165 reg-names = "mdss";
4661 3166
4662 interconnects = <&mms !! 3167 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 3168 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 3169 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 3170
4666 power-domains = <&dis 3171 power-domains = <&dispcc MDSS_GDSC>;
4667 3172
4668 clocks = <&dispcc DIS 3173 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 3174 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 3175 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 3176 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 3177 clock-names = "iface", "bus", "nrt_bus", "core";
4673 3178
>> 3179 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 3180 assigned-clock-rates = <460000000>;
>> 3181
4674 interrupts = <GIC_SPI 3182 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 3183 interrupt-controller;
4676 #interrupt-cells = <1 3184 #interrupt-cells = <1>;
4677 3185
4678 iommus = <&apps_smmu 3186 iommus = <&apps_smmu 0x820 0x402>;
4679 3187
4680 status = "disabled"; 3188 status = "disabled";
4681 3189
4682 #address-cells = <2>; 3190 #address-cells = <2>;
4683 #size-cells = <2>; 3191 #size-cells = <2>;
4684 ranges; 3192 ranges;
4685 3193
4686 mdss_mdp: display-con !! 3194 mdss_mdp: mdp@ae01000 {
4687 compatible = 3195 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 3196 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 3197 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 3198 reg-names = "mdp", "vbif";
4691 3199
4692 clocks = <&di 3200 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 3201 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 3202 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 3203 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 3204 clock-names = "iface", "bus", "core", "vsync";
4697 3205
4698 assigned-cloc !! 3206 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 3207 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 3208 assigned-clock-rates = <460000000>,
>> 3209 <19200000>;
4700 3210
4701 operating-poi 3211 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 3212 power-domains = <&rpmhpd SM8250_MMCX>;
4703 3213
4704 interrupt-par 3214 interrupt-parent = <&mdss>;
4705 interrupts = !! 3215 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
4706 3216
4707 ports { 3217 ports {
4708 #addr 3218 #address-cells = <1>;
4709 #size 3219 #size-cells = <0>;
4710 3220
4711 port@ 3221 port@0 {
4712 3222 reg = <0>;
4713 3223 dpu_intf1_out: endpoint {
4714 !! 3224 remote-endpoint = <&dsi0_in>;
4715 3225 };
4716 }; 3226 };
4717 3227
4718 port@ 3228 port@1 {
4719 3229 reg = <1>;
4720 3230 dpu_intf2_out: endpoint {
4721 !! 3231 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 3232 };
4731 }; 3233 };
4732 }; 3234 };
4733 3235
4734 mdp_opp_table !! 3236 mdp_opp_table: mdp-opp-table {
4735 compa 3237 compatible = "operating-points-v2";
4736 3238
4737 opp-2 3239 opp-200000000 {
4738 3240 opp-hz = /bits/ 64 <200000000>;
4739 3241 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 3242 };
4741 3243
4742 opp-3 3244 opp-300000000 {
4743 3245 opp-hz = /bits/ 64 <300000000>;
4744 3246 required-opps = <&rpmhpd_opp_svs>;
4745 }; 3247 };
4746 3248
4747 opp-3 3249 opp-345000000 {
4748 3250 opp-hz = /bits/ 64 <345000000>;
4749 3251 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 3252 };
4751 3253
4752 opp-4 3254 opp-460000000 {
4753 3255 opp-hz = /bits/ 64 <460000000>;
4754 3256 required-opps = <&rpmhpd_opp_nom>;
4755 }; 3257 };
4756 }; 3258 };
4757 }; 3259 };
4758 3260
4759 mdss_dp: displayport- !! 3261 dsi0: dsi@ae94000 {
4760 compatible = !! 3262 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 3263 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 3264 reg-names = "dsi_ctrl";
4843 3265
4844 interrupt-par 3266 interrupt-parent = <&mdss>;
4845 interrupts = !! 3267 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
4846 3268
4847 clocks = <&di 3269 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 3270 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 3271 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 3272 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 3273 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 3274 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 3275 clock-names = "byte",
4854 3276 "byte_intf",
4855 3277 "pixel",
4856 3278 "core",
4857 3279 "iface",
4858 3280 "bus";
4859 3281
4860 assigned-cloc 3282 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 3283 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 3284
4863 operating-poi 3285 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 3286 power-domains = <&rpmhpd SM8250_MMCX>;
4865 3287
4866 phys = <&mdss !! 3288 phys = <&dsi0_phy>;
>> 3289 phy-names = "dsi";
4867 3290
4868 status = "dis 3291 status = "disabled";
4869 3292
4870 #address-cell 3293 #address-cells = <1>;
4871 #size-cells = 3294 #size-cells = <0>;
4872 3295
4873 ports { 3296 ports {
4874 #addr 3297 #address-cells = <1>;
4875 #size 3298 #size-cells = <0>;
4876 3299
4877 port@ 3300 port@0 {
4878 3301 reg = <0>;
4879 !! 3302 dsi0_in: endpoint {
4880 3303 remote-endpoint = <&dpu_intf1_out>;
4881 3304 };
4882 }; 3305 };
4883 3306
4884 port@ 3307 port@1 {
4885 3308 reg = <1>;
4886 !! 3309 dsi0_out: endpoint {
4887 3310 };
4888 }; 3311 };
4889 }; 3312 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 3313 };
4910 3314
4911 mdss_dsi0_phy: phy@ae !! 3315 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 3316 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 3317 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 3318 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 3319 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 3320 reg-names = "dsi_phy",
4917 " 3321 "dsi_phy_lane",
4918 " 3322 "dsi_pll";
4919 3323
4920 #clock-cells 3324 #clock-cells = <1>;
4921 #phy-cells = 3325 #phy-cells = <0>;
4922 3326
4923 clocks = <&di 3327 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 3328 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 3329 clock-names = "iface", "ref";
4926 3330
4927 status = "dis 3331 status = "disabled";
4928 }; 3332 };
4929 3333
4930 mdss_dsi1: dsi@ae9600 !! 3334 dsi1: dsi@ae96000 {
4931 compatible = !! 3335 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 3336 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 3337 reg-names = "dsi_ctrl";
4935 3338
4936 interrupt-par 3339 interrupt-parent = <&mdss>;
4937 interrupts = !! 3340 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
4938 3341
4939 clocks = <&di 3342 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 3343 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 3344 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 3345 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 3346 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 3347 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 3348 clock-names = "byte",
4946 3349 "byte_intf",
4947 3350 "pixel",
4948 3351 "core",
4949 3352 "iface",
4950 3353 "bus";
4951 3354
4952 assigned-cloc 3355 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 3356 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 3357
4955 operating-poi 3358 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 3359 power-domains = <&rpmhpd SM8250_MMCX>;
4957 3360
4958 phys = <&mdss !! 3361 phys = <&dsi1_phy>;
>> 3362 phy-names = "dsi";
4959 3363
4960 status = "dis 3364 status = "disabled";
4961 3365
4962 #address-cell 3366 #address-cells = <1>;
4963 #size-cells = 3367 #size-cells = <0>;
4964 3368
4965 ports { 3369 ports {
4966 #addr 3370 #address-cells = <1>;
4967 #size 3371 #size-cells = <0>;
4968 3372
4969 port@ 3373 port@0 {
4970 3374 reg = <0>;
4971 !! 3375 dsi1_in: endpoint {
4972 3376 remote-endpoint = <&dpu_intf2_out>;
4973 3377 };
4974 }; 3378 };
4975 3379
4976 port@ 3380 port@1 {
4977 3381 reg = <1>;
4978 !! 3382 dsi1_out: endpoint {
4979 3383 };
4980 }; 3384 };
4981 }; 3385 };
4982 }; 3386 };
4983 3387
4984 mdss_dsi1_phy: phy@ae !! 3388 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 3389 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 3390 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 3391 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 3392 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 3393 reg-names = "dsi_phy",
4990 " 3394 "dsi_phy_lane",
4991 " 3395 "dsi_pll";
4992 3396
4993 #clock-cells 3397 #clock-cells = <1>;
4994 #phy-cells = 3398 #phy-cells = <0>;
4995 3399
4996 clocks = <&di 3400 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 3401 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 3402 clock-names = "iface", "ref";
4999 3403
5000 status = "dis 3404 status = "disabled";
>> 3405
>> 3406 dsi_opp_table: dsi-opp-table {
>> 3407 compatible = "operating-points-v2";
>> 3408
>> 3409 opp-187500000 {
>> 3410 opp-hz = /bits/ 64 <187500000>;
>> 3411 required-opps = <&rpmhpd_opp_low_svs>;
>> 3412 };
>> 3413
>> 3414 opp-300000000 {
>> 3415 opp-hz = /bits/ 64 <300000000>;
>> 3416 required-opps = <&rpmhpd_opp_svs>;
>> 3417 };
>> 3418
>> 3419 opp-358000000 {
>> 3420 opp-hz = /bits/ 64 <358000000>;
>> 3421 required-opps = <&rpmhpd_opp_svs_l1>;
>> 3422 };
>> 3423 };
5001 }; 3424 };
5002 }; 3425 };
5003 3426
5004 dispcc: clock-controller@af00 3427 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 3428 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 3429 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 3430 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 3431 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 3432 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 3433 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 3434 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 3435 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 3436 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 3437 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 3438 <&dp_phy 1>;
5016 clock-names = "bi_tcx 3439 clock-names = "bi_tcxo",
5017 "dsi0_p 3440 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 3441 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 3442 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 3443 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 3444 "dp_phy_pll_link_clk",
5022 "dp_phy 3445 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 3446 #clock-cells = <1>;
5024 #reset-cells = <1>; 3447 #reset-cells = <1>;
5025 #power-domain-cells = 3448 #power-domain-cells = <1>;
5026 }; 3449 };
5027 3450
5028 pdc: interrupt-controller@b22 3451 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 3452 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 3453 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 3454 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 3455 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 3456 #interrupt-cells = <2>;
5034 interrupt-parent = <& 3457 interrupt-parent = <&intc>;
5035 interrupt-controller; 3458 interrupt-controller;
5036 }; 3459 };
5037 3460
5038 tsens0: thermal-sensor@c26300 3461 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 3462 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 3463 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 3464 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 3465 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 3466 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 3467 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 3468 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 3469 #thermal-sensor-cells = <1>;
5047 }; 3470 };
5048 3471
5049 tsens1: thermal-sensor@c26500 3472 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 3473 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 3474 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 3475 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 3476 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 3477 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 3478 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 3479 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 3480 #thermal-sensor-cells = <1>;
5058 }; 3481 };
5059 3482
5060 aoss_qmp: power-management@c3 !! 3483 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm 3484 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 3485 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 3486 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 3487 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 3488 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 3489 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 3490 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 3491
5069 #clock-cells = <0>; 3492 #clock-cells = <0>;
5070 }; 3493 };
5071 3494
5072 sram@c3f0000 { 3495 sram@c3f0000 {
5073 compatible = "qcom,rp 3496 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 3497 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 3498 };
5076 3499
5077 spmi_bus: spmi@c440000 { 3500 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 3501 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 3502 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 3503 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 3504 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 3505 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 3506 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 3507 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 3508 interrupt-names = "periph_irq";
5086 interrupts-extended = 3509 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 3510 qcom,ee = <0>;
5088 qcom,channel = <0>; 3511 qcom,channel = <0>;
5089 #address-cells = <2>; 3512 #address-cells = <2>;
5090 #size-cells = <0>; 3513 #size-cells = <0>;
5091 interrupt-controller; 3514 interrupt-controller;
5092 #interrupt-cells = <4 3515 #interrupt-cells = <4>;
5093 }; 3516 };
5094 3517
5095 tlmm: pinctrl@f100000 { 3518 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 3519 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 3520 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 3521 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 3522 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 3523 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 3524 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 3525 gpio-controller;
5103 #gpio-cells = <2>; 3526 #gpio-cells = <2>;
5104 interrupt-controller; 3527 interrupt-controller;
5105 #interrupt-cells = <2 3528 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 3529 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 3530 wakeup-parent = <&pdc>;
5108 3531
5109 cam2_default: cam2-de !! 3532 pri_mi2s_active: pri-mi2s-active {
5110 rst-pins { !! 3533 sclk {
5111 pins !! 3534 pins = "gpio138";
5112 funct !! 3535 function = "mi2s0_sck";
5113 drive !! 3536 drive-strength = <8>;
5114 bias- 3537 bias-disable;
5115 }; 3538 };
5116 3539
5117 mclk-pins { !! 3540 ws {
5118 pins !! 3541 pins = "gpio141";
5119 funct !! 3542 function = "mi2s0_ws";
5120 drive !! 3543 drive-strength = <8>;
>> 3544 output-high;
>> 3545 };
>> 3546
>> 3547 data0 {
>> 3548 pins = "gpio139";
>> 3549 function = "mi2s0_data0";
>> 3550 drive-strength = <8>;
5121 bias- 3551 bias-disable;
>> 3552 output-high;
>> 3553 };
>> 3554
>> 3555 data1 {
>> 3556 pins = "gpio140";
>> 3557 function = "mi2s0_data1";
>> 3558 drive-strength = <8>;
>> 3559 output-high;
5122 }; 3560 };
5123 }; 3561 };
5124 3562
5125 cam2_suspend: cam2-su !! 3563 qup_i2c0_default: qup-i2c0-default {
5126 rst-pins { !! 3564 mux {
5127 pins !! 3565 pins = "gpio28", "gpio29";
5128 funct !! 3566 function = "qup0";
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; 3567 };
5133 3568
5134 mclk-pins { !! 3569 config {
5135 pins !! 3570 pins = "gpio28", "gpio29";
5136 funct <<
5137 drive 3571 drive-strength = <2>;
5138 bias- 3572 bias-disable;
5139 }; 3573 };
5140 }; 3574 };
5141 3575
5142 cci0_default: cci0-de !! 3576 qup_i2c1_default: qup-i2c1-default {
5143 cci0_i2c0_def !! 3577 pinmux {
5144 /* SD !! 3578 pins = "gpio4", "gpio5";
5145 pins !! 3579 function = "qup1";
5146 funct <<
5147 <<
5148 bias- <<
5149 drive <<
5150 }; 3580 };
5151 3581
5152 cci0_i2c1_def !! 3582 config {
5153 /* SD !! 3583 pins = "gpio4", "gpio5";
5154 pins !! 3584 drive-strength = <2>;
5155 funct !! 3585 bias-disable;
5156 <<
5157 bias- <<
5158 drive <<
5159 }; 3586 };
5160 }; 3587 };
5161 3588
5162 cci0_sleep: cci0-slee !! 3589 qup_i2c2_default: qup-i2c2-default {
5163 cci0_i2c0_sle !! 3590 mux {
5164 /* SD !! 3591 pins = "gpio115", "gpio116";
5165 pins !! 3592 function = "qup2";
5166 funct <<
5167 <<
5168 drive <<
5169 bias- <<
5170 }; 3593 };
5171 3594
5172 cci0_i2c1_sle !! 3595 config {
5173 /* SD !! 3596 pins = "gpio115", "gpio116";
5174 pins !! 3597 drive-strength = <2>;
5175 funct !! 3598 bias-disable;
5176 <<
5177 drive <<
5178 bias- <<
5179 }; 3599 };
5180 }; 3600 };
5181 3601
5182 cci1_default: cci1-de !! 3602 qup_i2c3_default: qup-i2c3-default {
5183 cci1_i2c0_def !! 3603 mux {
5184 /* SD !! 3604 pins = "gpio119", "gpio120";
5185 pins !! 3605 function = "qup3";
5186 funct !! 3606 };
5187 3607
5188 bias- !! 3608 config {
5189 drive !! 3609 pins = "gpio119", "gpio120";
>> 3610 drive-strength = <2>;
>> 3611 bias-disable;
5190 }; 3612 };
>> 3613 };
5191 3614
5192 cci1_i2c1_def !! 3615 qup_i2c4_default: qup-i2c4-default {
5193 /* SD !! 3616 mux {
5194 pins !! 3617 pins = "gpio8", "gpio9";
5195 funct !! 3618 function = "qup4";
>> 3619 };
5196 3620
5197 bias- !! 3621 config {
5198 drive !! 3622 pins = "gpio8", "gpio9";
>> 3623 drive-strength = <2>;
>> 3624 bias-disable;
5199 }; 3625 };
5200 }; 3626 };
5201 3627
5202 cci1_sleep: cci1-slee !! 3628 qup_i2c5_default: qup-i2c5-default {
5203 cci1_i2c0_sle !! 3629 mux {
5204 /* SD !! 3630 pins = "gpio12", "gpio13";
5205 pins !! 3631 function = "qup5";
5206 funct !! 3632 };
5207 3633
5208 bias- !! 3634 config {
5209 drive !! 3635 pins = "gpio12", "gpio13";
>> 3636 drive-strength = <2>;
>> 3637 bias-disable;
5210 }; 3638 };
>> 3639 };
5211 3640
5212 cci1_i2c1_sle !! 3641 qup_i2c6_default: qup-i2c6-default {
5213 /* SD !! 3642 mux {
5214 pins !! 3643 pins = "gpio16", "gpio17";
5215 funct !! 3644 function = "qup6";
>> 3645 };
5216 3646
5217 bias- !! 3647 config {
5218 drive !! 3648 pins = "gpio16", "gpio17";
>> 3649 drive-strength = <2>;
>> 3650 bias-disable;
5219 }; 3651 };
5220 }; 3652 };
5221 3653
5222 pri_mi2s_active: pri- !! 3654 qup_i2c7_default: qup-i2c7-default {
5223 sclk-pins { !! 3655 mux {
5224 pins !! 3656 pins = "gpio20", "gpio21";
5225 funct !! 3657 function = "qup7";
5226 drive !! 3658 };
>> 3659
>> 3660 config {
>> 3661 pins = "gpio20", "gpio21";
>> 3662 drive-strength = <2>;
5227 bias- 3663 bias-disable;
5228 }; 3664 };
>> 3665 };
5229 3666
5230 ws-pins { !! 3667 qup_i2c8_default: qup-i2c8-default {
5231 pins !! 3668 mux {
5232 funct !! 3669 pins = "gpio24", "gpio25";
5233 drive !! 3670 function = "qup8";
5234 outpu <<
5235 }; 3671 };
5236 3672
5237 data0-pins { !! 3673 config {
5238 pins !! 3674 pins = "gpio24", "gpio25";
5239 funct !! 3675 drive-strength = <2>;
5240 drive <<
5241 bias- 3676 bias-disable;
5242 outpu <<
5243 }; 3677 };
>> 3678 };
5244 3679
5245 data1-pins { !! 3680 qup_i2c9_default: qup-i2c9-default {
5246 pins !! 3681 mux {
5247 funct !! 3682 pins = "gpio125", "gpio126";
5248 drive !! 3683 function = "qup9";
5249 outpu <<
5250 }; 3684 };
5251 }; <<
5252 3685
5253 qup_i2c0_default: qup !! 3686 config {
5254 pins = "gpio2 !! 3687 pins = "gpio125", "gpio126";
5255 function = "q !! 3688 drive-strength = <2>;
5256 drive-strengt !! 3689 bias-disable;
5257 bias-disable; !! 3690 };
5258 }; 3691 };
5259 3692
5260 qup_i2c1_default: qup !! 3693 qup_i2c10_default: qup-i2c10-default {
5261 pins = "gpio4 !! 3694 mux {
5262 function = "q !! 3695 pins = "gpio129", "gpio130";
5263 drive-strengt !! 3696 function = "qup10";
5264 bias-disable; !! 3697 };
5265 }; <<
5266 3698
5267 qup_i2c2_default: qup !! 3699 config {
5268 pins = "gpio1 !! 3700 pins = "gpio129", "gpio130";
5269 function = "q !! 3701 drive-strength = <2>;
5270 drive-strengt !! 3702 bias-disable;
5271 bias-disable; !! 3703 };
5272 }; 3704 };
5273 3705
5274 qup_i2c3_default: qup !! 3706 qup_i2c11_default: qup-i2c11-default {
5275 pins = "gpio1 !! 3707 mux {
5276 function = "q !! 3708 pins = "gpio60", "gpio61";
5277 drive-strengt !! 3709 function = "qup11";
5278 bias-disable; !! 3710 };
5279 }; <<
5280 3711
5281 qup_i2c4_default: qup !! 3712 config {
5282 pins = "gpio8 !! 3713 pins = "gpio60", "gpio61";
5283 function = "q !! 3714 drive-strength = <2>;
5284 drive-strengt !! 3715 bias-disable;
5285 bias-disable; !! 3716 };
5286 }; 3717 };
5287 3718
5288 qup_i2c5_default: qup !! 3719 qup_i2c12_default: qup-i2c12-default {
5289 pins = "gpio1 !! 3720 mux {
5290 function = "q !! 3721 pins = "gpio32", "gpio33";
5291 drive-strengt !! 3722 function = "qup12";
5292 bias-disable; !! 3723 };
5293 }; <<
5294 3724
5295 qup_i2c6_default: qup !! 3725 config {
5296 pins = "gpio1 !! 3726 pins = "gpio32", "gpio33";
5297 function = "q !! 3727 drive-strength = <2>;
5298 drive-strengt !! 3728 bias-disable;
5299 bias-disable; !! 3729 };
5300 }; 3730 };
5301 3731
5302 qup_i2c7_default: qup !! 3732 qup_i2c13_default: qup-i2c13-default {
5303 pins = "gpio2 !! 3733 mux {
5304 function = "q !! 3734 pins = "gpio36", "gpio37";
5305 drive-strengt !! 3735 function = "qup13";
5306 bias-disable; !! 3736 };
5307 }; <<
5308 3737
5309 qup_i2c8_default: qup !! 3738 config {
5310 pins = "gpio2 !! 3739 pins = "gpio36", "gpio37";
5311 function = "q !! 3740 drive-strength = <2>;
5312 drive-strengt !! 3741 bias-disable;
5313 bias-disable; !! 3742 };
5314 }; 3743 };
5315 3744
5316 qup_i2c9_default: qup !! 3745 qup_i2c14_default: qup-i2c14-default {
5317 pins = "gpio1 !! 3746 mux {
5318 function = "q !! 3747 pins = "gpio40", "gpio41";
5319 drive-strengt !! 3748 function = "qup14";
5320 bias-disable; !! 3749 };
5321 }; <<
5322 3750
5323 qup_i2c10_default: qu !! 3751 config {
5324 pins = "gpio1 !! 3752 pins = "gpio40", "gpio41";
5325 function = "q !! 3753 drive-strength = <2>;
5326 drive-strengt !! 3754 bias-disable;
5327 bias-disable; !! 3755 };
5328 }; 3756 };
5329 3757
5330 qup_i2c11_default: qu !! 3758 qup_i2c15_default: qup-i2c15-default {
5331 pins = "gpio6 !! 3759 mux {
5332 function = "q !! 3760 pins = "gpio44", "gpio45";
5333 drive-strengt !! 3761 function = "qup15";
5334 bias-disable; !! 3762 };
5335 }; <<
5336 3763
5337 qup_i2c12_default: qu !! 3764 config {
5338 pins = "gpio3 !! 3765 pins = "gpio44", "gpio45";
5339 function = "q !! 3766 drive-strength = <2>;
5340 drive-strengt !! 3767 bias-disable;
5341 bias-disable; !! 3768 };
5342 }; 3769 };
5343 3770
5344 qup_i2c13_default: qu !! 3771 qup_i2c16_default: qup-i2c16-default {
5345 pins = "gpio3 !! 3772 mux {
5346 function = "q !! 3773 pins = "gpio48", "gpio49";
5347 drive-strengt !! 3774 function = "qup16";
5348 bias-disable; !! 3775 };
5349 }; <<
5350 3776
5351 qup_i2c14_default: qu !! 3777 config {
5352 pins = "gpio4 !! 3778 pins = "gpio48", "gpio49";
5353 function = "q !! 3779 drive-strength = <2>;
5354 drive-strengt !! 3780 bias-disable;
5355 bias-disable; !! 3781 };
5356 }; 3782 };
5357 3783
5358 qup_i2c15_default: qu !! 3784 qup_i2c17_default: qup-i2c17-default {
5359 pins = "gpio4 !! 3785 mux {
5360 function = "q !! 3786 pins = "gpio52", "gpio53";
5361 drive-strengt !! 3787 function = "qup17";
5362 bias-disable; !! 3788 };
5363 }; <<
5364 3789
5365 qup_i2c16_default: qu !! 3790 config {
5366 pins = "gpio4 !! 3791 pins = "gpio52", "gpio53";
5367 function = "q !! 3792 drive-strength = <2>;
5368 drive-strengt !! 3793 bias-disable;
5369 bias-disable; !! 3794 };
5370 }; 3795 };
5371 3796
5372 qup_i2c17_default: qu !! 3797 qup_i2c18_default: qup-i2c18-default {
5373 pins = "gpio5 !! 3798 mux {
5374 function = "q !! 3799 pins = "gpio56", "gpio57";
5375 drive-strengt !! 3800 function = "qup18";
5376 bias-disable; !! 3801 };
5377 }; <<
5378 3802
5379 qup_i2c18_default: qu !! 3803 config {
5380 pins = "gpio5 !! 3804 pins = "gpio56", "gpio57";
5381 function = "q !! 3805 drive-strength = <2>;
5382 drive-strengt !! 3806 bias-disable;
5383 bias-disable; !! 3807 };
5384 }; 3808 };
5385 3809
5386 qup_i2c19_default: qu !! 3810 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 3811 mux {
5388 function = "q !! 3812 pins = "gpio0", "gpio1";
5389 drive-strengt !! 3813 function = "qup19";
5390 bias-disable; !! 3814 };
>> 3815
>> 3816 config {
>> 3817 pins = "gpio0", "gpio1";
>> 3818 drive-strength = <2>;
>> 3819 bias-disable;
>> 3820 };
5391 }; 3821 };
5392 3822
5393 qup_spi0_cs: qup-spi0 !! 3823 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 3824 pins = "gpio31";
5395 function = "q 3825 function = "qup0";
5396 }; 3826 };
5397 3827
5398 qup_spi0_cs_gpio: qup !! 3828 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 3829 pins = "gpio31";
5400 function = "g 3830 function = "gpio";
5401 }; 3831 };
5402 3832
5403 qup_spi0_data_clk: qu !! 3833 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 3834 pins = "gpio28", "gpio29",
5405 "gpio3 3835 "gpio30";
5406 function = "q 3836 function = "qup0";
5407 }; 3837 };
5408 3838
5409 qup_spi1_cs: qup-spi1 !! 3839 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 3840 pins = "gpio7";
5411 function = "q 3841 function = "qup1";
5412 }; 3842 };
5413 3843
5414 qup_spi1_cs_gpio: qup !! 3844 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 3845 pins = "gpio7";
5416 function = "g 3846 function = "gpio";
5417 }; 3847 };
5418 3848
5419 qup_spi1_data_clk: qu !! 3849 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 3850 pins = "gpio4", "gpio5",
5421 "gpio6 3851 "gpio6";
5422 function = "q 3852 function = "qup1";
5423 }; 3853 };
5424 3854
5425 qup_spi2_cs: qup-spi2 !! 3855 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 3856 pins = "gpio118";
5427 function = "q 3857 function = "qup2";
5428 }; 3858 };
5429 3859
5430 qup_spi2_cs_gpio: qup !! 3860 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 3861 pins = "gpio118";
5432 function = "g 3862 function = "gpio";
5433 }; 3863 };
5434 3864
5435 qup_spi2_data_clk: qu !! 3865 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 3866 pins = "gpio115", "gpio116",
5437 "gpio1 3867 "gpio117";
5438 function = "q 3868 function = "qup2";
5439 }; 3869 };
5440 3870
5441 qup_spi3_cs: qup-spi3 !! 3871 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 3872 pins = "gpio122";
5443 function = "q 3873 function = "qup3";
5444 }; 3874 };
5445 3875
5446 qup_spi3_cs_gpio: qup !! 3876 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 3877 pins = "gpio122";
5448 function = "g 3878 function = "gpio";
5449 }; 3879 };
5450 3880
5451 qup_spi3_data_clk: qu !! 3881 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 3882 pins = "gpio119", "gpio120",
5453 "gpio1 3883 "gpio121";
5454 function = "q 3884 function = "qup3";
5455 }; 3885 };
5456 3886
5457 qup_spi4_cs: qup-spi4 !! 3887 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 3888 pins = "gpio11";
5459 function = "q 3889 function = "qup4";
5460 }; 3890 };
5461 3891
5462 qup_spi4_cs_gpio: qup !! 3892 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 3893 pins = "gpio11";
5464 function = "g 3894 function = "gpio";
5465 }; 3895 };
5466 3896
5467 qup_spi4_data_clk: qu !! 3897 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 3898 pins = "gpio8", "gpio9",
5469 "gpio1 3899 "gpio10";
5470 function = "q 3900 function = "qup4";
5471 }; 3901 };
5472 3902
5473 qup_spi5_cs: qup-spi5 !! 3903 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 3904 pins = "gpio15";
5475 function = "q 3905 function = "qup5";
5476 }; 3906 };
5477 3907
5478 qup_spi5_cs_gpio: qup !! 3908 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 3909 pins = "gpio15";
5480 function = "g 3910 function = "gpio";
5481 }; 3911 };
5482 3912
5483 qup_spi5_data_clk: qu !! 3913 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 3914 pins = "gpio12", "gpio13",
5485 "gpio1 3915 "gpio14";
5486 function = "q 3916 function = "qup5";
5487 }; 3917 };
5488 3918
5489 qup_spi6_cs: qup-spi6 !! 3919 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 3920 pins = "gpio19";
5491 function = "q 3921 function = "qup6";
5492 }; 3922 };
5493 3923
5494 qup_spi6_cs_gpio: qup !! 3924 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 3925 pins = "gpio19";
5496 function = "g 3926 function = "gpio";
5497 }; 3927 };
5498 3928
5499 qup_spi6_data_clk: qu !! 3929 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 3930 pins = "gpio16", "gpio17",
5501 "gpio1 3931 "gpio18";
5502 function = "q 3932 function = "qup6";
5503 }; 3933 };
5504 3934
5505 qup_spi7_cs: qup-spi7 !! 3935 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 3936 pins = "gpio23";
5507 function = "q 3937 function = "qup7";
5508 }; 3938 };
5509 3939
5510 qup_spi7_cs_gpio: qup !! 3940 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 3941 pins = "gpio23";
5512 function = "g 3942 function = "gpio";
5513 }; 3943 };
5514 3944
5515 qup_spi7_data_clk: qu !! 3945 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 3946 pins = "gpio20", "gpio21",
5517 "gpio2 3947 "gpio22";
5518 function = "q 3948 function = "qup7";
5519 }; 3949 };
5520 3950
5521 qup_spi8_cs: qup-spi8 !! 3951 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 3952 pins = "gpio27";
5523 function = "q 3953 function = "qup8";
5524 }; 3954 };
5525 3955
5526 qup_spi8_cs_gpio: qup !! 3956 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 3957 pins = "gpio27";
5528 function = "g 3958 function = "gpio";
5529 }; 3959 };
5530 3960
5531 qup_spi8_data_clk: qu !! 3961 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 3962 pins = "gpio24", "gpio25",
5533 "gpio2 3963 "gpio26";
5534 function = "q 3964 function = "qup8";
5535 }; 3965 };
5536 3966
5537 qup_spi9_cs: qup-spi9 !! 3967 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 3968 pins = "gpio128";
5539 function = "q 3969 function = "qup9";
5540 }; 3970 };
5541 3971
5542 qup_spi9_cs_gpio: qup !! 3972 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 3973 pins = "gpio128";
5544 function = "g 3974 function = "gpio";
5545 }; 3975 };
5546 3976
5547 qup_spi9_data_clk: qu !! 3977 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 3978 pins = "gpio125", "gpio126",
5549 "gpio1 3979 "gpio127";
5550 function = "q 3980 function = "qup9";
5551 }; 3981 };
5552 3982
5553 qup_spi10_cs: qup-spi !! 3983 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 3984 pins = "gpio132";
5555 function = "q 3985 function = "qup10";
5556 }; 3986 };
5557 3987
5558 qup_spi10_cs_gpio: qu !! 3988 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 3989 pins = "gpio132";
5560 function = "g 3990 function = "gpio";
5561 }; 3991 };
5562 3992
5563 qup_spi10_data_clk: q !! 3993 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 3994 pins = "gpio129", "gpio130",
5565 "gpio1 3995 "gpio131";
5566 function = "q 3996 function = "qup10";
5567 }; 3997 };
5568 3998
5569 qup_spi11_cs: qup-spi !! 3999 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 4000 pins = "gpio63";
5571 function = "q 4001 function = "qup11";
5572 }; 4002 };
5573 4003
5574 qup_spi11_cs_gpio: qu !! 4004 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 4005 pins = "gpio63";
5576 function = "g 4006 function = "gpio";
5577 }; 4007 };
5578 4008
5579 qup_spi11_data_clk: q !! 4009 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 4010 pins = "gpio60", "gpio61",
5581 "gpio6 4011 "gpio62";
5582 function = "q 4012 function = "qup11";
5583 }; 4013 };
5584 4014
5585 qup_spi12_cs: qup-spi !! 4015 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 4016 pins = "gpio35";
5587 function = "q 4017 function = "qup12";
5588 }; 4018 };
5589 4019
5590 qup_spi12_cs_gpio: qu !! 4020 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 4021 pins = "gpio35";
5592 function = "g 4022 function = "gpio";
5593 }; 4023 };
5594 4024
5595 qup_spi12_data_clk: q !! 4025 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 4026 pins = "gpio32", "gpio33",
5597 "gpio3 4027 "gpio34";
5598 function = "q 4028 function = "qup12";
5599 }; 4029 };
5600 4030
5601 qup_spi13_cs: qup-spi !! 4031 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 4032 pins = "gpio39";
5603 function = "q 4033 function = "qup13";
5604 }; 4034 };
5605 4035
5606 qup_spi13_cs_gpio: qu !! 4036 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 4037 pins = "gpio39";
5608 function = "g 4038 function = "gpio";
5609 }; 4039 };
5610 4040
5611 qup_spi13_data_clk: q !! 4041 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 4042 pins = "gpio36", "gpio37",
5613 "gpio3 4043 "gpio38";
5614 function = "q 4044 function = "qup13";
5615 }; 4045 };
5616 4046
5617 qup_spi14_cs: qup-spi !! 4047 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 4048 pins = "gpio43";
5619 function = "q 4049 function = "qup14";
5620 }; 4050 };
5621 4051
5622 qup_spi14_cs_gpio: qu !! 4052 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 4053 pins = "gpio43";
5624 function = "g 4054 function = "gpio";
5625 }; 4055 };
5626 4056
5627 qup_spi14_data_clk: q !! 4057 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 4058 pins = "gpio40", "gpio41",
5629 "gpio4 4059 "gpio42";
5630 function = "q 4060 function = "qup14";
5631 }; 4061 };
5632 4062
5633 qup_spi15_cs: qup-spi !! 4063 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 4064 pins = "gpio47";
5635 function = "q 4065 function = "qup15";
5636 }; 4066 };
5637 4067
5638 qup_spi15_cs_gpio: qu !! 4068 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 4069 pins = "gpio47";
5640 function = "g 4070 function = "gpio";
5641 }; 4071 };
5642 4072
5643 qup_spi15_data_clk: q !! 4073 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 4074 pins = "gpio44", "gpio45",
5645 "gpio4 4075 "gpio46";
5646 function = "q 4076 function = "qup15";
5647 }; 4077 };
5648 4078
5649 qup_spi16_cs: qup-spi !! 4079 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 4080 pins = "gpio51";
5651 function = "q 4081 function = "qup16";
5652 }; 4082 };
5653 4083
5654 qup_spi16_cs_gpio: qu !! 4084 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 4085 pins = "gpio51";
5656 function = "g 4086 function = "gpio";
5657 }; 4087 };
5658 4088
5659 qup_spi16_data_clk: q !! 4089 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 4090 pins = "gpio48", "gpio49",
5661 "gpio5 4091 "gpio50";
5662 function = "q 4092 function = "qup16";
5663 }; 4093 };
5664 4094
5665 qup_spi17_cs: qup-spi !! 4095 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 4096 pins = "gpio55";
5667 function = "q 4097 function = "qup17";
5668 }; 4098 };
5669 4099
5670 qup_spi17_cs_gpio: qu !! 4100 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 4101 pins = "gpio55";
5672 function = "g 4102 function = "gpio";
5673 }; 4103 };
5674 4104
5675 qup_spi17_data_clk: q !! 4105 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 4106 pins = "gpio52", "gpio53",
5677 "gpio5 4107 "gpio54";
5678 function = "q 4108 function = "qup17";
5679 }; 4109 };
5680 4110
5681 qup_spi18_cs: qup-spi !! 4111 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 4112 pins = "gpio59";
5683 function = "q 4113 function = "qup18";
5684 }; 4114 };
5685 4115
5686 qup_spi18_cs_gpio: qu !! 4116 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 4117 pins = "gpio59";
5688 function = "g 4118 function = "gpio";
5689 }; 4119 };
5690 4120
5691 qup_spi18_data_clk: q !! 4121 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 4122 pins = "gpio56", "gpio57",
5693 "gpio5 4123 "gpio58";
5694 function = "q 4124 function = "qup18";
5695 }; 4125 };
5696 4126
5697 qup_spi19_cs: qup-spi !! 4127 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 4128 pins = "gpio3";
5699 function = "q 4129 function = "qup19";
5700 }; 4130 };
5701 4131
5702 qup_spi19_cs_gpio: qu !! 4132 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 4133 pins = "gpio3";
5704 function = "g 4134 function = "gpio";
5705 }; 4135 };
5706 4136
5707 qup_spi19_data_clk: q !! 4137 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 4138 pins = "gpio0", "gpio1",
5709 "gpio2 4139 "gpio2";
5710 function = "q 4140 function = "qup19";
5711 }; 4141 };
5712 4142
5713 qup_uart2_default: qu !! 4143 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 4144 mux {
5715 function = "q !! 4145 pins = "gpio117", "gpio118";
>> 4146 function = "qup2";
>> 4147 };
5716 }; 4148 };
5717 4149
5718 qup_uart6_default: qu !! 4150 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 4151 mux {
5720 function = "q !! 4152 pins = "gpio16", "gpio17",
>> 4153 "gpio18", "gpio19";
>> 4154 function = "qup6";
>> 4155 };
5721 }; 4156 };
5722 4157
5723 qup_uart12_default: q !! 4158 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 4159 mux {
5725 function = "q !! 4160 pins = "gpio34", "gpio35";
>> 4161 function = "qup12";
>> 4162 };
5726 }; 4163 };
5727 4164
5728 qup_uart17_default: q !! 4165 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 4166 mux {
5730 function = "q !! 4167 pins = "gpio52", "gpio53",
>> 4168 "gpio54", "gpio55";
>> 4169 function = "qup17";
>> 4170 };
5731 }; 4171 };
5732 4172
5733 qup_uart18_default: q !! 4173 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 4174 mux {
5735 function = "q !! 4175 pins = "gpio58", "gpio59";
>> 4176 function = "qup18";
>> 4177 };
5736 }; 4178 };
5737 4179
5738 tert_mi2s_active: ter !! 4180 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 4181 sck {
5740 pins 4182 pins = "gpio133";
5741 funct 4183 function = "mi2s2_sck";
5742 drive 4184 drive-strength = <8>;
5743 bias- 4185 bias-disable;
5744 }; 4186 };
5745 4187
5746 data0-pins { !! 4188 data0 {
5747 pins 4189 pins = "gpio134";
5748 funct 4190 function = "mi2s2_data0";
5749 drive 4191 drive-strength = <8>;
5750 bias- 4192 bias-disable;
5751 outpu 4193 output-high;
5752 }; 4194 };
5753 4195
5754 ws-pins { !! 4196 ws {
5755 pins 4197 pins = "gpio135";
5756 funct 4198 function = "mi2s2_ws";
5757 drive 4199 drive-strength = <8>;
5758 outpu 4200 output-high;
5759 }; 4201 };
5760 }; 4202 };
5761 4203
5762 sdc2_sleep_state: sdc !! 4204 sdc2_sleep_state: sdc2-sleep {
5763 clk-pins { !! 4205 clk {
5764 pins 4206 pins = "sdc2_clk";
5765 drive 4207 drive-strength = <2>;
5766 bias- 4208 bias-disable;
5767 }; 4209 };
5768 4210
5769 cmd-pins { !! 4211 cmd {
5770 pins 4212 pins = "sdc2_cmd";
5771 drive 4213 drive-strength = <2>;
5772 bias- 4214 bias-pull-up;
5773 }; 4215 };
5774 4216
5775 data-pins { !! 4217 data {
5776 pins 4218 pins = "sdc2_data";
5777 drive 4219 drive-strength = <2>;
5778 bias- 4220 bias-pull-up;
5779 }; 4221 };
5780 }; 4222 };
5781 4223
5782 pcie0_default_state: !! 4224 pcie0_default_state: pcie0-default {
5783 perst-pins { !! 4225 perst {
5784 pins 4226 pins = "gpio79";
5785 funct 4227 function = "gpio";
5786 drive 4228 drive-strength = <2>;
5787 bias- 4229 bias-pull-down;
5788 }; 4230 };
5789 4231
5790 clkreq-pins { !! 4232 clkreq {
5791 pins 4233 pins = "gpio80";
5792 funct 4234 function = "pci_e0";
5793 drive 4235 drive-strength = <2>;
5794 bias- 4236 bias-pull-up;
5795 }; 4237 };
5796 4238
5797 wake-pins { !! 4239 wake {
5798 pins 4240 pins = "gpio81";
5799 funct 4241 function = "gpio";
5800 drive 4242 drive-strength = <2>;
5801 bias- 4243 bias-pull-up;
5802 }; 4244 };
5803 }; 4245 };
5804 4246
5805 pcie1_default_state: !! 4247 pcie1_default_state: pcie1-default {
5806 perst-pins { !! 4248 perst {
5807 pins 4249 pins = "gpio82";
5808 funct 4250 function = "gpio";
5809 drive 4251 drive-strength = <2>;
5810 bias- 4252 bias-pull-down;
5811 }; 4253 };
5812 4254
5813 clkreq-pins { !! 4255 clkreq {
5814 pins 4256 pins = "gpio83";
5815 funct 4257 function = "pci_e1";
5816 drive 4258 drive-strength = <2>;
5817 bias- 4259 bias-pull-up;
5818 }; 4260 };
5819 4261
5820 wake-pins { !! 4262 wake {
5821 pins 4263 pins = "gpio84";
5822 funct 4264 function = "gpio";
5823 drive 4265 drive-strength = <2>;
5824 bias- 4266 bias-pull-up;
5825 }; 4267 };
5826 }; 4268 };
5827 4269
5828 pcie2_default_state: !! 4270 pcie2_default_state: pcie2-default {
5829 perst-pins { !! 4271 perst {
5830 pins 4272 pins = "gpio85";
5831 funct 4273 function = "gpio";
5832 drive 4274 drive-strength = <2>;
5833 bias- 4275 bias-pull-down;
5834 }; 4276 };
5835 4277
5836 clkreq-pins { !! 4278 clkreq {
5837 pins 4279 pins = "gpio86";
5838 funct 4280 function = "pci_e2";
5839 drive 4281 drive-strength = <2>;
5840 bias- 4282 bias-pull-up;
5841 }; 4283 };
5842 4284
5843 wake-pins { !! 4285 wake {
5844 pins 4286 pins = "gpio87";
5845 funct 4287 function = "gpio";
5846 drive 4288 drive-strength = <2>;
5847 bias- 4289 bias-pull-up;
5848 }; 4290 };
5849 }; 4291 };
5850 }; 4292 };
5851 4293
5852 apps_smmu: iommu@15000000 { 4294 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 4295 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 4296 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 4297 #iommu-cells = <2>;
5856 #global-interrupts = 4298 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 4299 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 4300 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 4301 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 4302 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 4303 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 4304 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 4305 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 4306 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 4307 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 4308 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 4309 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 4310 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 4311 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 4312 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 4313 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 4314 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 4315 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 4316 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 4317 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 4318 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 4319 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 4320 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 4321 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 4322 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 4323 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 4324 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 4325 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 4326 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 4327 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 4328 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 4329 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 4330 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 4331 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 4332 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 4333 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 4334 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 4335 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 4336 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 4337 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 4338 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 4339 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 4340 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 4341 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 4342 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 4343 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 4344 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 4345 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 4346 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 4347 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 4348 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 4349 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 4350 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 4351 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 4352 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 4353 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 4354 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 4355 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 4356 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 4357 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 4358 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 4359 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 4360 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 4361 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 4362 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 4363 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 4364 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 4365 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 4366 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 4367 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 4368 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 4369 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 4370 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 4371 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 4372 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 4373 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 4374 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 4375 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 4376 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 4377 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 4378 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 4379 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 4380 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 4381 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 4382 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 4383 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 4384 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 4385 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 4386 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 4387 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 4388 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 4389 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 4390 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 4391 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 4392 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 4393 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 4394 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 4395 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 4396 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 4397 };
5957 4398
5958 adsp: remoteproc@17300000 { 4399 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 4400 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 4401 reg = <0 0x17300000 0 0x100>;
5961 4402
5962 interrupts-extended = !! 4403 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 4404 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 4405 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 4406 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 4407 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 4408 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 4409 "handover", "stop-ack";
5969 4410
5970 clocks = <&rpmhcc RPM 4411 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 4412 clock-names = "xo";
5972 4413
5973 power-domains = <&rpm !! 4414 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 4415 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 4416 power-domain-names = "lcx", "lmx";
5976 4417
5977 memory-region = <&ads 4418 memory-region = <&adsp_mem>;
5978 4419
5979 qcom,qmp = <&aoss_qmp 4420 qcom,qmp = <&aoss_qmp>;
5980 4421
5981 qcom,smem-states = <& 4422 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 4423 qcom,smem-state-names = "stop";
5983 4424
5984 status = "disabled"; 4425 status = "disabled";
5985 4426
5986 glink-edge { 4427 glink-edge {
5987 interrupts-ex 4428 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 4429 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 4430 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 4431 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 4432 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 4433
5993 label = "lpas 4434 label = "lpass";
5994 qcom,remote-p 4435 qcom,remote-pid = <2>;
5995 4436
5996 apr { 4437 apr {
5997 compa 4438 compatible = "qcom,apr-v2";
5998 qcom, 4439 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 4440 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 4441 #address-cells = <1>;
6001 #size 4442 #size-cells = <0>;
6002 4443
6003 servi !! 4444 apr-service@3 {
6004 4445 reg = <APR_SVC_ADSP_CORE>;
6005 4446 compatible = "qcom,q6core";
6006 4447 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 4448 };
6008 4449
6009 q6afe !! 4450 q6afe: apr-service@4 {
6010 4451 compatible = "qcom,q6afe";
6011 4452 reg = <APR_SVC_AFE>;
6012 4453 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 4454 q6afedai: dais {
6014 4455 compatible = "qcom,q6afe-dais";
6015 4456 #address-cells = <1>;
6016 4457 #size-cells = <0>;
6017 4458 #sound-dai-cells = <1>;
6018 4459 };
6019 4460
6020 !! 4461 q6afecc: cc {
6021 4462 compatible = "qcom,q6afe-clocks";
6022 4463 #clock-cells = <2>;
6023 4464 };
6024 }; 4465 };
6025 4466
6026 q6asm !! 4467 q6asm: apr-service@7 {
6027 4468 compatible = "qcom,q6asm";
6028 4469 reg = <APR_SVC_ASM>;
6029 4470 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 4471 q6asmdai: dais {
6031 4472 compatible = "qcom,q6asm-dais";
6032 4473 #address-cells = <1>;
6033 4474 #size-cells = <0>;
6034 4475 #sound-dai-cells = <1>;
6035 4476 iommus = <&apps_smmu 0x1801 0x0>;
6036 4477 };
6037 }; 4478 };
6038 4479
6039 q6adm !! 4480 q6adm: apr-service@8 {
6040 4481 compatible = "qcom,q6adm";
6041 4482 reg = <APR_SVC_ADM>;
6042 4483 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 4484 q6routing: routing {
6044 4485 compatible = "qcom,q6adm-routing";
6045 4486 #sound-dai-cells = <0>;
6046 4487 };
6047 }; 4488 };
6048 }; 4489 };
6049 4490
6050 fastrpc { 4491 fastrpc {
6051 compa 4492 compatible = "qcom,fastrpc";
6052 qcom, 4493 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 4494 label = "adsp";
6054 qcom, 4495 qcom,non-secure-domain;
6055 #addr 4496 #address-cells = <1>;
6056 #size 4497 #size-cells = <0>;
6057 4498
6058 compu 4499 compute-cb@3 {
6059 4500 compatible = "qcom,fastrpc-compute-cb";
6060 4501 reg = <3>;
6061 4502 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 4503 };
6063 4504
6064 compu 4505 compute-cb@4 {
6065 4506 compatible = "qcom,fastrpc-compute-cb";
6066 4507 reg = <4>;
6067 4508 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 4509 };
6069 4510
6070 compu 4511 compute-cb@5 {
6071 4512 compatible = "qcom,fastrpc-compute-cb";
6072 4513 reg = <5>;
6073 4514 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 4515 };
6075 }; 4516 };
6076 }; 4517 };
6077 }; 4518 };
6078 4519
6079 intc: interrupt-controller@17 4520 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 4521 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 4522 #interrupt-cells = <3>;
6082 interrupt-controller; 4523 interrupt-controller;
6083 reg = <0x0 0x17a00000 4524 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 4525 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 4526 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 4527 };
6087 4528
6088 watchdog@17c10000 { 4529 watchdog@17c10000 {
6089 compatible = "qcom,ap 4530 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 4531 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 4532 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 4533 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 4534 };
6094 4535
6095 timer@17c20000 { 4536 timer@17c20000 {
6096 #address-cells = <1>; 4537 #address-cells = <1>;
6097 #size-cells = <1>; 4538 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 4539 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 4540 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 4541 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 4542 clock-frequency = <19200000>;
6102 4543
6103 frame@17c21000 { 4544 frame@17c21000 {
6104 frame-number 4545 frame-number = <0>;
6105 interrupts = 4546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 4547 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 4548 reg = <0x17c21000 0x1000>,
6108 <0x17c2 4549 <0x17c22000 0x1000>;
6109 }; 4550 };
6110 4551
6111 frame@17c23000 { 4552 frame@17c23000 {
6112 frame-number 4553 frame-number = <1>;
6113 interrupts = 4554 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 4555 reg = <0x17c23000 0x1000>;
6115 status = "dis 4556 status = "disabled";
6116 }; 4557 };
6117 4558
6118 frame@17c25000 { 4559 frame@17c25000 {
6119 frame-number 4560 frame-number = <2>;
6120 interrupts = 4561 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 4562 reg = <0x17c25000 0x1000>;
6122 status = "dis 4563 status = "disabled";
6123 }; 4564 };
6124 4565
6125 frame@17c27000 { 4566 frame@17c27000 {
6126 frame-number 4567 frame-number = <3>;
6127 interrupts = 4568 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 4569 reg = <0x17c27000 0x1000>;
6129 status = "dis 4570 status = "disabled";
6130 }; 4571 };
6131 4572
6132 frame@17c29000 { 4573 frame@17c29000 {
6133 frame-number 4574 frame-number = <4>;
6134 interrupts = 4575 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 4576 reg = <0x17c29000 0x1000>;
6136 status = "dis 4577 status = "disabled";
6137 }; 4578 };
6138 4579
6139 frame@17c2b000 { 4580 frame@17c2b000 {
6140 frame-number 4581 frame-number = <5>;
6141 interrupts = 4582 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 4583 reg = <0x17c2b000 0x1000>;
6143 status = "dis 4584 status = "disabled";
6144 }; 4585 };
6145 4586
6146 frame@17c2d000 { 4587 frame@17c2d000 {
6147 frame-number 4588 frame-number = <6>;
6148 interrupts = 4589 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 4590 reg = <0x17c2d000 0x1000>;
6150 status = "dis 4591 status = "disabled";
6151 }; 4592 };
6152 }; 4593 };
6153 4594
6154 apps_rsc: rsc@18200000 { 4595 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 4596 label = "apps_rsc";
6156 compatible = "qcom,rp 4597 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 4598 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 4599 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 4600 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 4601 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 4602 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 4603 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 4604 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 4605 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 4606 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 4607 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 4608 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 4609
6170 rpmhcc: clock-control 4610 rpmhcc: clock-controller {
6171 compatible = 4611 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 4612 #clock-cells = <1>;
6173 clock-names = 4613 clock-names = "xo";
6174 clocks = <&xo 4614 clocks = <&xo_board>;
6175 }; 4615 };
6176 4616
6177 rpmhpd: power-control 4617 rpmhpd: power-controller {
6178 compatible = 4618 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 4619 #power-domain-cells = <1>;
6180 operating-poi 4620 operating-points-v2 = <&rpmhpd_opp_table>;
6181 4621
6182 rpmhpd_opp_ta 4622 rpmhpd_opp_table: opp-table {
6183 compa 4623 compatible = "operating-points-v2";
6184 4624
6185 rpmhp 4625 rpmhpd_opp_ret: opp1 {
6186 4626 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 4627 };
6188 4628
6189 rpmhp 4629 rpmhpd_opp_min_svs: opp2 {
6190 4630 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 4631 };
6192 4632
6193 rpmhp 4633 rpmhpd_opp_low_svs: opp3 {
6194 4634 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 4635 };
6196 4636
6197 rpmhp 4637 rpmhpd_opp_svs: opp4 {
6198 4638 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 4639 };
6200 4640
6201 rpmhp 4641 rpmhpd_opp_svs_l1: opp5 {
6202 4642 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 4643 };
6204 4644
6205 rpmhp 4645 rpmhpd_opp_nom: opp6 {
6206 4646 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 4647 };
6208 4648
6209 rpmhp 4649 rpmhpd_opp_nom_l1: opp7 {
6210 4650 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 4651 };
6212 4652
6213 rpmhp 4653 rpmhpd_opp_nom_l2: opp8 {
6214 4654 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 4655 };
6216 4656
6217 rpmhp 4657 rpmhpd_opp_turbo: opp9 {
6218 4658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 4659 };
6220 4660
6221 rpmhp 4661 rpmhpd_opp_turbo_l1: opp10 {
6222 4662 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 4663 };
6224 }; 4664 };
6225 }; 4665 };
6226 4666
6227 apps_bcm_voter: bcm-v !! 4667 apps_bcm_voter: bcm_voter {
6228 compatible = 4668 compatible = "qcom,bcm-voter";
6229 }; 4669 };
6230 }; 4670 };
6231 4671
6232 epss_l3: interconnect@1859000 4672 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 4673 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 4674 reg = <0 0x18590000 0 0x1000>;
6235 4675
6236 clocks = <&rpmhcc RPM 4676 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 4677 clock-names = "xo", "alternate";
6238 4678
6239 #interconnect-cells = 4679 #interconnect-cells = <1>;
6240 }; 4680 };
6241 4681
6242 cpufreq_hw: cpufreq@18591000 4682 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 4683 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 4684 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 4685 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 4686 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 4687 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 4688 "freq-domain2";
6249 4689
6250 clocks = <&rpmhcc RPM 4690 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 4691 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 4692 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 4693 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 4694 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 4695 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 4696 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 4697 };
6259 }; 4698 };
6260 4699
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 4700 timer {
6265 compatible = "arm,armv8-timer 4701 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 4702 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 4703 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 4704 <GIC_PPI 14
6269 (GIC_CPU_MASK 4705 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 4706 <GIC_PPI 11
6271 (GIC_CPU_MASK 4707 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 4708 <GIC_PPI 10
6273 (GIC_CPU_MASK 4709 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 4710 };
6275 4711
6276 thermal-zones { 4712 thermal-zones {
6277 cpu0-thermal { 4713 cpu0-thermal {
6278 polling-delay-passive 4714 polling-delay-passive = <250>;
>> 4715 polling-delay = <1000>;
6279 4716
6280 thermal-sensors = <&t 4717 thermal-sensors = <&tsens0 1>;
6281 4718
6282 trips { 4719 trips {
6283 cpu0_alert0: 4720 cpu0_alert0: trip-point0 {
6284 tempe 4721 temperature = <90000>;
6285 hyste 4722 hysteresis = <2000>;
6286 type 4723 type = "passive";
6287 }; 4724 };
6288 4725
6289 cpu0_alert1: 4726 cpu0_alert1: trip-point1 {
6290 tempe 4727 temperature = <95000>;
6291 hyste 4728 hysteresis = <2000>;
6292 type 4729 type = "passive";
6293 }; 4730 };
6294 4731
6295 cpu0_crit: cp !! 4732 cpu0_crit: cpu_crit {
6296 tempe 4733 temperature = <110000>;
6297 hyste 4734 hysteresis = <1000>;
6298 type 4735 type = "critical";
6299 }; 4736 };
6300 }; 4737 };
6301 4738
6302 cooling-maps { 4739 cooling-maps {
6303 map0 { 4740 map0 {
6304 trip 4741 trip = <&cpu0_alert0>;
6305 cooli 4742 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 4743 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 4744 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 4745 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 4746 };
6310 map1 { 4747 map1 {
6311 trip 4748 trip = <&cpu0_alert1>;
6312 cooli 4749 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 4750 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 4751 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 4752 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 4753 };
6317 }; 4754 };
6318 }; 4755 };
6319 4756
6320 cpu1-thermal { 4757 cpu1-thermal {
6321 polling-delay-passive 4758 polling-delay-passive = <250>;
>> 4759 polling-delay = <1000>;
6322 4760
6323 thermal-sensors = <&t 4761 thermal-sensors = <&tsens0 2>;
6324 4762
6325 trips { 4763 trips {
6326 cpu1_alert0: 4764 cpu1_alert0: trip-point0 {
6327 tempe 4765 temperature = <90000>;
6328 hyste 4766 hysteresis = <2000>;
6329 type 4767 type = "passive";
6330 }; 4768 };
6331 4769
6332 cpu1_alert1: 4770 cpu1_alert1: trip-point1 {
6333 tempe 4771 temperature = <95000>;
6334 hyste 4772 hysteresis = <2000>;
6335 type 4773 type = "passive";
6336 }; 4774 };
6337 4775
6338 cpu1_crit: cp !! 4776 cpu1_crit: cpu_crit {
6339 tempe 4777 temperature = <110000>;
6340 hyste 4778 hysteresis = <1000>;
6341 type 4779 type = "critical";
6342 }; 4780 };
6343 }; 4781 };
6344 4782
6345 cooling-maps { 4783 cooling-maps {
6346 map0 { 4784 map0 {
6347 trip 4785 trip = <&cpu1_alert0>;
6348 cooli 4786 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 4787 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 4788 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 4789 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 4790 };
6353 map1 { 4791 map1 {
6354 trip 4792 trip = <&cpu1_alert1>;
6355 cooli 4793 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 4794 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 4795 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 4796 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 4797 };
6360 }; 4798 };
6361 }; 4799 };
6362 4800
6363 cpu2-thermal { 4801 cpu2-thermal {
6364 polling-delay-passive 4802 polling-delay-passive = <250>;
>> 4803 polling-delay = <1000>;
6365 4804
6366 thermal-sensors = <&t 4805 thermal-sensors = <&tsens0 3>;
6367 4806
6368 trips { 4807 trips {
6369 cpu2_alert0: 4808 cpu2_alert0: trip-point0 {
6370 tempe 4809 temperature = <90000>;
6371 hyste 4810 hysteresis = <2000>;
6372 type 4811 type = "passive";
6373 }; 4812 };
6374 4813
6375 cpu2_alert1: 4814 cpu2_alert1: trip-point1 {
6376 tempe 4815 temperature = <95000>;
6377 hyste 4816 hysteresis = <2000>;
6378 type 4817 type = "passive";
6379 }; 4818 };
6380 4819
6381 cpu2_crit: cp !! 4820 cpu2_crit: cpu_crit {
6382 tempe 4821 temperature = <110000>;
6383 hyste 4822 hysteresis = <1000>;
6384 type 4823 type = "critical";
6385 }; 4824 };
6386 }; 4825 };
6387 4826
6388 cooling-maps { 4827 cooling-maps {
6389 map0 { 4828 map0 {
6390 trip 4829 trip = <&cpu2_alert0>;
6391 cooli 4830 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 4831 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 4832 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 4833 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 4834 };
6396 map1 { 4835 map1 {
6397 trip 4836 trip = <&cpu2_alert1>;
6398 cooli 4837 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 4838 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 4839 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 4840 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 4841 };
6403 }; 4842 };
6404 }; 4843 };
6405 4844
6406 cpu3-thermal { 4845 cpu3-thermal {
6407 polling-delay-passive 4846 polling-delay-passive = <250>;
>> 4847 polling-delay = <1000>;
6408 4848
6409 thermal-sensors = <&t 4849 thermal-sensors = <&tsens0 4>;
6410 4850
6411 trips { 4851 trips {
6412 cpu3_alert0: 4852 cpu3_alert0: trip-point0 {
6413 tempe 4853 temperature = <90000>;
6414 hyste 4854 hysteresis = <2000>;
6415 type 4855 type = "passive";
6416 }; 4856 };
6417 4857
6418 cpu3_alert1: 4858 cpu3_alert1: trip-point1 {
6419 tempe 4859 temperature = <95000>;
6420 hyste 4860 hysteresis = <2000>;
6421 type 4861 type = "passive";
6422 }; 4862 };
6423 4863
6424 cpu3_crit: cp !! 4864 cpu3_crit: cpu_crit {
6425 tempe 4865 temperature = <110000>;
6426 hyste 4866 hysteresis = <1000>;
6427 type 4867 type = "critical";
6428 }; 4868 };
6429 }; 4869 };
6430 4870
6431 cooling-maps { 4871 cooling-maps {
6432 map0 { 4872 map0 {
6433 trip 4873 trip = <&cpu3_alert0>;
6434 cooli 4874 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 4875 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 4876 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 4877 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 4878 };
6439 map1 { 4879 map1 {
6440 trip 4880 trip = <&cpu3_alert1>;
6441 cooli 4881 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 4882 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 4883 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 4884 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 4885 };
6446 }; 4886 };
6447 }; 4887 };
6448 4888
6449 cpu4-top-thermal { 4889 cpu4-top-thermal {
6450 polling-delay-passive 4890 polling-delay-passive = <250>;
>> 4891 polling-delay = <1000>;
6451 4892
6452 thermal-sensors = <&t 4893 thermal-sensors = <&tsens0 7>;
6453 4894
6454 trips { 4895 trips {
6455 cpu4_top_aler 4896 cpu4_top_alert0: trip-point0 {
6456 tempe 4897 temperature = <90000>;
6457 hyste 4898 hysteresis = <2000>;
6458 type 4899 type = "passive";
6459 }; 4900 };
6460 4901
6461 cpu4_top_aler 4902 cpu4_top_alert1: trip-point1 {
6462 tempe 4903 temperature = <95000>;
6463 hyste 4904 hysteresis = <2000>;
6464 type 4905 type = "passive";
6465 }; 4906 };
6466 4907
6467 cpu4_top_crit !! 4908 cpu4_top_crit: cpu_crit {
6468 tempe 4909 temperature = <110000>;
6469 hyste 4910 hysteresis = <1000>;
6470 type 4911 type = "critical";
6471 }; 4912 };
6472 }; 4913 };
6473 4914
6474 cooling-maps { 4915 cooling-maps {
6475 map0 { 4916 map0 {
6476 trip 4917 trip = <&cpu4_top_alert0>;
6477 cooli 4918 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 4919 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 4920 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 4921 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 4922 };
6482 map1 { 4923 map1 {
6483 trip 4924 trip = <&cpu4_top_alert1>;
6484 cooli 4925 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 4926 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 4927 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 4928 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 4929 };
6489 }; 4930 };
6490 }; 4931 };
6491 4932
6492 cpu5-top-thermal { 4933 cpu5-top-thermal {
6493 polling-delay-passive 4934 polling-delay-passive = <250>;
>> 4935 polling-delay = <1000>;
6494 4936
6495 thermal-sensors = <&t 4937 thermal-sensors = <&tsens0 8>;
6496 4938
6497 trips { 4939 trips {
6498 cpu5_top_aler 4940 cpu5_top_alert0: trip-point0 {
6499 tempe 4941 temperature = <90000>;
6500 hyste 4942 hysteresis = <2000>;
6501 type 4943 type = "passive";
6502 }; 4944 };
6503 4945
6504 cpu5_top_aler 4946 cpu5_top_alert1: trip-point1 {
6505 tempe 4947 temperature = <95000>;
6506 hyste 4948 hysteresis = <2000>;
6507 type 4949 type = "passive";
6508 }; 4950 };
6509 4951
6510 cpu5_top_crit !! 4952 cpu5_top_crit: cpu_crit {
6511 tempe 4953 temperature = <110000>;
6512 hyste 4954 hysteresis = <1000>;
6513 type 4955 type = "critical";
6514 }; 4956 };
6515 }; 4957 };
6516 4958
6517 cooling-maps { 4959 cooling-maps {
6518 map0 { 4960 map0 {
6519 trip 4961 trip = <&cpu5_top_alert0>;
6520 cooli 4962 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 4963 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 4964 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 4965 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 4966 };
6525 map1 { 4967 map1 {
6526 trip 4968 trip = <&cpu5_top_alert1>;
6527 cooli 4969 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 4970 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 4971 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 4972 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 4973 };
6532 }; 4974 };
6533 }; 4975 };
6534 4976
6535 cpu6-top-thermal { 4977 cpu6-top-thermal {
6536 polling-delay-passive 4978 polling-delay-passive = <250>;
>> 4979 polling-delay = <1000>;
6537 4980
6538 thermal-sensors = <&t 4981 thermal-sensors = <&tsens0 9>;
6539 4982
6540 trips { 4983 trips {
6541 cpu6_top_aler 4984 cpu6_top_alert0: trip-point0 {
6542 tempe 4985 temperature = <90000>;
6543 hyste 4986 hysteresis = <2000>;
6544 type 4987 type = "passive";
6545 }; 4988 };
6546 4989
6547 cpu6_top_aler 4990 cpu6_top_alert1: trip-point1 {
6548 tempe 4991 temperature = <95000>;
6549 hyste 4992 hysteresis = <2000>;
6550 type 4993 type = "passive";
6551 }; 4994 };
6552 4995
6553 cpu6_top_crit !! 4996 cpu6_top_crit: cpu_crit {
6554 tempe 4997 temperature = <110000>;
6555 hyste 4998 hysteresis = <1000>;
6556 type 4999 type = "critical";
6557 }; 5000 };
6558 }; 5001 };
6559 5002
6560 cooling-maps { 5003 cooling-maps {
6561 map0 { 5004 map0 {
6562 trip 5005 trip = <&cpu6_top_alert0>;
6563 cooli 5006 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 5007 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 5008 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 5009 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 5010 };
6568 map1 { 5011 map1 {
6569 trip 5012 trip = <&cpu6_top_alert1>;
6570 cooli 5013 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 5014 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 5015 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 5016 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 5017 };
6575 }; 5018 };
6576 }; 5019 };
6577 5020
6578 cpu7-top-thermal { 5021 cpu7-top-thermal {
6579 polling-delay-passive 5022 polling-delay-passive = <250>;
>> 5023 polling-delay = <1000>;
6580 5024
6581 thermal-sensors = <&t 5025 thermal-sensors = <&tsens0 10>;
6582 5026
6583 trips { 5027 trips {
6584 cpu7_top_aler 5028 cpu7_top_alert0: trip-point0 {
6585 tempe 5029 temperature = <90000>;
6586 hyste 5030 hysteresis = <2000>;
6587 type 5031 type = "passive";
6588 }; 5032 };
6589 5033
6590 cpu7_top_aler 5034 cpu7_top_alert1: trip-point1 {
6591 tempe 5035 temperature = <95000>;
6592 hyste 5036 hysteresis = <2000>;
6593 type 5037 type = "passive";
6594 }; 5038 };
6595 5039
6596 cpu7_top_crit !! 5040 cpu7_top_crit: cpu_crit {
6597 tempe 5041 temperature = <110000>;
6598 hyste 5042 hysteresis = <1000>;
6599 type 5043 type = "critical";
6600 }; 5044 };
6601 }; 5045 };
6602 5046
6603 cooling-maps { 5047 cooling-maps {
6604 map0 { 5048 map0 {
6605 trip 5049 trip = <&cpu7_top_alert0>;
6606 cooli 5050 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 5051 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 5052 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 5053 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 5054 };
6611 map1 { 5055 map1 {
6612 trip 5056 trip = <&cpu7_top_alert1>;
6613 cooli 5057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 5058 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 5059 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 5060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 5061 };
6618 }; 5062 };
6619 }; 5063 };
6620 5064
6621 cpu4-bottom-thermal { 5065 cpu4-bottom-thermal {
6622 polling-delay-passive 5066 polling-delay-passive = <250>;
>> 5067 polling-delay = <1000>;
6623 5068
6624 thermal-sensors = <&t 5069 thermal-sensors = <&tsens0 11>;
6625 5070
6626 trips { 5071 trips {
6627 cpu4_bottom_a 5072 cpu4_bottom_alert0: trip-point0 {
6628 tempe 5073 temperature = <90000>;
6629 hyste 5074 hysteresis = <2000>;
6630 type 5075 type = "passive";
6631 }; 5076 };
6632 5077
6633 cpu4_bottom_a 5078 cpu4_bottom_alert1: trip-point1 {
6634 tempe 5079 temperature = <95000>;
6635 hyste 5080 hysteresis = <2000>;
6636 type 5081 type = "passive";
6637 }; 5082 };
6638 5083
6639 cpu4_bottom_c !! 5084 cpu4_bottom_crit: cpu_crit {
6640 tempe 5085 temperature = <110000>;
6641 hyste 5086 hysteresis = <1000>;
6642 type 5087 type = "critical";
6643 }; 5088 };
6644 }; 5089 };
6645 5090
6646 cooling-maps { 5091 cooling-maps {
6647 map0 { 5092 map0 {
6648 trip 5093 trip = <&cpu4_bottom_alert0>;
6649 cooli 5094 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 5095 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 5096 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 5097 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 5098 };
6654 map1 { 5099 map1 {
6655 trip 5100 trip = <&cpu4_bottom_alert1>;
6656 cooli 5101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 5102 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 5103 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 5104 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 5105 };
6661 }; 5106 };
6662 }; 5107 };
6663 5108
6664 cpu5-bottom-thermal { 5109 cpu5-bottom-thermal {
6665 polling-delay-passive 5110 polling-delay-passive = <250>;
>> 5111 polling-delay = <1000>;
6666 5112
6667 thermal-sensors = <&t 5113 thermal-sensors = <&tsens0 12>;
6668 5114
6669 trips { 5115 trips {
6670 cpu5_bottom_a 5116 cpu5_bottom_alert0: trip-point0 {
6671 tempe 5117 temperature = <90000>;
6672 hyste 5118 hysteresis = <2000>;
6673 type 5119 type = "passive";
6674 }; 5120 };
6675 5121
6676 cpu5_bottom_a 5122 cpu5_bottom_alert1: trip-point1 {
6677 tempe 5123 temperature = <95000>;
6678 hyste 5124 hysteresis = <2000>;
6679 type 5125 type = "passive";
6680 }; 5126 };
6681 5127
6682 cpu5_bottom_c !! 5128 cpu5_bottom_crit: cpu_crit {
6683 tempe 5129 temperature = <110000>;
6684 hyste 5130 hysteresis = <1000>;
6685 type 5131 type = "critical";
6686 }; 5132 };
6687 }; 5133 };
6688 5134
6689 cooling-maps { 5135 cooling-maps {
6690 map0 { 5136 map0 {
6691 trip 5137 trip = <&cpu5_bottom_alert0>;
6692 cooli 5138 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 5139 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 5140 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 5141 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 5142 };
6697 map1 { 5143 map1 {
6698 trip 5144 trip = <&cpu5_bottom_alert1>;
6699 cooli 5145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 5146 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 5147 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 5148 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 5149 };
6704 }; 5150 };
6705 }; 5151 };
6706 5152
6707 cpu6-bottom-thermal { 5153 cpu6-bottom-thermal {
6708 polling-delay-passive 5154 polling-delay-passive = <250>;
>> 5155 polling-delay = <1000>;
6709 5156
6710 thermal-sensors = <&t 5157 thermal-sensors = <&tsens0 13>;
6711 5158
6712 trips { 5159 trips {
6713 cpu6_bottom_a 5160 cpu6_bottom_alert0: trip-point0 {
6714 tempe 5161 temperature = <90000>;
6715 hyste 5162 hysteresis = <2000>;
6716 type 5163 type = "passive";
6717 }; 5164 };
6718 5165
6719 cpu6_bottom_a 5166 cpu6_bottom_alert1: trip-point1 {
6720 tempe 5167 temperature = <95000>;
6721 hyste 5168 hysteresis = <2000>;
6722 type 5169 type = "passive";
6723 }; 5170 };
6724 5171
6725 cpu6_bottom_c !! 5172 cpu6_bottom_crit: cpu_crit {
6726 tempe 5173 temperature = <110000>;
6727 hyste 5174 hysteresis = <1000>;
6728 type 5175 type = "critical";
6729 }; 5176 };
6730 }; 5177 };
6731 5178
6732 cooling-maps { 5179 cooling-maps {
6733 map0 { 5180 map0 {
6734 trip 5181 trip = <&cpu6_bottom_alert0>;
6735 cooli 5182 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 5183 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 5184 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 5185 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 5186 };
6740 map1 { 5187 map1 {
6741 trip 5188 trip = <&cpu6_bottom_alert1>;
6742 cooli 5189 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 5190 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 5191 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 5192 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 5193 };
6747 }; 5194 };
6748 }; 5195 };
6749 5196
6750 cpu7-bottom-thermal { 5197 cpu7-bottom-thermal {
6751 polling-delay-passive 5198 polling-delay-passive = <250>;
>> 5199 polling-delay = <1000>;
6752 5200
6753 thermal-sensors = <&t 5201 thermal-sensors = <&tsens0 14>;
6754 5202
6755 trips { 5203 trips {
6756 cpu7_bottom_a 5204 cpu7_bottom_alert0: trip-point0 {
6757 tempe 5205 temperature = <90000>;
6758 hyste 5206 hysteresis = <2000>;
6759 type 5207 type = "passive";
6760 }; 5208 };
6761 5209
6762 cpu7_bottom_a 5210 cpu7_bottom_alert1: trip-point1 {
6763 tempe 5211 temperature = <95000>;
6764 hyste 5212 hysteresis = <2000>;
6765 type 5213 type = "passive";
6766 }; 5214 };
6767 5215
6768 cpu7_bottom_c !! 5216 cpu7_bottom_crit: cpu_crit {
6769 tempe 5217 temperature = <110000>;
6770 hyste 5218 hysteresis = <1000>;
6771 type 5219 type = "critical";
6772 }; 5220 };
6773 }; 5221 };
6774 5222
6775 cooling-maps { 5223 cooling-maps {
6776 map0 { 5224 map0 {
6777 trip 5225 trip = <&cpu7_bottom_alert0>;
6778 cooli 5226 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 5227 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 5228 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 5229 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 5230 };
6783 map1 { 5231 map1 {
6784 trip 5232 trip = <&cpu7_bottom_alert1>;
6785 cooli 5233 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 5234 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 5235 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 5236 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 5237 };
6790 }; 5238 };
6791 }; 5239 };
6792 5240
6793 aoss0-thermal { 5241 aoss0-thermal {
6794 polling-delay-passive 5242 polling-delay-passive = <250>;
>> 5243 polling-delay = <1000>;
6795 5244
6796 thermal-sensors = <&t 5245 thermal-sensors = <&tsens0 0>;
6797 5246
6798 trips { 5247 trips {
6799 aoss0_alert0: 5248 aoss0_alert0: trip-point0 {
6800 tempe 5249 temperature = <90000>;
6801 hyste 5250 hysteresis = <2000>;
6802 type 5251 type = "hot";
6803 }; 5252 };
6804 }; 5253 };
6805 }; 5254 };
6806 5255
6807 cluster0-thermal { 5256 cluster0-thermal {
6808 polling-delay-passive 5257 polling-delay-passive = <250>;
>> 5258 polling-delay = <1000>;
6809 5259
6810 thermal-sensors = <&t 5260 thermal-sensors = <&tsens0 5>;
6811 5261
6812 trips { 5262 trips {
6813 cluster0_aler 5263 cluster0_alert0: trip-point0 {
6814 tempe 5264 temperature = <90000>;
6815 hyste 5265 hysteresis = <2000>;
6816 type 5266 type = "hot";
6817 }; 5267 };
6818 cluster0_crit !! 5268 cluster0_crit: cluster0_crit {
6819 tempe 5269 temperature = <110000>;
6820 hyste 5270 hysteresis = <2000>;
6821 type 5271 type = "critical";
6822 }; 5272 };
6823 }; 5273 };
6824 }; 5274 };
6825 5275
6826 cluster1-thermal { 5276 cluster1-thermal {
6827 polling-delay-passive 5277 polling-delay-passive = <250>;
>> 5278 polling-delay = <1000>;
6828 5279
6829 thermal-sensors = <&t 5280 thermal-sensors = <&tsens0 6>;
6830 5281
6831 trips { 5282 trips {
6832 cluster1_aler 5283 cluster1_alert0: trip-point0 {
6833 tempe 5284 temperature = <90000>;
6834 hyste 5285 hysteresis = <2000>;
6835 type 5286 type = "hot";
6836 }; 5287 };
6837 cluster1_crit !! 5288 cluster1_crit: cluster1_crit {
6838 tempe 5289 temperature = <110000>;
6839 hyste 5290 hysteresis = <2000>;
6840 type 5291 type = "critical";
6841 }; 5292 };
6842 }; 5293 };
6843 }; 5294 };
6844 5295
6845 gpu-top-thermal { 5296 gpu-top-thermal {
6846 polling-delay-passive 5297 polling-delay-passive = <250>;
>> 5298 polling-delay = <1000>;
6847 5299
6848 thermal-sensors = <&t 5300 thermal-sensors = <&tsens0 15>;
6849 5301
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 5302 trips {
6858 gpu_top_alert !! 5303 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 5304 temperature = <90000>;
6866 hyste !! 5305 hysteresis = <2000>;
6867 type 5306 type = "hot";
6868 }; 5307 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 5308 };
6876 }; 5309 };
6877 5310
6878 aoss1-thermal { 5311 aoss1-thermal {
6879 polling-delay-passive 5312 polling-delay-passive = <250>;
>> 5313 polling-delay = <1000>;
6880 5314
6881 thermal-sensors = <&t 5315 thermal-sensors = <&tsens1 0>;
6882 5316
6883 trips { 5317 trips {
6884 aoss1_alert0: 5318 aoss1_alert0: trip-point0 {
6885 tempe 5319 temperature = <90000>;
6886 hyste 5320 hysteresis = <2000>;
6887 type 5321 type = "hot";
6888 }; 5322 };
6889 }; 5323 };
6890 }; 5324 };
6891 5325
6892 wlan-thermal { 5326 wlan-thermal {
6893 polling-delay-passive 5327 polling-delay-passive = <250>;
>> 5328 polling-delay = <1000>;
6894 5329
6895 thermal-sensors = <&t 5330 thermal-sensors = <&tsens1 1>;
6896 5331
6897 trips { 5332 trips {
6898 wlan_alert0: 5333 wlan_alert0: trip-point0 {
6899 tempe 5334 temperature = <90000>;
6900 hyste 5335 hysteresis = <2000>;
6901 type 5336 type = "hot";
6902 }; 5337 };
6903 }; 5338 };
6904 }; 5339 };
6905 5340
6906 video-thermal { 5341 video-thermal {
6907 polling-delay-passive 5342 polling-delay-passive = <250>;
>> 5343 polling-delay = <1000>;
6908 5344
6909 thermal-sensors = <&t 5345 thermal-sensors = <&tsens1 2>;
6910 5346
6911 trips { 5347 trips {
6912 video_alert0: 5348 video_alert0: trip-point0 {
6913 tempe 5349 temperature = <90000>;
6914 hyste 5350 hysteresis = <2000>;
6915 type 5351 type = "hot";
6916 }; 5352 };
6917 }; 5353 };
6918 }; 5354 };
6919 5355
6920 mem-thermal { 5356 mem-thermal {
6921 polling-delay-passive 5357 polling-delay-passive = <250>;
>> 5358 polling-delay = <1000>;
6922 5359
6923 thermal-sensors = <&t 5360 thermal-sensors = <&tsens1 3>;
6924 5361
6925 trips { 5362 trips {
6926 mem_alert0: t 5363 mem_alert0: trip-point0 {
6927 tempe 5364 temperature = <90000>;
6928 hyste 5365 hysteresis = <2000>;
6929 type 5366 type = "hot";
6930 }; 5367 };
6931 }; 5368 };
6932 }; 5369 };
6933 5370
6934 q6-hvx-thermal { 5371 q6-hvx-thermal {
6935 polling-delay-passive 5372 polling-delay-passive = <250>;
>> 5373 polling-delay = <1000>;
6936 5374
6937 thermal-sensors = <&t 5375 thermal-sensors = <&tsens1 4>;
6938 5376
6939 trips { 5377 trips {
6940 q6_hvx_alert0 5378 q6_hvx_alert0: trip-point0 {
6941 tempe 5379 temperature = <90000>;
6942 hyste 5380 hysteresis = <2000>;
6943 type 5381 type = "hot";
6944 }; 5382 };
6945 }; 5383 };
6946 }; 5384 };
6947 5385
6948 camera-thermal { 5386 camera-thermal {
6949 polling-delay-passive 5387 polling-delay-passive = <250>;
>> 5388 polling-delay = <1000>;
6950 5389
6951 thermal-sensors = <&t 5390 thermal-sensors = <&tsens1 5>;
6952 5391
6953 trips { 5392 trips {
6954 camera_alert0 5393 camera_alert0: trip-point0 {
6955 tempe 5394 temperature = <90000>;
6956 hyste 5395 hysteresis = <2000>;
6957 type 5396 type = "hot";
6958 }; 5397 };
6959 }; 5398 };
6960 }; 5399 };
6961 5400
6962 compute-thermal { 5401 compute-thermal {
6963 polling-delay-passive 5402 polling-delay-passive = <250>;
>> 5403 polling-delay = <1000>;
6964 5404
6965 thermal-sensors = <&t 5405 thermal-sensors = <&tsens1 6>;
6966 5406
6967 trips { 5407 trips {
6968 compute_alert 5408 compute_alert0: trip-point0 {
6969 tempe 5409 temperature = <90000>;
6970 hyste 5410 hysteresis = <2000>;
6971 type 5411 type = "hot";
6972 }; 5412 };
6973 }; 5413 };
6974 }; 5414 };
6975 5415
6976 npu-thermal { 5416 npu-thermal {
6977 polling-delay-passive 5417 polling-delay-passive = <250>;
>> 5418 polling-delay = <1000>;
6978 5419
6979 thermal-sensors = <&t 5420 thermal-sensors = <&tsens1 7>;
6980 5421
6981 trips { 5422 trips {
6982 npu_alert0: t 5423 npu_alert0: trip-point0 {
6983 tempe 5424 temperature = <90000>;
6984 hyste 5425 hysteresis = <2000>;
6985 type 5426 type = "hot";
6986 }; 5427 };
6987 }; 5428 };
6988 }; 5429 };
6989 5430
6990 gpu-bottom-thermal { 5431 gpu-bottom-thermal {
6991 polling-delay-passive 5432 polling-delay-passive = <250>;
>> 5433 polling-delay = <1000>;
6992 5434
6993 thermal-sensors = <&t 5435 thermal-sensors = <&tsens1 8>;
6994 5436
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 5437 trips {
7003 gpu_bottom_al !! 5438 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 5439 temperature = <90000>;
7011 hyste !! 5440 hysteresis = <2000>;
7012 type 5441 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 5442 };
7020 }; 5443 };
7021 }; 5444 };
7022 }; 5445 };
7023 }; 5446 };
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