1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 14 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 16 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 17 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 19 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 20 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 21 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 22 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 23
26 / { 24 / {
27 interrupt-parent = <&intc>; 25 interrupt-parent = <&intc>;
28 26
29 #address-cells = <2>; 27 #address-cells = <2>;
30 #size-cells = <2>; 28 #size-cells = <2>;
31 29
32 aliases { 30 aliases {
33 i2c0 = &i2c0; 31 i2c0 = &i2c0;
34 i2c1 = &i2c1; 32 i2c1 = &i2c1;
35 i2c2 = &i2c2; 33 i2c2 = &i2c2;
36 i2c3 = &i2c3; 34 i2c3 = &i2c3;
37 i2c4 = &i2c4; 35 i2c4 = &i2c4;
38 i2c5 = &i2c5; 36 i2c5 = &i2c5;
39 i2c6 = &i2c6; 37 i2c6 = &i2c6;
40 i2c7 = &i2c7; 38 i2c7 = &i2c7;
41 i2c8 = &i2c8; 39 i2c8 = &i2c8;
42 i2c9 = &i2c9; 40 i2c9 = &i2c9;
43 i2c10 = &i2c10; 41 i2c10 = &i2c10;
44 i2c11 = &i2c11; 42 i2c11 = &i2c11;
45 i2c12 = &i2c12; 43 i2c12 = &i2c12;
46 i2c13 = &i2c13; 44 i2c13 = &i2c13;
47 i2c14 = &i2c14; 45 i2c14 = &i2c14;
48 i2c15 = &i2c15; 46 i2c15 = &i2c15;
49 i2c16 = &i2c16; 47 i2c16 = &i2c16;
50 i2c17 = &i2c17; 48 i2c17 = &i2c17;
51 i2c18 = &i2c18; 49 i2c18 = &i2c18;
52 i2c19 = &i2c19; 50 i2c19 = &i2c19;
53 spi0 = &spi0; 51 spi0 = &spi0;
54 spi1 = &spi1; 52 spi1 = &spi1;
55 spi2 = &spi2; 53 spi2 = &spi2;
56 spi3 = &spi3; 54 spi3 = &spi3;
57 spi4 = &spi4; 55 spi4 = &spi4;
58 spi5 = &spi5; 56 spi5 = &spi5;
59 spi6 = &spi6; 57 spi6 = &spi6;
60 spi7 = &spi7; 58 spi7 = &spi7;
61 spi8 = &spi8; 59 spi8 = &spi8;
62 spi9 = &spi9; 60 spi9 = &spi9;
63 spi10 = &spi10; 61 spi10 = &spi10;
64 spi11 = &spi11; 62 spi11 = &spi11;
65 spi12 = &spi12; 63 spi12 = &spi12;
66 spi13 = &spi13; 64 spi13 = &spi13;
67 spi14 = &spi14; 65 spi14 = &spi14;
68 spi15 = &spi15; 66 spi15 = &spi15;
69 spi16 = &spi16; 67 spi16 = &spi16;
70 spi17 = &spi17; 68 spi17 = &spi17;
71 spi18 = &spi18; 69 spi18 = &spi18;
72 spi19 = &spi19; 70 spi19 = &spi19;
73 }; 71 };
74 72
75 chosen { }; 73 chosen { };
76 74
77 clocks { 75 clocks {
78 xo_board: xo-board { 76 xo_board: xo-board {
79 compatible = "fixed-cl 77 compatible = "fixed-clock";
80 #clock-cells = <0>; 78 #clock-cells = <0>;
81 clock-frequency = <384 79 clock-frequency = <38400000>;
82 clock-output-names = " 80 clock-output-names = "xo_board";
83 }; 81 };
84 82
85 sleep_clk: sleep-clk { 83 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 84 compatible = "fixed-clock";
87 clock-frequency = <327 85 clock-frequency = <32768>;
88 #clock-cells = <0>; 86 #clock-cells = <0>;
89 }; 87 };
90 }; 88 };
91 89
92 cpus { 90 cpus {
93 #address-cells = <2>; 91 #address-cells = <2>;
94 #size-cells = <0>; 92 #size-cells = <0>;
95 93
96 CPU0: cpu@0 { 94 CPU0: cpu@0 {
97 device_type = "cpu"; 95 device_type = "cpu";
98 compatible = "qcom,kry 96 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 97 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 98 enable-method = "psci";
102 capacity-dmips-mhz = < 99 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 100 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 101 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 102 power-domains = <&CPU_PD0>;
106 power-domain-names = " 103 power-domain-names = "psci";
107 qcom,freq-domain = <&c 104 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 105 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ !! 106 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
110 <&epss 107 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 108 #cooling-cells = <2>;
112 L2_0: l2-cache { 109 L2_0: l2-cache {
113 compatible = " 110 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 111 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 112 L3_0: l3-cache {
119 compat 113 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 114 };
124 }; 115 };
125 }; 116 };
126 117
127 CPU1: cpu@100 { 118 CPU1: cpu@100 {
128 device_type = "cpu"; 119 device_type = "cpu";
129 compatible = "qcom,kry 120 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 121 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 122 enable-method = "psci";
133 capacity-dmips-mhz = < 123 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 124 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 125 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 126 power-domains = <&CPU_PD1>;
137 power-domain-names = " 127 power-domain-names = "psci";
138 qcom,freq-domain = <&c 128 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 129 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ !! 130 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
141 <&epss 131 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 132 #cooling-cells = <2>;
143 L2_100: l2-cache { 133 L2_100: l2-cache {
144 compatible = " 134 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 135 next-level-cache = <&L3_0>;
149 }; 136 };
150 }; 137 };
151 138
152 CPU2: cpu@200 { 139 CPU2: cpu@200 {
153 device_type = "cpu"; 140 device_type = "cpu";
154 compatible = "qcom,kry 141 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 142 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 143 enable-method = "psci";
158 capacity-dmips-mhz = < 144 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 145 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 146 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 147 power-domains = <&CPU_PD2>;
162 power-domain-names = " 148 power-domain-names = "psci";
163 qcom,freq-domain = <&c 149 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 150 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ !! 151 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
166 <&epss 152 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 153 #cooling-cells = <2>;
168 L2_200: l2-cache { 154 L2_200: l2-cache {
169 compatible = " 155 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 156 next-level-cache = <&L3_0>;
174 }; 157 };
175 }; 158 };
176 159
177 CPU3: cpu@300 { 160 CPU3: cpu@300 {
178 device_type = "cpu"; 161 device_type = "cpu";
179 compatible = "qcom,kry 162 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 163 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 164 enable-method = "psci";
183 capacity-dmips-mhz = < 165 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 166 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 167 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 168 power-domains = <&CPU_PD3>;
187 power-domain-names = " 169 power-domain-names = "psci";
188 qcom,freq-domain = <&c 170 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 171 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ !! 172 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
191 <&epss 173 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 174 #cooling-cells = <2>;
193 L2_300: l2-cache { 175 L2_300: l2-cache {
194 compatible = " 176 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 177 next-level-cache = <&L3_0>;
199 }; 178 };
200 }; 179 };
201 180
202 CPU4: cpu@400 { 181 CPU4: cpu@400 {
203 device_type = "cpu"; 182 device_type = "cpu";
204 compatible = "qcom,kry 183 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 184 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 185 enable-method = "psci";
208 capacity-dmips-mhz = < 186 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 187 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 188 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 189 power-domains = <&CPU_PD4>;
212 power-domain-names = " 190 power-domain-names = "psci";
213 qcom,freq-domain = <&c 191 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 192 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ !! 193 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
216 <&epss 194 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 195 #cooling-cells = <2>;
218 L2_400: l2-cache { 196 L2_400: l2-cache {
219 compatible = " 197 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 198 next-level-cache = <&L3_0>;
224 }; 199 };
225 }; 200 };
226 201
227 CPU5: cpu@500 { 202 CPU5: cpu@500 {
228 device_type = "cpu"; 203 device_type = "cpu";
229 compatible = "qcom,kry 204 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 205 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 206 enable-method = "psci";
233 capacity-dmips-mhz = < 207 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 208 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 209 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 210 power-domains = <&CPU_PD5>;
237 power-domain-names = " 211 power-domain-names = "psci";
238 qcom,freq-domain = <&c 212 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 213 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ !! 214 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
241 <&epss 215 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 216 #cooling-cells = <2>;
243 L2_500: l2-cache { 217 L2_500: l2-cache {
244 compatible = " 218 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 219 next-level-cache = <&L3_0>;
249 }; 220 };
>> 221
250 }; 222 };
251 223
252 CPU6: cpu@600 { 224 CPU6: cpu@600 {
253 device_type = "cpu"; 225 device_type = "cpu";
254 compatible = "qcom,kry 226 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 227 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 228 enable-method = "psci";
258 capacity-dmips-mhz = < 229 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 230 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 231 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 232 power-domains = <&CPU_PD6>;
262 power-domain-names = " 233 power-domain-names = "psci";
263 qcom,freq-domain = <&c 234 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 235 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ !! 236 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
266 <&epss 237 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 238 #cooling-cells = <2>;
268 L2_600: l2-cache { 239 L2_600: l2-cache {
269 compatible = " 240 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 241 next-level-cache = <&L3_0>;
274 }; 242 };
275 }; 243 };
276 244
277 CPU7: cpu@700 { 245 CPU7: cpu@700 {
278 device_type = "cpu"; 246 device_type = "cpu";
279 compatible = "qcom,kry 247 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 248 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 249 enable-method = "psci";
283 capacity-dmips-mhz = < 250 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 251 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 252 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 253 power-domains = <&CPU_PD7>;
287 power-domain-names = " 254 power-domain-names = "psci";
288 qcom,freq-domain = <&c 255 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 256 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ !! 257 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
291 <&epss 258 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 259 #cooling-cells = <2>;
293 L2_700: l2-cache { 260 L2_700: l2-cache {
294 compatible = " 261 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 262 next-level-cache = <&L3_0>;
299 }; 263 };
300 }; 264 };
301 265
302 cpu-map { 266 cpu-map {
303 cluster0 { 267 cluster0 {
304 core0 { 268 core0 {
305 cpu = 269 cpu = <&CPU0>;
306 }; 270 };
307 271
308 core1 { 272 core1 {
309 cpu = 273 cpu = <&CPU1>;
310 }; 274 };
311 275
312 core2 { 276 core2 {
313 cpu = 277 cpu = <&CPU2>;
314 }; 278 };
315 279
316 core3 { 280 core3 {
317 cpu = 281 cpu = <&CPU3>;
318 }; 282 };
319 283
320 core4 { 284 core4 {
321 cpu = 285 cpu = <&CPU4>;
322 }; 286 };
323 287
324 core5 { 288 core5 {
325 cpu = 289 cpu = <&CPU5>;
326 }; 290 };
327 291
328 core6 { 292 core6 {
329 cpu = 293 cpu = <&CPU6>;
330 }; 294 };
331 295
332 core7 { 296 core7 {
333 cpu = 297 cpu = <&CPU7>;
334 }; 298 };
335 }; 299 };
336 }; 300 };
337 301
338 idle-states { 302 idle-states {
339 entry-method = "psci"; 303 entry-method = "psci";
340 304
341 LITTLE_CPU_SLEEP_0: cp 305 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 306 compatible = "arm,idle-state";
343 idle-state-nam 307 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 308 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 309 entry-latency-us = <360>;
346 exit-latency-u 310 exit-latency-us = <531>;
347 min-residency- 311 min-residency-us = <3934>;
348 local-timer-st 312 local-timer-stop;
349 }; 313 };
350 314
351 BIG_CPU_SLEEP_0: cpu-s 315 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 316 compatible = "arm,idle-state";
353 idle-state-nam 317 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 318 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 319 entry-latency-us = <702>;
356 exit-latency-u 320 exit-latency-us = <1061>;
357 min-residency- 321 min-residency-us = <4488>;
358 local-timer-st 322 local-timer-stop;
359 }; 323 };
360 }; 324 };
361 325
362 domain-idle-states { 326 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 327 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 328 compatible = "domain-idle-state";
>> 329 idle-state-name = "cluster-llcc-off";
365 arm,psci-suspe 330 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 331 entry-latency-us = <3264>;
367 exit-latency-u 332 exit-latency-us = <6562>;
368 min-residency- 333 min-residency-us = <9987>;
>> 334 local-timer-stop;
369 }; 335 };
370 }; 336 };
371 }; 337 };
372 338
373 qup_virt: interconnect-qup-virt { !! 339 cpu0_opp_table: cpu0_opp_table {
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { <<
380 compatible = "operating-points 340 compatible = "operating-points-v2";
381 opp-shared; 341 opp-shared;
382 342
383 cpu0_opp1: opp-300000000 { 343 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 344 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 345 opp-peak-kBps = <800000 9600000>;
386 }; 346 };
387 347
388 cpu0_opp2: opp-403200000 { 348 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 349 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 350 opp-peak-kBps = <800000 9600000>;
391 }; 351 };
392 352
393 cpu0_opp3: opp-518400000 { 353 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 354 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 355 opp-peak-kBps = <800000 16588800>;
396 }; 356 };
397 357
398 cpu0_opp4: opp-614400000 { 358 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 359 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 360 opp-peak-kBps = <800000 16588800>;
401 }; 361 };
402 362
403 cpu0_opp5: opp-691200000 { 363 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 364 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 365 opp-peak-kBps = <800000 19660800>;
406 }; 366 };
407 367
408 cpu0_opp6: opp-787200000 { 368 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 369 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 370 opp-peak-kBps = <1804000 19660800>;
411 }; 371 };
412 372
413 cpu0_opp7: opp-883200000 { 373 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 374 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 375 opp-peak-kBps = <1804000 23347200>;
416 }; 376 };
417 377
418 cpu0_opp8: opp-979200000 { 378 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 379 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 380 opp-peak-kBps = <1804000 26419200>;
421 }; 381 };
422 382
423 cpu0_opp9: opp-1075200000 { 383 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 384 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 385 opp-peak-kBps = <1804000 29491200>;
426 }; 386 };
427 387
428 cpu0_opp10: opp-1171200000 { 388 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 389 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 390 opp-peak-kBps = <1804000 32563200>;
431 }; 391 };
432 392
433 cpu0_opp11: opp-1248000000 { 393 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 394 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 395 opp-peak-kBps = <1804000 36249600>;
436 }; 396 };
437 397
438 cpu0_opp12: opp-1344000000 { 398 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 399 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 400 opp-peak-kBps = <2188000 36249600>;
441 }; 401 };
442 402
443 cpu0_opp13: opp-1420800000 { 403 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 404 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 405 opp-peak-kBps = <2188000 39321600>;
446 }; 406 };
447 407
448 cpu0_opp14: opp-1516800000 { 408 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 409 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 410 opp-peak-kBps = <3072000 42393600>;
451 }; 411 };
452 412
453 cpu0_opp15: opp-1612800000 { 413 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 414 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 415 opp-peak-kBps = <3072000 42393600>;
456 }; 416 };
457 417
458 cpu0_opp16: opp-1708800000 { 418 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 419 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 420 opp-peak-kBps = <4068000 42393600>;
461 }; 421 };
462 422
463 cpu0_opp17: opp-1804800000 { 423 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 424 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 425 opp-peak-kBps = <4068000 42393600>;
466 }; 426 };
467 }; 427 };
468 428
469 cpu4_opp_table: opp-table-cpu4 { !! 429 cpu4_opp_table: cpu4_opp_table {
470 compatible = "operating-points 430 compatible = "operating-points-v2";
471 opp-shared; 431 opp-shared;
472 432
473 cpu4_opp1: opp-710400000 { 433 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 434 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 435 opp-peak-kBps = <1804000 19660800>;
476 }; 436 };
477 437
478 cpu4_opp2: opp-825600000 { 438 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 439 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 440 opp-peak-kBps = <2188000 23347200>;
481 }; 441 };
482 442
483 cpu4_opp3: opp-940800000 { 443 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 444 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 445 opp-peak-kBps = <2188000 26419200>;
486 }; 446 };
487 447
488 cpu4_opp4: opp-1056000000 { 448 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 449 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 450 opp-peak-kBps = <3072000 26419200>;
491 }; 451 };
492 452
493 cpu4_opp5: opp-1171200000 { 453 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 454 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 455 opp-peak-kBps = <3072000 29491200>;
496 }; 456 };
497 457
498 cpu4_opp6: opp-1286400000 { 458 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 459 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 460 opp-peak-kBps = <4068000 29491200>;
501 }; 461 };
502 462
503 cpu4_opp7: opp-1382400000 { 463 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 464 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 465 opp-peak-kBps = <4068000 32563200>;
506 }; 466 };
507 467
508 cpu4_opp8: opp-1478400000 { 468 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 469 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 470 opp-peak-kBps = <4068000 32563200>;
511 }; 471 };
512 472
513 cpu4_opp9: opp-1574400000 { 473 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 474 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 475 opp-peak-kBps = <5412000 39321600>;
516 }; 476 };
517 477
518 cpu4_opp10: opp-1670400000 { 478 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 479 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 480 opp-peak-kBps = <5412000 42393600>;
521 }; 481 };
522 482
523 cpu4_opp11: opp-1766400000 { 483 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 484 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 485 opp-peak-kBps = <5412000 45465600>;
526 }; 486 };
527 487
528 cpu4_opp12: opp-1862400000 { 488 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 489 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 490 opp-peak-kBps = <6220000 45465600>;
531 }; 491 };
532 492
533 cpu4_opp13: opp-1958400000 { 493 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 494 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 495 opp-peak-kBps = <6220000 48537600>;
536 }; 496 };
537 497
538 cpu4_opp14: opp-2054400000 { 498 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 499 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 500 opp-peak-kBps = <7216000 48537600>;
541 }; 501 };
542 502
543 cpu4_opp15: opp-2150400000 { 503 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 504 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 505 opp-peak-kBps = <7216000 51609600>;
546 }; 506 };
547 507
548 cpu4_opp16: opp-2246400000 { 508 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 509 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 510 opp-peak-kBps = <7216000 51609600>;
551 }; 511 };
552 512
553 cpu4_opp17: opp-2342400000 { 513 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 514 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 515 opp-peak-kBps = <8368000 51609600>;
556 }; 516 };
557 517
558 cpu4_opp18: opp-2419200000 { 518 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 519 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 520 opp-peak-kBps = <8368000 51609600>;
561 }; 521 };
562 }; 522 };
563 523
564 cpu7_opp_table: opp-table-cpu7 { !! 524 cpu7_opp_table: cpu7_opp_table {
565 compatible = "operating-points 525 compatible = "operating-points-v2";
566 opp-shared; 526 opp-shared;
567 527
568 cpu7_opp1: opp-844800000 { 528 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 529 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 530 opp-peak-kBps = <2188000 19660800>;
571 }; 531 };
572 532
573 cpu7_opp2: opp-960000000 { 533 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 534 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 535 opp-peak-kBps = <2188000 26419200>;
576 }; 536 };
577 537
578 cpu7_opp3: opp-1075200000 { 538 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 539 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 540 opp-peak-kBps = <3072000 26419200>;
581 }; 541 };
582 542
583 cpu7_opp4: opp-1190400000 { 543 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 544 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 545 opp-peak-kBps = <3072000 29491200>;
586 }; 546 };
587 547
588 cpu7_opp5: opp-1305600000 { 548 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 549 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 550 opp-peak-kBps = <4068000 32563200>;
591 }; 551 };
592 552
593 cpu7_opp6: opp-1401600000 { 553 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 554 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 555 opp-peak-kBps = <4068000 32563200>;
596 }; 556 };
597 557
598 cpu7_opp7: opp-1516800000 { 558 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 559 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 560 opp-peak-kBps = <4068000 36249600>;
601 }; 561 };
602 562
603 cpu7_opp8: opp-1632000000 { 563 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 564 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 565 opp-peak-kBps = <5412000 39321600>;
606 }; 566 };
607 567
608 cpu7_opp9: opp-1747200000 { 568 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 569 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 570 opp-peak-kBps = <5412000 42393600>;
611 }; 571 };
612 572
613 cpu7_opp10: opp-1862400000 { 573 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 574 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 575 opp-peak-kBps = <6220000 45465600>;
616 }; 576 };
617 577
618 cpu7_opp11: opp-1977600000 { 578 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 579 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 580 opp-peak-kBps = <6220000 48537600>;
621 }; 581 };
622 582
623 cpu7_opp12: opp-2073600000 { 583 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 584 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 585 opp-peak-kBps = <7216000 48537600>;
626 }; 586 };
627 587
628 cpu7_opp13: opp-2169600000 { 588 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 589 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 590 opp-peak-kBps = <7216000 51609600>;
631 }; 591 };
632 592
633 cpu7_opp14: opp-2265600000 { 593 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 594 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 595 opp-peak-kBps = <7216000 51609600>;
636 }; 596 };
637 597
638 cpu7_opp15: opp-2361600000 { 598 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 599 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 600 opp-peak-kBps = <8368000 51609600>;
641 }; 601 };
642 602
643 cpu7_opp16: opp-2457600000 { 603 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 604 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 605 opp-peak-kBps = <8368000 51609600>;
646 }; 606 };
647 607
648 cpu7_opp17: opp-2553600000 { 608 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 609 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 610 opp-peak-kBps = <8368000 51609600>;
651 }; 611 };
652 612
653 cpu7_opp18: opp-2649600000 { 613 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 614 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 615 opp-peak-kBps = <8368000 51609600>;
656 }; 616 };
657 617
658 cpu7_opp19: opp-2745600000 { 618 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 619 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 620 opp-peak-kBps = <8368000 51609600>;
661 }; 621 };
662 622
663 cpu7_opp20: opp-2841600000 { 623 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 624 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 625 opp-peak-kBps = <8368000 51609600>;
666 }; 626 };
667 }; 627 };
668 628
669 firmware { 629 firmware {
670 scm: scm { 630 scm: scm {
671 compatible = "qcom,scm !! 631 compatible = "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 632 #reset-cells = <1>;
674 }; 633 };
675 }; 634 };
676 635
677 memory@80000000 { 636 memory@80000000 {
678 device_type = "memory"; 637 device_type = "memory";
679 /* We expect the bootloader to 638 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 639 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 640 };
682 641
683 pmu { 642 pmu {
684 compatible = "arm,armv8-pmuv3" 643 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 644 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 645 };
687 646
688 psci { 647 psci {
689 compatible = "arm,psci-1.0"; 648 compatible = "arm,psci-1.0";
690 method = "smc"; 649 method = "smc";
691 650
692 CPU_PD0: power-domain-cpu0 { !! 651 CPU_PD0: cpu0 {
693 #power-domain-cells = 652 #power-domain-cells = <0>;
694 power-domains = <&CLUS 653 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 654 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 655 };
697 656
698 CPU_PD1: power-domain-cpu1 { !! 657 CPU_PD1: cpu1 {
699 #power-domain-cells = 658 #power-domain-cells = <0>;
700 power-domains = <&CLUS 659 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 660 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 661 };
703 662
704 CPU_PD2: power-domain-cpu2 { !! 663 CPU_PD2: cpu2 {
705 #power-domain-cells = 664 #power-domain-cells = <0>;
706 power-domains = <&CLUS 665 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 666 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 667 };
709 668
710 CPU_PD3: power-domain-cpu3 { !! 669 CPU_PD3: cpu3 {
711 #power-domain-cells = 670 #power-domain-cells = <0>;
712 power-domains = <&CLUS 671 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 672 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 673 };
715 674
716 CPU_PD4: power-domain-cpu4 { !! 675 CPU_PD4: cpu4 {
717 #power-domain-cells = 676 #power-domain-cells = <0>;
718 power-domains = <&CLUS 677 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 678 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 679 };
721 680
722 CPU_PD5: power-domain-cpu5 { !! 681 CPU_PD5: cpu5 {
723 #power-domain-cells = 682 #power-domain-cells = <0>;
724 power-domains = <&CLUS 683 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 684 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 685 };
727 686
728 CPU_PD6: power-domain-cpu6 { !! 687 CPU_PD6: cpu6 {
729 #power-domain-cells = 688 #power-domain-cells = <0>;
730 power-domains = <&CLUS 689 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 690 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 691 };
733 692
734 CPU_PD7: power-domain-cpu7 { !! 693 CPU_PD7: cpu7 {
735 #power-domain-cells = 694 #power-domain-cells = <0>;
736 power-domains = <&CLUS 695 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 696 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 697 };
739 698
740 CLUSTER_PD: power-domain-cpu-c !! 699 CLUSTER_PD: cpu-cluster0 {
741 #power-domain-cells = 700 #power-domain-cells = <0>;
742 domain-idle-states = < 701 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 702 };
744 }; 703 };
745 704
746 qup_opp_table: opp-table-qup { <<
747 compatible = "operating-points <<
748 <<
749 opp-50000000 { <<
750 opp-hz = /bits/ 64 <50 <<
751 required-opps = <&rpmh <<
752 }; <<
753 <<
754 opp-75000000 { <<
755 opp-hz = /bits/ 64 <75 <<
756 required-opps = <&rpmh <<
757 }; <<
758 <<
759 opp-120000000 { <<
760 opp-hz = /bits/ 64 <12 <<
761 required-opps = <&rpmh <<
762 }; <<
763 }; <<
764 <<
765 reserved-memory { 705 reserved-memory {
766 #address-cells = <2>; 706 #address-cells = <2>;
767 #size-cells = <2>; 707 #size-cells = <2>;
768 ranges; 708 ranges;
769 709
770 hyp_mem: memory@80000000 { 710 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 711 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 712 no-map;
773 }; 713 };
774 714
775 xbl_aop_mem: memory@80700000 { 715 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 716 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 717 no-map;
778 }; 718 };
779 719
780 cmd_db: memory@80860000 { 720 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 721 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 722 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 723 no-map;
784 }; 724 };
785 725
786 smem_mem: memory@80900000 { 726 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 727 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 728 no-map;
789 }; 729 };
790 730
791 removed_mem: memory@80b00000 { 731 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 732 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 733 no-map;
794 }; 734 };
795 735
796 camera_mem: memory@86200000 { 736 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 737 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 738 no-map;
799 }; 739 };
800 740
801 wlan_mem: memory@86700000 { 741 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 742 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 743 no-map;
804 }; 744 };
805 745
806 ipa_fw_mem: memory@86800000 { 746 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 747 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 748 no-map;
809 }; 749 };
810 750
811 ipa_gsi_mem: memory@86810000 { 751 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 752 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 753 no-map;
814 }; 754 };
815 755
816 gpu_mem: memory@8681a000 { 756 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 757 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 758 no-map;
819 }; 759 };
820 760
821 npu_mem: memory@86900000 { 761 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 762 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 763 no-map;
824 }; 764 };
825 765
826 video_mem: memory@86e00000 { 766 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 767 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 768 no-map;
829 }; 769 };
830 770
831 cvp_mem: memory@87300000 { 771 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 772 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 773 no-map;
834 }; 774 };
835 775
836 cdsp_mem: memory@87800000 { 776 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 777 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 778 no-map;
839 }; 779 };
840 780
841 slpi_mem: memory@88c00000 { 781 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 782 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 783 no-map;
844 }; 784 };
845 785
846 adsp_mem: memory@8a100000 { 786 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 787 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 788 no-map;
849 }; 789 };
850 790
851 spss_mem: memory@8be00000 { 791 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 792 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 793 no-map;
854 }; 794 };
855 795
856 cdsp_secure_heap: memory@8bf00 796 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 797 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 798 no-map;
859 }; 799 };
860 }; 800 };
861 801
862 smem { 802 smem {
863 compatible = "qcom,smem"; 803 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 804 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 805 hwlocks = <&tcsr_mutex 3>;
866 }; 806 };
867 807
868 smp2p-adsp { 808 smp2p-adsp {
869 compatible = "qcom,smp2p"; 809 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 810 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 811 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 812 IPCC_MPROC_SIGNAL_SMP2P
873 I 813 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 814 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 815 IPCC_MPROC_SIGNAL_SMP2P>;
876 816
877 qcom,local-pid = <0>; 817 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 818 qcom,remote-pid = <2>;
879 819
880 smp2p_adsp_out: master-kernel 820 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 821 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 822 #qcom,smem-state-cells = <1>;
883 }; 823 };
884 824
885 smp2p_adsp_in: slave-kernel { 825 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 826 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 827 interrupt-controller;
888 #interrupt-cells = <2> 828 #interrupt-cells = <2>;
889 }; 829 };
890 }; 830 };
891 831
892 smp2p-cdsp { 832 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 833 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 834 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 835 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 836 IPCC_MPROC_SIGNAL_SMP2P
897 I 837 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 838 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 839 IPCC_MPROC_SIGNAL_SMP2P>;
900 840
901 qcom,local-pid = <0>; 841 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 842 qcom,remote-pid = <5>;
903 843
904 smp2p_cdsp_out: master-kernel 844 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 845 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 846 #qcom,smem-state-cells = <1>;
907 }; 847 };
908 848
909 smp2p_cdsp_in: slave-kernel { 849 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 850 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 851 interrupt-controller;
912 #interrupt-cells = <2> 852 #interrupt-cells = <2>;
913 }; 853 };
914 }; 854 };
915 855
916 smp2p-slpi { 856 smp2p-slpi {
917 compatible = "qcom,smp2p"; 857 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 858 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 859 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 860 IPCC_MPROC_SIGNAL_SMP2P
921 I 861 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 862 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 863 IPCC_MPROC_SIGNAL_SMP2P>;
924 864
925 qcom,local-pid = <0>; 865 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 866 qcom,remote-pid = <3>;
927 867
928 smp2p_slpi_out: master-kernel 868 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 869 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 870 #qcom,smem-state-cells = <1>;
931 }; 871 };
932 872
933 smp2p_slpi_in: slave-kernel { 873 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 874 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 875 interrupt-controller;
936 #interrupt-cells = <2> 876 #interrupt-cells = <2>;
937 }; 877 };
938 }; 878 };
939 879
940 soc: soc@0 { 880 soc: soc@0 {
941 #address-cells = <2>; 881 #address-cells = <2>;
942 #size-cells = <2>; 882 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 883 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 884 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 885 compatible = "simple-bus";
946 886
947 gcc: clock-controller@100000 { 887 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 888 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 889 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 890 #clock-cells = <1>;
951 #reset-cells = <1>; 891 #reset-cells = <1>;
952 #power-domain-cells = 892 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 893 clock-names = "bi_tcxo",
954 "bi_tcxo 894 "bi_tcxo_ao",
955 "sleep_c 895 "sleep_clk";
956 clocks = <&rpmhcc RPMH 896 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 897 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 898 <&sleep_clk>;
959 }; 899 };
960 900
961 ipcc: mailbox@408000 { 901 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 902 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 903 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 904 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 905 interrupt-controller;
966 #interrupt-cells = <3> 906 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 907 #mbox-cells = <2>;
968 }; 908 };
969 909
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 910 rng: rng@793000 {
983 compatible = "qcom,prn 911 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 912 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 913 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 914 clock-names = "core";
987 }; 915 };
988 916
>> 917 qup_opp_table: qup-opp-table {
>> 918 compatible = "operating-points-v2";
>> 919
>> 920 opp-50000000 {
>> 921 opp-hz = /bits/ 64 <50000000>;
>> 922 required-opps = <&rpmhpd_opp_min_svs>;
>> 923 };
>> 924
>> 925 opp-75000000 {
>> 926 opp-hz = /bits/ 64 <75000000>;
>> 927 required-opps = <&rpmhpd_opp_low_svs>;
>> 928 };
>> 929
>> 930 opp-120000000 {
>> 931 opp-hz = /bits/ 64 <120000000>;
>> 932 required-opps = <&rpmhpd_opp_svs>;
>> 933 };
>> 934 };
>> 935
989 gpi_dma2: dma-controller@80000 936 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 !! 937 compatible = "qcom,sm8250-gpi-dma";
991 reg = <0 0x00800000 0 938 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 939 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 940 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 941 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 942 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 943 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 944 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 945 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 946 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 947 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 948 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 949 dma-channels = <10>;
1003 dma-channel-mask = <0 950 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 951 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 952 #dma-cells = <3>;
1006 status = "disabled"; 953 status = "disabled";
1007 }; 954 };
1008 955
1009 qupv3_id_2: geniqup@8c0000 { 956 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 957 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 958 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 959 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 960 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 961 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 962 #address-cells = <2>;
1016 #size-cells = <2>; 963 #size-cells = <2>;
1017 iommus = <&apps_smmu 964 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 965 ranges;
1019 status = "disabled"; 966 status = "disabled";
1020 967
1021 i2c14: i2c@880000 { 968 i2c14: i2c@880000 {
1022 compatible = 969 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 970 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 971 clock-names = "se";
1025 clocks = <&gc 972 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 973 pinctrl-names = "default";
1027 pinctrl-0 = < 974 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 975 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 976 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 977 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 978 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 979 #address-cells = <1>;
1040 #size-cells = 980 #size-cells = <0>;
1041 status = "dis 981 status = "disabled";
1042 }; 982 };
1043 983
1044 spi14: spi@880000 { 984 spi14: spi@880000 {
1045 compatible = 985 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 986 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 987 clock-names = "se";
1048 clocks = <&gc 988 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 989 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 990 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 991 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 992 dma-names = "tx", "rx";
1053 power-domains !! 993 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 994 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 995 #address-cells = <1>;
1062 #size-cells = 996 #size-cells = <0>;
1063 status = "dis 997 status = "disabled";
1064 }; 998 };
1065 999
1066 i2c15: i2c@884000 { 1000 i2c15: i2c@884000 {
1067 compatible = 1001 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1002 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1003 clock-names = "se";
1070 clocks = <&gc 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1005 pinctrl-names = "default";
1072 pinctrl-0 = < 1006 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1007 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1008 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1009 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1010 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 1011 #address-cells = <1>;
1085 #size-cells = 1012 #size-cells = <0>;
1086 status = "dis 1013 status = "disabled";
1087 }; 1014 };
1088 1015
1089 spi15: spi@884000 { 1016 spi15: spi@884000 {
1090 compatible = 1017 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1018 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1019 clock-names = "se";
1093 clocks = <&gc 1020 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1021 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1022 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1023 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1024 dma-names = "tx", "rx";
1098 power-domains !! 1025 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 1026 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 1027 #address-cells = <1>;
1107 #size-cells = 1028 #size-cells = <0>;
1108 status = "dis 1029 status = "disabled";
1109 }; 1030 };
1110 1031
1111 i2c16: i2c@888000 { 1032 i2c16: i2c@888000 {
1112 compatible = 1033 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1034 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1035 clock-names = "se";
1115 clocks = <&gc 1036 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1037 pinctrl-names = "default";
1117 pinctrl-0 = < 1038 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1039 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1040 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1041 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1042 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 1043 #address-cells = <1>;
1130 #size-cells = 1044 #size-cells = <0>;
1131 status = "dis 1045 status = "disabled";
1132 }; 1046 };
1133 1047
1134 spi16: spi@888000 { 1048 spi16: spi@888000 {
1135 compatible = 1049 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1050 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1051 clock-names = "se";
1138 clocks = <&gc 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1053 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1054 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1055 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1056 dma-names = "tx", "rx";
1143 power-domains !! 1057 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 1058 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 1059 #address-cells = <1>;
1152 #size-cells = 1060 #size-cells = <0>;
1153 status = "dis 1061 status = "disabled";
1154 }; 1062 };
1155 1063
1156 i2c17: i2c@88c000 { 1064 i2c17: i2c@88c000 {
1157 compatible = 1065 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1066 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1067 clock-names = "se";
1160 clocks = <&gc 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1069 pinctrl-names = "default";
1162 pinctrl-0 = < 1070 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1071 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1072 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1073 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1074 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 1075 #address-cells = <1>;
1175 #size-cells = 1076 #size-cells = <0>;
1176 status = "dis 1077 status = "disabled";
1177 }; 1078 };
1178 1079
1179 spi17: spi@88c000 { 1080 spi17: spi@88c000 {
1180 compatible = 1081 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1082 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1083 clock-names = "se";
1183 clocks = <&gc 1084 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1085 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1086 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1087 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1088 dma-names = "tx", "rx";
1188 power-domains !! 1089 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 1090 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 1091 #address-cells = <1>;
1197 #size-cells = 1092 #size-cells = <0>;
1198 status = "dis 1093 status = "disabled";
1199 }; 1094 };
1200 1095
1201 uart17: serial@88c000 1096 uart17: serial@88c000 {
1202 compatible = 1097 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1098 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1099 clock-names = "se";
1205 clocks = <&gc 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1101 pinctrl-names = "default";
1207 pinctrl-0 = < 1102 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1103 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 1104 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 1105 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1106 status = "disabled";
1216 }; 1107 };
1217 1108
1218 i2c18: i2c@890000 { 1109 i2c18: i2c@890000 {
1219 compatible = 1110 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1111 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1112 clock-names = "se";
1222 clocks = <&gc 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1114 pinctrl-names = "default";
1224 pinctrl-0 = < 1115 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1116 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1117 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1118 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1119 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1120 #address-cells = <1>;
1237 #size-cells = 1121 #size-cells = <0>;
1238 status = "dis 1122 status = "disabled";
1239 }; 1123 };
1240 1124
1241 spi18: spi@890000 { 1125 spi18: spi@890000 {
1242 compatible = 1126 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1127 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1128 clock-names = "se";
1245 clocks = <&gc 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1130 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1131 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1132 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1133 dma-names = "tx", "rx";
1250 power-domains !! 1134 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 1135 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1136 #address-cells = <1>;
1259 #size-cells = 1137 #size-cells = <0>;
1260 status = "dis 1138 status = "disabled";
1261 }; 1139 };
1262 1140
1263 uart18: serial@890000 1141 uart18: serial@890000 {
1264 compatible = 1142 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1143 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1144 clock-names = "se";
1267 clocks = <&gc 1145 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1146 pinctrl-names = "default";
1269 pinctrl-0 = < 1147 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1148 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 1149 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 1150 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1151 status = "disabled";
1278 }; 1152 };
1279 1153
1280 i2c19: i2c@894000 { 1154 i2c19: i2c@894000 {
1281 compatible = 1155 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1156 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1157 clock-names = "se";
1284 clocks = <&gc 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1159 pinctrl-names = "default";
1286 pinctrl-0 = < 1160 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1161 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1162 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1163 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1164 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1165 #address-cells = <1>;
1299 #size-cells = 1166 #size-cells = <0>;
1300 status = "dis 1167 status = "disabled";
1301 }; 1168 };
1302 1169
1303 spi19: spi@894000 { 1170 spi19: spi@894000 {
1304 compatible = 1171 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1172 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1173 clock-names = "se";
1307 clocks = <&gc 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1175 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1176 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1177 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1178 dma-names = "tx", "rx";
1312 power-domains !! 1179 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 1180 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1181 #address-cells = <1>;
1321 #size-cells = 1182 #size-cells = <0>;
1322 status = "dis 1183 status = "disabled";
1323 }; 1184 };
1324 }; 1185 };
1325 1186
1326 gpi_dma0: dma-controller@9000 1187 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm !! 1188 compatible = "qcom,sm8250-gpi-dma";
1328 reg = <0 0x00900000 0 1189 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1190 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1191 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1192 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1193 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1194 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1195 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1196 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1197 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1198 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1199 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1200 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1201 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1202 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1203 dma-channels = <15>;
1343 dma-channel-mask = <0 1204 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1205 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1206 #dma-cells = <3>;
1346 status = "disabled"; 1207 status = "disabled";
1347 }; 1208 };
1348 1209
1349 qupv3_id_0: geniqup@9c0000 { 1210 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1211 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1212 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1213 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1214 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1215 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1216 #address-cells = <2>;
1356 #size-cells = <2>; 1217 #size-cells = <2>;
1357 iommus = <&apps_smmu 1218 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1219 ranges;
1359 status = "disabled"; 1220 status = "disabled";
1360 1221
1361 i2c0: i2c@980000 { 1222 i2c0: i2c@980000 {
1362 compatible = 1223 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1224 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1225 clock-names = "se";
1365 clocks = <&gc 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1227 pinctrl-names = "default";
1367 pinctrl-0 = < 1228 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1229 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1230 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1231 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1232 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1233 #address-cells = <1>;
1380 #size-cells = 1234 #size-cells = <0>;
1381 status = "dis 1235 status = "disabled";
1382 }; 1236 };
1383 1237
1384 spi0: spi@980000 { 1238 spi0: spi@980000 {
1385 compatible = 1239 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1240 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1241 clock-names = "se";
1388 clocks = <&gc 1242 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1243 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1244 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1245 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1246 dma-names = "tx", "rx";
1393 power-domains !! 1247 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 1248 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1249 #address-cells = <1>;
1402 #size-cells = 1250 #size-cells = <0>;
1403 status = "dis 1251 status = "disabled";
1404 }; 1252 };
1405 1253
1406 i2c1: i2c@984000 { 1254 i2c1: i2c@984000 {
1407 compatible = 1255 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1256 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1257 clock-names = "se";
1410 clocks = <&gc 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1259 pinctrl-names = "default";
1412 pinctrl-0 = < 1260 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1261 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1262 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1263 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1264 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1265 #address-cells = <1>;
1425 #size-cells = 1266 #size-cells = <0>;
1426 status = "dis 1267 status = "disabled";
1427 }; 1268 };
1428 1269
1429 spi1: spi@984000 { 1270 spi1: spi@984000 {
1430 compatible = 1271 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1272 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1273 clock-names = "se";
1433 clocks = <&gc 1274 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1275 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1276 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1277 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1278 dma-names = "tx", "rx";
1438 power-domains !! 1279 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 1280 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1281 #address-cells = <1>;
1447 #size-cells = 1282 #size-cells = <0>;
1448 status = "dis 1283 status = "disabled";
1449 }; 1284 };
1450 1285
1451 i2c2: i2c@988000 { 1286 i2c2: i2c@988000 {
1452 compatible = 1287 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1288 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1289 clock-names = "se";
1455 clocks = <&gc 1290 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1291 pinctrl-names = "default";
1457 pinctrl-0 = < 1292 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1293 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1294 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1295 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1296 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1297 #address-cells = <1>;
1470 #size-cells = 1298 #size-cells = <0>;
1471 status = "dis 1299 status = "disabled";
1472 }; 1300 };
1473 1301
1474 spi2: spi@988000 { 1302 spi2: spi@988000 {
1475 compatible = 1303 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1304 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1305 clock-names = "se";
1478 clocks = <&gc 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1307 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1308 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1309 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1310 dma-names = "tx", "rx";
1483 power-domains !! 1311 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 1312 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1313 #address-cells = <1>;
1492 #size-cells = 1314 #size-cells = <0>;
1493 status = "dis 1315 status = "disabled";
1494 }; 1316 };
1495 1317
1496 uart2: serial@988000 1318 uart2: serial@988000 {
1497 compatible = 1319 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1320 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1321 clock-names = "se";
1500 clocks = <&gc 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1323 pinctrl-names = "default";
1502 pinctrl-0 = < 1324 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1325 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 1326 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 1327 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1328 status = "disabled";
1511 }; 1329 };
1512 1330
1513 i2c3: i2c@98c000 { 1331 i2c3: i2c@98c000 {
1514 compatible = 1332 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1333 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1334 clock-names = "se";
1517 clocks = <&gc 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1336 pinctrl-names = "default";
1519 pinctrl-0 = < 1337 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1338 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1339 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1340 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1341 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1342 #address-cells = <1>;
1532 #size-cells = 1343 #size-cells = <0>;
1533 status = "dis 1344 status = "disabled";
1534 }; 1345 };
1535 1346
1536 spi3: spi@98c000 { 1347 spi3: spi@98c000 {
1537 compatible = 1348 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1349 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1350 clock-names = "se";
1540 clocks = <&gc 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1352 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1353 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1354 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1355 dma-names = "tx", "rx";
1545 power-domains !! 1356 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 1357 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1358 #address-cells = <1>;
1554 #size-cells = 1359 #size-cells = <0>;
1555 status = "dis 1360 status = "disabled";
1556 }; 1361 };
1557 1362
1558 i2c4: i2c@990000 { 1363 i2c4: i2c@990000 {
1559 compatible = 1364 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1365 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1366 clock-names = "se";
1562 clocks = <&gc 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1368 pinctrl-names = "default";
1564 pinctrl-0 = < 1369 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1370 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1371 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1372 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1373 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1374 #address-cells = <1>;
1577 #size-cells = 1375 #size-cells = <0>;
1578 status = "dis 1376 status = "disabled";
1579 }; 1377 };
1580 1378
1581 spi4: spi@990000 { 1379 spi4: spi@990000 {
1582 compatible = 1380 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1381 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1382 clock-names = "se";
1585 clocks = <&gc 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1384 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1385 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1386 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1387 dma-names = "tx", "rx";
1590 power-domains !! 1388 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 1389 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1390 #address-cells = <1>;
1599 #size-cells = 1391 #size-cells = <0>;
1600 status = "dis 1392 status = "disabled";
1601 }; 1393 };
1602 1394
1603 i2c5: i2c@994000 { 1395 i2c5: i2c@994000 {
1604 compatible = 1396 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1397 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1398 clock-names = "se";
1607 clocks = <&gc 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1400 pinctrl-names = "default";
1609 pinctrl-0 = < 1401 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1402 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1403 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1404 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1405 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1406 #address-cells = <1>;
1622 #size-cells = 1407 #size-cells = <0>;
1623 status = "dis 1408 status = "disabled";
1624 }; 1409 };
1625 1410
1626 spi5: spi@994000 { 1411 spi5: spi@994000 {
1627 compatible = 1412 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1413 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1414 clock-names = "se";
1630 clocks = <&gc 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1416 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1417 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1418 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1419 dma-names = "tx", "rx";
1635 power-domains !! 1420 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1421 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1422 #address-cells = <1>;
1644 #size-cells = 1423 #size-cells = <0>;
1645 status = "dis 1424 status = "disabled";
1646 }; 1425 };
1647 1426
1648 i2c6: i2c@998000 { 1427 i2c6: i2c@998000 {
1649 compatible = 1428 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1429 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1430 clock-names = "se";
1652 clocks = <&gc 1431 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1432 pinctrl-names = "default";
1654 pinctrl-0 = < 1433 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1434 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1435 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1436 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1437 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1438 #address-cells = <1>;
1667 #size-cells = 1439 #size-cells = <0>;
1668 status = "dis 1440 status = "disabled";
1669 }; 1441 };
1670 1442
1671 spi6: spi@998000 { 1443 spi6: spi@998000 {
1672 compatible = 1444 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1445 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1446 clock-names = "se";
1675 clocks = <&gc 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1448 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1449 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1450 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1451 dma-names = "tx", "rx";
1680 power-domains !! 1452 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1453 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1454 #address-cells = <1>;
1689 #size-cells = 1455 #size-cells = <0>;
1690 status = "dis 1456 status = "disabled";
1691 }; 1457 };
1692 1458
1693 uart6: serial@998000 1459 uart6: serial@998000 {
1694 compatible = 1460 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1461 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1462 clock-names = "se";
1697 clocks = <&gc 1463 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1464 pinctrl-names = "default";
1699 pinctrl-0 = < 1465 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1466 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1467 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1468 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1469 status = "disabled";
1708 }; 1470 };
1709 1471
1710 i2c7: i2c@99c000 { 1472 i2c7: i2c@99c000 {
1711 compatible = 1473 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1474 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1475 clock-names = "se";
1714 clocks = <&gc 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1477 pinctrl-names = "default";
1716 pinctrl-0 = < 1478 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1479 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1480 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1481 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1482 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1483 #address-cells = <1>;
1729 #size-cells = 1484 #size-cells = <0>;
1730 status = "dis 1485 status = "disabled";
1731 }; 1486 };
1732 1487
1733 spi7: spi@99c000 { 1488 spi7: spi@99c000 {
1734 compatible = 1489 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1490 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1491 clock-names = "se";
1737 clocks = <&gc 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1493 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1494 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1495 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1496 dma-names = "tx", "rx";
1742 power-domains !! 1497 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1498 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1499 #address-cells = <1>;
1751 #size-cells = 1500 #size-cells = <0>;
1752 status = "dis 1501 status = "disabled";
1753 }; 1502 };
1754 }; 1503 };
1755 1504
1756 gpi_dma1: dma-controller@a000 1505 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm !! 1506 compatible = "qcom,sm8250-gpi-dma";
1758 reg = <0 0x00a00000 0 1507 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1508 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1509 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1510 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1511 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1512 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1513 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1514 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1515 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1516 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1517 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1518 dma-channels = <10>;
1770 dma-channel-mask = <0 1519 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1520 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1521 #dma-cells = <3>;
1773 status = "disabled"; 1522 status = "disabled";
1774 }; 1523 };
1775 1524
1776 qupv3_id_1: geniqup@ac0000 { 1525 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1526 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1527 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1528 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1529 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1530 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1531 #address-cells = <2>;
1783 #size-cells = <2>; 1532 #size-cells = <2>;
1784 iommus = <&apps_smmu 1533 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1534 ranges;
1786 status = "disabled"; 1535 status = "disabled";
1787 1536
1788 i2c8: i2c@a80000 { 1537 i2c8: i2c@a80000 {
1789 compatible = 1538 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1539 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1540 clock-names = "se";
1792 clocks = <&gc 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1542 pinctrl-names = "default";
1794 pinctrl-0 = < 1543 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1544 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1545 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1546 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1547 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1548 #address-cells = <1>;
1807 #size-cells = 1549 #size-cells = <0>;
1808 status = "dis 1550 status = "disabled";
1809 }; 1551 };
1810 1552
1811 spi8: spi@a80000 { 1553 spi8: spi@a80000 {
1812 compatible = 1554 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1555 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1556 clock-names = "se";
1815 clocks = <&gc 1557 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1559 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1560 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1561 dma-names = "tx", "rx";
1820 power-domains !! 1562 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1563 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1564 #address-cells = <1>;
1829 #size-cells = 1565 #size-cells = <0>;
1830 status = "dis 1566 status = "disabled";
1831 }; 1567 };
1832 1568
1833 i2c9: i2c@a84000 { 1569 i2c9: i2c@a84000 {
1834 compatible = 1570 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1571 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1572 clock-names = "se";
1837 clocks = <&gc 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1574 pinctrl-names = "default";
1839 pinctrl-0 = < 1575 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1576 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1577 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1578 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1579 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1580 #address-cells = <1>;
1852 #size-cells = 1581 #size-cells = <0>;
1853 status = "dis 1582 status = "disabled";
1854 }; 1583 };
1855 1584
1856 spi9: spi@a84000 { 1585 spi9: spi@a84000 {
1857 compatible = 1586 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1587 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1588 clock-names = "se";
1860 clocks = <&gc 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1590 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1591 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1592 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1593 dma-names = "tx", "rx";
1865 power-domains !! 1594 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1595 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1596 #address-cells = <1>;
1874 #size-cells = 1597 #size-cells = <0>;
1875 status = "dis 1598 status = "disabled";
1876 }; 1599 };
1877 1600
1878 i2c10: i2c@a88000 { 1601 i2c10: i2c@a88000 {
1879 compatible = 1602 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1603 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1604 clock-names = "se";
1882 clocks = <&gc 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1606 pinctrl-names = "default";
1884 pinctrl-0 = < 1607 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1608 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1609 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1610 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1611 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1612 #address-cells = <1>;
1897 #size-cells = 1613 #size-cells = <0>;
1898 status = "dis 1614 status = "disabled";
1899 }; 1615 };
1900 1616
1901 spi10: spi@a88000 { 1617 spi10: spi@a88000 {
1902 compatible = 1618 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1619 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1620 clock-names = "se";
1905 clocks = <&gc 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1622 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1623 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1624 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1625 dma-names = "tx", "rx";
1910 power-domains !! 1626 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1627 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1628 #address-cells = <1>;
1919 #size-cells = 1629 #size-cells = <0>;
1920 status = "dis 1630 status = "disabled";
1921 }; 1631 };
1922 1632
1923 i2c11: i2c@a8c000 { 1633 i2c11: i2c@a8c000 {
1924 compatible = 1634 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1635 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1636 clock-names = "se";
1927 clocks = <&gc 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1638 pinctrl-names = "default";
1929 pinctrl-0 = < 1639 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1640 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1641 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1642 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1643 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1644 #address-cells = <1>;
1942 #size-cells = 1645 #size-cells = <0>;
1943 status = "dis 1646 status = "disabled";
1944 }; 1647 };
1945 1648
1946 spi11: spi@a8c000 { 1649 spi11: spi@a8c000 {
1947 compatible = 1650 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1651 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1652 clock-names = "se";
1950 clocks = <&gc 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1654 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1655 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1656 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1657 dma-names = "tx", "rx";
1955 power-domains !! 1658 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1659 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1660 #address-cells = <1>;
1964 #size-cells = 1661 #size-cells = <0>;
1965 status = "dis 1662 status = "disabled";
1966 }; 1663 };
1967 1664
1968 i2c12: i2c@a90000 { 1665 i2c12: i2c@a90000 {
1969 compatible = 1666 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1667 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1668 clock-names = "se";
1972 clocks = <&gc 1669 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1670 pinctrl-names = "default";
1974 pinctrl-0 = < 1671 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1672 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1673 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1674 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1675 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1676 #address-cells = <1>;
1987 #size-cells = 1677 #size-cells = <0>;
1988 status = "dis 1678 status = "disabled";
1989 }; 1679 };
1990 1680
1991 spi12: spi@a90000 { 1681 spi12: spi@a90000 {
1992 compatible = 1682 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1683 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1684 clock-names = "se";
1995 clocks = <&gc 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1686 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1687 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1688 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1689 dma-names = "tx", "rx";
2000 power-domains !! 1690 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1691 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1692 #address-cells = <1>;
2009 #size-cells = 1693 #size-cells = <0>;
2010 status = "dis 1694 status = "disabled";
2011 }; 1695 };
2012 1696
2013 uart12: serial@a90000 1697 uart12: serial@a90000 {
2014 compatible = 1698 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1699 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1700 clock-names = "se";
2017 clocks = <&gc 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1702 pinctrl-names = "default";
2019 pinctrl-0 = < 1703 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1704 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1705 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1706 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1707 status = "disabled";
2028 }; 1708 };
2029 1709
2030 i2c13: i2c@a94000 { 1710 i2c13: i2c@a94000 {
2031 compatible = 1711 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1712 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1713 clock-names = "se";
2034 clocks = <&gc 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1715 pinctrl-names = "default";
2036 pinctrl-0 = < 1716 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1717 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1718 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1719 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1720 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1721 #address-cells = <1>;
2049 #size-cells = 1722 #size-cells = <0>;
2050 status = "dis 1723 status = "disabled";
2051 }; 1724 };
2052 1725
2053 spi13: spi@a94000 { 1726 spi13: spi@a94000 {
2054 compatible = 1727 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1728 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1729 clock-names = "se";
2057 clocks = <&gc 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1731 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1732 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1733 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1734 dma-names = "tx", "rx";
2062 power-domains !! 1735 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1736 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1737 #address-cells = <1>;
2071 #size-cells = 1738 #size-cells = <0>;
2072 status = "dis 1739 status = "disabled";
2073 }; 1740 };
2074 }; 1741 };
2075 1742
2076 config_noc: interconnect@1500 1743 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1744 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1745 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1746 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1747 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1748 };
2082 1749
2083 system_noc: interconnect@1620 1750 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1751 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1752 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1753 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1754 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1755 };
2089 1756
2090 mc_virt: interconnect@163d000 1757 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1758 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1759 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1760 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1761 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1762 };
2096 1763
2097 aggre1_noc: interconnect@16e0 1764 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1765 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1766 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1767 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1768 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1769 };
2103 1770
2104 aggre2_noc: interconnect@1700 1771 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1772 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1773 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1774 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1775 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1776 };
2110 1777
2111 compute_noc: interconnect@173 1778 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1779 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1780 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1781 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1782 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1783 };
2117 1784
2118 mmss_noc: interconnect@174000 1785 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1786 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1787 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1788 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1789 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1790 };
2124 1791
2125 pcie0: pcie@1c00000 { !! 1792 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc !! 1793 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2127 reg = <0 0x01c00000 0 1794 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1795 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1796 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1797 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1798 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1799 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1800 device_type = "pci";
2135 linux,pci-domain = <0 1801 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1802 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1803 num-lanes = <1>;
2138 1804
2139 #address-cells = <3>; 1805 #address-cells = <3>;
2140 #size-cells = <2>; 1806 #size-cells = <2>;
2141 1807
2142 ranges = <0x01000000 !! 1808 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
2143 <0x02000000 !! 1809 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
2144 1810
2145 interrupts = <GIC_SPI !! 1811 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2146 <GIC_SPI !! 1812 interrupt-names = "msi";
2147 <GIC_SPI <<
2148 <GIC_SPI <<
2149 <GIC_SPI <<
2150 <GIC_SPI <<
2151 <GIC_SPI <<
2152 <GIC_SPI <<
2153 interrupt-names = "ms <<
2154 "ms <<
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1813 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1814 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1815 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1816 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1817 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1818 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1819
2168 clocks = <&gcc GCC_PC 1820 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1821 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1822 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1823 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1824 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1825 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1826 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1827 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1828 clock-names = "pipe",
2177 "aux", 1829 "aux",
2178 "cfg", 1830 "cfg",
2179 "bus_ma 1831 "bus_master",
2180 "bus_sl 1832 "bus_slave",
2181 "slave_ 1833 "slave_q2a",
2182 "tbu", 1834 "tbu",
2183 "ddrss_ 1835 "ddrss_sf_tbu";
2184 1836
>> 1837 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1838 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1839 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1840
2188 resets = <&gcc GCC_PC 1841 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1842 reset-names = "pci";
2190 1843
2191 power-domains = <&gcc 1844 power-domains = <&gcc PCIE_0_GDSC>;
2192 1845
2193 phys = <&pcie0_phy>; !! 1846 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1847 phy-names = "pciephy";
2195 1848
2196 perst-gpios = <&tlmm 1849 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1850 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1851
2199 pinctrl-names = "defa 1852 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1853 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1854
2203 status = "disabled"; 1855 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1856 };
2215 1857
2216 pcie0_phy: phy@1c06000 { 1858 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1859 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1860 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1861 #address-cells = <2>;
>> 1862 #size-cells = <2>;
>> 1863 ranges;
2220 clocks = <&gcc GCC_PC 1864 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1865 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1866 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1867 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1868 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1869
2236 resets = <&gcc GCC_PC 1870 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1871 reset-names = "phy";
2238 1872
2239 assigned-clocks = <&g 1873 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1874 assigned-clock-rates = <100000000>;
2241 1875
2242 status = "disabled"; 1876 status = "disabled";
>> 1877
>> 1878 pcie0_lane: phy@1c06200 {
>> 1879 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1880 <0 0x1c06400 0 0x200>, /* rx */
>> 1881 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1882 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1883 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1884 clock-names = "pipe0";
>> 1885
>> 1886 #phy-cells = <0>;
>> 1887
>> 1888 #clock-cells = <0>;
>> 1889 clock-output-names = "pcie_0_pipe_clk";
>> 1890 };
2243 }; 1891 };
2244 1892
2245 pcie1: pcie@1c08000 { !! 1893 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc !! 1894 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2247 reg = <0 0x01c08000 0 1895 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1896 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1897 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1898 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1899 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1900 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1901 device_type = "pci";
2255 linux,pci-domain = <1 1902 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1903 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1904 num-lanes = <2>;
2258 1905
2259 #address-cells = <3>; 1906 #address-cells = <3>;
2260 #size-cells = <2>; 1907 #size-cells = <2>;
2261 1908
2262 ranges = <0x01000000 !! 1909 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1910 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1911
2265 interrupts = <GIC_SPI !! 1912 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1913 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1914 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1915 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1916 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1917 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1918 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1919 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1920
2288 clocks = <&gcc GCC_PC 1921 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1922 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1923 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1924 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1925 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1926 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1927 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1928 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1929 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1930 clock-names = "pipe",
2298 "aux", 1931 "aux",
2299 "cfg", 1932 "cfg",
2300 "bus_ma 1933 "bus_master",
2301 "bus_sl 1934 "bus_slave",
2302 "slave_ 1935 "slave_q2a",
2303 "ref", 1936 "ref",
2304 "tbu", 1937 "tbu",
2305 "ddrss_ 1938 "ddrss_sf_tbu";
2306 1939
2307 assigned-clocks = <&g 1940 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1941 assigned-clock-rates = <19200000>;
2309 1942
>> 1943 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1944 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1945 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1946
2313 resets = <&gcc GCC_PC 1947 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1948 reset-names = "pci";
2315 1949
2316 power-domains = <&gcc 1950 power-domains = <&gcc PCIE_1_GDSC>;
2317 1951
2318 phys = <&pcie1_phy>; !! 1952 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1953 phy-names = "pciephy";
2320 1954
2321 perst-gpios = <&tlmm 1955 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1956 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1957
2324 pinctrl-names = "defa 1958 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1959 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1960
2328 status = "disabled"; 1961 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1962 };
2340 1963
2341 pcie1_phy: phy@1c0e000 { 1964 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1965 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1966 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1967 #address-cells = <2>;
>> 1968 #size-cells = <2>;
>> 1969 ranges;
2345 clocks = <&gcc GCC_PC 1970 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1971 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1972 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1973 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1974 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1975
2361 resets = <&gcc GCC_PC 1976 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1977 reset-names = "phy";
2363 1978
2364 assigned-clocks = <&g 1979 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1980 assigned-clock-rates = <100000000>;
2366 1981
2367 status = "disabled"; 1982 status = "disabled";
>> 1983
>> 1984 pcie1_lane: phy@1c0e200 {
>> 1985 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1986 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1987 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1988 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1989 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 1990 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 1991 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 1992 clock-names = "pipe0";
>> 1993
>> 1994 #phy-cells = <0>;
>> 1995
>> 1996 #clock-cells = <0>;
>> 1997 clock-output-names = "pcie_1_pipe_clk";
>> 1998 };
2368 }; 1999 };
2369 2000
2370 pcie2: pcie@1c10000 { !! 2001 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc !! 2002 compatible = "qcom,pcie-sm8250", "snps,dw-pcie";
2372 reg = <0 0x01c10000 0 2003 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2004 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2005 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2006 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 2007 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 2008 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 2009 device_type = "pci";
2380 linux,pci-domain = <2 2010 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2011 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2012 num-lanes = <2>;
2383 2013
2384 #address-cells = <3>; 2014 #address-cells = <3>;
2385 #size-cells = <2>; 2015 #size-cells = <2>;
2386 2016
2387 ranges = <0x01000000 !! 2017 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2018 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2019
2390 interrupts = <GIC_SPI !! 2020 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2021 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2022 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2023 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2024 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2025 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2026 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2027 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2028
2413 clocks = <&gcc GCC_PC 2029 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2030 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2031 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2032 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2033 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2034 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2035 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2036 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2037 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2038 clock-names = "pipe",
2423 "aux", 2039 "aux",
2424 "cfg", 2040 "cfg",
2425 "bus_ma 2041 "bus_master",
2426 "bus_sl 2042 "bus_slave",
2427 "slave_ 2043 "slave_q2a",
2428 "ref", 2044 "ref",
2429 "tbu", 2045 "tbu",
2430 "ddrss_ 2046 "ddrss_sf_tbu";
2431 2047
2432 assigned-clocks = <&g 2048 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2049 assigned-clock-rates = <19200000>;
2434 2050
>> 2051 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 2052 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2053 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2054
2438 resets = <&gcc GCC_PC 2055 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2056 reset-names = "pci";
2440 2057
2441 power-domains = <&gcc 2058 power-domains = <&gcc PCIE_2_GDSC>;
2442 2059
2443 phys = <&pcie2_phy>; !! 2060 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 2061 phy-names = "pciephy";
2445 2062
2446 perst-gpios = <&tlmm 2063 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2064 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2065
2449 pinctrl-names = "defa 2066 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2067 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 2068
2453 status = "disabled"; 2069 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2070 };
2465 2071
2466 pcie2_phy: phy@1c16000 { 2072 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2073 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 2074 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 2075 #address-cells = <2>;
>> 2076 #size-cells = <2>;
>> 2077 ranges;
2470 clocks = <&gcc GCC_PC 2078 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2079 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2080 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 2081 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 2082 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 2083
2486 resets = <&gcc GCC_PC 2084 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2085 reset-names = "phy";
2488 2086
2489 assigned-clocks = <&g 2087 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2088 assigned-clock-rates = <100000000>;
2491 2089
2492 status = "disabled"; 2090 status = "disabled";
>> 2091
>> 2092 pcie2_lane: phy@1c16200 {
>> 2093 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 2094 <0 0x1c16400 0 0x200>, /* rx0 */
>> 2095 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 2096 <0 0x1c16600 0 0x170>, /* tx1 */
>> 2097 <0 0x1c16800 0 0x200>, /* rx1 */
>> 2098 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2099 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 2100 clock-names = "pipe0";
>> 2101
>> 2102 #phy-cells = <0>;
>> 2103
>> 2104 #clock-cells = <0>;
>> 2105 clock-output-names = "pcie_2_pipe_clk";
>> 2106 };
2493 }; 2107 };
2494 2108
2495 ufs_mem_hc: ufshc@1d84000 { 2109 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2110 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2111 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2112 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2113 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2114 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2115 phy-names = "ufsphy";
2502 lanes-per-direction = 2116 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2117 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2118 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2119 reset-names = "rst";
2506 2120
2507 power-domains = <&gcc 2121 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2122
2509 iommus = <&apps_smmu 2123 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2124
2511 clock-names = 2125 clock-names =
2512 "core_clk", 2126 "core_clk",
2513 "bus_aggr_clk 2127 "bus_aggr_clk",
2514 "iface_clk", 2128 "iface_clk",
2515 "core_clk_uni 2129 "core_clk_unipro",
2516 "ref_clk", 2130 "ref_clk",
2517 "tx_lane0_syn 2131 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2132 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2133 "rx_lane1_sync_clk";
2520 clocks = 2134 clocks =
2521 <&gcc GCC_UFS 2135 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2136 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2137 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2138 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2139 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2140 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2141 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2142 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2143 freq-table-hz =
2530 operating-points-v2 = !! 2144 <37500000 300000000>,
2531 !! 2145 <0 0>,
2532 interconnects = <&agg !! 2146 <0 0>,
2533 <&gem !! 2147 <37500000 300000000>,
2534 interconnect-names = !! 2148 <0 0>,
>> 2149 <0 0>,
>> 2150 <0 0>,
>> 2151 <0 0>;
2535 2152
2536 status = "disabled"; 2153 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2154 };
2566 2155
2567 ufs_mem_phy: phy@1d87000 { 2156 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2157 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2158 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2159 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2160 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2161 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2162 clock-names = "ref",
2575 "ref_au !! 2163 "ref_aux";
2576 "qref"; !! 2164 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2165 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2166
2578 resets = <&ufs_mem_hc 2167 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2168 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2169 status = "disabled";
>> 2170
>> 2171 ufs_mem_phy_lanes: phy@1d87400 {
>> 2172 reg = <0 0x01d87400 0 0x108>,
>> 2173 <0 0x01d87600 0 0x1e0>,
>> 2174 <0 0x01d87c00 0 0x1dc>,
>> 2175 <0 0x01d87800 0 0x108>,
>> 2176 <0 0x01d87a00 0 0x1e0>;
>> 2177 #phy-cells = <0>;
>> 2178 };
2586 }; 2179 };
2587 2180
2588 cryptobam: dma-controller@1dc !! 2181 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 2182 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 2183 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 2184 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 2185 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 2186 };
2619 2187
2620 tcsr_mutex: hwlock@1f40000 { 2188 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2189 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2190 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2191 #hwlock-cells = <1>;
2624 }; 2192 };
2625 2193
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2194 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2195 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2196 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2197 clocks = <&audiocc 1>,
2635 <&q6afecc LP !! 2198 <&audiocc 0>,
2636 <&q6afecc LP 2199 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2200 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2201 <&aoncc 0>,
2638 <&vamacro>; 2202 <&vamacro>;
2639 2203
2640 clock-names = "mclk", !! 2204 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2205
2642 #clock-cells = <0>; 2206 #clock-cells = <0>;
>> 2207 clock-frequency = <9600000>;
2643 clock-output-names = 2208 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2209 #sound-dai-cells = <1>;
2645 2210
2646 pinctrl-names = "defa 2211 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2212 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 2213 };
2651 2214
2652 swr0: soundwire@3250000 { !! 2215 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2216 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2217 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2218 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2219 clocks = <&wsamacro>;
2657 clock-names = "iface" 2220 clock-names = "iface";
2658 2221
2659 qcom,din-ports = <2>; 2222 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2223 qcom,dout-ports = <6>;
2661 2224
2662 qcom,ports-sinterval- 2225 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2226 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2227 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2228 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2229
2667 #sound-dai-cells = <1 2230 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2231 #address-cells = <2>;
2669 #size-cells = <0>; 2232 #size-cells = <0>;
>> 2233 };
2670 2234
2671 status = "disabled"; !! 2235 audiocc: clock-controller@3300000 {
>> 2236 compatible = "qcom,sm8250-lpass-audiocc";
>> 2237 reg = <0 0x03300000 0 0x30000>;
>> 2238 #clock-cells = <1>;
>> 2239 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2240 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2241 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2242 clock-names = "core", "audio", "bus";
2672 }; 2243 };
2673 2244
2674 vamacro: codec@3370000 { 2245 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2246 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2247 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2248 clocks = <&aoncc 0>,
2678 <&q6afecc LPA 2249 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2250 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2251
2681 clock-names = "mclk", 2252 clock-names = "mclk", "macro", "dcodec";
2682 2253
2683 #clock-cells = <0>; 2254 #clock-cells = <0>;
>> 2255 clock-frequency = <9600000>;
2684 clock-output-names = 2256 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2257 #sound-dai-cells = <1>;
2686 }; 2258 };
2687 2259
2688 rxmacro: rxmacro@3200000 { 2260 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2261 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2262 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2263 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 !! 2264 reg = <0 0x3200000 0 0x1000>;
2693 status = "disabled"; 2265 status = "disabled";
2694 2266
2695 clocks = <&q6afecc LP 2267 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2268 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2269 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2270 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2271 <&vamacro>;
2700 2272
2701 clock-names = "mclk", 2273 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2274
2703 #clock-cells = <0>; 2275 #clock-cells = <0>;
>> 2276 clock-frequency = <9600000>;
2704 clock-output-names = 2277 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2278 #sound-dai-cells = <1>;
2706 }; 2279 };
2707 2280
2708 swr1: soundwire@3210000 { !! 2281 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 !! 2282 reg = <0 0x3210000 0 0x2000>;
2710 compatible = "qcom,so 2283 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2284 status = "disabled";
2712 interrupts = <GIC_SPI 2285 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2286 clocks = <&rxmacro>;
2714 clock-names = "iface" 2287 clock-names = "iface";
2715 label = "RX"; 2288 label = "RX";
2716 qcom,din-ports = <0>; 2289 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2290 qcom,dout-ports = <5>;
2718 2291
2719 qcom,ports-sinterval- !! 2292 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2720 qcom,ports-offset1 = !! 2293 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2721 qcom,ports-offset2 = !! 2294 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2722 qcom,ports-hstart = !! 2295 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2723 qcom,ports-hstop = !! 2296 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2724 qcom,ports-word-lengt !! 2297 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2725 qcom,ports-block-pack !! 2298 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2726 qcom,ports-lane-contr 2299 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou !! 2300 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2728 2301
2729 #sound-dai-cells = <1 2302 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2303 #address-cells = <2>;
2731 #size-cells = <0>; 2304 #size-cells = <0>;
2732 }; 2305 };
2733 2306
2734 txmacro: txmacro@3220000 { 2307 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2308 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2309 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2310 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 !! 2311 reg = <0 0x3220000 0 0x1000>;
2739 status = "disabled"; 2312 status = "disabled";
2740 2313
2741 clocks = <&q6afecc LP 2314 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2315 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2316 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2317 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2318 <&vamacro>;
2746 2319
2747 clock-names = "mclk", 2320 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2321
2749 #clock-cells = <0>; 2322 #clock-cells = <0>;
>> 2323 clock-frequency = <9600000>;
2750 clock-output-names = 2324 clock-output-names = "mclk";
>> 2325 #address-cells = <2>;
>> 2326 #size-cells = <2>;
2751 #sound-dai-cells = <1 2327 #sound-dai-cells = <1>;
2752 }; 2328 };
2753 2329
2754 /* tx macro */ 2330 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2331 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 !! 2332 reg = <0 0x3230000 0 0x2000>;
2757 compatible = "qcom,so 2333 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI !! 2334 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2335 interrupt-names = "core";
2760 status = "disabled"; 2336 status = "disabled";
2761 2337
2762 clocks = <&txmacro>; 2338 clocks = <&txmacro>;
2763 clock-names = "iface" 2339 clock-names = "iface";
2764 label = "TX"; 2340 label = "TX";
2765 2341
2766 qcom,din-ports = <5>; 2342 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2343 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- !! 2344 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = !! 2345 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = !! 2346 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack !! 2347 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2772 qcom,ports-hstart = !! 2348 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2773 qcom,ports-hstop = !! 2349 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2774 qcom,ports-word-lengt !! 2350 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2775 qcom,ports-block-grou !! 2351 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2776 qcom,ports-lane-contr !! 2352 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
>> 2353 qcom,port-offset = <1>;
2777 #sound-dai-cells = <1 2354 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2355 #address-cells = <2>;
2779 #size-cells = <0>; 2356 #size-cells = <0>;
2780 }; 2357 };
2781 2358
2782 lpass_tlmm: pinctrl@33c0000 { !! 2359 aoncc: clock-controller@3380000 {
>> 2360 compatible = "qcom,sm8250-lpass-aoncc";
>> 2361 reg = <0 0x03380000 0 0x40000>;
>> 2362 #clock-cells = <1>;
>> 2363 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2364 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2365 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2366 clock-names = "core", "audio", "bus";
>> 2367 };
>> 2368
>> 2369 lpass_tlmm: pinctrl@33c0000{
2783 compatible = "qcom,sm 2370 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2371 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2372 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2373 gpio-controller;
2787 #gpio-cells = <2>; 2374 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2375 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2376
2790 clocks = <&q6afecc LP 2377 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2378 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2379 clock-names = "core", "audio";
2793 2380
2794 wsa_swr_active: wsa-s !! 2381 wsa_swr_active: wsa-swr-active-pins {
2795 clk-pins { !! 2382 clk {
2796 pins 2383 pins = "gpio10";
2797 funct 2384 function = "wsa_swr_clk";
2798 drive 2385 drive-strength = <2>;
2799 slew- 2386 slew-rate = <1>;
2800 bias- 2387 bias-disable;
2801 }; 2388 };
2802 2389
2803 data-pins { !! 2390 data {
2804 pins 2391 pins = "gpio11";
2805 funct 2392 function = "wsa_swr_data";
2806 drive 2393 drive-strength = <2>;
2807 slew- 2394 slew-rate = <1>;
2808 bias- 2395 bias-bus-hold;
>> 2396
2809 }; 2397 };
2810 }; 2398 };
2811 2399
2812 wsa_swr_sleep: wsa-sw !! 2400 wsa_swr_sleep: wsa-swr-sleep-pins {
2813 clk-pins { !! 2401 clk {
2814 pins 2402 pins = "gpio10";
2815 funct 2403 function = "wsa_swr_clk";
2816 drive 2404 drive-strength = <2>;
>> 2405 input-enable;
2817 bias- 2406 bias-pull-down;
2818 }; 2407 };
2819 2408
2820 data-pins { !! 2409 data {
2821 pins 2410 pins = "gpio11";
2822 funct 2411 function = "wsa_swr_data";
2823 drive 2412 drive-strength = <2>;
>> 2413 input-enable;
2824 bias- 2414 bias-pull-down;
>> 2415
2825 }; 2416 };
2826 }; 2417 };
2827 2418
2828 dmic01_active: dmic01 !! 2419 dmic01_active: dmic01-active-pins {
2829 clk-pins { !! 2420 clk {
2830 pins 2421 pins = "gpio6";
2831 funct 2422 function = "dmic1_clk";
2832 drive 2423 drive-strength = <8>;
2833 outpu 2424 output-high;
2834 }; 2425 };
2835 data-pins { !! 2426 data {
2836 pins 2427 pins = "gpio7";
2837 funct 2428 function = "dmic1_data";
2838 drive 2429 drive-strength = <8>;
>> 2430 input-enable;
2839 }; 2431 };
2840 }; 2432 };
2841 2433
2842 dmic01_sleep: dmic01- !! 2434 dmic01_sleep: dmic01-sleep-pins {
2843 clk-pins { !! 2435 clk {
2844 pins 2436 pins = "gpio6";
2845 funct 2437 function = "dmic1_clk";
2846 drive 2438 drive-strength = <2>;
2847 bias- 2439 bias-disable;
2848 outpu 2440 output-low;
2849 }; 2441 };
2850 2442
2851 data-pins { !! 2443 data {
2852 pins 2444 pins = "gpio7";
2853 funct 2445 function = "dmic1_data";
2854 drive 2446 drive-strength = <2>;
2855 bias- !! 2447 pull-down;
>> 2448 input-enable;
2856 }; 2449 };
2857 }; 2450 };
2858 2451
2859 rx_swr_active: rx-swr !! 2452 rx_swr_active: rx_swr-active-pins {
2860 clk-pins { !! 2453 clk {
2861 pins 2454 pins = "gpio3";
2862 funct 2455 function = "swr_rx_clk";
2863 drive 2456 drive-strength = <2>;
2864 slew- 2457 slew-rate = <1>;
2865 bias- 2458 bias-disable;
2866 }; 2459 };
2867 2460
2868 data-pins { !! 2461 data {
2869 pins 2462 pins = "gpio4", "gpio5";
2870 funct 2463 function = "swr_rx_data";
2871 drive 2464 drive-strength = <2>;
2872 slew- 2465 slew-rate = <1>;
2873 bias- 2466 bias-bus-hold;
2874 }; 2467 };
2875 }; 2468 };
2876 2469
2877 tx_swr_active: tx-swr !! 2470 tx_swr_active: tx_swr-active-pins {
2878 clk-pins { !! 2471 clk {
2879 pins 2472 pins = "gpio0";
2880 funct 2473 function = "swr_tx_clk";
2881 drive 2474 drive-strength = <2>;
2882 slew- 2475 slew-rate = <1>;
2883 bias- 2476 bias-disable;
2884 }; 2477 };
2885 2478
2886 data-pins { !! 2479 data {
2887 pins 2480 pins = "gpio1", "gpio2";
2888 funct 2481 function = "swr_tx_data";
2889 drive 2482 drive-strength = <2>;
2890 slew- 2483 slew-rate = <1>;
2891 bias- 2484 bias-bus-hold;
2892 }; 2485 };
2893 }; 2486 };
2894 2487
2895 tx_swr_sleep: tx-swr- !! 2488 tx_swr_sleep: tx_swr-sleep-pins {
2896 clk-pins { !! 2489 clk {
2897 pins 2490 pins = "gpio0";
2898 funct 2491 function = "swr_tx_clk";
2899 drive 2492 drive-strength = <2>;
>> 2493 input-enable;
2900 bias- 2494 bias-pull-down;
2901 }; 2495 };
2902 2496
2903 data1-pins { !! 2497 data1 {
2904 pins 2498 pins = "gpio1";
2905 funct 2499 function = "swr_tx_data";
2906 drive 2500 drive-strength = <2>;
>> 2501 input-enable;
2907 bias- 2502 bias-bus-hold;
2908 }; 2503 };
2909 2504
2910 data2-pins { !! 2505 data2 {
2911 pins 2506 pins = "gpio2";
2912 funct 2507 function = "swr_tx_data";
2913 drive 2508 drive-strength = <2>;
>> 2509 input-enable;
2914 bias- 2510 bias-pull-down;
2915 }; 2511 };
2916 }; 2512 };
2917 }; 2513 };
2918 2514
2919 gpu: gpu@3d00000 { 2515 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2516 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2517 "qcom,adreno";
2922 2518
2923 reg = <0 0x03d00000 0 2519 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2520 reg-names = "kgsl_3d0_reg_memory";
2925 2521
2926 interrupts = <GIC_SPI 2522 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2523
2928 iommus = <&adreno_smm 2524 iommus = <&adreno_smmu 0 0x401>;
2929 2525
2930 operating-points-v2 = 2526 operating-points-v2 = <&gpu_opp_table>;
2931 2527
2932 qcom,gmu = <&gmu>; 2528 qcom,gmu = <&gmu>;
2933 2529
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 2530 status = "disabled";
2939 2531
2940 zap-shader { 2532 zap-shader {
2941 memory-region 2533 memory-region = <&gpu_mem>;
2942 }; 2534 };
2943 2535
>> 2536 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 2537 gpu_opp_table: opp-table {
2945 compatible = 2538 compatible = "operating-points-v2";
2946 2539
2947 opp-670000000 2540 opp-670000000 {
2948 opp-h 2541 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2542 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 2543 };
2952 2544
2953 opp-587000000 2545 opp-587000000 {
2954 opp-h 2546 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2547 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 2548 };
2958 2549
2959 opp-525000000 2550 opp-525000000 {
2960 opp-h 2551 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2552 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 2553 };
2964 2554
2965 opp-490000000 2555 opp-490000000 {
2966 opp-h 2556 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2557 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 2558 };
2970 2559
2971 opp-441600000 2560 opp-441600000 {
2972 opp-h 2561 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2562 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 2563 };
2976 2564
2977 opp-400000000 2565 opp-400000000 {
2978 opp-h 2566 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2567 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 2568 };
2982 2569
2983 opp-305000000 2570 opp-305000000 {
2984 opp-h 2571 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2572 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 2573 };
2988 }; 2574 };
2989 }; 2575 };
2990 2576
2991 gmu: gmu@3d6a000 { 2577 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad !! 2578 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2579
2994 reg = <0 0x03d6a000 0 2580 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2581 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2582 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2583 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2584 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2585
3000 interrupts = <GIC_SPI 2586 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2587 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2588 interrupt-names = "hfi", "gmu";
3003 2589
3004 clocks = <&gpucc GPU_ 2590 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2591 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2592 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2593 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2594 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2595 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2596
3011 power-domains = <&gpu 2597 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2598 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2599 power-domain-names = "cx", "gx";
3014 2600
3015 iommus = <&adreno_smm 2601 iommus = <&adreno_smmu 5 0x400>;
3016 2602
3017 operating-points-v2 = 2603 operating-points-v2 = <&gmu_opp_table>;
3018 2604
3019 status = "disabled"; 2605 status = "disabled";
3020 2606
3021 gmu_opp_table: opp-ta 2607 gmu_opp_table: opp-table {
3022 compatible = 2608 compatible = "operating-points-v2";
3023 2609
3024 opp-200000000 2610 opp-200000000 {
3025 opp-h 2611 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2612 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2613 };
3028 }; 2614 };
3029 }; 2615 };
3030 2616
3031 gpucc: clock-controller@3d900 2617 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2618 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2619 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2620 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2621 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2622 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2623 clock-names = "bi_tcxo",
3038 "gcc_gp 2624 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2625 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2626 #clock-cells = <1>;
3041 #reset-cells = <1>; 2627 #reset-cells = <1>;
3042 #power-domain-cells = 2628 #power-domain-cells = <1>;
3043 }; 2629 };
3044 2630
3045 adreno_smmu: iommu@3da0000 { 2631 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2632 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2633 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2634 #iommu-cells = <2>;
3050 #global-interrupts = 2635 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2636 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2637 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2638 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2639 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2640 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2641 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2642 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2643 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2644 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2645 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2646 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2647 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2648 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2649 clock-names = "ahb", "bus", "iface";
3065 2650
3066 power-domains = <&gpu 2651 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2652 };
3069 2653
3070 slpi: remoteproc@5c00000 { 2654 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2655 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2656 reg = <0 0x05c00000 0 0x4000>;
3073 2657
3074 interrupts-extended = !! 2658 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2659 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2660 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2661 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2662 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2663 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2664 "handover", "stop-ack";
3081 2665
3082 clocks = <&rpmhcc RPM 2666 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2667 clock-names = "xo";
3084 2668
3085 power-domains = <&rpm !! 2669 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2670 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2671 power-domain-names = "lcx", "lmx";
3088 2672
3089 memory-region = <&slp 2673 memory-region = <&slpi_mem>;
3090 2674
3091 qcom,qmp = <&aoss_qmp 2675 qcom,qmp = <&aoss_qmp>;
3092 2676
3093 qcom,smem-states = <& 2677 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2678 qcom,smem-state-names = "stop";
3095 2679
3096 status = "disabled"; 2680 status = "disabled";
3097 2681
3098 glink-edge { 2682 glink-edge {
3099 interrupts-ex 2683 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2684 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2685 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2686 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2687 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2688
3105 label = "slpi 2689 label = "slpi";
3106 qcom,remote-p 2690 qcom,remote-pid = <3>;
3107 2691
3108 fastrpc { 2692 fastrpc {
3109 compa 2693 compatible = "qcom,fastrpc";
3110 qcom, 2694 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2695 label = "sdsp";
3112 qcom, 2696 qcom,non-secure-domain;
3113 #addr 2697 #address-cells = <1>;
3114 #size 2698 #size-cells = <0>;
3115 2699
3116 compu 2700 compute-cb@1 {
3117 2701 compatible = "qcom,fastrpc-compute-cb";
3118 2702 reg = <1>;
3119 2703 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2704 };
3121 2705
3122 compu 2706 compute-cb@2 {
3123 2707 compatible = "qcom,fastrpc-compute-cb";
3124 2708 reg = <2>;
3125 2709 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2710 };
3127 2711
3128 compu 2712 compute-cb@3 {
3129 2713 compatible = "qcom,fastrpc-compute-cb";
3130 2714 reg = <3>;
3131 2715 iommus = <&apps_smmu 0x0543 0x0>;
3132 2716 /* note: shared-cb = <4> in downstream */
3133 }; 2717 };
3134 }; 2718 };
3135 }; 2719 };
3136 }; 2720 };
3137 2721
3138 stm@6002000 { <<
3139 compatible = "arm,cor <<
3140 reg = <0 0x06002000 0 <<
3141 reg-names = "stm-base <<
3142 <<
3143 clocks = <&aoss_qmp>; <<
3144 clock-names = "apb_pc <<
3145 <<
3146 out-ports { <<
3147 port { <<
3148 stm_o <<
3149 <<
3150 }; <<
3151 }; <<
3152 }; <<
3153 }; <<
3154 <<
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { <<
3216 compatible = "arm,cor <<
3217 reg = <0 0x06041000 0 <<
3218 <<
3219 clocks = <&aoss_qmp>; <<
3220 clock-names = "apb_pc <<
3221 <<
3222 out-ports { <<
3223 port { <<
3224 funne <<
3225 <<
3226 }; <<
3227 }; <<
3228 }; <<
3229 <<
3230 in-ports { <<
3231 #address-cell <<
3232 #size-cells = <<
3233 <<
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { <<
3242 reg = <<
3243 funne <<
3244 <<
3245 }; <<
3246 }; <<
3247 }; <<
3248 }; <<
3249 <<
3250 funnel@6042000 { <<
3251 compatible = "arm,cor <<
3252 reg = <0 0x06042000 0 <<
3253 <<
3254 clocks = <&aoss_qmp>; <<
3255 clock-names = "apb_pc <<
3256 <<
3257 out-ports { <<
3258 port { <<
3259 funne <<
3260 <<
3261 }; <<
3262 }; <<
3263 }; <<
3264 <<
3265 in-ports { <<
3266 #address-cell <<
3267 #size-cells = <<
3268 <<
3269 port@4 { <<
3270 reg = <<
3271 funne <<
3272 remot <<
3273 }; <<
3274 }; <<
3275 }; <<
3276 }; <<
3277 <<
3278 funnel@6045000 { <<
3279 compatible = "arm,cor <<
3280 reg = <0 0x06045000 0 <<
3281 <<
3282 clocks = <&aoss_qmp>; <<
3283 clock-names = "apb_pc <<
3284 <<
3285 out-ports { <<
3286 port { <<
3287 funne <<
3288 remot <<
3289 }; <<
3290 }; <<
3291 }; <<
3292 <<
3293 in-ports { <<
3294 #address-cell <<
3295 #size-cells = <<
3296 <<
3297 port@0 { <<
3298 reg = <<
3299 funne <<
3300 remot <<
3301 }; <<
3302 }; <<
3303 <<
3304 port@1 { <<
3305 reg = <<
3306 funne <<
3307 remot <<
3308 }; <<
3309 }; <<
3310 }; <<
3311 }; <<
3312 <<
3313 replicator@6046000 { <<
3314 compatible = "arm,cor <<
3315 reg = <0 0x06046000 0 <<
3316 <<
3317 clocks = <&aoss_qmp>; <<
3318 clock-names = "apb_pc <<
3319 <<
3320 out-ports { <<
3321 port { <<
3322 repli <<
3323 <<
3324 }; <<
3325 }; <<
3326 }; <<
3327 <<
3328 in-ports { <<
3329 port { <<
3330 repli <<
3331 <<
3332 }; <<
3333 }; <<
3334 }; <<
3335 }; <<
3336 <<
3337 etr@6048000 { <<
3338 compatible = "arm,cor <<
3339 reg = <0 0x06048000 0 <<
3340 <<
3341 clocks = <&aoss_qmp>; <<
3342 clock-names = "apb_pc <<
3343 arm,scatter-gather; <<
3344 <<
3345 in-ports { <<
3346 port { <<
3347 etr_i <<
3348 <<
3349 }; <<
3350 }; <<
3351 }; <<
3352 }; <<
3353 <<
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { <<
3371 compatible = "arm,cor <<
3372 arm,primecell-periphi <<
3373 <<
3374 reg = <0 0x06b04000 0 <<
3375 <<
3376 clocks = <&aoss_qmp>; <<
3377 clock-names = "apb_pc <<
3378 <<
3379 out-ports { <<
3380 port { <<
3381 funne <<
3382 <<
3383 }; <<
3384 }; <<
3385 }; <<
3386 <<
3387 in-ports { <<
3388 #address-cell <<
3389 #size-cells = <<
3390 <<
3391 port@7 { <<
3392 reg = <<
3393 funne <<
3394 <<
3395 }; <<
3396 }; <<
3397 }; <<
3398 }; <<
3399 <<
3400 etf@6b05000 { <<
3401 compatible = "arm,cor <<
3402 reg = <0 0x06b05000 0 <<
3403 <<
3404 clocks = <&aoss_qmp>; <<
3405 clock-names = "apb_pc <<
3406 <<
3407 out-ports { <<
3408 port { <<
3409 etf_o <<
3410 <<
3411 }; <<
3412 }; <<
3413 }; <<
3414 <<
3415 in-ports { <<
3416 <<
3417 port { <<
3418 etf_i <<
3419 <<
3420 }; <<
3421 }; <<
3422 }; <<
3423 }; <<
3424 <<
3425 replicator@6b06000 { <<
3426 compatible = "arm,cor <<
3427 reg = <0 0x06b06000 0 <<
3428 <<
3429 clocks = <&aoss_qmp>; <<
3430 clock-names = "apb_pc <<
3431 <<
3432 out-ports { <<
3433 port { <<
3434 repli <<
3435 <<
3436 }; <<
3437 }; <<
3438 }; <<
3439 <<
3440 in-ports { <<
3441 port { <<
3442 repli <<
3443 <<
3444 }; <<
3445 }; <<
3446 }; <<
3447 }; <<
3448 <<
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { <<
3522 compatible = "arm,cor <<
3523 reg = <0 0x07040000 0 <<
3524 <<
3525 cpu = <&CPU0>; <<
3526 <<
3527 clocks = <&aoss_qmp>; <<
3528 clock-names = "apb_pc <<
3529 arm,coresight-loses-c <<
3530 <<
3531 out-ports { <<
3532 port { <<
3533 etm0_ <<
3534 <<
3535 }; <<
3536 }; <<
3537 }; <<
3538 }; <<
3539 <<
3540 etm@7140000 { <<
3541 compatible = "arm,cor <<
3542 reg = <0 0x07140000 0 <<
3543 <<
3544 cpu = <&CPU1>; <<
3545 <<
3546 clocks = <&aoss_qmp>; <<
3547 clock-names = "apb_pc <<
3548 arm,coresight-loses-c <<
3549 <<
3550 out-ports { <<
3551 port { <<
3552 etm1_ <<
3553 <<
3554 }; <<
3555 }; <<
3556 }; <<
3557 }; <<
3558 <<
3559 etm@7240000 { <<
3560 compatible = "arm,cor <<
3561 reg = <0 0x07240000 0 <<
3562 <<
3563 cpu = <&CPU2>; <<
3564 <<
3565 clocks = <&aoss_qmp>; <<
3566 clock-names = "apb_pc <<
3567 arm,coresight-loses-c <<
3568 <<
3569 out-ports { <<
3570 port { <<
3571 etm2_ <<
3572 <<
3573 }; <<
3574 }; <<
3575 }; <<
3576 }; <<
3577 <<
3578 etm@7340000 { <<
3579 compatible = "arm,cor <<
3580 reg = <0 0x07340000 0 <<
3581 <<
3582 cpu = <&CPU3>; <<
3583 <<
3584 clocks = <&aoss_qmp>; <<
3585 clock-names = "apb_pc <<
3586 arm,coresight-loses-c <<
3587 <<
3588 out-ports { <<
3589 port { <<
3590 etm3_ <<
3591 <<
3592 }; <<
3593 }; <<
3594 }; <<
3595 }; <<
3596 <<
3597 etm@7440000 { <<
3598 compatible = "arm,cor <<
3599 reg = <0 0x07440000 0 <<
3600 <<
3601 cpu = <&CPU4>; <<
3602 <<
3603 clocks = <&aoss_qmp>; <<
3604 clock-names = "apb_pc <<
3605 arm,coresight-loses-c <<
3606 <<
3607 out-ports { <<
3608 port { <<
3609 etm4_ <<
3610 <<
3611 }; <<
3612 }; <<
3613 }; <<
3614 }; <<
3615 <<
3616 etm@7540000 { <<
3617 compatible = "arm,cor <<
3618 reg = <0 0x07540000 0 <<
3619 <<
3620 cpu = <&CPU5>; <<
3621 <<
3622 clocks = <&aoss_qmp>; <<
3623 clock-names = "apb_pc <<
3624 arm,coresight-loses-c <<
3625 <<
3626 out-ports { <<
3627 port { <<
3628 etm5_ <<
3629 <<
3630 }; <<
3631 }; <<
3632 }; <<
3633 }; <<
3634 <<
3635 etm@7640000 { <<
3636 compatible = "arm,cor <<
3637 reg = <0 0x07640000 0 <<
3638 <<
3639 cpu = <&CPU6>; <<
3640 <<
3641 clocks = <&aoss_qmp>; <<
3642 clock-names = "apb_pc <<
3643 arm,coresight-loses-c <<
3644 <<
3645 out-ports { <<
3646 port { <<
3647 etm6_ <<
3648 <<
3649 }; <<
3650 }; <<
3651 }; <<
3652 }; <<
3653 <<
3654 etm@7740000 { <<
3655 compatible = "arm,cor <<
3656 reg = <0 0x07740000 0 <<
3657 <<
3658 cpu = <&CPU7>; <<
3659 <<
3660 clocks = <&aoss_qmp>; <<
3661 clock-names = "apb_pc <<
3662 arm,coresight-loses-c <<
3663 <<
3664 out-ports { <<
3665 port { <<
3666 etm7_ <<
3667 <<
3668 }; <<
3669 }; <<
3670 }; <<
3671 }; <<
3672 <<
3673 funnel@7800000 { <<
3674 compatible = "arm,cor <<
3675 reg = <0 0x07800000 0 <<
3676 <<
3677 clocks = <&aoss_qmp>; <<
3678 clock-names = "apb_pc <<
3679 <<
3680 out-ports { <<
3681 port { <<
3682 funne <<
3683 remot <<
3684 }; <<
3685 }; <<
3686 }; <<
3687 <<
3688 in-ports { <<
3689 #address-cell <<
3690 #size-cells = <<
3691 <<
3692 port@0 { <<
3693 reg = <<
3694 apss_ <<
3695 <<
3696 }; <<
3697 }; <<
3698 <<
3699 port@1 { <<
3700 reg = <<
3701 apss_ <<
3702 <<
3703 }; <<
3704 }; <<
3705 <<
3706 port@2 { <<
3707 reg = <<
3708 apss_ <<
3709 <<
3710 }; <<
3711 }; <<
3712 <<
3713 port@3 { <<
3714 reg = <<
3715 apss_ <<
3716 <<
3717 }; <<
3718 }; <<
3719 <<
3720 port@4 { <<
3721 reg = <<
3722 apss_ <<
3723 <<
3724 }; <<
3725 }; <<
3726 <<
3727 port@5 { <<
3728 reg = <<
3729 apss_ <<
3730 <<
3731 }; <<
3732 }; <<
3733 <<
3734 port@6 { <<
3735 reg = <<
3736 apss_ <<
3737 <<
3738 }; <<
3739 }; <<
3740 <<
3741 port@7 { <<
3742 reg = <<
3743 apss_ <<
3744 <<
3745 }; <<
3746 }; <<
3747 }; <<
3748 }; <<
3749 <<
3750 funnel@7810000 { <<
3751 compatible = "arm,cor <<
3752 reg = <0 0x07810000 0 <<
3753 <<
3754 clocks = <&aoss_qmp>; <<
3755 clock-names = "apb_pc <<
3756 <<
3757 out-ports { <<
3758 port { <<
3759 funne <<
3760 remot <<
3761 }; <<
3762 }; <<
3763 }; <<
3764 <<
3765 in-ports { <<
3766 port { <<
3767 funne <<
3768 remot <<
3769 }; <<
3770 }; <<
3771 }; <<
3772 }; <<
3773 <<
3774 cdsp: remoteproc@8300000 { 2722 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 2723 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 2724 reg = <0 0x08300000 0 0x10000>;
3777 2725
3778 interrupts-extended = !! 2726 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 2727 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 2728 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 2729 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 2730 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 2731 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 2732 "handover", "stop-ack";
3785 2733
3786 clocks = <&rpmhcc RPM 2734 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 2735 clock-names = "xo";
3788 2736
3789 power-domains = <&rpm !! 2737 power-domains = <&rpmhpd SM8250_CX>;
3790 2738
3791 memory-region = <&cds 2739 memory-region = <&cdsp_mem>;
3792 2740
3793 qcom,qmp = <&aoss_qmp 2741 qcom,qmp = <&aoss_qmp>;
3794 2742
3795 qcom,smem-states = <& 2743 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 2744 qcom,smem-state-names = "stop";
3797 2745
3798 status = "disabled"; 2746 status = "disabled";
3799 2747
3800 glink-edge { 2748 glink-edge {
3801 interrupts-ex 2749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 2750 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 2751 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 2752 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 2753 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 2754
3807 label = "cdsp 2755 label = "cdsp";
3808 qcom,remote-p 2756 qcom,remote-pid = <5>;
3809 2757
3810 fastrpc { 2758 fastrpc {
3811 compa 2759 compatible = "qcom,fastrpc";
3812 qcom, 2760 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 2761 label = "cdsp";
3814 qcom, 2762 qcom,non-secure-domain;
3815 #addr 2763 #address-cells = <1>;
3816 #size 2764 #size-cells = <0>;
3817 2765
3818 compu 2766 compute-cb@1 {
3819 2767 compatible = "qcom,fastrpc-compute-cb";
3820 2768 reg = <1>;
3821 2769 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 2770 };
3823 2771
3824 compu 2772 compute-cb@2 {
3825 2773 compatible = "qcom,fastrpc-compute-cb";
3826 2774 reg = <2>;
3827 2775 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 2776 };
3829 2777
3830 compu 2778 compute-cb@3 {
3831 2779 compatible = "qcom,fastrpc-compute-cb";
3832 2780 reg = <3>;
3833 2781 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 2782 };
3835 2783
3836 compu 2784 compute-cb@4 {
3837 2785 compatible = "qcom,fastrpc-compute-cb";
3838 2786 reg = <4>;
3839 2787 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 2788 };
3841 2789
3842 compu 2790 compute-cb@5 {
3843 2791 compatible = "qcom,fastrpc-compute-cb";
3844 2792 reg = <5>;
3845 2793 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 2794 };
3847 2795
3848 compu 2796 compute-cb@6 {
3849 2797 compatible = "qcom,fastrpc-compute-cb";
3850 2798 reg = <6>;
3851 2799 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 2800 };
3853 2801
3854 compu 2802 compute-cb@7 {
3855 2803 compatible = "qcom,fastrpc-compute-cb";
3856 2804 reg = <7>;
3857 2805 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 2806 };
3859 2807
3860 compu 2808 compute-cb@8 {
3861 2809 compatible = "qcom,fastrpc-compute-cb";
3862 2810 reg = <8>;
3863 2811 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 2812 };
3865 2813
3866 /* no 2814 /* note: secure cb9 in downstream */
3867 }; 2815 };
3868 }; 2816 };
3869 }; 2817 };
3870 2818
>> 2819 sound: sound {
>> 2820 };
>> 2821
3871 usb_1_hsphy: phy@88e3000 { 2822 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 2823 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 2824 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 2825 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 2826 status = "disabled";
3876 #phy-cells = <0>; 2827 #phy-cells = <0>;
3877 2828
3878 clocks = <&rpmhcc RPM 2829 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 2830 clock-names = "ref";
3880 2831
3881 resets = <&gcc GCC_QU 2832 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 2833 };
3883 2834
3884 usb_2_hsphy: phy@88e4000 { 2835 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 2836 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 2837 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 2838 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 2839 status = "disabled";
3889 #phy-cells = <0>; 2840 #phy-cells = <0>;
3890 2841
3891 clocks = <&rpmhcc RPM 2842 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 2843 clock-names = "ref";
3893 2844
3894 resets = <&gcc GCC_QU 2845 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 2846 };
3896 2847
3897 usb_1_qmpphy: phy@88e8000 { !! 2848 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 2849 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 2850 reg = <0 0x088e9000 0 0x200>,
>> 2851 <0 0x088e8000 0 0x40>,
>> 2852 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 2853 status = "disabled";
>> 2854 #address-cells = <2>;
>> 2855 #size-cells = <2>;
>> 2856 ranges;
3901 2857
3902 clocks = <&gcc GCC_US 2858 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 2859 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 2860 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 2861 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 2862
3911 resets = <&gcc GCC_US 2863 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 2864 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 2865 reset-names = "phy", "common";
3914 2866
3915 #clock-cells = <1>; !! 2867 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 2868 reg = <0 0x088e9200 0 0x200>,
3917 !! 2869 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 2870 <0 0x088e9c00 0 0x400>,
3919 !! 2871 <0 0x088e9600 0 0x200>,
3920 ports { !! 2872 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 2873 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 2874 #clock-cells = <0>;
3923 !! 2875 #phy-cells = <0>;
3924 port@0 { !! 2876 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 2877 clock-names = "pipe0";
3926 usb_1 !! 2878 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 2879 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 2880
3940 usb_1 !! 2881 dp_phy: dp-phy@88ea200 {
3941 }; !! 2882 reg = <0 0x088ea200 0 0x200>,
>> 2883 <0 0x088ea400 0 0x200>,
>> 2884 <0 0x088eac00 0 0x400>,
>> 2885 <0 0x088ea600 0 0x200>,
>> 2886 <0 0x088ea800 0 0x200>,
>> 2887 <0 0x088eaa00 0 0x100>;
>> 2888 #phy-cells = <0>;
>> 2889 #clock-cells = <1>;
>> 2890 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> 2891 clock-names = "pipe0";
>> 2892 clock-output-names = "usb3_phy_pipe_clk_src";
3942 }; 2893 };
3943 }; 2894 };
3944 2895
3945 usb_2_qmpphy: phy@88eb000 { 2896 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 2897 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 2898 reg = <0 0x088eb000 0 0x200>;
>> 2899 status = "disabled";
>> 2900 #address-cells = <2>;
>> 2901 #size-cells = <2>;
>> 2902 ranges;
3948 2903
3949 clocks = <&gcc GCC_US 2904 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 2905 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 2906 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 2907 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 2908 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 2909
3961 resets = <&gcc GCC_US !! 2910 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 2911 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 2912 reset-names = "phy", "common";
3964 "phy_ph <<
3965 2913
3966 status = "disabled"; !! 2914 usb_2_ssphy: phy@88eb200 {
>> 2915 reg = <0 0x088eb200 0 0x200>,
>> 2916 <0 0x088eb400 0 0x200>,
>> 2917 <0 0x088eb800 0 0x800>;
>> 2918 #clock-cells = <0>;
>> 2919 #phy-cells = <0>;
>> 2920 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 2921 clock-names = "pipe0";
>> 2922 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 2923 };
3967 }; 2924 };
3968 2925
3969 sdhc_2: mmc@8804000 { !! 2926 sdhc_2: sdhci@8804000 {
3970 compatible = "qcom,sm 2927 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 2928 reg = <0 0x08804000 0 0x1000>;
3972 2929
3973 interrupts = <GIC_SPI 2930 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 2931 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 2932 interrupt-names = "hc_irq", "pwr_irq";
3976 2933
3977 clocks = <&gcc GCC_SD 2934 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 2935 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 2936 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 2937 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 2938 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 2939 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 2940 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 2941 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 2942 operating-points-v2 = <&sdhc2_opp_table>;
3986 2943
3987 status = "disabled"; 2944 status = "disabled";
3988 2945
3989 sdhc2_opp_table: opp- !! 2946 sdhc2_opp_table: sdhc2-opp-table {
3990 compatible = 2947 compatible = "operating-points-v2";
3991 2948
3992 opp-19200000 2949 opp-19200000 {
3993 opp-h 2950 opp-hz = /bits/ 64 <19200000>;
3994 requi 2951 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 2952 };
3996 2953
3997 opp-50000000 2954 opp-50000000 {
3998 opp-h 2955 opp-hz = /bits/ 64 <50000000>;
3999 requi 2956 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 2957 };
4001 2958
4002 opp-100000000 2959 opp-100000000 {
4003 opp-h 2960 opp-hz = /bits/ 64 <100000000>;
4004 requi 2961 required-opps = <&rpmhpd_opp_svs>;
4005 }; 2962 };
4006 2963
4007 opp-202000000 2964 opp-202000000 {
4008 opp-h 2965 opp-hz = /bits/ 64 <202000000>;
4009 requi 2966 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 2967 };
4011 }; 2968 };
4012 }; 2969 };
4013 2970
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 2971 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 2972 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 2973 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 2974 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 2975 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 2976 };
4142 2977
4143 gem_noc: interconnect@9100000 2978 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 2979 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 2980 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 2981 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 2982 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 2983 };
4149 2984
4150 npu_noc: interconnect@9990000 2985 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 2986 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 2987 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 2988 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 2989 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 2990 };
4156 2991
4157 usb_1: usb@a6f8800 { 2992 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 2993 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 2994 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 2995 status = "disabled";
4161 #address-cells = <2>; 2996 #address-cells = <2>;
4162 #size-cells = <2>; 2997 #size-cells = <2>;
4163 ranges; 2998 ranges;
4164 dma-ranges; 2999 dma-ranges;
4165 3000
4166 clocks = <&gcc GCC_CF 3001 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 3002 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 3003 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 3004 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 3005 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 3006 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 3007 clock-names = "cfg_noc",
4173 "core", 3008 "core",
4174 "iface" 3009 "iface",
4175 "sleep" 3010 "sleep",
4176 "mock_u 3011 "mock_utmi",
4177 "xo"; 3012 "xo";
4178 3013
4179 assigned-clocks = <&g 3014 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 3015 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 3016 assigned-clock-rates = <19200000>, <200000000>;
4182 3017
4183 interrupts-extended = !! 3018 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 <<
4185 3019 <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
4186 3020 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 3021 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
4188 interrupt-names = "pw !! 3022 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4189 "hs !! 3023 "dm_hs_phy_irq", "ss_phy_irq";
4190 "dp <<
4191 "dm <<
4192 "ss <<
4193 3024
4194 power-domains = <&gcc 3025 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 3026
4197 resets = <&gcc GCC_US 3027 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 3028
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 3029 usb_1_dwc3: usb@a600000 {
4204 compatible = 3030 compatible = "snps,dwc3";
4205 reg = <0 0x0a 3031 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 3032 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 3033 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 3034 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 3035 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 3036 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 3037 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 3038 };
4233 }; 3039 };
4234 3040
4235 system-cache-controller@92000 3041 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 3042 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 3043 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 3044 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 3045 };
4243 3046
4244 usb_2: usb@a8f8800 { 3047 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 3048 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 3049 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 3050 status = "disabled";
4248 #address-cells = <2>; 3051 #address-cells = <2>;
4249 #size-cells = <2>; 3052 #size-cells = <2>;
4250 ranges; 3053 ranges;
4251 dma-ranges; 3054 dma-ranges;
4252 3055
4253 clocks = <&gcc GCC_CF 3056 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 3057 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 3058 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 3059 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 3060 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 3061 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 3062 clock-names = "cfg_noc",
4260 "core", 3063 "core",
4261 "iface" 3064 "iface",
4262 "sleep" 3065 "sleep",
4263 "mock_u 3066 "mock_utmi",
4264 "xo"; 3067 "xo";
4265 3068
4266 assigned-clocks = <&g 3069 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 3070 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 3071 assigned-clock-rates = <19200000>, <200000000>;
4269 3072
4270 interrupts-extended = !! 3073 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 <<
4272 3074 <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
4273 3075 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 3076 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
4275 interrupt-names = "pw !! 3077 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
4276 "hs !! 3078 "dm_hs_phy_irq", "ss_phy_irq";
4277 "dp <<
4278 "dm <<
4279 "ss <<
4280 3079
4281 power-domains = <&gcc 3080 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 3081
4284 resets = <&gcc GCC_US 3082 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 3083
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 3084 usb_2_dwc3: usb@a800000 {
4291 compatible = 3085 compatible = "snps,dwc3";
4292 reg = <0 0x0a 3086 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 3087 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 3088 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 3089 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 3090 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 3091 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 3092 phy-names = "usb2-phy", "usb3-phy";
4299 }; 3093 };
4300 }; 3094 };
4301 3095
4302 venus: video-codec@aa00000 { 3096 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 3097 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 3098 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 3099 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 3100 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 3101 <&videocc MVS0_GDSC>,
4308 <&rpm !! 3102 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 3103 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 3104 operating-points-v2 = <&venus_opp_table>;
4311 3105
4312 clocks = <&gcc GCC_VI 3106 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 3107 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 3108 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 3109 clock-names = "iface", "core", "vcodec0_core";
4316 3110
4317 interconnects = <&gem !! 3111 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 3112 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 3113 interconnect-names = "cpu-cfg", "video-mem";
4320 3114
4321 iommus = <&apps_smmu 3115 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 3116 memory-region = <&video_mem>;
4323 3117
4324 resets = <&gcc GCC_VI 3118 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 3119 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 3120 reset-names = "bus", "core";
4327 3121
4328 status = "disabled"; 3122 status = "disabled";
4329 3123
4330 video-decoder { 3124 video-decoder {
4331 compatible = 3125 compatible = "venus-decoder";
4332 }; 3126 };
4333 3127
4334 video-encoder { 3128 video-encoder {
4335 compatible = 3129 compatible = "venus-encoder";
4336 }; 3130 };
4337 3131
4338 venus_opp_table: opp- !! 3132 venus_opp_table: venus-opp-table {
4339 compatible = 3133 compatible = "operating-points-v2";
4340 3134
4341 opp-720000000 3135 opp-720000000 {
4342 opp-h 3136 opp-hz = /bits/ 64 <720000000>;
4343 requi 3137 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3138 };
4345 3139
4346 opp-101400000 3140 opp-1014000000 {
4347 opp-h 3141 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3142 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3143 };
4350 3144
4351 opp-109800000 3145 opp-1098000000 {
4352 opp-h 3146 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3147 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3148 };
4355 3149
4356 opp-133200000 3150 opp-1332000000 {
4357 opp-h 3151 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3152 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3153 };
4360 }; 3154 };
4361 }; 3155 };
4362 3156
4363 videocc: clock-controller@abf 3157 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 3158 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 3159 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 3160 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 3161 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 3162 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 3163 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 3164 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 3165 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 3166 #clock-cells = <1>;
4373 #reset-cells = <1>; 3167 #reset-cells = <1>;
4374 #power-domain-cells = 3168 #power-domain-cells = <1>;
4375 }; 3169 };
4376 3170
4377 cci0: cci@ac4f000 { 3171 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm !! 3172 compatible = "qcom,sm8250-cci";
4379 #address-cells = <1>; 3173 #address-cells = <1>;
4380 #size-cells = <0>; 3174 #size-cells = <0>;
4381 3175
4382 reg = <0 0x0ac4f000 0 3176 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 3177 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 3178 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 3179
4386 clocks = <&camcc CAM_ 3180 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 3181 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 3182 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 3183 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 3184 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 3185 clock-names = "camnoc_axi",
4392 "slow_a 3186 "slow_ahb_src",
4393 "cpas_a 3187 "cpas_ahb",
4394 "cci", 3188 "cci",
4395 "cci_sr 3189 "cci_src";
4396 3190
4397 pinctrl-0 = <&cci0_de 3191 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 3192 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 3193 pinctrl-names = "default", "sleep";
4400 3194
4401 status = "disabled"; 3195 status = "disabled";
4402 3196
4403 cci0_i2c0: i2c-bus@0 3197 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 3198 reg = <0>;
4405 clock-frequen 3199 clock-frequency = <1000000>;
4406 #address-cell 3200 #address-cells = <1>;
4407 #size-cells = 3201 #size-cells = <0>;
4408 }; 3202 };
4409 3203
4410 cci0_i2c1: i2c-bus@1 3204 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 3205 reg = <1>;
4412 clock-frequen 3206 clock-frequency = <1000000>;
4413 #address-cell 3207 #address-cells = <1>;
4414 #size-cells = 3208 #size-cells = <0>;
4415 }; 3209 };
4416 }; 3210 };
4417 3211
4418 cci1: cci@ac50000 { 3212 cci1: cci@ac50000 {
4419 compatible = "qcom,sm !! 3213 compatible = "qcom,sm8250-cci";
4420 #address-cells = <1>; 3214 #address-cells = <1>;
4421 #size-cells = <0>; 3215 #size-cells = <0>;
4422 3216
4423 reg = <0 0x0ac50000 0 3217 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 3218 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 3219 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 3220
4427 clocks = <&camcc CAM_ 3221 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 3222 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 3223 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 3224 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 3225 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 3226 clock-names = "camnoc_axi",
4433 "slow_a 3227 "slow_ahb_src",
4434 "cpas_a 3228 "cpas_ahb",
4435 "cci", 3229 "cci",
4436 "cci_sr 3230 "cci_src";
4437 3231
4438 pinctrl-0 = <&cci1_de 3232 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 3233 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 3234 pinctrl-names = "default", "sleep";
4441 3235
4442 status = "disabled"; 3236 status = "disabled";
4443 3237
4444 cci1_i2c0: i2c-bus@0 3238 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 3239 reg = <0>;
4446 clock-frequen 3240 clock-frequency = <1000000>;
4447 #address-cell 3241 #address-cells = <1>;
4448 #size-cells = 3242 #size-cells = <0>;
4449 }; 3243 };
4450 3244
4451 cci1_i2c1: i2c-bus@1 3245 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 3246 reg = <1>;
4453 clock-frequen 3247 clock-frequency = <1000000>;
4454 #address-cell 3248 #address-cells = <1>;
4455 #size-cells = 3249 #size-cells = <0>;
4456 }; 3250 };
4457 }; 3251 };
4458 3252
4459 camss: camss@ac6a000 { 3253 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 3254 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 3255 status = "disabled";
4462 3256
4463 reg = <0 0x0ac6a000 0 !! 3257 reg = <0 0xac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 !! 3258 <0 0xac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 !! 3259 <0 0xac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 !! 3260 <0 0xac70000 0 0x1000>,
4467 <0 0x0ac72000 0 !! 3261 <0 0xac72000 0 0x1000>,
4468 <0 0x0ac74000 0 !! 3262 <0 0xac74000 0 0x1000>,
4469 <0 0x0acb4000 0 !! 3263 <0 0xacb4000 0 0xd000>,
4470 <0 0x0acc3000 0 !! 3264 <0 0xacc3000 0 0xd000>,
4471 <0 0x0acd9000 0 !! 3265 <0 0xacd9000 0 0x2200>,
4472 <0 0x0acdb200 0 !! 3266 <0 0xacdb200 0 0x2200>;
4473 reg-names = "csiphy0" 3267 reg-names = "csiphy0",
4474 "csiphy1" 3268 "csiphy1",
4475 "csiphy2" 3269 "csiphy2",
4476 "csiphy3" 3270 "csiphy3",
4477 "csiphy4" 3271 "csiphy4",
4478 "csiphy5" 3272 "csiphy5",
4479 "vfe0", 3273 "vfe0",
4480 "vfe1", 3274 "vfe1",
4481 "vfe_lite 3275 "vfe_lite0",
4482 "vfe_lite 3276 "vfe_lite1";
4483 3277
4484 interrupts = <GIC_SPI 3278 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 3279 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 3280 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 3281 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 3282 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 3283 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 3284 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 3285 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 3286 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 3287 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 3288 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 3289 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 3290 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 3291 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 3292 interrupt-names = "csiphy0",
4499 "cs 3293 "csiphy1",
4500 "cs 3294 "csiphy2",
4501 "cs 3295 "csiphy3",
4502 "cs 3296 "csiphy4",
4503 "cs 3297 "csiphy5",
4504 "cs 3298 "csid0",
4505 "cs 3299 "csid1",
4506 "cs 3300 "csid2",
4507 "cs 3301 "csid3",
4508 "vf 3302 "vfe0",
4509 "vf 3303 "vfe1",
4510 "vf 3304 "vfe_lite0",
4511 "vf 3305 "vfe_lite1";
4512 3306
4513 power-domains = <&cam 3307 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 3308 <&camcc IFE_1_GDSC>,
4515 <&cam 3309 <&camcc TITAN_TOP_GDSC>;
4516 3310
4517 clocks = <&gcc GCC_CA 3311 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 3312 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 3313 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 3314 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 3315 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 3316 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 3317 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 3318 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 3319 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 3320 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 3321 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 3322 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 3323 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 3324 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 3325 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 3326 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 3327 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 3328 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 3329 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 3330 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 3331 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 3332 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 3333 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 3334 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 3335 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 3336 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 3337 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 3338 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 3339 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 3340 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 3341 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 3342 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 3343 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 3344 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 3345 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 3346 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 3347 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 3348
4555 clock-names = "cam_ah 3349 clock-names = "cam_ahb_clk",
4556 "cam_hf 3350 "cam_hf_axi",
4557 "cam_sf 3351 "cam_sf_axi",
4558 "camnoc 3352 "camnoc_axi",
4559 "camnoc 3353 "camnoc_axi_src",
4560 "core_a 3354 "core_ahb",
4561 "cpas_a 3355 "cpas_ahb",
4562 "csiphy 3356 "csiphy0",
4563 "csiphy 3357 "csiphy0_timer",
4564 "csiphy 3358 "csiphy1",
4565 "csiphy 3359 "csiphy1_timer",
4566 "csiphy 3360 "csiphy2",
4567 "csiphy 3361 "csiphy2_timer",
4568 "csiphy 3362 "csiphy3",
4569 "csiphy 3363 "csiphy3_timer",
4570 "csiphy 3364 "csiphy4",
4571 "csiphy 3365 "csiphy4_timer",
4572 "csiphy 3366 "csiphy5",
4573 "csiphy 3367 "csiphy5_timer",
4574 "slow_a 3368 "slow_ahb_src",
4575 "vfe0_a 3369 "vfe0_ahb",
4576 "vfe0_a 3370 "vfe0_axi",
4577 "vfe0", 3371 "vfe0",
4578 "vfe0_c 3372 "vfe0_cphy_rx",
4579 "vfe0_c 3373 "vfe0_csid",
4580 "vfe0_a 3374 "vfe0_areg",
4581 "vfe1_a 3375 "vfe1_ahb",
4582 "vfe1_a 3376 "vfe1_axi",
4583 "vfe1", 3377 "vfe1",
4584 "vfe1_c 3378 "vfe1_cphy_rx",
4585 "vfe1_c 3379 "vfe1_csid",
4586 "vfe1_a 3380 "vfe1_areg",
4587 "vfe_li 3381 "vfe_lite_ahb",
4588 "vfe_li 3382 "vfe_lite_axi",
4589 "vfe_li 3383 "vfe_lite",
4590 "vfe_li 3384 "vfe_lite_cphy_rx",
4591 "vfe_li 3385 "vfe_lite_csid";
4592 3386
4593 iommus = <&apps_smmu 3387 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 3388 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 3389 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 3390 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 3391 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 3392 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 3393 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 3394 <&apps_smmu 0xc41 0x400>;
4601 3395
4602 interconnects = <&gem !! 3396 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
4603 <&mms !! 3397 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
4604 <&mms !! 3398 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
4605 <&mms !! 3399 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
4606 interconnect-names = 3400 interconnect-names = "cam_ahb",
4607 3401 "cam_hf_0_mnoc",
4608 3402 "cam_sf_0_mnoc",
4609 3403 "cam_sf_icp_mnoc";
4610 <<
4611 ports { <<
4612 #address-cell <<
4613 #size-cells = <<
4614 <<
4615 port@0 { <<
4616 reg = <<
4617 }; <<
4618 <<
4619 port@1 { <<
4620 reg = <<
4621 }; <<
4622 <<
4623 port@2 { <<
4624 reg = <<
4625 }; <<
4626 <<
4627 port@3 { <<
4628 reg = <<
4629 }; <<
4630 <<
4631 port@4 { <<
4632 reg = <<
4633 }; <<
4634 <<
4635 port@5 { <<
4636 reg = <<
4637 }; <<
4638 }; <<
4639 }; 3404 };
4640 3405
4641 camcc: clock-controller@ad000 3406 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 3407 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 3408 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 3409 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 3410 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 3411 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 3412 <&sleep_clk>;
4648 clock-names = "iface" 3413 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm !! 3414 power-domains = <&rpmhpd SM8250_MMCX>;
4650 required-opps = <&rpm 3415 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; <<
4652 #clock-cells = <1>; 3416 #clock-cells = <1>;
4653 #reset-cells = <1>; 3417 #reset-cells = <1>;
4654 #power-domain-cells = 3418 #power-domain-cells = <1>;
4655 }; 3419 };
4656 3420
4657 mdss: display-subsystem@ae000 !! 3421 mdss: mdss@ae00000 {
4658 compatible = "qcom,sm 3422 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 3423 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 3424 reg-names = "mdss";
4661 3425
4662 interconnects = <&mms !! 3426 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 3427 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 3428 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 3429
4666 power-domains = <&dis 3430 power-domains = <&dispcc MDSS_GDSC>;
4667 3431
4668 clocks = <&dispcc DIS 3432 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 3433 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 3434 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 3435 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 3436 clock-names = "iface", "bus", "nrt_bus", "core";
4673 3437
>> 3438 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> 3439 assigned-clock-rates = <460000000>;
>> 3440
4674 interrupts = <GIC_SPI 3441 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 3442 interrupt-controller;
4676 #interrupt-cells = <1 3443 #interrupt-cells = <1>;
4677 3444
4678 iommus = <&apps_smmu 3445 iommus = <&apps_smmu 0x820 0x402>;
4679 3446
4680 status = "disabled"; 3447 status = "disabled";
4681 3448
4682 #address-cells = <2>; 3449 #address-cells = <2>;
4683 #size-cells = <2>; 3450 #size-cells = <2>;
4684 ranges; 3451 ranges;
4685 3452
4686 mdss_mdp: display-con !! 3453 mdss_mdp: mdp@ae01000 {
4687 compatible = 3454 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 3455 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 3456 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 3457 reg-names = "mdp", "vbif";
4691 3458
4692 clocks = <&di 3459 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 3460 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 3461 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 3462 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 3463 clock-names = "iface", "bus", "core", "vsync";
4697 3464
4698 assigned-cloc !! 3465 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
4699 assigned-cloc !! 3466 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> 3467 assigned-clock-rates = <460000000>,
>> 3468 <19200000>;
4700 3469
4701 operating-poi 3470 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 3471 power-domains = <&rpmhpd SM8250_MMCX>;
4703 3472
4704 interrupt-par 3473 interrupt-parent = <&mdss>;
4705 interrupts = 3474 interrupts = <0>;
4706 3475
4707 ports { 3476 ports {
4708 #addr 3477 #address-cells = <1>;
4709 #size 3478 #size-cells = <0>;
4710 3479
4711 port@ 3480 port@0 {
4712 3481 reg = <0>;
4713 3482 dpu_intf1_out: endpoint {
4714 !! 3483 remote-endpoint = <&dsi0_in>;
4715 3484 };
4716 }; 3485 };
4717 3486
4718 port@ 3487 port@1 {
4719 3488 reg = <1>;
4720 3489 dpu_intf2_out: endpoint {
4721 !! 3490 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 3491 };
4731 }; 3492 };
4732 }; 3493 };
4733 3494
4734 mdp_opp_table !! 3495 mdp_opp_table: mdp-opp-table {
4735 compa 3496 compatible = "operating-points-v2";
4736 3497
4737 opp-2 3498 opp-200000000 {
4738 3499 opp-hz = /bits/ 64 <200000000>;
4739 3500 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 3501 };
4741 3502
4742 opp-3 3503 opp-300000000 {
4743 3504 opp-hz = /bits/ 64 <300000000>;
4744 3505 required-opps = <&rpmhpd_opp_svs>;
4745 }; 3506 };
4746 3507
4747 opp-3 3508 opp-345000000 {
4748 3509 opp-hz = /bits/ 64 <345000000>;
4749 3510 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 3511 };
4751 3512
4752 opp-4 3513 opp-460000000 {
4753 3514 opp-hz = /bits/ 64 <460000000>;
4754 3515 required-opps = <&rpmhpd_opp_nom>;
4755 }; 3516 };
4756 }; 3517 };
4757 }; 3518 };
4758 3519
4759 mdss_dp: displayport- !! 3520 dsi0: dsi@ae94000 {
4760 compatible = !! 3521 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 3522 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 3523 reg-names = "dsi_ctrl";
4843 3524
4844 interrupt-par 3525 interrupt-parent = <&mdss>;
4845 interrupts = 3526 interrupts = <4>;
4846 3527
4847 clocks = <&di 3528 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 3529 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 3530 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 3531 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 3532 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 3533 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 3534 clock-names = "byte",
4854 3535 "byte_intf",
4855 3536 "pixel",
4856 3537 "core",
4857 3538 "iface",
4858 3539 "bus";
4859 3540
4860 assigned-cloc 3541 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 3542 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 3543
4863 operating-poi 3544 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 3545 power-domains = <&rpmhpd SM8250_MMCX>;
4865 3546
4866 phys = <&mdss !! 3547 phys = <&dsi0_phy>;
>> 3548 phy-names = "dsi";
4867 3549
4868 status = "dis 3550 status = "disabled";
4869 3551
4870 #address-cell 3552 #address-cells = <1>;
4871 #size-cells = 3553 #size-cells = <0>;
4872 3554
4873 ports { 3555 ports {
4874 #addr 3556 #address-cells = <1>;
4875 #size 3557 #size-cells = <0>;
4876 3558
4877 port@ 3559 port@0 {
4878 3560 reg = <0>;
4879 !! 3561 dsi0_in: endpoint {
4880 3562 remote-endpoint = <&dpu_intf1_out>;
4881 3563 };
4882 }; 3564 };
4883 3565
4884 port@ 3566 port@1 {
4885 3567 reg = <1>;
4886 !! 3568 dsi0_out: endpoint {
4887 3569 };
4888 }; 3570 };
4889 }; 3571 };
4890 <<
4891 dsi_opp_table <<
4892 compa <<
4893 <<
4894 opp-1 <<
4895 <<
4896 <<
4897 }; <<
4898 <<
4899 opp-3 <<
4900 <<
4901 <<
4902 }; <<
4903 <<
4904 opp-3 <<
4905 <<
4906 <<
4907 }; <<
4908 }; <<
4909 }; 3572 };
4910 3573
4911 mdss_dsi0_phy: phy@ae !! 3574 dsi0_phy: dsi-phy@ae94400 {
4912 compatible = 3575 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 3576 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 3577 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 3578 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 3579 reg-names = "dsi_phy",
4917 " 3580 "dsi_phy_lane",
4918 " 3581 "dsi_pll";
4919 3582
4920 #clock-cells 3583 #clock-cells = <1>;
4921 #phy-cells = 3584 #phy-cells = <0>;
4922 3585
4923 clocks = <&di 3586 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 3587 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 3588 clock-names = "iface", "ref";
4926 3589
4927 status = "dis 3590 status = "disabled";
4928 }; 3591 };
4929 3592
4930 mdss_dsi1: dsi@ae9600 !! 3593 dsi1: dsi@ae96000 {
4931 compatible = !! 3594 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 3595 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 3596 reg-names = "dsi_ctrl";
4935 3597
4936 interrupt-par 3598 interrupt-parent = <&mdss>;
4937 interrupts = 3599 interrupts = <5>;
4938 3600
4939 clocks = <&di 3601 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 3602 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 3603 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 3604 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 3605 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 3606 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 3607 clock-names = "byte",
4946 3608 "byte_intf",
4947 3609 "pixel",
4948 3610 "core",
4949 3611 "iface",
4950 3612 "bus";
4951 3613
4952 assigned-cloc 3614 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 3615 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 3616
4955 operating-poi 3617 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 3618 power-domains = <&rpmhpd SM8250_MMCX>;
4957 3619
4958 phys = <&mdss !! 3620 phys = <&dsi1_phy>;
>> 3621 phy-names = "dsi";
4959 3622
4960 status = "dis 3623 status = "disabled";
4961 3624
4962 #address-cell 3625 #address-cells = <1>;
4963 #size-cells = 3626 #size-cells = <0>;
4964 3627
4965 ports { 3628 ports {
4966 #addr 3629 #address-cells = <1>;
4967 #size 3630 #size-cells = <0>;
4968 3631
4969 port@ 3632 port@0 {
4970 3633 reg = <0>;
4971 !! 3634 dsi1_in: endpoint {
4972 3635 remote-endpoint = <&dpu_intf2_out>;
4973 3636 };
4974 }; 3637 };
4975 3638
4976 port@ 3639 port@1 {
4977 3640 reg = <1>;
4978 !! 3641 dsi1_out: endpoint {
4979 3642 };
4980 }; 3643 };
4981 }; 3644 };
4982 }; 3645 };
4983 3646
4984 mdss_dsi1_phy: phy@ae !! 3647 dsi1_phy: dsi-phy@ae96400 {
4985 compatible = 3648 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 3649 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 3650 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 3651 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 3652 reg-names = "dsi_phy",
4990 " 3653 "dsi_phy_lane",
4991 " 3654 "dsi_pll";
4992 3655
4993 #clock-cells 3656 #clock-cells = <1>;
4994 #phy-cells = 3657 #phy-cells = <0>;
4995 3658
4996 clocks = <&di 3659 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 3660 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 3661 clock-names = "iface", "ref";
4999 3662
5000 status = "dis 3663 status = "disabled";
>> 3664
>> 3665 dsi_opp_table: dsi-opp-table {
>> 3666 compatible = "operating-points-v2";
>> 3667
>> 3668 opp-187500000 {
>> 3669 opp-hz = /bits/ 64 <187500000>;
>> 3670 required-opps = <&rpmhpd_opp_low_svs>;
>> 3671 };
>> 3672
>> 3673 opp-300000000 {
>> 3674 opp-hz = /bits/ 64 <300000000>;
>> 3675 required-opps = <&rpmhpd_opp_svs>;
>> 3676 };
>> 3677
>> 3678 opp-358000000 {
>> 3679 opp-hz = /bits/ 64 <358000000>;
>> 3680 required-opps = <&rpmhpd_opp_svs_l1>;
>> 3681 };
>> 3682 };
5001 }; 3683 };
5002 }; 3684 };
5003 3685
5004 dispcc: clock-controller@af00 3686 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 3687 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 3688 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 3689 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 3690 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 3691 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 3692 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 3693 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 3694 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 3695 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 3696 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 3697 <&dp_phy 1>;
5016 clock-names = "bi_tcx 3698 clock-names = "bi_tcxo",
5017 "dsi0_p 3699 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 3700 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 3701 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 3702 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 3703 "dp_phy_pll_link_clk",
5022 "dp_phy 3704 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 3705 #clock-cells = <1>;
5024 #reset-cells = <1>; 3706 #reset-cells = <1>;
5025 #power-domain-cells = 3707 #power-domain-cells = <1>;
5026 }; 3708 };
5027 3709
5028 pdc: interrupt-controller@b22 3710 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 3711 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 3712 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 3713 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 3714 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 3715 #interrupt-cells = <2>;
5034 interrupt-parent = <& 3716 interrupt-parent = <&intc>;
5035 interrupt-controller; 3717 interrupt-controller;
5036 }; 3718 };
5037 3719
5038 tsens0: thermal-sensor@c26300 3720 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 3721 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 3722 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 3723 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 3724 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 3725 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 3726 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 3727 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 3728 #thermal-sensor-cells = <1>;
5047 }; 3729 };
5048 3730
5049 tsens1: thermal-sensor@c26500 3731 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 3732 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 3733 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 3734 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 3735 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 3736 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 3737 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 3738 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 3739 #thermal-sensor-cells = <1>;
5058 }; 3740 };
5059 3741
5060 aoss_qmp: power-management@c3 !! 3742 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm 3743 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 3744 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 3745 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 3746 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 3747 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 3748 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 3749 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 3750
5069 #clock-cells = <0>; 3751 #clock-cells = <0>;
5070 }; 3752 };
5071 3753
5072 sram@c3f0000 { 3754 sram@c3f0000 {
5073 compatible = "qcom,rp 3755 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 3756 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 3757 };
5076 3758
5077 spmi_bus: spmi@c440000 { 3759 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 3760 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 3761 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 3762 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 3763 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 3764 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 3765 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 3766 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 3767 interrupt-names = "periph_irq";
5086 interrupts-extended = 3768 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 3769 qcom,ee = <0>;
5088 qcom,channel = <0>; 3770 qcom,channel = <0>;
5089 #address-cells = <2>; 3771 #address-cells = <2>;
5090 #size-cells = <0>; 3772 #size-cells = <0>;
5091 interrupt-controller; 3773 interrupt-controller;
5092 #interrupt-cells = <4 3774 #interrupt-cells = <4>;
5093 }; 3775 };
5094 3776
5095 tlmm: pinctrl@f100000 { 3777 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 3778 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 3779 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 3780 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 3781 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 3782 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 3783 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 3784 gpio-controller;
5103 #gpio-cells = <2>; 3785 #gpio-cells = <2>;
5104 interrupt-controller; 3786 interrupt-controller;
5105 #interrupt-cells = <2 3787 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 3788 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 3789 wakeup-parent = <&pdc>;
5108 3790
5109 cam2_default: cam2-de !! 3791 cci0_default: cci0-default {
5110 rst-pins { !! 3792 cci0_i2c0_default: cci0-i2c0-default {
5111 pins <<
5112 funct <<
5113 drive <<
5114 bias- <<
5115 }; <<
5116 <<
5117 mclk-pins { <<
5118 pins <<
5119 funct <<
5120 drive <<
5121 bias- <<
5122 }; <<
5123 }; <<
5124 <<
5125 cam2_suspend: cam2-su <<
5126 rst-pins { <<
5127 pins <<
5128 funct <<
5129 drive <<
5130 bias- <<
5131 outpu <<
5132 }; <<
5133 <<
5134 mclk-pins { <<
5135 pins <<
5136 funct <<
5137 drive <<
5138 bias- <<
5139 }; <<
5140 }; <<
5141 <<
5142 cci0_default: cci0-de <<
5143 cci0_i2c0_def <<
5144 /* SD 3793 /* SDA, SCL */
5145 pins 3794 pins = "gpio101", "gpio102";
5146 funct 3795 function = "cci_i2c";
5147 3796
5148 bias- 3797 bias-pull-up;
5149 drive 3798 drive-strength = <2>; /* 2 mA */
5150 }; 3799 };
5151 3800
5152 cci0_i2c1_def !! 3801 cci0_i2c1_default: cci0-i2c1-default {
5153 /* SD 3802 /* SDA, SCL */
5154 pins 3803 pins = "gpio103", "gpio104";
5155 funct 3804 function = "cci_i2c";
5156 3805
5157 bias- 3806 bias-pull-up;
5158 drive 3807 drive-strength = <2>; /* 2 mA */
5159 }; 3808 };
5160 }; 3809 };
5161 3810
5162 cci0_sleep: cci0-slee !! 3811 cci0_sleep: cci0-sleep {
5163 cci0_i2c0_sle !! 3812 cci0_i2c0_sleep: cci0-i2c0-sleep {
5164 /* SD 3813 /* SDA, SCL */
5165 pins 3814 pins = "gpio101", "gpio102";
5166 funct 3815 function = "cci_i2c";
5167 3816
5168 drive 3817 drive-strength = <2>; /* 2 mA */
5169 bias- 3818 bias-pull-down;
5170 }; 3819 };
5171 3820
5172 cci0_i2c1_sle !! 3821 cci0_i2c1_sleep: cci0-i2c1-sleep {
5173 /* SD 3822 /* SDA, SCL */
5174 pins 3823 pins = "gpio103", "gpio104";
5175 funct 3824 function = "cci_i2c";
5176 3825
5177 drive 3826 drive-strength = <2>; /* 2 mA */
5178 bias- 3827 bias-pull-down;
5179 }; 3828 };
5180 }; 3829 };
5181 3830
5182 cci1_default: cci1-de !! 3831 cci1_default: cci1-default {
5183 cci1_i2c0_def !! 3832 cci1_i2c0_default: cci1-i2c0-default {
5184 /* SD 3833 /* SDA, SCL */
5185 pins 3834 pins = "gpio105","gpio106";
5186 funct 3835 function = "cci_i2c";
5187 3836
5188 bias- 3837 bias-pull-up;
5189 drive 3838 drive-strength = <2>; /* 2 mA */
5190 }; 3839 };
5191 3840
5192 cci1_i2c1_def !! 3841 cci1_i2c1_default: cci1-i2c1-default {
5193 /* SD 3842 /* SDA, SCL */
5194 pins 3843 pins = "gpio107","gpio108";
5195 funct 3844 function = "cci_i2c";
5196 3845
5197 bias- 3846 bias-pull-up;
5198 drive 3847 drive-strength = <2>; /* 2 mA */
5199 }; 3848 };
5200 }; 3849 };
5201 3850
5202 cci1_sleep: cci1-slee !! 3851 cci1_sleep: cci1-sleep {
5203 cci1_i2c0_sle !! 3852 cci1_i2c0_sleep: cci1-i2c0-sleep {
5204 /* SD 3853 /* SDA, SCL */
5205 pins 3854 pins = "gpio105","gpio106";
5206 funct 3855 function = "cci_i2c";
5207 3856
5208 bias- 3857 bias-pull-down;
5209 drive 3858 drive-strength = <2>; /* 2 mA */
5210 }; 3859 };
5211 3860
5212 cci1_i2c1_sle !! 3861 cci1_i2c1_sleep: cci1-i2c1-sleep {
5213 /* SD 3862 /* SDA, SCL */
5214 pins 3863 pins = "gpio107","gpio108";
5215 funct 3864 function = "cci_i2c";
5216 3865
5217 bias- 3866 bias-pull-down;
5218 drive 3867 drive-strength = <2>; /* 2 mA */
5219 }; 3868 };
5220 }; 3869 };
5221 3870
5222 pri_mi2s_active: pri- !! 3871 pri_mi2s_active: pri-mi2s-active {
5223 sclk-pins { !! 3872 sclk {
5224 pins 3873 pins = "gpio138";
5225 funct 3874 function = "mi2s0_sck";
5226 drive 3875 drive-strength = <8>;
5227 bias- 3876 bias-disable;
5228 }; 3877 };
5229 3878
5230 ws-pins { !! 3879 ws {
5231 pins 3880 pins = "gpio141";
5232 funct 3881 function = "mi2s0_ws";
5233 drive 3882 drive-strength = <8>;
5234 outpu 3883 output-high;
5235 }; 3884 };
5236 3885
5237 data0-pins { !! 3886 data0 {
5238 pins 3887 pins = "gpio139";
5239 funct 3888 function = "mi2s0_data0";
5240 drive 3889 drive-strength = <8>;
5241 bias- 3890 bias-disable;
5242 outpu 3891 output-high;
5243 }; 3892 };
5244 3893
5245 data1-pins { !! 3894 data1 {
5246 pins 3895 pins = "gpio140";
5247 funct 3896 function = "mi2s0_data1";
5248 drive 3897 drive-strength = <8>;
5249 outpu 3898 output-high;
5250 }; 3899 };
5251 }; 3900 };
5252 3901
5253 qup_i2c0_default: qup !! 3902 qup_i2c0_default: qup-i2c0-default {
5254 pins = "gpio2 !! 3903 mux {
5255 function = "q !! 3904 pins = "gpio28", "gpio29";
5256 drive-strengt !! 3905 function = "qup0";
5257 bias-disable; !! 3906 };
>> 3907
>> 3908 config {
>> 3909 pins = "gpio28", "gpio29";
>> 3910 drive-strength = <2>;
>> 3911 bias-disable;
>> 3912 };
5258 }; 3913 };
5259 3914
5260 qup_i2c1_default: qup !! 3915 qup_i2c1_default: qup-i2c1-default {
5261 pins = "gpio4 !! 3916 pinmux {
5262 function = "q !! 3917 pins = "gpio4", "gpio5";
5263 drive-strengt !! 3918 function = "qup1";
5264 bias-disable; !! 3919 };
>> 3920
>> 3921 config {
>> 3922 pins = "gpio4", "gpio5";
>> 3923 drive-strength = <2>;
>> 3924 bias-disable;
>> 3925 };
5265 }; 3926 };
5266 3927
5267 qup_i2c2_default: qup !! 3928 qup_i2c2_default: qup-i2c2-default {
5268 pins = "gpio1 !! 3929 mux {
5269 function = "q !! 3930 pins = "gpio115", "gpio116";
5270 drive-strengt !! 3931 function = "qup2";
5271 bias-disable; !! 3932 };
>> 3933
>> 3934 config {
>> 3935 pins = "gpio115", "gpio116";
>> 3936 drive-strength = <2>;
>> 3937 bias-disable;
>> 3938 };
5272 }; 3939 };
5273 3940
5274 qup_i2c3_default: qup !! 3941 qup_i2c3_default: qup-i2c3-default {
5275 pins = "gpio1 !! 3942 mux {
5276 function = "q !! 3943 pins = "gpio119", "gpio120";
5277 drive-strengt !! 3944 function = "qup3";
5278 bias-disable; !! 3945 };
>> 3946
>> 3947 config {
>> 3948 pins = "gpio119", "gpio120";
>> 3949 drive-strength = <2>;
>> 3950 bias-disable;
>> 3951 };
5279 }; 3952 };
5280 3953
5281 qup_i2c4_default: qup !! 3954 qup_i2c4_default: qup-i2c4-default {
5282 pins = "gpio8 !! 3955 mux {
5283 function = "q !! 3956 pins = "gpio8", "gpio9";
5284 drive-strengt !! 3957 function = "qup4";
5285 bias-disable; !! 3958 };
>> 3959
>> 3960 config {
>> 3961 pins = "gpio8", "gpio9";
>> 3962 drive-strength = <2>;
>> 3963 bias-disable;
>> 3964 };
5286 }; 3965 };
5287 3966
5288 qup_i2c5_default: qup !! 3967 qup_i2c5_default: qup-i2c5-default {
5289 pins = "gpio1 !! 3968 mux {
5290 function = "q !! 3969 pins = "gpio12", "gpio13";
5291 drive-strengt !! 3970 function = "qup5";
5292 bias-disable; !! 3971 };
>> 3972
>> 3973 config {
>> 3974 pins = "gpio12", "gpio13";
>> 3975 drive-strength = <2>;
>> 3976 bias-disable;
>> 3977 };
5293 }; 3978 };
5294 3979
5295 qup_i2c6_default: qup !! 3980 qup_i2c6_default: qup-i2c6-default {
5296 pins = "gpio1 !! 3981 mux {
5297 function = "q !! 3982 pins = "gpio16", "gpio17";
5298 drive-strengt !! 3983 function = "qup6";
5299 bias-disable; !! 3984 };
>> 3985
>> 3986 config {
>> 3987 pins = "gpio16", "gpio17";
>> 3988 drive-strength = <2>;
>> 3989 bias-disable;
>> 3990 };
5300 }; 3991 };
5301 3992
5302 qup_i2c7_default: qup !! 3993 qup_i2c7_default: qup-i2c7-default {
5303 pins = "gpio2 !! 3994 mux {
5304 function = "q !! 3995 pins = "gpio20", "gpio21";
5305 drive-strengt !! 3996 function = "qup7";
5306 bias-disable; !! 3997 };
>> 3998
>> 3999 config {
>> 4000 pins = "gpio20", "gpio21";
>> 4001 drive-strength = <2>;
>> 4002 bias-disable;
>> 4003 };
5307 }; 4004 };
5308 4005
5309 qup_i2c8_default: qup !! 4006 qup_i2c8_default: qup-i2c8-default {
5310 pins = "gpio2 !! 4007 mux {
5311 function = "q !! 4008 pins = "gpio24", "gpio25";
5312 drive-strengt !! 4009 function = "qup8";
5313 bias-disable; !! 4010 };
>> 4011
>> 4012 config {
>> 4013 pins = "gpio24", "gpio25";
>> 4014 drive-strength = <2>;
>> 4015 bias-disable;
>> 4016 };
5314 }; 4017 };
5315 4018
5316 qup_i2c9_default: qup !! 4019 qup_i2c9_default: qup-i2c9-default {
5317 pins = "gpio1 !! 4020 mux {
5318 function = "q !! 4021 pins = "gpio125", "gpio126";
5319 drive-strengt !! 4022 function = "qup9";
5320 bias-disable; !! 4023 };
>> 4024
>> 4025 config {
>> 4026 pins = "gpio125", "gpio126";
>> 4027 drive-strength = <2>;
>> 4028 bias-disable;
>> 4029 };
5321 }; 4030 };
5322 4031
5323 qup_i2c10_default: qu !! 4032 qup_i2c10_default: qup-i2c10-default {
5324 pins = "gpio1 !! 4033 mux {
5325 function = "q !! 4034 pins = "gpio129", "gpio130";
5326 drive-strengt !! 4035 function = "qup10";
5327 bias-disable; !! 4036 };
>> 4037
>> 4038 config {
>> 4039 pins = "gpio129", "gpio130";
>> 4040 drive-strength = <2>;
>> 4041 bias-disable;
>> 4042 };
5328 }; 4043 };
5329 4044
5330 qup_i2c11_default: qu !! 4045 qup_i2c11_default: qup-i2c11-default {
5331 pins = "gpio6 !! 4046 mux {
5332 function = "q !! 4047 pins = "gpio60", "gpio61";
5333 drive-strengt !! 4048 function = "qup11";
5334 bias-disable; !! 4049 };
>> 4050
>> 4051 config {
>> 4052 pins = "gpio60", "gpio61";
>> 4053 drive-strength = <2>;
>> 4054 bias-disable;
>> 4055 };
5335 }; 4056 };
5336 4057
5337 qup_i2c12_default: qu !! 4058 qup_i2c12_default: qup-i2c12-default {
5338 pins = "gpio3 !! 4059 mux {
5339 function = "q !! 4060 pins = "gpio32", "gpio33";
5340 drive-strengt !! 4061 function = "qup12";
5341 bias-disable; !! 4062 };
>> 4063
>> 4064 config {
>> 4065 pins = "gpio32", "gpio33";
>> 4066 drive-strength = <2>;
>> 4067 bias-disable;
>> 4068 };
5342 }; 4069 };
5343 4070
5344 qup_i2c13_default: qu !! 4071 qup_i2c13_default: qup-i2c13-default {
5345 pins = "gpio3 !! 4072 mux {
5346 function = "q !! 4073 pins = "gpio36", "gpio37";
5347 drive-strengt !! 4074 function = "qup13";
5348 bias-disable; !! 4075 };
>> 4076
>> 4077 config {
>> 4078 pins = "gpio36", "gpio37";
>> 4079 drive-strength = <2>;
>> 4080 bias-disable;
>> 4081 };
5349 }; 4082 };
5350 4083
5351 qup_i2c14_default: qu !! 4084 qup_i2c14_default: qup-i2c14-default {
5352 pins = "gpio4 !! 4085 mux {
5353 function = "q !! 4086 pins = "gpio40", "gpio41";
5354 drive-strengt !! 4087 function = "qup14";
5355 bias-disable; !! 4088 };
>> 4089
>> 4090 config {
>> 4091 pins = "gpio40", "gpio41";
>> 4092 drive-strength = <2>;
>> 4093 bias-disable;
>> 4094 };
5356 }; 4095 };
5357 4096
5358 qup_i2c15_default: qu !! 4097 qup_i2c15_default: qup-i2c15-default {
5359 pins = "gpio4 !! 4098 mux {
5360 function = "q !! 4099 pins = "gpio44", "gpio45";
5361 drive-strengt !! 4100 function = "qup15";
5362 bias-disable; !! 4101 };
>> 4102
>> 4103 config {
>> 4104 pins = "gpio44", "gpio45";
>> 4105 drive-strength = <2>;
>> 4106 bias-disable;
>> 4107 };
5363 }; 4108 };
5364 4109
5365 qup_i2c16_default: qu !! 4110 qup_i2c16_default: qup-i2c16-default {
5366 pins = "gpio4 !! 4111 mux {
5367 function = "q !! 4112 pins = "gpio48", "gpio49";
5368 drive-strengt !! 4113 function = "qup16";
5369 bias-disable; !! 4114 };
>> 4115
>> 4116 config {
>> 4117 pins = "gpio48", "gpio49";
>> 4118 drive-strength = <2>;
>> 4119 bias-disable;
>> 4120 };
5370 }; 4121 };
5371 4122
5372 qup_i2c17_default: qu !! 4123 qup_i2c17_default: qup-i2c17-default {
5373 pins = "gpio5 !! 4124 mux {
5374 function = "q !! 4125 pins = "gpio52", "gpio53";
5375 drive-strengt !! 4126 function = "qup17";
5376 bias-disable; !! 4127 };
>> 4128
>> 4129 config {
>> 4130 pins = "gpio52", "gpio53";
>> 4131 drive-strength = <2>;
>> 4132 bias-disable;
>> 4133 };
5377 }; 4134 };
5378 4135
5379 qup_i2c18_default: qu !! 4136 qup_i2c18_default: qup-i2c18-default {
5380 pins = "gpio5 !! 4137 mux {
5381 function = "q !! 4138 pins = "gpio56", "gpio57";
5382 drive-strengt !! 4139 function = "qup18";
5383 bias-disable; !! 4140 };
>> 4141
>> 4142 config {
>> 4143 pins = "gpio56", "gpio57";
>> 4144 drive-strength = <2>;
>> 4145 bias-disable;
>> 4146 };
5384 }; 4147 };
5385 4148
5386 qup_i2c19_default: qu !! 4149 qup_i2c19_default: qup-i2c19-default {
5387 pins = "gpio0 !! 4150 mux {
5388 function = "q !! 4151 pins = "gpio0", "gpio1";
5389 drive-strengt !! 4152 function = "qup19";
5390 bias-disable; !! 4153 };
>> 4154
>> 4155 config {
>> 4156 pins = "gpio0", "gpio1";
>> 4157 drive-strength = <2>;
>> 4158 bias-disable;
>> 4159 };
5391 }; 4160 };
5392 4161
5393 qup_spi0_cs: qup-spi0 !! 4162 qup_spi0_cs: qup-spi0-cs {
5394 pins = "gpio3 4163 pins = "gpio31";
5395 function = "q 4164 function = "qup0";
5396 }; 4165 };
5397 4166
5398 qup_spi0_cs_gpio: qup !! 4167 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
5399 pins = "gpio3 4168 pins = "gpio31";
5400 function = "g 4169 function = "gpio";
5401 }; 4170 };
5402 4171
5403 qup_spi0_data_clk: qu !! 4172 qup_spi0_data_clk: qup-spi0-data-clk {
5404 pins = "gpio2 4173 pins = "gpio28", "gpio29",
5405 "gpio3 4174 "gpio30";
5406 function = "q 4175 function = "qup0";
5407 }; 4176 };
5408 4177
5409 qup_spi1_cs: qup-spi1 !! 4178 qup_spi1_cs: qup-spi1-cs {
5410 pins = "gpio7 4179 pins = "gpio7";
5411 function = "q 4180 function = "qup1";
5412 }; 4181 };
5413 4182
5414 qup_spi1_cs_gpio: qup !! 4183 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
5415 pins = "gpio7 4184 pins = "gpio7";
5416 function = "g 4185 function = "gpio";
5417 }; 4186 };
5418 4187
5419 qup_spi1_data_clk: qu !! 4188 qup_spi1_data_clk: qup-spi1-data-clk {
5420 pins = "gpio4 4189 pins = "gpio4", "gpio5",
5421 "gpio6 4190 "gpio6";
5422 function = "q 4191 function = "qup1";
5423 }; 4192 };
5424 4193
5425 qup_spi2_cs: qup-spi2 !! 4194 qup_spi2_cs: qup-spi2-cs {
5426 pins = "gpio1 4195 pins = "gpio118";
5427 function = "q 4196 function = "qup2";
5428 }; 4197 };
5429 4198
5430 qup_spi2_cs_gpio: qup !! 4199 qup_spi2_cs_gpio: qup-spi2-cs-gpio {
5431 pins = "gpio1 4200 pins = "gpio118";
5432 function = "g 4201 function = "gpio";
5433 }; 4202 };
5434 4203
5435 qup_spi2_data_clk: qu !! 4204 qup_spi2_data_clk: qup-spi2-data-clk {
5436 pins = "gpio1 4205 pins = "gpio115", "gpio116",
5437 "gpio1 4206 "gpio117";
5438 function = "q 4207 function = "qup2";
5439 }; 4208 };
5440 4209
5441 qup_spi3_cs: qup-spi3 !! 4210 qup_spi3_cs: qup-spi3-cs {
5442 pins = "gpio1 4211 pins = "gpio122";
5443 function = "q 4212 function = "qup3";
5444 }; 4213 };
5445 4214
5446 qup_spi3_cs_gpio: qup !! 4215 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
5447 pins = "gpio1 4216 pins = "gpio122";
5448 function = "g 4217 function = "gpio";
5449 }; 4218 };
5450 4219
5451 qup_spi3_data_clk: qu !! 4220 qup_spi3_data_clk: qup-spi3-data-clk {
5452 pins = "gpio1 4221 pins = "gpio119", "gpio120",
5453 "gpio1 4222 "gpio121";
5454 function = "q 4223 function = "qup3";
5455 }; 4224 };
5456 4225
5457 qup_spi4_cs: qup-spi4 !! 4226 qup_spi4_cs: qup-spi4-cs {
5458 pins = "gpio1 4227 pins = "gpio11";
5459 function = "q 4228 function = "qup4";
5460 }; 4229 };
5461 4230
5462 qup_spi4_cs_gpio: qup !! 4231 qup_spi4_cs_gpio: qup-spi4-cs-gpio {
5463 pins = "gpio1 4232 pins = "gpio11";
5464 function = "g 4233 function = "gpio";
5465 }; 4234 };
5466 4235
5467 qup_spi4_data_clk: qu !! 4236 qup_spi4_data_clk: qup-spi4-data-clk {
5468 pins = "gpio8 4237 pins = "gpio8", "gpio9",
5469 "gpio1 4238 "gpio10";
5470 function = "q 4239 function = "qup4";
5471 }; 4240 };
5472 4241
5473 qup_spi5_cs: qup-spi5 !! 4242 qup_spi5_cs: qup-spi5-cs {
5474 pins = "gpio1 4243 pins = "gpio15";
5475 function = "q 4244 function = "qup5";
5476 }; 4245 };
5477 4246
5478 qup_spi5_cs_gpio: qup !! 4247 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
5479 pins = "gpio1 4248 pins = "gpio15";
5480 function = "g 4249 function = "gpio";
5481 }; 4250 };
5482 4251
5483 qup_spi5_data_clk: qu !! 4252 qup_spi5_data_clk: qup-spi5-data-clk {
5484 pins = "gpio1 4253 pins = "gpio12", "gpio13",
5485 "gpio1 4254 "gpio14";
5486 function = "q 4255 function = "qup5";
5487 }; 4256 };
5488 4257
5489 qup_spi6_cs: qup-spi6 !! 4258 qup_spi6_cs: qup-spi6-cs {
5490 pins = "gpio1 4259 pins = "gpio19";
5491 function = "q 4260 function = "qup6";
5492 }; 4261 };
5493 4262
5494 qup_spi6_cs_gpio: qup !! 4263 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
5495 pins = "gpio1 4264 pins = "gpio19";
5496 function = "g 4265 function = "gpio";
5497 }; 4266 };
5498 4267
5499 qup_spi6_data_clk: qu !! 4268 qup_spi6_data_clk: qup-spi6-data-clk {
5500 pins = "gpio1 4269 pins = "gpio16", "gpio17",
5501 "gpio1 4270 "gpio18";
5502 function = "q 4271 function = "qup6";
5503 }; 4272 };
5504 4273
5505 qup_spi7_cs: qup-spi7 !! 4274 qup_spi7_cs: qup-spi7-cs {
5506 pins = "gpio2 4275 pins = "gpio23";
5507 function = "q 4276 function = "qup7";
5508 }; 4277 };
5509 4278
5510 qup_spi7_cs_gpio: qup !! 4279 qup_spi7_cs_gpio: qup-spi7-cs-gpio {
5511 pins = "gpio2 4280 pins = "gpio23";
5512 function = "g 4281 function = "gpio";
5513 }; 4282 };
5514 4283
5515 qup_spi7_data_clk: qu !! 4284 qup_spi7_data_clk: qup-spi7-data-clk {
5516 pins = "gpio2 4285 pins = "gpio20", "gpio21",
5517 "gpio2 4286 "gpio22";
5518 function = "q 4287 function = "qup7";
5519 }; 4288 };
5520 4289
5521 qup_spi8_cs: qup-spi8 !! 4290 qup_spi8_cs: qup-spi8-cs {
5522 pins = "gpio2 4291 pins = "gpio27";
5523 function = "q 4292 function = "qup8";
5524 }; 4293 };
5525 4294
5526 qup_spi8_cs_gpio: qup !! 4295 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
5527 pins = "gpio2 4296 pins = "gpio27";
5528 function = "g 4297 function = "gpio";
5529 }; 4298 };
5530 4299
5531 qup_spi8_data_clk: qu !! 4300 qup_spi8_data_clk: qup-spi8-data-clk {
5532 pins = "gpio2 4301 pins = "gpio24", "gpio25",
5533 "gpio2 4302 "gpio26";
5534 function = "q 4303 function = "qup8";
5535 }; 4304 };
5536 4305
5537 qup_spi9_cs: qup-spi9 !! 4306 qup_spi9_cs: qup-spi9-cs {
5538 pins = "gpio1 4307 pins = "gpio128";
5539 function = "q 4308 function = "qup9";
5540 }; 4309 };
5541 4310
5542 qup_spi9_cs_gpio: qup !! 4311 qup_spi9_cs_gpio: qup-spi9-cs-gpio {
5543 pins = "gpio1 4312 pins = "gpio128";
5544 function = "g 4313 function = "gpio";
5545 }; 4314 };
5546 4315
5547 qup_spi9_data_clk: qu !! 4316 qup_spi9_data_clk: qup-spi9-data-clk {
5548 pins = "gpio1 4317 pins = "gpio125", "gpio126",
5549 "gpio1 4318 "gpio127";
5550 function = "q 4319 function = "qup9";
5551 }; 4320 };
5552 4321
5553 qup_spi10_cs: qup-spi !! 4322 qup_spi10_cs: qup-spi10-cs {
5554 pins = "gpio1 4323 pins = "gpio132";
5555 function = "q 4324 function = "qup10";
5556 }; 4325 };
5557 4326
5558 qup_spi10_cs_gpio: qu !! 4327 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
5559 pins = "gpio1 4328 pins = "gpio132";
5560 function = "g 4329 function = "gpio";
5561 }; 4330 };
5562 4331
5563 qup_spi10_data_clk: q !! 4332 qup_spi10_data_clk: qup-spi10-data-clk {
5564 pins = "gpio1 4333 pins = "gpio129", "gpio130",
5565 "gpio1 4334 "gpio131";
5566 function = "q 4335 function = "qup10";
5567 }; 4336 };
5568 4337
5569 qup_spi11_cs: qup-spi !! 4338 qup_spi11_cs: qup-spi11-cs {
5570 pins = "gpio6 4339 pins = "gpio63";
5571 function = "q 4340 function = "qup11";
5572 }; 4341 };
5573 4342
5574 qup_spi11_cs_gpio: qu !! 4343 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
5575 pins = "gpio6 4344 pins = "gpio63";
5576 function = "g 4345 function = "gpio";
5577 }; 4346 };
5578 4347
5579 qup_spi11_data_clk: q !! 4348 qup_spi11_data_clk: qup-spi11-data-clk {
5580 pins = "gpio6 4349 pins = "gpio60", "gpio61",
5581 "gpio6 4350 "gpio62";
5582 function = "q 4351 function = "qup11";
5583 }; 4352 };
5584 4353
5585 qup_spi12_cs: qup-spi !! 4354 qup_spi12_cs: qup-spi12-cs {
5586 pins = "gpio3 4355 pins = "gpio35";
5587 function = "q 4356 function = "qup12";
5588 }; 4357 };
5589 4358
5590 qup_spi12_cs_gpio: qu !! 4359 qup_spi12_cs_gpio: qup-spi12-cs-gpio {
5591 pins = "gpio3 4360 pins = "gpio35";
5592 function = "g 4361 function = "gpio";
5593 }; 4362 };
5594 4363
5595 qup_spi12_data_clk: q !! 4364 qup_spi12_data_clk: qup-spi12-data-clk {
5596 pins = "gpio3 4365 pins = "gpio32", "gpio33",
5597 "gpio3 4366 "gpio34";
5598 function = "q 4367 function = "qup12";
5599 }; 4368 };
5600 4369
5601 qup_spi13_cs: qup-spi !! 4370 qup_spi13_cs: qup-spi13-cs {
5602 pins = "gpio3 4371 pins = "gpio39";
5603 function = "q 4372 function = "qup13";
5604 }; 4373 };
5605 4374
5606 qup_spi13_cs_gpio: qu !! 4375 qup_spi13_cs_gpio: qup-spi13-cs-gpio {
5607 pins = "gpio3 4376 pins = "gpio39";
5608 function = "g 4377 function = "gpio";
5609 }; 4378 };
5610 4379
5611 qup_spi13_data_clk: q !! 4380 qup_spi13_data_clk: qup-spi13-data-clk {
5612 pins = "gpio3 4381 pins = "gpio36", "gpio37",
5613 "gpio3 4382 "gpio38";
5614 function = "q 4383 function = "qup13";
5615 }; 4384 };
5616 4385
5617 qup_spi14_cs: qup-spi !! 4386 qup_spi14_cs: qup-spi14-cs {
5618 pins = "gpio4 4387 pins = "gpio43";
5619 function = "q 4388 function = "qup14";
5620 }; 4389 };
5621 4390
5622 qup_spi14_cs_gpio: qu !! 4391 qup_spi14_cs_gpio: qup-spi14-cs-gpio {
5623 pins = "gpio4 4392 pins = "gpio43";
5624 function = "g 4393 function = "gpio";
5625 }; 4394 };
5626 4395
5627 qup_spi14_data_clk: q !! 4396 qup_spi14_data_clk: qup-spi14-data-clk {
5628 pins = "gpio4 4397 pins = "gpio40", "gpio41",
5629 "gpio4 4398 "gpio42";
5630 function = "q 4399 function = "qup14";
5631 }; 4400 };
5632 4401
5633 qup_spi15_cs: qup-spi !! 4402 qup_spi15_cs: qup-spi15-cs {
5634 pins = "gpio4 4403 pins = "gpio47";
5635 function = "q 4404 function = "qup15";
5636 }; 4405 };
5637 4406
5638 qup_spi15_cs_gpio: qu !! 4407 qup_spi15_cs_gpio: qup-spi15-cs-gpio {
5639 pins = "gpio4 4408 pins = "gpio47";
5640 function = "g 4409 function = "gpio";
5641 }; 4410 };
5642 4411
5643 qup_spi15_data_clk: q !! 4412 qup_spi15_data_clk: qup-spi15-data-clk {
5644 pins = "gpio4 4413 pins = "gpio44", "gpio45",
5645 "gpio4 4414 "gpio46";
5646 function = "q 4415 function = "qup15";
5647 }; 4416 };
5648 4417
5649 qup_spi16_cs: qup-spi !! 4418 qup_spi16_cs: qup-spi16-cs {
5650 pins = "gpio5 4419 pins = "gpio51";
5651 function = "q 4420 function = "qup16";
5652 }; 4421 };
5653 4422
5654 qup_spi16_cs_gpio: qu !! 4423 qup_spi16_cs_gpio: qup-spi16-cs-gpio {
5655 pins = "gpio5 4424 pins = "gpio51";
5656 function = "g 4425 function = "gpio";
5657 }; 4426 };
5658 4427
5659 qup_spi16_data_clk: q !! 4428 qup_spi16_data_clk: qup-spi16-data-clk {
5660 pins = "gpio4 4429 pins = "gpio48", "gpio49",
5661 "gpio5 4430 "gpio50";
5662 function = "q 4431 function = "qup16";
5663 }; 4432 };
5664 4433
5665 qup_spi17_cs: qup-spi !! 4434 qup_spi17_cs: qup-spi17-cs {
5666 pins = "gpio5 4435 pins = "gpio55";
5667 function = "q 4436 function = "qup17";
5668 }; 4437 };
5669 4438
5670 qup_spi17_cs_gpio: qu !! 4439 qup_spi17_cs_gpio: qup-spi17-cs-gpio {
5671 pins = "gpio5 4440 pins = "gpio55";
5672 function = "g 4441 function = "gpio";
5673 }; 4442 };
5674 4443
5675 qup_spi17_data_clk: q !! 4444 qup_spi17_data_clk: qup-spi17-data-clk {
5676 pins = "gpio5 4445 pins = "gpio52", "gpio53",
5677 "gpio5 4446 "gpio54";
5678 function = "q 4447 function = "qup17";
5679 }; 4448 };
5680 4449
5681 qup_spi18_cs: qup-spi !! 4450 qup_spi18_cs: qup-spi18-cs {
5682 pins = "gpio5 4451 pins = "gpio59";
5683 function = "q 4452 function = "qup18";
5684 }; 4453 };
5685 4454
5686 qup_spi18_cs_gpio: qu !! 4455 qup_spi18_cs_gpio: qup-spi18-cs-gpio {
5687 pins = "gpio5 4456 pins = "gpio59";
5688 function = "g 4457 function = "gpio";
5689 }; 4458 };
5690 4459
5691 qup_spi18_data_clk: q !! 4460 qup_spi18_data_clk: qup-spi18-data-clk {
5692 pins = "gpio5 4461 pins = "gpio56", "gpio57",
5693 "gpio5 4462 "gpio58";
5694 function = "q 4463 function = "qup18";
5695 }; 4464 };
5696 4465
5697 qup_spi19_cs: qup-spi !! 4466 qup_spi19_cs: qup-spi19-cs {
5698 pins = "gpio3 4467 pins = "gpio3";
5699 function = "q 4468 function = "qup19";
5700 }; 4469 };
5701 4470
5702 qup_spi19_cs_gpio: qu !! 4471 qup_spi19_cs_gpio: qup-spi19-cs-gpio {
5703 pins = "gpio3 4472 pins = "gpio3";
5704 function = "g 4473 function = "gpio";
5705 }; 4474 };
5706 4475
5707 qup_spi19_data_clk: q !! 4476 qup_spi19_data_clk: qup-spi19-data-clk {
5708 pins = "gpio0 4477 pins = "gpio0", "gpio1",
5709 "gpio2 4478 "gpio2";
5710 function = "q 4479 function = "qup19";
5711 }; 4480 };
5712 4481
5713 qup_uart2_default: qu !! 4482 qup_uart2_default: qup-uart2-default {
5714 pins = "gpio1 !! 4483 mux {
5715 function = "q !! 4484 pins = "gpio117", "gpio118";
>> 4485 function = "qup2";
>> 4486 };
5716 }; 4487 };
5717 4488
5718 qup_uart6_default: qu !! 4489 qup_uart6_default: qup-uart6-default {
5719 pins = "gpio1 !! 4490 mux {
5720 function = "q !! 4491 pins = "gpio16", "gpio17",
>> 4492 "gpio18", "gpio19";
>> 4493 function = "qup6";
>> 4494 };
5721 }; 4495 };
5722 4496
5723 qup_uart12_default: q !! 4497 qup_uart12_default: qup-uart12-default {
5724 pins = "gpio3 !! 4498 mux {
5725 function = "q !! 4499 pins = "gpio34", "gpio35";
>> 4500 function = "qup12";
>> 4501 };
5726 }; 4502 };
5727 4503
5728 qup_uart17_default: q !! 4504 qup_uart17_default: qup-uart17-default {
5729 pins = "gpio5 !! 4505 mux {
5730 function = "q !! 4506 pins = "gpio52", "gpio53",
>> 4507 "gpio54", "gpio55";
>> 4508 function = "qup17";
>> 4509 };
5731 }; 4510 };
5732 4511
5733 qup_uart18_default: q !! 4512 qup_uart18_default: qup-uart18-default {
5734 pins = "gpio5 !! 4513 mux {
5735 function = "q !! 4514 pins = "gpio58", "gpio59";
>> 4515 function = "qup18";
>> 4516 };
5736 }; 4517 };
5737 4518
5738 tert_mi2s_active: ter !! 4519 tert_mi2s_active: tert-mi2s-active {
5739 sck-pins { !! 4520 sck {
5740 pins 4521 pins = "gpio133";
5741 funct 4522 function = "mi2s2_sck";
5742 drive 4523 drive-strength = <8>;
5743 bias- 4524 bias-disable;
5744 }; 4525 };
5745 4526
5746 data0-pins { !! 4527 data0 {
5747 pins 4528 pins = "gpio134";
5748 funct 4529 function = "mi2s2_data0";
5749 drive 4530 drive-strength = <8>;
5750 bias- 4531 bias-disable;
5751 outpu 4532 output-high;
5752 }; 4533 };
5753 4534
5754 ws-pins { !! 4535 ws {
5755 pins 4536 pins = "gpio135";
5756 funct 4537 function = "mi2s2_ws";
5757 drive 4538 drive-strength = <8>;
5758 outpu 4539 output-high;
5759 }; 4540 };
5760 }; 4541 };
5761 4542
5762 sdc2_sleep_state: sdc !! 4543 sdc2_sleep_state: sdc2-sleep {
5763 clk-pins { !! 4544 clk {
5764 pins 4545 pins = "sdc2_clk";
5765 drive 4546 drive-strength = <2>;
5766 bias- 4547 bias-disable;
5767 }; 4548 };
5768 4549
5769 cmd-pins { !! 4550 cmd {
5770 pins 4551 pins = "sdc2_cmd";
5771 drive 4552 drive-strength = <2>;
5772 bias- 4553 bias-pull-up;
5773 }; 4554 };
5774 4555
5775 data-pins { !! 4556 data {
5776 pins 4557 pins = "sdc2_data";
5777 drive 4558 drive-strength = <2>;
5778 bias- 4559 bias-pull-up;
5779 }; 4560 };
5780 }; 4561 };
5781 4562
5782 pcie0_default_state: !! 4563 pcie0_default_state: pcie0-default {
5783 perst-pins { !! 4564 perst {
5784 pins 4565 pins = "gpio79";
5785 funct 4566 function = "gpio";
5786 drive 4567 drive-strength = <2>;
5787 bias- 4568 bias-pull-down;
5788 }; 4569 };
5789 4570
5790 clkreq-pins { !! 4571 clkreq {
5791 pins 4572 pins = "gpio80";
5792 funct 4573 function = "pci_e0";
5793 drive 4574 drive-strength = <2>;
5794 bias- 4575 bias-pull-up;
5795 }; 4576 };
5796 4577
5797 wake-pins { !! 4578 wake {
5798 pins 4579 pins = "gpio81";
5799 funct 4580 function = "gpio";
5800 drive 4581 drive-strength = <2>;
5801 bias- 4582 bias-pull-up;
5802 }; 4583 };
5803 }; 4584 };
5804 4585
5805 pcie1_default_state: !! 4586 pcie1_default_state: pcie1-default {
5806 perst-pins { !! 4587 perst {
5807 pins 4588 pins = "gpio82";
5808 funct 4589 function = "gpio";
5809 drive 4590 drive-strength = <2>;
5810 bias- 4591 bias-pull-down;
5811 }; 4592 };
5812 4593
5813 clkreq-pins { !! 4594 clkreq {
5814 pins 4595 pins = "gpio83";
5815 funct 4596 function = "pci_e1";
5816 drive 4597 drive-strength = <2>;
5817 bias- 4598 bias-pull-up;
5818 }; 4599 };
5819 4600
5820 wake-pins { !! 4601 wake {
5821 pins 4602 pins = "gpio84";
5822 funct 4603 function = "gpio";
5823 drive 4604 drive-strength = <2>;
5824 bias- 4605 bias-pull-up;
5825 }; 4606 };
5826 }; 4607 };
5827 4608
5828 pcie2_default_state: !! 4609 pcie2_default_state: pcie2-default {
5829 perst-pins { !! 4610 perst {
5830 pins 4611 pins = "gpio85";
5831 funct 4612 function = "gpio";
5832 drive 4613 drive-strength = <2>;
5833 bias- 4614 bias-pull-down;
5834 }; 4615 };
5835 4616
5836 clkreq-pins { !! 4617 clkreq {
5837 pins 4618 pins = "gpio86";
5838 funct 4619 function = "pci_e2";
5839 drive 4620 drive-strength = <2>;
5840 bias- 4621 bias-pull-up;
5841 }; 4622 };
5842 4623
5843 wake-pins { !! 4624 wake {
5844 pins 4625 pins = "gpio87";
5845 funct 4626 function = "gpio";
5846 drive 4627 drive-strength = <2>;
5847 bias- 4628 bias-pull-up;
5848 }; 4629 };
5849 }; 4630 };
5850 }; 4631 };
5851 4632
5852 apps_smmu: iommu@15000000 { 4633 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 4634 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 4635 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 4636 #iommu-cells = <2>;
5856 #global-interrupts = 4637 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 4638 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 4639 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 4640 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 4641 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 4642 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 4643 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 4644 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 4645 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 4646 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 4647 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 4648 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 4649 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 4650 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 4651 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 4652 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 4653 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 4654 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 4655 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 4656 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 4657 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 4658 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 4659 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 4660 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 4661 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 4662 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 4663 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 4664 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 4665 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 4666 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 4667 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 4668 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 4669 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 4670 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 4671 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 4672 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 4673 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 4674 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 4675 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 4676 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 4677 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 4678 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 4679 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 4680 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 4681 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 4682 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 4683 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 4684 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 4685 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 4686 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 4687 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 4688 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 4689 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 4690 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 4691 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 4692 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 4693 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 4694 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 4695 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 4696 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 4697 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 4698 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 4699 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 4700 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 4701 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 4702 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 4703 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 4704 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 4705 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 4706 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 4707 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 4708 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 4709 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 4710 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 4711 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 4712 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 4713 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 4714 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 4715 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 4716 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 4717 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 4718 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 4719 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 4720 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 4721 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 4722 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 4723 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 4724 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 4725 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 4726 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 4727 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 4728 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 4729 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 4730 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 4731 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 4732 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 4733 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 4734 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 4735 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 4736 };
5957 4737
5958 adsp: remoteproc@17300000 { 4738 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 4739 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 4740 reg = <0 0x17300000 0 0x100>;
5961 4741
5962 interrupts-extended = !! 4742 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 4743 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 4744 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 4745 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 4746 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 4747 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 4748 "handover", "stop-ack";
5969 4749
5970 clocks = <&rpmhcc RPM 4750 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 4751 clock-names = "xo";
5972 4752
5973 power-domains = <&rpm !! 4753 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 4754 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 4755 power-domain-names = "lcx", "lmx";
5976 4756
5977 memory-region = <&ads 4757 memory-region = <&adsp_mem>;
5978 4758
5979 qcom,qmp = <&aoss_qmp 4759 qcom,qmp = <&aoss_qmp>;
5980 4760
5981 qcom,smem-states = <& 4761 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 4762 qcom,smem-state-names = "stop";
5983 4763
5984 status = "disabled"; 4764 status = "disabled";
5985 4765
5986 glink-edge { 4766 glink-edge {
5987 interrupts-ex 4767 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 4768 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 4769 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 4770 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 4771 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 4772
5993 label = "lpas 4773 label = "lpass";
5994 qcom,remote-p 4774 qcom,remote-pid = <2>;
5995 4775
5996 apr { 4776 apr {
5997 compa 4777 compatible = "qcom,apr-v2";
5998 qcom, 4778 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 4779 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 4780 #address-cells = <1>;
6001 #size 4781 #size-cells = <0>;
6002 4782
6003 servi !! 4783 apr-service@3 {
6004 4784 reg = <APR_SVC_ADSP_CORE>;
6005 4785 compatible = "qcom,q6core";
6006 4786 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 4787 };
6008 4788
6009 q6afe !! 4789 q6afe: apr-service@4 {
6010 4790 compatible = "qcom,q6afe";
6011 4791 reg = <APR_SVC_AFE>;
6012 4792 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 4793 q6afedai: dais {
6014 4794 compatible = "qcom,q6afe-dais";
6015 4795 #address-cells = <1>;
6016 4796 #size-cells = <0>;
6017 4797 #sound-dai-cells = <1>;
6018 4798 };
6019 4799
6020 !! 4800 q6afecc: cc {
6021 4801 compatible = "qcom,q6afe-clocks";
6022 4802 #clock-cells = <2>;
6023 4803 };
6024 }; 4804 };
6025 4805
6026 q6asm !! 4806 q6asm: apr-service@7 {
6027 4807 compatible = "qcom,q6asm";
6028 4808 reg = <APR_SVC_ASM>;
6029 4809 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 4810 q6asmdai: dais {
6031 4811 compatible = "qcom,q6asm-dais";
6032 4812 #address-cells = <1>;
6033 4813 #size-cells = <0>;
6034 4814 #sound-dai-cells = <1>;
6035 4815 iommus = <&apps_smmu 0x1801 0x0>;
6036 4816 };
6037 }; 4817 };
6038 4818
6039 q6adm !! 4819 q6adm: apr-service@8 {
6040 4820 compatible = "qcom,q6adm";
6041 4821 reg = <APR_SVC_ADM>;
6042 4822 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 4823 q6routing: routing {
6044 4824 compatible = "qcom,q6adm-routing";
6045 4825 #sound-dai-cells = <0>;
6046 4826 };
6047 }; 4827 };
6048 }; 4828 };
6049 4829
6050 fastrpc { 4830 fastrpc {
6051 compa 4831 compatible = "qcom,fastrpc";
6052 qcom, 4832 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 4833 label = "adsp";
6054 qcom, 4834 qcom,non-secure-domain;
6055 #addr 4835 #address-cells = <1>;
6056 #size 4836 #size-cells = <0>;
6057 4837
6058 compu 4838 compute-cb@3 {
6059 4839 compatible = "qcom,fastrpc-compute-cb";
6060 4840 reg = <3>;
6061 4841 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 4842 };
6063 4843
6064 compu 4844 compute-cb@4 {
6065 4845 compatible = "qcom,fastrpc-compute-cb";
6066 4846 reg = <4>;
6067 4847 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 4848 };
6069 4849
6070 compu 4850 compute-cb@5 {
6071 4851 compatible = "qcom,fastrpc-compute-cb";
6072 4852 reg = <5>;
6073 4853 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 4854 };
6075 }; 4855 };
6076 }; 4856 };
6077 }; 4857 };
6078 4858
6079 intc: interrupt-controller@17 4859 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 4860 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 4861 #interrupt-cells = <3>;
6082 interrupt-controller; 4862 interrupt-controller;
6083 reg = <0x0 0x17a00000 4863 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 4864 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 4865 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 4866 };
6087 4867
6088 watchdog@17c10000 { 4868 watchdog@17c10000 {
6089 compatible = "qcom,ap 4869 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 4870 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 4871 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 4872 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 4873 };
6094 4874
6095 timer@17c20000 { 4875 timer@17c20000 {
6096 #address-cells = <1>; 4876 #address-cells = <1>;
6097 #size-cells = <1>; 4877 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 4878 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 4879 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 4880 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 4881 clock-frequency = <19200000>;
6102 4882
6103 frame@17c21000 { 4883 frame@17c21000 {
6104 frame-number 4884 frame-number = <0>;
6105 interrupts = 4885 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 4886 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 4887 reg = <0x17c21000 0x1000>,
6108 <0x17c2 4888 <0x17c22000 0x1000>;
6109 }; 4889 };
6110 4890
6111 frame@17c23000 { 4891 frame@17c23000 {
6112 frame-number 4892 frame-number = <1>;
6113 interrupts = 4893 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 4894 reg = <0x17c23000 0x1000>;
6115 status = "dis 4895 status = "disabled";
6116 }; 4896 };
6117 4897
6118 frame@17c25000 { 4898 frame@17c25000 {
6119 frame-number 4899 frame-number = <2>;
6120 interrupts = 4900 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 4901 reg = <0x17c25000 0x1000>;
6122 status = "dis 4902 status = "disabled";
6123 }; 4903 };
6124 4904
6125 frame@17c27000 { 4905 frame@17c27000 {
6126 frame-number 4906 frame-number = <3>;
6127 interrupts = 4907 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 4908 reg = <0x17c27000 0x1000>;
6129 status = "dis 4909 status = "disabled";
6130 }; 4910 };
6131 4911
6132 frame@17c29000 { 4912 frame@17c29000 {
6133 frame-number 4913 frame-number = <4>;
6134 interrupts = 4914 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 4915 reg = <0x17c29000 0x1000>;
6136 status = "dis 4916 status = "disabled";
6137 }; 4917 };
6138 4918
6139 frame@17c2b000 { 4919 frame@17c2b000 {
6140 frame-number 4920 frame-number = <5>;
6141 interrupts = 4921 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 4922 reg = <0x17c2b000 0x1000>;
6143 status = "dis 4923 status = "disabled";
6144 }; 4924 };
6145 4925
6146 frame@17c2d000 { 4926 frame@17c2d000 {
6147 frame-number 4927 frame-number = <6>;
6148 interrupts = 4928 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 4929 reg = <0x17c2d000 0x1000>;
6150 status = "dis 4930 status = "disabled";
6151 }; 4931 };
6152 }; 4932 };
6153 4933
6154 apps_rsc: rsc@18200000 { 4934 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 4935 label = "apps_rsc";
6156 compatible = "qcom,rp 4936 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 4937 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 4938 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 4939 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 4940 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 4941 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 4942 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 4943 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 4944 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 4945 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 4946 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 4947 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU <<
6169 4948
6170 rpmhcc: clock-control 4949 rpmhcc: clock-controller {
6171 compatible = 4950 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 4951 #clock-cells = <1>;
6173 clock-names = 4952 clock-names = "xo";
6174 clocks = <&xo 4953 clocks = <&xo_board>;
6175 }; 4954 };
6176 4955
6177 rpmhpd: power-control 4956 rpmhpd: power-controller {
6178 compatible = 4957 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 4958 #power-domain-cells = <1>;
6180 operating-poi 4959 operating-points-v2 = <&rpmhpd_opp_table>;
6181 4960
6182 rpmhpd_opp_ta 4961 rpmhpd_opp_table: opp-table {
6183 compa 4962 compatible = "operating-points-v2";
6184 4963
6185 rpmhp 4964 rpmhpd_opp_ret: opp1 {
6186 4965 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 4966 };
6188 4967
6189 rpmhp 4968 rpmhpd_opp_min_svs: opp2 {
6190 4969 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 4970 };
6192 4971
6193 rpmhp 4972 rpmhpd_opp_low_svs: opp3 {
6194 4973 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 4974 };
6196 4975
6197 rpmhp 4976 rpmhpd_opp_svs: opp4 {
6198 4977 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 4978 };
6200 4979
6201 rpmhp 4980 rpmhpd_opp_svs_l1: opp5 {
6202 4981 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 4982 };
6204 4983
6205 rpmhp 4984 rpmhpd_opp_nom: opp6 {
6206 4985 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 4986 };
6208 4987
6209 rpmhp 4988 rpmhpd_opp_nom_l1: opp7 {
6210 4989 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 4990 };
6212 4991
6213 rpmhp 4992 rpmhpd_opp_nom_l2: opp8 {
6214 4993 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 4994 };
6216 4995
6217 rpmhp 4996 rpmhpd_opp_turbo: opp9 {
6218 4997 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 4998 };
6220 4999
6221 rpmhp 5000 rpmhpd_opp_turbo_l1: opp10 {
6222 5001 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 5002 };
6224 }; 5003 };
6225 }; 5004 };
6226 5005
6227 apps_bcm_voter: bcm-v 5006 apps_bcm_voter: bcm-voter {
6228 compatible = 5007 compatible = "qcom,bcm-voter";
6229 }; 5008 };
6230 }; 5009 };
6231 5010
6232 epss_l3: interconnect@1859000 5011 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm !! 5012 compatible = "qcom,sm8250-epss-l3";
6234 reg = <0 0x18590000 0 5013 reg = <0 0x18590000 0 0x1000>;
6235 5014
6236 clocks = <&rpmhcc RPM 5015 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 5016 clock-names = "xo", "alternate";
6238 5017
6239 #interconnect-cells = 5018 #interconnect-cells = <1>;
6240 }; 5019 };
6241 5020
6242 cpufreq_hw: cpufreq@18591000 5021 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 5022 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 5023 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 5024 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 5025 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 5026 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 5027 "freq-domain2";
6249 5028
6250 clocks = <&rpmhcc RPM 5029 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 5030 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 5031 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 5032 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 5033 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 5034 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 5035 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 5036 };
6259 }; 5037 };
6260 5038
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 5039 timer {
6265 compatible = "arm,armv8-timer 5040 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 5041 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 5042 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 5043 <GIC_PPI 14
6269 (GIC_CPU_MASK 5044 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 5045 <GIC_PPI 11
6271 (GIC_CPU_MASK 5046 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 5047 <GIC_PPI 10
6273 (GIC_CPU_MASK 5048 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 5049 };
6275 5050
6276 thermal-zones { 5051 thermal-zones {
6277 cpu0-thermal { 5052 cpu0-thermal {
6278 polling-delay-passive 5053 polling-delay-passive = <250>;
>> 5054 polling-delay = <1000>;
6279 5055
6280 thermal-sensors = <&t 5056 thermal-sensors = <&tsens0 1>;
6281 5057
6282 trips { 5058 trips {
6283 cpu0_alert0: 5059 cpu0_alert0: trip-point0 {
6284 tempe 5060 temperature = <90000>;
6285 hyste 5061 hysteresis = <2000>;
6286 type 5062 type = "passive";
6287 }; 5063 };
6288 5064
6289 cpu0_alert1: 5065 cpu0_alert1: trip-point1 {
6290 tempe 5066 temperature = <95000>;
6291 hyste 5067 hysteresis = <2000>;
6292 type 5068 type = "passive";
6293 }; 5069 };
6294 5070
6295 cpu0_crit: cp !! 5071 cpu0_crit: cpu_crit {
6296 tempe 5072 temperature = <110000>;
6297 hyste 5073 hysteresis = <1000>;
6298 type 5074 type = "critical";
6299 }; 5075 };
6300 }; 5076 };
6301 5077
6302 cooling-maps { 5078 cooling-maps {
6303 map0 { 5079 map0 {
6304 trip 5080 trip = <&cpu0_alert0>;
6305 cooli 5081 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 5082 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 5083 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 5084 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 5085 };
6310 map1 { 5086 map1 {
6311 trip 5087 trip = <&cpu0_alert1>;
6312 cooli 5088 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 5089 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 5090 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 5091 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 5092 };
6317 }; 5093 };
6318 }; 5094 };
6319 5095
6320 cpu1-thermal { 5096 cpu1-thermal {
6321 polling-delay-passive 5097 polling-delay-passive = <250>;
>> 5098 polling-delay = <1000>;
6322 5099
6323 thermal-sensors = <&t 5100 thermal-sensors = <&tsens0 2>;
6324 5101
6325 trips { 5102 trips {
6326 cpu1_alert0: 5103 cpu1_alert0: trip-point0 {
6327 tempe 5104 temperature = <90000>;
6328 hyste 5105 hysteresis = <2000>;
6329 type 5106 type = "passive";
6330 }; 5107 };
6331 5108
6332 cpu1_alert1: 5109 cpu1_alert1: trip-point1 {
6333 tempe 5110 temperature = <95000>;
6334 hyste 5111 hysteresis = <2000>;
6335 type 5112 type = "passive";
6336 }; 5113 };
6337 5114
6338 cpu1_crit: cp !! 5115 cpu1_crit: cpu_crit {
6339 tempe 5116 temperature = <110000>;
6340 hyste 5117 hysteresis = <1000>;
6341 type 5118 type = "critical";
6342 }; 5119 };
6343 }; 5120 };
6344 5121
6345 cooling-maps { 5122 cooling-maps {
6346 map0 { 5123 map0 {
6347 trip 5124 trip = <&cpu1_alert0>;
6348 cooli 5125 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 5126 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 5127 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 5128 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 5129 };
6353 map1 { 5130 map1 {
6354 trip 5131 trip = <&cpu1_alert1>;
6355 cooli 5132 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 5133 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 5134 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 5135 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 5136 };
6360 }; 5137 };
6361 }; 5138 };
6362 5139
6363 cpu2-thermal { 5140 cpu2-thermal {
6364 polling-delay-passive 5141 polling-delay-passive = <250>;
>> 5142 polling-delay = <1000>;
6365 5143
6366 thermal-sensors = <&t 5144 thermal-sensors = <&tsens0 3>;
6367 5145
6368 trips { 5146 trips {
6369 cpu2_alert0: 5147 cpu2_alert0: trip-point0 {
6370 tempe 5148 temperature = <90000>;
6371 hyste 5149 hysteresis = <2000>;
6372 type 5150 type = "passive";
6373 }; 5151 };
6374 5152
6375 cpu2_alert1: 5153 cpu2_alert1: trip-point1 {
6376 tempe 5154 temperature = <95000>;
6377 hyste 5155 hysteresis = <2000>;
6378 type 5156 type = "passive";
6379 }; 5157 };
6380 5158
6381 cpu2_crit: cp !! 5159 cpu2_crit: cpu_crit {
6382 tempe 5160 temperature = <110000>;
6383 hyste 5161 hysteresis = <1000>;
6384 type 5162 type = "critical";
6385 }; 5163 };
6386 }; 5164 };
6387 5165
6388 cooling-maps { 5166 cooling-maps {
6389 map0 { 5167 map0 {
6390 trip 5168 trip = <&cpu2_alert0>;
6391 cooli 5169 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 5170 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 5171 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 5172 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 5173 };
6396 map1 { 5174 map1 {
6397 trip 5175 trip = <&cpu2_alert1>;
6398 cooli 5176 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 5177 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 5178 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 5179 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 5180 };
6403 }; 5181 };
6404 }; 5182 };
6405 5183
6406 cpu3-thermal { 5184 cpu3-thermal {
6407 polling-delay-passive 5185 polling-delay-passive = <250>;
>> 5186 polling-delay = <1000>;
6408 5187
6409 thermal-sensors = <&t 5188 thermal-sensors = <&tsens0 4>;
6410 5189
6411 trips { 5190 trips {
6412 cpu3_alert0: 5191 cpu3_alert0: trip-point0 {
6413 tempe 5192 temperature = <90000>;
6414 hyste 5193 hysteresis = <2000>;
6415 type 5194 type = "passive";
6416 }; 5195 };
6417 5196
6418 cpu3_alert1: 5197 cpu3_alert1: trip-point1 {
6419 tempe 5198 temperature = <95000>;
6420 hyste 5199 hysteresis = <2000>;
6421 type 5200 type = "passive";
6422 }; 5201 };
6423 5202
6424 cpu3_crit: cp !! 5203 cpu3_crit: cpu_crit {
6425 tempe 5204 temperature = <110000>;
6426 hyste 5205 hysteresis = <1000>;
6427 type 5206 type = "critical";
6428 }; 5207 };
6429 }; 5208 };
6430 5209
6431 cooling-maps { 5210 cooling-maps {
6432 map0 { 5211 map0 {
6433 trip 5212 trip = <&cpu3_alert0>;
6434 cooli 5213 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 5214 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 5215 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 5216 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 5217 };
6439 map1 { 5218 map1 {
6440 trip 5219 trip = <&cpu3_alert1>;
6441 cooli 5220 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 5221 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 5222 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 5223 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 5224 };
6446 }; 5225 };
6447 }; 5226 };
6448 5227
6449 cpu4-top-thermal { 5228 cpu4-top-thermal {
6450 polling-delay-passive 5229 polling-delay-passive = <250>;
>> 5230 polling-delay = <1000>;
6451 5231
6452 thermal-sensors = <&t 5232 thermal-sensors = <&tsens0 7>;
6453 5233
6454 trips { 5234 trips {
6455 cpu4_top_aler 5235 cpu4_top_alert0: trip-point0 {
6456 tempe 5236 temperature = <90000>;
6457 hyste 5237 hysteresis = <2000>;
6458 type 5238 type = "passive";
6459 }; 5239 };
6460 5240
6461 cpu4_top_aler 5241 cpu4_top_alert1: trip-point1 {
6462 tempe 5242 temperature = <95000>;
6463 hyste 5243 hysteresis = <2000>;
6464 type 5244 type = "passive";
6465 }; 5245 };
6466 5246
6467 cpu4_top_crit !! 5247 cpu4_top_crit: cpu_crit {
6468 tempe 5248 temperature = <110000>;
6469 hyste 5249 hysteresis = <1000>;
6470 type 5250 type = "critical";
6471 }; 5251 };
6472 }; 5252 };
6473 5253
6474 cooling-maps { 5254 cooling-maps {
6475 map0 { 5255 map0 {
6476 trip 5256 trip = <&cpu4_top_alert0>;
6477 cooli 5257 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 5258 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 5259 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 5260 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 5261 };
6482 map1 { 5262 map1 {
6483 trip 5263 trip = <&cpu4_top_alert1>;
6484 cooli 5264 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 5265 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 5266 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 5267 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 5268 };
6489 }; 5269 };
6490 }; 5270 };
6491 5271
6492 cpu5-top-thermal { 5272 cpu5-top-thermal {
6493 polling-delay-passive 5273 polling-delay-passive = <250>;
>> 5274 polling-delay = <1000>;
6494 5275
6495 thermal-sensors = <&t 5276 thermal-sensors = <&tsens0 8>;
6496 5277
6497 trips { 5278 trips {
6498 cpu5_top_aler 5279 cpu5_top_alert0: trip-point0 {
6499 tempe 5280 temperature = <90000>;
6500 hyste 5281 hysteresis = <2000>;
6501 type 5282 type = "passive";
6502 }; 5283 };
6503 5284
6504 cpu5_top_aler 5285 cpu5_top_alert1: trip-point1 {
6505 tempe 5286 temperature = <95000>;
6506 hyste 5287 hysteresis = <2000>;
6507 type 5288 type = "passive";
6508 }; 5289 };
6509 5290
6510 cpu5_top_crit !! 5291 cpu5_top_crit: cpu_crit {
6511 tempe 5292 temperature = <110000>;
6512 hyste 5293 hysteresis = <1000>;
6513 type 5294 type = "critical";
6514 }; 5295 };
6515 }; 5296 };
6516 5297
6517 cooling-maps { 5298 cooling-maps {
6518 map0 { 5299 map0 {
6519 trip 5300 trip = <&cpu5_top_alert0>;
6520 cooli 5301 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 5302 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 5303 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 5304 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 5305 };
6525 map1 { 5306 map1 {
6526 trip 5307 trip = <&cpu5_top_alert1>;
6527 cooli 5308 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 5309 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 5310 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 5311 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 5312 };
6532 }; 5313 };
6533 }; 5314 };
6534 5315
6535 cpu6-top-thermal { 5316 cpu6-top-thermal {
6536 polling-delay-passive 5317 polling-delay-passive = <250>;
>> 5318 polling-delay = <1000>;
6537 5319
6538 thermal-sensors = <&t 5320 thermal-sensors = <&tsens0 9>;
6539 5321
6540 trips { 5322 trips {
6541 cpu6_top_aler 5323 cpu6_top_alert0: trip-point0 {
6542 tempe 5324 temperature = <90000>;
6543 hyste 5325 hysteresis = <2000>;
6544 type 5326 type = "passive";
6545 }; 5327 };
6546 5328
6547 cpu6_top_aler 5329 cpu6_top_alert1: trip-point1 {
6548 tempe 5330 temperature = <95000>;
6549 hyste 5331 hysteresis = <2000>;
6550 type 5332 type = "passive";
6551 }; 5333 };
6552 5334
6553 cpu6_top_crit !! 5335 cpu6_top_crit: cpu_crit {
6554 tempe 5336 temperature = <110000>;
6555 hyste 5337 hysteresis = <1000>;
6556 type 5338 type = "critical";
6557 }; 5339 };
6558 }; 5340 };
6559 5341
6560 cooling-maps { 5342 cooling-maps {
6561 map0 { 5343 map0 {
6562 trip 5344 trip = <&cpu6_top_alert0>;
6563 cooli 5345 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 5346 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 5347 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 5348 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 5349 };
6568 map1 { 5350 map1 {
6569 trip 5351 trip = <&cpu6_top_alert1>;
6570 cooli 5352 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 5353 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 5354 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 5355 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 5356 };
6575 }; 5357 };
6576 }; 5358 };
6577 5359
6578 cpu7-top-thermal { 5360 cpu7-top-thermal {
6579 polling-delay-passive 5361 polling-delay-passive = <250>;
>> 5362 polling-delay = <1000>;
6580 5363
6581 thermal-sensors = <&t 5364 thermal-sensors = <&tsens0 10>;
6582 5365
6583 trips { 5366 trips {
6584 cpu7_top_aler 5367 cpu7_top_alert0: trip-point0 {
6585 tempe 5368 temperature = <90000>;
6586 hyste 5369 hysteresis = <2000>;
6587 type 5370 type = "passive";
6588 }; 5371 };
6589 5372
6590 cpu7_top_aler 5373 cpu7_top_alert1: trip-point1 {
6591 tempe 5374 temperature = <95000>;
6592 hyste 5375 hysteresis = <2000>;
6593 type 5376 type = "passive";
6594 }; 5377 };
6595 5378
6596 cpu7_top_crit !! 5379 cpu7_top_crit: cpu_crit {
6597 tempe 5380 temperature = <110000>;
6598 hyste 5381 hysteresis = <1000>;
6599 type 5382 type = "critical";
6600 }; 5383 };
6601 }; 5384 };
6602 5385
6603 cooling-maps { 5386 cooling-maps {
6604 map0 { 5387 map0 {
6605 trip 5388 trip = <&cpu7_top_alert0>;
6606 cooli 5389 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 5390 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 5391 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 5392 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 5393 };
6611 map1 { 5394 map1 {
6612 trip 5395 trip = <&cpu7_top_alert1>;
6613 cooli 5396 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 5397 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 5398 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 5399 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 5400 };
6618 }; 5401 };
6619 }; 5402 };
6620 5403
6621 cpu4-bottom-thermal { 5404 cpu4-bottom-thermal {
6622 polling-delay-passive 5405 polling-delay-passive = <250>;
>> 5406 polling-delay = <1000>;
6623 5407
6624 thermal-sensors = <&t 5408 thermal-sensors = <&tsens0 11>;
6625 5409
6626 trips { 5410 trips {
6627 cpu4_bottom_a 5411 cpu4_bottom_alert0: trip-point0 {
6628 tempe 5412 temperature = <90000>;
6629 hyste 5413 hysteresis = <2000>;
6630 type 5414 type = "passive";
6631 }; 5415 };
6632 5416
6633 cpu4_bottom_a 5417 cpu4_bottom_alert1: trip-point1 {
6634 tempe 5418 temperature = <95000>;
6635 hyste 5419 hysteresis = <2000>;
6636 type 5420 type = "passive";
6637 }; 5421 };
6638 5422
6639 cpu4_bottom_c !! 5423 cpu4_bottom_crit: cpu_crit {
6640 tempe 5424 temperature = <110000>;
6641 hyste 5425 hysteresis = <1000>;
6642 type 5426 type = "critical";
6643 }; 5427 };
6644 }; 5428 };
6645 5429
6646 cooling-maps { 5430 cooling-maps {
6647 map0 { 5431 map0 {
6648 trip 5432 trip = <&cpu4_bottom_alert0>;
6649 cooli 5433 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 5434 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 5435 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 5436 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 5437 };
6654 map1 { 5438 map1 {
6655 trip 5439 trip = <&cpu4_bottom_alert1>;
6656 cooli 5440 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 5441 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 5442 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 5443 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 5444 };
6661 }; 5445 };
6662 }; 5446 };
6663 5447
6664 cpu5-bottom-thermal { 5448 cpu5-bottom-thermal {
6665 polling-delay-passive 5449 polling-delay-passive = <250>;
>> 5450 polling-delay = <1000>;
6666 5451
6667 thermal-sensors = <&t 5452 thermal-sensors = <&tsens0 12>;
6668 5453
6669 trips { 5454 trips {
6670 cpu5_bottom_a 5455 cpu5_bottom_alert0: trip-point0 {
6671 tempe 5456 temperature = <90000>;
6672 hyste 5457 hysteresis = <2000>;
6673 type 5458 type = "passive";
6674 }; 5459 };
6675 5460
6676 cpu5_bottom_a 5461 cpu5_bottom_alert1: trip-point1 {
6677 tempe 5462 temperature = <95000>;
6678 hyste 5463 hysteresis = <2000>;
6679 type 5464 type = "passive";
6680 }; 5465 };
6681 5466
6682 cpu5_bottom_c !! 5467 cpu5_bottom_crit: cpu_crit {
6683 tempe 5468 temperature = <110000>;
6684 hyste 5469 hysteresis = <1000>;
6685 type 5470 type = "critical";
6686 }; 5471 };
6687 }; 5472 };
6688 5473
6689 cooling-maps { 5474 cooling-maps {
6690 map0 { 5475 map0 {
6691 trip 5476 trip = <&cpu5_bottom_alert0>;
6692 cooli 5477 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 5478 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 5479 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 5480 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 5481 };
6697 map1 { 5482 map1 {
6698 trip 5483 trip = <&cpu5_bottom_alert1>;
6699 cooli 5484 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 5485 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 5486 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 5487 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 5488 };
6704 }; 5489 };
6705 }; 5490 };
6706 5491
6707 cpu6-bottom-thermal { 5492 cpu6-bottom-thermal {
6708 polling-delay-passive 5493 polling-delay-passive = <250>;
>> 5494 polling-delay = <1000>;
6709 5495
6710 thermal-sensors = <&t 5496 thermal-sensors = <&tsens0 13>;
6711 5497
6712 trips { 5498 trips {
6713 cpu6_bottom_a 5499 cpu6_bottom_alert0: trip-point0 {
6714 tempe 5500 temperature = <90000>;
6715 hyste 5501 hysteresis = <2000>;
6716 type 5502 type = "passive";
6717 }; 5503 };
6718 5504
6719 cpu6_bottom_a 5505 cpu6_bottom_alert1: trip-point1 {
6720 tempe 5506 temperature = <95000>;
6721 hyste 5507 hysteresis = <2000>;
6722 type 5508 type = "passive";
6723 }; 5509 };
6724 5510
6725 cpu6_bottom_c !! 5511 cpu6_bottom_crit: cpu_crit {
6726 tempe 5512 temperature = <110000>;
6727 hyste 5513 hysteresis = <1000>;
6728 type 5514 type = "critical";
6729 }; 5515 };
6730 }; 5516 };
6731 5517
6732 cooling-maps { 5518 cooling-maps {
6733 map0 { 5519 map0 {
6734 trip 5520 trip = <&cpu6_bottom_alert0>;
6735 cooli 5521 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 5522 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 5523 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 5524 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 5525 };
6740 map1 { 5526 map1 {
6741 trip 5527 trip = <&cpu6_bottom_alert1>;
6742 cooli 5528 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 5529 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 5530 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 5531 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 5532 };
6747 }; 5533 };
6748 }; 5534 };
6749 5535
6750 cpu7-bottom-thermal { 5536 cpu7-bottom-thermal {
6751 polling-delay-passive 5537 polling-delay-passive = <250>;
>> 5538 polling-delay = <1000>;
6752 5539
6753 thermal-sensors = <&t 5540 thermal-sensors = <&tsens0 14>;
6754 5541
6755 trips { 5542 trips {
6756 cpu7_bottom_a 5543 cpu7_bottom_alert0: trip-point0 {
6757 tempe 5544 temperature = <90000>;
6758 hyste 5545 hysteresis = <2000>;
6759 type 5546 type = "passive";
6760 }; 5547 };
6761 5548
6762 cpu7_bottom_a 5549 cpu7_bottom_alert1: trip-point1 {
6763 tempe 5550 temperature = <95000>;
6764 hyste 5551 hysteresis = <2000>;
6765 type 5552 type = "passive";
6766 }; 5553 };
6767 5554
6768 cpu7_bottom_c !! 5555 cpu7_bottom_crit: cpu_crit {
6769 tempe 5556 temperature = <110000>;
6770 hyste 5557 hysteresis = <1000>;
6771 type 5558 type = "critical";
6772 }; 5559 };
6773 }; 5560 };
6774 5561
6775 cooling-maps { 5562 cooling-maps {
6776 map0 { 5563 map0 {
6777 trip 5564 trip = <&cpu7_bottom_alert0>;
6778 cooli 5565 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 5566 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 5567 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 5568 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 5569 };
6783 map1 { 5570 map1 {
6784 trip 5571 trip = <&cpu7_bottom_alert1>;
6785 cooli 5572 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 5573 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 5574 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 5575 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 5576 };
6790 }; 5577 };
6791 }; 5578 };
6792 5579
6793 aoss0-thermal { 5580 aoss0-thermal {
6794 polling-delay-passive 5581 polling-delay-passive = <250>;
>> 5582 polling-delay = <1000>;
6795 5583
6796 thermal-sensors = <&t 5584 thermal-sensors = <&tsens0 0>;
6797 5585
6798 trips { 5586 trips {
6799 aoss0_alert0: 5587 aoss0_alert0: trip-point0 {
6800 tempe 5588 temperature = <90000>;
6801 hyste 5589 hysteresis = <2000>;
6802 type 5590 type = "hot";
6803 }; 5591 };
6804 }; 5592 };
6805 }; 5593 };
6806 5594
6807 cluster0-thermal { 5595 cluster0-thermal {
6808 polling-delay-passive 5596 polling-delay-passive = <250>;
>> 5597 polling-delay = <1000>;
6809 5598
6810 thermal-sensors = <&t 5599 thermal-sensors = <&tsens0 5>;
6811 5600
6812 trips { 5601 trips {
6813 cluster0_aler 5602 cluster0_alert0: trip-point0 {
6814 tempe 5603 temperature = <90000>;
6815 hyste 5604 hysteresis = <2000>;
6816 type 5605 type = "hot";
6817 }; 5606 };
6818 cluster0_crit !! 5607 cluster0_crit: cluster0_crit {
6819 tempe 5608 temperature = <110000>;
6820 hyste 5609 hysteresis = <2000>;
6821 type 5610 type = "critical";
6822 }; 5611 };
6823 }; 5612 };
6824 }; 5613 };
6825 5614
6826 cluster1-thermal { 5615 cluster1-thermal {
6827 polling-delay-passive 5616 polling-delay-passive = <250>;
>> 5617 polling-delay = <1000>;
6828 5618
6829 thermal-sensors = <&t 5619 thermal-sensors = <&tsens0 6>;
6830 5620
6831 trips { 5621 trips {
6832 cluster1_aler 5622 cluster1_alert0: trip-point0 {
6833 tempe 5623 temperature = <90000>;
6834 hyste 5624 hysteresis = <2000>;
6835 type 5625 type = "hot";
6836 }; 5626 };
6837 cluster1_crit !! 5627 cluster1_crit: cluster1_crit {
6838 tempe 5628 temperature = <110000>;
6839 hyste 5629 hysteresis = <2000>;
6840 type 5630 type = "critical";
6841 }; 5631 };
6842 }; 5632 };
6843 }; 5633 };
6844 5634
6845 gpu-top-thermal { 5635 gpu-top-thermal {
6846 polling-delay-passive 5636 polling-delay-passive = <250>;
>> 5637 polling-delay = <1000>;
6847 5638
6848 thermal-sensors = <&t 5639 thermal-sensors = <&tsens0 15>;
6849 5640
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 5641 trips {
6858 gpu_top_alert !! 5642 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 5643 temperature = <90000>;
6866 hyste !! 5644 hysteresis = <2000>;
6867 type 5645 type = "hot";
6868 }; 5646 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 5647 };
6876 }; 5648 };
6877 5649
6878 aoss1-thermal { 5650 aoss1-thermal {
6879 polling-delay-passive 5651 polling-delay-passive = <250>;
>> 5652 polling-delay = <1000>;
6880 5653
6881 thermal-sensors = <&t 5654 thermal-sensors = <&tsens1 0>;
6882 5655
6883 trips { 5656 trips {
6884 aoss1_alert0: 5657 aoss1_alert0: trip-point0 {
6885 tempe 5658 temperature = <90000>;
6886 hyste 5659 hysteresis = <2000>;
6887 type 5660 type = "hot";
6888 }; 5661 };
6889 }; 5662 };
6890 }; 5663 };
6891 5664
6892 wlan-thermal { 5665 wlan-thermal {
6893 polling-delay-passive 5666 polling-delay-passive = <250>;
>> 5667 polling-delay = <1000>;
6894 5668
6895 thermal-sensors = <&t 5669 thermal-sensors = <&tsens1 1>;
6896 5670
6897 trips { 5671 trips {
6898 wlan_alert0: 5672 wlan_alert0: trip-point0 {
6899 tempe 5673 temperature = <90000>;
6900 hyste 5674 hysteresis = <2000>;
6901 type 5675 type = "hot";
6902 }; 5676 };
6903 }; 5677 };
6904 }; 5678 };
6905 5679
6906 video-thermal { 5680 video-thermal {
6907 polling-delay-passive 5681 polling-delay-passive = <250>;
>> 5682 polling-delay = <1000>;
6908 5683
6909 thermal-sensors = <&t 5684 thermal-sensors = <&tsens1 2>;
6910 5685
6911 trips { 5686 trips {
6912 video_alert0: 5687 video_alert0: trip-point0 {
6913 tempe 5688 temperature = <90000>;
6914 hyste 5689 hysteresis = <2000>;
6915 type 5690 type = "hot";
6916 }; 5691 };
6917 }; 5692 };
6918 }; 5693 };
6919 5694
6920 mem-thermal { 5695 mem-thermal {
6921 polling-delay-passive 5696 polling-delay-passive = <250>;
>> 5697 polling-delay = <1000>;
6922 5698
6923 thermal-sensors = <&t 5699 thermal-sensors = <&tsens1 3>;
6924 5700
6925 trips { 5701 trips {
6926 mem_alert0: t 5702 mem_alert0: trip-point0 {
6927 tempe 5703 temperature = <90000>;
6928 hyste 5704 hysteresis = <2000>;
6929 type 5705 type = "hot";
6930 }; 5706 };
6931 }; 5707 };
6932 }; 5708 };
6933 5709
6934 q6-hvx-thermal { 5710 q6-hvx-thermal {
6935 polling-delay-passive 5711 polling-delay-passive = <250>;
>> 5712 polling-delay = <1000>;
6936 5713
6937 thermal-sensors = <&t 5714 thermal-sensors = <&tsens1 4>;
6938 5715
6939 trips { 5716 trips {
6940 q6_hvx_alert0 5717 q6_hvx_alert0: trip-point0 {
6941 tempe 5718 temperature = <90000>;
6942 hyste 5719 hysteresis = <2000>;
6943 type 5720 type = "hot";
6944 }; 5721 };
6945 }; 5722 };
6946 }; 5723 };
6947 5724
6948 camera-thermal { 5725 camera-thermal {
6949 polling-delay-passive 5726 polling-delay-passive = <250>;
>> 5727 polling-delay = <1000>;
6950 5728
6951 thermal-sensors = <&t 5729 thermal-sensors = <&tsens1 5>;
6952 5730
6953 trips { 5731 trips {
6954 camera_alert0 5732 camera_alert0: trip-point0 {
6955 tempe 5733 temperature = <90000>;
6956 hyste 5734 hysteresis = <2000>;
6957 type 5735 type = "hot";
6958 }; 5736 };
6959 }; 5737 };
6960 }; 5738 };
6961 5739
6962 compute-thermal { 5740 compute-thermal {
6963 polling-delay-passive 5741 polling-delay-passive = <250>;
>> 5742 polling-delay = <1000>;
6964 5743
6965 thermal-sensors = <&t 5744 thermal-sensors = <&tsens1 6>;
6966 5745
6967 trips { 5746 trips {
6968 compute_alert 5747 compute_alert0: trip-point0 {
6969 tempe 5748 temperature = <90000>;
6970 hyste 5749 hysteresis = <2000>;
6971 type 5750 type = "hot";
6972 }; 5751 };
6973 }; 5752 };
6974 }; 5753 };
6975 5754
6976 npu-thermal { 5755 npu-thermal {
6977 polling-delay-passive 5756 polling-delay-passive = <250>;
>> 5757 polling-delay = <1000>;
6978 5758
6979 thermal-sensors = <&t 5759 thermal-sensors = <&tsens1 7>;
6980 5760
6981 trips { 5761 trips {
6982 npu_alert0: t 5762 npu_alert0: trip-point0 {
6983 tempe 5763 temperature = <90000>;
6984 hyste 5764 hysteresis = <2000>;
6985 type 5765 type = "hot";
6986 }; 5766 };
6987 }; 5767 };
6988 }; 5768 };
6989 5769
6990 gpu-bottom-thermal { 5770 gpu-bottom-thermal {
6991 polling-delay-passive 5771 polling-delay-passive = <250>;
>> 5772 polling-delay = <1000>;
6992 5773
6993 thermal-sensors = <&t 5774 thermal-sensors = <&tsens1 8>;
6994 5775
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 5776 trips {
7003 gpu_bottom_al !! 5777 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 5778 temperature = <90000>;
7011 hyste !! 5779 hysteresis = <2000>;
7012 type 5780 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 5781 };
7020 }; 5782 };
7021 }; 5783 };
7022 }; 5784 };
7023 }; 5785 };
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