1 // SPDX-License-Identifier: BSD-3-Clause 1 // SPDX-License-Identifier: BSD-3-Clause
2 /* 2 /*
3 * Copyright (c) 2020, The Linux Foundation. A 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250 7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h> 8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250. 9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h> 10 #include <dt-bindings/clock/qcom,rpmh.h>
>> 11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
>> 12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
11 #include <dt-bindings/dma/qcom-gpi.h> 13 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3 15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sm8250 16 #include <dt-bindings/interconnect/qcom,sm8250.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h> 17 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h> <<
17 #include <dt-bindings/power/qcom-rpmpd.h> 18 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h> <<
19 #include <dt-bindings/soc/qcom,apr.h> 19 #include <dt-bindings/soc/qcom,apr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6afe.h> 21 #include <dt-bindings/sound/qcom,q6afe.h>
22 #include <dt-bindings/thermal/thermal.h> 22 #include <dt-bindings/thermal/thermal.h>
23 #include <dt-bindings/clock/qcom,camcc-sm8250. 23 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
24 #include <dt-bindings/clock/qcom,videocc-sm825 24 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
25 25
26 / { 26 / {
27 interrupt-parent = <&intc>; 27 interrupt-parent = <&intc>;
28 28
29 #address-cells = <2>; 29 #address-cells = <2>;
30 #size-cells = <2>; 30 #size-cells = <2>;
31 31
32 aliases { 32 aliases {
33 i2c0 = &i2c0; 33 i2c0 = &i2c0;
34 i2c1 = &i2c1; 34 i2c1 = &i2c1;
35 i2c2 = &i2c2; 35 i2c2 = &i2c2;
36 i2c3 = &i2c3; 36 i2c3 = &i2c3;
37 i2c4 = &i2c4; 37 i2c4 = &i2c4;
38 i2c5 = &i2c5; 38 i2c5 = &i2c5;
39 i2c6 = &i2c6; 39 i2c6 = &i2c6;
40 i2c7 = &i2c7; 40 i2c7 = &i2c7;
41 i2c8 = &i2c8; 41 i2c8 = &i2c8;
42 i2c9 = &i2c9; 42 i2c9 = &i2c9;
43 i2c10 = &i2c10; 43 i2c10 = &i2c10;
44 i2c11 = &i2c11; 44 i2c11 = &i2c11;
45 i2c12 = &i2c12; 45 i2c12 = &i2c12;
46 i2c13 = &i2c13; 46 i2c13 = &i2c13;
47 i2c14 = &i2c14; 47 i2c14 = &i2c14;
48 i2c15 = &i2c15; 48 i2c15 = &i2c15;
49 i2c16 = &i2c16; 49 i2c16 = &i2c16;
50 i2c17 = &i2c17; 50 i2c17 = &i2c17;
51 i2c18 = &i2c18; 51 i2c18 = &i2c18;
52 i2c19 = &i2c19; 52 i2c19 = &i2c19;
53 spi0 = &spi0; 53 spi0 = &spi0;
54 spi1 = &spi1; 54 spi1 = &spi1;
55 spi2 = &spi2; 55 spi2 = &spi2;
56 spi3 = &spi3; 56 spi3 = &spi3;
57 spi4 = &spi4; 57 spi4 = &spi4;
58 spi5 = &spi5; 58 spi5 = &spi5;
59 spi6 = &spi6; 59 spi6 = &spi6;
60 spi7 = &spi7; 60 spi7 = &spi7;
61 spi8 = &spi8; 61 spi8 = &spi8;
62 spi9 = &spi9; 62 spi9 = &spi9;
63 spi10 = &spi10; 63 spi10 = &spi10;
64 spi11 = &spi11; 64 spi11 = &spi11;
65 spi12 = &spi12; 65 spi12 = &spi12;
66 spi13 = &spi13; 66 spi13 = &spi13;
67 spi14 = &spi14; 67 spi14 = &spi14;
68 spi15 = &spi15; 68 spi15 = &spi15;
69 spi16 = &spi16; 69 spi16 = &spi16;
70 spi17 = &spi17; 70 spi17 = &spi17;
71 spi18 = &spi18; 71 spi18 = &spi18;
72 spi19 = &spi19; 72 spi19 = &spi19;
73 }; 73 };
74 74
75 chosen { }; 75 chosen { };
76 76
77 clocks { 77 clocks {
78 xo_board: xo-board { 78 xo_board: xo-board {
79 compatible = "fixed-cl 79 compatible = "fixed-clock";
80 #clock-cells = <0>; 80 #clock-cells = <0>;
81 clock-frequency = <384 81 clock-frequency = <38400000>;
82 clock-output-names = " 82 clock-output-names = "xo_board";
83 }; 83 };
84 84
85 sleep_clk: sleep-clk { 85 sleep_clk: sleep-clk {
86 compatible = "fixed-cl 86 compatible = "fixed-clock";
87 clock-frequency = <327 87 clock-frequency = <32768>;
88 #clock-cells = <0>; 88 #clock-cells = <0>;
89 }; 89 };
90 }; 90 };
91 91
92 cpus { 92 cpus {
93 #address-cells = <2>; 93 #address-cells = <2>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 CPU0: cpu@0 { 96 CPU0: cpu@0 {
97 device_type = "cpu"; 97 device_type = "cpu";
98 compatible = "qcom,kry 98 compatible = "qcom,kryo485";
99 reg = <0x0 0x0>; 99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw <<
101 enable-method = "psci" 100 enable-method = "psci";
102 capacity-dmips-mhz = < 101 capacity-dmips-mhz = <448>;
103 dynamic-power-coeffici !! 102 dynamic-power-coefficient = <205>;
104 next-level-cache = <&L 103 next-level-cache = <&L2_0>;
105 power-domains = <&CPU_ 104 power-domains = <&CPU_PD0>;
106 power-domain-names = " 105 power-domain-names = "psci";
107 qcom,freq-domain = <&c 106 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = 107 operating-points-v2 = <&cpu0_opp_table>;
109 interconnects = <&gem_ !! 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
110 <&epss 109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
111 #cooling-cells = <2>; 110 #cooling-cells = <2>;
112 L2_0: l2-cache { 111 L2_0: l2-cache {
113 compatible = " 112 compatible = "cache";
114 cache-level = <<
115 cache-size = < <<
116 cache-unified; <<
117 next-level-cac 113 next-level-cache = <&L3_0>;
118 L3_0: l3-cache 114 L3_0: l3-cache {
119 compat 115 compatible = "cache";
120 cache- <<
121 cache- <<
122 cache- <<
123 }; 116 };
124 }; 117 };
125 }; 118 };
126 119
127 CPU1: cpu@100 { 120 CPU1: cpu@100 {
128 device_type = "cpu"; 121 device_type = "cpu";
129 compatible = "qcom,kry 122 compatible = "qcom,kryo485";
130 reg = <0x0 0x100>; 123 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw <<
132 enable-method = "psci" 124 enable-method = "psci";
133 capacity-dmips-mhz = < 125 capacity-dmips-mhz = <448>;
134 dynamic-power-coeffici !! 126 dynamic-power-coefficient = <205>;
135 next-level-cache = <&L 127 next-level-cache = <&L2_100>;
136 power-domains = <&CPU_ 128 power-domains = <&CPU_PD1>;
137 power-domain-names = " 129 power-domain-names = "psci";
138 qcom,freq-domain = <&c 130 qcom,freq-domain = <&cpufreq_hw 0>;
139 operating-points-v2 = 131 operating-points-v2 = <&cpu0_opp_table>;
140 interconnects = <&gem_ !! 132 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
141 <&epss 133 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
142 #cooling-cells = <2>; 134 #cooling-cells = <2>;
143 L2_100: l2-cache { 135 L2_100: l2-cache {
144 compatible = " 136 compatible = "cache";
145 cache-level = <<
146 cache-size = < <<
147 cache-unified; <<
148 next-level-cac 137 next-level-cache = <&L3_0>;
149 }; 138 };
150 }; 139 };
151 140
152 CPU2: cpu@200 { 141 CPU2: cpu@200 {
153 device_type = "cpu"; 142 device_type = "cpu";
154 compatible = "qcom,kry 143 compatible = "qcom,kryo485";
155 reg = <0x0 0x200>; 144 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw <<
157 enable-method = "psci" 145 enable-method = "psci";
158 capacity-dmips-mhz = < 146 capacity-dmips-mhz = <448>;
159 dynamic-power-coeffici !! 147 dynamic-power-coefficient = <205>;
160 next-level-cache = <&L 148 next-level-cache = <&L2_200>;
161 power-domains = <&CPU_ 149 power-domains = <&CPU_PD2>;
162 power-domain-names = " 150 power-domain-names = "psci";
163 qcom,freq-domain = <&c 151 qcom,freq-domain = <&cpufreq_hw 0>;
164 operating-points-v2 = 152 operating-points-v2 = <&cpu0_opp_table>;
165 interconnects = <&gem_ !! 153 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
166 <&epss 154 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
167 #cooling-cells = <2>; 155 #cooling-cells = <2>;
168 L2_200: l2-cache { 156 L2_200: l2-cache {
169 compatible = " 157 compatible = "cache";
170 cache-level = <<
171 cache-size = < <<
172 cache-unified; <<
173 next-level-cac 158 next-level-cache = <&L3_0>;
174 }; 159 };
175 }; 160 };
176 161
177 CPU3: cpu@300 { 162 CPU3: cpu@300 {
178 device_type = "cpu"; 163 device_type = "cpu";
179 compatible = "qcom,kry 164 compatible = "qcom,kryo485";
180 reg = <0x0 0x300>; 165 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw <<
182 enable-method = "psci" 166 enable-method = "psci";
183 capacity-dmips-mhz = < 167 capacity-dmips-mhz = <448>;
184 dynamic-power-coeffici !! 168 dynamic-power-coefficient = <205>;
185 next-level-cache = <&L 169 next-level-cache = <&L2_300>;
186 power-domains = <&CPU_ 170 power-domains = <&CPU_PD3>;
187 power-domain-names = " 171 power-domain-names = "psci";
188 qcom,freq-domain = <&c 172 qcom,freq-domain = <&cpufreq_hw 0>;
189 operating-points-v2 = 173 operating-points-v2 = <&cpu0_opp_table>;
190 interconnects = <&gem_ !! 174 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
191 <&epss 175 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
192 #cooling-cells = <2>; 176 #cooling-cells = <2>;
193 L2_300: l2-cache { 177 L2_300: l2-cache {
194 compatible = " 178 compatible = "cache";
195 cache-level = <<
196 cache-size = < <<
197 cache-unified; <<
198 next-level-cac 179 next-level-cache = <&L3_0>;
199 }; 180 };
200 }; 181 };
201 182
202 CPU4: cpu@400 { 183 CPU4: cpu@400 {
203 device_type = "cpu"; 184 device_type = "cpu";
204 compatible = "qcom,kry 185 compatible = "qcom,kryo485";
205 reg = <0x0 0x400>; 186 reg = <0x0 0x400>;
206 clocks = <&cpufreq_hw <<
207 enable-method = "psci" 187 enable-method = "psci";
208 capacity-dmips-mhz = < 188 capacity-dmips-mhz = <1024>;
209 dynamic-power-coeffici 189 dynamic-power-coefficient = <379>;
210 next-level-cache = <&L 190 next-level-cache = <&L2_400>;
211 power-domains = <&CPU_ 191 power-domains = <&CPU_PD4>;
212 power-domain-names = " 192 power-domain-names = "psci";
213 qcom,freq-domain = <&c 193 qcom,freq-domain = <&cpufreq_hw 1>;
214 operating-points-v2 = 194 operating-points-v2 = <&cpu4_opp_table>;
215 interconnects = <&gem_ !! 195 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
216 <&epss 196 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
217 #cooling-cells = <2>; 197 #cooling-cells = <2>;
218 L2_400: l2-cache { 198 L2_400: l2-cache {
219 compatible = " 199 compatible = "cache";
220 cache-level = <<
221 cache-size = < <<
222 cache-unified; <<
223 next-level-cac 200 next-level-cache = <&L3_0>;
224 }; 201 };
225 }; 202 };
226 203
227 CPU5: cpu@500 { 204 CPU5: cpu@500 {
228 device_type = "cpu"; 205 device_type = "cpu";
229 compatible = "qcom,kry 206 compatible = "qcom,kryo485";
230 reg = <0x0 0x500>; 207 reg = <0x0 0x500>;
231 clocks = <&cpufreq_hw <<
232 enable-method = "psci" 208 enable-method = "psci";
233 capacity-dmips-mhz = < 209 capacity-dmips-mhz = <1024>;
234 dynamic-power-coeffici 210 dynamic-power-coefficient = <379>;
235 next-level-cache = <&L 211 next-level-cache = <&L2_500>;
236 power-domains = <&CPU_ 212 power-domains = <&CPU_PD5>;
237 power-domain-names = " 213 power-domain-names = "psci";
238 qcom,freq-domain = <&c 214 qcom,freq-domain = <&cpufreq_hw 1>;
239 operating-points-v2 = 215 operating-points-v2 = <&cpu4_opp_table>;
240 interconnects = <&gem_ !! 216 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
241 <&epss 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
242 #cooling-cells = <2>; 218 #cooling-cells = <2>;
243 L2_500: l2-cache { 219 L2_500: l2-cache {
244 compatible = " 220 compatible = "cache";
245 cache-level = <<
246 cache-size = < <<
247 cache-unified; <<
248 next-level-cac 221 next-level-cache = <&L3_0>;
249 }; 222 };
>> 223
250 }; 224 };
251 225
252 CPU6: cpu@600 { 226 CPU6: cpu@600 {
253 device_type = "cpu"; 227 device_type = "cpu";
254 compatible = "qcom,kry 228 compatible = "qcom,kryo485";
255 reg = <0x0 0x600>; 229 reg = <0x0 0x600>;
256 clocks = <&cpufreq_hw <<
257 enable-method = "psci" 230 enable-method = "psci";
258 capacity-dmips-mhz = < 231 capacity-dmips-mhz = <1024>;
259 dynamic-power-coeffici 232 dynamic-power-coefficient = <379>;
260 next-level-cache = <&L 233 next-level-cache = <&L2_600>;
261 power-domains = <&CPU_ 234 power-domains = <&CPU_PD6>;
262 power-domain-names = " 235 power-domain-names = "psci";
263 qcom,freq-domain = <&c 236 qcom,freq-domain = <&cpufreq_hw 1>;
264 operating-points-v2 = 237 operating-points-v2 = <&cpu4_opp_table>;
265 interconnects = <&gem_ !! 238 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
266 <&epss 239 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
267 #cooling-cells = <2>; 240 #cooling-cells = <2>;
268 L2_600: l2-cache { 241 L2_600: l2-cache {
269 compatible = " 242 compatible = "cache";
270 cache-level = <<
271 cache-size = < <<
272 cache-unified; <<
273 next-level-cac 243 next-level-cache = <&L3_0>;
274 }; 244 };
275 }; 245 };
276 246
277 CPU7: cpu@700 { 247 CPU7: cpu@700 {
278 device_type = "cpu"; 248 device_type = "cpu";
279 compatible = "qcom,kry 249 compatible = "qcom,kryo485";
280 reg = <0x0 0x700>; 250 reg = <0x0 0x700>;
281 clocks = <&cpufreq_hw <<
282 enable-method = "psci" 251 enable-method = "psci";
283 capacity-dmips-mhz = < 252 capacity-dmips-mhz = <1024>;
284 dynamic-power-coeffici 253 dynamic-power-coefficient = <444>;
285 next-level-cache = <&L 254 next-level-cache = <&L2_700>;
286 power-domains = <&CPU_ 255 power-domains = <&CPU_PD7>;
287 power-domain-names = " 256 power-domain-names = "psci";
288 qcom,freq-domain = <&c 257 qcom,freq-domain = <&cpufreq_hw 2>;
289 operating-points-v2 = 258 operating-points-v2 = <&cpu7_opp_table>;
290 interconnects = <&gem_ !! 259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
291 <&epss 260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
292 #cooling-cells = <2>; 261 #cooling-cells = <2>;
293 L2_700: l2-cache { 262 L2_700: l2-cache {
294 compatible = " 263 compatible = "cache";
295 cache-level = <<
296 cache-size = < <<
297 cache-unified; <<
298 next-level-cac 264 next-level-cache = <&L3_0>;
299 }; 265 };
300 }; 266 };
301 267
302 cpu-map { 268 cpu-map {
303 cluster0 { 269 cluster0 {
304 core0 { 270 core0 {
305 cpu = 271 cpu = <&CPU0>;
306 }; 272 };
307 273
308 core1 { 274 core1 {
309 cpu = 275 cpu = <&CPU1>;
310 }; 276 };
311 277
312 core2 { 278 core2 {
313 cpu = 279 cpu = <&CPU2>;
314 }; 280 };
315 281
316 core3 { 282 core3 {
317 cpu = 283 cpu = <&CPU3>;
318 }; 284 };
319 285
320 core4 { 286 core4 {
321 cpu = 287 cpu = <&CPU4>;
322 }; 288 };
323 289
324 core5 { 290 core5 {
325 cpu = 291 cpu = <&CPU5>;
326 }; 292 };
327 293
328 core6 { 294 core6 {
329 cpu = 295 cpu = <&CPU6>;
330 }; 296 };
331 297
332 core7 { 298 core7 {
333 cpu = 299 cpu = <&CPU7>;
334 }; 300 };
335 }; 301 };
336 }; 302 };
337 303
338 idle-states { 304 idle-states {
339 entry-method = "psci"; 305 entry-method = "psci";
340 306
341 LITTLE_CPU_SLEEP_0: cp 307 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
342 compatible = " 308 compatible = "arm,idle-state";
343 idle-state-nam 309 idle-state-name = "silver-rail-power-collapse";
344 arm,psci-suspe 310 arm,psci-suspend-param = <0x40000004>;
345 entry-latency- 311 entry-latency-us = <360>;
346 exit-latency-u 312 exit-latency-us = <531>;
347 min-residency- 313 min-residency-us = <3934>;
348 local-timer-st 314 local-timer-stop;
349 }; 315 };
350 316
351 BIG_CPU_SLEEP_0: cpu-s 317 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
352 compatible = " 318 compatible = "arm,idle-state";
353 idle-state-nam 319 idle-state-name = "gold-rail-power-collapse";
354 arm,psci-suspe 320 arm,psci-suspend-param = <0x40000004>;
355 entry-latency- 321 entry-latency-us = <702>;
356 exit-latency-u 322 exit-latency-us = <1061>;
357 min-residency- 323 min-residency-us = <4488>;
358 local-timer-st 324 local-timer-stop;
359 }; 325 };
360 }; 326 };
361 327
362 domain-idle-states { 328 domain-idle-states {
363 CLUSTER_SLEEP_0: clust 329 CLUSTER_SLEEP_0: cluster-sleep-0 {
364 compatible = " 330 compatible = "domain-idle-state";
>> 331 idle-state-name = "cluster-llcc-off";
365 arm,psci-suspe 332 arm,psci-suspend-param = <0x4100c244>;
366 entry-latency- 333 entry-latency-us = <3264>;
367 exit-latency-u 334 exit-latency-us = <6562>;
368 min-residency- 335 min-residency-us = <9987>;
>> 336 local-timer-stop;
369 }; 337 };
370 }; 338 };
371 }; 339 };
372 340
373 qup_virt: interconnect-qup-virt { <<
374 compatible = "qcom,sm8250-qup- <<
375 #interconnect-cells = <2>; <<
376 qcom,bcm-voters = <&apps_bcm_v <<
377 }; <<
378 <<
379 cpu0_opp_table: opp-table-cpu0 { 341 cpu0_opp_table: opp-table-cpu0 {
380 compatible = "operating-points 342 compatible = "operating-points-v2";
381 opp-shared; 343 opp-shared;
382 344
383 cpu0_opp1: opp-300000000 { 345 cpu0_opp1: opp-300000000 {
384 opp-hz = /bits/ 64 <30 346 opp-hz = /bits/ 64 <300000000>;
385 opp-peak-kBps = <80000 347 opp-peak-kBps = <800000 9600000>;
386 }; 348 };
387 349
388 cpu0_opp2: opp-403200000 { 350 cpu0_opp2: opp-403200000 {
389 opp-hz = /bits/ 64 <40 351 opp-hz = /bits/ 64 <403200000>;
390 opp-peak-kBps = <80000 352 opp-peak-kBps = <800000 9600000>;
391 }; 353 };
392 354
393 cpu0_opp3: opp-518400000 { 355 cpu0_opp3: opp-518400000 {
394 opp-hz = /bits/ 64 <51 356 opp-hz = /bits/ 64 <518400000>;
395 opp-peak-kBps = <80000 357 opp-peak-kBps = <800000 16588800>;
396 }; 358 };
397 359
398 cpu0_opp4: opp-614400000 { 360 cpu0_opp4: opp-614400000 {
399 opp-hz = /bits/ 64 <61 361 opp-hz = /bits/ 64 <614400000>;
400 opp-peak-kBps = <80000 362 opp-peak-kBps = <800000 16588800>;
401 }; 363 };
402 364
403 cpu0_opp5: opp-691200000 { 365 cpu0_opp5: opp-691200000 {
404 opp-hz = /bits/ 64 <69 366 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <80000 367 opp-peak-kBps = <800000 19660800>;
406 }; 368 };
407 369
408 cpu0_opp6: opp-787200000 { 370 cpu0_opp6: opp-787200000 {
409 opp-hz = /bits/ 64 <78 371 opp-hz = /bits/ 64 <787200000>;
410 opp-peak-kBps = <18040 372 opp-peak-kBps = <1804000 19660800>;
411 }; 373 };
412 374
413 cpu0_opp7: opp-883200000 { 375 cpu0_opp7: opp-883200000 {
414 opp-hz = /bits/ 64 <88 376 opp-hz = /bits/ 64 <883200000>;
415 opp-peak-kBps = <18040 377 opp-peak-kBps = <1804000 23347200>;
416 }; 378 };
417 379
418 cpu0_opp8: opp-979200000 { 380 cpu0_opp8: opp-979200000 {
419 opp-hz = /bits/ 64 <97 381 opp-hz = /bits/ 64 <979200000>;
420 opp-peak-kBps = <18040 382 opp-peak-kBps = <1804000 26419200>;
421 }; 383 };
422 384
423 cpu0_opp9: opp-1075200000 { 385 cpu0_opp9: opp-1075200000 {
424 opp-hz = /bits/ 64 <10 386 opp-hz = /bits/ 64 <1075200000>;
425 opp-peak-kBps = <18040 387 opp-peak-kBps = <1804000 29491200>;
426 }; 388 };
427 389
428 cpu0_opp10: opp-1171200000 { 390 cpu0_opp10: opp-1171200000 {
429 opp-hz = /bits/ 64 <11 391 opp-hz = /bits/ 64 <1171200000>;
430 opp-peak-kBps = <18040 392 opp-peak-kBps = <1804000 32563200>;
431 }; 393 };
432 394
433 cpu0_opp11: opp-1248000000 { 395 cpu0_opp11: opp-1248000000 {
434 opp-hz = /bits/ 64 <12 396 opp-hz = /bits/ 64 <1248000000>;
435 opp-peak-kBps = <18040 397 opp-peak-kBps = <1804000 36249600>;
436 }; 398 };
437 399
438 cpu0_opp12: opp-1344000000 { 400 cpu0_opp12: opp-1344000000 {
439 opp-hz = /bits/ 64 <13 401 opp-hz = /bits/ 64 <1344000000>;
440 opp-peak-kBps = <21880 402 opp-peak-kBps = <2188000 36249600>;
441 }; 403 };
442 404
443 cpu0_opp13: opp-1420800000 { 405 cpu0_opp13: opp-1420800000 {
444 opp-hz = /bits/ 64 <14 406 opp-hz = /bits/ 64 <1420800000>;
445 opp-peak-kBps = <21880 407 opp-peak-kBps = <2188000 39321600>;
446 }; 408 };
447 409
448 cpu0_opp14: opp-1516800000 { 410 cpu0_opp14: opp-1516800000 {
449 opp-hz = /bits/ 64 <15 411 opp-hz = /bits/ 64 <1516800000>;
450 opp-peak-kBps = <30720 412 opp-peak-kBps = <3072000 42393600>;
451 }; 413 };
452 414
453 cpu0_opp15: opp-1612800000 { 415 cpu0_opp15: opp-1612800000 {
454 opp-hz = /bits/ 64 <16 416 opp-hz = /bits/ 64 <1612800000>;
455 opp-peak-kBps = <30720 417 opp-peak-kBps = <3072000 42393600>;
456 }; 418 };
457 419
458 cpu0_opp16: opp-1708800000 { 420 cpu0_opp16: opp-1708800000 {
459 opp-hz = /bits/ 64 <17 421 opp-hz = /bits/ 64 <1708800000>;
460 opp-peak-kBps = <40680 422 opp-peak-kBps = <4068000 42393600>;
461 }; 423 };
462 424
463 cpu0_opp17: opp-1804800000 { 425 cpu0_opp17: opp-1804800000 {
464 opp-hz = /bits/ 64 <18 426 opp-hz = /bits/ 64 <1804800000>;
465 opp-peak-kBps = <40680 427 opp-peak-kBps = <4068000 42393600>;
466 }; 428 };
467 }; 429 };
468 430
469 cpu4_opp_table: opp-table-cpu4 { 431 cpu4_opp_table: opp-table-cpu4 {
470 compatible = "operating-points 432 compatible = "operating-points-v2";
471 opp-shared; 433 opp-shared;
472 434
473 cpu4_opp1: opp-710400000 { 435 cpu4_opp1: opp-710400000 {
474 opp-hz = /bits/ 64 <71 436 opp-hz = /bits/ 64 <710400000>;
475 opp-peak-kBps = <18040 437 opp-peak-kBps = <1804000 19660800>;
476 }; 438 };
477 439
478 cpu4_opp2: opp-825600000 { 440 cpu4_opp2: opp-825600000 {
479 opp-hz = /bits/ 64 <82 441 opp-hz = /bits/ 64 <825600000>;
480 opp-peak-kBps = <21880 442 opp-peak-kBps = <2188000 23347200>;
481 }; 443 };
482 444
483 cpu4_opp3: opp-940800000 { 445 cpu4_opp3: opp-940800000 {
484 opp-hz = /bits/ 64 <94 446 opp-hz = /bits/ 64 <940800000>;
485 opp-peak-kBps = <21880 447 opp-peak-kBps = <2188000 26419200>;
486 }; 448 };
487 449
488 cpu4_opp4: opp-1056000000 { 450 cpu4_opp4: opp-1056000000 {
489 opp-hz = /bits/ 64 <10 451 opp-hz = /bits/ 64 <1056000000>;
490 opp-peak-kBps = <30720 452 opp-peak-kBps = <3072000 26419200>;
491 }; 453 };
492 454
493 cpu4_opp5: opp-1171200000 { 455 cpu4_opp5: opp-1171200000 {
494 opp-hz = /bits/ 64 <11 456 opp-hz = /bits/ 64 <1171200000>;
495 opp-peak-kBps = <30720 457 opp-peak-kBps = <3072000 29491200>;
496 }; 458 };
497 459
498 cpu4_opp6: opp-1286400000 { 460 cpu4_opp6: opp-1286400000 {
499 opp-hz = /bits/ 64 <12 461 opp-hz = /bits/ 64 <1286400000>;
500 opp-peak-kBps = <40680 462 opp-peak-kBps = <4068000 29491200>;
501 }; 463 };
502 464
503 cpu4_opp7: opp-1382400000 { 465 cpu4_opp7: opp-1382400000 {
504 opp-hz = /bits/ 64 <13 466 opp-hz = /bits/ 64 <1382400000>;
505 opp-peak-kBps = <40680 467 opp-peak-kBps = <4068000 32563200>;
506 }; 468 };
507 469
508 cpu4_opp8: opp-1478400000 { 470 cpu4_opp8: opp-1478400000 {
509 opp-hz = /bits/ 64 <14 471 opp-hz = /bits/ 64 <1478400000>;
510 opp-peak-kBps = <40680 472 opp-peak-kBps = <4068000 32563200>;
511 }; 473 };
512 474
513 cpu4_opp9: opp-1574400000 { 475 cpu4_opp9: opp-1574400000 {
514 opp-hz = /bits/ 64 <15 476 opp-hz = /bits/ 64 <1574400000>;
515 opp-peak-kBps = <54120 477 opp-peak-kBps = <5412000 39321600>;
516 }; 478 };
517 479
518 cpu4_opp10: opp-1670400000 { 480 cpu4_opp10: opp-1670400000 {
519 opp-hz = /bits/ 64 <16 481 opp-hz = /bits/ 64 <1670400000>;
520 opp-peak-kBps = <54120 482 opp-peak-kBps = <5412000 42393600>;
521 }; 483 };
522 484
523 cpu4_opp11: opp-1766400000 { 485 cpu4_opp11: opp-1766400000 {
524 opp-hz = /bits/ 64 <17 486 opp-hz = /bits/ 64 <1766400000>;
525 opp-peak-kBps = <54120 487 opp-peak-kBps = <5412000 45465600>;
526 }; 488 };
527 489
528 cpu4_opp12: opp-1862400000 { 490 cpu4_opp12: opp-1862400000 {
529 opp-hz = /bits/ 64 <18 491 opp-hz = /bits/ 64 <1862400000>;
530 opp-peak-kBps = <62200 492 opp-peak-kBps = <6220000 45465600>;
531 }; 493 };
532 494
533 cpu4_opp13: opp-1958400000 { 495 cpu4_opp13: opp-1958400000 {
534 opp-hz = /bits/ 64 <19 496 opp-hz = /bits/ 64 <1958400000>;
535 opp-peak-kBps = <62200 497 opp-peak-kBps = <6220000 48537600>;
536 }; 498 };
537 499
538 cpu4_opp14: opp-2054400000 { 500 cpu4_opp14: opp-2054400000 {
539 opp-hz = /bits/ 64 <20 501 opp-hz = /bits/ 64 <2054400000>;
540 opp-peak-kBps = <72160 502 opp-peak-kBps = <7216000 48537600>;
541 }; 503 };
542 504
543 cpu4_opp15: opp-2150400000 { 505 cpu4_opp15: opp-2150400000 {
544 opp-hz = /bits/ 64 <21 506 opp-hz = /bits/ 64 <2150400000>;
545 opp-peak-kBps = <72160 507 opp-peak-kBps = <7216000 51609600>;
546 }; 508 };
547 509
548 cpu4_opp16: opp-2246400000 { 510 cpu4_opp16: opp-2246400000 {
549 opp-hz = /bits/ 64 <22 511 opp-hz = /bits/ 64 <2246400000>;
550 opp-peak-kBps = <72160 512 opp-peak-kBps = <7216000 51609600>;
551 }; 513 };
552 514
553 cpu4_opp17: opp-2342400000 { 515 cpu4_opp17: opp-2342400000 {
554 opp-hz = /bits/ 64 <23 516 opp-hz = /bits/ 64 <2342400000>;
555 opp-peak-kBps = <83680 517 opp-peak-kBps = <8368000 51609600>;
556 }; 518 };
557 519
558 cpu4_opp18: opp-2419200000 { 520 cpu4_opp18: opp-2419200000 {
559 opp-hz = /bits/ 64 <24 521 opp-hz = /bits/ 64 <2419200000>;
560 opp-peak-kBps = <83680 522 opp-peak-kBps = <8368000 51609600>;
561 }; 523 };
562 }; 524 };
563 525
564 cpu7_opp_table: opp-table-cpu7 { 526 cpu7_opp_table: opp-table-cpu7 {
565 compatible = "operating-points 527 compatible = "operating-points-v2";
566 opp-shared; 528 opp-shared;
567 529
568 cpu7_opp1: opp-844800000 { 530 cpu7_opp1: opp-844800000 {
569 opp-hz = /bits/ 64 <84 531 opp-hz = /bits/ 64 <844800000>;
570 opp-peak-kBps = <21880 532 opp-peak-kBps = <2188000 19660800>;
571 }; 533 };
572 534
573 cpu7_opp2: opp-960000000 { 535 cpu7_opp2: opp-960000000 {
574 opp-hz = /bits/ 64 <96 536 opp-hz = /bits/ 64 <960000000>;
575 opp-peak-kBps = <21880 537 opp-peak-kBps = <2188000 26419200>;
576 }; 538 };
577 539
578 cpu7_opp3: opp-1075200000 { 540 cpu7_opp3: opp-1075200000 {
579 opp-hz = /bits/ 64 <10 541 opp-hz = /bits/ 64 <1075200000>;
580 opp-peak-kBps = <30720 542 opp-peak-kBps = <3072000 26419200>;
581 }; 543 };
582 544
583 cpu7_opp4: opp-1190400000 { 545 cpu7_opp4: opp-1190400000 {
584 opp-hz = /bits/ 64 <11 546 opp-hz = /bits/ 64 <1190400000>;
585 opp-peak-kBps = <30720 547 opp-peak-kBps = <3072000 29491200>;
586 }; 548 };
587 549
588 cpu7_opp5: opp-1305600000 { 550 cpu7_opp5: opp-1305600000 {
589 opp-hz = /bits/ 64 <13 551 opp-hz = /bits/ 64 <1305600000>;
590 opp-peak-kBps = <40680 552 opp-peak-kBps = <4068000 32563200>;
591 }; 553 };
592 554
593 cpu7_opp6: opp-1401600000 { 555 cpu7_opp6: opp-1401600000 {
594 opp-hz = /bits/ 64 <14 556 opp-hz = /bits/ 64 <1401600000>;
595 opp-peak-kBps = <40680 557 opp-peak-kBps = <4068000 32563200>;
596 }; 558 };
597 559
598 cpu7_opp7: opp-1516800000 { 560 cpu7_opp7: opp-1516800000 {
599 opp-hz = /bits/ 64 <15 561 opp-hz = /bits/ 64 <1516800000>;
600 opp-peak-kBps = <40680 562 opp-peak-kBps = <4068000 36249600>;
601 }; 563 };
602 564
603 cpu7_opp8: opp-1632000000 { 565 cpu7_opp8: opp-1632000000 {
604 opp-hz = /bits/ 64 <16 566 opp-hz = /bits/ 64 <1632000000>;
605 opp-peak-kBps = <54120 567 opp-peak-kBps = <5412000 39321600>;
606 }; 568 };
607 569
608 cpu7_opp9: opp-1747200000 { 570 cpu7_opp9: opp-1747200000 {
609 opp-hz = /bits/ 64 <17 571 opp-hz = /bits/ 64 <1708800000>;
610 opp-peak-kBps = <54120 572 opp-peak-kBps = <5412000 42393600>;
611 }; 573 };
612 574
613 cpu7_opp10: opp-1862400000 { 575 cpu7_opp10: opp-1862400000 {
614 opp-hz = /bits/ 64 <18 576 opp-hz = /bits/ 64 <1862400000>;
615 opp-peak-kBps = <62200 577 opp-peak-kBps = <6220000 45465600>;
616 }; 578 };
617 579
618 cpu7_opp11: opp-1977600000 { 580 cpu7_opp11: opp-1977600000 {
619 opp-hz = /bits/ 64 <19 581 opp-hz = /bits/ 64 <1977600000>;
620 opp-peak-kBps = <62200 582 opp-peak-kBps = <6220000 48537600>;
621 }; 583 };
622 584
623 cpu7_opp12: opp-2073600000 { 585 cpu7_opp12: opp-2073600000 {
624 opp-hz = /bits/ 64 <20 586 opp-hz = /bits/ 64 <2073600000>;
625 opp-peak-kBps = <72160 587 opp-peak-kBps = <7216000 48537600>;
626 }; 588 };
627 589
628 cpu7_opp13: opp-2169600000 { 590 cpu7_opp13: opp-2169600000 {
629 opp-hz = /bits/ 64 <21 591 opp-hz = /bits/ 64 <2169600000>;
630 opp-peak-kBps = <72160 592 opp-peak-kBps = <7216000 51609600>;
631 }; 593 };
632 594
633 cpu7_opp14: opp-2265600000 { 595 cpu7_opp14: opp-2265600000 {
634 opp-hz = /bits/ 64 <22 596 opp-hz = /bits/ 64 <2265600000>;
635 opp-peak-kBps = <72160 597 opp-peak-kBps = <7216000 51609600>;
636 }; 598 };
637 599
638 cpu7_opp15: opp-2361600000 { 600 cpu7_opp15: opp-2361600000 {
639 opp-hz = /bits/ 64 <23 601 opp-hz = /bits/ 64 <2361600000>;
640 opp-peak-kBps = <83680 602 opp-peak-kBps = <8368000 51609600>;
641 }; 603 };
642 604
643 cpu7_opp16: opp-2457600000 { 605 cpu7_opp16: opp-2457600000 {
644 opp-hz = /bits/ 64 <24 606 opp-hz = /bits/ 64 <2457600000>;
645 opp-peak-kBps = <83680 607 opp-peak-kBps = <8368000 51609600>;
646 }; 608 };
647 609
648 cpu7_opp17: opp-2553600000 { 610 cpu7_opp17: opp-2553600000 {
649 opp-hz = /bits/ 64 <25 611 opp-hz = /bits/ 64 <2553600000>;
650 opp-peak-kBps = <83680 612 opp-peak-kBps = <8368000 51609600>;
651 }; 613 };
652 614
653 cpu7_opp18: opp-2649600000 { 615 cpu7_opp18: opp-2649600000 {
654 opp-hz = /bits/ 64 <26 616 opp-hz = /bits/ 64 <2649600000>;
655 opp-peak-kBps = <83680 617 opp-peak-kBps = <8368000 51609600>;
656 }; 618 };
657 619
658 cpu7_opp19: opp-2745600000 { 620 cpu7_opp19: opp-2745600000 {
659 opp-hz = /bits/ 64 <27 621 opp-hz = /bits/ 64 <2745600000>;
660 opp-peak-kBps = <83680 622 opp-peak-kBps = <8368000 51609600>;
661 }; 623 };
662 624
663 cpu7_opp20: opp-2841600000 { 625 cpu7_opp20: opp-2841600000 {
664 opp-hz = /bits/ 64 <28 626 opp-hz = /bits/ 64 <2841600000>;
665 opp-peak-kBps = <83680 627 opp-peak-kBps = <8368000 51609600>;
666 }; 628 };
667 }; 629 };
668 630
669 firmware { 631 firmware {
670 scm: scm { 632 scm: scm {
671 compatible = "qcom,scm 633 compatible = "qcom,scm-sm8250", "qcom,scm";
672 qcom,dload-mode = <&tc <<
673 #reset-cells = <1>; 634 #reset-cells = <1>;
674 }; 635 };
675 }; 636 };
676 637
677 memory@80000000 { 638 memory@80000000 {
678 device_type = "memory"; 639 device_type = "memory";
679 /* We expect the bootloader to 640 /* We expect the bootloader to fill in the size */
680 reg = <0x0 0x80000000 0x0 0x0> 641 reg = <0x0 0x80000000 0x0 0x0>;
681 }; 642 };
682 643
683 pmu { 644 pmu {
684 compatible = "arm,armv8-pmuv3" 645 compatible = "arm,armv8-pmuv3";
685 interrupts = <GIC_PPI 7 IRQ_TY 646 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
686 }; 647 };
687 648
688 psci { 649 psci {
689 compatible = "arm,psci-1.0"; 650 compatible = "arm,psci-1.0";
690 method = "smc"; 651 method = "smc";
691 652
692 CPU_PD0: power-domain-cpu0 { !! 653 CPU_PD0: cpu0 {
693 #power-domain-cells = 654 #power-domain-cells = <0>;
694 power-domains = <&CLUS 655 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = < 656 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
696 }; 657 };
697 658
698 CPU_PD1: power-domain-cpu1 { !! 659 CPU_PD1: cpu1 {
699 #power-domain-cells = 660 #power-domain-cells = <0>;
700 power-domains = <&CLUS 661 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = < 662 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
702 }; 663 };
703 664
704 CPU_PD2: power-domain-cpu2 { !! 665 CPU_PD2: cpu2 {
705 #power-domain-cells = 666 #power-domain-cells = <0>;
706 power-domains = <&CLUS 667 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = < 668 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
708 }; 669 };
709 670
710 CPU_PD3: power-domain-cpu3 { !! 671 CPU_PD3: cpu3 {
711 #power-domain-cells = 672 #power-domain-cells = <0>;
712 power-domains = <&CLUS 673 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = < 674 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
714 }; 675 };
715 676
716 CPU_PD4: power-domain-cpu4 { !! 677 CPU_PD4: cpu4 {
717 #power-domain-cells = 678 #power-domain-cells = <0>;
718 power-domains = <&CLUS 679 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = < 680 domain-idle-states = <&BIG_CPU_SLEEP_0>;
720 }; 681 };
721 682
722 CPU_PD5: power-domain-cpu5 { !! 683 CPU_PD5: cpu5 {
723 #power-domain-cells = 684 #power-domain-cells = <0>;
724 power-domains = <&CLUS 685 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = < 686 domain-idle-states = <&BIG_CPU_SLEEP_0>;
726 }; 687 };
727 688
728 CPU_PD6: power-domain-cpu6 { !! 689 CPU_PD6: cpu6 {
729 #power-domain-cells = 690 #power-domain-cells = <0>;
730 power-domains = <&CLUS 691 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = < 692 domain-idle-states = <&BIG_CPU_SLEEP_0>;
732 }; 693 };
733 694
734 CPU_PD7: power-domain-cpu7 { !! 695 CPU_PD7: cpu7 {
735 #power-domain-cells = 696 #power-domain-cells = <0>;
736 power-domains = <&CLUS 697 power-domains = <&CLUSTER_PD>;
737 domain-idle-states = < 698 domain-idle-states = <&BIG_CPU_SLEEP_0>;
738 }; 699 };
739 700
740 CLUSTER_PD: power-domain-cpu-c !! 701 CLUSTER_PD: cpu-cluster0 {
741 #power-domain-cells = 702 #power-domain-cells = <0>;
742 domain-idle-states = < 703 domain-idle-states = <&CLUSTER_SLEEP_0>;
743 }; 704 };
744 }; 705 };
745 706
746 qup_opp_table: opp-table-qup { 707 qup_opp_table: opp-table-qup {
747 compatible = "operating-points 708 compatible = "operating-points-v2";
748 709
749 opp-50000000 { 710 opp-50000000 {
750 opp-hz = /bits/ 64 <50 711 opp-hz = /bits/ 64 <50000000>;
751 required-opps = <&rpmh 712 required-opps = <&rpmhpd_opp_min_svs>;
752 }; 713 };
753 714
754 opp-75000000 { 715 opp-75000000 {
755 opp-hz = /bits/ 64 <75 716 opp-hz = /bits/ 64 <75000000>;
756 required-opps = <&rpmh 717 required-opps = <&rpmhpd_opp_low_svs>;
757 }; 718 };
758 719
759 opp-120000000 { 720 opp-120000000 {
760 opp-hz = /bits/ 64 <12 721 opp-hz = /bits/ 64 <120000000>;
761 required-opps = <&rpmh 722 required-opps = <&rpmhpd_opp_svs>;
762 }; 723 };
763 }; 724 };
764 725
765 reserved-memory { 726 reserved-memory {
766 #address-cells = <2>; 727 #address-cells = <2>;
767 #size-cells = <2>; 728 #size-cells = <2>;
768 ranges; 729 ranges;
769 730
770 hyp_mem: memory@80000000 { 731 hyp_mem: memory@80000000 {
771 reg = <0x0 0x80000000 732 reg = <0x0 0x80000000 0x0 0x600000>;
772 no-map; 733 no-map;
773 }; 734 };
774 735
775 xbl_aop_mem: memory@80700000 { 736 xbl_aop_mem: memory@80700000 {
776 reg = <0x0 0x80700000 737 reg = <0x0 0x80700000 0x0 0x160000>;
777 no-map; 738 no-map;
778 }; 739 };
779 740
780 cmd_db: memory@80860000 { 741 cmd_db: memory@80860000 {
781 compatible = "qcom,cmd 742 compatible = "qcom,cmd-db";
782 reg = <0x0 0x80860000 743 reg = <0x0 0x80860000 0x0 0x20000>;
783 no-map; 744 no-map;
784 }; 745 };
785 746
786 smem_mem: memory@80900000 { 747 smem_mem: memory@80900000 {
787 reg = <0x0 0x80900000 748 reg = <0x0 0x80900000 0x0 0x200000>;
788 no-map; 749 no-map;
789 }; 750 };
790 751
791 removed_mem: memory@80b00000 { 752 removed_mem: memory@80b00000 {
792 reg = <0x0 0x80b00000 753 reg = <0x0 0x80b00000 0x0 0x5300000>;
793 no-map; 754 no-map;
794 }; 755 };
795 756
796 camera_mem: memory@86200000 { 757 camera_mem: memory@86200000 {
797 reg = <0x0 0x86200000 758 reg = <0x0 0x86200000 0x0 0x500000>;
798 no-map; 759 no-map;
799 }; 760 };
800 761
801 wlan_mem: memory@86700000 { 762 wlan_mem: memory@86700000 {
802 reg = <0x0 0x86700000 763 reg = <0x0 0x86700000 0x0 0x100000>;
803 no-map; 764 no-map;
804 }; 765 };
805 766
806 ipa_fw_mem: memory@86800000 { 767 ipa_fw_mem: memory@86800000 {
807 reg = <0x0 0x86800000 768 reg = <0x0 0x86800000 0x0 0x10000>;
808 no-map; 769 no-map;
809 }; 770 };
810 771
811 ipa_gsi_mem: memory@86810000 { 772 ipa_gsi_mem: memory@86810000 {
812 reg = <0x0 0x86810000 773 reg = <0x0 0x86810000 0x0 0xa000>;
813 no-map; 774 no-map;
814 }; 775 };
815 776
816 gpu_mem: memory@8681a000 { 777 gpu_mem: memory@8681a000 {
817 reg = <0x0 0x8681a000 778 reg = <0x0 0x8681a000 0x0 0x2000>;
818 no-map; 779 no-map;
819 }; 780 };
820 781
821 npu_mem: memory@86900000 { 782 npu_mem: memory@86900000 {
822 reg = <0x0 0x86900000 783 reg = <0x0 0x86900000 0x0 0x500000>;
823 no-map; 784 no-map;
824 }; 785 };
825 786
826 video_mem: memory@86e00000 { 787 video_mem: memory@86e00000 {
827 reg = <0x0 0x86e00000 788 reg = <0x0 0x86e00000 0x0 0x500000>;
828 no-map; 789 no-map;
829 }; 790 };
830 791
831 cvp_mem: memory@87300000 { 792 cvp_mem: memory@87300000 {
832 reg = <0x0 0x87300000 793 reg = <0x0 0x87300000 0x0 0x500000>;
833 no-map; 794 no-map;
834 }; 795 };
835 796
836 cdsp_mem: memory@87800000 { 797 cdsp_mem: memory@87800000 {
837 reg = <0x0 0x87800000 798 reg = <0x0 0x87800000 0x0 0x1400000>;
838 no-map; 799 no-map;
839 }; 800 };
840 801
841 slpi_mem: memory@88c00000 { 802 slpi_mem: memory@88c00000 {
842 reg = <0x0 0x88c00000 803 reg = <0x0 0x88c00000 0x0 0x1500000>;
843 no-map; 804 no-map;
844 }; 805 };
845 806
846 adsp_mem: memory@8a100000 { 807 adsp_mem: memory@8a100000 {
847 reg = <0x0 0x8a100000 808 reg = <0x0 0x8a100000 0x0 0x1d00000>;
848 no-map; 809 no-map;
849 }; 810 };
850 811
851 spss_mem: memory@8be00000 { 812 spss_mem: memory@8be00000 {
852 reg = <0x0 0x8be00000 813 reg = <0x0 0x8be00000 0x0 0x100000>;
853 no-map; 814 no-map;
854 }; 815 };
855 816
856 cdsp_secure_heap: memory@8bf00 817 cdsp_secure_heap: memory@8bf00000 {
857 reg = <0x0 0x8bf00000 818 reg = <0x0 0x8bf00000 0x0 0x4600000>;
858 no-map; 819 no-map;
859 }; 820 };
860 }; 821 };
861 822
862 smem { 823 smem {
863 compatible = "qcom,smem"; 824 compatible = "qcom,smem";
864 memory-region = <&smem_mem>; 825 memory-region = <&smem_mem>;
865 hwlocks = <&tcsr_mutex 3>; 826 hwlocks = <&tcsr_mutex 3>;
866 }; 827 };
867 828
868 smp2p-adsp { 829 smp2p-adsp {
869 compatible = "qcom,smp2p"; 830 compatible = "qcom,smp2p";
870 qcom,smem = <443>, <429>; 831 qcom,smem = <443>, <429>;
871 interrupts-extended = <&ipcc I 832 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
872 I 833 IPCC_MPROC_SIGNAL_SMP2P
873 I 834 IRQ_TYPE_EDGE_RISING>;
874 mboxes = <&ipcc IPCC_CLIENT_LP 835 mboxes = <&ipcc IPCC_CLIENT_LPASS
875 IPCC_MPROC_SIG 836 IPCC_MPROC_SIGNAL_SMP2P>;
876 837
877 qcom,local-pid = <0>; 838 qcom,local-pid = <0>;
878 qcom,remote-pid = <2>; 839 qcom,remote-pid = <2>;
879 840
880 smp2p_adsp_out: master-kernel 841 smp2p_adsp_out: master-kernel {
881 qcom,entry-name = "mas 842 qcom,entry-name = "master-kernel";
882 #qcom,smem-state-cells 843 #qcom,smem-state-cells = <1>;
883 }; 844 };
884 845
885 smp2p_adsp_in: slave-kernel { 846 smp2p_adsp_in: slave-kernel {
886 qcom,entry-name = "sla 847 qcom,entry-name = "slave-kernel";
887 interrupt-controller; 848 interrupt-controller;
888 #interrupt-cells = <2> 849 #interrupt-cells = <2>;
889 }; 850 };
890 }; 851 };
891 852
892 smp2p-cdsp { 853 smp2p-cdsp {
893 compatible = "qcom,smp2p"; 854 compatible = "qcom,smp2p";
894 qcom,smem = <94>, <432>; 855 qcom,smem = <94>, <432>;
895 interrupts-extended = <&ipcc I 856 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
896 I 857 IPCC_MPROC_SIGNAL_SMP2P
897 I 858 IRQ_TYPE_EDGE_RISING>;
898 mboxes = <&ipcc IPCC_CLIENT_CD 859 mboxes = <&ipcc IPCC_CLIENT_CDSP
899 IPCC_MPROC_SIG 860 IPCC_MPROC_SIGNAL_SMP2P>;
900 861
901 qcom,local-pid = <0>; 862 qcom,local-pid = <0>;
902 qcom,remote-pid = <5>; 863 qcom,remote-pid = <5>;
903 864
904 smp2p_cdsp_out: master-kernel 865 smp2p_cdsp_out: master-kernel {
905 qcom,entry-name = "mas 866 qcom,entry-name = "master-kernel";
906 #qcom,smem-state-cells 867 #qcom,smem-state-cells = <1>;
907 }; 868 };
908 869
909 smp2p_cdsp_in: slave-kernel { 870 smp2p_cdsp_in: slave-kernel {
910 qcom,entry-name = "sla 871 qcom,entry-name = "slave-kernel";
911 interrupt-controller; 872 interrupt-controller;
912 #interrupt-cells = <2> 873 #interrupt-cells = <2>;
913 }; 874 };
914 }; 875 };
915 876
916 smp2p-slpi { 877 smp2p-slpi {
917 compatible = "qcom,smp2p"; 878 compatible = "qcom,smp2p";
918 qcom,smem = <481>, <430>; 879 qcom,smem = <481>, <430>;
919 interrupts-extended = <&ipcc I 880 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
920 I 881 IPCC_MPROC_SIGNAL_SMP2P
921 I 882 IRQ_TYPE_EDGE_RISING>;
922 mboxes = <&ipcc IPCC_CLIENT_SL 883 mboxes = <&ipcc IPCC_CLIENT_SLPI
923 IPCC_MPROC_SIG 884 IPCC_MPROC_SIGNAL_SMP2P>;
924 885
925 qcom,local-pid = <0>; 886 qcom,local-pid = <0>;
926 qcom,remote-pid = <3>; 887 qcom,remote-pid = <3>;
927 888
928 smp2p_slpi_out: master-kernel 889 smp2p_slpi_out: master-kernel {
929 qcom,entry-name = "mas 890 qcom,entry-name = "master-kernel";
930 #qcom,smem-state-cells 891 #qcom,smem-state-cells = <1>;
931 }; 892 };
932 893
933 smp2p_slpi_in: slave-kernel { 894 smp2p_slpi_in: slave-kernel {
934 qcom,entry-name = "sla 895 qcom,entry-name = "slave-kernel";
935 interrupt-controller; 896 interrupt-controller;
936 #interrupt-cells = <2> 897 #interrupt-cells = <2>;
937 }; 898 };
938 }; 899 };
939 900
940 soc: soc@0 { 901 soc: soc@0 {
941 #address-cells = <2>; 902 #address-cells = <2>;
942 #size-cells = <2>; 903 #size-cells = <2>;
943 ranges = <0 0 0 0 0x10 0>; 904 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>; 905 dma-ranges = <0 0 0 0 0x10 0>;
945 compatible = "simple-bus"; 906 compatible = "simple-bus";
946 907
947 gcc: clock-controller@100000 { 908 gcc: clock-controller@100000 {
948 compatible = "qcom,gcc 909 compatible = "qcom,gcc-sm8250";
949 reg = <0x0 0x00100000 910 reg = <0x0 0x00100000 0x0 0x1f0000>;
950 #clock-cells = <1>; 911 #clock-cells = <1>;
951 #reset-cells = <1>; 912 #reset-cells = <1>;
952 #power-domain-cells = 913 #power-domain-cells = <1>;
953 clock-names = "bi_tcxo 914 clock-names = "bi_tcxo",
954 "bi_tcxo 915 "bi_tcxo_ao",
955 "sleep_c 916 "sleep_clk";
956 clocks = <&rpmhcc RPMH 917 clocks = <&rpmhcc RPMH_CXO_CLK>,
957 <&rpmhcc RPMH 918 <&rpmhcc RPMH_CXO_CLK_A>,
958 <&sleep_clk>; 919 <&sleep_clk>;
959 }; 920 };
960 921
961 ipcc: mailbox@408000 { 922 ipcc: mailbox@408000 {
962 compatible = "qcom,sm8 923 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
963 reg = <0 0x00408000 0 924 reg = <0 0x00408000 0 0x1000>;
964 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-controller; 926 interrupt-controller;
966 #interrupt-cells = <3> 927 #interrupt-cells = <3>;
967 #mbox-cells = <2>; 928 #mbox-cells = <2>;
968 }; 929 };
969 930
970 qfprom: efuse@784000 { <<
971 compatible = "qcom,sm8 <<
972 reg = <0 0x00784000 0 <<
973 #address-cells = <1>; <<
974 #size-cells = <1>; <<
975 <<
976 gpu_speed_bin: gpu-spe <<
977 reg = <0x19b 0 <<
978 bits = <5 3>; <<
979 }; <<
980 }; <<
981 <<
982 rng: rng@793000 { 931 rng: rng@793000 {
983 compatible = "qcom,prn 932 compatible = "qcom,prng-ee";
984 reg = <0 0x00793000 0 933 reg = <0 0x00793000 0 0x1000>;
985 clocks = <&gcc GCC_PRN 934 clocks = <&gcc GCC_PRNG_AHB_CLK>;
986 clock-names = "core"; 935 clock-names = "core";
987 }; 936 };
988 937
989 gpi_dma2: dma-controller@80000 938 gpi_dma2: dma-controller@800000 {
990 compatible = "qcom,sm8 939 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
991 reg = <0 0x00800000 0 940 reg = <0 0x00800000 0 0x70000>;
992 interrupts = <GIC_SPI 941 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 942 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 943 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 944 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 945 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 946 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 947 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 948 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1000 <GIC_SPI 949 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 950 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
1002 dma-channels = <10>; 951 dma-channels = <10>;
1003 dma-channel-mask = <0 952 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 953 iommus = <&apps_smmu 0x76 0x0>;
1005 #dma-cells = <3>; 954 #dma-cells = <3>;
1006 status = "disabled"; 955 status = "disabled";
1007 }; 956 };
1008 957
1009 qupv3_id_2: geniqup@8c0000 { 958 qupv3_id_2: geniqup@8c0000 {
1010 compatible = "qcom,ge 959 compatible = "qcom,geni-se-qup";
1011 reg = <0x0 0x008c0000 960 reg = <0x0 0x008c0000 0x0 0x6000>;
1012 clock-names = "m-ahb" 961 clock-names = "m-ahb", "s-ahb";
1013 clocks = <&gcc GCC_QU 962 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1014 <&gcc GCC_QU 963 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1015 #address-cells = <2>; 964 #address-cells = <2>;
1016 #size-cells = <2>; 965 #size-cells = <2>;
1017 iommus = <&apps_smmu 966 iommus = <&apps_smmu 0x63 0x0>;
1018 ranges; 967 ranges;
1019 status = "disabled"; 968 status = "disabled";
1020 969
1021 i2c14: i2c@880000 { 970 i2c14: i2c@880000 {
1022 compatible = 971 compatible = "qcom,geni-i2c";
1023 reg = <0 0x00 972 reg = <0 0x00880000 0 0x4000>;
1024 clock-names = 973 clock-names = "se";
1025 clocks = <&gc 974 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1026 pinctrl-names 975 pinctrl-names = "default";
1027 pinctrl-0 = < 976 pinctrl-0 = <&qup_i2c14_default>;
1028 interrupts = 977 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1029 dmas = <&gpi_ 978 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_ 979 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1031 dma-names = " 980 dma-names = "tx", "rx";
1032 power-domains <<
1033 interconnects <<
1034 <<
1035 <<
1036 interconnect- <<
1037 <<
1038 <<
1039 #address-cell 981 #address-cells = <1>;
1040 #size-cells = 982 #size-cells = <0>;
1041 status = "dis 983 status = "disabled";
1042 }; 984 };
1043 985
1044 spi14: spi@880000 { 986 spi14: spi@880000 {
1045 compatible = 987 compatible = "qcom,geni-spi";
1046 reg = <0 0x00 988 reg = <0 0x00880000 0 0x4000>;
1047 clock-names = 989 clock-names = "se";
1048 clocks = <&gc 990 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1049 interrupts = 991 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1050 dmas = <&gpi_ 992 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_ 993 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1052 dma-names = " 994 dma-names = "tx", "rx";
1053 power-domains !! 995 power-domains = <&rpmhpd SM8250_CX>;
1054 operating-poi 996 operating-points-v2 = <&qup_opp_table>;
1055 interconnects <<
1056 <<
1057 <<
1058 interconnect- <<
1059 <<
1060 <<
1061 #address-cell 997 #address-cells = <1>;
1062 #size-cells = 998 #size-cells = <0>;
1063 status = "dis 999 status = "disabled";
1064 }; 1000 };
1065 1001
1066 i2c15: i2c@884000 { 1002 i2c15: i2c@884000 {
1067 compatible = 1003 compatible = "qcom,geni-i2c";
1068 reg = <0 0x00 1004 reg = <0 0x00884000 0 0x4000>;
1069 clock-names = 1005 clock-names = "se";
1070 clocks = <&gc 1006 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1071 pinctrl-names 1007 pinctrl-names = "default";
1072 pinctrl-0 = < 1008 pinctrl-0 = <&qup_i2c15_default>;
1073 interrupts = 1009 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1074 dmas = <&gpi_ 1010 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1075 <&gpi_ 1011 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1076 dma-names = " 1012 dma-names = "tx", "rx";
1077 power-domains <<
1078 interconnects <<
1079 <<
1080 <<
1081 interconnect- <<
1082 <<
1083 <<
1084 #address-cell 1013 #address-cells = <1>;
1085 #size-cells = 1014 #size-cells = <0>;
1086 status = "dis 1015 status = "disabled";
1087 }; 1016 };
1088 1017
1089 spi15: spi@884000 { 1018 spi15: spi@884000 {
1090 compatible = 1019 compatible = "qcom,geni-spi";
1091 reg = <0 0x00 1020 reg = <0 0x00884000 0 0x4000>;
1092 clock-names = 1021 clock-names = "se";
1093 clocks = <&gc 1022 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1094 interrupts = 1023 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1095 dmas = <&gpi_ 1024 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1096 <&gpi_ 1025 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1097 dma-names = " 1026 dma-names = "tx", "rx";
1098 power-domains !! 1027 power-domains = <&rpmhpd SM8250_CX>;
1099 operating-poi 1028 operating-points-v2 = <&qup_opp_table>;
1100 interconnects <<
1101 <<
1102 <<
1103 interconnect- <<
1104 <<
1105 <<
1106 #address-cell 1029 #address-cells = <1>;
1107 #size-cells = 1030 #size-cells = <0>;
1108 status = "dis 1031 status = "disabled";
1109 }; 1032 };
1110 1033
1111 i2c16: i2c@888000 { 1034 i2c16: i2c@888000 {
1112 compatible = 1035 compatible = "qcom,geni-i2c";
1113 reg = <0 0x00 1036 reg = <0 0x00888000 0 0x4000>;
1114 clock-names = 1037 clock-names = "se";
1115 clocks = <&gc 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1116 pinctrl-names 1039 pinctrl-names = "default";
1117 pinctrl-0 = < 1040 pinctrl-0 = <&qup_i2c16_default>;
1118 interrupts = 1041 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1119 dmas = <&gpi_ 1042 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1120 <&gpi_ 1043 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1121 dma-names = " 1044 dma-names = "tx", "rx";
1122 power-domains <<
1123 interconnects <<
1124 <<
1125 <<
1126 interconnect- <<
1127 <<
1128 <<
1129 #address-cell 1045 #address-cells = <1>;
1130 #size-cells = 1046 #size-cells = <0>;
1131 status = "dis 1047 status = "disabled";
1132 }; 1048 };
1133 1049
1134 spi16: spi@888000 { 1050 spi16: spi@888000 {
1135 compatible = 1051 compatible = "qcom,geni-spi";
1136 reg = <0 0x00 1052 reg = <0 0x00888000 0 0x4000>;
1137 clock-names = 1053 clock-names = "se";
1138 clocks = <&gc 1054 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1139 interrupts = 1055 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1140 dmas = <&gpi_ 1056 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1141 <&gpi_ 1057 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1142 dma-names = " 1058 dma-names = "tx", "rx";
1143 power-domains !! 1059 power-domains = <&rpmhpd SM8250_CX>;
1144 operating-poi 1060 operating-points-v2 = <&qup_opp_table>;
1145 interconnects <<
1146 <<
1147 <<
1148 interconnect- <<
1149 <<
1150 <<
1151 #address-cell 1061 #address-cells = <1>;
1152 #size-cells = 1062 #size-cells = <0>;
1153 status = "dis 1063 status = "disabled";
1154 }; 1064 };
1155 1065
1156 i2c17: i2c@88c000 { 1066 i2c17: i2c@88c000 {
1157 compatible = 1067 compatible = "qcom,geni-i2c";
1158 reg = <0 0x00 1068 reg = <0 0x0088c000 0 0x4000>;
1159 clock-names = 1069 clock-names = "se";
1160 clocks = <&gc 1070 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1161 pinctrl-names 1071 pinctrl-names = "default";
1162 pinctrl-0 = < 1072 pinctrl-0 = <&qup_i2c17_default>;
1163 interrupts = 1073 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1164 dmas = <&gpi_ 1074 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1165 <&gpi_ 1075 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1166 dma-names = " 1076 dma-names = "tx", "rx";
1167 power-domains <<
1168 interconnects <<
1169 <<
1170 <<
1171 interconnect- <<
1172 <<
1173 <<
1174 #address-cell 1077 #address-cells = <1>;
1175 #size-cells = 1078 #size-cells = <0>;
1176 status = "dis 1079 status = "disabled";
1177 }; 1080 };
1178 1081
1179 spi17: spi@88c000 { 1082 spi17: spi@88c000 {
1180 compatible = 1083 compatible = "qcom,geni-spi";
1181 reg = <0 0x00 1084 reg = <0 0x0088c000 0 0x4000>;
1182 clock-names = 1085 clock-names = "se";
1183 clocks = <&gc 1086 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1184 interrupts = 1087 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&gpi_ 1088 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1186 <&gpi_ 1089 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1187 dma-names = " 1090 dma-names = "tx", "rx";
1188 power-domains !! 1091 power-domains = <&rpmhpd SM8250_CX>;
1189 operating-poi 1092 operating-points-v2 = <&qup_opp_table>;
1190 interconnects <<
1191 <<
1192 <<
1193 interconnect- <<
1194 <<
1195 <<
1196 #address-cell 1093 #address-cells = <1>;
1197 #size-cells = 1094 #size-cells = <0>;
1198 status = "dis 1095 status = "disabled";
1199 }; 1096 };
1200 1097
1201 uart17: serial@88c000 1098 uart17: serial@88c000 {
1202 compatible = 1099 compatible = "qcom,geni-uart";
1203 reg = <0 0x00 1100 reg = <0 0x0088c000 0 0x4000>;
1204 clock-names = 1101 clock-names = "se";
1205 clocks = <&gc 1102 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1206 pinctrl-names 1103 pinctrl-names = "default";
1207 pinctrl-0 = < 1104 pinctrl-0 = <&qup_uart17_default>;
1208 interrupts = 1105 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1209 power-domains !! 1106 power-domains = <&rpmhpd SM8250_CX>;
1210 operating-poi 1107 operating-points-v2 = <&qup_opp_table>;
1211 interconnects <<
1212 <<
1213 interconnect- <<
1214 <<
1215 status = "dis 1108 status = "disabled";
1216 }; 1109 };
1217 1110
1218 i2c18: i2c@890000 { 1111 i2c18: i2c@890000 {
1219 compatible = 1112 compatible = "qcom,geni-i2c";
1220 reg = <0 0x00 1113 reg = <0 0x00890000 0 0x4000>;
1221 clock-names = 1114 clock-names = "se";
1222 clocks = <&gc 1115 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1223 pinctrl-names 1116 pinctrl-names = "default";
1224 pinctrl-0 = < 1117 pinctrl-0 = <&qup_i2c18_default>;
1225 interrupts = 1118 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1226 dmas = <&gpi_ 1119 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1227 <&gpi_ 1120 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1228 dma-names = " 1121 dma-names = "tx", "rx";
1229 power-domains <<
1230 interconnects <<
1231 <<
1232 <<
1233 interconnect- <<
1234 <<
1235 <<
1236 #address-cell 1122 #address-cells = <1>;
1237 #size-cells = 1123 #size-cells = <0>;
1238 status = "dis 1124 status = "disabled";
1239 }; 1125 };
1240 1126
1241 spi18: spi@890000 { 1127 spi18: spi@890000 {
1242 compatible = 1128 compatible = "qcom,geni-spi";
1243 reg = <0 0x00 1129 reg = <0 0x00890000 0 0x4000>;
1244 clock-names = 1130 clock-names = "se";
1245 clocks = <&gc 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1246 interrupts = 1132 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1247 dmas = <&gpi_ 1133 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1248 <&gpi_ 1134 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1249 dma-names = " 1135 dma-names = "tx", "rx";
1250 power-domains !! 1136 power-domains = <&rpmhpd SM8250_CX>;
1251 operating-poi 1137 operating-points-v2 = <&qup_opp_table>;
1252 interconnects <<
1253 <<
1254 <<
1255 interconnect- <<
1256 <<
1257 <<
1258 #address-cell 1138 #address-cells = <1>;
1259 #size-cells = 1139 #size-cells = <0>;
1260 status = "dis 1140 status = "disabled";
1261 }; 1141 };
1262 1142
1263 uart18: serial@890000 1143 uart18: serial@890000 {
1264 compatible = 1144 compatible = "qcom,geni-uart";
1265 reg = <0 0x00 1145 reg = <0 0x00890000 0 0x4000>;
1266 clock-names = 1146 clock-names = "se";
1267 clocks = <&gc 1147 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1268 pinctrl-names 1148 pinctrl-names = "default";
1269 pinctrl-0 = < 1149 pinctrl-0 = <&qup_uart18_default>;
1270 interrupts = 1150 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1271 power-domains !! 1151 power-domains = <&rpmhpd SM8250_CX>;
1272 operating-poi 1152 operating-points-v2 = <&qup_opp_table>;
1273 interconnects <<
1274 <<
1275 interconnect- <<
1276 <<
1277 status = "dis 1153 status = "disabled";
1278 }; 1154 };
1279 1155
1280 i2c19: i2c@894000 { 1156 i2c19: i2c@894000 {
1281 compatible = 1157 compatible = "qcom,geni-i2c";
1282 reg = <0 0x00 1158 reg = <0 0x00894000 0 0x4000>;
1283 clock-names = 1159 clock-names = "se";
1284 clocks = <&gc 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1285 pinctrl-names 1161 pinctrl-names = "default";
1286 pinctrl-0 = < 1162 pinctrl-0 = <&qup_i2c19_default>;
1287 interrupts = 1163 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1288 dmas = <&gpi_ 1164 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1289 <&gpi_ 1165 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1290 dma-names = " 1166 dma-names = "tx", "rx";
1291 power-domains <<
1292 interconnects <<
1293 <<
1294 <<
1295 interconnect- <<
1296 <<
1297 <<
1298 #address-cell 1167 #address-cells = <1>;
1299 #size-cells = 1168 #size-cells = <0>;
1300 status = "dis 1169 status = "disabled";
1301 }; 1170 };
1302 1171
1303 spi19: spi@894000 { 1172 spi19: spi@894000 {
1304 compatible = 1173 compatible = "qcom,geni-spi";
1305 reg = <0 0x00 1174 reg = <0 0x00894000 0 0x4000>;
1306 clock-names = 1175 clock-names = "se";
1307 clocks = <&gc 1176 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1308 interrupts = 1177 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1309 dmas = <&gpi_ 1178 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1310 <&gpi_ 1179 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1311 dma-names = " 1180 dma-names = "tx", "rx";
1312 power-domains !! 1181 power-domains = <&rpmhpd SM8250_CX>;
1313 operating-poi 1182 operating-points-v2 = <&qup_opp_table>;
1314 interconnects <<
1315 <<
1316 <<
1317 interconnect- <<
1318 <<
1319 <<
1320 #address-cell 1183 #address-cells = <1>;
1321 #size-cells = 1184 #size-cells = <0>;
1322 status = "dis 1185 status = "disabled";
1323 }; 1186 };
1324 }; 1187 };
1325 1188
1326 gpi_dma0: dma-controller@9000 1189 gpi_dma0: dma-controller@900000 {
1327 compatible = "qcom,sm 1190 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1328 reg = <0 0x00900000 0 1191 reg = <0 0x00900000 0 0x70000>;
1329 interrupts = <GIC_SPI 1192 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 1193 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
1331 <GIC_SPI 1194 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
1332 <GIC_SPI 1195 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
1333 <GIC_SPI 1196 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 1197 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
1335 <GIC_SPI 1198 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
1336 <GIC_SPI 1199 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
1337 <GIC_SPI 1200 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
1338 <GIC_SPI 1201 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
1339 <GIC_SPI 1202 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 1203 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 1204 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
1342 dma-channels = <15>; 1205 dma-channels = <15>;
1343 dma-channel-mask = <0 1206 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 1207 iommus = <&apps_smmu 0x5b6 0x0>;
1345 #dma-cells = <3>; 1208 #dma-cells = <3>;
1346 status = "disabled"; 1209 status = "disabled";
1347 }; 1210 };
1348 1211
1349 qupv3_id_0: geniqup@9c0000 { 1212 qupv3_id_0: geniqup@9c0000 {
1350 compatible = "qcom,ge 1213 compatible = "qcom,geni-se-qup";
1351 reg = <0x0 0x009c0000 1214 reg = <0x0 0x009c0000 0x0 0x6000>;
1352 clock-names = "m-ahb" 1215 clock-names = "m-ahb", "s-ahb";
1353 clocks = <&gcc GCC_QU 1216 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1354 <&gcc GCC_QU 1217 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1355 #address-cells = <2>; 1218 #address-cells = <2>;
1356 #size-cells = <2>; 1219 #size-cells = <2>;
1357 iommus = <&apps_smmu 1220 iommus = <&apps_smmu 0x5a3 0x0>;
1358 ranges; 1221 ranges;
1359 status = "disabled"; 1222 status = "disabled";
1360 1223
1361 i2c0: i2c@980000 { 1224 i2c0: i2c@980000 {
1362 compatible = 1225 compatible = "qcom,geni-i2c";
1363 reg = <0 0x00 1226 reg = <0 0x00980000 0 0x4000>;
1364 clock-names = 1227 clock-names = "se";
1365 clocks = <&gc 1228 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1366 pinctrl-names 1229 pinctrl-names = "default";
1367 pinctrl-0 = < 1230 pinctrl-0 = <&qup_i2c0_default>;
1368 interrupts = 1231 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1369 dmas = <&gpi_ 1232 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_ 1233 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1371 dma-names = " 1234 dma-names = "tx", "rx";
1372 power-domains <<
1373 interconnects <<
1374 <<
1375 <<
1376 interconnect- <<
1377 <<
1378 <<
1379 #address-cell 1235 #address-cells = <1>;
1380 #size-cells = 1236 #size-cells = <0>;
1381 status = "dis 1237 status = "disabled";
1382 }; 1238 };
1383 1239
1384 spi0: spi@980000 { 1240 spi0: spi@980000 {
1385 compatible = 1241 compatible = "qcom,geni-spi";
1386 reg = <0 0x00 1242 reg = <0 0x00980000 0 0x4000>;
1387 clock-names = 1243 clock-names = "se";
1388 clocks = <&gc 1244 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1389 interrupts = 1245 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1390 dmas = <&gpi_ 1246 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_ 1247 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1392 dma-names = " 1248 dma-names = "tx", "rx";
1393 power-domains !! 1249 power-domains = <&rpmhpd SM8250_CX>;
1394 operating-poi 1250 operating-points-v2 = <&qup_opp_table>;
1395 interconnects <<
1396 <<
1397 <<
1398 interconnect- <<
1399 <<
1400 <<
1401 #address-cell 1251 #address-cells = <1>;
1402 #size-cells = 1252 #size-cells = <0>;
1403 status = "dis 1253 status = "disabled";
1404 }; 1254 };
1405 1255
1406 i2c1: i2c@984000 { 1256 i2c1: i2c@984000 {
1407 compatible = 1257 compatible = "qcom,geni-i2c";
1408 reg = <0 0x00 1258 reg = <0 0x00984000 0 0x4000>;
1409 clock-names = 1259 clock-names = "se";
1410 clocks = <&gc 1260 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1411 pinctrl-names 1261 pinctrl-names = "default";
1412 pinctrl-0 = < 1262 pinctrl-0 = <&qup_i2c1_default>;
1413 interrupts = 1263 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1414 dmas = <&gpi_ 1264 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1415 <&gpi_ 1265 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1416 dma-names = " 1266 dma-names = "tx", "rx";
1417 power-domains <<
1418 interconnects <<
1419 <<
1420 <<
1421 interconnect- <<
1422 <<
1423 <<
1424 #address-cell 1267 #address-cells = <1>;
1425 #size-cells = 1268 #size-cells = <0>;
1426 status = "dis 1269 status = "disabled";
1427 }; 1270 };
1428 1271
1429 spi1: spi@984000 { 1272 spi1: spi@984000 {
1430 compatible = 1273 compatible = "qcom,geni-spi";
1431 reg = <0 0x00 1274 reg = <0 0x00984000 0 0x4000>;
1432 clock-names = 1275 clock-names = "se";
1433 clocks = <&gc 1276 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1434 interrupts = 1277 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1435 dmas = <&gpi_ 1278 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1436 <&gpi_ 1279 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1437 dma-names = " 1280 dma-names = "tx", "rx";
1438 power-domains !! 1281 power-domains = <&rpmhpd SM8250_CX>;
1439 operating-poi 1282 operating-points-v2 = <&qup_opp_table>;
1440 interconnects <<
1441 <<
1442 <<
1443 interconnect- <<
1444 <<
1445 <<
1446 #address-cell 1283 #address-cells = <1>;
1447 #size-cells = 1284 #size-cells = <0>;
1448 status = "dis 1285 status = "disabled";
1449 }; 1286 };
1450 1287
1451 i2c2: i2c@988000 { 1288 i2c2: i2c@988000 {
1452 compatible = 1289 compatible = "qcom,geni-i2c";
1453 reg = <0 0x00 1290 reg = <0 0x00988000 0 0x4000>;
1454 clock-names = 1291 clock-names = "se";
1455 clocks = <&gc 1292 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1456 pinctrl-names 1293 pinctrl-names = "default";
1457 pinctrl-0 = < 1294 pinctrl-0 = <&qup_i2c2_default>;
1458 interrupts = 1295 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1459 dmas = <&gpi_ 1296 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1460 <&gpi_ 1297 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1461 dma-names = " 1298 dma-names = "tx", "rx";
1462 power-domains <<
1463 interconnects <<
1464 <<
1465 <<
1466 interconnect- <<
1467 <<
1468 <<
1469 #address-cell 1299 #address-cells = <1>;
1470 #size-cells = 1300 #size-cells = <0>;
1471 status = "dis 1301 status = "disabled";
1472 }; 1302 };
1473 1303
1474 spi2: spi@988000 { 1304 spi2: spi@988000 {
1475 compatible = 1305 compatible = "qcom,geni-spi";
1476 reg = <0 0x00 1306 reg = <0 0x00988000 0 0x4000>;
1477 clock-names = 1307 clock-names = "se";
1478 clocks = <&gc 1308 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1479 interrupts = 1309 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1480 dmas = <&gpi_ 1310 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1481 <&gpi_ 1311 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1482 dma-names = " 1312 dma-names = "tx", "rx";
1483 power-domains !! 1313 power-domains = <&rpmhpd SM8250_CX>;
1484 operating-poi 1314 operating-points-v2 = <&qup_opp_table>;
1485 interconnects <<
1486 <<
1487 <<
1488 interconnect- <<
1489 <<
1490 <<
1491 #address-cell 1315 #address-cells = <1>;
1492 #size-cells = 1316 #size-cells = <0>;
1493 status = "dis 1317 status = "disabled";
1494 }; 1318 };
1495 1319
1496 uart2: serial@988000 1320 uart2: serial@988000 {
1497 compatible = 1321 compatible = "qcom,geni-debug-uart";
1498 reg = <0 0x00 1322 reg = <0 0x00988000 0 0x4000>;
1499 clock-names = 1323 clock-names = "se";
1500 clocks = <&gc 1324 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1501 pinctrl-names 1325 pinctrl-names = "default";
1502 pinctrl-0 = < 1326 pinctrl-0 = <&qup_uart2_default>;
1503 interrupts = 1327 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1504 power-domains !! 1328 power-domains = <&rpmhpd SM8250_CX>;
1505 operating-poi 1329 operating-points-v2 = <&qup_opp_table>;
1506 interconnects <<
1507 <<
1508 interconnect- <<
1509 <<
1510 status = "dis 1330 status = "disabled";
1511 }; 1331 };
1512 1332
1513 i2c3: i2c@98c000 { 1333 i2c3: i2c@98c000 {
1514 compatible = 1334 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00 1335 reg = <0 0x0098c000 0 0x4000>;
1516 clock-names = 1336 clock-names = "se";
1517 clocks = <&gc 1337 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1518 pinctrl-names 1338 pinctrl-names = "default";
1519 pinctrl-0 = < 1339 pinctrl-0 = <&qup_i2c3_default>;
1520 interrupts = 1340 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1521 dmas = <&gpi_ 1341 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1522 <&gpi_ 1342 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1523 dma-names = " 1343 dma-names = "tx", "rx";
1524 power-domains <<
1525 interconnects <<
1526 <<
1527 <<
1528 interconnect- <<
1529 <<
1530 <<
1531 #address-cell 1344 #address-cells = <1>;
1532 #size-cells = 1345 #size-cells = <0>;
1533 status = "dis 1346 status = "disabled";
1534 }; 1347 };
1535 1348
1536 spi3: spi@98c000 { 1349 spi3: spi@98c000 {
1537 compatible = 1350 compatible = "qcom,geni-spi";
1538 reg = <0 0x00 1351 reg = <0 0x0098c000 0 0x4000>;
1539 clock-names = 1352 clock-names = "se";
1540 clocks = <&gc 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1541 interrupts = 1354 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1542 dmas = <&gpi_ 1355 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1543 <&gpi_ 1356 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1544 dma-names = " 1357 dma-names = "tx", "rx";
1545 power-domains !! 1358 power-domains = <&rpmhpd SM8250_CX>;
1546 operating-poi 1359 operating-points-v2 = <&qup_opp_table>;
1547 interconnects <<
1548 <<
1549 <<
1550 interconnect- <<
1551 <<
1552 <<
1553 #address-cell 1360 #address-cells = <1>;
1554 #size-cells = 1361 #size-cells = <0>;
1555 status = "dis 1362 status = "disabled";
1556 }; 1363 };
1557 1364
1558 i2c4: i2c@990000 { 1365 i2c4: i2c@990000 {
1559 compatible = 1366 compatible = "qcom,geni-i2c";
1560 reg = <0 0x00 1367 reg = <0 0x00990000 0 0x4000>;
1561 clock-names = 1368 clock-names = "se";
1562 clocks = <&gc 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1563 pinctrl-names 1370 pinctrl-names = "default";
1564 pinctrl-0 = < 1371 pinctrl-0 = <&qup_i2c4_default>;
1565 interrupts = 1372 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas = <&gpi_ 1373 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1567 <&gpi_ 1374 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1568 dma-names = " 1375 dma-names = "tx", "rx";
1569 power-domains <<
1570 interconnects <<
1571 <<
1572 <<
1573 interconnect- <<
1574 <<
1575 <<
1576 #address-cell 1376 #address-cells = <1>;
1577 #size-cells = 1377 #size-cells = <0>;
1578 status = "dis 1378 status = "disabled";
1579 }; 1379 };
1580 1380
1581 spi4: spi@990000 { 1381 spi4: spi@990000 {
1582 compatible = 1382 compatible = "qcom,geni-spi";
1583 reg = <0 0x00 1383 reg = <0 0x00990000 0 0x4000>;
1584 clock-names = 1384 clock-names = "se";
1585 clocks = <&gc 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1586 interrupts = 1386 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1587 dmas = <&gpi_ 1387 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1588 <&gpi_ 1388 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1589 dma-names = " 1389 dma-names = "tx", "rx";
1590 power-domains !! 1390 power-domains = <&rpmhpd SM8250_CX>;
1591 operating-poi 1391 operating-points-v2 = <&qup_opp_table>;
1592 interconnects <<
1593 <<
1594 <<
1595 interconnect- <<
1596 <<
1597 <<
1598 #address-cell 1392 #address-cells = <1>;
1599 #size-cells = 1393 #size-cells = <0>;
1600 status = "dis 1394 status = "disabled";
1601 }; 1395 };
1602 1396
1603 i2c5: i2c@994000 { 1397 i2c5: i2c@994000 {
1604 compatible = 1398 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00 1399 reg = <0 0x00994000 0 0x4000>;
1606 clock-names = 1400 clock-names = "se";
1607 clocks = <&gc 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1608 pinctrl-names 1402 pinctrl-names = "default";
1609 pinctrl-0 = < 1403 pinctrl-0 = <&qup_i2c5_default>;
1610 interrupts = 1404 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas = <&gpi_ 1405 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1612 <&gpi_ 1406 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1613 dma-names = " 1407 dma-names = "tx", "rx";
1614 power-domains <<
1615 interconnects <<
1616 <<
1617 <<
1618 interconnect- <<
1619 <<
1620 <<
1621 #address-cell 1408 #address-cells = <1>;
1622 #size-cells = 1409 #size-cells = <0>;
1623 status = "dis 1410 status = "disabled";
1624 }; 1411 };
1625 1412
1626 spi5: spi@994000 { 1413 spi5: spi@994000 {
1627 compatible = 1414 compatible = "qcom,geni-spi";
1628 reg = <0 0x00 1415 reg = <0 0x00994000 0 0x4000>;
1629 clock-names = 1416 clock-names = "se";
1630 clocks = <&gc 1417 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1631 interrupts = 1418 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1632 dmas = <&gpi_ 1419 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1633 <&gpi_ 1420 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1634 dma-names = " 1421 dma-names = "tx", "rx";
1635 power-domains !! 1422 power-domains = <&rpmhpd SM8250_CX>;
1636 operating-poi 1423 operating-points-v2 = <&qup_opp_table>;
1637 interconnects <<
1638 <<
1639 <<
1640 interconnect- <<
1641 <<
1642 <<
1643 #address-cell 1424 #address-cells = <1>;
1644 #size-cells = 1425 #size-cells = <0>;
1645 status = "dis 1426 status = "disabled";
1646 }; 1427 };
1647 1428
1648 i2c6: i2c@998000 { 1429 i2c6: i2c@998000 {
1649 compatible = 1430 compatible = "qcom,geni-i2c";
1650 reg = <0 0x00 1431 reg = <0 0x00998000 0 0x4000>;
1651 clock-names = 1432 clock-names = "se";
1652 clocks = <&gc 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1653 pinctrl-names 1434 pinctrl-names = "default";
1654 pinctrl-0 = < 1435 pinctrl-0 = <&qup_i2c6_default>;
1655 interrupts = 1436 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1656 dmas = <&gpi_ 1437 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1657 <&gpi_ 1438 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1658 dma-names = " 1439 dma-names = "tx", "rx";
1659 power-domains <<
1660 interconnects <<
1661 <<
1662 <<
1663 interconnect- <<
1664 <<
1665 <<
1666 #address-cell 1440 #address-cells = <1>;
1667 #size-cells = 1441 #size-cells = <0>;
1668 status = "dis 1442 status = "disabled";
1669 }; 1443 };
1670 1444
1671 spi6: spi@998000 { 1445 spi6: spi@998000 {
1672 compatible = 1446 compatible = "qcom,geni-spi";
1673 reg = <0 0x00 1447 reg = <0 0x00998000 0 0x4000>;
1674 clock-names = 1448 clock-names = "se";
1675 clocks = <&gc 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1676 interrupts = 1450 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1677 dmas = <&gpi_ 1451 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1678 <&gpi_ 1452 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1679 dma-names = " 1453 dma-names = "tx", "rx";
1680 power-domains !! 1454 power-domains = <&rpmhpd SM8250_CX>;
1681 operating-poi 1455 operating-points-v2 = <&qup_opp_table>;
1682 interconnects <<
1683 <<
1684 <<
1685 interconnect- <<
1686 <<
1687 <<
1688 #address-cell 1456 #address-cells = <1>;
1689 #size-cells = 1457 #size-cells = <0>;
1690 status = "dis 1458 status = "disabled";
1691 }; 1459 };
1692 1460
1693 uart6: serial@998000 1461 uart6: serial@998000 {
1694 compatible = 1462 compatible = "qcom,geni-uart";
1695 reg = <0 0x00 1463 reg = <0 0x00998000 0 0x4000>;
1696 clock-names = 1464 clock-names = "se";
1697 clocks = <&gc 1465 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1698 pinctrl-names 1466 pinctrl-names = "default";
1699 pinctrl-0 = < 1467 pinctrl-0 = <&qup_uart6_default>;
1700 interrupts = 1468 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1701 power-domains !! 1469 power-domains = <&rpmhpd SM8250_CX>;
1702 operating-poi 1470 operating-points-v2 = <&qup_opp_table>;
1703 interconnects <<
1704 <<
1705 interconnect- <<
1706 <<
1707 status = "dis 1471 status = "disabled";
1708 }; 1472 };
1709 1473
1710 i2c7: i2c@99c000 { 1474 i2c7: i2c@99c000 {
1711 compatible = 1475 compatible = "qcom,geni-i2c";
1712 reg = <0 0x00 1476 reg = <0 0x0099c000 0 0x4000>;
1713 clock-names = 1477 clock-names = "se";
1714 clocks = <&gc 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1715 pinctrl-names 1479 pinctrl-names = "default";
1716 pinctrl-0 = < 1480 pinctrl-0 = <&qup_i2c7_default>;
1717 interrupts = 1481 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1718 dmas = <&gpi_ 1482 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1719 <&gpi_ 1483 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1720 dma-names = " 1484 dma-names = "tx", "rx";
1721 power-domains <<
1722 interconnects <<
1723 <<
1724 <<
1725 interconnect- <<
1726 <<
1727 <<
1728 #address-cell 1485 #address-cells = <1>;
1729 #size-cells = 1486 #size-cells = <0>;
1730 status = "dis 1487 status = "disabled";
1731 }; 1488 };
1732 1489
1733 spi7: spi@99c000 { 1490 spi7: spi@99c000 {
1734 compatible = 1491 compatible = "qcom,geni-spi";
1735 reg = <0 0x00 1492 reg = <0 0x0099c000 0 0x4000>;
1736 clock-names = 1493 clock-names = "se";
1737 clocks = <&gc 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1738 interrupts = 1495 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1739 dmas = <&gpi_ 1496 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1740 <&gpi_ 1497 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1741 dma-names = " 1498 dma-names = "tx", "rx";
1742 power-domains !! 1499 power-domains = <&rpmhpd SM8250_CX>;
1743 operating-poi 1500 operating-points-v2 = <&qup_opp_table>;
1744 interconnects <<
1745 <<
1746 <<
1747 interconnect- <<
1748 <<
1749 <<
1750 #address-cell 1501 #address-cells = <1>;
1751 #size-cells = 1502 #size-cells = <0>;
1752 status = "dis 1503 status = "disabled";
1753 }; 1504 };
1754 }; 1505 };
1755 1506
1756 gpi_dma1: dma-controller@a000 1507 gpi_dma1: dma-controller@a00000 {
1757 compatible = "qcom,sm 1508 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1758 reg = <0 0x00a00000 0 1509 reg = <0 0x00a00000 0 0x70000>;
1759 interrupts = <GIC_SPI 1510 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 1511 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 1512 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 1513 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 1514 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1515 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 1516 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 1517 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 1518 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 1519 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
1769 dma-channels = <10>; 1520 dma-channels = <10>;
1770 dma-channel-mask = <0 1521 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 1522 iommus = <&apps_smmu 0x56 0x0>;
1772 #dma-cells = <3>; 1523 #dma-cells = <3>;
1773 status = "disabled"; 1524 status = "disabled";
1774 }; 1525 };
1775 1526
1776 qupv3_id_1: geniqup@ac0000 { 1527 qupv3_id_1: geniqup@ac0000 {
1777 compatible = "qcom,ge 1528 compatible = "qcom,geni-se-qup";
1778 reg = <0x0 0x00ac0000 1529 reg = <0x0 0x00ac0000 0x0 0x6000>;
1779 clock-names = "m-ahb" 1530 clock-names = "m-ahb", "s-ahb";
1780 clocks = <&gcc GCC_QU 1531 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1781 <&gcc GCC_QU 1532 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1782 #address-cells = <2>; 1533 #address-cells = <2>;
1783 #size-cells = <2>; 1534 #size-cells = <2>;
1784 iommus = <&apps_smmu 1535 iommus = <&apps_smmu 0x43 0x0>;
1785 ranges; 1536 ranges;
1786 status = "disabled"; 1537 status = "disabled";
1787 1538
1788 i2c8: i2c@a80000 { 1539 i2c8: i2c@a80000 {
1789 compatible = 1540 compatible = "qcom,geni-i2c";
1790 reg = <0 0x00 1541 reg = <0 0x00a80000 0 0x4000>;
1791 clock-names = 1542 clock-names = "se";
1792 clocks = <&gc 1543 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1793 pinctrl-names 1544 pinctrl-names = "default";
1794 pinctrl-0 = < 1545 pinctrl-0 = <&qup_i2c8_default>;
1795 interrupts = 1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1796 dmas = <&gpi_ 1547 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_ 1548 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1798 dma-names = " 1549 dma-names = "tx", "rx";
1799 power-domains <<
1800 interconnects <<
1801 <<
1802 <<
1803 interconnect- <<
1804 <<
1805 <<
1806 #address-cell 1550 #address-cells = <1>;
1807 #size-cells = 1551 #size-cells = <0>;
1808 status = "dis 1552 status = "disabled";
1809 }; 1553 };
1810 1554
1811 spi8: spi@a80000 { 1555 spi8: spi@a80000 {
1812 compatible = 1556 compatible = "qcom,geni-spi";
1813 reg = <0 0x00 1557 reg = <0 0x00a80000 0 0x4000>;
1814 clock-names = 1558 clock-names = "se";
1815 clocks = <&gc 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1816 interrupts = 1560 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1817 dmas = <&gpi_ 1561 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_ 1562 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1819 dma-names = " 1563 dma-names = "tx", "rx";
1820 power-domains !! 1564 power-domains = <&rpmhpd SM8250_CX>;
1821 operating-poi 1565 operating-points-v2 = <&qup_opp_table>;
1822 interconnects <<
1823 <<
1824 <<
1825 interconnect- <<
1826 <<
1827 <<
1828 #address-cell 1566 #address-cells = <1>;
1829 #size-cells = 1567 #size-cells = <0>;
1830 status = "dis 1568 status = "disabled";
1831 }; 1569 };
1832 1570
1833 i2c9: i2c@a84000 { 1571 i2c9: i2c@a84000 {
1834 compatible = 1572 compatible = "qcom,geni-i2c";
1835 reg = <0 0x00 1573 reg = <0 0x00a84000 0 0x4000>;
1836 clock-names = 1574 clock-names = "se";
1837 clocks = <&gc 1575 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1838 pinctrl-names 1576 pinctrl-names = "default";
1839 pinctrl-0 = < 1577 pinctrl-0 = <&qup_i2c9_default>;
1840 interrupts = 1578 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1841 dmas = <&gpi_ 1579 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 <&gpi_ 1580 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1843 dma-names = " 1581 dma-names = "tx", "rx";
1844 power-domains <<
1845 interconnects <<
1846 <<
1847 <<
1848 interconnect- <<
1849 <<
1850 <<
1851 #address-cell 1582 #address-cells = <1>;
1852 #size-cells = 1583 #size-cells = <0>;
1853 status = "dis 1584 status = "disabled";
1854 }; 1585 };
1855 1586
1856 spi9: spi@a84000 { 1587 spi9: spi@a84000 {
1857 compatible = 1588 compatible = "qcom,geni-spi";
1858 reg = <0 0x00 1589 reg = <0 0x00a84000 0 0x4000>;
1859 clock-names = 1590 clock-names = "se";
1860 clocks = <&gc 1591 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1861 interrupts = 1592 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1862 dmas = <&gpi_ 1593 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1863 <&gpi_ 1594 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1864 dma-names = " 1595 dma-names = "tx", "rx";
1865 power-domains !! 1596 power-domains = <&rpmhpd SM8250_CX>;
1866 operating-poi 1597 operating-points-v2 = <&qup_opp_table>;
1867 interconnects <<
1868 <<
1869 <<
1870 interconnect- <<
1871 <<
1872 <<
1873 #address-cell 1598 #address-cells = <1>;
1874 #size-cells = 1599 #size-cells = <0>;
1875 status = "dis 1600 status = "disabled";
1876 }; 1601 };
1877 1602
1878 i2c10: i2c@a88000 { 1603 i2c10: i2c@a88000 {
1879 compatible = 1604 compatible = "qcom,geni-i2c";
1880 reg = <0 0x00 1605 reg = <0 0x00a88000 0 0x4000>;
1881 clock-names = 1606 clock-names = "se";
1882 clocks = <&gc 1607 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1883 pinctrl-names 1608 pinctrl-names = "default";
1884 pinctrl-0 = < 1609 pinctrl-0 = <&qup_i2c10_default>;
1885 interrupts = 1610 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1886 dmas = <&gpi_ 1611 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1887 <&gpi_ 1612 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1888 dma-names = " 1613 dma-names = "tx", "rx";
1889 power-domains <<
1890 interconnects <<
1891 <<
1892 <<
1893 interconnect- <<
1894 <<
1895 <<
1896 #address-cell 1614 #address-cells = <1>;
1897 #size-cells = 1615 #size-cells = <0>;
1898 status = "dis 1616 status = "disabled";
1899 }; 1617 };
1900 1618
1901 spi10: spi@a88000 { 1619 spi10: spi@a88000 {
1902 compatible = 1620 compatible = "qcom,geni-spi";
1903 reg = <0 0x00 1621 reg = <0 0x00a88000 0 0x4000>;
1904 clock-names = 1622 clock-names = "se";
1905 clocks = <&gc 1623 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1906 interrupts = 1624 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1907 dmas = <&gpi_ 1625 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1908 <&gpi_ 1626 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1909 dma-names = " 1627 dma-names = "tx", "rx";
1910 power-domains !! 1628 power-domains = <&rpmhpd SM8250_CX>;
1911 operating-poi 1629 operating-points-v2 = <&qup_opp_table>;
1912 interconnects <<
1913 <<
1914 <<
1915 interconnect- <<
1916 <<
1917 <<
1918 #address-cell 1630 #address-cells = <1>;
1919 #size-cells = 1631 #size-cells = <0>;
1920 status = "dis 1632 status = "disabled";
1921 }; 1633 };
1922 1634
1923 i2c11: i2c@a8c000 { 1635 i2c11: i2c@a8c000 {
1924 compatible = 1636 compatible = "qcom,geni-i2c";
1925 reg = <0 0x00 1637 reg = <0 0x00a8c000 0 0x4000>;
1926 clock-names = 1638 clock-names = "se";
1927 clocks = <&gc 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1928 pinctrl-names 1640 pinctrl-names = "default";
1929 pinctrl-0 = < 1641 pinctrl-0 = <&qup_i2c11_default>;
1930 interrupts = 1642 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1931 dmas = <&gpi_ 1643 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1932 <&gpi_ 1644 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1933 dma-names = " 1645 dma-names = "tx", "rx";
1934 power-domains <<
1935 interconnects <<
1936 <<
1937 <<
1938 interconnect- <<
1939 <<
1940 <<
1941 #address-cell 1646 #address-cells = <1>;
1942 #size-cells = 1647 #size-cells = <0>;
1943 status = "dis 1648 status = "disabled";
1944 }; 1649 };
1945 1650
1946 spi11: spi@a8c000 { 1651 spi11: spi@a8c000 {
1947 compatible = 1652 compatible = "qcom,geni-spi";
1948 reg = <0 0x00 1653 reg = <0 0x00a8c000 0 0x4000>;
1949 clock-names = 1654 clock-names = "se";
1950 clocks = <&gc 1655 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1951 interrupts = 1656 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1952 dmas = <&gpi_ 1657 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1953 <&gpi_ 1658 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1954 dma-names = " 1659 dma-names = "tx", "rx";
1955 power-domains !! 1660 power-domains = <&rpmhpd SM8250_CX>;
1956 operating-poi 1661 operating-points-v2 = <&qup_opp_table>;
1957 interconnects <<
1958 <<
1959 <<
1960 interconnect- <<
1961 <<
1962 <<
1963 #address-cell 1662 #address-cells = <1>;
1964 #size-cells = 1663 #size-cells = <0>;
1965 status = "dis 1664 status = "disabled";
1966 }; 1665 };
1967 1666
1968 i2c12: i2c@a90000 { 1667 i2c12: i2c@a90000 {
1969 compatible = 1668 compatible = "qcom,geni-i2c";
1970 reg = <0 0x00 1669 reg = <0 0x00a90000 0 0x4000>;
1971 clock-names = 1670 clock-names = "se";
1972 clocks = <&gc 1671 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1973 pinctrl-names 1672 pinctrl-names = "default";
1974 pinctrl-0 = < 1673 pinctrl-0 = <&qup_i2c12_default>;
1975 interrupts = 1674 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1976 dmas = <&gpi_ 1675 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1977 <&gpi_ 1676 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1978 dma-names = " 1677 dma-names = "tx", "rx";
1979 power-domains <<
1980 interconnects <<
1981 <<
1982 <<
1983 interconnect- <<
1984 <<
1985 <<
1986 #address-cell 1678 #address-cells = <1>;
1987 #size-cells = 1679 #size-cells = <0>;
1988 status = "dis 1680 status = "disabled";
1989 }; 1681 };
1990 1682
1991 spi12: spi@a90000 { 1683 spi12: spi@a90000 {
1992 compatible = 1684 compatible = "qcom,geni-spi";
1993 reg = <0 0x00 1685 reg = <0 0x00a90000 0 0x4000>;
1994 clock-names = 1686 clock-names = "se";
1995 clocks = <&gc 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1996 interrupts = 1688 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1997 dmas = <&gpi_ 1689 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1998 <&gpi_ 1690 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1999 dma-names = " 1691 dma-names = "tx", "rx";
2000 power-domains !! 1692 power-domains = <&rpmhpd SM8250_CX>;
2001 operating-poi 1693 operating-points-v2 = <&qup_opp_table>;
2002 interconnects <<
2003 <<
2004 <<
2005 interconnect- <<
2006 <<
2007 <<
2008 #address-cell 1694 #address-cells = <1>;
2009 #size-cells = 1695 #size-cells = <0>;
2010 status = "dis 1696 status = "disabled";
2011 }; 1697 };
2012 1698
2013 uart12: serial@a90000 1699 uart12: serial@a90000 {
2014 compatible = 1700 compatible = "qcom,geni-debug-uart";
2015 reg = <0x0 0x 1701 reg = <0x0 0x00a90000 0x0 0x4000>;
2016 clock-names = 1702 clock-names = "se";
2017 clocks = <&gc 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
2018 pinctrl-names 1704 pinctrl-names = "default";
2019 pinctrl-0 = < 1705 pinctrl-0 = <&qup_uart12_default>;
2020 interrupts = 1706 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
2021 power-domains !! 1707 power-domains = <&rpmhpd SM8250_CX>;
2022 operating-poi 1708 operating-points-v2 = <&qup_opp_table>;
2023 interconnects <<
2024 <<
2025 interconnect- <<
2026 <<
2027 status = "dis 1709 status = "disabled";
2028 }; 1710 };
2029 1711
2030 i2c13: i2c@a94000 { 1712 i2c13: i2c@a94000 {
2031 compatible = 1713 compatible = "qcom,geni-i2c";
2032 reg = <0 0x00 1714 reg = <0 0x00a94000 0 0x4000>;
2033 clock-names = 1715 clock-names = "se";
2034 clocks = <&gc 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2035 pinctrl-names 1717 pinctrl-names = "default";
2036 pinctrl-0 = < 1718 pinctrl-0 = <&qup_i2c13_default>;
2037 interrupts = 1719 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2038 dmas = <&gpi_ 1720 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2039 <&gpi_ 1721 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
2040 dma-names = " 1722 dma-names = "tx", "rx";
2041 power-domains <<
2042 interconnects <<
2043 <<
2044 <<
2045 interconnect- <<
2046 <<
2047 <<
2048 #address-cell 1723 #address-cells = <1>;
2049 #size-cells = 1724 #size-cells = <0>;
2050 status = "dis 1725 status = "disabled";
2051 }; 1726 };
2052 1727
2053 spi13: spi@a94000 { 1728 spi13: spi@a94000 {
2054 compatible = 1729 compatible = "qcom,geni-spi";
2055 reg = <0 0x00 1730 reg = <0 0x00a94000 0 0x4000>;
2056 clock-names = 1731 clock-names = "se";
2057 clocks = <&gc 1732 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
2058 interrupts = 1733 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2059 dmas = <&gpi_ 1734 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2060 <&gpi_ 1735 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2061 dma-names = " 1736 dma-names = "tx", "rx";
2062 power-domains !! 1737 power-domains = <&rpmhpd SM8250_CX>;
2063 operating-poi 1738 operating-points-v2 = <&qup_opp_table>;
2064 interconnects <<
2065 <<
2066 <<
2067 interconnect- <<
2068 <<
2069 <<
2070 #address-cell 1739 #address-cells = <1>;
2071 #size-cells = 1740 #size-cells = <0>;
2072 status = "dis 1741 status = "disabled";
2073 }; 1742 };
2074 }; 1743 };
2075 1744
2076 config_noc: interconnect@1500 1745 config_noc: interconnect@1500000 {
2077 compatible = "qcom,sm 1746 compatible = "qcom,sm8250-config-noc";
2078 reg = <0 0x01500000 0 1747 reg = <0 0x01500000 0 0xa580>;
2079 #interconnect-cells = !! 1748 #interconnect-cells = <1>;
2080 qcom,bcm-voters = <&a 1749 qcom,bcm-voters = <&apps_bcm_voter>;
2081 }; 1750 };
2082 1751
2083 system_noc: interconnect@1620 1752 system_noc: interconnect@1620000 {
2084 compatible = "qcom,sm 1753 compatible = "qcom,sm8250-system-noc";
2085 reg = <0 0x01620000 0 1754 reg = <0 0x01620000 0 0x1c200>;
2086 #interconnect-cells = !! 1755 #interconnect-cells = <1>;
2087 qcom,bcm-voters = <&a 1756 qcom,bcm-voters = <&apps_bcm_voter>;
2088 }; 1757 };
2089 1758
2090 mc_virt: interconnect@163d000 1759 mc_virt: interconnect@163d000 {
2091 compatible = "qcom,sm 1760 compatible = "qcom,sm8250-mc-virt";
2092 reg = <0 0x0163d000 0 1761 reg = <0 0x0163d000 0 0x1000>;
2093 #interconnect-cells = !! 1762 #interconnect-cells = <1>;
2094 qcom,bcm-voters = <&a 1763 qcom,bcm-voters = <&apps_bcm_voter>;
2095 }; 1764 };
2096 1765
2097 aggre1_noc: interconnect@16e0 1766 aggre1_noc: interconnect@16e0000 {
2098 compatible = "qcom,sm 1767 compatible = "qcom,sm8250-aggre1-noc";
2099 reg = <0 0x016e0000 0 1768 reg = <0 0x016e0000 0 0x1f180>;
2100 #interconnect-cells = !! 1769 #interconnect-cells = <1>;
2101 qcom,bcm-voters = <&a 1770 qcom,bcm-voters = <&apps_bcm_voter>;
2102 }; 1771 };
2103 1772
2104 aggre2_noc: interconnect@1700 1773 aggre2_noc: interconnect@1700000 {
2105 compatible = "qcom,sm 1774 compatible = "qcom,sm8250-aggre2-noc";
2106 reg = <0 0x01700000 0 1775 reg = <0 0x01700000 0 0x33000>;
2107 #interconnect-cells = !! 1776 #interconnect-cells = <1>;
2108 qcom,bcm-voters = <&a 1777 qcom,bcm-voters = <&apps_bcm_voter>;
2109 }; 1778 };
2110 1779
2111 compute_noc: interconnect@173 1780 compute_noc: interconnect@1733000 {
2112 compatible = "qcom,sm 1781 compatible = "qcom,sm8250-compute-noc";
2113 reg = <0 0x01733000 0 1782 reg = <0 0x01733000 0 0xa180>;
2114 #interconnect-cells = !! 1783 #interconnect-cells = <1>;
2115 qcom,bcm-voters = <&a 1784 qcom,bcm-voters = <&apps_bcm_voter>;
2116 }; 1785 };
2117 1786
2118 mmss_noc: interconnect@174000 1787 mmss_noc: interconnect@1740000 {
2119 compatible = "qcom,sm 1788 compatible = "qcom,sm8250-mmss-noc";
2120 reg = <0 0x01740000 0 1789 reg = <0 0x01740000 0 0x1f080>;
2121 #interconnect-cells = !! 1790 #interconnect-cells = <1>;
2122 qcom,bcm-voters = <&a 1791 qcom,bcm-voters = <&apps_bcm_voter>;
2123 }; 1792 };
2124 1793
2125 pcie0: pcie@1c00000 { !! 1794 pcie0: pci@1c00000 {
2126 compatible = "qcom,pc 1795 compatible = "qcom,pcie-sm8250";
2127 reg = <0 0x01c00000 0 1796 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 1797 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 1798 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 1799 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 !! 1800 <0 0x60100000 0 0x100000>;
2132 <0 0x01c03000 0 !! 1801 reg-names = "parf", "dbi", "elbi", "atu", "config";
2133 reg-names = "parf", " <<
2134 device_type = "pci"; 1802 device_type = "pci";
2135 linux,pci-domain = <0 1803 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xf 1804 bus-range = <0x00 0xff>;
2137 num-lanes = <1>; 1805 num-lanes = <1>;
2138 1806
2139 #address-cells = <3>; 1807 #address-cells = <3>;
2140 #size-cells = <2>; 1808 #size-cells = <2>;
2141 1809
2142 ranges = <0x01000000 1810 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 1811 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2144 1812
2145 interrupts = <GIC_SPI 1813 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2146 <GIC_SPI 1814 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 1815 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 1816 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 1817 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 1818 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 1819 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 1820 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2153 interrupt-names = "ms !! 1821 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2154 "ms !! 1822 "msi4", "msi5", "msi6", "msi7";
2155 "ms <<
2156 "ms <<
2157 "ms <<
2158 "ms <<
2159 "ms <<
2160 "ms <<
2161 #interrupt-cells = <1 1823 #interrupt-cells = <1>;
2162 interrupt-map-mask = 1824 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 1825 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 1826 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 1827 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 1828 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2167 1829
2168 clocks = <&gcc GCC_PC 1830 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
2169 <&gcc GCC_PC 1831 <&gcc GCC_PCIE_0_AUX_CLK>,
2170 <&gcc GCC_PC 1832 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2171 <&gcc GCC_PC 1833 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2172 <&gcc GCC_PC 1834 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2173 <&gcc GCC_PC 1835 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
2174 <&gcc GCC_AG 1836 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2175 <&gcc GCC_DD 1837 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2176 clock-names = "pipe", 1838 clock-names = "pipe",
2177 "aux", 1839 "aux",
2178 "cfg", 1840 "cfg",
2179 "bus_ma 1841 "bus_master",
2180 "bus_sl 1842 "bus_slave",
2181 "slave_ 1843 "slave_q2a",
2182 "tbu", 1844 "tbu",
2183 "ddrss_ 1845 "ddrss_sf_tbu";
2184 1846
>> 1847 iommus = <&apps_smmu 0x1c00 0x7f>;
2185 iommu-map = <0x0 &a 1848 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &a 1849 <0x100 &apps_smmu 0x1c01 0x1>;
2187 1850
2188 resets = <&gcc GCC_PC 1851 resets = <&gcc GCC_PCIE_0_BCR>;
2189 reset-names = "pci"; 1852 reset-names = "pci";
2190 1853
2191 power-domains = <&gcc 1854 power-domains = <&gcc PCIE_0_GDSC>;
2192 1855
2193 phys = <&pcie0_phy>; !! 1856 phys = <&pcie0_lane>;
2194 phy-names = "pciephy" 1857 phy-names = "pciephy";
2195 1858
2196 perst-gpios = <&tlmm 1859 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
2197 wake-gpios = <&tlmm 8 1860 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
2198 1861
2199 pinctrl-names = "defa 1862 pinctrl-names = "default";
2200 pinctrl-0 = <&pcie0_d 1863 pinctrl-0 = <&pcie0_default_state>;
2201 dma-coherent; <<
2202 1864
2203 status = "disabled"; 1865 status = "disabled";
2204 <<
2205 pcieport0: pcie@0 { <<
2206 device_type = <<
2207 reg = <0x0 0x <<
2208 bus-range = < <<
2209 <<
2210 #address-cell <<
2211 #size-cells = <<
2212 ranges; <<
2213 }; <<
2214 }; 1866 };
2215 1867
2216 pcie0_phy: phy@1c06000 { 1868 pcie0_phy: phy@1c06000 {
2217 compatible = "qcom,sm 1869 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
2218 reg = <0 0x01c06000 0 !! 1870 reg = <0 0x01c06000 0 0x1c0>;
2219 !! 1871 #address-cells = <2>;
>> 1872 #size-cells = <2>;
>> 1873 ranges;
2220 clocks = <&gcc GCC_PC 1874 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2221 <&gcc GCC_PC 1875 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2222 <&gcc GCC_PC 1876 <&gcc GCC_PCIE_WIFI_CLKREF_EN>,
2223 <&gcc GCC_PC !! 1877 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2224 <&gcc GCC_PC !! 1878 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2225 clock-names = "aux", <<
2226 "cfg_ah <<
2227 "ref", <<
2228 "refgen <<
2229 "pipe"; <<
2230 <<
2231 clock-output-names = <<
2232 #clock-cells = <0>; <<
2233 <<
2234 #phy-cells = <0>; <<
2235 1879
2236 resets = <&gcc GCC_PC 1880 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2237 reset-names = "phy"; 1881 reset-names = "phy";
2238 1882
2239 assigned-clocks = <&g 1883 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
2240 assigned-clock-rates 1884 assigned-clock-rates = <100000000>;
2241 1885
2242 status = "disabled"; 1886 status = "disabled";
>> 1887
>> 1888 pcie0_lane: phy@1c06200 {
>> 1889 reg = <0 0x1c06200 0 0x170>, /* tx */
>> 1890 <0 0x1c06400 0 0x200>, /* rx */
>> 1891 <0 0x1c06800 0 0x1f0>, /* pcs */
>> 1892 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
>> 1893 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> 1894 clock-names = "pipe0";
>> 1895
>> 1896 #phy-cells = <0>;
>> 1897
>> 1898 #clock-cells = <0>;
>> 1899 clock-output-names = "pcie_0_pipe_clk";
>> 1900 };
2243 }; 1901 };
2244 1902
2245 pcie1: pcie@1c08000 { !! 1903 pcie1: pci@1c08000 {
2246 compatible = "qcom,pc 1904 compatible = "qcom,pcie-sm8250";
2247 reg = <0 0x01c08000 0 1905 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 1906 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 1907 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 1908 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 !! 1909 <0 0x40100000 0 0x100000>;
2252 <0 0x01c0b000 0 !! 1910 reg-names = "parf", "dbi", "elbi", "atu", "config";
2253 reg-names = "parf", " <<
2254 device_type = "pci"; 1911 device_type = "pci";
2255 linux,pci-domain = <1 1912 linux,pci-domain = <1>;
2256 bus-range = <0x00 0xf 1913 bus-range = <0x00 0xff>;
2257 num-lanes = <2>; 1914 num-lanes = <2>;
2258 1915
2259 #address-cells = <3>; 1916 #address-cells = <3>;
2260 #size-cells = <2>; 1917 #size-cells = <2>;
2261 1918
2262 ranges = <0x01000000 1919 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 1920 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2264 1921
2265 interrupts = <GIC_SPI !! 1922 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2266 <GIC_SPI !! 1923 interrupt-names = "msi";
2267 <GIC_SPI <<
2268 <GIC_SPI <<
2269 <GIC_SPI <<
2270 <GIC_SPI <<
2271 <GIC_SPI <<
2272 <GIC_SPI <<
2273 interrupt-names = "ms <<
2274 "ms <<
2275 "ms <<
2276 "ms <<
2277 "ms <<
2278 "ms <<
2279 "ms <<
2280 "ms <<
2281 #interrupt-cells = <1 1924 #interrupt-cells = <1>;
2282 interrupt-map-mask = 1925 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 1926 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 1927 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 1928 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 1929 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2287 1930
2288 clocks = <&gcc GCC_PC 1931 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2289 <&gcc GCC_PC 1932 <&gcc GCC_PCIE_1_AUX_CLK>,
2290 <&gcc GCC_PC 1933 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2291 <&gcc GCC_PC 1934 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2292 <&gcc GCC_PC 1935 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2293 <&gcc GCC_PC 1936 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2294 <&gcc GCC_PC 1937 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2295 <&gcc GCC_AG 1938 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2296 <&gcc GCC_DD 1939 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2297 clock-names = "pipe", 1940 clock-names = "pipe",
2298 "aux", 1941 "aux",
2299 "cfg", 1942 "cfg",
2300 "bus_ma 1943 "bus_master",
2301 "bus_sl 1944 "bus_slave",
2302 "slave_ 1945 "slave_q2a",
2303 "ref", 1946 "ref",
2304 "tbu", 1947 "tbu",
2305 "ddrss_ 1948 "ddrss_sf_tbu";
2306 1949
2307 assigned-clocks = <&g 1950 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2308 assigned-clock-rates 1951 assigned-clock-rates = <19200000>;
2309 1952
>> 1953 iommus = <&apps_smmu 0x1c80 0x7f>;
2310 iommu-map = <0x0 &a 1954 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &a 1955 <0x100 &apps_smmu 0x1c81 0x1>;
2312 1956
2313 resets = <&gcc GCC_PC 1957 resets = <&gcc GCC_PCIE_1_BCR>;
2314 reset-names = "pci"; 1958 reset-names = "pci";
2315 1959
2316 power-domains = <&gcc 1960 power-domains = <&gcc PCIE_1_GDSC>;
2317 1961
2318 phys = <&pcie1_phy>; !! 1962 phys = <&pcie1_lane>;
2319 phy-names = "pciephy" 1963 phy-names = "pciephy";
2320 1964
2321 perst-gpios = <&tlmm 1965 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2322 wake-gpios = <&tlmm 8 1966 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2323 1967
2324 pinctrl-names = "defa 1968 pinctrl-names = "default";
2325 pinctrl-0 = <&pcie1_d 1969 pinctrl-0 = <&pcie1_default_state>;
2326 dma-coherent; <<
2327 1970
2328 status = "disabled"; 1971 status = "disabled";
2329 <<
2330 pcie@0 { <<
2331 device_type = <<
2332 reg = <0x0 0x <<
2333 bus-range = < <<
2334 <<
2335 #address-cell <<
2336 #size-cells = <<
2337 ranges; <<
2338 }; <<
2339 }; 1972 };
2340 1973
2341 pcie1_phy: phy@1c0e000 { 1974 pcie1_phy: phy@1c0e000 {
2342 compatible = "qcom,sm 1975 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2343 reg = <0 0x01c0e000 0 !! 1976 reg = <0 0x01c0e000 0 0x1c0>;
2344 !! 1977 #address-cells = <2>;
>> 1978 #size-cells = <2>;
>> 1979 ranges;
2345 clocks = <&gcc GCC_PC 1980 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2346 <&gcc GCC_PC 1981 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2347 <&gcc GCC_PC 1982 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
2348 <&gcc GCC_PC !! 1983 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2349 <&gcc GCC_PC !! 1984 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2350 clock-names = "aux", <<
2351 "cfg_ah <<
2352 "ref", <<
2353 "refgen <<
2354 "pipe"; <<
2355 <<
2356 clock-output-names = <<
2357 #clock-cells = <0>; <<
2358 <<
2359 #phy-cells = <0>; <<
2360 1985
2361 resets = <&gcc GCC_PC 1986 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2362 reset-names = "phy"; 1987 reset-names = "phy";
2363 1988
2364 assigned-clocks = <&g 1989 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2365 assigned-clock-rates 1990 assigned-clock-rates = <100000000>;
2366 1991
2367 status = "disabled"; 1992 status = "disabled";
>> 1993
>> 1994 pcie1_lane: phy@1c0e200 {
>> 1995 reg = <0 0x1c0e200 0 0x170>, /* tx0 */
>> 1996 <0 0x1c0e400 0 0x200>, /* rx0 */
>> 1997 <0 0x1c0ea00 0 0x1f0>, /* pcs */
>> 1998 <0 0x1c0e600 0 0x170>, /* tx1 */
>> 1999 <0 0x1c0e800 0 0x200>, /* rx1 */
>> 2000 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2001 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
>> 2002 clock-names = "pipe0";
>> 2003
>> 2004 #phy-cells = <0>;
>> 2005
>> 2006 #clock-cells = <0>;
>> 2007 clock-output-names = "pcie_1_pipe_clk";
>> 2008 };
2368 }; 2009 };
2369 2010
2370 pcie2: pcie@1c10000 { !! 2011 pcie2: pci@1c10000 {
2371 compatible = "qcom,pc 2012 compatible = "qcom,pcie-sm8250";
2372 reg = <0 0x01c10000 0 2013 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 2014 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 2015 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 2016 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 !! 2017 <0 0x64100000 0 0x100000>;
2377 <0 0x01c13000 0 !! 2018 reg-names = "parf", "dbi", "elbi", "atu", "config";
2378 reg-names = "parf", " <<
2379 device_type = "pci"; 2019 device_type = "pci";
2380 linux,pci-domain = <2 2020 linux,pci-domain = <2>;
2381 bus-range = <0x00 0xf 2021 bus-range = <0x00 0xff>;
2382 num-lanes = <2>; 2022 num-lanes = <2>;
2383 2023
2384 #address-cells = <3>; 2024 #address-cells = <3>;
2385 #size-cells = <2>; 2025 #size-cells = <2>;
2386 2026
2387 ranges = <0x01000000 2027 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 2028 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2389 2029
2390 interrupts = <GIC_SPI !! 2030 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2391 <GIC_SPI !! 2031 interrupt-names = "msi";
2392 <GIC_SPI <<
2393 <GIC_SPI <<
2394 <GIC_SPI <<
2395 <GIC_SPI <<
2396 <GIC_SPI <<
2397 <GIC_SPI <<
2398 interrupt-names = "ms <<
2399 "ms <<
2400 "ms <<
2401 "ms <<
2402 "ms <<
2403 "ms <<
2404 "ms <<
2405 "ms <<
2406 #interrupt-cells = <1 2032 #interrupt-cells = <1>;
2407 interrupt-map-mask = 2033 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 2034 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 2035 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 2036 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 2037 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2412 2038
2413 clocks = <&gcc GCC_PC 2039 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2414 <&gcc GCC_PC 2040 <&gcc GCC_PCIE_2_AUX_CLK>,
2415 <&gcc GCC_PC 2041 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2416 <&gcc GCC_PC 2042 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2417 <&gcc GCC_PC 2043 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2418 <&gcc GCC_PC 2044 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2419 <&gcc GCC_PC 2045 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2420 <&gcc GCC_AG 2046 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2421 <&gcc GCC_DD 2047 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
2422 clock-names = "pipe", 2048 clock-names = "pipe",
2423 "aux", 2049 "aux",
2424 "cfg", 2050 "cfg",
2425 "bus_ma 2051 "bus_master",
2426 "bus_sl 2052 "bus_slave",
2427 "slave_ 2053 "slave_q2a",
2428 "ref", 2054 "ref",
2429 "tbu", 2055 "tbu",
2430 "ddrss_ 2056 "ddrss_sf_tbu";
2431 2057
2432 assigned-clocks = <&g 2058 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2433 assigned-clock-rates 2059 assigned-clock-rates = <19200000>;
2434 2060
>> 2061 iommus = <&apps_smmu 0x1d00 0x7f>;
2435 iommu-map = <0x0 &a 2062 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &a 2063 <0x100 &apps_smmu 0x1d01 0x1>;
2437 2064
2438 resets = <&gcc GCC_PC 2065 resets = <&gcc GCC_PCIE_2_BCR>;
2439 reset-names = "pci"; 2066 reset-names = "pci";
2440 2067
2441 power-domains = <&gcc 2068 power-domains = <&gcc PCIE_2_GDSC>;
2442 2069
2443 phys = <&pcie2_phy>; !! 2070 phys = <&pcie2_lane>;
2444 phy-names = "pciephy" 2071 phy-names = "pciephy";
2445 2072
2446 perst-gpios = <&tlmm 2073 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2447 wake-gpios = <&tlmm 8 2074 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2448 2075
2449 pinctrl-names = "defa 2076 pinctrl-names = "default";
2450 pinctrl-0 = <&pcie2_d 2077 pinctrl-0 = <&pcie2_default_state>;
2451 dma-coherent; <<
2452 2078
2453 status = "disabled"; 2079 status = "disabled";
2454 <<
2455 pcie@0 { <<
2456 device_type = <<
2457 reg = <0x0 0x <<
2458 bus-range = < <<
2459 <<
2460 #address-cell <<
2461 #size-cells = <<
2462 ranges; <<
2463 }; <<
2464 }; 2080 };
2465 2081
2466 pcie2_phy: phy@1c16000 { 2082 pcie2_phy: phy@1c16000 {
2467 compatible = "qcom,sm 2083 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2468 reg = <0 0x01c16000 0 !! 2084 reg = <0 0x1c16000 0 0x1c0>;
2469 !! 2085 #address-cells = <2>;
>> 2086 #size-cells = <2>;
>> 2087 ranges;
2470 clocks = <&gcc GCC_PC 2088 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2471 <&gcc GCC_PC 2089 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2472 <&gcc GCC_PC 2090 <&gcc GCC_PCIE_MDM_CLKREF_EN>,
2473 <&gcc GCC_PC !! 2091 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2474 <&gcc GCC_PC !! 2092 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2475 clock-names = "aux", <<
2476 "cfg_ah <<
2477 "ref", <<
2478 "refgen <<
2479 "pipe"; <<
2480 <<
2481 clock-output-names = <<
2482 #clock-cells = <0>; <<
2483 <<
2484 #phy-cells = <0>; <<
2485 2093
2486 resets = <&gcc GCC_PC 2094 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2487 reset-names = "phy"; 2095 reset-names = "phy";
2488 2096
2489 assigned-clocks = <&g 2097 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2490 assigned-clock-rates 2098 assigned-clock-rates = <100000000>;
2491 2099
2492 status = "disabled"; 2100 status = "disabled";
>> 2101
>> 2102 pcie2_lane: phy@1c16200 {
>> 2103 reg = <0 0x1c16200 0 0x170>, /* tx0 */
>> 2104 <0 0x1c16400 0 0x200>, /* rx0 */
>> 2105 <0 0x1c16a00 0 0x1f0>, /* pcs */
>> 2106 <0 0x1c16600 0 0x170>, /* tx1 */
>> 2107 <0 0x1c16800 0 0x200>, /* rx1 */
>> 2108 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
>> 2109 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
>> 2110 clock-names = "pipe0";
>> 2111
>> 2112 #phy-cells = <0>;
>> 2113
>> 2114 #clock-cells = <0>;
>> 2115 clock-output-names = "pcie_2_pipe_clk";
>> 2116 };
2493 }; 2117 };
2494 2118
2495 ufs_mem_hc: ufshc@1d84000 { 2119 ufs_mem_hc: ufshc@1d84000 {
2496 compatible = "qcom,sm 2120 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2497 "jedec,u 2121 "jedec,ufs-2.0";
2498 reg = <0 0x01d84000 0 2122 reg = <0 0x01d84000 0 0x3000>;
2499 interrupts = <GIC_SPI 2123 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2500 phys = <&ufs_mem_phy> !! 2124 phys = <&ufs_mem_phy_lanes>;
2501 phy-names = "ufsphy"; 2125 phy-names = "ufsphy";
2502 lanes-per-direction = 2126 lanes-per-direction = <2>;
2503 #reset-cells = <1>; 2127 #reset-cells = <1>;
2504 resets = <&gcc GCC_UF 2128 resets = <&gcc GCC_UFS_PHY_BCR>;
2505 reset-names = "rst"; 2129 reset-names = "rst";
2506 2130
2507 power-domains = <&gcc 2131 power-domains = <&gcc UFS_PHY_GDSC>;
2508 2132
2509 iommus = <&apps_smmu 2133 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2510 2134
2511 clock-names = 2135 clock-names =
2512 "core_clk", 2136 "core_clk",
2513 "bus_aggr_clk 2137 "bus_aggr_clk",
2514 "iface_clk", 2138 "iface_clk",
2515 "core_clk_uni 2139 "core_clk_unipro",
2516 "ref_clk", 2140 "ref_clk",
2517 "tx_lane0_syn 2141 "tx_lane0_sync_clk",
2518 "rx_lane0_syn 2142 "rx_lane0_sync_clk",
2519 "rx_lane1_syn 2143 "rx_lane1_sync_clk";
2520 clocks = 2144 clocks =
2521 <&gcc GCC_UFS 2145 <&gcc GCC_UFS_PHY_AXI_CLK>,
2522 <&gcc GCC_AGG 2146 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2523 <&gcc GCC_UFS 2147 <&gcc GCC_UFS_PHY_AHB_CLK>,
2524 <&gcc GCC_UFS 2148 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2525 <&rpmhcc RPMH 2149 <&rpmhcc RPMH_CXO_CLK>,
2526 <&gcc GCC_UFS 2150 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2527 <&gcc GCC_UFS 2151 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2528 <&gcc GCC_UFS 2152 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2529 !! 2153 freq-table-hz =
2530 operating-points-v2 = !! 2154 <37500000 300000000>,
2531 !! 2155 <0 0>,
2532 interconnects = <&agg !! 2156 <0 0>,
2533 <&gem !! 2157 <37500000 300000000>,
2534 interconnect-names = !! 2158 <0 0>,
>> 2159 <0 0>,
>> 2160 <0 0>,
>> 2161 <0 0>;
2535 2162
2536 status = "disabled"; 2163 status = "disabled";
2537 <<
2538 ufs_opp_table: opp-ta <<
2539 compatible = <<
2540 <<
2541 opp-37500000 <<
2542 opp-h <<
2543 <<
2544 <<
2545 <<
2546 <<
2547 <<
2548 <<
2549 <<
2550 requi <<
2551 }; <<
2552 <<
2553 opp-300000000 <<
2554 opp-h <<
2555 <<
2556 <<
2557 <<
2558 <<
2559 <<
2560 <<
2561 <<
2562 requi <<
2563 }; <<
2564 }; <<
2565 }; 2164 };
2566 2165
2567 ufs_mem_phy: phy@1d87000 { 2166 ufs_mem_phy: phy@1d87000 {
2568 compatible = "qcom,sm 2167 compatible = "qcom,sm8250-qmp-ufs-phy";
2569 reg = <0 0x01d87000 0 !! 2168 reg = <0 0x01d87000 0 0x1c0>;
2570 !! 2169 #address-cells = <2>;
2571 clocks = <&rpmhcc RPM !! 2170 #size-cells = <2>;
2572 <&gcc GCC_UF !! 2171 ranges;
2573 <&gcc GCC_UF <<
2574 clock-names = "ref", 2172 clock-names = "ref",
2575 "ref_au !! 2173 "ref_aux";
2576 "qref"; !! 2174 clocks = <&rpmhcc RPMH_CXO_CLK>,
>> 2175 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2577 2176
2578 resets = <&ufs_mem_hc 2177 resets = <&ufs_mem_hc 0>;
2579 reset-names = "ufsphy 2178 reset-names = "ufsphy";
2580 <<
2581 power-domains = <&gcc <<
2582 <<
2583 #phy-cells = <0>; <<
2584 <<
2585 status = "disabled"; 2179 status = "disabled";
>> 2180
>> 2181 ufs_mem_phy_lanes: phy@1d87400 {
>> 2182 reg = <0 0x01d87400 0 0x16c>,
>> 2183 <0 0x01d87600 0 0x200>,
>> 2184 <0 0x01d87c00 0 0x200>,
>> 2185 <0 0x01d87800 0 0x16c>,
>> 2186 <0 0x01d87a00 0 0x200>;
>> 2187 #phy-cells = <0>;
>> 2188 };
2586 }; 2189 };
2587 2190
2588 cryptobam: dma-controller@1dc !! 2191 ipa_virt: interconnect@1e00000 {
2589 compatible = "qcom,ba !! 2192 compatible = "qcom,sm8250-ipa-virt";
2590 reg = <0 0x01dc4000 0 !! 2193 reg = <0 0x01e00000 0 0x1000>;
2591 interrupts = <GIC_SPI !! 2194 #interconnect-cells = <1>;
2592 #dma-cells = <1>; !! 2195 qcom,bcm-voters = <&apps_bcm_voter>;
2593 qcom,ee = <0>; <<
2594 qcom,controlled-remot <<
2595 num-channels = <8>; <<
2596 qcom,num-ees = <2>; <<
2597 iommus = <&apps_smmu <<
2598 <&apps_smmu <<
2599 <&apps_smmu <<
2600 <&apps_smmu <<
2601 <&apps_smmu <<
2602 <&apps_smmu <<
2603 }; <<
2604 <<
2605 crypto: crypto@1dfa000 { <<
2606 compatible = "qcom,sm <<
2607 reg = <0 0x01dfa000 0 <<
2608 dmas = <&cryptobam 4> <<
2609 dma-names = "rx", "tx <<
2610 iommus = <&apps_smmu <<
2611 <&apps_smmu <<
2612 <&apps_smmu <<
2613 <&apps_smmu <<
2614 <&apps_smmu <<
2615 <&apps_smmu <<
2616 interconnects = <&agg <<
2617 interconnect-names = <<
2618 }; 2196 };
2619 2197
2620 tcsr_mutex: hwlock@1f40000 { 2198 tcsr_mutex: hwlock@1f40000 {
2621 compatible = "qcom,tc 2199 compatible = "qcom,tcsr-mutex";
2622 reg = <0x0 0x01f40000 2200 reg = <0x0 0x01f40000 0x0 0x40000>;
2623 #hwlock-cells = <1>; 2201 #hwlock-cells = <1>;
2624 }; 2202 };
2625 2203
2626 tcsr: syscon@1fc0000 { <<
2627 compatible = "qcom,sm <<
2628 reg = <0x0 0x1fc0000 <<
2629 }; <<
2630 <<
2631 wsamacro: codec@3240000 { 2204 wsamacro: codec@3240000 {
2632 compatible = "qcom,sm 2205 compatible = "qcom,sm8250-lpass-wsa-macro";
2633 reg = <0 0x03240000 0 2206 reg = <0 0x03240000 0 0x1000>;
2634 clocks = <&q6afecc LP !! 2207 clocks = <&audiocc LPASS_CDC_WSA_MCLK>,
2635 <&q6afecc LP !! 2208 <&audiocc LPASS_CDC_WSA_NPL>,
2636 <&q6afecc LP 2209 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2637 <&q6afecc LP 2210 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2211 <&aoncc LPASS_CDC_VA_MCLK>,
2638 <&vamacro>; 2212 <&vamacro>;
2639 2213
2640 clock-names = "mclk", !! 2214 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2641 2215
2642 #clock-cells = <0>; 2216 #clock-cells = <0>;
>> 2217 clock-frequency = <9600000>;
2643 clock-output-names = 2218 clock-output-names = "mclk";
2644 #sound-dai-cells = <1 2219 #sound-dai-cells = <1>;
2645 2220
2646 pinctrl-names = "defa 2221 pinctrl-names = "default";
2647 pinctrl-0 = <&wsa_swr 2222 pinctrl-0 = <&wsa_swr_active>;
2648 <<
2649 status = "disabled"; <<
2650 }; 2223 };
2651 2224
2652 swr0: soundwire@3250000 { !! 2225 swr0: soundwire-controller@3250000 {
2653 reg = <0 0x03250000 0 2226 reg = <0 0x03250000 0 0x2000>;
2654 compatible = "qcom,so 2227 compatible = "qcom,soundwire-v1.5.1";
2655 interrupts = <GIC_SPI 2228 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
2656 clocks = <&wsamacro>; 2229 clocks = <&wsamacro>;
2657 clock-names = "iface" 2230 clock-names = "iface";
2658 2231
2659 qcom,din-ports = <2>; 2232 qcom,din-ports = <2>;
2660 qcom,dout-ports = <6> 2233 qcom,dout-ports = <6>;
2661 2234
2662 qcom,ports-sinterval- 2235 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = 2236 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = 2237 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack 2238 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2666 2239
2667 #sound-dai-cells = <1 2240 #sound-dai-cells = <1>;
2668 #address-cells = <2>; 2241 #address-cells = <2>;
2669 #size-cells = <0>; 2242 #size-cells = <0>;
>> 2243 };
2670 2244
2671 status = "disabled"; !! 2245 audiocc: clock-controller@3300000 {
>> 2246 compatible = "qcom,sm8250-lpass-audiocc";
>> 2247 reg = <0 0x03300000 0 0x30000>;
>> 2248 #clock-cells = <1>;
>> 2249 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2250 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2251 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2252 clock-names = "core", "audio", "bus";
2672 }; 2253 };
2673 2254
2674 vamacro: codec@3370000 { 2255 vamacro: codec@3370000 {
2675 compatible = "qcom,sm 2256 compatible = "qcom,sm8250-lpass-va-macro";
2676 reg = <0 0x03370000 0 2257 reg = <0 0x03370000 0 0x1000>;
2677 clocks = <&q6afecc LP !! 2258 clocks = <&aoncc LPASS_CDC_VA_MCLK>,
2678 <&q6afecc LPA 2259 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2679 <&q6afecc LPA 2260 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2680 2261
2681 clock-names = "mclk", 2262 clock-names = "mclk", "macro", "dcodec";
2682 2263
2683 #clock-cells = <0>; 2264 #clock-cells = <0>;
>> 2265 clock-frequency = <9600000>;
2684 clock-output-names = 2266 clock-output-names = "fsgen";
2685 #sound-dai-cells = <1 2267 #sound-dai-cells = <1>;
2686 }; 2268 };
2687 2269
2688 rxmacro: rxmacro@3200000 { 2270 rxmacro: rxmacro@3200000 {
2689 pinctrl-names = "defa 2271 pinctrl-names = "default";
2690 pinctrl-0 = <&rx_swr_ 2272 pinctrl-0 = <&rx_swr_active>;
2691 compatible = "qcom,sm 2273 compatible = "qcom,sm8250-lpass-rx-macro";
2692 reg = <0 0x03200000 0 !! 2274 reg = <0 0x3200000 0 0x1000>;
2693 status = "disabled"; 2275 status = "disabled";
2694 2276
2695 clocks = <&q6afecc LP 2277 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2696 <&q6afecc LPA 2278 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2697 <&q6afecc LPA 2279 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2698 <&q6afecc LPA 2280 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2699 <&vamacro>; 2281 <&vamacro>;
2700 2282
2701 clock-names = "mclk", 2283 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2702 2284
2703 #clock-cells = <0>; 2285 #clock-cells = <0>;
>> 2286 clock-frequency = <9600000>;
2704 clock-output-names = 2287 clock-output-names = "mclk";
2705 #sound-dai-cells = <1 2288 #sound-dai-cells = <1>;
2706 }; 2289 };
2707 2290
2708 swr1: soundwire@3210000 { !! 2291 swr1: soundwire-controller@3210000 {
2709 reg = <0 0x03210000 0 !! 2292 reg = <0 0x3210000 0 0x2000>;
2710 compatible = "qcom,so 2293 compatible = "qcom,soundwire-v1.5.1";
2711 status = "disabled"; 2294 status = "disabled";
2712 interrupts = <GIC_SPI 2295 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
2713 clocks = <&rxmacro>; 2296 clocks = <&rxmacro>;
2714 clock-names = "iface" 2297 clock-names = "iface";
2715 label = "RX"; 2298 label = "RX";
2716 qcom,din-ports = <0>; 2299 qcom,din-ports = <0>;
2717 qcom,dout-ports = <5> 2300 qcom,dout-ports = <5>;
2718 2301
2719 qcom,ports-sinterval- !! 2302 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>;
2720 qcom,ports-offset1 = !! 2303 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2721 qcom,ports-offset2 = !! 2304 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2722 qcom,ports-hstart = !! 2305 qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>;
2723 qcom,ports-hstop = !! 2306 qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>;
2724 qcom,ports-word-lengt !! 2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>;
2725 qcom,ports-block-pack !! 2308 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>;
2726 qcom,ports-lane-contr 2309 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-grou !! 2310 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>;
2728 2311
2729 #sound-dai-cells = <1 2312 #sound-dai-cells = <1>;
2730 #address-cells = <2>; 2313 #address-cells = <2>;
2731 #size-cells = <0>; 2314 #size-cells = <0>;
2732 }; 2315 };
2733 2316
2734 txmacro: txmacro@3220000 { 2317 txmacro: txmacro@3220000 {
2735 pinctrl-names = "defa 2318 pinctrl-names = "default";
2736 pinctrl-0 = <&tx_swr_ 2319 pinctrl-0 = <&tx_swr_active>;
2737 compatible = "qcom,sm 2320 compatible = "qcom,sm8250-lpass-tx-macro";
2738 reg = <0 0x03220000 0 !! 2321 reg = <0 0x3220000 0 0x1000>;
2739 status = "disabled"; 2322 status = "disabled";
2740 2323
2741 clocks = <&q6afecc LP 2324 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2742 <&q6afecc LP 2325 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2743 <&q6afecc LP 2326 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2744 <&q6afecc LP 2327 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2745 <&vamacro>; 2328 <&vamacro>;
2746 2329
2747 clock-names = "mclk", 2330 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2748 2331
2749 #clock-cells = <0>; 2332 #clock-cells = <0>;
>> 2333 clock-frequency = <9600000>;
2750 clock-output-names = 2334 clock-output-names = "mclk";
>> 2335 #address-cells = <2>;
>> 2336 #size-cells = <2>;
2751 #sound-dai-cells = <1 2337 #sound-dai-cells = <1>;
2752 }; 2338 };
2753 2339
2754 /* tx macro */ 2340 /* tx macro */
2755 swr2: soundwire@3230000 { !! 2341 swr2: soundwire-controller@3230000 {
2756 reg = <0 0x03230000 0 !! 2342 reg = <0 0x3230000 0 0x2000>;
2757 compatible = "qcom,so 2343 compatible = "qcom,soundwire-v1.5.1";
2758 interrupts = <GIC_SPI !! 2344 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
2759 interrupt-names = "co 2345 interrupt-names = "core";
2760 status = "disabled"; 2346 status = "disabled";
2761 2347
2762 clocks = <&txmacro>; 2348 clocks = <&txmacro>;
2763 clock-names = "iface" 2349 clock-names = "iface";
2764 label = "TX"; 2350 label = "TX";
2765 2351
2766 qcom,din-ports = <5>; 2352 qcom,din-ports = <5>;
2767 qcom,dout-ports = <0> 2353 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval- !! 2354 qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = !! 2355 qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = !! 2356 qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack !! 2357 qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2772 qcom,ports-hstart = !! 2358 qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2773 qcom,ports-hstop = !! 2359 qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2774 qcom,ports-word-lengt !! 2360 qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2775 qcom,ports-block-grou !! 2361 qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>;
2776 qcom,ports-lane-contr !! 2362 qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>;
2777 #sound-dai-cells = <1 2363 #sound-dai-cells = <1>;
2778 #address-cells = <2>; 2364 #address-cells = <2>;
2779 #size-cells = <0>; 2365 #size-cells = <0>;
2780 }; 2366 };
2781 2367
2782 lpass_tlmm: pinctrl@33c0000 { !! 2368 aoncc: clock-controller@3380000 {
>> 2369 compatible = "qcom,sm8250-lpass-aoncc";
>> 2370 reg = <0 0x03380000 0 0x40000>;
>> 2371 #clock-cells = <1>;
>> 2372 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2373 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
>> 2374 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
>> 2375 clock-names = "core", "audio", "bus";
>> 2376 };
>> 2377
>> 2378 lpass_tlmm: pinctrl@33c0000{
2783 compatible = "qcom,sm 2379 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2784 reg = <0 0x033c0000 0 2380 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0 2381 <0 0x03550000 0x0 0x10000>;
2786 gpio-controller; 2382 gpio-controller;
2787 #gpio-cells = <2>; 2383 #gpio-cells = <2>;
2788 gpio-ranges = <&lpass 2384 gpio-ranges = <&lpass_tlmm 0 0 14>;
2789 2385
2790 clocks = <&q6afecc LP 2386 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2791 <&q6afecc LPA 2387 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2792 clock-names = "core", 2388 clock-names = "core", "audio";
2793 2389
2794 wsa_swr_active: wsa-s 2390 wsa_swr_active: wsa-swr-active-state {
2795 clk-pins { 2391 clk-pins {
2796 pins 2392 pins = "gpio10";
2797 funct 2393 function = "wsa_swr_clk";
2798 drive 2394 drive-strength = <2>;
2799 slew- 2395 slew-rate = <1>;
2800 bias- 2396 bias-disable;
2801 }; 2397 };
2802 2398
2803 data-pins { 2399 data-pins {
2804 pins 2400 pins = "gpio11";
2805 funct 2401 function = "wsa_swr_data";
2806 drive 2402 drive-strength = <2>;
2807 slew- 2403 slew-rate = <1>;
2808 bias- 2404 bias-bus-hold;
>> 2405
2809 }; 2406 };
2810 }; 2407 };
2811 2408
2812 wsa_swr_sleep: wsa-sw 2409 wsa_swr_sleep: wsa-swr-sleep-state {
2813 clk-pins { 2410 clk-pins {
2814 pins 2411 pins = "gpio10";
2815 funct 2412 function = "wsa_swr_clk";
2816 drive 2413 drive-strength = <2>;
>> 2414 input-enable;
2817 bias- 2415 bias-pull-down;
2818 }; 2416 };
2819 2417
2820 data-pins { 2418 data-pins {
2821 pins 2419 pins = "gpio11";
2822 funct 2420 function = "wsa_swr_data";
2823 drive 2421 drive-strength = <2>;
>> 2422 input-enable;
2824 bias- 2423 bias-pull-down;
>> 2424
2825 }; 2425 };
2826 }; 2426 };
2827 2427
2828 dmic01_active: dmic01 2428 dmic01_active: dmic01-active-state {
2829 clk-pins { 2429 clk-pins {
2830 pins 2430 pins = "gpio6";
2831 funct 2431 function = "dmic1_clk";
2832 drive 2432 drive-strength = <8>;
2833 outpu 2433 output-high;
2834 }; 2434 };
2835 data-pins { 2435 data-pins {
2836 pins 2436 pins = "gpio7";
2837 funct 2437 function = "dmic1_data";
2838 drive 2438 drive-strength = <8>;
>> 2439 input-enable;
2839 }; 2440 };
2840 }; 2441 };
2841 2442
2842 dmic01_sleep: dmic01- 2443 dmic01_sleep: dmic01-sleep-state {
2843 clk-pins { 2444 clk-pins {
2844 pins 2445 pins = "gpio6";
2845 funct 2446 function = "dmic1_clk";
2846 drive 2447 drive-strength = <2>;
2847 bias- 2448 bias-disable;
2848 outpu 2449 output-low;
2849 }; 2450 };
2850 2451
2851 data-pins { 2452 data-pins {
2852 pins 2453 pins = "gpio7";
2853 funct 2454 function = "dmic1_data";
2854 drive 2455 drive-strength = <2>;
2855 bias- 2456 bias-pull-down;
>> 2457 input-enable;
2856 }; 2458 };
2857 }; 2459 };
2858 2460
2859 rx_swr_active: rx-swr 2461 rx_swr_active: rx-swr-active-state {
2860 clk-pins { 2462 clk-pins {
2861 pins 2463 pins = "gpio3";
2862 funct 2464 function = "swr_rx_clk";
2863 drive 2465 drive-strength = <2>;
2864 slew- 2466 slew-rate = <1>;
2865 bias- 2467 bias-disable;
2866 }; 2468 };
2867 2469
2868 data-pins { 2470 data-pins {
2869 pins 2471 pins = "gpio4", "gpio5";
2870 funct 2472 function = "swr_rx_data";
2871 drive 2473 drive-strength = <2>;
2872 slew- 2474 slew-rate = <1>;
2873 bias- 2475 bias-bus-hold;
2874 }; 2476 };
2875 }; 2477 };
2876 2478
2877 tx_swr_active: tx-swr 2479 tx_swr_active: tx-swr-active-state {
2878 clk-pins { 2480 clk-pins {
2879 pins 2481 pins = "gpio0";
2880 funct 2482 function = "swr_tx_clk";
2881 drive 2483 drive-strength = <2>;
2882 slew- 2484 slew-rate = <1>;
2883 bias- 2485 bias-disable;
2884 }; 2486 };
2885 2487
2886 data-pins { 2488 data-pins {
2887 pins 2489 pins = "gpio1", "gpio2";
2888 funct 2490 function = "swr_tx_data";
2889 drive 2491 drive-strength = <2>;
2890 slew- 2492 slew-rate = <1>;
2891 bias- 2493 bias-bus-hold;
2892 }; 2494 };
2893 }; 2495 };
2894 2496
2895 tx_swr_sleep: tx-swr- 2497 tx_swr_sleep: tx-swr-sleep-state {
2896 clk-pins { 2498 clk-pins {
2897 pins 2499 pins = "gpio0";
2898 funct 2500 function = "swr_tx_clk";
2899 drive 2501 drive-strength = <2>;
>> 2502 input-enable;
2900 bias- 2503 bias-pull-down;
2901 }; 2504 };
2902 2505
2903 data1-pins { 2506 data1-pins {
2904 pins 2507 pins = "gpio1";
2905 funct 2508 function = "swr_tx_data";
2906 drive 2509 drive-strength = <2>;
>> 2510 input-enable;
2907 bias- 2511 bias-bus-hold;
2908 }; 2512 };
2909 2513
2910 data2-pins { 2514 data2-pins {
2911 pins 2515 pins = "gpio2";
2912 funct 2516 function = "swr_tx_data";
2913 drive 2517 drive-strength = <2>;
>> 2518 input-enable;
2914 bias- 2519 bias-pull-down;
2915 }; 2520 };
2916 }; 2521 };
2917 }; 2522 };
2918 2523
2919 gpu: gpu@3d00000 { 2524 gpu: gpu@3d00000 {
2920 compatible = "qcom,ad 2525 compatible = "qcom,adreno-650.2",
2921 "qcom,ad 2526 "qcom,adreno";
2922 2527
2923 reg = <0 0x03d00000 0 2528 reg = <0 0x03d00000 0 0x40000>;
2924 reg-names = "kgsl_3d0 2529 reg-names = "kgsl_3d0_reg_memory";
2925 2530
2926 interrupts = <GIC_SPI 2531 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2927 2532
2928 iommus = <&adreno_smm 2533 iommus = <&adreno_smmu 0 0x401>;
2929 2534
2930 operating-points-v2 = 2535 operating-points-v2 = <&gpu_opp_table>;
2931 2536
2932 qcom,gmu = <&gmu>; 2537 qcom,gmu = <&gmu>;
2933 2538
2934 nvmem-cells = <&gpu_s <<
2935 nvmem-cell-names = "s <<
2936 #cooling-cells = <2>; <<
2937 <<
2938 status = "disabled"; 2539 status = "disabled";
2939 2540
2940 zap-shader { 2541 zap-shader {
2941 memory-region 2542 memory-region = <&gpu_mem>;
2942 }; 2543 };
2943 2544
>> 2545 /* note: downstream checks gpu binning for 670 Mhz */
2944 gpu_opp_table: opp-ta 2546 gpu_opp_table: opp-table {
2945 compatible = 2547 compatible = "operating-points-v2";
2946 2548
2947 opp-670000000 2549 opp-670000000 {
2948 opp-h 2550 opp-hz = /bits/ 64 <670000000>;
2949 opp-l 2551 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2950 opp-s <<
2951 }; 2552 };
2952 2553
2953 opp-587000000 2554 opp-587000000 {
2954 opp-h 2555 opp-hz = /bits/ 64 <587000000>;
2955 opp-l 2556 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2956 opp-s <<
2957 }; 2557 };
2958 2558
2959 opp-525000000 2559 opp-525000000 {
2960 opp-h 2560 opp-hz = /bits/ 64 <525000000>;
2961 opp-l 2561 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2962 opp-s <<
2963 }; 2562 };
2964 2563
2965 opp-490000000 2564 opp-490000000 {
2966 opp-h 2565 opp-hz = /bits/ 64 <490000000>;
2967 opp-l 2566 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2968 opp-s <<
2969 }; 2567 };
2970 2568
2971 opp-441600000 2569 opp-441600000 {
2972 opp-h 2570 opp-hz = /bits/ 64 <441600000>;
2973 opp-l 2571 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2974 opp-s <<
2975 }; 2572 };
2976 2573
2977 opp-400000000 2574 opp-400000000 {
2978 opp-h 2575 opp-hz = /bits/ 64 <400000000>;
2979 opp-l 2576 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2980 opp-s <<
2981 }; 2577 };
2982 2578
2983 opp-305000000 2579 opp-305000000 {
2984 opp-h 2580 opp-hz = /bits/ 64 <305000000>;
2985 opp-l 2581 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2986 opp-s <<
2987 }; 2582 };
2988 }; 2583 };
2989 }; 2584 };
2990 2585
2991 gmu: gmu@3d6a000 { 2586 gmu: gmu@3d6a000 {
2992 compatible = "qcom,ad 2587 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2993 2588
2994 reg = <0 0x03d6a000 0 2589 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 2590 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 2591 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 2592 <0 0xb490000 0 0x10000>;
2998 reg-names = "gmu", "r 2593 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2999 2594
3000 interrupts = <GIC_SPI 2595 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
3001 <GIC_SPI 2596 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
3002 interrupt-names = "hf 2597 interrupt-names = "hfi", "gmu";
3003 2598
3004 clocks = <&gpucc GPU_ 2599 clocks = <&gpucc GPU_CC_AHB_CLK>,
3005 <&gpucc GPU_ 2600 <&gpucc GPU_CC_CX_GMU_CLK>,
3006 <&gpucc GPU_ 2601 <&gpucc GPU_CC_CXO_CLK>,
3007 <&gcc GCC_DD 2602 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
3008 <&gcc GCC_GP 2603 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
3009 clock-names = "ahb", 2604 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
3010 2605
3011 power-domains = <&gpu 2606 power-domains = <&gpucc GPU_CX_GDSC>,
3012 <&gpu 2607 <&gpucc GPU_GX_GDSC>;
3013 power-domain-names = 2608 power-domain-names = "cx", "gx";
3014 2609
3015 iommus = <&adreno_smm 2610 iommus = <&adreno_smmu 5 0x400>;
3016 2611
3017 operating-points-v2 = 2612 operating-points-v2 = <&gmu_opp_table>;
3018 2613
3019 status = "disabled"; 2614 status = "disabled";
3020 2615
3021 gmu_opp_table: opp-ta 2616 gmu_opp_table: opp-table {
3022 compatible = 2617 compatible = "operating-points-v2";
3023 2618
3024 opp-200000000 2619 opp-200000000 {
3025 opp-h 2620 opp-hz = /bits/ 64 <200000000>;
3026 opp-l 2621 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3027 }; 2622 };
3028 }; 2623 };
3029 }; 2624 };
3030 2625
3031 gpucc: clock-controller@3d900 2626 gpucc: clock-controller@3d90000 {
3032 compatible = "qcom,sm 2627 compatible = "qcom,sm8250-gpucc";
3033 reg = <0 0x03d90000 0 2628 reg = <0 0x03d90000 0 0x9000>;
3034 clocks = <&rpmhcc RPM 2629 clocks = <&rpmhcc RPMH_CXO_CLK>,
3035 <&gcc GCC_GP 2630 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
3036 <&gcc GCC_GP 2631 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
3037 clock-names = "bi_tcx 2632 clock-names = "bi_tcxo",
3038 "gcc_gp 2633 "gcc_gpu_gpll0_clk_src",
3039 "gcc_gp 2634 "gcc_gpu_gpll0_div_clk_src";
3040 #clock-cells = <1>; 2635 #clock-cells = <1>;
3041 #reset-cells = <1>; 2636 #reset-cells = <1>;
3042 #power-domain-cells = 2637 #power-domain-cells = <1>;
3043 }; 2638 };
3044 2639
3045 adreno_smmu: iommu@3da0000 { 2640 adreno_smmu: iommu@3da0000 {
3046 compatible = "qcom,sm !! 2641 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
3047 "qcom,sm <<
3048 reg = <0 0x03da0000 0 2642 reg = <0 0x03da0000 0 0x10000>;
3049 #iommu-cells = <2>; 2643 #iommu-cells = <2>;
3050 #global-interrupts = 2644 #global-interrupts = <2>;
3051 interrupts = <GIC_SPI 2645 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
3052 <GIC_SPI 2646 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 2647 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 2648 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 2649 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
3056 <GIC_SPI 2650 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
3057 <GIC_SPI 2651 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
3058 <GIC_SPI 2652 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 2653 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
3060 <GIC_SPI 2654 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
3061 clocks = <&gpucc GPU_ 2655 clocks = <&gpucc GPU_CC_AHB_CLK>,
3062 <&gcc GCC_GP 2656 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
3063 <&gcc GCC_GP 2657 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
3064 clock-names = "ahb", 2658 clock-names = "ahb", "bus", "iface";
3065 2659
3066 power-domains = <&gpu 2660 power-domains = <&gpucc GPU_CX_GDSC>;
3067 dma-coherent; <<
3068 }; 2661 };
3069 2662
3070 slpi: remoteproc@5c00000 { 2663 slpi: remoteproc@5c00000 {
3071 compatible = "qcom,sm 2664 compatible = "qcom,sm8250-slpi-pas";
3072 reg = <0 0x05c00000 0 2665 reg = <0 0x05c00000 0 0x4000>;
3073 2666
3074 interrupts-extended = !! 2667 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
3075 2668 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3076 2669 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
3077 2670 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
3078 2671 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
3079 interrupt-names = "wd 2672 interrupt-names = "wdog", "fatal", "ready",
3080 "ha 2673 "handover", "stop-ack";
3081 2674
3082 clocks = <&rpmhcc RPM 2675 clocks = <&rpmhcc RPMH_CXO_CLK>;
3083 clock-names = "xo"; 2676 clock-names = "xo";
3084 2677
3085 power-domains = <&rpm !! 2678 power-domains = <&rpmhpd SM8250_LCX>,
3086 <&rpm !! 2679 <&rpmhpd SM8250_LMX>;
3087 power-domain-names = 2680 power-domain-names = "lcx", "lmx";
3088 2681
3089 memory-region = <&slp 2682 memory-region = <&slpi_mem>;
3090 2683
3091 qcom,qmp = <&aoss_qmp 2684 qcom,qmp = <&aoss_qmp>;
3092 2685
3093 qcom,smem-states = <& 2686 qcom,smem-states = <&smp2p_slpi_out 0>;
3094 qcom,smem-state-names 2687 qcom,smem-state-names = "stop";
3095 2688
3096 status = "disabled"; 2689 status = "disabled";
3097 2690
3098 glink-edge { 2691 glink-edge {
3099 interrupts-ex 2692 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
3100 2693 IPCC_MPROC_SIGNAL_GLINK_QMP
3101 2694 IRQ_TYPE_EDGE_RISING>;
3102 mboxes = <&ip 2695 mboxes = <&ipcc IPCC_CLIENT_SLPI
3103 2696 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3104 2697
3105 label = "slpi 2698 label = "slpi";
3106 qcom,remote-p 2699 qcom,remote-pid = <3>;
3107 2700
3108 fastrpc { 2701 fastrpc {
3109 compa 2702 compatible = "qcom,fastrpc";
3110 qcom, 2703 qcom,glink-channels = "fastrpcglink-apps-dsp";
3111 label 2704 label = "sdsp";
3112 qcom, 2705 qcom,non-secure-domain;
3113 #addr 2706 #address-cells = <1>;
3114 #size 2707 #size-cells = <0>;
3115 2708
3116 compu 2709 compute-cb@1 {
3117 2710 compatible = "qcom,fastrpc-compute-cb";
3118 2711 reg = <1>;
3119 2712 iommus = <&apps_smmu 0x0541 0x0>;
3120 }; 2713 };
3121 2714
3122 compu 2715 compute-cb@2 {
3123 2716 compatible = "qcom,fastrpc-compute-cb";
3124 2717 reg = <2>;
3125 2718 iommus = <&apps_smmu 0x0542 0x0>;
3126 }; 2719 };
3127 2720
3128 compu 2721 compute-cb@3 {
3129 2722 compatible = "qcom,fastrpc-compute-cb";
3130 2723 reg = <3>;
3131 2724 iommus = <&apps_smmu 0x0543 0x0>;
3132 2725 /* note: shared-cb = <4> in downstream */
3133 }; 2726 };
3134 }; 2727 };
3135 }; 2728 };
3136 }; 2729 };
3137 2730
3138 stm@6002000 { 2731 stm@6002000 {
3139 compatible = "arm,cor 2732 compatible = "arm,coresight-stm", "arm,primecell";
3140 reg = <0 0x06002000 0 2733 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3141 reg-names = "stm-base 2734 reg-names = "stm-base", "stm-stimulus-base";
3142 2735
3143 clocks = <&aoss_qmp>; 2736 clocks = <&aoss_qmp>;
3144 clock-names = "apb_pc 2737 clock-names = "apb_pclk";
3145 2738
3146 out-ports { 2739 out-ports {
3147 port { 2740 port {
3148 stm_o 2741 stm_out: endpoint {
3149 2742 remote-endpoint = <&funnel0_in7>;
3150 }; 2743 };
3151 }; 2744 };
3152 }; 2745 };
3153 }; 2746 };
3154 2747
3155 tpda@6004000 { <<
3156 compatible = "qcom,co <<
3157 reg = <0 0x06004000 0 <<
3158 <<
3159 clocks = <&aoss_qmp>; <<
3160 clock-names = "apb_pc <<
3161 <<
3162 out-ports { <<
3163 <<
3164 port { <<
3165 tpda_ <<
3166 <<
3167 }; <<
3168 }; <<
3169 }; <<
3170 <<
3171 in-ports { <<
3172 #address-cell <<
3173 #size-cells = <<
3174 <<
3175 port@9 { <<
3176 reg = <<
3177 tpda_ <<
3178 <<
3179 }; <<
3180 }; <<
3181 <<
3182 port@17 { <<
3183 reg = <<
3184 tpda_ <<
3185 <<
3186 }; <<
3187 }; <<
3188 }; <<
3189 }; <<
3190 <<
3191 funnel@6005000 { <<
3192 compatible = "arm,cor <<
3193 reg = <0 0x06005000 0 <<
3194 <<
3195 clocks = <&aoss_qmp>; <<
3196 clock-names = "apb_pc <<
3197 <<
3198 out-ports { <<
3199 port { <<
3200 funne <<
3201 <<
3202 }; <<
3203 }; <<
3204 }; <<
3205 <<
3206 in-ports { <<
3207 port { <<
3208 funne <<
3209 <<
3210 }; <<
3211 }; <<
3212 }; <<
3213 }; <<
3214 <<
3215 funnel@6041000 { 2748 funnel@6041000 {
3216 compatible = "arm,cor 2749 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3217 reg = <0 0x06041000 0 2750 reg = <0 0x06041000 0 0x1000>;
3218 2751
3219 clocks = <&aoss_qmp>; 2752 clocks = <&aoss_qmp>;
3220 clock-names = "apb_pc 2753 clock-names = "apb_pclk";
3221 2754
3222 out-ports { 2755 out-ports {
3223 port { 2756 port {
3224 funne 2757 funnel_in0_out_funnel_merg: endpoint {
3225 2758 remote-endpoint = <&funnel_merg_in_funnel_in0>;
3226 }; 2759 };
3227 }; 2760 };
3228 }; 2761 };
3229 2762
3230 in-ports { 2763 in-ports {
3231 #address-cell 2764 #address-cells = <1>;
3232 #size-cells = 2765 #size-cells = <0>;
3233 2766
3234 port@6 { <<
3235 reg = <<
3236 funne <<
3237 <<
3238 }; <<
3239 }; <<
3240 <<
3241 port@7 { 2767 port@7 {
3242 reg = 2768 reg = <7>;
3243 funne 2769 funnel0_in7: endpoint {
3244 2770 remote-endpoint = <&stm_out>;
3245 }; 2771 };
3246 }; 2772 };
3247 }; 2773 };
3248 }; 2774 };
3249 2775
3250 funnel@6042000 { 2776 funnel@6042000 {
3251 compatible = "arm,cor 2777 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3252 reg = <0 0x06042000 0 2778 reg = <0 0x06042000 0 0x1000>;
3253 2779
3254 clocks = <&aoss_qmp>; 2780 clocks = <&aoss_qmp>;
3255 clock-names = "apb_pc 2781 clock-names = "apb_pclk";
3256 2782
3257 out-ports { 2783 out-ports {
3258 port { !! 2784 #address-cells = <1>;
>> 2785 #size-cells = <0>;
>> 2786
>> 2787 port@0 {
>> 2788 reg = <0>;
3259 funne 2789 funnel_in1_out_funnel_merg: endpoint {
3260 2790 remote-endpoint = <&funnel_merg_in_funnel_in1>;
3261 }; 2791 };
3262 }; 2792 };
3263 }; 2793 };
3264 2794
3265 in-ports { 2795 in-ports {
3266 #address-cell 2796 #address-cells = <1>;
3267 #size-cells = 2797 #size-cells = <0>;
3268 2798
3269 port@4 { 2799 port@4 {
3270 reg = 2800 reg = <4>;
3271 funne 2801 funnel_in1_in_funnel_apss_merg: endpoint {
3272 remot 2802 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
3273 }; 2803 };
3274 }; 2804 };
3275 }; 2805 };
3276 }; 2806 };
3277 2807
3278 funnel@6045000 { 2808 funnel@6045000 {
3279 compatible = "arm,cor 2809 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3280 reg = <0 0x06045000 0 2810 reg = <0 0x06045000 0 0x1000>;
3281 2811
3282 clocks = <&aoss_qmp>; 2812 clocks = <&aoss_qmp>;
3283 clock-names = "apb_pc 2813 clock-names = "apb_pclk";
3284 2814
3285 out-ports { 2815 out-ports {
3286 port { 2816 port {
3287 funne 2817 funnel_merg_out_funnel_swao: endpoint {
3288 remot 2818 remote-endpoint = <&funnel_swao_in_funnel_merg>;
3289 }; 2819 };
3290 }; 2820 };
3291 }; 2821 };
3292 2822
3293 in-ports { 2823 in-ports {
3294 #address-cell 2824 #address-cells = <1>;
3295 #size-cells = 2825 #size-cells = <0>;
3296 2826
3297 port@0 { 2827 port@0 {
3298 reg = 2828 reg = <0>;
3299 funne 2829 funnel_merg_in_funnel_in0: endpoint {
3300 remot 2830 remote-endpoint = <&funnel_in0_out_funnel_merg>;
3301 }; 2831 };
3302 }; 2832 };
3303 2833
3304 port@1 { 2834 port@1 {
3305 reg = 2835 reg = <1>;
3306 funne 2836 funnel_merg_in_funnel_in1: endpoint {
3307 remot 2837 remote-endpoint = <&funnel_in1_out_funnel_merg>;
3308 }; 2838 };
3309 }; 2839 };
3310 }; 2840 };
3311 }; 2841 };
3312 2842
3313 replicator@6046000 { 2843 replicator@6046000 {
3314 compatible = "arm,cor 2844 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3315 reg = <0 0x06046000 0 2845 reg = <0 0x06046000 0 0x1000>;
3316 2846
3317 clocks = <&aoss_qmp>; 2847 clocks = <&aoss_qmp>;
3318 clock-names = "apb_pc 2848 clock-names = "apb_pclk";
3319 2849
3320 out-ports { 2850 out-ports {
3321 port { 2851 port {
3322 repli 2852 replicator_out: endpoint {
3323 2853 remote-endpoint = <&etr_in>;
3324 }; 2854 };
3325 }; 2855 };
3326 }; 2856 };
3327 2857
3328 in-ports { 2858 in-ports {
3329 port { 2859 port {
3330 repli 2860 replicator_cx_in_swao_out: endpoint {
3331 2861 remote-endpoint = <&replicator_swao_out_cx_in>;
3332 }; 2862 };
3333 }; 2863 };
3334 }; 2864 };
3335 }; 2865 };
3336 2866
3337 etr@6048000 { 2867 etr@6048000 {
3338 compatible = "arm,cor 2868 compatible = "arm,coresight-tmc", "arm,primecell";
3339 reg = <0 0x06048000 0 2869 reg = <0 0x06048000 0 0x1000>;
3340 2870
3341 clocks = <&aoss_qmp>; 2871 clocks = <&aoss_qmp>;
3342 clock-names = "apb_pc 2872 clock-names = "apb_pclk";
3343 arm,scatter-gather; 2873 arm,scatter-gather;
3344 2874
3345 in-ports { 2875 in-ports {
3346 port { 2876 port {
3347 etr_i 2877 etr_in: endpoint {
3348 2878 remote-endpoint = <&replicator_out>;
3349 }; 2879 };
3350 }; 2880 };
3351 }; 2881 };
3352 }; 2882 };
3353 2883
3354 tpdm@684c000 { <<
3355 compatible = "qcom,co <<
3356 reg = <0 0x0684c000 0 <<
3357 <<
3358 clocks = <&aoss_qmp>; <<
3359 clock-names = "apb_pc <<
3360 <<
3361 out-ports { <<
3362 port { <<
3363 tpdm_ <<
3364 <<
3365 }; <<
3366 }; <<
3367 }; <<
3368 }; <<
3369 <<
3370 funnel@6b04000 { 2884 funnel@6b04000 {
3371 compatible = "arm,cor 2885 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3372 arm,primecell-periphi 2886 arm,primecell-periphid = <0x000bb908>;
3373 2887
3374 reg = <0 0x06b04000 0 2888 reg = <0 0x06b04000 0 0x1000>;
>> 2889 reg-names = "funnel-base";
3375 2890
3376 clocks = <&aoss_qmp>; 2891 clocks = <&aoss_qmp>;
3377 clock-names = "apb_pc 2892 clock-names = "apb_pclk";
3378 2893
3379 out-ports { 2894 out-ports {
3380 port { 2895 port {
3381 funne 2896 funnel_swao_out_etf: endpoint {
3382 2897 remote-endpoint = <&etf_in_funnel_swao_out>;
3383 }; 2898 };
3384 }; 2899 };
3385 }; 2900 };
3386 2901
3387 in-ports { 2902 in-ports {
3388 #address-cell 2903 #address-cells = <1>;
3389 #size-cells = 2904 #size-cells = <0>;
3390 2905
3391 port@7 { 2906 port@7 {
3392 reg = 2907 reg = <7>;
3393 funne 2908 funnel_swao_in_funnel_merg: endpoint {
3394 !! 2909 remote-endpoint= <&funnel_merg_out_funnel_swao>;
3395 }; 2910 };
3396 }; 2911 };
3397 }; 2912 };
>> 2913
3398 }; 2914 };
3399 2915
3400 etf@6b05000 { 2916 etf@6b05000 {
3401 compatible = "arm,cor 2917 compatible = "arm,coresight-tmc", "arm,primecell";
3402 reg = <0 0x06b05000 0 2918 reg = <0 0x06b05000 0 0x1000>;
3403 2919
3404 clocks = <&aoss_qmp>; 2920 clocks = <&aoss_qmp>;
3405 clock-names = "apb_pc 2921 clock-names = "apb_pclk";
3406 2922
3407 out-ports { 2923 out-ports {
3408 port { 2924 port {
3409 etf_o 2925 etf_out: endpoint {
3410 2926 remote-endpoint = <&replicator_in>;
3411 }; 2927 };
3412 }; 2928 };
3413 }; 2929 };
3414 2930
3415 in-ports { 2931 in-ports {
>> 2932 #address-cells = <1>;
>> 2933 #size-cells = <0>;
3416 2934
3417 port { !! 2935 port@0 {
>> 2936 reg = <0>;
3418 etf_i 2937 etf_in_funnel_swao_out: endpoint {
3419 2938 remote-endpoint = <&funnel_swao_out_etf>;
3420 }; 2939 };
3421 }; 2940 };
3422 }; 2941 };
3423 }; 2942 };
3424 2943
3425 replicator@6b06000 { 2944 replicator@6b06000 {
3426 compatible = "arm,cor 2945 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3427 reg = <0 0x06b06000 0 2946 reg = <0 0x06b06000 0 0x1000>;
3428 2947
3429 clocks = <&aoss_qmp>; 2948 clocks = <&aoss_qmp>;
3430 clock-names = "apb_pc 2949 clock-names = "apb_pclk";
3431 2950
3432 out-ports { 2951 out-ports {
3433 port { 2952 port {
3434 repli 2953 replicator_swao_out_cx_in: endpoint {
3435 2954 remote-endpoint = <&replicator_cx_in_swao_out>;
3436 }; 2955 };
3437 }; 2956 };
3438 }; 2957 };
3439 2958
3440 in-ports { 2959 in-ports {
3441 port { 2960 port {
3442 repli 2961 replicator_in: endpoint {
3443 2962 remote-endpoint = <&etf_out>;
3444 }; 2963 };
3445 }; 2964 };
3446 }; 2965 };
3447 }; 2966 };
3448 2967
3449 tpdm@6c08000 { <<
3450 compatible = "qcom,co <<
3451 reg = <0 0x06c08000 0 <<
3452 <<
3453 clocks = <&aoss_qmp>; <<
3454 clock-names = "apb_pc <<
3455 <<
3456 out-ports { <<
3457 port { <<
3458 tpdm_ <<
3459 <<
3460 }; <<
3461 }; <<
3462 }; <<
3463 }; <<
3464 <<
3465 funnel@6c0b000 { <<
3466 compatible = "arm,cor <<
3467 reg = <0 0x06c0b000 0 <<
3468 <<
3469 clocks = <&aoss_qmp>; <<
3470 clock-names = "apb_pc <<
3471 <<
3472 out-ports { <<
3473 port { <<
3474 funne <<
3475 remot <<
3476 }; <<
3477 }; <<
3478 }; <<
3479 <<
3480 in-ports { <<
3481 #address-cell <<
3482 #size-cells = <<
3483 <<
3484 port@3 { <<
3485 reg = <<
3486 funne <<
3487 <<
3488 }; <<
3489 }; <<
3490 }; <<
3491 }; <<
3492 <<
3493 funnel@6c2d000 { <<
3494 compatible = "arm,cor <<
3495 reg = <0 0x06c2d000 0 <<
3496 <<
3497 clocks = <&aoss_qmp>; <<
3498 clock-names = "apb_pc <<
3499 <<
3500 out-ports { <<
3501 port { <<
3502 tpdm_ <<
3503 <<
3504 }; <<
3505 }; <<
3506 }; <<
3507 <<
3508 in-ports { <<
3509 #address-cell <<
3510 #size-cells = <<
3511 <<
3512 port@2 { <<
3513 reg = <<
3514 funne <<
3515 remot <<
3516 }; <<
3517 }; <<
3518 }; <<
3519 }; <<
3520 <<
3521 etm@7040000 { 2968 etm@7040000 {
3522 compatible = "arm,cor 2969 compatible = "arm,coresight-etm4x", "arm,primecell";
3523 reg = <0 0x07040000 0 2970 reg = <0 0x07040000 0 0x1000>;
3524 2971
3525 cpu = <&CPU0>; 2972 cpu = <&CPU0>;
3526 2973
3527 clocks = <&aoss_qmp>; 2974 clocks = <&aoss_qmp>;
3528 clock-names = "apb_pc 2975 clock-names = "apb_pclk";
3529 arm,coresight-loses-c 2976 arm,coresight-loses-context-with-cpu;
3530 2977
3531 out-ports { 2978 out-ports {
3532 port { 2979 port {
3533 etm0_ 2980 etm0_out: endpoint {
3534 2981 remote-endpoint = <&apss_funnel_in0>;
3535 }; 2982 };
3536 }; 2983 };
3537 }; 2984 };
3538 }; 2985 };
3539 2986
3540 etm@7140000 { 2987 etm@7140000 {
3541 compatible = "arm,cor 2988 compatible = "arm,coresight-etm4x", "arm,primecell";
3542 reg = <0 0x07140000 0 2989 reg = <0 0x07140000 0 0x1000>;
3543 2990
3544 cpu = <&CPU1>; 2991 cpu = <&CPU1>;
3545 2992
3546 clocks = <&aoss_qmp>; 2993 clocks = <&aoss_qmp>;
3547 clock-names = "apb_pc 2994 clock-names = "apb_pclk";
3548 arm,coresight-loses-c 2995 arm,coresight-loses-context-with-cpu;
3549 2996
3550 out-ports { 2997 out-ports {
3551 port { 2998 port {
3552 etm1_ 2999 etm1_out: endpoint {
3553 3000 remote-endpoint = <&apss_funnel_in1>;
3554 }; 3001 };
3555 }; 3002 };
3556 }; 3003 };
3557 }; 3004 };
3558 3005
3559 etm@7240000 { 3006 etm@7240000 {
3560 compatible = "arm,cor 3007 compatible = "arm,coresight-etm4x", "arm,primecell";
3561 reg = <0 0x07240000 0 3008 reg = <0 0x07240000 0 0x1000>;
3562 3009
3563 cpu = <&CPU2>; 3010 cpu = <&CPU2>;
3564 3011
3565 clocks = <&aoss_qmp>; 3012 clocks = <&aoss_qmp>;
3566 clock-names = "apb_pc 3013 clock-names = "apb_pclk";
3567 arm,coresight-loses-c 3014 arm,coresight-loses-context-with-cpu;
3568 3015
3569 out-ports { 3016 out-ports {
3570 port { 3017 port {
3571 etm2_ 3018 etm2_out: endpoint {
3572 3019 remote-endpoint = <&apss_funnel_in2>;
3573 }; 3020 };
3574 }; 3021 };
3575 }; 3022 };
3576 }; 3023 };
3577 3024
3578 etm@7340000 { 3025 etm@7340000 {
3579 compatible = "arm,cor 3026 compatible = "arm,coresight-etm4x", "arm,primecell";
3580 reg = <0 0x07340000 0 3027 reg = <0 0x07340000 0 0x1000>;
3581 3028
3582 cpu = <&CPU3>; 3029 cpu = <&CPU3>;
3583 3030
3584 clocks = <&aoss_qmp>; 3031 clocks = <&aoss_qmp>;
3585 clock-names = "apb_pc 3032 clock-names = "apb_pclk";
3586 arm,coresight-loses-c 3033 arm,coresight-loses-context-with-cpu;
3587 3034
3588 out-ports { 3035 out-ports {
3589 port { 3036 port {
3590 etm3_ 3037 etm3_out: endpoint {
3591 3038 remote-endpoint = <&apss_funnel_in3>;
3592 }; 3039 };
3593 }; 3040 };
3594 }; 3041 };
3595 }; 3042 };
3596 3043
3597 etm@7440000 { 3044 etm@7440000 {
3598 compatible = "arm,cor 3045 compatible = "arm,coresight-etm4x", "arm,primecell";
3599 reg = <0 0x07440000 0 3046 reg = <0 0x07440000 0 0x1000>;
3600 3047
3601 cpu = <&CPU4>; 3048 cpu = <&CPU4>;
3602 3049
3603 clocks = <&aoss_qmp>; 3050 clocks = <&aoss_qmp>;
3604 clock-names = "apb_pc 3051 clock-names = "apb_pclk";
3605 arm,coresight-loses-c 3052 arm,coresight-loses-context-with-cpu;
3606 3053
3607 out-ports { 3054 out-ports {
3608 port { 3055 port {
3609 etm4_ 3056 etm4_out: endpoint {
3610 3057 remote-endpoint = <&apss_funnel_in4>;
3611 }; 3058 };
3612 }; 3059 };
3613 }; 3060 };
3614 }; 3061 };
3615 3062
3616 etm@7540000 { 3063 etm@7540000 {
3617 compatible = "arm,cor 3064 compatible = "arm,coresight-etm4x", "arm,primecell";
3618 reg = <0 0x07540000 0 3065 reg = <0 0x07540000 0 0x1000>;
3619 3066
3620 cpu = <&CPU5>; 3067 cpu = <&CPU5>;
3621 3068
3622 clocks = <&aoss_qmp>; 3069 clocks = <&aoss_qmp>;
3623 clock-names = "apb_pc 3070 clock-names = "apb_pclk";
3624 arm,coresight-loses-c 3071 arm,coresight-loses-context-with-cpu;
3625 3072
3626 out-ports { 3073 out-ports {
3627 port { 3074 port {
3628 etm5_ 3075 etm5_out: endpoint {
3629 3076 remote-endpoint = <&apss_funnel_in5>;
3630 }; 3077 };
3631 }; 3078 };
3632 }; 3079 };
3633 }; 3080 };
3634 3081
3635 etm@7640000 { 3082 etm@7640000 {
3636 compatible = "arm,cor 3083 compatible = "arm,coresight-etm4x", "arm,primecell";
3637 reg = <0 0x07640000 0 3084 reg = <0 0x07640000 0 0x1000>;
3638 3085
3639 cpu = <&CPU6>; 3086 cpu = <&CPU6>;
3640 3087
3641 clocks = <&aoss_qmp>; 3088 clocks = <&aoss_qmp>;
3642 clock-names = "apb_pc 3089 clock-names = "apb_pclk";
3643 arm,coresight-loses-c 3090 arm,coresight-loses-context-with-cpu;
3644 3091
3645 out-ports { 3092 out-ports {
3646 port { 3093 port {
3647 etm6_ 3094 etm6_out: endpoint {
3648 3095 remote-endpoint = <&apss_funnel_in6>;
3649 }; 3096 };
3650 }; 3097 };
3651 }; 3098 };
3652 }; 3099 };
3653 3100
3654 etm@7740000 { 3101 etm@7740000 {
3655 compatible = "arm,cor 3102 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 reg = <0 0x07740000 0 3103 reg = <0 0x07740000 0 0x1000>;
3657 3104
3658 cpu = <&CPU7>; 3105 cpu = <&CPU7>;
3659 3106
3660 clocks = <&aoss_qmp>; 3107 clocks = <&aoss_qmp>;
3661 clock-names = "apb_pc 3108 clock-names = "apb_pclk";
3662 arm,coresight-loses-c 3109 arm,coresight-loses-context-with-cpu;
3663 3110
3664 out-ports { 3111 out-ports {
3665 port { 3112 port {
3666 etm7_ 3113 etm7_out: endpoint {
3667 3114 remote-endpoint = <&apss_funnel_in7>;
3668 }; 3115 };
3669 }; 3116 };
3670 }; 3117 };
3671 }; 3118 };
3672 3119
3673 funnel@7800000 { 3120 funnel@7800000 {
3674 compatible = "arm,cor 3121 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3675 reg = <0 0x07800000 0 3122 reg = <0 0x07800000 0 0x1000>;
3676 3123
3677 clocks = <&aoss_qmp>; 3124 clocks = <&aoss_qmp>;
3678 clock-names = "apb_pc 3125 clock-names = "apb_pclk";
3679 3126
3680 out-ports { 3127 out-ports {
3681 port { 3128 port {
3682 funne 3129 funnel_apss_out_funnel_apss_merg: endpoint {
3683 remot 3130 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3684 }; 3131 };
3685 }; 3132 };
3686 }; 3133 };
3687 3134
3688 in-ports { 3135 in-ports {
3689 #address-cell 3136 #address-cells = <1>;
3690 #size-cells = 3137 #size-cells = <0>;
3691 3138
3692 port@0 { 3139 port@0 {
3693 reg = 3140 reg = <0>;
3694 apss_ 3141 apss_funnel_in0: endpoint {
3695 3142 remote-endpoint = <&etm0_out>;
3696 }; 3143 };
3697 }; 3144 };
3698 3145
3699 port@1 { 3146 port@1 {
3700 reg = 3147 reg = <1>;
3701 apss_ 3148 apss_funnel_in1: endpoint {
3702 3149 remote-endpoint = <&etm1_out>;
3703 }; 3150 };
3704 }; 3151 };
3705 3152
3706 port@2 { 3153 port@2 {
3707 reg = 3154 reg = <2>;
3708 apss_ 3155 apss_funnel_in2: endpoint {
3709 3156 remote-endpoint = <&etm2_out>;
3710 }; 3157 };
3711 }; 3158 };
3712 3159
3713 port@3 { 3160 port@3 {
3714 reg = 3161 reg = <3>;
3715 apss_ 3162 apss_funnel_in3: endpoint {
3716 3163 remote-endpoint = <&etm3_out>;
3717 }; 3164 };
3718 }; 3165 };
3719 3166
3720 port@4 { 3167 port@4 {
3721 reg = 3168 reg = <4>;
3722 apss_ 3169 apss_funnel_in4: endpoint {
3723 3170 remote-endpoint = <&etm4_out>;
3724 }; 3171 };
3725 }; 3172 };
3726 3173
3727 port@5 { 3174 port@5 {
3728 reg = 3175 reg = <5>;
3729 apss_ 3176 apss_funnel_in5: endpoint {
3730 3177 remote-endpoint = <&etm5_out>;
3731 }; 3178 };
3732 }; 3179 };
3733 3180
3734 port@6 { 3181 port@6 {
3735 reg = 3182 reg = <6>;
3736 apss_ 3183 apss_funnel_in6: endpoint {
3737 3184 remote-endpoint = <&etm6_out>;
3738 }; 3185 };
3739 }; 3186 };
3740 3187
3741 port@7 { 3188 port@7 {
3742 reg = 3189 reg = <7>;
3743 apss_ 3190 apss_funnel_in7: endpoint {
3744 3191 remote-endpoint = <&etm7_out>;
3745 }; 3192 };
3746 }; 3193 };
3747 }; 3194 };
3748 }; 3195 };
3749 3196
3750 funnel@7810000 { 3197 funnel@7810000 {
3751 compatible = "arm,cor 3198 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3752 reg = <0 0x07810000 0 3199 reg = <0 0x07810000 0 0x1000>;
3753 3200
3754 clocks = <&aoss_qmp>; 3201 clocks = <&aoss_qmp>;
3755 clock-names = "apb_pc 3202 clock-names = "apb_pclk";
3756 3203
3757 out-ports { 3204 out-ports {
>> 3205 #address-cells = <1>;
>> 3206 #size-cells = <0>;
>> 3207
3758 port { 3208 port {
3759 funne 3209 funnel_apss_merg_out_funnel_in1: endpoint {
3760 remot 3210 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3761 }; 3211 };
3762 }; 3212 };
3763 }; 3213 };
3764 3214
3765 in-ports { 3215 in-ports {
3766 port { !! 3216 #address-cells = <1>;
>> 3217 #size-cells = <0>;
>> 3218
>> 3219 port@0 {
>> 3220 reg = <0>;
3767 funne 3221 funnel_apss_merg_in_funnel_apss: endpoint {
3768 remot 3222 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3769 }; 3223 };
3770 }; 3224 };
3771 }; 3225 };
3772 }; 3226 };
3773 3227
3774 cdsp: remoteproc@8300000 { 3228 cdsp: remoteproc@8300000 {
3775 compatible = "qcom,sm 3229 compatible = "qcom,sm8250-cdsp-pas";
3776 reg = <0 0x08300000 0 3230 reg = <0 0x08300000 0 0x10000>;
3777 3231
3778 interrupts-extended = !! 3232 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3779 3233 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3780 3234 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3781 3235 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
3782 3236 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
3783 interrupt-names = "wd 3237 interrupt-names = "wdog", "fatal", "ready",
3784 "ha 3238 "handover", "stop-ack";
3785 3239
3786 clocks = <&rpmhcc RPM 3240 clocks = <&rpmhcc RPMH_CXO_CLK>;
3787 clock-names = "xo"; 3241 clock-names = "xo";
3788 3242
3789 power-domains = <&rpm !! 3243 power-domains = <&rpmhpd SM8250_CX>;
3790 3244
3791 memory-region = <&cds 3245 memory-region = <&cdsp_mem>;
3792 3246
3793 qcom,qmp = <&aoss_qmp 3247 qcom,qmp = <&aoss_qmp>;
3794 3248
3795 qcom,smem-states = <& 3249 qcom,smem-states = <&smp2p_cdsp_out 0>;
3796 qcom,smem-state-names 3250 qcom,smem-state-names = "stop";
3797 3251
3798 status = "disabled"; 3252 status = "disabled";
3799 3253
3800 glink-edge { 3254 glink-edge {
3801 interrupts-ex 3255 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3802 3256 IPCC_MPROC_SIGNAL_GLINK_QMP
3803 3257 IRQ_TYPE_EDGE_RISING>;
3804 mboxes = <&ip 3258 mboxes = <&ipcc IPCC_CLIENT_CDSP
3805 3259 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3806 3260
3807 label = "cdsp 3261 label = "cdsp";
3808 qcom,remote-p 3262 qcom,remote-pid = <5>;
3809 3263
3810 fastrpc { 3264 fastrpc {
3811 compa 3265 compatible = "qcom,fastrpc";
3812 qcom, 3266 qcom,glink-channels = "fastrpcglink-apps-dsp";
3813 label 3267 label = "cdsp";
3814 qcom, 3268 qcom,non-secure-domain;
3815 #addr 3269 #address-cells = <1>;
3816 #size 3270 #size-cells = <0>;
3817 3271
3818 compu 3272 compute-cb@1 {
3819 3273 compatible = "qcom,fastrpc-compute-cb";
3820 3274 reg = <1>;
3821 3275 iommus = <&apps_smmu 0x1001 0x0460>;
3822 }; 3276 };
3823 3277
3824 compu 3278 compute-cb@2 {
3825 3279 compatible = "qcom,fastrpc-compute-cb";
3826 3280 reg = <2>;
3827 3281 iommus = <&apps_smmu 0x1002 0x0460>;
3828 }; 3282 };
3829 3283
3830 compu 3284 compute-cb@3 {
3831 3285 compatible = "qcom,fastrpc-compute-cb";
3832 3286 reg = <3>;
3833 3287 iommus = <&apps_smmu 0x1003 0x0460>;
3834 }; 3288 };
3835 3289
3836 compu 3290 compute-cb@4 {
3837 3291 compatible = "qcom,fastrpc-compute-cb";
3838 3292 reg = <4>;
3839 3293 iommus = <&apps_smmu 0x1004 0x0460>;
3840 }; 3294 };
3841 3295
3842 compu 3296 compute-cb@5 {
3843 3297 compatible = "qcom,fastrpc-compute-cb";
3844 3298 reg = <5>;
3845 3299 iommus = <&apps_smmu 0x1005 0x0460>;
3846 }; 3300 };
3847 3301
3848 compu 3302 compute-cb@6 {
3849 3303 compatible = "qcom,fastrpc-compute-cb";
3850 3304 reg = <6>;
3851 3305 iommus = <&apps_smmu 0x1006 0x0460>;
3852 }; 3306 };
3853 3307
3854 compu 3308 compute-cb@7 {
3855 3309 compatible = "qcom,fastrpc-compute-cb";
3856 3310 reg = <7>;
3857 3311 iommus = <&apps_smmu 0x1007 0x0460>;
3858 }; 3312 };
3859 3313
3860 compu 3314 compute-cb@8 {
3861 3315 compatible = "qcom,fastrpc-compute-cb";
3862 3316 reg = <8>;
3863 3317 iommus = <&apps_smmu 0x1008 0x0460>;
3864 }; 3318 };
3865 3319
3866 /* no 3320 /* note: secure cb9 in downstream */
3867 }; 3321 };
3868 }; 3322 };
3869 }; 3323 };
3870 3324
>> 3325 sound: sound {
>> 3326 };
>> 3327
3871 usb_1_hsphy: phy@88e3000 { 3328 usb_1_hsphy: phy@88e3000 {
3872 compatible = "qcom,sm 3329 compatible = "qcom,sm8250-usb-hs-phy",
3873 "qcom,us 3330 "qcom,usb-snps-hs-7nm-phy";
3874 reg = <0 0x088e3000 0 3331 reg = <0 0x088e3000 0 0x400>;
3875 status = "disabled"; 3332 status = "disabled";
3876 #phy-cells = <0>; 3333 #phy-cells = <0>;
3877 3334
3878 clocks = <&rpmhcc RPM 3335 clocks = <&rpmhcc RPMH_CXO_CLK>;
3879 clock-names = "ref"; 3336 clock-names = "ref";
3880 3337
3881 resets = <&gcc GCC_QU 3338 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3882 }; 3339 };
3883 3340
3884 usb_2_hsphy: phy@88e4000 { 3341 usb_2_hsphy: phy@88e4000 {
3885 compatible = "qcom,sm 3342 compatible = "qcom,sm8250-usb-hs-phy",
3886 "qcom,us 3343 "qcom,usb-snps-hs-7nm-phy";
3887 reg = <0 0x088e4000 0 3344 reg = <0 0x088e4000 0 0x400>;
3888 status = "disabled"; 3345 status = "disabled";
3889 #phy-cells = <0>; 3346 #phy-cells = <0>;
3890 3347
3891 clocks = <&rpmhcc RPM 3348 clocks = <&rpmhcc RPMH_CXO_CLK>;
3892 clock-names = "ref"; 3349 clock-names = "ref";
3893 3350
3894 resets = <&gcc GCC_QU 3351 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3895 }; 3352 };
3896 3353
3897 usb_1_qmpphy: phy@88e8000 { !! 3354 usb_1_qmpphy: phy@88e9000 {
3898 compatible = "qcom,sm 3355 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3899 reg = <0 0x088e8000 0 !! 3356 reg = <0 0x088e9000 0 0x200>,
>> 3357 <0 0x088e8000 0 0x40>,
>> 3358 <0 0x088ea000 0 0x200>;
3900 status = "disabled"; 3359 status = "disabled";
>> 3360 #address-cells = <2>;
>> 3361 #size-cells = <2>;
>> 3362 ranges;
3901 3363
3902 clocks = <&gcc GCC_US 3364 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3903 <&rpmhcc RPM 3365 <&rpmhcc RPMH_CXO_CLK>,
3904 <&gcc GCC_US !! 3366 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3905 <&gcc GCC_US !! 3367 clock-names = "aux", "ref_clk_src", "com_aux";
3906 clock-names = "aux", <<
3907 "ref", <<
3908 "com_au <<
3909 "usb3_p <<
3910 3368
3911 resets = <&gcc GCC_US 3369 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3912 <&gcc GCC_US 3370 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3913 reset-names = "phy", 3371 reset-names = "phy", "common";
3914 3372
3915 #clock-cells = <1>; !! 3373 usb_1_ssphy: usb3-phy@88e9200 {
3916 #phy-cells = <1>; !! 3374 reg = <0 0x088e9200 0 0x200>,
3917 !! 3375 <0 0x088e9400 0 0x200>,
3918 orientation-switch; !! 3376 <0 0x088e9c00 0 0x400>,
3919 !! 3377 <0 0x088e9600 0 0x200>,
3920 ports { !! 3378 <0 0x088e9800 0 0x200>,
3921 #address-cell !! 3379 <0 0x088e9a00 0 0x100>;
3922 #size-cells = !! 3380 #clock-cells = <0>;
3923 !! 3381 #phy-cells = <0>;
3924 port@0 { !! 3382 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3925 reg = !! 3383 clock-names = "pipe0";
3926 usb_1 !! 3384 clock-output-names = "usb3_phy_pipe_clk_src";
3927 }; !! 3385 };
3928 <<
3929 port@1 { <<
3930 reg = <<
3931 <<
3932 usb_1 <<
3933 <<
3934 }; <<
3935 }; <<
3936 <<
3937 port@2 { <<
3938 reg = <<
3939 3386
3940 usb_1 !! 3387 dp_phy: dp-phy@88ea200 {
3941 }; !! 3388 reg = <0 0x088ea200 0 0x200>,
>> 3389 <0 0x088ea400 0 0x200>,
>> 3390 <0 0x088eaa00 0 0x200>,
>> 3391 <0 0x088ea600 0 0x200>,
>> 3392 <0 0x088ea800 0 0x200>;
>> 3393 #phy-cells = <0>;
>> 3394 #clock-cells = <1>;
3942 }; 3395 };
3943 }; 3396 };
3944 3397
3945 usb_2_qmpphy: phy@88eb000 { 3398 usb_2_qmpphy: phy@88eb000 {
3946 compatible = "qcom,sm 3399 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3947 reg = <0 0x088eb000 0 !! 3400 reg = <0 0x088eb000 0 0x200>;
>> 3401 status = "disabled";
>> 3402 #address-cells = <2>;
>> 3403 #size-cells = <2>;
>> 3404 ranges;
3948 3405
3949 clocks = <&gcc GCC_US 3406 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
>> 3407 <&rpmhcc RPMH_CXO_CLK>,
3950 <&gcc GCC_US 3408 <&gcc GCC_USB3_SEC_CLKREF_EN>,
3951 <&gcc GCC_US !! 3409 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3952 <&gcc GCC_US !! 3410 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3953 clock-names = "aux", <<
3954 "ref", <<
3955 "com_au <<
3956 "pipe"; <<
3957 clock-output-names = <<
3958 #clock-cells = <0>; <<
3959 #phy-cells = <0>; <<
3960 3411
3961 resets = <&gcc GCC_US !! 3412 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3962 <&gcc GCC_US !! 3413 <&gcc GCC_USB3_PHY_SEC_BCR>;
3963 reset-names = "phy", !! 3414 reset-names = "phy", "common";
3964 "phy_ph <<
3965 3415
3966 status = "disabled"; !! 3416 usb_2_ssphy: phy@88eb200 {
>> 3417 reg = <0 0x088eb200 0 0x200>,
>> 3418 <0 0x088eb400 0 0x200>,
>> 3419 <0 0x088eb800 0 0x800>;
>> 3420 #clock-cells = <0>;
>> 3421 #phy-cells = <0>;
>> 3422 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
>> 3423 clock-names = "pipe0";
>> 3424 clock-output-names = "usb3_uni_phy_pipe_clk_src";
>> 3425 };
3967 }; 3426 };
3968 3427
3969 sdhc_2: mmc@8804000 { 3428 sdhc_2: mmc@8804000 {
3970 compatible = "qcom,sm 3429 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3971 reg = <0 0x08804000 0 3430 reg = <0 0x08804000 0 0x1000>;
3972 3431
3973 interrupts = <GIC_SPI 3432 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3974 <GIC_SPI 3433 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3975 interrupt-names = "hc 3434 interrupt-names = "hc_irq", "pwr_irq";
3976 3435
3977 clocks = <&gcc GCC_SD 3436 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3978 <&gcc GCC_SD 3437 <&gcc GCC_SDCC2_APPS_CLK>,
3979 <&rpmhcc RPM 3438 <&rpmhcc RPMH_CXO_CLK>;
3980 clock-names = "iface" 3439 clock-names = "iface", "core", "xo";
3981 iommus = <&apps_smmu 3440 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x 3441 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x 3442 qcom,ddr-config = <0x80040868>;
3984 power-domains = <&rpm !! 3443 power-domains = <&rpmhpd SM8250_CX>;
3985 operating-points-v2 = 3444 operating-points-v2 = <&sdhc2_opp_table>;
3986 3445
3987 status = "disabled"; 3446 status = "disabled";
3988 3447
3989 sdhc2_opp_table: opp- 3448 sdhc2_opp_table: opp-table {
3990 compatible = 3449 compatible = "operating-points-v2";
3991 3450
3992 opp-19200000 3451 opp-19200000 {
3993 opp-h 3452 opp-hz = /bits/ 64 <19200000>;
3994 requi 3453 required-opps = <&rpmhpd_opp_min_svs>;
3995 }; 3454 };
3996 3455
3997 opp-50000000 3456 opp-50000000 {
3998 opp-h 3457 opp-hz = /bits/ 64 <50000000>;
3999 requi 3458 required-opps = <&rpmhpd_opp_low_svs>;
4000 }; 3459 };
4001 3460
4002 opp-100000000 3461 opp-100000000 {
4003 opp-h 3462 opp-hz = /bits/ 64 <100000000>;
4004 requi 3463 required-opps = <&rpmhpd_opp_svs>;
4005 }; 3464 };
4006 3465
4007 opp-202000000 3466 opp-202000000 {
4008 opp-h 3467 opp-hz = /bits/ 64 <202000000>;
4009 requi 3468 required-opps = <&rpmhpd_opp_svs_l1>;
4010 }; 3469 };
4011 }; 3470 };
4012 }; 3471 };
4013 3472
4014 pmu@9091000 { <<
4015 compatible = "qcom,sm <<
4016 reg = <0 0x09091000 0 <<
4017 <<
4018 interrupts = <GIC_SPI <<
4019 <<
4020 interconnects = <&mc_ <<
4021 <<
4022 operating-points-v2 = <<
4023 <<
4024 llcc_bwmon_opp_table: <<
4025 compatible = <<
4026 <<
4027 opp-800000 { <<
4028 opp-p <<
4029 }; <<
4030 <<
4031 opp-1200000 { <<
4032 opp-p <<
4033 }; <<
4034 <<
4035 opp-1804000 { <<
4036 opp-p <<
4037 }; <<
4038 <<
4039 opp-2188000 { <<
4040 opp-p <<
4041 }; <<
4042 <<
4043 opp-2724000 { <<
4044 opp-p <<
4045 }; <<
4046 <<
4047 opp-3072000 { <<
4048 opp-p <<
4049 }; <<
4050 <<
4051 opp-4068000 { <<
4052 opp-p <<
4053 }; <<
4054 <<
4055 /* 1353 MHz, <<
4056 <<
4057 opp-6220000 { <<
4058 opp-p <<
4059 }; <<
4060 <<
4061 opp-7216000 { <<
4062 opp-p <<
4063 }; <<
4064 <<
4065 opp-8368000 { <<
4066 opp-p <<
4067 }; <<
4068 <<
4069 /* LPDDR5 */ <<
4070 opp-10944000 <<
4071 opp-p <<
4072 }; <<
4073 }; <<
4074 }; <<
4075 <<
4076 pmu@90b6400 { <<
4077 compatible = "qcom,sm <<
4078 reg = <0 0x090b6400 0 <<
4079 <<
4080 interrupts = <GIC_SPI <<
4081 <<
4082 interconnects = <&gem <<
4083 operating-points-v2 = <<
4084 <<
4085 cpu_bwmon_opp_table: <<
4086 compatible = <<
4087 <<
4088 opp-800000 { <<
4089 opp-p <<
4090 }; <<
4091 <<
4092 opp-1804000 { <<
4093 opp-p <<
4094 }; <<
4095 <<
4096 opp-2188000 { <<
4097 opp-p <<
4098 }; <<
4099 <<
4100 opp-2724000 { <<
4101 opp-p <<
4102 }; <<
4103 <<
4104 opp-3072000 { <<
4105 opp-p <<
4106 }; <<
4107 <<
4108 /* 1017MHz, 1 <<
4109 <<
4110 opp-6220000 { <<
4111 opp-p <<
4112 }; <<
4113 <<
4114 opp-6832000 { <<
4115 opp-p <<
4116 }; <<
4117 <<
4118 opp-8368000 { <<
4119 opp-p <<
4120 }; <<
4121 <<
4122 /* 2133MHz, L <<
4123 <<
4124 /* LPDDR5 */ <<
4125 opp-10944000 <<
4126 opp-p <<
4127 }; <<
4128 <<
4129 /* LPDDR5 */ <<
4130 opp-12784000 <<
4131 opp-p <<
4132 }; <<
4133 }; <<
4134 }; <<
4135 <<
4136 dc_noc: interconnect@90c0000 3473 dc_noc: interconnect@90c0000 {
4137 compatible = "qcom,sm 3474 compatible = "qcom,sm8250-dc-noc";
4138 reg = <0 0x090c0000 0 3475 reg = <0 0x090c0000 0 0x4200>;
4139 #interconnect-cells = !! 3476 #interconnect-cells = <1>;
4140 qcom,bcm-voters = <&a 3477 qcom,bcm-voters = <&apps_bcm_voter>;
4141 }; 3478 };
4142 3479
4143 gem_noc: interconnect@9100000 3480 gem_noc: interconnect@9100000 {
4144 compatible = "qcom,sm 3481 compatible = "qcom,sm8250-gem-noc";
4145 reg = <0 0x09100000 0 3482 reg = <0 0x09100000 0 0xb4000>;
4146 #interconnect-cells = !! 3483 #interconnect-cells = <1>;
4147 qcom,bcm-voters = <&a 3484 qcom,bcm-voters = <&apps_bcm_voter>;
4148 }; 3485 };
4149 3486
4150 npu_noc: interconnect@9990000 3487 npu_noc: interconnect@9990000 {
4151 compatible = "qcom,sm 3488 compatible = "qcom,sm8250-npu-noc";
4152 reg = <0 0x09990000 0 3489 reg = <0 0x09990000 0 0x1600>;
4153 #interconnect-cells = !! 3490 #interconnect-cells = <1>;
4154 qcom,bcm-voters = <&a 3491 qcom,bcm-voters = <&apps_bcm_voter>;
4155 }; 3492 };
4156 3493
4157 usb_1: usb@a6f8800 { 3494 usb_1: usb@a6f8800 {
4158 compatible = "qcom,sm 3495 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4159 reg = <0 0x0a6f8800 0 3496 reg = <0 0x0a6f8800 0 0x400>;
4160 status = "disabled"; 3497 status = "disabled";
4161 #address-cells = <2>; 3498 #address-cells = <2>;
4162 #size-cells = <2>; 3499 #size-cells = <2>;
4163 ranges; 3500 ranges;
4164 dma-ranges; 3501 dma-ranges;
4165 3502
4166 clocks = <&gcc GCC_CF 3503 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
4167 <&gcc GCC_US 3504 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
4168 <&gcc GCC_AG 3505 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
4169 <&gcc GCC_US 3506 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
4170 <&gcc GCC_US 3507 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4171 <&gcc GCC_US 3508 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4172 clock-names = "cfg_no 3509 clock-names = "cfg_noc",
4173 "core", 3510 "core",
4174 "iface" 3511 "iface",
4175 "sleep" 3512 "sleep",
4176 "mock_u 3513 "mock_utmi",
4177 "xo"; 3514 "xo";
4178 3515
4179 assigned-clocks = <&g 3516 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4180 <&g 3517 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
4181 assigned-clock-rates 3518 assigned-clock-rates = <19200000>, <200000000>;
4182 3519
4183 interrupts-extended = !! 3520 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
4184 !! 3521 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
4185 <<
4186 3522 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
4187 !! 3523 <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
4188 interrupt-names = "pw !! 3524 interrupt-names = "hs_phy_irq",
4189 "hs !! 3525 "ss_phy_irq",
4190 "dp <<
4191 "dm 3526 "dm_hs_phy_irq",
4192 "ss !! 3527 "dp_hs_phy_irq";
4193 3528
4194 power-domains = <&gcc 3529 power-domains = <&gcc USB30_PRIM_GDSC>;
4195 wakeup-source; <<
4196 3530
4197 resets = <&gcc GCC_US 3531 resets = <&gcc GCC_USB30_PRIM_BCR>;
4198 3532
4199 interconnects = <&agg <<
4200 <&gem <<
4201 interconnect-names = <<
4202 <<
4203 usb_1_dwc3: usb@a6000 3533 usb_1_dwc3: usb@a600000 {
4204 compatible = 3534 compatible = "snps,dwc3";
4205 reg = <0 0x0a 3535 reg = <0 0x0a600000 0 0xcd00>;
4206 interrupts = 3536 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
4207 iommus = <&ap 3537 iommus = <&apps_smmu 0x0 0x0>;
4208 snps,dis_u2_s 3538 snps,dis_u2_susphy_quirk;
4209 snps,dis_enbl 3539 snps,dis_enblslpm_quirk;
4210 phys = <&usb_ !! 3540 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
4211 phy-names = " 3541 phy-names = "usb2-phy", "usb3-phy";
4212 <<
4213 ports { <<
4214 #addr <<
4215 #size <<
4216 <<
4217 port@ <<
4218 <<
4219 <<
4220 <<
4221 <<
4222 }; <<
4223 <<
4224 port@ <<
4225 <<
4226 <<
4227 <<
4228 <<
4229 <<
4230 }; <<
4231 }; <<
4232 }; 3542 };
4233 }; 3543 };
4234 3544
4235 system-cache-controller@92000 3545 system-cache-controller@9200000 {
4236 compatible = "qcom,sm 3546 compatible = "qcom,sm8250-llcc";
4237 reg = <0 0x09200000 0 !! 3547 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
4238 <0 0x09300000 0 !! 3548 reg-names = "llcc_base", "llcc_broadcast_base";
4239 <0 0x09600000 0 <<
4240 reg-names = "llcc0_ba <<
4241 "llcc3_ba <<
4242 }; 3549 };
4243 3550
4244 usb_2: usb@a8f8800 { 3551 usb_2: usb@a8f8800 {
4245 compatible = "qcom,sm 3552 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
4246 reg = <0 0x0a8f8800 0 3553 reg = <0 0x0a8f8800 0 0x400>;
4247 status = "disabled"; 3554 status = "disabled";
4248 #address-cells = <2>; 3555 #address-cells = <2>;
4249 #size-cells = <2>; 3556 #size-cells = <2>;
4250 ranges; 3557 ranges;
4251 dma-ranges; 3558 dma-ranges;
4252 3559
4253 clocks = <&gcc GCC_CF 3560 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
4254 <&gcc GCC_US 3561 <&gcc GCC_USB30_SEC_MASTER_CLK>,
4255 <&gcc GCC_AG 3562 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
4256 <&gcc GCC_US 3563 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
4257 <&gcc GCC_US 3564 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4258 <&gcc GCC_US 3565 <&gcc GCC_USB3_SEC_CLKREF_EN>;
4259 clock-names = "cfg_no 3566 clock-names = "cfg_noc",
4260 "core", 3567 "core",
4261 "iface" 3568 "iface",
4262 "sleep" 3569 "sleep",
4263 "mock_u 3570 "mock_utmi",
4264 "xo"; 3571 "xo";
4265 3572
4266 assigned-clocks = <&g 3573 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4267 <&g 3574 <&gcc GCC_USB30_SEC_MASTER_CLK>;
4268 assigned-clock-rates 3575 assigned-clock-rates = <19200000>, <200000000>;
4269 3576
4270 interrupts-extended = !! 3577 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
4271 !! 3578 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
4272 <<
4273 3579 <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
4274 !! 3580 <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
4275 interrupt-names = "pw !! 3581 interrupt-names = "hs_phy_irq",
4276 "hs !! 3582 "ss_phy_irq",
4277 "dp <<
4278 "dm 3583 "dm_hs_phy_irq",
4279 "ss !! 3584 "dp_hs_phy_irq";
4280 3585
4281 power-domains = <&gcc 3586 power-domains = <&gcc USB30_SEC_GDSC>;
4282 wakeup-source; <<
4283 3587
4284 resets = <&gcc GCC_US 3588 resets = <&gcc GCC_USB30_SEC_BCR>;
4285 3589
4286 interconnects = <&agg <<
4287 <&gem <<
4288 interconnect-names = <<
4289 <<
4290 usb_2_dwc3: usb@a8000 3590 usb_2_dwc3: usb@a800000 {
4291 compatible = 3591 compatible = "snps,dwc3";
4292 reg = <0 0x0a 3592 reg = <0 0x0a800000 0 0xcd00>;
4293 interrupts = 3593 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
4294 iommus = <&ap 3594 iommus = <&apps_smmu 0x20 0>;
4295 snps,dis_u2_s 3595 snps,dis_u2_susphy_quirk;
4296 snps,dis_enbl 3596 snps,dis_enblslpm_quirk;
4297 phys = <&usb_ !! 3597 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
4298 phy-names = " 3598 phy-names = "usb2-phy", "usb3-phy";
4299 }; 3599 };
4300 }; 3600 };
4301 3601
4302 venus: video-codec@aa00000 { 3602 venus: video-codec@aa00000 {
4303 compatible = "qcom,sm 3603 compatible = "qcom,sm8250-venus";
4304 reg = <0 0x0aa00000 0 3604 reg = <0 0x0aa00000 0 0x100000>;
4305 interrupts = <GIC_SPI 3605 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
4306 power-domains = <&vid 3606 power-domains = <&videocc MVS0C_GDSC>,
4307 <&vid 3607 <&videocc MVS0_GDSC>,
4308 <&rpm !! 3608 <&rpmhpd SM8250_MX>;
4309 power-domain-names = 3609 power-domain-names = "venus", "vcodec0", "mx";
4310 operating-points-v2 = 3610 operating-points-v2 = <&venus_opp_table>;
4311 3611
4312 clocks = <&gcc GCC_VI 3612 clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
4313 <&videocc VI 3613 <&videocc VIDEO_CC_MVS0C_CLK>,
4314 <&videocc VI 3614 <&videocc VIDEO_CC_MVS0_CLK>;
4315 clock-names = "iface" 3615 clock-names = "iface", "core", "vcodec0_core";
4316 3616
4317 interconnects = <&gem !! 3617 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>,
4318 <&mms !! 3618 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>;
4319 interconnect-names = 3619 interconnect-names = "cpu-cfg", "video-mem";
4320 3620
4321 iommus = <&apps_smmu 3621 iommus = <&apps_smmu 0x2100 0x0400>;
4322 memory-region = <&vid 3622 memory-region = <&video_mem>;
4323 3623
4324 resets = <&gcc GCC_VI 3624 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
4325 <&videocc VI 3625 <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
4326 reset-names = "bus", 3626 reset-names = "bus", "core";
4327 3627
4328 status = "disabled"; 3628 status = "disabled";
4329 3629
4330 video-decoder { 3630 video-decoder {
4331 compatible = 3631 compatible = "venus-decoder";
4332 }; 3632 };
4333 3633
4334 video-encoder { 3634 video-encoder {
4335 compatible = 3635 compatible = "venus-encoder";
4336 }; 3636 };
4337 3637
4338 venus_opp_table: opp- 3638 venus_opp_table: opp-table {
4339 compatible = 3639 compatible = "operating-points-v2";
4340 3640
4341 opp-720000000 3641 opp-720000000 {
4342 opp-h 3642 opp-hz = /bits/ 64 <720000000>;
4343 requi 3643 required-opps = <&rpmhpd_opp_low_svs>;
4344 }; 3644 };
4345 3645
4346 opp-101400000 3646 opp-1014000000 {
4347 opp-h 3647 opp-hz = /bits/ 64 <1014000000>;
4348 requi 3648 required-opps = <&rpmhpd_opp_svs>;
4349 }; 3649 };
4350 3650
4351 opp-109800000 3651 opp-1098000000 {
4352 opp-h 3652 opp-hz = /bits/ 64 <1098000000>;
4353 requi 3653 required-opps = <&rpmhpd_opp_svs_l1>;
4354 }; 3654 };
4355 3655
4356 opp-133200000 3656 opp-1332000000 {
4357 opp-h 3657 opp-hz = /bits/ 64 <1332000000>;
4358 requi 3658 required-opps = <&rpmhpd_opp_nom>;
4359 }; 3659 };
4360 }; 3660 };
4361 }; 3661 };
4362 3662
4363 videocc: clock-controller@abf 3663 videocc: clock-controller@abf0000 {
4364 compatible = "qcom,sm 3664 compatible = "qcom,sm8250-videocc";
4365 reg = <0 0x0abf0000 0 3665 reg = <0 0x0abf0000 0 0x10000>;
4366 clocks = <&gcc GCC_VI 3666 clocks = <&gcc GCC_VIDEO_AHB_CLK>,
4367 <&rpmhcc RPM 3667 <&rpmhcc RPMH_CXO_CLK>,
4368 <&rpmhcc RPM 3668 <&rpmhcc RPMH_CXO_CLK_A>;
4369 power-domains = <&rpm !! 3669 power-domains = <&rpmhpd SM8250_MMCX>;
4370 required-opps = <&rpm 3670 required-opps = <&rpmhpd_opp_low_svs>;
4371 clock-names = "iface" 3671 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4372 #clock-cells = <1>; 3672 #clock-cells = <1>;
4373 #reset-cells = <1>; 3673 #reset-cells = <1>;
4374 #power-domain-cells = 3674 #power-domain-cells = <1>;
4375 }; 3675 };
4376 3676
4377 cci0: cci@ac4f000 { 3677 cci0: cci@ac4f000 {
4378 compatible = "qcom,sm !! 3678 compatible = "qcom,sm8250-cci";
4379 #address-cells = <1>; 3679 #address-cells = <1>;
4380 #size-cells = <0>; 3680 #size-cells = <0>;
4381 3681
4382 reg = <0 0x0ac4f000 0 3682 reg = <0 0x0ac4f000 0 0x1000>;
4383 interrupts = <GIC_SPI 3683 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
4384 power-domains = <&cam 3684 power-domains = <&camcc TITAN_TOP_GDSC>;
4385 3685
4386 clocks = <&camcc CAM_ 3686 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4387 <&camcc CAM_ 3687 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4388 <&camcc CAM_ 3688 <&camcc CAM_CC_CPAS_AHB_CLK>,
4389 <&camcc CAM_ 3689 <&camcc CAM_CC_CCI_0_CLK>,
4390 <&camcc CAM_ 3690 <&camcc CAM_CC_CCI_0_CLK_SRC>;
4391 clock-names = "camnoc 3691 clock-names = "camnoc_axi",
4392 "slow_a 3692 "slow_ahb_src",
4393 "cpas_a 3693 "cpas_ahb",
4394 "cci", 3694 "cci",
4395 "cci_sr 3695 "cci_src";
4396 3696
4397 pinctrl-0 = <&cci0_de 3697 pinctrl-0 = <&cci0_default>;
4398 pinctrl-1 = <&cci0_sl 3698 pinctrl-1 = <&cci0_sleep>;
4399 pinctrl-names = "defa 3699 pinctrl-names = "default", "sleep";
4400 3700
4401 status = "disabled"; 3701 status = "disabled";
4402 3702
4403 cci0_i2c0: i2c-bus@0 3703 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>; 3704 reg = <0>;
4405 clock-frequen 3705 clock-frequency = <1000000>;
4406 #address-cell 3706 #address-cells = <1>;
4407 #size-cells = 3707 #size-cells = <0>;
4408 }; 3708 };
4409 3709
4410 cci0_i2c1: i2c-bus@1 3710 cci0_i2c1: i2c-bus@1 {
4411 reg = <1>; 3711 reg = <1>;
4412 clock-frequen 3712 clock-frequency = <1000000>;
4413 #address-cell 3713 #address-cells = <1>;
4414 #size-cells = 3714 #size-cells = <0>;
4415 }; 3715 };
4416 }; 3716 };
4417 3717
4418 cci1: cci@ac50000 { 3718 cci1: cci@ac50000 {
4419 compatible = "qcom,sm !! 3719 compatible = "qcom,sm8250-cci";
4420 #address-cells = <1>; 3720 #address-cells = <1>;
4421 #size-cells = <0>; 3721 #size-cells = <0>;
4422 3722
4423 reg = <0 0x0ac50000 0 3723 reg = <0 0x0ac50000 0 0x1000>;
4424 interrupts = <GIC_SPI 3724 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
4425 power-domains = <&cam 3725 power-domains = <&camcc TITAN_TOP_GDSC>;
4426 3726
4427 clocks = <&camcc CAM_ 3727 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4428 <&camcc CAM_ 3728 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4429 <&camcc CAM_ 3729 <&camcc CAM_CC_CPAS_AHB_CLK>,
4430 <&camcc CAM_ 3730 <&camcc CAM_CC_CCI_1_CLK>,
4431 <&camcc CAM_ 3731 <&camcc CAM_CC_CCI_1_CLK_SRC>;
4432 clock-names = "camnoc 3732 clock-names = "camnoc_axi",
4433 "slow_a 3733 "slow_ahb_src",
4434 "cpas_a 3734 "cpas_ahb",
4435 "cci", 3735 "cci",
4436 "cci_sr 3736 "cci_src";
4437 3737
4438 pinctrl-0 = <&cci1_de 3738 pinctrl-0 = <&cci1_default>;
4439 pinctrl-1 = <&cci1_sl 3739 pinctrl-1 = <&cci1_sleep>;
4440 pinctrl-names = "defa 3740 pinctrl-names = "default", "sleep";
4441 3741
4442 status = "disabled"; 3742 status = "disabled";
4443 3743
4444 cci1_i2c0: i2c-bus@0 3744 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>; 3745 reg = <0>;
4446 clock-frequen 3746 clock-frequency = <1000000>;
4447 #address-cell 3747 #address-cells = <1>;
4448 #size-cells = 3748 #size-cells = <0>;
4449 }; 3749 };
4450 3750
4451 cci1_i2c1: i2c-bus@1 3751 cci1_i2c1: i2c-bus@1 {
4452 reg = <1>; 3752 reg = <1>;
4453 clock-frequen 3753 clock-frequency = <1000000>;
4454 #address-cell 3754 #address-cells = <1>;
4455 #size-cells = 3755 #size-cells = <0>;
4456 }; 3756 };
4457 }; 3757 };
4458 3758
4459 camss: camss@ac6a000 { 3759 camss: camss@ac6a000 {
4460 compatible = "qcom,sm 3760 compatible = "qcom,sm8250-camss";
4461 status = "disabled"; 3761 status = "disabled";
4462 3762
4463 reg = <0 0x0ac6a000 0 !! 3763 reg = <0 0xac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 !! 3764 <0 0xac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 !! 3765 <0 0xac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 !! 3766 <0 0xac70000 0 0x1000>,
4467 <0 0x0ac72000 0 !! 3767 <0 0xac72000 0 0x1000>,
4468 <0 0x0ac74000 0 !! 3768 <0 0xac74000 0 0x1000>,
4469 <0 0x0acb4000 0 !! 3769 <0 0xacb4000 0 0xd000>,
4470 <0 0x0acc3000 0 !! 3770 <0 0xacc3000 0 0xd000>,
4471 <0 0x0acd9000 0 !! 3771 <0 0xacd9000 0 0x2200>,
4472 <0 0x0acdb200 0 !! 3772 <0 0xacdb200 0 0x2200>;
4473 reg-names = "csiphy0" 3773 reg-names = "csiphy0",
4474 "csiphy1" 3774 "csiphy1",
4475 "csiphy2" 3775 "csiphy2",
4476 "csiphy3" 3776 "csiphy3",
4477 "csiphy4" 3777 "csiphy4",
4478 "csiphy5" 3778 "csiphy5",
4479 "vfe0", 3779 "vfe0",
4480 "vfe1", 3780 "vfe1",
4481 "vfe_lite 3781 "vfe_lite0",
4482 "vfe_lite 3782 "vfe_lite1";
4483 3783
4484 interrupts = <GIC_SPI 3784 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
4485 <GIC_SPI 3785 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
4486 <GIC_SPI 3786 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
4487 <GIC_SPI 3787 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
4488 <GIC_SPI 3788 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
4489 <GIC_SPI 3789 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
4490 <GIC_SPI 3790 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
4491 <GIC_SPI 3791 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
4492 <GIC_SPI 3792 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
4493 <GIC_SPI 3793 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
4494 <GIC_SPI 3794 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
4495 <GIC_SPI 3795 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
4496 <GIC_SPI 3796 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
4497 <GIC_SPI 3797 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
4498 interrupt-names = "cs 3798 interrupt-names = "csiphy0",
4499 "cs 3799 "csiphy1",
4500 "cs 3800 "csiphy2",
4501 "cs 3801 "csiphy3",
4502 "cs 3802 "csiphy4",
4503 "cs 3803 "csiphy5",
4504 "cs 3804 "csid0",
4505 "cs 3805 "csid1",
4506 "cs 3806 "csid2",
4507 "cs 3807 "csid3",
4508 "vf 3808 "vfe0",
4509 "vf 3809 "vfe1",
4510 "vf 3810 "vfe_lite0",
4511 "vf 3811 "vfe_lite1";
4512 3812
4513 power-domains = <&cam 3813 power-domains = <&camcc IFE_0_GDSC>,
4514 <&cam 3814 <&camcc IFE_1_GDSC>,
4515 <&cam 3815 <&camcc TITAN_TOP_GDSC>;
4516 3816
4517 clocks = <&gcc GCC_CA 3817 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4518 <&gcc GCC_CA 3818 <&gcc GCC_CAMERA_HF_AXI_CLK>,
4519 <&gcc GCC_CA 3819 <&gcc GCC_CAMERA_SF_AXI_CLK>,
4520 <&camcc CAM_ 3820 <&camcc CAM_CC_CAMNOC_AXI_CLK>,
4521 <&camcc CAM_ 3821 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
4522 <&camcc CAM_ 3822 <&camcc CAM_CC_CORE_AHB_CLK>,
4523 <&camcc CAM_ 3823 <&camcc CAM_CC_CPAS_AHB_CLK>,
4524 <&camcc CAM_ 3824 <&camcc CAM_CC_CSIPHY0_CLK>,
4525 <&camcc CAM_ 3825 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
4526 <&camcc CAM_ 3826 <&camcc CAM_CC_CSIPHY1_CLK>,
4527 <&camcc CAM_ 3827 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
4528 <&camcc CAM_ 3828 <&camcc CAM_CC_CSIPHY2_CLK>,
4529 <&camcc CAM_ 3829 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
4530 <&camcc CAM_ 3830 <&camcc CAM_CC_CSIPHY3_CLK>,
4531 <&camcc CAM_ 3831 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
4532 <&camcc CAM_ 3832 <&camcc CAM_CC_CSIPHY4_CLK>,
4533 <&camcc CAM_ 3833 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
4534 <&camcc CAM_ 3834 <&camcc CAM_CC_CSIPHY5_CLK>,
4535 <&camcc CAM_ 3835 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
4536 <&camcc CAM_ 3836 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
4537 <&camcc CAM_ 3837 <&camcc CAM_CC_IFE_0_AHB_CLK>,
4538 <&camcc CAM_ 3838 <&camcc CAM_CC_IFE_0_AXI_CLK>,
4539 <&camcc CAM_ 3839 <&camcc CAM_CC_IFE_0_CLK>,
4540 <&camcc CAM_ 3840 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
4541 <&camcc CAM_ 3841 <&camcc CAM_CC_IFE_0_CSID_CLK>,
4542 <&camcc CAM_ 3842 <&camcc CAM_CC_IFE_0_AREG_CLK>,
4543 <&camcc CAM_ 3843 <&camcc CAM_CC_IFE_1_AHB_CLK>,
4544 <&camcc CAM_ 3844 <&camcc CAM_CC_IFE_1_AXI_CLK>,
4545 <&camcc CAM_ 3845 <&camcc CAM_CC_IFE_1_CLK>,
4546 <&camcc CAM_ 3846 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
4547 <&camcc CAM_ 3847 <&camcc CAM_CC_IFE_1_CSID_CLK>,
4548 <&camcc CAM_ 3848 <&camcc CAM_CC_IFE_1_AREG_CLK>,
4549 <&camcc CAM_ 3849 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
4550 <&camcc CAM_ 3850 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,
4551 <&camcc CAM_ 3851 <&camcc CAM_CC_IFE_LITE_CLK>,
4552 <&camcc CAM_ 3852 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
4553 <&camcc CAM_ 3853 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
4554 3854
4555 clock-names = "cam_ah 3855 clock-names = "cam_ahb_clk",
4556 "cam_hf 3856 "cam_hf_axi",
4557 "cam_sf 3857 "cam_sf_axi",
4558 "camnoc 3858 "camnoc_axi",
4559 "camnoc 3859 "camnoc_axi_src",
4560 "core_a 3860 "core_ahb",
4561 "cpas_a 3861 "cpas_ahb",
4562 "csiphy 3862 "csiphy0",
4563 "csiphy 3863 "csiphy0_timer",
4564 "csiphy 3864 "csiphy1",
4565 "csiphy 3865 "csiphy1_timer",
4566 "csiphy 3866 "csiphy2",
4567 "csiphy 3867 "csiphy2_timer",
4568 "csiphy 3868 "csiphy3",
4569 "csiphy 3869 "csiphy3_timer",
4570 "csiphy 3870 "csiphy4",
4571 "csiphy 3871 "csiphy4_timer",
4572 "csiphy 3872 "csiphy5",
4573 "csiphy 3873 "csiphy5_timer",
4574 "slow_a 3874 "slow_ahb_src",
4575 "vfe0_a 3875 "vfe0_ahb",
4576 "vfe0_a 3876 "vfe0_axi",
4577 "vfe0", 3877 "vfe0",
4578 "vfe0_c 3878 "vfe0_cphy_rx",
4579 "vfe0_c 3879 "vfe0_csid",
4580 "vfe0_a 3880 "vfe0_areg",
4581 "vfe1_a 3881 "vfe1_ahb",
4582 "vfe1_a 3882 "vfe1_axi",
4583 "vfe1", 3883 "vfe1",
4584 "vfe1_c 3884 "vfe1_cphy_rx",
4585 "vfe1_c 3885 "vfe1_csid",
4586 "vfe1_a 3886 "vfe1_areg",
4587 "vfe_li 3887 "vfe_lite_ahb",
4588 "vfe_li 3888 "vfe_lite_axi",
4589 "vfe_li 3889 "vfe_lite",
4590 "vfe_li 3890 "vfe_lite_cphy_rx",
4591 "vfe_li 3891 "vfe_lite_csid";
4592 3892
4593 iommus = <&apps_smmu 3893 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 3894 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 3895 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 3896 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 3897 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 3898 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 3899 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 3900 <&apps_smmu 0xc41 0x400>;
4601 3901
4602 interconnects = <&gem !! 3902 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,
4603 <&mms !! 3903 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,
4604 <&mms !! 3904 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,
4605 <&mms !! 3905 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;
4606 interconnect-names = 3906 interconnect-names = "cam_ahb",
4607 3907 "cam_hf_0_mnoc",
4608 3908 "cam_sf_0_mnoc",
4609 3909 "cam_sf_icp_mnoc";
4610 3910
4611 ports { 3911 ports {
4612 #address-cell 3912 #address-cells = <1>;
4613 #size-cells = 3913 #size-cells = <0>;
4614 3914
4615 port@0 { 3915 port@0 {
4616 reg = 3916 reg = <0>;
4617 }; 3917 };
4618 3918
4619 port@1 { 3919 port@1 {
4620 reg = 3920 reg = <1>;
4621 }; 3921 };
4622 3922
4623 port@2 { 3923 port@2 {
4624 reg = 3924 reg = <2>;
4625 }; 3925 };
4626 3926
4627 port@3 { 3927 port@3 {
4628 reg = 3928 reg = <3>;
4629 }; 3929 };
4630 3930
4631 port@4 { 3931 port@4 {
4632 reg = 3932 reg = <4>;
4633 }; 3933 };
4634 3934
4635 port@5 { 3935 port@5 {
4636 reg = 3936 reg = <5>;
4637 }; 3937 };
4638 }; 3938 };
4639 }; 3939 };
4640 3940
4641 camcc: clock-controller@ad000 3941 camcc: clock-controller@ad00000 {
4642 compatible = "qcom,sm 3942 compatible = "qcom,sm8250-camcc";
4643 reg = <0 0x0ad00000 0 3943 reg = <0 0x0ad00000 0 0x10000>;
4644 clocks = <&gcc GCC_CA 3944 clocks = <&gcc GCC_CAMERA_AHB_CLK>,
4645 <&rpmhcc RPM 3945 <&rpmhcc RPMH_CXO_CLK>,
4646 <&rpmhcc RPM 3946 <&rpmhcc RPMH_CXO_CLK_A>,
4647 <&sleep_clk> 3947 <&sleep_clk>;
4648 clock-names = "iface" 3948 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4649 power-domains = <&rpm !! 3949 power-domains = <&rpmhpd SM8250_MMCX>;
4650 required-opps = <&rpm 3950 required-opps = <&rpmhpd_opp_low_svs>;
4651 status = "disabled"; 3951 status = "disabled";
4652 #clock-cells = <1>; 3952 #clock-cells = <1>;
4653 #reset-cells = <1>; 3953 #reset-cells = <1>;
4654 #power-domain-cells = 3954 #power-domain-cells = <1>;
4655 }; 3955 };
4656 3956
4657 mdss: display-subsystem@ae000 !! 3957 mdss: mdss@ae00000 {
4658 compatible = "qcom,sm 3958 compatible = "qcom,sm8250-mdss";
4659 reg = <0 0x0ae00000 0 3959 reg = <0 0x0ae00000 0 0x1000>;
4660 reg-names = "mdss"; 3960 reg-names = "mdss";
4661 3961
4662 interconnects = <&mms !! 3962 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
4663 <&mms !! 3963 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
4664 interconnect-names = 3964 interconnect-names = "mdp0-mem", "mdp1-mem";
4665 3965
4666 power-domains = <&dis 3966 power-domains = <&dispcc MDSS_GDSC>;
4667 3967
4668 clocks = <&dispcc DIS 3968 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4669 <&gcc GCC_DI 3969 <&gcc GCC_DISP_HF_AXI_CLK>,
4670 <&gcc GCC_DI 3970 <&gcc GCC_DISP_SF_AXI_CLK>,
4671 <&dispcc DIS 3971 <&dispcc DISP_CC_MDSS_MDP_CLK>;
4672 clock-names = "iface" 3972 clock-names = "iface", "bus", "nrt_bus", "core";
4673 3973
4674 interrupts = <GIC_SPI 3974 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4675 interrupt-controller; 3975 interrupt-controller;
4676 #interrupt-cells = <1 3976 #interrupt-cells = <1>;
4677 3977
4678 iommus = <&apps_smmu 3978 iommus = <&apps_smmu 0x820 0x402>;
4679 3979
4680 status = "disabled"; 3980 status = "disabled";
4681 3981
4682 #address-cells = <2>; 3982 #address-cells = <2>;
4683 #size-cells = <2>; 3983 #size-cells = <2>;
4684 ranges; 3984 ranges;
4685 3985
4686 mdss_mdp: display-con 3986 mdss_mdp: display-controller@ae01000 {
4687 compatible = 3987 compatible = "qcom,sm8250-dpu";
4688 reg = <0 0x0a 3988 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0a 3989 <0 0x0aeb0000 0 0x2008>;
4690 reg-names = " 3990 reg-names = "mdp", "vbif";
4691 3991
4692 clocks = <&di 3992 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4693 <&gc 3993 <&gcc GCC_DISP_HF_AXI_CLK>,
4694 <&di 3994 <&dispcc DISP_CC_MDSS_MDP_CLK>,
4695 <&di 3995 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4696 clock-names = 3996 clock-names = "iface", "bus", "core", "vsync";
4697 3997
4698 assigned-cloc 3998 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4699 assigned-cloc 3999 assigned-clock-rates = <19200000>;
4700 4000
4701 operating-poi 4001 operating-points-v2 = <&mdp_opp_table>;
4702 power-domains !! 4002 power-domains = <&rpmhpd SM8250_MMCX>;
4703 4003
4704 interrupt-par 4004 interrupt-parent = <&mdss>;
4705 interrupts = 4005 interrupts = <0>;
4706 4006
4707 ports { 4007 ports {
4708 #addr 4008 #address-cells = <1>;
4709 #size 4009 #size-cells = <0>;
4710 4010
4711 port@ 4011 port@0 {
4712 4012 reg = <0>;
4713 4013 dpu_intf1_out: endpoint {
4714 !! 4014 remote-endpoint = <&dsi0_in>;
4715 4015 };
4716 }; 4016 };
4717 4017
4718 port@ 4018 port@1 {
4719 4019 reg = <1>;
4720 4020 dpu_intf2_out: endpoint {
4721 !! 4021 remote-endpoint = <&dsi1_in>;
4722 <<
4723 }; <<
4724 <<
4725 port@ <<
4726 <<
4727 <<
4728 <<
4729 <<
4730 4022 };
4731 }; 4023 };
4732 }; 4024 };
4733 4025
4734 mdp_opp_table 4026 mdp_opp_table: opp-table {
4735 compa 4027 compatible = "operating-points-v2";
4736 4028
4737 opp-2 4029 opp-200000000 {
4738 4030 opp-hz = /bits/ 64 <200000000>;
4739 4031 required-opps = <&rpmhpd_opp_low_svs>;
4740 }; 4032 };
4741 4033
4742 opp-3 4034 opp-300000000 {
4743 4035 opp-hz = /bits/ 64 <300000000>;
4744 4036 required-opps = <&rpmhpd_opp_svs>;
4745 }; 4037 };
4746 4038
4747 opp-3 4039 opp-345000000 {
4748 4040 opp-hz = /bits/ 64 <345000000>;
4749 4041 required-opps = <&rpmhpd_opp_svs_l1>;
4750 }; 4042 };
4751 4043
4752 opp-4 4044 opp-460000000 {
4753 4045 opp-hz = /bits/ 64 <460000000>;
4754 4046 required-opps = <&rpmhpd_opp_nom>;
4755 }; 4047 };
4756 }; 4048 };
4757 }; 4049 };
4758 4050
4759 mdss_dp: displayport- !! 4051 dsi0: dsi@ae94000 {
4760 compatible = !! 4052 compatible = "qcom,mdss-dsi-ctrl";
4761 reg = <0 0xae <<
4762 <0 0xae <<
4763 <0 0xae <<
4764 <0 0xae <<
4765 <0 0xae <<
4766 interrupt-par <<
4767 interrupts = <<
4768 clocks = <&di <<
4769 <&di <<
4770 <&di <<
4771 <&di <<
4772 <&di <<
4773 clock-names = <<
4774 <<
4775 <<
4776 <<
4777 <<
4778 <<
4779 assigned-cloc <<
4780 <<
4781 assigned-cloc <<
4782 <<
4783 <<
4784 phys = <&usb_ <<
4785 phy-names = " <<
4786 <<
4787 #sound-dai-ce <<
4788 <<
4789 operating-poi <<
4790 power-domains <<
4791 <<
4792 status = "dis <<
4793 <<
4794 ports { <<
4795 #addr <<
4796 #size <<
4797 <<
4798 port@ <<
4799 <<
4800 <<
4801 <<
4802 <<
4803 }; <<
4804 <<
4805 port@ <<
4806 <<
4807 <<
4808 <<
4809 <<
4810 }; <<
4811 }; <<
4812 <<
4813 dp_opp_table: <<
4814 compa <<
4815 <<
4816 opp-1 <<
4817 <<
4818 <<
4819 }; <<
4820 <<
4821 opp-2 <<
4822 <<
4823 <<
4824 }; <<
4825 <<
4826 opp-5 <<
4827 <<
4828 <<
4829 }; <<
4830 <<
4831 opp-8 <<
4832 <<
4833 <<
4834 }; <<
4835 }; <<
4836 }; <<
4837 <<
4838 mdss_dsi0: dsi@ae9400 <<
4839 compatible = <<
4840 <<
4841 reg = <0 0x0a 4053 reg = <0 0x0ae94000 0 0x400>;
4842 reg-names = " 4054 reg-names = "dsi_ctrl";
4843 4055
4844 interrupt-par 4056 interrupt-parent = <&mdss>;
4845 interrupts = 4057 interrupts = <4>;
4846 4058
4847 clocks = <&di 4059 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
4848 <&di 4060 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
4849 <&di 4061 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
4850 <&di 4062 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
4851 <&di 4063 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4852 <&gcc 4064 <&gcc GCC_DISP_HF_AXI_CLK>;
4853 clock-names = 4065 clock-names = "byte",
4854 4066 "byte_intf",
4855 4067 "pixel",
4856 4068 "core",
4857 4069 "iface",
4858 4070 "bus";
4859 4071
4860 assigned-cloc 4072 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4861 assigned-cloc !! 4073 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
4862 4074
4863 operating-poi 4075 operating-points-v2 = <&dsi_opp_table>;
4864 power-domains !! 4076 power-domains = <&rpmhpd SM8250_MMCX>;
4865 4077
4866 phys = <&mdss !! 4078 phys = <&dsi0_phy>;
4867 4079
4868 status = "dis 4080 status = "disabled";
4869 4081
4870 #address-cell 4082 #address-cells = <1>;
4871 #size-cells = 4083 #size-cells = <0>;
4872 4084
4873 ports { 4085 ports {
4874 #addr 4086 #address-cells = <1>;
4875 #size 4087 #size-cells = <0>;
4876 4088
4877 port@ 4089 port@0 {
4878 4090 reg = <0>;
4879 !! 4091 dsi0_in: endpoint {
4880 4092 remote-endpoint = <&dpu_intf1_out>;
4881 4093 };
4882 }; 4094 };
4883 4095
4884 port@ 4096 port@1 {
4885 4097 reg = <1>;
4886 !! 4098 dsi0_out: endpoint {
4887 4099 };
4888 }; 4100 };
4889 }; 4101 };
4890 4102
4891 dsi_opp_table 4103 dsi_opp_table: opp-table {
4892 compa 4104 compatible = "operating-points-v2";
4893 4105
4894 opp-1 4106 opp-187500000 {
4895 4107 opp-hz = /bits/ 64 <187500000>;
4896 4108 required-opps = <&rpmhpd_opp_low_svs>;
4897 }; 4109 };
4898 4110
4899 opp-3 4111 opp-300000000 {
4900 4112 opp-hz = /bits/ 64 <300000000>;
4901 4113 required-opps = <&rpmhpd_opp_svs>;
4902 }; 4114 };
4903 4115
4904 opp-3 4116 opp-358000000 {
4905 4117 opp-hz = /bits/ 64 <358000000>;
4906 4118 required-opps = <&rpmhpd_opp_svs_l1>;
4907 }; 4119 };
4908 }; 4120 };
4909 }; 4121 };
4910 4122
4911 mdss_dsi0_phy: phy@ae !! 4123 dsi0_phy: phy@ae94400 {
4912 compatible = 4124 compatible = "qcom,dsi-phy-7nm";
4913 reg = <0 0x0a 4125 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0a 4126 <0 0x0ae94600 0 0x280>,
4915 <0 0x0a 4127 <0 0x0ae94900 0 0x260>;
4916 reg-names = " 4128 reg-names = "dsi_phy",
4917 " 4129 "dsi_phy_lane",
4918 " 4130 "dsi_pll";
4919 4131
4920 #clock-cells 4132 #clock-cells = <1>;
4921 #phy-cells = 4133 #phy-cells = <0>;
4922 4134
4923 clocks = <&di 4135 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4924 <&rp 4136 <&rpmhcc RPMH_CXO_CLK>;
4925 clock-names = 4137 clock-names = "iface", "ref";
4926 4138
4927 status = "dis 4139 status = "disabled";
4928 }; 4140 };
4929 4141
4930 mdss_dsi1: dsi@ae9600 !! 4142 dsi1: dsi@ae96000 {
4931 compatible = !! 4143 compatible = "qcom,mdss-dsi-ctrl";
4932 <<
4933 reg = <0 0x0a 4144 reg = <0 0x0ae96000 0 0x400>;
4934 reg-names = " 4145 reg-names = "dsi_ctrl";
4935 4146
4936 interrupt-par 4147 interrupt-parent = <&mdss>;
4937 interrupts = 4148 interrupts = <5>;
4938 4149
4939 clocks = <&di 4150 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
4940 <&di 4151 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
4941 <&di 4152 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
4942 <&di 4153 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
4943 <&di 4154 <&dispcc DISP_CC_MDSS_AHB_CLK>,
4944 <&gc 4155 <&gcc GCC_DISP_HF_AXI_CLK>;
4945 clock-names = 4156 clock-names = "byte",
4946 4157 "byte_intf",
4947 4158 "pixel",
4948 4159 "core",
4949 4160 "iface",
4950 4161 "bus";
4951 4162
4952 assigned-cloc 4163 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4953 assigned-cloc !! 4164 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
4954 4165
4955 operating-poi 4166 operating-points-v2 = <&dsi_opp_table>;
4956 power-domains !! 4167 power-domains = <&rpmhpd SM8250_MMCX>;
4957 4168
4958 phys = <&mdss !! 4169 phys = <&dsi1_phy>;
4959 4170
4960 status = "dis 4171 status = "disabled";
4961 4172
4962 #address-cell 4173 #address-cells = <1>;
4963 #size-cells = 4174 #size-cells = <0>;
4964 4175
4965 ports { 4176 ports {
4966 #addr 4177 #address-cells = <1>;
4967 #size 4178 #size-cells = <0>;
4968 4179
4969 port@ 4180 port@0 {
4970 4181 reg = <0>;
4971 !! 4182 dsi1_in: endpoint {
4972 4183 remote-endpoint = <&dpu_intf2_out>;
4973 4184 };
4974 }; 4185 };
4975 4186
4976 port@ 4187 port@1 {
4977 4188 reg = <1>;
4978 !! 4189 dsi1_out: endpoint {
4979 4190 };
4980 }; 4191 };
4981 }; 4192 };
4982 }; 4193 };
4983 4194
4984 mdss_dsi1_phy: phy@ae !! 4195 dsi1_phy: phy@ae96400 {
4985 compatible = 4196 compatible = "qcom,dsi-phy-7nm";
4986 reg = <0 0x0a 4197 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0a 4198 <0 0x0ae96600 0 0x280>,
4988 <0 0x0a 4199 <0 0x0ae96900 0 0x260>;
4989 reg-names = " 4200 reg-names = "dsi_phy",
4990 " 4201 "dsi_phy_lane",
4991 " 4202 "dsi_pll";
4992 4203
4993 #clock-cells 4204 #clock-cells = <1>;
4994 #phy-cells = 4205 #phy-cells = <0>;
4995 4206
4996 clocks = <&di 4207 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4997 <&rp 4208 <&rpmhcc RPMH_CXO_CLK>;
4998 clock-names = 4209 clock-names = "iface", "ref";
4999 4210
5000 status = "dis 4211 status = "disabled";
5001 }; 4212 };
5002 }; 4213 };
5003 4214
5004 dispcc: clock-controller@af00 4215 dispcc: clock-controller@af00000 {
5005 compatible = "qcom,sm 4216 compatible = "qcom,sm8250-dispcc";
5006 reg = <0 0x0af00000 0 4217 reg = <0 0x0af00000 0 0x10000>;
5007 power-domains = <&rpm !! 4218 power-domains = <&rpmhpd SM8250_MMCX>;
5008 required-opps = <&rpm 4219 required-opps = <&rpmhpd_opp_low_svs>;
5009 clocks = <&rpmhcc RPM 4220 clocks = <&rpmhcc RPMH_CXO_CLK>,
5010 <&mdss_dsi0_ !! 4221 <&dsi0_phy 0>,
5011 <&mdss_dsi0_ !! 4222 <&dsi0_phy 1>,
5012 <&mdss_dsi1_ !! 4223 <&dsi1_phy 0>,
5013 <&mdss_dsi1_ !! 4224 <&dsi1_phy 1>,
5014 <&usb_1_qmpp !! 4225 <&dp_phy 0>,
5015 <&usb_1_qmpp !! 4226 <&dp_phy 1>;
5016 clock-names = "bi_tcx 4227 clock-names = "bi_tcxo",
5017 "dsi0_p 4228 "dsi0_phy_pll_out_byteclk",
5018 "dsi0_p 4229 "dsi0_phy_pll_out_dsiclk",
5019 "dsi1_p 4230 "dsi1_phy_pll_out_byteclk",
5020 "dsi1_p 4231 "dsi1_phy_pll_out_dsiclk",
5021 "dp_phy 4232 "dp_phy_pll_link_clk",
5022 "dp_phy 4233 "dp_phy_pll_vco_div_clk";
5023 #clock-cells = <1>; 4234 #clock-cells = <1>;
5024 #reset-cells = <1>; 4235 #reset-cells = <1>;
5025 #power-domain-cells = 4236 #power-domain-cells = <1>;
5026 }; 4237 };
5027 4238
5028 pdc: interrupt-controller@b22 4239 pdc: interrupt-controller@b220000 {
5029 compatible = "qcom,sm 4240 compatible = "qcom,sm8250-pdc", "qcom,pdc";
5030 reg = <0 0x0b220000 0 4241 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 4242 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5032 <12 4243 <125 63 1>, <126 716 12>;
5033 #interrupt-cells = <2 4244 #interrupt-cells = <2>;
5034 interrupt-parent = <& 4245 interrupt-parent = <&intc>;
5035 interrupt-controller; 4246 interrupt-controller;
5036 }; 4247 };
5037 4248
5038 tsens0: thermal-sensor@c26300 4249 tsens0: thermal-sensor@c263000 {
5039 compatible = "qcom,sm 4250 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5040 reg = <0 0x0c263000 0 4251 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 4252 <0 0x0c222000 0 0x1ff>; /* SROT */
5042 #qcom,sensors = <16>; 4253 #qcom,sensors = <16>;
5043 interrupts = <GIC_SPI 4254 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
5044 <GIC_SPI 4255 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
5045 interrupt-names = "up 4256 interrupt-names = "uplow", "critical";
5046 #thermal-sensor-cells 4257 #thermal-sensor-cells = <1>;
5047 }; 4258 };
5048 4259
5049 tsens1: thermal-sensor@c26500 4260 tsens1: thermal-sensor@c265000 {
5050 compatible = "qcom,sm 4261 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
5051 reg = <0 0x0c265000 0 4262 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 4263 <0 0x0c223000 0 0x1ff>; /* SROT */
5053 #qcom,sensors = <9>; 4264 #qcom,sensors = <9>;
5054 interrupts = <GIC_SPI 4265 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
5055 <GIC_SPI 4266 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
5056 interrupt-names = "up 4267 interrupt-names = "uplow", "critical";
5057 #thermal-sensor-cells 4268 #thermal-sensor-cells = <1>;
5058 }; 4269 };
5059 4270
5060 aoss_qmp: power-management@c3 !! 4271 aoss_qmp: power-controller@c300000 {
5061 compatible = "qcom,sm 4272 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
5062 reg = <0 0x0c300000 0 4273 reg = <0 0x0c300000 0 0x400>;
5063 interrupts-extended = 4274 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
5064 4275 IPCC_MPROC_SIGNAL_GLINK_QMP
5065 4276 IRQ_TYPE_EDGE_RISING>;
5066 mboxes = <&ipcc IPCC_ 4277 mboxes = <&ipcc IPCC_CLIENT_AOP
5067 IPCC_ 4278 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5068 4279
5069 #clock-cells = <0>; 4280 #clock-cells = <0>;
5070 }; 4281 };
5071 4282
5072 sram@c3f0000 { 4283 sram@c3f0000 {
5073 compatible = "qcom,rp 4284 compatible = "qcom,rpmh-stats";
5074 reg = <0 0x0c3f0000 0 4285 reg = <0 0x0c3f0000 0 0x400>;
5075 }; 4286 };
5076 4287
5077 spmi_bus: spmi@c440000 { 4288 spmi_bus: spmi@c440000 {
5078 compatible = "qcom,sp 4289 compatible = "qcom,spmi-pmic-arb";
5079 reg = <0x0 0x0c440000 4290 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 4291 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 4292 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 4293 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 4294 <0x0 0x0c40a000 0x0 0x0026000>;
5084 reg-names = "core", " 4295 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5085 interrupt-names = "pe 4296 interrupt-names = "periph_irq";
5086 interrupts-extended = 4297 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5087 qcom,ee = <0>; 4298 qcom,ee = <0>;
5088 qcom,channel = <0>; 4299 qcom,channel = <0>;
5089 #address-cells = <2>; 4300 #address-cells = <2>;
5090 #size-cells = <0>; 4301 #size-cells = <0>;
5091 interrupt-controller; 4302 interrupt-controller;
5092 #interrupt-cells = <4 4303 #interrupt-cells = <4>;
5093 }; 4304 };
5094 4305
5095 tlmm: pinctrl@f100000 { 4306 tlmm: pinctrl@f100000 {
5096 compatible = "qcom,sm 4307 compatible = "qcom,sm8250-pinctrl";
5097 reg = <0 0x0f100000 0 4308 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 4309 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 4310 <0 0x0f900000 0 0x300000>;
5100 reg-names = "west", " 4311 reg-names = "west", "south", "north";
5101 interrupts = <GIC_SPI 4312 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
5102 gpio-controller; 4313 gpio-controller;
5103 #gpio-cells = <2>; 4314 #gpio-cells = <2>;
5104 interrupt-controller; 4315 interrupt-controller;
5105 #interrupt-cells = <2 4316 #interrupt-cells = <2>;
5106 gpio-ranges = <&tlmm 4317 gpio-ranges = <&tlmm 0 0 181>;
5107 wakeup-parent = <&pdc 4318 wakeup-parent = <&pdc>;
5108 4319
5109 cam2_default: cam2-de 4320 cam2_default: cam2-default-state {
5110 rst-pins { 4321 rst-pins {
5111 pins 4322 pins = "gpio78";
5112 funct 4323 function = "gpio";
5113 drive 4324 drive-strength = <2>;
5114 bias- 4325 bias-disable;
5115 }; 4326 };
5116 4327
5117 mclk-pins { 4328 mclk-pins {
5118 pins 4329 pins = "gpio96";
5119 funct 4330 function = "cam_mclk";
5120 drive 4331 drive-strength = <16>;
5121 bias- 4332 bias-disable;
5122 }; 4333 };
5123 }; 4334 };
5124 4335
5125 cam2_suspend: cam2-su 4336 cam2_suspend: cam2-suspend-state {
5126 rst-pins { 4337 rst-pins {
5127 pins 4338 pins = "gpio78";
5128 funct 4339 function = "gpio";
5129 drive 4340 drive-strength = <2>;
5130 bias- 4341 bias-pull-down;
5131 outpu 4342 output-low;
5132 }; 4343 };
5133 4344
5134 mclk-pins { 4345 mclk-pins {
5135 pins 4346 pins = "gpio96";
5136 funct 4347 function = "cam_mclk";
5137 drive 4348 drive-strength = <2>;
5138 bias- 4349 bias-disable;
5139 }; 4350 };
5140 }; 4351 };
5141 4352
5142 cci0_default: cci0-de 4353 cci0_default: cci0-default-state {
5143 cci0_i2c0_def 4354 cci0_i2c0_default: cci0-i2c0-default-pins {
5144 /* SD 4355 /* SDA, SCL */
5145 pins 4356 pins = "gpio101", "gpio102";
5146 funct 4357 function = "cci_i2c";
5147 4358
5148 bias- 4359 bias-pull-up;
5149 drive 4360 drive-strength = <2>; /* 2 mA */
5150 }; 4361 };
5151 4362
5152 cci0_i2c1_def 4363 cci0_i2c1_default: cci0-i2c1-default-pins {
5153 /* SD 4364 /* SDA, SCL */
5154 pins 4365 pins = "gpio103", "gpio104";
5155 funct 4366 function = "cci_i2c";
5156 4367
5157 bias- 4368 bias-pull-up;
5158 drive 4369 drive-strength = <2>; /* 2 mA */
5159 }; 4370 };
5160 }; 4371 };
5161 4372
5162 cci0_sleep: cci0-slee 4373 cci0_sleep: cci0-sleep-state {
5163 cci0_i2c0_sle 4374 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
5164 /* SD 4375 /* SDA, SCL */
5165 pins 4376 pins = "gpio101", "gpio102";
5166 funct 4377 function = "cci_i2c";
5167 4378
5168 drive 4379 drive-strength = <2>; /* 2 mA */
5169 bias- 4380 bias-pull-down;
5170 }; 4381 };
5171 4382
5172 cci0_i2c1_sle 4383 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
5173 /* SD 4384 /* SDA, SCL */
5174 pins 4385 pins = "gpio103", "gpio104";
5175 funct 4386 function = "cci_i2c";
5176 4387
5177 drive 4388 drive-strength = <2>; /* 2 mA */
5178 bias- 4389 bias-pull-down;
5179 }; 4390 };
5180 }; 4391 };
5181 4392
5182 cci1_default: cci1-de 4393 cci1_default: cci1-default-state {
5183 cci1_i2c0_def 4394 cci1_i2c0_default: cci1-i2c0-default-pins {
5184 /* SD 4395 /* SDA, SCL */
5185 pins 4396 pins = "gpio105","gpio106";
5186 funct 4397 function = "cci_i2c";
5187 4398
5188 bias- 4399 bias-pull-up;
5189 drive 4400 drive-strength = <2>; /* 2 mA */
5190 }; 4401 };
5191 4402
5192 cci1_i2c1_def 4403 cci1_i2c1_default: cci1-i2c1-default-pins {
5193 /* SD 4404 /* SDA, SCL */
5194 pins 4405 pins = "gpio107","gpio108";
5195 funct 4406 function = "cci_i2c";
5196 4407
5197 bias- 4408 bias-pull-up;
5198 drive 4409 drive-strength = <2>; /* 2 mA */
5199 }; 4410 };
5200 }; 4411 };
5201 4412
5202 cci1_sleep: cci1-slee 4413 cci1_sleep: cci1-sleep-state {
5203 cci1_i2c0_sle 4414 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
5204 /* SD 4415 /* SDA, SCL */
5205 pins 4416 pins = "gpio105","gpio106";
5206 funct 4417 function = "cci_i2c";
5207 4418
5208 bias- 4419 bias-pull-down;
5209 drive 4420 drive-strength = <2>; /* 2 mA */
5210 }; 4421 };
5211 4422
5212 cci1_i2c1_sle 4423 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
5213 /* SD 4424 /* SDA, SCL */
5214 pins 4425 pins = "gpio107","gpio108";
5215 funct 4426 function = "cci_i2c";
5216 4427
5217 bias- 4428 bias-pull-down;
5218 drive 4429 drive-strength = <2>; /* 2 mA */
5219 }; 4430 };
5220 }; 4431 };
5221 4432
5222 pri_mi2s_active: pri- 4433 pri_mi2s_active: pri-mi2s-active-state {
5223 sclk-pins { 4434 sclk-pins {
5224 pins 4435 pins = "gpio138";
5225 funct 4436 function = "mi2s0_sck";
5226 drive 4437 drive-strength = <8>;
5227 bias- 4438 bias-disable;
5228 }; 4439 };
5229 4440
5230 ws-pins { 4441 ws-pins {
5231 pins 4442 pins = "gpio141";
5232 funct 4443 function = "mi2s0_ws";
5233 drive 4444 drive-strength = <8>;
5234 outpu 4445 output-high;
5235 }; 4446 };
5236 4447
5237 data0-pins { 4448 data0-pins {
5238 pins 4449 pins = "gpio139";
5239 funct 4450 function = "mi2s0_data0";
5240 drive 4451 drive-strength = <8>;
5241 bias- 4452 bias-disable;
5242 outpu 4453 output-high;
5243 }; 4454 };
5244 4455
5245 data1-pins { 4456 data1-pins {
5246 pins 4457 pins = "gpio140";
5247 funct 4458 function = "mi2s0_data1";
5248 drive 4459 drive-strength = <8>;
5249 outpu 4460 output-high;
5250 }; 4461 };
5251 }; 4462 };
5252 4463
5253 qup_i2c0_default: qup 4464 qup_i2c0_default: qup-i2c0-default-state {
5254 pins = "gpio2 4465 pins = "gpio28", "gpio29";
5255 function = "q 4466 function = "qup0";
5256 drive-strengt 4467 drive-strength = <2>;
5257 bias-disable; 4468 bias-disable;
5258 }; 4469 };
5259 4470
5260 qup_i2c1_default: qup 4471 qup_i2c1_default: qup-i2c1-default-state {
5261 pins = "gpio4 4472 pins = "gpio4", "gpio5";
5262 function = "q 4473 function = "qup1";
5263 drive-strengt 4474 drive-strength = <2>;
5264 bias-disable; 4475 bias-disable;
5265 }; 4476 };
5266 4477
5267 qup_i2c2_default: qup 4478 qup_i2c2_default: qup-i2c2-default-state {
5268 pins = "gpio1 4479 pins = "gpio115", "gpio116";
5269 function = "q 4480 function = "qup2";
5270 drive-strengt 4481 drive-strength = <2>;
5271 bias-disable; 4482 bias-disable;
5272 }; 4483 };
5273 4484
5274 qup_i2c3_default: qup 4485 qup_i2c3_default: qup-i2c3-default-state {
5275 pins = "gpio1 4486 pins = "gpio119", "gpio120";
5276 function = "q 4487 function = "qup3";
5277 drive-strengt 4488 drive-strength = <2>;
5278 bias-disable; 4489 bias-disable;
5279 }; 4490 };
5280 4491
5281 qup_i2c4_default: qup 4492 qup_i2c4_default: qup-i2c4-default-state {
5282 pins = "gpio8 4493 pins = "gpio8", "gpio9";
5283 function = "q 4494 function = "qup4";
5284 drive-strengt 4495 drive-strength = <2>;
5285 bias-disable; 4496 bias-disable;
5286 }; 4497 };
5287 4498
5288 qup_i2c5_default: qup 4499 qup_i2c5_default: qup-i2c5-default-state {
5289 pins = "gpio1 4500 pins = "gpio12", "gpio13";
5290 function = "q 4501 function = "qup5";
5291 drive-strengt 4502 drive-strength = <2>;
5292 bias-disable; 4503 bias-disable;
5293 }; 4504 };
5294 4505
5295 qup_i2c6_default: qup 4506 qup_i2c6_default: qup-i2c6-default-state {
5296 pins = "gpio1 4507 pins = "gpio16", "gpio17";
5297 function = "q 4508 function = "qup6";
5298 drive-strengt 4509 drive-strength = <2>;
5299 bias-disable; 4510 bias-disable;
5300 }; 4511 };
5301 4512
5302 qup_i2c7_default: qup 4513 qup_i2c7_default: qup-i2c7-default-state {
5303 pins = "gpio2 4514 pins = "gpio20", "gpio21";
5304 function = "q 4515 function = "qup7";
5305 drive-strengt 4516 drive-strength = <2>;
5306 bias-disable; 4517 bias-disable;
5307 }; 4518 };
5308 4519
5309 qup_i2c8_default: qup 4520 qup_i2c8_default: qup-i2c8-default-state {
5310 pins = "gpio2 4521 pins = "gpio24", "gpio25";
5311 function = "q 4522 function = "qup8";
5312 drive-strengt 4523 drive-strength = <2>;
5313 bias-disable; 4524 bias-disable;
5314 }; 4525 };
5315 4526
5316 qup_i2c9_default: qup 4527 qup_i2c9_default: qup-i2c9-default-state {
5317 pins = "gpio1 4528 pins = "gpio125", "gpio126";
5318 function = "q 4529 function = "qup9";
5319 drive-strengt 4530 drive-strength = <2>;
5320 bias-disable; 4531 bias-disable;
5321 }; 4532 };
5322 4533
5323 qup_i2c10_default: qu 4534 qup_i2c10_default: qup-i2c10-default-state {
5324 pins = "gpio1 4535 pins = "gpio129", "gpio130";
5325 function = "q 4536 function = "qup10";
5326 drive-strengt 4537 drive-strength = <2>;
5327 bias-disable; 4538 bias-disable;
5328 }; 4539 };
5329 4540
5330 qup_i2c11_default: qu 4541 qup_i2c11_default: qup-i2c11-default-state {
5331 pins = "gpio6 4542 pins = "gpio60", "gpio61";
5332 function = "q 4543 function = "qup11";
5333 drive-strengt 4544 drive-strength = <2>;
5334 bias-disable; 4545 bias-disable;
5335 }; 4546 };
5336 4547
5337 qup_i2c12_default: qu 4548 qup_i2c12_default: qup-i2c12-default-state {
5338 pins = "gpio3 4549 pins = "gpio32", "gpio33";
5339 function = "q 4550 function = "qup12";
5340 drive-strengt 4551 drive-strength = <2>;
5341 bias-disable; 4552 bias-disable;
5342 }; 4553 };
5343 4554
5344 qup_i2c13_default: qu 4555 qup_i2c13_default: qup-i2c13-default-state {
5345 pins = "gpio3 4556 pins = "gpio36", "gpio37";
5346 function = "q 4557 function = "qup13";
5347 drive-strengt 4558 drive-strength = <2>;
5348 bias-disable; 4559 bias-disable;
5349 }; 4560 };
5350 4561
5351 qup_i2c14_default: qu 4562 qup_i2c14_default: qup-i2c14-default-state {
5352 pins = "gpio4 4563 pins = "gpio40", "gpio41";
5353 function = "q 4564 function = "qup14";
5354 drive-strengt 4565 drive-strength = <2>;
5355 bias-disable; 4566 bias-disable;
5356 }; 4567 };
5357 4568
5358 qup_i2c15_default: qu 4569 qup_i2c15_default: qup-i2c15-default-state {
5359 pins = "gpio4 4570 pins = "gpio44", "gpio45";
5360 function = "q 4571 function = "qup15";
5361 drive-strengt 4572 drive-strength = <2>;
5362 bias-disable; 4573 bias-disable;
5363 }; 4574 };
5364 4575
5365 qup_i2c16_default: qu 4576 qup_i2c16_default: qup-i2c16-default-state {
5366 pins = "gpio4 4577 pins = "gpio48", "gpio49";
5367 function = "q 4578 function = "qup16";
5368 drive-strengt 4579 drive-strength = <2>;
5369 bias-disable; 4580 bias-disable;
5370 }; 4581 };
5371 4582
5372 qup_i2c17_default: qu 4583 qup_i2c17_default: qup-i2c17-default-state {
5373 pins = "gpio5 4584 pins = "gpio52", "gpio53";
5374 function = "q 4585 function = "qup17";
5375 drive-strengt 4586 drive-strength = <2>;
5376 bias-disable; 4587 bias-disable;
5377 }; 4588 };
5378 4589
5379 qup_i2c18_default: qu 4590 qup_i2c18_default: qup-i2c18-default-state {
5380 pins = "gpio5 4591 pins = "gpio56", "gpio57";
5381 function = "q 4592 function = "qup18";
5382 drive-strengt 4593 drive-strength = <2>;
5383 bias-disable; 4594 bias-disable;
5384 }; 4595 };
5385 4596
5386 qup_i2c19_default: qu 4597 qup_i2c19_default: qup-i2c19-default-state {
5387 pins = "gpio0 4598 pins = "gpio0", "gpio1";
5388 function = "q 4599 function = "qup19";
5389 drive-strengt 4600 drive-strength = <2>;
5390 bias-disable; 4601 bias-disable;
5391 }; 4602 };
5392 4603
5393 qup_spi0_cs: qup-spi0 4604 qup_spi0_cs: qup-spi0-cs-state {
5394 pins = "gpio3 4605 pins = "gpio31";
5395 function = "q 4606 function = "qup0";
5396 }; 4607 };
5397 4608
5398 qup_spi0_cs_gpio: qup 4609 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
5399 pins = "gpio3 4610 pins = "gpio31";
5400 function = "g 4611 function = "gpio";
5401 }; 4612 };
5402 4613
5403 qup_spi0_data_clk: qu 4614 qup_spi0_data_clk: qup-spi0-data-clk-state {
5404 pins = "gpio2 4615 pins = "gpio28", "gpio29",
5405 "gpio3 4616 "gpio30";
5406 function = "q 4617 function = "qup0";
5407 }; 4618 };
5408 4619
5409 qup_spi1_cs: qup-spi1 4620 qup_spi1_cs: qup-spi1-cs-state {
5410 pins = "gpio7 4621 pins = "gpio7";
5411 function = "q 4622 function = "qup1";
5412 }; 4623 };
5413 4624
5414 qup_spi1_cs_gpio: qup 4625 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
5415 pins = "gpio7 4626 pins = "gpio7";
5416 function = "g 4627 function = "gpio";
5417 }; 4628 };
5418 4629
5419 qup_spi1_data_clk: qu 4630 qup_spi1_data_clk: qup-spi1-data-clk-state {
5420 pins = "gpio4 4631 pins = "gpio4", "gpio5",
5421 "gpio6 4632 "gpio6";
5422 function = "q 4633 function = "qup1";
5423 }; 4634 };
5424 4635
5425 qup_spi2_cs: qup-spi2 4636 qup_spi2_cs: qup-spi2-cs-state {
5426 pins = "gpio1 4637 pins = "gpio118";
5427 function = "q 4638 function = "qup2";
5428 }; 4639 };
5429 4640
5430 qup_spi2_cs_gpio: qup 4641 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5431 pins = "gpio1 4642 pins = "gpio118";
5432 function = "g 4643 function = "gpio";
5433 }; 4644 };
5434 4645
5435 qup_spi2_data_clk: qu 4646 qup_spi2_data_clk: qup-spi2-data-clk-state {
5436 pins = "gpio1 4647 pins = "gpio115", "gpio116",
5437 "gpio1 4648 "gpio117";
5438 function = "q 4649 function = "qup2";
5439 }; 4650 };
5440 4651
5441 qup_spi3_cs: qup-spi3 4652 qup_spi3_cs: qup-spi3-cs-state {
5442 pins = "gpio1 4653 pins = "gpio122";
5443 function = "q 4654 function = "qup3";
5444 }; 4655 };
5445 4656
5446 qup_spi3_cs_gpio: qup 4657 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5447 pins = "gpio1 4658 pins = "gpio122";
5448 function = "g 4659 function = "gpio";
5449 }; 4660 };
5450 4661
5451 qup_spi3_data_clk: qu 4662 qup_spi3_data_clk: qup-spi3-data-clk-state {
5452 pins = "gpio1 4663 pins = "gpio119", "gpio120",
5453 "gpio1 4664 "gpio121";
5454 function = "q 4665 function = "qup3";
5455 }; 4666 };
5456 4667
5457 qup_spi4_cs: qup-spi4 4668 qup_spi4_cs: qup-spi4-cs-state {
5458 pins = "gpio1 4669 pins = "gpio11";
5459 function = "q 4670 function = "qup4";
5460 }; 4671 };
5461 4672
5462 qup_spi4_cs_gpio: qup 4673 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5463 pins = "gpio1 4674 pins = "gpio11";
5464 function = "g 4675 function = "gpio";
5465 }; 4676 };
5466 4677
5467 qup_spi4_data_clk: qu 4678 qup_spi4_data_clk: qup-spi4-data-clk-state {
5468 pins = "gpio8 4679 pins = "gpio8", "gpio9",
5469 "gpio1 4680 "gpio10";
5470 function = "q 4681 function = "qup4";
5471 }; 4682 };
5472 4683
5473 qup_spi5_cs: qup-spi5 4684 qup_spi5_cs: qup-spi5-cs-state {
5474 pins = "gpio1 4685 pins = "gpio15";
5475 function = "q 4686 function = "qup5";
5476 }; 4687 };
5477 4688
5478 qup_spi5_cs_gpio: qup 4689 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5479 pins = "gpio1 4690 pins = "gpio15";
5480 function = "g 4691 function = "gpio";
5481 }; 4692 };
5482 4693
5483 qup_spi5_data_clk: qu 4694 qup_spi5_data_clk: qup-spi5-data-clk-state {
5484 pins = "gpio1 4695 pins = "gpio12", "gpio13",
5485 "gpio1 4696 "gpio14";
5486 function = "q 4697 function = "qup5";
5487 }; 4698 };
5488 4699
5489 qup_spi6_cs: qup-spi6 4700 qup_spi6_cs: qup-spi6-cs-state {
5490 pins = "gpio1 4701 pins = "gpio19";
5491 function = "q 4702 function = "qup6";
5492 }; 4703 };
5493 4704
5494 qup_spi6_cs_gpio: qup 4705 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5495 pins = "gpio1 4706 pins = "gpio19";
5496 function = "g 4707 function = "gpio";
5497 }; 4708 };
5498 4709
5499 qup_spi6_data_clk: qu 4710 qup_spi6_data_clk: qup-spi6-data-clk-state {
5500 pins = "gpio1 4711 pins = "gpio16", "gpio17",
5501 "gpio1 4712 "gpio18";
5502 function = "q 4713 function = "qup6";
5503 }; 4714 };
5504 4715
5505 qup_spi7_cs: qup-spi7 4716 qup_spi7_cs: qup-spi7-cs-state {
5506 pins = "gpio2 4717 pins = "gpio23";
5507 function = "q 4718 function = "qup7";
5508 }; 4719 };
5509 4720
5510 qup_spi7_cs_gpio: qup 4721 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5511 pins = "gpio2 4722 pins = "gpio23";
5512 function = "g 4723 function = "gpio";
5513 }; 4724 };
5514 4725
5515 qup_spi7_data_clk: qu 4726 qup_spi7_data_clk: qup-spi7-data-clk-state {
5516 pins = "gpio2 4727 pins = "gpio20", "gpio21",
5517 "gpio2 4728 "gpio22";
5518 function = "q 4729 function = "qup7";
5519 }; 4730 };
5520 4731
5521 qup_spi8_cs: qup-spi8 4732 qup_spi8_cs: qup-spi8-cs-state {
5522 pins = "gpio2 4733 pins = "gpio27";
5523 function = "q 4734 function = "qup8";
5524 }; 4735 };
5525 4736
5526 qup_spi8_cs_gpio: qup 4737 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5527 pins = "gpio2 4738 pins = "gpio27";
5528 function = "g 4739 function = "gpio";
5529 }; 4740 };
5530 4741
5531 qup_spi8_data_clk: qu 4742 qup_spi8_data_clk: qup-spi8-data-clk-state {
5532 pins = "gpio2 4743 pins = "gpio24", "gpio25",
5533 "gpio2 4744 "gpio26";
5534 function = "q 4745 function = "qup8";
5535 }; 4746 };
5536 4747
5537 qup_spi9_cs: qup-spi9 4748 qup_spi9_cs: qup-spi9-cs-state {
5538 pins = "gpio1 4749 pins = "gpio128";
5539 function = "q 4750 function = "qup9";
5540 }; 4751 };
5541 4752
5542 qup_spi9_cs_gpio: qup 4753 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5543 pins = "gpio1 4754 pins = "gpio128";
5544 function = "g 4755 function = "gpio";
5545 }; 4756 };
5546 4757
5547 qup_spi9_data_clk: qu 4758 qup_spi9_data_clk: qup-spi9-data-clk-state {
5548 pins = "gpio1 4759 pins = "gpio125", "gpio126",
5549 "gpio1 4760 "gpio127";
5550 function = "q 4761 function = "qup9";
5551 }; 4762 };
5552 4763
5553 qup_spi10_cs: qup-spi 4764 qup_spi10_cs: qup-spi10-cs-state {
5554 pins = "gpio1 4765 pins = "gpio132";
5555 function = "q 4766 function = "qup10";
5556 }; 4767 };
5557 4768
5558 qup_spi10_cs_gpio: qu 4769 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5559 pins = "gpio1 4770 pins = "gpio132";
5560 function = "g 4771 function = "gpio";
5561 }; 4772 };
5562 4773
5563 qup_spi10_data_clk: q 4774 qup_spi10_data_clk: qup-spi10-data-clk-state {
5564 pins = "gpio1 4775 pins = "gpio129", "gpio130",
5565 "gpio1 4776 "gpio131";
5566 function = "q 4777 function = "qup10";
5567 }; 4778 };
5568 4779
5569 qup_spi11_cs: qup-spi 4780 qup_spi11_cs: qup-spi11-cs-state {
5570 pins = "gpio6 4781 pins = "gpio63";
5571 function = "q 4782 function = "qup11";
5572 }; 4783 };
5573 4784
5574 qup_spi11_cs_gpio: qu 4785 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5575 pins = "gpio6 4786 pins = "gpio63";
5576 function = "g 4787 function = "gpio";
5577 }; 4788 };
5578 4789
5579 qup_spi11_data_clk: q 4790 qup_spi11_data_clk: qup-spi11-data-clk-state {
5580 pins = "gpio6 4791 pins = "gpio60", "gpio61",
5581 "gpio6 4792 "gpio62";
5582 function = "q 4793 function = "qup11";
5583 }; 4794 };
5584 4795
5585 qup_spi12_cs: qup-spi 4796 qup_spi12_cs: qup-spi12-cs-state {
5586 pins = "gpio3 4797 pins = "gpio35";
5587 function = "q 4798 function = "qup12";
5588 }; 4799 };
5589 4800
5590 qup_spi12_cs_gpio: qu 4801 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5591 pins = "gpio3 4802 pins = "gpio35";
5592 function = "g 4803 function = "gpio";
5593 }; 4804 };
5594 4805
5595 qup_spi12_data_clk: q 4806 qup_spi12_data_clk: qup-spi12-data-clk-state {
5596 pins = "gpio3 4807 pins = "gpio32", "gpio33",
5597 "gpio3 4808 "gpio34";
5598 function = "q 4809 function = "qup12";
5599 }; 4810 };
5600 4811
5601 qup_spi13_cs: qup-spi 4812 qup_spi13_cs: qup-spi13-cs-state {
5602 pins = "gpio3 4813 pins = "gpio39";
5603 function = "q 4814 function = "qup13";
5604 }; 4815 };
5605 4816
5606 qup_spi13_cs_gpio: qu 4817 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5607 pins = "gpio3 4818 pins = "gpio39";
5608 function = "g 4819 function = "gpio";
5609 }; 4820 };
5610 4821
5611 qup_spi13_data_clk: q 4822 qup_spi13_data_clk: qup-spi13-data-clk-state {
5612 pins = "gpio3 4823 pins = "gpio36", "gpio37",
5613 "gpio3 4824 "gpio38";
5614 function = "q 4825 function = "qup13";
5615 }; 4826 };
5616 4827
5617 qup_spi14_cs: qup-spi 4828 qup_spi14_cs: qup-spi14-cs-state {
5618 pins = "gpio4 4829 pins = "gpio43";
5619 function = "q 4830 function = "qup14";
5620 }; 4831 };
5621 4832
5622 qup_spi14_cs_gpio: qu 4833 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5623 pins = "gpio4 4834 pins = "gpio43";
5624 function = "g 4835 function = "gpio";
5625 }; 4836 };
5626 4837
5627 qup_spi14_data_clk: q 4838 qup_spi14_data_clk: qup-spi14-data-clk-state {
5628 pins = "gpio4 4839 pins = "gpio40", "gpio41",
5629 "gpio4 4840 "gpio42";
5630 function = "q 4841 function = "qup14";
5631 }; 4842 };
5632 4843
5633 qup_spi15_cs: qup-spi 4844 qup_spi15_cs: qup-spi15-cs-state {
5634 pins = "gpio4 4845 pins = "gpio47";
5635 function = "q 4846 function = "qup15";
5636 }; 4847 };
5637 4848
5638 qup_spi15_cs_gpio: qu 4849 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5639 pins = "gpio4 4850 pins = "gpio47";
5640 function = "g 4851 function = "gpio";
5641 }; 4852 };
5642 4853
5643 qup_spi15_data_clk: q 4854 qup_spi15_data_clk: qup-spi15-data-clk-state {
5644 pins = "gpio4 4855 pins = "gpio44", "gpio45",
5645 "gpio4 4856 "gpio46";
5646 function = "q 4857 function = "qup15";
5647 }; 4858 };
5648 4859
5649 qup_spi16_cs: qup-spi 4860 qup_spi16_cs: qup-spi16-cs-state {
5650 pins = "gpio5 4861 pins = "gpio51";
5651 function = "q 4862 function = "qup16";
5652 }; 4863 };
5653 4864
5654 qup_spi16_cs_gpio: qu 4865 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5655 pins = "gpio5 4866 pins = "gpio51";
5656 function = "g 4867 function = "gpio";
5657 }; 4868 };
5658 4869
5659 qup_spi16_data_clk: q 4870 qup_spi16_data_clk: qup-spi16-data-clk-state {
5660 pins = "gpio4 4871 pins = "gpio48", "gpio49",
5661 "gpio5 4872 "gpio50";
5662 function = "q 4873 function = "qup16";
5663 }; 4874 };
5664 4875
5665 qup_spi17_cs: qup-spi 4876 qup_spi17_cs: qup-spi17-cs-state {
5666 pins = "gpio5 4877 pins = "gpio55";
5667 function = "q 4878 function = "qup17";
5668 }; 4879 };
5669 4880
5670 qup_spi17_cs_gpio: qu 4881 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5671 pins = "gpio5 4882 pins = "gpio55";
5672 function = "g 4883 function = "gpio";
5673 }; 4884 };
5674 4885
5675 qup_spi17_data_clk: q 4886 qup_spi17_data_clk: qup-spi17-data-clk-state {
5676 pins = "gpio5 4887 pins = "gpio52", "gpio53",
5677 "gpio5 4888 "gpio54";
5678 function = "q 4889 function = "qup17";
5679 }; 4890 };
5680 4891
5681 qup_spi18_cs: qup-spi 4892 qup_spi18_cs: qup-spi18-cs-state {
5682 pins = "gpio5 4893 pins = "gpio59";
5683 function = "q 4894 function = "qup18";
5684 }; 4895 };
5685 4896
5686 qup_spi18_cs_gpio: qu 4897 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5687 pins = "gpio5 4898 pins = "gpio59";
5688 function = "g 4899 function = "gpio";
5689 }; 4900 };
5690 4901
5691 qup_spi18_data_clk: q 4902 qup_spi18_data_clk: qup-spi18-data-clk-state {
5692 pins = "gpio5 4903 pins = "gpio56", "gpio57",
5693 "gpio5 4904 "gpio58";
5694 function = "q 4905 function = "qup18";
5695 }; 4906 };
5696 4907
5697 qup_spi19_cs: qup-spi 4908 qup_spi19_cs: qup-spi19-cs-state {
5698 pins = "gpio3 4909 pins = "gpio3";
5699 function = "q 4910 function = "qup19";
5700 }; 4911 };
5701 4912
5702 qup_spi19_cs_gpio: qu 4913 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5703 pins = "gpio3 4914 pins = "gpio3";
5704 function = "g 4915 function = "gpio";
5705 }; 4916 };
5706 4917
5707 qup_spi19_data_clk: q 4918 qup_spi19_data_clk: qup-spi19-data-clk-state {
5708 pins = "gpio0 4919 pins = "gpio0", "gpio1",
5709 "gpio2 4920 "gpio2";
5710 function = "q 4921 function = "qup19";
5711 }; 4922 };
5712 4923
5713 qup_uart2_default: qu 4924 qup_uart2_default: qup-uart2-default-state {
5714 pins = "gpio1 4925 pins = "gpio117", "gpio118";
5715 function = "q 4926 function = "qup2";
5716 }; 4927 };
5717 4928
5718 qup_uart6_default: qu 4929 qup_uart6_default: qup-uart6-default-state {
5719 pins = "gpio1 4930 pins = "gpio16", "gpio17", "gpio18", "gpio19";
5720 function = "q 4931 function = "qup6";
5721 }; 4932 };
5722 4933
5723 qup_uart12_default: q 4934 qup_uart12_default: qup-uart12-default-state {
5724 pins = "gpio3 4935 pins = "gpio34", "gpio35";
5725 function = "q 4936 function = "qup12";
5726 }; 4937 };
5727 4938
5728 qup_uart17_default: q 4939 qup_uart17_default: qup-uart17-default-state {
5729 pins = "gpio5 4940 pins = "gpio52", "gpio53", "gpio54", "gpio55";
5730 function = "q 4941 function = "qup17";
5731 }; 4942 };
5732 4943
5733 qup_uart18_default: q 4944 qup_uart18_default: qup-uart18-default-state {
5734 pins = "gpio5 4945 pins = "gpio58", "gpio59";
5735 function = "q 4946 function = "qup18";
5736 }; 4947 };
5737 4948
5738 tert_mi2s_active: ter 4949 tert_mi2s_active: tert-mi2s-active-state {
5739 sck-pins { 4950 sck-pins {
5740 pins 4951 pins = "gpio133";
5741 funct 4952 function = "mi2s2_sck";
5742 drive 4953 drive-strength = <8>;
5743 bias- 4954 bias-disable;
5744 }; 4955 };
5745 4956
5746 data0-pins { 4957 data0-pins {
5747 pins 4958 pins = "gpio134";
5748 funct 4959 function = "mi2s2_data0";
5749 drive 4960 drive-strength = <8>;
5750 bias- 4961 bias-disable;
5751 outpu 4962 output-high;
5752 }; 4963 };
5753 4964
5754 ws-pins { 4965 ws-pins {
5755 pins 4966 pins = "gpio135";
5756 funct 4967 function = "mi2s2_ws";
5757 drive 4968 drive-strength = <8>;
5758 outpu 4969 output-high;
5759 }; 4970 };
5760 }; 4971 };
5761 4972
5762 sdc2_sleep_state: sdc 4973 sdc2_sleep_state: sdc2-sleep-state {
5763 clk-pins { 4974 clk-pins {
5764 pins 4975 pins = "sdc2_clk";
5765 drive 4976 drive-strength = <2>;
5766 bias- 4977 bias-disable;
5767 }; 4978 };
5768 4979
5769 cmd-pins { 4980 cmd-pins {
5770 pins 4981 pins = "sdc2_cmd";
5771 drive 4982 drive-strength = <2>;
5772 bias- 4983 bias-pull-up;
5773 }; 4984 };
5774 4985
5775 data-pins { 4986 data-pins {
5776 pins 4987 pins = "sdc2_data";
5777 drive 4988 drive-strength = <2>;
5778 bias- 4989 bias-pull-up;
5779 }; 4990 };
5780 }; 4991 };
5781 4992
5782 pcie0_default_state: 4993 pcie0_default_state: pcie0-default-state {
5783 perst-pins { 4994 perst-pins {
5784 pins 4995 pins = "gpio79";
5785 funct 4996 function = "gpio";
5786 drive 4997 drive-strength = <2>;
5787 bias- 4998 bias-pull-down;
5788 }; 4999 };
5789 5000
5790 clkreq-pins { 5001 clkreq-pins {
5791 pins 5002 pins = "gpio80";
5792 funct 5003 function = "pci_e0";
5793 drive 5004 drive-strength = <2>;
5794 bias- 5005 bias-pull-up;
5795 }; 5006 };
5796 5007
5797 wake-pins { 5008 wake-pins {
5798 pins 5009 pins = "gpio81";
5799 funct 5010 function = "gpio";
5800 drive 5011 drive-strength = <2>;
5801 bias- 5012 bias-pull-up;
5802 }; 5013 };
5803 }; 5014 };
5804 5015
5805 pcie1_default_state: 5016 pcie1_default_state: pcie1-default-state {
5806 perst-pins { 5017 perst-pins {
5807 pins 5018 pins = "gpio82";
5808 funct 5019 function = "gpio";
5809 drive 5020 drive-strength = <2>;
5810 bias- 5021 bias-pull-down;
5811 }; 5022 };
5812 5023
5813 clkreq-pins { 5024 clkreq-pins {
5814 pins 5025 pins = "gpio83";
5815 funct 5026 function = "pci_e1";
5816 drive 5027 drive-strength = <2>;
5817 bias- 5028 bias-pull-up;
5818 }; 5029 };
5819 5030
5820 wake-pins { 5031 wake-pins {
5821 pins 5032 pins = "gpio84";
5822 funct 5033 function = "gpio";
5823 drive 5034 drive-strength = <2>;
5824 bias- 5035 bias-pull-up;
5825 }; 5036 };
5826 }; 5037 };
5827 5038
5828 pcie2_default_state: 5039 pcie2_default_state: pcie2-default-state {
5829 perst-pins { 5040 perst-pins {
5830 pins 5041 pins = "gpio85";
5831 funct 5042 function = "gpio";
5832 drive 5043 drive-strength = <2>;
5833 bias- 5044 bias-pull-down;
5834 }; 5045 };
5835 5046
5836 clkreq-pins { 5047 clkreq-pins {
5837 pins 5048 pins = "gpio86";
5838 funct 5049 function = "pci_e2";
5839 drive 5050 drive-strength = <2>;
5840 bias- 5051 bias-pull-up;
5841 }; 5052 };
5842 5053
5843 wake-pins { 5054 wake-pins {
5844 pins 5055 pins = "gpio87";
5845 funct 5056 function = "gpio";
5846 drive 5057 drive-strength = <2>;
5847 bias- 5058 bias-pull-up;
5848 }; 5059 };
5849 }; 5060 };
5850 }; 5061 };
5851 5062
5852 apps_smmu: iommu@15000000 { 5063 apps_smmu: iommu@15000000 {
5853 compatible = "qcom,sm !! 5064 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
5854 reg = <0 0x15000000 0 5065 reg = <0 0x15000000 0 0x100000>;
5855 #iommu-cells = <2>; 5066 #iommu-cells = <2>;
5856 #global-interrupts = 5067 #global-interrupts = <2>;
5857 interrupts = <GIC_SPI !! 5068 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
5858 <GIC_SPI !! 5069 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5859 <GIC_SPI !! 5070 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5860 <GIC_SPI !! 5071 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5861 <GIC_SPI !! 5072 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5862 <GIC_SPI !! 5073 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5863 <GIC_SPI !! 5074 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5864 <GIC_SPI !! 5075 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5865 <GIC_SPI !! 5076 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5866 <GIC_SPI !! 5077 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5867 <GIC_SPI !! 5078 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5868 <GIC_SPI !! 5079 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5869 <GIC_SPI !! 5080 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5870 <GIC_SPI !! 5081 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5871 <GIC_SPI !! 5082 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5872 <GIC_SPI !! 5083 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5873 <GIC_SPI !! 5084 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5874 <GIC_SPI !! 5085 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5875 <GIC_SPI !! 5086 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5876 <GIC_SPI !! 5087 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5877 <GIC_SPI !! 5088 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5878 <GIC_SPI !! 5089 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5879 <GIC_SPI !! 5090 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5880 <GIC_SPI !! 5091 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5881 <GIC_SPI !! 5092 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5882 <GIC_SPI !! 5093 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5883 <GIC_SPI !! 5094 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5884 <GIC_SPI !! 5095 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5885 <GIC_SPI !! 5096 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5886 <GIC_SPI !! 5097 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5887 <GIC_SPI !! 5098 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5888 <GIC_SPI !! 5099 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5889 <GIC_SPI !! 5100 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5890 <GIC_SPI !! 5101 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5891 <GIC_SPI !! 5102 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5892 <GIC_SPI !! 5103 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5893 <GIC_SPI !! 5104 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5894 <GIC_SPI !! 5105 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5895 <GIC_SPI !! 5106 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5896 <GIC_SPI !! 5107 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5897 <GIC_SPI !! 5108 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5898 <GIC_SPI !! 5109 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5899 <GIC_SPI !! 5110 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5900 <GIC_SPI !! 5111 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5901 <GIC_SPI !! 5112 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5902 <GIC_SPI !! 5113 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5903 <GIC_SPI !! 5114 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5904 <GIC_SPI !! 5115 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5905 <GIC_SPI !! 5116 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5906 <GIC_SPI !! 5117 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5907 <GIC_SPI !! 5118 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5908 <GIC_SPI !! 5119 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5909 <GIC_SPI !! 5120 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5910 <GIC_SPI !! 5121 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5911 <GIC_SPI !! 5122 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5912 <GIC_SPI !! 5123 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5913 <GIC_SPI !! 5124 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5914 <GIC_SPI !! 5125 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5915 <GIC_SPI !! 5126 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5916 <GIC_SPI !! 5127 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5917 <GIC_SPI !! 5128 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5918 <GIC_SPI !! 5129 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5919 <GIC_SPI !! 5130 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5920 <GIC_SPI !! 5131 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5921 <GIC_SPI !! 5132 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5922 <GIC_SPI !! 5133 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5923 <GIC_SPI !! 5134 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5924 <GIC_SPI !! 5135 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5925 <GIC_SPI !! 5136 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5926 <GIC_SPI !! 5137 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5927 <GIC_SPI !! 5138 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5928 <GIC_SPI !! 5139 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5929 <GIC_SPI !! 5140 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5930 <GIC_SPI !! 5141 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5931 <GIC_SPI !! 5142 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5932 <GIC_SPI !! 5143 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5933 <GIC_SPI !! 5144 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5934 <GIC_SPI !! 5145 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5935 <GIC_SPI !! 5146 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5936 <GIC_SPI !! 5147 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5937 <GIC_SPI !! 5148 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
5938 <GIC_SPI !! 5149 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
5939 <GIC_SPI !! 5150 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
5940 <GIC_SPI !! 5151 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
5941 <GIC_SPI !! 5152 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
5942 <GIC_SPI !! 5153 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
5943 <GIC_SPI !! 5154 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
5944 <GIC_SPI !! 5155 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
5945 <GIC_SPI !! 5156 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
5946 <GIC_SPI !! 5157 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
5947 <GIC_SPI !! 5158 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
5948 <GIC_SPI !! 5159 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
5949 <GIC_SPI !! 5160 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
5950 <GIC_SPI !! 5161 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
5951 <GIC_SPI !! 5162 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
5952 <GIC_SPI !! 5163 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
5953 <GIC_SPI !! 5164 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
5954 <GIC_SPI !! 5165 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
5955 dma-coherent; <<
5956 }; 5166 };
5957 5167
5958 adsp: remoteproc@17300000 { 5168 adsp: remoteproc@17300000 {
5959 compatible = "qcom,sm 5169 compatible = "qcom,sm8250-adsp-pas";
5960 reg = <0 0x17300000 0 5170 reg = <0 0x17300000 0 0x100>;
5961 5171
5962 interrupts-extended = !! 5172 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5963 5173 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5964 5174 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5965 5175 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
5966 5176 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
5967 interrupt-names = "wd 5177 interrupt-names = "wdog", "fatal", "ready",
5968 "ha 5178 "handover", "stop-ack";
5969 5179
5970 clocks = <&rpmhcc RPM 5180 clocks = <&rpmhcc RPMH_CXO_CLK>;
5971 clock-names = "xo"; 5181 clock-names = "xo";
5972 5182
5973 power-domains = <&rpm !! 5183 power-domains = <&rpmhpd SM8250_LCX>,
5974 <&rpm !! 5184 <&rpmhpd SM8250_LMX>;
5975 power-domain-names = 5185 power-domain-names = "lcx", "lmx";
5976 5186
5977 memory-region = <&ads 5187 memory-region = <&adsp_mem>;
5978 5188
5979 qcom,qmp = <&aoss_qmp 5189 qcom,qmp = <&aoss_qmp>;
5980 5190
5981 qcom,smem-states = <& 5191 qcom,smem-states = <&smp2p_adsp_out 0>;
5982 qcom,smem-state-names 5192 qcom,smem-state-names = "stop";
5983 5193
5984 status = "disabled"; 5194 status = "disabled";
5985 5195
5986 glink-edge { 5196 glink-edge {
5987 interrupts-ex 5197 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5988 5198 IPCC_MPROC_SIGNAL_GLINK_QMP
5989 5199 IRQ_TYPE_EDGE_RISING>;
5990 mboxes = <&ip 5200 mboxes = <&ipcc IPCC_CLIENT_LPASS
5991 5201 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5992 5202
5993 label = "lpas 5203 label = "lpass";
5994 qcom,remote-p 5204 qcom,remote-pid = <2>;
5995 5205
5996 apr { 5206 apr {
5997 compa 5207 compatible = "qcom,apr-v2";
5998 qcom, 5208 qcom,glink-channels = "apr_audio_svc";
5999 qcom, 5209 qcom,domain = <APR_DOMAIN_ADSP>;
6000 #addr 5210 #address-cells = <1>;
6001 #size 5211 #size-cells = <0>;
6002 5212
6003 servi 5213 service@3 {
6004 5214 reg = <APR_SVC_ADSP_CORE>;
6005 5215 compatible = "qcom,q6core";
6006 5216 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6007 }; 5217 };
6008 5218
6009 q6afe 5219 q6afe: service@4 {
6010 5220 compatible = "qcom,q6afe";
6011 5221 reg = <APR_SVC_AFE>;
6012 5222 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6013 5223 q6afedai: dais {
6014 5224 compatible = "qcom,q6afe-dais";
6015 5225 #address-cells = <1>;
6016 5226 #size-cells = <0>;
6017 5227 #sound-dai-cells = <1>;
6018 5228 };
6019 5229
6020 5230 q6afecc: clock-controller {
6021 5231 compatible = "qcom,q6afe-clocks";
6022 5232 #clock-cells = <2>;
6023 5233 };
6024 }; 5234 };
6025 5235
6026 q6asm 5236 q6asm: service@7 {
6027 5237 compatible = "qcom,q6asm";
6028 5238 reg = <APR_SVC_ASM>;
6029 5239 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6030 5240 q6asmdai: dais {
6031 5241 compatible = "qcom,q6asm-dais";
6032 5242 #address-cells = <1>;
6033 5243 #size-cells = <0>;
6034 5244 #sound-dai-cells = <1>;
6035 5245 iommus = <&apps_smmu 0x1801 0x0>;
6036 5246 };
6037 }; 5247 };
6038 5248
6039 q6adm 5249 q6adm: service@8 {
6040 5250 compatible = "qcom,q6adm";
6041 5251 reg = <APR_SVC_ADM>;
6042 5252 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
6043 5253 q6routing: routing {
6044 5254 compatible = "qcom,q6adm-routing";
6045 5255 #sound-dai-cells = <0>;
6046 5256 };
6047 }; 5257 };
6048 }; 5258 };
6049 5259
6050 fastrpc { 5260 fastrpc {
6051 compa 5261 compatible = "qcom,fastrpc";
6052 qcom, 5262 qcom,glink-channels = "fastrpcglink-apps-dsp";
6053 label 5263 label = "adsp";
6054 qcom, 5264 qcom,non-secure-domain;
6055 #addr 5265 #address-cells = <1>;
6056 #size 5266 #size-cells = <0>;
6057 5267
6058 compu 5268 compute-cb@3 {
6059 5269 compatible = "qcom,fastrpc-compute-cb";
6060 5270 reg = <3>;
6061 5271 iommus = <&apps_smmu 0x1803 0x0>;
6062 }; 5272 };
6063 5273
6064 compu 5274 compute-cb@4 {
6065 5275 compatible = "qcom,fastrpc-compute-cb";
6066 5276 reg = <4>;
6067 5277 iommus = <&apps_smmu 0x1804 0x0>;
6068 }; 5278 };
6069 5279
6070 compu 5280 compute-cb@5 {
6071 5281 compatible = "qcom,fastrpc-compute-cb";
6072 5282 reg = <5>;
6073 5283 iommus = <&apps_smmu 0x1805 0x0>;
6074 }; 5284 };
6075 }; 5285 };
6076 }; 5286 };
6077 }; 5287 };
6078 5288
6079 intc: interrupt-controller@17 5289 intc: interrupt-controller@17a00000 {
6080 compatible = "arm,gic 5290 compatible = "arm,gic-v3";
6081 #interrupt-cells = <3 5291 #interrupt-cells = <3>;
6082 interrupt-controller; 5292 interrupt-controller;
6083 reg = <0x0 0x17a00000 5293 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 5294 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6085 interrupts = <GIC_PPI 5295 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
6086 }; 5296 };
6087 5297
6088 watchdog@17c10000 { 5298 watchdog@17c10000 {
6089 compatible = "qcom,ap 5299 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
6090 reg = <0 0x17c10000 0 5300 reg = <0 0x17c10000 0 0x1000>;
6091 clocks = <&sleep_clk> 5301 clocks = <&sleep_clk>;
6092 interrupts = <GIC_SPI !! 5302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
6093 }; 5303 };
6094 5304
6095 timer@17c20000 { 5305 timer@17c20000 {
6096 #address-cells = <1>; 5306 #address-cells = <1>;
6097 #size-cells = <1>; 5307 #size-cells = <1>;
6098 ranges = <0 0 0 0x200 5308 ranges = <0 0 0 0x20000000>;
6099 compatible = "arm,arm 5309 compatible = "arm,armv7-timer-mem";
6100 reg = <0x0 0x17c20000 5310 reg = <0x0 0x17c20000 0x0 0x1000>;
6101 clock-frequency = <19 5311 clock-frequency = <19200000>;
6102 5312
6103 frame@17c21000 { 5313 frame@17c21000 {
6104 frame-number 5314 frame-number = <0>;
6105 interrupts = 5315 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
6106 5316 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
6107 reg = <0x17c2 5317 reg = <0x17c21000 0x1000>,
6108 <0x17c2 5318 <0x17c22000 0x1000>;
6109 }; 5319 };
6110 5320
6111 frame@17c23000 { 5321 frame@17c23000 {
6112 frame-number 5322 frame-number = <1>;
6113 interrupts = 5323 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
6114 reg = <0x17c2 5324 reg = <0x17c23000 0x1000>;
6115 status = "dis 5325 status = "disabled";
6116 }; 5326 };
6117 5327
6118 frame@17c25000 { 5328 frame@17c25000 {
6119 frame-number 5329 frame-number = <2>;
6120 interrupts = 5330 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6121 reg = <0x17c2 5331 reg = <0x17c25000 0x1000>;
6122 status = "dis 5332 status = "disabled";
6123 }; 5333 };
6124 5334
6125 frame@17c27000 { 5335 frame@17c27000 {
6126 frame-number 5336 frame-number = <3>;
6127 interrupts = 5337 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
6128 reg = <0x17c2 5338 reg = <0x17c27000 0x1000>;
6129 status = "dis 5339 status = "disabled";
6130 }; 5340 };
6131 5341
6132 frame@17c29000 { 5342 frame@17c29000 {
6133 frame-number 5343 frame-number = <4>;
6134 interrupts = 5344 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
6135 reg = <0x17c2 5345 reg = <0x17c29000 0x1000>;
6136 status = "dis 5346 status = "disabled";
6137 }; 5347 };
6138 5348
6139 frame@17c2b000 { 5349 frame@17c2b000 {
6140 frame-number 5350 frame-number = <5>;
6141 interrupts = 5351 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
6142 reg = <0x17c2 5352 reg = <0x17c2b000 0x1000>;
6143 status = "dis 5353 status = "disabled";
6144 }; 5354 };
6145 5355
6146 frame@17c2d000 { 5356 frame@17c2d000 {
6147 frame-number 5357 frame-number = <6>;
6148 interrupts = 5358 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
6149 reg = <0x17c2 5359 reg = <0x17c2d000 0x1000>;
6150 status = "dis 5360 status = "disabled";
6151 }; 5361 };
6152 }; 5362 };
6153 5363
6154 apps_rsc: rsc@18200000 { 5364 apps_rsc: rsc@18200000 {
6155 label = "apps_rsc"; 5365 label = "apps_rsc";
6156 compatible = "qcom,rp 5366 compatible = "qcom,rpmh-rsc";
6157 reg = <0x0 0x18200000 5367 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x182100 5368 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x182200 5369 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", 5370 reg-names = "drv-0", "drv-1", "drv-2";
6161 interrupts = <GIC_SPI 5371 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
6162 <GIC_SPI 5372 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
6163 <GIC_SPI 5373 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
6164 qcom,tcs-offset = <0x 5374 qcom,tcs-offset = <0xd00>;
6165 qcom,drv-id = <2>; 5375 qcom,drv-id = <2>;
6166 qcom,tcs-config = <AC 5376 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
6167 <WA 5377 <WAKE_TCS 3>, <CONTROL_TCS 1>;
6168 power-domains = <&CLU 5378 power-domains = <&CLUSTER_PD>;
6169 5379
6170 rpmhcc: clock-control 5380 rpmhcc: clock-controller {
6171 compatible = 5381 compatible = "qcom,sm8250-rpmh-clk";
6172 #clock-cells 5382 #clock-cells = <1>;
6173 clock-names = 5383 clock-names = "xo";
6174 clocks = <&xo 5384 clocks = <&xo_board>;
6175 }; 5385 };
6176 5386
6177 rpmhpd: power-control 5387 rpmhpd: power-controller {
6178 compatible = 5388 compatible = "qcom,sm8250-rpmhpd";
6179 #power-domain 5389 #power-domain-cells = <1>;
6180 operating-poi 5390 operating-points-v2 = <&rpmhpd_opp_table>;
6181 5391
6182 rpmhpd_opp_ta 5392 rpmhpd_opp_table: opp-table {
6183 compa 5393 compatible = "operating-points-v2";
6184 5394
6185 rpmhp 5395 rpmhpd_opp_ret: opp1 {
6186 5396 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
6187 }; 5397 };
6188 5398
6189 rpmhp 5399 rpmhpd_opp_min_svs: opp2 {
6190 5400 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
6191 }; 5401 };
6192 5402
6193 rpmhp 5403 rpmhpd_opp_low_svs: opp3 {
6194 5404 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
6195 }; 5405 };
6196 5406
6197 rpmhp 5407 rpmhpd_opp_svs: opp4 {
6198 5408 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
6199 }; 5409 };
6200 5410
6201 rpmhp 5411 rpmhpd_opp_svs_l1: opp5 {
6202 5412 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
6203 }; 5413 };
6204 5414
6205 rpmhp 5415 rpmhpd_opp_nom: opp6 {
6206 5416 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
6207 }; 5417 };
6208 5418
6209 rpmhp 5419 rpmhpd_opp_nom_l1: opp7 {
6210 5420 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
6211 }; 5421 };
6212 5422
6213 rpmhp 5423 rpmhpd_opp_nom_l2: opp8 {
6214 5424 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
6215 }; 5425 };
6216 5426
6217 rpmhp 5427 rpmhpd_opp_turbo: opp9 {
6218 5428 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
6219 }; 5429 };
6220 5430
6221 rpmhp 5431 rpmhpd_opp_turbo_l1: opp10 {
6222 5432 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
6223 }; 5433 };
6224 }; 5434 };
6225 }; 5435 };
6226 5436
6227 apps_bcm_voter: bcm-v 5437 apps_bcm_voter: bcm-voter {
6228 compatible = 5438 compatible = "qcom,bcm-voter";
6229 }; 5439 };
6230 }; 5440 };
6231 5441
6232 epss_l3: interconnect@1859000 5442 epss_l3: interconnect@18590000 {
6233 compatible = "qcom,sm 5443 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
6234 reg = <0 0x18590000 0 5444 reg = <0 0x18590000 0 0x1000>;
6235 5445
6236 clocks = <&rpmhcc RPM 5446 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6237 clock-names = "xo", " 5447 clock-names = "xo", "alternate";
6238 5448
6239 #interconnect-cells = 5449 #interconnect-cells = <1>;
6240 }; 5450 };
6241 5451
6242 cpufreq_hw: cpufreq@18591000 5452 cpufreq_hw: cpufreq@18591000 {
6243 compatible = "qcom,sm 5453 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
6244 reg = <0 0x18591000 0 5454 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 5455 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 5456 <0 0x18593000 0 0x1000>;
6247 reg-names = "freq-dom 5457 reg-names = "freq-domain0", "freq-domain1",
6248 "freq-dom 5458 "freq-domain2";
6249 5459
6250 clocks = <&rpmhcc RPM 5460 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
6251 clock-names = "xo", " 5461 clock-names = "xo", "alternate";
6252 interrupts = <GIC_SPI 5462 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
6253 <GIC_SPI 5463 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
6254 <GIC_SPI 5464 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
6255 interrupt-names = "dc 5465 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6256 #freq-domain-cells = 5466 #freq-domain-cells = <1>;
6257 #clock-cells = <1>; <<
6258 }; 5467 };
6259 }; 5468 };
6260 5469
6261 sound: sound { <<
6262 }; <<
6263 <<
6264 timer { 5470 timer {
6265 compatible = "arm,armv8-timer 5471 compatible = "arm,armv8-timer";
6266 interrupts = <GIC_PPI 13 5472 interrupts = <GIC_PPI 13
6267 (GIC_CPU_MASK 5473 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6268 <GIC_PPI 14 5474 <GIC_PPI 14
6269 (GIC_CPU_MASK 5475 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6270 <GIC_PPI 11 5476 <GIC_PPI 11
6271 (GIC_CPU_MASK 5477 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
6272 <GIC_PPI 10 5478 <GIC_PPI 10
6273 (GIC_CPU_MASK 5479 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
6274 }; 5480 };
6275 5481
6276 thermal-zones { 5482 thermal-zones {
6277 cpu0-thermal { 5483 cpu0-thermal {
6278 polling-delay-passive 5484 polling-delay-passive = <250>;
>> 5485 polling-delay = <1000>;
6279 5486
6280 thermal-sensors = <&t 5487 thermal-sensors = <&tsens0 1>;
6281 5488
6282 trips { 5489 trips {
6283 cpu0_alert0: 5490 cpu0_alert0: trip-point0 {
6284 tempe 5491 temperature = <90000>;
6285 hyste 5492 hysteresis = <2000>;
6286 type 5493 type = "passive";
6287 }; 5494 };
6288 5495
6289 cpu0_alert1: 5496 cpu0_alert1: trip-point1 {
6290 tempe 5497 temperature = <95000>;
6291 hyste 5498 hysteresis = <2000>;
6292 type 5499 type = "passive";
6293 }; 5500 };
6294 5501
6295 cpu0_crit: cp !! 5502 cpu0_crit: cpu_crit {
6296 tempe 5503 temperature = <110000>;
6297 hyste 5504 hysteresis = <1000>;
6298 type 5505 type = "critical";
6299 }; 5506 };
6300 }; 5507 };
6301 5508
6302 cooling-maps { 5509 cooling-maps {
6303 map0 { 5510 map0 {
6304 trip 5511 trip = <&cpu0_alert0>;
6305 cooli 5512 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6306 5513 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6307 5514 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6308 5515 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6309 }; 5516 };
6310 map1 { 5517 map1 {
6311 trip 5518 trip = <&cpu0_alert1>;
6312 cooli 5519 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6313 5520 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6314 5521 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6315 5522 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6316 }; 5523 };
6317 }; 5524 };
6318 }; 5525 };
6319 5526
6320 cpu1-thermal { 5527 cpu1-thermal {
6321 polling-delay-passive 5528 polling-delay-passive = <250>;
>> 5529 polling-delay = <1000>;
6322 5530
6323 thermal-sensors = <&t 5531 thermal-sensors = <&tsens0 2>;
6324 5532
6325 trips { 5533 trips {
6326 cpu1_alert0: 5534 cpu1_alert0: trip-point0 {
6327 tempe 5535 temperature = <90000>;
6328 hyste 5536 hysteresis = <2000>;
6329 type 5537 type = "passive";
6330 }; 5538 };
6331 5539
6332 cpu1_alert1: 5540 cpu1_alert1: trip-point1 {
6333 tempe 5541 temperature = <95000>;
6334 hyste 5542 hysteresis = <2000>;
6335 type 5543 type = "passive";
6336 }; 5544 };
6337 5545
6338 cpu1_crit: cp !! 5546 cpu1_crit: cpu_crit {
6339 tempe 5547 temperature = <110000>;
6340 hyste 5548 hysteresis = <1000>;
6341 type 5549 type = "critical";
6342 }; 5550 };
6343 }; 5551 };
6344 5552
6345 cooling-maps { 5553 cooling-maps {
6346 map0 { 5554 map0 {
6347 trip 5555 trip = <&cpu1_alert0>;
6348 cooli 5556 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6349 5557 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6350 5558 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6351 5559 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6352 }; 5560 };
6353 map1 { 5561 map1 {
6354 trip 5562 trip = <&cpu1_alert1>;
6355 cooli 5563 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6356 5564 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6357 5565 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6358 5566 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6359 }; 5567 };
6360 }; 5568 };
6361 }; 5569 };
6362 5570
6363 cpu2-thermal { 5571 cpu2-thermal {
6364 polling-delay-passive 5572 polling-delay-passive = <250>;
>> 5573 polling-delay = <1000>;
6365 5574
6366 thermal-sensors = <&t 5575 thermal-sensors = <&tsens0 3>;
6367 5576
6368 trips { 5577 trips {
6369 cpu2_alert0: 5578 cpu2_alert0: trip-point0 {
6370 tempe 5579 temperature = <90000>;
6371 hyste 5580 hysteresis = <2000>;
6372 type 5581 type = "passive";
6373 }; 5582 };
6374 5583
6375 cpu2_alert1: 5584 cpu2_alert1: trip-point1 {
6376 tempe 5585 temperature = <95000>;
6377 hyste 5586 hysteresis = <2000>;
6378 type 5587 type = "passive";
6379 }; 5588 };
6380 5589
6381 cpu2_crit: cp !! 5590 cpu2_crit: cpu_crit {
6382 tempe 5591 temperature = <110000>;
6383 hyste 5592 hysteresis = <1000>;
6384 type 5593 type = "critical";
6385 }; 5594 };
6386 }; 5595 };
6387 5596
6388 cooling-maps { 5597 cooling-maps {
6389 map0 { 5598 map0 {
6390 trip 5599 trip = <&cpu2_alert0>;
6391 cooli 5600 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6392 5601 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6393 5602 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6394 5603 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6395 }; 5604 };
6396 map1 { 5605 map1 {
6397 trip 5606 trip = <&cpu2_alert1>;
6398 cooli 5607 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6399 5608 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6400 5609 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6401 5610 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6402 }; 5611 };
6403 }; 5612 };
6404 }; 5613 };
6405 5614
6406 cpu3-thermal { 5615 cpu3-thermal {
6407 polling-delay-passive 5616 polling-delay-passive = <250>;
>> 5617 polling-delay = <1000>;
6408 5618
6409 thermal-sensors = <&t 5619 thermal-sensors = <&tsens0 4>;
6410 5620
6411 trips { 5621 trips {
6412 cpu3_alert0: 5622 cpu3_alert0: trip-point0 {
6413 tempe 5623 temperature = <90000>;
6414 hyste 5624 hysteresis = <2000>;
6415 type 5625 type = "passive";
6416 }; 5626 };
6417 5627
6418 cpu3_alert1: 5628 cpu3_alert1: trip-point1 {
6419 tempe 5629 temperature = <95000>;
6420 hyste 5630 hysteresis = <2000>;
6421 type 5631 type = "passive";
6422 }; 5632 };
6423 5633
6424 cpu3_crit: cp !! 5634 cpu3_crit: cpu_crit {
6425 tempe 5635 temperature = <110000>;
6426 hyste 5636 hysteresis = <1000>;
6427 type 5637 type = "critical";
6428 }; 5638 };
6429 }; 5639 };
6430 5640
6431 cooling-maps { 5641 cooling-maps {
6432 map0 { 5642 map0 {
6433 trip 5643 trip = <&cpu3_alert0>;
6434 cooli 5644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6435 5645 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6436 5646 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6437 5647 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6438 }; 5648 };
6439 map1 { 5649 map1 {
6440 trip 5650 trip = <&cpu3_alert1>;
6441 cooli 5651 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6442 5652 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6443 5653 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6444 5654 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6445 }; 5655 };
6446 }; 5656 };
6447 }; 5657 };
6448 5658
6449 cpu4-top-thermal { 5659 cpu4-top-thermal {
6450 polling-delay-passive 5660 polling-delay-passive = <250>;
>> 5661 polling-delay = <1000>;
6451 5662
6452 thermal-sensors = <&t 5663 thermal-sensors = <&tsens0 7>;
6453 5664
6454 trips { 5665 trips {
6455 cpu4_top_aler 5666 cpu4_top_alert0: trip-point0 {
6456 tempe 5667 temperature = <90000>;
6457 hyste 5668 hysteresis = <2000>;
6458 type 5669 type = "passive";
6459 }; 5670 };
6460 5671
6461 cpu4_top_aler 5672 cpu4_top_alert1: trip-point1 {
6462 tempe 5673 temperature = <95000>;
6463 hyste 5674 hysteresis = <2000>;
6464 type 5675 type = "passive";
6465 }; 5676 };
6466 5677
6467 cpu4_top_crit !! 5678 cpu4_top_crit: cpu_crit {
6468 tempe 5679 temperature = <110000>;
6469 hyste 5680 hysteresis = <1000>;
6470 type 5681 type = "critical";
6471 }; 5682 };
6472 }; 5683 };
6473 5684
6474 cooling-maps { 5685 cooling-maps {
6475 map0 { 5686 map0 {
6476 trip 5687 trip = <&cpu4_top_alert0>;
6477 cooli 5688 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6478 5689 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6479 5690 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6480 5691 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6481 }; 5692 };
6482 map1 { 5693 map1 {
6483 trip 5694 trip = <&cpu4_top_alert1>;
6484 cooli 5695 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6485 5696 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6486 5697 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6487 5698 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6488 }; 5699 };
6489 }; 5700 };
6490 }; 5701 };
6491 5702
6492 cpu5-top-thermal { 5703 cpu5-top-thermal {
6493 polling-delay-passive 5704 polling-delay-passive = <250>;
>> 5705 polling-delay = <1000>;
6494 5706
6495 thermal-sensors = <&t 5707 thermal-sensors = <&tsens0 8>;
6496 5708
6497 trips { 5709 trips {
6498 cpu5_top_aler 5710 cpu5_top_alert0: trip-point0 {
6499 tempe 5711 temperature = <90000>;
6500 hyste 5712 hysteresis = <2000>;
6501 type 5713 type = "passive";
6502 }; 5714 };
6503 5715
6504 cpu5_top_aler 5716 cpu5_top_alert1: trip-point1 {
6505 tempe 5717 temperature = <95000>;
6506 hyste 5718 hysteresis = <2000>;
6507 type 5719 type = "passive";
6508 }; 5720 };
6509 5721
6510 cpu5_top_crit !! 5722 cpu5_top_crit: cpu_crit {
6511 tempe 5723 temperature = <110000>;
6512 hyste 5724 hysteresis = <1000>;
6513 type 5725 type = "critical";
6514 }; 5726 };
6515 }; 5727 };
6516 5728
6517 cooling-maps { 5729 cooling-maps {
6518 map0 { 5730 map0 {
6519 trip 5731 trip = <&cpu5_top_alert0>;
6520 cooli 5732 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6521 5733 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6522 5734 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6523 5735 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6524 }; 5736 };
6525 map1 { 5737 map1 {
6526 trip 5738 trip = <&cpu5_top_alert1>;
6527 cooli 5739 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6528 5740 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6529 5741 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6530 5742 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6531 }; 5743 };
6532 }; 5744 };
6533 }; 5745 };
6534 5746
6535 cpu6-top-thermal { 5747 cpu6-top-thermal {
6536 polling-delay-passive 5748 polling-delay-passive = <250>;
>> 5749 polling-delay = <1000>;
6537 5750
6538 thermal-sensors = <&t 5751 thermal-sensors = <&tsens0 9>;
6539 5752
6540 trips { 5753 trips {
6541 cpu6_top_aler 5754 cpu6_top_alert0: trip-point0 {
6542 tempe 5755 temperature = <90000>;
6543 hyste 5756 hysteresis = <2000>;
6544 type 5757 type = "passive";
6545 }; 5758 };
6546 5759
6547 cpu6_top_aler 5760 cpu6_top_alert1: trip-point1 {
6548 tempe 5761 temperature = <95000>;
6549 hyste 5762 hysteresis = <2000>;
6550 type 5763 type = "passive";
6551 }; 5764 };
6552 5765
6553 cpu6_top_crit !! 5766 cpu6_top_crit: cpu_crit {
6554 tempe 5767 temperature = <110000>;
6555 hyste 5768 hysteresis = <1000>;
6556 type 5769 type = "critical";
6557 }; 5770 };
6558 }; 5771 };
6559 5772
6560 cooling-maps { 5773 cooling-maps {
6561 map0 { 5774 map0 {
6562 trip 5775 trip = <&cpu6_top_alert0>;
6563 cooli 5776 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6564 5777 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6565 5778 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6566 5779 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6567 }; 5780 };
6568 map1 { 5781 map1 {
6569 trip 5782 trip = <&cpu6_top_alert1>;
6570 cooli 5783 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6571 5784 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6572 5785 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6573 5786 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6574 }; 5787 };
6575 }; 5788 };
6576 }; 5789 };
6577 5790
6578 cpu7-top-thermal { 5791 cpu7-top-thermal {
6579 polling-delay-passive 5792 polling-delay-passive = <250>;
>> 5793 polling-delay = <1000>;
6580 5794
6581 thermal-sensors = <&t 5795 thermal-sensors = <&tsens0 10>;
6582 5796
6583 trips { 5797 trips {
6584 cpu7_top_aler 5798 cpu7_top_alert0: trip-point0 {
6585 tempe 5799 temperature = <90000>;
6586 hyste 5800 hysteresis = <2000>;
6587 type 5801 type = "passive";
6588 }; 5802 };
6589 5803
6590 cpu7_top_aler 5804 cpu7_top_alert1: trip-point1 {
6591 tempe 5805 temperature = <95000>;
6592 hyste 5806 hysteresis = <2000>;
6593 type 5807 type = "passive";
6594 }; 5808 };
6595 5809
6596 cpu7_top_crit !! 5810 cpu7_top_crit: cpu_crit {
6597 tempe 5811 temperature = <110000>;
6598 hyste 5812 hysteresis = <1000>;
6599 type 5813 type = "critical";
6600 }; 5814 };
6601 }; 5815 };
6602 5816
6603 cooling-maps { 5817 cooling-maps {
6604 map0 { 5818 map0 {
6605 trip 5819 trip = <&cpu7_top_alert0>;
6606 cooli 5820 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6607 5821 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6608 5822 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6609 5823 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6610 }; 5824 };
6611 map1 { 5825 map1 {
6612 trip 5826 trip = <&cpu7_top_alert1>;
6613 cooli 5827 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6614 5828 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6615 5829 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6616 5830 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6617 }; 5831 };
6618 }; 5832 };
6619 }; 5833 };
6620 5834
6621 cpu4-bottom-thermal { 5835 cpu4-bottom-thermal {
6622 polling-delay-passive 5836 polling-delay-passive = <250>;
>> 5837 polling-delay = <1000>;
6623 5838
6624 thermal-sensors = <&t 5839 thermal-sensors = <&tsens0 11>;
6625 5840
6626 trips { 5841 trips {
6627 cpu4_bottom_a 5842 cpu4_bottom_alert0: trip-point0 {
6628 tempe 5843 temperature = <90000>;
6629 hyste 5844 hysteresis = <2000>;
6630 type 5845 type = "passive";
6631 }; 5846 };
6632 5847
6633 cpu4_bottom_a 5848 cpu4_bottom_alert1: trip-point1 {
6634 tempe 5849 temperature = <95000>;
6635 hyste 5850 hysteresis = <2000>;
6636 type 5851 type = "passive";
6637 }; 5852 };
6638 5853
6639 cpu4_bottom_c !! 5854 cpu4_bottom_crit: cpu_crit {
6640 tempe 5855 temperature = <110000>;
6641 hyste 5856 hysteresis = <1000>;
6642 type 5857 type = "critical";
6643 }; 5858 };
6644 }; 5859 };
6645 5860
6646 cooling-maps { 5861 cooling-maps {
6647 map0 { 5862 map0 {
6648 trip 5863 trip = <&cpu4_bottom_alert0>;
6649 cooli 5864 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6650 5865 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6651 5866 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6652 5867 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6653 }; 5868 };
6654 map1 { 5869 map1 {
6655 trip 5870 trip = <&cpu4_bottom_alert1>;
6656 cooli 5871 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6657 5872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6658 5873 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6659 5874 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6660 }; 5875 };
6661 }; 5876 };
6662 }; 5877 };
6663 5878
6664 cpu5-bottom-thermal { 5879 cpu5-bottom-thermal {
6665 polling-delay-passive 5880 polling-delay-passive = <250>;
>> 5881 polling-delay = <1000>;
6666 5882
6667 thermal-sensors = <&t 5883 thermal-sensors = <&tsens0 12>;
6668 5884
6669 trips { 5885 trips {
6670 cpu5_bottom_a 5886 cpu5_bottom_alert0: trip-point0 {
6671 tempe 5887 temperature = <90000>;
6672 hyste 5888 hysteresis = <2000>;
6673 type 5889 type = "passive";
6674 }; 5890 };
6675 5891
6676 cpu5_bottom_a 5892 cpu5_bottom_alert1: trip-point1 {
6677 tempe 5893 temperature = <95000>;
6678 hyste 5894 hysteresis = <2000>;
6679 type 5895 type = "passive";
6680 }; 5896 };
6681 5897
6682 cpu5_bottom_c !! 5898 cpu5_bottom_crit: cpu_crit {
6683 tempe 5899 temperature = <110000>;
6684 hyste 5900 hysteresis = <1000>;
6685 type 5901 type = "critical";
6686 }; 5902 };
6687 }; 5903 };
6688 5904
6689 cooling-maps { 5905 cooling-maps {
6690 map0 { 5906 map0 {
6691 trip 5907 trip = <&cpu5_bottom_alert0>;
6692 cooli 5908 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6693 5909 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6694 5910 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6695 5911 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6696 }; 5912 };
6697 map1 { 5913 map1 {
6698 trip 5914 trip = <&cpu5_bottom_alert1>;
6699 cooli 5915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6700 5916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6701 5917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6702 5918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6703 }; 5919 };
6704 }; 5920 };
6705 }; 5921 };
6706 5922
6707 cpu6-bottom-thermal { 5923 cpu6-bottom-thermal {
6708 polling-delay-passive 5924 polling-delay-passive = <250>;
>> 5925 polling-delay = <1000>;
6709 5926
6710 thermal-sensors = <&t 5927 thermal-sensors = <&tsens0 13>;
6711 5928
6712 trips { 5929 trips {
6713 cpu6_bottom_a 5930 cpu6_bottom_alert0: trip-point0 {
6714 tempe 5931 temperature = <90000>;
6715 hyste 5932 hysteresis = <2000>;
6716 type 5933 type = "passive";
6717 }; 5934 };
6718 5935
6719 cpu6_bottom_a 5936 cpu6_bottom_alert1: trip-point1 {
6720 tempe 5937 temperature = <95000>;
6721 hyste 5938 hysteresis = <2000>;
6722 type 5939 type = "passive";
6723 }; 5940 };
6724 5941
6725 cpu6_bottom_c !! 5942 cpu6_bottom_crit: cpu_crit {
6726 tempe 5943 temperature = <110000>;
6727 hyste 5944 hysteresis = <1000>;
6728 type 5945 type = "critical";
6729 }; 5946 };
6730 }; 5947 };
6731 5948
6732 cooling-maps { 5949 cooling-maps {
6733 map0 { 5950 map0 {
6734 trip 5951 trip = <&cpu6_bottom_alert0>;
6735 cooli 5952 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6736 5953 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6737 5954 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6738 5955 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6739 }; 5956 };
6740 map1 { 5957 map1 {
6741 trip 5958 trip = <&cpu6_bottom_alert1>;
6742 cooli 5959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6743 5960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6744 5961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6745 5962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6746 }; 5963 };
6747 }; 5964 };
6748 }; 5965 };
6749 5966
6750 cpu7-bottom-thermal { 5967 cpu7-bottom-thermal {
6751 polling-delay-passive 5968 polling-delay-passive = <250>;
>> 5969 polling-delay = <1000>;
6752 5970
6753 thermal-sensors = <&t 5971 thermal-sensors = <&tsens0 14>;
6754 5972
6755 trips { 5973 trips {
6756 cpu7_bottom_a 5974 cpu7_bottom_alert0: trip-point0 {
6757 tempe 5975 temperature = <90000>;
6758 hyste 5976 hysteresis = <2000>;
6759 type 5977 type = "passive";
6760 }; 5978 };
6761 5979
6762 cpu7_bottom_a 5980 cpu7_bottom_alert1: trip-point1 {
6763 tempe 5981 temperature = <95000>;
6764 hyste 5982 hysteresis = <2000>;
6765 type 5983 type = "passive";
6766 }; 5984 };
6767 5985
6768 cpu7_bottom_c !! 5986 cpu7_bottom_crit: cpu_crit {
6769 tempe 5987 temperature = <110000>;
6770 hyste 5988 hysteresis = <1000>;
6771 type 5989 type = "critical";
6772 }; 5990 };
6773 }; 5991 };
6774 5992
6775 cooling-maps { 5993 cooling-maps {
6776 map0 { 5994 map0 {
6777 trip 5995 trip = <&cpu7_bottom_alert0>;
6778 cooli 5996 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6779 5997 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6780 5998 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6781 5999 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6782 }; 6000 };
6783 map1 { 6001 map1 {
6784 trip 6002 trip = <&cpu7_bottom_alert1>;
6785 cooli 6003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6786 6004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6787 6005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6788 6006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6789 }; 6007 };
6790 }; 6008 };
6791 }; 6009 };
6792 6010
6793 aoss0-thermal { 6011 aoss0-thermal {
6794 polling-delay-passive 6012 polling-delay-passive = <250>;
>> 6013 polling-delay = <1000>;
6795 6014
6796 thermal-sensors = <&t 6015 thermal-sensors = <&tsens0 0>;
6797 6016
6798 trips { 6017 trips {
6799 aoss0_alert0: 6018 aoss0_alert0: trip-point0 {
6800 tempe 6019 temperature = <90000>;
6801 hyste 6020 hysteresis = <2000>;
6802 type 6021 type = "hot";
6803 }; 6022 };
6804 }; 6023 };
6805 }; 6024 };
6806 6025
6807 cluster0-thermal { 6026 cluster0-thermal {
6808 polling-delay-passive 6027 polling-delay-passive = <250>;
>> 6028 polling-delay = <1000>;
6809 6029
6810 thermal-sensors = <&t 6030 thermal-sensors = <&tsens0 5>;
6811 6031
6812 trips { 6032 trips {
6813 cluster0_aler 6033 cluster0_alert0: trip-point0 {
6814 tempe 6034 temperature = <90000>;
6815 hyste 6035 hysteresis = <2000>;
6816 type 6036 type = "hot";
6817 }; 6037 };
6818 cluster0_crit !! 6038 cluster0_crit: cluster0_crit {
6819 tempe 6039 temperature = <110000>;
6820 hyste 6040 hysteresis = <2000>;
6821 type 6041 type = "critical";
6822 }; 6042 };
6823 }; 6043 };
6824 }; 6044 };
6825 6045
6826 cluster1-thermal { 6046 cluster1-thermal {
6827 polling-delay-passive 6047 polling-delay-passive = <250>;
>> 6048 polling-delay = <1000>;
6828 6049
6829 thermal-sensors = <&t 6050 thermal-sensors = <&tsens0 6>;
6830 6051
6831 trips { 6052 trips {
6832 cluster1_aler 6053 cluster1_alert0: trip-point0 {
6833 tempe 6054 temperature = <90000>;
6834 hyste 6055 hysteresis = <2000>;
6835 type 6056 type = "hot";
6836 }; 6057 };
6837 cluster1_crit !! 6058 cluster1_crit: cluster1_crit {
6838 tempe 6059 temperature = <110000>;
6839 hyste 6060 hysteresis = <2000>;
6840 type 6061 type = "critical";
6841 }; 6062 };
6842 }; 6063 };
6843 }; 6064 };
6844 6065
6845 gpu-top-thermal { 6066 gpu-top-thermal {
6846 polling-delay-passive 6067 polling-delay-passive = <250>;
>> 6068 polling-delay = <1000>;
6847 6069
6848 thermal-sensors = <&t 6070 thermal-sensors = <&tsens0 15>;
6849 6071
6850 cooling-maps { <<
6851 map0 { <<
6852 trip <<
6853 cooli <<
6854 }; <<
6855 }; <<
6856 <<
6857 trips { 6072 trips {
6858 gpu_top_alert !! 6073 gpu1_alert0: trip-point0 {
6859 tempe <<
6860 hyste <<
6861 type <<
6862 }; <<
6863 <<
6864 trip-point1 { <<
6865 tempe 6074 temperature = <90000>;
6866 hyste !! 6075 hysteresis = <2000>;
6867 type 6076 type = "hot";
6868 }; 6077 };
6869 <<
6870 trip-point2 { <<
6871 tempe <<
6872 hyste <<
6873 type <<
6874 }; <<
6875 }; 6078 };
6876 }; 6079 };
6877 6080
6878 aoss1-thermal { 6081 aoss1-thermal {
6879 polling-delay-passive 6082 polling-delay-passive = <250>;
>> 6083 polling-delay = <1000>;
6880 6084
6881 thermal-sensors = <&t 6085 thermal-sensors = <&tsens1 0>;
6882 6086
6883 trips { 6087 trips {
6884 aoss1_alert0: 6088 aoss1_alert0: trip-point0 {
6885 tempe 6089 temperature = <90000>;
6886 hyste 6090 hysteresis = <2000>;
6887 type 6091 type = "hot";
6888 }; 6092 };
6889 }; 6093 };
6890 }; 6094 };
6891 6095
6892 wlan-thermal { 6096 wlan-thermal {
6893 polling-delay-passive 6097 polling-delay-passive = <250>;
>> 6098 polling-delay = <1000>;
6894 6099
6895 thermal-sensors = <&t 6100 thermal-sensors = <&tsens1 1>;
6896 6101
6897 trips { 6102 trips {
6898 wlan_alert0: 6103 wlan_alert0: trip-point0 {
6899 tempe 6104 temperature = <90000>;
6900 hyste 6105 hysteresis = <2000>;
6901 type 6106 type = "hot";
6902 }; 6107 };
6903 }; 6108 };
6904 }; 6109 };
6905 6110
6906 video-thermal { 6111 video-thermal {
6907 polling-delay-passive 6112 polling-delay-passive = <250>;
>> 6113 polling-delay = <1000>;
6908 6114
6909 thermal-sensors = <&t 6115 thermal-sensors = <&tsens1 2>;
6910 6116
6911 trips { 6117 trips {
6912 video_alert0: 6118 video_alert0: trip-point0 {
6913 tempe 6119 temperature = <90000>;
6914 hyste 6120 hysteresis = <2000>;
6915 type 6121 type = "hot";
6916 }; 6122 };
6917 }; 6123 };
6918 }; 6124 };
6919 6125
6920 mem-thermal { 6126 mem-thermal {
6921 polling-delay-passive 6127 polling-delay-passive = <250>;
>> 6128 polling-delay = <1000>;
6922 6129
6923 thermal-sensors = <&t 6130 thermal-sensors = <&tsens1 3>;
6924 6131
6925 trips { 6132 trips {
6926 mem_alert0: t 6133 mem_alert0: trip-point0 {
6927 tempe 6134 temperature = <90000>;
6928 hyste 6135 hysteresis = <2000>;
6929 type 6136 type = "hot";
6930 }; 6137 };
6931 }; 6138 };
6932 }; 6139 };
6933 6140
6934 q6-hvx-thermal { 6141 q6-hvx-thermal {
6935 polling-delay-passive 6142 polling-delay-passive = <250>;
>> 6143 polling-delay = <1000>;
6936 6144
6937 thermal-sensors = <&t 6145 thermal-sensors = <&tsens1 4>;
6938 6146
6939 trips { 6147 trips {
6940 q6_hvx_alert0 6148 q6_hvx_alert0: trip-point0 {
6941 tempe 6149 temperature = <90000>;
6942 hyste 6150 hysteresis = <2000>;
6943 type 6151 type = "hot";
6944 }; 6152 };
6945 }; 6153 };
6946 }; 6154 };
6947 6155
6948 camera-thermal { 6156 camera-thermal {
6949 polling-delay-passive 6157 polling-delay-passive = <250>;
>> 6158 polling-delay = <1000>;
6950 6159
6951 thermal-sensors = <&t 6160 thermal-sensors = <&tsens1 5>;
6952 6161
6953 trips { 6162 trips {
6954 camera_alert0 6163 camera_alert0: trip-point0 {
6955 tempe 6164 temperature = <90000>;
6956 hyste 6165 hysteresis = <2000>;
6957 type 6166 type = "hot";
6958 }; 6167 };
6959 }; 6168 };
6960 }; 6169 };
6961 6170
6962 compute-thermal { 6171 compute-thermal {
6963 polling-delay-passive 6172 polling-delay-passive = <250>;
>> 6173 polling-delay = <1000>;
6964 6174
6965 thermal-sensors = <&t 6175 thermal-sensors = <&tsens1 6>;
6966 6176
6967 trips { 6177 trips {
6968 compute_alert 6178 compute_alert0: trip-point0 {
6969 tempe 6179 temperature = <90000>;
6970 hyste 6180 hysteresis = <2000>;
6971 type 6181 type = "hot";
6972 }; 6182 };
6973 }; 6183 };
6974 }; 6184 };
6975 6185
6976 npu-thermal { 6186 npu-thermal {
6977 polling-delay-passive 6187 polling-delay-passive = <250>;
>> 6188 polling-delay = <1000>;
6978 6189
6979 thermal-sensors = <&t 6190 thermal-sensors = <&tsens1 7>;
6980 6191
6981 trips { 6192 trips {
6982 npu_alert0: t 6193 npu_alert0: trip-point0 {
6983 tempe 6194 temperature = <90000>;
6984 hyste 6195 hysteresis = <2000>;
6985 type 6196 type = "hot";
6986 }; 6197 };
6987 }; 6198 };
6988 }; 6199 };
6989 6200
6990 gpu-bottom-thermal { 6201 gpu-bottom-thermal {
6991 polling-delay-passive 6202 polling-delay-passive = <250>;
>> 6203 polling-delay = <1000>;
6992 6204
6993 thermal-sensors = <&t 6205 thermal-sensors = <&tsens1 8>;
6994 6206
6995 cooling-maps { <<
6996 map0 { <<
6997 trip <<
6998 cooli <<
6999 }; <<
7000 }; <<
7001 <<
7002 trips { 6207 trips {
7003 gpu_bottom_al !! 6208 gpu2_alert0: trip-point0 {
7004 tempe <<
7005 hyste <<
7006 type <<
7007 }; <<
7008 <<
7009 trip-point1 { <<
7010 tempe 6209 temperature = <90000>;
7011 hyste !! 6210 hysteresis = <2000>;
7012 type 6211 type = "hot";
7013 }; <<
7014 <<
7015 trip-point2 { <<
7016 tempe <<
7017 hyste <<
7018 type <<
7019 }; 6212 };
7020 }; 6213 };
7021 }; 6214 };
7022 }; 6215 };
7023 }; 6216 };
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